1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h> 12#include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sm8250.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,apr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/sound/qcom,q6afe.h> 22#include <dt-bindings/thermal/thermal.h> 23#include <dt-bindings/clock/qcom,camcc-sm8250.h> 24#include <dt-bindings/clock/qcom,videocc-sm8250.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 aliases { 33 i2c0 = &i2c0; 34 i2c1 = &i2c1; 35 i2c2 = &i2c2; 36 i2c3 = &i2c3; 37 i2c4 = &i2c4; 38 i2c5 = &i2c5; 39 i2c6 = &i2c6; 40 i2c7 = &i2c7; 41 i2c8 = &i2c8; 42 i2c9 = &i2c9; 43 i2c10 = &i2c10; 44 i2c11 = &i2c11; 45 i2c12 = &i2c12; 46 i2c13 = &i2c13; 47 i2c14 = &i2c14; 48 i2c15 = &i2c15; 49 i2c16 = &i2c16; 50 i2c17 = &i2c17; 51 i2c18 = &i2c18; 52 i2c19 = &i2c19; 53 spi0 = &spi0; 54 spi1 = &spi1; 55 spi2 = &spi2; 56 spi3 = &spi3; 57 spi4 = &spi4; 58 spi5 = &spi5; 59 spi6 = &spi6; 60 spi7 = &spi7; 61 spi8 = &spi8; 62 spi9 = &spi9; 63 spi10 = &spi10; 64 spi11 = &spi11; 65 spi12 = &spi12; 66 spi13 = &spi13; 67 spi14 = &spi14; 68 spi15 = &spi15; 69 spi16 = &spi16; 70 spi17 = &spi17; 71 spi18 = &spi18; 72 spi19 = &spi19; 73 }; 74 75 chosen { }; 76 77 clocks { 78 xo_board: xo-board { 79 compatible = "fixed-clock"; 80 #clock-cells = <0>; 81 clock-frequency = <38400000>; 82 clock-output-names = "xo_board"; 83 }; 84 85 sleep_clk: sleep-clk { 86 compatible = "fixed-clock"; 87 clock-frequency = <32768>; 88 #clock-cells = <0>; 89 }; 90 }; 91 92 cpus { 93 #address-cells = <2>; 94 #size-cells = <0>; 95 96 CPU0: cpu@0 { 97 device_type = "cpu"; 98 compatible = "qcom,kryo485"; 99 reg = <0x0 0x0>; 100 clocks = <&cpufreq_hw 0>; 101 enable-method = "psci"; 102 capacity-dmips-mhz = <448>; 103 dynamic-power-coefficient = <205>; 104 next-level-cache = <&L2_0>; 105 power-domains = <&CPU_PD0>; 106 power-domain-names = "psci"; 107 qcom,freq-domain = <&cpufreq_hw 0>; 108 operating-points-v2 = <&cpu0_opp_table>; 109 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 110 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 111 #cooling-cells = <2>; 112 L2_0: l2-cache { 113 compatible = "cache"; 114 cache-level = <2>; 115 cache-size = <0x20000>; 116 cache-unified; 117 next-level-cache = <&L3_0>; 118 L3_0: l3-cache { 119 compatible = "cache"; 120 cache-level = <3>; 121 cache-size = <0x400000>; 122 cache-unified; 123 }; 124 }; 125 }; 126 127 CPU1: cpu@100 { 128 device_type = "cpu"; 129 compatible = "qcom,kryo485"; 130 reg = <0x0 0x100>; 131 clocks = <&cpufreq_hw 0>; 132 enable-method = "psci"; 133 capacity-dmips-mhz = <448>; 134 dynamic-power-coefficient = <205>; 135 next-level-cache = <&L2_100>; 136 power-domains = <&CPU_PD1>; 137 power-domain-names = "psci"; 138 qcom,freq-domain = <&cpufreq_hw 0>; 139 operating-points-v2 = <&cpu0_opp_table>; 140 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 141 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 142 #cooling-cells = <2>; 143 L2_100: l2-cache { 144 compatible = "cache"; 145 cache-level = <2>; 146 cache-size = <0x20000>; 147 cache-unified; 148 next-level-cache = <&L3_0>; 149 }; 150 }; 151 152 CPU2: cpu@200 { 153 device_type = "cpu"; 154 compatible = "qcom,kryo485"; 155 reg = <0x0 0x200>; 156 clocks = <&cpufreq_hw 0>; 157 enable-method = "psci"; 158 capacity-dmips-mhz = <448>; 159 dynamic-power-coefficient = <205>; 160 next-level-cache = <&L2_200>; 161 power-domains = <&CPU_PD2>; 162 power-domain-names = "psci"; 163 qcom,freq-domain = <&cpufreq_hw 0>; 164 operating-points-v2 = <&cpu0_opp_table>; 165 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 166 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 167 #cooling-cells = <2>; 168 L2_200: l2-cache { 169 compatible = "cache"; 170 cache-level = <2>; 171 cache-size = <0x20000>; 172 cache-unified; 173 next-level-cache = <&L3_0>; 174 }; 175 }; 176 177 CPU3: cpu@300 { 178 device_type = "cpu"; 179 compatible = "qcom,kryo485"; 180 reg = <0x0 0x300>; 181 clocks = <&cpufreq_hw 0>; 182 enable-method = "psci"; 183 capacity-dmips-mhz = <448>; 184 dynamic-power-coefficient = <205>; 185 next-level-cache = <&L2_300>; 186 power-domains = <&CPU_PD3>; 187 power-domain-names = "psci"; 188 qcom,freq-domain = <&cpufreq_hw 0>; 189 operating-points-v2 = <&cpu0_opp_table>; 190 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 191 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 192 #cooling-cells = <2>; 193 L2_300: l2-cache { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-size = <0x20000>; 197 cache-unified; 198 next-level-cache = <&L3_0>; 199 }; 200 }; 201 202 CPU4: cpu@400 { 203 device_type = "cpu"; 204 compatible = "qcom,kryo485"; 205 reg = <0x0 0x400>; 206 clocks = <&cpufreq_hw 1>; 207 enable-method = "psci"; 208 capacity-dmips-mhz = <1024>; 209 dynamic-power-coefficient = <379>; 210 next-level-cache = <&L2_400>; 211 power-domains = <&CPU_PD4>; 212 power-domain-names = "psci"; 213 qcom,freq-domain = <&cpufreq_hw 1>; 214 operating-points-v2 = <&cpu4_opp_table>; 215 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 216 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 217 #cooling-cells = <2>; 218 L2_400: l2-cache { 219 compatible = "cache"; 220 cache-level = <2>; 221 cache-size = <0x40000>; 222 cache-unified; 223 next-level-cache = <&L3_0>; 224 }; 225 }; 226 227 CPU5: cpu@500 { 228 device_type = "cpu"; 229 compatible = "qcom,kryo485"; 230 reg = <0x0 0x500>; 231 clocks = <&cpufreq_hw 1>; 232 enable-method = "psci"; 233 capacity-dmips-mhz = <1024>; 234 dynamic-power-coefficient = <379>; 235 next-level-cache = <&L2_500>; 236 power-domains = <&CPU_PD5>; 237 power-domain-names = "psci"; 238 qcom,freq-domain = <&cpufreq_hw 1>; 239 operating-points-v2 = <&cpu4_opp_table>; 240 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 241 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 242 #cooling-cells = <2>; 243 L2_500: l2-cache { 244 compatible = "cache"; 245 cache-level = <2>; 246 cache-size = <0x40000>; 247 cache-unified; 248 next-level-cache = <&L3_0>; 249 }; 250 }; 251 252 CPU6: cpu@600 { 253 device_type = "cpu"; 254 compatible = "qcom,kryo485"; 255 reg = <0x0 0x600>; 256 clocks = <&cpufreq_hw 1>; 257 enable-method = "psci"; 258 capacity-dmips-mhz = <1024>; 259 dynamic-power-coefficient = <379>; 260 next-level-cache = <&L2_600>; 261 power-domains = <&CPU_PD6>; 262 power-domain-names = "psci"; 263 qcom,freq-domain = <&cpufreq_hw 1>; 264 operating-points-v2 = <&cpu4_opp_table>; 265 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 266 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 267 #cooling-cells = <2>; 268 L2_600: l2-cache { 269 compatible = "cache"; 270 cache-level = <2>; 271 cache-size = <0x40000>; 272 cache-unified; 273 next-level-cache = <&L3_0>; 274 }; 275 }; 276 277 CPU7: cpu@700 { 278 device_type = "cpu"; 279 compatible = "qcom,kryo485"; 280 reg = <0x0 0x700>; 281 clocks = <&cpufreq_hw 2>; 282 enable-method = "psci"; 283 capacity-dmips-mhz = <1024>; 284 dynamic-power-coefficient = <444>; 285 next-level-cache = <&L2_700>; 286 power-domains = <&CPU_PD7>; 287 power-domain-names = "psci"; 288 qcom,freq-domain = <&cpufreq_hw 2>; 289 operating-points-v2 = <&cpu7_opp_table>; 290 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 291 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 292 #cooling-cells = <2>; 293 L2_700: l2-cache { 294 compatible = "cache"; 295 cache-level = <2>; 296 cache-size = <0x80000>; 297 cache-unified; 298 next-level-cache = <&L3_0>; 299 }; 300 }; 301 302 cpu-map { 303 cluster0 { 304 core0 { 305 cpu = <&CPU0>; 306 }; 307 308 core1 { 309 cpu = <&CPU1>; 310 }; 311 312 core2 { 313 cpu = <&CPU2>; 314 }; 315 316 core3 { 317 cpu = <&CPU3>; 318 }; 319 320 core4 { 321 cpu = <&CPU4>; 322 }; 323 324 core5 { 325 cpu = <&CPU5>; 326 }; 327 328 core6 { 329 cpu = <&CPU6>; 330 }; 331 332 core7 { 333 cpu = <&CPU7>; 334 }; 335 }; 336 }; 337 338 idle-states { 339 entry-method = "psci"; 340 341 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 342 compatible = "arm,idle-state"; 343 idle-state-name = "silver-rail-power-collapse"; 344 arm,psci-suspend-param = <0x40000004>; 345 entry-latency-us = <360>; 346 exit-latency-us = <531>; 347 min-residency-us = <3934>; 348 local-timer-stop; 349 }; 350 351 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 352 compatible = "arm,idle-state"; 353 idle-state-name = "gold-rail-power-collapse"; 354 arm,psci-suspend-param = <0x40000004>; 355 entry-latency-us = <702>; 356 exit-latency-us = <1061>; 357 min-residency-us = <4488>; 358 local-timer-stop; 359 }; 360 }; 361 362 domain-idle-states { 363 CLUSTER_SLEEP_0: cluster-sleep-0 { 364 compatible = "domain-idle-state"; 365 arm,psci-suspend-param = <0x4100c244>; 366 entry-latency-us = <3264>; 367 exit-latency-us = <6562>; 368 min-residency-us = <9987>; 369 }; 370 }; 371 }; 372 373 cpu0_opp_table: opp-table-cpu0 { 374 compatible = "operating-points-v2"; 375 opp-shared; 376 377 cpu0_opp1: opp-300000000 { 378 opp-hz = /bits/ 64 <300000000>; 379 opp-peak-kBps = <800000 9600000>; 380 }; 381 382 cpu0_opp2: opp-403200000 { 383 opp-hz = /bits/ 64 <403200000>; 384 opp-peak-kBps = <800000 9600000>; 385 }; 386 387 cpu0_opp3: opp-518400000 { 388 opp-hz = /bits/ 64 <518400000>; 389 opp-peak-kBps = <800000 16588800>; 390 }; 391 392 cpu0_opp4: opp-614400000 { 393 opp-hz = /bits/ 64 <614400000>; 394 opp-peak-kBps = <800000 16588800>; 395 }; 396 397 cpu0_opp5: opp-691200000 { 398 opp-hz = /bits/ 64 <691200000>; 399 opp-peak-kBps = <800000 19660800>; 400 }; 401 402 cpu0_opp6: opp-787200000 { 403 opp-hz = /bits/ 64 <787200000>; 404 opp-peak-kBps = <1804000 19660800>; 405 }; 406 407 cpu0_opp7: opp-883200000 { 408 opp-hz = /bits/ 64 <883200000>; 409 opp-peak-kBps = <1804000 23347200>; 410 }; 411 412 cpu0_opp8: opp-979200000 { 413 opp-hz = /bits/ 64 <979200000>; 414 opp-peak-kBps = <1804000 26419200>; 415 }; 416 417 cpu0_opp9: opp-1075200000 { 418 opp-hz = /bits/ 64 <1075200000>; 419 opp-peak-kBps = <1804000 29491200>; 420 }; 421 422 cpu0_opp10: opp-1171200000 { 423 opp-hz = /bits/ 64 <1171200000>; 424 opp-peak-kBps = <1804000 32563200>; 425 }; 426 427 cpu0_opp11: opp-1248000000 { 428 opp-hz = /bits/ 64 <1248000000>; 429 opp-peak-kBps = <1804000 36249600>; 430 }; 431 432 cpu0_opp12: opp-1344000000 { 433 opp-hz = /bits/ 64 <1344000000>; 434 opp-peak-kBps = <2188000 36249600>; 435 }; 436 437 cpu0_opp13: opp-1420800000 { 438 opp-hz = /bits/ 64 <1420800000>; 439 opp-peak-kBps = <2188000 39321600>; 440 }; 441 442 cpu0_opp14: opp-1516800000 { 443 opp-hz = /bits/ 64 <1516800000>; 444 opp-peak-kBps = <3072000 42393600>; 445 }; 446 447 cpu0_opp15: opp-1612800000 { 448 opp-hz = /bits/ 64 <1612800000>; 449 opp-peak-kBps = <3072000 42393600>; 450 }; 451 452 cpu0_opp16: opp-1708800000 { 453 opp-hz = /bits/ 64 <1708800000>; 454 opp-peak-kBps = <4068000 42393600>; 455 }; 456 457 cpu0_opp17: opp-1804800000 { 458 opp-hz = /bits/ 64 <1804800000>; 459 opp-peak-kBps = <4068000 42393600>; 460 }; 461 }; 462 463 cpu4_opp_table: opp-table-cpu4 { 464 compatible = "operating-points-v2"; 465 opp-shared; 466 467 cpu4_opp1: opp-710400000 { 468 opp-hz = /bits/ 64 <710400000>; 469 opp-peak-kBps = <1804000 19660800>; 470 }; 471 472 cpu4_opp2: opp-825600000 { 473 opp-hz = /bits/ 64 <825600000>; 474 opp-peak-kBps = <2188000 23347200>; 475 }; 476 477 cpu4_opp3: opp-940800000 { 478 opp-hz = /bits/ 64 <940800000>; 479 opp-peak-kBps = <2188000 26419200>; 480 }; 481 482 cpu4_opp4: opp-1056000000 { 483 opp-hz = /bits/ 64 <1056000000>; 484 opp-peak-kBps = <3072000 26419200>; 485 }; 486 487 cpu4_opp5: opp-1171200000 { 488 opp-hz = /bits/ 64 <1171200000>; 489 opp-peak-kBps = <3072000 29491200>; 490 }; 491 492 cpu4_opp6: opp-1286400000 { 493 opp-hz = /bits/ 64 <1286400000>; 494 opp-peak-kBps = <4068000 29491200>; 495 }; 496 497 cpu4_opp7: opp-1382400000 { 498 opp-hz = /bits/ 64 <1382400000>; 499 opp-peak-kBps = <4068000 32563200>; 500 }; 501 502 cpu4_opp8: opp-1478400000 { 503 opp-hz = /bits/ 64 <1478400000>; 504 opp-peak-kBps = <4068000 32563200>; 505 }; 506 507 cpu4_opp9: opp-1574400000 { 508 opp-hz = /bits/ 64 <1574400000>; 509 opp-peak-kBps = <5412000 39321600>; 510 }; 511 512 cpu4_opp10: opp-1670400000 { 513 opp-hz = /bits/ 64 <1670400000>; 514 opp-peak-kBps = <5412000 42393600>; 515 }; 516 517 cpu4_opp11: opp-1766400000 { 518 opp-hz = /bits/ 64 <1766400000>; 519 opp-peak-kBps = <5412000 45465600>; 520 }; 521 522 cpu4_opp12: opp-1862400000 { 523 opp-hz = /bits/ 64 <1862400000>; 524 opp-peak-kBps = <6220000 45465600>; 525 }; 526 527 cpu4_opp13: opp-1958400000 { 528 opp-hz = /bits/ 64 <1958400000>; 529 opp-peak-kBps = <6220000 48537600>; 530 }; 531 532 cpu4_opp14: opp-2054400000 { 533 opp-hz = /bits/ 64 <2054400000>; 534 opp-peak-kBps = <7216000 48537600>; 535 }; 536 537 cpu4_opp15: opp-2150400000 { 538 opp-hz = /bits/ 64 <2150400000>; 539 opp-peak-kBps = <7216000 51609600>; 540 }; 541 542 cpu4_opp16: opp-2246400000 { 543 opp-hz = /bits/ 64 <2246400000>; 544 opp-peak-kBps = <7216000 51609600>; 545 }; 546 547 cpu4_opp17: opp-2342400000 { 548 opp-hz = /bits/ 64 <2342400000>; 549 opp-peak-kBps = <8368000 51609600>; 550 }; 551 552 cpu4_opp18: opp-2419200000 { 553 opp-hz = /bits/ 64 <2419200000>; 554 opp-peak-kBps = <8368000 51609600>; 555 }; 556 }; 557 558 cpu7_opp_table: opp-table-cpu7 { 559 compatible = "operating-points-v2"; 560 opp-shared; 561 562 cpu7_opp1: opp-844800000 { 563 opp-hz = /bits/ 64 <844800000>; 564 opp-peak-kBps = <2188000 19660800>; 565 }; 566 567 cpu7_opp2: opp-960000000 { 568 opp-hz = /bits/ 64 <960000000>; 569 opp-peak-kBps = <2188000 26419200>; 570 }; 571 572 cpu7_opp3: opp-1075200000 { 573 opp-hz = /bits/ 64 <1075200000>; 574 opp-peak-kBps = <3072000 26419200>; 575 }; 576 577 cpu7_opp4: opp-1190400000 { 578 opp-hz = /bits/ 64 <1190400000>; 579 opp-peak-kBps = <3072000 29491200>; 580 }; 581 582 cpu7_opp5: opp-1305600000 { 583 opp-hz = /bits/ 64 <1305600000>; 584 opp-peak-kBps = <4068000 32563200>; 585 }; 586 587 cpu7_opp6: opp-1401600000 { 588 opp-hz = /bits/ 64 <1401600000>; 589 opp-peak-kBps = <4068000 32563200>; 590 }; 591 592 cpu7_opp7: opp-1516800000 { 593 opp-hz = /bits/ 64 <1516800000>; 594 opp-peak-kBps = <4068000 36249600>; 595 }; 596 597 cpu7_opp8: opp-1632000000 { 598 opp-hz = /bits/ 64 <1632000000>; 599 opp-peak-kBps = <5412000 39321600>; 600 }; 601 602 cpu7_opp9: opp-1747200000 { 603 opp-hz = /bits/ 64 <1708800000>; 604 opp-peak-kBps = <5412000 42393600>; 605 }; 606 607 cpu7_opp10: opp-1862400000 { 608 opp-hz = /bits/ 64 <1862400000>; 609 opp-peak-kBps = <6220000 45465600>; 610 }; 611 612 cpu7_opp11: opp-1977600000 { 613 opp-hz = /bits/ 64 <1977600000>; 614 opp-peak-kBps = <6220000 48537600>; 615 }; 616 617 cpu7_opp12: opp-2073600000 { 618 opp-hz = /bits/ 64 <2073600000>; 619 opp-peak-kBps = <7216000 48537600>; 620 }; 621 622 cpu7_opp13: opp-2169600000 { 623 opp-hz = /bits/ 64 <2169600000>; 624 opp-peak-kBps = <7216000 51609600>; 625 }; 626 627 cpu7_opp14: opp-2265600000 { 628 opp-hz = /bits/ 64 <2265600000>; 629 opp-peak-kBps = <7216000 51609600>; 630 }; 631 632 cpu7_opp15: opp-2361600000 { 633 opp-hz = /bits/ 64 <2361600000>; 634 opp-peak-kBps = <8368000 51609600>; 635 }; 636 637 cpu7_opp16: opp-2457600000 { 638 opp-hz = /bits/ 64 <2457600000>; 639 opp-peak-kBps = <8368000 51609600>; 640 }; 641 642 cpu7_opp17: opp-2553600000 { 643 opp-hz = /bits/ 64 <2553600000>; 644 opp-peak-kBps = <8368000 51609600>; 645 }; 646 647 cpu7_opp18: opp-2649600000 { 648 opp-hz = /bits/ 64 <2649600000>; 649 opp-peak-kBps = <8368000 51609600>; 650 }; 651 652 cpu7_opp19: opp-2745600000 { 653 opp-hz = /bits/ 64 <2745600000>; 654 opp-peak-kBps = <8368000 51609600>; 655 }; 656 657 cpu7_opp20: opp-2841600000 { 658 opp-hz = /bits/ 64 <2841600000>; 659 opp-peak-kBps = <8368000 51609600>; 660 }; 661 }; 662 663 firmware { 664 scm: scm { 665 compatible = "qcom,scm-sm8250", "qcom,scm"; 666 #reset-cells = <1>; 667 }; 668 }; 669 670 memory@80000000 { 671 device_type = "memory"; 672 /* We expect the bootloader to fill in the size */ 673 reg = <0x0 0x80000000 0x0 0x0>; 674 }; 675 676 pmu { 677 compatible = "arm,armv8-pmuv3"; 678 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 679 }; 680 681 psci { 682 compatible = "arm,psci-1.0"; 683 method = "smc"; 684 685 CPU_PD0: power-domain-cpu0 { 686 #power-domain-cells = <0>; 687 power-domains = <&CLUSTER_PD>; 688 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 689 }; 690 691 CPU_PD1: power-domain-cpu1 { 692 #power-domain-cells = <0>; 693 power-domains = <&CLUSTER_PD>; 694 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 695 }; 696 697 CPU_PD2: power-domain-cpu2 { 698 #power-domain-cells = <0>; 699 power-domains = <&CLUSTER_PD>; 700 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 701 }; 702 703 CPU_PD3: power-domain-cpu3 { 704 #power-domain-cells = <0>; 705 power-domains = <&CLUSTER_PD>; 706 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 707 }; 708 709 CPU_PD4: power-domain-cpu4 { 710 #power-domain-cells = <0>; 711 power-domains = <&CLUSTER_PD>; 712 domain-idle-states = <&BIG_CPU_SLEEP_0>; 713 }; 714 715 CPU_PD5: power-domain-cpu5 { 716 #power-domain-cells = <0>; 717 power-domains = <&CLUSTER_PD>; 718 domain-idle-states = <&BIG_CPU_SLEEP_0>; 719 }; 720 721 CPU_PD6: power-domain-cpu6 { 722 #power-domain-cells = <0>; 723 power-domains = <&CLUSTER_PD>; 724 domain-idle-states = <&BIG_CPU_SLEEP_0>; 725 }; 726 727 CPU_PD7: power-domain-cpu7 { 728 #power-domain-cells = <0>; 729 power-domains = <&CLUSTER_PD>; 730 domain-idle-states = <&BIG_CPU_SLEEP_0>; 731 }; 732 733 CLUSTER_PD: power-domain-cpu-cluster0 { 734 #power-domain-cells = <0>; 735 domain-idle-states = <&CLUSTER_SLEEP_0>; 736 }; 737 }; 738 739 qup_opp_table: opp-table-qup { 740 compatible = "operating-points-v2"; 741 742 opp-50000000 { 743 opp-hz = /bits/ 64 <50000000>; 744 required-opps = <&rpmhpd_opp_min_svs>; 745 }; 746 747 opp-75000000 { 748 opp-hz = /bits/ 64 <75000000>; 749 required-opps = <&rpmhpd_opp_low_svs>; 750 }; 751 752 opp-120000000 { 753 opp-hz = /bits/ 64 <120000000>; 754 required-opps = <&rpmhpd_opp_svs>; 755 }; 756 }; 757 758 reserved-memory { 759 #address-cells = <2>; 760 #size-cells = <2>; 761 ranges; 762 763 hyp_mem: memory@80000000 { 764 reg = <0x0 0x80000000 0x0 0x600000>; 765 no-map; 766 }; 767 768 xbl_aop_mem: memory@80700000 { 769 reg = <0x0 0x80700000 0x0 0x160000>; 770 no-map; 771 }; 772 773 cmd_db: memory@80860000 { 774 compatible = "qcom,cmd-db"; 775 reg = <0x0 0x80860000 0x0 0x20000>; 776 no-map; 777 }; 778 779 smem_mem: memory@80900000 { 780 reg = <0x0 0x80900000 0x0 0x200000>; 781 no-map; 782 }; 783 784 removed_mem: memory@80b00000 { 785 reg = <0x0 0x80b00000 0x0 0x5300000>; 786 no-map; 787 }; 788 789 camera_mem: memory@86200000 { 790 reg = <0x0 0x86200000 0x0 0x500000>; 791 no-map; 792 }; 793 794 wlan_mem: memory@86700000 { 795 reg = <0x0 0x86700000 0x0 0x100000>; 796 no-map; 797 }; 798 799 ipa_fw_mem: memory@86800000 { 800 reg = <0x0 0x86800000 0x0 0x10000>; 801 no-map; 802 }; 803 804 ipa_gsi_mem: memory@86810000 { 805 reg = <0x0 0x86810000 0x0 0xa000>; 806 no-map; 807 }; 808 809 gpu_mem: memory@8681a000 { 810 reg = <0x0 0x8681a000 0x0 0x2000>; 811 no-map; 812 }; 813 814 npu_mem: memory@86900000 { 815 reg = <0x0 0x86900000 0x0 0x500000>; 816 no-map; 817 }; 818 819 video_mem: memory@86e00000 { 820 reg = <0x0 0x86e00000 0x0 0x500000>; 821 no-map; 822 }; 823 824 cvp_mem: memory@87300000 { 825 reg = <0x0 0x87300000 0x0 0x500000>; 826 no-map; 827 }; 828 829 cdsp_mem: memory@87800000 { 830 reg = <0x0 0x87800000 0x0 0x1400000>; 831 no-map; 832 }; 833 834 slpi_mem: memory@88c00000 { 835 reg = <0x0 0x88c00000 0x0 0x1500000>; 836 no-map; 837 }; 838 839 adsp_mem: memory@8a100000 { 840 reg = <0x0 0x8a100000 0x0 0x1d00000>; 841 no-map; 842 }; 843 844 spss_mem: memory@8be00000 { 845 reg = <0x0 0x8be00000 0x0 0x100000>; 846 no-map; 847 }; 848 849 cdsp_secure_heap: memory@8bf00000 { 850 reg = <0x0 0x8bf00000 0x0 0x4600000>; 851 no-map; 852 }; 853 }; 854 855 smem { 856 compatible = "qcom,smem"; 857 memory-region = <&smem_mem>; 858 hwlocks = <&tcsr_mutex 3>; 859 }; 860 861 smp2p-adsp { 862 compatible = "qcom,smp2p"; 863 qcom,smem = <443>, <429>; 864 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 865 IPCC_MPROC_SIGNAL_SMP2P 866 IRQ_TYPE_EDGE_RISING>; 867 mboxes = <&ipcc IPCC_CLIENT_LPASS 868 IPCC_MPROC_SIGNAL_SMP2P>; 869 870 qcom,local-pid = <0>; 871 qcom,remote-pid = <2>; 872 873 smp2p_adsp_out: master-kernel { 874 qcom,entry-name = "master-kernel"; 875 #qcom,smem-state-cells = <1>; 876 }; 877 878 smp2p_adsp_in: slave-kernel { 879 qcom,entry-name = "slave-kernel"; 880 interrupt-controller; 881 #interrupt-cells = <2>; 882 }; 883 }; 884 885 smp2p-cdsp { 886 compatible = "qcom,smp2p"; 887 qcom,smem = <94>, <432>; 888 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 889 IPCC_MPROC_SIGNAL_SMP2P 890 IRQ_TYPE_EDGE_RISING>; 891 mboxes = <&ipcc IPCC_CLIENT_CDSP 892 IPCC_MPROC_SIGNAL_SMP2P>; 893 894 qcom,local-pid = <0>; 895 qcom,remote-pid = <5>; 896 897 smp2p_cdsp_out: master-kernel { 898 qcom,entry-name = "master-kernel"; 899 #qcom,smem-state-cells = <1>; 900 }; 901 902 smp2p_cdsp_in: slave-kernel { 903 qcom,entry-name = "slave-kernel"; 904 interrupt-controller; 905 #interrupt-cells = <2>; 906 }; 907 }; 908 909 smp2p-slpi { 910 compatible = "qcom,smp2p"; 911 qcom,smem = <481>, <430>; 912 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 913 IPCC_MPROC_SIGNAL_SMP2P 914 IRQ_TYPE_EDGE_RISING>; 915 mboxes = <&ipcc IPCC_CLIENT_SLPI 916 IPCC_MPROC_SIGNAL_SMP2P>; 917 918 qcom,local-pid = <0>; 919 qcom,remote-pid = <3>; 920 921 smp2p_slpi_out: master-kernel { 922 qcom,entry-name = "master-kernel"; 923 #qcom,smem-state-cells = <1>; 924 }; 925 926 smp2p_slpi_in: slave-kernel { 927 qcom,entry-name = "slave-kernel"; 928 interrupt-controller; 929 #interrupt-cells = <2>; 930 }; 931 }; 932 933 soc: soc@0 { 934 #address-cells = <2>; 935 #size-cells = <2>; 936 ranges = <0 0 0 0 0x10 0>; 937 dma-ranges = <0 0 0 0 0x10 0>; 938 compatible = "simple-bus"; 939 940 gcc: clock-controller@100000 { 941 compatible = "qcom,gcc-sm8250"; 942 reg = <0x0 0x00100000 0x0 0x1f0000>; 943 #clock-cells = <1>; 944 #reset-cells = <1>; 945 #power-domain-cells = <1>; 946 clock-names = "bi_tcxo", 947 "bi_tcxo_ao", 948 "sleep_clk"; 949 clocks = <&rpmhcc RPMH_CXO_CLK>, 950 <&rpmhcc RPMH_CXO_CLK_A>, 951 <&sleep_clk>; 952 }; 953 954 ipcc: mailbox@408000 { 955 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 956 reg = <0 0x00408000 0 0x1000>; 957 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 958 interrupt-controller; 959 #interrupt-cells = <3>; 960 #mbox-cells = <2>; 961 }; 962 963 qfprom: efuse@784000 { 964 compatible = "qcom,sm8250-qfprom", "qcom,qfprom"; 965 reg = <0 0x00784000 0 0x8ff>; 966 #address-cells = <1>; 967 #size-cells = <1>; 968 969 gpu_speed_bin: gpu_speed_bin@19b { 970 reg = <0x19b 0x1>; 971 bits = <5 3>; 972 }; 973 }; 974 975 rng: rng@793000 { 976 compatible = "qcom,prng-ee"; 977 reg = <0 0x00793000 0 0x1000>; 978 clocks = <&gcc GCC_PRNG_AHB_CLK>; 979 clock-names = "core"; 980 }; 981 982 gpi_dma2: dma-controller@800000 { 983 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 984 reg = <0 0x00800000 0 0x70000>; 985 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 995 dma-channels = <10>; 996 dma-channel-mask = <0x3f>; 997 iommus = <&apps_smmu 0x76 0x0>; 998 #dma-cells = <3>; 999 status = "disabled"; 1000 }; 1001 1002 qupv3_id_2: geniqup@8c0000 { 1003 compatible = "qcom,geni-se-qup"; 1004 reg = <0x0 0x008c0000 0x0 0x6000>; 1005 clock-names = "m-ahb", "s-ahb"; 1006 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1007 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1008 #address-cells = <2>; 1009 #size-cells = <2>; 1010 iommus = <&apps_smmu 0x63 0x0>; 1011 ranges; 1012 status = "disabled"; 1013 1014 i2c14: i2c@880000 { 1015 compatible = "qcom,geni-i2c"; 1016 reg = <0 0x00880000 0 0x4000>; 1017 clock-names = "se"; 1018 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&qup_i2c14_default>; 1021 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1022 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1023 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1024 dma-names = "tx", "rx"; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 status = "disabled"; 1028 }; 1029 1030 spi14: spi@880000 { 1031 compatible = "qcom,geni-spi"; 1032 reg = <0 0x00880000 0 0x4000>; 1033 clock-names = "se"; 1034 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1035 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1036 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1037 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1038 dma-names = "tx", "rx"; 1039 power-domains = <&rpmhpd SM8250_CX>; 1040 operating-points-v2 = <&qup_opp_table>; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 status = "disabled"; 1044 }; 1045 1046 i2c15: i2c@884000 { 1047 compatible = "qcom,geni-i2c"; 1048 reg = <0 0x00884000 0 0x4000>; 1049 clock-names = "se"; 1050 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1051 pinctrl-names = "default"; 1052 pinctrl-0 = <&qup_i2c15_default>; 1053 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1054 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1055 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1056 dma-names = "tx", "rx"; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 status = "disabled"; 1060 }; 1061 1062 spi15: spi@884000 { 1063 compatible = "qcom,geni-spi"; 1064 reg = <0 0x00884000 0 0x4000>; 1065 clock-names = "se"; 1066 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1067 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1068 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1069 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1070 dma-names = "tx", "rx"; 1071 power-domains = <&rpmhpd SM8250_CX>; 1072 operating-points-v2 = <&qup_opp_table>; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 status = "disabled"; 1076 }; 1077 1078 i2c16: i2c@888000 { 1079 compatible = "qcom,geni-i2c"; 1080 reg = <0 0x00888000 0 0x4000>; 1081 clock-names = "se"; 1082 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1083 pinctrl-names = "default"; 1084 pinctrl-0 = <&qup_i2c16_default>; 1085 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1086 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1087 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1088 dma-names = "tx", "rx"; 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 status = "disabled"; 1092 }; 1093 1094 spi16: spi@888000 { 1095 compatible = "qcom,geni-spi"; 1096 reg = <0 0x00888000 0 0x4000>; 1097 clock-names = "se"; 1098 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1099 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1100 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1101 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1102 dma-names = "tx", "rx"; 1103 power-domains = <&rpmhpd SM8250_CX>; 1104 operating-points-v2 = <&qup_opp_table>; 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 status = "disabled"; 1108 }; 1109 1110 i2c17: i2c@88c000 { 1111 compatible = "qcom,geni-i2c"; 1112 reg = <0 0x0088c000 0 0x4000>; 1113 clock-names = "se"; 1114 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1115 pinctrl-names = "default"; 1116 pinctrl-0 = <&qup_i2c17_default>; 1117 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1118 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1119 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1120 dma-names = "tx", "rx"; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 status = "disabled"; 1124 }; 1125 1126 spi17: spi@88c000 { 1127 compatible = "qcom,geni-spi"; 1128 reg = <0 0x0088c000 0 0x4000>; 1129 clock-names = "se"; 1130 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1131 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1132 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1133 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1134 dma-names = "tx", "rx"; 1135 power-domains = <&rpmhpd SM8250_CX>; 1136 operating-points-v2 = <&qup_opp_table>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 status = "disabled"; 1140 }; 1141 1142 uart17: serial@88c000 { 1143 compatible = "qcom,geni-uart"; 1144 reg = <0 0x0088c000 0 0x4000>; 1145 clock-names = "se"; 1146 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1147 pinctrl-names = "default"; 1148 pinctrl-0 = <&qup_uart17_default>; 1149 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1150 power-domains = <&rpmhpd SM8250_CX>; 1151 operating-points-v2 = <&qup_opp_table>; 1152 status = "disabled"; 1153 }; 1154 1155 i2c18: i2c@890000 { 1156 compatible = "qcom,geni-i2c"; 1157 reg = <0 0x00890000 0 0x4000>; 1158 clock-names = "se"; 1159 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1160 pinctrl-names = "default"; 1161 pinctrl-0 = <&qup_i2c18_default>; 1162 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1163 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1164 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1165 dma-names = "tx", "rx"; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 status = "disabled"; 1169 }; 1170 1171 spi18: spi@890000 { 1172 compatible = "qcom,geni-spi"; 1173 reg = <0 0x00890000 0 0x4000>; 1174 clock-names = "se"; 1175 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1176 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1177 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1178 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1179 dma-names = "tx", "rx"; 1180 power-domains = <&rpmhpd SM8250_CX>; 1181 operating-points-v2 = <&qup_opp_table>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 status = "disabled"; 1185 }; 1186 1187 uart18: serial@890000 { 1188 compatible = "qcom,geni-uart"; 1189 reg = <0 0x00890000 0 0x4000>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&qup_uart18_default>; 1194 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1195 power-domains = <&rpmhpd SM8250_CX>; 1196 operating-points-v2 = <&qup_opp_table>; 1197 status = "disabled"; 1198 }; 1199 1200 i2c19: i2c@894000 { 1201 compatible = "qcom,geni-i2c"; 1202 reg = <0 0x00894000 0 0x4000>; 1203 clock-names = "se"; 1204 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1205 pinctrl-names = "default"; 1206 pinctrl-0 = <&qup_i2c19_default>; 1207 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1208 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1209 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1210 dma-names = "tx", "rx"; 1211 #address-cells = <1>; 1212 #size-cells = <0>; 1213 status = "disabled"; 1214 }; 1215 1216 spi19: spi@894000 { 1217 compatible = "qcom,geni-spi"; 1218 reg = <0 0x00894000 0 0x4000>; 1219 clock-names = "se"; 1220 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1221 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1222 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1223 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1224 dma-names = "tx", "rx"; 1225 power-domains = <&rpmhpd SM8250_CX>; 1226 operating-points-v2 = <&qup_opp_table>; 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 status = "disabled"; 1230 }; 1231 }; 1232 1233 gpi_dma0: dma-controller@900000 { 1234 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1235 reg = <0 0x00900000 0 0x70000>; 1236 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1249 dma-channels = <15>; 1250 dma-channel-mask = <0x7ff>; 1251 iommus = <&apps_smmu 0x5b6 0x0>; 1252 #dma-cells = <3>; 1253 status = "disabled"; 1254 }; 1255 1256 qupv3_id_0: geniqup@9c0000 { 1257 compatible = "qcom,geni-se-qup"; 1258 reg = <0x0 0x009c0000 0x0 0x6000>; 1259 clock-names = "m-ahb", "s-ahb"; 1260 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1261 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1262 #address-cells = <2>; 1263 #size-cells = <2>; 1264 iommus = <&apps_smmu 0x5a3 0x0>; 1265 ranges; 1266 status = "disabled"; 1267 1268 i2c0: i2c@980000 { 1269 compatible = "qcom,geni-i2c"; 1270 reg = <0 0x00980000 0 0x4000>; 1271 clock-names = "se"; 1272 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1273 pinctrl-names = "default"; 1274 pinctrl-0 = <&qup_i2c0_default>; 1275 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1276 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1277 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1278 dma-names = "tx", "rx"; 1279 #address-cells = <1>; 1280 #size-cells = <0>; 1281 status = "disabled"; 1282 }; 1283 1284 spi0: spi@980000 { 1285 compatible = "qcom,geni-spi"; 1286 reg = <0 0x00980000 0 0x4000>; 1287 clock-names = "se"; 1288 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1289 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1290 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1291 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1292 dma-names = "tx", "rx"; 1293 power-domains = <&rpmhpd SM8250_CX>; 1294 operating-points-v2 = <&qup_opp_table>; 1295 #address-cells = <1>; 1296 #size-cells = <0>; 1297 status = "disabled"; 1298 }; 1299 1300 i2c1: i2c@984000 { 1301 compatible = "qcom,geni-i2c"; 1302 reg = <0 0x00984000 0 0x4000>; 1303 clock-names = "se"; 1304 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1305 pinctrl-names = "default"; 1306 pinctrl-0 = <&qup_i2c1_default>; 1307 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1308 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1309 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1310 dma-names = "tx", "rx"; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 status = "disabled"; 1314 }; 1315 1316 spi1: spi@984000 { 1317 compatible = "qcom,geni-spi"; 1318 reg = <0 0x00984000 0 0x4000>; 1319 clock-names = "se"; 1320 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1321 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1322 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1323 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1324 dma-names = "tx", "rx"; 1325 power-domains = <&rpmhpd SM8250_CX>; 1326 operating-points-v2 = <&qup_opp_table>; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 status = "disabled"; 1330 }; 1331 1332 i2c2: i2c@988000 { 1333 compatible = "qcom,geni-i2c"; 1334 reg = <0 0x00988000 0 0x4000>; 1335 clock-names = "se"; 1336 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1337 pinctrl-names = "default"; 1338 pinctrl-0 = <&qup_i2c2_default>; 1339 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1340 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1341 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1342 dma-names = "tx", "rx"; 1343 #address-cells = <1>; 1344 #size-cells = <0>; 1345 status = "disabled"; 1346 }; 1347 1348 spi2: spi@988000 { 1349 compatible = "qcom,geni-spi"; 1350 reg = <0 0x00988000 0 0x4000>; 1351 clock-names = "se"; 1352 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1353 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1354 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1355 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1356 dma-names = "tx", "rx"; 1357 power-domains = <&rpmhpd SM8250_CX>; 1358 operating-points-v2 = <&qup_opp_table>; 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 status = "disabled"; 1362 }; 1363 1364 uart2: serial@988000 { 1365 compatible = "qcom,geni-debug-uart"; 1366 reg = <0 0x00988000 0 0x4000>; 1367 clock-names = "se"; 1368 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1369 pinctrl-names = "default"; 1370 pinctrl-0 = <&qup_uart2_default>; 1371 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1372 power-domains = <&rpmhpd SM8250_CX>; 1373 operating-points-v2 = <&qup_opp_table>; 1374 status = "disabled"; 1375 }; 1376 1377 i2c3: i2c@98c000 { 1378 compatible = "qcom,geni-i2c"; 1379 reg = <0 0x0098c000 0 0x4000>; 1380 clock-names = "se"; 1381 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1382 pinctrl-names = "default"; 1383 pinctrl-0 = <&qup_i2c3_default>; 1384 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1385 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1386 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1387 dma-names = "tx", "rx"; 1388 #address-cells = <1>; 1389 #size-cells = <0>; 1390 status = "disabled"; 1391 }; 1392 1393 spi3: spi@98c000 { 1394 compatible = "qcom,geni-spi"; 1395 reg = <0 0x0098c000 0 0x4000>; 1396 clock-names = "se"; 1397 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1398 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1399 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1400 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1401 dma-names = "tx", "rx"; 1402 power-domains = <&rpmhpd SM8250_CX>; 1403 operating-points-v2 = <&qup_opp_table>; 1404 #address-cells = <1>; 1405 #size-cells = <0>; 1406 status = "disabled"; 1407 }; 1408 1409 i2c4: i2c@990000 { 1410 compatible = "qcom,geni-i2c"; 1411 reg = <0 0x00990000 0 0x4000>; 1412 clock-names = "se"; 1413 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1414 pinctrl-names = "default"; 1415 pinctrl-0 = <&qup_i2c4_default>; 1416 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1417 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1418 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1419 dma-names = "tx", "rx"; 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 status = "disabled"; 1423 }; 1424 1425 spi4: spi@990000 { 1426 compatible = "qcom,geni-spi"; 1427 reg = <0 0x00990000 0 0x4000>; 1428 clock-names = "se"; 1429 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1430 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1431 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1432 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1433 dma-names = "tx", "rx"; 1434 power-domains = <&rpmhpd SM8250_CX>; 1435 operating-points-v2 = <&qup_opp_table>; 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 status = "disabled"; 1439 }; 1440 1441 i2c5: i2c@994000 { 1442 compatible = "qcom,geni-i2c"; 1443 reg = <0 0x00994000 0 0x4000>; 1444 clock-names = "se"; 1445 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1446 pinctrl-names = "default"; 1447 pinctrl-0 = <&qup_i2c5_default>; 1448 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1449 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1450 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1451 dma-names = "tx", "rx"; 1452 #address-cells = <1>; 1453 #size-cells = <0>; 1454 status = "disabled"; 1455 }; 1456 1457 spi5: spi@994000 { 1458 compatible = "qcom,geni-spi"; 1459 reg = <0 0x00994000 0 0x4000>; 1460 clock-names = "se"; 1461 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1462 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1463 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1464 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1465 dma-names = "tx", "rx"; 1466 power-domains = <&rpmhpd SM8250_CX>; 1467 operating-points-v2 = <&qup_opp_table>; 1468 #address-cells = <1>; 1469 #size-cells = <0>; 1470 status = "disabled"; 1471 }; 1472 1473 i2c6: i2c@998000 { 1474 compatible = "qcom,geni-i2c"; 1475 reg = <0 0x00998000 0 0x4000>; 1476 clock-names = "se"; 1477 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1478 pinctrl-names = "default"; 1479 pinctrl-0 = <&qup_i2c6_default>; 1480 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1481 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1482 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1483 dma-names = "tx", "rx"; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 status = "disabled"; 1487 }; 1488 1489 spi6: spi@998000 { 1490 compatible = "qcom,geni-spi"; 1491 reg = <0 0x00998000 0 0x4000>; 1492 clock-names = "se"; 1493 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1494 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1495 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1496 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1497 dma-names = "tx", "rx"; 1498 power-domains = <&rpmhpd SM8250_CX>; 1499 operating-points-v2 = <&qup_opp_table>; 1500 #address-cells = <1>; 1501 #size-cells = <0>; 1502 status = "disabled"; 1503 }; 1504 1505 uart6: serial@998000 { 1506 compatible = "qcom,geni-uart"; 1507 reg = <0 0x00998000 0 0x4000>; 1508 clock-names = "se"; 1509 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1510 pinctrl-names = "default"; 1511 pinctrl-0 = <&qup_uart6_default>; 1512 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1513 power-domains = <&rpmhpd SM8250_CX>; 1514 operating-points-v2 = <&qup_opp_table>; 1515 status = "disabled"; 1516 }; 1517 1518 i2c7: i2c@99c000 { 1519 compatible = "qcom,geni-i2c"; 1520 reg = <0 0x0099c000 0 0x4000>; 1521 clock-names = "se"; 1522 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1523 pinctrl-names = "default"; 1524 pinctrl-0 = <&qup_i2c7_default>; 1525 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1526 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1527 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1528 dma-names = "tx", "rx"; 1529 #address-cells = <1>; 1530 #size-cells = <0>; 1531 status = "disabled"; 1532 }; 1533 1534 spi7: spi@99c000 { 1535 compatible = "qcom,geni-spi"; 1536 reg = <0 0x0099c000 0 0x4000>; 1537 clock-names = "se"; 1538 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1539 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1540 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1541 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1542 dma-names = "tx", "rx"; 1543 power-domains = <&rpmhpd SM8250_CX>; 1544 operating-points-v2 = <&qup_opp_table>; 1545 #address-cells = <1>; 1546 #size-cells = <0>; 1547 status = "disabled"; 1548 }; 1549 }; 1550 1551 gpi_dma1: dma-controller@a00000 { 1552 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1553 reg = <0 0x00a00000 0 0x70000>; 1554 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1564 dma-channels = <10>; 1565 dma-channel-mask = <0x3f>; 1566 iommus = <&apps_smmu 0x56 0x0>; 1567 #dma-cells = <3>; 1568 status = "disabled"; 1569 }; 1570 1571 qupv3_id_1: geniqup@ac0000 { 1572 compatible = "qcom,geni-se-qup"; 1573 reg = <0x0 0x00ac0000 0x0 0x6000>; 1574 clock-names = "m-ahb", "s-ahb"; 1575 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1576 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1577 #address-cells = <2>; 1578 #size-cells = <2>; 1579 iommus = <&apps_smmu 0x43 0x0>; 1580 ranges; 1581 status = "disabled"; 1582 1583 i2c8: i2c@a80000 { 1584 compatible = "qcom,geni-i2c"; 1585 reg = <0 0x00a80000 0 0x4000>; 1586 clock-names = "se"; 1587 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1588 pinctrl-names = "default"; 1589 pinctrl-0 = <&qup_i2c8_default>; 1590 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1591 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1592 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1593 dma-names = "tx", "rx"; 1594 #address-cells = <1>; 1595 #size-cells = <0>; 1596 status = "disabled"; 1597 }; 1598 1599 spi8: spi@a80000 { 1600 compatible = "qcom,geni-spi"; 1601 reg = <0 0x00a80000 0 0x4000>; 1602 clock-names = "se"; 1603 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1604 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1605 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1606 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1607 dma-names = "tx", "rx"; 1608 power-domains = <&rpmhpd SM8250_CX>; 1609 operating-points-v2 = <&qup_opp_table>; 1610 #address-cells = <1>; 1611 #size-cells = <0>; 1612 status = "disabled"; 1613 }; 1614 1615 i2c9: i2c@a84000 { 1616 compatible = "qcom,geni-i2c"; 1617 reg = <0 0x00a84000 0 0x4000>; 1618 clock-names = "se"; 1619 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1620 pinctrl-names = "default"; 1621 pinctrl-0 = <&qup_i2c9_default>; 1622 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1623 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1624 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1625 dma-names = "tx", "rx"; 1626 #address-cells = <1>; 1627 #size-cells = <0>; 1628 status = "disabled"; 1629 }; 1630 1631 spi9: spi@a84000 { 1632 compatible = "qcom,geni-spi"; 1633 reg = <0 0x00a84000 0 0x4000>; 1634 clock-names = "se"; 1635 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1636 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1637 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1638 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1639 dma-names = "tx", "rx"; 1640 power-domains = <&rpmhpd SM8250_CX>; 1641 operating-points-v2 = <&qup_opp_table>; 1642 #address-cells = <1>; 1643 #size-cells = <0>; 1644 status = "disabled"; 1645 }; 1646 1647 i2c10: i2c@a88000 { 1648 compatible = "qcom,geni-i2c"; 1649 reg = <0 0x00a88000 0 0x4000>; 1650 clock-names = "se"; 1651 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1652 pinctrl-names = "default"; 1653 pinctrl-0 = <&qup_i2c10_default>; 1654 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1655 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1656 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1657 dma-names = "tx", "rx"; 1658 #address-cells = <1>; 1659 #size-cells = <0>; 1660 status = "disabled"; 1661 }; 1662 1663 spi10: spi@a88000 { 1664 compatible = "qcom,geni-spi"; 1665 reg = <0 0x00a88000 0 0x4000>; 1666 clock-names = "se"; 1667 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1668 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1669 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1670 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1671 dma-names = "tx", "rx"; 1672 power-domains = <&rpmhpd SM8250_CX>; 1673 operating-points-v2 = <&qup_opp_table>; 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 status = "disabled"; 1677 }; 1678 1679 i2c11: i2c@a8c000 { 1680 compatible = "qcom,geni-i2c"; 1681 reg = <0 0x00a8c000 0 0x4000>; 1682 clock-names = "se"; 1683 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1684 pinctrl-names = "default"; 1685 pinctrl-0 = <&qup_i2c11_default>; 1686 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1687 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1688 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1689 dma-names = "tx", "rx"; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 status = "disabled"; 1693 }; 1694 1695 spi11: spi@a8c000 { 1696 compatible = "qcom,geni-spi"; 1697 reg = <0 0x00a8c000 0 0x4000>; 1698 clock-names = "se"; 1699 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1700 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1701 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1702 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1703 dma-names = "tx", "rx"; 1704 power-domains = <&rpmhpd SM8250_CX>; 1705 operating-points-v2 = <&qup_opp_table>; 1706 #address-cells = <1>; 1707 #size-cells = <0>; 1708 status = "disabled"; 1709 }; 1710 1711 i2c12: i2c@a90000 { 1712 compatible = "qcom,geni-i2c"; 1713 reg = <0 0x00a90000 0 0x4000>; 1714 clock-names = "se"; 1715 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1716 pinctrl-names = "default"; 1717 pinctrl-0 = <&qup_i2c12_default>; 1718 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1719 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1720 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1721 dma-names = "tx", "rx"; 1722 #address-cells = <1>; 1723 #size-cells = <0>; 1724 status = "disabled"; 1725 }; 1726 1727 spi12: spi@a90000 { 1728 compatible = "qcom,geni-spi"; 1729 reg = <0 0x00a90000 0 0x4000>; 1730 clock-names = "se"; 1731 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1732 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1733 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1734 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1735 dma-names = "tx", "rx"; 1736 power-domains = <&rpmhpd SM8250_CX>; 1737 operating-points-v2 = <&qup_opp_table>; 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 status = "disabled"; 1741 }; 1742 1743 uart12: serial@a90000 { 1744 compatible = "qcom,geni-debug-uart"; 1745 reg = <0x0 0x00a90000 0x0 0x4000>; 1746 clock-names = "se"; 1747 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1748 pinctrl-names = "default"; 1749 pinctrl-0 = <&qup_uart12_default>; 1750 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1751 power-domains = <&rpmhpd SM8250_CX>; 1752 operating-points-v2 = <&qup_opp_table>; 1753 status = "disabled"; 1754 }; 1755 1756 i2c13: i2c@a94000 { 1757 compatible = "qcom,geni-i2c"; 1758 reg = <0 0x00a94000 0 0x4000>; 1759 clock-names = "se"; 1760 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1761 pinctrl-names = "default"; 1762 pinctrl-0 = <&qup_i2c13_default>; 1763 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1764 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1765 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1766 dma-names = "tx", "rx"; 1767 #address-cells = <1>; 1768 #size-cells = <0>; 1769 status = "disabled"; 1770 }; 1771 1772 spi13: spi@a94000 { 1773 compatible = "qcom,geni-spi"; 1774 reg = <0 0x00a94000 0 0x4000>; 1775 clock-names = "se"; 1776 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1777 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1778 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1779 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1780 dma-names = "tx", "rx"; 1781 power-domains = <&rpmhpd SM8250_CX>; 1782 operating-points-v2 = <&qup_opp_table>; 1783 #address-cells = <1>; 1784 #size-cells = <0>; 1785 status = "disabled"; 1786 }; 1787 }; 1788 1789 config_noc: interconnect@1500000 { 1790 compatible = "qcom,sm8250-config-noc"; 1791 reg = <0 0x01500000 0 0xa580>; 1792 #interconnect-cells = <1>; 1793 qcom,bcm-voters = <&apps_bcm_voter>; 1794 }; 1795 1796 system_noc: interconnect@1620000 { 1797 compatible = "qcom,sm8250-system-noc"; 1798 reg = <0 0x01620000 0 0x1c200>; 1799 #interconnect-cells = <1>; 1800 qcom,bcm-voters = <&apps_bcm_voter>; 1801 }; 1802 1803 mc_virt: interconnect@163d000 { 1804 compatible = "qcom,sm8250-mc-virt"; 1805 reg = <0 0x0163d000 0 0x1000>; 1806 #interconnect-cells = <1>; 1807 qcom,bcm-voters = <&apps_bcm_voter>; 1808 }; 1809 1810 aggre1_noc: interconnect@16e0000 { 1811 compatible = "qcom,sm8250-aggre1-noc"; 1812 reg = <0 0x016e0000 0 0x1f180>; 1813 #interconnect-cells = <1>; 1814 qcom,bcm-voters = <&apps_bcm_voter>; 1815 }; 1816 1817 aggre2_noc: interconnect@1700000 { 1818 compatible = "qcom,sm8250-aggre2-noc"; 1819 reg = <0 0x01700000 0 0x33000>; 1820 #interconnect-cells = <1>; 1821 qcom,bcm-voters = <&apps_bcm_voter>; 1822 }; 1823 1824 compute_noc: interconnect@1733000 { 1825 compatible = "qcom,sm8250-compute-noc"; 1826 reg = <0 0x01733000 0 0xa180>; 1827 #interconnect-cells = <1>; 1828 qcom,bcm-voters = <&apps_bcm_voter>; 1829 }; 1830 1831 mmss_noc: interconnect@1740000 { 1832 compatible = "qcom,sm8250-mmss-noc"; 1833 reg = <0 0x01740000 0 0x1f080>; 1834 #interconnect-cells = <1>; 1835 qcom,bcm-voters = <&apps_bcm_voter>; 1836 }; 1837 1838 pcie0: pci@1c00000 { 1839 compatible = "qcom,pcie-sm8250"; 1840 reg = <0 0x01c00000 0 0x3000>, 1841 <0 0x60000000 0 0xf1d>, 1842 <0 0x60000f20 0 0xa8>, 1843 <0 0x60001000 0 0x1000>, 1844 <0 0x60100000 0 0x100000>, 1845 <0 0x01c03000 0 0x1000>; 1846 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1847 device_type = "pci"; 1848 linux,pci-domain = <0>; 1849 bus-range = <0x00 0xff>; 1850 num-lanes = <1>; 1851 1852 #address-cells = <3>; 1853 #size-cells = <2>; 1854 1855 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1856 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1857 1858 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1866 interrupt-names = "msi0", "msi1", "msi2", "msi3", 1867 "msi4", "msi5", "msi6", "msi7"; 1868 #interrupt-cells = <1>; 1869 interrupt-map-mask = <0 0 0 0x7>; 1870 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1871 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1872 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1873 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1874 1875 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1876 <&gcc GCC_PCIE_0_AUX_CLK>, 1877 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1878 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1879 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1880 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1881 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1882 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1883 clock-names = "pipe", 1884 "aux", 1885 "cfg", 1886 "bus_master", 1887 "bus_slave", 1888 "slave_q2a", 1889 "tbu", 1890 "ddrss_sf_tbu"; 1891 1892 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1893 <0x100 &apps_smmu 0x1c01 0x1>; 1894 1895 resets = <&gcc GCC_PCIE_0_BCR>; 1896 reset-names = "pci"; 1897 1898 power-domains = <&gcc PCIE_0_GDSC>; 1899 1900 phys = <&pcie0_lane>; 1901 phy-names = "pciephy"; 1902 1903 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; 1904 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 1905 1906 pinctrl-names = "default"; 1907 pinctrl-0 = <&pcie0_default_state>; 1908 1909 status = "disabled"; 1910 }; 1911 1912 pcie0_phy: phy@1c06000 { 1913 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1914 reg = <0 0x01c06000 0 0x1c0>; 1915 #address-cells = <2>; 1916 #size-cells = <2>; 1917 ranges; 1918 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1919 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1920 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1921 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1922 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1923 1924 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1925 reset-names = "phy"; 1926 1927 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1928 assigned-clock-rates = <100000000>; 1929 1930 status = "disabled"; 1931 1932 pcie0_lane: phy@1c06200 { 1933 reg = <0 0x01c06200 0 0x170>, /* tx */ 1934 <0 0x01c06400 0 0x200>, /* rx */ 1935 <0 0x01c06800 0 0x1f0>, /* pcs */ 1936 <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1937 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1938 clock-names = "pipe0"; 1939 1940 #phy-cells = <0>; 1941 1942 #clock-cells = <0>; 1943 clock-output-names = "pcie_0_pipe_clk"; 1944 }; 1945 }; 1946 1947 pcie1: pci@1c08000 { 1948 compatible = "qcom,pcie-sm8250"; 1949 reg = <0 0x01c08000 0 0x3000>, 1950 <0 0x40000000 0 0xf1d>, 1951 <0 0x40000f20 0 0xa8>, 1952 <0 0x40001000 0 0x1000>, 1953 <0 0x40100000 0 0x100000>, 1954 <0 0x01c0b000 0 0x1000>; 1955 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1956 device_type = "pci"; 1957 linux,pci-domain = <1>; 1958 bus-range = <0x00 0xff>; 1959 num-lanes = <2>; 1960 1961 #address-cells = <3>; 1962 #size-cells = <2>; 1963 1964 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1965 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1966 1967 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1968 interrupt-names = "msi"; 1969 #interrupt-cells = <1>; 1970 interrupt-map-mask = <0 0 0 0x7>; 1971 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1972 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1973 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1974 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1975 1976 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1977 <&gcc GCC_PCIE_1_AUX_CLK>, 1978 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1979 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1980 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1981 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1982 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1983 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1984 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1985 clock-names = "pipe", 1986 "aux", 1987 "cfg", 1988 "bus_master", 1989 "bus_slave", 1990 "slave_q2a", 1991 "ref", 1992 "tbu", 1993 "ddrss_sf_tbu"; 1994 1995 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1996 assigned-clock-rates = <19200000>; 1997 1998 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1999 <0x100 &apps_smmu 0x1c81 0x1>; 2000 2001 resets = <&gcc GCC_PCIE_1_BCR>; 2002 reset-names = "pci"; 2003 2004 power-domains = <&gcc PCIE_1_GDSC>; 2005 2006 phys = <&pcie1_lane>; 2007 phy-names = "pciephy"; 2008 2009 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; 2010 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; 2011 2012 pinctrl-names = "default"; 2013 pinctrl-0 = <&pcie1_default_state>; 2014 2015 status = "disabled"; 2016 }; 2017 2018 pcie1_phy: phy@1c0e000 { 2019 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2020 reg = <0 0x01c0e000 0 0x1c0>; 2021 #address-cells = <2>; 2022 #size-cells = <2>; 2023 ranges; 2024 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2025 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2026 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 2027 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2028 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2029 2030 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2031 reset-names = "phy"; 2032 2033 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2034 assigned-clock-rates = <100000000>; 2035 2036 status = "disabled"; 2037 2038 pcie1_lane: phy@1c0e200 { 2039 reg = <0 0x01c0e200 0 0x170>, /* tx0 */ 2040 <0 0x01c0e400 0 0x200>, /* rx0 */ 2041 <0 0x01c0ea00 0 0x1f0>, /* pcs */ 2042 <0 0x01c0e600 0 0x170>, /* tx1 */ 2043 <0 0x01c0e800 0 0x200>, /* rx1 */ 2044 <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2045 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2046 clock-names = "pipe0"; 2047 2048 #phy-cells = <0>; 2049 2050 #clock-cells = <0>; 2051 clock-output-names = "pcie_1_pipe_clk"; 2052 }; 2053 }; 2054 2055 pcie2: pci@1c10000 { 2056 compatible = "qcom,pcie-sm8250"; 2057 reg = <0 0x01c10000 0 0x3000>, 2058 <0 0x64000000 0 0xf1d>, 2059 <0 0x64000f20 0 0xa8>, 2060 <0 0x64001000 0 0x1000>, 2061 <0 0x64100000 0 0x100000>, 2062 <0 0x01c13000 0 0x1000>; 2063 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2064 device_type = "pci"; 2065 linux,pci-domain = <2>; 2066 bus-range = <0x00 0xff>; 2067 num-lanes = <2>; 2068 2069 #address-cells = <3>; 2070 #size-cells = <2>; 2071 2072 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>, 2073 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 2074 2075 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2076 interrupt-names = "msi"; 2077 #interrupt-cells = <1>; 2078 interrupt-map-mask = <0 0 0 0x7>; 2079 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2080 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2081 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2082 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2083 2084 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2085 <&gcc GCC_PCIE_2_AUX_CLK>, 2086 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2087 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2088 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2089 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2090 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2091 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2092 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2093 clock-names = "pipe", 2094 "aux", 2095 "cfg", 2096 "bus_master", 2097 "bus_slave", 2098 "slave_q2a", 2099 "ref", 2100 "tbu", 2101 "ddrss_sf_tbu"; 2102 2103 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2104 assigned-clock-rates = <19200000>; 2105 2106 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2107 <0x100 &apps_smmu 0x1d01 0x1>; 2108 2109 resets = <&gcc GCC_PCIE_2_BCR>; 2110 reset-names = "pci"; 2111 2112 power-domains = <&gcc PCIE_2_GDSC>; 2113 2114 phys = <&pcie2_lane>; 2115 phy-names = "pciephy"; 2116 2117 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; 2118 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 2119 2120 pinctrl-names = "default"; 2121 pinctrl-0 = <&pcie2_default_state>; 2122 2123 status = "disabled"; 2124 }; 2125 2126 pcie2_phy: phy@1c16000 { 2127 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 2128 reg = <0 0x01c16000 0 0x1c0>; 2129 #address-cells = <2>; 2130 #size-cells = <2>; 2131 ranges; 2132 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2133 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2134 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2135 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2136 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2137 2138 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2139 reset-names = "phy"; 2140 2141 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2142 assigned-clock-rates = <100000000>; 2143 2144 status = "disabled"; 2145 2146 pcie2_lane: phy@1c16200 { 2147 reg = <0 0x01c16200 0 0x170>, /* tx0 */ 2148 <0 0x01c16400 0 0x200>, /* rx0 */ 2149 <0 0x01c16a00 0 0x1f0>, /* pcs */ 2150 <0 0x01c16600 0 0x170>, /* tx1 */ 2151 <0 0x01c16800 0 0x200>, /* rx1 */ 2152 <0 0x01c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2153 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 2154 clock-names = "pipe0"; 2155 2156 #phy-cells = <0>; 2157 2158 #clock-cells = <0>; 2159 clock-output-names = "pcie_2_pipe_clk"; 2160 }; 2161 }; 2162 2163 ufs_mem_hc: ufshc@1d84000 { 2164 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 2165 "jedec,ufs-2.0"; 2166 reg = <0 0x01d84000 0 0x3000>; 2167 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2168 phys = <&ufs_mem_phy_lanes>; 2169 phy-names = "ufsphy"; 2170 lanes-per-direction = <2>; 2171 #reset-cells = <1>; 2172 resets = <&gcc GCC_UFS_PHY_BCR>; 2173 reset-names = "rst"; 2174 2175 power-domains = <&gcc UFS_PHY_GDSC>; 2176 2177 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 2178 2179 clock-names = 2180 "core_clk", 2181 "bus_aggr_clk", 2182 "iface_clk", 2183 "core_clk_unipro", 2184 "ref_clk", 2185 "tx_lane0_sync_clk", 2186 "rx_lane0_sync_clk", 2187 "rx_lane1_sync_clk"; 2188 clocks = 2189 <&gcc GCC_UFS_PHY_AXI_CLK>, 2190 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2191 <&gcc GCC_UFS_PHY_AHB_CLK>, 2192 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2193 <&rpmhcc RPMH_CXO_CLK>, 2194 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2195 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2196 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2197 freq-table-hz = 2198 <37500000 300000000>, 2199 <0 0>, 2200 <0 0>, 2201 <37500000 300000000>, 2202 <0 0>, 2203 <0 0>, 2204 <0 0>, 2205 <0 0>; 2206 2207 status = "disabled"; 2208 }; 2209 2210 ufs_mem_phy: phy@1d87000 { 2211 compatible = "qcom,sm8250-qmp-ufs-phy"; 2212 reg = <0 0x01d87000 0 0x1c0>; 2213 #address-cells = <2>; 2214 #size-cells = <2>; 2215 ranges; 2216 clock-names = "ref", 2217 "ref_aux"; 2218 clocks = <&rpmhcc RPMH_CXO_CLK>, 2219 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2220 2221 resets = <&ufs_mem_hc 0>; 2222 reset-names = "ufsphy"; 2223 status = "disabled"; 2224 2225 ufs_mem_phy_lanes: phy@1d87400 { 2226 reg = <0 0x01d87400 0 0x16c>, 2227 <0 0x01d87600 0 0x200>, 2228 <0 0x01d87c00 0 0x200>, 2229 <0 0x01d87800 0 0x16c>, 2230 <0 0x01d87a00 0 0x200>; 2231 #phy-cells = <0>; 2232 }; 2233 }; 2234 2235 tcsr_mutex: hwlock@1f40000 { 2236 compatible = "qcom,tcsr-mutex"; 2237 reg = <0x0 0x01f40000 0x0 0x40000>; 2238 #hwlock-cells = <1>; 2239 }; 2240 2241 wsamacro: codec@3240000 { 2242 compatible = "qcom,sm8250-lpass-wsa-macro"; 2243 reg = <0 0x03240000 0 0x1000>; 2244 clocks = <&audiocc LPASS_CDC_WSA_MCLK>, 2245 <&audiocc LPASS_CDC_WSA_NPL>, 2246 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2247 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2248 <&aoncc LPASS_CDC_VA_MCLK>, 2249 <&vamacro>; 2250 2251 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 2252 2253 #clock-cells = <0>; 2254 clock-output-names = "mclk"; 2255 #sound-dai-cells = <1>; 2256 2257 pinctrl-names = "default"; 2258 pinctrl-0 = <&wsa_swr_active>; 2259 2260 status = "disabled"; 2261 }; 2262 2263 swr0: soundwire-controller@3250000 { 2264 reg = <0 0x03250000 0 0x2000>; 2265 compatible = "qcom,soundwire-v1.5.1"; 2266 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 2267 clocks = <&wsamacro>; 2268 clock-names = "iface"; 2269 2270 qcom,din-ports = <2>; 2271 qcom,dout-ports = <6>; 2272 2273 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2274 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2275 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2276 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 2277 2278 #sound-dai-cells = <1>; 2279 #address-cells = <2>; 2280 #size-cells = <0>; 2281 2282 status = "disabled"; 2283 }; 2284 2285 audiocc: clock-controller@3300000 { 2286 compatible = "qcom,sm8250-lpass-audiocc"; 2287 reg = <0 0x03300000 0 0x30000>; 2288 #clock-cells = <1>; 2289 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2290 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2291 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2292 clock-names = "core", "audio", "bus"; 2293 }; 2294 2295 vamacro: codec@3370000 { 2296 compatible = "qcom,sm8250-lpass-va-macro"; 2297 reg = <0 0x03370000 0 0x1000>; 2298 clocks = <&aoncc LPASS_CDC_VA_MCLK>, 2299 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2300 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2301 2302 clock-names = "mclk", "macro", "dcodec"; 2303 2304 #clock-cells = <0>; 2305 clock-output-names = "fsgen"; 2306 #sound-dai-cells = <1>; 2307 }; 2308 2309 rxmacro: rxmacro@3200000 { 2310 pinctrl-names = "default"; 2311 pinctrl-0 = <&rx_swr_active>; 2312 compatible = "qcom,sm8250-lpass-rx-macro"; 2313 reg = <0 0x03200000 0 0x1000>; 2314 status = "disabled"; 2315 2316 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2317 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2318 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2319 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2320 <&vamacro>; 2321 2322 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2323 2324 #clock-cells = <0>; 2325 clock-output-names = "mclk"; 2326 #sound-dai-cells = <1>; 2327 }; 2328 2329 swr1: soundwire-controller@3210000 { 2330 reg = <0 0x03210000 0 0x2000>; 2331 compatible = "qcom,soundwire-v1.5.1"; 2332 status = "disabled"; 2333 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2334 clocks = <&rxmacro>; 2335 clock-names = "iface"; 2336 label = "RX"; 2337 qcom,din-ports = <0>; 2338 qcom,dout-ports = <5>; 2339 2340 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2341 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2342 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2343 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2344 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2345 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2346 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2347 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2348 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2349 2350 #sound-dai-cells = <1>; 2351 #address-cells = <2>; 2352 #size-cells = <0>; 2353 }; 2354 2355 txmacro: txmacro@3220000 { 2356 pinctrl-names = "default"; 2357 pinctrl-0 = <&tx_swr_active>; 2358 compatible = "qcom,sm8250-lpass-tx-macro"; 2359 reg = <0 0x03220000 0 0x1000>; 2360 status = "disabled"; 2361 2362 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2363 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2364 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2365 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2366 <&vamacro>; 2367 2368 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2369 2370 #clock-cells = <0>; 2371 clock-output-names = "mclk"; 2372 #sound-dai-cells = <1>; 2373 }; 2374 2375 /* tx macro */ 2376 swr2: soundwire-controller@3230000 { 2377 reg = <0 0x03230000 0 0x2000>; 2378 compatible = "qcom,soundwire-v1.5.1"; 2379 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 2380 interrupt-names = "core"; 2381 status = "disabled"; 2382 2383 clocks = <&txmacro>; 2384 clock-names = "iface"; 2385 label = "TX"; 2386 2387 qcom,din-ports = <5>; 2388 qcom,dout-ports = <0>; 2389 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>; 2390 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>; 2391 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>; 2392 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2393 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2394 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2395 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2396 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2397 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>; 2398 #sound-dai-cells = <1>; 2399 #address-cells = <2>; 2400 #size-cells = <0>; 2401 }; 2402 2403 aoncc: clock-controller@3380000 { 2404 compatible = "qcom,sm8250-lpass-aoncc"; 2405 reg = <0 0x03380000 0 0x40000>; 2406 #clock-cells = <1>; 2407 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2408 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2409 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2410 clock-names = "core", "audio", "bus"; 2411 }; 2412 2413 lpass_tlmm: pinctrl@33c0000 { 2414 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 2415 reg = <0 0x033c0000 0x0 0x20000>, 2416 <0 0x03550000 0x0 0x10000>; 2417 gpio-controller; 2418 #gpio-cells = <2>; 2419 gpio-ranges = <&lpass_tlmm 0 0 14>; 2420 2421 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2422 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2423 clock-names = "core", "audio"; 2424 2425 wsa_swr_active: wsa-swr-active-state { 2426 clk-pins { 2427 pins = "gpio10"; 2428 function = "wsa_swr_clk"; 2429 drive-strength = <2>; 2430 slew-rate = <1>; 2431 bias-disable; 2432 }; 2433 2434 data-pins { 2435 pins = "gpio11"; 2436 function = "wsa_swr_data"; 2437 drive-strength = <2>; 2438 slew-rate = <1>; 2439 bias-bus-hold; 2440 }; 2441 }; 2442 2443 wsa_swr_sleep: wsa-swr-sleep-state { 2444 clk-pins { 2445 pins = "gpio10"; 2446 function = "wsa_swr_clk"; 2447 drive-strength = <2>; 2448 bias-pull-down; 2449 }; 2450 2451 data-pins { 2452 pins = "gpio11"; 2453 function = "wsa_swr_data"; 2454 drive-strength = <2>; 2455 bias-pull-down; 2456 }; 2457 }; 2458 2459 dmic01_active: dmic01-active-state { 2460 clk-pins { 2461 pins = "gpio6"; 2462 function = "dmic1_clk"; 2463 drive-strength = <8>; 2464 output-high; 2465 }; 2466 data-pins { 2467 pins = "gpio7"; 2468 function = "dmic1_data"; 2469 drive-strength = <8>; 2470 }; 2471 }; 2472 2473 dmic01_sleep: dmic01-sleep-state { 2474 clk-pins { 2475 pins = "gpio6"; 2476 function = "dmic1_clk"; 2477 drive-strength = <2>; 2478 bias-disable; 2479 output-low; 2480 }; 2481 2482 data-pins { 2483 pins = "gpio7"; 2484 function = "dmic1_data"; 2485 drive-strength = <2>; 2486 bias-pull-down; 2487 }; 2488 }; 2489 2490 rx_swr_active: rx-swr-active-state { 2491 clk-pins { 2492 pins = "gpio3"; 2493 function = "swr_rx_clk"; 2494 drive-strength = <2>; 2495 slew-rate = <1>; 2496 bias-disable; 2497 }; 2498 2499 data-pins { 2500 pins = "gpio4", "gpio5"; 2501 function = "swr_rx_data"; 2502 drive-strength = <2>; 2503 slew-rate = <1>; 2504 bias-bus-hold; 2505 }; 2506 }; 2507 2508 tx_swr_active: tx-swr-active-state { 2509 clk-pins { 2510 pins = "gpio0"; 2511 function = "swr_tx_clk"; 2512 drive-strength = <2>; 2513 slew-rate = <1>; 2514 bias-disable; 2515 }; 2516 2517 data-pins { 2518 pins = "gpio1", "gpio2"; 2519 function = "swr_tx_data"; 2520 drive-strength = <2>; 2521 slew-rate = <1>; 2522 bias-bus-hold; 2523 }; 2524 }; 2525 2526 tx_swr_sleep: tx-swr-sleep-state { 2527 clk-pins { 2528 pins = "gpio0"; 2529 function = "swr_tx_clk"; 2530 drive-strength = <2>; 2531 bias-pull-down; 2532 }; 2533 2534 data1-pins { 2535 pins = "gpio1"; 2536 function = "swr_tx_data"; 2537 drive-strength = <2>; 2538 bias-bus-hold; 2539 }; 2540 2541 data2-pins { 2542 pins = "gpio2"; 2543 function = "swr_tx_data"; 2544 drive-strength = <2>; 2545 bias-pull-down; 2546 }; 2547 }; 2548 }; 2549 2550 gpu: gpu@3d00000 { 2551 compatible = "qcom,adreno-650.2", 2552 "qcom,adreno"; 2553 2554 reg = <0 0x03d00000 0 0x40000>; 2555 reg-names = "kgsl_3d0_reg_memory"; 2556 2557 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2558 2559 iommus = <&adreno_smmu 0 0x401>; 2560 2561 operating-points-v2 = <&gpu_opp_table>; 2562 2563 qcom,gmu = <&gmu>; 2564 2565 nvmem-cells = <&gpu_speed_bin>; 2566 nvmem-cell-names = "speed_bin"; 2567 2568 status = "disabled"; 2569 2570 zap-shader { 2571 memory-region = <&gpu_mem>; 2572 }; 2573 2574 gpu_opp_table: opp-table { 2575 compatible = "operating-points-v2"; 2576 2577 opp-670000000 { 2578 opp-hz = /bits/ 64 <670000000>; 2579 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2580 opp-supported-hw = <0xa>; 2581 }; 2582 2583 opp-587000000 { 2584 opp-hz = /bits/ 64 <587000000>; 2585 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2586 opp-supported-hw = <0xb>; 2587 }; 2588 2589 opp-525000000 { 2590 opp-hz = /bits/ 64 <525000000>; 2591 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2592 opp-supported-hw = <0xf>; 2593 }; 2594 2595 opp-490000000 { 2596 opp-hz = /bits/ 64 <490000000>; 2597 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2598 opp-supported-hw = <0xf>; 2599 }; 2600 2601 opp-441600000 { 2602 opp-hz = /bits/ 64 <441600000>; 2603 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2604 opp-supported-hw = <0xf>; 2605 }; 2606 2607 opp-400000000 { 2608 opp-hz = /bits/ 64 <400000000>; 2609 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2610 opp-supported-hw = <0xf>; 2611 }; 2612 2613 opp-305000000 { 2614 opp-hz = /bits/ 64 <305000000>; 2615 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2616 opp-supported-hw = <0xf>; 2617 }; 2618 }; 2619 }; 2620 2621 gmu: gmu@3d6a000 { 2622 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2623 2624 reg = <0 0x03d6a000 0 0x30000>, 2625 <0 0x3de0000 0 0x10000>, 2626 <0 0xb290000 0 0x10000>, 2627 <0 0xb490000 0 0x10000>; 2628 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 2629 2630 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2631 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2632 interrupt-names = "hfi", "gmu"; 2633 2634 clocks = <&gpucc GPU_CC_AHB_CLK>, 2635 <&gpucc GPU_CC_CX_GMU_CLK>, 2636 <&gpucc GPU_CC_CXO_CLK>, 2637 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2638 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2639 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2640 2641 power-domains = <&gpucc GPU_CX_GDSC>, 2642 <&gpucc GPU_GX_GDSC>; 2643 power-domain-names = "cx", "gx"; 2644 2645 iommus = <&adreno_smmu 5 0x400>; 2646 2647 operating-points-v2 = <&gmu_opp_table>; 2648 2649 status = "disabled"; 2650 2651 gmu_opp_table: opp-table { 2652 compatible = "operating-points-v2"; 2653 2654 opp-200000000 { 2655 opp-hz = /bits/ 64 <200000000>; 2656 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2657 }; 2658 }; 2659 }; 2660 2661 gpucc: clock-controller@3d90000 { 2662 compatible = "qcom,sm8250-gpucc"; 2663 reg = <0 0x03d90000 0 0x9000>; 2664 clocks = <&rpmhcc RPMH_CXO_CLK>, 2665 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2666 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2667 clock-names = "bi_tcxo", 2668 "gcc_gpu_gpll0_clk_src", 2669 "gcc_gpu_gpll0_div_clk_src"; 2670 #clock-cells = <1>; 2671 #reset-cells = <1>; 2672 #power-domain-cells = <1>; 2673 }; 2674 2675 adreno_smmu: iommu@3da0000 { 2676 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", 2677 "qcom,smmu-500", "arm,mmu-500"; 2678 reg = <0 0x03da0000 0 0x10000>; 2679 #iommu-cells = <2>; 2680 #global-interrupts = <2>; 2681 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2682 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2683 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2684 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2685 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2686 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2687 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2688 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2689 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2690 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 2691 clocks = <&gpucc GPU_CC_AHB_CLK>, 2692 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2693 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2694 clock-names = "ahb", "bus", "iface"; 2695 2696 power-domains = <&gpucc GPU_CX_GDSC>; 2697 }; 2698 2699 slpi: remoteproc@5c00000 { 2700 compatible = "qcom,sm8250-slpi-pas"; 2701 reg = <0 0x05c00000 0 0x4000>; 2702 2703 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2704 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2705 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2706 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2707 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2708 interrupt-names = "wdog", "fatal", "ready", 2709 "handover", "stop-ack"; 2710 2711 clocks = <&rpmhcc RPMH_CXO_CLK>; 2712 clock-names = "xo"; 2713 2714 power-domains = <&rpmhpd SM8250_LCX>, 2715 <&rpmhpd SM8250_LMX>; 2716 power-domain-names = "lcx", "lmx"; 2717 2718 memory-region = <&slpi_mem>; 2719 2720 qcom,qmp = <&aoss_qmp>; 2721 2722 qcom,smem-states = <&smp2p_slpi_out 0>; 2723 qcom,smem-state-names = "stop"; 2724 2725 status = "disabled"; 2726 2727 glink-edge { 2728 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2729 IPCC_MPROC_SIGNAL_GLINK_QMP 2730 IRQ_TYPE_EDGE_RISING>; 2731 mboxes = <&ipcc IPCC_CLIENT_SLPI 2732 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2733 2734 label = "slpi"; 2735 qcom,remote-pid = <3>; 2736 2737 fastrpc { 2738 compatible = "qcom,fastrpc"; 2739 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2740 label = "sdsp"; 2741 qcom,non-secure-domain; 2742 #address-cells = <1>; 2743 #size-cells = <0>; 2744 2745 compute-cb@1 { 2746 compatible = "qcom,fastrpc-compute-cb"; 2747 reg = <1>; 2748 iommus = <&apps_smmu 0x0541 0x0>; 2749 }; 2750 2751 compute-cb@2 { 2752 compatible = "qcom,fastrpc-compute-cb"; 2753 reg = <2>; 2754 iommus = <&apps_smmu 0x0542 0x0>; 2755 }; 2756 2757 compute-cb@3 { 2758 compatible = "qcom,fastrpc-compute-cb"; 2759 reg = <3>; 2760 iommus = <&apps_smmu 0x0543 0x0>; 2761 /* note: shared-cb = <4> in downstream */ 2762 }; 2763 }; 2764 }; 2765 }; 2766 2767 stm@6002000 { 2768 compatible = "arm,coresight-stm", "arm,primecell"; 2769 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>; 2770 reg-names = "stm-base", "stm-stimulus-base"; 2771 2772 clocks = <&aoss_qmp>; 2773 clock-names = "apb_pclk"; 2774 2775 out-ports { 2776 port { 2777 stm_out: endpoint { 2778 remote-endpoint = <&funnel0_in7>; 2779 }; 2780 }; 2781 }; 2782 }; 2783 2784 tpda@6004000 { 2785 compatible = "qcom,coresight-tpda", "arm,primecell"; 2786 reg = <0 0x06004000 0 0x1000>; 2787 2788 clocks = <&aoss_qmp>; 2789 clock-names = "apb_pclk"; 2790 2791 out-ports { 2792 #address-cells = <1>; 2793 #size-cells = <0>; 2794 2795 port@0 { 2796 reg = <0>; 2797 tpda_out_funnel_qatb: endpoint { 2798 remote-endpoint = <&funnel_qatb_in_tpda>; 2799 }; 2800 }; 2801 }; 2802 2803 in-ports { 2804 #address-cells = <1>; 2805 #size-cells = <0>; 2806 2807 port@9 { 2808 reg = <9>; 2809 tpda_9_in_tpdm_mm: endpoint { 2810 remote-endpoint = <&tpdm_mm_out_tpda9>; 2811 }; 2812 }; 2813 2814 port@17 { 2815 reg = <23>; 2816 tpda_23_in_tpdm_prng: endpoint { 2817 remote-endpoint = <&tpdm_prng_out_tpda_23>; 2818 }; 2819 }; 2820 }; 2821 }; 2822 2823 funnel@6005000 { 2824 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2825 reg = <0 0x06005000 0 0x1000>; 2826 2827 clocks = <&aoss_qmp>; 2828 clock-names = "apb_pclk"; 2829 2830 out-ports { 2831 port { 2832 funnel_qatb_out_funnel_in0: endpoint { 2833 remote-endpoint = <&funnel_in0_in_funnel_qatb>; 2834 }; 2835 }; 2836 }; 2837 2838 in-ports { 2839 #address-cells = <1>; 2840 #size-cells = <0>; 2841 2842 port@0 { 2843 reg = <0>; 2844 funnel_qatb_in_tpda: endpoint { 2845 remote-endpoint = <&tpda_out_funnel_qatb>; 2846 }; 2847 }; 2848 }; 2849 }; 2850 2851 funnel@6041000 { 2852 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2853 reg = <0 0x06041000 0 0x1000>; 2854 2855 clocks = <&aoss_qmp>; 2856 clock-names = "apb_pclk"; 2857 2858 out-ports { 2859 port { 2860 funnel_in0_out_funnel_merg: endpoint { 2861 remote-endpoint = <&funnel_merg_in_funnel_in0>; 2862 }; 2863 }; 2864 }; 2865 2866 in-ports { 2867 #address-cells = <1>; 2868 #size-cells = <0>; 2869 2870 port@6 { 2871 reg = <6>; 2872 funnel_in0_in_funnel_qatb: endpoint { 2873 remote-endpoint = <&funnel_qatb_out_funnel_in0>; 2874 }; 2875 }; 2876 2877 port@7 { 2878 reg = <7>; 2879 funnel0_in7: endpoint { 2880 remote-endpoint = <&stm_out>; 2881 }; 2882 }; 2883 }; 2884 }; 2885 2886 funnel@6042000 { 2887 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2888 reg = <0 0x06042000 0 0x1000>; 2889 2890 clocks = <&aoss_qmp>; 2891 clock-names = "apb_pclk"; 2892 2893 out-ports { 2894 port { 2895 funnel_in1_out_funnel_merg: endpoint { 2896 remote-endpoint = <&funnel_merg_in_funnel_in1>; 2897 }; 2898 }; 2899 }; 2900 2901 in-ports { 2902 #address-cells = <1>; 2903 #size-cells = <0>; 2904 2905 port@4 { 2906 reg = <4>; 2907 funnel_in1_in_funnel_apss_merg: endpoint { 2908 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>; 2909 }; 2910 }; 2911 }; 2912 }; 2913 2914 funnel@6045000 { 2915 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2916 reg = <0 0x06045000 0 0x1000>; 2917 2918 clocks = <&aoss_qmp>; 2919 clock-names = "apb_pclk"; 2920 2921 out-ports { 2922 port { 2923 funnel_merg_out_funnel_swao: endpoint { 2924 remote-endpoint = <&funnel_swao_in_funnel_merg>; 2925 }; 2926 }; 2927 }; 2928 2929 in-ports { 2930 #address-cells = <1>; 2931 #size-cells = <0>; 2932 2933 port@0 { 2934 reg = <0>; 2935 funnel_merg_in_funnel_in0: endpoint { 2936 remote-endpoint = <&funnel_in0_out_funnel_merg>; 2937 }; 2938 }; 2939 2940 port@1 { 2941 reg = <1>; 2942 funnel_merg_in_funnel_in1: endpoint { 2943 remote-endpoint = <&funnel_in1_out_funnel_merg>; 2944 }; 2945 }; 2946 }; 2947 }; 2948 2949 replicator@6046000 { 2950 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2951 reg = <0 0x06046000 0 0x1000>; 2952 2953 clocks = <&aoss_qmp>; 2954 clock-names = "apb_pclk"; 2955 2956 out-ports { 2957 port { 2958 replicator_out: endpoint { 2959 remote-endpoint = <&etr_in>; 2960 }; 2961 }; 2962 }; 2963 2964 in-ports { 2965 port { 2966 replicator_cx_in_swao_out: endpoint { 2967 remote-endpoint = <&replicator_swao_out_cx_in>; 2968 }; 2969 }; 2970 }; 2971 }; 2972 2973 etr@6048000 { 2974 compatible = "arm,coresight-tmc", "arm,primecell"; 2975 reg = <0 0x06048000 0 0x1000>; 2976 2977 clocks = <&aoss_qmp>; 2978 clock-names = "apb_pclk"; 2979 arm,scatter-gather; 2980 2981 in-ports { 2982 port { 2983 etr_in: endpoint { 2984 remote-endpoint = <&replicator_out>; 2985 }; 2986 }; 2987 }; 2988 }; 2989 2990 tpdm@684c000 { 2991 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2992 reg = <0 0x0684c000 0 0x1000>; 2993 2994 clocks = <&aoss_qmp>; 2995 clock-names = "apb_pclk"; 2996 2997 out-ports { 2998 port { 2999 tpdm_prng_out_tpda_23: endpoint { 3000 remote-endpoint = <&tpda_23_in_tpdm_prng>; 3001 }; 3002 }; 3003 }; 3004 }; 3005 3006 funnel@6b04000 { 3007 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3008 arm,primecell-periphid = <0x000bb908>; 3009 3010 reg = <0 0x06b04000 0 0x1000>; 3011 3012 clocks = <&aoss_qmp>; 3013 clock-names = "apb_pclk"; 3014 3015 out-ports { 3016 port { 3017 funnel_swao_out_etf: endpoint { 3018 remote-endpoint = <&etf_in_funnel_swao_out>; 3019 }; 3020 }; 3021 }; 3022 3023 in-ports { 3024 #address-cells = <1>; 3025 #size-cells = <0>; 3026 3027 port@7 { 3028 reg = <7>; 3029 funnel_swao_in_funnel_merg: endpoint { 3030 remote-endpoint= <&funnel_merg_out_funnel_swao>; 3031 }; 3032 }; 3033 }; 3034 }; 3035 3036 etf@6b05000 { 3037 compatible = "arm,coresight-tmc", "arm,primecell"; 3038 reg = <0 0x06b05000 0 0x1000>; 3039 3040 clocks = <&aoss_qmp>; 3041 clock-names = "apb_pclk"; 3042 3043 out-ports { 3044 port { 3045 etf_out: endpoint { 3046 remote-endpoint = <&replicator_in>; 3047 }; 3048 }; 3049 }; 3050 3051 in-ports { 3052 #address-cells = <1>; 3053 #size-cells = <0>; 3054 3055 port@0 { 3056 reg = <0>; 3057 etf_in_funnel_swao_out: endpoint { 3058 remote-endpoint = <&funnel_swao_out_etf>; 3059 }; 3060 }; 3061 }; 3062 }; 3063 3064 replicator@6b06000 { 3065 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3066 reg = <0 0x06b06000 0 0x1000>; 3067 3068 clocks = <&aoss_qmp>; 3069 clock-names = "apb_pclk"; 3070 3071 out-ports { 3072 port { 3073 replicator_swao_out_cx_in: endpoint { 3074 remote-endpoint = <&replicator_cx_in_swao_out>; 3075 }; 3076 }; 3077 }; 3078 3079 in-ports { 3080 port { 3081 replicator_in: endpoint { 3082 remote-endpoint = <&etf_out>; 3083 }; 3084 }; 3085 }; 3086 }; 3087 3088 tpdm@6c08000 { 3089 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3090 reg = <0 0x06c08000 0 0x1000>; 3091 3092 clocks = <&aoss_qmp>; 3093 clock-names = "apb_pclk"; 3094 3095 out-ports { 3096 port { 3097 tpdm_mm_out_funnel_dl_mm: endpoint { 3098 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>; 3099 }; 3100 }; 3101 }; 3102 }; 3103 3104 funnel@6c0b000 { 3105 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3106 reg = <0 0x06c0b000 0 0x1000>; 3107 3108 clocks = <&aoss_qmp>; 3109 clock-names = "apb_pclk"; 3110 3111 out-ports { 3112 port { 3113 funnel_dl_mm_out_funnel_dl_center: endpoint { 3114 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>; 3115 }; 3116 }; 3117 }; 3118 3119 in-ports { 3120 #address-cells = <1>; 3121 #size-cells = <0>; 3122 3123 port@3 { 3124 reg = <3>; 3125 funnel_dl_mm_in_tpdm_mm: endpoint { 3126 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>; 3127 }; 3128 }; 3129 }; 3130 }; 3131 3132 funnel@6c2d000 { 3133 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3134 reg = <0 0x06c2d000 0 0x1000>; 3135 3136 clocks = <&aoss_qmp>; 3137 clock-names = "apb_pclk"; 3138 3139 out-ports { 3140 #address-cells = <1>; 3141 #size-cells = <0>; 3142 port { 3143 tpdm_mm_out_tpda9: endpoint { 3144 remote-endpoint = <&tpda_9_in_tpdm_mm>; 3145 }; 3146 }; 3147 }; 3148 3149 in-ports { 3150 #address-cells = <1>; 3151 #size-cells = <0>; 3152 3153 port@2 { 3154 reg = <2>; 3155 funnel_dl_center_in_funnel_dl_mm: endpoint { 3156 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>; 3157 }; 3158 }; 3159 }; 3160 }; 3161 3162 etm@7040000 { 3163 compatible = "arm,coresight-etm4x", "arm,primecell"; 3164 reg = <0 0x07040000 0 0x1000>; 3165 3166 cpu = <&CPU0>; 3167 3168 clocks = <&aoss_qmp>; 3169 clock-names = "apb_pclk"; 3170 arm,coresight-loses-context-with-cpu; 3171 3172 out-ports { 3173 port { 3174 etm0_out: endpoint { 3175 remote-endpoint = <&apss_funnel_in0>; 3176 }; 3177 }; 3178 }; 3179 }; 3180 3181 etm@7140000 { 3182 compatible = "arm,coresight-etm4x", "arm,primecell"; 3183 reg = <0 0x07140000 0 0x1000>; 3184 3185 cpu = <&CPU1>; 3186 3187 clocks = <&aoss_qmp>; 3188 clock-names = "apb_pclk"; 3189 arm,coresight-loses-context-with-cpu; 3190 3191 out-ports { 3192 port { 3193 etm1_out: endpoint { 3194 remote-endpoint = <&apss_funnel_in1>; 3195 }; 3196 }; 3197 }; 3198 }; 3199 3200 etm@7240000 { 3201 compatible = "arm,coresight-etm4x", "arm,primecell"; 3202 reg = <0 0x07240000 0 0x1000>; 3203 3204 cpu = <&CPU2>; 3205 3206 clocks = <&aoss_qmp>; 3207 clock-names = "apb_pclk"; 3208 arm,coresight-loses-context-with-cpu; 3209 3210 out-ports { 3211 port { 3212 etm2_out: endpoint { 3213 remote-endpoint = <&apss_funnel_in2>; 3214 }; 3215 }; 3216 }; 3217 }; 3218 3219 etm@7340000 { 3220 compatible = "arm,coresight-etm4x", "arm,primecell"; 3221 reg = <0 0x07340000 0 0x1000>; 3222 3223 cpu = <&CPU3>; 3224 3225 clocks = <&aoss_qmp>; 3226 clock-names = "apb_pclk"; 3227 arm,coresight-loses-context-with-cpu; 3228 3229 out-ports { 3230 port { 3231 etm3_out: endpoint { 3232 remote-endpoint = <&apss_funnel_in3>; 3233 }; 3234 }; 3235 }; 3236 }; 3237 3238 etm@7440000 { 3239 compatible = "arm,coresight-etm4x", "arm,primecell"; 3240 reg = <0 0x07440000 0 0x1000>; 3241 3242 cpu = <&CPU4>; 3243 3244 clocks = <&aoss_qmp>; 3245 clock-names = "apb_pclk"; 3246 arm,coresight-loses-context-with-cpu; 3247 3248 out-ports { 3249 port { 3250 etm4_out: endpoint { 3251 remote-endpoint = <&apss_funnel_in4>; 3252 }; 3253 }; 3254 }; 3255 }; 3256 3257 etm@7540000 { 3258 compatible = "arm,coresight-etm4x", "arm,primecell"; 3259 reg = <0 0x07540000 0 0x1000>; 3260 3261 cpu = <&CPU5>; 3262 3263 clocks = <&aoss_qmp>; 3264 clock-names = "apb_pclk"; 3265 arm,coresight-loses-context-with-cpu; 3266 3267 out-ports { 3268 port { 3269 etm5_out: endpoint { 3270 remote-endpoint = <&apss_funnel_in5>; 3271 }; 3272 }; 3273 }; 3274 }; 3275 3276 etm@7640000 { 3277 compatible = "arm,coresight-etm4x", "arm,primecell"; 3278 reg = <0 0x07640000 0 0x1000>; 3279 3280 cpu = <&CPU6>; 3281 3282 clocks = <&aoss_qmp>; 3283 clock-names = "apb_pclk"; 3284 arm,coresight-loses-context-with-cpu; 3285 3286 out-ports { 3287 port { 3288 etm6_out: endpoint { 3289 remote-endpoint = <&apss_funnel_in6>; 3290 }; 3291 }; 3292 }; 3293 }; 3294 3295 etm@7740000 { 3296 compatible = "arm,coresight-etm4x", "arm,primecell"; 3297 reg = <0 0x07740000 0 0x1000>; 3298 3299 cpu = <&CPU7>; 3300 3301 clocks = <&aoss_qmp>; 3302 clock-names = "apb_pclk"; 3303 arm,coresight-loses-context-with-cpu; 3304 3305 out-ports { 3306 port { 3307 etm7_out: endpoint { 3308 remote-endpoint = <&apss_funnel_in7>; 3309 }; 3310 }; 3311 }; 3312 }; 3313 3314 funnel@7800000 { 3315 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3316 reg = <0 0x07800000 0 0x1000>; 3317 3318 clocks = <&aoss_qmp>; 3319 clock-names = "apb_pclk"; 3320 3321 out-ports { 3322 port { 3323 funnel_apss_out_funnel_apss_merg: endpoint { 3324 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>; 3325 }; 3326 }; 3327 }; 3328 3329 in-ports { 3330 #address-cells = <1>; 3331 #size-cells = <0>; 3332 3333 port@0 { 3334 reg = <0>; 3335 apss_funnel_in0: endpoint { 3336 remote-endpoint = <&etm0_out>; 3337 }; 3338 }; 3339 3340 port@1 { 3341 reg = <1>; 3342 apss_funnel_in1: endpoint { 3343 remote-endpoint = <&etm1_out>; 3344 }; 3345 }; 3346 3347 port@2 { 3348 reg = <2>; 3349 apss_funnel_in2: endpoint { 3350 remote-endpoint = <&etm2_out>; 3351 }; 3352 }; 3353 3354 port@3 { 3355 reg = <3>; 3356 apss_funnel_in3: endpoint { 3357 remote-endpoint = <&etm3_out>; 3358 }; 3359 }; 3360 3361 port@4 { 3362 reg = <4>; 3363 apss_funnel_in4: endpoint { 3364 remote-endpoint = <&etm4_out>; 3365 }; 3366 }; 3367 3368 port@5 { 3369 reg = <5>; 3370 apss_funnel_in5: endpoint { 3371 remote-endpoint = <&etm5_out>; 3372 }; 3373 }; 3374 3375 port@6 { 3376 reg = <6>; 3377 apss_funnel_in6: endpoint { 3378 remote-endpoint = <&etm6_out>; 3379 }; 3380 }; 3381 3382 port@7 { 3383 reg = <7>; 3384 apss_funnel_in7: endpoint { 3385 remote-endpoint = <&etm7_out>; 3386 }; 3387 }; 3388 }; 3389 }; 3390 3391 funnel@7810000 { 3392 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3393 reg = <0 0x07810000 0 0x1000>; 3394 3395 clocks = <&aoss_qmp>; 3396 clock-names = "apb_pclk"; 3397 3398 out-ports { 3399 port { 3400 funnel_apss_merg_out_funnel_in1: endpoint { 3401 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>; 3402 }; 3403 }; 3404 }; 3405 3406 in-ports { 3407 #address-cells = <1>; 3408 #size-cells = <0>; 3409 3410 port@0 { 3411 reg = <0>; 3412 funnel_apss_merg_in_funnel_apss: endpoint { 3413 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>; 3414 }; 3415 }; 3416 }; 3417 }; 3418 3419 cdsp: remoteproc@8300000 { 3420 compatible = "qcom,sm8250-cdsp-pas"; 3421 reg = <0 0x08300000 0 0x10000>; 3422 3423 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 3424 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3425 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3426 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3427 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3428 interrupt-names = "wdog", "fatal", "ready", 3429 "handover", "stop-ack"; 3430 3431 clocks = <&rpmhcc RPMH_CXO_CLK>; 3432 clock-names = "xo"; 3433 3434 power-domains = <&rpmhpd SM8250_CX>; 3435 3436 memory-region = <&cdsp_mem>; 3437 3438 qcom,qmp = <&aoss_qmp>; 3439 3440 qcom,smem-states = <&smp2p_cdsp_out 0>; 3441 qcom,smem-state-names = "stop"; 3442 3443 status = "disabled"; 3444 3445 glink-edge { 3446 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3447 IPCC_MPROC_SIGNAL_GLINK_QMP 3448 IRQ_TYPE_EDGE_RISING>; 3449 mboxes = <&ipcc IPCC_CLIENT_CDSP 3450 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3451 3452 label = "cdsp"; 3453 qcom,remote-pid = <5>; 3454 3455 fastrpc { 3456 compatible = "qcom,fastrpc"; 3457 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3458 label = "cdsp"; 3459 qcom,non-secure-domain; 3460 #address-cells = <1>; 3461 #size-cells = <0>; 3462 3463 compute-cb@1 { 3464 compatible = "qcom,fastrpc-compute-cb"; 3465 reg = <1>; 3466 iommus = <&apps_smmu 0x1001 0x0460>; 3467 }; 3468 3469 compute-cb@2 { 3470 compatible = "qcom,fastrpc-compute-cb"; 3471 reg = <2>; 3472 iommus = <&apps_smmu 0x1002 0x0460>; 3473 }; 3474 3475 compute-cb@3 { 3476 compatible = "qcom,fastrpc-compute-cb"; 3477 reg = <3>; 3478 iommus = <&apps_smmu 0x1003 0x0460>; 3479 }; 3480 3481 compute-cb@4 { 3482 compatible = "qcom,fastrpc-compute-cb"; 3483 reg = <4>; 3484 iommus = <&apps_smmu 0x1004 0x0460>; 3485 }; 3486 3487 compute-cb@5 { 3488 compatible = "qcom,fastrpc-compute-cb"; 3489 reg = <5>; 3490 iommus = <&apps_smmu 0x1005 0x0460>; 3491 }; 3492 3493 compute-cb@6 { 3494 compatible = "qcom,fastrpc-compute-cb"; 3495 reg = <6>; 3496 iommus = <&apps_smmu 0x1006 0x0460>; 3497 }; 3498 3499 compute-cb@7 { 3500 compatible = "qcom,fastrpc-compute-cb"; 3501 reg = <7>; 3502 iommus = <&apps_smmu 0x1007 0x0460>; 3503 }; 3504 3505 compute-cb@8 { 3506 compatible = "qcom,fastrpc-compute-cb"; 3507 reg = <8>; 3508 iommus = <&apps_smmu 0x1008 0x0460>; 3509 }; 3510 3511 /* note: secure cb9 in downstream */ 3512 }; 3513 }; 3514 }; 3515 3516 usb_1_hsphy: phy@88e3000 { 3517 compatible = "qcom,sm8250-usb-hs-phy", 3518 "qcom,usb-snps-hs-7nm-phy"; 3519 reg = <0 0x088e3000 0 0x400>; 3520 status = "disabled"; 3521 #phy-cells = <0>; 3522 3523 clocks = <&rpmhcc RPMH_CXO_CLK>; 3524 clock-names = "ref"; 3525 3526 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3527 }; 3528 3529 usb_2_hsphy: phy@88e4000 { 3530 compatible = "qcom,sm8250-usb-hs-phy", 3531 "qcom,usb-snps-hs-7nm-phy"; 3532 reg = <0 0x088e4000 0 0x400>; 3533 status = "disabled"; 3534 #phy-cells = <0>; 3535 3536 clocks = <&rpmhcc RPMH_CXO_CLK>; 3537 clock-names = "ref"; 3538 3539 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3540 }; 3541 3542 usb_1_qmpphy: phy@88e9000 { 3543 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 3544 reg = <0 0x088e9000 0 0x200>, 3545 <0 0x088e8000 0 0x40>, 3546 <0 0x088ea000 0 0x200>; 3547 status = "disabled"; 3548 #address-cells = <2>; 3549 #size-cells = <2>; 3550 ranges; 3551 3552 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3553 <&rpmhcc RPMH_CXO_CLK>, 3554 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3555 clock-names = "aux", "ref_clk_src", "com_aux"; 3556 3557 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3558 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3559 reset-names = "phy", "common"; 3560 3561 usb_1_ssphy: usb3-phy@88e9200 { 3562 reg = <0 0x088e9200 0 0x200>, 3563 <0 0x088e9400 0 0x200>, 3564 <0 0x088e9c00 0 0x400>, 3565 <0 0x088e9600 0 0x200>, 3566 <0 0x088e9800 0 0x200>, 3567 <0 0x088e9a00 0 0x100>; 3568 #clock-cells = <0>; 3569 #phy-cells = <0>; 3570 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3571 clock-names = "pipe0"; 3572 clock-output-names = "usb3_phy_pipe_clk_src"; 3573 }; 3574 3575 dp_phy: dp-phy@88ea200 { 3576 reg = <0 0x088ea200 0 0x200>, 3577 <0 0x088ea400 0 0x200>, 3578 <0 0x088eaa00 0 0x200>, 3579 <0 0x088ea600 0 0x200>, 3580 <0 0x088ea800 0 0x200>; 3581 #phy-cells = <0>; 3582 #clock-cells = <1>; 3583 }; 3584 }; 3585 3586 usb_2_qmpphy: phy@88eb000 { 3587 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 3588 reg = <0 0x088eb000 0 0x200>; 3589 status = "disabled"; 3590 #address-cells = <2>; 3591 #size-cells = <2>; 3592 ranges; 3593 3594 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3595 <&rpmhcc RPMH_CXO_CLK>, 3596 <&gcc GCC_USB3_SEC_CLKREF_EN>, 3597 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3598 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3599 3600 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3601 <&gcc GCC_USB3_PHY_SEC_BCR>; 3602 reset-names = "phy", "common"; 3603 3604 usb_2_ssphy: phy@88eb200 { 3605 reg = <0 0x088eb200 0 0x200>, 3606 <0 0x088eb400 0 0x200>, 3607 <0 0x088eb800 0 0x800>; 3608 #clock-cells = <0>; 3609 #phy-cells = <0>; 3610 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3611 clock-names = "pipe0"; 3612 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3613 }; 3614 }; 3615 3616 sdhc_2: mmc@8804000 { 3617 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 3618 reg = <0 0x08804000 0 0x1000>; 3619 3620 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3621 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3622 interrupt-names = "hc_irq", "pwr_irq"; 3623 3624 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3625 <&gcc GCC_SDCC2_APPS_CLK>, 3626 <&rpmhcc RPMH_CXO_CLK>; 3627 clock-names = "iface", "core", "xo"; 3628 iommus = <&apps_smmu 0x4a0 0x0>; 3629 qcom,dll-config = <0x0007642c>; 3630 qcom,ddr-config = <0x80040868>; 3631 power-domains = <&rpmhpd SM8250_CX>; 3632 operating-points-v2 = <&sdhc2_opp_table>; 3633 3634 status = "disabled"; 3635 3636 sdhc2_opp_table: opp-table { 3637 compatible = "operating-points-v2"; 3638 3639 opp-19200000 { 3640 opp-hz = /bits/ 64 <19200000>; 3641 required-opps = <&rpmhpd_opp_min_svs>; 3642 }; 3643 3644 opp-50000000 { 3645 opp-hz = /bits/ 64 <50000000>; 3646 required-opps = <&rpmhpd_opp_low_svs>; 3647 }; 3648 3649 opp-100000000 { 3650 opp-hz = /bits/ 64 <100000000>; 3651 required-opps = <&rpmhpd_opp_svs>; 3652 }; 3653 3654 opp-202000000 { 3655 opp-hz = /bits/ 64 <202000000>; 3656 required-opps = <&rpmhpd_opp_svs_l1>; 3657 }; 3658 }; 3659 }; 3660 3661 dc_noc: interconnect@90c0000 { 3662 compatible = "qcom,sm8250-dc-noc"; 3663 reg = <0 0x090c0000 0 0x4200>; 3664 #interconnect-cells = <1>; 3665 qcom,bcm-voters = <&apps_bcm_voter>; 3666 }; 3667 3668 gem_noc: interconnect@9100000 { 3669 compatible = "qcom,sm8250-gem-noc"; 3670 reg = <0 0x09100000 0 0xb4000>; 3671 #interconnect-cells = <1>; 3672 qcom,bcm-voters = <&apps_bcm_voter>; 3673 }; 3674 3675 npu_noc: interconnect@9990000 { 3676 compatible = "qcom,sm8250-npu-noc"; 3677 reg = <0 0x09990000 0 0x1600>; 3678 #interconnect-cells = <1>; 3679 qcom,bcm-voters = <&apps_bcm_voter>; 3680 }; 3681 3682 usb_1: usb@a6f8800 { 3683 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3684 reg = <0 0x0a6f8800 0 0x400>; 3685 status = "disabled"; 3686 #address-cells = <2>; 3687 #size-cells = <2>; 3688 ranges; 3689 dma-ranges; 3690 3691 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3692 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3693 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3694 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3695 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3696 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3697 clock-names = "cfg_noc", 3698 "core", 3699 "iface", 3700 "sleep", 3701 "mock_utmi", 3702 "xo"; 3703 3704 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3705 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3706 assigned-clock-rates = <19200000>, <200000000>; 3707 3708 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3709 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 3710 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3711 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 3712 interrupt-names = "hs_phy_irq", 3713 "ss_phy_irq", 3714 "dm_hs_phy_irq", 3715 "dp_hs_phy_irq"; 3716 3717 power-domains = <&gcc USB30_PRIM_GDSC>; 3718 3719 resets = <&gcc GCC_USB30_PRIM_BCR>; 3720 3721 usb_1_dwc3: usb@a600000 { 3722 compatible = "snps,dwc3"; 3723 reg = <0 0x0a600000 0 0xcd00>; 3724 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3725 iommus = <&apps_smmu 0x0 0x0>; 3726 snps,dis_u2_susphy_quirk; 3727 snps,dis_enblslpm_quirk; 3728 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3729 phy-names = "usb2-phy", "usb3-phy"; 3730 }; 3731 }; 3732 3733 system-cache-controller@9200000 { 3734 compatible = "qcom,sm8250-llcc"; 3735 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 3736 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 3737 <0 0x09600000 0 0x50000>; 3738 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3739 "llcc3_base", "llcc_broadcast_base"; 3740 }; 3741 3742 usb_2: usb@a8f8800 { 3743 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3744 reg = <0 0x0a8f8800 0 0x400>; 3745 status = "disabled"; 3746 #address-cells = <2>; 3747 #size-cells = <2>; 3748 ranges; 3749 dma-ranges; 3750 3751 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3752 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3753 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3754 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3755 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3756 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3757 clock-names = "cfg_noc", 3758 "core", 3759 "iface", 3760 "sleep", 3761 "mock_utmi", 3762 "xo"; 3763 3764 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3765 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3766 assigned-clock-rates = <19200000>, <200000000>; 3767 3768 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3769 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 3770 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3771 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 3772 interrupt-names = "hs_phy_irq", 3773 "ss_phy_irq", 3774 "dm_hs_phy_irq", 3775 "dp_hs_phy_irq"; 3776 3777 power-domains = <&gcc USB30_SEC_GDSC>; 3778 3779 resets = <&gcc GCC_USB30_SEC_BCR>; 3780 3781 usb_2_dwc3: usb@a800000 { 3782 compatible = "snps,dwc3"; 3783 reg = <0 0x0a800000 0 0xcd00>; 3784 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3785 iommus = <&apps_smmu 0x20 0>; 3786 snps,dis_u2_susphy_quirk; 3787 snps,dis_enblslpm_quirk; 3788 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3789 phy-names = "usb2-phy", "usb3-phy"; 3790 }; 3791 }; 3792 3793 venus: video-codec@aa00000 { 3794 compatible = "qcom,sm8250-venus"; 3795 reg = <0 0x0aa00000 0 0x100000>; 3796 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3797 power-domains = <&videocc MVS0C_GDSC>, 3798 <&videocc MVS0_GDSC>, 3799 <&rpmhpd SM8250_MX>; 3800 power-domain-names = "venus", "vcodec0", "mx"; 3801 operating-points-v2 = <&venus_opp_table>; 3802 3803 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 3804 <&videocc VIDEO_CC_MVS0C_CLK>, 3805 <&videocc VIDEO_CC_MVS0_CLK>; 3806 clock-names = "iface", "core", "vcodec0_core"; 3807 3808 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, 3809 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; 3810 interconnect-names = "cpu-cfg", "video-mem"; 3811 3812 iommus = <&apps_smmu 0x2100 0x0400>; 3813 memory-region = <&video_mem>; 3814 3815 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 3816 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 3817 reset-names = "bus", "core"; 3818 3819 status = "disabled"; 3820 3821 video-decoder { 3822 compatible = "venus-decoder"; 3823 }; 3824 3825 video-encoder { 3826 compatible = "venus-encoder"; 3827 }; 3828 3829 venus_opp_table: opp-table { 3830 compatible = "operating-points-v2"; 3831 3832 opp-720000000 { 3833 opp-hz = /bits/ 64 <720000000>; 3834 required-opps = <&rpmhpd_opp_low_svs>; 3835 }; 3836 3837 opp-1014000000 { 3838 opp-hz = /bits/ 64 <1014000000>; 3839 required-opps = <&rpmhpd_opp_svs>; 3840 }; 3841 3842 opp-1098000000 { 3843 opp-hz = /bits/ 64 <1098000000>; 3844 required-opps = <&rpmhpd_opp_svs_l1>; 3845 }; 3846 3847 opp-1332000000 { 3848 opp-hz = /bits/ 64 <1332000000>; 3849 required-opps = <&rpmhpd_opp_nom>; 3850 }; 3851 }; 3852 }; 3853 3854 videocc: clock-controller@abf0000 { 3855 compatible = "qcom,sm8250-videocc"; 3856 reg = <0 0x0abf0000 0 0x10000>; 3857 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 3858 <&rpmhcc RPMH_CXO_CLK>, 3859 <&rpmhcc RPMH_CXO_CLK_A>; 3860 power-domains = <&rpmhpd SM8250_MMCX>; 3861 required-opps = <&rpmhpd_opp_low_svs>; 3862 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 3863 #clock-cells = <1>; 3864 #reset-cells = <1>; 3865 #power-domain-cells = <1>; 3866 }; 3867 3868 cci0: cci@ac4f000 { 3869 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 3870 #address-cells = <1>; 3871 #size-cells = <0>; 3872 3873 reg = <0 0x0ac4f000 0 0x1000>; 3874 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3875 power-domains = <&camcc TITAN_TOP_GDSC>; 3876 3877 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3878 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3879 <&camcc CAM_CC_CPAS_AHB_CLK>, 3880 <&camcc CAM_CC_CCI_0_CLK>, 3881 <&camcc CAM_CC_CCI_0_CLK_SRC>; 3882 clock-names = "camnoc_axi", 3883 "slow_ahb_src", 3884 "cpas_ahb", 3885 "cci", 3886 "cci_src"; 3887 3888 pinctrl-0 = <&cci0_default>; 3889 pinctrl-1 = <&cci0_sleep>; 3890 pinctrl-names = "default", "sleep"; 3891 3892 status = "disabled"; 3893 3894 cci0_i2c0: i2c-bus@0 { 3895 reg = <0>; 3896 clock-frequency = <1000000>; 3897 #address-cells = <1>; 3898 #size-cells = <0>; 3899 }; 3900 3901 cci0_i2c1: i2c-bus@1 { 3902 reg = <1>; 3903 clock-frequency = <1000000>; 3904 #address-cells = <1>; 3905 #size-cells = <0>; 3906 }; 3907 }; 3908 3909 cci1: cci@ac50000 { 3910 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 3911 #address-cells = <1>; 3912 #size-cells = <0>; 3913 3914 reg = <0 0x0ac50000 0 0x1000>; 3915 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 3916 power-domains = <&camcc TITAN_TOP_GDSC>; 3917 3918 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3919 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3920 <&camcc CAM_CC_CPAS_AHB_CLK>, 3921 <&camcc CAM_CC_CCI_1_CLK>, 3922 <&camcc CAM_CC_CCI_1_CLK_SRC>; 3923 clock-names = "camnoc_axi", 3924 "slow_ahb_src", 3925 "cpas_ahb", 3926 "cci", 3927 "cci_src"; 3928 3929 pinctrl-0 = <&cci1_default>; 3930 pinctrl-1 = <&cci1_sleep>; 3931 pinctrl-names = "default", "sleep"; 3932 3933 status = "disabled"; 3934 3935 cci1_i2c0: i2c-bus@0 { 3936 reg = <0>; 3937 clock-frequency = <1000000>; 3938 #address-cells = <1>; 3939 #size-cells = <0>; 3940 }; 3941 3942 cci1_i2c1: i2c-bus@1 { 3943 reg = <1>; 3944 clock-frequency = <1000000>; 3945 #address-cells = <1>; 3946 #size-cells = <0>; 3947 }; 3948 }; 3949 3950 camss: camss@ac6a000 { 3951 compatible = "qcom,sm8250-camss"; 3952 status = "disabled"; 3953 3954 reg = <0 0x0ac6a000 0 0x2000>, 3955 <0 0x0ac6c000 0 0x2000>, 3956 <0 0x0ac6e000 0 0x1000>, 3957 <0 0x0ac70000 0 0x1000>, 3958 <0 0x0ac72000 0 0x1000>, 3959 <0 0x0ac74000 0 0x1000>, 3960 <0 0x0acb4000 0 0xd000>, 3961 <0 0x0acc3000 0 0xd000>, 3962 <0 0x0acd9000 0 0x2200>, 3963 <0 0x0acdb200 0 0x2200>; 3964 reg-names = "csiphy0", 3965 "csiphy1", 3966 "csiphy2", 3967 "csiphy3", 3968 "csiphy4", 3969 "csiphy5", 3970 "vfe0", 3971 "vfe1", 3972 "vfe_lite0", 3973 "vfe_lite1"; 3974 3975 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 3976 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 3977 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 3978 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 3979 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 3980 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 3981 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 3982 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 3983 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 3984 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 3985 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 3986 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 3987 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 3988 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 3989 interrupt-names = "csiphy0", 3990 "csiphy1", 3991 "csiphy2", 3992 "csiphy3", 3993 "csiphy4", 3994 "csiphy5", 3995 "csid0", 3996 "csid1", 3997 "csid2", 3998 "csid3", 3999 "vfe0", 4000 "vfe1", 4001 "vfe_lite0", 4002 "vfe_lite1"; 4003 4004 power-domains = <&camcc IFE_0_GDSC>, 4005 <&camcc IFE_1_GDSC>, 4006 <&camcc TITAN_TOP_GDSC>; 4007 4008 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4009 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4010 <&gcc GCC_CAMERA_SF_AXI_CLK>, 4011 <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4012 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, 4013 <&camcc CAM_CC_CORE_AHB_CLK>, 4014 <&camcc CAM_CC_CPAS_AHB_CLK>, 4015 <&camcc CAM_CC_CSIPHY0_CLK>, 4016 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4017 <&camcc CAM_CC_CSIPHY1_CLK>, 4018 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4019 <&camcc CAM_CC_CSIPHY2_CLK>, 4020 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4021 <&camcc CAM_CC_CSIPHY3_CLK>, 4022 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 4023 <&camcc CAM_CC_CSIPHY4_CLK>, 4024 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 4025 <&camcc CAM_CC_CSIPHY5_CLK>, 4026 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 4027 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4028 <&camcc CAM_CC_IFE_0_AHB_CLK>, 4029 <&camcc CAM_CC_IFE_0_AXI_CLK>, 4030 <&camcc CAM_CC_IFE_0_CLK>, 4031 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4032 <&camcc CAM_CC_IFE_0_CSID_CLK>, 4033 <&camcc CAM_CC_IFE_0_AREG_CLK>, 4034 <&camcc CAM_CC_IFE_1_AHB_CLK>, 4035 <&camcc CAM_CC_IFE_1_AXI_CLK>, 4036 <&camcc CAM_CC_IFE_1_CLK>, 4037 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4038 <&camcc CAM_CC_IFE_1_CSID_CLK>, 4039 <&camcc CAM_CC_IFE_1_AREG_CLK>, 4040 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 4041 <&camcc CAM_CC_IFE_LITE_AXI_CLK>, 4042 <&camcc CAM_CC_IFE_LITE_CLK>, 4043 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4044 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 4045 4046 clock-names = "cam_ahb_clk", 4047 "cam_hf_axi", 4048 "cam_sf_axi", 4049 "camnoc_axi", 4050 "camnoc_axi_src", 4051 "core_ahb", 4052 "cpas_ahb", 4053 "csiphy0", 4054 "csiphy0_timer", 4055 "csiphy1", 4056 "csiphy1_timer", 4057 "csiphy2", 4058 "csiphy2_timer", 4059 "csiphy3", 4060 "csiphy3_timer", 4061 "csiphy4", 4062 "csiphy4_timer", 4063 "csiphy5", 4064 "csiphy5_timer", 4065 "slow_ahb_src", 4066 "vfe0_ahb", 4067 "vfe0_axi", 4068 "vfe0", 4069 "vfe0_cphy_rx", 4070 "vfe0_csid", 4071 "vfe0_areg", 4072 "vfe1_ahb", 4073 "vfe1_axi", 4074 "vfe1", 4075 "vfe1_cphy_rx", 4076 "vfe1_csid", 4077 "vfe1_areg", 4078 "vfe_lite_ahb", 4079 "vfe_lite_axi", 4080 "vfe_lite", 4081 "vfe_lite_cphy_rx", 4082 "vfe_lite_csid"; 4083 4084 iommus = <&apps_smmu 0x800 0x400>, 4085 <&apps_smmu 0x801 0x400>, 4086 <&apps_smmu 0x840 0x400>, 4087 <&apps_smmu 0x841 0x400>, 4088 <&apps_smmu 0xc00 0x400>, 4089 <&apps_smmu 0xc01 0x400>, 4090 <&apps_smmu 0xc40 0x400>, 4091 <&apps_smmu 0xc41 0x400>; 4092 4093 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>, 4094 <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>, 4095 <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>, 4096 <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>; 4097 interconnect-names = "cam_ahb", 4098 "cam_hf_0_mnoc", 4099 "cam_sf_0_mnoc", 4100 "cam_sf_icp_mnoc"; 4101 4102 ports { 4103 #address-cells = <1>; 4104 #size-cells = <0>; 4105 4106 port@0 { 4107 reg = <0>; 4108 }; 4109 4110 port@1 { 4111 reg = <1>; 4112 }; 4113 4114 port@2 { 4115 reg = <2>; 4116 }; 4117 4118 port@3 { 4119 reg = <3>; 4120 }; 4121 4122 port@4 { 4123 reg = <4>; 4124 }; 4125 4126 port@5 { 4127 reg = <5>; 4128 }; 4129 }; 4130 }; 4131 4132 camcc: clock-controller@ad00000 { 4133 compatible = "qcom,sm8250-camcc"; 4134 reg = <0 0x0ad00000 0 0x10000>; 4135 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4136 <&rpmhcc RPMH_CXO_CLK>, 4137 <&rpmhcc RPMH_CXO_CLK_A>, 4138 <&sleep_clk>; 4139 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 4140 power-domains = <&rpmhpd SM8250_MMCX>; 4141 required-opps = <&rpmhpd_opp_low_svs>; 4142 status = "disabled"; 4143 #clock-cells = <1>; 4144 #reset-cells = <1>; 4145 #power-domain-cells = <1>; 4146 }; 4147 4148 mdss: display-subsystem@ae00000 { 4149 compatible = "qcom,sm8250-mdss"; 4150 reg = <0 0x0ae00000 0 0x1000>; 4151 reg-names = "mdss"; 4152 4153 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 4154 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 4155 interconnect-names = "mdp0-mem", "mdp1-mem"; 4156 4157 power-domains = <&dispcc MDSS_GDSC>; 4158 4159 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4160 <&gcc GCC_DISP_HF_AXI_CLK>, 4161 <&gcc GCC_DISP_SF_AXI_CLK>, 4162 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4163 clock-names = "iface", "bus", "nrt_bus", "core"; 4164 4165 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4166 interrupt-controller; 4167 #interrupt-cells = <1>; 4168 4169 iommus = <&apps_smmu 0x820 0x402>; 4170 4171 status = "disabled"; 4172 4173 #address-cells = <2>; 4174 #size-cells = <2>; 4175 ranges; 4176 4177 mdss_mdp: display-controller@ae01000 { 4178 compatible = "qcom,sm8250-dpu"; 4179 reg = <0 0x0ae01000 0 0x8f000>, 4180 <0 0x0aeb0000 0 0x2008>; 4181 reg-names = "mdp", "vbif"; 4182 4183 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4184 <&gcc GCC_DISP_HF_AXI_CLK>, 4185 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4186 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4187 clock-names = "iface", "bus", "core", "vsync"; 4188 4189 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4190 assigned-clock-rates = <19200000>; 4191 4192 operating-points-v2 = <&mdp_opp_table>; 4193 power-domains = <&rpmhpd SM8250_MMCX>; 4194 4195 interrupt-parent = <&mdss>; 4196 interrupts = <0>; 4197 4198 ports { 4199 #address-cells = <1>; 4200 #size-cells = <0>; 4201 4202 port@0 { 4203 reg = <0>; 4204 dpu_intf1_out: endpoint { 4205 remote-endpoint = <&dsi0_in>; 4206 }; 4207 }; 4208 4209 port@1 { 4210 reg = <1>; 4211 dpu_intf2_out: endpoint { 4212 remote-endpoint = <&dsi1_in>; 4213 }; 4214 }; 4215 }; 4216 4217 mdp_opp_table: opp-table { 4218 compatible = "operating-points-v2"; 4219 4220 opp-200000000 { 4221 opp-hz = /bits/ 64 <200000000>; 4222 required-opps = <&rpmhpd_opp_low_svs>; 4223 }; 4224 4225 opp-300000000 { 4226 opp-hz = /bits/ 64 <300000000>; 4227 required-opps = <&rpmhpd_opp_svs>; 4228 }; 4229 4230 opp-345000000 { 4231 opp-hz = /bits/ 64 <345000000>; 4232 required-opps = <&rpmhpd_opp_svs_l1>; 4233 }; 4234 4235 opp-460000000 { 4236 opp-hz = /bits/ 64 <460000000>; 4237 required-opps = <&rpmhpd_opp_nom>; 4238 }; 4239 }; 4240 }; 4241 4242 dsi0: dsi@ae94000 { 4243 compatible = "qcom,sm8250-dsi-ctrl", 4244 "qcom,mdss-dsi-ctrl"; 4245 reg = <0 0x0ae94000 0 0x400>; 4246 reg-names = "dsi_ctrl"; 4247 4248 interrupt-parent = <&mdss>; 4249 interrupts = <4>; 4250 4251 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4252 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4253 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4254 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4255 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4256 <&gcc GCC_DISP_HF_AXI_CLK>; 4257 clock-names = "byte", 4258 "byte_intf", 4259 "pixel", 4260 "core", 4261 "iface", 4262 "bus"; 4263 4264 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4265 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 4266 4267 operating-points-v2 = <&dsi_opp_table>; 4268 power-domains = <&rpmhpd SM8250_MMCX>; 4269 4270 phys = <&dsi0_phy>; 4271 4272 status = "disabled"; 4273 4274 #address-cells = <1>; 4275 #size-cells = <0>; 4276 4277 ports { 4278 #address-cells = <1>; 4279 #size-cells = <0>; 4280 4281 port@0 { 4282 reg = <0>; 4283 dsi0_in: endpoint { 4284 remote-endpoint = <&dpu_intf1_out>; 4285 }; 4286 }; 4287 4288 port@1 { 4289 reg = <1>; 4290 dsi0_out: endpoint { 4291 }; 4292 }; 4293 }; 4294 4295 dsi_opp_table: opp-table { 4296 compatible = "operating-points-v2"; 4297 4298 opp-187500000 { 4299 opp-hz = /bits/ 64 <187500000>; 4300 required-opps = <&rpmhpd_opp_low_svs>; 4301 }; 4302 4303 opp-300000000 { 4304 opp-hz = /bits/ 64 <300000000>; 4305 required-opps = <&rpmhpd_opp_svs>; 4306 }; 4307 4308 opp-358000000 { 4309 opp-hz = /bits/ 64 <358000000>; 4310 required-opps = <&rpmhpd_opp_svs_l1>; 4311 }; 4312 }; 4313 }; 4314 4315 dsi0_phy: phy@ae94400 { 4316 compatible = "qcom,dsi-phy-7nm"; 4317 reg = <0 0x0ae94400 0 0x200>, 4318 <0 0x0ae94600 0 0x280>, 4319 <0 0x0ae94900 0 0x260>; 4320 reg-names = "dsi_phy", 4321 "dsi_phy_lane", 4322 "dsi_pll"; 4323 4324 #clock-cells = <1>; 4325 #phy-cells = <0>; 4326 4327 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4328 <&rpmhcc RPMH_CXO_CLK>; 4329 clock-names = "iface", "ref"; 4330 4331 status = "disabled"; 4332 }; 4333 4334 dsi1: dsi@ae96000 { 4335 compatible = "qcom,sm8250-dsi-ctrl", 4336 "qcom,mdss-dsi-ctrl"; 4337 reg = <0 0x0ae96000 0 0x400>; 4338 reg-names = "dsi_ctrl"; 4339 4340 interrupt-parent = <&mdss>; 4341 interrupts = <5>; 4342 4343 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4344 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4345 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4346 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4347 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4348 <&gcc GCC_DISP_HF_AXI_CLK>; 4349 clock-names = "byte", 4350 "byte_intf", 4351 "pixel", 4352 "core", 4353 "iface", 4354 "bus"; 4355 4356 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4357 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 4358 4359 operating-points-v2 = <&dsi_opp_table>; 4360 power-domains = <&rpmhpd SM8250_MMCX>; 4361 4362 phys = <&dsi1_phy>; 4363 4364 status = "disabled"; 4365 4366 #address-cells = <1>; 4367 #size-cells = <0>; 4368 4369 ports { 4370 #address-cells = <1>; 4371 #size-cells = <0>; 4372 4373 port@0 { 4374 reg = <0>; 4375 dsi1_in: endpoint { 4376 remote-endpoint = <&dpu_intf2_out>; 4377 }; 4378 }; 4379 4380 port@1 { 4381 reg = <1>; 4382 dsi1_out: endpoint { 4383 }; 4384 }; 4385 }; 4386 }; 4387 4388 dsi1_phy: phy@ae96400 { 4389 compatible = "qcom,dsi-phy-7nm"; 4390 reg = <0 0x0ae96400 0 0x200>, 4391 <0 0x0ae96600 0 0x280>, 4392 <0 0x0ae96900 0 0x260>; 4393 reg-names = "dsi_phy", 4394 "dsi_phy_lane", 4395 "dsi_pll"; 4396 4397 #clock-cells = <1>; 4398 #phy-cells = <0>; 4399 4400 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4401 <&rpmhcc RPMH_CXO_CLK>; 4402 clock-names = "iface", "ref"; 4403 4404 status = "disabled"; 4405 }; 4406 }; 4407 4408 dispcc: clock-controller@af00000 { 4409 compatible = "qcom,sm8250-dispcc"; 4410 reg = <0 0x0af00000 0 0x10000>; 4411 power-domains = <&rpmhpd SM8250_MMCX>; 4412 required-opps = <&rpmhpd_opp_low_svs>; 4413 clocks = <&rpmhcc RPMH_CXO_CLK>, 4414 <&dsi0_phy 0>, 4415 <&dsi0_phy 1>, 4416 <&dsi1_phy 0>, 4417 <&dsi1_phy 1>, 4418 <&dp_phy 0>, 4419 <&dp_phy 1>; 4420 clock-names = "bi_tcxo", 4421 "dsi0_phy_pll_out_byteclk", 4422 "dsi0_phy_pll_out_dsiclk", 4423 "dsi1_phy_pll_out_byteclk", 4424 "dsi1_phy_pll_out_dsiclk", 4425 "dp_phy_pll_link_clk", 4426 "dp_phy_pll_vco_div_clk"; 4427 #clock-cells = <1>; 4428 #reset-cells = <1>; 4429 #power-domain-cells = <1>; 4430 }; 4431 4432 pdc: interrupt-controller@b220000 { 4433 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 4434 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 4435 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4436 <125 63 1>, <126 716 12>; 4437 #interrupt-cells = <2>; 4438 interrupt-parent = <&intc>; 4439 interrupt-controller; 4440 }; 4441 4442 tsens0: thermal-sensor@c263000 { 4443 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 4444 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4445 <0 0x0c222000 0 0x1ff>; /* SROT */ 4446 #qcom,sensors = <16>; 4447 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4448 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4449 interrupt-names = "uplow", "critical"; 4450 #thermal-sensor-cells = <1>; 4451 }; 4452 4453 tsens1: thermal-sensor@c265000 { 4454 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 4455 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4456 <0 0x0c223000 0 0x1ff>; /* SROT */ 4457 #qcom,sensors = <9>; 4458 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4459 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4460 interrupt-names = "uplow", "critical"; 4461 #thermal-sensor-cells = <1>; 4462 }; 4463 4464 aoss_qmp: power-management@c300000 { 4465 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; 4466 reg = <0 0x0c300000 0 0x400>; 4467 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4468 IPCC_MPROC_SIGNAL_GLINK_QMP 4469 IRQ_TYPE_EDGE_RISING>; 4470 mboxes = <&ipcc IPCC_CLIENT_AOP 4471 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4472 4473 #clock-cells = <0>; 4474 }; 4475 4476 sram@c3f0000 { 4477 compatible = "qcom,rpmh-stats"; 4478 reg = <0 0x0c3f0000 0 0x400>; 4479 }; 4480 4481 spmi_bus: spmi@c440000 { 4482 compatible = "qcom,spmi-pmic-arb"; 4483 reg = <0x0 0x0c440000 0x0 0x0001100>, 4484 <0x0 0x0c600000 0x0 0x2000000>, 4485 <0x0 0x0e600000 0x0 0x0100000>, 4486 <0x0 0x0e700000 0x0 0x00a0000>, 4487 <0x0 0x0c40a000 0x0 0x0026000>; 4488 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4489 interrupt-names = "periph_irq"; 4490 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4491 qcom,ee = <0>; 4492 qcom,channel = <0>; 4493 #address-cells = <2>; 4494 #size-cells = <0>; 4495 interrupt-controller; 4496 #interrupt-cells = <4>; 4497 }; 4498 4499 tlmm: pinctrl@f100000 { 4500 compatible = "qcom,sm8250-pinctrl"; 4501 reg = <0 0x0f100000 0 0x300000>, 4502 <0 0x0f500000 0 0x300000>, 4503 <0 0x0f900000 0 0x300000>; 4504 reg-names = "west", "south", "north"; 4505 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4506 gpio-controller; 4507 #gpio-cells = <2>; 4508 interrupt-controller; 4509 #interrupt-cells = <2>; 4510 gpio-ranges = <&tlmm 0 0 181>; 4511 wakeup-parent = <&pdc>; 4512 4513 cam2_default: cam2-default-state { 4514 rst-pins { 4515 pins = "gpio78"; 4516 function = "gpio"; 4517 drive-strength = <2>; 4518 bias-disable; 4519 }; 4520 4521 mclk-pins { 4522 pins = "gpio96"; 4523 function = "cam_mclk"; 4524 drive-strength = <16>; 4525 bias-disable; 4526 }; 4527 }; 4528 4529 cam2_suspend: cam2-suspend-state { 4530 rst-pins { 4531 pins = "gpio78"; 4532 function = "gpio"; 4533 drive-strength = <2>; 4534 bias-pull-down; 4535 output-low; 4536 }; 4537 4538 mclk-pins { 4539 pins = "gpio96"; 4540 function = "cam_mclk"; 4541 drive-strength = <2>; 4542 bias-disable; 4543 }; 4544 }; 4545 4546 cci0_default: cci0-default-state { 4547 cci0_i2c0_default: cci0-i2c0-default-pins { 4548 /* SDA, SCL */ 4549 pins = "gpio101", "gpio102"; 4550 function = "cci_i2c"; 4551 4552 bias-pull-up; 4553 drive-strength = <2>; /* 2 mA */ 4554 }; 4555 4556 cci0_i2c1_default: cci0-i2c1-default-pins { 4557 /* SDA, SCL */ 4558 pins = "gpio103", "gpio104"; 4559 function = "cci_i2c"; 4560 4561 bias-pull-up; 4562 drive-strength = <2>; /* 2 mA */ 4563 }; 4564 }; 4565 4566 cci0_sleep: cci0-sleep-state { 4567 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 4568 /* SDA, SCL */ 4569 pins = "gpio101", "gpio102"; 4570 function = "cci_i2c"; 4571 4572 drive-strength = <2>; /* 2 mA */ 4573 bias-pull-down; 4574 }; 4575 4576 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 4577 /* SDA, SCL */ 4578 pins = "gpio103", "gpio104"; 4579 function = "cci_i2c"; 4580 4581 drive-strength = <2>; /* 2 mA */ 4582 bias-pull-down; 4583 }; 4584 }; 4585 4586 cci1_default: cci1-default-state { 4587 cci1_i2c0_default: cci1-i2c0-default-pins { 4588 /* SDA, SCL */ 4589 pins = "gpio105","gpio106"; 4590 function = "cci_i2c"; 4591 4592 bias-pull-up; 4593 drive-strength = <2>; /* 2 mA */ 4594 }; 4595 4596 cci1_i2c1_default: cci1-i2c1-default-pins { 4597 /* SDA, SCL */ 4598 pins = "gpio107","gpio108"; 4599 function = "cci_i2c"; 4600 4601 bias-pull-up; 4602 drive-strength = <2>; /* 2 mA */ 4603 }; 4604 }; 4605 4606 cci1_sleep: cci1-sleep-state { 4607 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 4608 /* SDA, SCL */ 4609 pins = "gpio105","gpio106"; 4610 function = "cci_i2c"; 4611 4612 bias-pull-down; 4613 drive-strength = <2>; /* 2 mA */ 4614 }; 4615 4616 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 4617 /* SDA, SCL */ 4618 pins = "gpio107","gpio108"; 4619 function = "cci_i2c"; 4620 4621 bias-pull-down; 4622 drive-strength = <2>; /* 2 mA */ 4623 }; 4624 }; 4625 4626 pri_mi2s_active: pri-mi2s-active-state { 4627 sclk-pins { 4628 pins = "gpio138"; 4629 function = "mi2s0_sck"; 4630 drive-strength = <8>; 4631 bias-disable; 4632 }; 4633 4634 ws-pins { 4635 pins = "gpio141"; 4636 function = "mi2s0_ws"; 4637 drive-strength = <8>; 4638 output-high; 4639 }; 4640 4641 data0-pins { 4642 pins = "gpio139"; 4643 function = "mi2s0_data0"; 4644 drive-strength = <8>; 4645 bias-disable; 4646 output-high; 4647 }; 4648 4649 data1-pins { 4650 pins = "gpio140"; 4651 function = "mi2s0_data1"; 4652 drive-strength = <8>; 4653 output-high; 4654 }; 4655 }; 4656 4657 qup_i2c0_default: qup-i2c0-default-state { 4658 pins = "gpio28", "gpio29"; 4659 function = "qup0"; 4660 drive-strength = <2>; 4661 bias-disable; 4662 }; 4663 4664 qup_i2c1_default: qup-i2c1-default-state { 4665 pins = "gpio4", "gpio5"; 4666 function = "qup1"; 4667 drive-strength = <2>; 4668 bias-disable; 4669 }; 4670 4671 qup_i2c2_default: qup-i2c2-default-state { 4672 pins = "gpio115", "gpio116"; 4673 function = "qup2"; 4674 drive-strength = <2>; 4675 bias-disable; 4676 }; 4677 4678 qup_i2c3_default: qup-i2c3-default-state { 4679 pins = "gpio119", "gpio120"; 4680 function = "qup3"; 4681 drive-strength = <2>; 4682 bias-disable; 4683 }; 4684 4685 qup_i2c4_default: qup-i2c4-default-state { 4686 pins = "gpio8", "gpio9"; 4687 function = "qup4"; 4688 drive-strength = <2>; 4689 bias-disable; 4690 }; 4691 4692 qup_i2c5_default: qup-i2c5-default-state { 4693 pins = "gpio12", "gpio13"; 4694 function = "qup5"; 4695 drive-strength = <2>; 4696 bias-disable; 4697 }; 4698 4699 qup_i2c6_default: qup-i2c6-default-state { 4700 pins = "gpio16", "gpio17"; 4701 function = "qup6"; 4702 drive-strength = <2>; 4703 bias-disable; 4704 }; 4705 4706 qup_i2c7_default: qup-i2c7-default-state { 4707 pins = "gpio20", "gpio21"; 4708 function = "qup7"; 4709 drive-strength = <2>; 4710 bias-disable; 4711 }; 4712 4713 qup_i2c8_default: qup-i2c8-default-state { 4714 pins = "gpio24", "gpio25"; 4715 function = "qup8"; 4716 drive-strength = <2>; 4717 bias-disable; 4718 }; 4719 4720 qup_i2c9_default: qup-i2c9-default-state { 4721 pins = "gpio125", "gpio126"; 4722 function = "qup9"; 4723 drive-strength = <2>; 4724 bias-disable; 4725 }; 4726 4727 qup_i2c10_default: qup-i2c10-default-state { 4728 pins = "gpio129", "gpio130"; 4729 function = "qup10"; 4730 drive-strength = <2>; 4731 bias-disable; 4732 }; 4733 4734 qup_i2c11_default: qup-i2c11-default-state { 4735 pins = "gpio60", "gpio61"; 4736 function = "qup11"; 4737 drive-strength = <2>; 4738 bias-disable; 4739 }; 4740 4741 qup_i2c12_default: qup-i2c12-default-state { 4742 pins = "gpio32", "gpio33"; 4743 function = "qup12"; 4744 drive-strength = <2>; 4745 bias-disable; 4746 }; 4747 4748 qup_i2c13_default: qup-i2c13-default-state { 4749 pins = "gpio36", "gpio37"; 4750 function = "qup13"; 4751 drive-strength = <2>; 4752 bias-disable; 4753 }; 4754 4755 qup_i2c14_default: qup-i2c14-default-state { 4756 pins = "gpio40", "gpio41"; 4757 function = "qup14"; 4758 drive-strength = <2>; 4759 bias-disable; 4760 }; 4761 4762 qup_i2c15_default: qup-i2c15-default-state { 4763 pins = "gpio44", "gpio45"; 4764 function = "qup15"; 4765 drive-strength = <2>; 4766 bias-disable; 4767 }; 4768 4769 qup_i2c16_default: qup-i2c16-default-state { 4770 pins = "gpio48", "gpio49"; 4771 function = "qup16"; 4772 drive-strength = <2>; 4773 bias-disable; 4774 }; 4775 4776 qup_i2c17_default: qup-i2c17-default-state { 4777 pins = "gpio52", "gpio53"; 4778 function = "qup17"; 4779 drive-strength = <2>; 4780 bias-disable; 4781 }; 4782 4783 qup_i2c18_default: qup-i2c18-default-state { 4784 pins = "gpio56", "gpio57"; 4785 function = "qup18"; 4786 drive-strength = <2>; 4787 bias-disable; 4788 }; 4789 4790 qup_i2c19_default: qup-i2c19-default-state { 4791 pins = "gpio0", "gpio1"; 4792 function = "qup19"; 4793 drive-strength = <2>; 4794 bias-disable; 4795 }; 4796 4797 qup_spi0_cs: qup-spi0-cs-state { 4798 pins = "gpio31"; 4799 function = "qup0"; 4800 }; 4801 4802 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4803 pins = "gpio31"; 4804 function = "gpio"; 4805 }; 4806 4807 qup_spi0_data_clk: qup-spi0-data-clk-state { 4808 pins = "gpio28", "gpio29", 4809 "gpio30"; 4810 function = "qup0"; 4811 }; 4812 4813 qup_spi1_cs: qup-spi1-cs-state { 4814 pins = "gpio7"; 4815 function = "qup1"; 4816 }; 4817 4818 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4819 pins = "gpio7"; 4820 function = "gpio"; 4821 }; 4822 4823 qup_spi1_data_clk: qup-spi1-data-clk-state { 4824 pins = "gpio4", "gpio5", 4825 "gpio6"; 4826 function = "qup1"; 4827 }; 4828 4829 qup_spi2_cs: qup-spi2-cs-state { 4830 pins = "gpio118"; 4831 function = "qup2"; 4832 }; 4833 4834 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4835 pins = "gpio118"; 4836 function = "gpio"; 4837 }; 4838 4839 qup_spi2_data_clk: qup-spi2-data-clk-state { 4840 pins = "gpio115", "gpio116", 4841 "gpio117"; 4842 function = "qup2"; 4843 }; 4844 4845 qup_spi3_cs: qup-spi3-cs-state { 4846 pins = "gpio122"; 4847 function = "qup3"; 4848 }; 4849 4850 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4851 pins = "gpio122"; 4852 function = "gpio"; 4853 }; 4854 4855 qup_spi3_data_clk: qup-spi3-data-clk-state { 4856 pins = "gpio119", "gpio120", 4857 "gpio121"; 4858 function = "qup3"; 4859 }; 4860 4861 qup_spi4_cs: qup-spi4-cs-state { 4862 pins = "gpio11"; 4863 function = "qup4"; 4864 }; 4865 4866 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4867 pins = "gpio11"; 4868 function = "gpio"; 4869 }; 4870 4871 qup_spi4_data_clk: qup-spi4-data-clk-state { 4872 pins = "gpio8", "gpio9", 4873 "gpio10"; 4874 function = "qup4"; 4875 }; 4876 4877 qup_spi5_cs: qup-spi5-cs-state { 4878 pins = "gpio15"; 4879 function = "qup5"; 4880 }; 4881 4882 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4883 pins = "gpio15"; 4884 function = "gpio"; 4885 }; 4886 4887 qup_spi5_data_clk: qup-spi5-data-clk-state { 4888 pins = "gpio12", "gpio13", 4889 "gpio14"; 4890 function = "qup5"; 4891 }; 4892 4893 qup_spi6_cs: qup-spi6-cs-state { 4894 pins = "gpio19"; 4895 function = "qup6"; 4896 }; 4897 4898 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4899 pins = "gpio19"; 4900 function = "gpio"; 4901 }; 4902 4903 qup_spi6_data_clk: qup-spi6-data-clk-state { 4904 pins = "gpio16", "gpio17", 4905 "gpio18"; 4906 function = "qup6"; 4907 }; 4908 4909 qup_spi7_cs: qup-spi7-cs-state { 4910 pins = "gpio23"; 4911 function = "qup7"; 4912 }; 4913 4914 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4915 pins = "gpio23"; 4916 function = "gpio"; 4917 }; 4918 4919 qup_spi7_data_clk: qup-spi7-data-clk-state { 4920 pins = "gpio20", "gpio21", 4921 "gpio22"; 4922 function = "qup7"; 4923 }; 4924 4925 qup_spi8_cs: qup-spi8-cs-state { 4926 pins = "gpio27"; 4927 function = "qup8"; 4928 }; 4929 4930 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4931 pins = "gpio27"; 4932 function = "gpio"; 4933 }; 4934 4935 qup_spi8_data_clk: qup-spi8-data-clk-state { 4936 pins = "gpio24", "gpio25", 4937 "gpio26"; 4938 function = "qup8"; 4939 }; 4940 4941 qup_spi9_cs: qup-spi9-cs-state { 4942 pins = "gpio128"; 4943 function = "qup9"; 4944 }; 4945 4946 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4947 pins = "gpio128"; 4948 function = "gpio"; 4949 }; 4950 4951 qup_spi9_data_clk: qup-spi9-data-clk-state { 4952 pins = "gpio125", "gpio126", 4953 "gpio127"; 4954 function = "qup9"; 4955 }; 4956 4957 qup_spi10_cs: qup-spi10-cs-state { 4958 pins = "gpio132"; 4959 function = "qup10"; 4960 }; 4961 4962 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4963 pins = "gpio132"; 4964 function = "gpio"; 4965 }; 4966 4967 qup_spi10_data_clk: qup-spi10-data-clk-state { 4968 pins = "gpio129", "gpio130", 4969 "gpio131"; 4970 function = "qup10"; 4971 }; 4972 4973 qup_spi11_cs: qup-spi11-cs-state { 4974 pins = "gpio63"; 4975 function = "qup11"; 4976 }; 4977 4978 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4979 pins = "gpio63"; 4980 function = "gpio"; 4981 }; 4982 4983 qup_spi11_data_clk: qup-spi11-data-clk-state { 4984 pins = "gpio60", "gpio61", 4985 "gpio62"; 4986 function = "qup11"; 4987 }; 4988 4989 qup_spi12_cs: qup-spi12-cs-state { 4990 pins = "gpio35"; 4991 function = "qup12"; 4992 }; 4993 4994 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4995 pins = "gpio35"; 4996 function = "gpio"; 4997 }; 4998 4999 qup_spi12_data_clk: qup-spi12-data-clk-state { 5000 pins = "gpio32", "gpio33", 5001 "gpio34"; 5002 function = "qup12"; 5003 }; 5004 5005 qup_spi13_cs: qup-spi13-cs-state { 5006 pins = "gpio39"; 5007 function = "qup13"; 5008 }; 5009 5010 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 5011 pins = "gpio39"; 5012 function = "gpio"; 5013 }; 5014 5015 qup_spi13_data_clk: qup-spi13-data-clk-state { 5016 pins = "gpio36", "gpio37", 5017 "gpio38"; 5018 function = "qup13"; 5019 }; 5020 5021 qup_spi14_cs: qup-spi14-cs-state { 5022 pins = "gpio43"; 5023 function = "qup14"; 5024 }; 5025 5026 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 5027 pins = "gpio43"; 5028 function = "gpio"; 5029 }; 5030 5031 qup_spi14_data_clk: qup-spi14-data-clk-state { 5032 pins = "gpio40", "gpio41", 5033 "gpio42"; 5034 function = "qup14"; 5035 }; 5036 5037 qup_spi15_cs: qup-spi15-cs-state { 5038 pins = "gpio47"; 5039 function = "qup15"; 5040 }; 5041 5042 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 5043 pins = "gpio47"; 5044 function = "gpio"; 5045 }; 5046 5047 qup_spi15_data_clk: qup-spi15-data-clk-state { 5048 pins = "gpio44", "gpio45", 5049 "gpio46"; 5050 function = "qup15"; 5051 }; 5052 5053 qup_spi16_cs: qup-spi16-cs-state { 5054 pins = "gpio51"; 5055 function = "qup16"; 5056 }; 5057 5058 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 5059 pins = "gpio51"; 5060 function = "gpio"; 5061 }; 5062 5063 qup_spi16_data_clk: qup-spi16-data-clk-state { 5064 pins = "gpio48", "gpio49", 5065 "gpio50"; 5066 function = "qup16"; 5067 }; 5068 5069 qup_spi17_cs: qup-spi17-cs-state { 5070 pins = "gpio55"; 5071 function = "qup17"; 5072 }; 5073 5074 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state { 5075 pins = "gpio55"; 5076 function = "gpio"; 5077 }; 5078 5079 qup_spi17_data_clk: qup-spi17-data-clk-state { 5080 pins = "gpio52", "gpio53", 5081 "gpio54"; 5082 function = "qup17"; 5083 }; 5084 5085 qup_spi18_cs: qup-spi18-cs-state { 5086 pins = "gpio59"; 5087 function = "qup18"; 5088 }; 5089 5090 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state { 5091 pins = "gpio59"; 5092 function = "gpio"; 5093 }; 5094 5095 qup_spi18_data_clk: qup-spi18-data-clk-state { 5096 pins = "gpio56", "gpio57", 5097 "gpio58"; 5098 function = "qup18"; 5099 }; 5100 5101 qup_spi19_cs: qup-spi19-cs-state { 5102 pins = "gpio3"; 5103 function = "qup19"; 5104 }; 5105 5106 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state { 5107 pins = "gpio3"; 5108 function = "gpio"; 5109 }; 5110 5111 qup_spi19_data_clk: qup-spi19-data-clk-state { 5112 pins = "gpio0", "gpio1", 5113 "gpio2"; 5114 function = "qup19"; 5115 }; 5116 5117 qup_uart2_default: qup-uart2-default-state { 5118 pins = "gpio117", "gpio118"; 5119 function = "qup2"; 5120 }; 5121 5122 qup_uart6_default: qup-uart6-default-state { 5123 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 5124 function = "qup6"; 5125 }; 5126 5127 qup_uart12_default: qup-uart12-default-state { 5128 pins = "gpio34", "gpio35"; 5129 function = "qup12"; 5130 }; 5131 5132 qup_uart17_default: qup-uart17-default-state { 5133 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 5134 function = "qup17"; 5135 }; 5136 5137 qup_uart18_default: qup-uart18-default-state { 5138 pins = "gpio58", "gpio59"; 5139 function = "qup18"; 5140 }; 5141 5142 tert_mi2s_active: tert-mi2s-active-state { 5143 sck-pins { 5144 pins = "gpio133"; 5145 function = "mi2s2_sck"; 5146 drive-strength = <8>; 5147 bias-disable; 5148 }; 5149 5150 data0-pins { 5151 pins = "gpio134"; 5152 function = "mi2s2_data0"; 5153 drive-strength = <8>; 5154 bias-disable; 5155 output-high; 5156 }; 5157 5158 ws-pins { 5159 pins = "gpio135"; 5160 function = "mi2s2_ws"; 5161 drive-strength = <8>; 5162 output-high; 5163 }; 5164 }; 5165 5166 sdc2_sleep_state: sdc2-sleep-state { 5167 clk-pins { 5168 pins = "sdc2_clk"; 5169 drive-strength = <2>; 5170 bias-disable; 5171 }; 5172 5173 cmd-pins { 5174 pins = "sdc2_cmd"; 5175 drive-strength = <2>; 5176 bias-pull-up; 5177 }; 5178 5179 data-pins { 5180 pins = "sdc2_data"; 5181 drive-strength = <2>; 5182 bias-pull-up; 5183 }; 5184 }; 5185 5186 pcie0_default_state: pcie0-default-state { 5187 perst-pins { 5188 pins = "gpio79"; 5189 function = "gpio"; 5190 drive-strength = <2>; 5191 bias-pull-down; 5192 }; 5193 5194 clkreq-pins { 5195 pins = "gpio80"; 5196 function = "pci_e0"; 5197 drive-strength = <2>; 5198 bias-pull-up; 5199 }; 5200 5201 wake-pins { 5202 pins = "gpio81"; 5203 function = "gpio"; 5204 drive-strength = <2>; 5205 bias-pull-up; 5206 }; 5207 }; 5208 5209 pcie1_default_state: pcie1-default-state { 5210 perst-pins { 5211 pins = "gpio82"; 5212 function = "gpio"; 5213 drive-strength = <2>; 5214 bias-pull-down; 5215 }; 5216 5217 clkreq-pins { 5218 pins = "gpio83"; 5219 function = "pci_e1"; 5220 drive-strength = <2>; 5221 bias-pull-up; 5222 }; 5223 5224 wake-pins { 5225 pins = "gpio84"; 5226 function = "gpio"; 5227 drive-strength = <2>; 5228 bias-pull-up; 5229 }; 5230 }; 5231 5232 pcie2_default_state: pcie2-default-state { 5233 perst-pins { 5234 pins = "gpio85"; 5235 function = "gpio"; 5236 drive-strength = <2>; 5237 bias-pull-down; 5238 }; 5239 5240 clkreq-pins { 5241 pins = "gpio86"; 5242 function = "pci_e2"; 5243 drive-strength = <2>; 5244 bias-pull-up; 5245 }; 5246 5247 wake-pins { 5248 pins = "gpio87"; 5249 function = "gpio"; 5250 drive-strength = <2>; 5251 bias-pull-up; 5252 }; 5253 }; 5254 }; 5255 5256 apps_smmu: iommu@15000000 { 5257 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 5258 reg = <0 0x15000000 0 0x100000>; 5259 #iommu-cells = <2>; 5260 #global-interrupts = <2>; 5261 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 5262 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5263 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5264 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5265 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5266 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5267 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5268 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5269 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5270 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5271 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5272 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5273 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5274 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5275 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5276 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5277 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5278 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5279 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5280 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5281 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5282 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5283 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5284 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5285 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5286 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5287 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5288 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5289 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5290 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5291 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5292 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5293 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5294 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5295 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5296 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5297 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5298 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5299 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5300 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5301 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5302 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5303 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5304 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5305 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5306 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5307 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5308 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5309 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5310 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5311 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5312 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5313 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5314 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5315 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5316 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5317 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5318 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5319 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5320 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5321 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5322 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5323 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5324 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5325 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5326 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5327 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5328 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5329 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5330 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5331 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5332 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5333 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5334 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5335 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5336 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5337 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5338 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5339 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5340 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5341 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5342 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5343 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5344 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5345 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5346 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5347 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5348 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5349 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5350 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5351 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5352 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5353 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5354 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5355 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5356 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5357 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 5358 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 5359 }; 5360 5361 adsp: remoteproc@17300000 { 5362 compatible = "qcom,sm8250-adsp-pas"; 5363 reg = <0 0x17300000 0 0x100>; 5364 5365 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 5366 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 5367 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 5368 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 5369 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 5370 interrupt-names = "wdog", "fatal", "ready", 5371 "handover", "stop-ack"; 5372 5373 clocks = <&rpmhcc RPMH_CXO_CLK>; 5374 clock-names = "xo"; 5375 5376 power-domains = <&rpmhpd SM8250_LCX>, 5377 <&rpmhpd SM8250_LMX>; 5378 power-domain-names = "lcx", "lmx"; 5379 5380 memory-region = <&adsp_mem>; 5381 5382 qcom,qmp = <&aoss_qmp>; 5383 5384 qcom,smem-states = <&smp2p_adsp_out 0>; 5385 qcom,smem-state-names = "stop"; 5386 5387 status = "disabled"; 5388 5389 glink-edge { 5390 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 5391 IPCC_MPROC_SIGNAL_GLINK_QMP 5392 IRQ_TYPE_EDGE_RISING>; 5393 mboxes = <&ipcc IPCC_CLIENT_LPASS 5394 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5395 5396 label = "lpass"; 5397 qcom,remote-pid = <2>; 5398 5399 apr { 5400 compatible = "qcom,apr-v2"; 5401 qcom,glink-channels = "apr_audio_svc"; 5402 qcom,domain = <APR_DOMAIN_ADSP>; 5403 #address-cells = <1>; 5404 #size-cells = <0>; 5405 5406 service@3 { 5407 reg = <APR_SVC_ADSP_CORE>; 5408 compatible = "qcom,q6core"; 5409 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5410 }; 5411 5412 q6afe: service@4 { 5413 compatible = "qcom,q6afe"; 5414 reg = <APR_SVC_AFE>; 5415 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5416 q6afedai: dais { 5417 compatible = "qcom,q6afe-dais"; 5418 #address-cells = <1>; 5419 #size-cells = <0>; 5420 #sound-dai-cells = <1>; 5421 }; 5422 5423 q6afecc: clock-controller { 5424 compatible = "qcom,q6afe-clocks"; 5425 #clock-cells = <2>; 5426 }; 5427 }; 5428 5429 q6asm: service@7 { 5430 compatible = "qcom,q6asm"; 5431 reg = <APR_SVC_ASM>; 5432 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5433 q6asmdai: dais { 5434 compatible = "qcom,q6asm-dais"; 5435 #address-cells = <1>; 5436 #size-cells = <0>; 5437 #sound-dai-cells = <1>; 5438 iommus = <&apps_smmu 0x1801 0x0>; 5439 }; 5440 }; 5441 5442 q6adm: service@8 { 5443 compatible = "qcom,q6adm"; 5444 reg = <APR_SVC_ADM>; 5445 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5446 q6routing: routing { 5447 compatible = "qcom,q6adm-routing"; 5448 #sound-dai-cells = <0>; 5449 }; 5450 }; 5451 }; 5452 5453 fastrpc { 5454 compatible = "qcom,fastrpc"; 5455 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5456 label = "adsp"; 5457 qcom,non-secure-domain; 5458 #address-cells = <1>; 5459 #size-cells = <0>; 5460 5461 compute-cb@3 { 5462 compatible = "qcom,fastrpc-compute-cb"; 5463 reg = <3>; 5464 iommus = <&apps_smmu 0x1803 0x0>; 5465 }; 5466 5467 compute-cb@4 { 5468 compatible = "qcom,fastrpc-compute-cb"; 5469 reg = <4>; 5470 iommus = <&apps_smmu 0x1804 0x0>; 5471 }; 5472 5473 compute-cb@5 { 5474 compatible = "qcom,fastrpc-compute-cb"; 5475 reg = <5>; 5476 iommus = <&apps_smmu 0x1805 0x0>; 5477 }; 5478 }; 5479 }; 5480 }; 5481 5482 intc: interrupt-controller@17a00000 { 5483 compatible = "arm,gic-v3"; 5484 #interrupt-cells = <3>; 5485 interrupt-controller; 5486 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 5487 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 5488 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5489 }; 5490 5491 watchdog@17c10000 { 5492 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 5493 reg = <0 0x17c10000 0 0x1000>; 5494 clocks = <&sleep_clk>; 5495 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5496 }; 5497 5498 timer@17c20000 { 5499 #address-cells = <1>; 5500 #size-cells = <1>; 5501 ranges = <0 0 0 0x20000000>; 5502 compatible = "arm,armv7-timer-mem"; 5503 reg = <0x0 0x17c20000 0x0 0x1000>; 5504 clock-frequency = <19200000>; 5505 5506 frame@17c21000 { 5507 frame-number = <0>; 5508 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5509 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5510 reg = <0x17c21000 0x1000>, 5511 <0x17c22000 0x1000>; 5512 }; 5513 5514 frame@17c23000 { 5515 frame-number = <1>; 5516 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5517 reg = <0x17c23000 0x1000>; 5518 status = "disabled"; 5519 }; 5520 5521 frame@17c25000 { 5522 frame-number = <2>; 5523 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5524 reg = <0x17c25000 0x1000>; 5525 status = "disabled"; 5526 }; 5527 5528 frame@17c27000 { 5529 frame-number = <3>; 5530 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5531 reg = <0x17c27000 0x1000>; 5532 status = "disabled"; 5533 }; 5534 5535 frame@17c29000 { 5536 frame-number = <4>; 5537 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5538 reg = <0x17c29000 0x1000>; 5539 status = "disabled"; 5540 }; 5541 5542 frame@17c2b000 { 5543 frame-number = <5>; 5544 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5545 reg = <0x17c2b000 0x1000>; 5546 status = "disabled"; 5547 }; 5548 5549 frame@17c2d000 { 5550 frame-number = <6>; 5551 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5552 reg = <0x17c2d000 0x1000>; 5553 status = "disabled"; 5554 }; 5555 }; 5556 5557 apps_rsc: rsc@18200000 { 5558 label = "apps_rsc"; 5559 compatible = "qcom,rpmh-rsc"; 5560 reg = <0x0 0x18200000 0x0 0x10000>, 5561 <0x0 0x18210000 0x0 0x10000>, 5562 <0x0 0x18220000 0x0 0x10000>; 5563 reg-names = "drv-0", "drv-1", "drv-2"; 5564 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5565 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5566 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5567 qcom,tcs-offset = <0xd00>; 5568 qcom,drv-id = <2>; 5569 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 5570 <WAKE_TCS 3>, <CONTROL_TCS 1>; 5571 power-domains = <&CLUSTER_PD>; 5572 5573 rpmhcc: clock-controller { 5574 compatible = "qcom,sm8250-rpmh-clk"; 5575 #clock-cells = <1>; 5576 clock-names = "xo"; 5577 clocks = <&xo_board>; 5578 }; 5579 5580 rpmhpd: power-controller { 5581 compatible = "qcom,sm8250-rpmhpd"; 5582 #power-domain-cells = <1>; 5583 operating-points-v2 = <&rpmhpd_opp_table>; 5584 5585 rpmhpd_opp_table: opp-table { 5586 compatible = "operating-points-v2"; 5587 5588 rpmhpd_opp_ret: opp1 { 5589 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5590 }; 5591 5592 rpmhpd_opp_min_svs: opp2 { 5593 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5594 }; 5595 5596 rpmhpd_opp_low_svs: opp3 { 5597 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5598 }; 5599 5600 rpmhpd_opp_svs: opp4 { 5601 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5602 }; 5603 5604 rpmhpd_opp_svs_l1: opp5 { 5605 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5606 }; 5607 5608 rpmhpd_opp_nom: opp6 { 5609 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5610 }; 5611 5612 rpmhpd_opp_nom_l1: opp7 { 5613 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5614 }; 5615 5616 rpmhpd_opp_nom_l2: opp8 { 5617 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5618 }; 5619 5620 rpmhpd_opp_turbo: opp9 { 5621 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5622 }; 5623 5624 rpmhpd_opp_turbo_l1: opp10 { 5625 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5626 }; 5627 }; 5628 }; 5629 5630 apps_bcm_voter: bcm-voter { 5631 compatible = "qcom,bcm-voter"; 5632 }; 5633 }; 5634 5635 epss_l3: interconnect@18590000 { 5636 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3"; 5637 reg = <0 0x18590000 0 0x1000>; 5638 5639 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5640 clock-names = "xo", "alternate"; 5641 5642 #interconnect-cells = <1>; 5643 }; 5644 5645 cpufreq_hw: cpufreq@18591000 { 5646 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 5647 reg = <0 0x18591000 0 0x1000>, 5648 <0 0x18592000 0 0x1000>, 5649 <0 0x18593000 0 0x1000>; 5650 reg-names = "freq-domain0", "freq-domain1", 5651 "freq-domain2"; 5652 5653 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5654 clock-names = "xo", "alternate"; 5655 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5656 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5657 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5658 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 5659 #freq-domain-cells = <1>; 5660 #clock-cells = <1>; 5661 }; 5662 }; 5663 5664 sound: sound { 5665 }; 5666 5667 timer { 5668 compatible = "arm,armv8-timer"; 5669 interrupts = <GIC_PPI 13 5670 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5671 <GIC_PPI 14 5672 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5673 <GIC_PPI 11 5674 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5675 <GIC_PPI 10 5676 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5677 }; 5678 5679 thermal-zones { 5680 cpu0-thermal { 5681 polling-delay-passive = <250>; 5682 polling-delay = <1000>; 5683 5684 thermal-sensors = <&tsens0 1>; 5685 5686 trips { 5687 cpu0_alert0: trip-point0 { 5688 temperature = <90000>; 5689 hysteresis = <2000>; 5690 type = "passive"; 5691 }; 5692 5693 cpu0_alert1: trip-point1 { 5694 temperature = <95000>; 5695 hysteresis = <2000>; 5696 type = "passive"; 5697 }; 5698 5699 cpu0_crit: cpu-crit { 5700 temperature = <110000>; 5701 hysteresis = <1000>; 5702 type = "critical"; 5703 }; 5704 }; 5705 5706 cooling-maps { 5707 map0 { 5708 trip = <&cpu0_alert0>; 5709 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5710 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5711 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5712 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5713 }; 5714 map1 { 5715 trip = <&cpu0_alert1>; 5716 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5717 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5718 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5719 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5720 }; 5721 }; 5722 }; 5723 5724 cpu1-thermal { 5725 polling-delay-passive = <250>; 5726 polling-delay = <1000>; 5727 5728 thermal-sensors = <&tsens0 2>; 5729 5730 trips { 5731 cpu1_alert0: trip-point0 { 5732 temperature = <90000>; 5733 hysteresis = <2000>; 5734 type = "passive"; 5735 }; 5736 5737 cpu1_alert1: trip-point1 { 5738 temperature = <95000>; 5739 hysteresis = <2000>; 5740 type = "passive"; 5741 }; 5742 5743 cpu1_crit: cpu-crit { 5744 temperature = <110000>; 5745 hysteresis = <1000>; 5746 type = "critical"; 5747 }; 5748 }; 5749 5750 cooling-maps { 5751 map0 { 5752 trip = <&cpu1_alert0>; 5753 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5754 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5755 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5756 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5757 }; 5758 map1 { 5759 trip = <&cpu1_alert1>; 5760 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5761 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5762 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5763 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5764 }; 5765 }; 5766 }; 5767 5768 cpu2-thermal { 5769 polling-delay-passive = <250>; 5770 polling-delay = <1000>; 5771 5772 thermal-sensors = <&tsens0 3>; 5773 5774 trips { 5775 cpu2_alert0: trip-point0 { 5776 temperature = <90000>; 5777 hysteresis = <2000>; 5778 type = "passive"; 5779 }; 5780 5781 cpu2_alert1: trip-point1 { 5782 temperature = <95000>; 5783 hysteresis = <2000>; 5784 type = "passive"; 5785 }; 5786 5787 cpu2_crit: cpu-crit { 5788 temperature = <110000>; 5789 hysteresis = <1000>; 5790 type = "critical"; 5791 }; 5792 }; 5793 5794 cooling-maps { 5795 map0 { 5796 trip = <&cpu2_alert0>; 5797 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5798 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5799 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5800 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5801 }; 5802 map1 { 5803 trip = <&cpu2_alert1>; 5804 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5805 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5806 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5807 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5808 }; 5809 }; 5810 }; 5811 5812 cpu3-thermal { 5813 polling-delay-passive = <250>; 5814 polling-delay = <1000>; 5815 5816 thermal-sensors = <&tsens0 4>; 5817 5818 trips { 5819 cpu3_alert0: trip-point0 { 5820 temperature = <90000>; 5821 hysteresis = <2000>; 5822 type = "passive"; 5823 }; 5824 5825 cpu3_alert1: trip-point1 { 5826 temperature = <95000>; 5827 hysteresis = <2000>; 5828 type = "passive"; 5829 }; 5830 5831 cpu3_crit: cpu-crit { 5832 temperature = <110000>; 5833 hysteresis = <1000>; 5834 type = "critical"; 5835 }; 5836 }; 5837 5838 cooling-maps { 5839 map0 { 5840 trip = <&cpu3_alert0>; 5841 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5842 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5843 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5844 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5845 }; 5846 map1 { 5847 trip = <&cpu3_alert1>; 5848 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5849 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5850 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5851 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5852 }; 5853 }; 5854 }; 5855 5856 cpu4-top-thermal { 5857 polling-delay-passive = <250>; 5858 polling-delay = <1000>; 5859 5860 thermal-sensors = <&tsens0 7>; 5861 5862 trips { 5863 cpu4_top_alert0: trip-point0 { 5864 temperature = <90000>; 5865 hysteresis = <2000>; 5866 type = "passive"; 5867 }; 5868 5869 cpu4_top_alert1: trip-point1 { 5870 temperature = <95000>; 5871 hysteresis = <2000>; 5872 type = "passive"; 5873 }; 5874 5875 cpu4_top_crit: cpu-crit { 5876 temperature = <110000>; 5877 hysteresis = <1000>; 5878 type = "critical"; 5879 }; 5880 }; 5881 5882 cooling-maps { 5883 map0 { 5884 trip = <&cpu4_top_alert0>; 5885 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5886 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5887 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5888 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5889 }; 5890 map1 { 5891 trip = <&cpu4_top_alert1>; 5892 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5893 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5894 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5895 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5896 }; 5897 }; 5898 }; 5899 5900 cpu5-top-thermal { 5901 polling-delay-passive = <250>; 5902 polling-delay = <1000>; 5903 5904 thermal-sensors = <&tsens0 8>; 5905 5906 trips { 5907 cpu5_top_alert0: trip-point0 { 5908 temperature = <90000>; 5909 hysteresis = <2000>; 5910 type = "passive"; 5911 }; 5912 5913 cpu5_top_alert1: trip-point1 { 5914 temperature = <95000>; 5915 hysteresis = <2000>; 5916 type = "passive"; 5917 }; 5918 5919 cpu5_top_crit: cpu-crit { 5920 temperature = <110000>; 5921 hysteresis = <1000>; 5922 type = "critical"; 5923 }; 5924 }; 5925 5926 cooling-maps { 5927 map0 { 5928 trip = <&cpu5_top_alert0>; 5929 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5930 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5931 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5932 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5933 }; 5934 map1 { 5935 trip = <&cpu5_top_alert1>; 5936 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5937 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5938 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5939 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5940 }; 5941 }; 5942 }; 5943 5944 cpu6-top-thermal { 5945 polling-delay-passive = <250>; 5946 polling-delay = <1000>; 5947 5948 thermal-sensors = <&tsens0 9>; 5949 5950 trips { 5951 cpu6_top_alert0: trip-point0 { 5952 temperature = <90000>; 5953 hysteresis = <2000>; 5954 type = "passive"; 5955 }; 5956 5957 cpu6_top_alert1: trip-point1 { 5958 temperature = <95000>; 5959 hysteresis = <2000>; 5960 type = "passive"; 5961 }; 5962 5963 cpu6_top_crit: cpu-crit { 5964 temperature = <110000>; 5965 hysteresis = <1000>; 5966 type = "critical"; 5967 }; 5968 }; 5969 5970 cooling-maps { 5971 map0 { 5972 trip = <&cpu6_top_alert0>; 5973 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5974 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5975 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5976 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5977 }; 5978 map1 { 5979 trip = <&cpu6_top_alert1>; 5980 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5981 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5982 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5983 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5984 }; 5985 }; 5986 }; 5987 5988 cpu7-top-thermal { 5989 polling-delay-passive = <250>; 5990 polling-delay = <1000>; 5991 5992 thermal-sensors = <&tsens0 10>; 5993 5994 trips { 5995 cpu7_top_alert0: trip-point0 { 5996 temperature = <90000>; 5997 hysteresis = <2000>; 5998 type = "passive"; 5999 }; 6000 6001 cpu7_top_alert1: trip-point1 { 6002 temperature = <95000>; 6003 hysteresis = <2000>; 6004 type = "passive"; 6005 }; 6006 6007 cpu7_top_crit: cpu-crit { 6008 temperature = <110000>; 6009 hysteresis = <1000>; 6010 type = "critical"; 6011 }; 6012 }; 6013 6014 cooling-maps { 6015 map0 { 6016 trip = <&cpu7_top_alert0>; 6017 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6018 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6019 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6020 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6021 }; 6022 map1 { 6023 trip = <&cpu7_top_alert1>; 6024 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6025 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6026 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6027 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6028 }; 6029 }; 6030 }; 6031 6032 cpu4-bottom-thermal { 6033 polling-delay-passive = <250>; 6034 polling-delay = <1000>; 6035 6036 thermal-sensors = <&tsens0 11>; 6037 6038 trips { 6039 cpu4_bottom_alert0: trip-point0 { 6040 temperature = <90000>; 6041 hysteresis = <2000>; 6042 type = "passive"; 6043 }; 6044 6045 cpu4_bottom_alert1: trip-point1 { 6046 temperature = <95000>; 6047 hysteresis = <2000>; 6048 type = "passive"; 6049 }; 6050 6051 cpu4_bottom_crit: cpu-crit { 6052 temperature = <110000>; 6053 hysteresis = <1000>; 6054 type = "critical"; 6055 }; 6056 }; 6057 6058 cooling-maps { 6059 map0 { 6060 trip = <&cpu4_bottom_alert0>; 6061 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6062 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6063 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6064 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6065 }; 6066 map1 { 6067 trip = <&cpu4_bottom_alert1>; 6068 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6069 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6070 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6071 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6072 }; 6073 }; 6074 }; 6075 6076 cpu5-bottom-thermal { 6077 polling-delay-passive = <250>; 6078 polling-delay = <1000>; 6079 6080 thermal-sensors = <&tsens0 12>; 6081 6082 trips { 6083 cpu5_bottom_alert0: trip-point0 { 6084 temperature = <90000>; 6085 hysteresis = <2000>; 6086 type = "passive"; 6087 }; 6088 6089 cpu5_bottom_alert1: trip-point1 { 6090 temperature = <95000>; 6091 hysteresis = <2000>; 6092 type = "passive"; 6093 }; 6094 6095 cpu5_bottom_crit: cpu-crit { 6096 temperature = <110000>; 6097 hysteresis = <1000>; 6098 type = "critical"; 6099 }; 6100 }; 6101 6102 cooling-maps { 6103 map0 { 6104 trip = <&cpu5_bottom_alert0>; 6105 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6106 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6107 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6108 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6109 }; 6110 map1 { 6111 trip = <&cpu5_bottom_alert1>; 6112 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6113 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6114 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6115 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6116 }; 6117 }; 6118 }; 6119 6120 cpu6-bottom-thermal { 6121 polling-delay-passive = <250>; 6122 polling-delay = <1000>; 6123 6124 thermal-sensors = <&tsens0 13>; 6125 6126 trips { 6127 cpu6_bottom_alert0: trip-point0 { 6128 temperature = <90000>; 6129 hysteresis = <2000>; 6130 type = "passive"; 6131 }; 6132 6133 cpu6_bottom_alert1: trip-point1 { 6134 temperature = <95000>; 6135 hysteresis = <2000>; 6136 type = "passive"; 6137 }; 6138 6139 cpu6_bottom_crit: cpu-crit { 6140 temperature = <110000>; 6141 hysteresis = <1000>; 6142 type = "critical"; 6143 }; 6144 }; 6145 6146 cooling-maps { 6147 map0 { 6148 trip = <&cpu6_bottom_alert0>; 6149 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6150 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6151 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6152 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6153 }; 6154 map1 { 6155 trip = <&cpu6_bottom_alert1>; 6156 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6157 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6158 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6159 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6160 }; 6161 }; 6162 }; 6163 6164 cpu7-bottom-thermal { 6165 polling-delay-passive = <250>; 6166 polling-delay = <1000>; 6167 6168 thermal-sensors = <&tsens0 14>; 6169 6170 trips { 6171 cpu7_bottom_alert0: trip-point0 { 6172 temperature = <90000>; 6173 hysteresis = <2000>; 6174 type = "passive"; 6175 }; 6176 6177 cpu7_bottom_alert1: trip-point1 { 6178 temperature = <95000>; 6179 hysteresis = <2000>; 6180 type = "passive"; 6181 }; 6182 6183 cpu7_bottom_crit: cpu-crit { 6184 temperature = <110000>; 6185 hysteresis = <1000>; 6186 type = "critical"; 6187 }; 6188 }; 6189 6190 cooling-maps { 6191 map0 { 6192 trip = <&cpu7_bottom_alert0>; 6193 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6194 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6195 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6196 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6197 }; 6198 map1 { 6199 trip = <&cpu7_bottom_alert1>; 6200 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6201 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6202 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6203 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6204 }; 6205 }; 6206 }; 6207 6208 aoss0-thermal { 6209 polling-delay-passive = <250>; 6210 polling-delay = <1000>; 6211 6212 thermal-sensors = <&tsens0 0>; 6213 6214 trips { 6215 aoss0_alert0: trip-point0 { 6216 temperature = <90000>; 6217 hysteresis = <2000>; 6218 type = "hot"; 6219 }; 6220 }; 6221 }; 6222 6223 cluster0-thermal { 6224 polling-delay-passive = <250>; 6225 polling-delay = <1000>; 6226 6227 thermal-sensors = <&tsens0 5>; 6228 6229 trips { 6230 cluster0_alert0: trip-point0 { 6231 temperature = <90000>; 6232 hysteresis = <2000>; 6233 type = "hot"; 6234 }; 6235 cluster0_crit: cluster0_crit { 6236 temperature = <110000>; 6237 hysteresis = <2000>; 6238 type = "critical"; 6239 }; 6240 }; 6241 }; 6242 6243 cluster1-thermal { 6244 polling-delay-passive = <250>; 6245 polling-delay = <1000>; 6246 6247 thermal-sensors = <&tsens0 6>; 6248 6249 trips { 6250 cluster1_alert0: trip-point0 { 6251 temperature = <90000>; 6252 hysteresis = <2000>; 6253 type = "hot"; 6254 }; 6255 cluster1_crit: cluster1_crit { 6256 temperature = <110000>; 6257 hysteresis = <2000>; 6258 type = "critical"; 6259 }; 6260 }; 6261 }; 6262 6263 gpu-top-thermal { 6264 polling-delay-passive = <250>; 6265 polling-delay = <1000>; 6266 6267 thermal-sensors = <&tsens0 15>; 6268 6269 trips { 6270 gpu1_alert0: trip-point0 { 6271 temperature = <90000>; 6272 hysteresis = <2000>; 6273 type = "hot"; 6274 }; 6275 }; 6276 }; 6277 6278 aoss1-thermal { 6279 polling-delay-passive = <250>; 6280 polling-delay = <1000>; 6281 6282 thermal-sensors = <&tsens1 0>; 6283 6284 trips { 6285 aoss1_alert0: trip-point0 { 6286 temperature = <90000>; 6287 hysteresis = <2000>; 6288 type = "hot"; 6289 }; 6290 }; 6291 }; 6292 6293 wlan-thermal { 6294 polling-delay-passive = <250>; 6295 polling-delay = <1000>; 6296 6297 thermal-sensors = <&tsens1 1>; 6298 6299 trips { 6300 wlan_alert0: trip-point0 { 6301 temperature = <90000>; 6302 hysteresis = <2000>; 6303 type = "hot"; 6304 }; 6305 }; 6306 }; 6307 6308 video-thermal { 6309 polling-delay-passive = <250>; 6310 polling-delay = <1000>; 6311 6312 thermal-sensors = <&tsens1 2>; 6313 6314 trips { 6315 video_alert0: trip-point0 { 6316 temperature = <90000>; 6317 hysteresis = <2000>; 6318 type = "hot"; 6319 }; 6320 }; 6321 }; 6322 6323 mem-thermal { 6324 polling-delay-passive = <250>; 6325 polling-delay = <1000>; 6326 6327 thermal-sensors = <&tsens1 3>; 6328 6329 trips { 6330 mem_alert0: trip-point0 { 6331 temperature = <90000>; 6332 hysteresis = <2000>; 6333 type = "hot"; 6334 }; 6335 }; 6336 }; 6337 6338 q6-hvx-thermal { 6339 polling-delay-passive = <250>; 6340 polling-delay = <1000>; 6341 6342 thermal-sensors = <&tsens1 4>; 6343 6344 trips { 6345 q6_hvx_alert0: trip-point0 { 6346 temperature = <90000>; 6347 hysteresis = <2000>; 6348 type = "hot"; 6349 }; 6350 }; 6351 }; 6352 6353 camera-thermal { 6354 polling-delay-passive = <250>; 6355 polling-delay = <1000>; 6356 6357 thermal-sensors = <&tsens1 5>; 6358 6359 trips { 6360 camera_alert0: trip-point0 { 6361 temperature = <90000>; 6362 hysteresis = <2000>; 6363 type = "hot"; 6364 }; 6365 }; 6366 }; 6367 6368 compute-thermal { 6369 polling-delay-passive = <250>; 6370 polling-delay = <1000>; 6371 6372 thermal-sensors = <&tsens1 6>; 6373 6374 trips { 6375 compute_alert0: trip-point0 { 6376 temperature = <90000>; 6377 hysteresis = <2000>; 6378 type = "hot"; 6379 }; 6380 }; 6381 }; 6382 6383 npu-thermal { 6384 polling-delay-passive = <250>; 6385 polling-delay = <1000>; 6386 6387 thermal-sensors = <&tsens1 7>; 6388 6389 trips { 6390 npu_alert0: trip-point0 { 6391 temperature = <90000>; 6392 hysteresis = <2000>; 6393 type = "hot"; 6394 }; 6395 }; 6396 }; 6397 6398 gpu-bottom-thermal { 6399 polling-delay-passive = <250>; 6400 polling-delay = <1000>; 6401 6402 thermal-sensors = <&tsens1 8>; 6403 6404 trips { 6405 gpu2_alert0: trip-point0 { 6406 temperature = <90000>; 6407 hysteresis = <2000>; 6408 type = "hot"; 6409 }; 6410 }; 6411 }; 6412 }; 6413}; 6414