1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sm8250.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/soc/qcom,apr.h> 18#include <dt-bindings/soc/qcom,rpmh-rsc.h> 19#include <dt-bindings/sound/qcom,q6afe.h> 20#include <dt-bindings/thermal/thermal.h> 21#include <dt-bindings/clock/qcom,videocc-sm8250.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 aliases { 30 i2c0 = &i2c0; 31 i2c1 = &i2c1; 32 i2c2 = &i2c2; 33 i2c3 = &i2c3; 34 i2c4 = &i2c4; 35 i2c5 = &i2c5; 36 i2c6 = &i2c6; 37 i2c7 = &i2c7; 38 i2c8 = &i2c8; 39 i2c9 = &i2c9; 40 i2c10 = &i2c10; 41 i2c11 = &i2c11; 42 i2c12 = &i2c12; 43 i2c13 = &i2c13; 44 i2c14 = &i2c14; 45 i2c15 = &i2c15; 46 i2c16 = &i2c16; 47 i2c17 = &i2c17; 48 i2c18 = &i2c18; 49 i2c19 = &i2c19; 50 spi0 = &spi0; 51 spi1 = &spi1; 52 spi2 = &spi2; 53 spi3 = &spi3; 54 spi4 = &spi4; 55 spi5 = &spi5; 56 spi6 = &spi6; 57 spi7 = &spi7; 58 spi8 = &spi8; 59 spi9 = &spi9; 60 spi10 = &spi10; 61 spi11 = &spi11; 62 spi12 = &spi12; 63 spi13 = &spi13; 64 spi14 = &spi14; 65 spi15 = &spi15; 66 spi16 = &spi16; 67 spi17 = &spi17; 68 spi18 = &spi18; 69 spi19 = &spi19; 70 }; 71 72 chosen { }; 73 74 clocks { 75 xo_board: xo-board { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <38400000>; 79 clock-output-names = "xo_board"; 80 }; 81 82 sleep_clk: sleep-clk { 83 compatible = "fixed-clock"; 84 clock-frequency = <32768>; 85 #clock-cells = <0>; 86 }; 87 }; 88 89 cpus { 90 #address-cells = <2>; 91 #size-cells = <0>; 92 93 CPU0: cpu@0 { 94 device_type = "cpu"; 95 compatible = "qcom,kryo485"; 96 reg = <0x0 0x0>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <448>; 99 dynamic-power-coefficient = <205>; 100 next-level-cache = <&L2_0>; 101 qcom,freq-domain = <&cpufreq_hw 0>; 102 #cooling-cells = <2>; 103 L2_0: l2-cache { 104 compatible = "cache"; 105 next-level-cache = <&L3_0>; 106 L3_0: l3-cache { 107 compatible = "cache"; 108 }; 109 }; 110 }; 111 112 CPU1: cpu@100 { 113 device_type = "cpu"; 114 compatible = "qcom,kryo485"; 115 reg = <0x0 0x100>; 116 enable-method = "psci"; 117 capacity-dmips-mhz = <448>; 118 dynamic-power-coefficient = <205>; 119 next-level-cache = <&L2_100>; 120 qcom,freq-domain = <&cpufreq_hw 0>; 121 #cooling-cells = <2>; 122 L2_100: l2-cache { 123 compatible = "cache"; 124 next-level-cache = <&L3_0>; 125 }; 126 }; 127 128 CPU2: cpu@200 { 129 device_type = "cpu"; 130 compatible = "qcom,kryo485"; 131 reg = <0x0 0x200>; 132 enable-method = "psci"; 133 capacity-dmips-mhz = <448>; 134 dynamic-power-coefficient = <205>; 135 next-level-cache = <&L2_200>; 136 qcom,freq-domain = <&cpufreq_hw 0>; 137 #cooling-cells = <2>; 138 L2_200: l2-cache { 139 compatible = "cache"; 140 next-level-cache = <&L3_0>; 141 }; 142 }; 143 144 CPU3: cpu@300 { 145 device_type = "cpu"; 146 compatible = "qcom,kryo485"; 147 reg = <0x0 0x300>; 148 enable-method = "psci"; 149 capacity-dmips-mhz = <448>; 150 dynamic-power-coefficient = <205>; 151 next-level-cache = <&L2_300>; 152 qcom,freq-domain = <&cpufreq_hw 0>; 153 #cooling-cells = <2>; 154 L2_300: l2-cache { 155 compatible = "cache"; 156 next-level-cache = <&L3_0>; 157 }; 158 }; 159 160 CPU4: cpu@400 { 161 device_type = "cpu"; 162 compatible = "qcom,kryo485"; 163 reg = <0x0 0x400>; 164 enable-method = "psci"; 165 capacity-dmips-mhz = <1024>; 166 dynamic-power-coefficient = <379>; 167 next-level-cache = <&L2_400>; 168 qcom,freq-domain = <&cpufreq_hw 1>; 169 #cooling-cells = <2>; 170 L2_400: l2-cache { 171 compatible = "cache"; 172 next-level-cache = <&L3_0>; 173 }; 174 }; 175 176 CPU5: cpu@500 { 177 device_type = "cpu"; 178 compatible = "qcom,kryo485"; 179 reg = <0x0 0x500>; 180 enable-method = "psci"; 181 capacity-dmips-mhz = <1024>; 182 dynamic-power-coefficient = <379>; 183 next-level-cache = <&L2_500>; 184 qcom,freq-domain = <&cpufreq_hw 1>; 185 #cooling-cells = <2>; 186 L2_500: l2-cache { 187 compatible = "cache"; 188 next-level-cache = <&L3_0>; 189 }; 190 191 }; 192 193 CPU6: cpu@600 { 194 device_type = "cpu"; 195 compatible = "qcom,kryo485"; 196 reg = <0x0 0x600>; 197 enable-method = "psci"; 198 capacity-dmips-mhz = <1024>; 199 dynamic-power-coefficient = <379>; 200 next-level-cache = <&L2_600>; 201 qcom,freq-domain = <&cpufreq_hw 1>; 202 #cooling-cells = <2>; 203 L2_600: l2-cache { 204 compatible = "cache"; 205 next-level-cache = <&L3_0>; 206 }; 207 }; 208 209 CPU7: cpu@700 { 210 device_type = "cpu"; 211 compatible = "qcom,kryo485"; 212 reg = <0x0 0x700>; 213 enable-method = "psci"; 214 capacity-dmips-mhz = <1024>; 215 dynamic-power-coefficient = <444>; 216 next-level-cache = <&L2_700>; 217 qcom,freq-domain = <&cpufreq_hw 2>; 218 #cooling-cells = <2>; 219 L2_700: l2-cache { 220 compatible = "cache"; 221 next-level-cache = <&L3_0>; 222 }; 223 }; 224 225 cpu-map { 226 cluster0 { 227 core0 { 228 cpu = <&CPU0>; 229 }; 230 231 core1 { 232 cpu = <&CPU1>; 233 }; 234 235 core2 { 236 cpu = <&CPU2>; 237 }; 238 239 core3 { 240 cpu = <&CPU3>; 241 }; 242 243 core4 { 244 cpu = <&CPU4>; 245 }; 246 247 core5 { 248 cpu = <&CPU5>; 249 }; 250 251 core6 { 252 cpu = <&CPU6>; 253 }; 254 255 core7 { 256 cpu = <&CPU7>; 257 }; 258 }; 259 }; 260 }; 261 262 firmware { 263 scm: scm { 264 compatible = "qcom,scm"; 265 #reset-cells = <1>; 266 }; 267 }; 268 269 memory@80000000 { 270 device_type = "memory"; 271 /* We expect the bootloader to fill in the size */ 272 reg = <0x0 0x80000000 0x0 0x0>; 273 }; 274 275 pmu { 276 compatible = "arm,armv8-pmuv3"; 277 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 278 }; 279 280 psci { 281 compatible = "arm,psci-1.0"; 282 method = "smc"; 283 }; 284 285 reserved-memory { 286 #address-cells = <2>; 287 #size-cells = <2>; 288 ranges; 289 290 hyp_mem: memory@80000000 { 291 reg = <0x0 0x80000000 0x0 0x600000>; 292 no-map; 293 }; 294 295 xbl_aop_mem: memory@80700000 { 296 reg = <0x0 0x80700000 0x0 0x160000>; 297 no-map; 298 }; 299 300 cmd_db: memory@80860000 { 301 compatible = "qcom,cmd-db"; 302 reg = <0x0 0x80860000 0x0 0x20000>; 303 no-map; 304 }; 305 306 smem_mem: memory@80900000 { 307 reg = <0x0 0x80900000 0x0 0x200000>; 308 no-map; 309 }; 310 311 removed_mem: memory@80b00000 { 312 reg = <0x0 0x80b00000 0x0 0x5300000>; 313 no-map; 314 }; 315 316 camera_mem: memory@86200000 { 317 reg = <0x0 0x86200000 0x0 0x500000>; 318 no-map; 319 }; 320 321 wlan_mem: memory@86700000 { 322 reg = <0x0 0x86700000 0x0 0x100000>; 323 no-map; 324 }; 325 326 ipa_fw_mem: memory@86800000 { 327 reg = <0x0 0x86800000 0x0 0x10000>; 328 no-map; 329 }; 330 331 ipa_gsi_mem: memory@86810000 { 332 reg = <0x0 0x86810000 0x0 0xa000>; 333 no-map; 334 }; 335 336 gpu_mem: memory@8681a000 { 337 reg = <0x0 0x8681a000 0x0 0x2000>; 338 no-map; 339 }; 340 341 npu_mem: memory@86900000 { 342 reg = <0x0 0x86900000 0x0 0x500000>; 343 no-map; 344 }; 345 346 video_mem: memory@86e00000 { 347 reg = <0x0 0x86e00000 0x0 0x500000>; 348 no-map; 349 }; 350 351 cvp_mem: memory@87300000 { 352 reg = <0x0 0x87300000 0x0 0x500000>; 353 no-map; 354 }; 355 356 cdsp_mem: memory@87800000 { 357 reg = <0x0 0x87800000 0x0 0x1400000>; 358 no-map; 359 }; 360 361 slpi_mem: memory@88c00000 { 362 reg = <0x0 0x88c00000 0x0 0x1500000>; 363 no-map; 364 }; 365 366 adsp_mem: memory@8a100000 { 367 reg = <0x0 0x8a100000 0x0 0x1d00000>; 368 no-map; 369 }; 370 371 spss_mem: memory@8be00000 { 372 reg = <0x0 0x8be00000 0x0 0x100000>; 373 no-map; 374 }; 375 376 cdsp_secure_heap: memory@8bf00000 { 377 reg = <0x0 0x8bf00000 0x0 0x4600000>; 378 no-map; 379 }; 380 }; 381 382 smem { 383 compatible = "qcom,smem"; 384 memory-region = <&smem_mem>; 385 hwlocks = <&tcsr_mutex 3>; 386 }; 387 388 smp2p-adsp { 389 compatible = "qcom,smp2p"; 390 qcom,smem = <443>, <429>; 391 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 392 IPCC_MPROC_SIGNAL_SMP2P 393 IRQ_TYPE_EDGE_RISING>; 394 mboxes = <&ipcc IPCC_CLIENT_LPASS 395 IPCC_MPROC_SIGNAL_SMP2P>; 396 397 qcom,local-pid = <0>; 398 qcom,remote-pid = <2>; 399 400 smp2p_adsp_out: master-kernel { 401 qcom,entry-name = "master-kernel"; 402 #qcom,smem-state-cells = <1>; 403 }; 404 405 smp2p_adsp_in: slave-kernel { 406 qcom,entry-name = "slave-kernel"; 407 interrupt-controller; 408 #interrupt-cells = <2>; 409 }; 410 }; 411 412 smp2p-cdsp { 413 compatible = "qcom,smp2p"; 414 qcom,smem = <94>, <432>; 415 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 416 IPCC_MPROC_SIGNAL_SMP2P 417 IRQ_TYPE_EDGE_RISING>; 418 mboxes = <&ipcc IPCC_CLIENT_CDSP 419 IPCC_MPROC_SIGNAL_SMP2P>; 420 421 qcom,local-pid = <0>; 422 qcom,remote-pid = <5>; 423 424 smp2p_cdsp_out: master-kernel { 425 qcom,entry-name = "master-kernel"; 426 #qcom,smem-state-cells = <1>; 427 }; 428 429 smp2p_cdsp_in: slave-kernel { 430 qcom,entry-name = "slave-kernel"; 431 interrupt-controller; 432 #interrupt-cells = <2>; 433 }; 434 }; 435 436 smp2p-slpi { 437 compatible = "qcom,smp2p"; 438 qcom,smem = <481>, <430>; 439 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 440 IPCC_MPROC_SIGNAL_SMP2P 441 IRQ_TYPE_EDGE_RISING>; 442 mboxes = <&ipcc IPCC_CLIENT_SLPI 443 IPCC_MPROC_SIGNAL_SMP2P>; 444 445 qcom,local-pid = <0>; 446 qcom,remote-pid = <3>; 447 448 smp2p_slpi_out: master-kernel { 449 qcom,entry-name = "master-kernel"; 450 #qcom,smem-state-cells = <1>; 451 }; 452 453 smp2p_slpi_in: slave-kernel { 454 qcom,entry-name = "slave-kernel"; 455 interrupt-controller; 456 #interrupt-cells = <2>; 457 }; 458 }; 459 460 soc: soc@0 { 461 #address-cells = <2>; 462 #size-cells = <2>; 463 ranges = <0 0 0 0 0x10 0>; 464 dma-ranges = <0 0 0 0 0x10 0>; 465 compatible = "simple-bus"; 466 467 gcc: clock-controller@100000 { 468 compatible = "qcom,gcc-sm8250"; 469 reg = <0x0 0x00100000 0x0 0x1f0000>; 470 #clock-cells = <1>; 471 #reset-cells = <1>; 472 #power-domain-cells = <1>; 473 clock-names = "bi_tcxo", 474 "bi_tcxo_ao", 475 "sleep_clk"; 476 clocks = <&rpmhcc RPMH_CXO_CLK>, 477 <&rpmhcc RPMH_CXO_CLK_A>, 478 <&sleep_clk>; 479 }; 480 481 ipcc: mailbox@408000 { 482 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 483 reg = <0 0x00408000 0 0x1000>; 484 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 485 interrupt-controller; 486 #interrupt-cells = <3>; 487 #mbox-cells = <2>; 488 }; 489 490 rng: rng@793000 { 491 compatible = "qcom,prng-ee"; 492 reg = <0 0x00793000 0 0x1000>; 493 clocks = <&gcc GCC_PRNG_AHB_CLK>; 494 clock-names = "core"; 495 }; 496 497 qup_opp_table: qup-opp-table { 498 compatible = "operating-points-v2"; 499 500 opp-50000000 { 501 opp-hz = /bits/ 64 <50000000>; 502 required-opps = <&rpmhpd_opp_min_svs>; 503 }; 504 505 opp-75000000 { 506 opp-hz = /bits/ 64 <75000000>; 507 required-opps = <&rpmhpd_opp_low_svs>; 508 }; 509 510 opp-120000000 { 511 opp-hz = /bits/ 64 <120000000>; 512 required-opps = <&rpmhpd_opp_svs>; 513 }; 514 }; 515 516 gpi_dma2: dma-controller@800000 { 517 compatible = "qcom,sm8250-gpi-dma"; 518 reg = <0 0x00800000 0 0x70000>; 519 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 529 dma-channels = <10>; 530 dma-channel-mask = <0x3f>; 531 iommus = <&apps_smmu 0x76 0x0>; 532 #dma-cells = <3>; 533 status = "disabled"; 534 }; 535 536 qupv3_id_2: geniqup@8c0000 { 537 compatible = "qcom,geni-se-qup"; 538 reg = <0x0 0x008c0000 0x0 0x6000>; 539 clock-names = "m-ahb", "s-ahb"; 540 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 541 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 542 #address-cells = <2>; 543 #size-cells = <2>; 544 iommus = <&apps_smmu 0x63 0x0>; 545 ranges; 546 status = "disabled"; 547 548 i2c14: i2c@880000 { 549 compatible = "qcom,geni-i2c"; 550 reg = <0 0x00880000 0 0x4000>; 551 clock-names = "se"; 552 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 553 pinctrl-names = "default"; 554 pinctrl-0 = <&qup_i2c14_default>; 555 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 556 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 557 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 558 dma-names = "tx", "rx"; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 status = "disabled"; 562 }; 563 564 spi14: spi@880000 { 565 compatible = "qcom,geni-spi"; 566 reg = <0 0x00880000 0 0x4000>; 567 clock-names = "se"; 568 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 569 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 570 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 571 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 572 dma-names = "tx", "rx"; 573 power-domains = <&rpmhpd SM8250_CX>; 574 operating-points-v2 = <&qup_opp_table>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 status = "disabled"; 578 }; 579 580 i2c15: i2c@884000 { 581 compatible = "qcom,geni-i2c"; 582 reg = <0 0x00884000 0 0x4000>; 583 clock-names = "se"; 584 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 585 pinctrl-names = "default"; 586 pinctrl-0 = <&qup_i2c15_default>; 587 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 588 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 589 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 590 dma-names = "tx", "rx"; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 status = "disabled"; 594 }; 595 596 spi15: spi@884000 { 597 compatible = "qcom,geni-spi"; 598 reg = <0 0x00884000 0 0x4000>; 599 clock-names = "se"; 600 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 601 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 602 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 603 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 604 dma-names = "tx", "rx"; 605 power-domains = <&rpmhpd SM8250_CX>; 606 operating-points-v2 = <&qup_opp_table>; 607 #address-cells = <1>; 608 #size-cells = <0>; 609 status = "disabled"; 610 }; 611 612 i2c16: i2c@888000 { 613 compatible = "qcom,geni-i2c"; 614 reg = <0 0x00888000 0 0x4000>; 615 clock-names = "se"; 616 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 617 pinctrl-names = "default"; 618 pinctrl-0 = <&qup_i2c16_default>; 619 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 620 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 621 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 622 dma-names = "tx", "rx"; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 status = "disabled"; 626 }; 627 628 spi16: spi@888000 { 629 compatible = "qcom,geni-spi"; 630 reg = <0 0x00888000 0 0x4000>; 631 clock-names = "se"; 632 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 633 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 634 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 635 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 636 dma-names = "tx", "rx"; 637 power-domains = <&rpmhpd SM8250_CX>; 638 operating-points-v2 = <&qup_opp_table>; 639 #address-cells = <1>; 640 #size-cells = <0>; 641 status = "disabled"; 642 }; 643 644 i2c17: i2c@88c000 { 645 compatible = "qcom,geni-i2c"; 646 reg = <0 0x0088c000 0 0x4000>; 647 clock-names = "se"; 648 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 649 pinctrl-names = "default"; 650 pinctrl-0 = <&qup_i2c17_default>; 651 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 652 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 653 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 654 dma-names = "tx", "rx"; 655 #address-cells = <1>; 656 #size-cells = <0>; 657 status = "disabled"; 658 }; 659 660 spi17: spi@88c000 { 661 compatible = "qcom,geni-spi"; 662 reg = <0 0x0088c000 0 0x4000>; 663 clock-names = "se"; 664 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 665 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 666 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 667 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 668 dma-names = "tx", "rx"; 669 power-domains = <&rpmhpd SM8250_CX>; 670 operating-points-v2 = <&qup_opp_table>; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 status = "disabled"; 674 }; 675 676 uart17: serial@88c000 { 677 compatible = "qcom,geni-uart"; 678 reg = <0 0x0088c000 0 0x4000>; 679 clock-names = "se"; 680 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&qup_uart17_default>; 683 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 684 power-domains = <&rpmhpd SM8250_CX>; 685 operating-points-v2 = <&qup_opp_table>; 686 status = "disabled"; 687 }; 688 689 i2c18: i2c@890000 { 690 compatible = "qcom,geni-i2c"; 691 reg = <0 0x00890000 0 0x4000>; 692 clock-names = "se"; 693 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 694 pinctrl-names = "default"; 695 pinctrl-0 = <&qup_i2c18_default>; 696 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 697 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 698 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 699 dma-names = "tx", "rx"; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 status = "disabled"; 703 }; 704 705 spi18: spi@890000 { 706 compatible = "qcom,geni-spi"; 707 reg = <0 0x00890000 0 0x4000>; 708 clock-names = "se"; 709 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 710 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 711 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 712 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 713 dma-names = "tx", "rx"; 714 power-domains = <&rpmhpd SM8250_CX>; 715 operating-points-v2 = <&qup_opp_table>; 716 #address-cells = <1>; 717 #size-cells = <0>; 718 status = "disabled"; 719 }; 720 721 uart18: serial@890000 { 722 compatible = "qcom,geni-uart"; 723 reg = <0 0x00890000 0 0x4000>; 724 clock-names = "se"; 725 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 726 pinctrl-names = "default"; 727 pinctrl-0 = <&qup_uart18_default>; 728 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 729 power-domains = <&rpmhpd SM8250_CX>; 730 operating-points-v2 = <&qup_opp_table>; 731 status = "disabled"; 732 }; 733 734 i2c19: i2c@894000 { 735 compatible = "qcom,geni-i2c"; 736 reg = <0 0x00894000 0 0x4000>; 737 clock-names = "se"; 738 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 739 pinctrl-names = "default"; 740 pinctrl-0 = <&qup_i2c19_default>; 741 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 742 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 743 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 744 dma-names = "tx", "rx"; 745 #address-cells = <1>; 746 #size-cells = <0>; 747 status = "disabled"; 748 }; 749 750 spi19: spi@894000 { 751 compatible = "qcom,geni-spi"; 752 reg = <0 0x00894000 0 0x4000>; 753 clock-names = "se"; 754 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 755 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 756 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 757 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 758 dma-names = "tx", "rx"; 759 power-domains = <&rpmhpd SM8250_CX>; 760 operating-points-v2 = <&qup_opp_table>; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 status = "disabled"; 764 }; 765 }; 766 767 gpi_dma0: dma-controller@900000 { 768 compatible = "qcom,sm8250-gpi-dma"; 769 reg = <0 0x00900000 0 0x70000>; 770 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 783 dma-channels = <15>; 784 dma-channel-mask = <0x7ff>; 785 iommus = <&apps_smmu 0x5b6 0x0>; 786 #dma-cells = <3>; 787 status = "disabled"; 788 }; 789 790 qupv3_id_0: geniqup@9c0000 { 791 compatible = "qcom,geni-se-qup"; 792 reg = <0x0 0x009c0000 0x0 0x6000>; 793 clock-names = "m-ahb", "s-ahb"; 794 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 795 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 796 #address-cells = <2>; 797 #size-cells = <2>; 798 iommus = <&apps_smmu 0x5a3 0x0>; 799 ranges; 800 status = "disabled"; 801 802 i2c0: i2c@980000 { 803 compatible = "qcom,geni-i2c"; 804 reg = <0 0x00980000 0 0x4000>; 805 clock-names = "se"; 806 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 807 pinctrl-names = "default"; 808 pinctrl-0 = <&qup_i2c0_default>; 809 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 810 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 811 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 812 dma-names = "tx", "rx"; 813 #address-cells = <1>; 814 #size-cells = <0>; 815 status = "disabled"; 816 }; 817 818 spi0: spi@980000 { 819 compatible = "qcom,geni-spi"; 820 reg = <0 0x00980000 0 0x4000>; 821 clock-names = "se"; 822 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 823 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 824 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 825 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 826 dma-names = "tx", "rx"; 827 power-domains = <&rpmhpd SM8250_CX>; 828 operating-points-v2 = <&qup_opp_table>; 829 #address-cells = <1>; 830 #size-cells = <0>; 831 status = "disabled"; 832 }; 833 834 i2c1: i2c@984000 { 835 compatible = "qcom,geni-i2c"; 836 reg = <0 0x00984000 0 0x4000>; 837 clock-names = "se"; 838 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 839 pinctrl-names = "default"; 840 pinctrl-0 = <&qup_i2c1_default>; 841 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 842 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 843 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 844 dma-names = "tx", "rx"; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 status = "disabled"; 848 }; 849 850 spi1: spi@984000 { 851 compatible = "qcom,geni-spi"; 852 reg = <0 0x00984000 0 0x4000>; 853 clock-names = "se"; 854 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 855 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 856 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 857 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 858 dma-names = "tx", "rx"; 859 power-domains = <&rpmhpd SM8250_CX>; 860 operating-points-v2 = <&qup_opp_table>; 861 #address-cells = <1>; 862 #size-cells = <0>; 863 status = "disabled"; 864 }; 865 866 i2c2: i2c@988000 { 867 compatible = "qcom,geni-i2c"; 868 reg = <0 0x00988000 0 0x4000>; 869 clock-names = "se"; 870 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 871 pinctrl-names = "default"; 872 pinctrl-0 = <&qup_i2c2_default>; 873 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 874 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 875 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 876 dma-names = "tx", "rx"; 877 #address-cells = <1>; 878 #size-cells = <0>; 879 status = "disabled"; 880 }; 881 882 spi2: spi@988000 { 883 compatible = "qcom,geni-spi"; 884 reg = <0 0x00988000 0 0x4000>; 885 clock-names = "se"; 886 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 887 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 888 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 889 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 890 dma-names = "tx", "rx"; 891 power-domains = <&rpmhpd SM8250_CX>; 892 operating-points-v2 = <&qup_opp_table>; 893 #address-cells = <1>; 894 #size-cells = <0>; 895 status = "disabled"; 896 }; 897 898 uart2: serial@988000 { 899 compatible = "qcom,geni-debug-uart"; 900 reg = <0 0x00988000 0 0x4000>; 901 clock-names = "se"; 902 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 903 pinctrl-names = "default"; 904 pinctrl-0 = <&qup_uart2_default>; 905 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 906 power-domains = <&rpmhpd SM8250_CX>; 907 operating-points-v2 = <&qup_opp_table>; 908 status = "disabled"; 909 }; 910 911 i2c3: i2c@98c000 { 912 compatible = "qcom,geni-i2c"; 913 reg = <0 0x0098c000 0 0x4000>; 914 clock-names = "se"; 915 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 916 pinctrl-names = "default"; 917 pinctrl-0 = <&qup_i2c3_default>; 918 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 919 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 920 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 921 dma-names = "tx", "rx"; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 status = "disabled"; 925 }; 926 927 spi3: spi@98c000 { 928 compatible = "qcom,geni-spi"; 929 reg = <0 0x0098c000 0 0x4000>; 930 clock-names = "se"; 931 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 932 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 933 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 934 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 935 dma-names = "tx", "rx"; 936 power-domains = <&rpmhpd SM8250_CX>; 937 operating-points-v2 = <&qup_opp_table>; 938 #address-cells = <1>; 939 #size-cells = <0>; 940 status = "disabled"; 941 }; 942 943 i2c4: i2c@990000 { 944 compatible = "qcom,geni-i2c"; 945 reg = <0 0x00990000 0 0x4000>; 946 clock-names = "se"; 947 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 948 pinctrl-names = "default"; 949 pinctrl-0 = <&qup_i2c4_default>; 950 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 951 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 952 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 953 dma-names = "tx", "rx"; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 status = "disabled"; 957 }; 958 959 spi4: spi@990000 { 960 compatible = "qcom,geni-spi"; 961 reg = <0 0x00990000 0 0x4000>; 962 clock-names = "se"; 963 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 964 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 965 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 966 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 967 dma-names = "tx", "rx"; 968 power-domains = <&rpmhpd SM8250_CX>; 969 operating-points-v2 = <&qup_opp_table>; 970 #address-cells = <1>; 971 #size-cells = <0>; 972 status = "disabled"; 973 }; 974 975 i2c5: i2c@994000 { 976 compatible = "qcom,geni-i2c"; 977 reg = <0 0x00994000 0 0x4000>; 978 clock-names = "se"; 979 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 980 pinctrl-names = "default"; 981 pinctrl-0 = <&qup_i2c5_default>; 982 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 983 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 984 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 985 dma-names = "tx", "rx"; 986 #address-cells = <1>; 987 #size-cells = <0>; 988 status = "disabled"; 989 }; 990 991 spi5: spi@994000 { 992 compatible = "qcom,geni-spi"; 993 reg = <0 0x00994000 0 0x4000>; 994 clock-names = "se"; 995 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 996 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 997 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 998 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 999 dma-names = "tx", "rx"; 1000 power-domains = <&rpmhpd SM8250_CX>; 1001 operating-points-v2 = <&qup_opp_table>; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 status = "disabled"; 1005 }; 1006 1007 i2c6: i2c@998000 { 1008 compatible = "qcom,geni-i2c"; 1009 reg = <0 0x00998000 0 0x4000>; 1010 clock-names = "se"; 1011 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1012 pinctrl-names = "default"; 1013 pinctrl-0 = <&qup_i2c6_default>; 1014 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1015 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1016 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1017 dma-names = "tx", "rx"; 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 status = "disabled"; 1021 }; 1022 1023 spi6: spi@998000 { 1024 compatible = "qcom,geni-spi"; 1025 reg = <0 0x00998000 0 0x4000>; 1026 clock-names = "se"; 1027 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1028 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1029 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1030 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1031 dma-names = "tx", "rx"; 1032 power-domains = <&rpmhpd SM8250_CX>; 1033 operating-points-v2 = <&qup_opp_table>; 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 status = "disabled"; 1037 }; 1038 1039 uart6: serial@998000 { 1040 compatible = "qcom,geni-uart"; 1041 reg = <0 0x00998000 0 0x4000>; 1042 clock-names = "se"; 1043 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1044 pinctrl-names = "default"; 1045 pinctrl-0 = <&qup_uart6_default>; 1046 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1047 power-domains = <&rpmhpd SM8250_CX>; 1048 operating-points-v2 = <&qup_opp_table>; 1049 status = "disabled"; 1050 }; 1051 1052 i2c7: i2c@99c000 { 1053 compatible = "qcom,geni-i2c"; 1054 reg = <0 0x0099c000 0 0x4000>; 1055 clock-names = "se"; 1056 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1057 pinctrl-names = "default"; 1058 pinctrl-0 = <&qup_i2c7_default>; 1059 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1060 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1061 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1062 dma-names = "tx", "rx"; 1063 #address-cells = <1>; 1064 #size-cells = <0>; 1065 status = "disabled"; 1066 }; 1067 1068 spi7: spi@99c000 { 1069 compatible = "qcom,geni-spi"; 1070 reg = <0 0x0099c000 0 0x4000>; 1071 clock-names = "se"; 1072 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1073 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1074 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1075 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1076 dma-names = "tx", "rx"; 1077 power-domains = <&rpmhpd SM8250_CX>; 1078 operating-points-v2 = <&qup_opp_table>; 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 status = "disabled"; 1082 }; 1083 }; 1084 1085 gpi_dma1: dma-controller@a00000 { 1086 compatible = "qcom,sm8250-gpi-dma"; 1087 reg = <0 0x00a00000 0 0x70000>; 1088 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1098 dma-channels = <10>; 1099 dma-channel-mask = <0x3f>; 1100 iommus = <&apps_smmu 0x56 0x0>; 1101 #dma-cells = <3>; 1102 status = "disabled"; 1103 }; 1104 1105 qupv3_id_1: geniqup@ac0000 { 1106 compatible = "qcom,geni-se-qup"; 1107 reg = <0x0 0x00ac0000 0x0 0x6000>; 1108 clock-names = "m-ahb", "s-ahb"; 1109 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1110 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1111 #address-cells = <2>; 1112 #size-cells = <2>; 1113 iommus = <&apps_smmu 0x43 0x0>; 1114 ranges; 1115 status = "disabled"; 1116 1117 i2c8: i2c@a80000 { 1118 compatible = "qcom,geni-i2c"; 1119 reg = <0 0x00a80000 0 0x4000>; 1120 clock-names = "se"; 1121 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1122 pinctrl-names = "default"; 1123 pinctrl-0 = <&qup_i2c8_default>; 1124 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1125 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1126 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1127 dma-names = "tx", "rx"; 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 status = "disabled"; 1131 }; 1132 1133 spi8: spi@a80000 { 1134 compatible = "qcom,geni-spi"; 1135 reg = <0 0x00a80000 0 0x4000>; 1136 clock-names = "se"; 1137 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1138 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1139 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1140 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1141 dma-names = "tx", "rx"; 1142 power-domains = <&rpmhpd SM8250_CX>; 1143 operating-points-v2 = <&qup_opp_table>; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 status = "disabled"; 1147 }; 1148 1149 i2c9: i2c@a84000 { 1150 compatible = "qcom,geni-i2c"; 1151 reg = <0 0x00a84000 0 0x4000>; 1152 clock-names = "se"; 1153 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1154 pinctrl-names = "default"; 1155 pinctrl-0 = <&qup_i2c9_default>; 1156 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1157 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1158 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1159 dma-names = "tx", "rx"; 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 status = "disabled"; 1163 }; 1164 1165 spi9: spi@a84000 { 1166 compatible = "qcom,geni-spi"; 1167 reg = <0 0x00a84000 0 0x4000>; 1168 clock-names = "se"; 1169 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1170 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1171 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1172 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1173 dma-names = "tx", "rx"; 1174 power-domains = <&rpmhpd SM8250_CX>; 1175 operating-points-v2 = <&qup_opp_table>; 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 status = "disabled"; 1179 }; 1180 1181 i2c10: i2c@a88000 { 1182 compatible = "qcom,geni-i2c"; 1183 reg = <0 0x00a88000 0 0x4000>; 1184 clock-names = "se"; 1185 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1186 pinctrl-names = "default"; 1187 pinctrl-0 = <&qup_i2c10_default>; 1188 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1189 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1190 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1191 dma-names = "tx", "rx"; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 status = "disabled"; 1195 }; 1196 1197 spi10: spi@a88000 { 1198 compatible = "qcom,geni-spi"; 1199 reg = <0 0x00a88000 0 0x4000>; 1200 clock-names = "se"; 1201 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1202 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1203 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1204 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1205 dma-names = "tx", "rx"; 1206 power-domains = <&rpmhpd SM8250_CX>; 1207 operating-points-v2 = <&qup_opp_table>; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 status = "disabled"; 1211 }; 1212 1213 i2c11: i2c@a8c000 { 1214 compatible = "qcom,geni-i2c"; 1215 reg = <0 0x00a8c000 0 0x4000>; 1216 clock-names = "se"; 1217 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1218 pinctrl-names = "default"; 1219 pinctrl-0 = <&qup_i2c11_default>; 1220 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1221 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1222 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1223 dma-names = "tx", "rx"; 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 status = "disabled"; 1227 }; 1228 1229 spi11: spi@a8c000 { 1230 compatible = "qcom,geni-spi"; 1231 reg = <0 0x00a8c000 0 0x4000>; 1232 clock-names = "se"; 1233 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1234 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1235 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1236 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1237 dma-names = "tx", "rx"; 1238 power-domains = <&rpmhpd SM8250_CX>; 1239 operating-points-v2 = <&qup_opp_table>; 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 status = "disabled"; 1243 }; 1244 1245 i2c12: i2c@a90000 { 1246 compatible = "qcom,geni-i2c"; 1247 reg = <0 0x00a90000 0 0x4000>; 1248 clock-names = "se"; 1249 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1250 pinctrl-names = "default"; 1251 pinctrl-0 = <&qup_i2c12_default>; 1252 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1253 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1254 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1255 dma-names = "tx", "rx"; 1256 #address-cells = <1>; 1257 #size-cells = <0>; 1258 status = "disabled"; 1259 }; 1260 1261 spi12: spi@a90000 { 1262 compatible = "qcom,geni-spi"; 1263 reg = <0 0x00a90000 0 0x4000>; 1264 clock-names = "se"; 1265 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1266 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1267 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1268 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1269 dma-names = "tx", "rx"; 1270 power-domains = <&rpmhpd SM8250_CX>; 1271 operating-points-v2 = <&qup_opp_table>; 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 status = "disabled"; 1275 }; 1276 1277 uart12: serial@a90000 { 1278 compatible = "qcom,geni-debug-uart"; 1279 reg = <0x0 0x00a90000 0x0 0x4000>; 1280 clock-names = "se"; 1281 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1282 pinctrl-names = "default"; 1283 pinctrl-0 = <&qup_uart12_default>; 1284 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1285 power-domains = <&rpmhpd SM8250_CX>; 1286 operating-points-v2 = <&qup_opp_table>; 1287 status = "disabled"; 1288 }; 1289 1290 i2c13: i2c@a94000 { 1291 compatible = "qcom,geni-i2c"; 1292 reg = <0 0x00a94000 0 0x4000>; 1293 clock-names = "se"; 1294 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1295 pinctrl-names = "default"; 1296 pinctrl-0 = <&qup_i2c13_default>; 1297 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1298 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1299 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1300 dma-names = "tx", "rx"; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 status = "disabled"; 1304 }; 1305 1306 spi13: spi@a94000 { 1307 compatible = "qcom,geni-spi"; 1308 reg = <0 0x00a94000 0 0x4000>; 1309 clock-names = "se"; 1310 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1311 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1312 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1313 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1314 dma-names = "tx", "rx"; 1315 power-domains = <&rpmhpd SM8250_CX>; 1316 operating-points-v2 = <&qup_opp_table>; 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 status = "disabled"; 1320 }; 1321 }; 1322 1323 config_noc: interconnect@1500000 { 1324 compatible = "qcom,sm8250-config-noc"; 1325 reg = <0 0x01500000 0 0xa580>; 1326 #interconnect-cells = <1>; 1327 qcom,bcm-voters = <&apps_bcm_voter>; 1328 }; 1329 1330 system_noc: interconnect@1620000 { 1331 compatible = "qcom,sm8250-system-noc"; 1332 reg = <0 0x01620000 0 0x1c200>; 1333 #interconnect-cells = <1>; 1334 qcom,bcm-voters = <&apps_bcm_voter>; 1335 }; 1336 1337 mc_virt: interconnect@163d000 { 1338 compatible = "qcom,sm8250-mc-virt"; 1339 reg = <0 0x0163d000 0 0x1000>; 1340 #interconnect-cells = <1>; 1341 qcom,bcm-voters = <&apps_bcm_voter>; 1342 }; 1343 1344 aggre1_noc: interconnect@16e0000 { 1345 compatible = "qcom,sm8250-aggre1-noc"; 1346 reg = <0 0x016e0000 0 0x1f180>; 1347 #interconnect-cells = <1>; 1348 qcom,bcm-voters = <&apps_bcm_voter>; 1349 }; 1350 1351 aggre2_noc: interconnect@1700000 { 1352 compatible = "qcom,sm8250-aggre2-noc"; 1353 reg = <0 0x01700000 0 0x33000>; 1354 #interconnect-cells = <1>; 1355 qcom,bcm-voters = <&apps_bcm_voter>; 1356 }; 1357 1358 compute_noc: interconnect@1733000 { 1359 compatible = "qcom,sm8250-compute-noc"; 1360 reg = <0 0x01733000 0 0xa180>; 1361 #interconnect-cells = <1>; 1362 qcom,bcm-voters = <&apps_bcm_voter>; 1363 }; 1364 1365 mmss_noc: interconnect@1740000 { 1366 compatible = "qcom,sm8250-mmss-noc"; 1367 reg = <0 0x01740000 0 0x1f080>; 1368 #interconnect-cells = <1>; 1369 qcom,bcm-voters = <&apps_bcm_voter>; 1370 }; 1371 1372 pcie0: pci@1c00000 { 1373 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1374 reg = <0 0x01c00000 0 0x3000>, 1375 <0 0x60000000 0 0xf1d>, 1376 <0 0x60000f20 0 0xa8>, 1377 <0 0x60001000 0 0x1000>, 1378 <0 0x60100000 0 0x100000>; 1379 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1380 device_type = "pci"; 1381 linux,pci-domain = <0>; 1382 bus-range = <0x00 0xff>; 1383 num-lanes = <1>; 1384 1385 #address-cells = <3>; 1386 #size-cells = <2>; 1387 1388 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1389 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1390 1391 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1392 interrupt-names = "msi"; 1393 #interrupt-cells = <1>; 1394 interrupt-map-mask = <0 0 0 0x7>; 1395 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1396 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1397 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1398 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1399 1400 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1401 <&gcc GCC_PCIE_0_AUX_CLK>, 1402 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1403 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1404 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1405 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1406 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1407 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1408 clock-names = "pipe", 1409 "aux", 1410 "cfg", 1411 "bus_master", 1412 "bus_slave", 1413 "slave_q2a", 1414 "tbu", 1415 "ddrss_sf_tbu"; 1416 1417 iommus = <&apps_smmu 0x1c00 0x7f>; 1418 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1419 <0x100 &apps_smmu 0x1c01 0x1>; 1420 1421 resets = <&gcc GCC_PCIE_0_BCR>; 1422 reset-names = "pci"; 1423 1424 power-domains = <&gcc PCIE_0_GDSC>; 1425 1426 phys = <&pcie0_lane>; 1427 phy-names = "pciephy"; 1428 1429 perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; 1430 enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; 1431 1432 pinctrl-names = "default"; 1433 pinctrl-0 = <&pcie0_default_state>; 1434 1435 status = "disabled"; 1436 }; 1437 1438 pcie0_phy: phy@1c06000 { 1439 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1440 reg = <0 0x01c06000 0 0x1c0>; 1441 #address-cells = <2>; 1442 #size-cells = <2>; 1443 ranges; 1444 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1445 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1446 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1447 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1448 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1449 1450 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1451 reset-names = "phy"; 1452 1453 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1454 assigned-clock-rates = <100000000>; 1455 1456 status = "disabled"; 1457 1458 pcie0_lane: phy@1c06200 { 1459 reg = <0 0x1c06200 0 0x170>, /* tx */ 1460 <0 0x1c06400 0 0x200>, /* rx */ 1461 <0 0x1c06800 0 0x1f0>, /* pcs */ 1462 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1463 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1464 clock-names = "pipe0"; 1465 1466 #phy-cells = <0>; 1467 clock-output-names = "pcie_0_pipe_clk"; 1468 }; 1469 }; 1470 1471 pcie1: pci@1c08000 { 1472 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1473 reg = <0 0x01c08000 0 0x3000>, 1474 <0 0x40000000 0 0xf1d>, 1475 <0 0x40000f20 0 0xa8>, 1476 <0 0x40001000 0 0x1000>, 1477 <0 0x40100000 0 0x100000>; 1478 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1479 device_type = "pci"; 1480 linux,pci-domain = <1>; 1481 bus-range = <0x00 0xff>; 1482 num-lanes = <2>; 1483 1484 #address-cells = <3>; 1485 #size-cells = <2>; 1486 1487 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1488 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1489 1490 interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>; 1491 interrupt-names = "msi"; 1492 #interrupt-cells = <1>; 1493 interrupt-map-mask = <0 0 0 0x7>; 1494 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1495 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1496 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1497 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1498 1499 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1500 <&gcc GCC_PCIE_1_AUX_CLK>, 1501 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1502 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1503 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1504 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1505 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1506 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1507 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1508 clock-names = "pipe", 1509 "aux", 1510 "cfg", 1511 "bus_master", 1512 "bus_slave", 1513 "slave_q2a", 1514 "ref", 1515 "tbu", 1516 "ddrss_sf_tbu"; 1517 1518 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1519 assigned-clock-rates = <19200000>; 1520 1521 iommus = <&apps_smmu 0x1c80 0x7f>; 1522 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1523 <0x100 &apps_smmu 0x1c81 0x1>; 1524 1525 resets = <&gcc GCC_PCIE_1_BCR>; 1526 reset-names = "pci"; 1527 1528 power-domains = <&gcc PCIE_1_GDSC>; 1529 1530 phys = <&pcie1_lane>; 1531 phy-names = "pciephy"; 1532 1533 perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>; 1534 enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; 1535 1536 pinctrl-names = "default"; 1537 pinctrl-0 = <&pcie1_default_state>; 1538 1539 status = "disabled"; 1540 }; 1541 1542 pcie1_phy: phy@1c0e000 { 1543 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1544 reg = <0 0x01c0e000 0 0x1c0>; 1545 #address-cells = <2>; 1546 #size-cells = <2>; 1547 ranges; 1548 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1549 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1550 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1551 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1552 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1553 1554 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1555 reset-names = "phy"; 1556 1557 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1558 assigned-clock-rates = <100000000>; 1559 1560 status = "disabled"; 1561 1562 pcie1_lane: phy@1c0e200 { 1563 reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1564 <0 0x1c0e400 0 0x200>, /* rx0 */ 1565 <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1566 <0 0x1c0e600 0 0x170>, /* tx1 */ 1567 <0 0x1c0e800 0 0x200>, /* rx1 */ 1568 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1569 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1570 clock-names = "pipe0"; 1571 1572 #phy-cells = <0>; 1573 clock-output-names = "pcie_1_pipe_clk"; 1574 }; 1575 }; 1576 1577 pcie2: pci@1c10000 { 1578 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1579 reg = <0 0x01c10000 0 0x3000>, 1580 <0 0x64000000 0 0xf1d>, 1581 <0 0x64000f20 0 0xa8>, 1582 <0 0x64001000 0 0x1000>, 1583 <0 0x64100000 0 0x100000>; 1584 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1585 device_type = "pci"; 1586 linux,pci-domain = <2>; 1587 bus-range = <0x00 0xff>; 1588 num-lanes = <2>; 1589 1590 #address-cells = <3>; 1591 #size-cells = <2>; 1592 1593 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, 1594 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 1595 1596 interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; 1597 interrupt-names = "msi"; 1598 #interrupt-cells = <1>; 1599 interrupt-map-mask = <0 0 0 0x7>; 1600 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1601 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1602 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1603 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1604 1605 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1606 <&gcc GCC_PCIE_2_AUX_CLK>, 1607 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1608 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1609 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 1610 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 1611 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1612 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1613 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1614 clock-names = "pipe", 1615 "aux", 1616 "cfg", 1617 "bus_master", 1618 "bus_slave", 1619 "slave_q2a", 1620 "ref", 1621 "tbu", 1622 "ddrss_sf_tbu"; 1623 1624 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 1625 assigned-clock-rates = <19200000>; 1626 1627 iommus = <&apps_smmu 0x1d00 0x7f>; 1628 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 1629 <0x100 &apps_smmu 0x1d01 0x1>; 1630 1631 resets = <&gcc GCC_PCIE_2_BCR>; 1632 reset-names = "pci"; 1633 1634 power-domains = <&gcc PCIE_2_GDSC>; 1635 1636 phys = <&pcie2_lane>; 1637 phy-names = "pciephy"; 1638 1639 perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>; 1640 enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; 1641 1642 pinctrl-names = "default"; 1643 pinctrl-0 = <&pcie2_default_state>; 1644 1645 status = "disabled"; 1646 }; 1647 1648 pcie2_phy: phy@1c16000 { 1649 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 1650 reg = <0 0x1c16000 0 0x1c0>; 1651 #address-cells = <2>; 1652 #size-cells = <2>; 1653 ranges; 1654 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1655 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1656 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1657 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1658 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1659 1660 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 1661 reset-names = "phy"; 1662 1663 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1664 assigned-clock-rates = <100000000>; 1665 1666 status = "disabled"; 1667 1668 pcie2_lane: phy@1c16200 { 1669 reg = <0 0x1c16200 0 0x170>, /* tx0 */ 1670 <0 0x1c16400 0 0x200>, /* rx0 */ 1671 <0 0x1c16a00 0 0x1f0>, /* pcs */ 1672 <0 0x1c16600 0 0x170>, /* tx1 */ 1673 <0 0x1c16800 0 0x200>, /* rx1 */ 1674 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1675 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 1676 clock-names = "pipe0"; 1677 1678 #phy-cells = <0>; 1679 clock-output-names = "pcie_2_pipe_clk"; 1680 }; 1681 }; 1682 1683 ufs_mem_hc: ufshc@1d84000 { 1684 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 1685 "jedec,ufs-2.0"; 1686 reg = <0 0x01d84000 0 0x3000>; 1687 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1688 phys = <&ufs_mem_phy_lanes>; 1689 phy-names = "ufsphy"; 1690 lanes-per-direction = <2>; 1691 #reset-cells = <1>; 1692 resets = <&gcc GCC_UFS_PHY_BCR>; 1693 reset-names = "rst"; 1694 1695 power-domains = <&gcc UFS_PHY_GDSC>; 1696 1697 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 1698 1699 clock-names = 1700 "core_clk", 1701 "bus_aggr_clk", 1702 "iface_clk", 1703 "core_clk_unipro", 1704 "ref_clk", 1705 "tx_lane0_sync_clk", 1706 "rx_lane0_sync_clk", 1707 "rx_lane1_sync_clk"; 1708 clocks = 1709 <&gcc GCC_UFS_PHY_AXI_CLK>, 1710 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1711 <&gcc GCC_UFS_PHY_AHB_CLK>, 1712 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1713 <&rpmhcc RPMH_CXO_CLK>, 1714 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1715 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1716 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1717 freq-table-hz = 1718 <37500000 300000000>, 1719 <0 0>, 1720 <0 0>, 1721 <37500000 300000000>, 1722 <0 0>, 1723 <0 0>, 1724 <0 0>, 1725 <0 0>; 1726 1727 status = "disabled"; 1728 }; 1729 1730 ufs_mem_phy: phy@1d87000 { 1731 compatible = "qcom,sm8250-qmp-ufs-phy"; 1732 reg = <0 0x01d87000 0 0x1c0>; 1733 #address-cells = <2>; 1734 #size-cells = <2>; 1735 ranges; 1736 clock-names = "ref", 1737 "ref_aux"; 1738 clocks = <&rpmhcc RPMH_CXO_CLK>, 1739 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1740 1741 resets = <&ufs_mem_hc 0>; 1742 reset-names = "ufsphy"; 1743 status = "disabled"; 1744 1745 ufs_mem_phy_lanes: phy@1d87400 { 1746 reg = <0 0x01d87400 0 0x108>, 1747 <0 0x01d87600 0 0x1e0>, 1748 <0 0x01d87c00 0 0x1dc>, 1749 <0 0x01d87800 0 0x108>, 1750 <0 0x01d87a00 0 0x1e0>; 1751 #phy-cells = <0>; 1752 }; 1753 }; 1754 1755 ipa_virt: interconnect@1e00000 { 1756 compatible = "qcom,sm8250-ipa-virt"; 1757 reg = <0 0x01e00000 0 0x1000>; 1758 #interconnect-cells = <1>; 1759 qcom,bcm-voters = <&apps_bcm_voter>; 1760 }; 1761 1762 tcsr_mutex: hwlock@1f40000 { 1763 compatible = "qcom,tcsr-mutex"; 1764 reg = <0x0 0x01f40000 0x0 0x40000>; 1765 #hwlock-cells = <1>; 1766 }; 1767 1768 wsamacro: codec@3240000 { 1769 compatible = "qcom,sm8250-lpass-wsa-macro"; 1770 reg = <0 0x03240000 0 0x1000>; 1771 clocks = <&audiocc 1>, 1772 <&audiocc 0>, 1773 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1774 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1775 <&aoncc 0>, 1776 <&vamacro>; 1777 1778 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 1779 1780 #clock-cells = <0>; 1781 clock-frequency = <9600000>; 1782 clock-output-names = "mclk"; 1783 #sound-dai-cells = <1>; 1784 1785 pinctrl-names = "default"; 1786 pinctrl-0 = <&wsa_swr_active>; 1787 }; 1788 1789 swr0: soundwire-controller@3250000 { 1790 reg = <0 0x03250000 0 0x2000>; 1791 compatible = "qcom,soundwire-v1.5.1"; 1792 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1793 clocks = <&wsamacro>; 1794 clock-names = "iface"; 1795 1796 qcom,din-ports = <2>; 1797 qcom,dout-ports = <6>; 1798 1799 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 1800 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 1801 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 1802 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 1803 1804 #sound-dai-cells = <1>; 1805 #address-cells = <2>; 1806 #size-cells = <0>; 1807 }; 1808 1809 audiocc: clock-controller@3300000 { 1810 compatible = "qcom,sm8250-lpass-audiocc"; 1811 reg = <0 0x03300000 0 0x30000>; 1812 #clock-cells = <1>; 1813 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1814 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1815 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1816 clock-names = "core", "audio", "bus"; 1817 }; 1818 1819 vamacro: codec@3370000 { 1820 compatible = "qcom,sm8250-lpass-va-macro"; 1821 reg = <0 0x03370000 0 0x1000>; 1822 clocks = <&aoncc 0>, 1823 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1824 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1825 1826 clock-names = "mclk", "macro", "dcodec"; 1827 1828 #clock-cells = <0>; 1829 clock-frequency = <9600000>; 1830 clock-output-names = "fsgen"; 1831 #sound-dai-cells = <1>; 1832 }; 1833 1834 aoncc: clock-controller@3380000 { 1835 compatible = "qcom,sm8250-lpass-aoncc"; 1836 reg = <0 0x03380000 0 0x40000>; 1837 #clock-cells = <1>; 1838 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1839 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1840 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1841 clock-names = "core", "audio", "bus"; 1842 }; 1843 1844 lpass_tlmm: pinctrl@33c0000{ 1845 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 1846 reg = <0 0x033c0000 0x0 0x20000>, 1847 <0 0x03550000 0x0 0x10000>; 1848 gpio-controller; 1849 #gpio-cells = <2>; 1850 gpio-ranges = <&lpass_tlmm 0 0 14>; 1851 1852 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1853 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1854 clock-names = "core", "audio"; 1855 1856 wsa_swr_active: wsa-swr-active-pins { 1857 clk { 1858 pins = "gpio10"; 1859 function = "wsa_swr_clk"; 1860 drive-strength = <2>; 1861 slew-rate = <1>; 1862 bias-disable; 1863 }; 1864 1865 data { 1866 pins = "gpio11"; 1867 function = "wsa_swr_data"; 1868 drive-strength = <2>; 1869 slew-rate = <1>; 1870 bias-bus-hold; 1871 1872 }; 1873 }; 1874 1875 wsa_swr_sleep: wsa-swr-sleep-pins { 1876 clk { 1877 pins = "gpio10"; 1878 function = "wsa_swr_clk"; 1879 drive-strength = <2>; 1880 input-enable; 1881 bias-pull-down; 1882 }; 1883 1884 data { 1885 pins = "gpio11"; 1886 function = "wsa_swr_data"; 1887 drive-strength = <2>; 1888 input-enable; 1889 bias-pull-down; 1890 1891 }; 1892 }; 1893 1894 dmic01_active: dmic01-active-pins { 1895 clk { 1896 pins = "gpio6"; 1897 function = "dmic1_clk"; 1898 drive-strength = <8>; 1899 output-high; 1900 }; 1901 data { 1902 pins = "gpio7"; 1903 function = "dmic1_data"; 1904 drive-strength = <8>; 1905 input-enable; 1906 }; 1907 }; 1908 1909 dmic01_sleep: dmic01-sleep-pins { 1910 clk { 1911 pins = "gpio6"; 1912 function = "dmic1_clk"; 1913 drive-strength = <2>; 1914 bias-disable; 1915 output-low; 1916 }; 1917 1918 data { 1919 pins = "gpio7"; 1920 function = "dmic1_data"; 1921 drive-strength = <2>; 1922 pull-down; 1923 input-enable; 1924 }; 1925 }; 1926 }; 1927 1928 gpu: gpu@3d00000 { 1929 compatible = "qcom,adreno-650.2", 1930 "qcom,adreno"; 1931 #stream-id-cells = <16>; 1932 1933 reg = <0 0x03d00000 0 0x40000>; 1934 reg-names = "kgsl_3d0_reg_memory"; 1935 1936 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1937 1938 iommus = <&adreno_smmu 0 0x401>; 1939 1940 operating-points-v2 = <&gpu_opp_table>; 1941 1942 qcom,gmu = <&gmu>; 1943 1944 status = "disabled"; 1945 1946 zap-shader { 1947 memory-region = <&gpu_mem>; 1948 }; 1949 1950 /* note: downstream checks gpu binning for 670 Mhz */ 1951 gpu_opp_table: opp-table { 1952 compatible = "operating-points-v2"; 1953 1954 opp-670000000 { 1955 opp-hz = /bits/ 64 <670000000>; 1956 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1957 }; 1958 1959 opp-587000000 { 1960 opp-hz = /bits/ 64 <587000000>; 1961 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1962 }; 1963 1964 opp-525000000 { 1965 opp-hz = /bits/ 64 <525000000>; 1966 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1967 }; 1968 1969 opp-490000000 { 1970 opp-hz = /bits/ 64 <490000000>; 1971 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1972 }; 1973 1974 opp-441600000 { 1975 opp-hz = /bits/ 64 <441600000>; 1976 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1977 }; 1978 1979 opp-400000000 { 1980 opp-hz = /bits/ 64 <400000000>; 1981 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1982 }; 1983 1984 opp-305000000 { 1985 opp-hz = /bits/ 64 <305000000>; 1986 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1987 }; 1988 }; 1989 }; 1990 1991 gmu: gmu@3d6a000 { 1992 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 1993 1994 reg = <0 0x03d6a000 0 0x30000>, 1995 <0 0x3de0000 0 0x10000>, 1996 <0 0xb290000 0 0x10000>, 1997 <0 0xb490000 0 0x10000>; 1998 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 1999 2000 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2001 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2002 interrupt-names = "hfi", "gmu"; 2003 2004 clocks = <&gpucc GPU_CC_AHB_CLK>, 2005 <&gpucc GPU_CC_CX_GMU_CLK>, 2006 <&gpucc GPU_CC_CXO_CLK>, 2007 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2008 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2009 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2010 2011 power-domains = <&gpucc GPU_CX_GDSC>, 2012 <&gpucc GPU_GX_GDSC>; 2013 power-domain-names = "cx", "gx"; 2014 2015 iommus = <&adreno_smmu 5 0x400>; 2016 2017 operating-points-v2 = <&gmu_opp_table>; 2018 2019 status = "disabled"; 2020 2021 gmu_opp_table: opp-table { 2022 compatible = "operating-points-v2"; 2023 2024 opp-200000000 { 2025 opp-hz = /bits/ 64 <200000000>; 2026 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2027 }; 2028 }; 2029 }; 2030 2031 gpucc: clock-controller@3d90000 { 2032 compatible = "qcom,sm8250-gpucc"; 2033 reg = <0 0x03d90000 0 0x9000>; 2034 clocks = <&rpmhcc RPMH_CXO_CLK>, 2035 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2036 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2037 clock-names = "bi_tcxo", 2038 "gcc_gpu_gpll0_clk_src", 2039 "gcc_gpu_gpll0_div_clk_src"; 2040 #clock-cells = <1>; 2041 #reset-cells = <1>; 2042 #power-domain-cells = <1>; 2043 }; 2044 2045 adreno_smmu: iommu@3da0000 { 2046 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 2047 reg = <0 0x03da0000 0 0x10000>; 2048 #iommu-cells = <2>; 2049 #global-interrupts = <2>; 2050 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2052 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2053 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2054 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2055 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2057 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 2060 clocks = <&gpucc GPU_CC_AHB_CLK>, 2061 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2062 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2063 clock-names = "ahb", "bus", "iface"; 2064 2065 power-domains = <&gpucc GPU_CX_GDSC>; 2066 }; 2067 2068 slpi: remoteproc@5c00000 { 2069 compatible = "qcom,sm8250-slpi-pas"; 2070 reg = <0 0x05c00000 0 0x4000>; 2071 2072 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2073 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2074 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2075 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2076 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2077 interrupt-names = "wdog", "fatal", "ready", 2078 "handover", "stop-ack"; 2079 2080 clocks = <&rpmhcc RPMH_CXO_CLK>; 2081 clock-names = "xo"; 2082 2083 power-domains = <&rpmhpd SM8250_LCX>, 2084 <&rpmhpd SM8250_LMX>; 2085 power-domain-names = "lcx", "lmx"; 2086 2087 memory-region = <&slpi_mem>; 2088 2089 qcom,qmp = <&aoss_qmp>; 2090 2091 qcom,smem-states = <&smp2p_slpi_out 0>; 2092 qcom,smem-state-names = "stop"; 2093 2094 status = "disabled"; 2095 2096 glink-edge { 2097 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2098 IPCC_MPROC_SIGNAL_GLINK_QMP 2099 IRQ_TYPE_EDGE_RISING>; 2100 mboxes = <&ipcc IPCC_CLIENT_SLPI 2101 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2102 2103 label = "slpi"; 2104 qcom,remote-pid = <3>; 2105 2106 fastrpc { 2107 compatible = "qcom,fastrpc"; 2108 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2109 label = "sdsp"; 2110 #address-cells = <1>; 2111 #size-cells = <0>; 2112 2113 compute-cb@1 { 2114 compatible = "qcom,fastrpc-compute-cb"; 2115 reg = <1>; 2116 iommus = <&apps_smmu 0x0541 0x0>; 2117 }; 2118 2119 compute-cb@2 { 2120 compatible = "qcom,fastrpc-compute-cb"; 2121 reg = <2>; 2122 iommus = <&apps_smmu 0x0542 0x0>; 2123 }; 2124 2125 compute-cb@3 { 2126 compatible = "qcom,fastrpc-compute-cb"; 2127 reg = <3>; 2128 iommus = <&apps_smmu 0x0543 0x0>; 2129 /* note: shared-cb = <4> in downstream */ 2130 }; 2131 }; 2132 }; 2133 }; 2134 2135 cdsp: remoteproc@8300000 { 2136 compatible = "qcom,sm8250-cdsp-pas"; 2137 reg = <0 0x08300000 0 0x10000>; 2138 2139 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 2140 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2141 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2142 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2143 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2144 interrupt-names = "wdog", "fatal", "ready", 2145 "handover", "stop-ack"; 2146 2147 clocks = <&rpmhcc RPMH_CXO_CLK>; 2148 clock-names = "xo"; 2149 2150 power-domains = <&rpmhpd SM8250_CX>; 2151 2152 memory-region = <&cdsp_mem>; 2153 2154 qcom,qmp = <&aoss_qmp>; 2155 2156 qcom,smem-states = <&smp2p_cdsp_out 0>; 2157 qcom,smem-state-names = "stop"; 2158 2159 status = "disabled"; 2160 2161 glink-edge { 2162 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2163 IPCC_MPROC_SIGNAL_GLINK_QMP 2164 IRQ_TYPE_EDGE_RISING>; 2165 mboxes = <&ipcc IPCC_CLIENT_CDSP 2166 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2167 2168 label = "cdsp"; 2169 qcom,remote-pid = <5>; 2170 2171 fastrpc { 2172 compatible = "qcom,fastrpc"; 2173 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2174 label = "cdsp"; 2175 #address-cells = <1>; 2176 #size-cells = <0>; 2177 2178 compute-cb@1 { 2179 compatible = "qcom,fastrpc-compute-cb"; 2180 reg = <1>; 2181 iommus = <&apps_smmu 0x1001 0x0460>; 2182 }; 2183 2184 compute-cb@2 { 2185 compatible = "qcom,fastrpc-compute-cb"; 2186 reg = <2>; 2187 iommus = <&apps_smmu 0x1002 0x0460>; 2188 }; 2189 2190 compute-cb@3 { 2191 compatible = "qcom,fastrpc-compute-cb"; 2192 reg = <3>; 2193 iommus = <&apps_smmu 0x1003 0x0460>; 2194 }; 2195 2196 compute-cb@4 { 2197 compatible = "qcom,fastrpc-compute-cb"; 2198 reg = <4>; 2199 iommus = <&apps_smmu 0x1004 0x0460>; 2200 }; 2201 2202 compute-cb@5 { 2203 compatible = "qcom,fastrpc-compute-cb"; 2204 reg = <5>; 2205 iommus = <&apps_smmu 0x1005 0x0460>; 2206 }; 2207 2208 compute-cb@6 { 2209 compatible = "qcom,fastrpc-compute-cb"; 2210 reg = <6>; 2211 iommus = <&apps_smmu 0x1006 0x0460>; 2212 }; 2213 2214 compute-cb@7 { 2215 compatible = "qcom,fastrpc-compute-cb"; 2216 reg = <7>; 2217 iommus = <&apps_smmu 0x1007 0x0460>; 2218 }; 2219 2220 compute-cb@8 { 2221 compatible = "qcom,fastrpc-compute-cb"; 2222 reg = <8>; 2223 iommus = <&apps_smmu 0x1008 0x0460>; 2224 }; 2225 2226 /* note: secure cb9 in downstream */ 2227 }; 2228 }; 2229 }; 2230 2231 sound: sound { 2232 }; 2233 2234 usb_1_hsphy: phy@88e3000 { 2235 compatible = "qcom,sm8250-usb-hs-phy", 2236 "qcom,usb-snps-hs-7nm-phy"; 2237 reg = <0 0x088e3000 0 0x400>; 2238 status = "disabled"; 2239 #phy-cells = <0>; 2240 2241 clocks = <&rpmhcc RPMH_CXO_CLK>; 2242 clock-names = "ref"; 2243 2244 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2245 }; 2246 2247 usb_2_hsphy: phy@88e4000 { 2248 compatible = "qcom,sm8250-usb-hs-phy", 2249 "qcom,usb-snps-hs-7nm-phy"; 2250 reg = <0 0x088e4000 0 0x400>; 2251 status = "disabled"; 2252 #phy-cells = <0>; 2253 2254 clocks = <&rpmhcc RPMH_CXO_CLK>; 2255 clock-names = "ref"; 2256 2257 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2258 }; 2259 2260 usb_1_qmpphy: phy@88e9000 { 2261 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 2262 reg = <0 0x088e9000 0 0x200>, 2263 <0 0x088e8000 0 0x40>, 2264 <0 0x088ea000 0 0x200>; 2265 status = "disabled"; 2266 #address-cells = <2>; 2267 #size-cells = <2>; 2268 ranges; 2269 2270 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2271 <&rpmhcc RPMH_CXO_CLK>, 2272 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2273 clock-names = "aux", "ref_clk_src", "com_aux"; 2274 2275 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2276 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2277 reset-names = "phy", "common"; 2278 2279 usb_1_ssphy: usb3-phy@88e9200 { 2280 reg = <0 0x088e9200 0 0x200>, 2281 <0 0x088e9400 0 0x200>, 2282 <0 0x088e9c00 0 0x400>, 2283 <0 0x088e9600 0 0x200>, 2284 <0 0x088e9800 0 0x200>, 2285 <0 0x088e9a00 0 0x100>; 2286 #clock-cells = <0>; 2287 #phy-cells = <0>; 2288 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2289 clock-names = "pipe0"; 2290 clock-output-names = "usb3_phy_pipe_clk_src"; 2291 }; 2292 2293 dp_phy: dp-phy@88ea200 { 2294 reg = <0 0x088ea200 0 0x200>, 2295 <0 0x088ea400 0 0x200>, 2296 <0 0x088eac00 0 0x400>, 2297 <0 0x088ea600 0 0x200>, 2298 <0 0x088ea800 0 0x200>, 2299 <0 0x088eaa00 0 0x100>; 2300 #phy-cells = <0>; 2301 #clock-cells = <1>; 2302 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2303 clock-names = "pipe0"; 2304 clock-output-names = "usb3_phy_pipe_clk_src"; 2305 }; 2306 }; 2307 2308 usb_2_qmpphy: phy@88eb000 { 2309 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 2310 reg = <0 0x088eb000 0 0x200>; 2311 status = "disabled"; 2312 #address-cells = <2>; 2313 #size-cells = <2>; 2314 ranges; 2315 2316 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2317 <&rpmhcc RPMH_CXO_CLK>, 2318 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2319 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2320 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2321 2322 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2323 <&gcc GCC_USB3_PHY_SEC_BCR>; 2324 reset-names = "phy", "common"; 2325 2326 usb_2_ssphy: phy@88eb200 { 2327 reg = <0 0x088eb200 0 0x200>, 2328 <0 0x088eb400 0 0x200>, 2329 <0 0x088eb800 0 0x800>; 2330 #clock-cells = <0>; 2331 #phy-cells = <0>; 2332 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2333 clock-names = "pipe0"; 2334 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2335 }; 2336 }; 2337 2338 sdhc_2: sdhci@8804000 { 2339 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 2340 reg = <0 0x08804000 0 0x1000>; 2341 2342 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2343 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2344 interrupt-names = "hc_irq", "pwr_irq"; 2345 2346 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2347 <&gcc GCC_SDCC2_APPS_CLK>, 2348 <&rpmhcc RPMH_CXO_CLK>; 2349 clock-names = "iface", "core", "xo"; 2350 iommus = <&apps_smmu 0x4a0 0x0>; 2351 qcom,dll-config = <0x0007642c>; 2352 qcom,ddr-config = <0x80040868>; 2353 power-domains = <&rpmhpd SM8250_CX>; 2354 operating-points-v2 = <&sdhc2_opp_table>; 2355 2356 status = "disabled"; 2357 2358 sdhc2_opp_table: sdhc2-opp-table { 2359 compatible = "operating-points-v2"; 2360 2361 opp-19200000 { 2362 opp-hz = /bits/ 64 <19200000>; 2363 required-opps = <&rpmhpd_opp_min_svs>; 2364 }; 2365 2366 opp-50000000 { 2367 opp-hz = /bits/ 64 <50000000>; 2368 required-opps = <&rpmhpd_opp_low_svs>; 2369 }; 2370 2371 opp-100000000 { 2372 opp-hz = /bits/ 64 <100000000>; 2373 required-opps = <&rpmhpd_opp_svs>; 2374 }; 2375 2376 opp-202000000 { 2377 opp-hz = /bits/ 64 <202000000>; 2378 required-opps = <&rpmhpd_opp_svs_l1>; 2379 }; 2380 }; 2381 }; 2382 2383 dc_noc: interconnect@90c0000 { 2384 compatible = "qcom,sm8250-dc-noc"; 2385 reg = <0 0x090c0000 0 0x4200>; 2386 #interconnect-cells = <1>; 2387 qcom,bcm-voters = <&apps_bcm_voter>; 2388 }; 2389 2390 gem_noc: interconnect@9100000 { 2391 compatible = "qcom,sm8250-gem-noc"; 2392 reg = <0 0x09100000 0 0xb4000>; 2393 #interconnect-cells = <1>; 2394 qcom,bcm-voters = <&apps_bcm_voter>; 2395 }; 2396 2397 npu_noc: interconnect@9990000 { 2398 compatible = "qcom,sm8250-npu-noc"; 2399 reg = <0 0x09990000 0 0x1600>; 2400 #interconnect-cells = <1>; 2401 qcom,bcm-voters = <&apps_bcm_voter>; 2402 }; 2403 2404 usb_1: usb@a6f8800 { 2405 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 2406 reg = <0 0x0a6f8800 0 0x400>; 2407 status = "disabled"; 2408 #address-cells = <2>; 2409 #size-cells = <2>; 2410 ranges; 2411 dma-ranges; 2412 2413 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2414 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2415 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2416 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2417 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2418 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2419 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2420 "sleep", "xo"; 2421 2422 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2423 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2424 assigned-clock-rates = <19200000>, <200000000>; 2425 2426 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2427 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2428 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2429 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2430 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2431 "dm_hs_phy_irq", "ss_phy_irq"; 2432 2433 power-domains = <&gcc USB30_PRIM_GDSC>; 2434 2435 resets = <&gcc GCC_USB30_PRIM_BCR>; 2436 2437 usb_1_dwc3: usb@a600000 { 2438 compatible = "snps,dwc3"; 2439 reg = <0 0x0a600000 0 0xcd00>; 2440 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2441 iommus = <&apps_smmu 0x0 0x0>; 2442 snps,dis_u2_susphy_quirk; 2443 snps,dis_enblslpm_quirk; 2444 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2445 phy-names = "usb2-phy", "usb3-phy"; 2446 }; 2447 }; 2448 2449 system-cache-controller@9200000 { 2450 compatible = "qcom,sm8250-llcc"; 2451 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 2452 reg-names = "llcc_base", "llcc_broadcast_base"; 2453 }; 2454 2455 usb_2: usb@a8f8800 { 2456 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 2457 reg = <0 0x0a8f8800 0 0x400>; 2458 status = "disabled"; 2459 #address-cells = <2>; 2460 #size-cells = <2>; 2461 ranges; 2462 dma-ranges; 2463 2464 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2465 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2466 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2467 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2468 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2469 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2470 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2471 "sleep", "xo"; 2472 2473 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2474 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2475 assigned-clock-rates = <19200000>, <200000000>; 2476 2477 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2478 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 2479 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2480 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 2481 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2482 "dm_hs_phy_irq", "ss_phy_irq"; 2483 2484 power-domains = <&gcc USB30_SEC_GDSC>; 2485 2486 resets = <&gcc GCC_USB30_SEC_BCR>; 2487 2488 usb_2_dwc3: usb@a800000 { 2489 compatible = "snps,dwc3"; 2490 reg = <0 0x0a800000 0 0xcd00>; 2491 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2492 iommus = <&apps_smmu 0x20 0>; 2493 snps,dis_u2_susphy_quirk; 2494 snps,dis_enblslpm_quirk; 2495 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2496 phy-names = "usb2-phy", "usb3-phy"; 2497 }; 2498 }; 2499 2500 venus: video-codec@aa00000 { 2501 compatible = "qcom,sm8250-venus"; 2502 reg = <0 0x0aa00000 0 0x100000>; 2503 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2504 power-domains = <&videocc MVS0C_GDSC>, 2505 <&videocc MVS0_GDSC>, 2506 <&rpmhpd SM8250_MX>; 2507 power-domain-names = "venus", "vcodec0", "mx"; 2508 operating-points-v2 = <&venus_opp_table>; 2509 2510 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 2511 <&videocc VIDEO_CC_MVS0C_CLK>, 2512 <&videocc VIDEO_CC_MVS0_CLK>; 2513 clock-names = "iface", "core", "vcodec0_core"; 2514 2515 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, 2516 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; 2517 interconnect-names = "cpu-cfg", "video-mem"; 2518 2519 iommus = <&apps_smmu 0x2100 0x0400>; 2520 memory-region = <&video_mem>; 2521 2522 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 2523 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 2524 reset-names = "bus", "core"; 2525 2526 status = "disabled"; 2527 2528 video-decoder { 2529 compatible = "venus-decoder"; 2530 }; 2531 2532 video-encoder { 2533 compatible = "venus-encoder"; 2534 }; 2535 2536 venus_opp_table: venus-opp-table { 2537 compatible = "operating-points-v2"; 2538 2539 opp-720000000 { 2540 opp-hz = /bits/ 64 <720000000>; 2541 required-opps = <&rpmhpd_opp_low_svs>; 2542 }; 2543 2544 opp-1014000000 { 2545 opp-hz = /bits/ 64 <1014000000>; 2546 required-opps = <&rpmhpd_opp_svs>; 2547 }; 2548 2549 opp-1098000000 { 2550 opp-hz = /bits/ 64 <1098000000>; 2551 required-opps = <&rpmhpd_opp_svs_l1>; 2552 }; 2553 2554 opp-1332000000 { 2555 opp-hz = /bits/ 64 <1332000000>; 2556 required-opps = <&rpmhpd_opp_nom>; 2557 }; 2558 }; 2559 }; 2560 2561 videocc: clock-controller@abf0000 { 2562 compatible = "qcom,sm8250-videocc"; 2563 reg = <0 0x0abf0000 0 0x10000>; 2564 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 2565 <&rpmhcc RPMH_CXO_CLK>, 2566 <&rpmhcc RPMH_CXO_CLK_A>; 2567 power-domains = <&rpmhpd SM8250_MMCX>; 2568 required-opps = <&rpmhpd_opp_low_svs>; 2569 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 2570 #clock-cells = <1>; 2571 #reset-cells = <1>; 2572 #power-domain-cells = <1>; 2573 }; 2574 2575 mdss: mdss@ae00000 { 2576 compatible = "qcom,sm8250-mdss"; 2577 reg = <0 0x0ae00000 0 0x1000>; 2578 reg-names = "mdss"; 2579 2580 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 2581 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 2582 interconnect-names = "mdp0-mem", "mdp1-mem"; 2583 2584 power-domains = <&dispcc MDSS_GDSC>; 2585 2586 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2587 <&gcc GCC_DISP_HF_AXI_CLK>, 2588 <&gcc GCC_DISP_SF_AXI_CLK>, 2589 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2590 clock-names = "iface", "bus", "nrt_bus", "core"; 2591 2592 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2593 assigned-clock-rates = <460000000>; 2594 2595 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2596 interrupt-controller; 2597 #interrupt-cells = <1>; 2598 2599 iommus = <&apps_smmu 0x820 0x402>; 2600 2601 status = "disabled"; 2602 2603 #address-cells = <2>; 2604 #size-cells = <2>; 2605 ranges; 2606 2607 mdss_mdp: mdp@ae01000 { 2608 compatible = "qcom,sm8250-dpu"; 2609 reg = <0 0x0ae01000 0 0x8f000>, 2610 <0 0x0aeb0000 0 0x2008>; 2611 reg-names = "mdp", "vbif"; 2612 2613 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2614 <&gcc GCC_DISP_HF_AXI_CLK>, 2615 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2616 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2617 clock-names = "iface", "bus", "core", "vsync"; 2618 2619 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2620 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2621 assigned-clock-rates = <460000000>, 2622 <19200000>; 2623 2624 operating-points-v2 = <&mdp_opp_table>; 2625 power-domains = <&rpmhpd SM8250_MMCX>; 2626 2627 interrupt-parent = <&mdss>; 2628 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2629 2630 ports { 2631 #address-cells = <1>; 2632 #size-cells = <0>; 2633 2634 port@0 { 2635 reg = <0>; 2636 dpu_intf1_out: endpoint { 2637 remote-endpoint = <&dsi0_in>; 2638 }; 2639 }; 2640 2641 port@1 { 2642 reg = <1>; 2643 dpu_intf2_out: endpoint { 2644 remote-endpoint = <&dsi1_in>; 2645 }; 2646 }; 2647 }; 2648 2649 mdp_opp_table: mdp-opp-table { 2650 compatible = "operating-points-v2"; 2651 2652 opp-200000000 { 2653 opp-hz = /bits/ 64 <200000000>; 2654 required-opps = <&rpmhpd_opp_low_svs>; 2655 }; 2656 2657 opp-300000000 { 2658 opp-hz = /bits/ 64 <300000000>; 2659 required-opps = <&rpmhpd_opp_svs>; 2660 }; 2661 2662 opp-345000000 { 2663 opp-hz = /bits/ 64 <345000000>; 2664 required-opps = <&rpmhpd_opp_svs_l1>; 2665 }; 2666 2667 opp-460000000 { 2668 opp-hz = /bits/ 64 <460000000>; 2669 required-opps = <&rpmhpd_opp_nom>; 2670 }; 2671 }; 2672 }; 2673 2674 dsi0: dsi@ae94000 { 2675 compatible = "qcom,mdss-dsi-ctrl"; 2676 reg = <0 0x0ae94000 0 0x400>; 2677 reg-names = "dsi_ctrl"; 2678 2679 interrupt-parent = <&mdss>; 2680 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 2681 2682 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2683 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2684 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2685 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2686 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2687 <&gcc GCC_DISP_HF_AXI_CLK>; 2688 clock-names = "byte", 2689 "byte_intf", 2690 "pixel", 2691 "core", 2692 "iface", 2693 "bus"; 2694 2695 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2696 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 2697 2698 operating-points-v2 = <&dsi_opp_table>; 2699 power-domains = <&rpmhpd SM8250_MMCX>; 2700 2701 phys = <&dsi0_phy>; 2702 phy-names = "dsi"; 2703 2704 status = "disabled"; 2705 2706 #address-cells = <1>; 2707 #size-cells = <0>; 2708 2709 ports { 2710 #address-cells = <1>; 2711 #size-cells = <0>; 2712 2713 port@0 { 2714 reg = <0>; 2715 dsi0_in: endpoint { 2716 remote-endpoint = <&dpu_intf1_out>; 2717 }; 2718 }; 2719 2720 port@1 { 2721 reg = <1>; 2722 dsi0_out: endpoint { 2723 }; 2724 }; 2725 }; 2726 }; 2727 2728 dsi0_phy: dsi-phy@ae94400 { 2729 compatible = "qcom,dsi-phy-7nm"; 2730 reg = <0 0x0ae94400 0 0x200>, 2731 <0 0x0ae94600 0 0x280>, 2732 <0 0x0ae94900 0 0x260>; 2733 reg-names = "dsi_phy", 2734 "dsi_phy_lane", 2735 "dsi_pll"; 2736 2737 #clock-cells = <1>; 2738 #phy-cells = <0>; 2739 2740 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2741 <&rpmhcc RPMH_CXO_CLK>; 2742 clock-names = "iface", "ref"; 2743 2744 status = "disabled"; 2745 }; 2746 2747 dsi1: dsi@ae96000 { 2748 compatible = "qcom,mdss-dsi-ctrl"; 2749 reg = <0 0x0ae96000 0 0x400>; 2750 reg-names = "dsi_ctrl"; 2751 2752 interrupt-parent = <&mdss>; 2753 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 2754 2755 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2756 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2757 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2758 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2759 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2760 <&gcc GCC_DISP_HF_AXI_CLK>; 2761 clock-names = "byte", 2762 "byte_intf", 2763 "pixel", 2764 "core", 2765 "iface", 2766 "bus"; 2767 2768 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2769 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 2770 2771 operating-points-v2 = <&dsi_opp_table>; 2772 power-domains = <&rpmhpd SM8250_MMCX>; 2773 2774 phys = <&dsi1_phy>; 2775 phy-names = "dsi"; 2776 2777 status = "disabled"; 2778 2779 #address-cells = <1>; 2780 #size-cells = <0>; 2781 2782 ports { 2783 #address-cells = <1>; 2784 #size-cells = <0>; 2785 2786 port@0 { 2787 reg = <0>; 2788 dsi1_in: endpoint { 2789 remote-endpoint = <&dpu_intf2_out>; 2790 }; 2791 }; 2792 2793 port@1 { 2794 reg = <1>; 2795 dsi1_out: endpoint { 2796 }; 2797 }; 2798 }; 2799 }; 2800 2801 dsi1_phy: dsi-phy@ae96400 { 2802 compatible = "qcom,dsi-phy-7nm"; 2803 reg = <0 0x0ae96400 0 0x200>, 2804 <0 0x0ae96600 0 0x280>, 2805 <0 0x0ae96900 0 0x260>; 2806 reg-names = "dsi_phy", 2807 "dsi_phy_lane", 2808 "dsi_pll"; 2809 2810 #clock-cells = <1>; 2811 #phy-cells = <0>; 2812 2813 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2814 <&rpmhcc RPMH_CXO_CLK>; 2815 clock-names = "iface", "ref"; 2816 2817 status = "disabled"; 2818 2819 dsi_opp_table: dsi-opp-table { 2820 compatible = "operating-points-v2"; 2821 2822 opp-187500000 { 2823 opp-hz = /bits/ 64 <187500000>; 2824 required-opps = <&rpmhpd_opp_low_svs>; 2825 }; 2826 2827 opp-300000000 { 2828 opp-hz = /bits/ 64 <300000000>; 2829 required-opps = <&rpmhpd_opp_svs>; 2830 }; 2831 2832 opp-358000000 { 2833 opp-hz = /bits/ 64 <358000000>; 2834 required-opps = <&rpmhpd_opp_svs_l1>; 2835 }; 2836 }; 2837 }; 2838 }; 2839 2840 dispcc: clock-controller@af00000 { 2841 compatible = "qcom,sm8250-dispcc"; 2842 reg = <0 0x0af00000 0 0x10000>; 2843 power-domains = <&rpmhpd SM8250_MMCX>; 2844 required-opps = <&rpmhpd_opp_low_svs>; 2845 clocks = <&rpmhcc RPMH_CXO_CLK>, 2846 <&dsi0_phy 0>, 2847 <&dsi0_phy 1>, 2848 <&dsi1_phy 0>, 2849 <&dsi1_phy 1>, 2850 <&dp_phy 0>, 2851 <&dp_phy 1>; 2852 clock-names = "bi_tcxo", 2853 "dsi0_phy_pll_out_byteclk", 2854 "dsi0_phy_pll_out_dsiclk", 2855 "dsi1_phy_pll_out_byteclk", 2856 "dsi1_phy_pll_out_dsiclk", 2857 "dp_phy_pll_link_clk", 2858 "dp_phy_pll_vco_div_clk"; 2859 #clock-cells = <1>; 2860 #reset-cells = <1>; 2861 #power-domain-cells = <1>; 2862 }; 2863 2864 pdc: interrupt-controller@b220000 { 2865 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 2866 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 2867 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2868 <125 63 1>, <126 716 12>; 2869 #interrupt-cells = <2>; 2870 interrupt-parent = <&intc>; 2871 interrupt-controller; 2872 }; 2873 2874 tsens0: thermal-sensor@c263000 { 2875 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 2876 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2877 <0 0x0c222000 0 0x1ff>; /* SROT */ 2878 #qcom,sensors = <16>; 2879 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2880 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2881 interrupt-names = "uplow", "critical"; 2882 #thermal-sensor-cells = <1>; 2883 }; 2884 2885 tsens1: thermal-sensor@c265000 { 2886 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 2887 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2888 <0 0x0c223000 0 0x1ff>; /* SROT */ 2889 #qcom,sensors = <9>; 2890 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2891 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2892 interrupt-names = "uplow", "critical"; 2893 #thermal-sensor-cells = <1>; 2894 }; 2895 2896 aoss_qmp: power-controller@c300000 { 2897 compatible = "qcom,sm8250-aoss-qmp"; 2898 reg = <0 0x0c300000 0 0x400>; 2899 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2900 IPCC_MPROC_SIGNAL_GLINK_QMP 2901 IRQ_TYPE_EDGE_RISING>; 2902 mboxes = <&ipcc IPCC_CLIENT_AOP 2903 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2904 2905 #clock-cells = <0>; 2906 }; 2907 2908 sram@c3f0000 { 2909 compatible = "qcom,rpmh-stats"; 2910 reg = <0 0x0c3f0000 0 0x400>; 2911 }; 2912 2913 spmi_bus: spmi@c440000 { 2914 compatible = "qcom,spmi-pmic-arb"; 2915 reg = <0x0 0x0c440000 0x0 0x0001100>, 2916 <0x0 0x0c600000 0x0 0x2000000>, 2917 <0x0 0x0e600000 0x0 0x0100000>, 2918 <0x0 0x0e700000 0x0 0x00a0000>, 2919 <0x0 0x0c40a000 0x0 0x0026000>; 2920 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2921 interrupt-names = "periph_irq"; 2922 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2923 qcom,ee = <0>; 2924 qcom,channel = <0>; 2925 #address-cells = <2>; 2926 #size-cells = <0>; 2927 interrupt-controller; 2928 #interrupt-cells = <4>; 2929 }; 2930 2931 tlmm: pinctrl@f100000 { 2932 compatible = "qcom,sm8250-pinctrl"; 2933 reg = <0 0x0f100000 0 0x300000>, 2934 <0 0x0f500000 0 0x300000>, 2935 <0 0x0f900000 0 0x300000>; 2936 reg-names = "west", "south", "north"; 2937 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2938 gpio-controller; 2939 #gpio-cells = <2>; 2940 interrupt-controller; 2941 #interrupt-cells = <2>; 2942 gpio-ranges = <&tlmm 0 0 181>; 2943 wakeup-parent = <&pdc>; 2944 2945 pri_mi2s_active: pri-mi2s-active { 2946 sclk { 2947 pins = "gpio138"; 2948 function = "mi2s0_sck"; 2949 drive-strength = <8>; 2950 bias-disable; 2951 }; 2952 2953 ws { 2954 pins = "gpio141"; 2955 function = "mi2s0_ws"; 2956 drive-strength = <8>; 2957 output-high; 2958 }; 2959 2960 data0 { 2961 pins = "gpio139"; 2962 function = "mi2s0_data0"; 2963 drive-strength = <8>; 2964 bias-disable; 2965 output-high; 2966 }; 2967 2968 data1 { 2969 pins = "gpio140"; 2970 function = "mi2s0_data1"; 2971 drive-strength = <8>; 2972 output-high; 2973 }; 2974 }; 2975 2976 qup_i2c0_default: qup-i2c0-default { 2977 mux { 2978 pins = "gpio28", "gpio29"; 2979 function = "qup0"; 2980 }; 2981 2982 config { 2983 pins = "gpio28", "gpio29"; 2984 drive-strength = <2>; 2985 bias-disable; 2986 }; 2987 }; 2988 2989 qup_i2c1_default: qup-i2c1-default { 2990 pinmux { 2991 pins = "gpio4", "gpio5"; 2992 function = "qup1"; 2993 }; 2994 2995 config { 2996 pins = "gpio4", "gpio5"; 2997 drive-strength = <2>; 2998 bias-disable; 2999 }; 3000 }; 3001 3002 qup_i2c2_default: qup-i2c2-default { 3003 mux { 3004 pins = "gpio115", "gpio116"; 3005 function = "qup2"; 3006 }; 3007 3008 config { 3009 pins = "gpio115", "gpio116"; 3010 drive-strength = <2>; 3011 bias-disable; 3012 }; 3013 }; 3014 3015 qup_i2c3_default: qup-i2c3-default { 3016 mux { 3017 pins = "gpio119", "gpio120"; 3018 function = "qup3"; 3019 }; 3020 3021 config { 3022 pins = "gpio119", "gpio120"; 3023 drive-strength = <2>; 3024 bias-disable; 3025 }; 3026 }; 3027 3028 qup_i2c4_default: qup-i2c4-default { 3029 mux { 3030 pins = "gpio8", "gpio9"; 3031 function = "qup4"; 3032 }; 3033 3034 config { 3035 pins = "gpio8", "gpio9"; 3036 drive-strength = <2>; 3037 bias-disable; 3038 }; 3039 }; 3040 3041 qup_i2c5_default: qup-i2c5-default { 3042 mux { 3043 pins = "gpio12", "gpio13"; 3044 function = "qup5"; 3045 }; 3046 3047 config { 3048 pins = "gpio12", "gpio13"; 3049 drive-strength = <2>; 3050 bias-disable; 3051 }; 3052 }; 3053 3054 qup_i2c6_default: qup-i2c6-default { 3055 mux { 3056 pins = "gpio16", "gpio17"; 3057 function = "qup6"; 3058 }; 3059 3060 config { 3061 pins = "gpio16", "gpio17"; 3062 drive-strength = <2>; 3063 bias-disable; 3064 }; 3065 }; 3066 3067 qup_i2c7_default: qup-i2c7-default { 3068 mux { 3069 pins = "gpio20", "gpio21"; 3070 function = "qup7"; 3071 }; 3072 3073 config { 3074 pins = "gpio20", "gpio21"; 3075 drive-strength = <2>; 3076 bias-disable; 3077 }; 3078 }; 3079 3080 qup_i2c8_default: qup-i2c8-default { 3081 mux { 3082 pins = "gpio24", "gpio25"; 3083 function = "qup8"; 3084 }; 3085 3086 config { 3087 pins = "gpio24", "gpio25"; 3088 drive-strength = <2>; 3089 bias-disable; 3090 }; 3091 }; 3092 3093 qup_i2c9_default: qup-i2c9-default { 3094 mux { 3095 pins = "gpio125", "gpio126"; 3096 function = "qup9"; 3097 }; 3098 3099 config { 3100 pins = "gpio125", "gpio126"; 3101 drive-strength = <2>; 3102 bias-disable; 3103 }; 3104 }; 3105 3106 qup_i2c10_default: qup-i2c10-default { 3107 mux { 3108 pins = "gpio129", "gpio130"; 3109 function = "qup10"; 3110 }; 3111 3112 config { 3113 pins = "gpio129", "gpio130"; 3114 drive-strength = <2>; 3115 bias-disable; 3116 }; 3117 }; 3118 3119 qup_i2c11_default: qup-i2c11-default { 3120 mux { 3121 pins = "gpio60", "gpio61"; 3122 function = "qup11"; 3123 }; 3124 3125 config { 3126 pins = "gpio60", "gpio61"; 3127 drive-strength = <2>; 3128 bias-disable; 3129 }; 3130 }; 3131 3132 qup_i2c12_default: qup-i2c12-default { 3133 mux { 3134 pins = "gpio32", "gpio33"; 3135 function = "qup12"; 3136 }; 3137 3138 config { 3139 pins = "gpio32", "gpio33"; 3140 drive-strength = <2>; 3141 bias-disable; 3142 }; 3143 }; 3144 3145 qup_i2c13_default: qup-i2c13-default { 3146 mux { 3147 pins = "gpio36", "gpio37"; 3148 function = "qup13"; 3149 }; 3150 3151 config { 3152 pins = "gpio36", "gpio37"; 3153 drive-strength = <2>; 3154 bias-disable; 3155 }; 3156 }; 3157 3158 qup_i2c14_default: qup-i2c14-default { 3159 mux { 3160 pins = "gpio40", "gpio41"; 3161 function = "qup14"; 3162 }; 3163 3164 config { 3165 pins = "gpio40", "gpio41"; 3166 drive-strength = <2>; 3167 bias-disable; 3168 }; 3169 }; 3170 3171 qup_i2c15_default: qup-i2c15-default { 3172 mux { 3173 pins = "gpio44", "gpio45"; 3174 function = "qup15"; 3175 }; 3176 3177 config { 3178 pins = "gpio44", "gpio45"; 3179 drive-strength = <2>; 3180 bias-disable; 3181 }; 3182 }; 3183 3184 qup_i2c16_default: qup-i2c16-default { 3185 mux { 3186 pins = "gpio48", "gpio49"; 3187 function = "qup16"; 3188 }; 3189 3190 config { 3191 pins = "gpio48", "gpio49"; 3192 drive-strength = <2>; 3193 bias-disable; 3194 }; 3195 }; 3196 3197 qup_i2c17_default: qup-i2c17-default { 3198 mux { 3199 pins = "gpio52", "gpio53"; 3200 function = "qup17"; 3201 }; 3202 3203 config { 3204 pins = "gpio52", "gpio53"; 3205 drive-strength = <2>; 3206 bias-disable; 3207 }; 3208 }; 3209 3210 qup_i2c18_default: qup-i2c18-default { 3211 mux { 3212 pins = "gpio56", "gpio57"; 3213 function = "qup18"; 3214 }; 3215 3216 config { 3217 pins = "gpio56", "gpio57"; 3218 drive-strength = <2>; 3219 bias-disable; 3220 }; 3221 }; 3222 3223 qup_i2c19_default: qup-i2c19-default { 3224 mux { 3225 pins = "gpio0", "gpio1"; 3226 function = "qup19"; 3227 }; 3228 3229 config { 3230 pins = "gpio0", "gpio1"; 3231 drive-strength = <2>; 3232 bias-disable; 3233 }; 3234 }; 3235 3236 qup_spi0_cs: qup-spi0-cs { 3237 pins = "gpio31"; 3238 function = "qup0"; 3239 }; 3240 3241 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3242 pins = "gpio31"; 3243 function = "gpio"; 3244 }; 3245 3246 qup_spi0_data_clk: qup-spi0-data-clk { 3247 pins = "gpio28", "gpio29", 3248 "gpio30"; 3249 function = "qup0"; 3250 }; 3251 3252 qup_spi1_cs: qup-spi1-cs { 3253 pins = "gpio7"; 3254 function = "qup1"; 3255 }; 3256 3257 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3258 pins = "gpio7"; 3259 function = "gpio"; 3260 }; 3261 3262 qup_spi1_data_clk: qup-spi1-data-clk { 3263 pins = "gpio4", "gpio5", 3264 "gpio6"; 3265 function = "qup1"; 3266 }; 3267 3268 qup_spi2_cs: qup-spi2-cs { 3269 pins = "gpio118"; 3270 function = "qup2"; 3271 }; 3272 3273 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3274 pins = "gpio118"; 3275 function = "gpio"; 3276 }; 3277 3278 qup_spi2_data_clk: qup-spi2-data-clk { 3279 pins = "gpio115", "gpio116", 3280 "gpio117"; 3281 function = "qup2"; 3282 }; 3283 3284 qup_spi3_cs: qup-spi3-cs { 3285 pins = "gpio122"; 3286 function = "qup3"; 3287 }; 3288 3289 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3290 pins = "gpio122"; 3291 function = "gpio"; 3292 }; 3293 3294 qup_spi3_data_clk: qup-spi3-data-clk { 3295 pins = "gpio119", "gpio120", 3296 "gpio121"; 3297 function = "qup3"; 3298 }; 3299 3300 qup_spi4_cs: qup-spi4-cs { 3301 pins = "gpio11"; 3302 function = "qup4"; 3303 }; 3304 3305 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3306 pins = "gpio11"; 3307 function = "gpio"; 3308 }; 3309 3310 qup_spi4_data_clk: qup-spi4-data-clk { 3311 pins = "gpio8", "gpio9", 3312 "gpio10"; 3313 function = "qup4"; 3314 }; 3315 3316 qup_spi5_cs: qup-spi5-cs { 3317 pins = "gpio15"; 3318 function = "qup5"; 3319 }; 3320 3321 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3322 pins = "gpio15"; 3323 function = "gpio"; 3324 }; 3325 3326 qup_spi5_data_clk: qup-spi5-data-clk { 3327 pins = "gpio12", "gpio13", 3328 "gpio14"; 3329 function = "qup5"; 3330 }; 3331 3332 qup_spi6_cs: qup-spi6-cs { 3333 pins = "gpio19"; 3334 function = "qup6"; 3335 }; 3336 3337 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3338 pins = "gpio19"; 3339 function = "gpio"; 3340 }; 3341 3342 qup_spi6_data_clk: qup-spi6-data-clk { 3343 pins = "gpio16", "gpio17", 3344 "gpio18"; 3345 function = "qup6"; 3346 }; 3347 3348 qup_spi7_cs: qup-spi7-cs { 3349 pins = "gpio23"; 3350 function = "qup7"; 3351 }; 3352 3353 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3354 pins = "gpio23"; 3355 function = "gpio"; 3356 }; 3357 3358 qup_spi7_data_clk: qup-spi7-data-clk { 3359 pins = "gpio20", "gpio21", 3360 "gpio22"; 3361 function = "qup7"; 3362 }; 3363 3364 qup_spi8_cs: qup-spi8-cs { 3365 pins = "gpio27"; 3366 function = "qup8"; 3367 }; 3368 3369 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3370 pins = "gpio27"; 3371 function = "gpio"; 3372 }; 3373 3374 qup_spi8_data_clk: qup-spi8-data-clk { 3375 pins = "gpio24", "gpio25", 3376 "gpio26"; 3377 function = "qup8"; 3378 }; 3379 3380 qup_spi9_cs: qup-spi9-cs { 3381 pins = "gpio128"; 3382 function = "qup9"; 3383 }; 3384 3385 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3386 pins = "gpio128"; 3387 function = "gpio"; 3388 }; 3389 3390 qup_spi9_data_clk: qup-spi9-data-clk { 3391 pins = "gpio125", "gpio126", 3392 "gpio127"; 3393 function = "qup9"; 3394 }; 3395 3396 qup_spi10_cs: qup-spi10-cs { 3397 pins = "gpio132"; 3398 function = "qup10"; 3399 }; 3400 3401 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3402 pins = "gpio132"; 3403 function = "gpio"; 3404 }; 3405 3406 qup_spi10_data_clk: qup-spi10-data-clk { 3407 pins = "gpio129", "gpio130", 3408 "gpio131"; 3409 function = "qup10"; 3410 }; 3411 3412 qup_spi11_cs: qup-spi11-cs { 3413 pins = "gpio63"; 3414 function = "qup11"; 3415 }; 3416 3417 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3418 pins = "gpio63"; 3419 function = "gpio"; 3420 }; 3421 3422 qup_spi11_data_clk: qup-spi11-data-clk { 3423 pins = "gpio60", "gpio61", 3424 "gpio62"; 3425 function = "qup11"; 3426 }; 3427 3428 qup_spi12_cs: qup-spi12-cs { 3429 pins = "gpio35"; 3430 function = "qup12"; 3431 }; 3432 3433 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3434 pins = "gpio35"; 3435 function = "gpio"; 3436 }; 3437 3438 qup_spi12_data_clk: qup-spi12-data-clk { 3439 pins = "gpio32", "gpio33", 3440 "gpio34"; 3441 function = "qup12"; 3442 }; 3443 3444 qup_spi13_cs: qup-spi13-cs { 3445 pins = "gpio39"; 3446 function = "qup13"; 3447 }; 3448 3449 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3450 pins = "gpio39"; 3451 function = "gpio"; 3452 }; 3453 3454 qup_spi13_data_clk: qup-spi13-data-clk { 3455 pins = "gpio36", "gpio37", 3456 "gpio38"; 3457 function = "qup13"; 3458 }; 3459 3460 qup_spi14_cs: qup-spi14-cs { 3461 pins = "gpio43"; 3462 function = "qup14"; 3463 }; 3464 3465 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3466 pins = "gpio43"; 3467 function = "gpio"; 3468 }; 3469 3470 qup_spi14_data_clk: qup-spi14-data-clk { 3471 pins = "gpio40", "gpio41", 3472 "gpio42"; 3473 function = "qup14"; 3474 }; 3475 3476 qup_spi15_cs: qup-spi15-cs { 3477 pins = "gpio47"; 3478 function = "qup15"; 3479 }; 3480 3481 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3482 pins = "gpio47"; 3483 function = "gpio"; 3484 }; 3485 3486 qup_spi15_data_clk: qup-spi15-data-clk { 3487 pins = "gpio44", "gpio45", 3488 "gpio46"; 3489 function = "qup15"; 3490 }; 3491 3492 qup_spi16_cs: qup-spi16-cs { 3493 pins = "gpio51"; 3494 function = "qup16"; 3495 }; 3496 3497 qup_spi16_cs_gpio: qup-spi16-cs-gpio { 3498 pins = "gpio51"; 3499 function = "gpio"; 3500 }; 3501 3502 qup_spi16_data_clk: qup-spi16-data-clk { 3503 pins = "gpio48", "gpio49", 3504 "gpio50"; 3505 function = "qup16"; 3506 }; 3507 3508 qup_spi17_cs: qup-spi17-cs { 3509 pins = "gpio55"; 3510 function = "qup17"; 3511 }; 3512 3513 qup_spi17_cs_gpio: qup-spi17-cs-gpio { 3514 pins = "gpio55"; 3515 function = "gpio"; 3516 }; 3517 3518 qup_spi17_data_clk: qup-spi17-data-clk { 3519 pins = "gpio52", "gpio53", 3520 "gpio54"; 3521 function = "qup17"; 3522 }; 3523 3524 qup_spi18_cs: qup-spi18-cs { 3525 pins = "gpio59"; 3526 function = "qup18"; 3527 }; 3528 3529 qup_spi18_cs_gpio: qup-spi18-cs-gpio { 3530 pins = "gpio59"; 3531 function = "gpio"; 3532 }; 3533 3534 qup_spi18_data_clk: qup-spi18-data-clk { 3535 pins = "gpio56", "gpio57", 3536 "gpio58"; 3537 function = "qup18"; 3538 }; 3539 3540 qup_spi19_cs: qup-spi19-cs { 3541 pins = "gpio3"; 3542 function = "qup19"; 3543 }; 3544 3545 qup_spi19_cs_gpio: qup-spi19-cs-gpio { 3546 pins = "gpio3"; 3547 function = "gpio"; 3548 }; 3549 3550 qup_spi19_data_clk: qup-spi19-data-clk { 3551 pins = "gpio0", "gpio1", 3552 "gpio2"; 3553 function = "qup19"; 3554 }; 3555 3556 qup_uart2_default: qup-uart2-default { 3557 mux { 3558 pins = "gpio117", "gpio118"; 3559 function = "qup2"; 3560 }; 3561 }; 3562 3563 qup_uart6_default: qup-uart6-default { 3564 mux { 3565 pins = "gpio16", "gpio17", 3566 "gpio18", "gpio19"; 3567 function = "qup6"; 3568 }; 3569 }; 3570 3571 qup_uart12_default: qup-uart12-default { 3572 mux { 3573 pins = "gpio34", "gpio35"; 3574 function = "qup12"; 3575 }; 3576 }; 3577 3578 qup_uart17_default: qup-uart17-default { 3579 mux { 3580 pins = "gpio52", "gpio53", 3581 "gpio54", "gpio55"; 3582 function = "qup17"; 3583 }; 3584 }; 3585 3586 qup_uart18_default: qup-uart18-default { 3587 mux { 3588 pins = "gpio58", "gpio59"; 3589 function = "qup18"; 3590 }; 3591 }; 3592 3593 tert_mi2s_active: tert-mi2s-active { 3594 sck { 3595 pins = "gpio133"; 3596 function = "mi2s2_sck"; 3597 drive-strength = <8>; 3598 bias-disable; 3599 }; 3600 3601 data0 { 3602 pins = "gpio134"; 3603 function = "mi2s2_data0"; 3604 drive-strength = <8>; 3605 bias-disable; 3606 output-high; 3607 }; 3608 3609 ws { 3610 pins = "gpio135"; 3611 function = "mi2s2_ws"; 3612 drive-strength = <8>; 3613 output-high; 3614 }; 3615 }; 3616 3617 sdc2_sleep_state: sdc2-sleep { 3618 clk { 3619 pins = "sdc2_clk"; 3620 drive-strength = <2>; 3621 bias-disable; 3622 }; 3623 3624 cmd { 3625 pins = "sdc2_cmd"; 3626 drive-strength = <2>; 3627 bias-pull-up; 3628 }; 3629 3630 data { 3631 pins = "sdc2_data"; 3632 drive-strength = <2>; 3633 bias-pull-up; 3634 }; 3635 }; 3636 3637 pcie0_default_state: pcie0-default { 3638 perst { 3639 pins = "gpio79"; 3640 function = "gpio"; 3641 drive-strength = <2>; 3642 bias-pull-down; 3643 }; 3644 3645 clkreq { 3646 pins = "gpio80"; 3647 function = "pci_e0"; 3648 drive-strength = <2>; 3649 bias-pull-up; 3650 }; 3651 3652 wake { 3653 pins = "gpio81"; 3654 function = "gpio"; 3655 drive-strength = <2>; 3656 bias-pull-up; 3657 }; 3658 }; 3659 3660 pcie1_default_state: pcie1-default { 3661 perst { 3662 pins = "gpio82"; 3663 function = "gpio"; 3664 drive-strength = <2>; 3665 bias-pull-down; 3666 }; 3667 3668 clkreq { 3669 pins = "gpio83"; 3670 function = "pci_e1"; 3671 drive-strength = <2>; 3672 bias-pull-up; 3673 }; 3674 3675 wake { 3676 pins = "gpio84"; 3677 function = "gpio"; 3678 drive-strength = <2>; 3679 bias-pull-up; 3680 }; 3681 }; 3682 3683 pcie2_default_state: pcie2-default { 3684 perst { 3685 pins = "gpio85"; 3686 function = "gpio"; 3687 drive-strength = <2>; 3688 bias-pull-down; 3689 }; 3690 3691 clkreq { 3692 pins = "gpio86"; 3693 function = "pci_e2"; 3694 drive-strength = <2>; 3695 bias-pull-up; 3696 }; 3697 3698 wake { 3699 pins = "gpio87"; 3700 function = "gpio"; 3701 drive-strength = <2>; 3702 bias-pull-up; 3703 }; 3704 }; 3705 }; 3706 3707 apps_smmu: iommu@15000000 { 3708 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 3709 reg = <0 0x15000000 0 0x100000>; 3710 #iommu-cells = <2>; 3711 #global-interrupts = <2>; 3712 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3713 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3714 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3715 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3716 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3717 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3718 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3719 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3720 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3721 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3722 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3723 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3724 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3725 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3726 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3727 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3728 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3729 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3730 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3731 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3732 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3733 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3734 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3735 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3736 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3737 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3738 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3739 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3740 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3741 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3742 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3743 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3744 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3745 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3746 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3747 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3748 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3749 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3750 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3751 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3752 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3753 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3754 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3755 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3756 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3757 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3758 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3759 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3760 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3761 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3762 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3763 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3764 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3765 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3766 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3770 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3771 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3773 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3782 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3783 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3784 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3785 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3786 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3787 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3788 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3789 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3790 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3792 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3793 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3794 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3795 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3796 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3798 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3799 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3800 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3801 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3802 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3803 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3804 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3805 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3806 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3807 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3808 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3809 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3810 }; 3811 3812 adsp: remoteproc@17300000 { 3813 compatible = "qcom,sm8250-adsp-pas"; 3814 reg = <0 0x17300000 0 0x100>; 3815 3816 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 3817 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3818 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3819 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3820 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3821 interrupt-names = "wdog", "fatal", "ready", 3822 "handover", "stop-ack"; 3823 3824 clocks = <&rpmhcc RPMH_CXO_CLK>; 3825 clock-names = "xo"; 3826 3827 power-domains = <&rpmhpd SM8250_LCX>, 3828 <&rpmhpd SM8250_LMX>; 3829 power-domain-names = "lcx", "lmx"; 3830 3831 memory-region = <&adsp_mem>; 3832 3833 qcom,qmp = <&aoss_qmp>; 3834 3835 qcom,smem-states = <&smp2p_adsp_out 0>; 3836 qcom,smem-state-names = "stop"; 3837 3838 status = "disabled"; 3839 3840 glink-edge { 3841 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3842 IPCC_MPROC_SIGNAL_GLINK_QMP 3843 IRQ_TYPE_EDGE_RISING>; 3844 mboxes = <&ipcc IPCC_CLIENT_LPASS 3845 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3846 3847 label = "lpass"; 3848 qcom,remote-pid = <2>; 3849 3850 apr { 3851 compatible = "qcom,apr-v2"; 3852 qcom,glink-channels = "apr_audio_svc"; 3853 qcom,apr-domain = <APR_DOMAIN_ADSP>; 3854 #address-cells = <1>; 3855 #size-cells = <0>; 3856 3857 apr-service@3 { 3858 reg = <APR_SVC_ADSP_CORE>; 3859 compatible = "qcom,q6core"; 3860 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3861 }; 3862 3863 q6afe: apr-service@4 { 3864 compatible = "qcom,q6afe"; 3865 reg = <APR_SVC_AFE>; 3866 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3867 q6afedai: dais { 3868 compatible = "qcom,q6afe-dais"; 3869 #address-cells = <1>; 3870 #size-cells = <0>; 3871 #sound-dai-cells = <1>; 3872 }; 3873 3874 q6afecc: cc { 3875 compatible = "qcom,q6afe-clocks"; 3876 #clock-cells = <2>; 3877 }; 3878 }; 3879 3880 q6asm: apr-service@7 { 3881 compatible = "qcom,q6asm"; 3882 reg = <APR_SVC_ASM>; 3883 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3884 q6asmdai: dais { 3885 compatible = "qcom,q6asm-dais"; 3886 #address-cells = <1>; 3887 #size-cells = <0>; 3888 #sound-dai-cells = <1>; 3889 iommus = <&apps_smmu 0x1801 0x0>; 3890 }; 3891 }; 3892 3893 q6adm: apr-service@8 { 3894 compatible = "qcom,q6adm"; 3895 reg = <APR_SVC_ADM>; 3896 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3897 q6routing: routing { 3898 compatible = "qcom,q6adm-routing"; 3899 #sound-dai-cells = <0>; 3900 }; 3901 }; 3902 }; 3903 3904 fastrpc { 3905 compatible = "qcom,fastrpc"; 3906 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3907 label = "adsp"; 3908 #address-cells = <1>; 3909 #size-cells = <0>; 3910 3911 compute-cb@3 { 3912 compatible = "qcom,fastrpc-compute-cb"; 3913 reg = <3>; 3914 iommus = <&apps_smmu 0x1803 0x0>; 3915 }; 3916 3917 compute-cb@4 { 3918 compatible = "qcom,fastrpc-compute-cb"; 3919 reg = <4>; 3920 iommus = <&apps_smmu 0x1804 0x0>; 3921 }; 3922 3923 compute-cb@5 { 3924 compatible = "qcom,fastrpc-compute-cb"; 3925 reg = <5>; 3926 iommus = <&apps_smmu 0x1805 0x0>; 3927 }; 3928 }; 3929 }; 3930 }; 3931 3932 intc: interrupt-controller@17a00000 { 3933 compatible = "arm,gic-v3"; 3934 #interrupt-cells = <3>; 3935 interrupt-controller; 3936 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3937 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3938 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3939 }; 3940 3941 watchdog@17c10000 { 3942 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 3943 reg = <0 0x17c10000 0 0x1000>; 3944 clocks = <&sleep_clk>; 3945 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3946 }; 3947 3948 timer@17c20000 { 3949 #address-cells = <2>; 3950 #size-cells = <2>; 3951 ranges; 3952 compatible = "arm,armv7-timer-mem"; 3953 reg = <0x0 0x17c20000 0x0 0x1000>; 3954 clock-frequency = <19200000>; 3955 3956 frame@17c21000 { 3957 frame-number = <0>; 3958 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3959 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3960 reg = <0x0 0x17c21000 0x0 0x1000>, 3961 <0x0 0x17c22000 0x0 0x1000>; 3962 }; 3963 3964 frame@17c23000 { 3965 frame-number = <1>; 3966 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3967 reg = <0x0 0x17c23000 0x0 0x1000>; 3968 status = "disabled"; 3969 }; 3970 3971 frame@17c25000 { 3972 frame-number = <2>; 3973 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3974 reg = <0x0 0x17c25000 0x0 0x1000>; 3975 status = "disabled"; 3976 }; 3977 3978 frame@17c27000 { 3979 frame-number = <3>; 3980 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3981 reg = <0x0 0x17c27000 0x0 0x1000>; 3982 status = "disabled"; 3983 }; 3984 3985 frame@17c29000 { 3986 frame-number = <4>; 3987 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3988 reg = <0x0 0x17c29000 0x0 0x1000>; 3989 status = "disabled"; 3990 }; 3991 3992 frame@17c2b000 { 3993 frame-number = <5>; 3994 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3995 reg = <0x0 0x17c2b000 0x0 0x1000>; 3996 status = "disabled"; 3997 }; 3998 3999 frame@17c2d000 { 4000 frame-number = <6>; 4001 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4002 reg = <0x0 0x17c2d000 0x0 0x1000>; 4003 status = "disabled"; 4004 }; 4005 }; 4006 4007 apps_rsc: rsc@18200000 { 4008 label = "apps_rsc"; 4009 compatible = "qcom,rpmh-rsc"; 4010 reg = <0x0 0x18200000 0x0 0x10000>, 4011 <0x0 0x18210000 0x0 0x10000>, 4012 <0x0 0x18220000 0x0 0x10000>; 4013 reg-names = "drv-0", "drv-1", "drv-2"; 4014 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4015 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4016 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4017 qcom,tcs-offset = <0xd00>; 4018 qcom,drv-id = <2>; 4019 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 4020 <WAKE_TCS 3>, <CONTROL_TCS 1>; 4021 4022 rpmhcc: clock-controller { 4023 compatible = "qcom,sm8250-rpmh-clk"; 4024 #clock-cells = <1>; 4025 clock-names = "xo"; 4026 clocks = <&xo_board>; 4027 }; 4028 4029 rpmhpd: power-controller { 4030 compatible = "qcom,sm8250-rpmhpd"; 4031 #power-domain-cells = <1>; 4032 operating-points-v2 = <&rpmhpd_opp_table>; 4033 4034 rpmhpd_opp_table: opp-table { 4035 compatible = "operating-points-v2"; 4036 4037 rpmhpd_opp_ret: opp1 { 4038 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4039 }; 4040 4041 rpmhpd_opp_min_svs: opp2 { 4042 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4043 }; 4044 4045 rpmhpd_opp_low_svs: opp3 { 4046 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4047 }; 4048 4049 rpmhpd_opp_svs: opp4 { 4050 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4051 }; 4052 4053 rpmhpd_opp_svs_l1: opp5 { 4054 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4055 }; 4056 4057 rpmhpd_opp_nom: opp6 { 4058 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4059 }; 4060 4061 rpmhpd_opp_nom_l1: opp7 { 4062 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4063 }; 4064 4065 rpmhpd_opp_nom_l2: opp8 { 4066 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4067 }; 4068 4069 rpmhpd_opp_turbo: opp9 { 4070 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4071 }; 4072 4073 rpmhpd_opp_turbo_l1: opp10 { 4074 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4075 }; 4076 }; 4077 }; 4078 4079 apps_bcm_voter: bcm_voter { 4080 compatible = "qcom,bcm-voter"; 4081 }; 4082 }; 4083 4084 epss_l3: interconnect@18590000 { 4085 compatible = "qcom,sm8250-epss-l3"; 4086 reg = <0 0x18590000 0 0x1000>; 4087 4088 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4089 clock-names = "xo", "alternate"; 4090 4091 #interconnect-cells = <1>; 4092 }; 4093 4094 cpufreq_hw: cpufreq@18591000 { 4095 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 4096 reg = <0 0x18591000 0 0x1000>, 4097 <0 0x18592000 0 0x1000>, 4098 <0 0x18593000 0 0x1000>; 4099 reg-names = "freq-domain0", "freq-domain1", 4100 "freq-domain2"; 4101 4102 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4103 clock-names = "xo", "alternate"; 4104 4105 #freq-domain-cells = <1>; 4106 }; 4107 }; 4108 4109 timer { 4110 compatible = "arm,armv8-timer"; 4111 interrupts = <GIC_PPI 13 4112 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4113 <GIC_PPI 14 4114 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4115 <GIC_PPI 11 4116 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4117 <GIC_PPI 10 4118 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4119 }; 4120 4121 thermal-zones { 4122 cpu0-thermal { 4123 polling-delay-passive = <250>; 4124 polling-delay = <1000>; 4125 4126 thermal-sensors = <&tsens0 1>; 4127 4128 trips { 4129 cpu0_alert0: trip-point0 { 4130 temperature = <90000>; 4131 hysteresis = <2000>; 4132 type = "passive"; 4133 }; 4134 4135 cpu0_alert1: trip-point1 { 4136 temperature = <95000>; 4137 hysteresis = <2000>; 4138 type = "passive"; 4139 }; 4140 4141 cpu0_crit: cpu_crit { 4142 temperature = <110000>; 4143 hysteresis = <1000>; 4144 type = "critical"; 4145 }; 4146 }; 4147 4148 cooling-maps { 4149 map0 { 4150 trip = <&cpu0_alert0>; 4151 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4152 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4153 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4154 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4155 }; 4156 map1 { 4157 trip = <&cpu0_alert1>; 4158 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4159 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4160 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4161 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4162 }; 4163 }; 4164 }; 4165 4166 cpu1-thermal { 4167 polling-delay-passive = <250>; 4168 polling-delay = <1000>; 4169 4170 thermal-sensors = <&tsens0 2>; 4171 4172 trips { 4173 cpu1_alert0: trip-point0 { 4174 temperature = <90000>; 4175 hysteresis = <2000>; 4176 type = "passive"; 4177 }; 4178 4179 cpu1_alert1: trip-point1 { 4180 temperature = <95000>; 4181 hysteresis = <2000>; 4182 type = "passive"; 4183 }; 4184 4185 cpu1_crit: cpu_crit { 4186 temperature = <110000>; 4187 hysteresis = <1000>; 4188 type = "critical"; 4189 }; 4190 }; 4191 4192 cooling-maps { 4193 map0 { 4194 trip = <&cpu1_alert0>; 4195 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4196 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4197 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4198 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4199 }; 4200 map1 { 4201 trip = <&cpu1_alert1>; 4202 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4203 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4204 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4205 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4206 }; 4207 }; 4208 }; 4209 4210 cpu2-thermal { 4211 polling-delay-passive = <250>; 4212 polling-delay = <1000>; 4213 4214 thermal-sensors = <&tsens0 3>; 4215 4216 trips { 4217 cpu2_alert0: trip-point0 { 4218 temperature = <90000>; 4219 hysteresis = <2000>; 4220 type = "passive"; 4221 }; 4222 4223 cpu2_alert1: trip-point1 { 4224 temperature = <95000>; 4225 hysteresis = <2000>; 4226 type = "passive"; 4227 }; 4228 4229 cpu2_crit: cpu_crit { 4230 temperature = <110000>; 4231 hysteresis = <1000>; 4232 type = "critical"; 4233 }; 4234 }; 4235 4236 cooling-maps { 4237 map0 { 4238 trip = <&cpu2_alert0>; 4239 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4240 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4241 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4242 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4243 }; 4244 map1 { 4245 trip = <&cpu2_alert1>; 4246 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4247 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4248 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4249 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4250 }; 4251 }; 4252 }; 4253 4254 cpu3-thermal { 4255 polling-delay-passive = <250>; 4256 polling-delay = <1000>; 4257 4258 thermal-sensors = <&tsens0 4>; 4259 4260 trips { 4261 cpu3_alert0: trip-point0 { 4262 temperature = <90000>; 4263 hysteresis = <2000>; 4264 type = "passive"; 4265 }; 4266 4267 cpu3_alert1: trip-point1 { 4268 temperature = <95000>; 4269 hysteresis = <2000>; 4270 type = "passive"; 4271 }; 4272 4273 cpu3_crit: cpu_crit { 4274 temperature = <110000>; 4275 hysteresis = <1000>; 4276 type = "critical"; 4277 }; 4278 }; 4279 4280 cooling-maps { 4281 map0 { 4282 trip = <&cpu3_alert0>; 4283 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4284 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4285 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4286 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4287 }; 4288 map1 { 4289 trip = <&cpu3_alert1>; 4290 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4291 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4292 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4293 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4294 }; 4295 }; 4296 }; 4297 4298 cpu4-top-thermal { 4299 polling-delay-passive = <250>; 4300 polling-delay = <1000>; 4301 4302 thermal-sensors = <&tsens0 7>; 4303 4304 trips { 4305 cpu4_top_alert0: trip-point0 { 4306 temperature = <90000>; 4307 hysteresis = <2000>; 4308 type = "passive"; 4309 }; 4310 4311 cpu4_top_alert1: trip-point1 { 4312 temperature = <95000>; 4313 hysteresis = <2000>; 4314 type = "passive"; 4315 }; 4316 4317 cpu4_top_crit: cpu_crit { 4318 temperature = <110000>; 4319 hysteresis = <1000>; 4320 type = "critical"; 4321 }; 4322 }; 4323 4324 cooling-maps { 4325 map0 { 4326 trip = <&cpu4_top_alert0>; 4327 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4328 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4329 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4330 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4331 }; 4332 map1 { 4333 trip = <&cpu4_top_alert1>; 4334 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4335 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4336 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4337 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4338 }; 4339 }; 4340 }; 4341 4342 cpu5-top-thermal { 4343 polling-delay-passive = <250>; 4344 polling-delay = <1000>; 4345 4346 thermal-sensors = <&tsens0 8>; 4347 4348 trips { 4349 cpu5_top_alert0: trip-point0 { 4350 temperature = <90000>; 4351 hysteresis = <2000>; 4352 type = "passive"; 4353 }; 4354 4355 cpu5_top_alert1: trip-point1 { 4356 temperature = <95000>; 4357 hysteresis = <2000>; 4358 type = "passive"; 4359 }; 4360 4361 cpu5_top_crit: cpu_crit { 4362 temperature = <110000>; 4363 hysteresis = <1000>; 4364 type = "critical"; 4365 }; 4366 }; 4367 4368 cooling-maps { 4369 map0 { 4370 trip = <&cpu5_top_alert0>; 4371 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4372 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4373 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4374 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4375 }; 4376 map1 { 4377 trip = <&cpu5_top_alert1>; 4378 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4379 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4380 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4381 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4382 }; 4383 }; 4384 }; 4385 4386 cpu6-top-thermal { 4387 polling-delay-passive = <250>; 4388 polling-delay = <1000>; 4389 4390 thermal-sensors = <&tsens0 9>; 4391 4392 trips { 4393 cpu6_top_alert0: trip-point0 { 4394 temperature = <90000>; 4395 hysteresis = <2000>; 4396 type = "passive"; 4397 }; 4398 4399 cpu6_top_alert1: trip-point1 { 4400 temperature = <95000>; 4401 hysteresis = <2000>; 4402 type = "passive"; 4403 }; 4404 4405 cpu6_top_crit: cpu_crit { 4406 temperature = <110000>; 4407 hysteresis = <1000>; 4408 type = "critical"; 4409 }; 4410 }; 4411 4412 cooling-maps { 4413 map0 { 4414 trip = <&cpu6_top_alert0>; 4415 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4416 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4417 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4418 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4419 }; 4420 map1 { 4421 trip = <&cpu6_top_alert1>; 4422 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4423 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4424 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4425 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4426 }; 4427 }; 4428 }; 4429 4430 cpu7-top-thermal { 4431 polling-delay-passive = <250>; 4432 polling-delay = <1000>; 4433 4434 thermal-sensors = <&tsens0 10>; 4435 4436 trips { 4437 cpu7_top_alert0: trip-point0 { 4438 temperature = <90000>; 4439 hysteresis = <2000>; 4440 type = "passive"; 4441 }; 4442 4443 cpu7_top_alert1: trip-point1 { 4444 temperature = <95000>; 4445 hysteresis = <2000>; 4446 type = "passive"; 4447 }; 4448 4449 cpu7_top_crit: cpu_crit { 4450 temperature = <110000>; 4451 hysteresis = <1000>; 4452 type = "critical"; 4453 }; 4454 }; 4455 4456 cooling-maps { 4457 map0 { 4458 trip = <&cpu7_top_alert0>; 4459 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4460 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4461 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4462 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4463 }; 4464 map1 { 4465 trip = <&cpu7_top_alert1>; 4466 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4467 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4468 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4469 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4470 }; 4471 }; 4472 }; 4473 4474 cpu4-bottom-thermal { 4475 polling-delay-passive = <250>; 4476 polling-delay = <1000>; 4477 4478 thermal-sensors = <&tsens0 11>; 4479 4480 trips { 4481 cpu4_bottom_alert0: trip-point0 { 4482 temperature = <90000>; 4483 hysteresis = <2000>; 4484 type = "passive"; 4485 }; 4486 4487 cpu4_bottom_alert1: trip-point1 { 4488 temperature = <95000>; 4489 hysteresis = <2000>; 4490 type = "passive"; 4491 }; 4492 4493 cpu4_bottom_crit: cpu_crit { 4494 temperature = <110000>; 4495 hysteresis = <1000>; 4496 type = "critical"; 4497 }; 4498 }; 4499 4500 cooling-maps { 4501 map0 { 4502 trip = <&cpu4_bottom_alert0>; 4503 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4504 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4505 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4506 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4507 }; 4508 map1 { 4509 trip = <&cpu4_bottom_alert1>; 4510 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4511 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4512 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4513 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4514 }; 4515 }; 4516 }; 4517 4518 cpu5-bottom-thermal { 4519 polling-delay-passive = <250>; 4520 polling-delay = <1000>; 4521 4522 thermal-sensors = <&tsens0 12>; 4523 4524 trips { 4525 cpu5_bottom_alert0: trip-point0 { 4526 temperature = <90000>; 4527 hysteresis = <2000>; 4528 type = "passive"; 4529 }; 4530 4531 cpu5_bottom_alert1: trip-point1 { 4532 temperature = <95000>; 4533 hysteresis = <2000>; 4534 type = "passive"; 4535 }; 4536 4537 cpu5_bottom_crit: cpu_crit { 4538 temperature = <110000>; 4539 hysteresis = <1000>; 4540 type = "critical"; 4541 }; 4542 }; 4543 4544 cooling-maps { 4545 map0 { 4546 trip = <&cpu5_bottom_alert0>; 4547 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4548 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4549 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4550 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4551 }; 4552 map1 { 4553 trip = <&cpu5_bottom_alert1>; 4554 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4555 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4556 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4557 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4558 }; 4559 }; 4560 }; 4561 4562 cpu6-bottom-thermal { 4563 polling-delay-passive = <250>; 4564 polling-delay = <1000>; 4565 4566 thermal-sensors = <&tsens0 13>; 4567 4568 trips { 4569 cpu6_bottom_alert0: trip-point0 { 4570 temperature = <90000>; 4571 hysteresis = <2000>; 4572 type = "passive"; 4573 }; 4574 4575 cpu6_bottom_alert1: trip-point1 { 4576 temperature = <95000>; 4577 hysteresis = <2000>; 4578 type = "passive"; 4579 }; 4580 4581 cpu6_bottom_crit: cpu_crit { 4582 temperature = <110000>; 4583 hysteresis = <1000>; 4584 type = "critical"; 4585 }; 4586 }; 4587 4588 cooling-maps { 4589 map0 { 4590 trip = <&cpu6_bottom_alert0>; 4591 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4592 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4593 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4594 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4595 }; 4596 map1 { 4597 trip = <&cpu6_bottom_alert1>; 4598 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4599 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4600 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4601 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4602 }; 4603 }; 4604 }; 4605 4606 cpu7-bottom-thermal { 4607 polling-delay-passive = <250>; 4608 polling-delay = <1000>; 4609 4610 thermal-sensors = <&tsens0 14>; 4611 4612 trips { 4613 cpu7_bottom_alert0: trip-point0 { 4614 temperature = <90000>; 4615 hysteresis = <2000>; 4616 type = "passive"; 4617 }; 4618 4619 cpu7_bottom_alert1: trip-point1 { 4620 temperature = <95000>; 4621 hysteresis = <2000>; 4622 type = "passive"; 4623 }; 4624 4625 cpu7_bottom_crit: cpu_crit { 4626 temperature = <110000>; 4627 hysteresis = <1000>; 4628 type = "critical"; 4629 }; 4630 }; 4631 4632 cooling-maps { 4633 map0 { 4634 trip = <&cpu7_bottom_alert0>; 4635 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4636 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4637 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4638 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4639 }; 4640 map1 { 4641 trip = <&cpu7_bottom_alert1>; 4642 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4643 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4644 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4645 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4646 }; 4647 }; 4648 }; 4649 4650 aoss0-thermal { 4651 polling-delay-passive = <250>; 4652 polling-delay = <1000>; 4653 4654 thermal-sensors = <&tsens0 0>; 4655 4656 trips { 4657 aoss0_alert0: trip-point0 { 4658 temperature = <90000>; 4659 hysteresis = <2000>; 4660 type = "hot"; 4661 }; 4662 }; 4663 }; 4664 4665 cluster0-thermal { 4666 polling-delay-passive = <250>; 4667 polling-delay = <1000>; 4668 4669 thermal-sensors = <&tsens0 5>; 4670 4671 trips { 4672 cluster0_alert0: trip-point0 { 4673 temperature = <90000>; 4674 hysteresis = <2000>; 4675 type = "hot"; 4676 }; 4677 cluster0_crit: cluster0_crit { 4678 temperature = <110000>; 4679 hysteresis = <2000>; 4680 type = "critical"; 4681 }; 4682 }; 4683 }; 4684 4685 cluster1-thermal { 4686 polling-delay-passive = <250>; 4687 polling-delay = <1000>; 4688 4689 thermal-sensors = <&tsens0 6>; 4690 4691 trips { 4692 cluster1_alert0: trip-point0 { 4693 temperature = <90000>; 4694 hysteresis = <2000>; 4695 type = "hot"; 4696 }; 4697 cluster1_crit: cluster1_crit { 4698 temperature = <110000>; 4699 hysteresis = <2000>; 4700 type = "critical"; 4701 }; 4702 }; 4703 }; 4704 4705 gpu-thermal-top { 4706 polling-delay-passive = <250>; 4707 polling-delay = <1000>; 4708 4709 thermal-sensors = <&tsens0 15>; 4710 4711 trips { 4712 gpu1_alert0: trip-point0 { 4713 temperature = <90000>; 4714 hysteresis = <2000>; 4715 type = "hot"; 4716 }; 4717 }; 4718 }; 4719 4720 aoss1-thermal { 4721 polling-delay-passive = <250>; 4722 polling-delay = <1000>; 4723 4724 thermal-sensors = <&tsens1 0>; 4725 4726 trips { 4727 aoss1_alert0: trip-point0 { 4728 temperature = <90000>; 4729 hysteresis = <2000>; 4730 type = "hot"; 4731 }; 4732 }; 4733 }; 4734 4735 wlan-thermal { 4736 polling-delay-passive = <250>; 4737 polling-delay = <1000>; 4738 4739 thermal-sensors = <&tsens1 1>; 4740 4741 trips { 4742 wlan_alert0: trip-point0 { 4743 temperature = <90000>; 4744 hysteresis = <2000>; 4745 type = "hot"; 4746 }; 4747 }; 4748 }; 4749 4750 video-thermal { 4751 polling-delay-passive = <250>; 4752 polling-delay = <1000>; 4753 4754 thermal-sensors = <&tsens1 2>; 4755 4756 trips { 4757 video_alert0: trip-point0 { 4758 temperature = <90000>; 4759 hysteresis = <2000>; 4760 type = "hot"; 4761 }; 4762 }; 4763 }; 4764 4765 mem-thermal { 4766 polling-delay-passive = <250>; 4767 polling-delay = <1000>; 4768 4769 thermal-sensors = <&tsens1 3>; 4770 4771 trips { 4772 mem_alert0: trip-point0 { 4773 temperature = <90000>; 4774 hysteresis = <2000>; 4775 type = "hot"; 4776 }; 4777 }; 4778 }; 4779 4780 q6-hvx-thermal { 4781 polling-delay-passive = <250>; 4782 polling-delay = <1000>; 4783 4784 thermal-sensors = <&tsens1 4>; 4785 4786 trips { 4787 q6_hvx_alert0: trip-point0 { 4788 temperature = <90000>; 4789 hysteresis = <2000>; 4790 type = "hot"; 4791 }; 4792 }; 4793 }; 4794 4795 camera-thermal { 4796 polling-delay-passive = <250>; 4797 polling-delay = <1000>; 4798 4799 thermal-sensors = <&tsens1 5>; 4800 4801 trips { 4802 camera_alert0: trip-point0 { 4803 temperature = <90000>; 4804 hysteresis = <2000>; 4805 type = "hot"; 4806 }; 4807 }; 4808 }; 4809 4810 compute-thermal { 4811 polling-delay-passive = <250>; 4812 polling-delay = <1000>; 4813 4814 thermal-sensors = <&tsens1 6>; 4815 4816 trips { 4817 compute_alert0: trip-point0 { 4818 temperature = <90000>; 4819 hysteresis = <2000>; 4820 type = "hot"; 4821 }; 4822 }; 4823 }; 4824 4825 npu-thermal { 4826 polling-delay-passive = <250>; 4827 polling-delay = <1000>; 4828 4829 thermal-sensors = <&tsens1 7>; 4830 4831 trips { 4832 npu_alert0: trip-point0 { 4833 temperature = <90000>; 4834 hysteresis = <2000>; 4835 type = "hot"; 4836 }; 4837 }; 4838 }; 4839 4840 gpu-thermal-bottom { 4841 polling-delay-passive = <250>; 4842 polling-delay = <1000>; 4843 4844 thermal-sensors = <&tsens1 8>; 4845 4846 trips { 4847 gpu2_alert0: trip-point0 { 4848 temperature = <90000>; 4849 hysteresis = <2000>; 4850 type = "hot"; 4851 }; 4852 }; 4853 }; 4854 }; 4855}; 4856