1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sm8250.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-aoss-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/soc/qcom,apr.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/sound/qcom,q6afe.h> 21#include <dt-bindings/thermal/thermal.h> 22#include <dt-bindings/clock/qcom,videocc-sm8250.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 aliases { 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 i2c8 = &i2c8; 40 i2c9 = &i2c9; 41 i2c10 = &i2c10; 42 i2c11 = &i2c11; 43 i2c12 = &i2c12; 44 i2c13 = &i2c13; 45 i2c14 = &i2c14; 46 i2c15 = &i2c15; 47 i2c16 = &i2c16; 48 i2c17 = &i2c17; 49 i2c18 = &i2c18; 50 i2c19 = &i2c19; 51 spi0 = &spi0; 52 spi1 = &spi1; 53 spi2 = &spi2; 54 spi3 = &spi3; 55 spi4 = &spi4; 56 spi5 = &spi5; 57 spi6 = &spi6; 58 spi7 = &spi7; 59 spi8 = &spi8; 60 spi9 = &spi9; 61 spi10 = &spi10; 62 spi11 = &spi11; 63 spi12 = &spi12; 64 spi13 = &spi13; 65 spi14 = &spi14; 66 spi15 = &spi15; 67 spi16 = &spi16; 68 spi17 = &spi17; 69 spi18 = &spi18; 70 spi19 = &spi19; 71 }; 72 73 chosen { }; 74 75 clocks { 76 xo_board: xo-board { 77 compatible = "fixed-clock"; 78 #clock-cells = <0>; 79 clock-frequency = <38400000>; 80 clock-output-names = "xo_board"; 81 }; 82 83 sleep_clk: sleep-clk { 84 compatible = "fixed-clock"; 85 clock-frequency = <32768>; 86 #clock-cells = <0>; 87 }; 88 }; 89 90 cpus { 91 #address-cells = <2>; 92 #size-cells = <0>; 93 94 CPU0: cpu@0 { 95 device_type = "cpu"; 96 compatible = "qcom,kryo485"; 97 reg = <0x0 0x0>; 98 enable-method = "psci"; 99 capacity-dmips-mhz = <448>; 100 dynamic-power-coefficient = <205>; 101 next-level-cache = <&L2_0>; 102 qcom,freq-domain = <&cpufreq_hw 0>; 103 #cooling-cells = <2>; 104 L2_0: l2-cache { 105 compatible = "cache"; 106 next-level-cache = <&L3_0>; 107 L3_0: l3-cache { 108 compatible = "cache"; 109 }; 110 }; 111 }; 112 113 CPU1: cpu@100 { 114 device_type = "cpu"; 115 compatible = "qcom,kryo485"; 116 reg = <0x0 0x100>; 117 enable-method = "psci"; 118 capacity-dmips-mhz = <448>; 119 dynamic-power-coefficient = <205>; 120 next-level-cache = <&L2_100>; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 #cooling-cells = <2>; 123 L2_100: l2-cache { 124 compatible = "cache"; 125 next-level-cache = <&L3_0>; 126 }; 127 }; 128 129 CPU2: cpu@200 { 130 device_type = "cpu"; 131 compatible = "qcom,kryo485"; 132 reg = <0x0 0x200>; 133 enable-method = "psci"; 134 capacity-dmips-mhz = <448>; 135 dynamic-power-coefficient = <205>; 136 next-level-cache = <&L2_200>; 137 qcom,freq-domain = <&cpufreq_hw 0>; 138 #cooling-cells = <2>; 139 L2_200: l2-cache { 140 compatible = "cache"; 141 next-level-cache = <&L3_0>; 142 }; 143 }; 144 145 CPU3: cpu@300 { 146 device_type = "cpu"; 147 compatible = "qcom,kryo485"; 148 reg = <0x0 0x300>; 149 enable-method = "psci"; 150 capacity-dmips-mhz = <448>; 151 dynamic-power-coefficient = <205>; 152 next-level-cache = <&L2_300>; 153 qcom,freq-domain = <&cpufreq_hw 0>; 154 #cooling-cells = <2>; 155 L2_300: l2-cache { 156 compatible = "cache"; 157 next-level-cache = <&L3_0>; 158 }; 159 }; 160 161 CPU4: cpu@400 { 162 device_type = "cpu"; 163 compatible = "qcom,kryo485"; 164 reg = <0x0 0x400>; 165 enable-method = "psci"; 166 capacity-dmips-mhz = <1024>; 167 dynamic-power-coefficient = <379>; 168 next-level-cache = <&L2_400>; 169 qcom,freq-domain = <&cpufreq_hw 1>; 170 #cooling-cells = <2>; 171 L2_400: l2-cache { 172 compatible = "cache"; 173 next-level-cache = <&L3_0>; 174 }; 175 }; 176 177 CPU5: cpu@500 { 178 device_type = "cpu"; 179 compatible = "qcom,kryo485"; 180 reg = <0x0 0x500>; 181 enable-method = "psci"; 182 capacity-dmips-mhz = <1024>; 183 dynamic-power-coefficient = <379>; 184 next-level-cache = <&L2_500>; 185 qcom,freq-domain = <&cpufreq_hw 1>; 186 #cooling-cells = <2>; 187 L2_500: l2-cache { 188 compatible = "cache"; 189 next-level-cache = <&L3_0>; 190 }; 191 192 }; 193 194 CPU6: cpu@600 { 195 device_type = "cpu"; 196 compatible = "qcom,kryo485"; 197 reg = <0x0 0x600>; 198 enable-method = "psci"; 199 capacity-dmips-mhz = <1024>; 200 dynamic-power-coefficient = <379>; 201 next-level-cache = <&L2_600>; 202 qcom,freq-domain = <&cpufreq_hw 1>; 203 #cooling-cells = <2>; 204 L2_600: l2-cache { 205 compatible = "cache"; 206 next-level-cache = <&L3_0>; 207 }; 208 }; 209 210 CPU7: cpu@700 { 211 device_type = "cpu"; 212 compatible = "qcom,kryo485"; 213 reg = <0x0 0x700>; 214 enable-method = "psci"; 215 capacity-dmips-mhz = <1024>; 216 dynamic-power-coefficient = <444>; 217 next-level-cache = <&L2_700>; 218 qcom,freq-domain = <&cpufreq_hw 2>; 219 #cooling-cells = <2>; 220 L2_700: l2-cache { 221 compatible = "cache"; 222 next-level-cache = <&L3_0>; 223 }; 224 }; 225 226 cpu-map { 227 cluster0 { 228 core0 { 229 cpu = <&CPU0>; 230 }; 231 232 core1 { 233 cpu = <&CPU1>; 234 }; 235 236 core2 { 237 cpu = <&CPU2>; 238 }; 239 240 core3 { 241 cpu = <&CPU3>; 242 }; 243 244 core4 { 245 cpu = <&CPU4>; 246 }; 247 248 core5 { 249 cpu = <&CPU5>; 250 }; 251 252 core6 { 253 cpu = <&CPU6>; 254 }; 255 256 core7 { 257 cpu = <&CPU7>; 258 }; 259 }; 260 }; 261 }; 262 263 firmware { 264 scm: scm { 265 compatible = "qcom,scm"; 266 #reset-cells = <1>; 267 }; 268 }; 269 270 memory@80000000 { 271 device_type = "memory"; 272 /* We expect the bootloader to fill in the size */ 273 reg = <0x0 0x80000000 0x0 0x0>; 274 }; 275 276 mmcx_reg: mmcx-reg { 277 compatible = "regulator-fixed-domain"; 278 power-domains = <&rpmhpd SM8250_MMCX>; 279 required-opps = <&rpmhpd_opp_low_svs>; 280 regulator-name = "MMCX"; 281 }; 282 283 pmu { 284 compatible = "arm,armv8-pmuv3"; 285 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 286 }; 287 288 psci { 289 compatible = "arm,psci-1.0"; 290 method = "smc"; 291 }; 292 293 reserved-memory { 294 #address-cells = <2>; 295 #size-cells = <2>; 296 ranges; 297 298 hyp_mem: memory@80000000 { 299 reg = <0x0 0x80000000 0x0 0x600000>; 300 no-map; 301 }; 302 303 xbl_aop_mem: memory@80700000 { 304 reg = <0x0 0x80700000 0x0 0x160000>; 305 no-map; 306 }; 307 308 cmd_db: memory@80860000 { 309 compatible = "qcom,cmd-db"; 310 reg = <0x0 0x80860000 0x0 0x20000>; 311 no-map; 312 }; 313 314 smem_mem: memory@80900000 { 315 reg = <0x0 0x80900000 0x0 0x200000>; 316 no-map; 317 }; 318 319 removed_mem: memory@80b00000 { 320 reg = <0x0 0x80b00000 0x0 0x5300000>; 321 no-map; 322 }; 323 324 camera_mem: memory@86200000 { 325 reg = <0x0 0x86200000 0x0 0x500000>; 326 no-map; 327 }; 328 329 wlan_mem: memory@86700000 { 330 reg = <0x0 0x86700000 0x0 0x100000>; 331 no-map; 332 }; 333 334 ipa_fw_mem: memory@86800000 { 335 reg = <0x0 0x86800000 0x0 0x10000>; 336 no-map; 337 }; 338 339 ipa_gsi_mem: memory@86810000 { 340 reg = <0x0 0x86810000 0x0 0xa000>; 341 no-map; 342 }; 343 344 gpu_mem: memory@8681a000 { 345 reg = <0x0 0x8681a000 0x0 0x2000>; 346 no-map; 347 }; 348 349 npu_mem: memory@86900000 { 350 reg = <0x0 0x86900000 0x0 0x500000>; 351 no-map; 352 }; 353 354 video_mem: memory@86e00000 { 355 reg = <0x0 0x86e00000 0x0 0x500000>; 356 no-map; 357 }; 358 359 cvp_mem: memory@87300000 { 360 reg = <0x0 0x87300000 0x0 0x500000>; 361 no-map; 362 }; 363 364 cdsp_mem: memory@87800000 { 365 reg = <0x0 0x87800000 0x0 0x1400000>; 366 no-map; 367 }; 368 369 slpi_mem: memory@88c00000 { 370 reg = <0x0 0x88c00000 0x0 0x1500000>; 371 no-map; 372 }; 373 374 adsp_mem: memory@8a100000 { 375 reg = <0x0 0x8a100000 0x0 0x1d00000>; 376 no-map; 377 }; 378 379 spss_mem: memory@8be00000 { 380 reg = <0x0 0x8be00000 0x0 0x100000>; 381 no-map; 382 }; 383 384 cdsp_secure_heap: memory@8bf00000 { 385 reg = <0x0 0x8bf00000 0x0 0x4600000>; 386 no-map; 387 }; 388 }; 389 390 smem { 391 compatible = "qcom,smem"; 392 memory-region = <&smem_mem>; 393 hwlocks = <&tcsr_mutex 3>; 394 }; 395 396 smp2p-adsp { 397 compatible = "qcom,smp2p"; 398 qcom,smem = <443>, <429>; 399 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 400 IPCC_MPROC_SIGNAL_SMP2P 401 IRQ_TYPE_EDGE_RISING>; 402 mboxes = <&ipcc IPCC_CLIENT_LPASS 403 IPCC_MPROC_SIGNAL_SMP2P>; 404 405 qcom,local-pid = <0>; 406 qcom,remote-pid = <2>; 407 408 smp2p_adsp_out: master-kernel { 409 qcom,entry-name = "master-kernel"; 410 #qcom,smem-state-cells = <1>; 411 }; 412 413 smp2p_adsp_in: slave-kernel { 414 qcom,entry-name = "slave-kernel"; 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 }; 418 }; 419 420 smp2p-cdsp { 421 compatible = "qcom,smp2p"; 422 qcom,smem = <94>, <432>; 423 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 424 IPCC_MPROC_SIGNAL_SMP2P 425 IRQ_TYPE_EDGE_RISING>; 426 mboxes = <&ipcc IPCC_CLIENT_CDSP 427 IPCC_MPROC_SIGNAL_SMP2P>; 428 429 qcom,local-pid = <0>; 430 qcom,remote-pid = <5>; 431 432 smp2p_cdsp_out: master-kernel { 433 qcom,entry-name = "master-kernel"; 434 #qcom,smem-state-cells = <1>; 435 }; 436 437 smp2p_cdsp_in: slave-kernel { 438 qcom,entry-name = "slave-kernel"; 439 interrupt-controller; 440 #interrupt-cells = <2>; 441 }; 442 }; 443 444 smp2p-slpi { 445 compatible = "qcom,smp2p"; 446 qcom,smem = <481>, <430>; 447 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 448 IPCC_MPROC_SIGNAL_SMP2P 449 IRQ_TYPE_EDGE_RISING>; 450 mboxes = <&ipcc IPCC_CLIENT_SLPI 451 IPCC_MPROC_SIGNAL_SMP2P>; 452 453 qcom,local-pid = <0>; 454 qcom,remote-pid = <3>; 455 456 smp2p_slpi_out: master-kernel { 457 qcom,entry-name = "master-kernel"; 458 #qcom,smem-state-cells = <1>; 459 }; 460 461 smp2p_slpi_in: slave-kernel { 462 qcom,entry-name = "slave-kernel"; 463 interrupt-controller; 464 #interrupt-cells = <2>; 465 }; 466 }; 467 468 soc: soc@0 { 469 #address-cells = <2>; 470 #size-cells = <2>; 471 ranges = <0 0 0 0 0x10 0>; 472 dma-ranges = <0 0 0 0 0x10 0>; 473 compatible = "simple-bus"; 474 475 gcc: clock-controller@100000 { 476 compatible = "qcom,gcc-sm8250"; 477 reg = <0x0 0x00100000 0x0 0x1f0000>; 478 #clock-cells = <1>; 479 #reset-cells = <1>; 480 #power-domain-cells = <1>; 481 clock-names = "bi_tcxo", 482 "bi_tcxo_ao", 483 "sleep_clk"; 484 clocks = <&rpmhcc RPMH_CXO_CLK>, 485 <&rpmhcc RPMH_CXO_CLK_A>, 486 <&sleep_clk>; 487 }; 488 489 ipcc: mailbox@408000 { 490 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 491 reg = <0 0x00408000 0 0x1000>; 492 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 493 interrupt-controller; 494 #interrupt-cells = <3>; 495 #mbox-cells = <2>; 496 }; 497 498 rng: rng@793000 { 499 compatible = "qcom,prng-ee"; 500 reg = <0 0x00793000 0 0x1000>; 501 clocks = <&gcc GCC_PRNG_AHB_CLK>; 502 clock-names = "core"; 503 }; 504 505 qup_opp_table: qup-opp-table { 506 compatible = "operating-points-v2"; 507 508 opp-50000000 { 509 opp-hz = /bits/ 64 <50000000>; 510 required-opps = <&rpmhpd_opp_min_svs>; 511 }; 512 513 opp-75000000 { 514 opp-hz = /bits/ 64 <75000000>; 515 required-opps = <&rpmhpd_opp_low_svs>; 516 }; 517 518 opp-120000000 { 519 opp-hz = /bits/ 64 <120000000>; 520 required-opps = <&rpmhpd_opp_svs>; 521 }; 522 }; 523 524 gpi_dma2: dma-controller@800000 { 525 compatible = "qcom,sm8250-gpi-dma"; 526 reg = <0 0x00800000 0 0x70000>; 527 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 537 dma-channels = <10>; 538 dma-channel-mask = <0x3f>; 539 iommus = <&apps_smmu 0x76 0x0>; 540 #dma-cells = <3>; 541 status = "disabled"; 542 }; 543 544 qupv3_id_2: geniqup@8c0000 { 545 compatible = "qcom,geni-se-qup"; 546 reg = <0x0 0x008c0000 0x0 0x6000>; 547 clock-names = "m-ahb", "s-ahb"; 548 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 549 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 550 #address-cells = <2>; 551 #size-cells = <2>; 552 iommus = <&apps_smmu 0x63 0x0>; 553 ranges; 554 status = "disabled"; 555 556 i2c14: i2c@880000 { 557 compatible = "qcom,geni-i2c"; 558 reg = <0 0x00880000 0 0x4000>; 559 clock-names = "se"; 560 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&qup_i2c14_default>; 563 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 564 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 565 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 566 dma-names = "tx", "rx"; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 status = "disabled"; 570 }; 571 572 spi14: spi@880000 { 573 compatible = "qcom,geni-spi"; 574 reg = <0 0x00880000 0 0x4000>; 575 clock-names = "se"; 576 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 577 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 578 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 579 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 580 dma-names = "tx", "rx"; 581 power-domains = <&rpmhpd SM8250_CX>; 582 operating-points-v2 = <&qup_opp_table>; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 status = "disabled"; 586 }; 587 588 i2c15: i2c@884000 { 589 compatible = "qcom,geni-i2c"; 590 reg = <0 0x00884000 0 0x4000>; 591 clock-names = "se"; 592 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 593 pinctrl-names = "default"; 594 pinctrl-0 = <&qup_i2c15_default>; 595 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 596 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 597 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 598 dma-names = "tx", "rx"; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 status = "disabled"; 602 }; 603 604 spi15: spi@884000 { 605 compatible = "qcom,geni-spi"; 606 reg = <0 0x00884000 0 0x4000>; 607 clock-names = "se"; 608 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 609 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 610 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 611 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 612 dma-names = "tx", "rx"; 613 power-domains = <&rpmhpd SM8250_CX>; 614 operating-points-v2 = <&qup_opp_table>; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 status = "disabled"; 618 }; 619 620 i2c16: i2c@888000 { 621 compatible = "qcom,geni-i2c"; 622 reg = <0 0x00888000 0 0x4000>; 623 clock-names = "se"; 624 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 625 pinctrl-names = "default"; 626 pinctrl-0 = <&qup_i2c16_default>; 627 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 628 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 629 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 630 dma-names = "tx", "rx"; 631 #address-cells = <1>; 632 #size-cells = <0>; 633 status = "disabled"; 634 }; 635 636 spi16: spi@888000 { 637 compatible = "qcom,geni-spi"; 638 reg = <0 0x00888000 0 0x4000>; 639 clock-names = "se"; 640 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 641 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 642 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 643 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 644 dma-names = "tx", "rx"; 645 power-domains = <&rpmhpd SM8250_CX>; 646 operating-points-v2 = <&qup_opp_table>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 status = "disabled"; 650 }; 651 652 i2c17: i2c@88c000 { 653 compatible = "qcom,geni-i2c"; 654 reg = <0 0x0088c000 0 0x4000>; 655 clock-names = "se"; 656 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 657 pinctrl-names = "default"; 658 pinctrl-0 = <&qup_i2c17_default>; 659 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 660 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 661 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 662 dma-names = "tx", "rx"; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 status = "disabled"; 666 }; 667 668 spi17: spi@88c000 { 669 compatible = "qcom,geni-spi"; 670 reg = <0 0x0088c000 0 0x4000>; 671 clock-names = "se"; 672 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 673 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 674 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 675 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 676 dma-names = "tx", "rx"; 677 power-domains = <&rpmhpd SM8250_CX>; 678 operating-points-v2 = <&qup_opp_table>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 status = "disabled"; 682 }; 683 684 uart17: serial@88c000 { 685 compatible = "qcom,geni-uart"; 686 reg = <0 0x0088c000 0 0x4000>; 687 clock-names = "se"; 688 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 689 pinctrl-names = "default"; 690 pinctrl-0 = <&qup_uart17_default>; 691 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 692 power-domains = <&rpmhpd SM8250_CX>; 693 operating-points-v2 = <&qup_opp_table>; 694 status = "disabled"; 695 }; 696 697 i2c18: i2c@890000 { 698 compatible = "qcom,geni-i2c"; 699 reg = <0 0x00890000 0 0x4000>; 700 clock-names = "se"; 701 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 702 pinctrl-names = "default"; 703 pinctrl-0 = <&qup_i2c18_default>; 704 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 705 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 706 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 707 dma-names = "tx", "rx"; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 status = "disabled"; 711 }; 712 713 spi18: spi@890000 { 714 compatible = "qcom,geni-spi"; 715 reg = <0 0x00890000 0 0x4000>; 716 clock-names = "se"; 717 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 718 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 719 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 720 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 721 dma-names = "tx", "rx"; 722 power-domains = <&rpmhpd SM8250_CX>; 723 operating-points-v2 = <&qup_opp_table>; 724 #address-cells = <1>; 725 #size-cells = <0>; 726 status = "disabled"; 727 }; 728 729 uart18: serial@890000 { 730 compatible = "qcom,geni-uart"; 731 reg = <0 0x00890000 0 0x4000>; 732 clock-names = "se"; 733 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 734 pinctrl-names = "default"; 735 pinctrl-0 = <&qup_uart18_default>; 736 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 737 power-domains = <&rpmhpd SM8250_CX>; 738 operating-points-v2 = <&qup_opp_table>; 739 status = "disabled"; 740 }; 741 742 i2c19: i2c@894000 { 743 compatible = "qcom,geni-i2c"; 744 reg = <0 0x00894000 0 0x4000>; 745 clock-names = "se"; 746 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 747 pinctrl-names = "default"; 748 pinctrl-0 = <&qup_i2c19_default>; 749 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 750 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 751 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 752 dma-names = "tx", "rx"; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 status = "disabled"; 756 }; 757 758 spi19: spi@894000 { 759 compatible = "qcom,geni-spi"; 760 reg = <0 0x00894000 0 0x4000>; 761 clock-names = "se"; 762 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 763 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 764 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 765 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 766 dma-names = "tx", "rx"; 767 power-domains = <&rpmhpd SM8250_CX>; 768 operating-points-v2 = <&qup_opp_table>; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 status = "disabled"; 772 }; 773 }; 774 775 gpi_dma0: dma-controller@900000 { 776 compatible = "qcom,sm8250-gpi-dma"; 777 reg = <0 0x00900000 0 0x70000>; 778 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 791 dma-channels = <15>; 792 dma-channel-mask = <0x7ff>; 793 iommus = <&apps_smmu 0x5b6 0x0>; 794 #dma-cells = <3>; 795 status = "disabled"; 796 }; 797 798 qupv3_id_0: geniqup@9c0000 { 799 compatible = "qcom,geni-se-qup"; 800 reg = <0x0 0x009c0000 0x0 0x6000>; 801 clock-names = "m-ahb", "s-ahb"; 802 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 803 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 804 #address-cells = <2>; 805 #size-cells = <2>; 806 iommus = <&apps_smmu 0x5a3 0x0>; 807 ranges; 808 status = "disabled"; 809 810 i2c0: i2c@980000 { 811 compatible = "qcom,geni-i2c"; 812 reg = <0 0x00980000 0 0x4000>; 813 clock-names = "se"; 814 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 815 pinctrl-names = "default"; 816 pinctrl-0 = <&qup_i2c0_default>; 817 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 818 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 819 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 820 dma-names = "tx", "rx"; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 status = "disabled"; 824 }; 825 826 spi0: spi@980000 { 827 compatible = "qcom,geni-spi"; 828 reg = <0 0x00980000 0 0x4000>; 829 clock-names = "se"; 830 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 831 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 832 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 833 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 834 dma-names = "tx", "rx"; 835 power-domains = <&rpmhpd SM8250_CX>; 836 operating-points-v2 = <&qup_opp_table>; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 status = "disabled"; 840 }; 841 842 i2c1: i2c@984000 { 843 compatible = "qcom,geni-i2c"; 844 reg = <0 0x00984000 0 0x4000>; 845 clock-names = "se"; 846 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 847 pinctrl-names = "default"; 848 pinctrl-0 = <&qup_i2c1_default>; 849 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 850 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 851 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 852 dma-names = "tx", "rx"; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 status = "disabled"; 856 }; 857 858 spi1: spi@984000 { 859 compatible = "qcom,geni-spi"; 860 reg = <0 0x00984000 0 0x4000>; 861 clock-names = "se"; 862 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 863 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 864 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 865 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 866 dma-names = "tx", "rx"; 867 power-domains = <&rpmhpd SM8250_CX>; 868 operating-points-v2 = <&qup_opp_table>; 869 #address-cells = <1>; 870 #size-cells = <0>; 871 status = "disabled"; 872 }; 873 874 i2c2: i2c@988000 { 875 compatible = "qcom,geni-i2c"; 876 reg = <0 0x00988000 0 0x4000>; 877 clock-names = "se"; 878 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 879 pinctrl-names = "default"; 880 pinctrl-0 = <&qup_i2c2_default>; 881 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 882 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 883 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 884 dma-names = "tx", "rx"; 885 #address-cells = <1>; 886 #size-cells = <0>; 887 status = "disabled"; 888 }; 889 890 spi2: spi@988000 { 891 compatible = "qcom,geni-spi"; 892 reg = <0 0x00988000 0 0x4000>; 893 clock-names = "se"; 894 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 895 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 896 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 897 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 898 dma-names = "tx", "rx"; 899 power-domains = <&rpmhpd SM8250_CX>; 900 operating-points-v2 = <&qup_opp_table>; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 status = "disabled"; 904 }; 905 906 uart2: serial@988000 { 907 compatible = "qcom,geni-debug-uart"; 908 reg = <0 0x00988000 0 0x4000>; 909 clock-names = "se"; 910 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 911 pinctrl-names = "default"; 912 pinctrl-0 = <&qup_uart2_default>; 913 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 914 power-domains = <&rpmhpd SM8250_CX>; 915 operating-points-v2 = <&qup_opp_table>; 916 status = "disabled"; 917 }; 918 919 i2c3: i2c@98c000 { 920 compatible = "qcom,geni-i2c"; 921 reg = <0 0x0098c000 0 0x4000>; 922 clock-names = "se"; 923 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 924 pinctrl-names = "default"; 925 pinctrl-0 = <&qup_i2c3_default>; 926 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 927 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 928 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 929 dma-names = "tx", "rx"; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 status = "disabled"; 933 }; 934 935 spi3: spi@98c000 { 936 compatible = "qcom,geni-spi"; 937 reg = <0 0x0098c000 0 0x4000>; 938 clock-names = "se"; 939 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 940 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 941 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 942 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 943 dma-names = "tx", "rx"; 944 power-domains = <&rpmhpd SM8250_CX>; 945 operating-points-v2 = <&qup_opp_table>; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 status = "disabled"; 949 }; 950 951 i2c4: i2c@990000 { 952 compatible = "qcom,geni-i2c"; 953 reg = <0 0x00990000 0 0x4000>; 954 clock-names = "se"; 955 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 956 pinctrl-names = "default"; 957 pinctrl-0 = <&qup_i2c4_default>; 958 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 959 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 960 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 961 dma-names = "tx", "rx"; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 status = "disabled"; 965 }; 966 967 spi4: spi@990000 { 968 compatible = "qcom,geni-spi"; 969 reg = <0 0x00990000 0 0x4000>; 970 clock-names = "se"; 971 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 972 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 973 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 974 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 975 dma-names = "tx", "rx"; 976 power-domains = <&rpmhpd SM8250_CX>; 977 operating-points-v2 = <&qup_opp_table>; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 status = "disabled"; 981 }; 982 983 i2c5: i2c@994000 { 984 compatible = "qcom,geni-i2c"; 985 reg = <0 0x00994000 0 0x4000>; 986 clock-names = "se"; 987 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 988 pinctrl-names = "default"; 989 pinctrl-0 = <&qup_i2c5_default>; 990 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 991 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 992 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 993 dma-names = "tx", "rx"; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 status = "disabled"; 997 }; 998 999 spi5: spi@994000 { 1000 compatible = "qcom,geni-spi"; 1001 reg = <0 0x00994000 0 0x4000>; 1002 clock-names = "se"; 1003 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1004 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1005 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1006 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1007 dma-names = "tx", "rx"; 1008 power-domains = <&rpmhpd SM8250_CX>; 1009 operating-points-v2 = <&qup_opp_table>; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 status = "disabled"; 1013 }; 1014 1015 i2c6: i2c@998000 { 1016 compatible = "qcom,geni-i2c"; 1017 reg = <0 0x00998000 0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&qup_i2c6_default>; 1022 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1023 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1024 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1025 dma-names = "tx", "rx"; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 status = "disabled"; 1029 }; 1030 1031 spi6: spi@998000 { 1032 compatible = "qcom,geni-spi"; 1033 reg = <0 0x00998000 0 0x4000>; 1034 clock-names = "se"; 1035 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1036 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1037 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1038 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1039 dma-names = "tx", "rx"; 1040 power-domains = <&rpmhpd SM8250_CX>; 1041 operating-points-v2 = <&qup_opp_table>; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 status = "disabled"; 1045 }; 1046 1047 uart6: serial@998000 { 1048 compatible = "qcom,geni-uart"; 1049 reg = <0 0x00998000 0 0x4000>; 1050 clock-names = "se"; 1051 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1052 pinctrl-names = "default"; 1053 pinctrl-0 = <&qup_uart6_default>; 1054 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1055 power-domains = <&rpmhpd SM8250_CX>; 1056 operating-points-v2 = <&qup_opp_table>; 1057 status = "disabled"; 1058 }; 1059 1060 i2c7: i2c@99c000 { 1061 compatible = "qcom,geni-i2c"; 1062 reg = <0 0x0099c000 0 0x4000>; 1063 clock-names = "se"; 1064 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1065 pinctrl-names = "default"; 1066 pinctrl-0 = <&qup_i2c7_default>; 1067 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1068 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1069 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1070 dma-names = "tx", "rx"; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 status = "disabled"; 1074 }; 1075 1076 spi7: spi@99c000 { 1077 compatible = "qcom,geni-spi"; 1078 reg = <0 0x0099c000 0 0x4000>; 1079 clock-names = "se"; 1080 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1081 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1082 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1083 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1084 dma-names = "tx", "rx"; 1085 power-domains = <&rpmhpd SM8250_CX>; 1086 operating-points-v2 = <&qup_opp_table>; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 status = "disabled"; 1090 }; 1091 }; 1092 1093 gpi_dma1: dma-controller@a00000 { 1094 compatible = "qcom,sm8250-gpi-dma"; 1095 reg = <0 0x00a00000 0 0x70000>; 1096 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1106 dma-channels = <10>; 1107 dma-channel-mask = <0x3f>; 1108 iommus = <&apps_smmu 0x56 0x0>; 1109 #dma-cells = <3>; 1110 status = "disabled"; 1111 }; 1112 1113 qupv3_id_1: geniqup@ac0000 { 1114 compatible = "qcom,geni-se-qup"; 1115 reg = <0x0 0x00ac0000 0x0 0x6000>; 1116 clock-names = "m-ahb", "s-ahb"; 1117 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1118 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1119 #address-cells = <2>; 1120 #size-cells = <2>; 1121 iommus = <&apps_smmu 0x43 0x0>; 1122 ranges; 1123 status = "disabled"; 1124 1125 i2c8: i2c@a80000 { 1126 compatible = "qcom,geni-i2c"; 1127 reg = <0 0x00a80000 0 0x4000>; 1128 clock-names = "se"; 1129 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1130 pinctrl-names = "default"; 1131 pinctrl-0 = <&qup_i2c8_default>; 1132 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1133 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1134 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1135 dma-names = "tx", "rx"; 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 status = "disabled"; 1139 }; 1140 1141 spi8: spi@a80000 { 1142 compatible = "qcom,geni-spi"; 1143 reg = <0 0x00a80000 0 0x4000>; 1144 clock-names = "se"; 1145 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1146 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1147 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1148 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1149 dma-names = "tx", "rx"; 1150 power-domains = <&rpmhpd SM8250_CX>; 1151 operating-points-v2 = <&qup_opp_table>; 1152 #address-cells = <1>; 1153 #size-cells = <0>; 1154 status = "disabled"; 1155 }; 1156 1157 i2c9: i2c@a84000 { 1158 compatible = "qcom,geni-i2c"; 1159 reg = <0 0x00a84000 0 0x4000>; 1160 clock-names = "se"; 1161 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&qup_i2c9_default>; 1164 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1165 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1166 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1167 dma-names = "tx", "rx"; 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 status = "disabled"; 1171 }; 1172 1173 spi9: spi@a84000 { 1174 compatible = "qcom,geni-spi"; 1175 reg = <0 0x00a84000 0 0x4000>; 1176 clock-names = "se"; 1177 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1178 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1179 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1180 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1181 dma-names = "tx", "rx"; 1182 power-domains = <&rpmhpd SM8250_CX>; 1183 operating-points-v2 = <&qup_opp_table>; 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 status = "disabled"; 1187 }; 1188 1189 i2c10: i2c@a88000 { 1190 compatible = "qcom,geni-i2c"; 1191 reg = <0 0x00a88000 0 0x4000>; 1192 clock-names = "se"; 1193 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1194 pinctrl-names = "default"; 1195 pinctrl-0 = <&qup_i2c10_default>; 1196 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1197 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1198 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1199 dma-names = "tx", "rx"; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 status = "disabled"; 1203 }; 1204 1205 spi10: spi@a88000 { 1206 compatible = "qcom,geni-spi"; 1207 reg = <0 0x00a88000 0 0x4000>; 1208 clock-names = "se"; 1209 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1210 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1211 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1212 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1213 dma-names = "tx", "rx"; 1214 power-domains = <&rpmhpd SM8250_CX>; 1215 operating-points-v2 = <&qup_opp_table>; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 status = "disabled"; 1219 }; 1220 1221 i2c11: i2c@a8c000 { 1222 compatible = "qcom,geni-i2c"; 1223 reg = <0 0x00a8c000 0 0x4000>; 1224 clock-names = "se"; 1225 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1226 pinctrl-names = "default"; 1227 pinctrl-0 = <&qup_i2c11_default>; 1228 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1229 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1230 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1231 dma-names = "tx", "rx"; 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 status = "disabled"; 1235 }; 1236 1237 spi11: spi@a8c000 { 1238 compatible = "qcom,geni-spi"; 1239 reg = <0 0x00a8c000 0 0x4000>; 1240 clock-names = "se"; 1241 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1242 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1243 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1244 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1245 dma-names = "tx", "rx"; 1246 power-domains = <&rpmhpd SM8250_CX>; 1247 operating-points-v2 = <&qup_opp_table>; 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 status = "disabled"; 1251 }; 1252 1253 i2c12: i2c@a90000 { 1254 compatible = "qcom,geni-i2c"; 1255 reg = <0 0x00a90000 0 0x4000>; 1256 clock-names = "se"; 1257 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1258 pinctrl-names = "default"; 1259 pinctrl-0 = <&qup_i2c12_default>; 1260 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1261 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1262 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1263 dma-names = "tx", "rx"; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 status = "disabled"; 1267 }; 1268 1269 spi12: spi@a90000 { 1270 compatible = "qcom,geni-spi"; 1271 reg = <0 0x00a90000 0 0x4000>; 1272 clock-names = "se"; 1273 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1274 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1275 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1276 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1277 dma-names = "tx", "rx"; 1278 power-domains = <&rpmhpd SM8250_CX>; 1279 operating-points-v2 = <&qup_opp_table>; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 status = "disabled"; 1283 }; 1284 1285 uart12: serial@a90000 { 1286 compatible = "qcom,geni-debug-uart"; 1287 reg = <0x0 0x00a90000 0x0 0x4000>; 1288 clock-names = "se"; 1289 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1290 pinctrl-names = "default"; 1291 pinctrl-0 = <&qup_uart12_default>; 1292 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1293 power-domains = <&rpmhpd SM8250_CX>; 1294 operating-points-v2 = <&qup_opp_table>; 1295 status = "disabled"; 1296 }; 1297 1298 i2c13: i2c@a94000 { 1299 compatible = "qcom,geni-i2c"; 1300 reg = <0 0x00a94000 0 0x4000>; 1301 clock-names = "se"; 1302 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1303 pinctrl-names = "default"; 1304 pinctrl-0 = <&qup_i2c13_default>; 1305 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1306 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1307 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1308 dma-names = "tx", "rx"; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 status = "disabled"; 1312 }; 1313 1314 spi13: spi@a94000 { 1315 compatible = "qcom,geni-spi"; 1316 reg = <0 0x00a94000 0 0x4000>; 1317 clock-names = "se"; 1318 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1319 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1320 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1321 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1322 dma-names = "tx", "rx"; 1323 power-domains = <&rpmhpd SM8250_CX>; 1324 operating-points-v2 = <&qup_opp_table>; 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 status = "disabled"; 1328 }; 1329 }; 1330 1331 config_noc: interconnect@1500000 { 1332 compatible = "qcom,sm8250-config-noc"; 1333 reg = <0 0x01500000 0 0xa580>; 1334 #interconnect-cells = <1>; 1335 qcom,bcm-voters = <&apps_bcm_voter>; 1336 }; 1337 1338 system_noc: interconnect@1620000 { 1339 compatible = "qcom,sm8250-system-noc"; 1340 reg = <0 0x01620000 0 0x1c200>; 1341 #interconnect-cells = <1>; 1342 qcom,bcm-voters = <&apps_bcm_voter>; 1343 }; 1344 1345 mc_virt: interconnect@163d000 { 1346 compatible = "qcom,sm8250-mc-virt"; 1347 reg = <0 0x0163d000 0 0x1000>; 1348 #interconnect-cells = <1>; 1349 qcom,bcm-voters = <&apps_bcm_voter>; 1350 }; 1351 1352 aggre1_noc: interconnect@16e0000 { 1353 compatible = "qcom,sm8250-aggre1-noc"; 1354 reg = <0 0x016e0000 0 0x1f180>; 1355 #interconnect-cells = <1>; 1356 qcom,bcm-voters = <&apps_bcm_voter>; 1357 }; 1358 1359 aggre2_noc: interconnect@1700000 { 1360 compatible = "qcom,sm8250-aggre2-noc"; 1361 reg = <0 0x01700000 0 0x33000>; 1362 #interconnect-cells = <1>; 1363 qcom,bcm-voters = <&apps_bcm_voter>; 1364 }; 1365 1366 compute_noc: interconnect@1733000 { 1367 compatible = "qcom,sm8250-compute-noc"; 1368 reg = <0 0x01733000 0 0xa180>; 1369 #interconnect-cells = <1>; 1370 qcom,bcm-voters = <&apps_bcm_voter>; 1371 }; 1372 1373 mmss_noc: interconnect@1740000 { 1374 compatible = "qcom,sm8250-mmss-noc"; 1375 reg = <0 0x01740000 0 0x1f080>; 1376 #interconnect-cells = <1>; 1377 qcom,bcm-voters = <&apps_bcm_voter>; 1378 }; 1379 1380 pcie0: pci@1c00000 { 1381 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1382 reg = <0 0x01c00000 0 0x3000>, 1383 <0 0x60000000 0 0xf1d>, 1384 <0 0x60000f20 0 0xa8>, 1385 <0 0x60001000 0 0x1000>, 1386 <0 0x60100000 0 0x100000>; 1387 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1388 device_type = "pci"; 1389 linux,pci-domain = <0>; 1390 bus-range = <0x00 0xff>; 1391 num-lanes = <1>; 1392 1393 #address-cells = <3>; 1394 #size-cells = <2>; 1395 1396 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1397 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1398 1399 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1400 interrupt-names = "msi"; 1401 #interrupt-cells = <1>; 1402 interrupt-map-mask = <0 0 0 0x7>; 1403 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1404 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1405 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1406 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1407 1408 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1409 <&gcc GCC_PCIE_0_AUX_CLK>, 1410 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1411 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1412 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1413 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1414 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1415 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1416 clock-names = "pipe", 1417 "aux", 1418 "cfg", 1419 "bus_master", 1420 "bus_slave", 1421 "slave_q2a", 1422 "tbu", 1423 "ddrss_sf_tbu"; 1424 1425 iommus = <&apps_smmu 0x1c00 0x7f>; 1426 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1427 <0x100 &apps_smmu 0x1c01 0x1>; 1428 1429 resets = <&gcc GCC_PCIE_0_BCR>; 1430 reset-names = "pci"; 1431 1432 power-domains = <&gcc PCIE_0_GDSC>; 1433 1434 phys = <&pcie0_lane>; 1435 phy-names = "pciephy"; 1436 1437 perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; 1438 enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; 1439 1440 pinctrl-names = "default"; 1441 pinctrl-0 = <&pcie0_default_state>; 1442 1443 status = "disabled"; 1444 }; 1445 1446 pcie0_phy: phy@1c06000 { 1447 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1448 reg = <0 0x01c06000 0 0x1c0>; 1449 #address-cells = <2>; 1450 #size-cells = <2>; 1451 ranges; 1452 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1453 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1454 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1455 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1456 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1457 1458 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1459 reset-names = "phy"; 1460 1461 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1462 assigned-clock-rates = <100000000>; 1463 1464 status = "disabled"; 1465 1466 pcie0_lane: lanes@1c06200 { 1467 reg = <0 0x1c06200 0 0x170>, /* tx */ 1468 <0 0x1c06400 0 0x200>, /* rx */ 1469 <0 0x1c06800 0 0x1f0>, /* pcs */ 1470 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1471 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1472 clock-names = "pipe0"; 1473 1474 #phy-cells = <0>; 1475 clock-output-names = "pcie_0_pipe_clk"; 1476 }; 1477 }; 1478 1479 pcie1: pci@1c08000 { 1480 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1481 reg = <0 0x01c08000 0 0x3000>, 1482 <0 0x40000000 0 0xf1d>, 1483 <0 0x40000f20 0 0xa8>, 1484 <0 0x40001000 0 0x1000>, 1485 <0 0x40100000 0 0x100000>; 1486 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1487 device_type = "pci"; 1488 linux,pci-domain = <1>; 1489 bus-range = <0x00 0xff>; 1490 num-lanes = <2>; 1491 1492 #address-cells = <3>; 1493 #size-cells = <2>; 1494 1495 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1496 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1497 1498 interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>; 1499 interrupt-names = "msi"; 1500 #interrupt-cells = <1>; 1501 interrupt-map-mask = <0 0 0 0x7>; 1502 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1503 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1504 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1505 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1506 1507 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1508 <&gcc GCC_PCIE_1_AUX_CLK>, 1509 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1510 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1511 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1512 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1513 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1514 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1515 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1516 clock-names = "pipe", 1517 "aux", 1518 "cfg", 1519 "bus_master", 1520 "bus_slave", 1521 "slave_q2a", 1522 "ref", 1523 "tbu", 1524 "ddrss_sf_tbu"; 1525 1526 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1527 assigned-clock-rates = <19200000>; 1528 1529 iommus = <&apps_smmu 0x1c80 0x7f>; 1530 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1531 <0x100 &apps_smmu 0x1c81 0x1>; 1532 1533 resets = <&gcc GCC_PCIE_1_BCR>; 1534 reset-names = "pci"; 1535 1536 power-domains = <&gcc PCIE_1_GDSC>; 1537 1538 phys = <&pcie1_lane>; 1539 phy-names = "pciephy"; 1540 1541 perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>; 1542 enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; 1543 1544 pinctrl-names = "default"; 1545 pinctrl-0 = <&pcie1_default_state>; 1546 1547 status = "disabled"; 1548 }; 1549 1550 pcie1_phy: phy@1c0e000 { 1551 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1552 reg = <0 0x01c0e000 0 0x1c0>; 1553 #address-cells = <2>; 1554 #size-cells = <2>; 1555 ranges; 1556 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1557 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1558 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1559 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1560 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1561 1562 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1563 reset-names = "phy"; 1564 1565 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1566 assigned-clock-rates = <100000000>; 1567 1568 status = "disabled"; 1569 1570 pcie1_lane: lanes@1c0e200 { 1571 reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1572 <0 0x1c0e400 0 0x200>, /* rx0 */ 1573 <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1574 <0 0x1c0e600 0 0x170>, /* tx1 */ 1575 <0 0x1c0e800 0 0x200>, /* rx1 */ 1576 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1577 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1578 clock-names = "pipe0"; 1579 1580 #phy-cells = <0>; 1581 clock-output-names = "pcie_1_pipe_clk"; 1582 }; 1583 }; 1584 1585 pcie2: pci@1c10000 { 1586 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1587 reg = <0 0x01c10000 0 0x3000>, 1588 <0 0x64000000 0 0xf1d>, 1589 <0 0x64000f20 0 0xa8>, 1590 <0 0x64001000 0 0x1000>, 1591 <0 0x64100000 0 0x100000>; 1592 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1593 device_type = "pci"; 1594 linux,pci-domain = <2>; 1595 bus-range = <0x00 0xff>; 1596 num-lanes = <2>; 1597 1598 #address-cells = <3>; 1599 #size-cells = <2>; 1600 1601 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, 1602 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 1603 1604 interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; 1605 interrupt-names = "msi"; 1606 #interrupt-cells = <1>; 1607 interrupt-map-mask = <0 0 0 0x7>; 1608 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1609 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1610 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1611 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1612 1613 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1614 <&gcc GCC_PCIE_2_AUX_CLK>, 1615 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1616 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1617 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 1618 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 1619 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1620 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1621 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1622 clock-names = "pipe", 1623 "aux", 1624 "cfg", 1625 "bus_master", 1626 "bus_slave", 1627 "slave_q2a", 1628 "ref", 1629 "tbu", 1630 "ddrss_sf_tbu"; 1631 1632 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 1633 assigned-clock-rates = <19200000>; 1634 1635 iommus = <&apps_smmu 0x1d00 0x7f>; 1636 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 1637 <0x100 &apps_smmu 0x1d01 0x1>; 1638 1639 resets = <&gcc GCC_PCIE_2_BCR>; 1640 reset-names = "pci"; 1641 1642 power-domains = <&gcc PCIE_2_GDSC>; 1643 1644 phys = <&pcie2_lane>; 1645 phy-names = "pciephy"; 1646 1647 perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>; 1648 enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; 1649 1650 pinctrl-names = "default"; 1651 pinctrl-0 = <&pcie2_default_state>; 1652 1653 status = "disabled"; 1654 }; 1655 1656 pcie2_phy: phy@1c16000 { 1657 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 1658 reg = <0 0x1c16000 0 0x1c0>; 1659 #address-cells = <2>; 1660 #size-cells = <2>; 1661 ranges; 1662 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1663 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1664 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1665 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1666 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1667 1668 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 1669 reset-names = "phy"; 1670 1671 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1672 assigned-clock-rates = <100000000>; 1673 1674 status = "disabled"; 1675 1676 pcie2_lane: lanes@1c16200 { 1677 reg = <0 0x1c16200 0 0x170>, /* tx0 */ 1678 <0 0x1c16400 0 0x200>, /* rx0 */ 1679 <0 0x1c16a00 0 0x1f0>, /* pcs */ 1680 <0 0x1c16600 0 0x170>, /* tx1 */ 1681 <0 0x1c16800 0 0x200>, /* rx1 */ 1682 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1683 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 1684 clock-names = "pipe0"; 1685 1686 #phy-cells = <0>; 1687 clock-output-names = "pcie_2_pipe_clk"; 1688 }; 1689 }; 1690 1691 ufs_mem_hc: ufshc@1d84000 { 1692 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 1693 "jedec,ufs-2.0"; 1694 reg = <0 0x01d84000 0 0x3000>; 1695 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1696 phys = <&ufs_mem_phy_lanes>; 1697 phy-names = "ufsphy"; 1698 lanes-per-direction = <2>; 1699 #reset-cells = <1>; 1700 resets = <&gcc GCC_UFS_PHY_BCR>; 1701 reset-names = "rst"; 1702 1703 power-domains = <&gcc UFS_PHY_GDSC>; 1704 1705 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 1706 1707 clock-names = 1708 "core_clk", 1709 "bus_aggr_clk", 1710 "iface_clk", 1711 "core_clk_unipro", 1712 "ref_clk", 1713 "tx_lane0_sync_clk", 1714 "rx_lane0_sync_clk", 1715 "rx_lane1_sync_clk"; 1716 clocks = 1717 <&gcc GCC_UFS_PHY_AXI_CLK>, 1718 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1719 <&gcc GCC_UFS_PHY_AHB_CLK>, 1720 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1721 <&rpmhcc RPMH_CXO_CLK>, 1722 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1723 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1724 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1725 freq-table-hz = 1726 <37500000 300000000>, 1727 <0 0>, 1728 <0 0>, 1729 <37500000 300000000>, 1730 <0 0>, 1731 <0 0>, 1732 <0 0>, 1733 <0 0>; 1734 1735 status = "disabled"; 1736 }; 1737 1738 ufs_mem_phy: phy@1d87000 { 1739 compatible = "qcom,sm8250-qmp-ufs-phy"; 1740 reg = <0 0x01d87000 0 0x1c0>; 1741 #address-cells = <2>; 1742 #size-cells = <2>; 1743 ranges; 1744 clock-names = "ref", 1745 "ref_aux"; 1746 clocks = <&rpmhcc RPMH_CXO_CLK>, 1747 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1748 1749 resets = <&ufs_mem_hc 0>; 1750 reset-names = "ufsphy"; 1751 status = "disabled"; 1752 1753 ufs_mem_phy_lanes: lanes@1d87400 { 1754 reg = <0 0x01d87400 0 0x108>, 1755 <0 0x01d87600 0 0x1e0>, 1756 <0 0x01d87c00 0 0x1dc>, 1757 <0 0x01d87800 0 0x108>, 1758 <0 0x01d87a00 0 0x1e0>; 1759 #phy-cells = <0>; 1760 }; 1761 }; 1762 1763 ipa_virt: interconnect@1e00000 { 1764 compatible = "qcom,sm8250-ipa-virt"; 1765 reg = <0 0x01e00000 0 0x1000>; 1766 #interconnect-cells = <1>; 1767 qcom,bcm-voters = <&apps_bcm_voter>; 1768 }; 1769 1770 tcsr_mutex: hwlock@1f40000 { 1771 compatible = "qcom,tcsr-mutex"; 1772 reg = <0x0 0x01f40000 0x0 0x40000>; 1773 #hwlock-cells = <1>; 1774 }; 1775 1776 wsamacro: codec@3240000 { 1777 compatible = "qcom,sm8250-lpass-wsa-macro"; 1778 reg = <0 0x03240000 0 0x1000>; 1779 clocks = <&audiocc 1>, 1780 <&audiocc 0>, 1781 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1782 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1783 <&aoncc 0>, 1784 <&vamacro>; 1785 1786 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 1787 1788 #clock-cells = <0>; 1789 clock-frequency = <9600000>; 1790 clock-output-names = "mclk"; 1791 #sound-dai-cells = <1>; 1792 1793 pinctrl-names = "default"; 1794 pinctrl-0 = <&wsa_swr_active>; 1795 }; 1796 1797 swr0: soundwire-controller@3250000 { 1798 reg = <0 0x03250000 0 0x2000>; 1799 compatible = "qcom,soundwire-v1.5.1"; 1800 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1801 clocks = <&wsamacro>; 1802 clock-names = "iface"; 1803 1804 qcom,din-ports = <2>; 1805 qcom,dout-ports = <6>; 1806 1807 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 1808 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 1809 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 1810 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 1811 1812 #sound-dai-cells = <1>; 1813 #address-cells = <2>; 1814 #size-cells = <0>; 1815 }; 1816 1817 audiocc: clock-controller@3300000 { 1818 compatible = "qcom,sm8250-lpass-audiocc"; 1819 reg = <0 0x03300000 0 0x30000>; 1820 #clock-cells = <1>; 1821 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1822 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1823 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1824 clock-names = "core", "audio", "bus"; 1825 }; 1826 1827 vamacro: codec@3370000 { 1828 compatible = "qcom,sm8250-lpass-va-macro"; 1829 reg = <0 0x03370000 0 0x1000>; 1830 clocks = <&aoncc 0>, 1831 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1832 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1833 1834 clock-names = "mclk", "macro", "dcodec"; 1835 1836 #clock-cells = <0>; 1837 clock-frequency = <9600000>; 1838 clock-output-names = "fsgen"; 1839 #sound-dai-cells = <1>; 1840 }; 1841 1842 aoncc: clock-controller@3380000 { 1843 compatible = "qcom,sm8250-lpass-aoncc"; 1844 reg = <0 0x03380000 0 0x40000>; 1845 #clock-cells = <1>; 1846 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1847 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1848 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1849 clock-names = "core", "audio", "bus"; 1850 }; 1851 1852 lpass_tlmm: pinctrl@33c0000{ 1853 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 1854 reg = <0 0x033c0000 0x0 0x20000>, 1855 <0 0x03550000 0x0 0x10000>; 1856 gpio-controller; 1857 #gpio-cells = <2>; 1858 gpio-ranges = <&lpass_tlmm 0 0 14>; 1859 1860 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1861 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1862 clock-names = "core", "audio"; 1863 1864 wsa_swr_active: wsa-swr-active-pins { 1865 clk { 1866 pins = "gpio10"; 1867 function = "wsa_swr_clk"; 1868 drive-strength = <2>; 1869 slew-rate = <1>; 1870 bias-disable; 1871 }; 1872 1873 data { 1874 pins = "gpio11"; 1875 function = "wsa_swr_data"; 1876 drive-strength = <2>; 1877 slew-rate = <1>; 1878 bias-bus-hold; 1879 1880 }; 1881 }; 1882 1883 wsa_swr_sleep: wsa-swr-sleep-pins { 1884 clk { 1885 pins = "gpio10"; 1886 function = "wsa_swr_clk"; 1887 drive-strength = <2>; 1888 input-enable; 1889 bias-pull-down; 1890 }; 1891 1892 data { 1893 pins = "gpio11"; 1894 function = "wsa_swr_data"; 1895 drive-strength = <2>; 1896 input-enable; 1897 bias-pull-down; 1898 1899 }; 1900 }; 1901 1902 dmic01_active: dmic01-active-pins { 1903 clk { 1904 pins = "gpio6"; 1905 function = "dmic1_clk"; 1906 drive-strength = <8>; 1907 output-high; 1908 }; 1909 data { 1910 pins = "gpio7"; 1911 function = "dmic1_data"; 1912 drive-strength = <8>; 1913 input-enable; 1914 }; 1915 }; 1916 1917 dmic01_sleep: dmic01-sleep-pins { 1918 clk { 1919 pins = "gpio6"; 1920 function = "dmic1_clk"; 1921 drive-strength = <2>; 1922 bias-disable; 1923 output-low; 1924 }; 1925 1926 data { 1927 pins = "gpio7"; 1928 function = "dmic1_data"; 1929 drive-strength = <2>; 1930 pull-down; 1931 input-enable; 1932 }; 1933 }; 1934 }; 1935 1936 gpu: gpu@3d00000 { 1937 compatible = "qcom,adreno-650.2", 1938 "qcom,adreno"; 1939 #stream-id-cells = <16>; 1940 1941 reg = <0 0x03d00000 0 0x40000>; 1942 reg-names = "kgsl_3d0_reg_memory"; 1943 1944 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1945 1946 iommus = <&adreno_smmu 0 0x401>; 1947 1948 operating-points-v2 = <&gpu_opp_table>; 1949 1950 qcom,gmu = <&gmu>; 1951 1952 status = "disabled"; 1953 1954 zap-shader { 1955 memory-region = <&gpu_mem>; 1956 }; 1957 1958 /* note: downstream checks gpu binning for 670 Mhz */ 1959 gpu_opp_table: opp-table { 1960 compatible = "operating-points-v2"; 1961 1962 opp-670000000 { 1963 opp-hz = /bits/ 64 <670000000>; 1964 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1965 }; 1966 1967 opp-587000000 { 1968 opp-hz = /bits/ 64 <587000000>; 1969 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1970 }; 1971 1972 opp-525000000 { 1973 opp-hz = /bits/ 64 <525000000>; 1974 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1975 }; 1976 1977 opp-490000000 { 1978 opp-hz = /bits/ 64 <490000000>; 1979 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1980 }; 1981 1982 opp-441600000 { 1983 opp-hz = /bits/ 64 <441600000>; 1984 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1985 }; 1986 1987 opp-400000000 { 1988 opp-hz = /bits/ 64 <400000000>; 1989 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1990 }; 1991 1992 opp-305000000 { 1993 opp-hz = /bits/ 64 <305000000>; 1994 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1995 }; 1996 }; 1997 }; 1998 1999 gmu: gmu@3d6a000 { 2000 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2001 2002 reg = <0 0x03d6a000 0 0x30000>, 2003 <0 0x3de0000 0 0x10000>, 2004 <0 0xb290000 0 0x10000>, 2005 <0 0xb490000 0 0x10000>; 2006 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 2007 2008 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2009 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2010 interrupt-names = "hfi", "gmu"; 2011 2012 clocks = <&gpucc GPU_CC_AHB_CLK>, 2013 <&gpucc GPU_CC_CX_GMU_CLK>, 2014 <&gpucc GPU_CC_CXO_CLK>, 2015 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2016 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2017 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2018 2019 power-domains = <&gpucc GPU_CX_GDSC>, 2020 <&gpucc GPU_GX_GDSC>; 2021 power-domain-names = "cx", "gx"; 2022 2023 iommus = <&adreno_smmu 5 0x400>; 2024 2025 operating-points-v2 = <&gmu_opp_table>; 2026 2027 status = "disabled"; 2028 2029 gmu_opp_table: opp-table { 2030 compatible = "operating-points-v2"; 2031 2032 opp-200000000 { 2033 opp-hz = /bits/ 64 <200000000>; 2034 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2035 }; 2036 }; 2037 }; 2038 2039 gpucc: clock-controller@3d90000 { 2040 compatible = "qcom,sm8250-gpucc"; 2041 reg = <0 0x03d90000 0 0x9000>; 2042 clocks = <&rpmhcc RPMH_CXO_CLK>, 2043 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2044 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2045 clock-names = "bi_tcxo", 2046 "gcc_gpu_gpll0_clk_src", 2047 "gcc_gpu_gpll0_div_clk_src"; 2048 #clock-cells = <1>; 2049 #reset-cells = <1>; 2050 #power-domain-cells = <1>; 2051 }; 2052 2053 adreno_smmu: iommu@3da0000 { 2054 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 2055 reg = <0 0x03da0000 0 0x10000>; 2056 #iommu-cells = <2>; 2057 #global-interrupts = <2>; 2058 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2060 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2061 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2062 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2063 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2064 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2065 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2066 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2067 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 2068 clocks = <&gpucc GPU_CC_AHB_CLK>, 2069 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2070 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2071 clock-names = "ahb", "bus", "iface"; 2072 2073 power-domains = <&gpucc GPU_CX_GDSC>; 2074 }; 2075 2076 slpi: remoteproc@5c00000 { 2077 compatible = "qcom,sm8250-slpi-pas"; 2078 reg = <0 0x05c00000 0 0x4000>; 2079 2080 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2081 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2082 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2083 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2084 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2085 interrupt-names = "wdog", "fatal", "ready", 2086 "handover", "stop-ack"; 2087 2088 clocks = <&rpmhcc RPMH_CXO_CLK>; 2089 clock-names = "xo"; 2090 2091 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, 2092 <&rpmhpd SM8250_LCX>, 2093 <&rpmhpd SM8250_LMX>; 2094 power-domain-names = "load_state", "lcx", "lmx"; 2095 2096 memory-region = <&slpi_mem>; 2097 2098 qcom,smem-states = <&smp2p_slpi_out 0>; 2099 qcom,smem-state-names = "stop"; 2100 2101 status = "disabled"; 2102 2103 glink-edge { 2104 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2105 IPCC_MPROC_SIGNAL_GLINK_QMP 2106 IRQ_TYPE_EDGE_RISING>; 2107 mboxes = <&ipcc IPCC_CLIENT_SLPI 2108 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2109 2110 label = "slpi"; 2111 qcom,remote-pid = <3>; 2112 2113 fastrpc { 2114 compatible = "qcom,fastrpc"; 2115 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2116 label = "sdsp"; 2117 #address-cells = <1>; 2118 #size-cells = <0>; 2119 2120 compute-cb@1 { 2121 compatible = "qcom,fastrpc-compute-cb"; 2122 reg = <1>; 2123 iommus = <&apps_smmu 0x0541 0x0>; 2124 }; 2125 2126 compute-cb@2 { 2127 compatible = "qcom,fastrpc-compute-cb"; 2128 reg = <2>; 2129 iommus = <&apps_smmu 0x0542 0x0>; 2130 }; 2131 2132 compute-cb@3 { 2133 compatible = "qcom,fastrpc-compute-cb"; 2134 reg = <3>; 2135 iommus = <&apps_smmu 0x0543 0x0>; 2136 /* note: shared-cb = <4> in downstream */ 2137 }; 2138 }; 2139 }; 2140 }; 2141 2142 cdsp: remoteproc@8300000 { 2143 compatible = "qcom,sm8250-cdsp-pas"; 2144 reg = <0 0x08300000 0 0x10000>; 2145 2146 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 2147 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2148 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2149 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2150 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2151 interrupt-names = "wdog", "fatal", "ready", 2152 "handover", "stop-ack"; 2153 2154 clocks = <&rpmhcc RPMH_CXO_CLK>; 2155 clock-names = "xo"; 2156 2157 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, 2158 <&rpmhpd SM8250_CX>; 2159 power-domain-names = "load_state", "cx"; 2160 2161 memory-region = <&cdsp_mem>; 2162 2163 qcom,smem-states = <&smp2p_cdsp_out 0>; 2164 qcom,smem-state-names = "stop"; 2165 2166 status = "disabled"; 2167 2168 glink-edge { 2169 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2170 IPCC_MPROC_SIGNAL_GLINK_QMP 2171 IRQ_TYPE_EDGE_RISING>; 2172 mboxes = <&ipcc IPCC_CLIENT_CDSP 2173 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2174 2175 label = "cdsp"; 2176 qcom,remote-pid = <5>; 2177 2178 fastrpc { 2179 compatible = "qcom,fastrpc"; 2180 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2181 label = "cdsp"; 2182 #address-cells = <1>; 2183 #size-cells = <0>; 2184 2185 compute-cb@1 { 2186 compatible = "qcom,fastrpc-compute-cb"; 2187 reg = <1>; 2188 iommus = <&apps_smmu 0x1001 0x0460>; 2189 }; 2190 2191 compute-cb@2 { 2192 compatible = "qcom,fastrpc-compute-cb"; 2193 reg = <2>; 2194 iommus = <&apps_smmu 0x1002 0x0460>; 2195 }; 2196 2197 compute-cb@3 { 2198 compatible = "qcom,fastrpc-compute-cb"; 2199 reg = <3>; 2200 iommus = <&apps_smmu 0x1003 0x0460>; 2201 }; 2202 2203 compute-cb@4 { 2204 compatible = "qcom,fastrpc-compute-cb"; 2205 reg = <4>; 2206 iommus = <&apps_smmu 0x1004 0x0460>; 2207 }; 2208 2209 compute-cb@5 { 2210 compatible = "qcom,fastrpc-compute-cb"; 2211 reg = <5>; 2212 iommus = <&apps_smmu 0x1005 0x0460>; 2213 }; 2214 2215 compute-cb@6 { 2216 compatible = "qcom,fastrpc-compute-cb"; 2217 reg = <6>; 2218 iommus = <&apps_smmu 0x1006 0x0460>; 2219 }; 2220 2221 compute-cb@7 { 2222 compatible = "qcom,fastrpc-compute-cb"; 2223 reg = <7>; 2224 iommus = <&apps_smmu 0x1007 0x0460>; 2225 }; 2226 2227 compute-cb@8 { 2228 compatible = "qcom,fastrpc-compute-cb"; 2229 reg = <8>; 2230 iommus = <&apps_smmu 0x1008 0x0460>; 2231 }; 2232 2233 /* note: secure cb9 in downstream */ 2234 }; 2235 }; 2236 }; 2237 2238 sound: sound { 2239 }; 2240 2241 usb_1_hsphy: phy@88e3000 { 2242 compatible = "qcom,sm8250-usb-hs-phy", 2243 "qcom,usb-snps-hs-7nm-phy"; 2244 reg = <0 0x088e3000 0 0x400>; 2245 status = "disabled"; 2246 #phy-cells = <0>; 2247 2248 clocks = <&rpmhcc RPMH_CXO_CLK>; 2249 clock-names = "ref"; 2250 2251 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2252 }; 2253 2254 usb_2_hsphy: phy@88e4000 { 2255 compatible = "qcom,sm8250-usb-hs-phy", 2256 "qcom,usb-snps-hs-7nm-phy"; 2257 reg = <0 0x088e4000 0 0x400>; 2258 status = "disabled"; 2259 #phy-cells = <0>; 2260 2261 clocks = <&rpmhcc RPMH_CXO_CLK>; 2262 clock-names = "ref"; 2263 2264 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2265 }; 2266 2267 usb_1_qmpphy: phy@88e9000 { 2268 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 2269 reg = <0 0x088e9000 0 0x200>, 2270 <0 0x088e8000 0 0x40>, 2271 <0 0x088ea000 0 0x200>; 2272 status = "disabled"; 2273 #address-cells = <2>; 2274 #size-cells = <2>; 2275 ranges; 2276 2277 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2278 <&rpmhcc RPMH_CXO_CLK>, 2279 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2280 clock-names = "aux", "ref_clk_src", "com_aux"; 2281 2282 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2283 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2284 reset-names = "phy", "common"; 2285 2286 usb_1_ssphy: usb3-phy@88e9200 { 2287 reg = <0 0x088e9200 0 0x200>, 2288 <0 0x088e9400 0 0x200>, 2289 <0 0x088e9c00 0 0x400>, 2290 <0 0x088e9600 0 0x200>, 2291 <0 0x088e9800 0 0x200>, 2292 <0 0x088e9a00 0 0x100>; 2293 #clock-cells = <0>; 2294 #phy-cells = <0>; 2295 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2296 clock-names = "pipe0"; 2297 clock-output-names = "usb3_phy_pipe_clk_src"; 2298 }; 2299 2300 dp_phy: dp-phy@88ea200 { 2301 reg = <0 0x088ea200 0 0x200>, 2302 <0 0x088ea400 0 0x200>, 2303 <0 0x088eac00 0 0x400>, 2304 <0 0x088ea600 0 0x200>, 2305 <0 0x088ea800 0 0x200>, 2306 <0 0x088eaa00 0 0x100>; 2307 #phy-cells = <0>; 2308 #clock-cells = <1>; 2309 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2310 clock-names = "pipe0"; 2311 clock-output-names = "usb3_phy_pipe_clk_src"; 2312 }; 2313 }; 2314 2315 usb_2_qmpphy: phy@88eb000 { 2316 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 2317 reg = <0 0x088eb000 0 0x200>; 2318 status = "disabled"; 2319 #address-cells = <2>; 2320 #size-cells = <2>; 2321 ranges; 2322 2323 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2324 <&rpmhcc RPMH_CXO_CLK>, 2325 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2326 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2327 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2328 2329 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2330 <&gcc GCC_USB3_PHY_SEC_BCR>; 2331 reset-names = "phy", "common"; 2332 2333 usb_2_ssphy: lanes@88eb200 { 2334 reg = <0 0x088eb200 0 0x200>, 2335 <0 0x088eb400 0 0x200>, 2336 <0 0x088eb800 0 0x800>; 2337 #clock-cells = <0>; 2338 #phy-cells = <0>; 2339 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2340 clock-names = "pipe0"; 2341 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2342 }; 2343 }; 2344 2345 sdhc_2: sdhci@8804000 { 2346 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 2347 reg = <0 0x08804000 0 0x1000>; 2348 2349 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2350 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2351 interrupt-names = "hc_irq", "pwr_irq"; 2352 2353 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2354 <&gcc GCC_SDCC2_APPS_CLK>, 2355 <&rpmhcc RPMH_CXO_CLK>; 2356 clock-names = "iface", "core", "xo"; 2357 iommus = <&apps_smmu 0x4a0 0x0>; 2358 qcom,dll-config = <0x0007642c>; 2359 qcom,ddr-config = <0x80040868>; 2360 power-domains = <&rpmhpd SM8250_CX>; 2361 operating-points-v2 = <&sdhc2_opp_table>; 2362 2363 status = "disabled"; 2364 2365 sdhc2_opp_table: sdhc2-opp-table { 2366 compatible = "operating-points-v2"; 2367 2368 opp-19200000 { 2369 opp-hz = /bits/ 64 <19200000>; 2370 required-opps = <&rpmhpd_opp_min_svs>; 2371 }; 2372 2373 opp-50000000 { 2374 opp-hz = /bits/ 64 <50000000>; 2375 required-opps = <&rpmhpd_opp_low_svs>; 2376 }; 2377 2378 opp-100000000 { 2379 opp-hz = /bits/ 64 <100000000>; 2380 required-opps = <&rpmhpd_opp_svs>; 2381 }; 2382 2383 opp-202000000 { 2384 opp-hz = /bits/ 64 <202000000>; 2385 required-opps = <&rpmhpd_opp_svs_l1>; 2386 }; 2387 }; 2388 }; 2389 2390 dc_noc: interconnect@90c0000 { 2391 compatible = "qcom,sm8250-dc-noc"; 2392 reg = <0 0x090c0000 0 0x4200>; 2393 #interconnect-cells = <1>; 2394 qcom,bcm-voters = <&apps_bcm_voter>; 2395 }; 2396 2397 gem_noc: interconnect@9100000 { 2398 compatible = "qcom,sm8250-gem-noc"; 2399 reg = <0 0x09100000 0 0xb4000>; 2400 #interconnect-cells = <1>; 2401 qcom,bcm-voters = <&apps_bcm_voter>; 2402 }; 2403 2404 npu_noc: interconnect@9990000 { 2405 compatible = "qcom,sm8250-npu-noc"; 2406 reg = <0 0x09990000 0 0x1600>; 2407 #interconnect-cells = <1>; 2408 qcom,bcm-voters = <&apps_bcm_voter>; 2409 }; 2410 2411 usb_1: usb@a6f8800 { 2412 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 2413 reg = <0 0x0a6f8800 0 0x400>; 2414 status = "disabled"; 2415 #address-cells = <2>; 2416 #size-cells = <2>; 2417 ranges; 2418 dma-ranges; 2419 2420 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2421 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2422 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2423 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2424 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2425 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2426 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2427 "sleep", "xo"; 2428 2429 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2430 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2431 assigned-clock-rates = <19200000>, <200000000>; 2432 2433 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2434 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2435 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2436 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2437 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2438 "dm_hs_phy_irq", "ss_phy_irq"; 2439 2440 power-domains = <&gcc USB30_PRIM_GDSC>; 2441 2442 resets = <&gcc GCC_USB30_PRIM_BCR>; 2443 2444 usb_1_dwc3: usb@a600000 { 2445 compatible = "snps,dwc3"; 2446 reg = <0 0x0a600000 0 0xcd00>; 2447 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2448 iommus = <&apps_smmu 0x0 0x0>; 2449 snps,dis_u2_susphy_quirk; 2450 snps,dis_enblslpm_quirk; 2451 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2452 phy-names = "usb2-phy", "usb3-phy"; 2453 }; 2454 }; 2455 2456 system-cache-controller@9200000 { 2457 compatible = "qcom,sm8250-llcc"; 2458 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 2459 reg-names = "llcc_base", "llcc_broadcast_base"; 2460 }; 2461 2462 usb_2: usb@a8f8800 { 2463 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 2464 reg = <0 0x0a8f8800 0 0x400>; 2465 status = "disabled"; 2466 #address-cells = <2>; 2467 #size-cells = <2>; 2468 ranges; 2469 dma-ranges; 2470 2471 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2472 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2473 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2474 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2475 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2476 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2477 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2478 "sleep", "xo"; 2479 2480 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2481 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2482 assigned-clock-rates = <19200000>, <200000000>; 2483 2484 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2485 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 2486 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2487 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 2488 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2489 "dm_hs_phy_irq", "ss_phy_irq"; 2490 2491 power-domains = <&gcc USB30_SEC_GDSC>; 2492 2493 resets = <&gcc GCC_USB30_SEC_BCR>; 2494 2495 usb_2_dwc3: usb@a800000 { 2496 compatible = "snps,dwc3"; 2497 reg = <0 0x0a800000 0 0xcd00>; 2498 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2499 iommus = <&apps_smmu 0x20 0>; 2500 snps,dis_u2_susphy_quirk; 2501 snps,dis_enblslpm_quirk; 2502 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2503 phy-names = "usb2-phy", "usb3-phy"; 2504 }; 2505 }; 2506 2507 venus: video-codec@aa00000 { 2508 compatible = "qcom,sm8250-venus"; 2509 reg = <0 0x0aa00000 0 0x100000>; 2510 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2511 power-domains = <&videocc MVS0C_GDSC>, 2512 <&videocc MVS0_GDSC>, 2513 <&rpmhpd SM8250_MX>; 2514 power-domain-names = "venus", "vcodec0", "mx"; 2515 operating-points-v2 = <&venus_opp_table>; 2516 2517 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 2518 <&videocc VIDEO_CC_MVS0C_CLK>, 2519 <&videocc VIDEO_CC_MVS0_CLK>; 2520 clock-names = "iface", "core", "vcodec0_core"; 2521 2522 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, 2523 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; 2524 interconnect-names = "cpu-cfg", "video-mem"; 2525 2526 iommus = <&apps_smmu 0x2100 0x0400>; 2527 memory-region = <&video_mem>; 2528 2529 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 2530 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 2531 reset-names = "bus", "core"; 2532 2533 status = "disabled"; 2534 2535 video-decoder { 2536 compatible = "venus-decoder"; 2537 }; 2538 2539 video-encoder { 2540 compatible = "venus-encoder"; 2541 }; 2542 2543 venus_opp_table: venus-opp-table { 2544 compatible = "operating-points-v2"; 2545 2546 opp-720000000 { 2547 opp-hz = /bits/ 64 <720000000>; 2548 required-opps = <&rpmhpd_opp_low_svs>; 2549 }; 2550 2551 opp-1014000000 { 2552 opp-hz = /bits/ 64 <1014000000>; 2553 required-opps = <&rpmhpd_opp_svs>; 2554 }; 2555 2556 opp-1098000000 { 2557 opp-hz = /bits/ 64 <1098000000>; 2558 required-opps = <&rpmhpd_opp_svs_l1>; 2559 }; 2560 2561 opp-1332000000 { 2562 opp-hz = /bits/ 64 <1332000000>; 2563 required-opps = <&rpmhpd_opp_nom>; 2564 }; 2565 }; 2566 }; 2567 2568 videocc: clock-controller@abf0000 { 2569 compatible = "qcom,sm8250-videocc"; 2570 reg = <0 0x0abf0000 0 0x10000>; 2571 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 2572 <&rpmhcc RPMH_CXO_CLK>, 2573 <&rpmhcc RPMH_CXO_CLK_A>; 2574 mmcx-supply = <&mmcx_reg>; 2575 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 2576 #clock-cells = <1>; 2577 #reset-cells = <1>; 2578 #power-domain-cells = <1>; 2579 }; 2580 2581 mdss: mdss@ae00000 { 2582 compatible = "qcom,sm8250-mdss"; 2583 reg = <0 0x0ae00000 0 0x1000>; 2584 reg-names = "mdss"; 2585 2586 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 2587 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 2588 interconnect-names = "mdp0-mem", "mdp1-mem"; 2589 2590 power-domains = <&dispcc MDSS_GDSC>; 2591 2592 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2593 <&gcc GCC_DISP_SF_AXI_CLK>, 2594 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2595 clock-names = "iface", "nrt_bus", "core"; 2596 2597 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2598 assigned-clock-rates = <460000000>; 2599 2600 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2601 interrupt-controller; 2602 #interrupt-cells = <1>; 2603 2604 iommus = <&apps_smmu 0x820 0x402>; 2605 2606 status = "disabled"; 2607 2608 #address-cells = <2>; 2609 #size-cells = <2>; 2610 ranges; 2611 2612 mdss_mdp: mdp@ae01000 { 2613 compatible = "qcom,sm8250-dpu"; 2614 reg = <0 0x0ae01000 0 0x8f000>, 2615 <0 0x0aeb0000 0 0x2008>; 2616 reg-names = "mdp", "vbif"; 2617 2618 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2619 <&gcc GCC_DISP_HF_AXI_CLK>, 2620 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2621 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2622 clock-names = "iface", "bus", "core", "vsync"; 2623 2624 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2625 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2626 assigned-clock-rates = <460000000>, 2627 <19200000>; 2628 2629 operating-points-v2 = <&mdp_opp_table>; 2630 power-domains = <&rpmhpd SM8250_MMCX>; 2631 2632 interrupt-parent = <&mdss>; 2633 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2634 2635 ports { 2636 #address-cells = <1>; 2637 #size-cells = <0>; 2638 2639 port@0 { 2640 reg = <0>; 2641 dpu_intf1_out: endpoint { 2642 remote-endpoint = <&dsi0_in>; 2643 }; 2644 }; 2645 2646 port@1 { 2647 reg = <1>; 2648 dpu_intf2_out: endpoint { 2649 remote-endpoint = <&dsi1_in>; 2650 }; 2651 }; 2652 }; 2653 2654 mdp_opp_table: mdp-opp-table { 2655 compatible = "operating-points-v2"; 2656 2657 opp-200000000 { 2658 opp-hz = /bits/ 64 <200000000>; 2659 required-opps = <&rpmhpd_opp_low_svs>; 2660 }; 2661 2662 opp-300000000 { 2663 opp-hz = /bits/ 64 <300000000>; 2664 required-opps = <&rpmhpd_opp_svs>; 2665 }; 2666 2667 opp-345000000 { 2668 opp-hz = /bits/ 64 <345000000>; 2669 required-opps = <&rpmhpd_opp_svs_l1>; 2670 }; 2671 2672 opp-460000000 { 2673 opp-hz = /bits/ 64 <460000000>; 2674 required-opps = <&rpmhpd_opp_nom>; 2675 }; 2676 }; 2677 }; 2678 2679 dsi0: dsi@ae94000 { 2680 compatible = "qcom,mdss-dsi-ctrl"; 2681 reg = <0 0x0ae94000 0 0x400>; 2682 reg-names = "dsi_ctrl"; 2683 2684 interrupt-parent = <&mdss>; 2685 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 2686 2687 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2688 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2689 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2690 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2691 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2692 <&gcc GCC_DISP_HF_AXI_CLK>; 2693 clock-names = "byte", 2694 "byte_intf", 2695 "pixel", 2696 "core", 2697 "iface", 2698 "bus"; 2699 2700 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2701 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 2702 2703 operating-points-v2 = <&dsi_opp_table>; 2704 power-domains = <&rpmhpd SM8250_MMCX>; 2705 2706 phys = <&dsi0_phy>; 2707 phy-names = "dsi"; 2708 2709 status = "disabled"; 2710 2711 #address-cells = <1>; 2712 #size-cells = <0>; 2713 2714 ports { 2715 #address-cells = <1>; 2716 #size-cells = <0>; 2717 2718 port@0 { 2719 reg = <0>; 2720 dsi0_in: endpoint { 2721 remote-endpoint = <&dpu_intf1_out>; 2722 }; 2723 }; 2724 2725 port@1 { 2726 reg = <1>; 2727 dsi0_out: endpoint { 2728 }; 2729 }; 2730 }; 2731 }; 2732 2733 dsi0_phy: dsi-phy@ae94400 { 2734 compatible = "qcom,dsi-phy-7nm"; 2735 reg = <0 0x0ae94400 0 0x200>, 2736 <0 0x0ae94600 0 0x280>, 2737 <0 0x0ae94900 0 0x260>; 2738 reg-names = "dsi_phy", 2739 "dsi_phy_lane", 2740 "dsi_pll"; 2741 2742 #clock-cells = <1>; 2743 #phy-cells = <0>; 2744 2745 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2746 <&rpmhcc RPMH_CXO_CLK>; 2747 clock-names = "iface", "ref"; 2748 2749 status = "disabled"; 2750 }; 2751 2752 dsi1: dsi@ae96000 { 2753 compatible = "qcom,mdss-dsi-ctrl"; 2754 reg = <0 0x0ae96000 0 0x400>; 2755 reg-names = "dsi_ctrl"; 2756 2757 interrupt-parent = <&mdss>; 2758 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 2759 2760 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2761 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2762 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2763 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2764 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2765 <&gcc GCC_DISP_HF_AXI_CLK>; 2766 clock-names = "byte", 2767 "byte_intf", 2768 "pixel", 2769 "core", 2770 "iface", 2771 "bus"; 2772 2773 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2774 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 2775 2776 operating-points-v2 = <&dsi_opp_table>; 2777 power-domains = <&rpmhpd SM8250_MMCX>; 2778 2779 phys = <&dsi1_phy>; 2780 phy-names = "dsi"; 2781 2782 status = "disabled"; 2783 2784 #address-cells = <1>; 2785 #size-cells = <0>; 2786 2787 ports { 2788 #address-cells = <1>; 2789 #size-cells = <0>; 2790 2791 port@0 { 2792 reg = <0>; 2793 dsi1_in: endpoint { 2794 remote-endpoint = <&dpu_intf2_out>; 2795 }; 2796 }; 2797 2798 port@1 { 2799 reg = <1>; 2800 dsi1_out: endpoint { 2801 }; 2802 }; 2803 }; 2804 }; 2805 2806 dsi1_phy: dsi-phy@ae96400 { 2807 compatible = "qcom,dsi-phy-7nm"; 2808 reg = <0 0x0ae96400 0 0x200>, 2809 <0 0x0ae96600 0 0x280>, 2810 <0 0x0ae96900 0 0x260>; 2811 reg-names = "dsi_phy", 2812 "dsi_phy_lane", 2813 "dsi_pll"; 2814 2815 #clock-cells = <1>; 2816 #phy-cells = <0>; 2817 2818 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2819 <&rpmhcc RPMH_CXO_CLK>; 2820 clock-names = "iface", "ref"; 2821 2822 status = "disabled"; 2823 2824 dsi_opp_table: dsi-opp-table { 2825 compatible = "operating-points-v2"; 2826 2827 opp-187500000 { 2828 opp-hz = /bits/ 64 <187500000>; 2829 required-opps = <&rpmhpd_opp_low_svs>; 2830 }; 2831 2832 opp-300000000 { 2833 opp-hz = /bits/ 64 <300000000>; 2834 required-opps = <&rpmhpd_opp_svs>; 2835 }; 2836 2837 opp-358000000 { 2838 opp-hz = /bits/ 64 <358000000>; 2839 required-opps = <&rpmhpd_opp_svs_l1>; 2840 }; 2841 }; 2842 }; 2843 }; 2844 2845 dispcc: clock-controller@af00000 { 2846 compatible = "qcom,sm8250-dispcc"; 2847 reg = <0 0x0af00000 0 0x10000>; 2848 mmcx-supply = <&mmcx_reg>; 2849 clocks = <&rpmhcc RPMH_CXO_CLK>, 2850 <&dsi0_phy 0>, 2851 <&dsi0_phy 1>, 2852 <&dsi1_phy 0>, 2853 <&dsi1_phy 1>, 2854 <&dp_phy 0>, 2855 <&dp_phy 1>; 2856 clock-names = "bi_tcxo", 2857 "dsi0_phy_pll_out_byteclk", 2858 "dsi0_phy_pll_out_dsiclk", 2859 "dsi1_phy_pll_out_byteclk", 2860 "dsi1_phy_pll_out_dsiclk", 2861 "dp_phy_pll_link_clk", 2862 "dp_phy_pll_vco_div_clk"; 2863 #clock-cells = <1>; 2864 #reset-cells = <1>; 2865 #power-domain-cells = <1>; 2866 }; 2867 2868 pdc: interrupt-controller@b220000 { 2869 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 2870 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 2871 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2872 <125 63 1>, <126 716 12>; 2873 #interrupt-cells = <2>; 2874 interrupt-parent = <&intc>; 2875 interrupt-controller; 2876 }; 2877 2878 tsens0: thermal-sensor@c263000 { 2879 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 2880 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2881 <0 0x0c222000 0 0x1ff>; /* SROT */ 2882 #qcom,sensors = <16>; 2883 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2884 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2885 interrupt-names = "uplow", "critical"; 2886 #thermal-sensor-cells = <1>; 2887 }; 2888 2889 tsens1: thermal-sensor@c265000 { 2890 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 2891 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2892 <0 0x0c223000 0 0x1ff>; /* SROT */ 2893 #qcom,sensors = <9>; 2894 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2895 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2896 interrupt-names = "uplow", "critical"; 2897 #thermal-sensor-cells = <1>; 2898 }; 2899 2900 aoss_qmp: power-controller@c300000 { 2901 compatible = "qcom,sm8250-aoss-qmp"; 2902 reg = <0 0x0c300000 0 0x100000>; 2903 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2904 IPCC_MPROC_SIGNAL_GLINK_QMP 2905 IRQ_TYPE_EDGE_RISING>; 2906 mboxes = <&ipcc IPCC_CLIENT_AOP 2907 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2908 2909 #clock-cells = <0>; 2910 #power-domain-cells = <1>; 2911 }; 2912 2913 spmi_bus: spmi@c440000 { 2914 compatible = "qcom,spmi-pmic-arb"; 2915 reg = <0x0 0x0c440000 0x0 0x0001100>, 2916 <0x0 0x0c600000 0x0 0x2000000>, 2917 <0x0 0x0e600000 0x0 0x0100000>, 2918 <0x0 0x0e700000 0x0 0x00a0000>, 2919 <0x0 0x0c40a000 0x0 0x0026000>; 2920 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2921 interrupt-names = "periph_irq"; 2922 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2923 qcom,ee = <0>; 2924 qcom,channel = <0>; 2925 #address-cells = <2>; 2926 #size-cells = <0>; 2927 interrupt-controller; 2928 #interrupt-cells = <4>; 2929 }; 2930 2931 tlmm: pinctrl@f100000 { 2932 compatible = "qcom,sm8250-pinctrl"; 2933 reg = <0 0x0f100000 0 0x300000>, 2934 <0 0x0f500000 0 0x300000>, 2935 <0 0x0f900000 0 0x300000>; 2936 reg-names = "west", "south", "north"; 2937 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2938 gpio-controller; 2939 #gpio-cells = <2>; 2940 interrupt-controller; 2941 #interrupt-cells = <2>; 2942 gpio-ranges = <&tlmm 0 0 181>; 2943 wakeup-parent = <&pdc>; 2944 2945 pri_mi2s_active: pri-mi2s-active { 2946 sclk { 2947 pins = "gpio138"; 2948 function = "mi2s0_sck"; 2949 drive-strength = <8>; 2950 bias-disable; 2951 }; 2952 2953 ws { 2954 pins = "gpio141"; 2955 function = "mi2s0_ws"; 2956 drive-strength = <8>; 2957 output-high; 2958 }; 2959 2960 data0 { 2961 pins = "gpio139"; 2962 function = "mi2s0_data0"; 2963 drive-strength = <8>; 2964 bias-disable; 2965 output-high; 2966 }; 2967 2968 data1 { 2969 pins = "gpio140"; 2970 function = "mi2s0_data1"; 2971 drive-strength = <8>; 2972 output-high; 2973 }; 2974 }; 2975 2976 qup_i2c0_default: qup-i2c0-default { 2977 mux { 2978 pins = "gpio28", "gpio29"; 2979 function = "qup0"; 2980 }; 2981 2982 config { 2983 pins = "gpio28", "gpio29"; 2984 drive-strength = <2>; 2985 bias-disable; 2986 }; 2987 }; 2988 2989 qup_i2c1_default: qup-i2c1-default { 2990 pinmux { 2991 pins = "gpio4", "gpio5"; 2992 function = "qup1"; 2993 }; 2994 2995 config { 2996 pins = "gpio4", "gpio5"; 2997 drive-strength = <2>; 2998 bias-disable; 2999 }; 3000 }; 3001 3002 qup_i2c2_default: qup-i2c2-default { 3003 mux { 3004 pins = "gpio115", "gpio116"; 3005 function = "qup2"; 3006 }; 3007 3008 config { 3009 pins = "gpio115", "gpio116"; 3010 drive-strength = <2>; 3011 bias-disable; 3012 }; 3013 }; 3014 3015 qup_i2c3_default: qup-i2c3-default { 3016 mux { 3017 pins = "gpio119", "gpio120"; 3018 function = "qup3"; 3019 }; 3020 3021 config { 3022 pins = "gpio119", "gpio120"; 3023 drive-strength = <2>; 3024 bias-disable; 3025 }; 3026 }; 3027 3028 qup_i2c4_default: qup-i2c4-default { 3029 mux { 3030 pins = "gpio8", "gpio9"; 3031 function = "qup4"; 3032 }; 3033 3034 config { 3035 pins = "gpio8", "gpio9"; 3036 drive-strength = <2>; 3037 bias-disable; 3038 }; 3039 }; 3040 3041 qup_i2c5_default: qup-i2c5-default { 3042 mux { 3043 pins = "gpio12", "gpio13"; 3044 function = "qup5"; 3045 }; 3046 3047 config { 3048 pins = "gpio12", "gpio13"; 3049 drive-strength = <2>; 3050 bias-disable; 3051 }; 3052 }; 3053 3054 qup_i2c6_default: qup-i2c6-default { 3055 mux { 3056 pins = "gpio16", "gpio17"; 3057 function = "qup6"; 3058 }; 3059 3060 config { 3061 pins = "gpio16", "gpio17"; 3062 drive-strength = <2>; 3063 bias-disable; 3064 }; 3065 }; 3066 3067 qup_i2c7_default: qup-i2c7-default { 3068 mux { 3069 pins = "gpio20", "gpio21"; 3070 function = "qup7"; 3071 }; 3072 3073 config { 3074 pins = "gpio20", "gpio21"; 3075 drive-strength = <2>; 3076 bias-disable; 3077 }; 3078 }; 3079 3080 qup_i2c8_default: qup-i2c8-default { 3081 mux { 3082 pins = "gpio24", "gpio25"; 3083 function = "qup8"; 3084 }; 3085 3086 config { 3087 pins = "gpio24", "gpio25"; 3088 drive-strength = <2>; 3089 bias-disable; 3090 }; 3091 }; 3092 3093 qup_i2c9_default: qup-i2c9-default { 3094 mux { 3095 pins = "gpio125", "gpio126"; 3096 function = "qup9"; 3097 }; 3098 3099 config { 3100 pins = "gpio125", "gpio126"; 3101 drive-strength = <2>; 3102 bias-disable; 3103 }; 3104 }; 3105 3106 qup_i2c10_default: qup-i2c10-default { 3107 mux { 3108 pins = "gpio129", "gpio130"; 3109 function = "qup10"; 3110 }; 3111 3112 config { 3113 pins = "gpio129", "gpio130"; 3114 drive-strength = <2>; 3115 bias-disable; 3116 }; 3117 }; 3118 3119 qup_i2c11_default: qup-i2c11-default { 3120 mux { 3121 pins = "gpio60", "gpio61"; 3122 function = "qup11"; 3123 }; 3124 3125 config { 3126 pins = "gpio60", "gpio61"; 3127 drive-strength = <2>; 3128 bias-disable; 3129 }; 3130 }; 3131 3132 qup_i2c12_default: qup-i2c12-default { 3133 mux { 3134 pins = "gpio32", "gpio33"; 3135 function = "qup12"; 3136 }; 3137 3138 config { 3139 pins = "gpio32", "gpio33"; 3140 drive-strength = <2>; 3141 bias-disable; 3142 }; 3143 }; 3144 3145 qup_i2c13_default: qup-i2c13-default { 3146 mux { 3147 pins = "gpio36", "gpio37"; 3148 function = "qup13"; 3149 }; 3150 3151 config { 3152 pins = "gpio36", "gpio37"; 3153 drive-strength = <2>; 3154 bias-disable; 3155 }; 3156 }; 3157 3158 qup_i2c14_default: qup-i2c14-default { 3159 mux { 3160 pins = "gpio40", "gpio41"; 3161 function = "qup14"; 3162 }; 3163 3164 config { 3165 pins = "gpio40", "gpio41"; 3166 drive-strength = <2>; 3167 bias-disable; 3168 }; 3169 }; 3170 3171 qup_i2c15_default: qup-i2c15-default { 3172 mux { 3173 pins = "gpio44", "gpio45"; 3174 function = "qup15"; 3175 }; 3176 3177 config { 3178 pins = "gpio44", "gpio45"; 3179 drive-strength = <2>; 3180 bias-disable; 3181 }; 3182 }; 3183 3184 qup_i2c16_default: qup-i2c16-default { 3185 mux { 3186 pins = "gpio48", "gpio49"; 3187 function = "qup16"; 3188 }; 3189 3190 config { 3191 pins = "gpio48", "gpio49"; 3192 drive-strength = <2>; 3193 bias-disable; 3194 }; 3195 }; 3196 3197 qup_i2c17_default: qup-i2c17-default { 3198 mux { 3199 pins = "gpio52", "gpio53"; 3200 function = "qup17"; 3201 }; 3202 3203 config { 3204 pins = "gpio52", "gpio53"; 3205 drive-strength = <2>; 3206 bias-disable; 3207 }; 3208 }; 3209 3210 qup_i2c18_default: qup-i2c18-default { 3211 mux { 3212 pins = "gpio56", "gpio57"; 3213 function = "qup18"; 3214 }; 3215 3216 config { 3217 pins = "gpio56", "gpio57"; 3218 drive-strength = <2>; 3219 bias-disable; 3220 }; 3221 }; 3222 3223 qup_i2c19_default: qup-i2c19-default { 3224 mux { 3225 pins = "gpio0", "gpio1"; 3226 function = "qup19"; 3227 }; 3228 3229 config { 3230 pins = "gpio0", "gpio1"; 3231 drive-strength = <2>; 3232 bias-disable; 3233 }; 3234 }; 3235 3236 qup_spi0_cs: qup-spi0-cs { 3237 pins = "gpio31"; 3238 function = "qup0"; 3239 }; 3240 3241 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3242 pins = "gpio31"; 3243 function = "gpio"; 3244 }; 3245 3246 qup_spi0_data_clk: qup-spi0-data-clk { 3247 pins = "gpio28", "gpio29", 3248 "gpio30"; 3249 function = "qup0"; 3250 }; 3251 3252 qup_spi1_cs: qup-spi1-cs { 3253 pins = "gpio7"; 3254 function = "qup1"; 3255 }; 3256 3257 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3258 pins = "gpio7"; 3259 function = "gpio"; 3260 }; 3261 3262 qup_spi1_data_clk: qup-spi1-data-clk { 3263 pins = "gpio4", "gpio5", 3264 "gpio6"; 3265 function = "qup1"; 3266 }; 3267 3268 qup_spi2_cs: qup-spi2-cs { 3269 pins = "gpio118"; 3270 function = "qup2"; 3271 }; 3272 3273 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3274 pins = "gpio118"; 3275 function = "gpio"; 3276 }; 3277 3278 qup_spi2_data_clk: qup-spi2-data-clk { 3279 pins = "gpio115", "gpio116", 3280 "gpio117"; 3281 function = "qup2"; 3282 }; 3283 3284 qup_spi3_cs: qup-spi3-cs { 3285 pins = "gpio122"; 3286 function = "qup3"; 3287 }; 3288 3289 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3290 pins = "gpio122"; 3291 function = "gpio"; 3292 }; 3293 3294 qup_spi3_data_clk: qup-spi3-data-clk { 3295 pins = "gpio119", "gpio120", 3296 "gpio121"; 3297 function = "qup3"; 3298 }; 3299 3300 qup_spi4_cs: qup-spi4-cs { 3301 pins = "gpio11"; 3302 function = "qup4"; 3303 }; 3304 3305 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3306 pins = "gpio11"; 3307 function = "gpio"; 3308 }; 3309 3310 qup_spi4_data_clk: qup-spi4-data-clk { 3311 pins = "gpio8", "gpio9", 3312 "gpio10"; 3313 function = "qup4"; 3314 }; 3315 3316 qup_spi5_cs: qup-spi5-cs { 3317 pins = "gpio15"; 3318 function = "qup5"; 3319 }; 3320 3321 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3322 pins = "gpio15"; 3323 function = "gpio"; 3324 }; 3325 3326 qup_spi5_data_clk: qup-spi5-data-clk { 3327 pins = "gpio12", "gpio13", 3328 "gpio14"; 3329 function = "qup5"; 3330 }; 3331 3332 qup_spi6_cs: qup-spi6-cs { 3333 pins = "gpio19"; 3334 function = "qup6"; 3335 }; 3336 3337 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3338 pins = "gpio19"; 3339 function = "gpio"; 3340 }; 3341 3342 qup_spi6_data_clk: qup-spi6-data-clk { 3343 pins = "gpio16", "gpio17", 3344 "gpio18"; 3345 function = "qup6"; 3346 }; 3347 3348 qup_spi7_cs: qup-spi7-cs { 3349 pins = "gpio23"; 3350 function = "qup7"; 3351 }; 3352 3353 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3354 pins = "gpio23"; 3355 function = "gpio"; 3356 }; 3357 3358 qup_spi7_data_clk: qup-spi7-data-clk { 3359 pins = "gpio20", "gpio21", 3360 "gpio22"; 3361 function = "qup7"; 3362 }; 3363 3364 qup_spi8_cs: qup-spi8-cs { 3365 pins = "gpio27"; 3366 function = "qup8"; 3367 }; 3368 3369 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3370 pins = "gpio27"; 3371 function = "gpio"; 3372 }; 3373 3374 qup_spi8_data_clk: qup-spi8-data-clk { 3375 pins = "gpio24", "gpio25", 3376 "gpio26"; 3377 function = "qup8"; 3378 }; 3379 3380 qup_spi9_cs: qup-spi9-cs { 3381 pins = "gpio128"; 3382 function = "qup9"; 3383 }; 3384 3385 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3386 pins = "gpio128"; 3387 function = "gpio"; 3388 }; 3389 3390 qup_spi9_data_clk: qup-spi9-data-clk { 3391 pins = "gpio125", "gpio126", 3392 "gpio127"; 3393 function = "qup9"; 3394 }; 3395 3396 qup_spi10_cs: qup-spi10-cs { 3397 pins = "gpio132"; 3398 function = "qup10"; 3399 }; 3400 3401 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3402 pins = "gpio132"; 3403 function = "gpio"; 3404 }; 3405 3406 qup_spi10_data_clk: qup-spi10-data-clk { 3407 pins = "gpio129", "gpio130", 3408 "gpio131"; 3409 function = "qup10"; 3410 }; 3411 3412 qup_spi11_cs: qup-spi11-cs { 3413 pins = "gpio63"; 3414 function = "qup11"; 3415 }; 3416 3417 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3418 pins = "gpio63"; 3419 function = "gpio"; 3420 }; 3421 3422 qup_spi11_data_clk: qup-spi11-data-clk { 3423 pins = "gpio60", "gpio61", 3424 "gpio62"; 3425 function = "qup11"; 3426 }; 3427 3428 qup_spi12_cs: qup-spi12-cs { 3429 pins = "gpio35"; 3430 function = "qup12"; 3431 }; 3432 3433 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3434 pins = "gpio35"; 3435 function = "gpio"; 3436 }; 3437 3438 qup_spi12_data_clk: qup-spi12-data-clk { 3439 pins = "gpio32", "gpio33", 3440 "gpio34"; 3441 function = "qup12"; 3442 }; 3443 3444 qup_spi13_cs: qup-spi13-cs { 3445 pins = "gpio39"; 3446 function = "qup13"; 3447 }; 3448 3449 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3450 pins = "gpio39"; 3451 function = "gpio"; 3452 }; 3453 3454 qup_spi13_data_clk: qup-spi13-data-clk { 3455 pins = "gpio36", "gpio37", 3456 "gpio38"; 3457 function = "qup13"; 3458 }; 3459 3460 qup_spi14_cs: qup-spi14-cs { 3461 pins = "gpio43"; 3462 function = "qup14"; 3463 }; 3464 3465 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3466 pins = "gpio43"; 3467 function = "gpio"; 3468 }; 3469 3470 qup_spi14_data_clk: qup-spi14-data-clk { 3471 pins = "gpio40", "gpio41", 3472 "gpio42"; 3473 function = "qup14"; 3474 }; 3475 3476 qup_spi15_cs: qup-spi15-cs { 3477 pins = "gpio47"; 3478 function = "qup15"; 3479 }; 3480 3481 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3482 pins = "gpio47"; 3483 function = "gpio"; 3484 }; 3485 3486 qup_spi15_data_clk: qup-spi15-data-clk { 3487 pins = "gpio44", "gpio45", 3488 "gpio46"; 3489 function = "qup15"; 3490 }; 3491 3492 qup_spi16_cs: qup-spi16-cs { 3493 pins = "gpio51"; 3494 function = "qup16"; 3495 }; 3496 3497 qup_spi16_cs_gpio: qup-spi16-cs-gpio { 3498 pins = "gpio51"; 3499 function = "gpio"; 3500 }; 3501 3502 qup_spi16_data_clk: qup-spi16-data-clk { 3503 pins = "gpio48", "gpio49", 3504 "gpio50"; 3505 function = "qup16"; 3506 }; 3507 3508 qup_spi17_cs: qup-spi17-cs { 3509 pins = "gpio55"; 3510 function = "qup17"; 3511 }; 3512 3513 qup_spi17_cs_gpio: qup-spi17-cs-gpio { 3514 pins = "gpio55"; 3515 function = "gpio"; 3516 }; 3517 3518 qup_spi17_data_clk: qup-spi17-data-clk { 3519 pins = "gpio52", "gpio53", 3520 "gpio54"; 3521 function = "qup17"; 3522 }; 3523 3524 qup_spi18_cs: qup-spi18-cs { 3525 pins = "gpio59"; 3526 function = "qup18"; 3527 }; 3528 3529 qup_spi18_cs_gpio: qup-spi18-cs-gpio { 3530 pins = "gpio59"; 3531 function = "gpio"; 3532 }; 3533 3534 qup_spi18_data_clk: qup-spi18-data-clk { 3535 pins = "gpio56", "gpio57", 3536 "gpio58"; 3537 function = "qup18"; 3538 }; 3539 3540 qup_spi19_cs: qup-spi19-cs { 3541 pins = "gpio3"; 3542 function = "qup19"; 3543 }; 3544 3545 qup_spi19_cs_gpio: qup-spi19-cs-gpio { 3546 pins = "gpio3"; 3547 function = "gpio"; 3548 }; 3549 3550 qup_spi19_data_clk: qup-spi19-data-clk { 3551 pins = "gpio0", "gpio1", 3552 "gpio2"; 3553 function = "qup19"; 3554 }; 3555 3556 qup_uart2_default: qup-uart2-default { 3557 mux { 3558 pins = "gpio117", "gpio118"; 3559 function = "qup2"; 3560 }; 3561 }; 3562 3563 qup_uart6_default: qup-uart6-default { 3564 mux { 3565 pins = "gpio16", "gpio17", 3566 "gpio18", "gpio19"; 3567 function = "qup6"; 3568 }; 3569 }; 3570 3571 qup_uart12_default: qup-uart12-default { 3572 mux { 3573 pins = "gpio34", "gpio35"; 3574 function = "qup12"; 3575 }; 3576 }; 3577 3578 qup_uart17_default: qup-uart17-default { 3579 mux { 3580 pins = "gpio52", "gpio53", 3581 "gpio54", "gpio55"; 3582 function = "qup17"; 3583 }; 3584 }; 3585 3586 qup_uart18_default: qup-uart18-default { 3587 mux { 3588 pins = "gpio58", "gpio59"; 3589 function = "qup18"; 3590 }; 3591 }; 3592 3593 tert_mi2s_active: tert-mi2s-active { 3594 sck { 3595 pins = "gpio133"; 3596 function = "mi2s2_sck"; 3597 drive-strength = <8>; 3598 bias-disable; 3599 }; 3600 3601 data0 { 3602 pins = "gpio134"; 3603 function = "mi2s2_data0"; 3604 drive-strength = <8>; 3605 bias-disable; 3606 output-high; 3607 }; 3608 3609 ws { 3610 pins = "gpio135"; 3611 function = "mi2s2_ws"; 3612 drive-strength = <8>; 3613 output-high; 3614 }; 3615 }; 3616 3617 sdc2_sleep_state: sdc2-sleep { 3618 clk { 3619 pins = "sdc2_clk"; 3620 drive-strength = <2>; 3621 bias-disable; 3622 }; 3623 3624 cmd { 3625 pins = "sdc2_cmd"; 3626 drive-strength = <2>; 3627 bias-pull-up; 3628 }; 3629 3630 data { 3631 pins = "sdc2_data"; 3632 drive-strength = <2>; 3633 bias-pull-up; 3634 }; 3635 }; 3636 3637 pcie0_default_state: pcie0-default { 3638 perst { 3639 pins = "gpio79"; 3640 function = "gpio"; 3641 drive-strength = <2>; 3642 bias-pull-down; 3643 }; 3644 3645 clkreq { 3646 pins = "gpio80"; 3647 function = "pci_e0"; 3648 drive-strength = <2>; 3649 bias-pull-up; 3650 }; 3651 3652 wake { 3653 pins = "gpio81"; 3654 function = "gpio"; 3655 drive-strength = <2>; 3656 bias-pull-up; 3657 }; 3658 }; 3659 3660 pcie1_default_state: pcie1-default { 3661 perst { 3662 pins = "gpio82"; 3663 function = "gpio"; 3664 drive-strength = <2>; 3665 bias-pull-down; 3666 }; 3667 3668 clkreq { 3669 pins = "gpio83"; 3670 function = "pci_e1"; 3671 drive-strength = <2>; 3672 bias-pull-up; 3673 }; 3674 3675 wake { 3676 pins = "gpio84"; 3677 function = "gpio"; 3678 drive-strength = <2>; 3679 bias-pull-up; 3680 }; 3681 }; 3682 3683 pcie2_default_state: pcie2-default { 3684 perst { 3685 pins = "gpio85"; 3686 function = "gpio"; 3687 drive-strength = <2>; 3688 bias-pull-down; 3689 }; 3690 3691 clkreq { 3692 pins = "gpio86"; 3693 function = "pci_e2"; 3694 drive-strength = <2>; 3695 bias-pull-up; 3696 }; 3697 3698 wake { 3699 pins = "gpio87"; 3700 function = "gpio"; 3701 drive-strength = <2>; 3702 bias-pull-up; 3703 }; 3704 }; 3705 }; 3706 3707 apps_smmu: iommu@15000000 { 3708 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 3709 reg = <0 0x15000000 0 0x100000>; 3710 #iommu-cells = <2>; 3711 #global-interrupts = <2>; 3712 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3713 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3714 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3715 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3716 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3717 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3718 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3719 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3720 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3721 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3722 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3723 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3724 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3725 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3726 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3727 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3728 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3729 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3730 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3731 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3732 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3733 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3734 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3735 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3736 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3737 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3738 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3739 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3740 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3741 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3742 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3743 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3744 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3745 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3746 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3747 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3748 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3749 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3750 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3751 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3752 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3753 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3754 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3755 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3756 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3757 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3758 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3759 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3760 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3761 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3762 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3763 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3764 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3765 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3766 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3770 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3771 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3773 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3782 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3783 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3784 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3785 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3786 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3787 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3788 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3789 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3790 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3792 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3793 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3794 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3795 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3796 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3798 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3799 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3800 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3801 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3802 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3803 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3804 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3805 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3806 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3807 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3808 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3809 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3810 }; 3811 3812 adsp: remoteproc@17300000 { 3813 compatible = "qcom,sm8250-adsp-pas"; 3814 reg = <0 0x17300000 0 0x100>; 3815 3816 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 3817 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3818 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3819 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3820 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3821 interrupt-names = "wdog", "fatal", "ready", 3822 "handover", "stop-ack"; 3823 3824 clocks = <&rpmhcc RPMH_CXO_CLK>; 3825 clock-names = "xo"; 3826 3827 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, 3828 <&rpmhpd SM8250_LCX>, 3829 <&rpmhpd SM8250_LMX>; 3830 power-domain-names = "load_state", "lcx", "lmx"; 3831 3832 memory-region = <&adsp_mem>; 3833 3834 qcom,smem-states = <&smp2p_adsp_out 0>; 3835 qcom,smem-state-names = "stop"; 3836 3837 status = "disabled"; 3838 3839 glink-edge { 3840 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3841 IPCC_MPROC_SIGNAL_GLINK_QMP 3842 IRQ_TYPE_EDGE_RISING>; 3843 mboxes = <&ipcc IPCC_CLIENT_LPASS 3844 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3845 3846 label = "lpass"; 3847 qcom,remote-pid = <2>; 3848 3849 apr { 3850 compatible = "qcom,apr-v2"; 3851 qcom,glink-channels = "apr_audio_svc"; 3852 qcom,apr-domain = <APR_DOMAIN_ADSP>; 3853 #address-cells = <1>; 3854 #size-cells = <0>; 3855 3856 apr-service@3 { 3857 reg = <APR_SVC_ADSP_CORE>; 3858 compatible = "qcom,q6core"; 3859 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3860 }; 3861 3862 q6afe: apr-service@4 { 3863 compatible = "qcom,q6afe"; 3864 reg = <APR_SVC_AFE>; 3865 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3866 q6afedai: dais { 3867 compatible = "qcom,q6afe-dais"; 3868 #address-cells = <1>; 3869 #size-cells = <0>; 3870 #sound-dai-cells = <1>; 3871 }; 3872 3873 q6afecc: cc { 3874 compatible = "qcom,q6afe-clocks"; 3875 #clock-cells = <2>; 3876 }; 3877 }; 3878 3879 q6asm: apr-service@7 { 3880 compatible = "qcom,q6asm"; 3881 reg = <APR_SVC_ASM>; 3882 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3883 q6asmdai: dais { 3884 compatible = "qcom,q6asm-dais"; 3885 #address-cells = <1>; 3886 #size-cells = <0>; 3887 #sound-dai-cells = <1>; 3888 iommus = <&apps_smmu 0x1801 0x0>; 3889 }; 3890 }; 3891 3892 q6adm: apr-service@8 { 3893 compatible = "qcom,q6adm"; 3894 reg = <APR_SVC_ADM>; 3895 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3896 q6routing: routing { 3897 compatible = "qcom,q6adm-routing"; 3898 #sound-dai-cells = <0>; 3899 }; 3900 }; 3901 }; 3902 3903 fastrpc { 3904 compatible = "qcom,fastrpc"; 3905 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3906 label = "adsp"; 3907 #address-cells = <1>; 3908 #size-cells = <0>; 3909 3910 compute-cb@3 { 3911 compatible = "qcom,fastrpc-compute-cb"; 3912 reg = <3>; 3913 iommus = <&apps_smmu 0x1803 0x0>; 3914 }; 3915 3916 compute-cb@4 { 3917 compatible = "qcom,fastrpc-compute-cb"; 3918 reg = <4>; 3919 iommus = <&apps_smmu 0x1804 0x0>; 3920 }; 3921 3922 compute-cb@5 { 3923 compatible = "qcom,fastrpc-compute-cb"; 3924 reg = <5>; 3925 iommus = <&apps_smmu 0x1805 0x0>; 3926 }; 3927 }; 3928 }; 3929 }; 3930 3931 intc: interrupt-controller@17a00000 { 3932 compatible = "arm,gic-v3"; 3933 #interrupt-cells = <3>; 3934 interrupt-controller; 3935 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3936 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3937 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3938 }; 3939 3940 watchdog@17c10000 { 3941 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 3942 reg = <0 0x17c10000 0 0x1000>; 3943 clocks = <&sleep_clk>; 3944 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3945 }; 3946 3947 timer@17c20000 { 3948 #address-cells = <2>; 3949 #size-cells = <2>; 3950 ranges; 3951 compatible = "arm,armv7-timer-mem"; 3952 reg = <0x0 0x17c20000 0x0 0x1000>; 3953 clock-frequency = <19200000>; 3954 3955 frame@17c21000 { 3956 frame-number = <0>; 3957 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3958 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3959 reg = <0x0 0x17c21000 0x0 0x1000>, 3960 <0x0 0x17c22000 0x0 0x1000>; 3961 }; 3962 3963 frame@17c23000 { 3964 frame-number = <1>; 3965 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3966 reg = <0x0 0x17c23000 0x0 0x1000>; 3967 status = "disabled"; 3968 }; 3969 3970 frame@17c25000 { 3971 frame-number = <2>; 3972 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3973 reg = <0x0 0x17c25000 0x0 0x1000>; 3974 status = "disabled"; 3975 }; 3976 3977 frame@17c27000 { 3978 frame-number = <3>; 3979 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3980 reg = <0x0 0x17c27000 0x0 0x1000>; 3981 status = "disabled"; 3982 }; 3983 3984 frame@17c29000 { 3985 frame-number = <4>; 3986 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3987 reg = <0x0 0x17c29000 0x0 0x1000>; 3988 status = "disabled"; 3989 }; 3990 3991 frame@17c2b000 { 3992 frame-number = <5>; 3993 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3994 reg = <0x0 0x17c2b000 0x0 0x1000>; 3995 status = "disabled"; 3996 }; 3997 3998 frame@17c2d000 { 3999 frame-number = <6>; 4000 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4001 reg = <0x0 0x17c2d000 0x0 0x1000>; 4002 status = "disabled"; 4003 }; 4004 }; 4005 4006 apps_rsc: rsc@18200000 { 4007 label = "apps_rsc"; 4008 compatible = "qcom,rpmh-rsc"; 4009 reg = <0x0 0x18200000 0x0 0x10000>, 4010 <0x0 0x18210000 0x0 0x10000>, 4011 <0x0 0x18220000 0x0 0x10000>; 4012 reg-names = "drv-0", "drv-1", "drv-2"; 4013 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4014 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4015 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4016 qcom,tcs-offset = <0xd00>; 4017 qcom,drv-id = <2>; 4018 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 4019 <WAKE_TCS 3>, <CONTROL_TCS 1>; 4020 4021 rpmhcc: clock-controller { 4022 compatible = "qcom,sm8250-rpmh-clk"; 4023 #clock-cells = <1>; 4024 clock-names = "xo"; 4025 clocks = <&xo_board>; 4026 }; 4027 4028 rpmhpd: power-controller { 4029 compatible = "qcom,sm8250-rpmhpd"; 4030 #power-domain-cells = <1>; 4031 operating-points-v2 = <&rpmhpd_opp_table>; 4032 4033 rpmhpd_opp_table: opp-table { 4034 compatible = "operating-points-v2"; 4035 4036 rpmhpd_opp_ret: opp1 { 4037 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4038 }; 4039 4040 rpmhpd_opp_min_svs: opp2 { 4041 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4042 }; 4043 4044 rpmhpd_opp_low_svs: opp3 { 4045 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4046 }; 4047 4048 rpmhpd_opp_svs: opp4 { 4049 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4050 }; 4051 4052 rpmhpd_opp_svs_l1: opp5 { 4053 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4054 }; 4055 4056 rpmhpd_opp_nom: opp6 { 4057 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4058 }; 4059 4060 rpmhpd_opp_nom_l1: opp7 { 4061 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4062 }; 4063 4064 rpmhpd_opp_nom_l2: opp8 { 4065 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4066 }; 4067 4068 rpmhpd_opp_turbo: opp9 { 4069 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4070 }; 4071 4072 rpmhpd_opp_turbo_l1: opp10 { 4073 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4074 }; 4075 }; 4076 }; 4077 4078 apps_bcm_voter: bcm_voter { 4079 compatible = "qcom,bcm-voter"; 4080 }; 4081 }; 4082 4083 epss_l3: interconnect@18590000 { 4084 compatible = "qcom,sm8250-epss-l3"; 4085 reg = <0 0x18590000 0 0x1000>; 4086 4087 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4088 clock-names = "xo", "alternate"; 4089 4090 #interconnect-cells = <1>; 4091 }; 4092 4093 cpufreq_hw: cpufreq@18591000 { 4094 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 4095 reg = <0 0x18591000 0 0x1000>, 4096 <0 0x18592000 0 0x1000>, 4097 <0 0x18593000 0 0x1000>; 4098 reg-names = "freq-domain0", "freq-domain1", 4099 "freq-domain2"; 4100 4101 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4102 clock-names = "xo", "alternate"; 4103 4104 #freq-domain-cells = <1>; 4105 }; 4106 }; 4107 4108 timer { 4109 compatible = "arm,armv8-timer"; 4110 interrupts = <GIC_PPI 13 4111 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4112 <GIC_PPI 14 4113 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4114 <GIC_PPI 11 4115 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4116 <GIC_PPI 10 4117 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4118 }; 4119 4120 thermal-zones { 4121 cpu0-thermal { 4122 polling-delay-passive = <250>; 4123 polling-delay = <1000>; 4124 4125 thermal-sensors = <&tsens0 1>; 4126 4127 trips { 4128 cpu0_alert0: trip-point0 { 4129 temperature = <90000>; 4130 hysteresis = <2000>; 4131 type = "passive"; 4132 }; 4133 4134 cpu0_alert1: trip-point1 { 4135 temperature = <95000>; 4136 hysteresis = <2000>; 4137 type = "passive"; 4138 }; 4139 4140 cpu0_crit: cpu_crit { 4141 temperature = <110000>; 4142 hysteresis = <1000>; 4143 type = "critical"; 4144 }; 4145 }; 4146 4147 cooling-maps { 4148 map0 { 4149 trip = <&cpu0_alert0>; 4150 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4151 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4152 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4153 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4154 }; 4155 map1 { 4156 trip = <&cpu0_alert1>; 4157 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4158 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4159 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4160 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4161 }; 4162 }; 4163 }; 4164 4165 cpu1-thermal { 4166 polling-delay-passive = <250>; 4167 polling-delay = <1000>; 4168 4169 thermal-sensors = <&tsens0 2>; 4170 4171 trips { 4172 cpu1_alert0: trip-point0 { 4173 temperature = <90000>; 4174 hysteresis = <2000>; 4175 type = "passive"; 4176 }; 4177 4178 cpu1_alert1: trip-point1 { 4179 temperature = <95000>; 4180 hysteresis = <2000>; 4181 type = "passive"; 4182 }; 4183 4184 cpu1_crit: cpu_crit { 4185 temperature = <110000>; 4186 hysteresis = <1000>; 4187 type = "critical"; 4188 }; 4189 }; 4190 4191 cooling-maps { 4192 map0 { 4193 trip = <&cpu1_alert0>; 4194 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4195 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4196 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4197 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4198 }; 4199 map1 { 4200 trip = <&cpu1_alert1>; 4201 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4202 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4203 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4204 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4205 }; 4206 }; 4207 }; 4208 4209 cpu2-thermal { 4210 polling-delay-passive = <250>; 4211 polling-delay = <1000>; 4212 4213 thermal-sensors = <&tsens0 3>; 4214 4215 trips { 4216 cpu2_alert0: trip-point0 { 4217 temperature = <90000>; 4218 hysteresis = <2000>; 4219 type = "passive"; 4220 }; 4221 4222 cpu2_alert1: trip-point1 { 4223 temperature = <95000>; 4224 hysteresis = <2000>; 4225 type = "passive"; 4226 }; 4227 4228 cpu2_crit: cpu_crit { 4229 temperature = <110000>; 4230 hysteresis = <1000>; 4231 type = "critical"; 4232 }; 4233 }; 4234 4235 cooling-maps { 4236 map0 { 4237 trip = <&cpu2_alert0>; 4238 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4239 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4240 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4241 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4242 }; 4243 map1 { 4244 trip = <&cpu2_alert1>; 4245 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4246 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4247 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4248 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4249 }; 4250 }; 4251 }; 4252 4253 cpu3-thermal { 4254 polling-delay-passive = <250>; 4255 polling-delay = <1000>; 4256 4257 thermal-sensors = <&tsens0 4>; 4258 4259 trips { 4260 cpu3_alert0: trip-point0 { 4261 temperature = <90000>; 4262 hysteresis = <2000>; 4263 type = "passive"; 4264 }; 4265 4266 cpu3_alert1: trip-point1 { 4267 temperature = <95000>; 4268 hysteresis = <2000>; 4269 type = "passive"; 4270 }; 4271 4272 cpu3_crit: cpu_crit { 4273 temperature = <110000>; 4274 hysteresis = <1000>; 4275 type = "critical"; 4276 }; 4277 }; 4278 4279 cooling-maps { 4280 map0 { 4281 trip = <&cpu3_alert0>; 4282 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4283 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4284 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4285 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4286 }; 4287 map1 { 4288 trip = <&cpu3_alert1>; 4289 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4290 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4291 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4292 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4293 }; 4294 }; 4295 }; 4296 4297 cpu4-top-thermal { 4298 polling-delay-passive = <250>; 4299 polling-delay = <1000>; 4300 4301 thermal-sensors = <&tsens0 7>; 4302 4303 trips { 4304 cpu4_top_alert0: trip-point0 { 4305 temperature = <90000>; 4306 hysteresis = <2000>; 4307 type = "passive"; 4308 }; 4309 4310 cpu4_top_alert1: trip-point1 { 4311 temperature = <95000>; 4312 hysteresis = <2000>; 4313 type = "passive"; 4314 }; 4315 4316 cpu4_top_crit: cpu_crit { 4317 temperature = <110000>; 4318 hysteresis = <1000>; 4319 type = "critical"; 4320 }; 4321 }; 4322 4323 cooling-maps { 4324 map0 { 4325 trip = <&cpu4_top_alert0>; 4326 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4327 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4328 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4329 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4330 }; 4331 map1 { 4332 trip = <&cpu4_top_alert1>; 4333 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4334 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4335 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4336 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4337 }; 4338 }; 4339 }; 4340 4341 cpu5-top-thermal { 4342 polling-delay-passive = <250>; 4343 polling-delay = <1000>; 4344 4345 thermal-sensors = <&tsens0 8>; 4346 4347 trips { 4348 cpu5_top_alert0: trip-point0 { 4349 temperature = <90000>; 4350 hysteresis = <2000>; 4351 type = "passive"; 4352 }; 4353 4354 cpu5_top_alert1: trip-point1 { 4355 temperature = <95000>; 4356 hysteresis = <2000>; 4357 type = "passive"; 4358 }; 4359 4360 cpu5_top_crit: cpu_crit { 4361 temperature = <110000>; 4362 hysteresis = <1000>; 4363 type = "critical"; 4364 }; 4365 }; 4366 4367 cooling-maps { 4368 map0 { 4369 trip = <&cpu5_top_alert0>; 4370 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4371 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4372 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4373 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4374 }; 4375 map1 { 4376 trip = <&cpu5_top_alert1>; 4377 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4378 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4379 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4380 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4381 }; 4382 }; 4383 }; 4384 4385 cpu6-top-thermal { 4386 polling-delay-passive = <250>; 4387 polling-delay = <1000>; 4388 4389 thermal-sensors = <&tsens0 9>; 4390 4391 trips { 4392 cpu6_top_alert0: trip-point0 { 4393 temperature = <90000>; 4394 hysteresis = <2000>; 4395 type = "passive"; 4396 }; 4397 4398 cpu6_top_alert1: trip-point1 { 4399 temperature = <95000>; 4400 hysteresis = <2000>; 4401 type = "passive"; 4402 }; 4403 4404 cpu6_top_crit: cpu_crit { 4405 temperature = <110000>; 4406 hysteresis = <1000>; 4407 type = "critical"; 4408 }; 4409 }; 4410 4411 cooling-maps { 4412 map0 { 4413 trip = <&cpu6_top_alert0>; 4414 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4415 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4416 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4417 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4418 }; 4419 map1 { 4420 trip = <&cpu6_top_alert1>; 4421 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4422 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4423 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4424 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4425 }; 4426 }; 4427 }; 4428 4429 cpu7-top-thermal { 4430 polling-delay-passive = <250>; 4431 polling-delay = <1000>; 4432 4433 thermal-sensors = <&tsens0 10>; 4434 4435 trips { 4436 cpu7_top_alert0: trip-point0 { 4437 temperature = <90000>; 4438 hysteresis = <2000>; 4439 type = "passive"; 4440 }; 4441 4442 cpu7_top_alert1: trip-point1 { 4443 temperature = <95000>; 4444 hysteresis = <2000>; 4445 type = "passive"; 4446 }; 4447 4448 cpu7_top_crit: cpu_crit { 4449 temperature = <110000>; 4450 hysteresis = <1000>; 4451 type = "critical"; 4452 }; 4453 }; 4454 4455 cooling-maps { 4456 map0 { 4457 trip = <&cpu7_top_alert0>; 4458 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4459 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4460 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4461 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4462 }; 4463 map1 { 4464 trip = <&cpu7_top_alert1>; 4465 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4466 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4467 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4468 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4469 }; 4470 }; 4471 }; 4472 4473 cpu4-bottom-thermal { 4474 polling-delay-passive = <250>; 4475 polling-delay = <1000>; 4476 4477 thermal-sensors = <&tsens0 11>; 4478 4479 trips { 4480 cpu4_bottom_alert0: trip-point0 { 4481 temperature = <90000>; 4482 hysteresis = <2000>; 4483 type = "passive"; 4484 }; 4485 4486 cpu4_bottom_alert1: trip-point1 { 4487 temperature = <95000>; 4488 hysteresis = <2000>; 4489 type = "passive"; 4490 }; 4491 4492 cpu4_bottom_crit: cpu_crit { 4493 temperature = <110000>; 4494 hysteresis = <1000>; 4495 type = "critical"; 4496 }; 4497 }; 4498 4499 cooling-maps { 4500 map0 { 4501 trip = <&cpu4_bottom_alert0>; 4502 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4503 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4504 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4505 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4506 }; 4507 map1 { 4508 trip = <&cpu4_bottom_alert1>; 4509 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4510 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4511 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4512 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4513 }; 4514 }; 4515 }; 4516 4517 cpu5-bottom-thermal { 4518 polling-delay-passive = <250>; 4519 polling-delay = <1000>; 4520 4521 thermal-sensors = <&tsens0 12>; 4522 4523 trips { 4524 cpu5_bottom_alert0: trip-point0 { 4525 temperature = <90000>; 4526 hysteresis = <2000>; 4527 type = "passive"; 4528 }; 4529 4530 cpu5_bottom_alert1: trip-point1 { 4531 temperature = <95000>; 4532 hysteresis = <2000>; 4533 type = "passive"; 4534 }; 4535 4536 cpu5_bottom_crit: cpu_crit { 4537 temperature = <110000>; 4538 hysteresis = <1000>; 4539 type = "critical"; 4540 }; 4541 }; 4542 4543 cooling-maps { 4544 map0 { 4545 trip = <&cpu5_bottom_alert0>; 4546 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4547 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4548 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4549 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4550 }; 4551 map1 { 4552 trip = <&cpu5_bottom_alert1>; 4553 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4554 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4555 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4556 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4557 }; 4558 }; 4559 }; 4560 4561 cpu6-bottom-thermal { 4562 polling-delay-passive = <250>; 4563 polling-delay = <1000>; 4564 4565 thermal-sensors = <&tsens0 13>; 4566 4567 trips { 4568 cpu6_bottom_alert0: trip-point0 { 4569 temperature = <90000>; 4570 hysteresis = <2000>; 4571 type = "passive"; 4572 }; 4573 4574 cpu6_bottom_alert1: trip-point1 { 4575 temperature = <95000>; 4576 hysteresis = <2000>; 4577 type = "passive"; 4578 }; 4579 4580 cpu6_bottom_crit: cpu_crit { 4581 temperature = <110000>; 4582 hysteresis = <1000>; 4583 type = "critical"; 4584 }; 4585 }; 4586 4587 cooling-maps { 4588 map0 { 4589 trip = <&cpu6_bottom_alert0>; 4590 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4591 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4592 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4593 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4594 }; 4595 map1 { 4596 trip = <&cpu6_bottom_alert1>; 4597 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4598 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4599 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4600 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4601 }; 4602 }; 4603 }; 4604 4605 cpu7-bottom-thermal { 4606 polling-delay-passive = <250>; 4607 polling-delay = <1000>; 4608 4609 thermal-sensors = <&tsens0 14>; 4610 4611 trips { 4612 cpu7_bottom_alert0: trip-point0 { 4613 temperature = <90000>; 4614 hysteresis = <2000>; 4615 type = "passive"; 4616 }; 4617 4618 cpu7_bottom_alert1: trip-point1 { 4619 temperature = <95000>; 4620 hysteresis = <2000>; 4621 type = "passive"; 4622 }; 4623 4624 cpu7_bottom_crit: cpu_crit { 4625 temperature = <110000>; 4626 hysteresis = <1000>; 4627 type = "critical"; 4628 }; 4629 }; 4630 4631 cooling-maps { 4632 map0 { 4633 trip = <&cpu7_bottom_alert0>; 4634 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4635 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4636 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4637 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4638 }; 4639 map1 { 4640 trip = <&cpu7_bottom_alert1>; 4641 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4642 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4643 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4644 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4645 }; 4646 }; 4647 }; 4648 4649 aoss0-thermal { 4650 polling-delay-passive = <250>; 4651 polling-delay = <1000>; 4652 4653 thermal-sensors = <&tsens0 0>; 4654 4655 trips { 4656 aoss0_alert0: trip-point0 { 4657 temperature = <90000>; 4658 hysteresis = <2000>; 4659 type = "hot"; 4660 }; 4661 }; 4662 }; 4663 4664 cluster0-thermal { 4665 polling-delay-passive = <250>; 4666 polling-delay = <1000>; 4667 4668 thermal-sensors = <&tsens0 5>; 4669 4670 trips { 4671 cluster0_alert0: trip-point0 { 4672 temperature = <90000>; 4673 hysteresis = <2000>; 4674 type = "hot"; 4675 }; 4676 cluster0_crit: cluster0_crit { 4677 temperature = <110000>; 4678 hysteresis = <2000>; 4679 type = "critical"; 4680 }; 4681 }; 4682 }; 4683 4684 cluster1-thermal { 4685 polling-delay-passive = <250>; 4686 polling-delay = <1000>; 4687 4688 thermal-sensors = <&tsens0 6>; 4689 4690 trips { 4691 cluster1_alert0: trip-point0 { 4692 temperature = <90000>; 4693 hysteresis = <2000>; 4694 type = "hot"; 4695 }; 4696 cluster1_crit: cluster1_crit { 4697 temperature = <110000>; 4698 hysteresis = <2000>; 4699 type = "critical"; 4700 }; 4701 }; 4702 }; 4703 4704 gpu-thermal-top { 4705 polling-delay-passive = <250>; 4706 polling-delay = <1000>; 4707 4708 thermal-sensors = <&tsens0 15>; 4709 4710 trips { 4711 gpu1_alert0: trip-point0 { 4712 temperature = <90000>; 4713 hysteresis = <2000>; 4714 type = "hot"; 4715 }; 4716 }; 4717 }; 4718 4719 aoss1-thermal { 4720 polling-delay-passive = <250>; 4721 polling-delay = <1000>; 4722 4723 thermal-sensors = <&tsens1 0>; 4724 4725 trips { 4726 aoss1_alert0: trip-point0 { 4727 temperature = <90000>; 4728 hysteresis = <2000>; 4729 type = "hot"; 4730 }; 4731 }; 4732 }; 4733 4734 wlan-thermal { 4735 polling-delay-passive = <250>; 4736 polling-delay = <1000>; 4737 4738 thermal-sensors = <&tsens1 1>; 4739 4740 trips { 4741 wlan_alert0: trip-point0 { 4742 temperature = <90000>; 4743 hysteresis = <2000>; 4744 type = "hot"; 4745 }; 4746 }; 4747 }; 4748 4749 video-thermal { 4750 polling-delay-passive = <250>; 4751 polling-delay = <1000>; 4752 4753 thermal-sensors = <&tsens1 2>; 4754 4755 trips { 4756 video_alert0: trip-point0 { 4757 temperature = <90000>; 4758 hysteresis = <2000>; 4759 type = "hot"; 4760 }; 4761 }; 4762 }; 4763 4764 mem-thermal { 4765 polling-delay-passive = <250>; 4766 polling-delay = <1000>; 4767 4768 thermal-sensors = <&tsens1 3>; 4769 4770 trips { 4771 mem_alert0: trip-point0 { 4772 temperature = <90000>; 4773 hysteresis = <2000>; 4774 type = "hot"; 4775 }; 4776 }; 4777 }; 4778 4779 q6-hvx-thermal { 4780 polling-delay-passive = <250>; 4781 polling-delay = <1000>; 4782 4783 thermal-sensors = <&tsens1 4>; 4784 4785 trips { 4786 q6_hvx_alert0: trip-point0 { 4787 temperature = <90000>; 4788 hysteresis = <2000>; 4789 type = "hot"; 4790 }; 4791 }; 4792 }; 4793 4794 camera-thermal { 4795 polling-delay-passive = <250>; 4796 polling-delay = <1000>; 4797 4798 thermal-sensors = <&tsens1 5>; 4799 4800 trips { 4801 camera_alert0: trip-point0 { 4802 temperature = <90000>; 4803 hysteresis = <2000>; 4804 type = "hot"; 4805 }; 4806 }; 4807 }; 4808 4809 compute-thermal { 4810 polling-delay-passive = <250>; 4811 polling-delay = <1000>; 4812 4813 thermal-sensors = <&tsens1 6>; 4814 4815 trips { 4816 compute_alert0: trip-point0 { 4817 temperature = <90000>; 4818 hysteresis = <2000>; 4819 type = "hot"; 4820 }; 4821 }; 4822 }; 4823 4824 npu-thermal { 4825 polling-delay-passive = <250>; 4826 polling-delay = <1000>; 4827 4828 thermal-sensors = <&tsens1 7>; 4829 4830 trips { 4831 npu_alert0: trip-point0 { 4832 temperature = <90000>; 4833 hysteresis = <2000>; 4834 type = "hot"; 4835 }; 4836 }; 4837 }; 4838 4839 gpu-thermal-bottom { 4840 polling-delay-passive = <250>; 4841 polling-delay = <1000>; 4842 4843 thermal-sensors = <&tsens1 8>; 4844 4845 trips { 4846 gpu2_alert0: trip-point0 { 4847 temperature = <90000>; 4848 hysteresis = <2000>; 4849 type = "hot"; 4850 }; 4851 }; 4852 }; 4853 }; 4854}; 4855