1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sm8250.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/soc/qcom,apr.h> 18#include <dt-bindings/soc/qcom,rpmh-rsc.h> 19#include <dt-bindings/sound/qcom,q6afe.h> 20#include <dt-bindings/thermal/thermal.h> 21#include <dt-bindings/clock/qcom,videocc-sm8250.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 aliases { 30 i2c0 = &i2c0; 31 i2c1 = &i2c1; 32 i2c2 = &i2c2; 33 i2c3 = &i2c3; 34 i2c4 = &i2c4; 35 i2c5 = &i2c5; 36 i2c6 = &i2c6; 37 i2c7 = &i2c7; 38 i2c8 = &i2c8; 39 i2c9 = &i2c9; 40 i2c10 = &i2c10; 41 i2c11 = &i2c11; 42 i2c12 = &i2c12; 43 i2c13 = &i2c13; 44 i2c14 = &i2c14; 45 i2c15 = &i2c15; 46 i2c16 = &i2c16; 47 i2c17 = &i2c17; 48 i2c18 = &i2c18; 49 i2c19 = &i2c19; 50 spi0 = &spi0; 51 spi1 = &spi1; 52 spi2 = &spi2; 53 spi3 = &spi3; 54 spi4 = &spi4; 55 spi5 = &spi5; 56 spi6 = &spi6; 57 spi7 = &spi7; 58 spi8 = &spi8; 59 spi9 = &spi9; 60 spi10 = &spi10; 61 spi11 = &spi11; 62 spi12 = &spi12; 63 spi13 = &spi13; 64 spi14 = &spi14; 65 spi15 = &spi15; 66 spi16 = &spi16; 67 spi17 = &spi17; 68 spi18 = &spi18; 69 spi19 = &spi19; 70 }; 71 72 chosen { }; 73 74 clocks { 75 xo_board: xo-board { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <38400000>; 79 clock-output-names = "xo_board"; 80 }; 81 82 sleep_clk: sleep-clk { 83 compatible = "fixed-clock"; 84 clock-frequency = <32768>; 85 #clock-cells = <0>; 86 }; 87 }; 88 89 cpus { 90 #address-cells = <2>; 91 #size-cells = <0>; 92 93 CPU0: cpu@0 { 94 device_type = "cpu"; 95 compatible = "qcom,kryo485"; 96 reg = <0x0 0x0>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <448>; 99 dynamic-power-coefficient = <205>; 100 next-level-cache = <&L2_0>; 101 qcom,freq-domain = <&cpufreq_hw 0>; 102 operating-points-v2 = <&cpu0_opp_table>; 103 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 104 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 105 #cooling-cells = <2>; 106 L2_0: l2-cache { 107 compatible = "cache"; 108 next-level-cache = <&L3_0>; 109 L3_0: l3-cache { 110 compatible = "cache"; 111 }; 112 }; 113 }; 114 115 CPU1: cpu@100 { 116 device_type = "cpu"; 117 compatible = "qcom,kryo485"; 118 reg = <0x0 0x100>; 119 enable-method = "psci"; 120 capacity-dmips-mhz = <448>; 121 dynamic-power-coefficient = <205>; 122 next-level-cache = <&L2_100>; 123 qcom,freq-domain = <&cpufreq_hw 0>; 124 operating-points-v2 = <&cpu0_opp_table>; 125 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 126 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 127 #cooling-cells = <2>; 128 L2_100: l2-cache { 129 compatible = "cache"; 130 next-level-cache = <&L3_0>; 131 }; 132 }; 133 134 CPU2: cpu@200 { 135 device_type = "cpu"; 136 compatible = "qcom,kryo485"; 137 reg = <0x0 0x200>; 138 enable-method = "psci"; 139 capacity-dmips-mhz = <448>; 140 dynamic-power-coefficient = <205>; 141 next-level-cache = <&L2_200>; 142 qcom,freq-domain = <&cpufreq_hw 0>; 143 operating-points-v2 = <&cpu0_opp_table>; 144 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 145 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 146 #cooling-cells = <2>; 147 L2_200: l2-cache { 148 compatible = "cache"; 149 next-level-cache = <&L3_0>; 150 }; 151 }; 152 153 CPU3: cpu@300 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo485"; 156 reg = <0x0 0x300>; 157 enable-method = "psci"; 158 capacity-dmips-mhz = <448>; 159 dynamic-power-coefficient = <205>; 160 next-level-cache = <&L2_300>; 161 qcom,freq-domain = <&cpufreq_hw 0>; 162 operating-points-v2 = <&cpu0_opp_table>; 163 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 164 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 165 #cooling-cells = <2>; 166 L2_300: l2-cache { 167 compatible = "cache"; 168 next-level-cache = <&L3_0>; 169 }; 170 }; 171 172 CPU4: cpu@400 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo485"; 175 reg = <0x0 0x400>; 176 enable-method = "psci"; 177 capacity-dmips-mhz = <1024>; 178 dynamic-power-coefficient = <379>; 179 next-level-cache = <&L2_400>; 180 qcom,freq-domain = <&cpufreq_hw 1>; 181 operating-points-v2 = <&cpu4_opp_table>; 182 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 183 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 184 #cooling-cells = <2>; 185 L2_400: l2-cache { 186 compatible = "cache"; 187 next-level-cache = <&L3_0>; 188 }; 189 }; 190 191 CPU5: cpu@500 { 192 device_type = "cpu"; 193 compatible = "qcom,kryo485"; 194 reg = <0x0 0x500>; 195 enable-method = "psci"; 196 capacity-dmips-mhz = <1024>; 197 dynamic-power-coefficient = <379>; 198 next-level-cache = <&L2_500>; 199 qcom,freq-domain = <&cpufreq_hw 1>; 200 operating-points-v2 = <&cpu4_opp_table>; 201 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 202 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 203 #cooling-cells = <2>; 204 L2_500: l2-cache { 205 compatible = "cache"; 206 next-level-cache = <&L3_0>; 207 }; 208 209 }; 210 211 CPU6: cpu@600 { 212 device_type = "cpu"; 213 compatible = "qcom,kryo485"; 214 reg = <0x0 0x600>; 215 enable-method = "psci"; 216 capacity-dmips-mhz = <1024>; 217 dynamic-power-coefficient = <379>; 218 next-level-cache = <&L2_600>; 219 qcom,freq-domain = <&cpufreq_hw 1>; 220 operating-points-v2 = <&cpu4_opp_table>; 221 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 222 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 223 #cooling-cells = <2>; 224 L2_600: l2-cache { 225 compatible = "cache"; 226 next-level-cache = <&L3_0>; 227 }; 228 }; 229 230 CPU7: cpu@700 { 231 device_type = "cpu"; 232 compatible = "qcom,kryo485"; 233 reg = <0x0 0x700>; 234 enable-method = "psci"; 235 capacity-dmips-mhz = <1024>; 236 dynamic-power-coefficient = <444>; 237 next-level-cache = <&L2_700>; 238 qcom,freq-domain = <&cpufreq_hw 2>; 239 operating-points-v2 = <&cpu7_opp_table>; 240 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 241 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 242 #cooling-cells = <2>; 243 L2_700: l2-cache { 244 compatible = "cache"; 245 next-level-cache = <&L3_0>; 246 }; 247 }; 248 249 cpu-map { 250 cluster0 { 251 core0 { 252 cpu = <&CPU0>; 253 }; 254 255 core1 { 256 cpu = <&CPU1>; 257 }; 258 259 core2 { 260 cpu = <&CPU2>; 261 }; 262 263 core3 { 264 cpu = <&CPU3>; 265 }; 266 267 core4 { 268 cpu = <&CPU4>; 269 }; 270 271 core5 { 272 cpu = <&CPU5>; 273 }; 274 275 core6 { 276 cpu = <&CPU6>; 277 }; 278 279 core7 { 280 cpu = <&CPU7>; 281 }; 282 }; 283 }; 284 }; 285 286 cpu0_opp_table: cpu0_opp_table { 287 compatible = "operating-points-v2"; 288 opp-shared; 289 290 cpu0_opp1: opp-300000000 { 291 opp-hz = /bits/ 64 <300000000>; 292 opp-peak-kBps = <800000 9600000>; 293 }; 294 295 cpu0_opp2: opp-403200000 { 296 opp-hz = /bits/ 64 <403200000>; 297 opp-peak-kBps = <800000 9600000>; 298 }; 299 300 cpu0_opp3: opp-518400000 { 301 opp-hz = /bits/ 64 <518400000>; 302 opp-peak-kBps = <800000 16588800>; 303 }; 304 305 cpu0_opp4: opp-614400000 { 306 opp-hz = /bits/ 64 <614400000>; 307 opp-peak-kBps = <800000 16588800>; 308 }; 309 310 cpu0_opp5: opp-691200000 { 311 opp-hz = /bits/ 64 <691200000>; 312 opp-peak-kBps = <800000 19660800>; 313 }; 314 315 cpu0_opp6: opp-787200000 { 316 opp-hz = /bits/ 64 <787200000>; 317 opp-peak-kBps = <1804000 19660800>; 318 }; 319 320 cpu0_opp7: opp-883200000 { 321 opp-hz = /bits/ 64 <883200000>; 322 opp-peak-kBps = <1804000 23347200>; 323 }; 324 325 cpu0_opp8: opp-979200000 { 326 opp-hz = /bits/ 64 <979200000>; 327 opp-peak-kBps = <1804000 26419200>; 328 }; 329 330 cpu0_opp9: opp-1075200000 { 331 opp-hz = /bits/ 64 <1075200000>; 332 opp-peak-kBps = <1804000 29491200>; 333 }; 334 335 cpu0_opp10: opp-1171200000 { 336 opp-hz = /bits/ 64 <1171200000>; 337 opp-peak-kBps = <1804000 32563200>; 338 }; 339 340 cpu0_opp11: opp-1248000000 { 341 opp-hz = /bits/ 64 <1248000000>; 342 opp-peak-kBps = <1804000 36249600>; 343 }; 344 345 cpu0_opp12: opp-1344000000 { 346 opp-hz = /bits/ 64 <1344000000>; 347 opp-peak-kBps = <2188000 36249600>; 348 }; 349 350 cpu0_opp13: opp-1420800000 { 351 opp-hz = /bits/ 64 <1420800000>; 352 opp-peak-kBps = <2188000 39321600>; 353 }; 354 355 cpu0_opp14: opp-1516800000 { 356 opp-hz = /bits/ 64 <1516800000>; 357 opp-peak-kBps = <3072000 42393600>; 358 }; 359 360 cpu0_opp15: opp-1612800000 { 361 opp-hz = /bits/ 64 <1612800000>; 362 opp-peak-kBps = <3072000 42393600>; 363 }; 364 365 cpu0_opp16: opp-1708800000 { 366 opp-hz = /bits/ 64 <1708800000>; 367 opp-peak-kBps = <4068000 42393600>; 368 }; 369 370 cpu0_opp17: opp-1804800000 { 371 opp-hz = /bits/ 64 <1804800000>; 372 opp-peak-kBps = <4068000 42393600>; 373 }; 374 }; 375 376 cpu4_opp_table: cpu4_opp_table { 377 compatible = "operating-points-v2"; 378 opp-shared; 379 380 cpu4_opp1: opp-710400000 { 381 opp-hz = /bits/ 64 <710400000>; 382 opp-peak-kBps = <1804000 19660800>; 383 }; 384 385 cpu4_opp2: opp-825600000 { 386 opp-hz = /bits/ 64 <825600000>; 387 opp-peak-kBps = <2188000 23347200>; 388 }; 389 390 cpu4_opp3: opp-940800000 { 391 opp-hz = /bits/ 64 <940800000>; 392 opp-peak-kBps = <2188000 26419200>; 393 }; 394 395 cpu4_opp4: opp-1056000000 { 396 opp-hz = /bits/ 64 <1056000000>; 397 opp-peak-kBps = <3072000 26419200>; 398 }; 399 400 cpu4_opp5: opp-1171200000 { 401 opp-hz = /bits/ 64 <1171200000>; 402 opp-peak-kBps = <3072000 29491200>; 403 }; 404 405 cpu4_opp6: opp-1286400000 { 406 opp-hz = /bits/ 64 <1286400000>; 407 opp-peak-kBps = <4068000 29491200>; 408 }; 409 410 cpu4_opp7: opp-1382400000 { 411 opp-hz = /bits/ 64 <1382400000>; 412 opp-peak-kBps = <4068000 32563200>; 413 }; 414 415 cpu4_opp8: opp-1478400000 { 416 opp-hz = /bits/ 64 <1478400000>; 417 opp-peak-kBps = <4068000 32563200>; 418 }; 419 420 cpu4_opp9: opp-1574400000 { 421 opp-hz = /bits/ 64 <1574400000>; 422 opp-peak-kBps = <5412000 39321600>; 423 }; 424 425 cpu4_opp10: opp-1670400000 { 426 opp-hz = /bits/ 64 <1670400000>; 427 opp-peak-kBps = <5412000 42393600>; 428 }; 429 430 cpu4_opp11: opp-1766400000 { 431 opp-hz = /bits/ 64 <1766400000>; 432 opp-peak-kBps = <5412000 45465600>; 433 }; 434 435 cpu4_opp12: opp-1862400000 { 436 opp-hz = /bits/ 64 <1862400000>; 437 opp-peak-kBps = <6220000 45465600>; 438 }; 439 440 cpu4_opp13: opp-1958400000 { 441 opp-hz = /bits/ 64 <1958400000>; 442 opp-peak-kBps = <6220000 48537600>; 443 }; 444 445 cpu4_opp14: opp-2054400000 { 446 opp-hz = /bits/ 64 <2054400000>; 447 opp-peak-kBps = <7216000 48537600>; 448 }; 449 450 cpu4_opp15: opp-2150400000 { 451 opp-hz = /bits/ 64 <2150400000>; 452 opp-peak-kBps = <7216000 51609600>; 453 }; 454 455 cpu4_opp16: opp-2246400000 { 456 opp-hz = /bits/ 64 <2246400000>; 457 opp-peak-kBps = <7216000 51609600>; 458 }; 459 460 cpu4_opp17: opp-2342400000 { 461 opp-hz = /bits/ 64 <2342400000>; 462 opp-peak-kBps = <8368000 51609600>; 463 }; 464 465 cpu4_opp18: opp-2419200000 { 466 opp-hz = /bits/ 64 <2419200000>; 467 opp-peak-kBps = <8368000 51609600>; 468 }; 469 }; 470 471 cpu7_opp_table: cpu7_opp_table { 472 compatible = "operating-points-v2"; 473 opp-shared; 474 475 cpu7_opp1: opp-844800000 { 476 opp-hz = /bits/ 64 <844800000>; 477 opp-peak-kBps = <2188000 19660800>; 478 }; 479 480 cpu7_opp2: opp-960000000 { 481 opp-hz = /bits/ 64 <960000000>; 482 opp-peak-kBps = <2188000 26419200>; 483 }; 484 485 cpu7_opp3: opp-1075200000 { 486 opp-hz = /bits/ 64 <1075200000>; 487 opp-peak-kBps = <3072000 26419200>; 488 }; 489 490 cpu7_opp4: opp-1190400000 { 491 opp-hz = /bits/ 64 <1190400000>; 492 opp-peak-kBps = <3072000 29491200>; 493 }; 494 495 cpu7_opp5: opp-1305600000 { 496 opp-hz = /bits/ 64 <1305600000>; 497 opp-peak-kBps = <4068000 32563200>; 498 }; 499 500 cpu7_opp6: opp-1401600000 { 501 opp-hz = /bits/ 64 <1401600000>; 502 opp-peak-kBps = <4068000 32563200>; 503 }; 504 505 cpu7_opp7: opp-1516800000 { 506 opp-hz = /bits/ 64 <1516800000>; 507 opp-peak-kBps = <4068000 36249600>; 508 }; 509 510 cpu7_opp8: opp-1632000000 { 511 opp-hz = /bits/ 64 <1632000000>; 512 opp-peak-kBps = <5412000 39321600>; 513 }; 514 515 cpu7_opp9: opp-1747200000 { 516 opp-hz = /bits/ 64 <1708800000>; 517 opp-peak-kBps = <5412000 42393600>; 518 }; 519 520 cpu7_opp10: opp-1862400000 { 521 opp-hz = /bits/ 64 <1862400000>; 522 opp-peak-kBps = <6220000 45465600>; 523 }; 524 525 cpu7_opp11: opp-1977600000 { 526 opp-hz = /bits/ 64 <1977600000>; 527 opp-peak-kBps = <6220000 48537600>; 528 }; 529 530 cpu7_opp12: opp-2073600000 { 531 opp-hz = /bits/ 64 <2073600000>; 532 opp-peak-kBps = <7216000 48537600>; 533 }; 534 535 cpu7_opp13: opp-2169600000 { 536 opp-hz = /bits/ 64 <2169600000>; 537 opp-peak-kBps = <7216000 51609600>; 538 }; 539 540 cpu7_opp14: opp-2265600000 { 541 opp-hz = /bits/ 64 <2265600000>; 542 opp-peak-kBps = <7216000 51609600>; 543 }; 544 545 cpu7_opp15: opp-2361600000 { 546 opp-hz = /bits/ 64 <2361600000>; 547 opp-peak-kBps = <8368000 51609600>; 548 }; 549 550 cpu7_opp16: opp-2457600000 { 551 opp-hz = /bits/ 64 <2457600000>; 552 opp-peak-kBps = <8368000 51609600>; 553 }; 554 555 cpu7_opp17: opp-2553600000 { 556 opp-hz = /bits/ 64 <2553600000>; 557 opp-peak-kBps = <8368000 51609600>; 558 }; 559 560 cpu7_opp18: opp-2649600000 { 561 opp-hz = /bits/ 64 <2649600000>; 562 opp-peak-kBps = <8368000 51609600>; 563 }; 564 565 cpu7_opp19: opp-2745600000 { 566 opp-hz = /bits/ 64 <2745600000>; 567 opp-peak-kBps = <8368000 51609600>; 568 }; 569 570 cpu7_opp20: opp-2841600000 { 571 opp-hz = /bits/ 64 <2841600000>; 572 opp-peak-kBps = <8368000 51609600>; 573 }; 574 }; 575 576 firmware { 577 scm: scm { 578 compatible = "qcom,scm"; 579 #reset-cells = <1>; 580 }; 581 }; 582 583 memory@80000000 { 584 device_type = "memory"; 585 /* We expect the bootloader to fill in the size */ 586 reg = <0x0 0x80000000 0x0 0x0>; 587 }; 588 589 pmu { 590 compatible = "arm,armv8-pmuv3"; 591 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 592 }; 593 594 psci { 595 compatible = "arm,psci-1.0"; 596 method = "smc"; 597 }; 598 599 reserved-memory { 600 #address-cells = <2>; 601 #size-cells = <2>; 602 ranges; 603 604 hyp_mem: memory@80000000 { 605 reg = <0x0 0x80000000 0x0 0x600000>; 606 no-map; 607 }; 608 609 xbl_aop_mem: memory@80700000 { 610 reg = <0x0 0x80700000 0x0 0x160000>; 611 no-map; 612 }; 613 614 cmd_db: memory@80860000 { 615 compatible = "qcom,cmd-db"; 616 reg = <0x0 0x80860000 0x0 0x20000>; 617 no-map; 618 }; 619 620 smem_mem: memory@80900000 { 621 reg = <0x0 0x80900000 0x0 0x200000>; 622 no-map; 623 }; 624 625 removed_mem: memory@80b00000 { 626 reg = <0x0 0x80b00000 0x0 0x5300000>; 627 no-map; 628 }; 629 630 camera_mem: memory@86200000 { 631 reg = <0x0 0x86200000 0x0 0x500000>; 632 no-map; 633 }; 634 635 wlan_mem: memory@86700000 { 636 reg = <0x0 0x86700000 0x0 0x100000>; 637 no-map; 638 }; 639 640 ipa_fw_mem: memory@86800000 { 641 reg = <0x0 0x86800000 0x0 0x10000>; 642 no-map; 643 }; 644 645 ipa_gsi_mem: memory@86810000 { 646 reg = <0x0 0x86810000 0x0 0xa000>; 647 no-map; 648 }; 649 650 gpu_mem: memory@8681a000 { 651 reg = <0x0 0x8681a000 0x0 0x2000>; 652 no-map; 653 }; 654 655 npu_mem: memory@86900000 { 656 reg = <0x0 0x86900000 0x0 0x500000>; 657 no-map; 658 }; 659 660 video_mem: memory@86e00000 { 661 reg = <0x0 0x86e00000 0x0 0x500000>; 662 no-map; 663 }; 664 665 cvp_mem: memory@87300000 { 666 reg = <0x0 0x87300000 0x0 0x500000>; 667 no-map; 668 }; 669 670 cdsp_mem: memory@87800000 { 671 reg = <0x0 0x87800000 0x0 0x1400000>; 672 no-map; 673 }; 674 675 slpi_mem: memory@88c00000 { 676 reg = <0x0 0x88c00000 0x0 0x1500000>; 677 no-map; 678 }; 679 680 adsp_mem: memory@8a100000 { 681 reg = <0x0 0x8a100000 0x0 0x1d00000>; 682 no-map; 683 }; 684 685 spss_mem: memory@8be00000 { 686 reg = <0x0 0x8be00000 0x0 0x100000>; 687 no-map; 688 }; 689 690 cdsp_secure_heap: memory@8bf00000 { 691 reg = <0x0 0x8bf00000 0x0 0x4600000>; 692 no-map; 693 }; 694 }; 695 696 smem { 697 compatible = "qcom,smem"; 698 memory-region = <&smem_mem>; 699 hwlocks = <&tcsr_mutex 3>; 700 }; 701 702 smp2p-adsp { 703 compatible = "qcom,smp2p"; 704 qcom,smem = <443>, <429>; 705 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 706 IPCC_MPROC_SIGNAL_SMP2P 707 IRQ_TYPE_EDGE_RISING>; 708 mboxes = <&ipcc IPCC_CLIENT_LPASS 709 IPCC_MPROC_SIGNAL_SMP2P>; 710 711 qcom,local-pid = <0>; 712 qcom,remote-pid = <2>; 713 714 smp2p_adsp_out: master-kernel { 715 qcom,entry-name = "master-kernel"; 716 #qcom,smem-state-cells = <1>; 717 }; 718 719 smp2p_adsp_in: slave-kernel { 720 qcom,entry-name = "slave-kernel"; 721 interrupt-controller; 722 #interrupt-cells = <2>; 723 }; 724 }; 725 726 smp2p-cdsp { 727 compatible = "qcom,smp2p"; 728 qcom,smem = <94>, <432>; 729 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 730 IPCC_MPROC_SIGNAL_SMP2P 731 IRQ_TYPE_EDGE_RISING>; 732 mboxes = <&ipcc IPCC_CLIENT_CDSP 733 IPCC_MPROC_SIGNAL_SMP2P>; 734 735 qcom,local-pid = <0>; 736 qcom,remote-pid = <5>; 737 738 smp2p_cdsp_out: master-kernel { 739 qcom,entry-name = "master-kernel"; 740 #qcom,smem-state-cells = <1>; 741 }; 742 743 smp2p_cdsp_in: slave-kernel { 744 qcom,entry-name = "slave-kernel"; 745 interrupt-controller; 746 #interrupt-cells = <2>; 747 }; 748 }; 749 750 smp2p-slpi { 751 compatible = "qcom,smp2p"; 752 qcom,smem = <481>, <430>; 753 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 754 IPCC_MPROC_SIGNAL_SMP2P 755 IRQ_TYPE_EDGE_RISING>; 756 mboxes = <&ipcc IPCC_CLIENT_SLPI 757 IPCC_MPROC_SIGNAL_SMP2P>; 758 759 qcom,local-pid = <0>; 760 qcom,remote-pid = <3>; 761 762 smp2p_slpi_out: master-kernel { 763 qcom,entry-name = "master-kernel"; 764 #qcom,smem-state-cells = <1>; 765 }; 766 767 smp2p_slpi_in: slave-kernel { 768 qcom,entry-name = "slave-kernel"; 769 interrupt-controller; 770 #interrupt-cells = <2>; 771 }; 772 }; 773 774 soc: soc@0 { 775 #address-cells = <2>; 776 #size-cells = <2>; 777 ranges = <0 0 0 0 0x10 0>; 778 dma-ranges = <0 0 0 0 0x10 0>; 779 compatible = "simple-bus"; 780 781 gcc: clock-controller@100000 { 782 compatible = "qcom,gcc-sm8250"; 783 reg = <0x0 0x00100000 0x0 0x1f0000>; 784 #clock-cells = <1>; 785 #reset-cells = <1>; 786 #power-domain-cells = <1>; 787 clock-names = "bi_tcxo", 788 "bi_tcxo_ao", 789 "sleep_clk"; 790 clocks = <&rpmhcc RPMH_CXO_CLK>, 791 <&rpmhcc RPMH_CXO_CLK_A>, 792 <&sleep_clk>; 793 }; 794 795 ipcc: mailbox@408000 { 796 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 797 reg = <0 0x00408000 0 0x1000>; 798 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 799 interrupt-controller; 800 #interrupt-cells = <3>; 801 #mbox-cells = <2>; 802 }; 803 804 rng: rng@793000 { 805 compatible = "qcom,prng-ee"; 806 reg = <0 0x00793000 0 0x1000>; 807 clocks = <&gcc GCC_PRNG_AHB_CLK>; 808 clock-names = "core"; 809 }; 810 811 qup_opp_table: qup-opp-table { 812 compatible = "operating-points-v2"; 813 814 opp-50000000 { 815 opp-hz = /bits/ 64 <50000000>; 816 required-opps = <&rpmhpd_opp_min_svs>; 817 }; 818 819 opp-75000000 { 820 opp-hz = /bits/ 64 <75000000>; 821 required-opps = <&rpmhpd_opp_low_svs>; 822 }; 823 824 opp-120000000 { 825 opp-hz = /bits/ 64 <120000000>; 826 required-opps = <&rpmhpd_opp_svs>; 827 }; 828 }; 829 830 gpi_dma2: dma-controller@800000 { 831 compatible = "qcom,sm8250-gpi-dma"; 832 reg = <0 0x00800000 0 0x70000>; 833 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 843 dma-channels = <10>; 844 dma-channel-mask = <0x3f>; 845 iommus = <&apps_smmu 0x76 0x0>; 846 #dma-cells = <3>; 847 status = "disabled"; 848 }; 849 850 qupv3_id_2: geniqup@8c0000 { 851 compatible = "qcom,geni-se-qup"; 852 reg = <0x0 0x008c0000 0x0 0x6000>; 853 clock-names = "m-ahb", "s-ahb"; 854 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 855 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 856 #address-cells = <2>; 857 #size-cells = <2>; 858 iommus = <&apps_smmu 0x63 0x0>; 859 ranges; 860 status = "disabled"; 861 862 i2c14: i2c@880000 { 863 compatible = "qcom,geni-i2c"; 864 reg = <0 0x00880000 0 0x4000>; 865 clock-names = "se"; 866 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 867 pinctrl-names = "default"; 868 pinctrl-0 = <&qup_i2c14_default>; 869 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 870 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 871 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 872 dma-names = "tx", "rx"; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 status = "disabled"; 876 }; 877 878 spi14: spi@880000 { 879 compatible = "qcom,geni-spi"; 880 reg = <0 0x00880000 0 0x4000>; 881 clock-names = "se"; 882 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 883 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 884 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 885 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 886 dma-names = "tx", "rx"; 887 power-domains = <&rpmhpd SM8250_CX>; 888 operating-points-v2 = <&qup_opp_table>; 889 #address-cells = <1>; 890 #size-cells = <0>; 891 status = "disabled"; 892 }; 893 894 i2c15: i2c@884000 { 895 compatible = "qcom,geni-i2c"; 896 reg = <0 0x00884000 0 0x4000>; 897 clock-names = "se"; 898 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 899 pinctrl-names = "default"; 900 pinctrl-0 = <&qup_i2c15_default>; 901 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 902 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 903 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 904 dma-names = "tx", "rx"; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 status = "disabled"; 908 }; 909 910 spi15: spi@884000 { 911 compatible = "qcom,geni-spi"; 912 reg = <0 0x00884000 0 0x4000>; 913 clock-names = "se"; 914 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 915 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 916 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 917 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 918 dma-names = "tx", "rx"; 919 power-domains = <&rpmhpd SM8250_CX>; 920 operating-points-v2 = <&qup_opp_table>; 921 #address-cells = <1>; 922 #size-cells = <0>; 923 status = "disabled"; 924 }; 925 926 i2c16: i2c@888000 { 927 compatible = "qcom,geni-i2c"; 928 reg = <0 0x00888000 0 0x4000>; 929 clock-names = "se"; 930 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 931 pinctrl-names = "default"; 932 pinctrl-0 = <&qup_i2c16_default>; 933 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 934 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 935 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 936 dma-names = "tx", "rx"; 937 #address-cells = <1>; 938 #size-cells = <0>; 939 status = "disabled"; 940 }; 941 942 spi16: spi@888000 { 943 compatible = "qcom,geni-spi"; 944 reg = <0 0x00888000 0 0x4000>; 945 clock-names = "se"; 946 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 947 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 948 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 949 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 950 dma-names = "tx", "rx"; 951 power-domains = <&rpmhpd SM8250_CX>; 952 operating-points-v2 = <&qup_opp_table>; 953 #address-cells = <1>; 954 #size-cells = <0>; 955 status = "disabled"; 956 }; 957 958 i2c17: i2c@88c000 { 959 compatible = "qcom,geni-i2c"; 960 reg = <0 0x0088c000 0 0x4000>; 961 clock-names = "se"; 962 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 963 pinctrl-names = "default"; 964 pinctrl-0 = <&qup_i2c17_default>; 965 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 966 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 967 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 968 dma-names = "tx", "rx"; 969 #address-cells = <1>; 970 #size-cells = <0>; 971 status = "disabled"; 972 }; 973 974 spi17: spi@88c000 { 975 compatible = "qcom,geni-spi"; 976 reg = <0 0x0088c000 0 0x4000>; 977 clock-names = "se"; 978 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 979 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 980 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 981 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 982 dma-names = "tx", "rx"; 983 power-domains = <&rpmhpd SM8250_CX>; 984 operating-points-v2 = <&qup_opp_table>; 985 #address-cells = <1>; 986 #size-cells = <0>; 987 status = "disabled"; 988 }; 989 990 uart17: serial@88c000 { 991 compatible = "qcom,geni-uart"; 992 reg = <0 0x0088c000 0 0x4000>; 993 clock-names = "se"; 994 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 995 pinctrl-names = "default"; 996 pinctrl-0 = <&qup_uart17_default>; 997 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 998 power-domains = <&rpmhpd SM8250_CX>; 999 operating-points-v2 = <&qup_opp_table>; 1000 status = "disabled"; 1001 }; 1002 1003 i2c18: i2c@890000 { 1004 compatible = "qcom,geni-i2c"; 1005 reg = <0 0x00890000 0 0x4000>; 1006 clock-names = "se"; 1007 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1008 pinctrl-names = "default"; 1009 pinctrl-0 = <&qup_i2c18_default>; 1010 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1011 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1012 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1013 dma-names = "tx", "rx"; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 status = "disabled"; 1017 }; 1018 1019 spi18: spi@890000 { 1020 compatible = "qcom,geni-spi"; 1021 reg = <0 0x00890000 0 0x4000>; 1022 clock-names = "se"; 1023 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1024 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1025 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1026 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1027 dma-names = "tx", "rx"; 1028 power-domains = <&rpmhpd SM8250_CX>; 1029 operating-points-v2 = <&qup_opp_table>; 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 status = "disabled"; 1033 }; 1034 1035 uart18: serial@890000 { 1036 compatible = "qcom,geni-uart"; 1037 reg = <0 0x00890000 0 0x4000>; 1038 clock-names = "se"; 1039 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1040 pinctrl-names = "default"; 1041 pinctrl-0 = <&qup_uart18_default>; 1042 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1043 power-domains = <&rpmhpd SM8250_CX>; 1044 operating-points-v2 = <&qup_opp_table>; 1045 status = "disabled"; 1046 }; 1047 1048 i2c19: i2c@894000 { 1049 compatible = "qcom,geni-i2c"; 1050 reg = <0 0x00894000 0 0x4000>; 1051 clock-names = "se"; 1052 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1053 pinctrl-names = "default"; 1054 pinctrl-0 = <&qup_i2c19_default>; 1055 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1056 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1057 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1058 dma-names = "tx", "rx"; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 status = "disabled"; 1062 }; 1063 1064 spi19: spi@894000 { 1065 compatible = "qcom,geni-spi"; 1066 reg = <0 0x00894000 0 0x4000>; 1067 clock-names = "se"; 1068 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1069 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1070 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1071 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1072 dma-names = "tx", "rx"; 1073 power-domains = <&rpmhpd SM8250_CX>; 1074 operating-points-v2 = <&qup_opp_table>; 1075 #address-cells = <1>; 1076 #size-cells = <0>; 1077 status = "disabled"; 1078 }; 1079 }; 1080 1081 gpi_dma0: dma-controller@900000 { 1082 compatible = "qcom,sm8250-gpi-dma"; 1083 reg = <0 0x00900000 0 0x70000>; 1084 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1097 dma-channels = <15>; 1098 dma-channel-mask = <0x7ff>; 1099 iommus = <&apps_smmu 0x5b6 0x0>; 1100 #dma-cells = <3>; 1101 status = "disabled"; 1102 }; 1103 1104 qupv3_id_0: geniqup@9c0000 { 1105 compatible = "qcom,geni-se-qup"; 1106 reg = <0x0 0x009c0000 0x0 0x6000>; 1107 clock-names = "m-ahb", "s-ahb"; 1108 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1109 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1110 #address-cells = <2>; 1111 #size-cells = <2>; 1112 iommus = <&apps_smmu 0x5a3 0x0>; 1113 ranges; 1114 status = "disabled"; 1115 1116 i2c0: i2c@980000 { 1117 compatible = "qcom,geni-i2c"; 1118 reg = <0 0x00980000 0 0x4000>; 1119 clock-names = "se"; 1120 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1121 pinctrl-names = "default"; 1122 pinctrl-0 = <&qup_i2c0_default>; 1123 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1124 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1125 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1126 dma-names = "tx", "rx"; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 status = "disabled"; 1130 }; 1131 1132 spi0: spi@980000 { 1133 compatible = "qcom,geni-spi"; 1134 reg = <0 0x00980000 0 0x4000>; 1135 clock-names = "se"; 1136 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1137 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1138 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1139 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1140 dma-names = "tx", "rx"; 1141 power-domains = <&rpmhpd SM8250_CX>; 1142 operating-points-v2 = <&qup_opp_table>; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 status = "disabled"; 1146 }; 1147 1148 i2c1: i2c@984000 { 1149 compatible = "qcom,geni-i2c"; 1150 reg = <0 0x00984000 0 0x4000>; 1151 clock-names = "se"; 1152 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&qup_i2c1_default>; 1155 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1156 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1157 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1158 dma-names = "tx", "rx"; 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 status = "disabled"; 1162 }; 1163 1164 spi1: spi@984000 { 1165 compatible = "qcom,geni-spi"; 1166 reg = <0 0x00984000 0 0x4000>; 1167 clock-names = "se"; 1168 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1169 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1170 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1171 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1172 dma-names = "tx", "rx"; 1173 power-domains = <&rpmhpd SM8250_CX>; 1174 operating-points-v2 = <&qup_opp_table>; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 status = "disabled"; 1178 }; 1179 1180 i2c2: i2c@988000 { 1181 compatible = "qcom,geni-i2c"; 1182 reg = <0 0x00988000 0 0x4000>; 1183 clock-names = "se"; 1184 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1185 pinctrl-names = "default"; 1186 pinctrl-0 = <&qup_i2c2_default>; 1187 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1188 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1189 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1190 dma-names = "tx", "rx"; 1191 #address-cells = <1>; 1192 #size-cells = <0>; 1193 status = "disabled"; 1194 }; 1195 1196 spi2: spi@988000 { 1197 compatible = "qcom,geni-spi"; 1198 reg = <0 0x00988000 0 0x4000>; 1199 clock-names = "se"; 1200 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1201 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1202 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1203 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1204 dma-names = "tx", "rx"; 1205 power-domains = <&rpmhpd SM8250_CX>; 1206 operating-points-v2 = <&qup_opp_table>; 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 status = "disabled"; 1210 }; 1211 1212 uart2: serial@988000 { 1213 compatible = "qcom,geni-debug-uart"; 1214 reg = <0 0x00988000 0 0x4000>; 1215 clock-names = "se"; 1216 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1217 pinctrl-names = "default"; 1218 pinctrl-0 = <&qup_uart2_default>; 1219 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1220 power-domains = <&rpmhpd SM8250_CX>; 1221 operating-points-v2 = <&qup_opp_table>; 1222 status = "disabled"; 1223 }; 1224 1225 i2c3: i2c@98c000 { 1226 compatible = "qcom,geni-i2c"; 1227 reg = <0 0x0098c000 0 0x4000>; 1228 clock-names = "se"; 1229 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1230 pinctrl-names = "default"; 1231 pinctrl-0 = <&qup_i2c3_default>; 1232 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1233 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1234 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1235 dma-names = "tx", "rx"; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 status = "disabled"; 1239 }; 1240 1241 spi3: spi@98c000 { 1242 compatible = "qcom,geni-spi"; 1243 reg = <0 0x0098c000 0 0x4000>; 1244 clock-names = "se"; 1245 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1246 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1247 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1248 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1249 dma-names = "tx", "rx"; 1250 power-domains = <&rpmhpd SM8250_CX>; 1251 operating-points-v2 = <&qup_opp_table>; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 status = "disabled"; 1255 }; 1256 1257 i2c4: i2c@990000 { 1258 compatible = "qcom,geni-i2c"; 1259 reg = <0 0x00990000 0 0x4000>; 1260 clock-names = "se"; 1261 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1262 pinctrl-names = "default"; 1263 pinctrl-0 = <&qup_i2c4_default>; 1264 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1265 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1266 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1267 dma-names = "tx", "rx"; 1268 #address-cells = <1>; 1269 #size-cells = <0>; 1270 status = "disabled"; 1271 }; 1272 1273 spi4: spi@990000 { 1274 compatible = "qcom,geni-spi"; 1275 reg = <0 0x00990000 0 0x4000>; 1276 clock-names = "se"; 1277 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1278 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1279 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1280 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1281 dma-names = "tx", "rx"; 1282 power-domains = <&rpmhpd SM8250_CX>; 1283 operating-points-v2 = <&qup_opp_table>; 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 status = "disabled"; 1287 }; 1288 1289 i2c5: i2c@994000 { 1290 compatible = "qcom,geni-i2c"; 1291 reg = <0 0x00994000 0 0x4000>; 1292 clock-names = "se"; 1293 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1294 pinctrl-names = "default"; 1295 pinctrl-0 = <&qup_i2c5_default>; 1296 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1297 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1298 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1299 dma-names = "tx", "rx"; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 status = "disabled"; 1303 }; 1304 1305 spi5: spi@994000 { 1306 compatible = "qcom,geni-spi"; 1307 reg = <0 0x00994000 0 0x4000>; 1308 clock-names = "se"; 1309 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1310 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1311 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1312 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1313 dma-names = "tx", "rx"; 1314 power-domains = <&rpmhpd SM8250_CX>; 1315 operating-points-v2 = <&qup_opp_table>; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 status = "disabled"; 1319 }; 1320 1321 i2c6: i2c@998000 { 1322 compatible = "qcom,geni-i2c"; 1323 reg = <0 0x00998000 0 0x4000>; 1324 clock-names = "se"; 1325 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1326 pinctrl-names = "default"; 1327 pinctrl-0 = <&qup_i2c6_default>; 1328 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1329 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1330 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1331 dma-names = "tx", "rx"; 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 status = "disabled"; 1335 }; 1336 1337 spi6: spi@998000 { 1338 compatible = "qcom,geni-spi"; 1339 reg = <0 0x00998000 0 0x4000>; 1340 clock-names = "se"; 1341 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1342 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1343 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1344 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1345 dma-names = "tx", "rx"; 1346 power-domains = <&rpmhpd SM8250_CX>; 1347 operating-points-v2 = <&qup_opp_table>; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 status = "disabled"; 1351 }; 1352 1353 uart6: serial@998000 { 1354 compatible = "qcom,geni-uart"; 1355 reg = <0 0x00998000 0 0x4000>; 1356 clock-names = "se"; 1357 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&qup_uart6_default>; 1360 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1361 power-domains = <&rpmhpd SM8250_CX>; 1362 operating-points-v2 = <&qup_opp_table>; 1363 status = "disabled"; 1364 }; 1365 1366 i2c7: i2c@99c000 { 1367 compatible = "qcom,geni-i2c"; 1368 reg = <0 0x0099c000 0 0x4000>; 1369 clock-names = "se"; 1370 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1371 pinctrl-names = "default"; 1372 pinctrl-0 = <&qup_i2c7_default>; 1373 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1374 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1375 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1376 dma-names = "tx", "rx"; 1377 #address-cells = <1>; 1378 #size-cells = <0>; 1379 status = "disabled"; 1380 }; 1381 1382 spi7: spi@99c000 { 1383 compatible = "qcom,geni-spi"; 1384 reg = <0 0x0099c000 0 0x4000>; 1385 clock-names = "se"; 1386 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1387 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1388 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1389 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1390 dma-names = "tx", "rx"; 1391 power-domains = <&rpmhpd SM8250_CX>; 1392 operating-points-v2 = <&qup_opp_table>; 1393 #address-cells = <1>; 1394 #size-cells = <0>; 1395 status = "disabled"; 1396 }; 1397 }; 1398 1399 gpi_dma1: dma-controller@a00000 { 1400 compatible = "qcom,sm8250-gpi-dma"; 1401 reg = <0 0x00a00000 0 0x70000>; 1402 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1412 dma-channels = <10>; 1413 dma-channel-mask = <0x3f>; 1414 iommus = <&apps_smmu 0x56 0x0>; 1415 #dma-cells = <3>; 1416 status = "disabled"; 1417 }; 1418 1419 qupv3_id_1: geniqup@ac0000 { 1420 compatible = "qcom,geni-se-qup"; 1421 reg = <0x0 0x00ac0000 0x0 0x6000>; 1422 clock-names = "m-ahb", "s-ahb"; 1423 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1424 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1425 #address-cells = <2>; 1426 #size-cells = <2>; 1427 iommus = <&apps_smmu 0x43 0x0>; 1428 ranges; 1429 status = "disabled"; 1430 1431 i2c8: i2c@a80000 { 1432 compatible = "qcom,geni-i2c"; 1433 reg = <0 0x00a80000 0 0x4000>; 1434 clock-names = "se"; 1435 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1436 pinctrl-names = "default"; 1437 pinctrl-0 = <&qup_i2c8_default>; 1438 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1439 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1440 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1441 dma-names = "tx", "rx"; 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 status = "disabled"; 1445 }; 1446 1447 spi8: spi@a80000 { 1448 compatible = "qcom,geni-spi"; 1449 reg = <0 0x00a80000 0 0x4000>; 1450 clock-names = "se"; 1451 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1452 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1453 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1454 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1455 dma-names = "tx", "rx"; 1456 power-domains = <&rpmhpd SM8250_CX>; 1457 operating-points-v2 = <&qup_opp_table>; 1458 #address-cells = <1>; 1459 #size-cells = <0>; 1460 status = "disabled"; 1461 }; 1462 1463 i2c9: i2c@a84000 { 1464 compatible = "qcom,geni-i2c"; 1465 reg = <0 0x00a84000 0 0x4000>; 1466 clock-names = "se"; 1467 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1468 pinctrl-names = "default"; 1469 pinctrl-0 = <&qup_i2c9_default>; 1470 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1471 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1472 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1473 dma-names = "tx", "rx"; 1474 #address-cells = <1>; 1475 #size-cells = <0>; 1476 status = "disabled"; 1477 }; 1478 1479 spi9: spi@a84000 { 1480 compatible = "qcom,geni-spi"; 1481 reg = <0 0x00a84000 0 0x4000>; 1482 clock-names = "se"; 1483 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1484 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1485 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1486 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1487 dma-names = "tx", "rx"; 1488 power-domains = <&rpmhpd SM8250_CX>; 1489 operating-points-v2 = <&qup_opp_table>; 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 status = "disabled"; 1493 }; 1494 1495 i2c10: i2c@a88000 { 1496 compatible = "qcom,geni-i2c"; 1497 reg = <0 0x00a88000 0 0x4000>; 1498 clock-names = "se"; 1499 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1500 pinctrl-names = "default"; 1501 pinctrl-0 = <&qup_i2c10_default>; 1502 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1503 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1504 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1505 dma-names = "tx", "rx"; 1506 #address-cells = <1>; 1507 #size-cells = <0>; 1508 status = "disabled"; 1509 }; 1510 1511 spi10: spi@a88000 { 1512 compatible = "qcom,geni-spi"; 1513 reg = <0 0x00a88000 0 0x4000>; 1514 clock-names = "se"; 1515 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1516 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1517 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1518 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1519 dma-names = "tx", "rx"; 1520 power-domains = <&rpmhpd SM8250_CX>; 1521 operating-points-v2 = <&qup_opp_table>; 1522 #address-cells = <1>; 1523 #size-cells = <0>; 1524 status = "disabled"; 1525 }; 1526 1527 i2c11: i2c@a8c000 { 1528 compatible = "qcom,geni-i2c"; 1529 reg = <0 0x00a8c000 0 0x4000>; 1530 clock-names = "se"; 1531 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1532 pinctrl-names = "default"; 1533 pinctrl-0 = <&qup_i2c11_default>; 1534 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1535 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1536 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1537 dma-names = "tx", "rx"; 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 status = "disabled"; 1541 }; 1542 1543 spi11: spi@a8c000 { 1544 compatible = "qcom,geni-spi"; 1545 reg = <0 0x00a8c000 0 0x4000>; 1546 clock-names = "se"; 1547 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1548 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1549 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1550 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1551 dma-names = "tx", "rx"; 1552 power-domains = <&rpmhpd SM8250_CX>; 1553 operating-points-v2 = <&qup_opp_table>; 1554 #address-cells = <1>; 1555 #size-cells = <0>; 1556 status = "disabled"; 1557 }; 1558 1559 i2c12: i2c@a90000 { 1560 compatible = "qcom,geni-i2c"; 1561 reg = <0 0x00a90000 0 0x4000>; 1562 clock-names = "se"; 1563 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1564 pinctrl-names = "default"; 1565 pinctrl-0 = <&qup_i2c12_default>; 1566 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1567 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1568 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1569 dma-names = "tx", "rx"; 1570 #address-cells = <1>; 1571 #size-cells = <0>; 1572 status = "disabled"; 1573 }; 1574 1575 spi12: spi@a90000 { 1576 compatible = "qcom,geni-spi"; 1577 reg = <0 0x00a90000 0 0x4000>; 1578 clock-names = "se"; 1579 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1580 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1581 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1582 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1583 dma-names = "tx", "rx"; 1584 power-domains = <&rpmhpd SM8250_CX>; 1585 operating-points-v2 = <&qup_opp_table>; 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 status = "disabled"; 1589 }; 1590 1591 uart12: serial@a90000 { 1592 compatible = "qcom,geni-debug-uart"; 1593 reg = <0x0 0x00a90000 0x0 0x4000>; 1594 clock-names = "se"; 1595 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1596 pinctrl-names = "default"; 1597 pinctrl-0 = <&qup_uart12_default>; 1598 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1599 power-domains = <&rpmhpd SM8250_CX>; 1600 operating-points-v2 = <&qup_opp_table>; 1601 status = "disabled"; 1602 }; 1603 1604 i2c13: i2c@a94000 { 1605 compatible = "qcom,geni-i2c"; 1606 reg = <0 0x00a94000 0 0x4000>; 1607 clock-names = "se"; 1608 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1609 pinctrl-names = "default"; 1610 pinctrl-0 = <&qup_i2c13_default>; 1611 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1612 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1613 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1614 dma-names = "tx", "rx"; 1615 #address-cells = <1>; 1616 #size-cells = <0>; 1617 status = "disabled"; 1618 }; 1619 1620 spi13: spi@a94000 { 1621 compatible = "qcom,geni-spi"; 1622 reg = <0 0x00a94000 0 0x4000>; 1623 clock-names = "se"; 1624 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1625 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1626 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1627 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1628 dma-names = "tx", "rx"; 1629 power-domains = <&rpmhpd SM8250_CX>; 1630 operating-points-v2 = <&qup_opp_table>; 1631 #address-cells = <1>; 1632 #size-cells = <0>; 1633 status = "disabled"; 1634 }; 1635 }; 1636 1637 config_noc: interconnect@1500000 { 1638 compatible = "qcom,sm8250-config-noc"; 1639 reg = <0 0x01500000 0 0xa580>; 1640 #interconnect-cells = <1>; 1641 qcom,bcm-voters = <&apps_bcm_voter>; 1642 }; 1643 1644 system_noc: interconnect@1620000 { 1645 compatible = "qcom,sm8250-system-noc"; 1646 reg = <0 0x01620000 0 0x1c200>; 1647 #interconnect-cells = <1>; 1648 qcom,bcm-voters = <&apps_bcm_voter>; 1649 }; 1650 1651 mc_virt: interconnect@163d000 { 1652 compatible = "qcom,sm8250-mc-virt"; 1653 reg = <0 0x0163d000 0 0x1000>; 1654 #interconnect-cells = <1>; 1655 qcom,bcm-voters = <&apps_bcm_voter>; 1656 }; 1657 1658 aggre1_noc: interconnect@16e0000 { 1659 compatible = "qcom,sm8250-aggre1-noc"; 1660 reg = <0 0x016e0000 0 0x1f180>; 1661 #interconnect-cells = <1>; 1662 qcom,bcm-voters = <&apps_bcm_voter>; 1663 }; 1664 1665 aggre2_noc: interconnect@1700000 { 1666 compatible = "qcom,sm8250-aggre2-noc"; 1667 reg = <0 0x01700000 0 0x33000>; 1668 #interconnect-cells = <1>; 1669 qcom,bcm-voters = <&apps_bcm_voter>; 1670 }; 1671 1672 compute_noc: interconnect@1733000 { 1673 compatible = "qcom,sm8250-compute-noc"; 1674 reg = <0 0x01733000 0 0xa180>; 1675 #interconnect-cells = <1>; 1676 qcom,bcm-voters = <&apps_bcm_voter>; 1677 }; 1678 1679 mmss_noc: interconnect@1740000 { 1680 compatible = "qcom,sm8250-mmss-noc"; 1681 reg = <0 0x01740000 0 0x1f080>; 1682 #interconnect-cells = <1>; 1683 qcom,bcm-voters = <&apps_bcm_voter>; 1684 }; 1685 1686 pcie0: pci@1c00000 { 1687 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1688 reg = <0 0x01c00000 0 0x3000>, 1689 <0 0x60000000 0 0xf1d>, 1690 <0 0x60000f20 0 0xa8>, 1691 <0 0x60001000 0 0x1000>, 1692 <0 0x60100000 0 0x100000>; 1693 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1694 device_type = "pci"; 1695 linux,pci-domain = <0>; 1696 bus-range = <0x00 0xff>; 1697 num-lanes = <1>; 1698 1699 #address-cells = <3>; 1700 #size-cells = <2>; 1701 1702 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1703 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1704 1705 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1706 interrupt-names = "msi"; 1707 #interrupt-cells = <1>; 1708 interrupt-map-mask = <0 0 0 0x7>; 1709 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1710 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1711 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1712 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1713 1714 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1715 <&gcc GCC_PCIE_0_AUX_CLK>, 1716 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1717 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1718 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1719 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1720 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1721 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1722 clock-names = "pipe", 1723 "aux", 1724 "cfg", 1725 "bus_master", 1726 "bus_slave", 1727 "slave_q2a", 1728 "tbu", 1729 "ddrss_sf_tbu"; 1730 1731 iommus = <&apps_smmu 0x1c00 0x7f>; 1732 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1733 <0x100 &apps_smmu 0x1c01 0x1>; 1734 1735 resets = <&gcc GCC_PCIE_0_BCR>; 1736 reset-names = "pci"; 1737 1738 power-domains = <&gcc PCIE_0_GDSC>; 1739 1740 phys = <&pcie0_lane>; 1741 phy-names = "pciephy"; 1742 1743 perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; 1744 enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; 1745 1746 pinctrl-names = "default"; 1747 pinctrl-0 = <&pcie0_default_state>; 1748 1749 status = "disabled"; 1750 }; 1751 1752 pcie0_phy: phy@1c06000 { 1753 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1754 reg = <0 0x01c06000 0 0x1c0>; 1755 #address-cells = <2>; 1756 #size-cells = <2>; 1757 ranges; 1758 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1759 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1760 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1761 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1762 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1763 1764 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1765 reset-names = "phy"; 1766 1767 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1768 assigned-clock-rates = <100000000>; 1769 1770 status = "disabled"; 1771 1772 pcie0_lane: phy@1c06200 { 1773 reg = <0 0x1c06200 0 0x170>, /* tx */ 1774 <0 0x1c06400 0 0x200>, /* rx */ 1775 <0 0x1c06800 0 0x1f0>, /* pcs */ 1776 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1777 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1778 clock-names = "pipe0"; 1779 1780 #phy-cells = <0>; 1781 clock-output-names = "pcie_0_pipe_clk"; 1782 }; 1783 }; 1784 1785 pcie1: pci@1c08000 { 1786 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1787 reg = <0 0x01c08000 0 0x3000>, 1788 <0 0x40000000 0 0xf1d>, 1789 <0 0x40000f20 0 0xa8>, 1790 <0 0x40001000 0 0x1000>, 1791 <0 0x40100000 0 0x100000>; 1792 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1793 device_type = "pci"; 1794 linux,pci-domain = <1>; 1795 bus-range = <0x00 0xff>; 1796 num-lanes = <2>; 1797 1798 #address-cells = <3>; 1799 #size-cells = <2>; 1800 1801 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1802 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1803 1804 interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>; 1805 interrupt-names = "msi"; 1806 #interrupt-cells = <1>; 1807 interrupt-map-mask = <0 0 0 0x7>; 1808 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1809 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1810 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1811 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1812 1813 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1814 <&gcc GCC_PCIE_1_AUX_CLK>, 1815 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1816 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1817 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1818 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1819 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1820 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1821 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1822 clock-names = "pipe", 1823 "aux", 1824 "cfg", 1825 "bus_master", 1826 "bus_slave", 1827 "slave_q2a", 1828 "ref", 1829 "tbu", 1830 "ddrss_sf_tbu"; 1831 1832 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1833 assigned-clock-rates = <19200000>; 1834 1835 iommus = <&apps_smmu 0x1c80 0x7f>; 1836 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1837 <0x100 &apps_smmu 0x1c81 0x1>; 1838 1839 resets = <&gcc GCC_PCIE_1_BCR>; 1840 reset-names = "pci"; 1841 1842 power-domains = <&gcc PCIE_1_GDSC>; 1843 1844 phys = <&pcie1_lane>; 1845 phy-names = "pciephy"; 1846 1847 perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>; 1848 enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; 1849 1850 pinctrl-names = "default"; 1851 pinctrl-0 = <&pcie1_default_state>; 1852 1853 status = "disabled"; 1854 }; 1855 1856 pcie1_phy: phy@1c0e000 { 1857 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1858 reg = <0 0x01c0e000 0 0x1c0>; 1859 #address-cells = <2>; 1860 #size-cells = <2>; 1861 ranges; 1862 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1863 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1864 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1865 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1866 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1867 1868 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1869 reset-names = "phy"; 1870 1871 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1872 assigned-clock-rates = <100000000>; 1873 1874 status = "disabled"; 1875 1876 pcie1_lane: phy@1c0e200 { 1877 reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1878 <0 0x1c0e400 0 0x200>, /* rx0 */ 1879 <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1880 <0 0x1c0e600 0 0x170>, /* tx1 */ 1881 <0 0x1c0e800 0 0x200>, /* rx1 */ 1882 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1883 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1884 clock-names = "pipe0"; 1885 1886 #phy-cells = <0>; 1887 clock-output-names = "pcie_1_pipe_clk"; 1888 }; 1889 }; 1890 1891 pcie2: pci@1c10000 { 1892 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1893 reg = <0 0x01c10000 0 0x3000>, 1894 <0 0x64000000 0 0xf1d>, 1895 <0 0x64000f20 0 0xa8>, 1896 <0 0x64001000 0 0x1000>, 1897 <0 0x64100000 0 0x100000>; 1898 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1899 device_type = "pci"; 1900 linux,pci-domain = <2>; 1901 bus-range = <0x00 0xff>; 1902 num-lanes = <2>; 1903 1904 #address-cells = <3>; 1905 #size-cells = <2>; 1906 1907 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, 1908 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 1909 1910 interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; 1911 interrupt-names = "msi"; 1912 #interrupt-cells = <1>; 1913 interrupt-map-mask = <0 0 0 0x7>; 1914 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1915 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1916 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1917 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1918 1919 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1920 <&gcc GCC_PCIE_2_AUX_CLK>, 1921 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1922 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1923 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 1924 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 1925 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1926 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1927 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1928 clock-names = "pipe", 1929 "aux", 1930 "cfg", 1931 "bus_master", 1932 "bus_slave", 1933 "slave_q2a", 1934 "ref", 1935 "tbu", 1936 "ddrss_sf_tbu"; 1937 1938 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 1939 assigned-clock-rates = <19200000>; 1940 1941 iommus = <&apps_smmu 0x1d00 0x7f>; 1942 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 1943 <0x100 &apps_smmu 0x1d01 0x1>; 1944 1945 resets = <&gcc GCC_PCIE_2_BCR>; 1946 reset-names = "pci"; 1947 1948 power-domains = <&gcc PCIE_2_GDSC>; 1949 1950 phys = <&pcie2_lane>; 1951 phy-names = "pciephy"; 1952 1953 perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>; 1954 enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; 1955 1956 pinctrl-names = "default"; 1957 pinctrl-0 = <&pcie2_default_state>; 1958 1959 status = "disabled"; 1960 }; 1961 1962 pcie2_phy: phy@1c16000 { 1963 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 1964 reg = <0 0x1c16000 0 0x1c0>; 1965 #address-cells = <2>; 1966 #size-cells = <2>; 1967 ranges; 1968 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1969 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1970 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1971 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1972 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1973 1974 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 1975 reset-names = "phy"; 1976 1977 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1978 assigned-clock-rates = <100000000>; 1979 1980 status = "disabled"; 1981 1982 pcie2_lane: phy@1c16200 { 1983 reg = <0 0x1c16200 0 0x170>, /* tx0 */ 1984 <0 0x1c16400 0 0x200>, /* rx0 */ 1985 <0 0x1c16a00 0 0x1f0>, /* pcs */ 1986 <0 0x1c16600 0 0x170>, /* tx1 */ 1987 <0 0x1c16800 0 0x200>, /* rx1 */ 1988 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1989 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 1990 clock-names = "pipe0"; 1991 1992 #phy-cells = <0>; 1993 clock-output-names = "pcie_2_pipe_clk"; 1994 }; 1995 }; 1996 1997 ufs_mem_hc: ufshc@1d84000 { 1998 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 1999 "jedec,ufs-2.0"; 2000 reg = <0 0x01d84000 0 0x3000>; 2001 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2002 phys = <&ufs_mem_phy_lanes>; 2003 phy-names = "ufsphy"; 2004 lanes-per-direction = <2>; 2005 #reset-cells = <1>; 2006 resets = <&gcc GCC_UFS_PHY_BCR>; 2007 reset-names = "rst"; 2008 2009 power-domains = <&gcc UFS_PHY_GDSC>; 2010 2011 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 2012 2013 clock-names = 2014 "core_clk", 2015 "bus_aggr_clk", 2016 "iface_clk", 2017 "core_clk_unipro", 2018 "ref_clk", 2019 "tx_lane0_sync_clk", 2020 "rx_lane0_sync_clk", 2021 "rx_lane1_sync_clk"; 2022 clocks = 2023 <&gcc GCC_UFS_PHY_AXI_CLK>, 2024 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2025 <&gcc GCC_UFS_PHY_AHB_CLK>, 2026 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2027 <&rpmhcc RPMH_CXO_CLK>, 2028 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2029 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2030 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2031 freq-table-hz = 2032 <37500000 300000000>, 2033 <0 0>, 2034 <0 0>, 2035 <37500000 300000000>, 2036 <0 0>, 2037 <0 0>, 2038 <0 0>, 2039 <0 0>; 2040 2041 status = "disabled"; 2042 }; 2043 2044 ufs_mem_phy: phy@1d87000 { 2045 compatible = "qcom,sm8250-qmp-ufs-phy"; 2046 reg = <0 0x01d87000 0 0x1c0>; 2047 #address-cells = <2>; 2048 #size-cells = <2>; 2049 ranges; 2050 clock-names = "ref", 2051 "ref_aux"; 2052 clocks = <&rpmhcc RPMH_CXO_CLK>, 2053 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2054 2055 resets = <&ufs_mem_hc 0>; 2056 reset-names = "ufsphy"; 2057 status = "disabled"; 2058 2059 ufs_mem_phy_lanes: phy@1d87400 { 2060 reg = <0 0x01d87400 0 0x108>, 2061 <0 0x01d87600 0 0x1e0>, 2062 <0 0x01d87c00 0 0x1dc>, 2063 <0 0x01d87800 0 0x108>, 2064 <0 0x01d87a00 0 0x1e0>; 2065 #phy-cells = <0>; 2066 }; 2067 }; 2068 2069 ipa_virt: interconnect@1e00000 { 2070 compatible = "qcom,sm8250-ipa-virt"; 2071 reg = <0 0x01e00000 0 0x1000>; 2072 #interconnect-cells = <1>; 2073 qcom,bcm-voters = <&apps_bcm_voter>; 2074 }; 2075 2076 tcsr_mutex: hwlock@1f40000 { 2077 compatible = "qcom,tcsr-mutex"; 2078 reg = <0x0 0x01f40000 0x0 0x40000>; 2079 #hwlock-cells = <1>; 2080 }; 2081 2082 wsamacro: codec@3240000 { 2083 compatible = "qcom,sm8250-lpass-wsa-macro"; 2084 reg = <0 0x03240000 0 0x1000>; 2085 clocks = <&audiocc 1>, 2086 <&audiocc 0>, 2087 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2088 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2089 <&aoncc 0>, 2090 <&vamacro>; 2091 2092 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 2093 2094 #clock-cells = <0>; 2095 clock-frequency = <9600000>; 2096 clock-output-names = "mclk"; 2097 #sound-dai-cells = <1>; 2098 2099 pinctrl-names = "default"; 2100 pinctrl-0 = <&wsa_swr_active>; 2101 }; 2102 2103 swr0: soundwire-controller@3250000 { 2104 reg = <0 0x03250000 0 0x2000>; 2105 compatible = "qcom,soundwire-v1.5.1"; 2106 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 2107 clocks = <&wsamacro>; 2108 clock-names = "iface"; 2109 2110 qcom,din-ports = <2>; 2111 qcom,dout-ports = <6>; 2112 2113 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2114 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2115 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2116 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 2117 2118 #sound-dai-cells = <1>; 2119 #address-cells = <2>; 2120 #size-cells = <0>; 2121 }; 2122 2123 audiocc: clock-controller@3300000 { 2124 compatible = "qcom,sm8250-lpass-audiocc"; 2125 reg = <0 0x03300000 0 0x30000>; 2126 #clock-cells = <1>; 2127 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2128 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2129 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2130 clock-names = "core", "audio", "bus"; 2131 }; 2132 2133 vamacro: codec@3370000 { 2134 compatible = "qcom,sm8250-lpass-va-macro"; 2135 reg = <0 0x03370000 0 0x1000>; 2136 clocks = <&aoncc 0>, 2137 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2138 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2139 2140 clock-names = "mclk", "macro", "dcodec"; 2141 2142 #clock-cells = <0>; 2143 clock-frequency = <9600000>; 2144 clock-output-names = "fsgen"; 2145 #sound-dai-cells = <1>; 2146 }; 2147 2148 rxmacro: rxmacro@3200000 { 2149 pinctrl-names = "default"; 2150 pinctrl-0 = <&rx_swr_active>; 2151 compatible = "qcom,sm8250-lpass-rx-macro"; 2152 reg = <0 0x3200000 0 0x1000>; 2153 2154 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2155 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2156 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2157 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2158 <&vamacro>; 2159 2160 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2161 2162 #clock-cells = <0>; 2163 clock-frequency = <9600000>; 2164 clock-output-names = "mclk"; 2165 #sound-dai-cells = <1>; 2166 }; 2167 2168 swr1: soundwire-controller@3210000 { 2169 reg = <0 0x3210000 0 0x2000>; 2170 compatible = "qcom,soundwire-v1.5.1"; 2171 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2172 clocks = <&rxmacro>; 2173 clock-names = "iface"; 2174 label = "RX"; 2175 qcom,din-ports = <0>; 2176 qcom,dout-ports = <5>; 2177 2178 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>; 2179 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 2180 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 2181 qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>; 2182 qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>; 2183 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>; 2184 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>; 2185 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2186 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>; 2187 2188 #sound-dai-cells = <1>; 2189 #address-cells = <2>; 2190 #size-cells = <0>; 2191 }; 2192 2193 txmacro: txmacro@3220000 { 2194 pinctrl-names = "default"; 2195 pinctrl-0 = <&tx_swr_active>; 2196 compatible = "qcom,sm8250-lpass-tx-macro"; 2197 reg = <0 0x3220000 0 0x1000>; 2198 2199 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2200 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2201 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2202 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2203 <&vamacro>; 2204 2205 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2206 2207 #clock-cells = <0>; 2208 clock-frequency = <9600000>; 2209 clock-output-names = "mclk"; 2210 #address-cells = <2>; 2211 #size-cells = <2>; 2212 #sound-dai-cells = <1>; 2213 }; 2214 2215 /* tx macro */ 2216 swr2: soundwire-controller@3230000 { 2217 reg = <0 0x3230000 0 0x2000>; 2218 compatible = "qcom,soundwire-v1.5.1"; 2219 interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 2220 interrupt-names = "core"; 2221 2222 clocks = <&txmacro>; 2223 clock-names = "iface"; 2224 label = "TX"; 2225 2226 qcom,din-ports = <5>; 2227 qcom,dout-ports = <0>; 2228 qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>; 2229 qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>; 2230 qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>; 2231 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2232 qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2233 qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2234 qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2235 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2236 qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>; 2237 qcom,port-offset = <1>; 2238 #sound-dai-cells = <1>; 2239 #address-cells = <2>; 2240 #size-cells = <0>; 2241 }; 2242 2243 aoncc: clock-controller@3380000 { 2244 compatible = "qcom,sm8250-lpass-aoncc"; 2245 reg = <0 0x03380000 0 0x40000>; 2246 #clock-cells = <1>; 2247 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2248 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2249 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2250 clock-names = "core", "audio", "bus"; 2251 }; 2252 2253 lpass_tlmm: pinctrl@33c0000{ 2254 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 2255 reg = <0 0x033c0000 0x0 0x20000>, 2256 <0 0x03550000 0x0 0x10000>; 2257 gpio-controller; 2258 #gpio-cells = <2>; 2259 gpio-ranges = <&lpass_tlmm 0 0 14>; 2260 2261 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2262 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2263 clock-names = "core", "audio"; 2264 2265 wsa_swr_active: wsa-swr-active-pins { 2266 clk { 2267 pins = "gpio10"; 2268 function = "wsa_swr_clk"; 2269 drive-strength = <2>; 2270 slew-rate = <1>; 2271 bias-disable; 2272 }; 2273 2274 data { 2275 pins = "gpio11"; 2276 function = "wsa_swr_data"; 2277 drive-strength = <2>; 2278 slew-rate = <1>; 2279 bias-bus-hold; 2280 2281 }; 2282 }; 2283 2284 wsa_swr_sleep: wsa-swr-sleep-pins { 2285 clk { 2286 pins = "gpio10"; 2287 function = "wsa_swr_clk"; 2288 drive-strength = <2>; 2289 input-enable; 2290 bias-pull-down; 2291 }; 2292 2293 data { 2294 pins = "gpio11"; 2295 function = "wsa_swr_data"; 2296 drive-strength = <2>; 2297 input-enable; 2298 bias-pull-down; 2299 2300 }; 2301 }; 2302 2303 dmic01_active: dmic01-active-pins { 2304 clk { 2305 pins = "gpio6"; 2306 function = "dmic1_clk"; 2307 drive-strength = <8>; 2308 output-high; 2309 }; 2310 data { 2311 pins = "gpio7"; 2312 function = "dmic1_data"; 2313 drive-strength = <8>; 2314 input-enable; 2315 }; 2316 }; 2317 2318 dmic01_sleep: dmic01-sleep-pins { 2319 clk { 2320 pins = "gpio6"; 2321 function = "dmic1_clk"; 2322 drive-strength = <2>; 2323 bias-disable; 2324 output-low; 2325 }; 2326 2327 data { 2328 pins = "gpio7"; 2329 function = "dmic1_data"; 2330 drive-strength = <2>; 2331 pull-down; 2332 input-enable; 2333 }; 2334 }; 2335 2336 rx_swr_active: rx_swr-active-pins { 2337 clk { 2338 pins = "gpio3"; 2339 function = "swr_rx_clk"; 2340 drive-strength = <2>; 2341 slew-rate = <1>; 2342 bias-disable; 2343 }; 2344 2345 data { 2346 pins = "gpio4", "gpio5"; 2347 function = "swr_rx_data"; 2348 drive-strength = <2>; 2349 slew-rate = <1>; 2350 bias-bus-hold; 2351 }; 2352 }; 2353 2354 tx_swr_active: tx_swr-active-pins { 2355 clk { 2356 pins = "gpio0"; 2357 function = "swr_tx_clk"; 2358 drive-strength = <2>; 2359 slew-rate = <1>; 2360 bias-disable; 2361 }; 2362 2363 data { 2364 pins = "gpio1", "gpio2"; 2365 function = "swr_tx_data"; 2366 drive-strength = <2>; 2367 slew-rate = <1>; 2368 bias-bus-hold; 2369 }; 2370 }; 2371 2372 tx_swr_sleep: tx_swr-sleep-pins { 2373 clk { 2374 pins = "gpio0"; 2375 function = "swr_tx_clk"; 2376 drive-strength = <2>; 2377 input-enable; 2378 bias-pull-down; 2379 }; 2380 2381 data1 { 2382 pins = "gpio1"; 2383 function = "swr_tx_data"; 2384 drive-strength = <2>; 2385 input-enable; 2386 bias-bus-hold; 2387 }; 2388 2389 data2 { 2390 pins = "gpio2"; 2391 function = "swr_tx_data"; 2392 drive-strength = <2>; 2393 input-enable; 2394 bias-pull-down; 2395 }; 2396 }; 2397 }; 2398 2399 gpu: gpu@3d00000 { 2400 compatible = "qcom,adreno-650.2", 2401 "qcom,adreno"; 2402 2403 reg = <0 0x03d00000 0 0x40000>; 2404 reg-names = "kgsl_3d0_reg_memory"; 2405 2406 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2407 2408 iommus = <&adreno_smmu 0 0x401>; 2409 2410 operating-points-v2 = <&gpu_opp_table>; 2411 2412 qcom,gmu = <&gmu>; 2413 2414 status = "disabled"; 2415 2416 zap-shader { 2417 memory-region = <&gpu_mem>; 2418 }; 2419 2420 /* note: downstream checks gpu binning for 670 Mhz */ 2421 gpu_opp_table: opp-table { 2422 compatible = "operating-points-v2"; 2423 2424 opp-670000000 { 2425 opp-hz = /bits/ 64 <670000000>; 2426 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2427 }; 2428 2429 opp-587000000 { 2430 opp-hz = /bits/ 64 <587000000>; 2431 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2432 }; 2433 2434 opp-525000000 { 2435 opp-hz = /bits/ 64 <525000000>; 2436 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2437 }; 2438 2439 opp-490000000 { 2440 opp-hz = /bits/ 64 <490000000>; 2441 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2442 }; 2443 2444 opp-441600000 { 2445 opp-hz = /bits/ 64 <441600000>; 2446 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2447 }; 2448 2449 opp-400000000 { 2450 opp-hz = /bits/ 64 <400000000>; 2451 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2452 }; 2453 2454 opp-305000000 { 2455 opp-hz = /bits/ 64 <305000000>; 2456 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2457 }; 2458 }; 2459 }; 2460 2461 gmu: gmu@3d6a000 { 2462 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2463 2464 reg = <0 0x03d6a000 0 0x30000>, 2465 <0 0x3de0000 0 0x10000>, 2466 <0 0xb290000 0 0x10000>, 2467 <0 0xb490000 0 0x10000>; 2468 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 2469 2470 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2471 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2472 interrupt-names = "hfi", "gmu"; 2473 2474 clocks = <&gpucc GPU_CC_AHB_CLK>, 2475 <&gpucc GPU_CC_CX_GMU_CLK>, 2476 <&gpucc GPU_CC_CXO_CLK>, 2477 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2478 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2479 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2480 2481 power-domains = <&gpucc GPU_CX_GDSC>, 2482 <&gpucc GPU_GX_GDSC>; 2483 power-domain-names = "cx", "gx"; 2484 2485 iommus = <&adreno_smmu 5 0x400>; 2486 2487 operating-points-v2 = <&gmu_opp_table>; 2488 2489 status = "disabled"; 2490 2491 gmu_opp_table: opp-table { 2492 compatible = "operating-points-v2"; 2493 2494 opp-200000000 { 2495 opp-hz = /bits/ 64 <200000000>; 2496 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2497 }; 2498 }; 2499 }; 2500 2501 gpucc: clock-controller@3d90000 { 2502 compatible = "qcom,sm8250-gpucc"; 2503 reg = <0 0x03d90000 0 0x9000>; 2504 clocks = <&rpmhcc RPMH_CXO_CLK>, 2505 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2506 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2507 clock-names = "bi_tcxo", 2508 "gcc_gpu_gpll0_clk_src", 2509 "gcc_gpu_gpll0_div_clk_src"; 2510 #clock-cells = <1>; 2511 #reset-cells = <1>; 2512 #power-domain-cells = <1>; 2513 }; 2514 2515 adreno_smmu: iommu@3da0000 { 2516 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 2517 reg = <0 0x03da0000 0 0x10000>; 2518 #iommu-cells = <2>; 2519 #global-interrupts = <2>; 2520 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2521 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2522 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2523 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2524 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2525 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2526 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2527 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2528 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2529 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 2530 clocks = <&gpucc GPU_CC_AHB_CLK>, 2531 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2532 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2533 clock-names = "ahb", "bus", "iface"; 2534 2535 power-domains = <&gpucc GPU_CX_GDSC>; 2536 }; 2537 2538 slpi: remoteproc@5c00000 { 2539 compatible = "qcom,sm8250-slpi-pas"; 2540 reg = <0 0x05c00000 0 0x4000>; 2541 2542 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2543 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2544 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2545 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2546 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2547 interrupt-names = "wdog", "fatal", "ready", 2548 "handover", "stop-ack"; 2549 2550 clocks = <&rpmhcc RPMH_CXO_CLK>; 2551 clock-names = "xo"; 2552 2553 power-domains = <&rpmhpd SM8250_LCX>, 2554 <&rpmhpd SM8250_LMX>; 2555 power-domain-names = "lcx", "lmx"; 2556 2557 memory-region = <&slpi_mem>; 2558 2559 qcom,qmp = <&aoss_qmp>; 2560 2561 qcom,smem-states = <&smp2p_slpi_out 0>; 2562 qcom,smem-state-names = "stop"; 2563 2564 status = "disabled"; 2565 2566 glink-edge { 2567 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2568 IPCC_MPROC_SIGNAL_GLINK_QMP 2569 IRQ_TYPE_EDGE_RISING>; 2570 mboxes = <&ipcc IPCC_CLIENT_SLPI 2571 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2572 2573 label = "slpi"; 2574 qcom,remote-pid = <3>; 2575 2576 fastrpc { 2577 compatible = "qcom,fastrpc"; 2578 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2579 label = "sdsp"; 2580 #address-cells = <1>; 2581 #size-cells = <0>; 2582 2583 compute-cb@1 { 2584 compatible = "qcom,fastrpc-compute-cb"; 2585 reg = <1>; 2586 iommus = <&apps_smmu 0x0541 0x0>; 2587 }; 2588 2589 compute-cb@2 { 2590 compatible = "qcom,fastrpc-compute-cb"; 2591 reg = <2>; 2592 iommus = <&apps_smmu 0x0542 0x0>; 2593 }; 2594 2595 compute-cb@3 { 2596 compatible = "qcom,fastrpc-compute-cb"; 2597 reg = <3>; 2598 iommus = <&apps_smmu 0x0543 0x0>; 2599 /* note: shared-cb = <4> in downstream */ 2600 }; 2601 }; 2602 }; 2603 }; 2604 2605 cdsp: remoteproc@8300000 { 2606 compatible = "qcom,sm8250-cdsp-pas"; 2607 reg = <0 0x08300000 0 0x10000>; 2608 2609 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 2610 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2611 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2612 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2613 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2614 interrupt-names = "wdog", "fatal", "ready", 2615 "handover", "stop-ack"; 2616 2617 clocks = <&rpmhcc RPMH_CXO_CLK>; 2618 clock-names = "xo"; 2619 2620 power-domains = <&rpmhpd SM8250_CX>; 2621 2622 memory-region = <&cdsp_mem>; 2623 2624 qcom,qmp = <&aoss_qmp>; 2625 2626 qcom,smem-states = <&smp2p_cdsp_out 0>; 2627 qcom,smem-state-names = "stop"; 2628 2629 status = "disabled"; 2630 2631 glink-edge { 2632 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2633 IPCC_MPROC_SIGNAL_GLINK_QMP 2634 IRQ_TYPE_EDGE_RISING>; 2635 mboxes = <&ipcc IPCC_CLIENT_CDSP 2636 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2637 2638 label = "cdsp"; 2639 qcom,remote-pid = <5>; 2640 2641 fastrpc { 2642 compatible = "qcom,fastrpc"; 2643 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2644 label = "cdsp"; 2645 #address-cells = <1>; 2646 #size-cells = <0>; 2647 2648 compute-cb@1 { 2649 compatible = "qcom,fastrpc-compute-cb"; 2650 reg = <1>; 2651 iommus = <&apps_smmu 0x1001 0x0460>; 2652 }; 2653 2654 compute-cb@2 { 2655 compatible = "qcom,fastrpc-compute-cb"; 2656 reg = <2>; 2657 iommus = <&apps_smmu 0x1002 0x0460>; 2658 }; 2659 2660 compute-cb@3 { 2661 compatible = "qcom,fastrpc-compute-cb"; 2662 reg = <3>; 2663 iommus = <&apps_smmu 0x1003 0x0460>; 2664 }; 2665 2666 compute-cb@4 { 2667 compatible = "qcom,fastrpc-compute-cb"; 2668 reg = <4>; 2669 iommus = <&apps_smmu 0x1004 0x0460>; 2670 }; 2671 2672 compute-cb@5 { 2673 compatible = "qcom,fastrpc-compute-cb"; 2674 reg = <5>; 2675 iommus = <&apps_smmu 0x1005 0x0460>; 2676 }; 2677 2678 compute-cb@6 { 2679 compatible = "qcom,fastrpc-compute-cb"; 2680 reg = <6>; 2681 iommus = <&apps_smmu 0x1006 0x0460>; 2682 }; 2683 2684 compute-cb@7 { 2685 compatible = "qcom,fastrpc-compute-cb"; 2686 reg = <7>; 2687 iommus = <&apps_smmu 0x1007 0x0460>; 2688 }; 2689 2690 compute-cb@8 { 2691 compatible = "qcom,fastrpc-compute-cb"; 2692 reg = <8>; 2693 iommus = <&apps_smmu 0x1008 0x0460>; 2694 }; 2695 2696 /* note: secure cb9 in downstream */ 2697 }; 2698 }; 2699 }; 2700 2701 sound: sound { 2702 }; 2703 2704 usb_1_hsphy: phy@88e3000 { 2705 compatible = "qcom,sm8250-usb-hs-phy", 2706 "qcom,usb-snps-hs-7nm-phy"; 2707 reg = <0 0x088e3000 0 0x400>; 2708 status = "disabled"; 2709 #phy-cells = <0>; 2710 2711 clocks = <&rpmhcc RPMH_CXO_CLK>; 2712 clock-names = "ref"; 2713 2714 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2715 }; 2716 2717 usb_2_hsphy: phy@88e4000 { 2718 compatible = "qcom,sm8250-usb-hs-phy", 2719 "qcom,usb-snps-hs-7nm-phy"; 2720 reg = <0 0x088e4000 0 0x400>; 2721 status = "disabled"; 2722 #phy-cells = <0>; 2723 2724 clocks = <&rpmhcc RPMH_CXO_CLK>; 2725 clock-names = "ref"; 2726 2727 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2728 }; 2729 2730 usb_1_qmpphy: phy@88e9000 { 2731 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 2732 reg = <0 0x088e9000 0 0x200>, 2733 <0 0x088e8000 0 0x40>, 2734 <0 0x088ea000 0 0x200>; 2735 status = "disabled"; 2736 #address-cells = <2>; 2737 #size-cells = <2>; 2738 ranges; 2739 2740 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2741 <&rpmhcc RPMH_CXO_CLK>, 2742 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2743 clock-names = "aux", "ref_clk_src", "com_aux"; 2744 2745 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2746 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2747 reset-names = "phy", "common"; 2748 2749 usb_1_ssphy: usb3-phy@88e9200 { 2750 reg = <0 0x088e9200 0 0x200>, 2751 <0 0x088e9400 0 0x200>, 2752 <0 0x088e9c00 0 0x400>, 2753 <0 0x088e9600 0 0x200>, 2754 <0 0x088e9800 0 0x200>, 2755 <0 0x088e9a00 0 0x100>; 2756 #clock-cells = <0>; 2757 #phy-cells = <0>; 2758 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2759 clock-names = "pipe0"; 2760 clock-output-names = "usb3_phy_pipe_clk_src"; 2761 }; 2762 2763 dp_phy: dp-phy@88ea200 { 2764 reg = <0 0x088ea200 0 0x200>, 2765 <0 0x088ea400 0 0x200>, 2766 <0 0x088eac00 0 0x400>, 2767 <0 0x088ea600 0 0x200>, 2768 <0 0x088ea800 0 0x200>, 2769 <0 0x088eaa00 0 0x100>; 2770 #phy-cells = <0>; 2771 #clock-cells = <1>; 2772 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2773 clock-names = "pipe0"; 2774 clock-output-names = "usb3_phy_pipe_clk_src"; 2775 }; 2776 }; 2777 2778 usb_2_qmpphy: phy@88eb000 { 2779 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 2780 reg = <0 0x088eb000 0 0x200>; 2781 status = "disabled"; 2782 #address-cells = <2>; 2783 #size-cells = <2>; 2784 ranges; 2785 2786 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2787 <&rpmhcc RPMH_CXO_CLK>, 2788 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2789 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2790 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2791 2792 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2793 <&gcc GCC_USB3_PHY_SEC_BCR>; 2794 reset-names = "phy", "common"; 2795 2796 usb_2_ssphy: phy@88eb200 { 2797 reg = <0 0x088eb200 0 0x200>, 2798 <0 0x088eb400 0 0x200>, 2799 <0 0x088eb800 0 0x800>; 2800 #clock-cells = <0>; 2801 #phy-cells = <0>; 2802 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2803 clock-names = "pipe0"; 2804 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2805 }; 2806 }; 2807 2808 sdhc_2: sdhci@8804000 { 2809 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 2810 reg = <0 0x08804000 0 0x1000>; 2811 2812 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2813 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2814 interrupt-names = "hc_irq", "pwr_irq"; 2815 2816 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2817 <&gcc GCC_SDCC2_APPS_CLK>, 2818 <&rpmhcc RPMH_CXO_CLK>; 2819 clock-names = "iface", "core", "xo"; 2820 iommus = <&apps_smmu 0x4a0 0x0>; 2821 qcom,dll-config = <0x0007642c>; 2822 qcom,ddr-config = <0x80040868>; 2823 power-domains = <&rpmhpd SM8250_CX>; 2824 operating-points-v2 = <&sdhc2_opp_table>; 2825 2826 status = "disabled"; 2827 2828 sdhc2_opp_table: sdhc2-opp-table { 2829 compatible = "operating-points-v2"; 2830 2831 opp-19200000 { 2832 opp-hz = /bits/ 64 <19200000>; 2833 required-opps = <&rpmhpd_opp_min_svs>; 2834 }; 2835 2836 opp-50000000 { 2837 opp-hz = /bits/ 64 <50000000>; 2838 required-opps = <&rpmhpd_opp_low_svs>; 2839 }; 2840 2841 opp-100000000 { 2842 opp-hz = /bits/ 64 <100000000>; 2843 required-opps = <&rpmhpd_opp_svs>; 2844 }; 2845 2846 opp-202000000 { 2847 opp-hz = /bits/ 64 <202000000>; 2848 required-opps = <&rpmhpd_opp_svs_l1>; 2849 }; 2850 }; 2851 }; 2852 2853 dc_noc: interconnect@90c0000 { 2854 compatible = "qcom,sm8250-dc-noc"; 2855 reg = <0 0x090c0000 0 0x4200>; 2856 #interconnect-cells = <1>; 2857 qcom,bcm-voters = <&apps_bcm_voter>; 2858 }; 2859 2860 gem_noc: interconnect@9100000 { 2861 compatible = "qcom,sm8250-gem-noc"; 2862 reg = <0 0x09100000 0 0xb4000>; 2863 #interconnect-cells = <1>; 2864 qcom,bcm-voters = <&apps_bcm_voter>; 2865 }; 2866 2867 npu_noc: interconnect@9990000 { 2868 compatible = "qcom,sm8250-npu-noc"; 2869 reg = <0 0x09990000 0 0x1600>; 2870 #interconnect-cells = <1>; 2871 qcom,bcm-voters = <&apps_bcm_voter>; 2872 }; 2873 2874 usb_1: usb@a6f8800 { 2875 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 2876 reg = <0 0x0a6f8800 0 0x400>; 2877 status = "disabled"; 2878 #address-cells = <2>; 2879 #size-cells = <2>; 2880 ranges; 2881 dma-ranges; 2882 2883 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2884 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2885 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2886 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2887 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2888 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2889 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2890 "sleep", "xo"; 2891 2892 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2893 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2894 assigned-clock-rates = <19200000>, <200000000>; 2895 2896 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2897 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2898 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2899 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2900 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2901 "dm_hs_phy_irq", "ss_phy_irq"; 2902 2903 power-domains = <&gcc USB30_PRIM_GDSC>; 2904 2905 resets = <&gcc GCC_USB30_PRIM_BCR>; 2906 2907 usb_1_dwc3: usb@a600000 { 2908 compatible = "snps,dwc3"; 2909 reg = <0 0x0a600000 0 0xcd00>; 2910 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2911 iommus = <&apps_smmu 0x0 0x0>; 2912 snps,dis_u2_susphy_quirk; 2913 snps,dis_enblslpm_quirk; 2914 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2915 phy-names = "usb2-phy", "usb3-phy"; 2916 }; 2917 }; 2918 2919 system-cache-controller@9200000 { 2920 compatible = "qcom,sm8250-llcc"; 2921 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 2922 reg-names = "llcc_base", "llcc_broadcast_base"; 2923 }; 2924 2925 usb_2: usb@a8f8800 { 2926 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 2927 reg = <0 0x0a8f8800 0 0x400>; 2928 status = "disabled"; 2929 #address-cells = <2>; 2930 #size-cells = <2>; 2931 ranges; 2932 dma-ranges; 2933 2934 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2935 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2936 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2937 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2938 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2939 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2940 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2941 "sleep", "xo"; 2942 2943 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2944 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2945 assigned-clock-rates = <19200000>, <200000000>; 2946 2947 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2948 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 2949 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2950 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 2951 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2952 "dm_hs_phy_irq", "ss_phy_irq"; 2953 2954 power-domains = <&gcc USB30_SEC_GDSC>; 2955 2956 resets = <&gcc GCC_USB30_SEC_BCR>; 2957 2958 usb_2_dwc3: usb@a800000 { 2959 compatible = "snps,dwc3"; 2960 reg = <0 0x0a800000 0 0xcd00>; 2961 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2962 iommus = <&apps_smmu 0x20 0>; 2963 snps,dis_u2_susphy_quirk; 2964 snps,dis_enblslpm_quirk; 2965 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2966 phy-names = "usb2-phy", "usb3-phy"; 2967 }; 2968 }; 2969 2970 venus: video-codec@aa00000 { 2971 compatible = "qcom,sm8250-venus"; 2972 reg = <0 0x0aa00000 0 0x100000>; 2973 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2974 power-domains = <&videocc MVS0C_GDSC>, 2975 <&videocc MVS0_GDSC>, 2976 <&rpmhpd SM8250_MX>; 2977 power-domain-names = "venus", "vcodec0", "mx"; 2978 operating-points-v2 = <&venus_opp_table>; 2979 2980 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 2981 <&videocc VIDEO_CC_MVS0C_CLK>, 2982 <&videocc VIDEO_CC_MVS0_CLK>; 2983 clock-names = "iface", "core", "vcodec0_core"; 2984 2985 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, 2986 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; 2987 interconnect-names = "cpu-cfg", "video-mem"; 2988 2989 iommus = <&apps_smmu 0x2100 0x0400>; 2990 memory-region = <&video_mem>; 2991 2992 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 2993 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 2994 reset-names = "bus", "core"; 2995 2996 status = "disabled"; 2997 2998 video-decoder { 2999 compatible = "venus-decoder"; 3000 }; 3001 3002 video-encoder { 3003 compatible = "venus-encoder"; 3004 }; 3005 3006 venus_opp_table: venus-opp-table { 3007 compatible = "operating-points-v2"; 3008 3009 opp-720000000 { 3010 opp-hz = /bits/ 64 <720000000>; 3011 required-opps = <&rpmhpd_opp_low_svs>; 3012 }; 3013 3014 opp-1014000000 { 3015 opp-hz = /bits/ 64 <1014000000>; 3016 required-opps = <&rpmhpd_opp_svs>; 3017 }; 3018 3019 opp-1098000000 { 3020 opp-hz = /bits/ 64 <1098000000>; 3021 required-opps = <&rpmhpd_opp_svs_l1>; 3022 }; 3023 3024 opp-1332000000 { 3025 opp-hz = /bits/ 64 <1332000000>; 3026 required-opps = <&rpmhpd_opp_nom>; 3027 }; 3028 }; 3029 }; 3030 3031 videocc: clock-controller@abf0000 { 3032 compatible = "qcom,sm8250-videocc"; 3033 reg = <0 0x0abf0000 0 0x10000>; 3034 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 3035 <&rpmhcc RPMH_CXO_CLK>, 3036 <&rpmhcc RPMH_CXO_CLK_A>; 3037 power-domains = <&rpmhpd SM8250_MMCX>; 3038 required-opps = <&rpmhpd_opp_low_svs>; 3039 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 3040 #clock-cells = <1>; 3041 #reset-cells = <1>; 3042 #power-domain-cells = <1>; 3043 }; 3044 3045 mdss: mdss@ae00000 { 3046 compatible = "qcom,sm8250-mdss"; 3047 reg = <0 0x0ae00000 0 0x1000>; 3048 reg-names = "mdss"; 3049 3050 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 3051 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 3052 interconnect-names = "mdp0-mem", "mdp1-mem"; 3053 3054 power-domains = <&dispcc MDSS_GDSC>; 3055 3056 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3057 <&gcc GCC_DISP_HF_AXI_CLK>, 3058 <&gcc GCC_DISP_SF_AXI_CLK>, 3059 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3060 clock-names = "iface", "bus", "nrt_bus", "core"; 3061 3062 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 3063 assigned-clock-rates = <460000000>; 3064 3065 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3066 interrupt-controller; 3067 #interrupt-cells = <1>; 3068 3069 iommus = <&apps_smmu 0x820 0x402>; 3070 3071 status = "disabled"; 3072 3073 #address-cells = <2>; 3074 #size-cells = <2>; 3075 ranges; 3076 3077 mdss_mdp: mdp@ae01000 { 3078 compatible = "qcom,sm8250-dpu"; 3079 reg = <0 0x0ae01000 0 0x8f000>, 3080 <0 0x0aeb0000 0 0x2008>; 3081 reg-names = "mdp", "vbif"; 3082 3083 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3084 <&gcc GCC_DISP_HF_AXI_CLK>, 3085 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3086 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3087 clock-names = "iface", "bus", "core", "vsync"; 3088 3089 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3090 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3091 assigned-clock-rates = <460000000>, 3092 <19200000>; 3093 3094 operating-points-v2 = <&mdp_opp_table>; 3095 power-domains = <&rpmhpd SM8250_MMCX>; 3096 3097 interrupt-parent = <&mdss>; 3098 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 3099 3100 ports { 3101 #address-cells = <1>; 3102 #size-cells = <0>; 3103 3104 port@0 { 3105 reg = <0>; 3106 dpu_intf1_out: endpoint { 3107 remote-endpoint = <&dsi0_in>; 3108 }; 3109 }; 3110 3111 port@1 { 3112 reg = <1>; 3113 dpu_intf2_out: endpoint { 3114 remote-endpoint = <&dsi1_in>; 3115 }; 3116 }; 3117 }; 3118 3119 mdp_opp_table: mdp-opp-table { 3120 compatible = "operating-points-v2"; 3121 3122 opp-200000000 { 3123 opp-hz = /bits/ 64 <200000000>; 3124 required-opps = <&rpmhpd_opp_low_svs>; 3125 }; 3126 3127 opp-300000000 { 3128 opp-hz = /bits/ 64 <300000000>; 3129 required-opps = <&rpmhpd_opp_svs>; 3130 }; 3131 3132 opp-345000000 { 3133 opp-hz = /bits/ 64 <345000000>; 3134 required-opps = <&rpmhpd_opp_svs_l1>; 3135 }; 3136 3137 opp-460000000 { 3138 opp-hz = /bits/ 64 <460000000>; 3139 required-opps = <&rpmhpd_opp_nom>; 3140 }; 3141 }; 3142 }; 3143 3144 dsi0: dsi@ae94000 { 3145 compatible = "qcom,mdss-dsi-ctrl"; 3146 reg = <0 0x0ae94000 0 0x400>; 3147 reg-names = "dsi_ctrl"; 3148 3149 interrupt-parent = <&mdss>; 3150 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 3151 3152 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3153 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3154 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3155 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3156 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3157 <&gcc GCC_DISP_HF_AXI_CLK>; 3158 clock-names = "byte", 3159 "byte_intf", 3160 "pixel", 3161 "core", 3162 "iface", 3163 "bus"; 3164 3165 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3166 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 3167 3168 operating-points-v2 = <&dsi_opp_table>; 3169 power-domains = <&rpmhpd SM8250_MMCX>; 3170 3171 phys = <&dsi0_phy>; 3172 phy-names = "dsi"; 3173 3174 status = "disabled"; 3175 3176 #address-cells = <1>; 3177 #size-cells = <0>; 3178 3179 ports { 3180 #address-cells = <1>; 3181 #size-cells = <0>; 3182 3183 port@0 { 3184 reg = <0>; 3185 dsi0_in: endpoint { 3186 remote-endpoint = <&dpu_intf1_out>; 3187 }; 3188 }; 3189 3190 port@1 { 3191 reg = <1>; 3192 dsi0_out: endpoint { 3193 }; 3194 }; 3195 }; 3196 }; 3197 3198 dsi0_phy: dsi-phy@ae94400 { 3199 compatible = "qcom,dsi-phy-7nm"; 3200 reg = <0 0x0ae94400 0 0x200>, 3201 <0 0x0ae94600 0 0x280>, 3202 <0 0x0ae94900 0 0x260>; 3203 reg-names = "dsi_phy", 3204 "dsi_phy_lane", 3205 "dsi_pll"; 3206 3207 #clock-cells = <1>; 3208 #phy-cells = <0>; 3209 3210 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3211 <&rpmhcc RPMH_CXO_CLK>; 3212 clock-names = "iface", "ref"; 3213 3214 status = "disabled"; 3215 }; 3216 3217 dsi1: dsi@ae96000 { 3218 compatible = "qcom,mdss-dsi-ctrl"; 3219 reg = <0 0x0ae96000 0 0x400>; 3220 reg-names = "dsi_ctrl"; 3221 3222 interrupt-parent = <&mdss>; 3223 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 3224 3225 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3226 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3227 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3228 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3229 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3230 <&gcc GCC_DISP_HF_AXI_CLK>; 3231 clock-names = "byte", 3232 "byte_intf", 3233 "pixel", 3234 "core", 3235 "iface", 3236 "bus"; 3237 3238 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3239 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 3240 3241 operating-points-v2 = <&dsi_opp_table>; 3242 power-domains = <&rpmhpd SM8250_MMCX>; 3243 3244 phys = <&dsi1_phy>; 3245 phy-names = "dsi"; 3246 3247 status = "disabled"; 3248 3249 #address-cells = <1>; 3250 #size-cells = <0>; 3251 3252 ports { 3253 #address-cells = <1>; 3254 #size-cells = <0>; 3255 3256 port@0 { 3257 reg = <0>; 3258 dsi1_in: endpoint { 3259 remote-endpoint = <&dpu_intf2_out>; 3260 }; 3261 }; 3262 3263 port@1 { 3264 reg = <1>; 3265 dsi1_out: endpoint { 3266 }; 3267 }; 3268 }; 3269 }; 3270 3271 dsi1_phy: dsi-phy@ae96400 { 3272 compatible = "qcom,dsi-phy-7nm"; 3273 reg = <0 0x0ae96400 0 0x200>, 3274 <0 0x0ae96600 0 0x280>, 3275 <0 0x0ae96900 0 0x260>; 3276 reg-names = "dsi_phy", 3277 "dsi_phy_lane", 3278 "dsi_pll"; 3279 3280 #clock-cells = <1>; 3281 #phy-cells = <0>; 3282 3283 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3284 <&rpmhcc RPMH_CXO_CLK>; 3285 clock-names = "iface", "ref"; 3286 3287 status = "disabled"; 3288 3289 dsi_opp_table: dsi-opp-table { 3290 compatible = "operating-points-v2"; 3291 3292 opp-187500000 { 3293 opp-hz = /bits/ 64 <187500000>; 3294 required-opps = <&rpmhpd_opp_low_svs>; 3295 }; 3296 3297 opp-300000000 { 3298 opp-hz = /bits/ 64 <300000000>; 3299 required-opps = <&rpmhpd_opp_svs>; 3300 }; 3301 3302 opp-358000000 { 3303 opp-hz = /bits/ 64 <358000000>; 3304 required-opps = <&rpmhpd_opp_svs_l1>; 3305 }; 3306 }; 3307 }; 3308 }; 3309 3310 dispcc: clock-controller@af00000 { 3311 compatible = "qcom,sm8250-dispcc"; 3312 reg = <0 0x0af00000 0 0x10000>; 3313 power-domains = <&rpmhpd SM8250_MMCX>; 3314 required-opps = <&rpmhpd_opp_low_svs>; 3315 clocks = <&rpmhcc RPMH_CXO_CLK>, 3316 <&dsi0_phy 0>, 3317 <&dsi0_phy 1>, 3318 <&dsi1_phy 0>, 3319 <&dsi1_phy 1>, 3320 <&dp_phy 0>, 3321 <&dp_phy 1>; 3322 clock-names = "bi_tcxo", 3323 "dsi0_phy_pll_out_byteclk", 3324 "dsi0_phy_pll_out_dsiclk", 3325 "dsi1_phy_pll_out_byteclk", 3326 "dsi1_phy_pll_out_dsiclk", 3327 "dp_phy_pll_link_clk", 3328 "dp_phy_pll_vco_div_clk"; 3329 #clock-cells = <1>; 3330 #reset-cells = <1>; 3331 #power-domain-cells = <1>; 3332 }; 3333 3334 pdc: interrupt-controller@b220000 { 3335 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 3336 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 3337 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3338 <125 63 1>, <126 716 12>; 3339 #interrupt-cells = <2>; 3340 interrupt-parent = <&intc>; 3341 interrupt-controller; 3342 }; 3343 3344 tsens0: thermal-sensor@c263000 { 3345 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 3346 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3347 <0 0x0c222000 0 0x1ff>; /* SROT */ 3348 #qcom,sensors = <16>; 3349 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3350 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3351 interrupt-names = "uplow", "critical"; 3352 #thermal-sensor-cells = <1>; 3353 }; 3354 3355 tsens1: thermal-sensor@c265000 { 3356 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 3357 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3358 <0 0x0c223000 0 0x1ff>; /* SROT */ 3359 #qcom,sensors = <9>; 3360 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3362 interrupt-names = "uplow", "critical"; 3363 #thermal-sensor-cells = <1>; 3364 }; 3365 3366 aoss_qmp: power-controller@c300000 { 3367 compatible = "qcom,sm8250-aoss-qmp"; 3368 reg = <0 0x0c300000 0 0x400>; 3369 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3370 IPCC_MPROC_SIGNAL_GLINK_QMP 3371 IRQ_TYPE_EDGE_RISING>; 3372 mboxes = <&ipcc IPCC_CLIENT_AOP 3373 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3374 3375 #clock-cells = <0>; 3376 }; 3377 3378 sram@c3f0000 { 3379 compatible = "qcom,rpmh-stats"; 3380 reg = <0 0x0c3f0000 0 0x400>; 3381 }; 3382 3383 spmi_bus: spmi@c440000 { 3384 compatible = "qcom,spmi-pmic-arb"; 3385 reg = <0x0 0x0c440000 0x0 0x0001100>, 3386 <0x0 0x0c600000 0x0 0x2000000>, 3387 <0x0 0x0e600000 0x0 0x0100000>, 3388 <0x0 0x0e700000 0x0 0x00a0000>, 3389 <0x0 0x0c40a000 0x0 0x0026000>; 3390 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3391 interrupt-names = "periph_irq"; 3392 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3393 qcom,ee = <0>; 3394 qcom,channel = <0>; 3395 #address-cells = <2>; 3396 #size-cells = <0>; 3397 interrupt-controller; 3398 #interrupt-cells = <4>; 3399 }; 3400 3401 tlmm: pinctrl@f100000 { 3402 compatible = "qcom,sm8250-pinctrl"; 3403 reg = <0 0x0f100000 0 0x300000>, 3404 <0 0x0f500000 0 0x300000>, 3405 <0 0x0f900000 0 0x300000>; 3406 reg-names = "west", "south", "north"; 3407 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3408 gpio-controller; 3409 #gpio-cells = <2>; 3410 interrupt-controller; 3411 #interrupt-cells = <2>; 3412 gpio-ranges = <&tlmm 0 0 181>; 3413 wakeup-parent = <&pdc>; 3414 3415 pri_mi2s_active: pri-mi2s-active { 3416 sclk { 3417 pins = "gpio138"; 3418 function = "mi2s0_sck"; 3419 drive-strength = <8>; 3420 bias-disable; 3421 }; 3422 3423 ws { 3424 pins = "gpio141"; 3425 function = "mi2s0_ws"; 3426 drive-strength = <8>; 3427 output-high; 3428 }; 3429 3430 data0 { 3431 pins = "gpio139"; 3432 function = "mi2s0_data0"; 3433 drive-strength = <8>; 3434 bias-disable; 3435 output-high; 3436 }; 3437 3438 data1 { 3439 pins = "gpio140"; 3440 function = "mi2s0_data1"; 3441 drive-strength = <8>; 3442 output-high; 3443 }; 3444 }; 3445 3446 qup_i2c0_default: qup-i2c0-default { 3447 mux { 3448 pins = "gpio28", "gpio29"; 3449 function = "qup0"; 3450 }; 3451 3452 config { 3453 pins = "gpio28", "gpio29"; 3454 drive-strength = <2>; 3455 bias-disable; 3456 }; 3457 }; 3458 3459 qup_i2c1_default: qup-i2c1-default { 3460 pinmux { 3461 pins = "gpio4", "gpio5"; 3462 function = "qup1"; 3463 }; 3464 3465 config { 3466 pins = "gpio4", "gpio5"; 3467 drive-strength = <2>; 3468 bias-disable; 3469 }; 3470 }; 3471 3472 qup_i2c2_default: qup-i2c2-default { 3473 mux { 3474 pins = "gpio115", "gpio116"; 3475 function = "qup2"; 3476 }; 3477 3478 config { 3479 pins = "gpio115", "gpio116"; 3480 drive-strength = <2>; 3481 bias-disable; 3482 }; 3483 }; 3484 3485 qup_i2c3_default: qup-i2c3-default { 3486 mux { 3487 pins = "gpio119", "gpio120"; 3488 function = "qup3"; 3489 }; 3490 3491 config { 3492 pins = "gpio119", "gpio120"; 3493 drive-strength = <2>; 3494 bias-disable; 3495 }; 3496 }; 3497 3498 qup_i2c4_default: qup-i2c4-default { 3499 mux { 3500 pins = "gpio8", "gpio9"; 3501 function = "qup4"; 3502 }; 3503 3504 config { 3505 pins = "gpio8", "gpio9"; 3506 drive-strength = <2>; 3507 bias-disable; 3508 }; 3509 }; 3510 3511 qup_i2c5_default: qup-i2c5-default { 3512 mux { 3513 pins = "gpio12", "gpio13"; 3514 function = "qup5"; 3515 }; 3516 3517 config { 3518 pins = "gpio12", "gpio13"; 3519 drive-strength = <2>; 3520 bias-disable; 3521 }; 3522 }; 3523 3524 qup_i2c6_default: qup-i2c6-default { 3525 mux { 3526 pins = "gpio16", "gpio17"; 3527 function = "qup6"; 3528 }; 3529 3530 config { 3531 pins = "gpio16", "gpio17"; 3532 drive-strength = <2>; 3533 bias-disable; 3534 }; 3535 }; 3536 3537 qup_i2c7_default: qup-i2c7-default { 3538 mux { 3539 pins = "gpio20", "gpio21"; 3540 function = "qup7"; 3541 }; 3542 3543 config { 3544 pins = "gpio20", "gpio21"; 3545 drive-strength = <2>; 3546 bias-disable; 3547 }; 3548 }; 3549 3550 qup_i2c8_default: qup-i2c8-default { 3551 mux { 3552 pins = "gpio24", "gpio25"; 3553 function = "qup8"; 3554 }; 3555 3556 config { 3557 pins = "gpio24", "gpio25"; 3558 drive-strength = <2>; 3559 bias-disable; 3560 }; 3561 }; 3562 3563 qup_i2c9_default: qup-i2c9-default { 3564 mux { 3565 pins = "gpio125", "gpio126"; 3566 function = "qup9"; 3567 }; 3568 3569 config { 3570 pins = "gpio125", "gpio126"; 3571 drive-strength = <2>; 3572 bias-disable; 3573 }; 3574 }; 3575 3576 qup_i2c10_default: qup-i2c10-default { 3577 mux { 3578 pins = "gpio129", "gpio130"; 3579 function = "qup10"; 3580 }; 3581 3582 config { 3583 pins = "gpio129", "gpio130"; 3584 drive-strength = <2>; 3585 bias-disable; 3586 }; 3587 }; 3588 3589 qup_i2c11_default: qup-i2c11-default { 3590 mux { 3591 pins = "gpio60", "gpio61"; 3592 function = "qup11"; 3593 }; 3594 3595 config { 3596 pins = "gpio60", "gpio61"; 3597 drive-strength = <2>; 3598 bias-disable; 3599 }; 3600 }; 3601 3602 qup_i2c12_default: qup-i2c12-default { 3603 mux { 3604 pins = "gpio32", "gpio33"; 3605 function = "qup12"; 3606 }; 3607 3608 config { 3609 pins = "gpio32", "gpio33"; 3610 drive-strength = <2>; 3611 bias-disable; 3612 }; 3613 }; 3614 3615 qup_i2c13_default: qup-i2c13-default { 3616 mux { 3617 pins = "gpio36", "gpio37"; 3618 function = "qup13"; 3619 }; 3620 3621 config { 3622 pins = "gpio36", "gpio37"; 3623 drive-strength = <2>; 3624 bias-disable; 3625 }; 3626 }; 3627 3628 qup_i2c14_default: qup-i2c14-default { 3629 mux { 3630 pins = "gpio40", "gpio41"; 3631 function = "qup14"; 3632 }; 3633 3634 config { 3635 pins = "gpio40", "gpio41"; 3636 drive-strength = <2>; 3637 bias-disable; 3638 }; 3639 }; 3640 3641 qup_i2c15_default: qup-i2c15-default { 3642 mux { 3643 pins = "gpio44", "gpio45"; 3644 function = "qup15"; 3645 }; 3646 3647 config { 3648 pins = "gpio44", "gpio45"; 3649 drive-strength = <2>; 3650 bias-disable; 3651 }; 3652 }; 3653 3654 qup_i2c16_default: qup-i2c16-default { 3655 mux { 3656 pins = "gpio48", "gpio49"; 3657 function = "qup16"; 3658 }; 3659 3660 config { 3661 pins = "gpio48", "gpio49"; 3662 drive-strength = <2>; 3663 bias-disable; 3664 }; 3665 }; 3666 3667 qup_i2c17_default: qup-i2c17-default { 3668 mux { 3669 pins = "gpio52", "gpio53"; 3670 function = "qup17"; 3671 }; 3672 3673 config { 3674 pins = "gpio52", "gpio53"; 3675 drive-strength = <2>; 3676 bias-disable; 3677 }; 3678 }; 3679 3680 qup_i2c18_default: qup-i2c18-default { 3681 mux { 3682 pins = "gpio56", "gpio57"; 3683 function = "qup18"; 3684 }; 3685 3686 config { 3687 pins = "gpio56", "gpio57"; 3688 drive-strength = <2>; 3689 bias-disable; 3690 }; 3691 }; 3692 3693 qup_i2c19_default: qup-i2c19-default { 3694 mux { 3695 pins = "gpio0", "gpio1"; 3696 function = "qup19"; 3697 }; 3698 3699 config { 3700 pins = "gpio0", "gpio1"; 3701 drive-strength = <2>; 3702 bias-disable; 3703 }; 3704 }; 3705 3706 qup_spi0_cs: qup-spi0-cs { 3707 pins = "gpio31"; 3708 function = "qup0"; 3709 }; 3710 3711 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3712 pins = "gpio31"; 3713 function = "gpio"; 3714 }; 3715 3716 qup_spi0_data_clk: qup-spi0-data-clk { 3717 pins = "gpio28", "gpio29", 3718 "gpio30"; 3719 function = "qup0"; 3720 }; 3721 3722 qup_spi1_cs: qup-spi1-cs { 3723 pins = "gpio7"; 3724 function = "qup1"; 3725 }; 3726 3727 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3728 pins = "gpio7"; 3729 function = "gpio"; 3730 }; 3731 3732 qup_spi1_data_clk: qup-spi1-data-clk { 3733 pins = "gpio4", "gpio5", 3734 "gpio6"; 3735 function = "qup1"; 3736 }; 3737 3738 qup_spi2_cs: qup-spi2-cs { 3739 pins = "gpio118"; 3740 function = "qup2"; 3741 }; 3742 3743 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3744 pins = "gpio118"; 3745 function = "gpio"; 3746 }; 3747 3748 qup_spi2_data_clk: qup-spi2-data-clk { 3749 pins = "gpio115", "gpio116", 3750 "gpio117"; 3751 function = "qup2"; 3752 }; 3753 3754 qup_spi3_cs: qup-spi3-cs { 3755 pins = "gpio122"; 3756 function = "qup3"; 3757 }; 3758 3759 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3760 pins = "gpio122"; 3761 function = "gpio"; 3762 }; 3763 3764 qup_spi3_data_clk: qup-spi3-data-clk { 3765 pins = "gpio119", "gpio120", 3766 "gpio121"; 3767 function = "qup3"; 3768 }; 3769 3770 qup_spi4_cs: qup-spi4-cs { 3771 pins = "gpio11"; 3772 function = "qup4"; 3773 }; 3774 3775 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3776 pins = "gpio11"; 3777 function = "gpio"; 3778 }; 3779 3780 qup_spi4_data_clk: qup-spi4-data-clk { 3781 pins = "gpio8", "gpio9", 3782 "gpio10"; 3783 function = "qup4"; 3784 }; 3785 3786 qup_spi5_cs: qup-spi5-cs { 3787 pins = "gpio15"; 3788 function = "qup5"; 3789 }; 3790 3791 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3792 pins = "gpio15"; 3793 function = "gpio"; 3794 }; 3795 3796 qup_spi5_data_clk: qup-spi5-data-clk { 3797 pins = "gpio12", "gpio13", 3798 "gpio14"; 3799 function = "qup5"; 3800 }; 3801 3802 qup_spi6_cs: qup-spi6-cs { 3803 pins = "gpio19"; 3804 function = "qup6"; 3805 }; 3806 3807 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3808 pins = "gpio19"; 3809 function = "gpio"; 3810 }; 3811 3812 qup_spi6_data_clk: qup-spi6-data-clk { 3813 pins = "gpio16", "gpio17", 3814 "gpio18"; 3815 function = "qup6"; 3816 }; 3817 3818 qup_spi7_cs: qup-spi7-cs { 3819 pins = "gpio23"; 3820 function = "qup7"; 3821 }; 3822 3823 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3824 pins = "gpio23"; 3825 function = "gpio"; 3826 }; 3827 3828 qup_spi7_data_clk: qup-spi7-data-clk { 3829 pins = "gpio20", "gpio21", 3830 "gpio22"; 3831 function = "qup7"; 3832 }; 3833 3834 qup_spi8_cs: qup-spi8-cs { 3835 pins = "gpio27"; 3836 function = "qup8"; 3837 }; 3838 3839 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3840 pins = "gpio27"; 3841 function = "gpio"; 3842 }; 3843 3844 qup_spi8_data_clk: qup-spi8-data-clk { 3845 pins = "gpio24", "gpio25", 3846 "gpio26"; 3847 function = "qup8"; 3848 }; 3849 3850 qup_spi9_cs: qup-spi9-cs { 3851 pins = "gpio128"; 3852 function = "qup9"; 3853 }; 3854 3855 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3856 pins = "gpio128"; 3857 function = "gpio"; 3858 }; 3859 3860 qup_spi9_data_clk: qup-spi9-data-clk { 3861 pins = "gpio125", "gpio126", 3862 "gpio127"; 3863 function = "qup9"; 3864 }; 3865 3866 qup_spi10_cs: qup-spi10-cs { 3867 pins = "gpio132"; 3868 function = "qup10"; 3869 }; 3870 3871 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3872 pins = "gpio132"; 3873 function = "gpio"; 3874 }; 3875 3876 qup_spi10_data_clk: qup-spi10-data-clk { 3877 pins = "gpio129", "gpio130", 3878 "gpio131"; 3879 function = "qup10"; 3880 }; 3881 3882 qup_spi11_cs: qup-spi11-cs { 3883 pins = "gpio63"; 3884 function = "qup11"; 3885 }; 3886 3887 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3888 pins = "gpio63"; 3889 function = "gpio"; 3890 }; 3891 3892 qup_spi11_data_clk: qup-spi11-data-clk { 3893 pins = "gpio60", "gpio61", 3894 "gpio62"; 3895 function = "qup11"; 3896 }; 3897 3898 qup_spi12_cs: qup-spi12-cs { 3899 pins = "gpio35"; 3900 function = "qup12"; 3901 }; 3902 3903 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3904 pins = "gpio35"; 3905 function = "gpio"; 3906 }; 3907 3908 qup_spi12_data_clk: qup-spi12-data-clk { 3909 pins = "gpio32", "gpio33", 3910 "gpio34"; 3911 function = "qup12"; 3912 }; 3913 3914 qup_spi13_cs: qup-spi13-cs { 3915 pins = "gpio39"; 3916 function = "qup13"; 3917 }; 3918 3919 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3920 pins = "gpio39"; 3921 function = "gpio"; 3922 }; 3923 3924 qup_spi13_data_clk: qup-spi13-data-clk { 3925 pins = "gpio36", "gpio37", 3926 "gpio38"; 3927 function = "qup13"; 3928 }; 3929 3930 qup_spi14_cs: qup-spi14-cs { 3931 pins = "gpio43"; 3932 function = "qup14"; 3933 }; 3934 3935 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3936 pins = "gpio43"; 3937 function = "gpio"; 3938 }; 3939 3940 qup_spi14_data_clk: qup-spi14-data-clk { 3941 pins = "gpio40", "gpio41", 3942 "gpio42"; 3943 function = "qup14"; 3944 }; 3945 3946 qup_spi15_cs: qup-spi15-cs { 3947 pins = "gpio47"; 3948 function = "qup15"; 3949 }; 3950 3951 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3952 pins = "gpio47"; 3953 function = "gpio"; 3954 }; 3955 3956 qup_spi15_data_clk: qup-spi15-data-clk { 3957 pins = "gpio44", "gpio45", 3958 "gpio46"; 3959 function = "qup15"; 3960 }; 3961 3962 qup_spi16_cs: qup-spi16-cs { 3963 pins = "gpio51"; 3964 function = "qup16"; 3965 }; 3966 3967 qup_spi16_cs_gpio: qup-spi16-cs-gpio { 3968 pins = "gpio51"; 3969 function = "gpio"; 3970 }; 3971 3972 qup_spi16_data_clk: qup-spi16-data-clk { 3973 pins = "gpio48", "gpio49", 3974 "gpio50"; 3975 function = "qup16"; 3976 }; 3977 3978 qup_spi17_cs: qup-spi17-cs { 3979 pins = "gpio55"; 3980 function = "qup17"; 3981 }; 3982 3983 qup_spi17_cs_gpio: qup-spi17-cs-gpio { 3984 pins = "gpio55"; 3985 function = "gpio"; 3986 }; 3987 3988 qup_spi17_data_clk: qup-spi17-data-clk { 3989 pins = "gpio52", "gpio53", 3990 "gpio54"; 3991 function = "qup17"; 3992 }; 3993 3994 qup_spi18_cs: qup-spi18-cs { 3995 pins = "gpio59"; 3996 function = "qup18"; 3997 }; 3998 3999 qup_spi18_cs_gpio: qup-spi18-cs-gpio { 4000 pins = "gpio59"; 4001 function = "gpio"; 4002 }; 4003 4004 qup_spi18_data_clk: qup-spi18-data-clk { 4005 pins = "gpio56", "gpio57", 4006 "gpio58"; 4007 function = "qup18"; 4008 }; 4009 4010 qup_spi19_cs: qup-spi19-cs { 4011 pins = "gpio3"; 4012 function = "qup19"; 4013 }; 4014 4015 qup_spi19_cs_gpio: qup-spi19-cs-gpio { 4016 pins = "gpio3"; 4017 function = "gpio"; 4018 }; 4019 4020 qup_spi19_data_clk: qup-spi19-data-clk { 4021 pins = "gpio0", "gpio1", 4022 "gpio2"; 4023 function = "qup19"; 4024 }; 4025 4026 qup_uart2_default: qup-uart2-default { 4027 mux { 4028 pins = "gpio117", "gpio118"; 4029 function = "qup2"; 4030 }; 4031 }; 4032 4033 qup_uart6_default: qup-uart6-default { 4034 mux { 4035 pins = "gpio16", "gpio17", 4036 "gpio18", "gpio19"; 4037 function = "qup6"; 4038 }; 4039 }; 4040 4041 qup_uart12_default: qup-uart12-default { 4042 mux { 4043 pins = "gpio34", "gpio35"; 4044 function = "qup12"; 4045 }; 4046 }; 4047 4048 qup_uart17_default: qup-uart17-default { 4049 mux { 4050 pins = "gpio52", "gpio53", 4051 "gpio54", "gpio55"; 4052 function = "qup17"; 4053 }; 4054 }; 4055 4056 qup_uart18_default: qup-uart18-default { 4057 mux { 4058 pins = "gpio58", "gpio59"; 4059 function = "qup18"; 4060 }; 4061 }; 4062 4063 tert_mi2s_active: tert-mi2s-active { 4064 sck { 4065 pins = "gpio133"; 4066 function = "mi2s2_sck"; 4067 drive-strength = <8>; 4068 bias-disable; 4069 }; 4070 4071 data0 { 4072 pins = "gpio134"; 4073 function = "mi2s2_data0"; 4074 drive-strength = <8>; 4075 bias-disable; 4076 output-high; 4077 }; 4078 4079 ws { 4080 pins = "gpio135"; 4081 function = "mi2s2_ws"; 4082 drive-strength = <8>; 4083 output-high; 4084 }; 4085 }; 4086 4087 sdc2_sleep_state: sdc2-sleep { 4088 clk { 4089 pins = "sdc2_clk"; 4090 drive-strength = <2>; 4091 bias-disable; 4092 }; 4093 4094 cmd { 4095 pins = "sdc2_cmd"; 4096 drive-strength = <2>; 4097 bias-pull-up; 4098 }; 4099 4100 data { 4101 pins = "sdc2_data"; 4102 drive-strength = <2>; 4103 bias-pull-up; 4104 }; 4105 }; 4106 4107 pcie0_default_state: pcie0-default { 4108 perst { 4109 pins = "gpio79"; 4110 function = "gpio"; 4111 drive-strength = <2>; 4112 bias-pull-down; 4113 }; 4114 4115 clkreq { 4116 pins = "gpio80"; 4117 function = "pci_e0"; 4118 drive-strength = <2>; 4119 bias-pull-up; 4120 }; 4121 4122 wake { 4123 pins = "gpio81"; 4124 function = "gpio"; 4125 drive-strength = <2>; 4126 bias-pull-up; 4127 }; 4128 }; 4129 4130 pcie1_default_state: pcie1-default { 4131 perst { 4132 pins = "gpio82"; 4133 function = "gpio"; 4134 drive-strength = <2>; 4135 bias-pull-down; 4136 }; 4137 4138 clkreq { 4139 pins = "gpio83"; 4140 function = "pci_e1"; 4141 drive-strength = <2>; 4142 bias-pull-up; 4143 }; 4144 4145 wake { 4146 pins = "gpio84"; 4147 function = "gpio"; 4148 drive-strength = <2>; 4149 bias-pull-up; 4150 }; 4151 }; 4152 4153 pcie2_default_state: pcie2-default { 4154 perst { 4155 pins = "gpio85"; 4156 function = "gpio"; 4157 drive-strength = <2>; 4158 bias-pull-down; 4159 }; 4160 4161 clkreq { 4162 pins = "gpio86"; 4163 function = "pci_e2"; 4164 drive-strength = <2>; 4165 bias-pull-up; 4166 }; 4167 4168 wake { 4169 pins = "gpio87"; 4170 function = "gpio"; 4171 drive-strength = <2>; 4172 bias-pull-up; 4173 }; 4174 }; 4175 }; 4176 4177 apps_smmu: iommu@15000000 { 4178 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 4179 reg = <0 0x15000000 0 0x100000>; 4180 #iommu-cells = <2>; 4181 #global-interrupts = <2>; 4182 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 4183 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4184 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4185 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4186 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4187 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4188 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4189 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4190 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4191 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4192 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4193 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4194 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4195 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4196 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4197 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4198 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4199 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4200 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4201 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4202 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4203 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4204 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4205 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4206 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4207 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4208 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4209 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4210 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4211 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4212 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4213 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4214 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4215 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4216 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4217 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4218 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4219 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4220 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4221 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4222 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4223 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4224 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4225 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4226 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4227 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4228 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4229 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4230 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4231 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4232 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4233 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4234 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4235 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4236 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4237 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4238 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4239 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4240 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4241 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4242 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4243 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4244 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4245 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4246 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4247 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4248 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4249 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4250 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4251 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4252 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4253 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4254 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4255 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4256 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4257 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4258 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4259 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4260 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4261 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4262 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4263 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4264 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4265 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4266 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4267 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4268 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4269 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4270 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4271 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4272 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4273 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4274 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4275 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4276 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4277 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4278 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 4279 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 4280 }; 4281 4282 adsp: remoteproc@17300000 { 4283 compatible = "qcom,sm8250-adsp-pas"; 4284 reg = <0 0x17300000 0 0x100>; 4285 4286 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 4287 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4288 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4289 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4290 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4291 interrupt-names = "wdog", "fatal", "ready", 4292 "handover", "stop-ack"; 4293 4294 clocks = <&rpmhcc RPMH_CXO_CLK>; 4295 clock-names = "xo"; 4296 4297 power-domains = <&rpmhpd SM8250_LCX>, 4298 <&rpmhpd SM8250_LMX>; 4299 power-domain-names = "lcx", "lmx"; 4300 4301 memory-region = <&adsp_mem>; 4302 4303 qcom,qmp = <&aoss_qmp>; 4304 4305 qcom,smem-states = <&smp2p_adsp_out 0>; 4306 qcom,smem-state-names = "stop"; 4307 4308 status = "disabled"; 4309 4310 glink-edge { 4311 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4312 IPCC_MPROC_SIGNAL_GLINK_QMP 4313 IRQ_TYPE_EDGE_RISING>; 4314 mboxes = <&ipcc IPCC_CLIENT_LPASS 4315 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4316 4317 label = "lpass"; 4318 qcom,remote-pid = <2>; 4319 4320 apr { 4321 compatible = "qcom,apr-v2"; 4322 qcom,glink-channels = "apr_audio_svc"; 4323 qcom,apr-domain = <APR_DOMAIN_ADSP>; 4324 #address-cells = <1>; 4325 #size-cells = <0>; 4326 4327 apr-service@3 { 4328 reg = <APR_SVC_ADSP_CORE>; 4329 compatible = "qcom,q6core"; 4330 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4331 }; 4332 4333 q6afe: apr-service@4 { 4334 compatible = "qcom,q6afe"; 4335 reg = <APR_SVC_AFE>; 4336 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4337 q6afedai: dais { 4338 compatible = "qcom,q6afe-dais"; 4339 #address-cells = <1>; 4340 #size-cells = <0>; 4341 #sound-dai-cells = <1>; 4342 }; 4343 4344 q6afecc: cc { 4345 compatible = "qcom,q6afe-clocks"; 4346 #clock-cells = <2>; 4347 }; 4348 }; 4349 4350 q6asm: apr-service@7 { 4351 compatible = "qcom,q6asm"; 4352 reg = <APR_SVC_ASM>; 4353 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4354 q6asmdai: dais { 4355 compatible = "qcom,q6asm-dais"; 4356 #address-cells = <1>; 4357 #size-cells = <0>; 4358 #sound-dai-cells = <1>; 4359 iommus = <&apps_smmu 0x1801 0x0>; 4360 }; 4361 }; 4362 4363 q6adm: apr-service@8 { 4364 compatible = "qcom,q6adm"; 4365 reg = <APR_SVC_ADM>; 4366 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4367 q6routing: routing { 4368 compatible = "qcom,q6adm-routing"; 4369 #sound-dai-cells = <0>; 4370 }; 4371 }; 4372 }; 4373 4374 fastrpc { 4375 compatible = "qcom,fastrpc"; 4376 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4377 label = "adsp"; 4378 #address-cells = <1>; 4379 #size-cells = <0>; 4380 4381 compute-cb@3 { 4382 compatible = "qcom,fastrpc-compute-cb"; 4383 reg = <3>; 4384 iommus = <&apps_smmu 0x1803 0x0>; 4385 }; 4386 4387 compute-cb@4 { 4388 compatible = "qcom,fastrpc-compute-cb"; 4389 reg = <4>; 4390 iommus = <&apps_smmu 0x1804 0x0>; 4391 }; 4392 4393 compute-cb@5 { 4394 compatible = "qcom,fastrpc-compute-cb"; 4395 reg = <5>; 4396 iommus = <&apps_smmu 0x1805 0x0>; 4397 }; 4398 }; 4399 }; 4400 }; 4401 4402 intc: interrupt-controller@17a00000 { 4403 compatible = "arm,gic-v3"; 4404 #interrupt-cells = <3>; 4405 interrupt-controller; 4406 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4407 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4408 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4409 }; 4410 4411 watchdog@17c10000 { 4412 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 4413 reg = <0 0x17c10000 0 0x1000>; 4414 clocks = <&sleep_clk>; 4415 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4416 }; 4417 4418 timer@17c20000 { 4419 #address-cells = <2>; 4420 #size-cells = <2>; 4421 ranges; 4422 compatible = "arm,armv7-timer-mem"; 4423 reg = <0x0 0x17c20000 0x0 0x1000>; 4424 clock-frequency = <19200000>; 4425 4426 frame@17c21000 { 4427 frame-number = <0>; 4428 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4429 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4430 reg = <0x0 0x17c21000 0x0 0x1000>, 4431 <0x0 0x17c22000 0x0 0x1000>; 4432 }; 4433 4434 frame@17c23000 { 4435 frame-number = <1>; 4436 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4437 reg = <0x0 0x17c23000 0x0 0x1000>; 4438 status = "disabled"; 4439 }; 4440 4441 frame@17c25000 { 4442 frame-number = <2>; 4443 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4444 reg = <0x0 0x17c25000 0x0 0x1000>; 4445 status = "disabled"; 4446 }; 4447 4448 frame@17c27000 { 4449 frame-number = <3>; 4450 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4451 reg = <0x0 0x17c27000 0x0 0x1000>; 4452 status = "disabled"; 4453 }; 4454 4455 frame@17c29000 { 4456 frame-number = <4>; 4457 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4458 reg = <0x0 0x17c29000 0x0 0x1000>; 4459 status = "disabled"; 4460 }; 4461 4462 frame@17c2b000 { 4463 frame-number = <5>; 4464 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4465 reg = <0x0 0x17c2b000 0x0 0x1000>; 4466 status = "disabled"; 4467 }; 4468 4469 frame@17c2d000 { 4470 frame-number = <6>; 4471 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4472 reg = <0x0 0x17c2d000 0x0 0x1000>; 4473 status = "disabled"; 4474 }; 4475 }; 4476 4477 apps_rsc: rsc@18200000 { 4478 label = "apps_rsc"; 4479 compatible = "qcom,rpmh-rsc"; 4480 reg = <0x0 0x18200000 0x0 0x10000>, 4481 <0x0 0x18210000 0x0 0x10000>, 4482 <0x0 0x18220000 0x0 0x10000>; 4483 reg-names = "drv-0", "drv-1", "drv-2"; 4484 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4485 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4486 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4487 qcom,tcs-offset = <0xd00>; 4488 qcom,drv-id = <2>; 4489 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 4490 <WAKE_TCS 3>, <CONTROL_TCS 1>; 4491 4492 rpmhcc: clock-controller { 4493 compatible = "qcom,sm8250-rpmh-clk"; 4494 #clock-cells = <1>; 4495 clock-names = "xo"; 4496 clocks = <&xo_board>; 4497 }; 4498 4499 rpmhpd: power-controller { 4500 compatible = "qcom,sm8250-rpmhpd"; 4501 #power-domain-cells = <1>; 4502 operating-points-v2 = <&rpmhpd_opp_table>; 4503 4504 rpmhpd_opp_table: opp-table { 4505 compatible = "operating-points-v2"; 4506 4507 rpmhpd_opp_ret: opp1 { 4508 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4509 }; 4510 4511 rpmhpd_opp_min_svs: opp2 { 4512 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4513 }; 4514 4515 rpmhpd_opp_low_svs: opp3 { 4516 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4517 }; 4518 4519 rpmhpd_opp_svs: opp4 { 4520 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4521 }; 4522 4523 rpmhpd_opp_svs_l1: opp5 { 4524 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4525 }; 4526 4527 rpmhpd_opp_nom: opp6 { 4528 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4529 }; 4530 4531 rpmhpd_opp_nom_l1: opp7 { 4532 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4533 }; 4534 4535 rpmhpd_opp_nom_l2: opp8 { 4536 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4537 }; 4538 4539 rpmhpd_opp_turbo: opp9 { 4540 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4541 }; 4542 4543 rpmhpd_opp_turbo_l1: opp10 { 4544 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4545 }; 4546 }; 4547 }; 4548 4549 apps_bcm_voter: bcm_voter { 4550 compatible = "qcom,bcm-voter"; 4551 }; 4552 }; 4553 4554 epss_l3: interconnect@18590000 { 4555 compatible = "qcom,sm8250-epss-l3"; 4556 reg = <0 0x18590000 0 0x1000>; 4557 4558 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4559 clock-names = "xo", "alternate"; 4560 4561 #interconnect-cells = <1>; 4562 }; 4563 4564 cpufreq_hw: cpufreq@18591000 { 4565 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 4566 reg = <0 0x18591000 0 0x1000>, 4567 <0 0x18592000 0 0x1000>, 4568 <0 0x18593000 0 0x1000>; 4569 reg-names = "freq-domain0", "freq-domain1", 4570 "freq-domain2"; 4571 4572 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4573 clock-names = "xo", "alternate"; 4574 4575 #freq-domain-cells = <1>; 4576 }; 4577 }; 4578 4579 timer { 4580 compatible = "arm,armv8-timer"; 4581 interrupts = <GIC_PPI 13 4582 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4583 <GIC_PPI 14 4584 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4585 <GIC_PPI 11 4586 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4587 <GIC_PPI 10 4588 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4589 }; 4590 4591 thermal-zones { 4592 cpu0-thermal { 4593 polling-delay-passive = <250>; 4594 polling-delay = <1000>; 4595 4596 thermal-sensors = <&tsens0 1>; 4597 4598 trips { 4599 cpu0_alert0: trip-point0 { 4600 temperature = <90000>; 4601 hysteresis = <2000>; 4602 type = "passive"; 4603 }; 4604 4605 cpu0_alert1: trip-point1 { 4606 temperature = <95000>; 4607 hysteresis = <2000>; 4608 type = "passive"; 4609 }; 4610 4611 cpu0_crit: cpu_crit { 4612 temperature = <110000>; 4613 hysteresis = <1000>; 4614 type = "critical"; 4615 }; 4616 }; 4617 4618 cooling-maps { 4619 map0 { 4620 trip = <&cpu0_alert0>; 4621 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4622 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4623 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4624 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4625 }; 4626 map1 { 4627 trip = <&cpu0_alert1>; 4628 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4629 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4630 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4631 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4632 }; 4633 }; 4634 }; 4635 4636 cpu1-thermal { 4637 polling-delay-passive = <250>; 4638 polling-delay = <1000>; 4639 4640 thermal-sensors = <&tsens0 2>; 4641 4642 trips { 4643 cpu1_alert0: trip-point0 { 4644 temperature = <90000>; 4645 hysteresis = <2000>; 4646 type = "passive"; 4647 }; 4648 4649 cpu1_alert1: trip-point1 { 4650 temperature = <95000>; 4651 hysteresis = <2000>; 4652 type = "passive"; 4653 }; 4654 4655 cpu1_crit: cpu_crit { 4656 temperature = <110000>; 4657 hysteresis = <1000>; 4658 type = "critical"; 4659 }; 4660 }; 4661 4662 cooling-maps { 4663 map0 { 4664 trip = <&cpu1_alert0>; 4665 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4666 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4667 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4668 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4669 }; 4670 map1 { 4671 trip = <&cpu1_alert1>; 4672 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4673 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4674 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4675 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4676 }; 4677 }; 4678 }; 4679 4680 cpu2-thermal { 4681 polling-delay-passive = <250>; 4682 polling-delay = <1000>; 4683 4684 thermal-sensors = <&tsens0 3>; 4685 4686 trips { 4687 cpu2_alert0: trip-point0 { 4688 temperature = <90000>; 4689 hysteresis = <2000>; 4690 type = "passive"; 4691 }; 4692 4693 cpu2_alert1: trip-point1 { 4694 temperature = <95000>; 4695 hysteresis = <2000>; 4696 type = "passive"; 4697 }; 4698 4699 cpu2_crit: cpu_crit { 4700 temperature = <110000>; 4701 hysteresis = <1000>; 4702 type = "critical"; 4703 }; 4704 }; 4705 4706 cooling-maps { 4707 map0 { 4708 trip = <&cpu2_alert0>; 4709 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4710 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4711 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4712 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4713 }; 4714 map1 { 4715 trip = <&cpu2_alert1>; 4716 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4717 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4718 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4719 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4720 }; 4721 }; 4722 }; 4723 4724 cpu3-thermal { 4725 polling-delay-passive = <250>; 4726 polling-delay = <1000>; 4727 4728 thermal-sensors = <&tsens0 4>; 4729 4730 trips { 4731 cpu3_alert0: trip-point0 { 4732 temperature = <90000>; 4733 hysteresis = <2000>; 4734 type = "passive"; 4735 }; 4736 4737 cpu3_alert1: trip-point1 { 4738 temperature = <95000>; 4739 hysteresis = <2000>; 4740 type = "passive"; 4741 }; 4742 4743 cpu3_crit: cpu_crit { 4744 temperature = <110000>; 4745 hysteresis = <1000>; 4746 type = "critical"; 4747 }; 4748 }; 4749 4750 cooling-maps { 4751 map0 { 4752 trip = <&cpu3_alert0>; 4753 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4754 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4755 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4756 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4757 }; 4758 map1 { 4759 trip = <&cpu3_alert1>; 4760 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4761 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4762 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4763 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4764 }; 4765 }; 4766 }; 4767 4768 cpu4-top-thermal { 4769 polling-delay-passive = <250>; 4770 polling-delay = <1000>; 4771 4772 thermal-sensors = <&tsens0 7>; 4773 4774 trips { 4775 cpu4_top_alert0: trip-point0 { 4776 temperature = <90000>; 4777 hysteresis = <2000>; 4778 type = "passive"; 4779 }; 4780 4781 cpu4_top_alert1: trip-point1 { 4782 temperature = <95000>; 4783 hysteresis = <2000>; 4784 type = "passive"; 4785 }; 4786 4787 cpu4_top_crit: cpu_crit { 4788 temperature = <110000>; 4789 hysteresis = <1000>; 4790 type = "critical"; 4791 }; 4792 }; 4793 4794 cooling-maps { 4795 map0 { 4796 trip = <&cpu4_top_alert0>; 4797 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4798 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4799 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4800 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4801 }; 4802 map1 { 4803 trip = <&cpu4_top_alert1>; 4804 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4805 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4806 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4807 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4808 }; 4809 }; 4810 }; 4811 4812 cpu5-top-thermal { 4813 polling-delay-passive = <250>; 4814 polling-delay = <1000>; 4815 4816 thermal-sensors = <&tsens0 8>; 4817 4818 trips { 4819 cpu5_top_alert0: trip-point0 { 4820 temperature = <90000>; 4821 hysteresis = <2000>; 4822 type = "passive"; 4823 }; 4824 4825 cpu5_top_alert1: trip-point1 { 4826 temperature = <95000>; 4827 hysteresis = <2000>; 4828 type = "passive"; 4829 }; 4830 4831 cpu5_top_crit: cpu_crit { 4832 temperature = <110000>; 4833 hysteresis = <1000>; 4834 type = "critical"; 4835 }; 4836 }; 4837 4838 cooling-maps { 4839 map0 { 4840 trip = <&cpu5_top_alert0>; 4841 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4842 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4843 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4844 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4845 }; 4846 map1 { 4847 trip = <&cpu5_top_alert1>; 4848 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4849 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4850 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4851 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4852 }; 4853 }; 4854 }; 4855 4856 cpu6-top-thermal { 4857 polling-delay-passive = <250>; 4858 polling-delay = <1000>; 4859 4860 thermal-sensors = <&tsens0 9>; 4861 4862 trips { 4863 cpu6_top_alert0: trip-point0 { 4864 temperature = <90000>; 4865 hysteresis = <2000>; 4866 type = "passive"; 4867 }; 4868 4869 cpu6_top_alert1: trip-point1 { 4870 temperature = <95000>; 4871 hysteresis = <2000>; 4872 type = "passive"; 4873 }; 4874 4875 cpu6_top_crit: cpu_crit { 4876 temperature = <110000>; 4877 hysteresis = <1000>; 4878 type = "critical"; 4879 }; 4880 }; 4881 4882 cooling-maps { 4883 map0 { 4884 trip = <&cpu6_top_alert0>; 4885 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4886 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4887 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4888 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4889 }; 4890 map1 { 4891 trip = <&cpu6_top_alert1>; 4892 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4893 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4894 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4895 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4896 }; 4897 }; 4898 }; 4899 4900 cpu7-top-thermal { 4901 polling-delay-passive = <250>; 4902 polling-delay = <1000>; 4903 4904 thermal-sensors = <&tsens0 10>; 4905 4906 trips { 4907 cpu7_top_alert0: trip-point0 { 4908 temperature = <90000>; 4909 hysteresis = <2000>; 4910 type = "passive"; 4911 }; 4912 4913 cpu7_top_alert1: trip-point1 { 4914 temperature = <95000>; 4915 hysteresis = <2000>; 4916 type = "passive"; 4917 }; 4918 4919 cpu7_top_crit: cpu_crit { 4920 temperature = <110000>; 4921 hysteresis = <1000>; 4922 type = "critical"; 4923 }; 4924 }; 4925 4926 cooling-maps { 4927 map0 { 4928 trip = <&cpu7_top_alert0>; 4929 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4930 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4931 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4932 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4933 }; 4934 map1 { 4935 trip = <&cpu7_top_alert1>; 4936 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4937 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4938 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4939 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4940 }; 4941 }; 4942 }; 4943 4944 cpu4-bottom-thermal { 4945 polling-delay-passive = <250>; 4946 polling-delay = <1000>; 4947 4948 thermal-sensors = <&tsens0 11>; 4949 4950 trips { 4951 cpu4_bottom_alert0: trip-point0 { 4952 temperature = <90000>; 4953 hysteresis = <2000>; 4954 type = "passive"; 4955 }; 4956 4957 cpu4_bottom_alert1: trip-point1 { 4958 temperature = <95000>; 4959 hysteresis = <2000>; 4960 type = "passive"; 4961 }; 4962 4963 cpu4_bottom_crit: cpu_crit { 4964 temperature = <110000>; 4965 hysteresis = <1000>; 4966 type = "critical"; 4967 }; 4968 }; 4969 4970 cooling-maps { 4971 map0 { 4972 trip = <&cpu4_bottom_alert0>; 4973 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4974 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4975 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4976 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4977 }; 4978 map1 { 4979 trip = <&cpu4_bottom_alert1>; 4980 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4981 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4982 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4983 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4984 }; 4985 }; 4986 }; 4987 4988 cpu5-bottom-thermal { 4989 polling-delay-passive = <250>; 4990 polling-delay = <1000>; 4991 4992 thermal-sensors = <&tsens0 12>; 4993 4994 trips { 4995 cpu5_bottom_alert0: trip-point0 { 4996 temperature = <90000>; 4997 hysteresis = <2000>; 4998 type = "passive"; 4999 }; 5000 5001 cpu5_bottom_alert1: trip-point1 { 5002 temperature = <95000>; 5003 hysteresis = <2000>; 5004 type = "passive"; 5005 }; 5006 5007 cpu5_bottom_crit: cpu_crit { 5008 temperature = <110000>; 5009 hysteresis = <1000>; 5010 type = "critical"; 5011 }; 5012 }; 5013 5014 cooling-maps { 5015 map0 { 5016 trip = <&cpu5_bottom_alert0>; 5017 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5018 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5019 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5020 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5021 }; 5022 map1 { 5023 trip = <&cpu5_bottom_alert1>; 5024 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5025 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5026 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5027 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5028 }; 5029 }; 5030 }; 5031 5032 cpu6-bottom-thermal { 5033 polling-delay-passive = <250>; 5034 polling-delay = <1000>; 5035 5036 thermal-sensors = <&tsens0 13>; 5037 5038 trips { 5039 cpu6_bottom_alert0: trip-point0 { 5040 temperature = <90000>; 5041 hysteresis = <2000>; 5042 type = "passive"; 5043 }; 5044 5045 cpu6_bottom_alert1: trip-point1 { 5046 temperature = <95000>; 5047 hysteresis = <2000>; 5048 type = "passive"; 5049 }; 5050 5051 cpu6_bottom_crit: cpu_crit { 5052 temperature = <110000>; 5053 hysteresis = <1000>; 5054 type = "critical"; 5055 }; 5056 }; 5057 5058 cooling-maps { 5059 map0 { 5060 trip = <&cpu6_bottom_alert0>; 5061 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5062 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5063 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5064 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5065 }; 5066 map1 { 5067 trip = <&cpu6_bottom_alert1>; 5068 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5069 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5070 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5071 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5072 }; 5073 }; 5074 }; 5075 5076 cpu7-bottom-thermal { 5077 polling-delay-passive = <250>; 5078 polling-delay = <1000>; 5079 5080 thermal-sensors = <&tsens0 14>; 5081 5082 trips { 5083 cpu7_bottom_alert0: trip-point0 { 5084 temperature = <90000>; 5085 hysteresis = <2000>; 5086 type = "passive"; 5087 }; 5088 5089 cpu7_bottom_alert1: trip-point1 { 5090 temperature = <95000>; 5091 hysteresis = <2000>; 5092 type = "passive"; 5093 }; 5094 5095 cpu7_bottom_crit: cpu_crit { 5096 temperature = <110000>; 5097 hysteresis = <1000>; 5098 type = "critical"; 5099 }; 5100 }; 5101 5102 cooling-maps { 5103 map0 { 5104 trip = <&cpu7_bottom_alert0>; 5105 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5106 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5107 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5108 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5109 }; 5110 map1 { 5111 trip = <&cpu7_bottom_alert1>; 5112 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5113 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5114 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5115 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5116 }; 5117 }; 5118 }; 5119 5120 aoss0-thermal { 5121 polling-delay-passive = <250>; 5122 polling-delay = <1000>; 5123 5124 thermal-sensors = <&tsens0 0>; 5125 5126 trips { 5127 aoss0_alert0: trip-point0 { 5128 temperature = <90000>; 5129 hysteresis = <2000>; 5130 type = "hot"; 5131 }; 5132 }; 5133 }; 5134 5135 cluster0-thermal { 5136 polling-delay-passive = <250>; 5137 polling-delay = <1000>; 5138 5139 thermal-sensors = <&tsens0 5>; 5140 5141 trips { 5142 cluster0_alert0: trip-point0 { 5143 temperature = <90000>; 5144 hysteresis = <2000>; 5145 type = "hot"; 5146 }; 5147 cluster0_crit: cluster0_crit { 5148 temperature = <110000>; 5149 hysteresis = <2000>; 5150 type = "critical"; 5151 }; 5152 }; 5153 }; 5154 5155 cluster1-thermal { 5156 polling-delay-passive = <250>; 5157 polling-delay = <1000>; 5158 5159 thermal-sensors = <&tsens0 6>; 5160 5161 trips { 5162 cluster1_alert0: trip-point0 { 5163 temperature = <90000>; 5164 hysteresis = <2000>; 5165 type = "hot"; 5166 }; 5167 cluster1_crit: cluster1_crit { 5168 temperature = <110000>; 5169 hysteresis = <2000>; 5170 type = "critical"; 5171 }; 5172 }; 5173 }; 5174 5175 gpu-thermal-top { 5176 polling-delay-passive = <250>; 5177 polling-delay = <1000>; 5178 5179 thermal-sensors = <&tsens0 15>; 5180 5181 trips { 5182 gpu1_alert0: trip-point0 { 5183 temperature = <90000>; 5184 hysteresis = <2000>; 5185 type = "hot"; 5186 }; 5187 }; 5188 }; 5189 5190 aoss1-thermal { 5191 polling-delay-passive = <250>; 5192 polling-delay = <1000>; 5193 5194 thermal-sensors = <&tsens1 0>; 5195 5196 trips { 5197 aoss1_alert0: trip-point0 { 5198 temperature = <90000>; 5199 hysteresis = <2000>; 5200 type = "hot"; 5201 }; 5202 }; 5203 }; 5204 5205 wlan-thermal { 5206 polling-delay-passive = <250>; 5207 polling-delay = <1000>; 5208 5209 thermal-sensors = <&tsens1 1>; 5210 5211 trips { 5212 wlan_alert0: trip-point0 { 5213 temperature = <90000>; 5214 hysteresis = <2000>; 5215 type = "hot"; 5216 }; 5217 }; 5218 }; 5219 5220 video-thermal { 5221 polling-delay-passive = <250>; 5222 polling-delay = <1000>; 5223 5224 thermal-sensors = <&tsens1 2>; 5225 5226 trips { 5227 video_alert0: trip-point0 { 5228 temperature = <90000>; 5229 hysteresis = <2000>; 5230 type = "hot"; 5231 }; 5232 }; 5233 }; 5234 5235 mem-thermal { 5236 polling-delay-passive = <250>; 5237 polling-delay = <1000>; 5238 5239 thermal-sensors = <&tsens1 3>; 5240 5241 trips { 5242 mem_alert0: trip-point0 { 5243 temperature = <90000>; 5244 hysteresis = <2000>; 5245 type = "hot"; 5246 }; 5247 }; 5248 }; 5249 5250 q6-hvx-thermal { 5251 polling-delay-passive = <250>; 5252 polling-delay = <1000>; 5253 5254 thermal-sensors = <&tsens1 4>; 5255 5256 trips { 5257 q6_hvx_alert0: trip-point0 { 5258 temperature = <90000>; 5259 hysteresis = <2000>; 5260 type = "hot"; 5261 }; 5262 }; 5263 }; 5264 5265 camera-thermal { 5266 polling-delay-passive = <250>; 5267 polling-delay = <1000>; 5268 5269 thermal-sensors = <&tsens1 5>; 5270 5271 trips { 5272 camera_alert0: trip-point0 { 5273 temperature = <90000>; 5274 hysteresis = <2000>; 5275 type = "hot"; 5276 }; 5277 }; 5278 }; 5279 5280 compute-thermal { 5281 polling-delay-passive = <250>; 5282 polling-delay = <1000>; 5283 5284 thermal-sensors = <&tsens1 6>; 5285 5286 trips { 5287 compute_alert0: trip-point0 { 5288 temperature = <90000>; 5289 hysteresis = <2000>; 5290 type = "hot"; 5291 }; 5292 }; 5293 }; 5294 5295 npu-thermal { 5296 polling-delay-passive = <250>; 5297 polling-delay = <1000>; 5298 5299 thermal-sensors = <&tsens1 7>; 5300 5301 trips { 5302 npu_alert0: trip-point0 { 5303 temperature = <90000>; 5304 hysteresis = <2000>; 5305 type = "hot"; 5306 }; 5307 }; 5308 }; 5309 5310 gpu-thermal-bottom { 5311 polling-delay-passive = <250>; 5312 polling-delay = <1000>; 5313 5314 thermal-sensors = <&tsens1 8>; 5315 5316 trips { 5317 gpu2_alert0: trip-point0 { 5318 temperature = <90000>; 5319 hysteresis = <2000>; 5320 type = "hot"; 5321 }; 5322 }; 5323 }; 5324 }; 5325}; 5326