1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h> 12#include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sm8250.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/soc/qcom,apr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/sound/qcom,q6afe.h> 23#include <dt-bindings/thermal/thermal.h> 24#include <dt-bindings/clock/qcom,camcc-sm8250.h> 25#include <dt-bindings/clock/qcom,videocc-sm8250.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 aliases { 34 i2c0 = &i2c0; 35 i2c1 = &i2c1; 36 i2c2 = &i2c2; 37 i2c3 = &i2c3; 38 i2c4 = &i2c4; 39 i2c5 = &i2c5; 40 i2c6 = &i2c6; 41 i2c7 = &i2c7; 42 i2c8 = &i2c8; 43 i2c9 = &i2c9; 44 i2c10 = &i2c10; 45 i2c11 = &i2c11; 46 i2c12 = &i2c12; 47 i2c13 = &i2c13; 48 i2c14 = &i2c14; 49 i2c15 = &i2c15; 50 i2c16 = &i2c16; 51 i2c17 = &i2c17; 52 i2c18 = &i2c18; 53 i2c19 = &i2c19; 54 spi0 = &spi0; 55 spi1 = &spi1; 56 spi2 = &spi2; 57 spi3 = &spi3; 58 spi4 = &spi4; 59 spi5 = &spi5; 60 spi6 = &spi6; 61 spi7 = &spi7; 62 spi8 = &spi8; 63 spi9 = &spi9; 64 spi10 = &spi10; 65 spi11 = &spi11; 66 spi12 = &spi12; 67 spi13 = &spi13; 68 spi14 = &spi14; 69 spi15 = &spi15; 70 spi16 = &spi16; 71 spi17 = &spi17; 72 spi18 = &spi18; 73 spi19 = &spi19; 74 }; 75 76 chosen { }; 77 78 clocks { 79 xo_board: xo-board { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 clock-frequency = <38400000>; 83 clock-output-names = "xo_board"; 84 }; 85 86 sleep_clk: sleep-clk { 87 compatible = "fixed-clock"; 88 clock-frequency = <32768>; 89 #clock-cells = <0>; 90 }; 91 }; 92 93 cpus { 94 #address-cells = <2>; 95 #size-cells = <0>; 96 97 CPU0: cpu@0 { 98 device_type = "cpu"; 99 compatible = "qcom,kryo485"; 100 reg = <0x0 0x0>; 101 clocks = <&cpufreq_hw 0>; 102 enable-method = "psci"; 103 capacity-dmips-mhz = <448>; 104 dynamic-power-coefficient = <105>; 105 next-level-cache = <&L2_0>; 106 power-domains = <&CPU_PD0>; 107 power-domain-names = "psci"; 108 qcom,freq-domain = <&cpufreq_hw 0>; 109 operating-points-v2 = <&cpu0_opp_table>; 110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 111 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 112 #cooling-cells = <2>; 113 L2_0: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-size = <0x20000>; 117 cache-unified; 118 next-level-cache = <&L3_0>; 119 L3_0: l3-cache { 120 compatible = "cache"; 121 cache-level = <3>; 122 cache-size = <0x400000>; 123 cache-unified; 124 }; 125 }; 126 }; 127 128 CPU1: cpu@100 { 129 device_type = "cpu"; 130 compatible = "qcom,kryo485"; 131 reg = <0x0 0x100>; 132 clocks = <&cpufreq_hw 0>; 133 enable-method = "psci"; 134 capacity-dmips-mhz = <448>; 135 dynamic-power-coefficient = <105>; 136 next-level-cache = <&L2_100>; 137 power-domains = <&CPU_PD1>; 138 power-domain-names = "psci"; 139 qcom,freq-domain = <&cpufreq_hw 0>; 140 operating-points-v2 = <&cpu0_opp_table>; 141 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 142 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 143 #cooling-cells = <2>; 144 L2_100: l2-cache { 145 compatible = "cache"; 146 cache-level = <2>; 147 cache-size = <0x20000>; 148 cache-unified; 149 next-level-cache = <&L3_0>; 150 }; 151 }; 152 153 CPU2: cpu@200 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo485"; 156 reg = <0x0 0x200>; 157 clocks = <&cpufreq_hw 0>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <448>; 160 dynamic-power-coefficient = <105>; 161 next-level-cache = <&L2_200>; 162 power-domains = <&CPU_PD2>; 163 power-domain-names = "psci"; 164 qcom,freq-domain = <&cpufreq_hw 0>; 165 operating-points-v2 = <&cpu0_opp_table>; 166 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 167 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 168 #cooling-cells = <2>; 169 L2_200: l2-cache { 170 compatible = "cache"; 171 cache-level = <2>; 172 cache-size = <0x20000>; 173 cache-unified; 174 next-level-cache = <&L3_0>; 175 }; 176 }; 177 178 CPU3: cpu@300 { 179 device_type = "cpu"; 180 compatible = "qcom,kryo485"; 181 reg = <0x0 0x300>; 182 clocks = <&cpufreq_hw 0>; 183 enable-method = "psci"; 184 capacity-dmips-mhz = <448>; 185 dynamic-power-coefficient = <105>; 186 next-level-cache = <&L2_300>; 187 power-domains = <&CPU_PD3>; 188 power-domain-names = "psci"; 189 qcom,freq-domain = <&cpufreq_hw 0>; 190 operating-points-v2 = <&cpu0_opp_table>; 191 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 192 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 193 #cooling-cells = <2>; 194 L2_300: l2-cache { 195 compatible = "cache"; 196 cache-level = <2>; 197 cache-size = <0x20000>; 198 cache-unified; 199 next-level-cache = <&L3_0>; 200 }; 201 }; 202 203 CPU4: cpu@400 { 204 device_type = "cpu"; 205 compatible = "qcom,kryo485"; 206 reg = <0x0 0x400>; 207 clocks = <&cpufreq_hw 1>; 208 enable-method = "psci"; 209 capacity-dmips-mhz = <1024>; 210 dynamic-power-coefficient = <379>; 211 next-level-cache = <&L2_400>; 212 power-domains = <&CPU_PD4>; 213 power-domain-names = "psci"; 214 qcom,freq-domain = <&cpufreq_hw 1>; 215 operating-points-v2 = <&cpu4_opp_table>; 216 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 217 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 218 #cooling-cells = <2>; 219 L2_400: l2-cache { 220 compatible = "cache"; 221 cache-level = <2>; 222 cache-size = <0x40000>; 223 cache-unified; 224 next-level-cache = <&L3_0>; 225 }; 226 }; 227 228 CPU5: cpu@500 { 229 device_type = "cpu"; 230 compatible = "qcom,kryo485"; 231 reg = <0x0 0x500>; 232 clocks = <&cpufreq_hw 1>; 233 enable-method = "psci"; 234 capacity-dmips-mhz = <1024>; 235 dynamic-power-coefficient = <379>; 236 next-level-cache = <&L2_500>; 237 power-domains = <&CPU_PD5>; 238 power-domain-names = "psci"; 239 qcom,freq-domain = <&cpufreq_hw 1>; 240 operating-points-v2 = <&cpu4_opp_table>; 241 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 242 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 243 #cooling-cells = <2>; 244 L2_500: l2-cache { 245 compatible = "cache"; 246 cache-level = <2>; 247 cache-size = <0x40000>; 248 cache-unified; 249 next-level-cache = <&L3_0>; 250 }; 251 }; 252 253 CPU6: cpu@600 { 254 device_type = "cpu"; 255 compatible = "qcom,kryo485"; 256 reg = <0x0 0x600>; 257 clocks = <&cpufreq_hw 1>; 258 enable-method = "psci"; 259 capacity-dmips-mhz = <1024>; 260 dynamic-power-coefficient = <379>; 261 next-level-cache = <&L2_600>; 262 power-domains = <&CPU_PD6>; 263 power-domain-names = "psci"; 264 qcom,freq-domain = <&cpufreq_hw 1>; 265 operating-points-v2 = <&cpu4_opp_table>; 266 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 267 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 268 #cooling-cells = <2>; 269 L2_600: l2-cache { 270 compatible = "cache"; 271 cache-level = <2>; 272 cache-size = <0x40000>; 273 cache-unified; 274 next-level-cache = <&L3_0>; 275 }; 276 }; 277 278 CPU7: cpu@700 { 279 device_type = "cpu"; 280 compatible = "qcom,kryo485"; 281 reg = <0x0 0x700>; 282 clocks = <&cpufreq_hw 2>; 283 enable-method = "psci"; 284 capacity-dmips-mhz = <1024>; 285 dynamic-power-coefficient = <444>; 286 next-level-cache = <&L2_700>; 287 power-domains = <&CPU_PD7>; 288 power-domain-names = "psci"; 289 qcom,freq-domain = <&cpufreq_hw 2>; 290 operating-points-v2 = <&cpu7_opp_table>; 291 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 292 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 293 #cooling-cells = <2>; 294 L2_700: l2-cache { 295 compatible = "cache"; 296 cache-level = <2>; 297 cache-size = <0x80000>; 298 cache-unified; 299 next-level-cache = <&L3_0>; 300 }; 301 }; 302 303 cpu-map { 304 cluster0 { 305 core0 { 306 cpu = <&CPU0>; 307 }; 308 309 core1 { 310 cpu = <&CPU1>; 311 }; 312 313 core2 { 314 cpu = <&CPU2>; 315 }; 316 317 core3 { 318 cpu = <&CPU3>; 319 }; 320 321 core4 { 322 cpu = <&CPU4>; 323 }; 324 325 core5 { 326 cpu = <&CPU5>; 327 }; 328 329 core6 { 330 cpu = <&CPU6>; 331 }; 332 333 core7 { 334 cpu = <&CPU7>; 335 }; 336 }; 337 }; 338 339 idle-states { 340 entry-method = "psci"; 341 342 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 343 compatible = "arm,idle-state"; 344 idle-state-name = "silver-rail-power-collapse"; 345 arm,psci-suspend-param = <0x40000004>; 346 entry-latency-us = <360>; 347 exit-latency-us = <531>; 348 min-residency-us = <3934>; 349 local-timer-stop; 350 }; 351 352 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 353 compatible = "arm,idle-state"; 354 idle-state-name = "gold-rail-power-collapse"; 355 arm,psci-suspend-param = <0x40000004>; 356 entry-latency-us = <702>; 357 exit-latency-us = <1061>; 358 min-residency-us = <4488>; 359 local-timer-stop; 360 }; 361 }; 362 363 domain-idle-states { 364 CLUSTER_SLEEP_0: cluster-sleep-0 { 365 compatible = "domain-idle-state"; 366 arm,psci-suspend-param = <0x4100c244>; 367 entry-latency-us = <3264>; 368 exit-latency-us = <6562>; 369 min-residency-us = <9987>; 370 }; 371 }; 372 }; 373 374 cpu0_opp_table: opp-table-cpu0 { 375 compatible = "operating-points-v2"; 376 opp-shared; 377 378 cpu0_opp1: opp-300000000 { 379 opp-hz = /bits/ 64 <300000000>; 380 opp-peak-kBps = <800000 9600000>; 381 }; 382 383 cpu0_opp2: opp-403200000 { 384 opp-hz = /bits/ 64 <403200000>; 385 opp-peak-kBps = <800000 9600000>; 386 }; 387 388 cpu0_opp3: opp-518400000 { 389 opp-hz = /bits/ 64 <518400000>; 390 opp-peak-kBps = <800000 16588800>; 391 }; 392 393 cpu0_opp4: opp-614400000 { 394 opp-hz = /bits/ 64 <614400000>; 395 opp-peak-kBps = <800000 16588800>; 396 }; 397 398 cpu0_opp5: opp-691200000 { 399 opp-hz = /bits/ 64 <691200000>; 400 opp-peak-kBps = <800000 19660800>; 401 }; 402 403 cpu0_opp6: opp-787200000 { 404 opp-hz = /bits/ 64 <787200000>; 405 opp-peak-kBps = <1804000 19660800>; 406 }; 407 408 cpu0_opp7: opp-883200000 { 409 opp-hz = /bits/ 64 <883200000>; 410 opp-peak-kBps = <1804000 23347200>; 411 }; 412 413 cpu0_opp8: opp-979200000 { 414 opp-hz = /bits/ 64 <979200000>; 415 opp-peak-kBps = <1804000 26419200>; 416 }; 417 418 cpu0_opp9: opp-1075200000 { 419 opp-hz = /bits/ 64 <1075200000>; 420 opp-peak-kBps = <1804000 29491200>; 421 }; 422 423 cpu0_opp10: opp-1171200000 { 424 opp-hz = /bits/ 64 <1171200000>; 425 opp-peak-kBps = <1804000 32563200>; 426 }; 427 428 cpu0_opp11: opp-1248000000 { 429 opp-hz = /bits/ 64 <1248000000>; 430 opp-peak-kBps = <1804000 36249600>; 431 }; 432 433 cpu0_opp12: opp-1344000000 { 434 opp-hz = /bits/ 64 <1344000000>; 435 opp-peak-kBps = <2188000 36249600>; 436 }; 437 438 cpu0_opp13: opp-1420800000 { 439 opp-hz = /bits/ 64 <1420800000>; 440 opp-peak-kBps = <2188000 39321600>; 441 }; 442 443 cpu0_opp14: opp-1516800000 { 444 opp-hz = /bits/ 64 <1516800000>; 445 opp-peak-kBps = <3072000 42393600>; 446 }; 447 448 cpu0_opp15: opp-1612800000 { 449 opp-hz = /bits/ 64 <1612800000>; 450 opp-peak-kBps = <3072000 42393600>; 451 }; 452 453 cpu0_opp16: opp-1708800000 { 454 opp-hz = /bits/ 64 <1708800000>; 455 opp-peak-kBps = <4068000 42393600>; 456 }; 457 458 cpu0_opp17: opp-1804800000 { 459 opp-hz = /bits/ 64 <1804800000>; 460 opp-peak-kBps = <4068000 42393600>; 461 }; 462 }; 463 464 cpu4_opp_table: opp-table-cpu4 { 465 compatible = "operating-points-v2"; 466 opp-shared; 467 468 cpu4_opp1: opp-710400000 { 469 opp-hz = /bits/ 64 <710400000>; 470 opp-peak-kBps = <1804000 19660800>; 471 }; 472 473 cpu4_opp2: opp-825600000 { 474 opp-hz = /bits/ 64 <825600000>; 475 opp-peak-kBps = <2188000 23347200>; 476 }; 477 478 cpu4_opp3: opp-940800000 { 479 opp-hz = /bits/ 64 <940800000>; 480 opp-peak-kBps = <2188000 26419200>; 481 }; 482 483 cpu4_opp4: opp-1056000000 { 484 opp-hz = /bits/ 64 <1056000000>; 485 opp-peak-kBps = <3072000 26419200>; 486 }; 487 488 cpu4_opp5: opp-1171200000 { 489 opp-hz = /bits/ 64 <1171200000>; 490 opp-peak-kBps = <3072000 29491200>; 491 }; 492 493 cpu4_opp6: opp-1286400000 { 494 opp-hz = /bits/ 64 <1286400000>; 495 opp-peak-kBps = <4068000 29491200>; 496 }; 497 498 cpu4_opp7: opp-1382400000 { 499 opp-hz = /bits/ 64 <1382400000>; 500 opp-peak-kBps = <4068000 32563200>; 501 }; 502 503 cpu4_opp8: opp-1478400000 { 504 opp-hz = /bits/ 64 <1478400000>; 505 opp-peak-kBps = <4068000 32563200>; 506 }; 507 508 cpu4_opp9: opp-1574400000 { 509 opp-hz = /bits/ 64 <1574400000>; 510 opp-peak-kBps = <5412000 39321600>; 511 }; 512 513 cpu4_opp10: opp-1670400000 { 514 opp-hz = /bits/ 64 <1670400000>; 515 opp-peak-kBps = <5412000 42393600>; 516 }; 517 518 cpu4_opp11: opp-1766400000 { 519 opp-hz = /bits/ 64 <1766400000>; 520 opp-peak-kBps = <5412000 45465600>; 521 }; 522 523 cpu4_opp12: opp-1862400000 { 524 opp-hz = /bits/ 64 <1862400000>; 525 opp-peak-kBps = <6220000 45465600>; 526 }; 527 528 cpu4_opp13: opp-1958400000 { 529 opp-hz = /bits/ 64 <1958400000>; 530 opp-peak-kBps = <6220000 48537600>; 531 }; 532 533 cpu4_opp14: opp-2054400000 { 534 opp-hz = /bits/ 64 <2054400000>; 535 opp-peak-kBps = <7216000 48537600>; 536 }; 537 538 cpu4_opp15: opp-2150400000 { 539 opp-hz = /bits/ 64 <2150400000>; 540 opp-peak-kBps = <7216000 51609600>; 541 }; 542 543 cpu4_opp16: opp-2246400000 { 544 opp-hz = /bits/ 64 <2246400000>; 545 opp-peak-kBps = <7216000 51609600>; 546 }; 547 548 cpu4_opp17: opp-2342400000 { 549 opp-hz = /bits/ 64 <2342400000>; 550 opp-peak-kBps = <8368000 51609600>; 551 }; 552 553 cpu4_opp18: opp-2419200000 { 554 opp-hz = /bits/ 64 <2419200000>; 555 opp-peak-kBps = <8368000 51609600>; 556 }; 557 }; 558 559 cpu7_opp_table: opp-table-cpu7 { 560 compatible = "operating-points-v2"; 561 opp-shared; 562 563 cpu7_opp1: opp-844800000 { 564 opp-hz = /bits/ 64 <844800000>; 565 opp-peak-kBps = <2188000 19660800>; 566 }; 567 568 cpu7_opp2: opp-960000000 { 569 opp-hz = /bits/ 64 <960000000>; 570 opp-peak-kBps = <2188000 26419200>; 571 }; 572 573 cpu7_opp3: opp-1075200000 { 574 opp-hz = /bits/ 64 <1075200000>; 575 opp-peak-kBps = <3072000 26419200>; 576 }; 577 578 cpu7_opp4: opp-1190400000 { 579 opp-hz = /bits/ 64 <1190400000>; 580 opp-peak-kBps = <3072000 29491200>; 581 }; 582 583 cpu7_opp5: opp-1305600000 { 584 opp-hz = /bits/ 64 <1305600000>; 585 opp-peak-kBps = <4068000 32563200>; 586 }; 587 588 cpu7_opp6: opp-1401600000 { 589 opp-hz = /bits/ 64 <1401600000>; 590 opp-peak-kBps = <4068000 32563200>; 591 }; 592 593 cpu7_opp7: opp-1516800000 { 594 opp-hz = /bits/ 64 <1516800000>; 595 opp-peak-kBps = <4068000 36249600>; 596 }; 597 598 cpu7_opp8: opp-1632000000 { 599 opp-hz = /bits/ 64 <1632000000>; 600 opp-peak-kBps = <5412000 39321600>; 601 }; 602 603 cpu7_opp9: opp-1747200000 { 604 opp-hz = /bits/ 64 <1708800000>; 605 opp-peak-kBps = <5412000 42393600>; 606 }; 607 608 cpu7_opp10: opp-1862400000 { 609 opp-hz = /bits/ 64 <1862400000>; 610 opp-peak-kBps = <6220000 45465600>; 611 }; 612 613 cpu7_opp11: opp-1977600000 { 614 opp-hz = /bits/ 64 <1977600000>; 615 opp-peak-kBps = <6220000 48537600>; 616 }; 617 618 cpu7_opp12: opp-2073600000 { 619 opp-hz = /bits/ 64 <2073600000>; 620 opp-peak-kBps = <7216000 48537600>; 621 }; 622 623 cpu7_opp13: opp-2169600000 { 624 opp-hz = /bits/ 64 <2169600000>; 625 opp-peak-kBps = <7216000 51609600>; 626 }; 627 628 cpu7_opp14: opp-2265600000 { 629 opp-hz = /bits/ 64 <2265600000>; 630 opp-peak-kBps = <7216000 51609600>; 631 }; 632 633 cpu7_opp15: opp-2361600000 { 634 opp-hz = /bits/ 64 <2361600000>; 635 opp-peak-kBps = <8368000 51609600>; 636 }; 637 638 cpu7_opp16: opp-2457600000 { 639 opp-hz = /bits/ 64 <2457600000>; 640 opp-peak-kBps = <8368000 51609600>; 641 }; 642 643 cpu7_opp17: opp-2553600000 { 644 opp-hz = /bits/ 64 <2553600000>; 645 opp-peak-kBps = <8368000 51609600>; 646 }; 647 648 cpu7_opp18: opp-2649600000 { 649 opp-hz = /bits/ 64 <2649600000>; 650 opp-peak-kBps = <8368000 51609600>; 651 }; 652 653 cpu7_opp19: opp-2745600000 { 654 opp-hz = /bits/ 64 <2745600000>; 655 opp-peak-kBps = <8368000 51609600>; 656 }; 657 658 cpu7_opp20: opp-2841600000 { 659 opp-hz = /bits/ 64 <2841600000>; 660 opp-peak-kBps = <8368000 51609600>; 661 }; 662 }; 663 664 firmware { 665 scm: scm { 666 compatible = "qcom,scm-sm8250", "qcom,scm"; 667 #reset-cells = <1>; 668 }; 669 }; 670 671 memory@80000000 { 672 device_type = "memory"; 673 /* We expect the bootloader to fill in the size */ 674 reg = <0x0 0x80000000 0x0 0x0>; 675 }; 676 677 pmu { 678 compatible = "arm,armv8-pmuv3"; 679 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 680 }; 681 682 psci { 683 compatible = "arm,psci-1.0"; 684 method = "smc"; 685 686 CPU_PD0: power-domain-cpu0 { 687 #power-domain-cells = <0>; 688 power-domains = <&CLUSTER_PD>; 689 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 690 }; 691 692 CPU_PD1: power-domain-cpu1 { 693 #power-domain-cells = <0>; 694 power-domains = <&CLUSTER_PD>; 695 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 696 }; 697 698 CPU_PD2: power-domain-cpu2 { 699 #power-domain-cells = <0>; 700 power-domains = <&CLUSTER_PD>; 701 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 702 }; 703 704 CPU_PD3: power-domain-cpu3 { 705 #power-domain-cells = <0>; 706 power-domains = <&CLUSTER_PD>; 707 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 708 }; 709 710 CPU_PD4: power-domain-cpu4 { 711 #power-domain-cells = <0>; 712 power-domains = <&CLUSTER_PD>; 713 domain-idle-states = <&BIG_CPU_SLEEP_0>; 714 }; 715 716 CPU_PD5: power-domain-cpu5 { 717 #power-domain-cells = <0>; 718 power-domains = <&CLUSTER_PD>; 719 domain-idle-states = <&BIG_CPU_SLEEP_0>; 720 }; 721 722 CPU_PD6: power-domain-cpu6 { 723 #power-domain-cells = <0>; 724 power-domains = <&CLUSTER_PD>; 725 domain-idle-states = <&BIG_CPU_SLEEP_0>; 726 }; 727 728 CPU_PD7: power-domain-cpu7 { 729 #power-domain-cells = <0>; 730 power-domains = <&CLUSTER_PD>; 731 domain-idle-states = <&BIG_CPU_SLEEP_0>; 732 }; 733 734 CLUSTER_PD: power-domain-cpu-cluster0 { 735 #power-domain-cells = <0>; 736 domain-idle-states = <&CLUSTER_SLEEP_0>; 737 }; 738 }; 739 740 qup_opp_table: opp-table-qup { 741 compatible = "operating-points-v2"; 742 743 opp-50000000 { 744 opp-hz = /bits/ 64 <50000000>; 745 required-opps = <&rpmhpd_opp_min_svs>; 746 }; 747 748 opp-75000000 { 749 opp-hz = /bits/ 64 <75000000>; 750 required-opps = <&rpmhpd_opp_low_svs>; 751 }; 752 753 opp-120000000 { 754 opp-hz = /bits/ 64 <120000000>; 755 required-opps = <&rpmhpd_opp_svs>; 756 }; 757 }; 758 759 reserved-memory { 760 #address-cells = <2>; 761 #size-cells = <2>; 762 ranges; 763 764 hyp_mem: memory@80000000 { 765 reg = <0x0 0x80000000 0x0 0x600000>; 766 no-map; 767 }; 768 769 xbl_aop_mem: memory@80700000 { 770 reg = <0x0 0x80700000 0x0 0x160000>; 771 no-map; 772 }; 773 774 cmd_db: memory@80860000 { 775 compatible = "qcom,cmd-db"; 776 reg = <0x0 0x80860000 0x0 0x20000>; 777 no-map; 778 }; 779 780 smem_mem: memory@80900000 { 781 reg = <0x0 0x80900000 0x0 0x200000>; 782 no-map; 783 }; 784 785 removed_mem: memory@80b00000 { 786 reg = <0x0 0x80b00000 0x0 0x5300000>; 787 no-map; 788 }; 789 790 camera_mem: memory@86200000 { 791 reg = <0x0 0x86200000 0x0 0x500000>; 792 no-map; 793 }; 794 795 wlan_mem: memory@86700000 { 796 reg = <0x0 0x86700000 0x0 0x100000>; 797 no-map; 798 }; 799 800 ipa_fw_mem: memory@86800000 { 801 reg = <0x0 0x86800000 0x0 0x10000>; 802 no-map; 803 }; 804 805 ipa_gsi_mem: memory@86810000 { 806 reg = <0x0 0x86810000 0x0 0xa000>; 807 no-map; 808 }; 809 810 gpu_mem: memory@8681a000 { 811 reg = <0x0 0x8681a000 0x0 0x2000>; 812 no-map; 813 }; 814 815 npu_mem: memory@86900000 { 816 reg = <0x0 0x86900000 0x0 0x500000>; 817 no-map; 818 }; 819 820 video_mem: memory@86e00000 { 821 reg = <0x0 0x86e00000 0x0 0x500000>; 822 no-map; 823 }; 824 825 cvp_mem: memory@87300000 { 826 reg = <0x0 0x87300000 0x0 0x500000>; 827 no-map; 828 }; 829 830 cdsp_mem: memory@87800000 { 831 reg = <0x0 0x87800000 0x0 0x1400000>; 832 no-map; 833 }; 834 835 slpi_mem: memory@88c00000 { 836 reg = <0x0 0x88c00000 0x0 0x1500000>; 837 no-map; 838 }; 839 840 adsp_mem: memory@8a100000 { 841 reg = <0x0 0x8a100000 0x0 0x1d00000>; 842 no-map; 843 }; 844 845 spss_mem: memory@8be00000 { 846 reg = <0x0 0x8be00000 0x0 0x100000>; 847 no-map; 848 }; 849 850 cdsp_secure_heap: memory@8bf00000 { 851 reg = <0x0 0x8bf00000 0x0 0x4600000>; 852 no-map; 853 }; 854 }; 855 856 smem { 857 compatible = "qcom,smem"; 858 memory-region = <&smem_mem>; 859 hwlocks = <&tcsr_mutex 3>; 860 }; 861 862 smp2p-adsp { 863 compatible = "qcom,smp2p"; 864 qcom,smem = <443>, <429>; 865 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 866 IPCC_MPROC_SIGNAL_SMP2P 867 IRQ_TYPE_EDGE_RISING>; 868 mboxes = <&ipcc IPCC_CLIENT_LPASS 869 IPCC_MPROC_SIGNAL_SMP2P>; 870 871 qcom,local-pid = <0>; 872 qcom,remote-pid = <2>; 873 874 smp2p_adsp_out: master-kernel { 875 qcom,entry-name = "master-kernel"; 876 #qcom,smem-state-cells = <1>; 877 }; 878 879 smp2p_adsp_in: slave-kernel { 880 qcom,entry-name = "slave-kernel"; 881 interrupt-controller; 882 #interrupt-cells = <2>; 883 }; 884 }; 885 886 smp2p-cdsp { 887 compatible = "qcom,smp2p"; 888 qcom,smem = <94>, <432>; 889 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 890 IPCC_MPROC_SIGNAL_SMP2P 891 IRQ_TYPE_EDGE_RISING>; 892 mboxes = <&ipcc IPCC_CLIENT_CDSP 893 IPCC_MPROC_SIGNAL_SMP2P>; 894 895 qcom,local-pid = <0>; 896 qcom,remote-pid = <5>; 897 898 smp2p_cdsp_out: master-kernel { 899 qcom,entry-name = "master-kernel"; 900 #qcom,smem-state-cells = <1>; 901 }; 902 903 smp2p_cdsp_in: slave-kernel { 904 qcom,entry-name = "slave-kernel"; 905 interrupt-controller; 906 #interrupt-cells = <2>; 907 }; 908 }; 909 910 smp2p-slpi { 911 compatible = "qcom,smp2p"; 912 qcom,smem = <481>, <430>; 913 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 914 IPCC_MPROC_SIGNAL_SMP2P 915 IRQ_TYPE_EDGE_RISING>; 916 mboxes = <&ipcc IPCC_CLIENT_SLPI 917 IPCC_MPROC_SIGNAL_SMP2P>; 918 919 qcom,local-pid = <0>; 920 qcom,remote-pid = <3>; 921 922 smp2p_slpi_out: master-kernel { 923 qcom,entry-name = "master-kernel"; 924 #qcom,smem-state-cells = <1>; 925 }; 926 927 smp2p_slpi_in: slave-kernel { 928 qcom,entry-name = "slave-kernel"; 929 interrupt-controller; 930 #interrupt-cells = <2>; 931 }; 932 }; 933 934 soc: soc@0 { 935 #address-cells = <2>; 936 #size-cells = <2>; 937 ranges = <0 0 0 0 0x10 0>; 938 dma-ranges = <0 0 0 0 0x10 0>; 939 compatible = "simple-bus"; 940 941 gcc: clock-controller@100000 { 942 compatible = "qcom,gcc-sm8250"; 943 reg = <0x0 0x00100000 0x0 0x1f0000>; 944 #clock-cells = <1>; 945 #reset-cells = <1>; 946 #power-domain-cells = <1>; 947 clock-names = "bi_tcxo", 948 "bi_tcxo_ao", 949 "sleep_clk"; 950 clocks = <&rpmhcc RPMH_CXO_CLK>, 951 <&rpmhcc RPMH_CXO_CLK_A>, 952 <&sleep_clk>; 953 }; 954 955 ipcc: mailbox@408000 { 956 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 957 reg = <0 0x00408000 0 0x1000>; 958 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 959 interrupt-controller; 960 #interrupt-cells = <3>; 961 #mbox-cells = <2>; 962 }; 963 964 qfprom: efuse@784000 { 965 compatible = "qcom,sm8250-qfprom", "qcom,qfprom"; 966 reg = <0 0x00784000 0 0x8ff>; 967 #address-cells = <1>; 968 #size-cells = <1>; 969 970 gpu_speed_bin: gpu_speed_bin@19b { 971 reg = <0x19b 0x1>; 972 bits = <5 3>; 973 }; 974 }; 975 976 rng: rng@793000 { 977 compatible = "qcom,prng-ee"; 978 reg = <0 0x00793000 0 0x1000>; 979 clocks = <&gcc GCC_PRNG_AHB_CLK>; 980 clock-names = "core"; 981 }; 982 983 gpi_dma2: dma-controller@800000 { 984 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 985 reg = <0 0x00800000 0 0x70000>; 986 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 996 dma-channels = <10>; 997 dma-channel-mask = <0x3f>; 998 iommus = <&apps_smmu 0x76 0x0>; 999 #dma-cells = <3>; 1000 status = "disabled"; 1001 }; 1002 1003 qupv3_id_2: geniqup@8c0000 { 1004 compatible = "qcom,geni-se-qup"; 1005 reg = <0x0 0x008c0000 0x0 0x6000>; 1006 clock-names = "m-ahb", "s-ahb"; 1007 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1008 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1009 #address-cells = <2>; 1010 #size-cells = <2>; 1011 iommus = <&apps_smmu 0x63 0x0>; 1012 ranges; 1013 status = "disabled"; 1014 1015 i2c14: i2c@880000 { 1016 compatible = "qcom,geni-i2c"; 1017 reg = <0 0x00880000 0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&qup_i2c14_default>; 1022 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1023 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1024 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1025 dma-names = "tx", "rx"; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 status = "disabled"; 1029 }; 1030 1031 spi14: spi@880000 { 1032 compatible = "qcom,geni-spi"; 1033 reg = <0 0x00880000 0 0x4000>; 1034 clock-names = "se"; 1035 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1036 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1037 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1038 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1039 dma-names = "tx", "rx"; 1040 power-domains = <&rpmhpd RPMHPD_CX>; 1041 operating-points-v2 = <&qup_opp_table>; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 status = "disabled"; 1045 }; 1046 1047 i2c15: i2c@884000 { 1048 compatible = "qcom,geni-i2c"; 1049 reg = <0 0x00884000 0 0x4000>; 1050 clock-names = "se"; 1051 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1052 pinctrl-names = "default"; 1053 pinctrl-0 = <&qup_i2c15_default>; 1054 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1055 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1056 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1057 dma-names = "tx", "rx"; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 status = "disabled"; 1061 }; 1062 1063 spi15: spi@884000 { 1064 compatible = "qcom,geni-spi"; 1065 reg = <0 0x00884000 0 0x4000>; 1066 clock-names = "se"; 1067 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1068 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1069 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1070 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1071 dma-names = "tx", "rx"; 1072 power-domains = <&rpmhpd RPMHPD_CX>; 1073 operating-points-v2 = <&qup_opp_table>; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 status = "disabled"; 1077 }; 1078 1079 i2c16: i2c@888000 { 1080 compatible = "qcom,geni-i2c"; 1081 reg = <0 0x00888000 0 0x4000>; 1082 clock-names = "se"; 1083 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1084 pinctrl-names = "default"; 1085 pinctrl-0 = <&qup_i2c16_default>; 1086 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1087 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1088 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1089 dma-names = "tx", "rx"; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 status = "disabled"; 1093 }; 1094 1095 spi16: spi@888000 { 1096 compatible = "qcom,geni-spi"; 1097 reg = <0 0x00888000 0 0x4000>; 1098 clock-names = "se"; 1099 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1100 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1101 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1102 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1103 dma-names = "tx", "rx"; 1104 power-domains = <&rpmhpd RPMHPD_CX>; 1105 operating-points-v2 = <&qup_opp_table>; 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 status = "disabled"; 1109 }; 1110 1111 i2c17: i2c@88c000 { 1112 compatible = "qcom,geni-i2c"; 1113 reg = <0 0x0088c000 0 0x4000>; 1114 clock-names = "se"; 1115 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1116 pinctrl-names = "default"; 1117 pinctrl-0 = <&qup_i2c17_default>; 1118 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1119 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1120 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1121 dma-names = "tx", "rx"; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 status = "disabled"; 1125 }; 1126 1127 spi17: spi@88c000 { 1128 compatible = "qcom,geni-spi"; 1129 reg = <0 0x0088c000 0 0x4000>; 1130 clock-names = "se"; 1131 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1132 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1133 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1134 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1135 dma-names = "tx", "rx"; 1136 power-domains = <&rpmhpd RPMHPD_CX>; 1137 operating-points-v2 = <&qup_opp_table>; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 status = "disabled"; 1141 }; 1142 1143 uart17: serial@88c000 { 1144 compatible = "qcom,geni-uart"; 1145 reg = <0 0x0088c000 0 0x4000>; 1146 clock-names = "se"; 1147 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1148 pinctrl-names = "default"; 1149 pinctrl-0 = <&qup_uart17_default>; 1150 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1151 power-domains = <&rpmhpd RPMHPD_CX>; 1152 operating-points-v2 = <&qup_opp_table>; 1153 status = "disabled"; 1154 }; 1155 1156 i2c18: i2c@890000 { 1157 compatible = "qcom,geni-i2c"; 1158 reg = <0 0x00890000 0 0x4000>; 1159 clock-names = "se"; 1160 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&qup_i2c18_default>; 1163 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1164 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1165 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1166 dma-names = "tx", "rx"; 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 status = "disabled"; 1170 }; 1171 1172 spi18: spi@890000 { 1173 compatible = "qcom,geni-spi"; 1174 reg = <0 0x00890000 0 0x4000>; 1175 clock-names = "se"; 1176 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1177 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1178 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1179 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1180 dma-names = "tx", "rx"; 1181 power-domains = <&rpmhpd RPMHPD_CX>; 1182 operating-points-v2 = <&qup_opp_table>; 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 status = "disabled"; 1186 }; 1187 1188 uart18: serial@890000 { 1189 compatible = "qcom,geni-uart"; 1190 reg = <0 0x00890000 0 0x4000>; 1191 clock-names = "se"; 1192 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1193 pinctrl-names = "default"; 1194 pinctrl-0 = <&qup_uart18_default>; 1195 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1196 power-domains = <&rpmhpd RPMHPD_CX>; 1197 operating-points-v2 = <&qup_opp_table>; 1198 status = "disabled"; 1199 }; 1200 1201 i2c19: i2c@894000 { 1202 compatible = "qcom,geni-i2c"; 1203 reg = <0 0x00894000 0 0x4000>; 1204 clock-names = "se"; 1205 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1206 pinctrl-names = "default"; 1207 pinctrl-0 = <&qup_i2c19_default>; 1208 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1209 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1210 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1211 dma-names = "tx", "rx"; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 status = "disabled"; 1215 }; 1216 1217 spi19: spi@894000 { 1218 compatible = "qcom,geni-spi"; 1219 reg = <0 0x00894000 0 0x4000>; 1220 clock-names = "se"; 1221 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1222 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1223 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1224 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1225 dma-names = "tx", "rx"; 1226 power-domains = <&rpmhpd RPMHPD_CX>; 1227 operating-points-v2 = <&qup_opp_table>; 1228 #address-cells = <1>; 1229 #size-cells = <0>; 1230 status = "disabled"; 1231 }; 1232 }; 1233 1234 gpi_dma0: dma-controller@900000 { 1235 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1236 reg = <0 0x00900000 0 0x70000>; 1237 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1250 dma-channels = <15>; 1251 dma-channel-mask = <0x7ff>; 1252 iommus = <&apps_smmu 0x5b6 0x0>; 1253 #dma-cells = <3>; 1254 status = "disabled"; 1255 }; 1256 1257 qupv3_id_0: geniqup@9c0000 { 1258 compatible = "qcom,geni-se-qup"; 1259 reg = <0x0 0x009c0000 0x0 0x6000>; 1260 clock-names = "m-ahb", "s-ahb"; 1261 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1262 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1263 #address-cells = <2>; 1264 #size-cells = <2>; 1265 iommus = <&apps_smmu 0x5a3 0x0>; 1266 ranges; 1267 status = "disabled"; 1268 1269 i2c0: i2c@980000 { 1270 compatible = "qcom,geni-i2c"; 1271 reg = <0 0x00980000 0 0x4000>; 1272 clock-names = "se"; 1273 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1274 pinctrl-names = "default"; 1275 pinctrl-0 = <&qup_i2c0_default>; 1276 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1277 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1278 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1279 dma-names = "tx", "rx"; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 status = "disabled"; 1283 }; 1284 1285 spi0: spi@980000 { 1286 compatible = "qcom,geni-spi"; 1287 reg = <0 0x00980000 0 0x4000>; 1288 clock-names = "se"; 1289 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1290 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1291 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1292 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1293 dma-names = "tx", "rx"; 1294 power-domains = <&rpmhpd RPMHPD_CX>; 1295 operating-points-v2 = <&qup_opp_table>; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 status = "disabled"; 1299 }; 1300 1301 i2c1: i2c@984000 { 1302 compatible = "qcom,geni-i2c"; 1303 reg = <0 0x00984000 0 0x4000>; 1304 clock-names = "se"; 1305 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1306 pinctrl-names = "default"; 1307 pinctrl-0 = <&qup_i2c1_default>; 1308 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1309 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1310 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1311 dma-names = "tx", "rx"; 1312 #address-cells = <1>; 1313 #size-cells = <0>; 1314 status = "disabled"; 1315 }; 1316 1317 spi1: spi@984000 { 1318 compatible = "qcom,geni-spi"; 1319 reg = <0 0x00984000 0 0x4000>; 1320 clock-names = "se"; 1321 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1322 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1323 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1324 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1325 dma-names = "tx", "rx"; 1326 power-domains = <&rpmhpd RPMHPD_CX>; 1327 operating-points-v2 = <&qup_opp_table>; 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 status = "disabled"; 1331 }; 1332 1333 i2c2: i2c@988000 { 1334 compatible = "qcom,geni-i2c"; 1335 reg = <0 0x00988000 0 0x4000>; 1336 clock-names = "se"; 1337 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1338 pinctrl-names = "default"; 1339 pinctrl-0 = <&qup_i2c2_default>; 1340 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1341 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1342 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1343 dma-names = "tx", "rx"; 1344 #address-cells = <1>; 1345 #size-cells = <0>; 1346 status = "disabled"; 1347 }; 1348 1349 spi2: spi@988000 { 1350 compatible = "qcom,geni-spi"; 1351 reg = <0 0x00988000 0 0x4000>; 1352 clock-names = "se"; 1353 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1354 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1355 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1356 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1357 dma-names = "tx", "rx"; 1358 power-domains = <&rpmhpd RPMHPD_CX>; 1359 operating-points-v2 = <&qup_opp_table>; 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 status = "disabled"; 1363 }; 1364 1365 uart2: serial@988000 { 1366 compatible = "qcom,geni-debug-uart"; 1367 reg = <0 0x00988000 0 0x4000>; 1368 clock-names = "se"; 1369 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1370 pinctrl-names = "default"; 1371 pinctrl-0 = <&qup_uart2_default>; 1372 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1373 power-domains = <&rpmhpd RPMHPD_CX>; 1374 operating-points-v2 = <&qup_opp_table>; 1375 status = "disabled"; 1376 }; 1377 1378 i2c3: i2c@98c000 { 1379 compatible = "qcom,geni-i2c"; 1380 reg = <0 0x0098c000 0 0x4000>; 1381 clock-names = "se"; 1382 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&qup_i2c3_default>; 1385 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1386 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1387 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1388 dma-names = "tx", "rx"; 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 status = "disabled"; 1392 }; 1393 1394 spi3: spi@98c000 { 1395 compatible = "qcom,geni-spi"; 1396 reg = <0 0x0098c000 0 0x4000>; 1397 clock-names = "se"; 1398 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1399 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1400 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1401 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1402 dma-names = "tx", "rx"; 1403 power-domains = <&rpmhpd RPMHPD_CX>; 1404 operating-points-v2 = <&qup_opp_table>; 1405 #address-cells = <1>; 1406 #size-cells = <0>; 1407 status = "disabled"; 1408 }; 1409 1410 i2c4: i2c@990000 { 1411 compatible = "qcom,geni-i2c"; 1412 reg = <0 0x00990000 0 0x4000>; 1413 clock-names = "se"; 1414 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1415 pinctrl-names = "default"; 1416 pinctrl-0 = <&qup_i2c4_default>; 1417 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1418 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1419 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1420 dma-names = "tx", "rx"; 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 status = "disabled"; 1424 }; 1425 1426 spi4: spi@990000 { 1427 compatible = "qcom,geni-spi"; 1428 reg = <0 0x00990000 0 0x4000>; 1429 clock-names = "se"; 1430 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1431 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1432 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1433 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1434 dma-names = "tx", "rx"; 1435 power-domains = <&rpmhpd RPMHPD_CX>; 1436 operating-points-v2 = <&qup_opp_table>; 1437 #address-cells = <1>; 1438 #size-cells = <0>; 1439 status = "disabled"; 1440 }; 1441 1442 i2c5: i2c@994000 { 1443 compatible = "qcom,geni-i2c"; 1444 reg = <0 0x00994000 0 0x4000>; 1445 clock-names = "se"; 1446 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1447 pinctrl-names = "default"; 1448 pinctrl-0 = <&qup_i2c5_default>; 1449 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1450 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1451 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1452 dma-names = "tx", "rx"; 1453 #address-cells = <1>; 1454 #size-cells = <0>; 1455 status = "disabled"; 1456 }; 1457 1458 spi5: spi@994000 { 1459 compatible = "qcom,geni-spi"; 1460 reg = <0 0x00994000 0 0x4000>; 1461 clock-names = "se"; 1462 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1463 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1464 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1465 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1466 dma-names = "tx", "rx"; 1467 power-domains = <&rpmhpd RPMHPD_CX>; 1468 operating-points-v2 = <&qup_opp_table>; 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 status = "disabled"; 1472 }; 1473 1474 i2c6: i2c@998000 { 1475 compatible = "qcom,geni-i2c"; 1476 reg = <0 0x00998000 0 0x4000>; 1477 clock-names = "se"; 1478 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1479 pinctrl-names = "default"; 1480 pinctrl-0 = <&qup_i2c6_default>; 1481 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1482 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1483 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1484 dma-names = "tx", "rx"; 1485 #address-cells = <1>; 1486 #size-cells = <0>; 1487 status = "disabled"; 1488 }; 1489 1490 spi6: spi@998000 { 1491 compatible = "qcom,geni-spi"; 1492 reg = <0 0x00998000 0 0x4000>; 1493 clock-names = "se"; 1494 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1495 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1496 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1497 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1498 dma-names = "tx", "rx"; 1499 power-domains = <&rpmhpd RPMHPD_CX>; 1500 operating-points-v2 = <&qup_opp_table>; 1501 #address-cells = <1>; 1502 #size-cells = <0>; 1503 status = "disabled"; 1504 }; 1505 1506 uart6: serial@998000 { 1507 compatible = "qcom,geni-uart"; 1508 reg = <0 0x00998000 0 0x4000>; 1509 clock-names = "se"; 1510 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1511 pinctrl-names = "default"; 1512 pinctrl-0 = <&qup_uart6_default>; 1513 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1514 power-domains = <&rpmhpd RPMHPD_CX>; 1515 operating-points-v2 = <&qup_opp_table>; 1516 status = "disabled"; 1517 }; 1518 1519 i2c7: i2c@99c000 { 1520 compatible = "qcom,geni-i2c"; 1521 reg = <0 0x0099c000 0 0x4000>; 1522 clock-names = "se"; 1523 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1524 pinctrl-names = "default"; 1525 pinctrl-0 = <&qup_i2c7_default>; 1526 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1527 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1528 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1529 dma-names = "tx", "rx"; 1530 #address-cells = <1>; 1531 #size-cells = <0>; 1532 status = "disabled"; 1533 }; 1534 1535 spi7: spi@99c000 { 1536 compatible = "qcom,geni-spi"; 1537 reg = <0 0x0099c000 0 0x4000>; 1538 clock-names = "se"; 1539 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1540 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1541 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1542 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1543 dma-names = "tx", "rx"; 1544 power-domains = <&rpmhpd RPMHPD_CX>; 1545 operating-points-v2 = <&qup_opp_table>; 1546 #address-cells = <1>; 1547 #size-cells = <0>; 1548 status = "disabled"; 1549 }; 1550 }; 1551 1552 gpi_dma1: dma-controller@a00000 { 1553 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1554 reg = <0 0x00a00000 0 0x70000>; 1555 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1565 dma-channels = <10>; 1566 dma-channel-mask = <0x3f>; 1567 iommus = <&apps_smmu 0x56 0x0>; 1568 #dma-cells = <3>; 1569 status = "disabled"; 1570 }; 1571 1572 qupv3_id_1: geniqup@ac0000 { 1573 compatible = "qcom,geni-se-qup"; 1574 reg = <0x0 0x00ac0000 0x0 0x6000>; 1575 clock-names = "m-ahb", "s-ahb"; 1576 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1577 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1578 #address-cells = <2>; 1579 #size-cells = <2>; 1580 iommus = <&apps_smmu 0x43 0x0>; 1581 ranges; 1582 status = "disabled"; 1583 1584 i2c8: i2c@a80000 { 1585 compatible = "qcom,geni-i2c"; 1586 reg = <0 0x00a80000 0 0x4000>; 1587 clock-names = "se"; 1588 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1589 pinctrl-names = "default"; 1590 pinctrl-0 = <&qup_i2c8_default>; 1591 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1592 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1593 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1594 dma-names = "tx", "rx"; 1595 #address-cells = <1>; 1596 #size-cells = <0>; 1597 status = "disabled"; 1598 }; 1599 1600 spi8: spi@a80000 { 1601 compatible = "qcom,geni-spi"; 1602 reg = <0 0x00a80000 0 0x4000>; 1603 clock-names = "se"; 1604 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1605 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1606 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1607 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1608 dma-names = "tx", "rx"; 1609 power-domains = <&rpmhpd RPMHPD_CX>; 1610 operating-points-v2 = <&qup_opp_table>; 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 status = "disabled"; 1614 }; 1615 1616 i2c9: i2c@a84000 { 1617 compatible = "qcom,geni-i2c"; 1618 reg = <0 0x00a84000 0 0x4000>; 1619 clock-names = "se"; 1620 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1621 pinctrl-names = "default"; 1622 pinctrl-0 = <&qup_i2c9_default>; 1623 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1624 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1625 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1626 dma-names = "tx", "rx"; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 status = "disabled"; 1630 }; 1631 1632 spi9: spi@a84000 { 1633 compatible = "qcom,geni-spi"; 1634 reg = <0 0x00a84000 0 0x4000>; 1635 clock-names = "se"; 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1637 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1638 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1639 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1640 dma-names = "tx", "rx"; 1641 power-domains = <&rpmhpd RPMHPD_CX>; 1642 operating-points-v2 = <&qup_opp_table>; 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 status = "disabled"; 1646 }; 1647 1648 i2c10: i2c@a88000 { 1649 compatible = "qcom,geni-i2c"; 1650 reg = <0 0x00a88000 0 0x4000>; 1651 clock-names = "se"; 1652 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1653 pinctrl-names = "default"; 1654 pinctrl-0 = <&qup_i2c10_default>; 1655 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1656 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1657 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1658 dma-names = "tx", "rx"; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 status = "disabled"; 1662 }; 1663 1664 spi10: spi@a88000 { 1665 compatible = "qcom,geni-spi"; 1666 reg = <0 0x00a88000 0 0x4000>; 1667 clock-names = "se"; 1668 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1669 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1670 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1671 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1672 dma-names = "tx", "rx"; 1673 power-domains = <&rpmhpd RPMHPD_CX>; 1674 operating-points-v2 = <&qup_opp_table>; 1675 #address-cells = <1>; 1676 #size-cells = <0>; 1677 status = "disabled"; 1678 }; 1679 1680 i2c11: i2c@a8c000 { 1681 compatible = "qcom,geni-i2c"; 1682 reg = <0 0x00a8c000 0 0x4000>; 1683 clock-names = "se"; 1684 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1685 pinctrl-names = "default"; 1686 pinctrl-0 = <&qup_i2c11_default>; 1687 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1688 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1689 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1690 dma-names = "tx", "rx"; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 status = "disabled"; 1694 }; 1695 1696 spi11: spi@a8c000 { 1697 compatible = "qcom,geni-spi"; 1698 reg = <0 0x00a8c000 0 0x4000>; 1699 clock-names = "se"; 1700 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1701 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1702 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1703 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1704 dma-names = "tx", "rx"; 1705 power-domains = <&rpmhpd RPMHPD_CX>; 1706 operating-points-v2 = <&qup_opp_table>; 1707 #address-cells = <1>; 1708 #size-cells = <0>; 1709 status = "disabled"; 1710 }; 1711 1712 i2c12: i2c@a90000 { 1713 compatible = "qcom,geni-i2c"; 1714 reg = <0 0x00a90000 0 0x4000>; 1715 clock-names = "se"; 1716 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1717 pinctrl-names = "default"; 1718 pinctrl-0 = <&qup_i2c12_default>; 1719 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1720 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1721 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1722 dma-names = "tx", "rx"; 1723 #address-cells = <1>; 1724 #size-cells = <0>; 1725 status = "disabled"; 1726 }; 1727 1728 spi12: spi@a90000 { 1729 compatible = "qcom,geni-spi"; 1730 reg = <0 0x00a90000 0 0x4000>; 1731 clock-names = "se"; 1732 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1733 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1734 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1735 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1736 dma-names = "tx", "rx"; 1737 power-domains = <&rpmhpd RPMHPD_CX>; 1738 operating-points-v2 = <&qup_opp_table>; 1739 #address-cells = <1>; 1740 #size-cells = <0>; 1741 status = "disabled"; 1742 }; 1743 1744 uart12: serial@a90000 { 1745 compatible = "qcom,geni-debug-uart"; 1746 reg = <0x0 0x00a90000 0x0 0x4000>; 1747 clock-names = "se"; 1748 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1749 pinctrl-names = "default"; 1750 pinctrl-0 = <&qup_uart12_default>; 1751 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1752 power-domains = <&rpmhpd RPMHPD_CX>; 1753 operating-points-v2 = <&qup_opp_table>; 1754 status = "disabled"; 1755 }; 1756 1757 i2c13: i2c@a94000 { 1758 compatible = "qcom,geni-i2c"; 1759 reg = <0 0x00a94000 0 0x4000>; 1760 clock-names = "se"; 1761 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1762 pinctrl-names = "default"; 1763 pinctrl-0 = <&qup_i2c13_default>; 1764 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1765 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1766 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1767 dma-names = "tx", "rx"; 1768 #address-cells = <1>; 1769 #size-cells = <0>; 1770 status = "disabled"; 1771 }; 1772 1773 spi13: spi@a94000 { 1774 compatible = "qcom,geni-spi"; 1775 reg = <0 0x00a94000 0 0x4000>; 1776 clock-names = "se"; 1777 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1778 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1779 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1780 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1781 dma-names = "tx", "rx"; 1782 power-domains = <&rpmhpd RPMHPD_CX>; 1783 operating-points-v2 = <&qup_opp_table>; 1784 #address-cells = <1>; 1785 #size-cells = <0>; 1786 status = "disabled"; 1787 }; 1788 }; 1789 1790 config_noc: interconnect@1500000 { 1791 compatible = "qcom,sm8250-config-noc"; 1792 reg = <0 0x01500000 0 0xa580>; 1793 #interconnect-cells = <2>; 1794 qcom,bcm-voters = <&apps_bcm_voter>; 1795 }; 1796 1797 system_noc: interconnect@1620000 { 1798 compatible = "qcom,sm8250-system-noc"; 1799 reg = <0 0x01620000 0 0x1c200>; 1800 #interconnect-cells = <2>; 1801 qcom,bcm-voters = <&apps_bcm_voter>; 1802 }; 1803 1804 mc_virt: interconnect@163d000 { 1805 compatible = "qcom,sm8250-mc-virt"; 1806 reg = <0 0x0163d000 0 0x1000>; 1807 #interconnect-cells = <2>; 1808 qcom,bcm-voters = <&apps_bcm_voter>; 1809 }; 1810 1811 aggre1_noc: interconnect@16e0000 { 1812 compatible = "qcom,sm8250-aggre1-noc"; 1813 reg = <0 0x016e0000 0 0x1f180>; 1814 #interconnect-cells = <2>; 1815 qcom,bcm-voters = <&apps_bcm_voter>; 1816 }; 1817 1818 aggre2_noc: interconnect@1700000 { 1819 compatible = "qcom,sm8250-aggre2-noc"; 1820 reg = <0 0x01700000 0 0x33000>; 1821 #interconnect-cells = <2>; 1822 qcom,bcm-voters = <&apps_bcm_voter>; 1823 }; 1824 1825 compute_noc: interconnect@1733000 { 1826 compatible = "qcom,sm8250-compute-noc"; 1827 reg = <0 0x01733000 0 0xa180>; 1828 #interconnect-cells = <2>; 1829 qcom,bcm-voters = <&apps_bcm_voter>; 1830 }; 1831 1832 mmss_noc: interconnect@1740000 { 1833 compatible = "qcom,sm8250-mmss-noc"; 1834 reg = <0 0x01740000 0 0x1f080>; 1835 #interconnect-cells = <2>; 1836 qcom,bcm-voters = <&apps_bcm_voter>; 1837 }; 1838 1839 pcie0: pci@1c00000 { 1840 compatible = "qcom,pcie-sm8250"; 1841 reg = <0 0x01c00000 0 0x3000>, 1842 <0 0x60000000 0 0xf1d>, 1843 <0 0x60000f20 0 0xa8>, 1844 <0 0x60001000 0 0x1000>, 1845 <0 0x60100000 0 0x100000>, 1846 <0 0x01c03000 0 0x1000>; 1847 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1848 device_type = "pci"; 1849 linux,pci-domain = <0>; 1850 bus-range = <0x00 0xff>; 1851 num-lanes = <1>; 1852 1853 #address-cells = <3>; 1854 #size-cells = <2>; 1855 1856 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1857 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1858 1859 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1867 interrupt-names = "msi0", "msi1", "msi2", "msi3", 1868 "msi4", "msi5", "msi6", "msi7"; 1869 #interrupt-cells = <1>; 1870 interrupt-map-mask = <0 0 0 0x7>; 1871 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1872 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1873 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1874 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1875 1876 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1877 <&gcc GCC_PCIE_0_AUX_CLK>, 1878 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1879 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1880 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1881 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1882 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1883 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1884 clock-names = "pipe", 1885 "aux", 1886 "cfg", 1887 "bus_master", 1888 "bus_slave", 1889 "slave_q2a", 1890 "tbu", 1891 "ddrss_sf_tbu"; 1892 1893 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1894 <0x100 &apps_smmu 0x1c01 0x1>; 1895 1896 resets = <&gcc GCC_PCIE_0_BCR>; 1897 reset-names = "pci"; 1898 1899 power-domains = <&gcc PCIE_0_GDSC>; 1900 1901 phys = <&pcie0_lane>; 1902 phy-names = "pciephy"; 1903 1904 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; 1905 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 1906 1907 pinctrl-names = "default"; 1908 pinctrl-0 = <&pcie0_default_state>; 1909 dma-coherent; 1910 1911 status = "disabled"; 1912 }; 1913 1914 pcie0_phy: phy@1c06000 { 1915 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1916 reg = <0 0x01c06000 0 0x1c0>; 1917 #address-cells = <2>; 1918 #size-cells = <2>; 1919 ranges; 1920 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1921 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1922 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1923 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1924 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1925 1926 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1927 reset-names = "phy"; 1928 1929 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1930 assigned-clock-rates = <100000000>; 1931 1932 status = "disabled"; 1933 1934 pcie0_lane: phy@1c06200 { 1935 reg = <0 0x01c06200 0 0x170>, /* tx */ 1936 <0 0x01c06400 0 0x200>, /* rx */ 1937 <0 0x01c06800 0 0x1f0>, /* pcs */ 1938 <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1939 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1940 clock-names = "pipe0"; 1941 1942 #phy-cells = <0>; 1943 1944 #clock-cells = <0>; 1945 clock-output-names = "pcie_0_pipe_clk"; 1946 }; 1947 }; 1948 1949 pcie1: pci@1c08000 { 1950 compatible = "qcom,pcie-sm8250"; 1951 reg = <0 0x01c08000 0 0x3000>, 1952 <0 0x40000000 0 0xf1d>, 1953 <0 0x40000f20 0 0xa8>, 1954 <0 0x40001000 0 0x1000>, 1955 <0 0x40100000 0 0x100000>, 1956 <0 0x01c0b000 0 0x1000>; 1957 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1958 device_type = "pci"; 1959 linux,pci-domain = <1>; 1960 bus-range = <0x00 0xff>; 1961 num-lanes = <2>; 1962 1963 #address-cells = <3>; 1964 #size-cells = <2>; 1965 1966 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1967 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1968 1969 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1970 interrupt-names = "msi"; 1971 #interrupt-cells = <1>; 1972 interrupt-map-mask = <0 0 0 0x7>; 1973 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1974 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1975 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1976 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1977 1978 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1979 <&gcc GCC_PCIE_1_AUX_CLK>, 1980 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1981 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1982 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1983 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1984 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1985 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1986 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1987 clock-names = "pipe", 1988 "aux", 1989 "cfg", 1990 "bus_master", 1991 "bus_slave", 1992 "slave_q2a", 1993 "ref", 1994 "tbu", 1995 "ddrss_sf_tbu"; 1996 1997 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1998 assigned-clock-rates = <19200000>; 1999 2000 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2001 <0x100 &apps_smmu 0x1c81 0x1>; 2002 2003 resets = <&gcc GCC_PCIE_1_BCR>; 2004 reset-names = "pci"; 2005 2006 power-domains = <&gcc PCIE_1_GDSC>; 2007 2008 phys = <&pcie1_lane>; 2009 phy-names = "pciephy"; 2010 2011 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; 2012 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; 2013 2014 pinctrl-names = "default"; 2015 pinctrl-0 = <&pcie1_default_state>; 2016 dma-coherent; 2017 2018 status = "disabled"; 2019 }; 2020 2021 pcie1_phy: phy@1c0e000 { 2022 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2023 reg = <0 0x01c0e000 0 0x1c0>; 2024 #address-cells = <2>; 2025 #size-cells = <2>; 2026 ranges; 2027 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2028 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2029 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 2030 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2031 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2032 2033 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2034 reset-names = "phy"; 2035 2036 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2037 assigned-clock-rates = <100000000>; 2038 2039 status = "disabled"; 2040 2041 pcie1_lane: phy@1c0e200 { 2042 reg = <0 0x01c0e200 0 0x170>, /* tx0 */ 2043 <0 0x01c0e400 0 0x200>, /* rx0 */ 2044 <0 0x01c0ea00 0 0x1f0>, /* pcs */ 2045 <0 0x01c0e600 0 0x170>, /* tx1 */ 2046 <0 0x01c0e800 0 0x200>, /* rx1 */ 2047 <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2048 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2049 clock-names = "pipe0"; 2050 2051 #phy-cells = <0>; 2052 2053 #clock-cells = <0>; 2054 clock-output-names = "pcie_1_pipe_clk"; 2055 }; 2056 }; 2057 2058 pcie2: pci@1c10000 { 2059 compatible = "qcom,pcie-sm8250"; 2060 reg = <0 0x01c10000 0 0x3000>, 2061 <0 0x64000000 0 0xf1d>, 2062 <0 0x64000f20 0 0xa8>, 2063 <0 0x64001000 0 0x1000>, 2064 <0 0x64100000 0 0x100000>, 2065 <0 0x01c13000 0 0x1000>; 2066 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2067 device_type = "pci"; 2068 linux,pci-domain = <2>; 2069 bus-range = <0x00 0xff>; 2070 num-lanes = <2>; 2071 2072 #address-cells = <3>; 2073 #size-cells = <2>; 2074 2075 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>, 2076 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 2077 2078 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2079 interrupt-names = "msi"; 2080 #interrupt-cells = <1>; 2081 interrupt-map-mask = <0 0 0 0x7>; 2082 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2083 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2084 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2085 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2086 2087 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2088 <&gcc GCC_PCIE_2_AUX_CLK>, 2089 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2090 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2091 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2092 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2093 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2094 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2095 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2096 clock-names = "pipe", 2097 "aux", 2098 "cfg", 2099 "bus_master", 2100 "bus_slave", 2101 "slave_q2a", 2102 "ref", 2103 "tbu", 2104 "ddrss_sf_tbu"; 2105 2106 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2107 assigned-clock-rates = <19200000>; 2108 2109 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2110 <0x100 &apps_smmu 0x1d01 0x1>; 2111 2112 resets = <&gcc GCC_PCIE_2_BCR>; 2113 reset-names = "pci"; 2114 2115 power-domains = <&gcc PCIE_2_GDSC>; 2116 2117 phys = <&pcie2_lane>; 2118 phy-names = "pciephy"; 2119 2120 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; 2121 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 2122 2123 pinctrl-names = "default"; 2124 pinctrl-0 = <&pcie2_default_state>; 2125 dma-coherent; 2126 2127 status = "disabled"; 2128 }; 2129 2130 pcie2_phy: phy@1c16000 { 2131 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 2132 reg = <0 0x01c16000 0 0x1c0>; 2133 #address-cells = <2>; 2134 #size-cells = <2>; 2135 ranges; 2136 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2137 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2138 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2139 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2140 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2141 2142 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2143 reset-names = "phy"; 2144 2145 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2146 assigned-clock-rates = <100000000>; 2147 2148 status = "disabled"; 2149 2150 pcie2_lane: phy@1c16200 { 2151 reg = <0 0x01c16200 0 0x170>, /* tx0 */ 2152 <0 0x01c16400 0 0x200>, /* rx0 */ 2153 <0 0x01c16a00 0 0x1f0>, /* pcs */ 2154 <0 0x01c16600 0 0x170>, /* tx1 */ 2155 <0 0x01c16800 0 0x200>, /* rx1 */ 2156 <0 0x01c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2157 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 2158 clock-names = "pipe0"; 2159 2160 #phy-cells = <0>; 2161 2162 #clock-cells = <0>; 2163 clock-output-names = "pcie_2_pipe_clk"; 2164 }; 2165 }; 2166 2167 ufs_mem_hc: ufshc@1d84000 { 2168 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 2169 "jedec,ufs-2.0"; 2170 reg = <0 0x01d84000 0 0x3000>; 2171 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2172 phys = <&ufs_mem_phy_lanes>; 2173 phy-names = "ufsphy"; 2174 lanes-per-direction = <2>; 2175 #reset-cells = <1>; 2176 resets = <&gcc GCC_UFS_PHY_BCR>; 2177 reset-names = "rst"; 2178 2179 power-domains = <&gcc UFS_PHY_GDSC>; 2180 2181 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 2182 2183 clock-names = 2184 "core_clk", 2185 "bus_aggr_clk", 2186 "iface_clk", 2187 "core_clk_unipro", 2188 "ref_clk", 2189 "tx_lane0_sync_clk", 2190 "rx_lane0_sync_clk", 2191 "rx_lane1_sync_clk"; 2192 clocks = 2193 <&gcc GCC_UFS_PHY_AXI_CLK>, 2194 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2195 <&gcc GCC_UFS_PHY_AHB_CLK>, 2196 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2197 <&rpmhcc RPMH_CXO_CLK>, 2198 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2199 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2200 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2201 freq-table-hz = 2202 <37500000 300000000>, 2203 <0 0>, 2204 <0 0>, 2205 <37500000 300000000>, 2206 <0 0>, 2207 <0 0>, 2208 <0 0>, 2209 <0 0>; 2210 2211 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>, 2212 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 2213 interconnect-names = "ufs-ddr", "cpu-ufs"; 2214 2215 status = "disabled"; 2216 }; 2217 2218 ufs_mem_phy: phy@1d87000 { 2219 compatible = "qcom,sm8250-qmp-ufs-phy"; 2220 reg = <0 0x01d87000 0 0x1c0>; 2221 #address-cells = <2>; 2222 #size-cells = <2>; 2223 ranges; 2224 clock-names = "ref", 2225 "ref_aux"; 2226 clocks = <&rpmhcc RPMH_CXO_CLK>, 2227 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2228 2229 resets = <&ufs_mem_hc 0>; 2230 reset-names = "ufsphy"; 2231 status = "disabled"; 2232 2233 ufs_mem_phy_lanes: phy@1d87400 { 2234 reg = <0 0x01d87400 0 0x16c>, 2235 <0 0x01d87600 0 0x200>, 2236 <0 0x01d87c00 0 0x200>, 2237 <0 0x01d87800 0 0x16c>, 2238 <0 0x01d87a00 0 0x200>; 2239 #phy-cells = <0>; 2240 }; 2241 }; 2242 2243 cryptobam: dma-controller@1dc4000 { 2244 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2245 reg = <0 0x01dc4000 0 0x24000>; 2246 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2247 #dma-cells = <1>; 2248 qcom,ee = <0>; 2249 qcom,controlled-remotely; 2250 num-channels = <8>; 2251 qcom,num-ees = <2>; 2252 iommus = <&apps_smmu 0x592 0x0000>, 2253 <&apps_smmu 0x598 0x0000>, 2254 <&apps_smmu 0x599 0x0000>, 2255 <&apps_smmu 0x59f 0x0000>, 2256 <&apps_smmu 0x586 0x0011>, 2257 <&apps_smmu 0x596 0x0011>; 2258 }; 2259 2260 crypto: crypto@1dfa000 { 2261 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce"; 2262 reg = <0 0x01dfa000 0 0x6000>; 2263 dmas = <&cryptobam 4>, <&cryptobam 5>; 2264 dma-names = "rx", "tx"; 2265 iommus = <&apps_smmu 0x592 0x0000>, 2266 <&apps_smmu 0x598 0x0000>, 2267 <&apps_smmu 0x599 0x0000>, 2268 <&apps_smmu 0x59f 0x0000>, 2269 <&apps_smmu 0x586 0x0011>, 2270 <&apps_smmu 0x596 0x0011>; 2271 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; 2272 interconnect-names = "memory"; 2273 }; 2274 2275 tcsr_mutex: hwlock@1f40000 { 2276 compatible = "qcom,tcsr-mutex"; 2277 reg = <0x0 0x01f40000 0x0 0x40000>; 2278 #hwlock-cells = <1>; 2279 }; 2280 2281 wsamacro: codec@3240000 { 2282 compatible = "qcom,sm8250-lpass-wsa-macro"; 2283 reg = <0 0x03240000 0 0x1000>; 2284 clocks = <&audiocc LPASS_CDC_WSA_MCLK>, 2285 <&audiocc LPASS_CDC_WSA_NPL>, 2286 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2287 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2288 <&aoncc LPASS_CDC_VA_MCLK>, 2289 <&vamacro>; 2290 2291 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 2292 2293 #clock-cells = <0>; 2294 clock-output-names = "mclk"; 2295 #sound-dai-cells = <1>; 2296 2297 pinctrl-names = "default"; 2298 pinctrl-0 = <&wsa_swr_active>; 2299 2300 status = "disabled"; 2301 }; 2302 2303 swr0: soundwire-controller@3250000 { 2304 reg = <0 0x03250000 0 0x2000>; 2305 compatible = "qcom,soundwire-v1.5.1"; 2306 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 2307 clocks = <&wsamacro>; 2308 clock-names = "iface"; 2309 2310 qcom,din-ports = <2>; 2311 qcom,dout-ports = <6>; 2312 2313 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2314 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2315 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2316 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 2317 2318 #sound-dai-cells = <1>; 2319 #address-cells = <2>; 2320 #size-cells = <0>; 2321 2322 status = "disabled"; 2323 }; 2324 2325 audiocc: clock-controller@3300000 { 2326 compatible = "qcom,sm8250-lpass-audiocc"; 2327 reg = <0 0x03300000 0 0x30000>; 2328 #clock-cells = <1>; 2329 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2330 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2331 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2332 clock-names = "core", "audio", "bus"; 2333 }; 2334 2335 vamacro: codec@3370000 { 2336 compatible = "qcom,sm8250-lpass-va-macro"; 2337 reg = <0 0x03370000 0 0x1000>; 2338 clocks = <&aoncc LPASS_CDC_VA_MCLK>, 2339 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2340 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2341 2342 clock-names = "mclk", "macro", "dcodec"; 2343 2344 #clock-cells = <0>; 2345 clock-output-names = "fsgen"; 2346 #sound-dai-cells = <1>; 2347 }; 2348 2349 rxmacro: rxmacro@3200000 { 2350 pinctrl-names = "default"; 2351 pinctrl-0 = <&rx_swr_active>; 2352 compatible = "qcom,sm8250-lpass-rx-macro"; 2353 reg = <0 0x03200000 0 0x1000>; 2354 status = "disabled"; 2355 2356 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2357 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2358 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2359 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2360 <&vamacro>; 2361 2362 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2363 2364 #clock-cells = <0>; 2365 clock-output-names = "mclk"; 2366 #sound-dai-cells = <1>; 2367 }; 2368 2369 swr1: soundwire-controller@3210000 { 2370 reg = <0 0x03210000 0 0x2000>; 2371 compatible = "qcom,soundwire-v1.5.1"; 2372 status = "disabled"; 2373 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2374 clocks = <&rxmacro>; 2375 clock-names = "iface"; 2376 label = "RX"; 2377 qcom,din-ports = <0>; 2378 qcom,dout-ports = <5>; 2379 2380 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2381 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2382 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2383 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2384 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2385 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2386 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2387 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2388 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2389 2390 #sound-dai-cells = <1>; 2391 #address-cells = <2>; 2392 #size-cells = <0>; 2393 }; 2394 2395 txmacro: txmacro@3220000 { 2396 pinctrl-names = "default"; 2397 pinctrl-0 = <&tx_swr_active>; 2398 compatible = "qcom,sm8250-lpass-tx-macro"; 2399 reg = <0 0x03220000 0 0x1000>; 2400 status = "disabled"; 2401 2402 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2403 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2404 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2405 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2406 <&vamacro>; 2407 2408 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2409 2410 #clock-cells = <0>; 2411 clock-output-names = "mclk"; 2412 #sound-dai-cells = <1>; 2413 }; 2414 2415 /* tx macro */ 2416 swr2: soundwire-controller@3230000 { 2417 reg = <0 0x03230000 0 0x2000>; 2418 compatible = "qcom,soundwire-v1.5.1"; 2419 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 2420 interrupt-names = "core"; 2421 status = "disabled"; 2422 2423 clocks = <&txmacro>; 2424 clock-names = "iface"; 2425 label = "TX"; 2426 2427 qcom,din-ports = <5>; 2428 qcom,dout-ports = <0>; 2429 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>; 2430 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>; 2431 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>; 2432 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2433 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2434 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2435 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2436 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2437 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>; 2438 #sound-dai-cells = <1>; 2439 #address-cells = <2>; 2440 #size-cells = <0>; 2441 }; 2442 2443 aoncc: clock-controller@3380000 { 2444 compatible = "qcom,sm8250-lpass-aoncc"; 2445 reg = <0 0x03380000 0 0x40000>; 2446 #clock-cells = <1>; 2447 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2448 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2449 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2450 clock-names = "core", "audio", "bus"; 2451 }; 2452 2453 lpass_tlmm: pinctrl@33c0000 { 2454 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 2455 reg = <0 0x033c0000 0x0 0x20000>, 2456 <0 0x03550000 0x0 0x10000>; 2457 gpio-controller; 2458 #gpio-cells = <2>; 2459 gpio-ranges = <&lpass_tlmm 0 0 14>; 2460 2461 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2462 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2463 clock-names = "core", "audio"; 2464 2465 wsa_swr_active: wsa-swr-active-state { 2466 clk-pins { 2467 pins = "gpio10"; 2468 function = "wsa_swr_clk"; 2469 drive-strength = <2>; 2470 slew-rate = <1>; 2471 bias-disable; 2472 }; 2473 2474 data-pins { 2475 pins = "gpio11"; 2476 function = "wsa_swr_data"; 2477 drive-strength = <2>; 2478 slew-rate = <1>; 2479 bias-bus-hold; 2480 }; 2481 }; 2482 2483 wsa_swr_sleep: wsa-swr-sleep-state { 2484 clk-pins { 2485 pins = "gpio10"; 2486 function = "wsa_swr_clk"; 2487 drive-strength = <2>; 2488 bias-pull-down; 2489 }; 2490 2491 data-pins { 2492 pins = "gpio11"; 2493 function = "wsa_swr_data"; 2494 drive-strength = <2>; 2495 bias-pull-down; 2496 }; 2497 }; 2498 2499 dmic01_active: dmic01-active-state { 2500 clk-pins { 2501 pins = "gpio6"; 2502 function = "dmic1_clk"; 2503 drive-strength = <8>; 2504 output-high; 2505 }; 2506 data-pins { 2507 pins = "gpio7"; 2508 function = "dmic1_data"; 2509 drive-strength = <8>; 2510 }; 2511 }; 2512 2513 dmic01_sleep: dmic01-sleep-state { 2514 clk-pins { 2515 pins = "gpio6"; 2516 function = "dmic1_clk"; 2517 drive-strength = <2>; 2518 bias-disable; 2519 output-low; 2520 }; 2521 2522 data-pins { 2523 pins = "gpio7"; 2524 function = "dmic1_data"; 2525 drive-strength = <2>; 2526 bias-pull-down; 2527 }; 2528 }; 2529 2530 rx_swr_active: rx-swr-active-state { 2531 clk-pins { 2532 pins = "gpio3"; 2533 function = "swr_rx_clk"; 2534 drive-strength = <2>; 2535 slew-rate = <1>; 2536 bias-disable; 2537 }; 2538 2539 data-pins { 2540 pins = "gpio4", "gpio5"; 2541 function = "swr_rx_data"; 2542 drive-strength = <2>; 2543 slew-rate = <1>; 2544 bias-bus-hold; 2545 }; 2546 }; 2547 2548 tx_swr_active: tx-swr-active-state { 2549 clk-pins { 2550 pins = "gpio0"; 2551 function = "swr_tx_clk"; 2552 drive-strength = <2>; 2553 slew-rate = <1>; 2554 bias-disable; 2555 }; 2556 2557 data-pins { 2558 pins = "gpio1", "gpio2"; 2559 function = "swr_tx_data"; 2560 drive-strength = <2>; 2561 slew-rate = <1>; 2562 bias-bus-hold; 2563 }; 2564 }; 2565 2566 tx_swr_sleep: tx-swr-sleep-state { 2567 clk-pins { 2568 pins = "gpio0"; 2569 function = "swr_tx_clk"; 2570 drive-strength = <2>; 2571 bias-pull-down; 2572 }; 2573 2574 data1-pins { 2575 pins = "gpio1"; 2576 function = "swr_tx_data"; 2577 drive-strength = <2>; 2578 bias-bus-hold; 2579 }; 2580 2581 data2-pins { 2582 pins = "gpio2"; 2583 function = "swr_tx_data"; 2584 drive-strength = <2>; 2585 bias-pull-down; 2586 }; 2587 }; 2588 }; 2589 2590 gpu: gpu@3d00000 { 2591 compatible = "qcom,adreno-650.2", 2592 "qcom,adreno"; 2593 2594 reg = <0 0x03d00000 0 0x40000>; 2595 reg-names = "kgsl_3d0_reg_memory"; 2596 2597 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2598 2599 iommus = <&adreno_smmu 0 0x401>; 2600 2601 operating-points-v2 = <&gpu_opp_table>; 2602 2603 qcom,gmu = <&gmu>; 2604 2605 nvmem-cells = <&gpu_speed_bin>; 2606 nvmem-cell-names = "speed_bin"; 2607 2608 status = "disabled"; 2609 2610 zap-shader { 2611 memory-region = <&gpu_mem>; 2612 }; 2613 2614 gpu_opp_table: opp-table { 2615 compatible = "operating-points-v2"; 2616 2617 opp-670000000 { 2618 opp-hz = /bits/ 64 <670000000>; 2619 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2620 opp-supported-hw = <0xa>; 2621 }; 2622 2623 opp-587000000 { 2624 opp-hz = /bits/ 64 <587000000>; 2625 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2626 opp-supported-hw = <0xb>; 2627 }; 2628 2629 opp-525000000 { 2630 opp-hz = /bits/ 64 <525000000>; 2631 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2632 opp-supported-hw = <0xf>; 2633 }; 2634 2635 opp-490000000 { 2636 opp-hz = /bits/ 64 <490000000>; 2637 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2638 opp-supported-hw = <0xf>; 2639 }; 2640 2641 opp-441600000 { 2642 opp-hz = /bits/ 64 <441600000>; 2643 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2644 opp-supported-hw = <0xf>; 2645 }; 2646 2647 opp-400000000 { 2648 opp-hz = /bits/ 64 <400000000>; 2649 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2650 opp-supported-hw = <0xf>; 2651 }; 2652 2653 opp-305000000 { 2654 opp-hz = /bits/ 64 <305000000>; 2655 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2656 opp-supported-hw = <0xf>; 2657 }; 2658 }; 2659 }; 2660 2661 gmu: gmu@3d6a000 { 2662 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2663 2664 reg = <0 0x03d6a000 0 0x30000>, 2665 <0 0x3de0000 0 0x10000>, 2666 <0 0xb290000 0 0x10000>, 2667 <0 0xb490000 0 0x10000>; 2668 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 2669 2670 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2671 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2672 interrupt-names = "hfi", "gmu"; 2673 2674 clocks = <&gpucc GPU_CC_AHB_CLK>, 2675 <&gpucc GPU_CC_CX_GMU_CLK>, 2676 <&gpucc GPU_CC_CXO_CLK>, 2677 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2678 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2679 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2680 2681 power-domains = <&gpucc GPU_CX_GDSC>, 2682 <&gpucc GPU_GX_GDSC>; 2683 power-domain-names = "cx", "gx"; 2684 2685 iommus = <&adreno_smmu 5 0x400>; 2686 2687 operating-points-v2 = <&gmu_opp_table>; 2688 2689 status = "disabled"; 2690 2691 gmu_opp_table: opp-table { 2692 compatible = "operating-points-v2"; 2693 2694 opp-200000000 { 2695 opp-hz = /bits/ 64 <200000000>; 2696 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2697 }; 2698 }; 2699 }; 2700 2701 gpucc: clock-controller@3d90000 { 2702 compatible = "qcom,sm8250-gpucc"; 2703 reg = <0 0x03d90000 0 0x9000>; 2704 clocks = <&rpmhcc RPMH_CXO_CLK>, 2705 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2706 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2707 clock-names = "bi_tcxo", 2708 "gcc_gpu_gpll0_clk_src", 2709 "gcc_gpu_gpll0_div_clk_src"; 2710 #clock-cells = <1>; 2711 #reset-cells = <1>; 2712 #power-domain-cells = <1>; 2713 }; 2714 2715 adreno_smmu: iommu@3da0000 { 2716 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", 2717 "qcom,smmu-500", "arm,mmu-500"; 2718 reg = <0 0x03da0000 0 0x10000>; 2719 #iommu-cells = <2>; 2720 #global-interrupts = <2>; 2721 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2722 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2723 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2724 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2725 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2726 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2727 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2728 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2729 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2730 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 2731 clocks = <&gpucc GPU_CC_AHB_CLK>, 2732 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2733 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2734 clock-names = "ahb", "bus", "iface"; 2735 2736 power-domains = <&gpucc GPU_CX_GDSC>; 2737 dma-coherent; 2738 }; 2739 2740 slpi: remoteproc@5c00000 { 2741 compatible = "qcom,sm8250-slpi-pas"; 2742 reg = <0 0x05c00000 0 0x4000>; 2743 2744 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2745 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2746 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2747 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2748 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2749 interrupt-names = "wdog", "fatal", "ready", 2750 "handover", "stop-ack"; 2751 2752 clocks = <&rpmhcc RPMH_CXO_CLK>; 2753 clock-names = "xo"; 2754 2755 power-domains = <&rpmhpd RPMHPD_LCX>, 2756 <&rpmhpd RPMHPD_LMX>; 2757 power-domain-names = "lcx", "lmx"; 2758 2759 memory-region = <&slpi_mem>; 2760 2761 qcom,qmp = <&aoss_qmp>; 2762 2763 qcom,smem-states = <&smp2p_slpi_out 0>; 2764 qcom,smem-state-names = "stop"; 2765 2766 status = "disabled"; 2767 2768 glink-edge { 2769 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2770 IPCC_MPROC_SIGNAL_GLINK_QMP 2771 IRQ_TYPE_EDGE_RISING>; 2772 mboxes = <&ipcc IPCC_CLIENT_SLPI 2773 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2774 2775 label = "slpi"; 2776 qcom,remote-pid = <3>; 2777 2778 fastrpc { 2779 compatible = "qcom,fastrpc"; 2780 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2781 label = "sdsp"; 2782 qcom,non-secure-domain; 2783 #address-cells = <1>; 2784 #size-cells = <0>; 2785 2786 compute-cb@1 { 2787 compatible = "qcom,fastrpc-compute-cb"; 2788 reg = <1>; 2789 iommus = <&apps_smmu 0x0541 0x0>; 2790 }; 2791 2792 compute-cb@2 { 2793 compatible = "qcom,fastrpc-compute-cb"; 2794 reg = <2>; 2795 iommus = <&apps_smmu 0x0542 0x0>; 2796 }; 2797 2798 compute-cb@3 { 2799 compatible = "qcom,fastrpc-compute-cb"; 2800 reg = <3>; 2801 iommus = <&apps_smmu 0x0543 0x0>; 2802 /* note: shared-cb = <4> in downstream */ 2803 }; 2804 }; 2805 }; 2806 }; 2807 2808 stm@6002000 { 2809 compatible = "arm,coresight-stm", "arm,primecell"; 2810 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>; 2811 reg-names = "stm-base", "stm-stimulus-base"; 2812 2813 clocks = <&aoss_qmp>; 2814 clock-names = "apb_pclk"; 2815 2816 out-ports { 2817 port { 2818 stm_out: endpoint { 2819 remote-endpoint = <&funnel0_in7>; 2820 }; 2821 }; 2822 }; 2823 }; 2824 2825 tpda@6004000 { 2826 compatible = "qcom,coresight-tpda", "arm,primecell"; 2827 reg = <0 0x06004000 0 0x1000>; 2828 2829 clocks = <&aoss_qmp>; 2830 clock-names = "apb_pclk"; 2831 2832 out-ports { 2833 2834 port { 2835 tpda_out_funnel_qatb: endpoint { 2836 remote-endpoint = <&funnel_qatb_in_tpda>; 2837 }; 2838 }; 2839 }; 2840 2841 in-ports { 2842 #address-cells = <1>; 2843 #size-cells = <0>; 2844 2845 port@9 { 2846 reg = <9>; 2847 tpda_9_in_tpdm_mm: endpoint { 2848 remote-endpoint = <&tpdm_mm_out_tpda9>; 2849 }; 2850 }; 2851 2852 port@17 { 2853 reg = <23>; 2854 tpda_23_in_tpdm_prng: endpoint { 2855 remote-endpoint = <&tpdm_prng_out_tpda_23>; 2856 }; 2857 }; 2858 }; 2859 }; 2860 2861 funnel@6005000 { 2862 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2863 reg = <0 0x06005000 0 0x1000>; 2864 2865 clocks = <&aoss_qmp>; 2866 clock-names = "apb_pclk"; 2867 2868 out-ports { 2869 port { 2870 funnel_qatb_out_funnel_in0: endpoint { 2871 remote-endpoint = <&funnel_in0_in_funnel_qatb>; 2872 }; 2873 }; 2874 }; 2875 2876 in-ports { 2877 port { 2878 funnel_qatb_in_tpda: endpoint { 2879 remote-endpoint = <&tpda_out_funnel_qatb>; 2880 }; 2881 }; 2882 }; 2883 }; 2884 2885 funnel@6041000 { 2886 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2887 reg = <0 0x06041000 0 0x1000>; 2888 2889 clocks = <&aoss_qmp>; 2890 clock-names = "apb_pclk"; 2891 2892 out-ports { 2893 port { 2894 funnel_in0_out_funnel_merg: endpoint { 2895 remote-endpoint = <&funnel_merg_in_funnel_in0>; 2896 }; 2897 }; 2898 }; 2899 2900 in-ports { 2901 #address-cells = <1>; 2902 #size-cells = <0>; 2903 2904 port@6 { 2905 reg = <6>; 2906 funnel_in0_in_funnel_qatb: endpoint { 2907 remote-endpoint = <&funnel_qatb_out_funnel_in0>; 2908 }; 2909 }; 2910 2911 port@7 { 2912 reg = <7>; 2913 funnel0_in7: endpoint { 2914 remote-endpoint = <&stm_out>; 2915 }; 2916 }; 2917 }; 2918 }; 2919 2920 funnel@6042000 { 2921 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2922 reg = <0 0x06042000 0 0x1000>; 2923 2924 clocks = <&aoss_qmp>; 2925 clock-names = "apb_pclk"; 2926 2927 out-ports { 2928 port { 2929 funnel_in1_out_funnel_merg: endpoint { 2930 remote-endpoint = <&funnel_merg_in_funnel_in1>; 2931 }; 2932 }; 2933 }; 2934 2935 in-ports { 2936 #address-cells = <1>; 2937 #size-cells = <0>; 2938 2939 port@4 { 2940 reg = <4>; 2941 funnel_in1_in_funnel_apss_merg: endpoint { 2942 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>; 2943 }; 2944 }; 2945 }; 2946 }; 2947 2948 funnel@6045000 { 2949 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2950 reg = <0 0x06045000 0 0x1000>; 2951 2952 clocks = <&aoss_qmp>; 2953 clock-names = "apb_pclk"; 2954 2955 out-ports { 2956 port { 2957 funnel_merg_out_funnel_swao: endpoint { 2958 remote-endpoint = <&funnel_swao_in_funnel_merg>; 2959 }; 2960 }; 2961 }; 2962 2963 in-ports { 2964 #address-cells = <1>; 2965 #size-cells = <0>; 2966 2967 port@0 { 2968 reg = <0>; 2969 funnel_merg_in_funnel_in0: endpoint { 2970 remote-endpoint = <&funnel_in0_out_funnel_merg>; 2971 }; 2972 }; 2973 2974 port@1 { 2975 reg = <1>; 2976 funnel_merg_in_funnel_in1: endpoint { 2977 remote-endpoint = <&funnel_in1_out_funnel_merg>; 2978 }; 2979 }; 2980 }; 2981 }; 2982 2983 replicator@6046000 { 2984 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2985 reg = <0 0x06046000 0 0x1000>; 2986 2987 clocks = <&aoss_qmp>; 2988 clock-names = "apb_pclk"; 2989 2990 out-ports { 2991 port { 2992 replicator_out: endpoint { 2993 remote-endpoint = <&etr_in>; 2994 }; 2995 }; 2996 }; 2997 2998 in-ports { 2999 port { 3000 replicator_cx_in_swao_out: endpoint { 3001 remote-endpoint = <&replicator_swao_out_cx_in>; 3002 }; 3003 }; 3004 }; 3005 }; 3006 3007 etr@6048000 { 3008 compatible = "arm,coresight-tmc", "arm,primecell"; 3009 reg = <0 0x06048000 0 0x1000>; 3010 3011 clocks = <&aoss_qmp>; 3012 clock-names = "apb_pclk"; 3013 arm,scatter-gather; 3014 3015 in-ports { 3016 port { 3017 etr_in: endpoint { 3018 remote-endpoint = <&replicator_out>; 3019 }; 3020 }; 3021 }; 3022 }; 3023 3024 tpdm@684c000 { 3025 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3026 reg = <0 0x0684c000 0 0x1000>; 3027 3028 clocks = <&aoss_qmp>; 3029 clock-names = "apb_pclk"; 3030 3031 out-ports { 3032 port { 3033 tpdm_prng_out_tpda_23: endpoint { 3034 remote-endpoint = <&tpda_23_in_tpdm_prng>; 3035 }; 3036 }; 3037 }; 3038 }; 3039 3040 funnel@6b04000 { 3041 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3042 arm,primecell-periphid = <0x000bb908>; 3043 3044 reg = <0 0x06b04000 0 0x1000>; 3045 3046 clocks = <&aoss_qmp>; 3047 clock-names = "apb_pclk"; 3048 3049 out-ports { 3050 port { 3051 funnel_swao_out_etf: endpoint { 3052 remote-endpoint = <&etf_in_funnel_swao_out>; 3053 }; 3054 }; 3055 }; 3056 3057 in-ports { 3058 #address-cells = <1>; 3059 #size-cells = <0>; 3060 3061 port@7 { 3062 reg = <7>; 3063 funnel_swao_in_funnel_merg: endpoint { 3064 remote-endpoint = <&funnel_merg_out_funnel_swao>; 3065 }; 3066 }; 3067 }; 3068 }; 3069 3070 etf@6b05000 { 3071 compatible = "arm,coresight-tmc", "arm,primecell"; 3072 reg = <0 0x06b05000 0 0x1000>; 3073 3074 clocks = <&aoss_qmp>; 3075 clock-names = "apb_pclk"; 3076 3077 out-ports { 3078 port { 3079 etf_out: endpoint { 3080 remote-endpoint = <&replicator_in>; 3081 }; 3082 }; 3083 }; 3084 3085 in-ports { 3086 3087 port { 3088 etf_in_funnel_swao_out: endpoint { 3089 remote-endpoint = <&funnel_swao_out_etf>; 3090 }; 3091 }; 3092 }; 3093 }; 3094 3095 replicator@6b06000 { 3096 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3097 reg = <0 0x06b06000 0 0x1000>; 3098 3099 clocks = <&aoss_qmp>; 3100 clock-names = "apb_pclk"; 3101 3102 out-ports { 3103 port { 3104 replicator_swao_out_cx_in: endpoint { 3105 remote-endpoint = <&replicator_cx_in_swao_out>; 3106 }; 3107 }; 3108 }; 3109 3110 in-ports { 3111 port { 3112 replicator_in: endpoint { 3113 remote-endpoint = <&etf_out>; 3114 }; 3115 }; 3116 }; 3117 }; 3118 3119 tpdm@6c08000 { 3120 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3121 reg = <0 0x06c08000 0 0x1000>; 3122 3123 clocks = <&aoss_qmp>; 3124 clock-names = "apb_pclk"; 3125 3126 out-ports { 3127 port { 3128 tpdm_mm_out_funnel_dl_mm: endpoint { 3129 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>; 3130 }; 3131 }; 3132 }; 3133 }; 3134 3135 funnel@6c0b000 { 3136 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3137 reg = <0 0x06c0b000 0 0x1000>; 3138 3139 clocks = <&aoss_qmp>; 3140 clock-names = "apb_pclk"; 3141 3142 out-ports { 3143 port { 3144 funnel_dl_mm_out_funnel_dl_center: endpoint { 3145 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>; 3146 }; 3147 }; 3148 }; 3149 3150 in-ports { 3151 #address-cells = <1>; 3152 #size-cells = <0>; 3153 3154 port@3 { 3155 reg = <3>; 3156 funnel_dl_mm_in_tpdm_mm: endpoint { 3157 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>; 3158 }; 3159 }; 3160 }; 3161 }; 3162 3163 funnel@6c2d000 { 3164 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3165 reg = <0 0x06c2d000 0 0x1000>; 3166 3167 clocks = <&aoss_qmp>; 3168 clock-names = "apb_pclk"; 3169 3170 out-ports { 3171 port { 3172 tpdm_mm_out_tpda9: endpoint { 3173 remote-endpoint = <&tpda_9_in_tpdm_mm>; 3174 }; 3175 }; 3176 }; 3177 3178 in-ports { 3179 #address-cells = <1>; 3180 #size-cells = <0>; 3181 3182 port@2 { 3183 reg = <2>; 3184 funnel_dl_center_in_funnel_dl_mm: endpoint { 3185 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>; 3186 }; 3187 }; 3188 }; 3189 }; 3190 3191 etm@7040000 { 3192 compatible = "arm,coresight-etm4x", "arm,primecell"; 3193 reg = <0 0x07040000 0 0x1000>; 3194 3195 cpu = <&CPU0>; 3196 3197 clocks = <&aoss_qmp>; 3198 clock-names = "apb_pclk"; 3199 arm,coresight-loses-context-with-cpu; 3200 3201 out-ports { 3202 port { 3203 etm0_out: endpoint { 3204 remote-endpoint = <&apss_funnel_in0>; 3205 }; 3206 }; 3207 }; 3208 }; 3209 3210 etm@7140000 { 3211 compatible = "arm,coresight-etm4x", "arm,primecell"; 3212 reg = <0 0x07140000 0 0x1000>; 3213 3214 cpu = <&CPU1>; 3215 3216 clocks = <&aoss_qmp>; 3217 clock-names = "apb_pclk"; 3218 arm,coresight-loses-context-with-cpu; 3219 3220 out-ports { 3221 port { 3222 etm1_out: endpoint { 3223 remote-endpoint = <&apss_funnel_in1>; 3224 }; 3225 }; 3226 }; 3227 }; 3228 3229 etm@7240000 { 3230 compatible = "arm,coresight-etm4x", "arm,primecell"; 3231 reg = <0 0x07240000 0 0x1000>; 3232 3233 cpu = <&CPU2>; 3234 3235 clocks = <&aoss_qmp>; 3236 clock-names = "apb_pclk"; 3237 arm,coresight-loses-context-with-cpu; 3238 3239 out-ports { 3240 port { 3241 etm2_out: endpoint { 3242 remote-endpoint = <&apss_funnel_in2>; 3243 }; 3244 }; 3245 }; 3246 }; 3247 3248 etm@7340000 { 3249 compatible = "arm,coresight-etm4x", "arm,primecell"; 3250 reg = <0 0x07340000 0 0x1000>; 3251 3252 cpu = <&CPU3>; 3253 3254 clocks = <&aoss_qmp>; 3255 clock-names = "apb_pclk"; 3256 arm,coresight-loses-context-with-cpu; 3257 3258 out-ports { 3259 port { 3260 etm3_out: endpoint { 3261 remote-endpoint = <&apss_funnel_in3>; 3262 }; 3263 }; 3264 }; 3265 }; 3266 3267 etm@7440000 { 3268 compatible = "arm,coresight-etm4x", "arm,primecell"; 3269 reg = <0 0x07440000 0 0x1000>; 3270 3271 cpu = <&CPU4>; 3272 3273 clocks = <&aoss_qmp>; 3274 clock-names = "apb_pclk"; 3275 arm,coresight-loses-context-with-cpu; 3276 3277 out-ports { 3278 port { 3279 etm4_out: endpoint { 3280 remote-endpoint = <&apss_funnel_in4>; 3281 }; 3282 }; 3283 }; 3284 }; 3285 3286 etm@7540000 { 3287 compatible = "arm,coresight-etm4x", "arm,primecell"; 3288 reg = <0 0x07540000 0 0x1000>; 3289 3290 cpu = <&CPU5>; 3291 3292 clocks = <&aoss_qmp>; 3293 clock-names = "apb_pclk"; 3294 arm,coresight-loses-context-with-cpu; 3295 3296 out-ports { 3297 port { 3298 etm5_out: endpoint { 3299 remote-endpoint = <&apss_funnel_in5>; 3300 }; 3301 }; 3302 }; 3303 }; 3304 3305 etm@7640000 { 3306 compatible = "arm,coresight-etm4x", "arm,primecell"; 3307 reg = <0 0x07640000 0 0x1000>; 3308 3309 cpu = <&CPU6>; 3310 3311 clocks = <&aoss_qmp>; 3312 clock-names = "apb_pclk"; 3313 arm,coresight-loses-context-with-cpu; 3314 3315 out-ports { 3316 port { 3317 etm6_out: endpoint { 3318 remote-endpoint = <&apss_funnel_in6>; 3319 }; 3320 }; 3321 }; 3322 }; 3323 3324 etm@7740000 { 3325 compatible = "arm,coresight-etm4x", "arm,primecell"; 3326 reg = <0 0x07740000 0 0x1000>; 3327 3328 cpu = <&CPU7>; 3329 3330 clocks = <&aoss_qmp>; 3331 clock-names = "apb_pclk"; 3332 arm,coresight-loses-context-with-cpu; 3333 3334 out-ports { 3335 port { 3336 etm7_out: endpoint { 3337 remote-endpoint = <&apss_funnel_in7>; 3338 }; 3339 }; 3340 }; 3341 }; 3342 3343 funnel@7800000 { 3344 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3345 reg = <0 0x07800000 0 0x1000>; 3346 3347 clocks = <&aoss_qmp>; 3348 clock-names = "apb_pclk"; 3349 3350 out-ports { 3351 port { 3352 funnel_apss_out_funnel_apss_merg: endpoint { 3353 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>; 3354 }; 3355 }; 3356 }; 3357 3358 in-ports { 3359 #address-cells = <1>; 3360 #size-cells = <0>; 3361 3362 port@0 { 3363 reg = <0>; 3364 apss_funnel_in0: endpoint { 3365 remote-endpoint = <&etm0_out>; 3366 }; 3367 }; 3368 3369 port@1 { 3370 reg = <1>; 3371 apss_funnel_in1: endpoint { 3372 remote-endpoint = <&etm1_out>; 3373 }; 3374 }; 3375 3376 port@2 { 3377 reg = <2>; 3378 apss_funnel_in2: endpoint { 3379 remote-endpoint = <&etm2_out>; 3380 }; 3381 }; 3382 3383 port@3 { 3384 reg = <3>; 3385 apss_funnel_in3: endpoint { 3386 remote-endpoint = <&etm3_out>; 3387 }; 3388 }; 3389 3390 port@4 { 3391 reg = <4>; 3392 apss_funnel_in4: endpoint { 3393 remote-endpoint = <&etm4_out>; 3394 }; 3395 }; 3396 3397 port@5 { 3398 reg = <5>; 3399 apss_funnel_in5: endpoint { 3400 remote-endpoint = <&etm5_out>; 3401 }; 3402 }; 3403 3404 port@6 { 3405 reg = <6>; 3406 apss_funnel_in6: endpoint { 3407 remote-endpoint = <&etm6_out>; 3408 }; 3409 }; 3410 3411 port@7 { 3412 reg = <7>; 3413 apss_funnel_in7: endpoint { 3414 remote-endpoint = <&etm7_out>; 3415 }; 3416 }; 3417 }; 3418 }; 3419 3420 funnel@7810000 { 3421 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3422 reg = <0 0x07810000 0 0x1000>; 3423 3424 clocks = <&aoss_qmp>; 3425 clock-names = "apb_pclk"; 3426 3427 out-ports { 3428 port { 3429 funnel_apss_merg_out_funnel_in1: endpoint { 3430 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>; 3431 }; 3432 }; 3433 }; 3434 3435 in-ports { 3436 port { 3437 funnel_apss_merg_in_funnel_apss: endpoint { 3438 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>; 3439 }; 3440 }; 3441 }; 3442 }; 3443 3444 cdsp: remoteproc@8300000 { 3445 compatible = "qcom,sm8250-cdsp-pas"; 3446 reg = <0 0x08300000 0 0x10000>; 3447 3448 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 3449 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3450 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3451 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3452 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3453 interrupt-names = "wdog", "fatal", "ready", 3454 "handover", "stop-ack"; 3455 3456 clocks = <&rpmhcc RPMH_CXO_CLK>; 3457 clock-names = "xo"; 3458 3459 power-domains = <&rpmhpd RPMHPD_CX>; 3460 3461 memory-region = <&cdsp_mem>; 3462 3463 qcom,qmp = <&aoss_qmp>; 3464 3465 qcom,smem-states = <&smp2p_cdsp_out 0>; 3466 qcom,smem-state-names = "stop"; 3467 3468 status = "disabled"; 3469 3470 glink-edge { 3471 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3472 IPCC_MPROC_SIGNAL_GLINK_QMP 3473 IRQ_TYPE_EDGE_RISING>; 3474 mboxes = <&ipcc IPCC_CLIENT_CDSP 3475 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3476 3477 label = "cdsp"; 3478 qcom,remote-pid = <5>; 3479 3480 fastrpc { 3481 compatible = "qcom,fastrpc"; 3482 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3483 label = "cdsp"; 3484 qcom,non-secure-domain; 3485 #address-cells = <1>; 3486 #size-cells = <0>; 3487 3488 compute-cb@1 { 3489 compatible = "qcom,fastrpc-compute-cb"; 3490 reg = <1>; 3491 iommus = <&apps_smmu 0x1001 0x0460>; 3492 }; 3493 3494 compute-cb@2 { 3495 compatible = "qcom,fastrpc-compute-cb"; 3496 reg = <2>; 3497 iommus = <&apps_smmu 0x1002 0x0460>; 3498 }; 3499 3500 compute-cb@3 { 3501 compatible = "qcom,fastrpc-compute-cb"; 3502 reg = <3>; 3503 iommus = <&apps_smmu 0x1003 0x0460>; 3504 }; 3505 3506 compute-cb@4 { 3507 compatible = "qcom,fastrpc-compute-cb"; 3508 reg = <4>; 3509 iommus = <&apps_smmu 0x1004 0x0460>; 3510 }; 3511 3512 compute-cb@5 { 3513 compatible = "qcom,fastrpc-compute-cb"; 3514 reg = <5>; 3515 iommus = <&apps_smmu 0x1005 0x0460>; 3516 }; 3517 3518 compute-cb@6 { 3519 compatible = "qcom,fastrpc-compute-cb"; 3520 reg = <6>; 3521 iommus = <&apps_smmu 0x1006 0x0460>; 3522 }; 3523 3524 compute-cb@7 { 3525 compatible = "qcom,fastrpc-compute-cb"; 3526 reg = <7>; 3527 iommus = <&apps_smmu 0x1007 0x0460>; 3528 }; 3529 3530 compute-cb@8 { 3531 compatible = "qcom,fastrpc-compute-cb"; 3532 reg = <8>; 3533 iommus = <&apps_smmu 0x1008 0x0460>; 3534 }; 3535 3536 /* note: secure cb9 in downstream */ 3537 }; 3538 }; 3539 }; 3540 3541 usb_1_hsphy: phy@88e3000 { 3542 compatible = "qcom,sm8250-usb-hs-phy", 3543 "qcom,usb-snps-hs-7nm-phy"; 3544 reg = <0 0x088e3000 0 0x400>; 3545 status = "disabled"; 3546 #phy-cells = <0>; 3547 3548 clocks = <&rpmhcc RPMH_CXO_CLK>; 3549 clock-names = "ref"; 3550 3551 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3552 }; 3553 3554 usb_2_hsphy: phy@88e4000 { 3555 compatible = "qcom,sm8250-usb-hs-phy", 3556 "qcom,usb-snps-hs-7nm-phy"; 3557 reg = <0 0x088e4000 0 0x400>; 3558 status = "disabled"; 3559 #phy-cells = <0>; 3560 3561 clocks = <&rpmhcc RPMH_CXO_CLK>; 3562 clock-names = "ref"; 3563 3564 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3565 }; 3566 3567 usb_1_qmpphy: phy@88e9000 { 3568 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 3569 reg = <0 0x088e9000 0 0x200>, 3570 <0 0x088e8000 0 0x40>, 3571 <0 0x088ea000 0 0x200>; 3572 status = "disabled"; 3573 #address-cells = <2>; 3574 #size-cells = <2>; 3575 ranges; 3576 3577 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3578 <&rpmhcc RPMH_CXO_CLK>, 3579 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3580 clock-names = "aux", "ref_clk_src", "com_aux"; 3581 3582 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3583 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3584 reset-names = "phy", "common"; 3585 3586 usb_1_ssphy: usb3-phy@88e9200 { 3587 reg = <0 0x088e9200 0 0x200>, 3588 <0 0x088e9400 0 0x200>, 3589 <0 0x088e9c00 0 0x400>, 3590 <0 0x088e9600 0 0x200>, 3591 <0 0x088e9800 0 0x200>, 3592 <0 0x088e9a00 0 0x100>; 3593 #clock-cells = <0>; 3594 #phy-cells = <0>; 3595 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3596 clock-names = "pipe0"; 3597 clock-output-names = "usb3_phy_pipe_clk_src"; 3598 }; 3599 3600 dp_phy: dp-phy@88ea200 { 3601 reg = <0 0x088ea200 0 0x200>, 3602 <0 0x088ea400 0 0x200>, 3603 <0 0x088eaa00 0 0x200>, 3604 <0 0x088ea600 0 0x200>, 3605 <0 0x088ea800 0 0x200>; 3606 #phy-cells = <0>; 3607 #clock-cells = <1>; 3608 }; 3609 }; 3610 3611 usb_2_qmpphy: phy@88eb000 { 3612 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 3613 reg = <0 0x088eb000 0 0x200>; 3614 status = "disabled"; 3615 #address-cells = <2>; 3616 #size-cells = <2>; 3617 ranges; 3618 3619 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3620 <&rpmhcc RPMH_CXO_CLK>, 3621 <&gcc GCC_USB3_SEC_CLKREF_EN>, 3622 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3623 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3624 3625 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3626 <&gcc GCC_USB3_PHY_SEC_BCR>; 3627 reset-names = "phy", "common"; 3628 3629 usb_2_ssphy: phy@88eb200 { 3630 reg = <0 0x088eb200 0 0x200>, 3631 <0 0x088eb400 0 0x200>, 3632 <0 0x088eb800 0 0x800>; 3633 #clock-cells = <0>; 3634 #phy-cells = <0>; 3635 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3636 clock-names = "pipe0"; 3637 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3638 }; 3639 }; 3640 3641 sdhc_2: mmc@8804000 { 3642 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 3643 reg = <0 0x08804000 0 0x1000>; 3644 3645 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3646 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3647 interrupt-names = "hc_irq", "pwr_irq"; 3648 3649 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3650 <&gcc GCC_SDCC2_APPS_CLK>, 3651 <&rpmhcc RPMH_CXO_CLK>; 3652 clock-names = "iface", "core", "xo"; 3653 iommus = <&apps_smmu 0x4a0 0x0>; 3654 qcom,dll-config = <0x0007642c>; 3655 qcom,ddr-config = <0x80040868>; 3656 power-domains = <&rpmhpd RPMHPD_CX>; 3657 operating-points-v2 = <&sdhc2_opp_table>; 3658 3659 status = "disabled"; 3660 3661 sdhc2_opp_table: opp-table { 3662 compatible = "operating-points-v2"; 3663 3664 opp-19200000 { 3665 opp-hz = /bits/ 64 <19200000>; 3666 required-opps = <&rpmhpd_opp_min_svs>; 3667 }; 3668 3669 opp-50000000 { 3670 opp-hz = /bits/ 64 <50000000>; 3671 required-opps = <&rpmhpd_opp_low_svs>; 3672 }; 3673 3674 opp-100000000 { 3675 opp-hz = /bits/ 64 <100000000>; 3676 required-opps = <&rpmhpd_opp_svs>; 3677 }; 3678 3679 opp-202000000 { 3680 opp-hz = /bits/ 64 <202000000>; 3681 required-opps = <&rpmhpd_opp_svs_l1>; 3682 }; 3683 }; 3684 }; 3685 3686 pmu@9091000 { 3687 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3688 reg = <0 0x09091000 0 0x1000>; 3689 3690 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3691 3692 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI_CH0 3>; 3693 3694 operating-points-v2 = <&llcc_bwmon_opp_table>; 3695 3696 llcc_bwmon_opp_table: opp-table { 3697 compatible = "operating-points-v2"; 3698 3699 opp-800000 { 3700 opp-peak-kBps = <(200 * 4 * 1000)>; 3701 }; 3702 3703 opp-1200000 { 3704 opp-peak-kBps = <(300 * 4 * 1000)>; 3705 }; 3706 3707 opp-1804000 { 3708 opp-peak-kBps = <(451 * 4 * 1000)>; 3709 }; 3710 3711 opp-2188000 { 3712 opp-peak-kBps = <(547 * 4 * 1000)>; 3713 }; 3714 3715 opp-2724000 { 3716 opp-peak-kBps = <(681 * 4 * 1000)>; 3717 }; 3718 3719 opp-3072000 { 3720 opp-peak-kBps = <(768 * 4 * 1000)>; 3721 }; 3722 3723 opp-4068000 { 3724 opp-peak-kBps = <(1017 * 4 * 1000)>; 3725 }; 3726 3727 /* 1353 MHz, LPDDR4X */ 3728 3729 opp-6220000 { 3730 opp-peak-kBps = <(1555 * 4 * 1000)>; 3731 }; 3732 3733 opp-7216000 { 3734 opp-peak-kBps = <(1804 * 4 * 1000)>; 3735 }; 3736 3737 opp-8368000 { 3738 opp-peak-kBps = <(2092 * 4 * 1000)>; 3739 }; 3740 3741 /* LPDDR5 */ 3742 opp-10944000 { 3743 opp-peak-kBps = <(2736 * 4 * 1000)>; 3744 }; 3745 }; 3746 }; 3747 3748 pmu@90b6400 { 3749 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon"; 3750 reg = <0 0x090b6400 0 0x600>; 3751 3752 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3753 3754 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &gem_noc SLAVE_LLCC 3>; 3755 operating-points-v2 = <&cpu_bwmon_opp_table>; 3756 3757 cpu_bwmon_opp_table: opp-table { 3758 compatible = "operating-points-v2"; 3759 3760 opp-800000 { 3761 opp-peak-kBps = <(200 * 4 * 1000)>; 3762 }; 3763 3764 opp-1804000 { 3765 opp-peak-kBps = <(451 * 4 * 1000)>; 3766 }; 3767 3768 opp-2188000 { 3769 opp-peak-kBps = <(547 * 4 * 1000)>; 3770 }; 3771 3772 opp-2724000 { 3773 opp-peak-kBps = <(681 * 4 * 1000)>; 3774 }; 3775 3776 opp-3072000 { 3777 opp-peak-kBps = <(768 * 4 * 1000)>; 3778 }; 3779 3780 /* 1017MHz, 1353 MHz, LPDDR4X */ 3781 3782 opp-6220000 { 3783 opp-peak-kBps = <(1555 * 4 * 1000)>; 3784 }; 3785 3786 opp-6832000 { 3787 opp-peak-kBps = <(1708 * 4 * 1000)>; 3788 }; 3789 3790 opp-8368000 { 3791 opp-peak-kBps = <(2092 * 4 * 1000)>; 3792 }; 3793 3794 /* 2133MHz, LPDDR4X */ 3795 3796 /* LPDDR5 */ 3797 opp-10944000 { 3798 opp-peak-kBps = <(2736 * 4 * 1000)>; 3799 }; 3800 3801 /* LPDDR5 */ 3802 opp-12784000 { 3803 opp-peak-kBps = <(3196 * 4 * 1000)>; 3804 }; 3805 }; 3806 }; 3807 3808 dc_noc: interconnect@90c0000 { 3809 compatible = "qcom,sm8250-dc-noc"; 3810 reg = <0 0x090c0000 0 0x4200>; 3811 #interconnect-cells = <2>; 3812 qcom,bcm-voters = <&apps_bcm_voter>; 3813 }; 3814 3815 gem_noc: interconnect@9100000 { 3816 compatible = "qcom,sm8250-gem-noc"; 3817 reg = <0 0x09100000 0 0xb4000>; 3818 #interconnect-cells = <2>; 3819 qcom,bcm-voters = <&apps_bcm_voter>; 3820 }; 3821 3822 npu_noc: interconnect@9990000 { 3823 compatible = "qcom,sm8250-npu-noc"; 3824 reg = <0 0x09990000 0 0x1600>; 3825 #interconnect-cells = <2>; 3826 qcom,bcm-voters = <&apps_bcm_voter>; 3827 }; 3828 3829 usb_1: usb@a6f8800 { 3830 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3831 reg = <0 0x0a6f8800 0 0x400>; 3832 status = "disabled"; 3833 #address-cells = <2>; 3834 #size-cells = <2>; 3835 ranges; 3836 dma-ranges; 3837 3838 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3839 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3840 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3841 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3842 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3843 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3844 clock-names = "cfg_noc", 3845 "core", 3846 "iface", 3847 "sleep", 3848 "mock_utmi", 3849 "xo"; 3850 3851 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3852 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3853 assigned-clock-rates = <19200000>, <200000000>; 3854 3855 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3856 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 3857 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3858 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 3859 interrupt-names = "hs_phy_irq", 3860 "ss_phy_irq", 3861 "dm_hs_phy_irq", 3862 "dp_hs_phy_irq"; 3863 3864 power-domains = <&gcc USB30_PRIM_GDSC>; 3865 3866 resets = <&gcc GCC_USB30_PRIM_BCR>; 3867 3868 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 3869 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 3870 interconnect-names = "usb-ddr", "apps-usb"; 3871 3872 usb_1_dwc3: usb@a600000 { 3873 compatible = "snps,dwc3"; 3874 reg = <0 0x0a600000 0 0xcd00>; 3875 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3876 iommus = <&apps_smmu 0x0 0x0>; 3877 snps,dis_u2_susphy_quirk; 3878 snps,dis_enblslpm_quirk; 3879 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3880 phy-names = "usb2-phy", "usb3-phy"; 3881 }; 3882 }; 3883 3884 system-cache-controller@9200000 { 3885 compatible = "qcom,sm8250-llcc"; 3886 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 3887 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 3888 <0 0x09600000 0 0x50000>; 3889 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3890 "llcc3_base", "llcc_broadcast_base"; 3891 }; 3892 3893 usb_2: usb@a8f8800 { 3894 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3895 reg = <0 0x0a8f8800 0 0x400>; 3896 status = "disabled"; 3897 #address-cells = <2>; 3898 #size-cells = <2>; 3899 ranges; 3900 dma-ranges; 3901 3902 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3903 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3904 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3905 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3906 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3907 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3908 clock-names = "cfg_noc", 3909 "core", 3910 "iface", 3911 "sleep", 3912 "mock_utmi", 3913 "xo"; 3914 3915 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3916 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3917 assigned-clock-rates = <19200000>, <200000000>; 3918 3919 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3920 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 3921 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3922 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 3923 interrupt-names = "hs_phy_irq", 3924 "ss_phy_irq", 3925 "dm_hs_phy_irq", 3926 "dp_hs_phy_irq"; 3927 3928 power-domains = <&gcc USB30_SEC_GDSC>; 3929 3930 resets = <&gcc GCC_USB30_SEC_BCR>; 3931 3932 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 3933 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 3934 interconnect-names = "usb-ddr", "apps-usb"; 3935 3936 usb_2_dwc3: usb@a800000 { 3937 compatible = "snps,dwc3"; 3938 reg = <0 0x0a800000 0 0xcd00>; 3939 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3940 iommus = <&apps_smmu 0x20 0>; 3941 snps,dis_u2_susphy_quirk; 3942 snps,dis_enblslpm_quirk; 3943 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3944 phy-names = "usb2-phy", "usb3-phy"; 3945 }; 3946 }; 3947 3948 venus: video-codec@aa00000 { 3949 compatible = "qcom,sm8250-venus"; 3950 reg = <0 0x0aa00000 0 0x100000>; 3951 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3952 power-domains = <&videocc MVS0C_GDSC>, 3953 <&videocc MVS0_GDSC>, 3954 <&rpmhpd RPMHPD_MX>; 3955 power-domain-names = "venus", "vcodec0", "mx"; 3956 operating-points-v2 = <&venus_opp_table>; 3957 3958 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 3959 <&videocc VIDEO_CC_MVS0C_CLK>, 3960 <&videocc VIDEO_CC_MVS0_CLK>; 3961 clock-names = "iface", "core", "vcodec0_core"; 3962 3963 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>, 3964 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>; 3965 interconnect-names = "cpu-cfg", "video-mem"; 3966 3967 iommus = <&apps_smmu 0x2100 0x0400>; 3968 memory-region = <&video_mem>; 3969 3970 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 3971 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 3972 reset-names = "bus", "core"; 3973 3974 status = "disabled"; 3975 3976 video-decoder { 3977 compatible = "venus-decoder"; 3978 }; 3979 3980 video-encoder { 3981 compatible = "venus-encoder"; 3982 }; 3983 3984 venus_opp_table: opp-table { 3985 compatible = "operating-points-v2"; 3986 3987 opp-720000000 { 3988 opp-hz = /bits/ 64 <720000000>; 3989 required-opps = <&rpmhpd_opp_low_svs>; 3990 }; 3991 3992 opp-1014000000 { 3993 opp-hz = /bits/ 64 <1014000000>; 3994 required-opps = <&rpmhpd_opp_svs>; 3995 }; 3996 3997 opp-1098000000 { 3998 opp-hz = /bits/ 64 <1098000000>; 3999 required-opps = <&rpmhpd_opp_svs_l1>; 4000 }; 4001 4002 opp-1332000000 { 4003 opp-hz = /bits/ 64 <1332000000>; 4004 required-opps = <&rpmhpd_opp_nom>; 4005 }; 4006 }; 4007 }; 4008 4009 videocc: clock-controller@abf0000 { 4010 compatible = "qcom,sm8250-videocc"; 4011 reg = <0 0x0abf0000 0 0x10000>; 4012 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 4013 <&rpmhcc RPMH_CXO_CLK>, 4014 <&rpmhcc RPMH_CXO_CLK_A>; 4015 power-domains = <&rpmhpd RPMHPD_MMCX>; 4016 required-opps = <&rpmhpd_opp_low_svs>; 4017 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 4018 #clock-cells = <1>; 4019 #reset-cells = <1>; 4020 #power-domain-cells = <1>; 4021 }; 4022 4023 cci0: cci@ac4f000 { 4024 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 4025 #address-cells = <1>; 4026 #size-cells = <0>; 4027 4028 reg = <0 0x0ac4f000 0 0x1000>; 4029 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4030 power-domains = <&camcc TITAN_TOP_GDSC>; 4031 4032 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4033 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4034 <&camcc CAM_CC_CPAS_AHB_CLK>, 4035 <&camcc CAM_CC_CCI_0_CLK>, 4036 <&camcc CAM_CC_CCI_0_CLK_SRC>; 4037 clock-names = "camnoc_axi", 4038 "slow_ahb_src", 4039 "cpas_ahb", 4040 "cci", 4041 "cci_src"; 4042 4043 pinctrl-0 = <&cci0_default>; 4044 pinctrl-1 = <&cci0_sleep>; 4045 pinctrl-names = "default", "sleep"; 4046 4047 status = "disabled"; 4048 4049 cci0_i2c0: i2c-bus@0 { 4050 reg = <0>; 4051 clock-frequency = <1000000>; 4052 #address-cells = <1>; 4053 #size-cells = <0>; 4054 }; 4055 4056 cci0_i2c1: i2c-bus@1 { 4057 reg = <1>; 4058 clock-frequency = <1000000>; 4059 #address-cells = <1>; 4060 #size-cells = <0>; 4061 }; 4062 }; 4063 4064 cci1: cci@ac50000 { 4065 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 4066 #address-cells = <1>; 4067 #size-cells = <0>; 4068 4069 reg = <0 0x0ac50000 0 0x1000>; 4070 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4071 power-domains = <&camcc TITAN_TOP_GDSC>; 4072 4073 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4074 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4075 <&camcc CAM_CC_CPAS_AHB_CLK>, 4076 <&camcc CAM_CC_CCI_1_CLK>, 4077 <&camcc CAM_CC_CCI_1_CLK_SRC>; 4078 clock-names = "camnoc_axi", 4079 "slow_ahb_src", 4080 "cpas_ahb", 4081 "cci", 4082 "cci_src"; 4083 4084 pinctrl-0 = <&cci1_default>; 4085 pinctrl-1 = <&cci1_sleep>; 4086 pinctrl-names = "default", "sleep"; 4087 4088 status = "disabled"; 4089 4090 cci1_i2c0: i2c-bus@0 { 4091 reg = <0>; 4092 clock-frequency = <1000000>; 4093 #address-cells = <1>; 4094 #size-cells = <0>; 4095 }; 4096 4097 cci1_i2c1: i2c-bus@1 { 4098 reg = <1>; 4099 clock-frequency = <1000000>; 4100 #address-cells = <1>; 4101 #size-cells = <0>; 4102 }; 4103 }; 4104 4105 camss: camss@ac6a000 { 4106 compatible = "qcom,sm8250-camss"; 4107 status = "disabled"; 4108 4109 reg = <0 0x0ac6a000 0 0x2000>, 4110 <0 0x0ac6c000 0 0x2000>, 4111 <0 0x0ac6e000 0 0x1000>, 4112 <0 0x0ac70000 0 0x1000>, 4113 <0 0x0ac72000 0 0x1000>, 4114 <0 0x0ac74000 0 0x1000>, 4115 <0 0x0acb4000 0 0xd000>, 4116 <0 0x0acc3000 0 0xd000>, 4117 <0 0x0acd9000 0 0x2200>, 4118 <0 0x0acdb200 0 0x2200>; 4119 reg-names = "csiphy0", 4120 "csiphy1", 4121 "csiphy2", 4122 "csiphy3", 4123 "csiphy4", 4124 "csiphy5", 4125 "vfe0", 4126 "vfe1", 4127 "vfe_lite0", 4128 "vfe_lite1"; 4129 4130 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 4131 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 4132 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 4133 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 4134 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 4135 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 4136 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 4137 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 4138 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 4139 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 4140 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 4141 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 4142 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 4143 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 4144 interrupt-names = "csiphy0", 4145 "csiphy1", 4146 "csiphy2", 4147 "csiphy3", 4148 "csiphy4", 4149 "csiphy5", 4150 "csid0", 4151 "csid1", 4152 "csid2", 4153 "csid3", 4154 "vfe0", 4155 "vfe1", 4156 "vfe_lite0", 4157 "vfe_lite1"; 4158 4159 power-domains = <&camcc IFE_0_GDSC>, 4160 <&camcc IFE_1_GDSC>, 4161 <&camcc TITAN_TOP_GDSC>; 4162 4163 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4164 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4165 <&gcc GCC_CAMERA_SF_AXI_CLK>, 4166 <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4167 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, 4168 <&camcc CAM_CC_CORE_AHB_CLK>, 4169 <&camcc CAM_CC_CPAS_AHB_CLK>, 4170 <&camcc CAM_CC_CSIPHY0_CLK>, 4171 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4172 <&camcc CAM_CC_CSIPHY1_CLK>, 4173 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4174 <&camcc CAM_CC_CSIPHY2_CLK>, 4175 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4176 <&camcc CAM_CC_CSIPHY3_CLK>, 4177 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 4178 <&camcc CAM_CC_CSIPHY4_CLK>, 4179 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 4180 <&camcc CAM_CC_CSIPHY5_CLK>, 4181 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 4182 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4183 <&camcc CAM_CC_IFE_0_AHB_CLK>, 4184 <&camcc CAM_CC_IFE_0_AXI_CLK>, 4185 <&camcc CAM_CC_IFE_0_CLK>, 4186 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4187 <&camcc CAM_CC_IFE_0_CSID_CLK>, 4188 <&camcc CAM_CC_IFE_0_AREG_CLK>, 4189 <&camcc CAM_CC_IFE_1_AHB_CLK>, 4190 <&camcc CAM_CC_IFE_1_AXI_CLK>, 4191 <&camcc CAM_CC_IFE_1_CLK>, 4192 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4193 <&camcc CAM_CC_IFE_1_CSID_CLK>, 4194 <&camcc CAM_CC_IFE_1_AREG_CLK>, 4195 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 4196 <&camcc CAM_CC_IFE_LITE_AXI_CLK>, 4197 <&camcc CAM_CC_IFE_LITE_CLK>, 4198 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4199 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 4200 4201 clock-names = "cam_ahb_clk", 4202 "cam_hf_axi", 4203 "cam_sf_axi", 4204 "camnoc_axi", 4205 "camnoc_axi_src", 4206 "core_ahb", 4207 "cpas_ahb", 4208 "csiphy0", 4209 "csiphy0_timer", 4210 "csiphy1", 4211 "csiphy1_timer", 4212 "csiphy2", 4213 "csiphy2_timer", 4214 "csiphy3", 4215 "csiphy3_timer", 4216 "csiphy4", 4217 "csiphy4_timer", 4218 "csiphy5", 4219 "csiphy5_timer", 4220 "slow_ahb_src", 4221 "vfe0_ahb", 4222 "vfe0_axi", 4223 "vfe0", 4224 "vfe0_cphy_rx", 4225 "vfe0_csid", 4226 "vfe0_areg", 4227 "vfe1_ahb", 4228 "vfe1_axi", 4229 "vfe1", 4230 "vfe1_cphy_rx", 4231 "vfe1_csid", 4232 "vfe1_areg", 4233 "vfe_lite_ahb", 4234 "vfe_lite_axi", 4235 "vfe_lite", 4236 "vfe_lite_cphy_rx", 4237 "vfe_lite_csid"; 4238 4239 iommus = <&apps_smmu 0x800 0x400>, 4240 <&apps_smmu 0x801 0x400>, 4241 <&apps_smmu 0x840 0x400>, 4242 <&apps_smmu 0x841 0x400>, 4243 <&apps_smmu 0xc00 0x400>, 4244 <&apps_smmu 0xc01 0x400>, 4245 <&apps_smmu 0xc40 0x400>, 4246 <&apps_smmu 0xc41 0x400>; 4247 4248 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>, 4249 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>, 4250 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>, 4251 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>; 4252 interconnect-names = "cam_ahb", 4253 "cam_hf_0_mnoc", 4254 "cam_sf_0_mnoc", 4255 "cam_sf_icp_mnoc"; 4256 4257 ports { 4258 #address-cells = <1>; 4259 #size-cells = <0>; 4260 4261 port@0 { 4262 reg = <0>; 4263 }; 4264 4265 port@1 { 4266 reg = <1>; 4267 }; 4268 4269 port@2 { 4270 reg = <2>; 4271 }; 4272 4273 port@3 { 4274 reg = <3>; 4275 }; 4276 4277 port@4 { 4278 reg = <4>; 4279 }; 4280 4281 port@5 { 4282 reg = <5>; 4283 }; 4284 }; 4285 }; 4286 4287 camcc: clock-controller@ad00000 { 4288 compatible = "qcom,sm8250-camcc"; 4289 reg = <0 0x0ad00000 0 0x10000>; 4290 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4291 <&rpmhcc RPMH_CXO_CLK>, 4292 <&rpmhcc RPMH_CXO_CLK_A>, 4293 <&sleep_clk>; 4294 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 4295 power-domains = <&rpmhpd RPMHPD_MMCX>; 4296 required-opps = <&rpmhpd_opp_low_svs>; 4297 status = "disabled"; 4298 #clock-cells = <1>; 4299 #reset-cells = <1>; 4300 #power-domain-cells = <1>; 4301 }; 4302 4303 mdss: display-subsystem@ae00000 { 4304 compatible = "qcom,sm8250-mdss"; 4305 reg = <0 0x0ae00000 0 0x1000>; 4306 reg-names = "mdss"; 4307 4308 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 4309 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 4310 interconnect-names = "mdp0-mem", "mdp1-mem"; 4311 4312 power-domains = <&dispcc MDSS_GDSC>; 4313 4314 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4315 <&gcc GCC_DISP_HF_AXI_CLK>, 4316 <&gcc GCC_DISP_SF_AXI_CLK>, 4317 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4318 clock-names = "iface", "bus", "nrt_bus", "core"; 4319 4320 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4321 interrupt-controller; 4322 #interrupt-cells = <1>; 4323 4324 iommus = <&apps_smmu 0x820 0x402>; 4325 4326 status = "disabled"; 4327 4328 #address-cells = <2>; 4329 #size-cells = <2>; 4330 ranges; 4331 4332 mdss_mdp: display-controller@ae01000 { 4333 compatible = "qcom,sm8250-dpu"; 4334 reg = <0 0x0ae01000 0 0x8f000>, 4335 <0 0x0aeb0000 0 0x2008>; 4336 reg-names = "mdp", "vbif"; 4337 4338 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4339 <&gcc GCC_DISP_HF_AXI_CLK>, 4340 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4341 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4342 clock-names = "iface", "bus", "core", "vsync"; 4343 4344 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4345 assigned-clock-rates = <19200000>; 4346 4347 operating-points-v2 = <&mdp_opp_table>; 4348 power-domains = <&rpmhpd RPMHPD_MMCX>; 4349 4350 interrupt-parent = <&mdss>; 4351 interrupts = <0>; 4352 4353 ports { 4354 #address-cells = <1>; 4355 #size-cells = <0>; 4356 4357 port@0 { 4358 reg = <0>; 4359 dpu_intf1_out: endpoint { 4360 remote-endpoint = <&mdss_dsi0_in>; 4361 }; 4362 }; 4363 4364 port@1 { 4365 reg = <1>; 4366 dpu_intf2_out: endpoint { 4367 remote-endpoint = <&mdss_dsi1_in>; 4368 }; 4369 }; 4370 }; 4371 4372 mdp_opp_table: opp-table { 4373 compatible = "operating-points-v2"; 4374 4375 opp-200000000 { 4376 opp-hz = /bits/ 64 <200000000>; 4377 required-opps = <&rpmhpd_opp_low_svs>; 4378 }; 4379 4380 opp-300000000 { 4381 opp-hz = /bits/ 64 <300000000>; 4382 required-opps = <&rpmhpd_opp_svs>; 4383 }; 4384 4385 opp-345000000 { 4386 opp-hz = /bits/ 64 <345000000>; 4387 required-opps = <&rpmhpd_opp_svs_l1>; 4388 }; 4389 4390 opp-460000000 { 4391 opp-hz = /bits/ 64 <460000000>; 4392 required-opps = <&rpmhpd_opp_nom>; 4393 }; 4394 }; 4395 }; 4396 4397 mdss_dsi0: dsi@ae94000 { 4398 compatible = "qcom,sm8250-dsi-ctrl", 4399 "qcom,mdss-dsi-ctrl"; 4400 reg = <0 0x0ae94000 0 0x400>; 4401 reg-names = "dsi_ctrl"; 4402 4403 interrupt-parent = <&mdss>; 4404 interrupts = <4>; 4405 4406 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4407 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4408 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4409 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4410 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4411 <&gcc GCC_DISP_HF_AXI_CLK>; 4412 clock-names = "byte", 4413 "byte_intf", 4414 "pixel", 4415 "core", 4416 "iface", 4417 "bus"; 4418 4419 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4420 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 4421 4422 operating-points-v2 = <&dsi_opp_table>; 4423 power-domains = <&rpmhpd RPMHPD_MMCX>; 4424 4425 phys = <&mdss_dsi0_phy>; 4426 4427 status = "disabled"; 4428 4429 #address-cells = <1>; 4430 #size-cells = <0>; 4431 4432 ports { 4433 #address-cells = <1>; 4434 #size-cells = <0>; 4435 4436 port@0 { 4437 reg = <0>; 4438 mdss_dsi0_in: endpoint { 4439 remote-endpoint = <&dpu_intf1_out>; 4440 }; 4441 }; 4442 4443 port@1 { 4444 reg = <1>; 4445 mdss_dsi0_out: endpoint { 4446 }; 4447 }; 4448 }; 4449 4450 dsi_opp_table: opp-table { 4451 compatible = "operating-points-v2"; 4452 4453 opp-187500000 { 4454 opp-hz = /bits/ 64 <187500000>; 4455 required-opps = <&rpmhpd_opp_low_svs>; 4456 }; 4457 4458 opp-300000000 { 4459 opp-hz = /bits/ 64 <300000000>; 4460 required-opps = <&rpmhpd_opp_svs>; 4461 }; 4462 4463 opp-358000000 { 4464 opp-hz = /bits/ 64 <358000000>; 4465 required-opps = <&rpmhpd_opp_svs_l1>; 4466 }; 4467 }; 4468 }; 4469 4470 mdss_dsi0_phy: phy@ae94400 { 4471 compatible = "qcom,dsi-phy-7nm"; 4472 reg = <0 0x0ae94400 0 0x200>, 4473 <0 0x0ae94600 0 0x280>, 4474 <0 0x0ae94900 0 0x260>; 4475 reg-names = "dsi_phy", 4476 "dsi_phy_lane", 4477 "dsi_pll"; 4478 4479 #clock-cells = <1>; 4480 #phy-cells = <0>; 4481 4482 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4483 <&rpmhcc RPMH_CXO_CLK>; 4484 clock-names = "iface", "ref"; 4485 4486 status = "disabled"; 4487 }; 4488 4489 mdss_dsi1: dsi@ae96000 { 4490 compatible = "qcom,sm8250-dsi-ctrl", 4491 "qcom,mdss-dsi-ctrl"; 4492 reg = <0 0x0ae96000 0 0x400>; 4493 reg-names = "dsi_ctrl"; 4494 4495 interrupt-parent = <&mdss>; 4496 interrupts = <5>; 4497 4498 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4499 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4500 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4501 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4502 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4503 <&gcc GCC_DISP_HF_AXI_CLK>; 4504 clock-names = "byte", 4505 "byte_intf", 4506 "pixel", 4507 "core", 4508 "iface", 4509 "bus"; 4510 4511 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4512 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 4513 4514 operating-points-v2 = <&dsi_opp_table>; 4515 power-domains = <&rpmhpd RPMHPD_MMCX>; 4516 4517 phys = <&mdss_dsi1_phy>; 4518 4519 status = "disabled"; 4520 4521 #address-cells = <1>; 4522 #size-cells = <0>; 4523 4524 ports { 4525 #address-cells = <1>; 4526 #size-cells = <0>; 4527 4528 port@0 { 4529 reg = <0>; 4530 mdss_dsi1_in: endpoint { 4531 remote-endpoint = <&dpu_intf2_out>; 4532 }; 4533 }; 4534 4535 port@1 { 4536 reg = <1>; 4537 mdss_dsi1_out: endpoint { 4538 }; 4539 }; 4540 }; 4541 }; 4542 4543 mdss_dsi1_phy: phy@ae96400 { 4544 compatible = "qcom,dsi-phy-7nm"; 4545 reg = <0 0x0ae96400 0 0x200>, 4546 <0 0x0ae96600 0 0x280>, 4547 <0 0x0ae96900 0 0x260>; 4548 reg-names = "dsi_phy", 4549 "dsi_phy_lane", 4550 "dsi_pll"; 4551 4552 #clock-cells = <1>; 4553 #phy-cells = <0>; 4554 4555 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4556 <&rpmhcc RPMH_CXO_CLK>; 4557 clock-names = "iface", "ref"; 4558 4559 status = "disabled"; 4560 }; 4561 }; 4562 4563 dispcc: clock-controller@af00000 { 4564 compatible = "qcom,sm8250-dispcc"; 4565 reg = <0 0x0af00000 0 0x10000>; 4566 power-domains = <&rpmhpd RPMHPD_MMCX>; 4567 required-opps = <&rpmhpd_opp_low_svs>; 4568 clocks = <&rpmhcc RPMH_CXO_CLK>, 4569 <&mdss_dsi0_phy 0>, 4570 <&mdss_dsi0_phy 1>, 4571 <&mdss_dsi1_phy 0>, 4572 <&mdss_dsi1_phy 1>, 4573 <&dp_phy 0>, 4574 <&dp_phy 1>; 4575 clock-names = "bi_tcxo", 4576 "dsi0_phy_pll_out_byteclk", 4577 "dsi0_phy_pll_out_dsiclk", 4578 "dsi1_phy_pll_out_byteclk", 4579 "dsi1_phy_pll_out_dsiclk", 4580 "dp_phy_pll_link_clk", 4581 "dp_phy_pll_vco_div_clk"; 4582 #clock-cells = <1>; 4583 #reset-cells = <1>; 4584 #power-domain-cells = <1>; 4585 }; 4586 4587 pdc: interrupt-controller@b220000 { 4588 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 4589 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 4590 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4591 <125 63 1>, <126 716 12>; 4592 #interrupt-cells = <2>; 4593 interrupt-parent = <&intc>; 4594 interrupt-controller; 4595 }; 4596 4597 tsens0: thermal-sensor@c263000 { 4598 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 4599 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4600 <0 0x0c222000 0 0x1ff>; /* SROT */ 4601 #qcom,sensors = <16>; 4602 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4603 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4604 interrupt-names = "uplow", "critical"; 4605 #thermal-sensor-cells = <1>; 4606 }; 4607 4608 tsens1: thermal-sensor@c265000 { 4609 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 4610 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4611 <0 0x0c223000 0 0x1ff>; /* SROT */ 4612 #qcom,sensors = <9>; 4613 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4614 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4615 interrupt-names = "uplow", "critical"; 4616 #thermal-sensor-cells = <1>; 4617 }; 4618 4619 aoss_qmp: power-management@c300000 { 4620 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; 4621 reg = <0 0x0c300000 0 0x400>; 4622 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4623 IPCC_MPROC_SIGNAL_GLINK_QMP 4624 IRQ_TYPE_EDGE_RISING>; 4625 mboxes = <&ipcc IPCC_CLIENT_AOP 4626 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4627 4628 #clock-cells = <0>; 4629 }; 4630 4631 sram@c3f0000 { 4632 compatible = "qcom,rpmh-stats"; 4633 reg = <0 0x0c3f0000 0 0x400>; 4634 }; 4635 4636 spmi_bus: spmi@c440000 { 4637 compatible = "qcom,spmi-pmic-arb"; 4638 reg = <0x0 0x0c440000 0x0 0x0001100>, 4639 <0x0 0x0c600000 0x0 0x2000000>, 4640 <0x0 0x0e600000 0x0 0x0100000>, 4641 <0x0 0x0e700000 0x0 0x00a0000>, 4642 <0x0 0x0c40a000 0x0 0x0026000>; 4643 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4644 interrupt-names = "periph_irq"; 4645 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4646 qcom,ee = <0>; 4647 qcom,channel = <0>; 4648 #address-cells = <2>; 4649 #size-cells = <0>; 4650 interrupt-controller; 4651 #interrupt-cells = <4>; 4652 }; 4653 4654 tlmm: pinctrl@f100000 { 4655 compatible = "qcom,sm8250-pinctrl"; 4656 reg = <0 0x0f100000 0 0x300000>, 4657 <0 0x0f500000 0 0x300000>, 4658 <0 0x0f900000 0 0x300000>; 4659 reg-names = "west", "south", "north"; 4660 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4661 gpio-controller; 4662 #gpio-cells = <2>; 4663 interrupt-controller; 4664 #interrupt-cells = <2>; 4665 gpio-ranges = <&tlmm 0 0 181>; 4666 wakeup-parent = <&pdc>; 4667 4668 cam2_default: cam2-default-state { 4669 rst-pins { 4670 pins = "gpio78"; 4671 function = "gpio"; 4672 drive-strength = <2>; 4673 bias-disable; 4674 }; 4675 4676 mclk-pins { 4677 pins = "gpio96"; 4678 function = "cam_mclk"; 4679 drive-strength = <16>; 4680 bias-disable; 4681 }; 4682 }; 4683 4684 cam2_suspend: cam2-suspend-state { 4685 rst-pins { 4686 pins = "gpio78"; 4687 function = "gpio"; 4688 drive-strength = <2>; 4689 bias-pull-down; 4690 output-low; 4691 }; 4692 4693 mclk-pins { 4694 pins = "gpio96"; 4695 function = "cam_mclk"; 4696 drive-strength = <2>; 4697 bias-disable; 4698 }; 4699 }; 4700 4701 cci0_default: cci0-default-state { 4702 cci0_i2c0_default: cci0-i2c0-default-pins { 4703 /* SDA, SCL */ 4704 pins = "gpio101", "gpio102"; 4705 function = "cci_i2c"; 4706 4707 bias-pull-up; 4708 drive-strength = <2>; /* 2 mA */ 4709 }; 4710 4711 cci0_i2c1_default: cci0-i2c1-default-pins { 4712 /* SDA, SCL */ 4713 pins = "gpio103", "gpio104"; 4714 function = "cci_i2c"; 4715 4716 bias-pull-up; 4717 drive-strength = <2>; /* 2 mA */ 4718 }; 4719 }; 4720 4721 cci0_sleep: cci0-sleep-state { 4722 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 4723 /* SDA, SCL */ 4724 pins = "gpio101", "gpio102"; 4725 function = "cci_i2c"; 4726 4727 drive-strength = <2>; /* 2 mA */ 4728 bias-pull-down; 4729 }; 4730 4731 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 4732 /* SDA, SCL */ 4733 pins = "gpio103", "gpio104"; 4734 function = "cci_i2c"; 4735 4736 drive-strength = <2>; /* 2 mA */ 4737 bias-pull-down; 4738 }; 4739 }; 4740 4741 cci1_default: cci1-default-state { 4742 cci1_i2c0_default: cci1-i2c0-default-pins { 4743 /* SDA, SCL */ 4744 pins = "gpio105","gpio106"; 4745 function = "cci_i2c"; 4746 4747 bias-pull-up; 4748 drive-strength = <2>; /* 2 mA */ 4749 }; 4750 4751 cci1_i2c1_default: cci1-i2c1-default-pins { 4752 /* SDA, SCL */ 4753 pins = "gpio107","gpio108"; 4754 function = "cci_i2c"; 4755 4756 bias-pull-up; 4757 drive-strength = <2>; /* 2 mA */ 4758 }; 4759 }; 4760 4761 cci1_sleep: cci1-sleep-state { 4762 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 4763 /* SDA, SCL */ 4764 pins = "gpio105","gpio106"; 4765 function = "cci_i2c"; 4766 4767 bias-pull-down; 4768 drive-strength = <2>; /* 2 mA */ 4769 }; 4770 4771 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 4772 /* SDA, SCL */ 4773 pins = "gpio107","gpio108"; 4774 function = "cci_i2c"; 4775 4776 bias-pull-down; 4777 drive-strength = <2>; /* 2 mA */ 4778 }; 4779 }; 4780 4781 pri_mi2s_active: pri-mi2s-active-state { 4782 sclk-pins { 4783 pins = "gpio138"; 4784 function = "mi2s0_sck"; 4785 drive-strength = <8>; 4786 bias-disable; 4787 }; 4788 4789 ws-pins { 4790 pins = "gpio141"; 4791 function = "mi2s0_ws"; 4792 drive-strength = <8>; 4793 output-high; 4794 }; 4795 4796 data0-pins { 4797 pins = "gpio139"; 4798 function = "mi2s0_data0"; 4799 drive-strength = <8>; 4800 bias-disable; 4801 output-high; 4802 }; 4803 4804 data1-pins { 4805 pins = "gpio140"; 4806 function = "mi2s0_data1"; 4807 drive-strength = <8>; 4808 output-high; 4809 }; 4810 }; 4811 4812 qup_i2c0_default: qup-i2c0-default-state { 4813 pins = "gpio28", "gpio29"; 4814 function = "qup0"; 4815 drive-strength = <2>; 4816 bias-disable; 4817 }; 4818 4819 qup_i2c1_default: qup-i2c1-default-state { 4820 pins = "gpio4", "gpio5"; 4821 function = "qup1"; 4822 drive-strength = <2>; 4823 bias-disable; 4824 }; 4825 4826 qup_i2c2_default: qup-i2c2-default-state { 4827 pins = "gpio115", "gpio116"; 4828 function = "qup2"; 4829 drive-strength = <2>; 4830 bias-disable; 4831 }; 4832 4833 qup_i2c3_default: qup-i2c3-default-state { 4834 pins = "gpio119", "gpio120"; 4835 function = "qup3"; 4836 drive-strength = <2>; 4837 bias-disable; 4838 }; 4839 4840 qup_i2c4_default: qup-i2c4-default-state { 4841 pins = "gpio8", "gpio9"; 4842 function = "qup4"; 4843 drive-strength = <2>; 4844 bias-disable; 4845 }; 4846 4847 qup_i2c5_default: qup-i2c5-default-state { 4848 pins = "gpio12", "gpio13"; 4849 function = "qup5"; 4850 drive-strength = <2>; 4851 bias-disable; 4852 }; 4853 4854 qup_i2c6_default: qup-i2c6-default-state { 4855 pins = "gpio16", "gpio17"; 4856 function = "qup6"; 4857 drive-strength = <2>; 4858 bias-disable; 4859 }; 4860 4861 qup_i2c7_default: qup-i2c7-default-state { 4862 pins = "gpio20", "gpio21"; 4863 function = "qup7"; 4864 drive-strength = <2>; 4865 bias-disable; 4866 }; 4867 4868 qup_i2c8_default: qup-i2c8-default-state { 4869 pins = "gpio24", "gpio25"; 4870 function = "qup8"; 4871 drive-strength = <2>; 4872 bias-disable; 4873 }; 4874 4875 qup_i2c9_default: qup-i2c9-default-state { 4876 pins = "gpio125", "gpio126"; 4877 function = "qup9"; 4878 drive-strength = <2>; 4879 bias-disable; 4880 }; 4881 4882 qup_i2c10_default: qup-i2c10-default-state { 4883 pins = "gpio129", "gpio130"; 4884 function = "qup10"; 4885 drive-strength = <2>; 4886 bias-disable; 4887 }; 4888 4889 qup_i2c11_default: qup-i2c11-default-state { 4890 pins = "gpio60", "gpio61"; 4891 function = "qup11"; 4892 drive-strength = <2>; 4893 bias-disable; 4894 }; 4895 4896 qup_i2c12_default: qup-i2c12-default-state { 4897 pins = "gpio32", "gpio33"; 4898 function = "qup12"; 4899 drive-strength = <2>; 4900 bias-disable; 4901 }; 4902 4903 qup_i2c13_default: qup-i2c13-default-state { 4904 pins = "gpio36", "gpio37"; 4905 function = "qup13"; 4906 drive-strength = <2>; 4907 bias-disable; 4908 }; 4909 4910 qup_i2c14_default: qup-i2c14-default-state { 4911 pins = "gpio40", "gpio41"; 4912 function = "qup14"; 4913 drive-strength = <2>; 4914 bias-disable; 4915 }; 4916 4917 qup_i2c15_default: qup-i2c15-default-state { 4918 pins = "gpio44", "gpio45"; 4919 function = "qup15"; 4920 drive-strength = <2>; 4921 bias-disable; 4922 }; 4923 4924 qup_i2c16_default: qup-i2c16-default-state { 4925 pins = "gpio48", "gpio49"; 4926 function = "qup16"; 4927 drive-strength = <2>; 4928 bias-disable; 4929 }; 4930 4931 qup_i2c17_default: qup-i2c17-default-state { 4932 pins = "gpio52", "gpio53"; 4933 function = "qup17"; 4934 drive-strength = <2>; 4935 bias-disable; 4936 }; 4937 4938 qup_i2c18_default: qup-i2c18-default-state { 4939 pins = "gpio56", "gpio57"; 4940 function = "qup18"; 4941 drive-strength = <2>; 4942 bias-disable; 4943 }; 4944 4945 qup_i2c19_default: qup-i2c19-default-state { 4946 pins = "gpio0", "gpio1"; 4947 function = "qup19"; 4948 drive-strength = <2>; 4949 bias-disable; 4950 }; 4951 4952 qup_spi0_cs: qup-spi0-cs-state { 4953 pins = "gpio31"; 4954 function = "qup0"; 4955 }; 4956 4957 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4958 pins = "gpio31"; 4959 function = "gpio"; 4960 }; 4961 4962 qup_spi0_data_clk: qup-spi0-data-clk-state { 4963 pins = "gpio28", "gpio29", 4964 "gpio30"; 4965 function = "qup0"; 4966 }; 4967 4968 qup_spi1_cs: qup-spi1-cs-state { 4969 pins = "gpio7"; 4970 function = "qup1"; 4971 }; 4972 4973 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4974 pins = "gpio7"; 4975 function = "gpio"; 4976 }; 4977 4978 qup_spi1_data_clk: qup-spi1-data-clk-state { 4979 pins = "gpio4", "gpio5", 4980 "gpio6"; 4981 function = "qup1"; 4982 }; 4983 4984 qup_spi2_cs: qup-spi2-cs-state { 4985 pins = "gpio118"; 4986 function = "qup2"; 4987 }; 4988 4989 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4990 pins = "gpio118"; 4991 function = "gpio"; 4992 }; 4993 4994 qup_spi2_data_clk: qup-spi2-data-clk-state { 4995 pins = "gpio115", "gpio116", 4996 "gpio117"; 4997 function = "qup2"; 4998 }; 4999 5000 qup_spi3_cs: qup-spi3-cs-state { 5001 pins = "gpio122"; 5002 function = "qup3"; 5003 }; 5004 5005 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 5006 pins = "gpio122"; 5007 function = "gpio"; 5008 }; 5009 5010 qup_spi3_data_clk: qup-spi3-data-clk-state { 5011 pins = "gpio119", "gpio120", 5012 "gpio121"; 5013 function = "qup3"; 5014 }; 5015 5016 qup_spi4_cs: qup-spi4-cs-state { 5017 pins = "gpio11"; 5018 function = "qup4"; 5019 }; 5020 5021 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 5022 pins = "gpio11"; 5023 function = "gpio"; 5024 }; 5025 5026 qup_spi4_data_clk: qup-spi4-data-clk-state { 5027 pins = "gpio8", "gpio9", 5028 "gpio10"; 5029 function = "qup4"; 5030 }; 5031 5032 qup_spi5_cs: qup-spi5-cs-state { 5033 pins = "gpio15"; 5034 function = "qup5"; 5035 }; 5036 5037 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 5038 pins = "gpio15"; 5039 function = "gpio"; 5040 }; 5041 5042 qup_spi5_data_clk: qup-spi5-data-clk-state { 5043 pins = "gpio12", "gpio13", 5044 "gpio14"; 5045 function = "qup5"; 5046 }; 5047 5048 qup_spi6_cs: qup-spi6-cs-state { 5049 pins = "gpio19"; 5050 function = "qup6"; 5051 }; 5052 5053 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 5054 pins = "gpio19"; 5055 function = "gpio"; 5056 }; 5057 5058 qup_spi6_data_clk: qup-spi6-data-clk-state { 5059 pins = "gpio16", "gpio17", 5060 "gpio18"; 5061 function = "qup6"; 5062 }; 5063 5064 qup_spi7_cs: qup-spi7-cs-state { 5065 pins = "gpio23"; 5066 function = "qup7"; 5067 }; 5068 5069 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 5070 pins = "gpio23"; 5071 function = "gpio"; 5072 }; 5073 5074 qup_spi7_data_clk: qup-spi7-data-clk-state { 5075 pins = "gpio20", "gpio21", 5076 "gpio22"; 5077 function = "qup7"; 5078 }; 5079 5080 qup_spi8_cs: qup-spi8-cs-state { 5081 pins = "gpio27"; 5082 function = "qup8"; 5083 }; 5084 5085 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 5086 pins = "gpio27"; 5087 function = "gpio"; 5088 }; 5089 5090 qup_spi8_data_clk: qup-spi8-data-clk-state { 5091 pins = "gpio24", "gpio25", 5092 "gpio26"; 5093 function = "qup8"; 5094 }; 5095 5096 qup_spi9_cs: qup-spi9-cs-state { 5097 pins = "gpio128"; 5098 function = "qup9"; 5099 }; 5100 5101 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 5102 pins = "gpio128"; 5103 function = "gpio"; 5104 }; 5105 5106 qup_spi9_data_clk: qup-spi9-data-clk-state { 5107 pins = "gpio125", "gpio126", 5108 "gpio127"; 5109 function = "qup9"; 5110 }; 5111 5112 qup_spi10_cs: qup-spi10-cs-state { 5113 pins = "gpio132"; 5114 function = "qup10"; 5115 }; 5116 5117 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 5118 pins = "gpio132"; 5119 function = "gpio"; 5120 }; 5121 5122 qup_spi10_data_clk: qup-spi10-data-clk-state { 5123 pins = "gpio129", "gpio130", 5124 "gpio131"; 5125 function = "qup10"; 5126 }; 5127 5128 qup_spi11_cs: qup-spi11-cs-state { 5129 pins = "gpio63"; 5130 function = "qup11"; 5131 }; 5132 5133 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 5134 pins = "gpio63"; 5135 function = "gpio"; 5136 }; 5137 5138 qup_spi11_data_clk: qup-spi11-data-clk-state { 5139 pins = "gpio60", "gpio61", 5140 "gpio62"; 5141 function = "qup11"; 5142 }; 5143 5144 qup_spi12_cs: qup-spi12-cs-state { 5145 pins = "gpio35"; 5146 function = "qup12"; 5147 }; 5148 5149 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 5150 pins = "gpio35"; 5151 function = "gpio"; 5152 }; 5153 5154 qup_spi12_data_clk: qup-spi12-data-clk-state { 5155 pins = "gpio32", "gpio33", 5156 "gpio34"; 5157 function = "qup12"; 5158 }; 5159 5160 qup_spi13_cs: qup-spi13-cs-state { 5161 pins = "gpio39"; 5162 function = "qup13"; 5163 }; 5164 5165 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 5166 pins = "gpio39"; 5167 function = "gpio"; 5168 }; 5169 5170 qup_spi13_data_clk: qup-spi13-data-clk-state { 5171 pins = "gpio36", "gpio37", 5172 "gpio38"; 5173 function = "qup13"; 5174 }; 5175 5176 qup_spi14_cs: qup-spi14-cs-state { 5177 pins = "gpio43"; 5178 function = "qup14"; 5179 }; 5180 5181 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 5182 pins = "gpio43"; 5183 function = "gpio"; 5184 }; 5185 5186 qup_spi14_data_clk: qup-spi14-data-clk-state { 5187 pins = "gpio40", "gpio41", 5188 "gpio42"; 5189 function = "qup14"; 5190 }; 5191 5192 qup_spi15_cs: qup-spi15-cs-state { 5193 pins = "gpio47"; 5194 function = "qup15"; 5195 }; 5196 5197 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 5198 pins = "gpio47"; 5199 function = "gpio"; 5200 }; 5201 5202 qup_spi15_data_clk: qup-spi15-data-clk-state { 5203 pins = "gpio44", "gpio45", 5204 "gpio46"; 5205 function = "qup15"; 5206 }; 5207 5208 qup_spi16_cs: qup-spi16-cs-state { 5209 pins = "gpio51"; 5210 function = "qup16"; 5211 }; 5212 5213 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 5214 pins = "gpio51"; 5215 function = "gpio"; 5216 }; 5217 5218 qup_spi16_data_clk: qup-spi16-data-clk-state { 5219 pins = "gpio48", "gpio49", 5220 "gpio50"; 5221 function = "qup16"; 5222 }; 5223 5224 qup_spi17_cs: qup-spi17-cs-state { 5225 pins = "gpio55"; 5226 function = "qup17"; 5227 }; 5228 5229 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state { 5230 pins = "gpio55"; 5231 function = "gpio"; 5232 }; 5233 5234 qup_spi17_data_clk: qup-spi17-data-clk-state { 5235 pins = "gpio52", "gpio53", 5236 "gpio54"; 5237 function = "qup17"; 5238 }; 5239 5240 qup_spi18_cs: qup-spi18-cs-state { 5241 pins = "gpio59"; 5242 function = "qup18"; 5243 }; 5244 5245 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state { 5246 pins = "gpio59"; 5247 function = "gpio"; 5248 }; 5249 5250 qup_spi18_data_clk: qup-spi18-data-clk-state { 5251 pins = "gpio56", "gpio57", 5252 "gpio58"; 5253 function = "qup18"; 5254 }; 5255 5256 qup_spi19_cs: qup-spi19-cs-state { 5257 pins = "gpio3"; 5258 function = "qup19"; 5259 }; 5260 5261 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state { 5262 pins = "gpio3"; 5263 function = "gpio"; 5264 }; 5265 5266 qup_spi19_data_clk: qup-spi19-data-clk-state { 5267 pins = "gpio0", "gpio1", 5268 "gpio2"; 5269 function = "qup19"; 5270 }; 5271 5272 qup_uart2_default: qup-uart2-default-state { 5273 pins = "gpio117", "gpio118"; 5274 function = "qup2"; 5275 }; 5276 5277 qup_uart6_default: qup-uart6-default-state { 5278 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 5279 function = "qup6"; 5280 }; 5281 5282 qup_uart12_default: qup-uart12-default-state { 5283 pins = "gpio34", "gpio35"; 5284 function = "qup12"; 5285 }; 5286 5287 qup_uart17_default: qup-uart17-default-state { 5288 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 5289 function = "qup17"; 5290 }; 5291 5292 qup_uart18_default: qup-uart18-default-state { 5293 pins = "gpio58", "gpio59"; 5294 function = "qup18"; 5295 }; 5296 5297 tert_mi2s_active: tert-mi2s-active-state { 5298 sck-pins { 5299 pins = "gpio133"; 5300 function = "mi2s2_sck"; 5301 drive-strength = <8>; 5302 bias-disable; 5303 }; 5304 5305 data0-pins { 5306 pins = "gpio134"; 5307 function = "mi2s2_data0"; 5308 drive-strength = <8>; 5309 bias-disable; 5310 output-high; 5311 }; 5312 5313 ws-pins { 5314 pins = "gpio135"; 5315 function = "mi2s2_ws"; 5316 drive-strength = <8>; 5317 output-high; 5318 }; 5319 }; 5320 5321 sdc2_sleep_state: sdc2-sleep-state { 5322 clk-pins { 5323 pins = "sdc2_clk"; 5324 drive-strength = <2>; 5325 bias-disable; 5326 }; 5327 5328 cmd-pins { 5329 pins = "sdc2_cmd"; 5330 drive-strength = <2>; 5331 bias-pull-up; 5332 }; 5333 5334 data-pins { 5335 pins = "sdc2_data"; 5336 drive-strength = <2>; 5337 bias-pull-up; 5338 }; 5339 }; 5340 5341 pcie0_default_state: pcie0-default-state { 5342 perst-pins { 5343 pins = "gpio79"; 5344 function = "gpio"; 5345 drive-strength = <2>; 5346 bias-pull-down; 5347 }; 5348 5349 clkreq-pins { 5350 pins = "gpio80"; 5351 function = "pci_e0"; 5352 drive-strength = <2>; 5353 bias-pull-up; 5354 }; 5355 5356 wake-pins { 5357 pins = "gpio81"; 5358 function = "gpio"; 5359 drive-strength = <2>; 5360 bias-pull-up; 5361 }; 5362 }; 5363 5364 pcie1_default_state: pcie1-default-state { 5365 perst-pins { 5366 pins = "gpio82"; 5367 function = "gpio"; 5368 drive-strength = <2>; 5369 bias-pull-down; 5370 }; 5371 5372 clkreq-pins { 5373 pins = "gpio83"; 5374 function = "pci_e1"; 5375 drive-strength = <2>; 5376 bias-pull-up; 5377 }; 5378 5379 wake-pins { 5380 pins = "gpio84"; 5381 function = "gpio"; 5382 drive-strength = <2>; 5383 bias-pull-up; 5384 }; 5385 }; 5386 5387 pcie2_default_state: pcie2-default-state { 5388 perst-pins { 5389 pins = "gpio85"; 5390 function = "gpio"; 5391 drive-strength = <2>; 5392 bias-pull-down; 5393 }; 5394 5395 clkreq-pins { 5396 pins = "gpio86"; 5397 function = "pci_e2"; 5398 drive-strength = <2>; 5399 bias-pull-up; 5400 }; 5401 5402 wake-pins { 5403 pins = "gpio87"; 5404 function = "gpio"; 5405 drive-strength = <2>; 5406 bias-pull-up; 5407 }; 5408 }; 5409 }; 5410 5411 apps_smmu: iommu@15000000 { 5412 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5413 reg = <0 0x15000000 0 0x100000>; 5414 #iommu-cells = <2>; 5415 #global-interrupts = <2>; 5416 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 5417 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5418 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5419 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5420 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5421 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5422 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5423 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5424 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5425 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5426 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5427 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5428 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5429 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5430 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5431 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5432 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5433 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5434 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5435 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5436 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5437 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5438 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5439 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5440 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5441 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5442 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5443 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5444 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5445 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5446 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5447 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5448 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5449 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5450 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5451 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5452 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5453 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5454 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5455 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5456 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5457 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5458 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5459 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5460 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5461 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5462 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5463 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5464 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5465 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5466 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5467 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5468 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5469 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5470 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5471 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5472 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5473 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5474 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5475 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5476 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5477 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5478 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5479 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5480 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5481 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5482 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5483 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5484 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5485 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5486 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5487 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5488 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5489 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5490 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5491 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5492 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5493 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5494 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5495 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5496 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5497 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5498 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5499 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5500 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5501 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5502 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5503 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5504 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5505 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5506 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5507 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5508 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5509 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5510 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5511 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5512 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 5513 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 5514 dma-coherent; 5515 }; 5516 5517 adsp: remoteproc@17300000 { 5518 compatible = "qcom,sm8250-adsp-pas"; 5519 reg = <0 0x17300000 0 0x100>; 5520 5521 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 5522 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 5523 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 5524 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 5525 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 5526 interrupt-names = "wdog", "fatal", "ready", 5527 "handover", "stop-ack"; 5528 5529 clocks = <&rpmhcc RPMH_CXO_CLK>; 5530 clock-names = "xo"; 5531 5532 power-domains = <&rpmhpd RPMHPD_LCX>, 5533 <&rpmhpd RPMHPD_LMX>; 5534 power-domain-names = "lcx", "lmx"; 5535 5536 memory-region = <&adsp_mem>; 5537 5538 qcom,qmp = <&aoss_qmp>; 5539 5540 qcom,smem-states = <&smp2p_adsp_out 0>; 5541 qcom,smem-state-names = "stop"; 5542 5543 status = "disabled"; 5544 5545 glink-edge { 5546 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 5547 IPCC_MPROC_SIGNAL_GLINK_QMP 5548 IRQ_TYPE_EDGE_RISING>; 5549 mboxes = <&ipcc IPCC_CLIENT_LPASS 5550 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5551 5552 label = "lpass"; 5553 qcom,remote-pid = <2>; 5554 5555 apr { 5556 compatible = "qcom,apr-v2"; 5557 qcom,glink-channels = "apr_audio_svc"; 5558 qcom,domain = <APR_DOMAIN_ADSP>; 5559 #address-cells = <1>; 5560 #size-cells = <0>; 5561 5562 service@3 { 5563 reg = <APR_SVC_ADSP_CORE>; 5564 compatible = "qcom,q6core"; 5565 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5566 }; 5567 5568 q6afe: service@4 { 5569 compatible = "qcom,q6afe"; 5570 reg = <APR_SVC_AFE>; 5571 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5572 q6afedai: dais { 5573 compatible = "qcom,q6afe-dais"; 5574 #address-cells = <1>; 5575 #size-cells = <0>; 5576 #sound-dai-cells = <1>; 5577 }; 5578 5579 q6afecc: clock-controller { 5580 compatible = "qcom,q6afe-clocks"; 5581 #clock-cells = <2>; 5582 }; 5583 }; 5584 5585 q6asm: service@7 { 5586 compatible = "qcom,q6asm"; 5587 reg = <APR_SVC_ASM>; 5588 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5589 q6asmdai: dais { 5590 compatible = "qcom,q6asm-dais"; 5591 #address-cells = <1>; 5592 #size-cells = <0>; 5593 #sound-dai-cells = <1>; 5594 iommus = <&apps_smmu 0x1801 0x0>; 5595 }; 5596 }; 5597 5598 q6adm: service@8 { 5599 compatible = "qcom,q6adm"; 5600 reg = <APR_SVC_ADM>; 5601 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5602 q6routing: routing { 5603 compatible = "qcom,q6adm-routing"; 5604 #sound-dai-cells = <0>; 5605 }; 5606 }; 5607 }; 5608 5609 fastrpc { 5610 compatible = "qcom,fastrpc"; 5611 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5612 label = "adsp"; 5613 qcom,non-secure-domain; 5614 #address-cells = <1>; 5615 #size-cells = <0>; 5616 5617 compute-cb@3 { 5618 compatible = "qcom,fastrpc-compute-cb"; 5619 reg = <3>; 5620 iommus = <&apps_smmu 0x1803 0x0>; 5621 }; 5622 5623 compute-cb@4 { 5624 compatible = "qcom,fastrpc-compute-cb"; 5625 reg = <4>; 5626 iommus = <&apps_smmu 0x1804 0x0>; 5627 }; 5628 5629 compute-cb@5 { 5630 compatible = "qcom,fastrpc-compute-cb"; 5631 reg = <5>; 5632 iommus = <&apps_smmu 0x1805 0x0>; 5633 }; 5634 }; 5635 }; 5636 }; 5637 5638 intc: interrupt-controller@17a00000 { 5639 compatible = "arm,gic-v3"; 5640 #interrupt-cells = <3>; 5641 interrupt-controller; 5642 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 5643 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 5644 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5645 }; 5646 5647 watchdog@17c10000 { 5648 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 5649 reg = <0 0x17c10000 0 0x1000>; 5650 clocks = <&sleep_clk>; 5651 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5652 }; 5653 5654 timer@17c20000 { 5655 #address-cells = <1>; 5656 #size-cells = <1>; 5657 ranges = <0 0 0 0x20000000>; 5658 compatible = "arm,armv7-timer-mem"; 5659 reg = <0x0 0x17c20000 0x0 0x1000>; 5660 clock-frequency = <19200000>; 5661 5662 frame@17c21000 { 5663 frame-number = <0>; 5664 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5665 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5666 reg = <0x17c21000 0x1000>, 5667 <0x17c22000 0x1000>; 5668 }; 5669 5670 frame@17c23000 { 5671 frame-number = <1>; 5672 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5673 reg = <0x17c23000 0x1000>; 5674 status = "disabled"; 5675 }; 5676 5677 frame@17c25000 { 5678 frame-number = <2>; 5679 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5680 reg = <0x17c25000 0x1000>; 5681 status = "disabled"; 5682 }; 5683 5684 frame@17c27000 { 5685 frame-number = <3>; 5686 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5687 reg = <0x17c27000 0x1000>; 5688 status = "disabled"; 5689 }; 5690 5691 frame@17c29000 { 5692 frame-number = <4>; 5693 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5694 reg = <0x17c29000 0x1000>; 5695 status = "disabled"; 5696 }; 5697 5698 frame@17c2b000 { 5699 frame-number = <5>; 5700 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5701 reg = <0x17c2b000 0x1000>; 5702 status = "disabled"; 5703 }; 5704 5705 frame@17c2d000 { 5706 frame-number = <6>; 5707 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5708 reg = <0x17c2d000 0x1000>; 5709 status = "disabled"; 5710 }; 5711 }; 5712 5713 apps_rsc: rsc@18200000 { 5714 label = "apps_rsc"; 5715 compatible = "qcom,rpmh-rsc"; 5716 reg = <0x0 0x18200000 0x0 0x10000>, 5717 <0x0 0x18210000 0x0 0x10000>, 5718 <0x0 0x18220000 0x0 0x10000>; 5719 reg-names = "drv-0", "drv-1", "drv-2"; 5720 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5721 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5722 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5723 qcom,tcs-offset = <0xd00>; 5724 qcom,drv-id = <2>; 5725 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 5726 <WAKE_TCS 3>, <CONTROL_TCS 1>; 5727 power-domains = <&CLUSTER_PD>; 5728 5729 rpmhcc: clock-controller { 5730 compatible = "qcom,sm8250-rpmh-clk"; 5731 #clock-cells = <1>; 5732 clock-names = "xo"; 5733 clocks = <&xo_board>; 5734 }; 5735 5736 rpmhpd: power-controller { 5737 compatible = "qcom,sm8250-rpmhpd"; 5738 #power-domain-cells = <1>; 5739 operating-points-v2 = <&rpmhpd_opp_table>; 5740 5741 rpmhpd_opp_table: opp-table { 5742 compatible = "operating-points-v2"; 5743 5744 rpmhpd_opp_ret: opp1 { 5745 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5746 }; 5747 5748 rpmhpd_opp_min_svs: opp2 { 5749 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5750 }; 5751 5752 rpmhpd_opp_low_svs: opp3 { 5753 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5754 }; 5755 5756 rpmhpd_opp_svs: opp4 { 5757 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5758 }; 5759 5760 rpmhpd_opp_svs_l1: opp5 { 5761 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5762 }; 5763 5764 rpmhpd_opp_nom: opp6 { 5765 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5766 }; 5767 5768 rpmhpd_opp_nom_l1: opp7 { 5769 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5770 }; 5771 5772 rpmhpd_opp_nom_l2: opp8 { 5773 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5774 }; 5775 5776 rpmhpd_opp_turbo: opp9 { 5777 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5778 }; 5779 5780 rpmhpd_opp_turbo_l1: opp10 { 5781 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5782 }; 5783 }; 5784 }; 5785 5786 apps_bcm_voter: bcm-voter { 5787 compatible = "qcom,bcm-voter"; 5788 }; 5789 }; 5790 5791 epss_l3: interconnect@18590000 { 5792 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3"; 5793 reg = <0 0x18590000 0 0x1000>; 5794 5795 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5796 clock-names = "xo", "alternate"; 5797 5798 #interconnect-cells = <1>; 5799 }; 5800 5801 cpufreq_hw: cpufreq@18591000 { 5802 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 5803 reg = <0 0x18591000 0 0x1000>, 5804 <0 0x18592000 0 0x1000>, 5805 <0 0x18593000 0 0x1000>; 5806 reg-names = "freq-domain0", "freq-domain1", 5807 "freq-domain2"; 5808 5809 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5810 clock-names = "xo", "alternate"; 5811 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5812 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5813 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5814 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 5815 #freq-domain-cells = <1>; 5816 #clock-cells = <1>; 5817 }; 5818 }; 5819 5820 sound: sound { 5821 }; 5822 5823 timer { 5824 compatible = "arm,armv8-timer"; 5825 interrupts = <GIC_PPI 13 5826 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5827 <GIC_PPI 14 5828 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5829 <GIC_PPI 11 5830 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5831 <GIC_PPI 10 5832 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5833 }; 5834 5835 thermal-zones { 5836 cpu0-thermal { 5837 polling-delay-passive = <250>; 5838 polling-delay = <1000>; 5839 5840 thermal-sensors = <&tsens0 1>; 5841 5842 trips { 5843 cpu0_alert0: trip-point0 { 5844 temperature = <90000>; 5845 hysteresis = <2000>; 5846 type = "passive"; 5847 }; 5848 5849 cpu0_alert1: trip-point1 { 5850 temperature = <95000>; 5851 hysteresis = <2000>; 5852 type = "passive"; 5853 }; 5854 5855 cpu0_crit: cpu-crit { 5856 temperature = <110000>; 5857 hysteresis = <1000>; 5858 type = "critical"; 5859 }; 5860 }; 5861 5862 cooling-maps { 5863 map0 { 5864 trip = <&cpu0_alert0>; 5865 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5866 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5867 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5868 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5869 }; 5870 map1 { 5871 trip = <&cpu0_alert1>; 5872 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5873 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5874 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5875 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5876 }; 5877 }; 5878 }; 5879 5880 cpu1-thermal { 5881 polling-delay-passive = <250>; 5882 polling-delay = <1000>; 5883 5884 thermal-sensors = <&tsens0 2>; 5885 5886 trips { 5887 cpu1_alert0: trip-point0 { 5888 temperature = <90000>; 5889 hysteresis = <2000>; 5890 type = "passive"; 5891 }; 5892 5893 cpu1_alert1: trip-point1 { 5894 temperature = <95000>; 5895 hysteresis = <2000>; 5896 type = "passive"; 5897 }; 5898 5899 cpu1_crit: cpu-crit { 5900 temperature = <110000>; 5901 hysteresis = <1000>; 5902 type = "critical"; 5903 }; 5904 }; 5905 5906 cooling-maps { 5907 map0 { 5908 trip = <&cpu1_alert0>; 5909 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5910 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5911 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5912 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5913 }; 5914 map1 { 5915 trip = <&cpu1_alert1>; 5916 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5917 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5918 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5919 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5920 }; 5921 }; 5922 }; 5923 5924 cpu2-thermal { 5925 polling-delay-passive = <250>; 5926 polling-delay = <1000>; 5927 5928 thermal-sensors = <&tsens0 3>; 5929 5930 trips { 5931 cpu2_alert0: trip-point0 { 5932 temperature = <90000>; 5933 hysteresis = <2000>; 5934 type = "passive"; 5935 }; 5936 5937 cpu2_alert1: trip-point1 { 5938 temperature = <95000>; 5939 hysteresis = <2000>; 5940 type = "passive"; 5941 }; 5942 5943 cpu2_crit: cpu-crit { 5944 temperature = <110000>; 5945 hysteresis = <1000>; 5946 type = "critical"; 5947 }; 5948 }; 5949 5950 cooling-maps { 5951 map0 { 5952 trip = <&cpu2_alert0>; 5953 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5954 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5955 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5956 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5957 }; 5958 map1 { 5959 trip = <&cpu2_alert1>; 5960 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5961 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5962 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5963 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5964 }; 5965 }; 5966 }; 5967 5968 cpu3-thermal { 5969 polling-delay-passive = <250>; 5970 polling-delay = <1000>; 5971 5972 thermal-sensors = <&tsens0 4>; 5973 5974 trips { 5975 cpu3_alert0: trip-point0 { 5976 temperature = <90000>; 5977 hysteresis = <2000>; 5978 type = "passive"; 5979 }; 5980 5981 cpu3_alert1: trip-point1 { 5982 temperature = <95000>; 5983 hysteresis = <2000>; 5984 type = "passive"; 5985 }; 5986 5987 cpu3_crit: cpu-crit { 5988 temperature = <110000>; 5989 hysteresis = <1000>; 5990 type = "critical"; 5991 }; 5992 }; 5993 5994 cooling-maps { 5995 map0 { 5996 trip = <&cpu3_alert0>; 5997 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5998 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5999 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6000 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6001 }; 6002 map1 { 6003 trip = <&cpu3_alert1>; 6004 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6005 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6006 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6007 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6008 }; 6009 }; 6010 }; 6011 6012 cpu4-top-thermal { 6013 polling-delay-passive = <250>; 6014 polling-delay = <1000>; 6015 6016 thermal-sensors = <&tsens0 7>; 6017 6018 trips { 6019 cpu4_top_alert0: trip-point0 { 6020 temperature = <90000>; 6021 hysteresis = <2000>; 6022 type = "passive"; 6023 }; 6024 6025 cpu4_top_alert1: trip-point1 { 6026 temperature = <95000>; 6027 hysteresis = <2000>; 6028 type = "passive"; 6029 }; 6030 6031 cpu4_top_crit: cpu-crit { 6032 temperature = <110000>; 6033 hysteresis = <1000>; 6034 type = "critical"; 6035 }; 6036 }; 6037 6038 cooling-maps { 6039 map0 { 6040 trip = <&cpu4_top_alert0>; 6041 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6042 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6043 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6044 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6045 }; 6046 map1 { 6047 trip = <&cpu4_top_alert1>; 6048 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6049 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6050 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6051 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6052 }; 6053 }; 6054 }; 6055 6056 cpu5-top-thermal { 6057 polling-delay-passive = <250>; 6058 polling-delay = <1000>; 6059 6060 thermal-sensors = <&tsens0 8>; 6061 6062 trips { 6063 cpu5_top_alert0: trip-point0 { 6064 temperature = <90000>; 6065 hysteresis = <2000>; 6066 type = "passive"; 6067 }; 6068 6069 cpu5_top_alert1: trip-point1 { 6070 temperature = <95000>; 6071 hysteresis = <2000>; 6072 type = "passive"; 6073 }; 6074 6075 cpu5_top_crit: cpu-crit { 6076 temperature = <110000>; 6077 hysteresis = <1000>; 6078 type = "critical"; 6079 }; 6080 }; 6081 6082 cooling-maps { 6083 map0 { 6084 trip = <&cpu5_top_alert0>; 6085 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6086 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6087 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6088 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6089 }; 6090 map1 { 6091 trip = <&cpu5_top_alert1>; 6092 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6093 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6094 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6095 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6096 }; 6097 }; 6098 }; 6099 6100 cpu6-top-thermal { 6101 polling-delay-passive = <250>; 6102 polling-delay = <1000>; 6103 6104 thermal-sensors = <&tsens0 9>; 6105 6106 trips { 6107 cpu6_top_alert0: trip-point0 { 6108 temperature = <90000>; 6109 hysteresis = <2000>; 6110 type = "passive"; 6111 }; 6112 6113 cpu6_top_alert1: trip-point1 { 6114 temperature = <95000>; 6115 hysteresis = <2000>; 6116 type = "passive"; 6117 }; 6118 6119 cpu6_top_crit: cpu-crit { 6120 temperature = <110000>; 6121 hysteresis = <1000>; 6122 type = "critical"; 6123 }; 6124 }; 6125 6126 cooling-maps { 6127 map0 { 6128 trip = <&cpu6_top_alert0>; 6129 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6130 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6131 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6132 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6133 }; 6134 map1 { 6135 trip = <&cpu6_top_alert1>; 6136 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6137 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6138 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6139 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6140 }; 6141 }; 6142 }; 6143 6144 cpu7-top-thermal { 6145 polling-delay-passive = <250>; 6146 polling-delay = <1000>; 6147 6148 thermal-sensors = <&tsens0 10>; 6149 6150 trips { 6151 cpu7_top_alert0: trip-point0 { 6152 temperature = <90000>; 6153 hysteresis = <2000>; 6154 type = "passive"; 6155 }; 6156 6157 cpu7_top_alert1: trip-point1 { 6158 temperature = <95000>; 6159 hysteresis = <2000>; 6160 type = "passive"; 6161 }; 6162 6163 cpu7_top_crit: cpu-crit { 6164 temperature = <110000>; 6165 hysteresis = <1000>; 6166 type = "critical"; 6167 }; 6168 }; 6169 6170 cooling-maps { 6171 map0 { 6172 trip = <&cpu7_top_alert0>; 6173 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6174 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6175 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6176 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6177 }; 6178 map1 { 6179 trip = <&cpu7_top_alert1>; 6180 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6181 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6182 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6183 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6184 }; 6185 }; 6186 }; 6187 6188 cpu4-bottom-thermal { 6189 polling-delay-passive = <250>; 6190 polling-delay = <1000>; 6191 6192 thermal-sensors = <&tsens0 11>; 6193 6194 trips { 6195 cpu4_bottom_alert0: trip-point0 { 6196 temperature = <90000>; 6197 hysteresis = <2000>; 6198 type = "passive"; 6199 }; 6200 6201 cpu4_bottom_alert1: trip-point1 { 6202 temperature = <95000>; 6203 hysteresis = <2000>; 6204 type = "passive"; 6205 }; 6206 6207 cpu4_bottom_crit: cpu-crit { 6208 temperature = <110000>; 6209 hysteresis = <1000>; 6210 type = "critical"; 6211 }; 6212 }; 6213 6214 cooling-maps { 6215 map0 { 6216 trip = <&cpu4_bottom_alert0>; 6217 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6218 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6219 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6220 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6221 }; 6222 map1 { 6223 trip = <&cpu4_bottom_alert1>; 6224 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6225 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6226 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6227 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6228 }; 6229 }; 6230 }; 6231 6232 cpu5-bottom-thermal { 6233 polling-delay-passive = <250>; 6234 polling-delay = <1000>; 6235 6236 thermal-sensors = <&tsens0 12>; 6237 6238 trips { 6239 cpu5_bottom_alert0: trip-point0 { 6240 temperature = <90000>; 6241 hysteresis = <2000>; 6242 type = "passive"; 6243 }; 6244 6245 cpu5_bottom_alert1: trip-point1 { 6246 temperature = <95000>; 6247 hysteresis = <2000>; 6248 type = "passive"; 6249 }; 6250 6251 cpu5_bottom_crit: cpu-crit { 6252 temperature = <110000>; 6253 hysteresis = <1000>; 6254 type = "critical"; 6255 }; 6256 }; 6257 6258 cooling-maps { 6259 map0 { 6260 trip = <&cpu5_bottom_alert0>; 6261 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6262 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6263 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6264 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6265 }; 6266 map1 { 6267 trip = <&cpu5_bottom_alert1>; 6268 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6269 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6270 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6271 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6272 }; 6273 }; 6274 }; 6275 6276 cpu6-bottom-thermal { 6277 polling-delay-passive = <250>; 6278 polling-delay = <1000>; 6279 6280 thermal-sensors = <&tsens0 13>; 6281 6282 trips { 6283 cpu6_bottom_alert0: trip-point0 { 6284 temperature = <90000>; 6285 hysteresis = <2000>; 6286 type = "passive"; 6287 }; 6288 6289 cpu6_bottom_alert1: trip-point1 { 6290 temperature = <95000>; 6291 hysteresis = <2000>; 6292 type = "passive"; 6293 }; 6294 6295 cpu6_bottom_crit: cpu-crit { 6296 temperature = <110000>; 6297 hysteresis = <1000>; 6298 type = "critical"; 6299 }; 6300 }; 6301 6302 cooling-maps { 6303 map0 { 6304 trip = <&cpu6_bottom_alert0>; 6305 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6306 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6307 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6308 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6309 }; 6310 map1 { 6311 trip = <&cpu6_bottom_alert1>; 6312 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6313 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6314 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6315 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6316 }; 6317 }; 6318 }; 6319 6320 cpu7-bottom-thermal { 6321 polling-delay-passive = <250>; 6322 polling-delay = <1000>; 6323 6324 thermal-sensors = <&tsens0 14>; 6325 6326 trips { 6327 cpu7_bottom_alert0: trip-point0 { 6328 temperature = <90000>; 6329 hysteresis = <2000>; 6330 type = "passive"; 6331 }; 6332 6333 cpu7_bottom_alert1: trip-point1 { 6334 temperature = <95000>; 6335 hysteresis = <2000>; 6336 type = "passive"; 6337 }; 6338 6339 cpu7_bottom_crit: cpu-crit { 6340 temperature = <110000>; 6341 hysteresis = <1000>; 6342 type = "critical"; 6343 }; 6344 }; 6345 6346 cooling-maps { 6347 map0 { 6348 trip = <&cpu7_bottom_alert0>; 6349 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6350 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6351 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6352 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6353 }; 6354 map1 { 6355 trip = <&cpu7_bottom_alert1>; 6356 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6357 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6358 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6359 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6360 }; 6361 }; 6362 }; 6363 6364 aoss0-thermal { 6365 polling-delay-passive = <250>; 6366 polling-delay = <1000>; 6367 6368 thermal-sensors = <&tsens0 0>; 6369 6370 trips { 6371 aoss0_alert0: trip-point0 { 6372 temperature = <90000>; 6373 hysteresis = <2000>; 6374 type = "hot"; 6375 }; 6376 }; 6377 }; 6378 6379 cluster0-thermal { 6380 polling-delay-passive = <250>; 6381 polling-delay = <1000>; 6382 6383 thermal-sensors = <&tsens0 5>; 6384 6385 trips { 6386 cluster0_alert0: trip-point0 { 6387 temperature = <90000>; 6388 hysteresis = <2000>; 6389 type = "hot"; 6390 }; 6391 cluster0_crit: cluster0_crit { 6392 temperature = <110000>; 6393 hysteresis = <2000>; 6394 type = "critical"; 6395 }; 6396 }; 6397 }; 6398 6399 cluster1-thermal { 6400 polling-delay-passive = <250>; 6401 polling-delay = <1000>; 6402 6403 thermal-sensors = <&tsens0 6>; 6404 6405 trips { 6406 cluster1_alert0: trip-point0 { 6407 temperature = <90000>; 6408 hysteresis = <2000>; 6409 type = "hot"; 6410 }; 6411 cluster1_crit: cluster1_crit { 6412 temperature = <110000>; 6413 hysteresis = <2000>; 6414 type = "critical"; 6415 }; 6416 }; 6417 }; 6418 6419 gpu-top-thermal { 6420 polling-delay-passive = <250>; 6421 polling-delay = <1000>; 6422 6423 thermal-sensors = <&tsens0 15>; 6424 6425 trips { 6426 gpu1_alert0: trip-point0 { 6427 temperature = <90000>; 6428 hysteresis = <2000>; 6429 type = "hot"; 6430 }; 6431 }; 6432 }; 6433 6434 aoss1-thermal { 6435 polling-delay-passive = <250>; 6436 polling-delay = <1000>; 6437 6438 thermal-sensors = <&tsens1 0>; 6439 6440 trips { 6441 aoss1_alert0: trip-point0 { 6442 temperature = <90000>; 6443 hysteresis = <2000>; 6444 type = "hot"; 6445 }; 6446 }; 6447 }; 6448 6449 wlan-thermal { 6450 polling-delay-passive = <250>; 6451 polling-delay = <1000>; 6452 6453 thermal-sensors = <&tsens1 1>; 6454 6455 trips { 6456 wlan_alert0: trip-point0 { 6457 temperature = <90000>; 6458 hysteresis = <2000>; 6459 type = "hot"; 6460 }; 6461 }; 6462 }; 6463 6464 video-thermal { 6465 polling-delay-passive = <250>; 6466 polling-delay = <1000>; 6467 6468 thermal-sensors = <&tsens1 2>; 6469 6470 trips { 6471 video_alert0: trip-point0 { 6472 temperature = <90000>; 6473 hysteresis = <2000>; 6474 type = "hot"; 6475 }; 6476 }; 6477 }; 6478 6479 mem-thermal { 6480 polling-delay-passive = <250>; 6481 polling-delay = <1000>; 6482 6483 thermal-sensors = <&tsens1 3>; 6484 6485 trips { 6486 mem_alert0: trip-point0 { 6487 temperature = <90000>; 6488 hysteresis = <2000>; 6489 type = "hot"; 6490 }; 6491 }; 6492 }; 6493 6494 q6-hvx-thermal { 6495 polling-delay-passive = <250>; 6496 polling-delay = <1000>; 6497 6498 thermal-sensors = <&tsens1 4>; 6499 6500 trips { 6501 q6_hvx_alert0: trip-point0 { 6502 temperature = <90000>; 6503 hysteresis = <2000>; 6504 type = "hot"; 6505 }; 6506 }; 6507 }; 6508 6509 camera-thermal { 6510 polling-delay-passive = <250>; 6511 polling-delay = <1000>; 6512 6513 thermal-sensors = <&tsens1 5>; 6514 6515 trips { 6516 camera_alert0: trip-point0 { 6517 temperature = <90000>; 6518 hysteresis = <2000>; 6519 type = "hot"; 6520 }; 6521 }; 6522 }; 6523 6524 compute-thermal { 6525 polling-delay-passive = <250>; 6526 polling-delay = <1000>; 6527 6528 thermal-sensors = <&tsens1 6>; 6529 6530 trips { 6531 compute_alert0: trip-point0 { 6532 temperature = <90000>; 6533 hysteresis = <2000>; 6534 type = "hot"; 6535 }; 6536 }; 6537 }; 6538 6539 npu-thermal { 6540 polling-delay-passive = <250>; 6541 polling-delay = <1000>; 6542 6543 thermal-sensors = <&tsens1 7>; 6544 6545 trips { 6546 npu_alert0: trip-point0 { 6547 temperature = <90000>; 6548 hysteresis = <2000>; 6549 type = "hot"; 6550 }; 6551 }; 6552 }; 6553 6554 gpu-bottom-thermal { 6555 polling-delay-passive = <250>; 6556 polling-delay = <1000>; 6557 6558 thermal-sensors = <&tsens1 8>; 6559 6560 trips { 6561 gpu2_alert0: trip-point0 { 6562 temperature = <90000>; 6563 hysteresis = <2000>; 6564 type = "hot"; 6565 }; 6566 }; 6567 }; 6568 }; 6569}; 6570