1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/interconnect/qcom,osm-l3.h> 12#include <dt-bindings/interconnect/qcom,sm8250.h> 13#include <dt-bindings/mailbox/qcom-ipcc.h> 14#include <dt-bindings/power/qcom-aoss-qmp.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/soc/qcom,apr.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18#include <dt-bindings/sound/qcom,q6afe.h> 19#include <dt-bindings/thermal/thermal.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 aliases { 28 i2c0 = &i2c0; 29 i2c1 = &i2c1; 30 i2c2 = &i2c2; 31 i2c3 = &i2c3; 32 i2c4 = &i2c4; 33 i2c5 = &i2c5; 34 i2c6 = &i2c6; 35 i2c7 = &i2c7; 36 i2c8 = &i2c8; 37 i2c9 = &i2c9; 38 i2c10 = &i2c10; 39 i2c11 = &i2c11; 40 i2c12 = &i2c12; 41 i2c13 = &i2c13; 42 i2c14 = &i2c14; 43 i2c15 = &i2c15; 44 i2c16 = &i2c16; 45 i2c17 = &i2c17; 46 i2c18 = &i2c18; 47 i2c19 = &i2c19; 48 spi0 = &spi0; 49 spi1 = &spi1; 50 spi2 = &spi2; 51 spi3 = &spi3; 52 spi4 = &spi4; 53 spi5 = &spi5; 54 spi6 = &spi6; 55 spi7 = &spi7; 56 spi8 = &spi8; 57 spi9 = &spi9; 58 spi10 = &spi10; 59 spi11 = &spi11; 60 spi12 = &spi12; 61 spi13 = &spi13; 62 spi14 = &spi14; 63 spi15 = &spi15; 64 spi16 = &spi16; 65 spi17 = &spi17; 66 spi18 = &spi18; 67 spi19 = &spi19; 68 }; 69 70 chosen { }; 71 72 clocks { 73 xo_board: xo-board { 74 compatible = "fixed-clock"; 75 #clock-cells = <0>; 76 clock-frequency = <38400000>; 77 clock-output-names = "xo_board"; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32768>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 cpus { 88 #address-cells = <2>; 89 #size-cells = <0>; 90 91 CPU0: cpu@0 { 92 device_type = "cpu"; 93 compatible = "qcom,kryo485"; 94 reg = <0x0 0x0>; 95 enable-method = "psci"; 96 capacity-dmips-mhz = <448>; 97 dynamic-power-coefficient = <205>; 98 next-level-cache = <&L2_0>; 99 qcom,freq-domain = <&cpufreq_hw 0>; 100 #cooling-cells = <2>; 101 L2_0: l2-cache { 102 compatible = "cache"; 103 next-level-cache = <&L3_0>; 104 L3_0: l3-cache { 105 compatible = "cache"; 106 }; 107 }; 108 }; 109 110 CPU1: cpu@100 { 111 device_type = "cpu"; 112 compatible = "qcom,kryo485"; 113 reg = <0x0 0x100>; 114 enable-method = "psci"; 115 capacity-dmips-mhz = <448>; 116 dynamic-power-coefficient = <205>; 117 next-level-cache = <&L2_100>; 118 qcom,freq-domain = <&cpufreq_hw 0>; 119 #cooling-cells = <2>; 120 L2_100: l2-cache { 121 compatible = "cache"; 122 next-level-cache = <&L3_0>; 123 }; 124 }; 125 126 CPU2: cpu@200 { 127 device_type = "cpu"; 128 compatible = "qcom,kryo485"; 129 reg = <0x0 0x200>; 130 enable-method = "psci"; 131 capacity-dmips-mhz = <448>; 132 dynamic-power-coefficient = <205>; 133 next-level-cache = <&L2_200>; 134 qcom,freq-domain = <&cpufreq_hw 0>; 135 #cooling-cells = <2>; 136 L2_200: l2-cache { 137 compatible = "cache"; 138 next-level-cache = <&L3_0>; 139 }; 140 }; 141 142 CPU3: cpu@300 { 143 device_type = "cpu"; 144 compatible = "qcom,kryo485"; 145 reg = <0x0 0x300>; 146 enable-method = "psci"; 147 capacity-dmips-mhz = <448>; 148 dynamic-power-coefficient = <205>; 149 next-level-cache = <&L2_300>; 150 qcom,freq-domain = <&cpufreq_hw 0>; 151 #cooling-cells = <2>; 152 L2_300: l2-cache { 153 compatible = "cache"; 154 next-level-cache = <&L3_0>; 155 }; 156 }; 157 158 CPU4: cpu@400 { 159 device_type = "cpu"; 160 compatible = "qcom,kryo485"; 161 reg = <0x0 0x400>; 162 enable-method = "psci"; 163 capacity-dmips-mhz = <1024>; 164 dynamic-power-coefficient = <379>; 165 next-level-cache = <&L2_400>; 166 qcom,freq-domain = <&cpufreq_hw 1>; 167 #cooling-cells = <2>; 168 L2_400: l2-cache { 169 compatible = "cache"; 170 next-level-cache = <&L3_0>; 171 }; 172 }; 173 174 CPU5: cpu@500 { 175 device_type = "cpu"; 176 compatible = "qcom,kryo485"; 177 reg = <0x0 0x500>; 178 enable-method = "psci"; 179 capacity-dmips-mhz = <1024>; 180 dynamic-power-coefficient = <379>; 181 next-level-cache = <&L2_500>; 182 qcom,freq-domain = <&cpufreq_hw 1>; 183 #cooling-cells = <2>; 184 L2_500: l2-cache { 185 compatible = "cache"; 186 next-level-cache = <&L3_0>; 187 }; 188 189 }; 190 191 CPU6: cpu@600 { 192 device_type = "cpu"; 193 compatible = "qcom,kryo485"; 194 reg = <0x0 0x600>; 195 enable-method = "psci"; 196 capacity-dmips-mhz = <1024>; 197 dynamic-power-coefficient = <379>; 198 next-level-cache = <&L2_600>; 199 qcom,freq-domain = <&cpufreq_hw 1>; 200 #cooling-cells = <2>; 201 L2_600: l2-cache { 202 compatible = "cache"; 203 next-level-cache = <&L3_0>; 204 }; 205 }; 206 207 CPU7: cpu@700 { 208 device_type = "cpu"; 209 compatible = "qcom,kryo485"; 210 reg = <0x0 0x700>; 211 enable-method = "psci"; 212 capacity-dmips-mhz = <1024>; 213 dynamic-power-coefficient = <444>; 214 next-level-cache = <&L2_700>; 215 qcom,freq-domain = <&cpufreq_hw 2>; 216 #cooling-cells = <2>; 217 L2_700: l2-cache { 218 compatible = "cache"; 219 next-level-cache = <&L3_0>; 220 }; 221 }; 222 223 cpu-map { 224 cluster0 { 225 core0 { 226 cpu = <&CPU0>; 227 }; 228 229 core1 { 230 cpu = <&CPU1>; 231 }; 232 233 core2 { 234 cpu = <&CPU2>; 235 }; 236 237 core3 { 238 cpu = <&CPU3>; 239 }; 240 241 core4 { 242 cpu = <&CPU4>; 243 }; 244 245 core5 { 246 cpu = <&CPU5>; 247 }; 248 249 core6 { 250 cpu = <&CPU6>; 251 }; 252 253 core7 { 254 cpu = <&CPU7>; 255 }; 256 }; 257 }; 258 }; 259 260 firmware { 261 scm: scm { 262 compatible = "qcom,scm"; 263 #reset-cells = <1>; 264 }; 265 }; 266 267 memory@80000000 { 268 device_type = "memory"; 269 /* We expect the bootloader to fill in the size */ 270 reg = <0x0 0x80000000 0x0 0x0>; 271 }; 272 273 mmcx_reg: mmcx-reg { 274 compatible = "regulator-fixed-domain"; 275 power-domains = <&rpmhpd SM8250_MMCX>; 276 required-opps = <&rpmhpd_opp_low_svs>; 277 regulator-name = "MMCX"; 278 }; 279 280 pmu { 281 compatible = "arm,armv8-pmuv3"; 282 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 283 }; 284 285 psci { 286 compatible = "arm,psci-1.0"; 287 method = "smc"; 288 }; 289 290 reserved-memory { 291 #address-cells = <2>; 292 #size-cells = <2>; 293 ranges; 294 295 hyp_mem: memory@80000000 { 296 reg = <0x0 0x80000000 0x0 0x600000>; 297 no-map; 298 }; 299 300 xbl_aop_mem: memory@80700000 { 301 reg = <0x0 0x80700000 0x0 0x160000>; 302 no-map; 303 }; 304 305 cmd_db: memory@80860000 { 306 compatible = "qcom,cmd-db"; 307 reg = <0x0 0x80860000 0x0 0x20000>; 308 no-map; 309 }; 310 311 smem_mem: memory@80900000 { 312 reg = <0x0 0x80900000 0x0 0x200000>; 313 no-map; 314 }; 315 316 removed_mem: memory@80b00000 { 317 reg = <0x0 0x80b00000 0x0 0x5300000>; 318 no-map; 319 }; 320 321 camera_mem: memory@86200000 { 322 reg = <0x0 0x86200000 0x0 0x500000>; 323 no-map; 324 }; 325 326 wlan_mem: memory@86700000 { 327 reg = <0x0 0x86700000 0x0 0x100000>; 328 no-map; 329 }; 330 331 ipa_fw_mem: memory@86800000 { 332 reg = <0x0 0x86800000 0x0 0x10000>; 333 no-map; 334 }; 335 336 ipa_gsi_mem: memory@86810000 { 337 reg = <0x0 0x86810000 0x0 0xa000>; 338 no-map; 339 }; 340 341 gpu_mem: memory@8681a000 { 342 reg = <0x0 0x8681a000 0x0 0x2000>; 343 no-map; 344 }; 345 346 npu_mem: memory@86900000 { 347 reg = <0x0 0x86900000 0x0 0x500000>; 348 no-map; 349 }; 350 351 video_mem: memory@86e00000 { 352 reg = <0x0 0x86e00000 0x0 0x500000>; 353 no-map; 354 }; 355 356 cvp_mem: memory@87300000 { 357 reg = <0x0 0x87300000 0x0 0x500000>; 358 no-map; 359 }; 360 361 cdsp_mem: memory@87800000 { 362 reg = <0x0 0x87800000 0x0 0x1400000>; 363 no-map; 364 }; 365 366 slpi_mem: memory@88c00000 { 367 reg = <0x0 0x88c00000 0x0 0x1500000>; 368 no-map; 369 }; 370 371 adsp_mem: memory@8a100000 { 372 reg = <0x0 0x8a100000 0x0 0x1d00000>; 373 no-map; 374 }; 375 376 spss_mem: memory@8be00000 { 377 reg = <0x0 0x8be00000 0x0 0x100000>; 378 no-map; 379 }; 380 381 cdsp_secure_heap: memory@8bf00000 { 382 reg = <0x0 0x8bf00000 0x0 0x4600000>; 383 no-map; 384 }; 385 }; 386 387 smem { 388 compatible = "qcom,smem"; 389 memory-region = <&smem_mem>; 390 hwlocks = <&tcsr_mutex 3>; 391 }; 392 393 smp2p-adsp { 394 compatible = "qcom,smp2p"; 395 qcom,smem = <443>, <429>; 396 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 397 IPCC_MPROC_SIGNAL_SMP2P 398 IRQ_TYPE_EDGE_RISING>; 399 mboxes = <&ipcc IPCC_CLIENT_LPASS 400 IPCC_MPROC_SIGNAL_SMP2P>; 401 402 qcom,local-pid = <0>; 403 qcom,remote-pid = <2>; 404 405 smp2p_adsp_out: master-kernel { 406 qcom,entry-name = "master-kernel"; 407 #qcom,smem-state-cells = <1>; 408 }; 409 410 smp2p_adsp_in: slave-kernel { 411 qcom,entry-name = "slave-kernel"; 412 interrupt-controller; 413 #interrupt-cells = <2>; 414 }; 415 }; 416 417 smp2p-cdsp { 418 compatible = "qcom,smp2p"; 419 qcom,smem = <94>, <432>; 420 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 421 IPCC_MPROC_SIGNAL_SMP2P 422 IRQ_TYPE_EDGE_RISING>; 423 mboxes = <&ipcc IPCC_CLIENT_CDSP 424 IPCC_MPROC_SIGNAL_SMP2P>; 425 426 qcom,local-pid = <0>; 427 qcom,remote-pid = <5>; 428 429 smp2p_cdsp_out: master-kernel { 430 qcom,entry-name = "master-kernel"; 431 #qcom,smem-state-cells = <1>; 432 }; 433 434 smp2p_cdsp_in: slave-kernel { 435 qcom,entry-name = "slave-kernel"; 436 interrupt-controller; 437 #interrupt-cells = <2>; 438 }; 439 }; 440 441 smp2p-slpi { 442 compatible = "qcom,smp2p"; 443 qcom,smem = <481>, <430>; 444 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 445 IPCC_MPROC_SIGNAL_SMP2P 446 IRQ_TYPE_EDGE_RISING>; 447 mboxes = <&ipcc IPCC_CLIENT_SLPI 448 IPCC_MPROC_SIGNAL_SMP2P>; 449 450 qcom,local-pid = <0>; 451 qcom,remote-pid = <3>; 452 453 smp2p_slpi_out: master-kernel { 454 qcom,entry-name = "master-kernel"; 455 #qcom,smem-state-cells = <1>; 456 }; 457 458 smp2p_slpi_in: slave-kernel { 459 qcom,entry-name = "slave-kernel"; 460 interrupt-controller; 461 #interrupt-cells = <2>; 462 }; 463 }; 464 465 soc: soc@0 { 466 #address-cells = <2>; 467 #size-cells = <2>; 468 ranges = <0 0 0 0 0x10 0>; 469 dma-ranges = <0 0 0 0 0x10 0>; 470 compatible = "simple-bus"; 471 472 gcc: clock-controller@100000 { 473 compatible = "qcom,gcc-sm8250"; 474 reg = <0x0 0x00100000 0x0 0x1f0000>; 475 #clock-cells = <1>; 476 #reset-cells = <1>; 477 #power-domain-cells = <1>; 478 clock-names = "bi_tcxo", 479 "bi_tcxo_ao", 480 "sleep_clk"; 481 clocks = <&rpmhcc RPMH_CXO_CLK>, 482 <&rpmhcc RPMH_CXO_CLK_A>, 483 <&sleep_clk>; 484 }; 485 486 ipcc: mailbox@408000 { 487 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 488 reg = <0 0x00408000 0 0x1000>; 489 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 490 interrupt-controller; 491 #interrupt-cells = <3>; 492 #mbox-cells = <2>; 493 }; 494 495 rng: rng@793000 { 496 compatible = "qcom,prng-ee"; 497 reg = <0 0x00793000 0 0x1000>; 498 clocks = <&gcc GCC_PRNG_AHB_CLK>; 499 clock-names = "core"; 500 }; 501 502 qup_opp_table: qup-opp-table { 503 compatible = "operating-points-v2"; 504 505 opp-50000000 { 506 opp-hz = /bits/ 64 <50000000>; 507 required-opps = <&rpmhpd_opp_min_svs>; 508 }; 509 510 opp-75000000 { 511 opp-hz = /bits/ 64 <75000000>; 512 required-opps = <&rpmhpd_opp_low_svs>; 513 }; 514 515 opp-120000000 { 516 opp-hz = /bits/ 64 <120000000>; 517 required-opps = <&rpmhpd_opp_svs>; 518 }; 519 }; 520 521 qupv3_id_2: geniqup@8c0000 { 522 compatible = "qcom,geni-se-qup"; 523 reg = <0x0 0x008c0000 0x0 0x6000>; 524 clock-names = "m-ahb", "s-ahb"; 525 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 526 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 527 #address-cells = <2>; 528 #size-cells = <2>; 529 iommus = <&apps_smmu 0x63 0x0>; 530 ranges; 531 status = "disabled"; 532 533 i2c14: i2c@880000 { 534 compatible = "qcom,geni-i2c"; 535 reg = <0 0x00880000 0 0x4000>; 536 clock-names = "se"; 537 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 538 pinctrl-names = "default"; 539 pinctrl-0 = <&qup_i2c14_default>; 540 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 status = "disabled"; 544 }; 545 546 spi14: spi@880000 { 547 compatible = "qcom,geni-spi"; 548 reg = <0 0x00880000 0 0x4000>; 549 clock-names = "se"; 550 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 551 pinctrl-names = "default"; 552 pinctrl-0 = <&qup_spi14_default>; 553 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 power-domains = <&rpmhpd SM8250_CX>; 557 operating-points-v2 = <&qup_opp_table>; 558 status = "disabled"; 559 }; 560 561 i2c15: i2c@884000 { 562 compatible = "qcom,geni-i2c"; 563 reg = <0 0x00884000 0 0x4000>; 564 clock-names = "se"; 565 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 566 pinctrl-names = "default"; 567 pinctrl-0 = <&qup_i2c15_default>; 568 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 569 #address-cells = <1>; 570 #size-cells = <0>; 571 status = "disabled"; 572 }; 573 574 spi15: spi@884000 { 575 compatible = "qcom,geni-spi"; 576 reg = <0 0x00884000 0 0x4000>; 577 clock-names = "se"; 578 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 579 pinctrl-names = "default"; 580 pinctrl-0 = <&qup_spi15_default>; 581 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 power-domains = <&rpmhpd SM8250_CX>; 585 operating-points-v2 = <&qup_opp_table>; 586 status = "disabled"; 587 }; 588 589 i2c16: i2c@888000 { 590 compatible = "qcom,geni-i2c"; 591 reg = <0 0x00888000 0 0x4000>; 592 clock-names = "se"; 593 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 594 pinctrl-names = "default"; 595 pinctrl-0 = <&qup_i2c16_default>; 596 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 status = "disabled"; 600 }; 601 602 spi16: spi@888000 { 603 compatible = "qcom,geni-spi"; 604 reg = <0 0x00888000 0 0x4000>; 605 clock-names = "se"; 606 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 607 pinctrl-names = "default"; 608 pinctrl-0 = <&qup_spi16_default>; 609 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 power-domains = <&rpmhpd SM8250_CX>; 613 operating-points-v2 = <&qup_opp_table>; 614 status = "disabled"; 615 }; 616 617 i2c17: i2c@88c000 { 618 compatible = "qcom,geni-i2c"; 619 reg = <0 0x0088c000 0 0x4000>; 620 clock-names = "se"; 621 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 622 pinctrl-names = "default"; 623 pinctrl-0 = <&qup_i2c17_default>; 624 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 625 #address-cells = <1>; 626 #size-cells = <0>; 627 status = "disabled"; 628 }; 629 630 spi17: spi@88c000 { 631 compatible = "qcom,geni-spi"; 632 reg = <0 0x0088c000 0 0x4000>; 633 clock-names = "se"; 634 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 635 pinctrl-names = "default"; 636 pinctrl-0 = <&qup_spi17_default>; 637 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 power-domains = <&rpmhpd SM8250_CX>; 641 operating-points-v2 = <&qup_opp_table>; 642 status = "disabled"; 643 }; 644 645 uart17: serial@88c000 { 646 compatible = "qcom,geni-uart"; 647 reg = <0 0x0088c000 0 0x4000>; 648 clock-names = "se"; 649 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 650 pinctrl-names = "default"; 651 pinctrl-0 = <&qup_uart17_default>; 652 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 653 power-domains = <&rpmhpd SM8250_CX>; 654 operating-points-v2 = <&qup_opp_table>; 655 status = "disabled"; 656 }; 657 658 i2c18: i2c@890000 { 659 compatible = "qcom,geni-i2c"; 660 reg = <0 0x00890000 0 0x4000>; 661 clock-names = "se"; 662 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 663 pinctrl-names = "default"; 664 pinctrl-0 = <&qup_i2c18_default>; 665 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 666 #address-cells = <1>; 667 #size-cells = <0>; 668 status = "disabled"; 669 }; 670 671 spi18: spi@890000 { 672 compatible = "qcom,geni-spi"; 673 reg = <0 0x00890000 0 0x4000>; 674 clock-names = "se"; 675 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 676 pinctrl-names = "default"; 677 pinctrl-0 = <&qup_spi18_default>; 678 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 power-domains = <&rpmhpd SM8250_CX>; 682 operating-points-v2 = <&qup_opp_table>; 683 status = "disabled"; 684 }; 685 686 uart18: serial@890000 { 687 compatible = "qcom,geni-uart"; 688 reg = <0 0x00890000 0 0x4000>; 689 clock-names = "se"; 690 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 691 pinctrl-names = "default"; 692 pinctrl-0 = <&qup_uart18_default>; 693 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 694 power-domains = <&rpmhpd SM8250_CX>; 695 operating-points-v2 = <&qup_opp_table>; 696 status = "disabled"; 697 }; 698 699 i2c19: i2c@894000 { 700 compatible = "qcom,geni-i2c"; 701 reg = <0 0x00894000 0 0x4000>; 702 clock-names = "se"; 703 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 704 pinctrl-names = "default"; 705 pinctrl-0 = <&qup_i2c19_default>; 706 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 status = "disabled"; 710 }; 711 712 spi19: spi@894000 { 713 compatible = "qcom,geni-spi"; 714 reg = <0 0x00894000 0 0x4000>; 715 clock-names = "se"; 716 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 717 pinctrl-names = "default"; 718 pinctrl-0 = <&qup_spi19_default>; 719 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 power-domains = <&rpmhpd SM8250_CX>; 723 operating-points-v2 = <&qup_opp_table>; 724 status = "disabled"; 725 }; 726 }; 727 728 qupv3_id_0: geniqup@9c0000 { 729 compatible = "qcom,geni-se-qup"; 730 reg = <0x0 0x009c0000 0x0 0x6000>; 731 clock-names = "m-ahb", "s-ahb"; 732 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 733 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 734 #address-cells = <2>; 735 #size-cells = <2>; 736 iommus = <&apps_smmu 0x5a3 0x0>; 737 ranges; 738 status = "disabled"; 739 740 i2c0: i2c@980000 { 741 compatible = "qcom,geni-i2c"; 742 reg = <0 0x00980000 0 0x4000>; 743 clock-names = "se"; 744 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 745 pinctrl-names = "default"; 746 pinctrl-0 = <&qup_i2c0_default>; 747 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 748 #address-cells = <1>; 749 #size-cells = <0>; 750 status = "disabled"; 751 }; 752 753 spi0: spi@980000 { 754 compatible = "qcom,geni-spi"; 755 reg = <0 0x00980000 0 0x4000>; 756 clock-names = "se"; 757 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 758 pinctrl-names = "default"; 759 pinctrl-0 = <&qup_spi0_default>; 760 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 power-domains = <&rpmhpd SM8250_CX>; 764 operating-points-v2 = <&qup_opp_table>; 765 status = "disabled"; 766 }; 767 768 i2c1: i2c@984000 { 769 compatible = "qcom,geni-i2c"; 770 reg = <0 0x00984000 0 0x4000>; 771 clock-names = "se"; 772 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 773 pinctrl-names = "default"; 774 pinctrl-0 = <&qup_i2c1_default>; 775 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 776 #address-cells = <1>; 777 #size-cells = <0>; 778 status = "disabled"; 779 }; 780 781 spi1: spi@984000 { 782 compatible = "qcom,geni-spi"; 783 reg = <0 0x00984000 0 0x4000>; 784 clock-names = "se"; 785 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 786 pinctrl-names = "default"; 787 pinctrl-0 = <&qup_spi1_default>; 788 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 power-domains = <&rpmhpd SM8250_CX>; 792 operating-points-v2 = <&qup_opp_table>; 793 status = "disabled"; 794 }; 795 796 i2c2: i2c@988000 { 797 compatible = "qcom,geni-i2c"; 798 reg = <0 0x00988000 0 0x4000>; 799 clock-names = "se"; 800 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 801 pinctrl-names = "default"; 802 pinctrl-0 = <&qup_i2c2_default>; 803 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 804 #address-cells = <1>; 805 #size-cells = <0>; 806 status = "disabled"; 807 }; 808 809 spi2: spi@988000 { 810 compatible = "qcom,geni-spi"; 811 reg = <0 0x00988000 0 0x4000>; 812 clock-names = "se"; 813 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 814 pinctrl-names = "default"; 815 pinctrl-0 = <&qup_spi2_default>; 816 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 power-domains = <&rpmhpd SM8250_CX>; 820 operating-points-v2 = <&qup_opp_table>; 821 status = "disabled"; 822 }; 823 824 uart2: serial@988000 { 825 compatible = "qcom,geni-debug-uart"; 826 reg = <0 0x00988000 0 0x4000>; 827 clock-names = "se"; 828 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 829 pinctrl-names = "default"; 830 pinctrl-0 = <&qup_uart2_default>; 831 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 832 power-domains = <&rpmhpd SM8250_CX>; 833 operating-points-v2 = <&qup_opp_table>; 834 status = "disabled"; 835 }; 836 837 i2c3: i2c@98c000 { 838 compatible = "qcom,geni-i2c"; 839 reg = <0 0x0098c000 0 0x4000>; 840 clock-names = "se"; 841 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 842 pinctrl-names = "default"; 843 pinctrl-0 = <&qup_i2c3_default>; 844 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 status = "disabled"; 848 }; 849 850 spi3: spi@98c000 { 851 compatible = "qcom,geni-spi"; 852 reg = <0 0x0098c000 0 0x4000>; 853 clock-names = "se"; 854 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 855 pinctrl-names = "default"; 856 pinctrl-0 = <&qup_spi3_default>; 857 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 858 #address-cells = <1>; 859 #size-cells = <0>; 860 power-domains = <&rpmhpd SM8250_CX>; 861 operating-points-v2 = <&qup_opp_table>; 862 status = "disabled"; 863 }; 864 865 i2c4: i2c@990000 { 866 compatible = "qcom,geni-i2c"; 867 reg = <0 0x00990000 0 0x4000>; 868 clock-names = "se"; 869 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 870 pinctrl-names = "default"; 871 pinctrl-0 = <&qup_i2c4_default>; 872 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 status = "disabled"; 876 }; 877 878 spi4: spi@990000 { 879 compatible = "qcom,geni-spi"; 880 reg = <0 0x00990000 0 0x4000>; 881 clock-names = "se"; 882 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 883 pinctrl-names = "default"; 884 pinctrl-0 = <&qup_spi4_default>; 885 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 886 #address-cells = <1>; 887 #size-cells = <0>; 888 power-domains = <&rpmhpd SM8250_CX>; 889 operating-points-v2 = <&qup_opp_table>; 890 status = "disabled"; 891 }; 892 893 i2c5: i2c@994000 { 894 compatible = "qcom,geni-i2c"; 895 reg = <0 0x00994000 0 0x4000>; 896 clock-names = "se"; 897 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 898 pinctrl-names = "default"; 899 pinctrl-0 = <&qup_i2c5_default>; 900 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 status = "disabled"; 904 }; 905 906 spi5: spi@994000 { 907 compatible = "qcom,geni-spi"; 908 reg = <0 0x00994000 0 0x4000>; 909 clock-names = "se"; 910 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 911 pinctrl-names = "default"; 912 pinctrl-0 = <&qup_spi5_default>; 913 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 power-domains = <&rpmhpd SM8250_CX>; 917 operating-points-v2 = <&qup_opp_table>; 918 status = "disabled"; 919 }; 920 921 i2c6: i2c@998000 { 922 compatible = "qcom,geni-i2c"; 923 reg = <0 0x00998000 0 0x4000>; 924 clock-names = "se"; 925 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 926 pinctrl-names = "default"; 927 pinctrl-0 = <&qup_i2c6_default>; 928 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 status = "disabled"; 932 }; 933 934 spi6: spi@998000 { 935 compatible = "qcom,geni-spi"; 936 reg = <0 0x00998000 0 0x4000>; 937 clock-names = "se"; 938 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 939 pinctrl-names = "default"; 940 pinctrl-0 = <&qup_spi6_default>; 941 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 942 #address-cells = <1>; 943 #size-cells = <0>; 944 power-domains = <&rpmhpd SM8250_CX>; 945 operating-points-v2 = <&qup_opp_table>; 946 status = "disabled"; 947 }; 948 949 uart6: serial@998000 { 950 compatible = "qcom,geni-uart"; 951 reg = <0 0x00998000 0 0x4000>; 952 clock-names = "se"; 953 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 954 pinctrl-names = "default"; 955 pinctrl-0 = <&qup_uart6_default>; 956 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 957 power-domains = <&rpmhpd SM8250_CX>; 958 operating-points-v2 = <&qup_opp_table>; 959 status = "disabled"; 960 }; 961 962 i2c7: i2c@99c000 { 963 compatible = "qcom,geni-i2c"; 964 reg = <0 0x0099c000 0 0x4000>; 965 clock-names = "se"; 966 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 967 pinctrl-names = "default"; 968 pinctrl-0 = <&qup_i2c7_default>; 969 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 970 #address-cells = <1>; 971 #size-cells = <0>; 972 status = "disabled"; 973 }; 974 975 spi7: spi@99c000 { 976 compatible = "qcom,geni-spi"; 977 reg = <0 0x0099c000 0 0x4000>; 978 clock-names = "se"; 979 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 980 pinctrl-names = "default"; 981 pinctrl-0 = <&qup_spi7_default>; 982 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 983 #address-cells = <1>; 984 #size-cells = <0>; 985 power-domains = <&rpmhpd SM8250_CX>; 986 operating-points-v2 = <&qup_opp_table>; 987 status = "disabled"; 988 }; 989 }; 990 991 qupv3_id_1: geniqup@ac0000 { 992 compatible = "qcom,geni-se-qup"; 993 reg = <0x0 0x00ac0000 0x0 0x6000>; 994 clock-names = "m-ahb", "s-ahb"; 995 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 996 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 997 #address-cells = <2>; 998 #size-cells = <2>; 999 iommus = <&apps_smmu 0x43 0x0>; 1000 ranges; 1001 status = "disabled"; 1002 1003 i2c8: i2c@a80000 { 1004 compatible = "qcom,geni-i2c"; 1005 reg = <0 0x00a80000 0 0x4000>; 1006 clock-names = "se"; 1007 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1008 pinctrl-names = "default"; 1009 pinctrl-0 = <&qup_i2c8_default>; 1010 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 status = "disabled"; 1014 }; 1015 1016 spi8: spi@a80000 { 1017 compatible = "qcom,geni-spi"; 1018 reg = <0 0x00a80000 0 0x4000>; 1019 clock-names = "se"; 1020 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1021 pinctrl-names = "default"; 1022 pinctrl-0 = <&qup_spi8_default>; 1023 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 power-domains = <&rpmhpd SM8250_CX>; 1027 operating-points-v2 = <&qup_opp_table>; 1028 status = "disabled"; 1029 }; 1030 1031 i2c9: i2c@a84000 { 1032 compatible = "qcom,geni-i2c"; 1033 reg = <0 0x00a84000 0 0x4000>; 1034 clock-names = "se"; 1035 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1036 pinctrl-names = "default"; 1037 pinctrl-0 = <&qup_i2c9_default>; 1038 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 status = "disabled"; 1042 }; 1043 1044 spi9: spi@a84000 { 1045 compatible = "qcom,geni-spi"; 1046 reg = <0 0x00a84000 0 0x4000>; 1047 clock-names = "se"; 1048 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1049 pinctrl-names = "default"; 1050 pinctrl-0 = <&qup_spi9_default>; 1051 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1052 #address-cells = <1>; 1053 #size-cells = <0>; 1054 power-domains = <&rpmhpd SM8250_CX>; 1055 operating-points-v2 = <&qup_opp_table>; 1056 status = "disabled"; 1057 }; 1058 1059 i2c10: i2c@a88000 { 1060 compatible = "qcom,geni-i2c"; 1061 reg = <0 0x00a88000 0 0x4000>; 1062 clock-names = "se"; 1063 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1064 pinctrl-names = "default"; 1065 pinctrl-0 = <&qup_i2c10_default>; 1066 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 status = "disabled"; 1070 }; 1071 1072 spi10: spi@a88000 { 1073 compatible = "qcom,geni-spi"; 1074 reg = <0 0x00a88000 0 0x4000>; 1075 clock-names = "se"; 1076 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1077 pinctrl-names = "default"; 1078 pinctrl-0 = <&qup_spi10_default>; 1079 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 power-domains = <&rpmhpd SM8250_CX>; 1083 operating-points-v2 = <&qup_opp_table>; 1084 status = "disabled"; 1085 }; 1086 1087 i2c11: i2c@a8c000 { 1088 compatible = "qcom,geni-i2c"; 1089 reg = <0 0x00a8c000 0 0x4000>; 1090 clock-names = "se"; 1091 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1092 pinctrl-names = "default"; 1093 pinctrl-0 = <&qup_i2c11_default>; 1094 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 status = "disabled"; 1098 }; 1099 1100 spi11: spi@a8c000 { 1101 compatible = "qcom,geni-spi"; 1102 reg = <0 0x00a8c000 0 0x4000>; 1103 clock-names = "se"; 1104 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1105 pinctrl-names = "default"; 1106 pinctrl-0 = <&qup_spi11_default>; 1107 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 power-domains = <&rpmhpd SM8250_CX>; 1111 operating-points-v2 = <&qup_opp_table>; 1112 status = "disabled"; 1113 }; 1114 1115 i2c12: i2c@a90000 { 1116 compatible = "qcom,geni-i2c"; 1117 reg = <0 0x00a90000 0 0x4000>; 1118 clock-names = "se"; 1119 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1120 pinctrl-names = "default"; 1121 pinctrl-0 = <&qup_i2c12_default>; 1122 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 status = "disabled"; 1126 }; 1127 1128 spi12: spi@a90000 { 1129 compatible = "qcom,geni-spi"; 1130 reg = <0 0x00a90000 0 0x4000>; 1131 clock-names = "se"; 1132 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1133 pinctrl-names = "default"; 1134 pinctrl-0 = <&qup_spi12_default>; 1135 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 power-domains = <&rpmhpd SM8250_CX>; 1139 operating-points-v2 = <&qup_opp_table>; 1140 status = "disabled"; 1141 }; 1142 1143 uart12: serial@a90000 { 1144 compatible = "qcom,geni-debug-uart"; 1145 reg = <0x0 0x00a90000 0x0 0x4000>; 1146 clock-names = "se"; 1147 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1148 pinctrl-names = "default"; 1149 pinctrl-0 = <&qup_uart12_default>; 1150 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1151 power-domains = <&rpmhpd SM8250_CX>; 1152 operating-points-v2 = <&qup_opp_table>; 1153 status = "disabled"; 1154 }; 1155 1156 i2c13: i2c@a94000 { 1157 compatible = "qcom,geni-i2c"; 1158 reg = <0 0x00a94000 0 0x4000>; 1159 clock-names = "se"; 1160 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&qup_i2c13_default>; 1163 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1164 #address-cells = <1>; 1165 #size-cells = <0>; 1166 status = "disabled"; 1167 }; 1168 1169 spi13: spi@a94000 { 1170 compatible = "qcom,geni-spi"; 1171 reg = <0 0x00a94000 0 0x4000>; 1172 clock-names = "se"; 1173 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&qup_spi13_default>; 1176 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 power-domains = <&rpmhpd SM8250_CX>; 1180 operating-points-v2 = <&qup_opp_table>; 1181 status = "disabled"; 1182 }; 1183 }; 1184 1185 config_noc: interconnect@1500000 { 1186 compatible = "qcom,sm8250-config-noc"; 1187 reg = <0 0x01500000 0 0xa580>; 1188 #interconnect-cells = <1>; 1189 qcom,bcm-voters = <&apps_bcm_voter>; 1190 }; 1191 1192 system_noc: interconnect@1620000 { 1193 compatible = "qcom,sm8250-system-noc"; 1194 reg = <0 0x01620000 0 0x1c200>; 1195 #interconnect-cells = <1>; 1196 qcom,bcm-voters = <&apps_bcm_voter>; 1197 }; 1198 1199 mc_virt: interconnect@163d000 { 1200 compatible = "qcom,sm8250-mc-virt"; 1201 reg = <0 0x0163d000 0 0x1000>; 1202 #interconnect-cells = <1>; 1203 qcom,bcm-voters = <&apps_bcm_voter>; 1204 }; 1205 1206 aggre1_noc: interconnect@16e0000 { 1207 compatible = "qcom,sm8250-aggre1-noc"; 1208 reg = <0 0x016e0000 0 0x1f180>; 1209 #interconnect-cells = <1>; 1210 qcom,bcm-voters = <&apps_bcm_voter>; 1211 }; 1212 1213 aggre2_noc: interconnect@1700000 { 1214 compatible = "qcom,sm8250-aggre2-noc"; 1215 reg = <0 0x01700000 0 0x33000>; 1216 #interconnect-cells = <1>; 1217 qcom,bcm-voters = <&apps_bcm_voter>; 1218 }; 1219 1220 compute_noc: interconnect@1733000 { 1221 compatible = "qcom,sm8250-compute-noc"; 1222 reg = <0 0x01733000 0 0xa180>; 1223 #interconnect-cells = <1>; 1224 qcom,bcm-voters = <&apps_bcm_voter>; 1225 }; 1226 1227 mmss_noc: interconnect@1740000 { 1228 compatible = "qcom,sm8250-mmss-noc"; 1229 reg = <0 0x01740000 0 0x1f080>; 1230 #interconnect-cells = <1>; 1231 qcom,bcm-voters = <&apps_bcm_voter>; 1232 }; 1233 1234 pcie0: pci@1c00000 { 1235 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1236 reg = <0 0x01c00000 0 0x3000>, 1237 <0 0x60000000 0 0xf1d>, 1238 <0 0x60000f20 0 0xa8>, 1239 <0 0x60001000 0 0x1000>, 1240 <0 0x60100000 0 0x100000>; 1241 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1242 device_type = "pci"; 1243 linux,pci-domain = <0>; 1244 bus-range = <0x00 0xff>; 1245 num-lanes = <1>; 1246 1247 #address-cells = <3>; 1248 #size-cells = <2>; 1249 1250 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1251 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1252 1253 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1254 interrupt-names = "msi"; 1255 #interrupt-cells = <1>; 1256 interrupt-map-mask = <0 0 0 0x7>; 1257 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1258 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1259 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1260 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1261 1262 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1263 <&gcc GCC_PCIE_0_AUX_CLK>, 1264 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1265 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1266 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1267 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1268 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1269 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1270 clock-names = "pipe", 1271 "aux", 1272 "cfg", 1273 "bus_master", 1274 "bus_slave", 1275 "slave_q2a", 1276 "tbu", 1277 "ddrss_sf_tbu"; 1278 1279 iommus = <&apps_smmu 0x1c00 0x7f>; 1280 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1281 <0x100 &apps_smmu 0x1c01 0x1>; 1282 1283 resets = <&gcc GCC_PCIE_0_BCR>; 1284 reset-names = "pci"; 1285 1286 power-domains = <&gcc PCIE_0_GDSC>; 1287 1288 phys = <&pcie0_lane>; 1289 phy-names = "pciephy"; 1290 1291 status = "disabled"; 1292 }; 1293 1294 pcie0_phy: phy@1c06000 { 1295 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1296 reg = <0 0x01c06000 0 0x1c0>; 1297 #address-cells = <2>; 1298 #size-cells = <2>; 1299 ranges; 1300 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1301 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1302 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1303 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1304 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1305 1306 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1307 reset-names = "phy"; 1308 1309 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1310 assigned-clock-rates = <100000000>; 1311 1312 status = "disabled"; 1313 1314 pcie0_lane: lanes@1c06200 { 1315 reg = <0 0x1c06200 0 0x170>, /* tx */ 1316 <0 0x1c06400 0 0x200>, /* rx */ 1317 <0 0x1c06800 0 0x1f0>, /* pcs */ 1318 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1319 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1320 clock-names = "pipe0"; 1321 1322 #phy-cells = <0>; 1323 clock-output-names = "pcie_0_pipe_clk"; 1324 }; 1325 }; 1326 1327 pcie1: pci@1c08000 { 1328 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1329 reg = <0 0x01c08000 0 0x3000>, 1330 <0 0x40000000 0 0xf1d>, 1331 <0 0x40000f20 0 0xa8>, 1332 <0 0x40001000 0 0x1000>, 1333 <0 0x40100000 0 0x100000>; 1334 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1335 device_type = "pci"; 1336 linux,pci-domain = <1>; 1337 bus-range = <0x00 0xff>; 1338 num-lanes = <2>; 1339 1340 #address-cells = <3>; 1341 #size-cells = <2>; 1342 1343 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1344 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1345 1346 interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>; 1347 interrupt-names = "msi"; 1348 #interrupt-cells = <1>; 1349 interrupt-map-mask = <0 0 0 0x7>; 1350 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1351 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1352 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1353 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1354 1355 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1356 <&gcc GCC_PCIE_1_AUX_CLK>, 1357 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1358 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1359 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1360 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1361 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1362 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1363 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1364 clock-names = "pipe", 1365 "aux", 1366 "cfg", 1367 "bus_master", 1368 "bus_slave", 1369 "slave_q2a", 1370 "ref", 1371 "tbu", 1372 "ddrss_sf_tbu"; 1373 1374 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1375 assigned-clock-rates = <19200000>; 1376 1377 iommus = <&apps_smmu 0x1c80 0x7f>; 1378 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1379 <0x100 &apps_smmu 0x1c81 0x1>; 1380 1381 resets = <&gcc GCC_PCIE_1_BCR>; 1382 reset-names = "pci"; 1383 1384 power-domains = <&gcc PCIE_1_GDSC>; 1385 1386 phys = <&pcie1_lane>; 1387 phy-names = "pciephy"; 1388 1389 status = "disabled"; 1390 }; 1391 1392 pcie1_phy: phy@1c0e000 { 1393 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1394 reg = <0 0x01c0e000 0 0x1c0>; 1395 #address-cells = <2>; 1396 #size-cells = <2>; 1397 ranges; 1398 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1399 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1400 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1401 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1402 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1403 1404 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1405 reset-names = "phy"; 1406 1407 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1408 assigned-clock-rates = <100000000>; 1409 1410 status = "disabled"; 1411 1412 pcie1_lane: lanes@1c0e200 { 1413 reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1414 <0 0x1c0e400 0 0x200>, /* rx0 */ 1415 <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1416 <0 0x1c0e600 0 0x170>, /* tx1 */ 1417 <0 0x1c0e800 0 0x200>, /* rx1 */ 1418 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1419 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1420 clock-names = "pipe0"; 1421 1422 #phy-cells = <0>; 1423 clock-output-names = "pcie_1_pipe_clk"; 1424 }; 1425 }; 1426 1427 pcie2: pci@1c10000 { 1428 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1429 reg = <0 0x01c10000 0 0x3000>, 1430 <0 0x64000000 0 0xf1d>, 1431 <0 0x64000f20 0 0xa8>, 1432 <0 0x64001000 0 0x1000>, 1433 <0 0x64100000 0 0x100000>; 1434 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1435 device_type = "pci"; 1436 linux,pci-domain = <2>; 1437 bus-range = <0x00 0xff>; 1438 num-lanes = <2>; 1439 1440 #address-cells = <3>; 1441 #size-cells = <2>; 1442 1443 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, 1444 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 1445 1446 interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; 1447 interrupt-names = "msi"; 1448 #interrupt-cells = <1>; 1449 interrupt-map-mask = <0 0 0 0x7>; 1450 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1451 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1452 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1453 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1454 1455 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1456 <&gcc GCC_PCIE_2_AUX_CLK>, 1457 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1458 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1459 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 1460 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 1461 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1462 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1463 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1464 clock-names = "pipe", 1465 "aux", 1466 "cfg", 1467 "bus_master", 1468 "bus_slave", 1469 "slave_q2a", 1470 "ref", 1471 "tbu", 1472 "ddrss_sf_tbu"; 1473 1474 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 1475 assigned-clock-rates = <19200000>; 1476 1477 iommus = <&apps_smmu 0x1d00 0x7f>; 1478 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 1479 <0x100 &apps_smmu 0x1d01 0x1>; 1480 1481 resets = <&gcc GCC_PCIE_2_BCR>; 1482 reset-names = "pci"; 1483 1484 power-domains = <&gcc PCIE_2_GDSC>; 1485 1486 phys = <&pcie2_lane>; 1487 phy-names = "pciephy"; 1488 1489 status = "disabled"; 1490 }; 1491 1492 pcie2_phy: phy@1c16000 { 1493 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 1494 reg = <0 0x1c16000 0 0x1c0>; 1495 #address-cells = <2>; 1496 #size-cells = <2>; 1497 ranges; 1498 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1499 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1500 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1501 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1502 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1503 1504 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 1505 reset-names = "phy"; 1506 1507 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1508 assigned-clock-rates = <100000000>; 1509 1510 status = "disabled"; 1511 1512 pcie2_lane: lanes@1c0e200 { 1513 reg = <0 0x1c16200 0 0x170>, /* tx0 */ 1514 <0 0x1c16400 0 0x200>, /* rx0 */ 1515 <0 0x1c16a00 0 0x1f0>, /* pcs */ 1516 <0 0x1c16600 0 0x170>, /* tx1 */ 1517 <0 0x1c16800 0 0x200>, /* rx1 */ 1518 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1519 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 1520 clock-names = "pipe0"; 1521 1522 #phy-cells = <0>; 1523 clock-output-names = "pcie_2_pipe_clk"; 1524 }; 1525 }; 1526 1527 ufs_mem_hc: ufshc@1d84000 { 1528 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 1529 "jedec,ufs-2.0"; 1530 reg = <0 0x01d84000 0 0x3000>; 1531 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1532 phys = <&ufs_mem_phy_lanes>; 1533 phy-names = "ufsphy"; 1534 lanes-per-direction = <2>; 1535 #reset-cells = <1>; 1536 resets = <&gcc GCC_UFS_PHY_BCR>; 1537 reset-names = "rst"; 1538 1539 power-domains = <&gcc UFS_PHY_GDSC>; 1540 1541 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 1542 1543 clock-names = 1544 "core_clk", 1545 "bus_aggr_clk", 1546 "iface_clk", 1547 "core_clk_unipro", 1548 "ref_clk", 1549 "tx_lane0_sync_clk", 1550 "rx_lane0_sync_clk", 1551 "rx_lane1_sync_clk"; 1552 clocks = 1553 <&gcc GCC_UFS_PHY_AXI_CLK>, 1554 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1555 <&gcc GCC_UFS_PHY_AHB_CLK>, 1556 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1557 <&rpmhcc RPMH_CXO_CLK>, 1558 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1559 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1560 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1561 freq-table-hz = 1562 <37500000 300000000>, 1563 <0 0>, 1564 <0 0>, 1565 <37500000 300000000>, 1566 <0 0>, 1567 <0 0>, 1568 <0 0>, 1569 <0 0>; 1570 1571 status = "disabled"; 1572 }; 1573 1574 ufs_mem_phy: phy@1d87000 { 1575 compatible = "qcom,sm8250-qmp-ufs-phy"; 1576 reg = <0 0x01d87000 0 0x1c0>; 1577 #address-cells = <2>; 1578 #size-cells = <2>; 1579 ranges; 1580 clock-names = "ref", 1581 "ref_aux"; 1582 clocks = <&rpmhcc RPMH_CXO_CLK>, 1583 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1584 1585 resets = <&ufs_mem_hc 0>; 1586 reset-names = "ufsphy"; 1587 status = "disabled"; 1588 1589 ufs_mem_phy_lanes: lanes@1d87400 { 1590 reg = <0 0x01d87400 0 0x108>, 1591 <0 0x01d87600 0 0x1e0>, 1592 <0 0x01d87c00 0 0x1dc>, 1593 <0 0x01d87800 0 0x108>, 1594 <0 0x01d87a00 0 0x1e0>; 1595 #phy-cells = <0>; 1596 }; 1597 }; 1598 1599 ipa_virt: interconnect@1e00000 { 1600 compatible = "qcom,sm8250-ipa-virt"; 1601 reg = <0 0x01e00000 0 0x1000>; 1602 #interconnect-cells = <1>; 1603 qcom,bcm-voters = <&apps_bcm_voter>; 1604 }; 1605 1606 tcsr_mutex: hwlock@1f40000 { 1607 compatible = "qcom,tcsr-mutex"; 1608 reg = <0x0 0x01f40000 0x0 0x40000>; 1609 #hwlock-cells = <1>; 1610 }; 1611 1612 wsamacro: codec@3240000 { 1613 compatible = "qcom,sm8250-lpass-wsa-macro"; 1614 reg = <0 0x03240000 0 0x1000>; 1615 clocks = <&audiocc 1>, 1616 <&audiocc 0>, 1617 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1618 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1619 <&aoncc 0>, 1620 <&vamacro>; 1621 1622 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 1623 1624 #clock-cells = <0>; 1625 clock-frequency = <9600000>; 1626 clock-output-names = "mclk"; 1627 #sound-dai-cells = <1>; 1628 1629 pinctrl-names = "default"; 1630 pinctrl-0 = <&wsa_swr_active>; 1631 }; 1632 1633 swr0: soundwire-controller@3250000 { 1634 reg = <0 0x03250000 0 0x2000>; 1635 compatible = "qcom,soundwire-v1.5.1"; 1636 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1637 clocks = <&wsamacro>; 1638 clock-names = "iface"; 1639 1640 qcom,din-ports = <2>; 1641 qcom,dout-ports = <6>; 1642 1643 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 1644 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 1645 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 1646 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 1647 1648 #sound-dai-cells = <1>; 1649 #address-cells = <2>; 1650 #size-cells = <0>; 1651 }; 1652 1653 audiocc: clock-controller@3300000 { 1654 compatible = "qcom,sm8250-lpass-audiocc"; 1655 reg = <0 0x03300000 0 0x30000>; 1656 #clock-cells = <1>; 1657 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1658 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1659 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1660 clock-names = "core", "audio", "bus"; 1661 }; 1662 1663 vamacro: codec@3370000 { 1664 compatible = "qcom,sm8250-lpass-va-macro"; 1665 reg = <0 0x03370000 0 0x1000>; 1666 clocks = <&aoncc 0>, 1667 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1668 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1669 1670 clock-names = "mclk", "macro", "dcodec"; 1671 1672 #clock-cells = <0>; 1673 clock-frequency = <9600000>; 1674 clock-output-names = "fsgen"; 1675 #sound-dai-cells = <1>; 1676 }; 1677 1678 aoncc: clock-controller@3380000 { 1679 compatible = "qcom,sm8250-lpass-aoncc"; 1680 reg = <0 0x03380000 0 0x40000>; 1681 #clock-cells = <1>; 1682 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1683 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1684 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1685 clock-names = "core", "audio", "bus"; 1686 }; 1687 1688 lpass_tlmm: pinctrl@33c0000{ 1689 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 1690 reg = <0 0x033c0000 0x0 0x20000>, 1691 <0 0x03550000 0x0 0x10000>; 1692 gpio-controller; 1693 #gpio-cells = <2>; 1694 gpio-ranges = <&lpass_tlmm 0 0 14>; 1695 1696 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1697 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1698 clock-names = "core", "audio"; 1699 1700 wsa_swr_active: wsa-swr-active-pins { 1701 clk { 1702 pins = "gpio10"; 1703 function = "wsa_swr_clk"; 1704 drive-strength = <2>; 1705 slew-rate = <1>; 1706 bias-disable; 1707 }; 1708 1709 data { 1710 pins = "gpio11"; 1711 function = "wsa_swr_data"; 1712 drive-strength = <2>; 1713 slew-rate = <1>; 1714 bias-bus-hold; 1715 1716 }; 1717 }; 1718 1719 wsa_swr_sleep: wsa-swr-sleep-pins { 1720 clk { 1721 pins = "gpio10"; 1722 function = "wsa_swr_clk"; 1723 drive-strength = <2>; 1724 input-enable; 1725 bias-pull-down; 1726 }; 1727 1728 data { 1729 pins = "gpio11"; 1730 function = "wsa_swr_data"; 1731 drive-strength = <2>; 1732 input-enable; 1733 bias-pull-down; 1734 1735 }; 1736 }; 1737 1738 dmic01_active: dmic01-active-pins { 1739 clk { 1740 pins = "gpio6"; 1741 function = "dmic1_clk"; 1742 drive-strength = <8>; 1743 output-high; 1744 }; 1745 data { 1746 pins = "gpio7"; 1747 function = "dmic1_data"; 1748 drive-strength = <8>; 1749 input-enable; 1750 }; 1751 }; 1752 1753 dmic01_sleep: dmic01-sleep-pins { 1754 clk { 1755 pins = "gpio6"; 1756 function = "dmic1_clk"; 1757 drive-strength = <2>; 1758 bias-disable; 1759 output-low; 1760 }; 1761 1762 data { 1763 pins = "gpio7"; 1764 function = "dmic1_data"; 1765 drive-strength = <2>; 1766 pull-down; 1767 input-enable; 1768 }; 1769 }; 1770 }; 1771 1772 gpu: gpu@3d00000 { 1773 compatible = "qcom,adreno-650.2", 1774 "qcom,adreno"; 1775 #stream-id-cells = <16>; 1776 1777 reg = <0 0x03d00000 0 0x40000>; 1778 reg-names = "kgsl_3d0_reg_memory"; 1779 1780 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1781 1782 iommus = <&adreno_smmu 0 0x401>; 1783 1784 operating-points-v2 = <&gpu_opp_table>; 1785 1786 qcom,gmu = <&gmu>; 1787 1788 zap-shader { 1789 memory-region = <&gpu_mem>; 1790 }; 1791 1792 /* note: downstream checks gpu binning for 670 Mhz */ 1793 gpu_opp_table: opp-table { 1794 compatible = "operating-points-v2"; 1795 1796 opp-670000000 { 1797 opp-hz = /bits/ 64 <670000000>; 1798 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1799 }; 1800 1801 opp-587000000 { 1802 opp-hz = /bits/ 64 <587000000>; 1803 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1804 }; 1805 1806 opp-525000000 { 1807 opp-hz = /bits/ 64 <525000000>; 1808 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1809 }; 1810 1811 opp-490000000 { 1812 opp-hz = /bits/ 64 <490000000>; 1813 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1814 }; 1815 1816 opp-441600000 { 1817 opp-hz = /bits/ 64 <441600000>; 1818 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1819 }; 1820 1821 opp-400000000 { 1822 opp-hz = /bits/ 64 <400000000>; 1823 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1824 }; 1825 1826 opp-305000000 { 1827 opp-hz = /bits/ 64 <305000000>; 1828 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1829 }; 1830 }; 1831 }; 1832 1833 gmu: gmu@3d6a000 { 1834 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 1835 1836 reg = <0 0x03d6a000 0 0x30000>, 1837 <0 0x3de0000 0 0x10000>, 1838 <0 0xb290000 0 0x10000>, 1839 <0 0xb490000 0 0x10000>; 1840 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 1841 1842 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1844 interrupt-names = "hfi", "gmu"; 1845 1846 clocks = <&gpucc GPU_CC_AHB_CLK>, 1847 <&gpucc GPU_CC_CX_GMU_CLK>, 1848 <&gpucc GPU_CC_CXO_CLK>, 1849 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1850 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1851 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 1852 1853 power-domains = <&gpucc GPU_CX_GDSC>, 1854 <&gpucc GPU_GX_GDSC>; 1855 power-domain-names = "cx", "gx"; 1856 1857 iommus = <&adreno_smmu 5 0x400>; 1858 1859 operating-points-v2 = <&gmu_opp_table>; 1860 1861 gmu_opp_table: opp-table { 1862 compatible = "operating-points-v2"; 1863 1864 opp-200000000 { 1865 opp-hz = /bits/ 64 <200000000>; 1866 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1867 }; 1868 }; 1869 }; 1870 1871 gpucc: clock-controller@3d90000 { 1872 compatible = "qcom,sm8250-gpucc"; 1873 reg = <0 0x03d90000 0 0x9000>; 1874 clocks = <&rpmhcc RPMH_CXO_CLK>, 1875 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1876 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1877 clock-names = "bi_tcxo", 1878 "gcc_gpu_gpll0_clk_src", 1879 "gcc_gpu_gpll0_div_clk_src"; 1880 #clock-cells = <1>; 1881 #reset-cells = <1>; 1882 #power-domain-cells = <1>; 1883 }; 1884 1885 adreno_smmu: iommu@3da0000 { 1886 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 1887 reg = <0 0x03da0000 0 0x10000>; 1888 #iommu-cells = <2>; 1889 #global-interrupts = <2>; 1890 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 1900 clocks = <&gpucc GPU_CC_AHB_CLK>, 1901 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1902 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1903 clock-names = "ahb", "bus", "iface"; 1904 1905 power-domains = <&gpucc GPU_CX_GDSC>; 1906 }; 1907 1908 slpi: remoteproc@5c00000 { 1909 compatible = "qcom,sm8250-slpi-pas"; 1910 reg = <0 0x05c00000 0 0x4000>; 1911 1912 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 1913 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 1914 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 1915 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 1916 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 1917 interrupt-names = "wdog", "fatal", "ready", 1918 "handover", "stop-ack"; 1919 1920 clocks = <&rpmhcc RPMH_CXO_CLK>; 1921 clock-names = "xo"; 1922 1923 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, 1924 <&rpmhpd SM8250_LCX>, 1925 <&rpmhpd SM8250_LMX>; 1926 power-domain-names = "load_state", "lcx", "lmx"; 1927 1928 memory-region = <&slpi_mem>; 1929 1930 qcom,smem-states = <&smp2p_slpi_out 0>; 1931 qcom,smem-state-names = "stop"; 1932 1933 status = "disabled"; 1934 1935 glink-edge { 1936 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 1937 IPCC_MPROC_SIGNAL_GLINK_QMP 1938 IRQ_TYPE_EDGE_RISING>; 1939 mboxes = <&ipcc IPCC_CLIENT_SLPI 1940 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1941 1942 label = "slpi"; 1943 qcom,remote-pid = <3>; 1944 1945 fastrpc { 1946 compatible = "qcom,fastrpc"; 1947 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1948 label = "sdsp"; 1949 #address-cells = <1>; 1950 #size-cells = <0>; 1951 1952 compute-cb@1 { 1953 compatible = "qcom,fastrpc-compute-cb"; 1954 reg = <1>; 1955 iommus = <&apps_smmu 0x0541 0x0>; 1956 }; 1957 1958 compute-cb@2 { 1959 compatible = "qcom,fastrpc-compute-cb"; 1960 reg = <2>; 1961 iommus = <&apps_smmu 0x0542 0x0>; 1962 }; 1963 1964 compute-cb@3 { 1965 compatible = "qcom,fastrpc-compute-cb"; 1966 reg = <3>; 1967 iommus = <&apps_smmu 0x0543 0x0>; 1968 /* note: shared-cb = <4> in downstream */ 1969 }; 1970 }; 1971 }; 1972 }; 1973 1974 cdsp: remoteproc@8300000 { 1975 compatible = "qcom,sm8250-cdsp-pas"; 1976 reg = <0 0x08300000 0 0x10000>; 1977 1978 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 1979 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1980 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1981 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1982 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1983 interrupt-names = "wdog", "fatal", "ready", 1984 "handover", "stop-ack"; 1985 1986 clocks = <&rpmhcc RPMH_CXO_CLK>; 1987 clock-names = "xo"; 1988 1989 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, 1990 <&rpmhpd SM8250_CX>; 1991 power-domain-names = "load_state", "cx"; 1992 1993 memory-region = <&cdsp_mem>; 1994 1995 qcom,smem-states = <&smp2p_cdsp_out 0>; 1996 qcom,smem-state-names = "stop"; 1997 1998 status = "disabled"; 1999 2000 glink-edge { 2001 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2002 IPCC_MPROC_SIGNAL_GLINK_QMP 2003 IRQ_TYPE_EDGE_RISING>; 2004 mboxes = <&ipcc IPCC_CLIENT_CDSP 2005 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2006 2007 label = "cdsp"; 2008 qcom,remote-pid = <5>; 2009 2010 fastrpc { 2011 compatible = "qcom,fastrpc"; 2012 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2013 label = "cdsp"; 2014 #address-cells = <1>; 2015 #size-cells = <0>; 2016 2017 compute-cb@1 { 2018 compatible = "qcom,fastrpc-compute-cb"; 2019 reg = <1>; 2020 iommus = <&apps_smmu 0x1001 0x0460>; 2021 }; 2022 2023 compute-cb@2 { 2024 compatible = "qcom,fastrpc-compute-cb"; 2025 reg = <2>; 2026 iommus = <&apps_smmu 0x1002 0x0460>; 2027 }; 2028 2029 compute-cb@3 { 2030 compatible = "qcom,fastrpc-compute-cb"; 2031 reg = <3>; 2032 iommus = <&apps_smmu 0x1003 0x0460>; 2033 }; 2034 2035 compute-cb@4 { 2036 compatible = "qcom,fastrpc-compute-cb"; 2037 reg = <4>; 2038 iommus = <&apps_smmu 0x1004 0x0460>; 2039 }; 2040 2041 compute-cb@5 { 2042 compatible = "qcom,fastrpc-compute-cb"; 2043 reg = <5>; 2044 iommus = <&apps_smmu 0x1005 0x0460>; 2045 }; 2046 2047 compute-cb@6 { 2048 compatible = "qcom,fastrpc-compute-cb"; 2049 reg = <6>; 2050 iommus = <&apps_smmu 0x1006 0x0460>; 2051 }; 2052 2053 compute-cb@7 { 2054 compatible = "qcom,fastrpc-compute-cb"; 2055 reg = <7>; 2056 iommus = <&apps_smmu 0x1007 0x0460>; 2057 }; 2058 2059 compute-cb@8 { 2060 compatible = "qcom,fastrpc-compute-cb"; 2061 reg = <8>; 2062 iommus = <&apps_smmu 0x1008 0x0460>; 2063 }; 2064 2065 /* note: secure cb9 in downstream */ 2066 }; 2067 }; 2068 }; 2069 2070 sound: sound { 2071 }; 2072 2073 usb_1_hsphy: phy@88e3000 { 2074 compatible = "qcom,sm8250-usb-hs-phy", 2075 "qcom,usb-snps-hs-7nm-phy"; 2076 reg = <0 0x088e3000 0 0x400>; 2077 status = "disabled"; 2078 #phy-cells = <0>; 2079 2080 clocks = <&rpmhcc RPMH_CXO_CLK>; 2081 clock-names = "ref"; 2082 2083 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2084 }; 2085 2086 usb_2_hsphy: phy@88e4000 { 2087 compatible = "qcom,sm8250-usb-hs-phy", 2088 "qcom,usb-snps-hs-7nm-phy"; 2089 reg = <0 0x088e4000 0 0x400>; 2090 status = "disabled"; 2091 #phy-cells = <0>; 2092 2093 clocks = <&rpmhcc RPMH_CXO_CLK>; 2094 clock-names = "ref"; 2095 2096 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2097 }; 2098 2099 usb_1_qmpphy: phy@88e9000 { 2100 compatible = "qcom,sm8250-qmp-usb3-phy"; 2101 reg = <0 0x088e9000 0 0x200>, 2102 <0 0x088e8000 0 0x20>; 2103 reg-names = "reg-base", "dp_com"; 2104 status = "disabled"; 2105 #clock-cells = <1>; 2106 #address-cells = <2>; 2107 #size-cells = <2>; 2108 ranges; 2109 2110 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2111 <&rpmhcc RPMH_CXO_CLK>, 2112 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2113 clock-names = "aux", "ref_clk_src", "com_aux"; 2114 2115 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2116 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2117 reset-names = "phy", "common"; 2118 2119 usb_1_ssphy: lanes@88e9200 { 2120 reg = <0 0x088e9200 0 0x200>, 2121 <0 0x088e9400 0 0x200>, 2122 <0 0x088e9c00 0 0x400>, 2123 <0 0x088e9600 0 0x200>, 2124 <0 0x088e9800 0 0x200>, 2125 <0 0x088e9a00 0 0x100>; 2126 #phy-cells = <0>; 2127 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2128 clock-names = "pipe0"; 2129 clock-output-names = "usb3_phy_pipe_clk_src"; 2130 }; 2131 }; 2132 2133 usb_2_qmpphy: phy@88eb000 { 2134 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 2135 reg = <0 0x088eb000 0 0x200>; 2136 status = "disabled"; 2137 #clock-cells = <1>; 2138 #address-cells = <2>; 2139 #size-cells = <2>; 2140 ranges; 2141 2142 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2143 <&rpmhcc RPMH_CXO_CLK>, 2144 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2145 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2146 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2147 2148 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2149 <&gcc GCC_USB3_PHY_SEC_BCR>; 2150 reset-names = "phy", "common"; 2151 2152 usb_2_ssphy: lane@88eb200 { 2153 reg = <0 0x088eb200 0 0x200>, 2154 <0 0x088eb400 0 0x200>, 2155 <0 0x088eb800 0 0x800>; 2156 #phy-cells = <0>; 2157 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2158 clock-names = "pipe0"; 2159 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2160 }; 2161 }; 2162 2163 sdhc_2: sdhci@8804000 { 2164 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 2165 reg = <0 0x08804000 0 0x1000>; 2166 2167 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2168 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2169 interrupt-names = "hc_irq", "pwr_irq"; 2170 2171 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2172 <&gcc GCC_SDCC2_APPS_CLK>, 2173 <&rpmhcc RPMH_CXO_CLK>; 2174 clock-names = "iface", "core", "xo"; 2175 iommus = <&apps_smmu 0x4a0 0x0>; 2176 qcom,dll-config = <0x0007642c>; 2177 qcom,ddr-config = <0x80040868>; 2178 power-domains = <&rpmhpd SM8250_CX>; 2179 operating-points-v2 = <&sdhc2_opp_table>; 2180 2181 status = "disabled"; 2182 2183 sdhc2_opp_table: sdhc2-opp-table { 2184 compatible = "operating-points-v2"; 2185 2186 opp-19200000 { 2187 opp-hz = /bits/ 64 <19200000>; 2188 required-opps = <&rpmhpd_opp_min_svs>; 2189 }; 2190 2191 opp-50000000 { 2192 opp-hz = /bits/ 64 <50000000>; 2193 required-opps = <&rpmhpd_opp_low_svs>; 2194 }; 2195 2196 opp-100000000 { 2197 opp-hz = /bits/ 64 <100000000>; 2198 required-opps = <&rpmhpd_opp_svs>; 2199 }; 2200 2201 opp-202000000 { 2202 opp-hz = /bits/ 64 <202000000>; 2203 required-opps = <&rpmhpd_opp_svs_l1>; 2204 }; 2205 }; 2206 }; 2207 2208 dc_noc: interconnect@90c0000 { 2209 compatible = "qcom,sm8250-dc-noc"; 2210 reg = <0 0x090c0000 0 0x4200>; 2211 #interconnect-cells = <1>; 2212 qcom,bcm-voters = <&apps_bcm_voter>; 2213 }; 2214 2215 gem_noc: interconnect@9100000 { 2216 compatible = "qcom,sm8250-gem-noc"; 2217 reg = <0 0x09100000 0 0xb4000>; 2218 #interconnect-cells = <1>; 2219 qcom,bcm-voters = <&apps_bcm_voter>; 2220 }; 2221 2222 npu_noc: interconnect@9990000 { 2223 compatible = "qcom,sm8250-npu-noc"; 2224 reg = <0 0x09990000 0 0x1600>; 2225 #interconnect-cells = <1>; 2226 qcom,bcm-voters = <&apps_bcm_voter>; 2227 }; 2228 2229 usb_1: usb@a6f8800 { 2230 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 2231 reg = <0 0x0a6f8800 0 0x400>; 2232 status = "disabled"; 2233 #address-cells = <2>; 2234 #size-cells = <2>; 2235 ranges; 2236 dma-ranges; 2237 2238 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2239 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2240 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2241 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2242 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2243 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2244 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2245 "sleep", "xo"; 2246 2247 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2248 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2249 assigned-clock-rates = <19200000>, <200000000>; 2250 2251 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2252 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2253 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2254 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2255 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2256 "dm_hs_phy_irq", "ss_phy_irq"; 2257 2258 power-domains = <&gcc USB30_PRIM_GDSC>; 2259 2260 resets = <&gcc GCC_USB30_PRIM_BCR>; 2261 2262 usb_1_dwc3: dwc3@a600000 { 2263 compatible = "snps,dwc3"; 2264 reg = <0 0x0a600000 0 0xcd00>; 2265 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2266 iommus = <&apps_smmu 0x0 0x0>; 2267 snps,dis_u2_susphy_quirk; 2268 snps,dis_enblslpm_quirk; 2269 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2270 phy-names = "usb2-phy", "usb3-phy"; 2271 }; 2272 }; 2273 2274 system-cache-controller@9200000 { 2275 compatible = "qcom,sm8250-llcc"; 2276 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 2277 reg-names = "llcc_base", "llcc_broadcast_base"; 2278 }; 2279 2280 usb_2: usb@a8f8800 { 2281 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 2282 reg = <0 0x0a8f8800 0 0x400>; 2283 status = "disabled"; 2284 #address-cells = <2>; 2285 #size-cells = <2>; 2286 ranges; 2287 dma-ranges; 2288 2289 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2290 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2291 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2292 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2293 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2294 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2295 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2296 "sleep", "xo"; 2297 2298 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2299 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2300 assigned-clock-rates = <19200000>, <200000000>; 2301 2302 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2303 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 2304 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2305 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 2306 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2307 "dm_hs_phy_irq", "ss_phy_irq"; 2308 2309 power-domains = <&gcc USB30_SEC_GDSC>; 2310 2311 resets = <&gcc GCC_USB30_SEC_BCR>; 2312 2313 usb_2_dwc3: dwc3@a800000 { 2314 compatible = "snps,dwc3"; 2315 reg = <0 0x0a800000 0 0xcd00>; 2316 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2317 iommus = <&apps_smmu 0x20 0>; 2318 snps,dis_u2_susphy_quirk; 2319 snps,dis_enblslpm_quirk; 2320 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2321 phy-names = "usb2-phy", "usb3-phy"; 2322 }; 2323 }; 2324 2325 mdss: mdss@ae00000 { 2326 compatible = "qcom,sdm845-mdss"; 2327 reg = <0 0x0ae00000 0 0x1000>; 2328 reg-names = "mdss"; 2329 2330 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>, 2331 <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 2332 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 2333 interconnect-names = "notused", "mdp0-mem", "mdp1-mem"; 2334 2335 power-domains = <&dispcc MDSS_GDSC>; 2336 2337 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2338 <&gcc GCC_DISP_HF_AXI_CLK>, 2339 <&gcc GCC_DISP_SF_AXI_CLK>, 2340 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2341 clock-names = "iface", "bus", "nrt_bus", "core"; 2342 2343 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2344 assigned-clock-rates = <460000000>; 2345 2346 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2347 interrupt-controller; 2348 #interrupt-cells = <1>; 2349 2350 iommus = <&apps_smmu 0x820 0x402>; 2351 2352 status = "disabled"; 2353 2354 #address-cells = <2>; 2355 #size-cells = <2>; 2356 ranges; 2357 2358 mdss_mdp: mdp@ae01000 { 2359 compatible = "qcom,sdm845-dpu"; 2360 reg = <0 0x0ae01000 0 0x8f000>, 2361 <0 0x0aeb0000 0 0x2008>; 2362 reg-names = "mdp", "vbif"; 2363 2364 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2365 <&gcc GCC_DISP_HF_AXI_CLK>, 2366 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2367 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2368 clock-names = "iface", "bus", "core", "vsync"; 2369 2370 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2371 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2372 assigned-clock-rates = <460000000>, 2373 <19200000>; 2374 2375 operating-points-v2 = <&mdp_opp_table>; 2376 power-domains = <&rpmhpd SM8250_MMCX>; 2377 2378 interrupt-parent = <&mdss>; 2379 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2380 2381 status = "disabled"; 2382 2383 ports { 2384 #address-cells = <1>; 2385 #size-cells = <0>; 2386 2387 port@0 { 2388 reg = <0>; 2389 dpu_intf1_out: endpoint { 2390 remote-endpoint = <&dsi0_in>; 2391 }; 2392 }; 2393 2394 port@1 { 2395 reg = <1>; 2396 dpu_intf2_out: endpoint { 2397 remote-endpoint = <&dsi1_in>; 2398 }; 2399 }; 2400 }; 2401 2402 mdp_opp_table: mdp-opp-table { 2403 compatible = "operating-points-v2"; 2404 2405 opp-200000000 { 2406 opp-hz = /bits/ 64 <200000000>; 2407 required-opps = <&rpmhpd_opp_low_svs>; 2408 }; 2409 2410 opp-300000000 { 2411 opp-hz = /bits/ 64 <300000000>; 2412 required-opps = <&rpmhpd_opp_svs>; 2413 }; 2414 2415 opp-345000000 { 2416 opp-hz = /bits/ 64 <345000000>; 2417 required-opps = <&rpmhpd_opp_svs_l1>; 2418 }; 2419 2420 opp-460000000 { 2421 opp-hz = /bits/ 64 <460000000>; 2422 required-opps = <&rpmhpd_opp_nom>; 2423 }; 2424 }; 2425 }; 2426 2427 dsi0: dsi@ae94000 { 2428 compatible = "qcom,mdss-dsi-ctrl"; 2429 reg = <0 0x0ae94000 0 0x400>; 2430 reg-names = "dsi_ctrl"; 2431 2432 interrupt-parent = <&mdss>; 2433 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 2434 2435 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2436 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2437 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2438 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2439 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2440 <&gcc GCC_DISP_HF_AXI_CLK>; 2441 clock-names = "byte", 2442 "byte_intf", 2443 "pixel", 2444 "core", 2445 "iface", 2446 "bus"; 2447 2448 operating-points-v2 = <&dsi_opp_table>; 2449 power-domains = <&rpmhpd SM8250_MMCX>; 2450 2451 phys = <&dsi0_phy>; 2452 phy-names = "dsi"; 2453 2454 status = "disabled"; 2455 2456 ports { 2457 #address-cells = <1>; 2458 #size-cells = <0>; 2459 2460 port@0 { 2461 reg = <0>; 2462 dsi0_in: endpoint { 2463 remote-endpoint = <&dpu_intf1_out>; 2464 }; 2465 }; 2466 2467 port@1 { 2468 reg = <1>; 2469 dsi0_out: endpoint { 2470 }; 2471 }; 2472 }; 2473 }; 2474 2475 dsi0_phy: dsi-phy@ae94400 { 2476 compatible = "qcom,dsi-phy-7nm"; 2477 reg = <0 0x0ae94400 0 0x200>, 2478 <0 0x0ae94600 0 0x280>, 2479 <0 0x0ae94900 0 0x260>; 2480 reg-names = "dsi_phy", 2481 "dsi_phy_lane", 2482 "dsi_pll"; 2483 2484 #clock-cells = <1>; 2485 #phy-cells = <0>; 2486 2487 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2488 <&rpmhcc RPMH_CXO_CLK>; 2489 clock-names = "iface", "ref"; 2490 2491 status = "disabled"; 2492 }; 2493 2494 dsi1: dsi@ae96000 { 2495 compatible = "qcom,mdss-dsi-ctrl"; 2496 reg = <0 0x0ae96000 0 0x400>; 2497 reg-names = "dsi_ctrl"; 2498 2499 interrupt-parent = <&mdss>; 2500 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 2501 2502 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2503 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2504 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2505 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2506 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2507 <&gcc GCC_DISP_HF_AXI_CLK>; 2508 clock-names = "byte", 2509 "byte_intf", 2510 "pixel", 2511 "core", 2512 "iface", 2513 "bus"; 2514 2515 operating-points-v2 = <&dsi_opp_table>; 2516 power-domains = <&rpmhpd SM8250_MMCX>; 2517 2518 phys = <&dsi1_phy>; 2519 phy-names = "dsi"; 2520 2521 status = "disabled"; 2522 2523 ports { 2524 #address-cells = <1>; 2525 #size-cells = <0>; 2526 2527 port@0 { 2528 reg = <0>; 2529 dsi1_in: endpoint { 2530 remote-endpoint = <&dpu_intf2_out>; 2531 }; 2532 }; 2533 2534 port@1 { 2535 reg = <1>; 2536 dsi1_out: endpoint { 2537 }; 2538 }; 2539 }; 2540 }; 2541 2542 dsi1_phy: dsi-phy@ae96400 { 2543 compatible = "qcom,dsi-phy-7nm"; 2544 reg = <0 0x0ae96400 0 0x200>, 2545 <0 0x0ae96600 0 0x280>, 2546 <0 0x0ae96900 0 0x260>; 2547 reg-names = "dsi_phy", 2548 "dsi_phy_lane", 2549 "dsi_pll"; 2550 2551 #clock-cells = <1>; 2552 #phy-cells = <0>; 2553 2554 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2555 <&rpmhcc RPMH_CXO_CLK>; 2556 clock-names = "iface", "ref"; 2557 2558 status = "disabled"; 2559 2560 dsi_opp_table: dsi-opp-table { 2561 compatible = "operating-points-v2"; 2562 2563 opp-187500000 { 2564 opp-hz = /bits/ 64 <187500000>; 2565 required-opps = <&rpmhpd_opp_low_svs>; 2566 }; 2567 2568 opp-300000000 { 2569 opp-hz = /bits/ 64 <300000000>; 2570 required-opps = <&rpmhpd_opp_svs>; 2571 }; 2572 2573 opp-358000000 { 2574 opp-hz = /bits/ 64 <358000000>; 2575 required-opps = <&rpmhpd_opp_svs_l1>; 2576 }; 2577 }; 2578 }; 2579 }; 2580 2581 dispcc: clock-controller@af00000 { 2582 compatible = "qcom,sm8250-dispcc"; 2583 reg = <0 0x0af00000 0 0x20000>; 2584 mmcx-supply = <&mmcx_reg>; 2585 clocks = <&rpmhcc RPMH_CXO_CLK>, 2586 <&dsi0_phy 0>, 2587 <&dsi0_phy 1>, 2588 <&dsi1_phy 0>, 2589 <&dsi1_phy 1>, 2590 <0>, 2591 <0>, 2592 <0>, 2593 <0>, 2594 <0>, 2595 <0>, 2596 <0>, 2597 <0>, 2598 <&sleep_clk>; 2599 clock-names = "bi_tcxo", 2600 "dsi0_phy_pll_out_byteclk", 2601 "dsi0_phy_pll_out_dsiclk", 2602 "dsi1_phy_pll_out_byteclk", 2603 "dsi1_phy_pll_out_dsiclk", 2604 "dp_link_clk_divsel_ten", 2605 "dp_vco_divided_clk_src_mux", 2606 "dptx1_phy_pll_link_clk", 2607 "dptx1_phy_pll_vco_div_clk", 2608 "dptx2_phy_pll_link_clk", 2609 "dptx2_phy_pll_vco_div_clk", 2610 "edp_phy_pll_link_clk", 2611 "edp_phy_pll_vco_div_clk", 2612 "sleep_clk"; 2613 #clock-cells = <1>; 2614 #reset-cells = <1>; 2615 #power-domain-cells = <1>; 2616 }; 2617 2618 pdc: interrupt-controller@b220000 { 2619 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 2620 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 2621 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2622 <125 63 1>, <126 716 12>; 2623 #interrupt-cells = <2>; 2624 interrupt-parent = <&intc>; 2625 interrupt-controller; 2626 }; 2627 2628 tsens0: thermal-sensor@c263000 { 2629 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 2630 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2631 <0 0x0c222000 0 0x1ff>; /* SROT */ 2632 #qcom,sensors = <16>; 2633 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2634 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2635 interrupt-names = "uplow", "critical"; 2636 #thermal-sensor-cells = <1>; 2637 }; 2638 2639 tsens1: thermal-sensor@c265000 { 2640 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 2641 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2642 <0 0x0c223000 0 0x1ff>; /* SROT */ 2643 #qcom,sensors = <9>; 2644 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2645 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2646 interrupt-names = "uplow", "critical"; 2647 #thermal-sensor-cells = <1>; 2648 }; 2649 2650 aoss_qmp: qmp@c300000 { 2651 compatible = "qcom,sm8250-aoss-qmp"; 2652 reg = <0 0x0c300000 0 0x100000>; 2653 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2654 IPCC_MPROC_SIGNAL_GLINK_QMP 2655 IRQ_TYPE_EDGE_RISING>; 2656 mboxes = <&ipcc IPCC_CLIENT_AOP 2657 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2658 2659 #clock-cells = <0>; 2660 #power-domain-cells = <1>; 2661 }; 2662 2663 spmi_bus: spmi@c440000 { 2664 compatible = "qcom,spmi-pmic-arb"; 2665 reg = <0x0 0x0c440000 0x0 0x0001100>, 2666 <0x0 0x0c600000 0x0 0x2000000>, 2667 <0x0 0x0e600000 0x0 0x0100000>, 2668 <0x0 0x0e700000 0x0 0x00a0000>, 2669 <0x0 0x0c40a000 0x0 0x0026000>; 2670 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2671 interrupt-names = "periph_irq"; 2672 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2673 qcom,ee = <0>; 2674 qcom,channel = <0>; 2675 #address-cells = <2>; 2676 #size-cells = <0>; 2677 interrupt-controller; 2678 #interrupt-cells = <4>; 2679 }; 2680 2681 tlmm: pinctrl@f100000 { 2682 compatible = "qcom,sm8250-pinctrl"; 2683 reg = <0 0x0f100000 0 0x300000>, 2684 <0 0x0f500000 0 0x300000>, 2685 <0 0x0f900000 0 0x300000>; 2686 reg-names = "west", "south", "north"; 2687 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2688 gpio-controller; 2689 #gpio-cells = <2>; 2690 interrupt-controller; 2691 #interrupt-cells = <2>; 2692 gpio-ranges = <&tlmm 0 0 180>; 2693 wakeup-parent = <&pdc>; 2694 2695 pri_mi2s_active: pri-mi2s-active { 2696 sclk { 2697 pins = "gpio138"; 2698 function = "mi2s0_sck"; 2699 drive-strength = <8>; 2700 bias-disable; 2701 }; 2702 2703 ws { 2704 pins = "gpio141"; 2705 function = "mi2s0_ws"; 2706 drive-strength = <8>; 2707 output-high; 2708 }; 2709 2710 data0 { 2711 pins = "gpio139"; 2712 function = "mi2s0_data0"; 2713 drive-strength = <8>; 2714 bias-disable; 2715 output-high; 2716 }; 2717 2718 data1 { 2719 pins = "gpio140"; 2720 function = "mi2s0_data1"; 2721 drive-strength = <8>; 2722 output-high; 2723 }; 2724 }; 2725 2726 qup_i2c0_default: qup-i2c0-default { 2727 mux { 2728 pins = "gpio28", "gpio29"; 2729 function = "qup0"; 2730 }; 2731 2732 config { 2733 pins = "gpio28", "gpio29"; 2734 drive-strength = <2>; 2735 bias-disable; 2736 }; 2737 }; 2738 2739 qup_i2c1_default: qup-i2c1-default { 2740 pinmux { 2741 pins = "gpio4", "gpio5"; 2742 function = "qup1"; 2743 }; 2744 2745 config { 2746 pins = "gpio4", "gpio5"; 2747 drive-strength = <2>; 2748 bias-disable; 2749 }; 2750 }; 2751 2752 qup_i2c2_default: qup-i2c2-default { 2753 mux { 2754 pins = "gpio115", "gpio116"; 2755 function = "qup2"; 2756 }; 2757 2758 config { 2759 pins = "gpio115", "gpio116"; 2760 drive-strength = <2>; 2761 bias-disable; 2762 }; 2763 }; 2764 2765 qup_i2c3_default: qup-i2c3-default { 2766 mux { 2767 pins = "gpio119", "gpio120"; 2768 function = "qup3"; 2769 }; 2770 2771 config { 2772 pins = "gpio119", "gpio120"; 2773 drive-strength = <2>; 2774 bias-disable; 2775 }; 2776 }; 2777 2778 qup_i2c4_default: qup-i2c4-default { 2779 mux { 2780 pins = "gpio8", "gpio9"; 2781 function = "qup4"; 2782 }; 2783 2784 config { 2785 pins = "gpio8", "gpio9"; 2786 drive-strength = <2>; 2787 bias-disable; 2788 }; 2789 }; 2790 2791 qup_i2c5_default: qup-i2c5-default { 2792 mux { 2793 pins = "gpio12", "gpio13"; 2794 function = "qup5"; 2795 }; 2796 2797 config { 2798 pins = "gpio12", "gpio13"; 2799 drive-strength = <2>; 2800 bias-disable; 2801 }; 2802 }; 2803 2804 qup_i2c6_default: qup-i2c6-default { 2805 mux { 2806 pins = "gpio16", "gpio17"; 2807 function = "qup6"; 2808 }; 2809 2810 config { 2811 pins = "gpio16", "gpio17"; 2812 drive-strength = <2>; 2813 bias-disable; 2814 }; 2815 }; 2816 2817 qup_i2c7_default: qup-i2c7-default { 2818 mux { 2819 pins = "gpio20", "gpio21"; 2820 function = "qup7"; 2821 }; 2822 2823 config { 2824 pins = "gpio20", "gpio21"; 2825 drive-strength = <2>; 2826 bias-disable; 2827 }; 2828 }; 2829 2830 qup_i2c8_default: qup-i2c8-default { 2831 mux { 2832 pins = "gpio24", "gpio25"; 2833 function = "qup8"; 2834 }; 2835 2836 config { 2837 pins = "gpio24", "gpio25"; 2838 drive-strength = <2>; 2839 bias-disable; 2840 }; 2841 }; 2842 2843 qup_i2c9_default: qup-i2c9-default { 2844 mux { 2845 pins = "gpio125", "gpio126"; 2846 function = "qup9"; 2847 }; 2848 2849 config { 2850 pins = "gpio125", "gpio126"; 2851 drive-strength = <2>; 2852 bias-disable; 2853 }; 2854 }; 2855 2856 qup_i2c10_default: qup-i2c10-default { 2857 mux { 2858 pins = "gpio129", "gpio130"; 2859 function = "qup10"; 2860 }; 2861 2862 config { 2863 pins = "gpio129", "gpio130"; 2864 drive-strength = <2>; 2865 bias-disable; 2866 }; 2867 }; 2868 2869 qup_i2c11_default: qup-i2c11-default { 2870 mux { 2871 pins = "gpio60", "gpio61"; 2872 function = "qup11"; 2873 }; 2874 2875 config { 2876 pins = "gpio60", "gpio61"; 2877 drive-strength = <2>; 2878 bias-disable; 2879 }; 2880 }; 2881 2882 qup_i2c12_default: qup-i2c12-default { 2883 mux { 2884 pins = "gpio32", "gpio33"; 2885 function = "qup12"; 2886 }; 2887 2888 config { 2889 pins = "gpio32", "gpio33"; 2890 drive-strength = <2>; 2891 bias-disable; 2892 }; 2893 }; 2894 2895 qup_i2c13_default: qup-i2c13-default { 2896 mux { 2897 pins = "gpio36", "gpio37"; 2898 function = "qup13"; 2899 }; 2900 2901 config { 2902 pins = "gpio36", "gpio37"; 2903 drive-strength = <2>; 2904 bias-disable; 2905 }; 2906 }; 2907 2908 qup_i2c14_default: qup-i2c14-default { 2909 mux { 2910 pins = "gpio40", "gpio41"; 2911 function = "qup14"; 2912 }; 2913 2914 config { 2915 pins = "gpio40", "gpio41"; 2916 drive-strength = <2>; 2917 bias-disable; 2918 }; 2919 }; 2920 2921 qup_i2c15_default: qup-i2c15-default { 2922 mux { 2923 pins = "gpio44", "gpio45"; 2924 function = "qup15"; 2925 }; 2926 2927 config { 2928 pins = "gpio44", "gpio45"; 2929 drive-strength = <2>; 2930 bias-disable; 2931 }; 2932 }; 2933 2934 qup_i2c16_default: qup-i2c16-default { 2935 mux { 2936 pins = "gpio48", "gpio49"; 2937 function = "qup16"; 2938 }; 2939 2940 config { 2941 pins = "gpio48", "gpio49"; 2942 drive-strength = <2>; 2943 bias-disable; 2944 }; 2945 }; 2946 2947 qup_i2c17_default: qup-i2c17-default { 2948 mux { 2949 pins = "gpio52", "gpio53"; 2950 function = "qup17"; 2951 }; 2952 2953 config { 2954 pins = "gpio52", "gpio53"; 2955 drive-strength = <2>; 2956 bias-disable; 2957 }; 2958 }; 2959 2960 qup_i2c18_default: qup-i2c18-default { 2961 mux { 2962 pins = "gpio56", "gpio57"; 2963 function = "qup18"; 2964 }; 2965 2966 config { 2967 pins = "gpio56", "gpio57"; 2968 drive-strength = <2>; 2969 bias-disable; 2970 }; 2971 }; 2972 2973 qup_i2c19_default: qup-i2c19-default { 2974 mux { 2975 pins = "gpio0", "gpio1"; 2976 function = "qup19"; 2977 }; 2978 2979 config { 2980 pins = "gpio0", "gpio1"; 2981 drive-strength = <2>; 2982 bias-disable; 2983 }; 2984 }; 2985 2986 qup_spi0_default: qup-spi0-default { 2987 mux { 2988 pins = "gpio28", "gpio29", 2989 "gpio30", "gpio31"; 2990 function = "qup0"; 2991 }; 2992 2993 config { 2994 pins = "gpio28", "gpio29", 2995 "gpio30", "gpio31"; 2996 drive-strength = <6>; 2997 bias-disable; 2998 }; 2999 }; 3000 3001 qup_spi1_default: qup-spi1-default { 3002 mux { 3003 pins = "gpio4", "gpio5", 3004 "gpio6", "gpio7"; 3005 function = "qup1"; 3006 }; 3007 3008 config { 3009 pins = "gpio4", "gpio5", 3010 "gpio6", "gpio7"; 3011 drive-strength = <6>; 3012 bias-disable; 3013 }; 3014 }; 3015 3016 qup_spi2_default: qup-spi2-default { 3017 mux { 3018 pins = "gpio115", "gpio116", 3019 "gpio117", "gpio118"; 3020 function = "qup2"; 3021 }; 3022 3023 config { 3024 pins = "gpio115", "gpio116", 3025 "gpio117", "gpio118"; 3026 drive-strength = <6>; 3027 bias-disable; 3028 }; 3029 }; 3030 3031 qup_spi3_default: qup-spi3-default { 3032 mux { 3033 pins = "gpio119", "gpio120", 3034 "gpio121", "gpio122"; 3035 function = "qup3"; 3036 }; 3037 3038 config { 3039 pins = "gpio119", "gpio120", 3040 "gpio121", "gpio122"; 3041 drive-strength = <6>; 3042 bias-disable; 3043 }; 3044 }; 3045 3046 qup_spi4_default: qup-spi4-default { 3047 mux { 3048 pins = "gpio8", "gpio9", 3049 "gpio10", "gpio11"; 3050 function = "qup4"; 3051 }; 3052 3053 config { 3054 pins = "gpio8", "gpio9", 3055 "gpio10", "gpio11"; 3056 drive-strength = <6>; 3057 bias-disable; 3058 }; 3059 }; 3060 3061 qup_spi5_default: qup-spi5-default { 3062 mux { 3063 pins = "gpio12", "gpio13", 3064 "gpio14", "gpio15"; 3065 function = "qup5"; 3066 }; 3067 3068 config { 3069 pins = "gpio12", "gpio13", 3070 "gpio14", "gpio15"; 3071 drive-strength = <6>; 3072 bias-disable; 3073 }; 3074 }; 3075 3076 qup_spi6_default: qup-spi6-default { 3077 mux { 3078 pins = "gpio16", "gpio17", 3079 "gpio18", "gpio19"; 3080 function = "qup6"; 3081 }; 3082 3083 config { 3084 pins = "gpio16", "gpio17", 3085 "gpio18", "gpio19"; 3086 drive-strength = <6>; 3087 bias-disable; 3088 }; 3089 }; 3090 3091 qup_spi7_default: qup-spi7-default { 3092 mux { 3093 pins = "gpio20", "gpio21", 3094 "gpio22", "gpio23"; 3095 function = "qup7"; 3096 }; 3097 3098 config { 3099 pins = "gpio20", "gpio21", 3100 "gpio22", "gpio23"; 3101 drive-strength = <6>; 3102 bias-disable; 3103 }; 3104 }; 3105 3106 qup_spi8_default: qup-spi8-default { 3107 mux { 3108 pins = "gpio24", "gpio25", 3109 "gpio26", "gpio27"; 3110 function = "qup8"; 3111 }; 3112 3113 config { 3114 pins = "gpio24", "gpio25", 3115 "gpio26", "gpio27"; 3116 drive-strength = <6>; 3117 bias-disable; 3118 }; 3119 }; 3120 3121 qup_spi9_default: qup-spi9-default { 3122 mux { 3123 pins = "gpio125", "gpio126", 3124 "gpio127", "gpio128"; 3125 function = "qup9"; 3126 }; 3127 3128 config { 3129 pins = "gpio125", "gpio126", 3130 "gpio127", "gpio128"; 3131 drive-strength = <6>; 3132 bias-disable; 3133 }; 3134 }; 3135 3136 qup_spi10_default: qup-spi10-default { 3137 mux { 3138 pins = "gpio129", "gpio130", 3139 "gpio131", "gpio132"; 3140 function = "qup10"; 3141 }; 3142 3143 config { 3144 pins = "gpio129", "gpio130", 3145 "gpio131", "gpio132"; 3146 drive-strength = <6>; 3147 bias-disable; 3148 }; 3149 }; 3150 3151 qup_spi11_default: qup-spi11-default { 3152 mux { 3153 pins = "gpio60", "gpio61", 3154 "gpio62", "gpio63"; 3155 function = "qup11"; 3156 }; 3157 3158 config { 3159 pins = "gpio60", "gpio61", 3160 "gpio62", "gpio63"; 3161 drive-strength = <6>; 3162 bias-disable; 3163 }; 3164 }; 3165 3166 qup_spi12_default: qup-spi12-default { 3167 mux { 3168 pins = "gpio32", "gpio33", 3169 "gpio34", "gpio35"; 3170 function = "qup12"; 3171 }; 3172 3173 config { 3174 pins = "gpio32", "gpio33", 3175 "gpio34", "gpio35"; 3176 drive-strength = <6>; 3177 bias-disable; 3178 }; 3179 }; 3180 3181 qup_spi13_default: qup-spi13-default { 3182 mux { 3183 pins = "gpio36", "gpio37", 3184 "gpio38", "gpio39"; 3185 function = "qup13"; 3186 }; 3187 3188 config { 3189 pins = "gpio36", "gpio37", 3190 "gpio38", "gpio39"; 3191 drive-strength = <6>; 3192 bias-disable; 3193 }; 3194 }; 3195 3196 qup_spi14_default: qup-spi14-default { 3197 mux { 3198 pins = "gpio40", "gpio41", 3199 "gpio42", "gpio43"; 3200 function = "qup14"; 3201 }; 3202 3203 config { 3204 pins = "gpio40", "gpio41", 3205 "gpio42", "gpio43"; 3206 drive-strength = <6>; 3207 bias-disable; 3208 }; 3209 }; 3210 3211 qup_spi15_default: qup-spi15-default { 3212 mux { 3213 pins = "gpio44", "gpio45", 3214 "gpio46", "gpio47"; 3215 function = "qup15"; 3216 }; 3217 3218 config { 3219 pins = "gpio44", "gpio45", 3220 "gpio46", "gpio47"; 3221 drive-strength = <6>; 3222 bias-disable; 3223 }; 3224 }; 3225 3226 qup_spi16_default: qup-spi16-default { 3227 mux { 3228 pins = "gpio48", "gpio49", 3229 "gpio50", "gpio51"; 3230 function = "qup16"; 3231 }; 3232 3233 config { 3234 pins = "gpio48", "gpio49", 3235 "gpio50", "gpio51"; 3236 drive-strength = <6>; 3237 bias-disable; 3238 }; 3239 }; 3240 3241 qup_spi17_default: qup-spi17-default { 3242 mux { 3243 pins = "gpio52", "gpio53", 3244 "gpio54", "gpio55"; 3245 function = "qup17"; 3246 }; 3247 3248 config { 3249 pins = "gpio52", "gpio53", 3250 "gpio54", "gpio55"; 3251 drive-strength = <6>; 3252 bias-disable; 3253 }; 3254 }; 3255 3256 qup_spi18_default: qup-spi18-default { 3257 mux { 3258 pins = "gpio56", "gpio57", 3259 "gpio58", "gpio59"; 3260 function = "qup18"; 3261 }; 3262 3263 config { 3264 pins = "gpio56", "gpio57", 3265 "gpio58", "gpio59"; 3266 drive-strength = <6>; 3267 bias-disable; 3268 }; 3269 }; 3270 3271 qup_spi19_default: qup-spi19-default { 3272 mux { 3273 pins = "gpio0", "gpio1", 3274 "gpio2", "gpio3"; 3275 function = "qup19"; 3276 }; 3277 3278 config { 3279 pins = "gpio0", "gpio1", 3280 "gpio2", "gpio3"; 3281 drive-strength = <6>; 3282 bias-disable; 3283 }; 3284 }; 3285 3286 qup_uart2_default: qup-uart2-default { 3287 mux { 3288 pins = "gpio117", "gpio118"; 3289 function = "qup2"; 3290 }; 3291 }; 3292 3293 qup_uart6_default: qup-uart6-default { 3294 mux { 3295 pins = "gpio16", "gpio17", 3296 "gpio18", "gpio19"; 3297 function = "qup6"; 3298 }; 3299 }; 3300 3301 qup_uart12_default: qup-uart12-default { 3302 mux { 3303 pins = "gpio34", "gpio35"; 3304 function = "qup12"; 3305 }; 3306 }; 3307 3308 qup_uart17_default: qup-uart17-default { 3309 mux { 3310 pins = "gpio52", "gpio53", 3311 "gpio54", "gpio55"; 3312 function = "qup17"; 3313 }; 3314 }; 3315 3316 qup_uart18_default: qup-uart18-default { 3317 mux { 3318 pins = "gpio58", "gpio59"; 3319 function = "qup18"; 3320 }; 3321 }; 3322 3323 tert_mi2s_active: tert-mi2s-active { 3324 sck { 3325 pins = "gpio133"; 3326 function = "mi2s2_sck"; 3327 drive-strength = <8>; 3328 bias-disable; 3329 }; 3330 3331 data0 { 3332 pins = "gpio134"; 3333 function = "mi2s2_data0"; 3334 drive-strength = <8>; 3335 bias-disable; 3336 output-high; 3337 }; 3338 3339 ws { 3340 pins = "gpio135"; 3341 function = "mi2s2_ws"; 3342 drive-strength = <8>; 3343 output-high; 3344 }; 3345 }; 3346 }; 3347 3348 apps_smmu: iommu@15000000 { 3349 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 3350 reg = <0 0x15000000 0 0x100000>; 3351 #iommu-cells = <2>; 3352 #global-interrupts = <2>; 3353 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3354 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3360 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3362 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3387 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3388 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3389 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3390 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3391 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3393 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3394 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3395 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3396 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3397 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3398 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3399 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3400 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3401 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3402 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3403 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3404 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3405 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3406 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3407 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3408 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3409 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3410 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3411 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3412 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3413 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3414 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3415 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3416 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3417 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3418 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3419 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3420 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3421 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3422 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3423 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3424 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3425 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3426 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3427 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3428 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3429 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3430 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3431 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3432 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3433 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3434 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3435 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3436 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3437 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3438 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3439 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3440 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3441 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3442 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3443 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3444 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3445 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3446 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3447 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3448 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3449 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3450 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3451 }; 3452 3453 adsp: remoteproc@17300000 { 3454 compatible = "qcom,sm8250-adsp-pas"; 3455 reg = <0 0x17300000 0 0x100>; 3456 3457 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 3458 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3459 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3460 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3461 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3462 interrupt-names = "wdog", "fatal", "ready", 3463 "handover", "stop-ack"; 3464 3465 clocks = <&rpmhcc RPMH_CXO_CLK>; 3466 clock-names = "xo"; 3467 3468 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, 3469 <&rpmhpd SM8250_LCX>, 3470 <&rpmhpd SM8250_LMX>; 3471 power-domain-names = "load_state", "lcx", "lmx"; 3472 3473 memory-region = <&adsp_mem>; 3474 3475 qcom,smem-states = <&smp2p_adsp_out 0>; 3476 qcom,smem-state-names = "stop"; 3477 3478 status = "disabled"; 3479 3480 glink-edge { 3481 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3482 IPCC_MPROC_SIGNAL_GLINK_QMP 3483 IRQ_TYPE_EDGE_RISING>; 3484 mboxes = <&ipcc IPCC_CLIENT_LPASS 3485 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3486 3487 label = "lpass"; 3488 qcom,remote-pid = <2>; 3489 3490 apr { 3491 compatible = "qcom,apr-v2"; 3492 qcom,glink-channels = "apr_audio_svc"; 3493 qcom,apr-domain = <APR_DOMAIN_ADSP>; 3494 #address-cells = <1>; 3495 #size-cells = <0>; 3496 3497 apr-service@3 { 3498 reg = <APR_SVC_ADSP_CORE>; 3499 compatible = "qcom,q6core"; 3500 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3501 }; 3502 3503 q6afe: apr-service@4 { 3504 compatible = "qcom,q6afe"; 3505 reg = <APR_SVC_AFE>; 3506 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3507 q6afedai: dais { 3508 compatible = "qcom,q6afe-dais"; 3509 #address-cells = <1>; 3510 #size-cells = <0>; 3511 #sound-dai-cells = <1>; 3512 }; 3513 3514 q6afecc: cc { 3515 compatible = "qcom,q6afe-clocks"; 3516 #clock-cells = <2>; 3517 }; 3518 }; 3519 3520 q6asm: apr-service@7 { 3521 compatible = "qcom,q6asm"; 3522 reg = <APR_SVC_ASM>; 3523 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3524 q6asmdai: dais { 3525 compatible = "qcom,q6asm-dais"; 3526 #address-cells = <1>; 3527 #size-cells = <0>; 3528 #sound-dai-cells = <1>; 3529 iommus = <&apps_smmu 0x1801 0x0>; 3530 }; 3531 }; 3532 3533 q6adm: apr-service@8 { 3534 compatible = "qcom,q6adm"; 3535 reg = <APR_SVC_ADM>; 3536 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3537 q6routing: routing { 3538 compatible = "qcom,q6adm-routing"; 3539 #sound-dai-cells = <0>; 3540 }; 3541 }; 3542 }; 3543 3544 fastrpc { 3545 compatible = "qcom,fastrpc"; 3546 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3547 label = "adsp"; 3548 #address-cells = <1>; 3549 #size-cells = <0>; 3550 3551 compute-cb@3 { 3552 compatible = "qcom,fastrpc-compute-cb"; 3553 reg = <3>; 3554 iommus = <&apps_smmu 0x1803 0x0>; 3555 }; 3556 3557 compute-cb@4 { 3558 compatible = "qcom,fastrpc-compute-cb"; 3559 reg = <4>; 3560 iommus = <&apps_smmu 0x1804 0x0>; 3561 }; 3562 3563 compute-cb@5 { 3564 compatible = "qcom,fastrpc-compute-cb"; 3565 reg = <5>; 3566 iommus = <&apps_smmu 0x1805 0x0>; 3567 }; 3568 }; 3569 }; 3570 }; 3571 3572 intc: interrupt-controller@17a00000 { 3573 compatible = "arm,gic-v3"; 3574 #interrupt-cells = <3>; 3575 interrupt-controller; 3576 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3577 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3578 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3579 }; 3580 3581 watchdog@17c10000 { 3582 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 3583 reg = <0 0x17c10000 0 0x1000>; 3584 clocks = <&sleep_clk>; 3585 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3586 }; 3587 3588 timer@17c20000 { 3589 #address-cells = <2>; 3590 #size-cells = <2>; 3591 ranges; 3592 compatible = "arm,armv7-timer-mem"; 3593 reg = <0x0 0x17c20000 0x0 0x1000>; 3594 clock-frequency = <19200000>; 3595 3596 frame@17c21000 { 3597 frame-number = <0>; 3598 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3599 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3600 reg = <0x0 0x17c21000 0x0 0x1000>, 3601 <0x0 0x17c22000 0x0 0x1000>; 3602 }; 3603 3604 frame@17c23000 { 3605 frame-number = <1>; 3606 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3607 reg = <0x0 0x17c23000 0x0 0x1000>; 3608 status = "disabled"; 3609 }; 3610 3611 frame@17c25000 { 3612 frame-number = <2>; 3613 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3614 reg = <0x0 0x17c25000 0x0 0x1000>; 3615 status = "disabled"; 3616 }; 3617 3618 frame@17c27000 { 3619 frame-number = <3>; 3620 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3621 reg = <0x0 0x17c27000 0x0 0x1000>; 3622 status = "disabled"; 3623 }; 3624 3625 frame@17c29000 { 3626 frame-number = <4>; 3627 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3628 reg = <0x0 0x17c29000 0x0 0x1000>; 3629 status = "disabled"; 3630 }; 3631 3632 frame@17c2b000 { 3633 frame-number = <5>; 3634 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3635 reg = <0x0 0x17c2b000 0x0 0x1000>; 3636 status = "disabled"; 3637 }; 3638 3639 frame@17c2d000 { 3640 frame-number = <6>; 3641 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3642 reg = <0x0 0x17c2d000 0x0 0x1000>; 3643 status = "disabled"; 3644 }; 3645 }; 3646 3647 apps_rsc: rsc@18200000 { 3648 label = "apps_rsc"; 3649 compatible = "qcom,rpmh-rsc"; 3650 reg = <0x0 0x18200000 0x0 0x10000>, 3651 <0x0 0x18210000 0x0 0x10000>, 3652 <0x0 0x18220000 0x0 0x10000>; 3653 reg-names = "drv-0", "drv-1", "drv-2"; 3654 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3655 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3656 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3657 qcom,tcs-offset = <0xd00>; 3658 qcom,drv-id = <2>; 3659 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3660 <WAKE_TCS 3>, <CONTROL_TCS 1>; 3661 3662 rpmhcc: clock-controller { 3663 compatible = "qcom,sm8250-rpmh-clk"; 3664 #clock-cells = <1>; 3665 clock-names = "xo"; 3666 clocks = <&xo_board>; 3667 }; 3668 3669 rpmhpd: power-controller { 3670 compatible = "qcom,sm8250-rpmhpd"; 3671 #power-domain-cells = <1>; 3672 operating-points-v2 = <&rpmhpd_opp_table>; 3673 3674 rpmhpd_opp_table: opp-table { 3675 compatible = "operating-points-v2"; 3676 3677 rpmhpd_opp_ret: opp1 { 3678 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3679 }; 3680 3681 rpmhpd_opp_min_svs: opp2 { 3682 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3683 }; 3684 3685 rpmhpd_opp_low_svs: opp3 { 3686 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3687 }; 3688 3689 rpmhpd_opp_svs: opp4 { 3690 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3691 }; 3692 3693 rpmhpd_opp_svs_l1: opp5 { 3694 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3695 }; 3696 3697 rpmhpd_opp_nom: opp6 { 3698 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3699 }; 3700 3701 rpmhpd_opp_nom_l1: opp7 { 3702 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3703 }; 3704 3705 rpmhpd_opp_nom_l2: opp8 { 3706 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3707 }; 3708 3709 rpmhpd_opp_turbo: opp9 { 3710 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3711 }; 3712 3713 rpmhpd_opp_turbo_l1: opp10 { 3714 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3715 }; 3716 }; 3717 }; 3718 3719 apps_bcm_voter: bcm_voter { 3720 compatible = "qcom,bcm-voter"; 3721 }; 3722 }; 3723 3724 epss_l3: interconnect@18591000 { 3725 compatible = "qcom,sm8250-epss-l3"; 3726 reg = <0 0x18590000 0 0x1000>; 3727 3728 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3729 clock-names = "xo", "alternate"; 3730 3731 #interconnect-cells = <1>; 3732 }; 3733 3734 cpufreq_hw: cpufreq@18591000 { 3735 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 3736 reg = <0 0x18591000 0 0x1000>, 3737 <0 0x18592000 0 0x1000>, 3738 <0 0x18593000 0 0x1000>; 3739 reg-names = "freq-domain0", "freq-domain1", 3740 "freq-domain2"; 3741 3742 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3743 clock-names = "xo", "alternate"; 3744 3745 #freq-domain-cells = <1>; 3746 }; 3747 }; 3748 3749 timer { 3750 compatible = "arm,armv8-timer"; 3751 interrupts = <GIC_PPI 13 3752 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3753 <GIC_PPI 14 3754 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3755 <GIC_PPI 11 3756 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3757 <GIC_PPI 12 3758 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 3759 }; 3760 3761 thermal-zones { 3762 cpu0-thermal { 3763 polling-delay-passive = <250>; 3764 polling-delay = <1000>; 3765 3766 thermal-sensors = <&tsens0 1>; 3767 3768 trips { 3769 cpu0_alert0: trip-point0 { 3770 temperature = <90000>; 3771 hysteresis = <2000>; 3772 type = "passive"; 3773 }; 3774 3775 cpu0_alert1: trip-point1 { 3776 temperature = <95000>; 3777 hysteresis = <2000>; 3778 type = "passive"; 3779 }; 3780 3781 cpu0_crit: cpu_crit { 3782 temperature = <110000>; 3783 hysteresis = <1000>; 3784 type = "critical"; 3785 }; 3786 }; 3787 3788 cooling-maps { 3789 map0 { 3790 trip = <&cpu0_alert0>; 3791 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3792 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3793 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3794 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3795 }; 3796 map1 { 3797 trip = <&cpu0_alert1>; 3798 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3799 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3800 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3801 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3802 }; 3803 }; 3804 }; 3805 3806 cpu1-thermal { 3807 polling-delay-passive = <250>; 3808 polling-delay = <1000>; 3809 3810 thermal-sensors = <&tsens0 2>; 3811 3812 trips { 3813 cpu1_alert0: trip-point0 { 3814 temperature = <90000>; 3815 hysteresis = <2000>; 3816 type = "passive"; 3817 }; 3818 3819 cpu1_alert1: trip-point1 { 3820 temperature = <95000>; 3821 hysteresis = <2000>; 3822 type = "passive"; 3823 }; 3824 3825 cpu1_crit: cpu_crit { 3826 temperature = <110000>; 3827 hysteresis = <1000>; 3828 type = "critical"; 3829 }; 3830 }; 3831 3832 cooling-maps { 3833 map0 { 3834 trip = <&cpu1_alert0>; 3835 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3836 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3837 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3838 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3839 }; 3840 map1 { 3841 trip = <&cpu1_alert1>; 3842 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3843 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3844 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3845 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3846 }; 3847 }; 3848 }; 3849 3850 cpu2-thermal { 3851 polling-delay-passive = <250>; 3852 polling-delay = <1000>; 3853 3854 thermal-sensors = <&tsens0 3>; 3855 3856 trips { 3857 cpu2_alert0: trip-point0 { 3858 temperature = <90000>; 3859 hysteresis = <2000>; 3860 type = "passive"; 3861 }; 3862 3863 cpu2_alert1: trip-point1 { 3864 temperature = <95000>; 3865 hysteresis = <2000>; 3866 type = "passive"; 3867 }; 3868 3869 cpu2_crit: cpu_crit { 3870 temperature = <110000>; 3871 hysteresis = <1000>; 3872 type = "critical"; 3873 }; 3874 }; 3875 3876 cooling-maps { 3877 map0 { 3878 trip = <&cpu2_alert0>; 3879 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3880 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3881 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3882 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3883 }; 3884 map1 { 3885 trip = <&cpu2_alert1>; 3886 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3887 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3888 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3889 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3890 }; 3891 }; 3892 }; 3893 3894 cpu3-thermal { 3895 polling-delay-passive = <250>; 3896 polling-delay = <1000>; 3897 3898 thermal-sensors = <&tsens0 4>; 3899 3900 trips { 3901 cpu3_alert0: trip-point0 { 3902 temperature = <90000>; 3903 hysteresis = <2000>; 3904 type = "passive"; 3905 }; 3906 3907 cpu3_alert1: trip-point1 { 3908 temperature = <95000>; 3909 hysteresis = <2000>; 3910 type = "passive"; 3911 }; 3912 3913 cpu3_crit: cpu_crit { 3914 temperature = <110000>; 3915 hysteresis = <1000>; 3916 type = "critical"; 3917 }; 3918 }; 3919 3920 cooling-maps { 3921 map0 { 3922 trip = <&cpu3_alert0>; 3923 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3924 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3925 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3926 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3927 }; 3928 map1 { 3929 trip = <&cpu3_alert1>; 3930 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3931 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3932 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3933 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3934 }; 3935 }; 3936 }; 3937 3938 cpu4-top-thermal { 3939 polling-delay-passive = <250>; 3940 polling-delay = <1000>; 3941 3942 thermal-sensors = <&tsens0 7>; 3943 3944 trips { 3945 cpu4_top_alert0: trip-point0 { 3946 temperature = <90000>; 3947 hysteresis = <2000>; 3948 type = "passive"; 3949 }; 3950 3951 cpu4_top_alert1: trip-point1 { 3952 temperature = <95000>; 3953 hysteresis = <2000>; 3954 type = "passive"; 3955 }; 3956 3957 cpu4_top_crit: cpu_crit { 3958 temperature = <110000>; 3959 hysteresis = <1000>; 3960 type = "critical"; 3961 }; 3962 }; 3963 3964 cooling-maps { 3965 map0 { 3966 trip = <&cpu4_top_alert0>; 3967 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3968 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3969 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3970 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3971 }; 3972 map1 { 3973 trip = <&cpu4_top_alert1>; 3974 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3975 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3976 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3977 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3978 }; 3979 }; 3980 }; 3981 3982 cpu5-top-thermal { 3983 polling-delay-passive = <250>; 3984 polling-delay = <1000>; 3985 3986 thermal-sensors = <&tsens0 8>; 3987 3988 trips { 3989 cpu5_top_alert0: trip-point0 { 3990 temperature = <90000>; 3991 hysteresis = <2000>; 3992 type = "passive"; 3993 }; 3994 3995 cpu5_top_alert1: trip-point1 { 3996 temperature = <95000>; 3997 hysteresis = <2000>; 3998 type = "passive"; 3999 }; 4000 4001 cpu5_top_crit: cpu_crit { 4002 temperature = <110000>; 4003 hysteresis = <1000>; 4004 type = "critical"; 4005 }; 4006 }; 4007 4008 cooling-maps { 4009 map0 { 4010 trip = <&cpu5_top_alert0>; 4011 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4012 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4013 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4014 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4015 }; 4016 map1 { 4017 trip = <&cpu5_top_alert1>; 4018 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4019 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4020 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4021 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4022 }; 4023 }; 4024 }; 4025 4026 cpu6-top-thermal { 4027 polling-delay-passive = <250>; 4028 polling-delay = <1000>; 4029 4030 thermal-sensors = <&tsens0 9>; 4031 4032 trips { 4033 cpu6_top_alert0: trip-point0 { 4034 temperature = <90000>; 4035 hysteresis = <2000>; 4036 type = "passive"; 4037 }; 4038 4039 cpu6_top_alert1: trip-point1 { 4040 temperature = <95000>; 4041 hysteresis = <2000>; 4042 type = "passive"; 4043 }; 4044 4045 cpu6_top_crit: cpu_crit { 4046 temperature = <110000>; 4047 hysteresis = <1000>; 4048 type = "critical"; 4049 }; 4050 }; 4051 4052 cooling-maps { 4053 map0 { 4054 trip = <&cpu6_top_alert0>; 4055 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4056 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4057 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4058 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4059 }; 4060 map1 { 4061 trip = <&cpu6_top_alert1>; 4062 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4063 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4064 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4065 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4066 }; 4067 }; 4068 }; 4069 4070 cpu7-top-thermal { 4071 polling-delay-passive = <250>; 4072 polling-delay = <1000>; 4073 4074 thermal-sensors = <&tsens0 10>; 4075 4076 trips { 4077 cpu7_top_alert0: trip-point0 { 4078 temperature = <90000>; 4079 hysteresis = <2000>; 4080 type = "passive"; 4081 }; 4082 4083 cpu7_top_alert1: trip-point1 { 4084 temperature = <95000>; 4085 hysteresis = <2000>; 4086 type = "passive"; 4087 }; 4088 4089 cpu7_top_crit: cpu_crit { 4090 temperature = <110000>; 4091 hysteresis = <1000>; 4092 type = "critical"; 4093 }; 4094 }; 4095 4096 cooling-maps { 4097 map0 { 4098 trip = <&cpu7_top_alert0>; 4099 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4100 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4101 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4102 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4103 }; 4104 map1 { 4105 trip = <&cpu7_top_alert1>; 4106 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4107 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4108 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4109 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4110 }; 4111 }; 4112 }; 4113 4114 cpu4-bottom-thermal { 4115 polling-delay-passive = <250>; 4116 polling-delay = <1000>; 4117 4118 thermal-sensors = <&tsens0 11>; 4119 4120 trips { 4121 cpu4_bottom_alert0: trip-point0 { 4122 temperature = <90000>; 4123 hysteresis = <2000>; 4124 type = "passive"; 4125 }; 4126 4127 cpu4_bottom_alert1: trip-point1 { 4128 temperature = <95000>; 4129 hysteresis = <2000>; 4130 type = "passive"; 4131 }; 4132 4133 cpu4_bottom_crit: cpu_crit { 4134 temperature = <110000>; 4135 hysteresis = <1000>; 4136 type = "critical"; 4137 }; 4138 }; 4139 4140 cooling-maps { 4141 map0 { 4142 trip = <&cpu4_bottom_alert0>; 4143 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4144 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4145 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4146 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4147 }; 4148 map1 { 4149 trip = <&cpu4_bottom_alert1>; 4150 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4151 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4152 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4153 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4154 }; 4155 }; 4156 }; 4157 4158 cpu5-bottom-thermal { 4159 polling-delay-passive = <250>; 4160 polling-delay = <1000>; 4161 4162 thermal-sensors = <&tsens0 12>; 4163 4164 trips { 4165 cpu5_bottom_alert0: trip-point0 { 4166 temperature = <90000>; 4167 hysteresis = <2000>; 4168 type = "passive"; 4169 }; 4170 4171 cpu5_bottom_alert1: trip-point1 { 4172 temperature = <95000>; 4173 hysteresis = <2000>; 4174 type = "passive"; 4175 }; 4176 4177 cpu5_bottom_crit: cpu_crit { 4178 temperature = <110000>; 4179 hysteresis = <1000>; 4180 type = "critical"; 4181 }; 4182 }; 4183 4184 cooling-maps { 4185 map0 { 4186 trip = <&cpu5_bottom_alert0>; 4187 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4188 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4189 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4190 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4191 }; 4192 map1 { 4193 trip = <&cpu5_bottom_alert1>; 4194 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4195 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4196 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4197 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4198 }; 4199 }; 4200 }; 4201 4202 cpu6-bottom-thermal { 4203 polling-delay-passive = <250>; 4204 polling-delay = <1000>; 4205 4206 thermal-sensors = <&tsens0 13>; 4207 4208 trips { 4209 cpu6_bottom_alert0: trip-point0 { 4210 temperature = <90000>; 4211 hysteresis = <2000>; 4212 type = "passive"; 4213 }; 4214 4215 cpu6_bottom_alert1: trip-point1 { 4216 temperature = <95000>; 4217 hysteresis = <2000>; 4218 type = "passive"; 4219 }; 4220 4221 cpu6_bottom_crit: cpu_crit { 4222 temperature = <110000>; 4223 hysteresis = <1000>; 4224 type = "critical"; 4225 }; 4226 }; 4227 4228 cooling-maps { 4229 map0 { 4230 trip = <&cpu6_bottom_alert0>; 4231 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4232 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4233 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4234 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4235 }; 4236 map1 { 4237 trip = <&cpu6_bottom_alert1>; 4238 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4239 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4240 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4241 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4242 }; 4243 }; 4244 }; 4245 4246 cpu7-bottom-thermal { 4247 polling-delay-passive = <250>; 4248 polling-delay = <1000>; 4249 4250 thermal-sensors = <&tsens0 14>; 4251 4252 trips { 4253 cpu7_bottom_alert0: trip-point0 { 4254 temperature = <90000>; 4255 hysteresis = <2000>; 4256 type = "passive"; 4257 }; 4258 4259 cpu7_bottom_alert1: trip-point1 { 4260 temperature = <95000>; 4261 hysteresis = <2000>; 4262 type = "passive"; 4263 }; 4264 4265 cpu7_bottom_crit: cpu_crit { 4266 temperature = <110000>; 4267 hysteresis = <1000>; 4268 type = "critical"; 4269 }; 4270 }; 4271 4272 cooling-maps { 4273 map0 { 4274 trip = <&cpu7_bottom_alert0>; 4275 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4276 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4277 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4278 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4279 }; 4280 map1 { 4281 trip = <&cpu7_bottom_alert1>; 4282 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4283 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4284 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4285 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4286 }; 4287 }; 4288 }; 4289 4290 aoss0-thermal { 4291 polling-delay-passive = <250>; 4292 polling-delay = <1000>; 4293 4294 thermal-sensors = <&tsens0 0>; 4295 4296 trips { 4297 aoss0_alert0: trip-point0 { 4298 temperature = <90000>; 4299 hysteresis = <2000>; 4300 type = "hot"; 4301 }; 4302 }; 4303 }; 4304 4305 cluster0-thermal { 4306 polling-delay-passive = <250>; 4307 polling-delay = <1000>; 4308 4309 thermal-sensors = <&tsens0 5>; 4310 4311 trips { 4312 cluster0_alert0: trip-point0 { 4313 temperature = <90000>; 4314 hysteresis = <2000>; 4315 type = "hot"; 4316 }; 4317 cluster0_crit: cluster0_crit { 4318 temperature = <110000>; 4319 hysteresis = <2000>; 4320 type = "critical"; 4321 }; 4322 }; 4323 }; 4324 4325 cluster1-thermal { 4326 polling-delay-passive = <250>; 4327 polling-delay = <1000>; 4328 4329 thermal-sensors = <&tsens0 6>; 4330 4331 trips { 4332 cluster1_alert0: trip-point0 { 4333 temperature = <90000>; 4334 hysteresis = <2000>; 4335 type = "hot"; 4336 }; 4337 cluster1_crit: cluster1_crit { 4338 temperature = <110000>; 4339 hysteresis = <2000>; 4340 type = "critical"; 4341 }; 4342 }; 4343 }; 4344 4345 gpu-thermal-top { 4346 polling-delay-passive = <250>; 4347 polling-delay = <1000>; 4348 4349 thermal-sensors = <&tsens0 15>; 4350 4351 trips { 4352 gpu1_alert0: trip-point0 { 4353 temperature = <90000>; 4354 hysteresis = <2000>; 4355 type = "hot"; 4356 }; 4357 }; 4358 }; 4359 4360 aoss1-thermal { 4361 polling-delay-passive = <250>; 4362 polling-delay = <1000>; 4363 4364 thermal-sensors = <&tsens1 0>; 4365 4366 trips { 4367 aoss1_alert0: trip-point0 { 4368 temperature = <90000>; 4369 hysteresis = <2000>; 4370 type = "hot"; 4371 }; 4372 }; 4373 }; 4374 4375 wlan-thermal { 4376 polling-delay-passive = <250>; 4377 polling-delay = <1000>; 4378 4379 thermal-sensors = <&tsens1 1>; 4380 4381 trips { 4382 wlan_alert0: trip-point0 { 4383 temperature = <90000>; 4384 hysteresis = <2000>; 4385 type = "hot"; 4386 }; 4387 }; 4388 }; 4389 4390 video-thermal { 4391 polling-delay-passive = <250>; 4392 polling-delay = <1000>; 4393 4394 thermal-sensors = <&tsens1 2>; 4395 4396 trips { 4397 video_alert0: trip-point0 { 4398 temperature = <90000>; 4399 hysteresis = <2000>; 4400 type = "hot"; 4401 }; 4402 }; 4403 }; 4404 4405 mem-thermal { 4406 polling-delay-passive = <250>; 4407 polling-delay = <1000>; 4408 4409 thermal-sensors = <&tsens1 3>; 4410 4411 trips { 4412 mem_alert0: trip-point0 { 4413 temperature = <90000>; 4414 hysteresis = <2000>; 4415 type = "hot"; 4416 }; 4417 }; 4418 }; 4419 4420 q6-hvx-thermal { 4421 polling-delay-passive = <250>; 4422 polling-delay = <1000>; 4423 4424 thermal-sensors = <&tsens1 4>; 4425 4426 trips { 4427 q6_hvx_alert0: trip-point0 { 4428 temperature = <90000>; 4429 hysteresis = <2000>; 4430 type = "hot"; 4431 }; 4432 }; 4433 }; 4434 4435 camera-thermal { 4436 polling-delay-passive = <250>; 4437 polling-delay = <1000>; 4438 4439 thermal-sensors = <&tsens1 5>; 4440 4441 trips { 4442 camera_alert0: trip-point0 { 4443 temperature = <90000>; 4444 hysteresis = <2000>; 4445 type = "hot"; 4446 }; 4447 }; 4448 }; 4449 4450 compute-thermal { 4451 polling-delay-passive = <250>; 4452 polling-delay = <1000>; 4453 4454 thermal-sensors = <&tsens1 6>; 4455 4456 trips { 4457 compute_alert0: trip-point0 { 4458 temperature = <90000>; 4459 hysteresis = <2000>; 4460 type = "hot"; 4461 }; 4462 }; 4463 }; 4464 4465 npu-thermal { 4466 polling-delay-passive = <250>; 4467 polling-delay = <1000>; 4468 4469 thermal-sensors = <&tsens1 7>; 4470 4471 trips { 4472 npu_alert0: trip-point0 { 4473 temperature = <90000>; 4474 hysteresis = <2000>; 4475 type = "hot"; 4476 }; 4477 }; 4478 }; 4479 4480 gpu-thermal-bottom { 4481 polling-delay-passive = <250>; 4482 polling-delay = <1000>; 4483 4484 thermal-sensors = <&tsens1 8>; 4485 4486 trips { 4487 gpu2_alert0: trip-point0 { 4488 temperature = <90000>; 4489 hysteresis = <2000>; 4490 type = "hot"; 4491 }; 4492 }; 4493 }; 4494 }; 4495}; 4496