1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h> 12#include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sm8250.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,apr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/sound/qcom,q6afe.h> 22#include <dt-bindings/thermal/thermal.h> 23#include <dt-bindings/clock/qcom,camcc-sm8250.h> 24#include <dt-bindings/clock/qcom,videocc-sm8250.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 aliases { 33 i2c0 = &i2c0; 34 i2c1 = &i2c1; 35 i2c2 = &i2c2; 36 i2c3 = &i2c3; 37 i2c4 = &i2c4; 38 i2c5 = &i2c5; 39 i2c6 = &i2c6; 40 i2c7 = &i2c7; 41 i2c8 = &i2c8; 42 i2c9 = &i2c9; 43 i2c10 = &i2c10; 44 i2c11 = &i2c11; 45 i2c12 = &i2c12; 46 i2c13 = &i2c13; 47 i2c14 = &i2c14; 48 i2c15 = &i2c15; 49 i2c16 = &i2c16; 50 i2c17 = &i2c17; 51 i2c18 = &i2c18; 52 i2c19 = &i2c19; 53 spi0 = &spi0; 54 spi1 = &spi1; 55 spi2 = &spi2; 56 spi3 = &spi3; 57 spi4 = &spi4; 58 spi5 = &spi5; 59 spi6 = &spi6; 60 spi7 = &spi7; 61 spi8 = &spi8; 62 spi9 = &spi9; 63 spi10 = &spi10; 64 spi11 = &spi11; 65 spi12 = &spi12; 66 spi13 = &spi13; 67 spi14 = &spi14; 68 spi15 = &spi15; 69 spi16 = &spi16; 70 spi17 = &spi17; 71 spi18 = &spi18; 72 spi19 = &spi19; 73 }; 74 75 chosen { }; 76 77 clocks { 78 xo_board: xo-board { 79 compatible = "fixed-clock"; 80 #clock-cells = <0>; 81 clock-frequency = <38400000>; 82 clock-output-names = "xo_board"; 83 }; 84 85 sleep_clk: sleep-clk { 86 compatible = "fixed-clock"; 87 clock-frequency = <32768>; 88 #clock-cells = <0>; 89 }; 90 }; 91 92 cpus { 93 #address-cells = <2>; 94 #size-cells = <0>; 95 96 CPU0: cpu@0 { 97 device_type = "cpu"; 98 compatible = "qcom,kryo485"; 99 reg = <0x0 0x0>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <448>; 102 dynamic-power-coefficient = <205>; 103 next-level-cache = <&L2_0>; 104 power-domains = <&CPU_PD0>; 105 power-domain-names = "psci"; 106 qcom,freq-domain = <&cpufreq_hw 0>; 107 operating-points-v2 = <&cpu0_opp_table>; 108 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 109 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 110 #cooling-cells = <2>; 111 L2_0: l2-cache { 112 compatible = "cache"; 113 cache-level = <2>; 114 cache-size = <0x20000>; 115 cache-unified; 116 next-level-cache = <&L3_0>; 117 L3_0: l3-cache { 118 compatible = "cache"; 119 cache-level = <3>; 120 cache-size = <0x400000>; 121 cache-unified; 122 }; 123 }; 124 }; 125 126 CPU1: cpu@100 { 127 device_type = "cpu"; 128 compatible = "qcom,kryo485"; 129 reg = <0x0 0x100>; 130 enable-method = "psci"; 131 capacity-dmips-mhz = <448>; 132 dynamic-power-coefficient = <205>; 133 next-level-cache = <&L2_100>; 134 power-domains = <&CPU_PD1>; 135 power-domain-names = "psci"; 136 qcom,freq-domain = <&cpufreq_hw 0>; 137 operating-points-v2 = <&cpu0_opp_table>; 138 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 139 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 140 #cooling-cells = <2>; 141 L2_100: l2-cache { 142 compatible = "cache"; 143 cache-level = <2>; 144 cache-size = <0x20000>; 145 cache-unified; 146 next-level-cache = <&L3_0>; 147 }; 148 }; 149 150 CPU2: cpu@200 { 151 device_type = "cpu"; 152 compatible = "qcom,kryo485"; 153 reg = <0x0 0x200>; 154 enable-method = "psci"; 155 capacity-dmips-mhz = <448>; 156 dynamic-power-coefficient = <205>; 157 next-level-cache = <&L2_200>; 158 power-domains = <&CPU_PD2>; 159 power-domain-names = "psci"; 160 qcom,freq-domain = <&cpufreq_hw 0>; 161 operating-points-v2 = <&cpu0_opp_table>; 162 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 163 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 164 #cooling-cells = <2>; 165 L2_200: l2-cache { 166 compatible = "cache"; 167 cache-level = <2>; 168 cache-size = <0x20000>; 169 cache-unified; 170 next-level-cache = <&L3_0>; 171 }; 172 }; 173 174 CPU3: cpu@300 { 175 device_type = "cpu"; 176 compatible = "qcom,kryo485"; 177 reg = <0x0 0x300>; 178 enable-method = "psci"; 179 capacity-dmips-mhz = <448>; 180 dynamic-power-coefficient = <205>; 181 next-level-cache = <&L2_300>; 182 power-domains = <&CPU_PD3>; 183 power-domain-names = "psci"; 184 qcom,freq-domain = <&cpufreq_hw 0>; 185 operating-points-v2 = <&cpu0_opp_table>; 186 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 187 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 188 #cooling-cells = <2>; 189 L2_300: l2-cache { 190 compatible = "cache"; 191 cache-level = <2>; 192 cache-size = <0x20000>; 193 cache-unified; 194 next-level-cache = <&L3_0>; 195 }; 196 }; 197 198 CPU4: cpu@400 { 199 device_type = "cpu"; 200 compatible = "qcom,kryo485"; 201 reg = <0x0 0x400>; 202 enable-method = "psci"; 203 capacity-dmips-mhz = <1024>; 204 dynamic-power-coefficient = <379>; 205 next-level-cache = <&L2_400>; 206 power-domains = <&CPU_PD4>; 207 power-domain-names = "psci"; 208 qcom,freq-domain = <&cpufreq_hw 1>; 209 operating-points-v2 = <&cpu4_opp_table>; 210 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 211 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 212 #cooling-cells = <2>; 213 L2_400: l2-cache { 214 compatible = "cache"; 215 cache-level = <2>; 216 cache-size = <0x40000>; 217 cache-unified; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 CPU5: cpu@500 { 223 device_type = "cpu"; 224 compatible = "qcom,kryo485"; 225 reg = <0x0 0x500>; 226 enable-method = "psci"; 227 capacity-dmips-mhz = <1024>; 228 dynamic-power-coefficient = <379>; 229 next-level-cache = <&L2_500>; 230 power-domains = <&CPU_PD5>; 231 power-domain-names = "psci"; 232 qcom,freq-domain = <&cpufreq_hw 1>; 233 operating-points-v2 = <&cpu4_opp_table>; 234 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 235 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 236 #cooling-cells = <2>; 237 L2_500: l2-cache { 238 compatible = "cache"; 239 cache-level = <2>; 240 cache-size = <0x40000>; 241 cache-unified; 242 next-level-cache = <&L3_0>; 243 }; 244 245 }; 246 247 CPU6: cpu@600 { 248 device_type = "cpu"; 249 compatible = "qcom,kryo485"; 250 reg = <0x0 0x600>; 251 enable-method = "psci"; 252 capacity-dmips-mhz = <1024>; 253 dynamic-power-coefficient = <379>; 254 next-level-cache = <&L2_600>; 255 power-domains = <&CPU_PD6>; 256 power-domain-names = "psci"; 257 qcom,freq-domain = <&cpufreq_hw 1>; 258 operating-points-v2 = <&cpu4_opp_table>; 259 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 260 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 261 #cooling-cells = <2>; 262 L2_600: l2-cache { 263 compatible = "cache"; 264 cache-level = <2>; 265 cache-size = <0x40000>; 266 cache-unified; 267 next-level-cache = <&L3_0>; 268 }; 269 }; 270 271 CPU7: cpu@700 { 272 device_type = "cpu"; 273 compatible = "qcom,kryo485"; 274 reg = <0x0 0x700>; 275 enable-method = "psci"; 276 capacity-dmips-mhz = <1024>; 277 dynamic-power-coefficient = <444>; 278 next-level-cache = <&L2_700>; 279 power-domains = <&CPU_PD7>; 280 power-domain-names = "psci"; 281 qcom,freq-domain = <&cpufreq_hw 2>; 282 operating-points-v2 = <&cpu7_opp_table>; 283 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 284 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 285 #cooling-cells = <2>; 286 L2_700: l2-cache { 287 compatible = "cache"; 288 cache-level = <2>; 289 cache-size = <0x80000>; 290 cache-unified; 291 next-level-cache = <&L3_0>; 292 }; 293 }; 294 295 cpu-map { 296 cluster0 { 297 core0 { 298 cpu = <&CPU0>; 299 }; 300 301 core1 { 302 cpu = <&CPU1>; 303 }; 304 305 core2 { 306 cpu = <&CPU2>; 307 }; 308 309 core3 { 310 cpu = <&CPU3>; 311 }; 312 313 core4 { 314 cpu = <&CPU4>; 315 }; 316 317 core5 { 318 cpu = <&CPU5>; 319 }; 320 321 core6 { 322 cpu = <&CPU6>; 323 }; 324 325 core7 { 326 cpu = <&CPU7>; 327 }; 328 }; 329 }; 330 331 idle-states { 332 entry-method = "psci"; 333 334 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 335 compatible = "arm,idle-state"; 336 idle-state-name = "silver-rail-power-collapse"; 337 arm,psci-suspend-param = <0x40000004>; 338 entry-latency-us = <360>; 339 exit-latency-us = <531>; 340 min-residency-us = <3934>; 341 local-timer-stop; 342 }; 343 344 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 345 compatible = "arm,idle-state"; 346 idle-state-name = "gold-rail-power-collapse"; 347 arm,psci-suspend-param = <0x40000004>; 348 entry-latency-us = <702>; 349 exit-latency-us = <1061>; 350 min-residency-us = <4488>; 351 local-timer-stop; 352 }; 353 }; 354 355 domain-idle-states { 356 CLUSTER_SLEEP_0: cluster-sleep-0 { 357 compatible = "domain-idle-state"; 358 idle-state-name = "cluster-llcc-off"; 359 arm,psci-suspend-param = <0x4100c244>; 360 entry-latency-us = <3264>; 361 exit-latency-us = <6562>; 362 min-residency-us = <9987>; 363 local-timer-stop; 364 }; 365 }; 366 }; 367 368 cpu0_opp_table: opp-table-cpu0 { 369 compatible = "operating-points-v2"; 370 opp-shared; 371 372 cpu0_opp1: opp-300000000 { 373 opp-hz = /bits/ 64 <300000000>; 374 opp-peak-kBps = <800000 9600000>; 375 }; 376 377 cpu0_opp2: opp-403200000 { 378 opp-hz = /bits/ 64 <403200000>; 379 opp-peak-kBps = <800000 9600000>; 380 }; 381 382 cpu0_opp3: opp-518400000 { 383 opp-hz = /bits/ 64 <518400000>; 384 opp-peak-kBps = <800000 16588800>; 385 }; 386 387 cpu0_opp4: opp-614400000 { 388 opp-hz = /bits/ 64 <614400000>; 389 opp-peak-kBps = <800000 16588800>; 390 }; 391 392 cpu0_opp5: opp-691200000 { 393 opp-hz = /bits/ 64 <691200000>; 394 opp-peak-kBps = <800000 19660800>; 395 }; 396 397 cpu0_opp6: opp-787200000 { 398 opp-hz = /bits/ 64 <787200000>; 399 opp-peak-kBps = <1804000 19660800>; 400 }; 401 402 cpu0_opp7: opp-883200000 { 403 opp-hz = /bits/ 64 <883200000>; 404 opp-peak-kBps = <1804000 23347200>; 405 }; 406 407 cpu0_opp8: opp-979200000 { 408 opp-hz = /bits/ 64 <979200000>; 409 opp-peak-kBps = <1804000 26419200>; 410 }; 411 412 cpu0_opp9: opp-1075200000 { 413 opp-hz = /bits/ 64 <1075200000>; 414 opp-peak-kBps = <1804000 29491200>; 415 }; 416 417 cpu0_opp10: opp-1171200000 { 418 opp-hz = /bits/ 64 <1171200000>; 419 opp-peak-kBps = <1804000 32563200>; 420 }; 421 422 cpu0_opp11: opp-1248000000 { 423 opp-hz = /bits/ 64 <1248000000>; 424 opp-peak-kBps = <1804000 36249600>; 425 }; 426 427 cpu0_opp12: opp-1344000000 { 428 opp-hz = /bits/ 64 <1344000000>; 429 opp-peak-kBps = <2188000 36249600>; 430 }; 431 432 cpu0_opp13: opp-1420800000 { 433 opp-hz = /bits/ 64 <1420800000>; 434 opp-peak-kBps = <2188000 39321600>; 435 }; 436 437 cpu0_opp14: opp-1516800000 { 438 opp-hz = /bits/ 64 <1516800000>; 439 opp-peak-kBps = <3072000 42393600>; 440 }; 441 442 cpu0_opp15: opp-1612800000 { 443 opp-hz = /bits/ 64 <1612800000>; 444 opp-peak-kBps = <3072000 42393600>; 445 }; 446 447 cpu0_opp16: opp-1708800000 { 448 opp-hz = /bits/ 64 <1708800000>; 449 opp-peak-kBps = <4068000 42393600>; 450 }; 451 452 cpu0_opp17: opp-1804800000 { 453 opp-hz = /bits/ 64 <1804800000>; 454 opp-peak-kBps = <4068000 42393600>; 455 }; 456 }; 457 458 cpu4_opp_table: opp-table-cpu4 { 459 compatible = "operating-points-v2"; 460 opp-shared; 461 462 cpu4_opp1: opp-710400000 { 463 opp-hz = /bits/ 64 <710400000>; 464 opp-peak-kBps = <1804000 19660800>; 465 }; 466 467 cpu4_opp2: opp-825600000 { 468 opp-hz = /bits/ 64 <825600000>; 469 opp-peak-kBps = <2188000 23347200>; 470 }; 471 472 cpu4_opp3: opp-940800000 { 473 opp-hz = /bits/ 64 <940800000>; 474 opp-peak-kBps = <2188000 26419200>; 475 }; 476 477 cpu4_opp4: opp-1056000000 { 478 opp-hz = /bits/ 64 <1056000000>; 479 opp-peak-kBps = <3072000 26419200>; 480 }; 481 482 cpu4_opp5: opp-1171200000 { 483 opp-hz = /bits/ 64 <1171200000>; 484 opp-peak-kBps = <3072000 29491200>; 485 }; 486 487 cpu4_opp6: opp-1286400000 { 488 opp-hz = /bits/ 64 <1286400000>; 489 opp-peak-kBps = <4068000 29491200>; 490 }; 491 492 cpu4_opp7: opp-1382400000 { 493 opp-hz = /bits/ 64 <1382400000>; 494 opp-peak-kBps = <4068000 32563200>; 495 }; 496 497 cpu4_opp8: opp-1478400000 { 498 opp-hz = /bits/ 64 <1478400000>; 499 opp-peak-kBps = <4068000 32563200>; 500 }; 501 502 cpu4_opp9: opp-1574400000 { 503 opp-hz = /bits/ 64 <1574400000>; 504 opp-peak-kBps = <5412000 39321600>; 505 }; 506 507 cpu4_opp10: opp-1670400000 { 508 opp-hz = /bits/ 64 <1670400000>; 509 opp-peak-kBps = <5412000 42393600>; 510 }; 511 512 cpu4_opp11: opp-1766400000 { 513 opp-hz = /bits/ 64 <1766400000>; 514 opp-peak-kBps = <5412000 45465600>; 515 }; 516 517 cpu4_opp12: opp-1862400000 { 518 opp-hz = /bits/ 64 <1862400000>; 519 opp-peak-kBps = <6220000 45465600>; 520 }; 521 522 cpu4_opp13: opp-1958400000 { 523 opp-hz = /bits/ 64 <1958400000>; 524 opp-peak-kBps = <6220000 48537600>; 525 }; 526 527 cpu4_opp14: opp-2054400000 { 528 opp-hz = /bits/ 64 <2054400000>; 529 opp-peak-kBps = <7216000 48537600>; 530 }; 531 532 cpu4_opp15: opp-2150400000 { 533 opp-hz = /bits/ 64 <2150400000>; 534 opp-peak-kBps = <7216000 51609600>; 535 }; 536 537 cpu4_opp16: opp-2246400000 { 538 opp-hz = /bits/ 64 <2246400000>; 539 opp-peak-kBps = <7216000 51609600>; 540 }; 541 542 cpu4_opp17: opp-2342400000 { 543 opp-hz = /bits/ 64 <2342400000>; 544 opp-peak-kBps = <8368000 51609600>; 545 }; 546 547 cpu4_opp18: opp-2419200000 { 548 opp-hz = /bits/ 64 <2419200000>; 549 opp-peak-kBps = <8368000 51609600>; 550 }; 551 }; 552 553 cpu7_opp_table: opp-table-cpu7 { 554 compatible = "operating-points-v2"; 555 opp-shared; 556 557 cpu7_opp1: opp-844800000 { 558 opp-hz = /bits/ 64 <844800000>; 559 opp-peak-kBps = <2188000 19660800>; 560 }; 561 562 cpu7_opp2: opp-960000000 { 563 opp-hz = /bits/ 64 <960000000>; 564 opp-peak-kBps = <2188000 26419200>; 565 }; 566 567 cpu7_opp3: opp-1075200000 { 568 opp-hz = /bits/ 64 <1075200000>; 569 opp-peak-kBps = <3072000 26419200>; 570 }; 571 572 cpu7_opp4: opp-1190400000 { 573 opp-hz = /bits/ 64 <1190400000>; 574 opp-peak-kBps = <3072000 29491200>; 575 }; 576 577 cpu7_opp5: opp-1305600000 { 578 opp-hz = /bits/ 64 <1305600000>; 579 opp-peak-kBps = <4068000 32563200>; 580 }; 581 582 cpu7_opp6: opp-1401600000 { 583 opp-hz = /bits/ 64 <1401600000>; 584 opp-peak-kBps = <4068000 32563200>; 585 }; 586 587 cpu7_opp7: opp-1516800000 { 588 opp-hz = /bits/ 64 <1516800000>; 589 opp-peak-kBps = <4068000 36249600>; 590 }; 591 592 cpu7_opp8: opp-1632000000 { 593 opp-hz = /bits/ 64 <1632000000>; 594 opp-peak-kBps = <5412000 39321600>; 595 }; 596 597 cpu7_opp9: opp-1747200000 { 598 opp-hz = /bits/ 64 <1708800000>; 599 opp-peak-kBps = <5412000 42393600>; 600 }; 601 602 cpu7_opp10: opp-1862400000 { 603 opp-hz = /bits/ 64 <1862400000>; 604 opp-peak-kBps = <6220000 45465600>; 605 }; 606 607 cpu7_opp11: opp-1977600000 { 608 opp-hz = /bits/ 64 <1977600000>; 609 opp-peak-kBps = <6220000 48537600>; 610 }; 611 612 cpu7_opp12: opp-2073600000 { 613 opp-hz = /bits/ 64 <2073600000>; 614 opp-peak-kBps = <7216000 48537600>; 615 }; 616 617 cpu7_opp13: opp-2169600000 { 618 opp-hz = /bits/ 64 <2169600000>; 619 opp-peak-kBps = <7216000 51609600>; 620 }; 621 622 cpu7_opp14: opp-2265600000 { 623 opp-hz = /bits/ 64 <2265600000>; 624 opp-peak-kBps = <7216000 51609600>; 625 }; 626 627 cpu7_opp15: opp-2361600000 { 628 opp-hz = /bits/ 64 <2361600000>; 629 opp-peak-kBps = <8368000 51609600>; 630 }; 631 632 cpu7_opp16: opp-2457600000 { 633 opp-hz = /bits/ 64 <2457600000>; 634 opp-peak-kBps = <8368000 51609600>; 635 }; 636 637 cpu7_opp17: opp-2553600000 { 638 opp-hz = /bits/ 64 <2553600000>; 639 opp-peak-kBps = <8368000 51609600>; 640 }; 641 642 cpu7_opp18: opp-2649600000 { 643 opp-hz = /bits/ 64 <2649600000>; 644 opp-peak-kBps = <8368000 51609600>; 645 }; 646 647 cpu7_opp19: opp-2745600000 { 648 opp-hz = /bits/ 64 <2745600000>; 649 opp-peak-kBps = <8368000 51609600>; 650 }; 651 652 cpu7_opp20: opp-2841600000 { 653 opp-hz = /bits/ 64 <2841600000>; 654 opp-peak-kBps = <8368000 51609600>; 655 }; 656 }; 657 658 firmware { 659 scm: scm { 660 compatible = "qcom,scm-sm8250", "qcom,scm"; 661 #reset-cells = <1>; 662 }; 663 }; 664 665 memory@80000000 { 666 device_type = "memory"; 667 /* We expect the bootloader to fill in the size */ 668 reg = <0x0 0x80000000 0x0 0x0>; 669 }; 670 671 pmu { 672 compatible = "arm,armv8-pmuv3"; 673 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 674 }; 675 676 psci { 677 compatible = "arm,psci-1.0"; 678 method = "smc"; 679 680 CPU_PD0: power-domain-cpu0 { 681 #power-domain-cells = <0>; 682 power-domains = <&CLUSTER_PD>; 683 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 684 }; 685 686 CPU_PD1: power-domain-cpu1 { 687 #power-domain-cells = <0>; 688 power-domains = <&CLUSTER_PD>; 689 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 690 }; 691 692 CPU_PD2: power-domain-cpu2 { 693 #power-domain-cells = <0>; 694 power-domains = <&CLUSTER_PD>; 695 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 696 }; 697 698 CPU_PD3: power-domain-cpu3 { 699 #power-domain-cells = <0>; 700 power-domains = <&CLUSTER_PD>; 701 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 702 }; 703 704 CPU_PD4: power-domain-cpu4 { 705 #power-domain-cells = <0>; 706 power-domains = <&CLUSTER_PD>; 707 domain-idle-states = <&BIG_CPU_SLEEP_0>; 708 }; 709 710 CPU_PD5: power-domain-cpu5 { 711 #power-domain-cells = <0>; 712 power-domains = <&CLUSTER_PD>; 713 domain-idle-states = <&BIG_CPU_SLEEP_0>; 714 }; 715 716 CPU_PD6: power-domain-cpu6 { 717 #power-domain-cells = <0>; 718 power-domains = <&CLUSTER_PD>; 719 domain-idle-states = <&BIG_CPU_SLEEP_0>; 720 }; 721 722 CPU_PD7: power-domain-cpu7 { 723 #power-domain-cells = <0>; 724 power-domains = <&CLUSTER_PD>; 725 domain-idle-states = <&BIG_CPU_SLEEP_0>; 726 }; 727 728 CLUSTER_PD: power-domain-cpu-cluster0 { 729 #power-domain-cells = <0>; 730 domain-idle-states = <&CLUSTER_SLEEP_0>; 731 }; 732 }; 733 734 qup_opp_table: opp-table-qup { 735 compatible = "operating-points-v2"; 736 737 opp-50000000 { 738 opp-hz = /bits/ 64 <50000000>; 739 required-opps = <&rpmhpd_opp_min_svs>; 740 }; 741 742 opp-75000000 { 743 opp-hz = /bits/ 64 <75000000>; 744 required-opps = <&rpmhpd_opp_low_svs>; 745 }; 746 747 opp-120000000 { 748 opp-hz = /bits/ 64 <120000000>; 749 required-opps = <&rpmhpd_opp_svs>; 750 }; 751 }; 752 753 reserved-memory { 754 #address-cells = <2>; 755 #size-cells = <2>; 756 ranges; 757 758 hyp_mem: memory@80000000 { 759 reg = <0x0 0x80000000 0x0 0x600000>; 760 no-map; 761 }; 762 763 xbl_aop_mem: memory@80700000 { 764 reg = <0x0 0x80700000 0x0 0x160000>; 765 no-map; 766 }; 767 768 cmd_db: memory@80860000 { 769 compatible = "qcom,cmd-db"; 770 reg = <0x0 0x80860000 0x0 0x20000>; 771 no-map; 772 }; 773 774 smem_mem: memory@80900000 { 775 reg = <0x0 0x80900000 0x0 0x200000>; 776 no-map; 777 }; 778 779 removed_mem: memory@80b00000 { 780 reg = <0x0 0x80b00000 0x0 0x5300000>; 781 no-map; 782 }; 783 784 camera_mem: memory@86200000 { 785 reg = <0x0 0x86200000 0x0 0x500000>; 786 no-map; 787 }; 788 789 wlan_mem: memory@86700000 { 790 reg = <0x0 0x86700000 0x0 0x100000>; 791 no-map; 792 }; 793 794 ipa_fw_mem: memory@86800000 { 795 reg = <0x0 0x86800000 0x0 0x10000>; 796 no-map; 797 }; 798 799 ipa_gsi_mem: memory@86810000 { 800 reg = <0x0 0x86810000 0x0 0xa000>; 801 no-map; 802 }; 803 804 gpu_mem: memory@8681a000 { 805 reg = <0x0 0x8681a000 0x0 0x2000>; 806 no-map; 807 }; 808 809 npu_mem: memory@86900000 { 810 reg = <0x0 0x86900000 0x0 0x500000>; 811 no-map; 812 }; 813 814 video_mem: memory@86e00000 { 815 reg = <0x0 0x86e00000 0x0 0x500000>; 816 no-map; 817 }; 818 819 cvp_mem: memory@87300000 { 820 reg = <0x0 0x87300000 0x0 0x500000>; 821 no-map; 822 }; 823 824 cdsp_mem: memory@87800000 { 825 reg = <0x0 0x87800000 0x0 0x1400000>; 826 no-map; 827 }; 828 829 slpi_mem: memory@88c00000 { 830 reg = <0x0 0x88c00000 0x0 0x1500000>; 831 no-map; 832 }; 833 834 adsp_mem: memory@8a100000 { 835 reg = <0x0 0x8a100000 0x0 0x1d00000>; 836 no-map; 837 }; 838 839 spss_mem: memory@8be00000 { 840 reg = <0x0 0x8be00000 0x0 0x100000>; 841 no-map; 842 }; 843 844 cdsp_secure_heap: memory@8bf00000 { 845 reg = <0x0 0x8bf00000 0x0 0x4600000>; 846 no-map; 847 }; 848 }; 849 850 smem { 851 compatible = "qcom,smem"; 852 memory-region = <&smem_mem>; 853 hwlocks = <&tcsr_mutex 3>; 854 }; 855 856 smp2p-adsp { 857 compatible = "qcom,smp2p"; 858 qcom,smem = <443>, <429>; 859 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 860 IPCC_MPROC_SIGNAL_SMP2P 861 IRQ_TYPE_EDGE_RISING>; 862 mboxes = <&ipcc IPCC_CLIENT_LPASS 863 IPCC_MPROC_SIGNAL_SMP2P>; 864 865 qcom,local-pid = <0>; 866 qcom,remote-pid = <2>; 867 868 smp2p_adsp_out: master-kernel { 869 qcom,entry-name = "master-kernel"; 870 #qcom,smem-state-cells = <1>; 871 }; 872 873 smp2p_adsp_in: slave-kernel { 874 qcom,entry-name = "slave-kernel"; 875 interrupt-controller; 876 #interrupt-cells = <2>; 877 }; 878 }; 879 880 smp2p-cdsp { 881 compatible = "qcom,smp2p"; 882 qcom,smem = <94>, <432>; 883 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 884 IPCC_MPROC_SIGNAL_SMP2P 885 IRQ_TYPE_EDGE_RISING>; 886 mboxes = <&ipcc IPCC_CLIENT_CDSP 887 IPCC_MPROC_SIGNAL_SMP2P>; 888 889 qcom,local-pid = <0>; 890 qcom,remote-pid = <5>; 891 892 smp2p_cdsp_out: master-kernel { 893 qcom,entry-name = "master-kernel"; 894 #qcom,smem-state-cells = <1>; 895 }; 896 897 smp2p_cdsp_in: slave-kernel { 898 qcom,entry-name = "slave-kernel"; 899 interrupt-controller; 900 #interrupt-cells = <2>; 901 }; 902 }; 903 904 smp2p-slpi { 905 compatible = "qcom,smp2p"; 906 qcom,smem = <481>, <430>; 907 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 908 IPCC_MPROC_SIGNAL_SMP2P 909 IRQ_TYPE_EDGE_RISING>; 910 mboxes = <&ipcc IPCC_CLIENT_SLPI 911 IPCC_MPROC_SIGNAL_SMP2P>; 912 913 qcom,local-pid = <0>; 914 qcom,remote-pid = <3>; 915 916 smp2p_slpi_out: master-kernel { 917 qcom,entry-name = "master-kernel"; 918 #qcom,smem-state-cells = <1>; 919 }; 920 921 smp2p_slpi_in: slave-kernel { 922 qcom,entry-name = "slave-kernel"; 923 interrupt-controller; 924 #interrupt-cells = <2>; 925 }; 926 }; 927 928 soc: soc@0 { 929 #address-cells = <2>; 930 #size-cells = <2>; 931 ranges = <0 0 0 0 0x10 0>; 932 dma-ranges = <0 0 0 0 0x10 0>; 933 compatible = "simple-bus"; 934 935 gcc: clock-controller@100000 { 936 compatible = "qcom,gcc-sm8250"; 937 reg = <0x0 0x00100000 0x0 0x1f0000>; 938 #clock-cells = <1>; 939 #reset-cells = <1>; 940 #power-domain-cells = <1>; 941 clock-names = "bi_tcxo", 942 "bi_tcxo_ao", 943 "sleep_clk"; 944 clocks = <&rpmhcc RPMH_CXO_CLK>, 945 <&rpmhcc RPMH_CXO_CLK_A>, 946 <&sleep_clk>; 947 }; 948 949 ipcc: mailbox@408000 { 950 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 951 reg = <0 0x00408000 0 0x1000>; 952 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 953 interrupt-controller; 954 #interrupt-cells = <3>; 955 #mbox-cells = <2>; 956 }; 957 958 rng: rng@793000 { 959 compatible = "qcom,prng-ee"; 960 reg = <0 0x00793000 0 0x1000>; 961 clocks = <&gcc GCC_PRNG_AHB_CLK>; 962 clock-names = "core"; 963 }; 964 965 gpi_dma2: dma-controller@800000 { 966 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 967 reg = <0 0x00800000 0 0x70000>; 968 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 978 dma-channels = <10>; 979 dma-channel-mask = <0x3f>; 980 iommus = <&apps_smmu 0x76 0x0>; 981 #dma-cells = <3>; 982 status = "disabled"; 983 }; 984 985 qupv3_id_2: geniqup@8c0000 { 986 compatible = "qcom,geni-se-qup"; 987 reg = <0x0 0x008c0000 0x0 0x6000>; 988 clock-names = "m-ahb", "s-ahb"; 989 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 990 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 991 #address-cells = <2>; 992 #size-cells = <2>; 993 iommus = <&apps_smmu 0x63 0x0>; 994 ranges; 995 status = "disabled"; 996 997 i2c14: i2c@880000 { 998 compatible = "qcom,geni-i2c"; 999 reg = <0 0x00880000 0 0x4000>; 1000 clock-names = "se"; 1001 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&qup_i2c14_default>; 1004 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1005 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1006 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1007 dma-names = "tx", "rx"; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 status = "disabled"; 1011 }; 1012 1013 spi14: spi@880000 { 1014 compatible = "qcom,geni-spi"; 1015 reg = <0 0x00880000 0 0x4000>; 1016 clock-names = "se"; 1017 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1018 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1019 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1020 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1021 dma-names = "tx", "rx"; 1022 power-domains = <&rpmhpd SM8250_CX>; 1023 operating-points-v2 = <&qup_opp_table>; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 status = "disabled"; 1027 }; 1028 1029 i2c15: i2c@884000 { 1030 compatible = "qcom,geni-i2c"; 1031 reg = <0 0x00884000 0 0x4000>; 1032 clock-names = "se"; 1033 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1034 pinctrl-names = "default"; 1035 pinctrl-0 = <&qup_i2c15_default>; 1036 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1037 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1038 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1039 dma-names = "tx", "rx"; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 status = "disabled"; 1043 }; 1044 1045 spi15: spi@884000 { 1046 compatible = "qcom,geni-spi"; 1047 reg = <0 0x00884000 0 0x4000>; 1048 clock-names = "se"; 1049 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1050 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1051 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1052 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1053 dma-names = "tx", "rx"; 1054 power-domains = <&rpmhpd SM8250_CX>; 1055 operating-points-v2 = <&qup_opp_table>; 1056 #address-cells = <1>; 1057 #size-cells = <0>; 1058 status = "disabled"; 1059 }; 1060 1061 i2c16: i2c@888000 { 1062 compatible = "qcom,geni-i2c"; 1063 reg = <0 0x00888000 0 0x4000>; 1064 clock-names = "se"; 1065 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1066 pinctrl-names = "default"; 1067 pinctrl-0 = <&qup_i2c16_default>; 1068 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1069 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1070 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1071 dma-names = "tx", "rx"; 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 status = "disabled"; 1075 }; 1076 1077 spi16: spi@888000 { 1078 compatible = "qcom,geni-spi"; 1079 reg = <0 0x00888000 0 0x4000>; 1080 clock-names = "se"; 1081 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1082 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1083 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1084 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1085 dma-names = "tx", "rx"; 1086 power-domains = <&rpmhpd SM8250_CX>; 1087 operating-points-v2 = <&qup_opp_table>; 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 status = "disabled"; 1091 }; 1092 1093 i2c17: i2c@88c000 { 1094 compatible = "qcom,geni-i2c"; 1095 reg = <0 0x0088c000 0 0x4000>; 1096 clock-names = "se"; 1097 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1098 pinctrl-names = "default"; 1099 pinctrl-0 = <&qup_i2c17_default>; 1100 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1101 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1102 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1103 dma-names = "tx", "rx"; 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 status = "disabled"; 1107 }; 1108 1109 spi17: spi@88c000 { 1110 compatible = "qcom,geni-spi"; 1111 reg = <0 0x0088c000 0 0x4000>; 1112 clock-names = "se"; 1113 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1114 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1115 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1116 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1117 dma-names = "tx", "rx"; 1118 power-domains = <&rpmhpd SM8250_CX>; 1119 operating-points-v2 = <&qup_opp_table>; 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 status = "disabled"; 1123 }; 1124 1125 uart17: serial@88c000 { 1126 compatible = "qcom,geni-uart"; 1127 reg = <0 0x0088c000 0 0x4000>; 1128 clock-names = "se"; 1129 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1130 pinctrl-names = "default"; 1131 pinctrl-0 = <&qup_uart17_default>; 1132 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1133 power-domains = <&rpmhpd SM8250_CX>; 1134 operating-points-v2 = <&qup_opp_table>; 1135 status = "disabled"; 1136 }; 1137 1138 i2c18: i2c@890000 { 1139 compatible = "qcom,geni-i2c"; 1140 reg = <0 0x00890000 0 0x4000>; 1141 clock-names = "se"; 1142 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1143 pinctrl-names = "default"; 1144 pinctrl-0 = <&qup_i2c18_default>; 1145 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1146 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1147 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1148 dma-names = "tx", "rx"; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 status = "disabled"; 1152 }; 1153 1154 spi18: spi@890000 { 1155 compatible = "qcom,geni-spi"; 1156 reg = <0 0x00890000 0 0x4000>; 1157 clock-names = "se"; 1158 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1159 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1160 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1161 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1162 dma-names = "tx", "rx"; 1163 power-domains = <&rpmhpd SM8250_CX>; 1164 operating-points-v2 = <&qup_opp_table>; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 status = "disabled"; 1168 }; 1169 1170 uart18: serial@890000 { 1171 compatible = "qcom,geni-uart"; 1172 reg = <0 0x00890000 0 0x4000>; 1173 clock-names = "se"; 1174 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1175 pinctrl-names = "default"; 1176 pinctrl-0 = <&qup_uart18_default>; 1177 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1178 power-domains = <&rpmhpd SM8250_CX>; 1179 operating-points-v2 = <&qup_opp_table>; 1180 status = "disabled"; 1181 }; 1182 1183 i2c19: i2c@894000 { 1184 compatible = "qcom,geni-i2c"; 1185 reg = <0 0x00894000 0 0x4000>; 1186 clock-names = "se"; 1187 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1188 pinctrl-names = "default"; 1189 pinctrl-0 = <&qup_i2c19_default>; 1190 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1191 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1192 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1193 dma-names = "tx", "rx"; 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 status = "disabled"; 1197 }; 1198 1199 spi19: spi@894000 { 1200 compatible = "qcom,geni-spi"; 1201 reg = <0 0x00894000 0 0x4000>; 1202 clock-names = "se"; 1203 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1204 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1205 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1206 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1207 dma-names = "tx", "rx"; 1208 power-domains = <&rpmhpd SM8250_CX>; 1209 operating-points-v2 = <&qup_opp_table>; 1210 #address-cells = <1>; 1211 #size-cells = <0>; 1212 status = "disabled"; 1213 }; 1214 }; 1215 1216 gpi_dma0: dma-controller@900000 { 1217 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1218 reg = <0 0x00900000 0 0x70000>; 1219 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1232 dma-channels = <15>; 1233 dma-channel-mask = <0x7ff>; 1234 iommus = <&apps_smmu 0x5b6 0x0>; 1235 #dma-cells = <3>; 1236 status = "disabled"; 1237 }; 1238 1239 qupv3_id_0: geniqup@9c0000 { 1240 compatible = "qcom,geni-se-qup"; 1241 reg = <0x0 0x009c0000 0x0 0x6000>; 1242 clock-names = "m-ahb", "s-ahb"; 1243 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1244 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1245 #address-cells = <2>; 1246 #size-cells = <2>; 1247 iommus = <&apps_smmu 0x5a3 0x0>; 1248 ranges; 1249 status = "disabled"; 1250 1251 i2c0: i2c@980000 { 1252 compatible = "qcom,geni-i2c"; 1253 reg = <0 0x00980000 0 0x4000>; 1254 clock-names = "se"; 1255 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1256 pinctrl-names = "default"; 1257 pinctrl-0 = <&qup_i2c0_default>; 1258 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1259 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1260 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1261 dma-names = "tx", "rx"; 1262 #address-cells = <1>; 1263 #size-cells = <0>; 1264 status = "disabled"; 1265 }; 1266 1267 spi0: spi@980000 { 1268 compatible = "qcom,geni-spi"; 1269 reg = <0 0x00980000 0 0x4000>; 1270 clock-names = "se"; 1271 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1272 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1273 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1274 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1275 dma-names = "tx", "rx"; 1276 power-domains = <&rpmhpd SM8250_CX>; 1277 operating-points-v2 = <&qup_opp_table>; 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 status = "disabled"; 1281 }; 1282 1283 i2c1: i2c@984000 { 1284 compatible = "qcom,geni-i2c"; 1285 reg = <0 0x00984000 0 0x4000>; 1286 clock-names = "se"; 1287 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1288 pinctrl-names = "default"; 1289 pinctrl-0 = <&qup_i2c1_default>; 1290 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1291 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1292 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1293 dma-names = "tx", "rx"; 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 status = "disabled"; 1297 }; 1298 1299 spi1: spi@984000 { 1300 compatible = "qcom,geni-spi"; 1301 reg = <0 0x00984000 0 0x4000>; 1302 clock-names = "se"; 1303 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1304 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1305 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1306 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1307 dma-names = "tx", "rx"; 1308 power-domains = <&rpmhpd SM8250_CX>; 1309 operating-points-v2 = <&qup_opp_table>; 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 status = "disabled"; 1313 }; 1314 1315 i2c2: i2c@988000 { 1316 compatible = "qcom,geni-i2c"; 1317 reg = <0 0x00988000 0 0x4000>; 1318 clock-names = "se"; 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1320 pinctrl-names = "default"; 1321 pinctrl-0 = <&qup_i2c2_default>; 1322 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1323 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1324 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1325 dma-names = "tx", "rx"; 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 status = "disabled"; 1329 }; 1330 1331 spi2: spi@988000 { 1332 compatible = "qcom,geni-spi"; 1333 reg = <0 0x00988000 0 0x4000>; 1334 clock-names = "se"; 1335 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1336 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1337 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1338 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1339 dma-names = "tx", "rx"; 1340 power-domains = <&rpmhpd SM8250_CX>; 1341 operating-points-v2 = <&qup_opp_table>; 1342 #address-cells = <1>; 1343 #size-cells = <0>; 1344 status = "disabled"; 1345 }; 1346 1347 uart2: serial@988000 { 1348 compatible = "qcom,geni-debug-uart"; 1349 reg = <0 0x00988000 0 0x4000>; 1350 clock-names = "se"; 1351 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1352 pinctrl-names = "default"; 1353 pinctrl-0 = <&qup_uart2_default>; 1354 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1355 power-domains = <&rpmhpd SM8250_CX>; 1356 operating-points-v2 = <&qup_opp_table>; 1357 status = "disabled"; 1358 }; 1359 1360 i2c3: i2c@98c000 { 1361 compatible = "qcom,geni-i2c"; 1362 reg = <0 0x0098c000 0 0x4000>; 1363 clock-names = "se"; 1364 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1365 pinctrl-names = "default"; 1366 pinctrl-0 = <&qup_i2c3_default>; 1367 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1368 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1369 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1370 dma-names = "tx", "rx"; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 status = "disabled"; 1374 }; 1375 1376 spi3: spi@98c000 { 1377 compatible = "qcom,geni-spi"; 1378 reg = <0 0x0098c000 0 0x4000>; 1379 clock-names = "se"; 1380 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1381 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1382 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1383 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1384 dma-names = "tx", "rx"; 1385 power-domains = <&rpmhpd SM8250_CX>; 1386 operating-points-v2 = <&qup_opp_table>; 1387 #address-cells = <1>; 1388 #size-cells = <0>; 1389 status = "disabled"; 1390 }; 1391 1392 i2c4: i2c@990000 { 1393 compatible = "qcom,geni-i2c"; 1394 reg = <0 0x00990000 0 0x4000>; 1395 clock-names = "se"; 1396 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1397 pinctrl-names = "default"; 1398 pinctrl-0 = <&qup_i2c4_default>; 1399 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1400 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1401 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1402 dma-names = "tx", "rx"; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 status = "disabled"; 1406 }; 1407 1408 spi4: spi@990000 { 1409 compatible = "qcom,geni-spi"; 1410 reg = <0 0x00990000 0 0x4000>; 1411 clock-names = "se"; 1412 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1413 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1414 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1415 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1416 dma-names = "tx", "rx"; 1417 power-domains = <&rpmhpd SM8250_CX>; 1418 operating-points-v2 = <&qup_opp_table>; 1419 #address-cells = <1>; 1420 #size-cells = <0>; 1421 status = "disabled"; 1422 }; 1423 1424 i2c5: i2c@994000 { 1425 compatible = "qcom,geni-i2c"; 1426 reg = <0 0x00994000 0 0x4000>; 1427 clock-names = "se"; 1428 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1429 pinctrl-names = "default"; 1430 pinctrl-0 = <&qup_i2c5_default>; 1431 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1432 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1433 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1434 dma-names = "tx", "rx"; 1435 #address-cells = <1>; 1436 #size-cells = <0>; 1437 status = "disabled"; 1438 }; 1439 1440 spi5: spi@994000 { 1441 compatible = "qcom,geni-spi"; 1442 reg = <0 0x00994000 0 0x4000>; 1443 clock-names = "se"; 1444 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1445 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1446 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1447 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1448 dma-names = "tx", "rx"; 1449 power-domains = <&rpmhpd SM8250_CX>; 1450 operating-points-v2 = <&qup_opp_table>; 1451 #address-cells = <1>; 1452 #size-cells = <0>; 1453 status = "disabled"; 1454 }; 1455 1456 i2c6: i2c@998000 { 1457 compatible = "qcom,geni-i2c"; 1458 reg = <0 0x00998000 0 0x4000>; 1459 clock-names = "se"; 1460 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1461 pinctrl-names = "default"; 1462 pinctrl-0 = <&qup_i2c6_default>; 1463 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1464 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1465 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1466 dma-names = "tx", "rx"; 1467 #address-cells = <1>; 1468 #size-cells = <0>; 1469 status = "disabled"; 1470 }; 1471 1472 spi6: spi@998000 { 1473 compatible = "qcom,geni-spi"; 1474 reg = <0 0x00998000 0 0x4000>; 1475 clock-names = "se"; 1476 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1477 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1478 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1479 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1480 dma-names = "tx", "rx"; 1481 power-domains = <&rpmhpd SM8250_CX>; 1482 operating-points-v2 = <&qup_opp_table>; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 status = "disabled"; 1486 }; 1487 1488 uart6: serial@998000 { 1489 compatible = "qcom,geni-uart"; 1490 reg = <0 0x00998000 0 0x4000>; 1491 clock-names = "se"; 1492 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1493 pinctrl-names = "default"; 1494 pinctrl-0 = <&qup_uart6_default>; 1495 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1496 power-domains = <&rpmhpd SM8250_CX>; 1497 operating-points-v2 = <&qup_opp_table>; 1498 status = "disabled"; 1499 }; 1500 1501 i2c7: i2c@99c000 { 1502 compatible = "qcom,geni-i2c"; 1503 reg = <0 0x0099c000 0 0x4000>; 1504 clock-names = "se"; 1505 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1506 pinctrl-names = "default"; 1507 pinctrl-0 = <&qup_i2c7_default>; 1508 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1509 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1510 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1511 dma-names = "tx", "rx"; 1512 #address-cells = <1>; 1513 #size-cells = <0>; 1514 status = "disabled"; 1515 }; 1516 1517 spi7: spi@99c000 { 1518 compatible = "qcom,geni-spi"; 1519 reg = <0 0x0099c000 0 0x4000>; 1520 clock-names = "se"; 1521 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1522 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1523 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1524 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1525 dma-names = "tx", "rx"; 1526 power-domains = <&rpmhpd SM8250_CX>; 1527 operating-points-v2 = <&qup_opp_table>; 1528 #address-cells = <1>; 1529 #size-cells = <0>; 1530 status = "disabled"; 1531 }; 1532 }; 1533 1534 gpi_dma1: dma-controller@a00000 { 1535 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1536 reg = <0 0x00a00000 0 0x70000>; 1537 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1547 dma-channels = <10>; 1548 dma-channel-mask = <0x3f>; 1549 iommus = <&apps_smmu 0x56 0x0>; 1550 #dma-cells = <3>; 1551 status = "disabled"; 1552 }; 1553 1554 qupv3_id_1: geniqup@ac0000 { 1555 compatible = "qcom,geni-se-qup"; 1556 reg = <0x0 0x00ac0000 0x0 0x6000>; 1557 clock-names = "m-ahb", "s-ahb"; 1558 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1559 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1560 #address-cells = <2>; 1561 #size-cells = <2>; 1562 iommus = <&apps_smmu 0x43 0x0>; 1563 ranges; 1564 status = "disabled"; 1565 1566 i2c8: i2c@a80000 { 1567 compatible = "qcom,geni-i2c"; 1568 reg = <0 0x00a80000 0 0x4000>; 1569 clock-names = "se"; 1570 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1571 pinctrl-names = "default"; 1572 pinctrl-0 = <&qup_i2c8_default>; 1573 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1574 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1575 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1576 dma-names = "tx", "rx"; 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 status = "disabled"; 1580 }; 1581 1582 spi8: spi@a80000 { 1583 compatible = "qcom,geni-spi"; 1584 reg = <0 0x00a80000 0 0x4000>; 1585 clock-names = "se"; 1586 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1587 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1588 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1589 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1590 dma-names = "tx", "rx"; 1591 power-domains = <&rpmhpd SM8250_CX>; 1592 operating-points-v2 = <&qup_opp_table>; 1593 #address-cells = <1>; 1594 #size-cells = <0>; 1595 status = "disabled"; 1596 }; 1597 1598 i2c9: i2c@a84000 { 1599 compatible = "qcom,geni-i2c"; 1600 reg = <0 0x00a84000 0 0x4000>; 1601 clock-names = "se"; 1602 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1603 pinctrl-names = "default"; 1604 pinctrl-0 = <&qup_i2c9_default>; 1605 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1606 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1607 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1608 dma-names = "tx", "rx"; 1609 #address-cells = <1>; 1610 #size-cells = <0>; 1611 status = "disabled"; 1612 }; 1613 1614 spi9: spi@a84000 { 1615 compatible = "qcom,geni-spi"; 1616 reg = <0 0x00a84000 0 0x4000>; 1617 clock-names = "se"; 1618 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1619 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1620 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1621 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1622 dma-names = "tx", "rx"; 1623 power-domains = <&rpmhpd SM8250_CX>; 1624 operating-points-v2 = <&qup_opp_table>; 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 status = "disabled"; 1628 }; 1629 1630 i2c10: i2c@a88000 { 1631 compatible = "qcom,geni-i2c"; 1632 reg = <0 0x00a88000 0 0x4000>; 1633 clock-names = "se"; 1634 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1635 pinctrl-names = "default"; 1636 pinctrl-0 = <&qup_i2c10_default>; 1637 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1638 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1639 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1640 dma-names = "tx", "rx"; 1641 #address-cells = <1>; 1642 #size-cells = <0>; 1643 status = "disabled"; 1644 }; 1645 1646 spi10: spi@a88000 { 1647 compatible = "qcom,geni-spi"; 1648 reg = <0 0x00a88000 0 0x4000>; 1649 clock-names = "se"; 1650 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1651 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1652 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1653 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1654 dma-names = "tx", "rx"; 1655 power-domains = <&rpmhpd SM8250_CX>; 1656 operating-points-v2 = <&qup_opp_table>; 1657 #address-cells = <1>; 1658 #size-cells = <0>; 1659 status = "disabled"; 1660 }; 1661 1662 i2c11: i2c@a8c000 { 1663 compatible = "qcom,geni-i2c"; 1664 reg = <0 0x00a8c000 0 0x4000>; 1665 clock-names = "se"; 1666 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1667 pinctrl-names = "default"; 1668 pinctrl-0 = <&qup_i2c11_default>; 1669 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1670 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1671 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1672 dma-names = "tx", "rx"; 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 status = "disabled"; 1676 }; 1677 1678 spi11: spi@a8c000 { 1679 compatible = "qcom,geni-spi"; 1680 reg = <0 0x00a8c000 0 0x4000>; 1681 clock-names = "se"; 1682 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1683 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1684 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1685 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1686 dma-names = "tx", "rx"; 1687 power-domains = <&rpmhpd SM8250_CX>; 1688 operating-points-v2 = <&qup_opp_table>; 1689 #address-cells = <1>; 1690 #size-cells = <0>; 1691 status = "disabled"; 1692 }; 1693 1694 i2c12: i2c@a90000 { 1695 compatible = "qcom,geni-i2c"; 1696 reg = <0 0x00a90000 0 0x4000>; 1697 clock-names = "se"; 1698 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1699 pinctrl-names = "default"; 1700 pinctrl-0 = <&qup_i2c12_default>; 1701 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1702 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1703 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1704 dma-names = "tx", "rx"; 1705 #address-cells = <1>; 1706 #size-cells = <0>; 1707 status = "disabled"; 1708 }; 1709 1710 spi12: spi@a90000 { 1711 compatible = "qcom,geni-spi"; 1712 reg = <0 0x00a90000 0 0x4000>; 1713 clock-names = "se"; 1714 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1715 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1716 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1717 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1718 dma-names = "tx", "rx"; 1719 power-domains = <&rpmhpd SM8250_CX>; 1720 operating-points-v2 = <&qup_opp_table>; 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 status = "disabled"; 1724 }; 1725 1726 uart12: serial@a90000 { 1727 compatible = "qcom,geni-debug-uart"; 1728 reg = <0x0 0x00a90000 0x0 0x4000>; 1729 clock-names = "se"; 1730 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1731 pinctrl-names = "default"; 1732 pinctrl-0 = <&qup_uart12_default>; 1733 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1734 power-domains = <&rpmhpd SM8250_CX>; 1735 operating-points-v2 = <&qup_opp_table>; 1736 status = "disabled"; 1737 }; 1738 1739 i2c13: i2c@a94000 { 1740 compatible = "qcom,geni-i2c"; 1741 reg = <0 0x00a94000 0 0x4000>; 1742 clock-names = "se"; 1743 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1744 pinctrl-names = "default"; 1745 pinctrl-0 = <&qup_i2c13_default>; 1746 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1747 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1748 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1749 dma-names = "tx", "rx"; 1750 #address-cells = <1>; 1751 #size-cells = <0>; 1752 status = "disabled"; 1753 }; 1754 1755 spi13: spi@a94000 { 1756 compatible = "qcom,geni-spi"; 1757 reg = <0 0x00a94000 0 0x4000>; 1758 clock-names = "se"; 1759 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1760 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1761 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1762 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1763 dma-names = "tx", "rx"; 1764 power-domains = <&rpmhpd SM8250_CX>; 1765 operating-points-v2 = <&qup_opp_table>; 1766 #address-cells = <1>; 1767 #size-cells = <0>; 1768 status = "disabled"; 1769 }; 1770 }; 1771 1772 config_noc: interconnect@1500000 { 1773 compatible = "qcom,sm8250-config-noc"; 1774 reg = <0 0x01500000 0 0xa580>; 1775 #interconnect-cells = <1>; 1776 qcom,bcm-voters = <&apps_bcm_voter>; 1777 }; 1778 1779 system_noc: interconnect@1620000 { 1780 compatible = "qcom,sm8250-system-noc"; 1781 reg = <0 0x01620000 0 0x1c200>; 1782 #interconnect-cells = <1>; 1783 qcom,bcm-voters = <&apps_bcm_voter>; 1784 }; 1785 1786 mc_virt: interconnect@163d000 { 1787 compatible = "qcom,sm8250-mc-virt"; 1788 reg = <0 0x0163d000 0 0x1000>; 1789 #interconnect-cells = <1>; 1790 qcom,bcm-voters = <&apps_bcm_voter>; 1791 }; 1792 1793 aggre1_noc: interconnect@16e0000 { 1794 compatible = "qcom,sm8250-aggre1-noc"; 1795 reg = <0 0x016e0000 0 0x1f180>; 1796 #interconnect-cells = <1>; 1797 qcom,bcm-voters = <&apps_bcm_voter>; 1798 }; 1799 1800 aggre2_noc: interconnect@1700000 { 1801 compatible = "qcom,sm8250-aggre2-noc"; 1802 reg = <0 0x01700000 0 0x33000>; 1803 #interconnect-cells = <1>; 1804 qcom,bcm-voters = <&apps_bcm_voter>; 1805 }; 1806 1807 compute_noc: interconnect@1733000 { 1808 compatible = "qcom,sm8250-compute-noc"; 1809 reg = <0 0x01733000 0 0xa180>; 1810 #interconnect-cells = <1>; 1811 qcom,bcm-voters = <&apps_bcm_voter>; 1812 }; 1813 1814 mmss_noc: interconnect@1740000 { 1815 compatible = "qcom,sm8250-mmss-noc"; 1816 reg = <0 0x01740000 0 0x1f080>; 1817 #interconnect-cells = <1>; 1818 qcom,bcm-voters = <&apps_bcm_voter>; 1819 }; 1820 1821 pcie0: pci@1c00000 { 1822 compatible = "qcom,pcie-sm8250"; 1823 reg = <0 0x01c00000 0 0x3000>, 1824 <0 0x60000000 0 0xf1d>, 1825 <0 0x60000f20 0 0xa8>, 1826 <0 0x60001000 0 0x1000>, 1827 <0 0x60100000 0 0x100000>; 1828 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1829 device_type = "pci"; 1830 linux,pci-domain = <0>; 1831 bus-range = <0x00 0xff>; 1832 num-lanes = <1>; 1833 1834 #address-cells = <3>; 1835 #size-cells = <2>; 1836 1837 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1838 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1839 1840 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1848 interrupt-names = "msi0", "msi1", "msi2", "msi3", 1849 "msi4", "msi5", "msi6", "msi7"; 1850 #interrupt-cells = <1>; 1851 interrupt-map-mask = <0 0 0 0x7>; 1852 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1853 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1854 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1855 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1856 1857 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1858 <&gcc GCC_PCIE_0_AUX_CLK>, 1859 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1860 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1861 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1862 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1863 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1864 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1865 clock-names = "pipe", 1866 "aux", 1867 "cfg", 1868 "bus_master", 1869 "bus_slave", 1870 "slave_q2a", 1871 "tbu", 1872 "ddrss_sf_tbu"; 1873 1874 iommus = <&apps_smmu 0x1c00 0x7f>; 1875 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1876 <0x100 &apps_smmu 0x1c01 0x1>; 1877 1878 resets = <&gcc GCC_PCIE_0_BCR>; 1879 reset-names = "pci"; 1880 1881 power-domains = <&gcc PCIE_0_GDSC>; 1882 1883 phys = <&pcie0_lane>; 1884 phy-names = "pciephy"; 1885 1886 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; 1887 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 1888 1889 pinctrl-names = "default"; 1890 pinctrl-0 = <&pcie0_default_state>; 1891 1892 status = "disabled"; 1893 }; 1894 1895 pcie0_phy: phy@1c06000 { 1896 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1897 reg = <0 0x01c06000 0 0x1c0>; 1898 #address-cells = <2>; 1899 #size-cells = <2>; 1900 ranges; 1901 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1902 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1903 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1904 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1905 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1906 1907 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1908 reset-names = "phy"; 1909 1910 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1911 assigned-clock-rates = <100000000>; 1912 1913 status = "disabled"; 1914 1915 pcie0_lane: phy@1c06200 { 1916 reg = <0 0x01c06200 0 0x170>, /* tx */ 1917 <0 0x01c06400 0 0x200>, /* rx */ 1918 <0 0x01c06800 0 0x1f0>, /* pcs */ 1919 <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1920 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1921 clock-names = "pipe0"; 1922 1923 #phy-cells = <0>; 1924 1925 #clock-cells = <0>; 1926 clock-output-names = "pcie_0_pipe_clk"; 1927 }; 1928 }; 1929 1930 pcie1: pci@1c08000 { 1931 compatible = "qcom,pcie-sm8250"; 1932 reg = <0 0x01c08000 0 0x3000>, 1933 <0 0x40000000 0 0xf1d>, 1934 <0 0x40000f20 0 0xa8>, 1935 <0 0x40001000 0 0x1000>, 1936 <0 0x40100000 0 0x100000>; 1937 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1938 device_type = "pci"; 1939 linux,pci-domain = <1>; 1940 bus-range = <0x00 0xff>; 1941 num-lanes = <2>; 1942 1943 #address-cells = <3>; 1944 #size-cells = <2>; 1945 1946 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1947 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1948 1949 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1950 interrupt-names = "msi"; 1951 #interrupt-cells = <1>; 1952 interrupt-map-mask = <0 0 0 0x7>; 1953 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1954 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1955 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1956 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1957 1958 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1959 <&gcc GCC_PCIE_1_AUX_CLK>, 1960 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1961 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1962 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1963 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1964 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1965 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1966 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1967 clock-names = "pipe", 1968 "aux", 1969 "cfg", 1970 "bus_master", 1971 "bus_slave", 1972 "slave_q2a", 1973 "ref", 1974 "tbu", 1975 "ddrss_sf_tbu"; 1976 1977 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1978 assigned-clock-rates = <19200000>; 1979 1980 iommus = <&apps_smmu 0x1c80 0x7f>; 1981 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1982 <0x100 &apps_smmu 0x1c81 0x1>; 1983 1984 resets = <&gcc GCC_PCIE_1_BCR>; 1985 reset-names = "pci"; 1986 1987 power-domains = <&gcc PCIE_1_GDSC>; 1988 1989 phys = <&pcie1_lane>; 1990 phy-names = "pciephy"; 1991 1992 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; 1993 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; 1994 1995 pinctrl-names = "default"; 1996 pinctrl-0 = <&pcie1_default_state>; 1997 1998 status = "disabled"; 1999 }; 2000 2001 pcie1_phy: phy@1c0e000 { 2002 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2003 reg = <0 0x01c0e000 0 0x1c0>; 2004 #address-cells = <2>; 2005 #size-cells = <2>; 2006 ranges; 2007 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2008 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2009 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 2010 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2011 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2012 2013 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2014 reset-names = "phy"; 2015 2016 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2017 assigned-clock-rates = <100000000>; 2018 2019 status = "disabled"; 2020 2021 pcie1_lane: phy@1c0e200 { 2022 reg = <0 0x01c0e200 0 0x170>, /* tx0 */ 2023 <0 0x01c0e400 0 0x200>, /* rx0 */ 2024 <0 0x01c0ea00 0 0x1f0>, /* pcs */ 2025 <0 0x01c0e600 0 0x170>, /* tx1 */ 2026 <0 0x01c0e800 0 0x200>, /* rx1 */ 2027 <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2028 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2029 clock-names = "pipe0"; 2030 2031 #phy-cells = <0>; 2032 2033 #clock-cells = <0>; 2034 clock-output-names = "pcie_1_pipe_clk"; 2035 }; 2036 }; 2037 2038 pcie2: pci@1c10000 { 2039 compatible = "qcom,pcie-sm8250"; 2040 reg = <0 0x01c10000 0 0x3000>, 2041 <0 0x64000000 0 0xf1d>, 2042 <0 0x64000f20 0 0xa8>, 2043 <0 0x64001000 0 0x1000>, 2044 <0 0x64100000 0 0x100000>; 2045 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2046 device_type = "pci"; 2047 linux,pci-domain = <2>; 2048 bus-range = <0x00 0xff>; 2049 num-lanes = <2>; 2050 2051 #address-cells = <3>; 2052 #size-cells = <2>; 2053 2054 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, 2055 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 2056 2057 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2058 interrupt-names = "msi"; 2059 #interrupt-cells = <1>; 2060 interrupt-map-mask = <0 0 0 0x7>; 2061 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2062 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2063 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2064 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2065 2066 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2067 <&gcc GCC_PCIE_2_AUX_CLK>, 2068 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2069 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2070 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2071 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2072 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2073 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2074 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2075 clock-names = "pipe", 2076 "aux", 2077 "cfg", 2078 "bus_master", 2079 "bus_slave", 2080 "slave_q2a", 2081 "ref", 2082 "tbu", 2083 "ddrss_sf_tbu"; 2084 2085 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2086 assigned-clock-rates = <19200000>; 2087 2088 iommus = <&apps_smmu 0x1d00 0x7f>; 2089 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2090 <0x100 &apps_smmu 0x1d01 0x1>; 2091 2092 resets = <&gcc GCC_PCIE_2_BCR>; 2093 reset-names = "pci"; 2094 2095 power-domains = <&gcc PCIE_2_GDSC>; 2096 2097 phys = <&pcie2_lane>; 2098 phy-names = "pciephy"; 2099 2100 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; 2101 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 2102 2103 pinctrl-names = "default"; 2104 pinctrl-0 = <&pcie2_default_state>; 2105 2106 status = "disabled"; 2107 }; 2108 2109 pcie2_phy: phy@1c16000 { 2110 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 2111 reg = <0 0x01c16000 0 0x1c0>; 2112 #address-cells = <2>; 2113 #size-cells = <2>; 2114 ranges; 2115 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2116 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2117 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2118 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2119 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2120 2121 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2122 reset-names = "phy"; 2123 2124 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2125 assigned-clock-rates = <100000000>; 2126 2127 status = "disabled"; 2128 2129 pcie2_lane: phy@1c16200 { 2130 reg = <0 0x01c16200 0 0x170>, /* tx0 */ 2131 <0 0x01c16400 0 0x200>, /* rx0 */ 2132 <0 0x01c16a00 0 0x1f0>, /* pcs */ 2133 <0 0x01c16600 0 0x170>, /* tx1 */ 2134 <0 0x01c16800 0 0x200>, /* rx1 */ 2135 <0 0x01c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2136 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 2137 clock-names = "pipe0"; 2138 2139 #phy-cells = <0>; 2140 2141 #clock-cells = <0>; 2142 clock-output-names = "pcie_2_pipe_clk"; 2143 }; 2144 }; 2145 2146 ufs_mem_hc: ufshc@1d84000 { 2147 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 2148 "jedec,ufs-2.0"; 2149 reg = <0 0x01d84000 0 0x3000>; 2150 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2151 phys = <&ufs_mem_phy_lanes>; 2152 phy-names = "ufsphy"; 2153 lanes-per-direction = <2>; 2154 #reset-cells = <1>; 2155 resets = <&gcc GCC_UFS_PHY_BCR>; 2156 reset-names = "rst"; 2157 2158 power-domains = <&gcc UFS_PHY_GDSC>; 2159 2160 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 2161 2162 clock-names = 2163 "core_clk", 2164 "bus_aggr_clk", 2165 "iface_clk", 2166 "core_clk_unipro", 2167 "ref_clk", 2168 "tx_lane0_sync_clk", 2169 "rx_lane0_sync_clk", 2170 "rx_lane1_sync_clk"; 2171 clocks = 2172 <&gcc GCC_UFS_PHY_AXI_CLK>, 2173 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2174 <&gcc GCC_UFS_PHY_AHB_CLK>, 2175 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2176 <&rpmhcc RPMH_CXO_CLK>, 2177 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2178 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2179 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2180 freq-table-hz = 2181 <37500000 300000000>, 2182 <0 0>, 2183 <0 0>, 2184 <37500000 300000000>, 2185 <0 0>, 2186 <0 0>, 2187 <0 0>, 2188 <0 0>; 2189 2190 status = "disabled"; 2191 }; 2192 2193 ufs_mem_phy: phy@1d87000 { 2194 compatible = "qcom,sm8250-qmp-ufs-phy"; 2195 reg = <0 0x01d87000 0 0x1c0>; 2196 #address-cells = <2>; 2197 #size-cells = <2>; 2198 ranges; 2199 clock-names = "ref", 2200 "ref_aux"; 2201 clocks = <&rpmhcc RPMH_CXO_CLK>, 2202 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2203 2204 resets = <&ufs_mem_hc 0>; 2205 reset-names = "ufsphy"; 2206 status = "disabled"; 2207 2208 ufs_mem_phy_lanes: phy@1d87400 { 2209 reg = <0 0x01d87400 0 0x16c>, 2210 <0 0x01d87600 0 0x200>, 2211 <0 0x01d87c00 0 0x200>, 2212 <0 0x01d87800 0 0x16c>, 2213 <0 0x01d87a00 0 0x200>; 2214 #phy-cells = <0>; 2215 }; 2216 }; 2217 2218 tcsr_mutex: hwlock@1f40000 { 2219 compatible = "qcom,tcsr-mutex"; 2220 reg = <0x0 0x01f40000 0x0 0x40000>; 2221 #hwlock-cells = <1>; 2222 }; 2223 2224 wsamacro: codec@3240000 { 2225 compatible = "qcom,sm8250-lpass-wsa-macro"; 2226 reg = <0 0x03240000 0 0x1000>; 2227 clocks = <&audiocc LPASS_CDC_WSA_MCLK>, 2228 <&audiocc LPASS_CDC_WSA_NPL>, 2229 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2230 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2231 <&aoncc LPASS_CDC_VA_MCLK>, 2232 <&vamacro>; 2233 2234 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 2235 2236 #clock-cells = <0>; 2237 clock-output-names = "mclk"; 2238 #sound-dai-cells = <1>; 2239 2240 pinctrl-names = "default"; 2241 pinctrl-0 = <&wsa_swr_active>; 2242 }; 2243 2244 swr0: soundwire-controller@3250000 { 2245 reg = <0 0x03250000 0 0x2000>; 2246 compatible = "qcom,soundwire-v1.5.1"; 2247 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 2248 clocks = <&wsamacro>; 2249 clock-names = "iface"; 2250 2251 qcom,din-ports = <2>; 2252 qcom,dout-ports = <6>; 2253 2254 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2255 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2256 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2257 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 2258 2259 #sound-dai-cells = <1>; 2260 #address-cells = <2>; 2261 #size-cells = <0>; 2262 }; 2263 2264 audiocc: clock-controller@3300000 { 2265 compatible = "qcom,sm8250-lpass-audiocc"; 2266 reg = <0 0x03300000 0 0x30000>; 2267 #clock-cells = <1>; 2268 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2269 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2270 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2271 clock-names = "core", "audio", "bus"; 2272 }; 2273 2274 vamacro: codec@3370000 { 2275 compatible = "qcom,sm8250-lpass-va-macro"; 2276 reg = <0 0x03370000 0 0x1000>; 2277 clocks = <&aoncc LPASS_CDC_VA_MCLK>, 2278 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2279 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2280 2281 clock-names = "mclk", "macro", "dcodec"; 2282 2283 #clock-cells = <0>; 2284 clock-output-names = "fsgen"; 2285 #sound-dai-cells = <1>; 2286 }; 2287 2288 rxmacro: rxmacro@3200000 { 2289 pinctrl-names = "default"; 2290 pinctrl-0 = <&rx_swr_active>; 2291 compatible = "qcom,sm8250-lpass-rx-macro"; 2292 reg = <0 0x3200000 0 0x1000>; 2293 status = "disabled"; 2294 2295 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2296 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2297 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2298 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2299 <&vamacro>; 2300 2301 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2302 2303 #clock-cells = <0>; 2304 clock-output-names = "mclk"; 2305 #sound-dai-cells = <1>; 2306 }; 2307 2308 swr1: soundwire-controller@3210000 { 2309 reg = <0 0x3210000 0 0x2000>; 2310 compatible = "qcom,soundwire-v1.5.1"; 2311 status = "disabled"; 2312 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2313 clocks = <&rxmacro>; 2314 clock-names = "iface"; 2315 label = "RX"; 2316 qcom,din-ports = <0>; 2317 qcom,dout-ports = <5>; 2318 2319 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2320 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2321 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2322 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2323 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2324 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2325 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2326 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2327 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2328 2329 #sound-dai-cells = <1>; 2330 #address-cells = <2>; 2331 #size-cells = <0>; 2332 }; 2333 2334 txmacro: txmacro@3220000 { 2335 pinctrl-names = "default"; 2336 pinctrl-0 = <&tx_swr_active>; 2337 compatible = "qcom,sm8250-lpass-tx-macro"; 2338 reg = <0 0x3220000 0 0x1000>; 2339 status = "disabled"; 2340 2341 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2342 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2343 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2344 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2345 <&vamacro>; 2346 2347 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2348 2349 #clock-cells = <0>; 2350 clock-output-names = "mclk"; 2351 #sound-dai-cells = <1>; 2352 }; 2353 2354 /* tx macro */ 2355 swr2: soundwire-controller@3230000 { 2356 reg = <0 0x3230000 0 0x2000>; 2357 compatible = "qcom,soundwire-v1.5.1"; 2358 interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 2359 interrupt-names = "core"; 2360 status = "disabled"; 2361 2362 clocks = <&txmacro>; 2363 clock-names = "iface"; 2364 label = "TX"; 2365 2366 qcom,din-ports = <5>; 2367 qcom,dout-ports = <0>; 2368 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>; 2369 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>; 2370 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>; 2371 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2372 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2373 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2374 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2375 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2376 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>; 2377 #sound-dai-cells = <1>; 2378 #address-cells = <2>; 2379 #size-cells = <0>; 2380 }; 2381 2382 aoncc: clock-controller@3380000 { 2383 compatible = "qcom,sm8250-lpass-aoncc"; 2384 reg = <0 0x03380000 0 0x40000>; 2385 #clock-cells = <1>; 2386 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2387 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2388 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2389 clock-names = "core", "audio", "bus"; 2390 }; 2391 2392 lpass_tlmm: pinctrl@33c0000 { 2393 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 2394 reg = <0 0x033c0000 0x0 0x20000>, 2395 <0 0x03550000 0x0 0x10000>; 2396 gpio-controller; 2397 #gpio-cells = <2>; 2398 gpio-ranges = <&lpass_tlmm 0 0 14>; 2399 2400 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2401 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2402 clock-names = "core", "audio"; 2403 2404 wsa_swr_active: wsa-swr-active-state { 2405 clk-pins { 2406 pins = "gpio10"; 2407 function = "wsa_swr_clk"; 2408 drive-strength = <2>; 2409 slew-rate = <1>; 2410 bias-disable; 2411 }; 2412 2413 data-pins { 2414 pins = "gpio11"; 2415 function = "wsa_swr_data"; 2416 drive-strength = <2>; 2417 slew-rate = <1>; 2418 bias-bus-hold; 2419 2420 }; 2421 }; 2422 2423 wsa_swr_sleep: wsa-swr-sleep-state { 2424 clk-pins { 2425 pins = "gpio10"; 2426 function = "wsa_swr_clk"; 2427 drive-strength = <2>; 2428 input-enable; 2429 bias-pull-down; 2430 }; 2431 2432 data-pins { 2433 pins = "gpio11"; 2434 function = "wsa_swr_data"; 2435 drive-strength = <2>; 2436 input-enable; 2437 bias-pull-down; 2438 2439 }; 2440 }; 2441 2442 dmic01_active: dmic01-active-state { 2443 clk-pins { 2444 pins = "gpio6"; 2445 function = "dmic1_clk"; 2446 drive-strength = <8>; 2447 output-high; 2448 }; 2449 data-pins { 2450 pins = "gpio7"; 2451 function = "dmic1_data"; 2452 drive-strength = <8>; 2453 input-enable; 2454 }; 2455 }; 2456 2457 dmic01_sleep: dmic01-sleep-state { 2458 clk-pins { 2459 pins = "gpio6"; 2460 function = "dmic1_clk"; 2461 drive-strength = <2>; 2462 bias-disable; 2463 output-low; 2464 }; 2465 2466 data-pins { 2467 pins = "gpio7"; 2468 function = "dmic1_data"; 2469 drive-strength = <2>; 2470 bias-pull-down; 2471 input-enable; 2472 }; 2473 }; 2474 2475 rx_swr_active: rx-swr-active-state { 2476 clk-pins { 2477 pins = "gpio3"; 2478 function = "swr_rx_clk"; 2479 drive-strength = <2>; 2480 slew-rate = <1>; 2481 bias-disable; 2482 }; 2483 2484 data-pins { 2485 pins = "gpio4", "gpio5"; 2486 function = "swr_rx_data"; 2487 drive-strength = <2>; 2488 slew-rate = <1>; 2489 bias-bus-hold; 2490 }; 2491 }; 2492 2493 tx_swr_active: tx-swr-active-state { 2494 clk-pins { 2495 pins = "gpio0"; 2496 function = "swr_tx_clk"; 2497 drive-strength = <2>; 2498 slew-rate = <1>; 2499 bias-disable; 2500 }; 2501 2502 data-pins { 2503 pins = "gpio1", "gpio2"; 2504 function = "swr_tx_data"; 2505 drive-strength = <2>; 2506 slew-rate = <1>; 2507 bias-bus-hold; 2508 }; 2509 }; 2510 2511 tx_swr_sleep: tx-swr-sleep-state { 2512 clk-pins { 2513 pins = "gpio0"; 2514 function = "swr_tx_clk"; 2515 drive-strength = <2>; 2516 input-enable; 2517 bias-pull-down; 2518 }; 2519 2520 data1-pins { 2521 pins = "gpio1"; 2522 function = "swr_tx_data"; 2523 drive-strength = <2>; 2524 input-enable; 2525 bias-bus-hold; 2526 }; 2527 2528 data2-pins { 2529 pins = "gpio2"; 2530 function = "swr_tx_data"; 2531 drive-strength = <2>; 2532 input-enable; 2533 bias-pull-down; 2534 }; 2535 }; 2536 }; 2537 2538 gpu: gpu@3d00000 { 2539 compatible = "qcom,adreno-650.2", 2540 "qcom,adreno"; 2541 2542 reg = <0 0x03d00000 0 0x40000>; 2543 reg-names = "kgsl_3d0_reg_memory"; 2544 2545 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2546 2547 iommus = <&adreno_smmu 0 0x401>; 2548 2549 operating-points-v2 = <&gpu_opp_table>; 2550 2551 qcom,gmu = <&gmu>; 2552 2553 status = "disabled"; 2554 2555 zap-shader { 2556 memory-region = <&gpu_mem>; 2557 }; 2558 2559 /* note: downstream checks gpu binning for 670 Mhz */ 2560 gpu_opp_table: opp-table { 2561 compatible = "operating-points-v2"; 2562 2563 opp-670000000 { 2564 opp-hz = /bits/ 64 <670000000>; 2565 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2566 }; 2567 2568 opp-587000000 { 2569 opp-hz = /bits/ 64 <587000000>; 2570 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2571 }; 2572 2573 opp-525000000 { 2574 opp-hz = /bits/ 64 <525000000>; 2575 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2576 }; 2577 2578 opp-490000000 { 2579 opp-hz = /bits/ 64 <490000000>; 2580 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2581 }; 2582 2583 opp-441600000 { 2584 opp-hz = /bits/ 64 <441600000>; 2585 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2586 }; 2587 2588 opp-400000000 { 2589 opp-hz = /bits/ 64 <400000000>; 2590 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2591 }; 2592 2593 opp-305000000 { 2594 opp-hz = /bits/ 64 <305000000>; 2595 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2596 }; 2597 }; 2598 }; 2599 2600 gmu: gmu@3d6a000 { 2601 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2602 2603 reg = <0 0x03d6a000 0 0x30000>, 2604 <0 0x3de0000 0 0x10000>, 2605 <0 0xb290000 0 0x10000>, 2606 <0 0xb490000 0 0x10000>; 2607 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 2608 2609 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2610 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2611 interrupt-names = "hfi", "gmu"; 2612 2613 clocks = <&gpucc GPU_CC_AHB_CLK>, 2614 <&gpucc GPU_CC_CX_GMU_CLK>, 2615 <&gpucc GPU_CC_CXO_CLK>, 2616 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2617 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2618 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2619 2620 power-domains = <&gpucc GPU_CX_GDSC>, 2621 <&gpucc GPU_GX_GDSC>; 2622 power-domain-names = "cx", "gx"; 2623 2624 iommus = <&adreno_smmu 5 0x400>; 2625 2626 operating-points-v2 = <&gmu_opp_table>; 2627 2628 status = "disabled"; 2629 2630 gmu_opp_table: opp-table { 2631 compatible = "operating-points-v2"; 2632 2633 opp-200000000 { 2634 opp-hz = /bits/ 64 <200000000>; 2635 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2636 }; 2637 }; 2638 }; 2639 2640 gpucc: clock-controller@3d90000 { 2641 compatible = "qcom,sm8250-gpucc"; 2642 reg = <0 0x03d90000 0 0x9000>; 2643 clocks = <&rpmhcc RPMH_CXO_CLK>, 2644 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2645 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2646 clock-names = "bi_tcxo", 2647 "gcc_gpu_gpll0_clk_src", 2648 "gcc_gpu_gpll0_div_clk_src"; 2649 #clock-cells = <1>; 2650 #reset-cells = <1>; 2651 #power-domain-cells = <1>; 2652 }; 2653 2654 adreno_smmu: iommu@3da0000 { 2655 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2656 reg = <0 0x03da0000 0 0x10000>; 2657 #iommu-cells = <2>; 2658 #global-interrupts = <2>; 2659 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2660 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2661 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2662 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2663 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2664 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2665 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2666 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2667 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2668 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 2669 clocks = <&gpucc GPU_CC_AHB_CLK>, 2670 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2671 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2672 clock-names = "ahb", "bus", "iface"; 2673 2674 power-domains = <&gpucc GPU_CX_GDSC>; 2675 }; 2676 2677 slpi: remoteproc@5c00000 { 2678 compatible = "qcom,sm8250-slpi-pas"; 2679 reg = <0 0x05c00000 0 0x4000>; 2680 2681 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2682 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2683 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2684 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2685 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2686 interrupt-names = "wdog", "fatal", "ready", 2687 "handover", "stop-ack"; 2688 2689 clocks = <&rpmhcc RPMH_CXO_CLK>; 2690 clock-names = "xo"; 2691 2692 power-domains = <&rpmhpd SM8250_LCX>, 2693 <&rpmhpd SM8250_LMX>; 2694 power-domain-names = "lcx", "lmx"; 2695 2696 memory-region = <&slpi_mem>; 2697 2698 qcom,qmp = <&aoss_qmp>; 2699 2700 qcom,smem-states = <&smp2p_slpi_out 0>; 2701 qcom,smem-state-names = "stop"; 2702 2703 status = "disabled"; 2704 2705 glink-edge { 2706 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2707 IPCC_MPROC_SIGNAL_GLINK_QMP 2708 IRQ_TYPE_EDGE_RISING>; 2709 mboxes = <&ipcc IPCC_CLIENT_SLPI 2710 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2711 2712 label = "slpi"; 2713 qcom,remote-pid = <3>; 2714 2715 fastrpc { 2716 compatible = "qcom,fastrpc"; 2717 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2718 label = "sdsp"; 2719 qcom,non-secure-domain; 2720 #address-cells = <1>; 2721 #size-cells = <0>; 2722 2723 compute-cb@1 { 2724 compatible = "qcom,fastrpc-compute-cb"; 2725 reg = <1>; 2726 iommus = <&apps_smmu 0x0541 0x0>; 2727 }; 2728 2729 compute-cb@2 { 2730 compatible = "qcom,fastrpc-compute-cb"; 2731 reg = <2>; 2732 iommus = <&apps_smmu 0x0542 0x0>; 2733 }; 2734 2735 compute-cb@3 { 2736 compatible = "qcom,fastrpc-compute-cb"; 2737 reg = <3>; 2738 iommus = <&apps_smmu 0x0543 0x0>; 2739 /* note: shared-cb = <4> in downstream */ 2740 }; 2741 }; 2742 }; 2743 }; 2744 2745 stm@6002000 { 2746 compatible = "arm,coresight-stm", "arm,primecell"; 2747 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>; 2748 reg-names = "stm-base", "stm-stimulus-base"; 2749 2750 clocks = <&aoss_qmp>; 2751 clock-names = "apb_pclk"; 2752 2753 out-ports { 2754 port { 2755 stm_out: endpoint { 2756 remote-endpoint = <&funnel0_in7>; 2757 }; 2758 }; 2759 }; 2760 }; 2761 2762 funnel@6041000 { 2763 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2764 reg = <0 0x06041000 0 0x1000>; 2765 2766 clocks = <&aoss_qmp>; 2767 clock-names = "apb_pclk"; 2768 2769 out-ports { 2770 port { 2771 funnel_in0_out_funnel_merg: endpoint { 2772 remote-endpoint = <&funnel_merg_in_funnel_in0>; 2773 }; 2774 }; 2775 }; 2776 2777 in-ports { 2778 #address-cells = <1>; 2779 #size-cells = <0>; 2780 2781 port@7 { 2782 reg = <7>; 2783 funnel0_in7: endpoint { 2784 remote-endpoint = <&stm_out>; 2785 }; 2786 }; 2787 }; 2788 }; 2789 2790 funnel@6042000 { 2791 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2792 reg = <0 0x06042000 0 0x1000>; 2793 2794 clocks = <&aoss_qmp>; 2795 clock-names = "apb_pclk"; 2796 2797 out-ports { 2798 #address-cells = <1>; 2799 #size-cells = <0>; 2800 2801 port@0 { 2802 reg = <0>; 2803 funnel_in1_out_funnel_merg: endpoint { 2804 remote-endpoint = <&funnel_merg_in_funnel_in1>; 2805 }; 2806 }; 2807 }; 2808 2809 in-ports { 2810 #address-cells = <1>; 2811 #size-cells = <0>; 2812 2813 port@4 { 2814 reg = <4>; 2815 funnel_in1_in_funnel_apss_merg: endpoint { 2816 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>; 2817 }; 2818 }; 2819 }; 2820 }; 2821 2822 funnel@6045000 { 2823 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2824 reg = <0 0x06045000 0 0x1000>; 2825 2826 clocks = <&aoss_qmp>; 2827 clock-names = "apb_pclk"; 2828 2829 out-ports { 2830 port { 2831 funnel_merg_out_funnel_swao: endpoint { 2832 remote-endpoint = <&funnel_swao_in_funnel_merg>; 2833 }; 2834 }; 2835 }; 2836 2837 in-ports { 2838 #address-cells = <1>; 2839 #size-cells = <0>; 2840 2841 port@0 { 2842 reg = <0>; 2843 funnel_merg_in_funnel_in0: endpoint { 2844 remote-endpoint = <&funnel_in0_out_funnel_merg>; 2845 }; 2846 }; 2847 2848 port@1 { 2849 reg = <1>; 2850 funnel_merg_in_funnel_in1: endpoint { 2851 remote-endpoint = <&funnel_in1_out_funnel_merg>; 2852 }; 2853 }; 2854 }; 2855 }; 2856 2857 replicator@6046000 { 2858 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2859 reg = <0 0x06046000 0 0x1000>; 2860 2861 clocks = <&aoss_qmp>; 2862 clock-names = "apb_pclk"; 2863 2864 out-ports { 2865 port { 2866 replicator_out: endpoint { 2867 remote-endpoint = <&etr_in>; 2868 }; 2869 }; 2870 }; 2871 2872 in-ports { 2873 port { 2874 replicator_cx_in_swao_out: endpoint { 2875 remote-endpoint = <&replicator_swao_out_cx_in>; 2876 }; 2877 }; 2878 }; 2879 }; 2880 2881 etr@6048000 { 2882 compatible = "arm,coresight-tmc", "arm,primecell"; 2883 reg = <0 0x06048000 0 0x1000>; 2884 2885 clocks = <&aoss_qmp>; 2886 clock-names = "apb_pclk"; 2887 arm,scatter-gather; 2888 2889 in-ports { 2890 port { 2891 etr_in: endpoint { 2892 remote-endpoint = <&replicator_out>; 2893 }; 2894 }; 2895 }; 2896 }; 2897 2898 funnel@6b04000 { 2899 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2900 arm,primecell-periphid = <0x000bb908>; 2901 2902 reg = <0 0x06b04000 0 0x1000>; 2903 reg-names = "funnel-base"; 2904 2905 clocks = <&aoss_qmp>; 2906 clock-names = "apb_pclk"; 2907 2908 out-ports { 2909 port { 2910 funnel_swao_out_etf: endpoint { 2911 remote-endpoint = <&etf_in_funnel_swao_out>; 2912 }; 2913 }; 2914 }; 2915 2916 in-ports { 2917 #address-cells = <1>; 2918 #size-cells = <0>; 2919 2920 port@7 { 2921 reg = <7>; 2922 funnel_swao_in_funnel_merg: endpoint { 2923 remote-endpoint= <&funnel_merg_out_funnel_swao>; 2924 }; 2925 }; 2926 }; 2927 2928 }; 2929 2930 etf@6b05000 { 2931 compatible = "arm,coresight-tmc", "arm,primecell"; 2932 reg = <0 0x06b05000 0 0x1000>; 2933 2934 clocks = <&aoss_qmp>; 2935 clock-names = "apb_pclk"; 2936 2937 out-ports { 2938 port { 2939 etf_out: endpoint { 2940 remote-endpoint = <&replicator_in>; 2941 }; 2942 }; 2943 }; 2944 2945 in-ports { 2946 #address-cells = <1>; 2947 #size-cells = <0>; 2948 2949 port@0 { 2950 reg = <0>; 2951 etf_in_funnel_swao_out: endpoint { 2952 remote-endpoint = <&funnel_swao_out_etf>; 2953 }; 2954 }; 2955 }; 2956 }; 2957 2958 replicator@6b06000 { 2959 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2960 reg = <0 0x06b06000 0 0x1000>; 2961 2962 clocks = <&aoss_qmp>; 2963 clock-names = "apb_pclk"; 2964 2965 out-ports { 2966 port { 2967 replicator_swao_out_cx_in: endpoint { 2968 remote-endpoint = <&replicator_cx_in_swao_out>; 2969 }; 2970 }; 2971 }; 2972 2973 in-ports { 2974 port { 2975 replicator_in: endpoint { 2976 remote-endpoint = <&etf_out>; 2977 }; 2978 }; 2979 }; 2980 }; 2981 2982 etm@7040000 { 2983 compatible = "arm,coresight-etm4x", "arm,primecell"; 2984 reg = <0 0x07040000 0 0x1000>; 2985 2986 cpu = <&CPU0>; 2987 2988 clocks = <&aoss_qmp>; 2989 clock-names = "apb_pclk"; 2990 arm,coresight-loses-context-with-cpu; 2991 2992 out-ports { 2993 port { 2994 etm0_out: endpoint { 2995 remote-endpoint = <&apss_funnel_in0>; 2996 }; 2997 }; 2998 }; 2999 }; 3000 3001 etm@7140000 { 3002 compatible = "arm,coresight-etm4x", "arm,primecell"; 3003 reg = <0 0x07140000 0 0x1000>; 3004 3005 cpu = <&CPU1>; 3006 3007 clocks = <&aoss_qmp>; 3008 clock-names = "apb_pclk"; 3009 arm,coresight-loses-context-with-cpu; 3010 3011 out-ports { 3012 port { 3013 etm1_out: endpoint { 3014 remote-endpoint = <&apss_funnel_in1>; 3015 }; 3016 }; 3017 }; 3018 }; 3019 3020 etm@7240000 { 3021 compatible = "arm,coresight-etm4x", "arm,primecell"; 3022 reg = <0 0x07240000 0 0x1000>; 3023 3024 cpu = <&CPU2>; 3025 3026 clocks = <&aoss_qmp>; 3027 clock-names = "apb_pclk"; 3028 arm,coresight-loses-context-with-cpu; 3029 3030 out-ports { 3031 port { 3032 etm2_out: endpoint { 3033 remote-endpoint = <&apss_funnel_in2>; 3034 }; 3035 }; 3036 }; 3037 }; 3038 3039 etm@7340000 { 3040 compatible = "arm,coresight-etm4x", "arm,primecell"; 3041 reg = <0 0x07340000 0 0x1000>; 3042 3043 cpu = <&CPU3>; 3044 3045 clocks = <&aoss_qmp>; 3046 clock-names = "apb_pclk"; 3047 arm,coresight-loses-context-with-cpu; 3048 3049 out-ports { 3050 port { 3051 etm3_out: endpoint { 3052 remote-endpoint = <&apss_funnel_in3>; 3053 }; 3054 }; 3055 }; 3056 }; 3057 3058 etm@7440000 { 3059 compatible = "arm,coresight-etm4x", "arm,primecell"; 3060 reg = <0 0x07440000 0 0x1000>; 3061 3062 cpu = <&CPU4>; 3063 3064 clocks = <&aoss_qmp>; 3065 clock-names = "apb_pclk"; 3066 arm,coresight-loses-context-with-cpu; 3067 3068 out-ports { 3069 port { 3070 etm4_out: endpoint { 3071 remote-endpoint = <&apss_funnel_in4>; 3072 }; 3073 }; 3074 }; 3075 }; 3076 3077 etm@7540000 { 3078 compatible = "arm,coresight-etm4x", "arm,primecell"; 3079 reg = <0 0x07540000 0 0x1000>; 3080 3081 cpu = <&CPU5>; 3082 3083 clocks = <&aoss_qmp>; 3084 clock-names = "apb_pclk"; 3085 arm,coresight-loses-context-with-cpu; 3086 3087 out-ports { 3088 port { 3089 etm5_out: endpoint { 3090 remote-endpoint = <&apss_funnel_in5>; 3091 }; 3092 }; 3093 }; 3094 }; 3095 3096 etm@7640000 { 3097 compatible = "arm,coresight-etm4x", "arm,primecell"; 3098 reg = <0 0x07640000 0 0x1000>; 3099 3100 cpu = <&CPU6>; 3101 3102 clocks = <&aoss_qmp>; 3103 clock-names = "apb_pclk"; 3104 arm,coresight-loses-context-with-cpu; 3105 3106 out-ports { 3107 port { 3108 etm6_out: endpoint { 3109 remote-endpoint = <&apss_funnel_in6>; 3110 }; 3111 }; 3112 }; 3113 }; 3114 3115 etm@7740000 { 3116 compatible = "arm,coresight-etm4x", "arm,primecell"; 3117 reg = <0 0x07740000 0 0x1000>; 3118 3119 cpu = <&CPU7>; 3120 3121 clocks = <&aoss_qmp>; 3122 clock-names = "apb_pclk"; 3123 arm,coresight-loses-context-with-cpu; 3124 3125 out-ports { 3126 port { 3127 etm7_out: endpoint { 3128 remote-endpoint = <&apss_funnel_in7>; 3129 }; 3130 }; 3131 }; 3132 }; 3133 3134 funnel@7800000 { 3135 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3136 reg = <0 0x07800000 0 0x1000>; 3137 3138 clocks = <&aoss_qmp>; 3139 clock-names = "apb_pclk"; 3140 3141 out-ports { 3142 port { 3143 funnel_apss_out_funnel_apss_merg: endpoint { 3144 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>; 3145 }; 3146 }; 3147 }; 3148 3149 in-ports { 3150 #address-cells = <1>; 3151 #size-cells = <0>; 3152 3153 port@0 { 3154 reg = <0>; 3155 apss_funnel_in0: endpoint { 3156 remote-endpoint = <&etm0_out>; 3157 }; 3158 }; 3159 3160 port@1 { 3161 reg = <1>; 3162 apss_funnel_in1: endpoint { 3163 remote-endpoint = <&etm1_out>; 3164 }; 3165 }; 3166 3167 port@2 { 3168 reg = <2>; 3169 apss_funnel_in2: endpoint { 3170 remote-endpoint = <&etm2_out>; 3171 }; 3172 }; 3173 3174 port@3 { 3175 reg = <3>; 3176 apss_funnel_in3: endpoint { 3177 remote-endpoint = <&etm3_out>; 3178 }; 3179 }; 3180 3181 port@4 { 3182 reg = <4>; 3183 apss_funnel_in4: endpoint { 3184 remote-endpoint = <&etm4_out>; 3185 }; 3186 }; 3187 3188 port@5 { 3189 reg = <5>; 3190 apss_funnel_in5: endpoint { 3191 remote-endpoint = <&etm5_out>; 3192 }; 3193 }; 3194 3195 port@6 { 3196 reg = <6>; 3197 apss_funnel_in6: endpoint { 3198 remote-endpoint = <&etm6_out>; 3199 }; 3200 }; 3201 3202 port@7 { 3203 reg = <7>; 3204 apss_funnel_in7: endpoint { 3205 remote-endpoint = <&etm7_out>; 3206 }; 3207 }; 3208 }; 3209 }; 3210 3211 funnel@7810000 { 3212 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3213 reg = <0 0x07810000 0 0x1000>; 3214 3215 clocks = <&aoss_qmp>; 3216 clock-names = "apb_pclk"; 3217 3218 out-ports { 3219 #address-cells = <1>; 3220 #size-cells = <0>; 3221 3222 port { 3223 funnel_apss_merg_out_funnel_in1: endpoint { 3224 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>; 3225 }; 3226 }; 3227 }; 3228 3229 in-ports { 3230 #address-cells = <1>; 3231 #size-cells = <0>; 3232 3233 port@0 { 3234 reg = <0>; 3235 funnel_apss_merg_in_funnel_apss: endpoint { 3236 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>; 3237 }; 3238 }; 3239 }; 3240 }; 3241 3242 cdsp: remoteproc@8300000 { 3243 compatible = "qcom,sm8250-cdsp-pas"; 3244 reg = <0 0x08300000 0 0x10000>; 3245 3246 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 3247 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3248 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3249 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3250 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3251 interrupt-names = "wdog", "fatal", "ready", 3252 "handover", "stop-ack"; 3253 3254 clocks = <&rpmhcc RPMH_CXO_CLK>; 3255 clock-names = "xo"; 3256 3257 power-domains = <&rpmhpd SM8250_CX>; 3258 3259 memory-region = <&cdsp_mem>; 3260 3261 qcom,qmp = <&aoss_qmp>; 3262 3263 qcom,smem-states = <&smp2p_cdsp_out 0>; 3264 qcom,smem-state-names = "stop"; 3265 3266 status = "disabled"; 3267 3268 glink-edge { 3269 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3270 IPCC_MPROC_SIGNAL_GLINK_QMP 3271 IRQ_TYPE_EDGE_RISING>; 3272 mboxes = <&ipcc IPCC_CLIENT_CDSP 3273 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3274 3275 label = "cdsp"; 3276 qcom,remote-pid = <5>; 3277 3278 fastrpc { 3279 compatible = "qcom,fastrpc"; 3280 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3281 label = "cdsp"; 3282 qcom,non-secure-domain; 3283 #address-cells = <1>; 3284 #size-cells = <0>; 3285 3286 compute-cb@1 { 3287 compatible = "qcom,fastrpc-compute-cb"; 3288 reg = <1>; 3289 iommus = <&apps_smmu 0x1001 0x0460>; 3290 }; 3291 3292 compute-cb@2 { 3293 compatible = "qcom,fastrpc-compute-cb"; 3294 reg = <2>; 3295 iommus = <&apps_smmu 0x1002 0x0460>; 3296 }; 3297 3298 compute-cb@3 { 3299 compatible = "qcom,fastrpc-compute-cb"; 3300 reg = <3>; 3301 iommus = <&apps_smmu 0x1003 0x0460>; 3302 }; 3303 3304 compute-cb@4 { 3305 compatible = "qcom,fastrpc-compute-cb"; 3306 reg = <4>; 3307 iommus = <&apps_smmu 0x1004 0x0460>; 3308 }; 3309 3310 compute-cb@5 { 3311 compatible = "qcom,fastrpc-compute-cb"; 3312 reg = <5>; 3313 iommus = <&apps_smmu 0x1005 0x0460>; 3314 }; 3315 3316 compute-cb@6 { 3317 compatible = "qcom,fastrpc-compute-cb"; 3318 reg = <6>; 3319 iommus = <&apps_smmu 0x1006 0x0460>; 3320 }; 3321 3322 compute-cb@7 { 3323 compatible = "qcom,fastrpc-compute-cb"; 3324 reg = <7>; 3325 iommus = <&apps_smmu 0x1007 0x0460>; 3326 }; 3327 3328 compute-cb@8 { 3329 compatible = "qcom,fastrpc-compute-cb"; 3330 reg = <8>; 3331 iommus = <&apps_smmu 0x1008 0x0460>; 3332 }; 3333 3334 /* note: secure cb9 in downstream */ 3335 }; 3336 }; 3337 }; 3338 3339 usb_1_hsphy: phy@88e3000 { 3340 compatible = "qcom,sm8250-usb-hs-phy", 3341 "qcom,usb-snps-hs-7nm-phy"; 3342 reg = <0 0x088e3000 0 0x400>; 3343 status = "disabled"; 3344 #phy-cells = <0>; 3345 3346 clocks = <&rpmhcc RPMH_CXO_CLK>; 3347 clock-names = "ref"; 3348 3349 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3350 }; 3351 3352 usb_2_hsphy: phy@88e4000 { 3353 compatible = "qcom,sm8250-usb-hs-phy", 3354 "qcom,usb-snps-hs-7nm-phy"; 3355 reg = <0 0x088e4000 0 0x400>; 3356 status = "disabled"; 3357 #phy-cells = <0>; 3358 3359 clocks = <&rpmhcc RPMH_CXO_CLK>; 3360 clock-names = "ref"; 3361 3362 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3363 }; 3364 3365 usb_1_qmpphy: phy@88e9000 { 3366 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 3367 reg = <0 0x088e9000 0 0x200>, 3368 <0 0x088e8000 0 0x40>, 3369 <0 0x088ea000 0 0x200>; 3370 status = "disabled"; 3371 #address-cells = <2>; 3372 #size-cells = <2>; 3373 ranges; 3374 3375 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3376 <&rpmhcc RPMH_CXO_CLK>, 3377 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3378 clock-names = "aux", "ref_clk_src", "com_aux"; 3379 3380 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3381 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3382 reset-names = "phy", "common"; 3383 3384 usb_1_ssphy: usb3-phy@88e9200 { 3385 reg = <0 0x088e9200 0 0x200>, 3386 <0 0x088e9400 0 0x200>, 3387 <0 0x088e9c00 0 0x400>, 3388 <0 0x088e9600 0 0x200>, 3389 <0 0x088e9800 0 0x200>, 3390 <0 0x088e9a00 0 0x100>; 3391 #clock-cells = <0>; 3392 #phy-cells = <0>; 3393 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3394 clock-names = "pipe0"; 3395 clock-output-names = "usb3_phy_pipe_clk_src"; 3396 }; 3397 3398 dp_phy: dp-phy@88ea200 { 3399 reg = <0 0x088ea200 0 0x200>, 3400 <0 0x088ea400 0 0x200>, 3401 <0 0x088eaa00 0 0x200>, 3402 <0 0x088ea600 0 0x200>, 3403 <0 0x088ea800 0 0x200>; 3404 #phy-cells = <0>; 3405 #clock-cells = <1>; 3406 }; 3407 }; 3408 3409 usb_2_qmpphy: phy@88eb000 { 3410 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 3411 reg = <0 0x088eb000 0 0x200>; 3412 status = "disabled"; 3413 #address-cells = <2>; 3414 #size-cells = <2>; 3415 ranges; 3416 3417 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3418 <&rpmhcc RPMH_CXO_CLK>, 3419 <&gcc GCC_USB3_SEC_CLKREF_EN>, 3420 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3421 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3422 3423 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3424 <&gcc GCC_USB3_PHY_SEC_BCR>; 3425 reset-names = "phy", "common"; 3426 3427 usb_2_ssphy: phy@88eb200 { 3428 reg = <0 0x088eb200 0 0x200>, 3429 <0 0x088eb400 0 0x200>, 3430 <0 0x088eb800 0 0x800>; 3431 #clock-cells = <0>; 3432 #phy-cells = <0>; 3433 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3434 clock-names = "pipe0"; 3435 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3436 }; 3437 }; 3438 3439 sdhc_2: mmc@8804000 { 3440 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 3441 reg = <0 0x08804000 0 0x1000>; 3442 3443 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3444 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3445 interrupt-names = "hc_irq", "pwr_irq"; 3446 3447 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3448 <&gcc GCC_SDCC2_APPS_CLK>, 3449 <&rpmhcc RPMH_CXO_CLK>; 3450 clock-names = "iface", "core", "xo"; 3451 iommus = <&apps_smmu 0x4a0 0x0>; 3452 qcom,dll-config = <0x0007642c>; 3453 qcom,ddr-config = <0x80040868>; 3454 power-domains = <&rpmhpd SM8250_CX>; 3455 operating-points-v2 = <&sdhc2_opp_table>; 3456 3457 status = "disabled"; 3458 3459 sdhc2_opp_table: opp-table { 3460 compatible = "operating-points-v2"; 3461 3462 opp-19200000 { 3463 opp-hz = /bits/ 64 <19200000>; 3464 required-opps = <&rpmhpd_opp_min_svs>; 3465 }; 3466 3467 opp-50000000 { 3468 opp-hz = /bits/ 64 <50000000>; 3469 required-opps = <&rpmhpd_opp_low_svs>; 3470 }; 3471 3472 opp-100000000 { 3473 opp-hz = /bits/ 64 <100000000>; 3474 required-opps = <&rpmhpd_opp_svs>; 3475 }; 3476 3477 opp-202000000 { 3478 opp-hz = /bits/ 64 <202000000>; 3479 required-opps = <&rpmhpd_opp_svs_l1>; 3480 }; 3481 }; 3482 }; 3483 3484 dc_noc: interconnect@90c0000 { 3485 compatible = "qcom,sm8250-dc-noc"; 3486 reg = <0 0x090c0000 0 0x4200>; 3487 #interconnect-cells = <1>; 3488 qcom,bcm-voters = <&apps_bcm_voter>; 3489 }; 3490 3491 gem_noc: interconnect@9100000 { 3492 compatible = "qcom,sm8250-gem-noc"; 3493 reg = <0 0x09100000 0 0xb4000>; 3494 #interconnect-cells = <1>; 3495 qcom,bcm-voters = <&apps_bcm_voter>; 3496 }; 3497 3498 npu_noc: interconnect@9990000 { 3499 compatible = "qcom,sm8250-npu-noc"; 3500 reg = <0 0x09990000 0 0x1600>; 3501 #interconnect-cells = <1>; 3502 qcom,bcm-voters = <&apps_bcm_voter>; 3503 }; 3504 3505 usb_1: usb@a6f8800 { 3506 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3507 reg = <0 0x0a6f8800 0 0x400>; 3508 status = "disabled"; 3509 #address-cells = <2>; 3510 #size-cells = <2>; 3511 ranges; 3512 dma-ranges; 3513 3514 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3515 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3516 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3517 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3518 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3519 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3520 clock-names = "cfg_noc", 3521 "core", 3522 "iface", 3523 "sleep", 3524 "mock_utmi", 3525 "xo"; 3526 3527 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3528 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3529 assigned-clock-rates = <19200000>, <200000000>; 3530 3531 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3532 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 3533 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3534 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 3535 interrupt-names = "hs_phy_irq", 3536 "ss_phy_irq", 3537 "dm_hs_phy_irq", 3538 "dp_hs_phy_irq"; 3539 3540 power-domains = <&gcc USB30_PRIM_GDSC>; 3541 3542 resets = <&gcc GCC_USB30_PRIM_BCR>; 3543 3544 usb_1_dwc3: usb@a600000 { 3545 compatible = "snps,dwc3"; 3546 reg = <0 0x0a600000 0 0xcd00>; 3547 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3548 iommus = <&apps_smmu 0x0 0x0>; 3549 snps,dis_u2_susphy_quirk; 3550 snps,dis_enblslpm_quirk; 3551 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3552 phy-names = "usb2-phy", "usb3-phy"; 3553 }; 3554 }; 3555 3556 system-cache-controller@9200000 { 3557 compatible = "qcom,sm8250-llcc"; 3558 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 3559 reg-names = "llcc_base", "llcc_broadcast_base"; 3560 }; 3561 3562 usb_2: usb@a8f8800 { 3563 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3564 reg = <0 0x0a8f8800 0 0x400>; 3565 status = "disabled"; 3566 #address-cells = <2>; 3567 #size-cells = <2>; 3568 ranges; 3569 dma-ranges; 3570 3571 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3572 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3573 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3574 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3575 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3576 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3577 clock-names = "cfg_noc", 3578 "core", 3579 "iface", 3580 "sleep", 3581 "mock_utmi", 3582 "xo"; 3583 3584 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3585 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3586 assigned-clock-rates = <19200000>, <200000000>; 3587 3588 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3589 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 3590 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3591 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 3592 interrupt-names = "hs_phy_irq", 3593 "ss_phy_irq", 3594 "dm_hs_phy_irq", 3595 "dp_hs_phy_irq"; 3596 3597 power-domains = <&gcc USB30_SEC_GDSC>; 3598 3599 resets = <&gcc GCC_USB30_SEC_BCR>; 3600 3601 usb_2_dwc3: usb@a800000 { 3602 compatible = "snps,dwc3"; 3603 reg = <0 0x0a800000 0 0xcd00>; 3604 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3605 iommus = <&apps_smmu 0x20 0>; 3606 snps,dis_u2_susphy_quirk; 3607 snps,dis_enblslpm_quirk; 3608 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3609 phy-names = "usb2-phy", "usb3-phy"; 3610 }; 3611 }; 3612 3613 venus: video-codec@aa00000 { 3614 compatible = "qcom,sm8250-venus"; 3615 reg = <0 0x0aa00000 0 0x100000>; 3616 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3617 power-domains = <&videocc MVS0C_GDSC>, 3618 <&videocc MVS0_GDSC>, 3619 <&rpmhpd SM8250_MX>; 3620 power-domain-names = "venus", "vcodec0", "mx"; 3621 operating-points-v2 = <&venus_opp_table>; 3622 3623 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 3624 <&videocc VIDEO_CC_MVS0C_CLK>, 3625 <&videocc VIDEO_CC_MVS0_CLK>; 3626 clock-names = "iface", "core", "vcodec0_core"; 3627 3628 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, 3629 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; 3630 interconnect-names = "cpu-cfg", "video-mem"; 3631 3632 iommus = <&apps_smmu 0x2100 0x0400>; 3633 memory-region = <&video_mem>; 3634 3635 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 3636 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 3637 reset-names = "bus", "core"; 3638 3639 status = "disabled"; 3640 3641 video-decoder { 3642 compatible = "venus-decoder"; 3643 }; 3644 3645 video-encoder { 3646 compatible = "venus-encoder"; 3647 }; 3648 3649 venus_opp_table: opp-table { 3650 compatible = "operating-points-v2"; 3651 3652 opp-720000000 { 3653 opp-hz = /bits/ 64 <720000000>; 3654 required-opps = <&rpmhpd_opp_low_svs>; 3655 }; 3656 3657 opp-1014000000 { 3658 opp-hz = /bits/ 64 <1014000000>; 3659 required-opps = <&rpmhpd_opp_svs>; 3660 }; 3661 3662 opp-1098000000 { 3663 opp-hz = /bits/ 64 <1098000000>; 3664 required-opps = <&rpmhpd_opp_svs_l1>; 3665 }; 3666 3667 opp-1332000000 { 3668 opp-hz = /bits/ 64 <1332000000>; 3669 required-opps = <&rpmhpd_opp_nom>; 3670 }; 3671 }; 3672 }; 3673 3674 videocc: clock-controller@abf0000 { 3675 compatible = "qcom,sm8250-videocc"; 3676 reg = <0 0x0abf0000 0 0x10000>; 3677 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 3678 <&rpmhcc RPMH_CXO_CLK>, 3679 <&rpmhcc RPMH_CXO_CLK_A>; 3680 power-domains = <&rpmhpd SM8250_MMCX>; 3681 required-opps = <&rpmhpd_opp_low_svs>; 3682 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 3683 #clock-cells = <1>; 3684 #reset-cells = <1>; 3685 #power-domain-cells = <1>; 3686 }; 3687 3688 cci0: cci@ac4f000 { 3689 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 3690 #address-cells = <1>; 3691 #size-cells = <0>; 3692 3693 reg = <0 0x0ac4f000 0 0x1000>; 3694 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3695 power-domains = <&camcc TITAN_TOP_GDSC>; 3696 3697 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3698 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3699 <&camcc CAM_CC_CPAS_AHB_CLK>, 3700 <&camcc CAM_CC_CCI_0_CLK>, 3701 <&camcc CAM_CC_CCI_0_CLK_SRC>; 3702 clock-names = "camnoc_axi", 3703 "slow_ahb_src", 3704 "cpas_ahb", 3705 "cci", 3706 "cci_src"; 3707 3708 pinctrl-0 = <&cci0_default>; 3709 pinctrl-1 = <&cci0_sleep>; 3710 pinctrl-names = "default", "sleep"; 3711 3712 status = "disabled"; 3713 3714 cci0_i2c0: i2c-bus@0 { 3715 reg = <0>; 3716 clock-frequency = <1000000>; 3717 #address-cells = <1>; 3718 #size-cells = <0>; 3719 }; 3720 3721 cci0_i2c1: i2c-bus@1 { 3722 reg = <1>; 3723 clock-frequency = <1000000>; 3724 #address-cells = <1>; 3725 #size-cells = <0>; 3726 }; 3727 }; 3728 3729 cci1: cci@ac50000 { 3730 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 3731 #address-cells = <1>; 3732 #size-cells = <0>; 3733 3734 reg = <0 0x0ac50000 0 0x1000>; 3735 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 3736 power-domains = <&camcc TITAN_TOP_GDSC>; 3737 3738 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3739 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3740 <&camcc CAM_CC_CPAS_AHB_CLK>, 3741 <&camcc CAM_CC_CCI_1_CLK>, 3742 <&camcc CAM_CC_CCI_1_CLK_SRC>; 3743 clock-names = "camnoc_axi", 3744 "slow_ahb_src", 3745 "cpas_ahb", 3746 "cci", 3747 "cci_src"; 3748 3749 pinctrl-0 = <&cci1_default>; 3750 pinctrl-1 = <&cci1_sleep>; 3751 pinctrl-names = "default", "sleep"; 3752 3753 status = "disabled"; 3754 3755 cci1_i2c0: i2c-bus@0 { 3756 reg = <0>; 3757 clock-frequency = <1000000>; 3758 #address-cells = <1>; 3759 #size-cells = <0>; 3760 }; 3761 3762 cci1_i2c1: i2c-bus@1 { 3763 reg = <1>; 3764 clock-frequency = <1000000>; 3765 #address-cells = <1>; 3766 #size-cells = <0>; 3767 }; 3768 }; 3769 3770 camss: camss@ac6a000 { 3771 compatible = "qcom,sm8250-camss"; 3772 status = "disabled"; 3773 3774 reg = <0 0x0ac6a000 0 0x2000>, 3775 <0 0x0ac6c000 0 0x2000>, 3776 <0 0x0ac6e000 0 0x1000>, 3777 <0 0x0ac70000 0 0x1000>, 3778 <0 0x0ac72000 0 0x1000>, 3779 <0 0x0ac74000 0 0x1000>, 3780 <0 0x0acb4000 0 0xd000>, 3781 <0 0x0acc3000 0 0xd000>, 3782 <0 0x0acd9000 0 0x2200>, 3783 <0 0x0acdb200 0 0x2200>; 3784 reg-names = "csiphy0", 3785 "csiphy1", 3786 "csiphy2", 3787 "csiphy3", 3788 "csiphy4", 3789 "csiphy5", 3790 "vfe0", 3791 "vfe1", 3792 "vfe_lite0", 3793 "vfe_lite1"; 3794 3795 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 3796 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 3798 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 3799 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 3800 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 3801 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 3802 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 3803 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 3804 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 3805 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 3806 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 3807 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 3808 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 3809 interrupt-names = "csiphy0", 3810 "csiphy1", 3811 "csiphy2", 3812 "csiphy3", 3813 "csiphy4", 3814 "csiphy5", 3815 "csid0", 3816 "csid1", 3817 "csid2", 3818 "csid3", 3819 "vfe0", 3820 "vfe1", 3821 "vfe_lite0", 3822 "vfe_lite1"; 3823 3824 power-domains = <&camcc IFE_0_GDSC>, 3825 <&camcc IFE_1_GDSC>, 3826 <&camcc TITAN_TOP_GDSC>; 3827 3828 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3829 <&gcc GCC_CAMERA_HF_AXI_CLK>, 3830 <&gcc GCC_CAMERA_SF_AXI_CLK>, 3831 <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3832 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, 3833 <&camcc CAM_CC_CORE_AHB_CLK>, 3834 <&camcc CAM_CC_CPAS_AHB_CLK>, 3835 <&camcc CAM_CC_CSIPHY0_CLK>, 3836 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 3837 <&camcc CAM_CC_CSIPHY1_CLK>, 3838 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 3839 <&camcc CAM_CC_CSIPHY2_CLK>, 3840 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 3841 <&camcc CAM_CC_CSIPHY3_CLK>, 3842 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 3843 <&camcc CAM_CC_CSIPHY4_CLK>, 3844 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 3845 <&camcc CAM_CC_CSIPHY5_CLK>, 3846 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 3847 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3848 <&camcc CAM_CC_IFE_0_AHB_CLK>, 3849 <&camcc CAM_CC_IFE_0_AXI_CLK>, 3850 <&camcc CAM_CC_IFE_0_CLK>, 3851 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 3852 <&camcc CAM_CC_IFE_0_CSID_CLK>, 3853 <&camcc CAM_CC_IFE_0_AREG_CLK>, 3854 <&camcc CAM_CC_IFE_1_AHB_CLK>, 3855 <&camcc CAM_CC_IFE_1_AXI_CLK>, 3856 <&camcc CAM_CC_IFE_1_CLK>, 3857 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 3858 <&camcc CAM_CC_IFE_1_CSID_CLK>, 3859 <&camcc CAM_CC_IFE_1_AREG_CLK>, 3860 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 3861 <&camcc CAM_CC_IFE_LITE_AXI_CLK>, 3862 <&camcc CAM_CC_IFE_LITE_CLK>, 3863 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 3864 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 3865 3866 clock-names = "cam_ahb_clk", 3867 "cam_hf_axi", 3868 "cam_sf_axi", 3869 "camnoc_axi", 3870 "camnoc_axi_src", 3871 "core_ahb", 3872 "cpas_ahb", 3873 "csiphy0", 3874 "csiphy0_timer", 3875 "csiphy1", 3876 "csiphy1_timer", 3877 "csiphy2", 3878 "csiphy2_timer", 3879 "csiphy3", 3880 "csiphy3_timer", 3881 "csiphy4", 3882 "csiphy4_timer", 3883 "csiphy5", 3884 "csiphy5_timer", 3885 "slow_ahb_src", 3886 "vfe0_ahb", 3887 "vfe0_axi", 3888 "vfe0", 3889 "vfe0_cphy_rx", 3890 "vfe0_csid", 3891 "vfe0_areg", 3892 "vfe1_ahb", 3893 "vfe1_axi", 3894 "vfe1", 3895 "vfe1_cphy_rx", 3896 "vfe1_csid", 3897 "vfe1_areg", 3898 "vfe_lite_ahb", 3899 "vfe_lite_axi", 3900 "vfe_lite", 3901 "vfe_lite_cphy_rx", 3902 "vfe_lite_csid"; 3903 3904 iommus = <&apps_smmu 0x800 0x400>, 3905 <&apps_smmu 0x801 0x400>, 3906 <&apps_smmu 0x840 0x400>, 3907 <&apps_smmu 0x841 0x400>, 3908 <&apps_smmu 0xc00 0x400>, 3909 <&apps_smmu 0xc01 0x400>, 3910 <&apps_smmu 0xc40 0x400>, 3911 <&apps_smmu 0xc41 0x400>; 3912 3913 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>, 3914 <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>, 3915 <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>, 3916 <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>; 3917 interconnect-names = "cam_ahb", 3918 "cam_hf_0_mnoc", 3919 "cam_sf_0_mnoc", 3920 "cam_sf_icp_mnoc"; 3921 3922 ports { 3923 #address-cells = <1>; 3924 #size-cells = <0>; 3925 3926 port@0 { 3927 reg = <0>; 3928 }; 3929 3930 port@1 { 3931 reg = <1>; 3932 }; 3933 3934 port@2 { 3935 reg = <2>; 3936 }; 3937 3938 port@3 { 3939 reg = <3>; 3940 }; 3941 3942 port@4 { 3943 reg = <4>; 3944 }; 3945 3946 port@5 { 3947 reg = <5>; 3948 }; 3949 }; 3950 }; 3951 3952 camcc: clock-controller@ad00000 { 3953 compatible = "qcom,sm8250-camcc"; 3954 reg = <0 0x0ad00000 0 0x10000>; 3955 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3956 <&rpmhcc RPMH_CXO_CLK>, 3957 <&rpmhcc RPMH_CXO_CLK_A>, 3958 <&sleep_clk>; 3959 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3960 power-domains = <&rpmhpd SM8250_MMCX>; 3961 required-opps = <&rpmhpd_opp_low_svs>; 3962 status = "disabled"; 3963 #clock-cells = <1>; 3964 #reset-cells = <1>; 3965 #power-domain-cells = <1>; 3966 }; 3967 3968 mdss: display-subsystem@ae00000 { 3969 compatible = "qcom,sm8250-mdss"; 3970 reg = <0 0x0ae00000 0 0x1000>; 3971 reg-names = "mdss"; 3972 3973 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 3974 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 3975 interconnect-names = "mdp0-mem", "mdp1-mem"; 3976 3977 power-domains = <&dispcc MDSS_GDSC>; 3978 3979 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3980 <&gcc GCC_DISP_HF_AXI_CLK>, 3981 <&gcc GCC_DISP_SF_AXI_CLK>, 3982 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3983 clock-names = "iface", "bus", "nrt_bus", "core"; 3984 3985 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3986 interrupt-controller; 3987 #interrupt-cells = <1>; 3988 3989 iommus = <&apps_smmu 0x820 0x402>; 3990 3991 status = "disabled"; 3992 3993 #address-cells = <2>; 3994 #size-cells = <2>; 3995 ranges; 3996 3997 mdss_mdp: display-controller@ae01000 { 3998 compatible = "qcom,sm8250-dpu"; 3999 reg = <0 0x0ae01000 0 0x8f000>, 4000 <0 0x0aeb0000 0 0x2008>; 4001 reg-names = "mdp", "vbif"; 4002 4003 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4004 <&gcc GCC_DISP_HF_AXI_CLK>, 4005 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4006 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4007 clock-names = "iface", "bus", "core", "vsync"; 4008 4009 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4010 assigned-clock-rates = <19200000>; 4011 4012 operating-points-v2 = <&mdp_opp_table>; 4013 power-domains = <&rpmhpd SM8250_MMCX>; 4014 4015 interrupt-parent = <&mdss>; 4016 interrupts = <0>; 4017 4018 ports { 4019 #address-cells = <1>; 4020 #size-cells = <0>; 4021 4022 port@0 { 4023 reg = <0>; 4024 dpu_intf1_out: endpoint { 4025 remote-endpoint = <&dsi0_in>; 4026 }; 4027 }; 4028 4029 port@1 { 4030 reg = <1>; 4031 dpu_intf2_out: endpoint { 4032 remote-endpoint = <&dsi1_in>; 4033 }; 4034 }; 4035 }; 4036 4037 mdp_opp_table: opp-table { 4038 compatible = "operating-points-v2"; 4039 4040 opp-200000000 { 4041 opp-hz = /bits/ 64 <200000000>; 4042 required-opps = <&rpmhpd_opp_low_svs>; 4043 }; 4044 4045 opp-300000000 { 4046 opp-hz = /bits/ 64 <300000000>; 4047 required-opps = <&rpmhpd_opp_svs>; 4048 }; 4049 4050 opp-345000000 { 4051 opp-hz = /bits/ 64 <345000000>; 4052 required-opps = <&rpmhpd_opp_svs_l1>; 4053 }; 4054 4055 opp-460000000 { 4056 opp-hz = /bits/ 64 <460000000>; 4057 required-opps = <&rpmhpd_opp_nom>; 4058 }; 4059 }; 4060 }; 4061 4062 dsi0: dsi@ae94000 { 4063 compatible = "qcom,sm8250-dsi-ctrl", 4064 "qcom,mdss-dsi-ctrl"; 4065 reg = <0 0x0ae94000 0 0x400>; 4066 reg-names = "dsi_ctrl"; 4067 4068 interrupt-parent = <&mdss>; 4069 interrupts = <4>; 4070 4071 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4072 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4073 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4074 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4075 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4076 <&gcc GCC_DISP_HF_AXI_CLK>; 4077 clock-names = "byte", 4078 "byte_intf", 4079 "pixel", 4080 "core", 4081 "iface", 4082 "bus"; 4083 4084 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4085 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 4086 4087 operating-points-v2 = <&dsi_opp_table>; 4088 power-domains = <&rpmhpd SM8250_MMCX>; 4089 4090 phys = <&dsi0_phy>; 4091 4092 status = "disabled"; 4093 4094 #address-cells = <1>; 4095 #size-cells = <0>; 4096 4097 ports { 4098 #address-cells = <1>; 4099 #size-cells = <0>; 4100 4101 port@0 { 4102 reg = <0>; 4103 dsi0_in: endpoint { 4104 remote-endpoint = <&dpu_intf1_out>; 4105 }; 4106 }; 4107 4108 port@1 { 4109 reg = <1>; 4110 dsi0_out: endpoint { 4111 }; 4112 }; 4113 }; 4114 4115 dsi_opp_table: opp-table { 4116 compatible = "operating-points-v2"; 4117 4118 opp-187500000 { 4119 opp-hz = /bits/ 64 <187500000>; 4120 required-opps = <&rpmhpd_opp_low_svs>; 4121 }; 4122 4123 opp-300000000 { 4124 opp-hz = /bits/ 64 <300000000>; 4125 required-opps = <&rpmhpd_opp_svs>; 4126 }; 4127 4128 opp-358000000 { 4129 opp-hz = /bits/ 64 <358000000>; 4130 required-opps = <&rpmhpd_opp_svs_l1>; 4131 }; 4132 }; 4133 }; 4134 4135 dsi0_phy: phy@ae94400 { 4136 compatible = "qcom,dsi-phy-7nm"; 4137 reg = <0 0x0ae94400 0 0x200>, 4138 <0 0x0ae94600 0 0x280>, 4139 <0 0x0ae94900 0 0x260>; 4140 reg-names = "dsi_phy", 4141 "dsi_phy_lane", 4142 "dsi_pll"; 4143 4144 #clock-cells = <1>; 4145 #phy-cells = <0>; 4146 4147 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4148 <&rpmhcc RPMH_CXO_CLK>; 4149 clock-names = "iface", "ref"; 4150 4151 status = "disabled"; 4152 }; 4153 4154 dsi1: dsi@ae96000 { 4155 compatible = "qcom,sm8250-dsi-ctrl", 4156 "qcom,mdss-dsi-ctrl"; 4157 reg = <0 0x0ae96000 0 0x400>; 4158 reg-names = "dsi_ctrl"; 4159 4160 interrupt-parent = <&mdss>; 4161 interrupts = <5>; 4162 4163 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4164 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4165 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4166 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4167 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4168 <&gcc GCC_DISP_HF_AXI_CLK>; 4169 clock-names = "byte", 4170 "byte_intf", 4171 "pixel", 4172 "core", 4173 "iface", 4174 "bus"; 4175 4176 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4177 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 4178 4179 operating-points-v2 = <&dsi_opp_table>; 4180 power-domains = <&rpmhpd SM8250_MMCX>; 4181 4182 phys = <&dsi1_phy>; 4183 4184 status = "disabled"; 4185 4186 #address-cells = <1>; 4187 #size-cells = <0>; 4188 4189 ports { 4190 #address-cells = <1>; 4191 #size-cells = <0>; 4192 4193 port@0 { 4194 reg = <0>; 4195 dsi1_in: endpoint { 4196 remote-endpoint = <&dpu_intf2_out>; 4197 }; 4198 }; 4199 4200 port@1 { 4201 reg = <1>; 4202 dsi1_out: endpoint { 4203 }; 4204 }; 4205 }; 4206 }; 4207 4208 dsi1_phy: phy@ae96400 { 4209 compatible = "qcom,dsi-phy-7nm"; 4210 reg = <0 0x0ae96400 0 0x200>, 4211 <0 0x0ae96600 0 0x280>, 4212 <0 0x0ae96900 0 0x260>; 4213 reg-names = "dsi_phy", 4214 "dsi_phy_lane", 4215 "dsi_pll"; 4216 4217 #clock-cells = <1>; 4218 #phy-cells = <0>; 4219 4220 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4221 <&rpmhcc RPMH_CXO_CLK>; 4222 clock-names = "iface", "ref"; 4223 4224 status = "disabled"; 4225 }; 4226 }; 4227 4228 dispcc: clock-controller@af00000 { 4229 compatible = "qcom,sm8250-dispcc"; 4230 reg = <0 0x0af00000 0 0x10000>; 4231 power-domains = <&rpmhpd SM8250_MMCX>; 4232 required-opps = <&rpmhpd_opp_low_svs>; 4233 clocks = <&rpmhcc RPMH_CXO_CLK>, 4234 <&dsi0_phy 0>, 4235 <&dsi0_phy 1>, 4236 <&dsi1_phy 0>, 4237 <&dsi1_phy 1>, 4238 <&dp_phy 0>, 4239 <&dp_phy 1>; 4240 clock-names = "bi_tcxo", 4241 "dsi0_phy_pll_out_byteclk", 4242 "dsi0_phy_pll_out_dsiclk", 4243 "dsi1_phy_pll_out_byteclk", 4244 "dsi1_phy_pll_out_dsiclk", 4245 "dp_phy_pll_link_clk", 4246 "dp_phy_pll_vco_div_clk"; 4247 #clock-cells = <1>; 4248 #reset-cells = <1>; 4249 #power-domain-cells = <1>; 4250 }; 4251 4252 pdc: interrupt-controller@b220000 { 4253 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 4254 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 4255 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4256 <125 63 1>, <126 716 12>; 4257 #interrupt-cells = <2>; 4258 interrupt-parent = <&intc>; 4259 interrupt-controller; 4260 }; 4261 4262 tsens0: thermal-sensor@c263000 { 4263 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 4264 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4265 <0 0x0c222000 0 0x1ff>; /* SROT */ 4266 #qcom,sensors = <16>; 4267 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4268 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4269 interrupt-names = "uplow", "critical"; 4270 #thermal-sensor-cells = <1>; 4271 }; 4272 4273 tsens1: thermal-sensor@c265000 { 4274 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 4275 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4276 <0 0x0c223000 0 0x1ff>; /* SROT */ 4277 #qcom,sensors = <9>; 4278 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4279 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4280 interrupt-names = "uplow", "critical"; 4281 #thermal-sensor-cells = <1>; 4282 }; 4283 4284 aoss_qmp: power-management@c300000 { 4285 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; 4286 reg = <0 0x0c300000 0 0x400>; 4287 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4288 IPCC_MPROC_SIGNAL_GLINK_QMP 4289 IRQ_TYPE_EDGE_RISING>; 4290 mboxes = <&ipcc IPCC_CLIENT_AOP 4291 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4292 4293 #clock-cells = <0>; 4294 }; 4295 4296 sram@c3f0000 { 4297 compatible = "qcom,rpmh-stats"; 4298 reg = <0 0x0c3f0000 0 0x400>; 4299 }; 4300 4301 spmi_bus: spmi@c440000 { 4302 compatible = "qcom,spmi-pmic-arb"; 4303 reg = <0x0 0x0c440000 0x0 0x0001100>, 4304 <0x0 0x0c600000 0x0 0x2000000>, 4305 <0x0 0x0e600000 0x0 0x0100000>, 4306 <0x0 0x0e700000 0x0 0x00a0000>, 4307 <0x0 0x0c40a000 0x0 0x0026000>; 4308 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4309 interrupt-names = "periph_irq"; 4310 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4311 qcom,ee = <0>; 4312 qcom,channel = <0>; 4313 #address-cells = <2>; 4314 #size-cells = <0>; 4315 interrupt-controller; 4316 #interrupt-cells = <4>; 4317 }; 4318 4319 tlmm: pinctrl@f100000 { 4320 compatible = "qcom,sm8250-pinctrl"; 4321 reg = <0 0x0f100000 0 0x300000>, 4322 <0 0x0f500000 0 0x300000>, 4323 <0 0x0f900000 0 0x300000>; 4324 reg-names = "west", "south", "north"; 4325 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4326 gpio-controller; 4327 #gpio-cells = <2>; 4328 interrupt-controller; 4329 #interrupt-cells = <2>; 4330 gpio-ranges = <&tlmm 0 0 181>; 4331 wakeup-parent = <&pdc>; 4332 4333 cam2_default: cam2-default-state { 4334 rst-pins { 4335 pins = "gpio78"; 4336 function = "gpio"; 4337 drive-strength = <2>; 4338 bias-disable; 4339 }; 4340 4341 mclk-pins { 4342 pins = "gpio96"; 4343 function = "cam_mclk"; 4344 drive-strength = <16>; 4345 bias-disable; 4346 }; 4347 }; 4348 4349 cam2_suspend: cam2-suspend-state { 4350 rst-pins { 4351 pins = "gpio78"; 4352 function = "gpio"; 4353 drive-strength = <2>; 4354 bias-pull-down; 4355 output-low; 4356 }; 4357 4358 mclk-pins { 4359 pins = "gpio96"; 4360 function = "cam_mclk"; 4361 drive-strength = <2>; 4362 bias-disable; 4363 }; 4364 }; 4365 4366 cci0_default: cci0-default-state { 4367 cci0_i2c0_default: cci0-i2c0-default-pins { 4368 /* SDA, SCL */ 4369 pins = "gpio101", "gpio102"; 4370 function = "cci_i2c"; 4371 4372 bias-pull-up; 4373 drive-strength = <2>; /* 2 mA */ 4374 }; 4375 4376 cci0_i2c1_default: cci0-i2c1-default-pins { 4377 /* SDA, SCL */ 4378 pins = "gpio103", "gpio104"; 4379 function = "cci_i2c"; 4380 4381 bias-pull-up; 4382 drive-strength = <2>; /* 2 mA */ 4383 }; 4384 }; 4385 4386 cci0_sleep: cci0-sleep-state { 4387 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 4388 /* SDA, SCL */ 4389 pins = "gpio101", "gpio102"; 4390 function = "cci_i2c"; 4391 4392 drive-strength = <2>; /* 2 mA */ 4393 bias-pull-down; 4394 }; 4395 4396 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 4397 /* SDA, SCL */ 4398 pins = "gpio103", "gpio104"; 4399 function = "cci_i2c"; 4400 4401 drive-strength = <2>; /* 2 mA */ 4402 bias-pull-down; 4403 }; 4404 }; 4405 4406 cci1_default: cci1-default-state { 4407 cci1_i2c0_default: cci1-i2c0-default-pins { 4408 /* SDA, SCL */ 4409 pins = "gpio105","gpio106"; 4410 function = "cci_i2c"; 4411 4412 bias-pull-up; 4413 drive-strength = <2>; /* 2 mA */ 4414 }; 4415 4416 cci1_i2c1_default: cci1-i2c1-default-pins { 4417 /* SDA, SCL */ 4418 pins = "gpio107","gpio108"; 4419 function = "cci_i2c"; 4420 4421 bias-pull-up; 4422 drive-strength = <2>; /* 2 mA */ 4423 }; 4424 }; 4425 4426 cci1_sleep: cci1-sleep-state { 4427 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 4428 /* SDA, SCL */ 4429 pins = "gpio105","gpio106"; 4430 function = "cci_i2c"; 4431 4432 bias-pull-down; 4433 drive-strength = <2>; /* 2 mA */ 4434 }; 4435 4436 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 4437 /* SDA, SCL */ 4438 pins = "gpio107","gpio108"; 4439 function = "cci_i2c"; 4440 4441 bias-pull-down; 4442 drive-strength = <2>; /* 2 mA */ 4443 }; 4444 }; 4445 4446 pri_mi2s_active: pri-mi2s-active-state { 4447 sclk-pins { 4448 pins = "gpio138"; 4449 function = "mi2s0_sck"; 4450 drive-strength = <8>; 4451 bias-disable; 4452 }; 4453 4454 ws-pins { 4455 pins = "gpio141"; 4456 function = "mi2s0_ws"; 4457 drive-strength = <8>; 4458 output-high; 4459 }; 4460 4461 data0-pins { 4462 pins = "gpio139"; 4463 function = "mi2s0_data0"; 4464 drive-strength = <8>; 4465 bias-disable; 4466 output-high; 4467 }; 4468 4469 data1-pins { 4470 pins = "gpio140"; 4471 function = "mi2s0_data1"; 4472 drive-strength = <8>; 4473 output-high; 4474 }; 4475 }; 4476 4477 qup_i2c0_default: qup-i2c0-default-state { 4478 pins = "gpio28", "gpio29"; 4479 function = "qup0"; 4480 drive-strength = <2>; 4481 bias-disable; 4482 }; 4483 4484 qup_i2c1_default: qup-i2c1-default-state { 4485 pins = "gpio4", "gpio5"; 4486 function = "qup1"; 4487 drive-strength = <2>; 4488 bias-disable; 4489 }; 4490 4491 qup_i2c2_default: qup-i2c2-default-state { 4492 pins = "gpio115", "gpio116"; 4493 function = "qup2"; 4494 drive-strength = <2>; 4495 bias-disable; 4496 }; 4497 4498 qup_i2c3_default: qup-i2c3-default-state { 4499 pins = "gpio119", "gpio120"; 4500 function = "qup3"; 4501 drive-strength = <2>; 4502 bias-disable; 4503 }; 4504 4505 qup_i2c4_default: qup-i2c4-default-state { 4506 pins = "gpio8", "gpio9"; 4507 function = "qup4"; 4508 drive-strength = <2>; 4509 bias-disable; 4510 }; 4511 4512 qup_i2c5_default: qup-i2c5-default-state { 4513 pins = "gpio12", "gpio13"; 4514 function = "qup5"; 4515 drive-strength = <2>; 4516 bias-disable; 4517 }; 4518 4519 qup_i2c6_default: qup-i2c6-default-state { 4520 pins = "gpio16", "gpio17"; 4521 function = "qup6"; 4522 drive-strength = <2>; 4523 bias-disable; 4524 }; 4525 4526 qup_i2c7_default: qup-i2c7-default-state { 4527 pins = "gpio20", "gpio21"; 4528 function = "qup7"; 4529 drive-strength = <2>; 4530 bias-disable; 4531 }; 4532 4533 qup_i2c8_default: qup-i2c8-default-state { 4534 pins = "gpio24", "gpio25"; 4535 function = "qup8"; 4536 drive-strength = <2>; 4537 bias-disable; 4538 }; 4539 4540 qup_i2c9_default: qup-i2c9-default-state { 4541 pins = "gpio125", "gpio126"; 4542 function = "qup9"; 4543 drive-strength = <2>; 4544 bias-disable; 4545 }; 4546 4547 qup_i2c10_default: qup-i2c10-default-state { 4548 pins = "gpio129", "gpio130"; 4549 function = "qup10"; 4550 drive-strength = <2>; 4551 bias-disable; 4552 }; 4553 4554 qup_i2c11_default: qup-i2c11-default-state { 4555 pins = "gpio60", "gpio61"; 4556 function = "qup11"; 4557 drive-strength = <2>; 4558 bias-disable; 4559 }; 4560 4561 qup_i2c12_default: qup-i2c12-default-state { 4562 pins = "gpio32", "gpio33"; 4563 function = "qup12"; 4564 drive-strength = <2>; 4565 bias-disable; 4566 }; 4567 4568 qup_i2c13_default: qup-i2c13-default-state { 4569 pins = "gpio36", "gpio37"; 4570 function = "qup13"; 4571 drive-strength = <2>; 4572 bias-disable; 4573 }; 4574 4575 qup_i2c14_default: qup-i2c14-default-state { 4576 pins = "gpio40", "gpio41"; 4577 function = "qup14"; 4578 drive-strength = <2>; 4579 bias-disable; 4580 }; 4581 4582 qup_i2c15_default: qup-i2c15-default-state { 4583 pins = "gpio44", "gpio45"; 4584 function = "qup15"; 4585 drive-strength = <2>; 4586 bias-disable; 4587 }; 4588 4589 qup_i2c16_default: qup-i2c16-default-state { 4590 pins = "gpio48", "gpio49"; 4591 function = "qup16"; 4592 drive-strength = <2>; 4593 bias-disable; 4594 }; 4595 4596 qup_i2c17_default: qup-i2c17-default-state { 4597 pins = "gpio52", "gpio53"; 4598 function = "qup17"; 4599 drive-strength = <2>; 4600 bias-disable; 4601 }; 4602 4603 qup_i2c18_default: qup-i2c18-default-state { 4604 pins = "gpio56", "gpio57"; 4605 function = "qup18"; 4606 drive-strength = <2>; 4607 bias-disable; 4608 }; 4609 4610 qup_i2c19_default: qup-i2c19-default-state { 4611 pins = "gpio0", "gpio1"; 4612 function = "qup19"; 4613 drive-strength = <2>; 4614 bias-disable; 4615 }; 4616 4617 qup_spi0_cs: qup-spi0-cs-state { 4618 pins = "gpio31"; 4619 function = "qup0"; 4620 }; 4621 4622 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4623 pins = "gpio31"; 4624 function = "gpio"; 4625 }; 4626 4627 qup_spi0_data_clk: qup-spi0-data-clk-state { 4628 pins = "gpio28", "gpio29", 4629 "gpio30"; 4630 function = "qup0"; 4631 }; 4632 4633 qup_spi1_cs: qup-spi1-cs-state { 4634 pins = "gpio7"; 4635 function = "qup1"; 4636 }; 4637 4638 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4639 pins = "gpio7"; 4640 function = "gpio"; 4641 }; 4642 4643 qup_spi1_data_clk: qup-spi1-data-clk-state { 4644 pins = "gpio4", "gpio5", 4645 "gpio6"; 4646 function = "qup1"; 4647 }; 4648 4649 qup_spi2_cs: qup-spi2-cs-state { 4650 pins = "gpio118"; 4651 function = "qup2"; 4652 }; 4653 4654 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4655 pins = "gpio118"; 4656 function = "gpio"; 4657 }; 4658 4659 qup_spi2_data_clk: qup-spi2-data-clk-state { 4660 pins = "gpio115", "gpio116", 4661 "gpio117"; 4662 function = "qup2"; 4663 }; 4664 4665 qup_spi3_cs: qup-spi3-cs-state { 4666 pins = "gpio122"; 4667 function = "qup3"; 4668 }; 4669 4670 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4671 pins = "gpio122"; 4672 function = "gpio"; 4673 }; 4674 4675 qup_spi3_data_clk: qup-spi3-data-clk-state { 4676 pins = "gpio119", "gpio120", 4677 "gpio121"; 4678 function = "qup3"; 4679 }; 4680 4681 qup_spi4_cs: qup-spi4-cs-state { 4682 pins = "gpio11"; 4683 function = "qup4"; 4684 }; 4685 4686 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4687 pins = "gpio11"; 4688 function = "gpio"; 4689 }; 4690 4691 qup_spi4_data_clk: qup-spi4-data-clk-state { 4692 pins = "gpio8", "gpio9", 4693 "gpio10"; 4694 function = "qup4"; 4695 }; 4696 4697 qup_spi5_cs: qup-spi5-cs-state { 4698 pins = "gpio15"; 4699 function = "qup5"; 4700 }; 4701 4702 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4703 pins = "gpio15"; 4704 function = "gpio"; 4705 }; 4706 4707 qup_spi5_data_clk: qup-spi5-data-clk-state { 4708 pins = "gpio12", "gpio13", 4709 "gpio14"; 4710 function = "qup5"; 4711 }; 4712 4713 qup_spi6_cs: qup-spi6-cs-state { 4714 pins = "gpio19"; 4715 function = "qup6"; 4716 }; 4717 4718 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4719 pins = "gpio19"; 4720 function = "gpio"; 4721 }; 4722 4723 qup_spi6_data_clk: qup-spi6-data-clk-state { 4724 pins = "gpio16", "gpio17", 4725 "gpio18"; 4726 function = "qup6"; 4727 }; 4728 4729 qup_spi7_cs: qup-spi7-cs-state { 4730 pins = "gpio23"; 4731 function = "qup7"; 4732 }; 4733 4734 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4735 pins = "gpio23"; 4736 function = "gpio"; 4737 }; 4738 4739 qup_spi7_data_clk: qup-spi7-data-clk-state { 4740 pins = "gpio20", "gpio21", 4741 "gpio22"; 4742 function = "qup7"; 4743 }; 4744 4745 qup_spi8_cs: qup-spi8-cs-state { 4746 pins = "gpio27"; 4747 function = "qup8"; 4748 }; 4749 4750 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4751 pins = "gpio27"; 4752 function = "gpio"; 4753 }; 4754 4755 qup_spi8_data_clk: qup-spi8-data-clk-state { 4756 pins = "gpio24", "gpio25", 4757 "gpio26"; 4758 function = "qup8"; 4759 }; 4760 4761 qup_spi9_cs: qup-spi9-cs-state { 4762 pins = "gpio128"; 4763 function = "qup9"; 4764 }; 4765 4766 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4767 pins = "gpio128"; 4768 function = "gpio"; 4769 }; 4770 4771 qup_spi9_data_clk: qup-spi9-data-clk-state { 4772 pins = "gpio125", "gpio126", 4773 "gpio127"; 4774 function = "qup9"; 4775 }; 4776 4777 qup_spi10_cs: qup-spi10-cs-state { 4778 pins = "gpio132"; 4779 function = "qup10"; 4780 }; 4781 4782 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4783 pins = "gpio132"; 4784 function = "gpio"; 4785 }; 4786 4787 qup_spi10_data_clk: qup-spi10-data-clk-state { 4788 pins = "gpio129", "gpio130", 4789 "gpio131"; 4790 function = "qup10"; 4791 }; 4792 4793 qup_spi11_cs: qup-spi11-cs-state { 4794 pins = "gpio63"; 4795 function = "qup11"; 4796 }; 4797 4798 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4799 pins = "gpio63"; 4800 function = "gpio"; 4801 }; 4802 4803 qup_spi11_data_clk: qup-spi11-data-clk-state { 4804 pins = "gpio60", "gpio61", 4805 "gpio62"; 4806 function = "qup11"; 4807 }; 4808 4809 qup_spi12_cs: qup-spi12-cs-state { 4810 pins = "gpio35"; 4811 function = "qup12"; 4812 }; 4813 4814 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4815 pins = "gpio35"; 4816 function = "gpio"; 4817 }; 4818 4819 qup_spi12_data_clk: qup-spi12-data-clk-state { 4820 pins = "gpio32", "gpio33", 4821 "gpio34"; 4822 function = "qup12"; 4823 }; 4824 4825 qup_spi13_cs: qup-spi13-cs-state { 4826 pins = "gpio39"; 4827 function = "qup13"; 4828 }; 4829 4830 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4831 pins = "gpio39"; 4832 function = "gpio"; 4833 }; 4834 4835 qup_spi13_data_clk: qup-spi13-data-clk-state { 4836 pins = "gpio36", "gpio37", 4837 "gpio38"; 4838 function = "qup13"; 4839 }; 4840 4841 qup_spi14_cs: qup-spi14-cs-state { 4842 pins = "gpio43"; 4843 function = "qup14"; 4844 }; 4845 4846 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4847 pins = "gpio43"; 4848 function = "gpio"; 4849 }; 4850 4851 qup_spi14_data_clk: qup-spi14-data-clk-state { 4852 pins = "gpio40", "gpio41", 4853 "gpio42"; 4854 function = "qup14"; 4855 }; 4856 4857 qup_spi15_cs: qup-spi15-cs-state { 4858 pins = "gpio47"; 4859 function = "qup15"; 4860 }; 4861 4862 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4863 pins = "gpio47"; 4864 function = "gpio"; 4865 }; 4866 4867 qup_spi15_data_clk: qup-spi15-data-clk-state { 4868 pins = "gpio44", "gpio45", 4869 "gpio46"; 4870 function = "qup15"; 4871 }; 4872 4873 qup_spi16_cs: qup-spi16-cs-state { 4874 pins = "gpio51"; 4875 function = "qup16"; 4876 }; 4877 4878 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 4879 pins = "gpio51"; 4880 function = "gpio"; 4881 }; 4882 4883 qup_spi16_data_clk: qup-spi16-data-clk-state { 4884 pins = "gpio48", "gpio49", 4885 "gpio50"; 4886 function = "qup16"; 4887 }; 4888 4889 qup_spi17_cs: qup-spi17-cs-state { 4890 pins = "gpio55"; 4891 function = "qup17"; 4892 }; 4893 4894 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state { 4895 pins = "gpio55"; 4896 function = "gpio"; 4897 }; 4898 4899 qup_spi17_data_clk: qup-spi17-data-clk-state { 4900 pins = "gpio52", "gpio53", 4901 "gpio54"; 4902 function = "qup17"; 4903 }; 4904 4905 qup_spi18_cs: qup-spi18-cs-state { 4906 pins = "gpio59"; 4907 function = "qup18"; 4908 }; 4909 4910 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state { 4911 pins = "gpio59"; 4912 function = "gpio"; 4913 }; 4914 4915 qup_spi18_data_clk: qup-spi18-data-clk-state { 4916 pins = "gpio56", "gpio57", 4917 "gpio58"; 4918 function = "qup18"; 4919 }; 4920 4921 qup_spi19_cs: qup-spi19-cs-state { 4922 pins = "gpio3"; 4923 function = "qup19"; 4924 }; 4925 4926 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state { 4927 pins = "gpio3"; 4928 function = "gpio"; 4929 }; 4930 4931 qup_spi19_data_clk: qup-spi19-data-clk-state { 4932 pins = "gpio0", "gpio1", 4933 "gpio2"; 4934 function = "qup19"; 4935 }; 4936 4937 qup_uart2_default: qup-uart2-default-state { 4938 pins = "gpio117", "gpio118"; 4939 function = "qup2"; 4940 }; 4941 4942 qup_uart6_default: qup-uart6-default-state { 4943 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 4944 function = "qup6"; 4945 }; 4946 4947 qup_uart12_default: qup-uart12-default-state { 4948 pins = "gpio34", "gpio35"; 4949 function = "qup12"; 4950 }; 4951 4952 qup_uart17_default: qup-uart17-default-state { 4953 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 4954 function = "qup17"; 4955 }; 4956 4957 qup_uart18_default: qup-uart18-default-state { 4958 pins = "gpio58", "gpio59"; 4959 function = "qup18"; 4960 }; 4961 4962 tert_mi2s_active: tert-mi2s-active-state { 4963 sck-pins { 4964 pins = "gpio133"; 4965 function = "mi2s2_sck"; 4966 drive-strength = <8>; 4967 bias-disable; 4968 }; 4969 4970 data0-pins { 4971 pins = "gpio134"; 4972 function = "mi2s2_data0"; 4973 drive-strength = <8>; 4974 bias-disable; 4975 output-high; 4976 }; 4977 4978 ws-pins { 4979 pins = "gpio135"; 4980 function = "mi2s2_ws"; 4981 drive-strength = <8>; 4982 output-high; 4983 }; 4984 }; 4985 4986 sdc2_sleep_state: sdc2-sleep-state { 4987 clk-pins { 4988 pins = "sdc2_clk"; 4989 drive-strength = <2>; 4990 bias-disable; 4991 }; 4992 4993 cmd-pins { 4994 pins = "sdc2_cmd"; 4995 drive-strength = <2>; 4996 bias-pull-up; 4997 }; 4998 4999 data-pins { 5000 pins = "sdc2_data"; 5001 drive-strength = <2>; 5002 bias-pull-up; 5003 }; 5004 }; 5005 5006 pcie0_default_state: pcie0-default-state { 5007 perst-pins { 5008 pins = "gpio79"; 5009 function = "gpio"; 5010 drive-strength = <2>; 5011 bias-pull-down; 5012 }; 5013 5014 clkreq-pins { 5015 pins = "gpio80"; 5016 function = "pci_e0"; 5017 drive-strength = <2>; 5018 bias-pull-up; 5019 }; 5020 5021 wake-pins { 5022 pins = "gpio81"; 5023 function = "gpio"; 5024 drive-strength = <2>; 5025 bias-pull-up; 5026 }; 5027 }; 5028 5029 pcie1_default_state: pcie1-default-state { 5030 perst-pins { 5031 pins = "gpio82"; 5032 function = "gpio"; 5033 drive-strength = <2>; 5034 bias-pull-down; 5035 }; 5036 5037 clkreq-pins { 5038 pins = "gpio83"; 5039 function = "pci_e1"; 5040 drive-strength = <2>; 5041 bias-pull-up; 5042 }; 5043 5044 wake-pins { 5045 pins = "gpio84"; 5046 function = "gpio"; 5047 drive-strength = <2>; 5048 bias-pull-up; 5049 }; 5050 }; 5051 5052 pcie2_default_state: pcie2-default-state { 5053 perst-pins { 5054 pins = "gpio85"; 5055 function = "gpio"; 5056 drive-strength = <2>; 5057 bias-pull-down; 5058 }; 5059 5060 clkreq-pins { 5061 pins = "gpio86"; 5062 function = "pci_e2"; 5063 drive-strength = <2>; 5064 bias-pull-up; 5065 }; 5066 5067 wake-pins { 5068 pins = "gpio87"; 5069 function = "gpio"; 5070 drive-strength = <2>; 5071 bias-pull-up; 5072 }; 5073 }; 5074 }; 5075 5076 apps_smmu: iommu@15000000 { 5077 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 5078 reg = <0 0x15000000 0 0x100000>; 5079 #iommu-cells = <2>; 5080 #global-interrupts = <2>; 5081 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5086 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5087 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5088 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5089 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5090 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5091 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5100 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 5179 }; 5180 5181 adsp: remoteproc@17300000 { 5182 compatible = "qcom,sm8250-adsp-pas"; 5183 reg = <0 0x17300000 0 0x100>; 5184 5185 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 5186 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 5187 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 5188 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 5189 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 5190 interrupt-names = "wdog", "fatal", "ready", 5191 "handover", "stop-ack"; 5192 5193 clocks = <&rpmhcc RPMH_CXO_CLK>; 5194 clock-names = "xo"; 5195 5196 power-domains = <&rpmhpd SM8250_LCX>, 5197 <&rpmhpd SM8250_LMX>; 5198 power-domain-names = "lcx", "lmx"; 5199 5200 memory-region = <&adsp_mem>; 5201 5202 qcom,qmp = <&aoss_qmp>; 5203 5204 qcom,smem-states = <&smp2p_adsp_out 0>; 5205 qcom,smem-state-names = "stop"; 5206 5207 status = "disabled"; 5208 5209 glink-edge { 5210 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 5211 IPCC_MPROC_SIGNAL_GLINK_QMP 5212 IRQ_TYPE_EDGE_RISING>; 5213 mboxes = <&ipcc IPCC_CLIENT_LPASS 5214 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5215 5216 label = "lpass"; 5217 qcom,remote-pid = <2>; 5218 5219 apr { 5220 compatible = "qcom,apr-v2"; 5221 qcom,glink-channels = "apr_audio_svc"; 5222 qcom,domain = <APR_DOMAIN_ADSP>; 5223 #address-cells = <1>; 5224 #size-cells = <0>; 5225 5226 service@3 { 5227 reg = <APR_SVC_ADSP_CORE>; 5228 compatible = "qcom,q6core"; 5229 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5230 }; 5231 5232 q6afe: service@4 { 5233 compatible = "qcom,q6afe"; 5234 reg = <APR_SVC_AFE>; 5235 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5236 q6afedai: dais { 5237 compatible = "qcom,q6afe-dais"; 5238 #address-cells = <1>; 5239 #size-cells = <0>; 5240 #sound-dai-cells = <1>; 5241 }; 5242 5243 q6afecc: clock-controller { 5244 compatible = "qcom,q6afe-clocks"; 5245 #clock-cells = <2>; 5246 }; 5247 }; 5248 5249 q6asm: service@7 { 5250 compatible = "qcom,q6asm"; 5251 reg = <APR_SVC_ASM>; 5252 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5253 q6asmdai: dais { 5254 compatible = "qcom,q6asm-dais"; 5255 #address-cells = <1>; 5256 #size-cells = <0>; 5257 #sound-dai-cells = <1>; 5258 iommus = <&apps_smmu 0x1801 0x0>; 5259 }; 5260 }; 5261 5262 q6adm: service@8 { 5263 compatible = "qcom,q6adm"; 5264 reg = <APR_SVC_ADM>; 5265 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5266 q6routing: routing { 5267 compatible = "qcom,q6adm-routing"; 5268 #sound-dai-cells = <0>; 5269 }; 5270 }; 5271 }; 5272 5273 fastrpc { 5274 compatible = "qcom,fastrpc"; 5275 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5276 label = "adsp"; 5277 qcom,non-secure-domain; 5278 #address-cells = <1>; 5279 #size-cells = <0>; 5280 5281 compute-cb@3 { 5282 compatible = "qcom,fastrpc-compute-cb"; 5283 reg = <3>; 5284 iommus = <&apps_smmu 0x1803 0x0>; 5285 }; 5286 5287 compute-cb@4 { 5288 compatible = "qcom,fastrpc-compute-cb"; 5289 reg = <4>; 5290 iommus = <&apps_smmu 0x1804 0x0>; 5291 }; 5292 5293 compute-cb@5 { 5294 compatible = "qcom,fastrpc-compute-cb"; 5295 reg = <5>; 5296 iommus = <&apps_smmu 0x1805 0x0>; 5297 }; 5298 }; 5299 }; 5300 }; 5301 5302 intc: interrupt-controller@17a00000 { 5303 compatible = "arm,gic-v3"; 5304 #interrupt-cells = <3>; 5305 interrupt-controller; 5306 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 5307 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 5308 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5309 }; 5310 5311 watchdog@17c10000 { 5312 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 5313 reg = <0 0x17c10000 0 0x1000>; 5314 clocks = <&sleep_clk>; 5315 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5316 }; 5317 5318 timer@17c20000 { 5319 #address-cells = <1>; 5320 #size-cells = <1>; 5321 ranges = <0 0 0 0x20000000>; 5322 compatible = "arm,armv7-timer-mem"; 5323 reg = <0x0 0x17c20000 0x0 0x1000>; 5324 clock-frequency = <19200000>; 5325 5326 frame@17c21000 { 5327 frame-number = <0>; 5328 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5329 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5330 reg = <0x17c21000 0x1000>, 5331 <0x17c22000 0x1000>; 5332 }; 5333 5334 frame@17c23000 { 5335 frame-number = <1>; 5336 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5337 reg = <0x17c23000 0x1000>; 5338 status = "disabled"; 5339 }; 5340 5341 frame@17c25000 { 5342 frame-number = <2>; 5343 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5344 reg = <0x17c25000 0x1000>; 5345 status = "disabled"; 5346 }; 5347 5348 frame@17c27000 { 5349 frame-number = <3>; 5350 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5351 reg = <0x17c27000 0x1000>; 5352 status = "disabled"; 5353 }; 5354 5355 frame@17c29000 { 5356 frame-number = <4>; 5357 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5358 reg = <0x17c29000 0x1000>; 5359 status = "disabled"; 5360 }; 5361 5362 frame@17c2b000 { 5363 frame-number = <5>; 5364 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5365 reg = <0x17c2b000 0x1000>; 5366 status = "disabled"; 5367 }; 5368 5369 frame@17c2d000 { 5370 frame-number = <6>; 5371 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5372 reg = <0x17c2d000 0x1000>; 5373 status = "disabled"; 5374 }; 5375 }; 5376 5377 apps_rsc: rsc@18200000 { 5378 label = "apps_rsc"; 5379 compatible = "qcom,rpmh-rsc"; 5380 reg = <0x0 0x18200000 0x0 0x10000>, 5381 <0x0 0x18210000 0x0 0x10000>, 5382 <0x0 0x18220000 0x0 0x10000>; 5383 reg-names = "drv-0", "drv-1", "drv-2"; 5384 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5385 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5386 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5387 qcom,tcs-offset = <0xd00>; 5388 qcom,drv-id = <2>; 5389 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 5390 <WAKE_TCS 3>, <CONTROL_TCS 1>; 5391 power-domains = <&CLUSTER_PD>; 5392 5393 rpmhcc: clock-controller { 5394 compatible = "qcom,sm8250-rpmh-clk"; 5395 #clock-cells = <1>; 5396 clock-names = "xo"; 5397 clocks = <&xo_board>; 5398 }; 5399 5400 rpmhpd: power-controller { 5401 compatible = "qcom,sm8250-rpmhpd"; 5402 #power-domain-cells = <1>; 5403 operating-points-v2 = <&rpmhpd_opp_table>; 5404 5405 rpmhpd_opp_table: opp-table { 5406 compatible = "operating-points-v2"; 5407 5408 rpmhpd_opp_ret: opp1 { 5409 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5410 }; 5411 5412 rpmhpd_opp_min_svs: opp2 { 5413 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5414 }; 5415 5416 rpmhpd_opp_low_svs: opp3 { 5417 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5418 }; 5419 5420 rpmhpd_opp_svs: opp4 { 5421 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5422 }; 5423 5424 rpmhpd_opp_svs_l1: opp5 { 5425 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5426 }; 5427 5428 rpmhpd_opp_nom: opp6 { 5429 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5430 }; 5431 5432 rpmhpd_opp_nom_l1: opp7 { 5433 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5434 }; 5435 5436 rpmhpd_opp_nom_l2: opp8 { 5437 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5438 }; 5439 5440 rpmhpd_opp_turbo: opp9 { 5441 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5442 }; 5443 5444 rpmhpd_opp_turbo_l1: opp10 { 5445 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5446 }; 5447 }; 5448 }; 5449 5450 apps_bcm_voter: bcm-voter { 5451 compatible = "qcom,bcm-voter"; 5452 }; 5453 }; 5454 5455 epss_l3: interconnect@18590000 { 5456 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3"; 5457 reg = <0 0x18590000 0 0x1000>; 5458 5459 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5460 clock-names = "xo", "alternate"; 5461 5462 #interconnect-cells = <1>; 5463 }; 5464 5465 cpufreq_hw: cpufreq@18591000 { 5466 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 5467 reg = <0 0x18591000 0 0x1000>, 5468 <0 0x18592000 0 0x1000>, 5469 <0 0x18593000 0 0x1000>; 5470 reg-names = "freq-domain0", "freq-domain1", 5471 "freq-domain2"; 5472 5473 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5474 clock-names = "xo", "alternate"; 5475 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5476 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5477 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5478 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 5479 #freq-domain-cells = <1>; 5480 }; 5481 }; 5482 5483 sound: sound { 5484 }; 5485 5486 timer { 5487 compatible = "arm,armv8-timer"; 5488 interrupts = <GIC_PPI 13 5489 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5490 <GIC_PPI 14 5491 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5492 <GIC_PPI 11 5493 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5494 <GIC_PPI 10 5495 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5496 }; 5497 5498 thermal-zones { 5499 cpu0-thermal { 5500 polling-delay-passive = <250>; 5501 polling-delay = <1000>; 5502 5503 thermal-sensors = <&tsens0 1>; 5504 5505 trips { 5506 cpu0_alert0: trip-point0 { 5507 temperature = <90000>; 5508 hysteresis = <2000>; 5509 type = "passive"; 5510 }; 5511 5512 cpu0_alert1: trip-point1 { 5513 temperature = <95000>; 5514 hysteresis = <2000>; 5515 type = "passive"; 5516 }; 5517 5518 cpu0_crit: cpu-crit { 5519 temperature = <110000>; 5520 hysteresis = <1000>; 5521 type = "critical"; 5522 }; 5523 }; 5524 5525 cooling-maps { 5526 map0 { 5527 trip = <&cpu0_alert0>; 5528 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5529 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5530 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5531 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5532 }; 5533 map1 { 5534 trip = <&cpu0_alert1>; 5535 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5536 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5537 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5538 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5539 }; 5540 }; 5541 }; 5542 5543 cpu1-thermal { 5544 polling-delay-passive = <250>; 5545 polling-delay = <1000>; 5546 5547 thermal-sensors = <&tsens0 2>; 5548 5549 trips { 5550 cpu1_alert0: trip-point0 { 5551 temperature = <90000>; 5552 hysteresis = <2000>; 5553 type = "passive"; 5554 }; 5555 5556 cpu1_alert1: trip-point1 { 5557 temperature = <95000>; 5558 hysteresis = <2000>; 5559 type = "passive"; 5560 }; 5561 5562 cpu1_crit: cpu-crit { 5563 temperature = <110000>; 5564 hysteresis = <1000>; 5565 type = "critical"; 5566 }; 5567 }; 5568 5569 cooling-maps { 5570 map0 { 5571 trip = <&cpu1_alert0>; 5572 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5573 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5574 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5575 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5576 }; 5577 map1 { 5578 trip = <&cpu1_alert1>; 5579 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5580 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5581 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5582 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5583 }; 5584 }; 5585 }; 5586 5587 cpu2-thermal { 5588 polling-delay-passive = <250>; 5589 polling-delay = <1000>; 5590 5591 thermal-sensors = <&tsens0 3>; 5592 5593 trips { 5594 cpu2_alert0: trip-point0 { 5595 temperature = <90000>; 5596 hysteresis = <2000>; 5597 type = "passive"; 5598 }; 5599 5600 cpu2_alert1: trip-point1 { 5601 temperature = <95000>; 5602 hysteresis = <2000>; 5603 type = "passive"; 5604 }; 5605 5606 cpu2_crit: cpu-crit { 5607 temperature = <110000>; 5608 hysteresis = <1000>; 5609 type = "critical"; 5610 }; 5611 }; 5612 5613 cooling-maps { 5614 map0 { 5615 trip = <&cpu2_alert0>; 5616 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5617 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5618 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5619 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5620 }; 5621 map1 { 5622 trip = <&cpu2_alert1>; 5623 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5624 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5625 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5626 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5627 }; 5628 }; 5629 }; 5630 5631 cpu3-thermal { 5632 polling-delay-passive = <250>; 5633 polling-delay = <1000>; 5634 5635 thermal-sensors = <&tsens0 4>; 5636 5637 trips { 5638 cpu3_alert0: trip-point0 { 5639 temperature = <90000>; 5640 hysteresis = <2000>; 5641 type = "passive"; 5642 }; 5643 5644 cpu3_alert1: trip-point1 { 5645 temperature = <95000>; 5646 hysteresis = <2000>; 5647 type = "passive"; 5648 }; 5649 5650 cpu3_crit: cpu-crit { 5651 temperature = <110000>; 5652 hysteresis = <1000>; 5653 type = "critical"; 5654 }; 5655 }; 5656 5657 cooling-maps { 5658 map0 { 5659 trip = <&cpu3_alert0>; 5660 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5661 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5662 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5663 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5664 }; 5665 map1 { 5666 trip = <&cpu3_alert1>; 5667 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5668 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5669 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5670 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5671 }; 5672 }; 5673 }; 5674 5675 cpu4-top-thermal { 5676 polling-delay-passive = <250>; 5677 polling-delay = <1000>; 5678 5679 thermal-sensors = <&tsens0 7>; 5680 5681 trips { 5682 cpu4_top_alert0: trip-point0 { 5683 temperature = <90000>; 5684 hysteresis = <2000>; 5685 type = "passive"; 5686 }; 5687 5688 cpu4_top_alert1: trip-point1 { 5689 temperature = <95000>; 5690 hysteresis = <2000>; 5691 type = "passive"; 5692 }; 5693 5694 cpu4_top_crit: cpu-crit { 5695 temperature = <110000>; 5696 hysteresis = <1000>; 5697 type = "critical"; 5698 }; 5699 }; 5700 5701 cooling-maps { 5702 map0 { 5703 trip = <&cpu4_top_alert0>; 5704 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5705 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5706 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5707 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5708 }; 5709 map1 { 5710 trip = <&cpu4_top_alert1>; 5711 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5712 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5713 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5714 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5715 }; 5716 }; 5717 }; 5718 5719 cpu5-top-thermal { 5720 polling-delay-passive = <250>; 5721 polling-delay = <1000>; 5722 5723 thermal-sensors = <&tsens0 8>; 5724 5725 trips { 5726 cpu5_top_alert0: trip-point0 { 5727 temperature = <90000>; 5728 hysteresis = <2000>; 5729 type = "passive"; 5730 }; 5731 5732 cpu5_top_alert1: trip-point1 { 5733 temperature = <95000>; 5734 hysteresis = <2000>; 5735 type = "passive"; 5736 }; 5737 5738 cpu5_top_crit: cpu-crit { 5739 temperature = <110000>; 5740 hysteresis = <1000>; 5741 type = "critical"; 5742 }; 5743 }; 5744 5745 cooling-maps { 5746 map0 { 5747 trip = <&cpu5_top_alert0>; 5748 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5749 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5750 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5751 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5752 }; 5753 map1 { 5754 trip = <&cpu5_top_alert1>; 5755 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5756 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5757 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5758 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5759 }; 5760 }; 5761 }; 5762 5763 cpu6-top-thermal { 5764 polling-delay-passive = <250>; 5765 polling-delay = <1000>; 5766 5767 thermal-sensors = <&tsens0 9>; 5768 5769 trips { 5770 cpu6_top_alert0: trip-point0 { 5771 temperature = <90000>; 5772 hysteresis = <2000>; 5773 type = "passive"; 5774 }; 5775 5776 cpu6_top_alert1: trip-point1 { 5777 temperature = <95000>; 5778 hysteresis = <2000>; 5779 type = "passive"; 5780 }; 5781 5782 cpu6_top_crit: cpu-crit { 5783 temperature = <110000>; 5784 hysteresis = <1000>; 5785 type = "critical"; 5786 }; 5787 }; 5788 5789 cooling-maps { 5790 map0 { 5791 trip = <&cpu6_top_alert0>; 5792 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5793 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5794 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5795 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5796 }; 5797 map1 { 5798 trip = <&cpu6_top_alert1>; 5799 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5800 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5801 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5802 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5803 }; 5804 }; 5805 }; 5806 5807 cpu7-top-thermal { 5808 polling-delay-passive = <250>; 5809 polling-delay = <1000>; 5810 5811 thermal-sensors = <&tsens0 10>; 5812 5813 trips { 5814 cpu7_top_alert0: trip-point0 { 5815 temperature = <90000>; 5816 hysteresis = <2000>; 5817 type = "passive"; 5818 }; 5819 5820 cpu7_top_alert1: trip-point1 { 5821 temperature = <95000>; 5822 hysteresis = <2000>; 5823 type = "passive"; 5824 }; 5825 5826 cpu7_top_crit: cpu-crit { 5827 temperature = <110000>; 5828 hysteresis = <1000>; 5829 type = "critical"; 5830 }; 5831 }; 5832 5833 cooling-maps { 5834 map0 { 5835 trip = <&cpu7_top_alert0>; 5836 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5837 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5838 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5839 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5840 }; 5841 map1 { 5842 trip = <&cpu7_top_alert1>; 5843 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5844 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5845 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5846 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5847 }; 5848 }; 5849 }; 5850 5851 cpu4-bottom-thermal { 5852 polling-delay-passive = <250>; 5853 polling-delay = <1000>; 5854 5855 thermal-sensors = <&tsens0 11>; 5856 5857 trips { 5858 cpu4_bottom_alert0: trip-point0 { 5859 temperature = <90000>; 5860 hysteresis = <2000>; 5861 type = "passive"; 5862 }; 5863 5864 cpu4_bottom_alert1: trip-point1 { 5865 temperature = <95000>; 5866 hysteresis = <2000>; 5867 type = "passive"; 5868 }; 5869 5870 cpu4_bottom_crit: cpu-crit { 5871 temperature = <110000>; 5872 hysteresis = <1000>; 5873 type = "critical"; 5874 }; 5875 }; 5876 5877 cooling-maps { 5878 map0 { 5879 trip = <&cpu4_bottom_alert0>; 5880 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5881 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5882 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5883 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5884 }; 5885 map1 { 5886 trip = <&cpu4_bottom_alert1>; 5887 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5888 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5889 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5890 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5891 }; 5892 }; 5893 }; 5894 5895 cpu5-bottom-thermal { 5896 polling-delay-passive = <250>; 5897 polling-delay = <1000>; 5898 5899 thermal-sensors = <&tsens0 12>; 5900 5901 trips { 5902 cpu5_bottom_alert0: trip-point0 { 5903 temperature = <90000>; 5904 hysteresis = <2000>; 5905 type = "passive"; 5906 }; 5907 5908 cpu5_bottom_alert1: trip-point1 { 5909 temperature = <95000>; 5910 hysteresis = <2000>; 5911 type = "passive"; 5912 }; 5913 5914 cpu5_bottom_crit: cpu-crit { 5915 temperature = <110000>; 5916 hysteresis = <1000>; 5917 type = "critical"; 5918 }; 5919 }; 5920 5921 cooling-maps { 5922 map0 { 5923 trip = <&cpu5_bottom_alert0>; 5924 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5925 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5926 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5927 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5928 }; 5929 map1 { 5930 trip = <&cpu5_bottom_alert1>; 5931 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5932 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5933 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5934 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5935 }; 5936 }; 5937 }; 5938 5939 cpu6-bottom-thermal { 5940 polling-delay-passive = <250>; 5941 polling-delay = <1000>; 5942 5943 thermal-sensors = <&tsens0 13>; 5944 5945 trips { 5946 cpu6_bottom_alert0: trip-point0 { 5947 temperature = <90000>; 5948 hysteresis = <2000>; 5949 type = "passive"; 5950 }; 5951 5952 cpu6_bottom_alert1: trip-point1 { 5953 temperature = <95000>; 5954 hysteresis = <2000>; 5955 type = "passive"; 5956 }; 5957 5958 cpu6_bottom_crit: cpu-crit { 5959 temperature = <110000>; 5960 hysteresis = <1000>; 5961 type = "critical"; 5962 }; 5963 }; 5964 5965 cooling-maps { 5966 map0 { 5967 trip = <&cpu6_bottom_alert0>; 5968 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5969 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5970 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5971 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5972 }; 5973 map1 { 5974 trip = <&cpu6_bottom_alert1>; 5975 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5976 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5977 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5978 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5979 }; 5980 }; 5981 }; 5982 5983 cpu7-bottom-thermal { 5984 polling-delay-passive = <250>; 5985 polling-delay = <1000>; 5986 5987 thermal-sensors = <&tsens0 14>; 5988 5989 trips { 5990 cpu7_bottom_alert0: trip-point0 { 5991 temperature = <90000>; 5992 hysteresis = <2000>; 5993 type = "passive"; 5994 }; 5995 5996 cpu7_bottom_alert1: trip-point1 { 5997 temperature = <95000>; 5998 hysteresis = <2000>; 5999 type = "passive"; 6000 }; 6001 6002 cpu7_bottom_crit: cpu-crit { 6003 temperature = <110000>; 6004 hysteresis = <1000>; 6005 type = "critical"; 6006 }; 6007 }; 6008 6009 cooling-maps { 6010 map0 { 6011 trip = <&cpu7_bottom_alert0>; 6012 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6013 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6014 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6015 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6016 }; 6017 map1 { 6018 trip = <&cpu7_bottom_alert1>; 6019 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6020 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6021 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6022 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6023 }; 6024 }; 6025 }; 6026 6027 aoss0-thermal { 6028 polling-delay-passive = <250>; 6029 polling-delay = <1000>; 6030 6031 thermal-sensors = <&tsens0 0>; 6032 6033 trips { 6034 aoss0_alert0: trip-point0 { 6035 temperature = <90000>; 6036 hysteresis = <2000>; 6037 type = "hot"; 6038 }; 6039 }; 6040 }; 6041 6042 cluster0-thermal { 6043 polling-delay-passive = <250>; 6044 polling-delay = <1000>; 6045 6046 thermal-sensors = <&tsens0 5>; 6047 6048 trips { 6049 cluster0_alert0: trip-point0 { 6050 temperature = <90000>; 6051 hysteresis = <2000>; 6052 type = "hot"; 6053 }; 6054 cluster0_crit: cluster0_crit { 6055 temperature = <110000>; 6056 hysteresis = <2000>; 6057 type = "critical"; 6058 }; 6059 }; 6060 }; 6061 6062 cluster1-thermal { 6063 polling-delay-passive = <250>; 6064 polling-delay = <1000>; 6065 6066 thermal-sensors = <&tsens0 6>; 6067 6068 trips { 6069 cluster1_alert0: trip-point0 { 6070 temperature = <90000>; 6071 hysteresis = <2000>; 6072 type = "hot"; 6073 }; 6074 cluster1_crit: cluster1_crit { 6075 temperature = <110000>; 6076 hysteresis = <2000>; 6077 type = "critical"; 6078 }; 6079 }; 6080 }; 6081 6082 gpu-top-thermal { 6083 polling-delay-passive = <250>; 6084 polling-delay = <1000>; 6085 6086 thermal-sensors = <&tsens0 15>; 6087 6088 trips { 6089 gpu1_alert0: trip-point0 { 6090 temperature = <90000>; 6091 hysteresis = <2000>; 6092 type = "hot"; 6093 }; 6094 }; 6095 }; 6096 6097 aoss1-thermal { 6098 polling-delay-passive = <250>; 6099 polling-delay = <1000>; 6100 6101 thermal-sensors = <&tsens1 0>; 6102 6103 trips { 6104 aoss1_alert0: trip-point0 { 6105 temperature = <90000>; 6106 hysteresis = <2000>; 6107 type = "hot"; 6108 }; 6109 }; 6110 }; 6111 6112 wlan-thermal { 6113 polling-delay-passive = <250>; 6114 polling-delay = <1000>; 6115 6116 thermal-sensors = <&tsens1 1>; 6117 6118 trips { 6119 wlan_alert0: trip-point0 { 6120 temperature = <90000>; 6121 hysteresis = <2000>; 6122 type = "hot"; 6123 }; 6124 }; 6125 }; 6126 6127 video-thermal { 6128 polling-delay-passive = <250>; 6129 polling-delay = <1000>; 6130 6131 thermal-sensors = <&tsens1 2>; 6132 6133 trips { 6134 video_alert0: trip-point0 { 6135 temperature = <90000>; 6136 hysteresis = <2000>; 6137 type = "hot"; 6138 }; 6139 }; 6140 }; 6141 6142 mem-thermal { 6143 polling-delay-passive = <250>; 6144 polling-delay = <1000>; 6145 6146 thermal-sensors = <&tsens1 3>; 6147 6148 trips { 6149 mem_alert0: trip-point0 { 6150 temperature = <90000>; 6151 hysteresis = <2000>; 6152 type = "hot"; 6153 }; 6154 }; 6155 }; 6156 6157 q6-hvx-thermal { 6158 polling-delay-passive = <250>; 6159 polling-delay = <1000>; 6160 6161 thermal-sensors = <&tsens1 4>; 6162 6163 trips { 6164 q6_hvx_alert0: trip-point0 { 6165 temperature = <90000>; 6166 hysteresis = <2000>; 6167 type = "hot"; 6168 }; 6169 }; 6170 }; 6171 6172 camera-thermal { 6173 polling-delay-passive = <250>; 6174 polling-delay = <1000>; 6175 6176 thermal-sensors = <&tsens1 5>; 6177 6178 trips { 6179 camera_alert0: trip-point0 { 6180 temperature = <90000>; 6181 hysteresis = <2000>; 6182 type = "hot"; 6183 }; 6184 }; 6185 }; 6186 6187 compute-thermal { 6188 polling-delay-passive = <250>; 6189 polling-delay = <1000>; 6190 6191 thermal-sensors = <&tsens1 6>; 6192 6193 trips { 6194 compute_alert0: trip-point0 { 6195 temperature = <90000>; 6196 hysteresis = <2000>; 6197 type = "hot"; 6198 }; 6199 }; 6200 }; 6201 6202 npu-thermal { 6203 polling-delay-passive = <250>; 6204 polling-delay = <1000>; 6205 6206 thermal-sensors = <&tsens1 7>; 6207 6208 trips { 6209 npu_alert0: trip-point0 { 6210 temperature = <90000>; 6211 hysteresis = <2000>; 6212 type = "hot"; 6213 }; 6214 }; 6215 }; 6216 6217 gpu-bottom-thermal { 6218 polling-delay-passive = <250>; 6219 polling-delay = <1000>; 6220 6221 thermal-sensors = <&tsens1 8>; 6222 6223 trips { 6224 gpu2_alert0: trip-point0 { 6225 temperature = <90000>; 6226 hysteresis = <2000>; 6227 type = "hot"; 6228 }; 6229 }; 6230 }; 6231 }; 6232}; 6233