1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h> 12#include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sm8250.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,apr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/sound/qcom,q6afe.h> 22#include <dt-bindings/thermal/thermal.h> 23#include <dt-bindings/clock/qcom,camcc-sm8250.h> 24#include <dt-bindings/clock/qcom,videocc-sm8250.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 aliases { 33 i2c0 = &i2c0; 34 i2c1 = &i2c1; 35 i2c2 = &i2c2; 36 i2c3 = &i2c3; 37 i2c4 = &i2c4; 38 i2c5 = &i2c5; 39 i2c6 = &i2c6; 40 i2c7 = &i2c7; 41 i2c8 = &i2c8; 42 i2c9 = &i2c9; 43 i2c10 = &i2c10; 44 i2c11 = &i2c11; 45 i2c12 = &i2c12; 46 i2c13 = &i2c13; 47 i2c14 = &i2c14; 48 i2c15 = &i2c15; 49 i2c16 = &i2c16; 50 i2c17 = &i2c17; 51 i2c18 = &i2c18; 52 i2c19 = &i2c19; 53 spi0 = &spi0; 54 spi1 = &spi1; 55 spi2 = &spi2; 56 spi3 = &spi3; 57 spi4 = &spi4; 58 spi5 = &spi5; 59 spi6 = &spi6; 60 spi7 = &spi7; 61 spi8 = &spi8; 62 spi9 = &spi9; 63 spi10 = &spi10; 64 spi11 = &spi11; 65 spi12 = &spi12; 66 spi13 = &spi13; 67 spi14 = &spi14; 68 spi15 = &spi15; 69 spi16 = &spi16; 70 spi17 = &spi17; 71 spi18 = &spi18; 72 spi19 = &spi19; 73 }; 74 75 chosen { }; 76 77 clocks { 78 xo_board: xo-board { 79 compatible = "fixed-clock"; 80 #clock-cells = <0>; 81 clock-frequency = <38400000>; 82 clock-output-names = "xo_board"; 83 }; 84 85 sleep_clk: sleep-clk { 86 compatible = "fixed-clock"; 87 clock-frequency = <32768>; 88 #clock-cells = <0>; 89 }; 90 }; 91 92 cpus { 93 #address-cells = <2>; 94 #size-cells = <0>; 95 96 CPU0: cpu@0 { 97 device_type = "cpu"; 98 compatible = "qcom,kryo485"; 99 reg = <0x0 0x0>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <448>; 102 dynamic-power-coefficient = <205>; 103 next-level-cache = <&L2_0>; 104 power-domains = <&CPU_PD0>; 105 power-domain-names = "psci"; 106 qcom,freq-domain = <&cpufreq_hw 0>; 107 operating-points-v2 = <&cpu0_opp_table>; 108 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 109 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 110 #cooling-cells = <2>; 111 L2_0: l2-cache { 112 compatible = "cache"; 113 next-level-cache = <&L3_0>; 114 L3_0: l3-cache { 115 compatible = "cache"; 116 }; 117 }; 118 }; 119 120 CPU1: cpu@100 { 121 device_type = "cpu"; 122 compatible = "qcom,kryo485"; 123 reg = <0x0 0x100>; 124 enable-method = "psci"; 125 capacity-dmips-mhz = <448>; 126 dynamic-power-coefficient = <205>; 127 next-level-cache = <&L2_100>; 128 power-domains = <&CPU_PD1>; 129 power-domain-names = "psci"; 130 qcom,freq-domain = <&cpufreq_hw 0>; 131 operating-points-v2 = <&cpu0_opp_table>; 132 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 133 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 134 #cooling-cells = <2>; 135 L2_100: l2-cache { 136 compatible = "cache"; 137 next-level-cache = <&L3_0>; 138 }; 139 }; 140 141 CPU2: cpu@200 { 142 device_type = "cpu"; 143 compatible = "qcom,kryo485"; 144 reg = <0x0 0x200>; 145 enable-method = "psci"; 146 capacity-dmips-mhz = <448>; 147 dynamic-power-coefficient = <205>; 148 next-level-cache = <&L2_200>; 149 power-domains = <&CPU_PD2>; 150 power-domain-names = "psci"; 151 qcom,freq-domain = <&cpufreq_hw 0>; 152 operating-points-v2 = <&cpu0_opp_table>; 153 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 154 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 155 #cooling-cells = <2>; 156 L2_200: l2-cache { 157 compatible = "cache"; 158 next-level-cache = <&L3_0>; 159 }; 160 }; 161 162 CPU3: cpu@300 { 163 device_type = "cpu"; 164 compatible = "qcom,kryo485"; 165 reg = <0x0 0x300>; 166 enable-method = "psci"; 167 capacity-dmips-mhz = <448>; 168 dynamic-power-coefficient = <205>; 169 next-level-cache = <&L2_300>; 170 power-domains = <&CPU_PD3>; 171 power-domain-names = "psci"; 172 qcom,freq-domain = <&cpufreq_hw 0>; 173 operating-points-v2 = <&cpu0_opp_table>; 174 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 175 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 176 #cooling-cells = <2>; 177 L2_300: l2-cache { 178 compatible = "cache"; 179 next-level-cache = <&L3_0>; 180 }; 181 }; 182 183 CPU4: cpu@400 { 184 device_type = "cpu"; 185 compatible = "qcom,kryo485"; 186 reg = <0x0 0x400>; 187 enable-method = "psci"; 188 capacity-dmips-mhz = <1024>; 189 dynamic-power-coefficient = <379>; 190 next-level-cache = <&L2_400>; 191 power-domains = <&CPU_PD4>; 192 power-domain-names = "psci"; 193 qcom,freq-domain = <&cpufreq_hw 1>; 194 operating-points-v2 = <&cpu4_opp_table>; 195 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 196 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 197 #cooling-cells = <2>; 198 L2_400: l2-cache { 199 compatible = "cache"; 200 next-level-cache = <&L3_0>; 201 }; 202 }; 203 204 CPU5: cpu@500 { 205 device_type = "cpu"; 206 compatible = "qcom,kryo485"; 207 reg = <0x0 0x500>; 208 enable-method = "psci"; 209 capacity-dmips-mhz = <1024>; 210 dynamic-power-coefficient = <379>; 211 next-level-cache = <&L2_500>; 212 power-domains = <&CPU_PD5>; 213 power-domain-names = "psci"; 214 qcom,freq-domain = <&cpufreq_hw 1>; 215 operating-points-v2 = <&cpu4_opp_table>; 216 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 217 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 218 #cooling-cells = <2>; 219 L2_500: l2-cache { 220 compatible = "cache"; 221 next-level-cache = <&L3_0>; 222 }; 223 224 }; 225 226 CPU6: cpu@600 { 227 device_type = "cpu"; 228 compatible = "qcom,kryo485"; 229 reg = <0x0 0x600>; 230 enable-method = "psci"; 231 capacity-dmips-mhz = <1024>; 232 dynamic-power-coefficient = <379>; 233 next-level-cache = <&L2_600>; 234 power-domains = <&CPU_PD6>; 235 power-domain-names = "psci"; 236 qcom,freq-domain = <&cpufreq_hw 1>; 237 operating-points-v2 = <&cpu4_opp_table>; 238 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 239 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 240 #cooling-cells = <2>; 241 L2_600: l2-cache { 242 compatible = "cache"; 243 next-level-cache = <&L3_0>; 244 }; 245 }; 246 247 CPU7: cpu@700 { 248 device_type = "cpu"; 249 compatible = "qcom,kryo485"; 250 reg = <0x0 0x700>; 251 enable-method = "psci"; 252 capacity-dmips-mhz = <1024>; 253 dynamic-power-coefficient = <444>; 254 next-level-cache = <&L2_700>; 255 power-domains = <&CPU_PD7>; 256 power-domain-names = "psci"; 257 qcom,freq-domain = <&cpufreq_hw 2>; 258 operating-points-v2 = <&cpu7_opp_table>; 259 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 260 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 261 #cooling-cells = <2>; 262 L2_700: l2-cache { 263 compatible = "cache"; 264 next-level-cache = <&L3_0>; 265 }; 266 }; 267 268 cpu-map { 269 cluster0 { 270 core0 { 271 cpu = <&CPU0>; 272 }; 273 274 core1 { 275 cpu = <&CPU1>; 276 }; 277 278 core2 { 279 cpu = <&CPU2>; 280 }; 281 282 core3 { 283 cpu = <&CPU3>; 284 }; 285 286 core4 { 287 cpu = <&CPU4>; 288 }; 289 290 core5 { 291 cpu = <&CPU5>; 292 }; 293 294 core6 { 295 cpu = <&CPU6>; 296 }; 297 298 core7 { 299 cpu = <&CPU7>; 300 }; 301 }; 302 }; 303 304 idle-states { 305 entry-method = "psci"; 306 307 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 308 compatible = "arm,idle-state"; 309 idle-state-name = "silver-rail-power-collapse"; 310 arm,psci-suspend-param = <0x40000004>; 311 entry-latency-us = <360>; 312 exit-latency-us = <531>; 313 min-residency-us = <3934>; 314 local-timer-stop; 315 }; 316 317 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 318 compatible = "arm,idle-state"; 319 idle-state-name = "gold-rail-power-collapse"; 320 arm,psci-suspend-param = <0x40000004>; 321 entry-latency-us = <702>; 322 exit-latency-us = <1061>; 323 min-residency-us = <4488>; 324 local-timer-stop; 325 }; 326 }; 327 328 domain-idle-states { 329 CLUSTER_SLEEP_0: cluster-sleep-0 { 330 compatible = "domain-idle-state"; 331 idle-state-name = "cluster-llcc-off"; 332 arm,psci-suspend-param = <0x4100c244>; 333 entry-latency-us = <3264>; 334 exit-latency-us = <6562>; 335 min-residency-us = <9987>; 336 local-timer-stop; 337 status = "disabled"; 338 }; 339 }; 340 }; 341 342 cpu0_opp_table: opp-table-cpu0 { 343 compatible = "operating-points-v2"; 344 opp-shared; 345 346 cpu0_opp1: opp-300000000 { 347 opp-hz = /bits/ 64 <300000000>; 348 opp-peak-kBps = <800000 9600000>; 349 }; 350 351 cpu0_opp2: opp-403200000 { 352 opp-hz = /bits/ 64 <403200000>; 353 opp-peak-kBps = <800000 9600000>; 354 }; 355 356 cpu0_opp3: opp-518400000 { 357 opp-hz = /bits/ 64 <518400000>; 358 opp-peak-kBps = <800000 16588800>; 359 }; 360 361 cpu0_opp4: opp-614400000 { 362 opp-hz = /bits/ 64 <614400000>; 363 opp-peak-kBps = <800000 16588800>; 364 }; 365 366 cpu0_opp5: opp-691200000 { 367 opp-hz = /bits/ 64 <691200000>; 368 opp-peak-kBps = <800000 19660800>; 369 }; 370 371 cpu0_opp6: opp-787200000 { 372 opp-hz = /bits/ 64 <787200000>; 373 opp-peak-kBps = <1804000 19660800>; 374 }; 375 376 cpu0_opp7: opp-883200000 { 377 opp-hz = /bits/ 64 <883200000>; 378 opp-peak-kBps = <1804000 23347200>; 379 }; 380 381 cpu0_opp8: opp-979200000 { 382 opp-hz = /bits/ 64 <979200000>; 383 opp-peak-kBps = <1804000 26419200>; 384 }; 385 386 cpu0_opp9: opp-1075200000 { 387 opp-hz = /bits/ 64 <1075200000>; 388 opp-peak-kBps = <1804000 29491200>; 389 }; 390 391 cpu0_opp10: opp-1171200000 { 392 opp-hz = /bits/ 64 <1171200000>; 393 opp-peak-kBps = <1804000 32563200>; 394 }; 395 396 cpu0_opp11: opp-1248000000 { 397 opp-hz = /bits/ 64 <1248000000>; 398 opp-peak-kBps = <1804000 36249600>; 399 }; 400 401 cpu0_opp12: opp-1344000000 { 402 opp-hz = /bits/ 64 <1344000000>; 403 opp-peak-kBps = <2188000 36249600>; 404 }; 405 406 cpu0_opp13: opp-1420800000 { 407 opp-hz = /bits/ 64 <1420800000>; 408 opp-peak-kBps = <2188000 39321600>; 409 }; 410 411 cpu0_opp14: opp-1516800000 { 412 opp-hz = /bits/ 64 <1516800000>; 413 opp-peak-kBps = <3072000 42393600>; 414 }; 415 416 cpu0_opp15: opp-1612800000 { 417 opp-hz = /bits/ 64 <1612800000>; 418 opp-peak-kBps = <3072000 42393600>; 419 }; 420 421 cpu0_opp16: opp-1708800000 { 422 opp-hz = /bits/ 64 <1708800000>; 423 opp-peak-kBps = <4068000 42393600>; 424 }; 425 426 cpu0_opp17: opp-1804800000 { 427 opp-hz = /bits/ 64 <1804800000>; 428 opp-peak-kBps = <4068000 42393600>; 429 }; 430 }; 431 432 cpu4_opp_table: opp-table-cpu4 { 433 compatible = "operating-points-v2"; 434 opp-shared; 435 436 cpu4_opp1: opp-710400000 { 437 opp-hz = /bits/ 64 <710400000>; 438 opp-peak-kBps = <1804000 19660800>; 439 }; 440 441 cpu4_opp2: opp-825600000 { 442 opp-hz = /bits/ 64 <825600000>; 443 opp-peak-kBps = <2188000 23347200>; 444 }; 445 446 cpu4_opp3: opp-940800000 { 447 opp-hz = /bits/ 64 <940800000>; 448 opp-peak-kBps = <2188000 26419200>; 449 }; 450 451 cpu4_opp4: opp-1056000000 { 452 opp-hz = /bits/ 64 <1056000000>; 453 opp-peak-kBps = <3072000 26419200>; 454 }; 455 456 cpu4_opp5: opp-1171200000 { 457 opp-hz = /bits/ 64 <1171200000>; 458 opp-peak-kBps = <3072000 29491200>; 459 }; 460 461 cpu4_opp6: opp-1286400000 { 462 opp-hz = /bits/ 64 <1286400000>; 463 opp-peak-kBps = <4068000 29491200>; 464 }; 465 466 cpu4_opp7: opp-1382400000 { 467 opp-hz = /bits/ 64 <1382400000>; 468 opp-peak-kBps = <4068000 32563200>; 469 }; 470 471 cpu4_opp8: opp-1478400000 { 472 opp-hz = /bits/ 64 <1478400000>; 473 opp-peak-kBps = <4068000 32563200>; 474 }; 475 476 cpu4_opp9: opp-1574400000 { 477 opp-hz = /bits/ 64 <1574400000>; 478 opp-peak-kBps = <5412000 39321600>; 479 }; 480 481 cpu4_opp10: opp-1670400000 { 482 opp-hz = /bits/ 64 <1670400000>; 483 opp-peak-kBps = <5412000 42393600>; 484 }; 485 486 cpu4_opp11: opp-1766400000 { 487 opp-hz = /bits/ 64 <1766400000>; 488 opp-peak-kBps = <5412000 45465600>; 489 }; 490 491 cpu4_opp12: opp-1862400000 { 492 opp-hz = /bits/ 64 <1862400000>; 493 opp-peak-kBps = <6220000 45465600>; 494 }; 495 496 cpu4_opp13: opp-1958400000 { 497 opp-hz = /bits/ 64 <1958400000>; 498 opp-peak-kBps = <6220000 48537600>; 499 }; 500 501 cpu4_opp14: opp-2054400000 { 502 opp-hz = /bits/ 64 <2054400000>; 503 opp-peak-kBps = <7216000 48537600>; 504 }; 505 506 cpu4_opp15: opp-2150400000 { 507 opp-hz = /bits/ 64 <2150400000>; 508 opp-peak-kBps = <7216000 51609600>; 509 }; 510 511 cpu4_opp16: opp-2246400000 { 512 opp-hz = /bits/ 64 <2246400000>; 513 opp-peak-kBps = <7216000 51609600>; 514 }; 515 516 cpu4_opp17: opp-2342400000 { 517 opp-hz = /bits/ 64 <2342400000>; 518 opp-peak-kBps = <8368000 51609600>; 519 }; 520 521 cpu4_opp18: opp-2419200000 { 522 opp-hz = /bits/ 64 <2419200000>; 523 opp-peak-kBps = <8368000 51609600>; 524 }; 525 }; 526 527 cpu7_opp_table: opp-table-cpu7 { 528 compatible = "operating-points-v2"; 529 opp-shared; 530 531 cpu7_opp1: opp-844800000 { 532 opp-hz = /bits/ 64 <844800000>; 533 opp-peak-kBps = <2188000 19660800>; 534 }; 535 536 cpu7_opp2: opp-960000000 { 537 opp-hz = /bits/ 64 <960000000>; 538 opp-peak-kBps = <2188000 26419200>; 539 }; 540 541 cpu7_opp3: opp-1075200000 { 542 opp-hz = /bits/ 64 <1075200000>; 543 opp-peak-kBps = <3072000 26419200>; 544 }; 545 546 cpu7_opp4: opp-1190400000 { 547 opp-hz = /bits/ 64 <1190400000>; 548 opp-peak-kBps = <3072000 29491200>; 549 }; 550 551 cpu7_opp5: opp-1305600000 { 552 opp-hz = /bits/ 64 <1305600000>; 553 opp-peak-kBps = <4068000 32563200>; 554 }; 555 556 cpu7_opp6: opp-1401600000 { 557 opp-hz = /bits/ 64 <1401600000>; 558 opp-peak-kBps = <4068000 32563200>; 559 }; 560 561 cpu7_opp7: opp-1516800000 { 562 opp-hz = /bits/ 64 <1516800000>; 563 opp-peak-kBps = <4068000 36249600>; 564 }; 565 566 cpu7_opp8: opp-1632000000 { 567 opp-hz = /bits/ 64 <1632000000>; 568 opp-peak-kBps = <5412000 39321600>; 569 }; 570 571 cpu7_opp9: opp-1747200000 { 572 opp-hz = /bits/ 64 <1708800000>; 573 opp-peak-kBps = <5412000 42393600>; 574 }; 575 576 cpu7_opp10: opp-1862400000 { 577 opp-hz = /bits/ 64 <1862400000>; 578 opp-peak-kBps = <6220000 45465600>; 579 }; 580 581 cpu7_opp11: opp-1977600000 { 582 opp-hz = /bits/ 64 <1977600000>; 583 opp-peak-kBps = <6220000 48537600>; 584 }; 585 586 cpu7_opp12: opp-2073600000 { 587 opp-hz = /bits/ 64 <2073600000>; 588 opp-peak-kBps = <7216000 48537600>; 589 }; 590 591 cpu7_opp13: opp-2169600000 { 592 opp-hz = /bits/ 64 <2169600000>; 593 opp-peak-kBps = <7216000 51609600>; 594 }; 595 596 cpu7_opp14: opp-2265600000 { 597 opp-hz = /bits/ 64 <2265600000>; 598 opp-peak-kBps = <7216000 51609600>; 599 }; 600 601 cpu7_opp15: opp-2361600000 { 602 opp-hz = /bits/ 64 <2361600000>; 603 opp-peak-kBps = <8368000 51609600>; 604 }; 605 606 cpu7_opp16: opp-2457600000 { 607 opp-hz = /bits/ 64 <2457600000>; 608 opp-peak-kBps = <8368000 51609600>; 609 }; 610 611 cpu7_opp17: opp-2553600000 { 612 opp-hz = /bits/ 64 <2553600000>; 613 opp-peak-kBps = <8368000 51609600>; 614 }; 615 616 cpu7_opp18: opp-2649600000 { 617 opp-hz = /bits/ 64 <2649600000>; 618 opp-peak-kBps = <8368000 51609600>; 619 }; 620 621 cpu7_opp19: opp-2745600000 { 622 opp-hz = /bits/ 64 <2745600000>; 623 opp-peak-kBps = <8368000 51609600>; 624 }; 625 626 cpu7_opp20: opp-2841600000 { 627 opp-hz = /bits/ 64 <2841600000>; 628 opp-peak-kBps = <8368000 51609600>; 629 }; 630 }; 631 632 firmware { 633 scm: scm { 634 compatible = "qcom,scm-sm8250", "qcom,scm"; 635 #reset-cells = <1>; 636 }; 637 }; 638 639 memory@80000000 { 640 device_type = "memory"; 641 /* We expect the bootloader to fill in the size */ 642 reg = <0x0 0x80000000 0x0 0x0>; 643 }; 644 645 pmu { 646 compatible = "arm,armv8-pmuv3"; 647 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 648 }; 649 650 psci { 651 compatible = "arm,psci-1.0"; 652 method = "smc"; 653 654 CPU_PD0: cpu0 { 655 #power-domain-cells = <0>; 656 power-domains = <&CLUSTER_PD>; 657 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 658 }; 659 660 CPU_PD1: cpu1 { 661 #power-domain-cells = <0>; 662 power-domains = <&CLUSTER_PD>; 663 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 664 }; 665 666 CPU_PD2: cpu2 { 667 #power-domain-cells = <0>; 668 power-domains = <&CLUSTER_PD>; 669 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 670 }; 671 672 CPU_PD3: cpu3 { 673 #power-domain-cells = <0>; 674 power-domains = <&CLUSTER_PD>; 675 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 676 }; 677 678 CPU_PD4: cpu4 { 679 #power-domain-cells = <0>; 680 power-domains = <&CLUSTER_PD>; 681 domain-idle-states = <&BIG_CPU_SLEEP_0>; 682 }; 683 684 CPU_PD5: cpu5 { 685 #power-domain-cells = <0>; 686 power-domains = <&CLUSTER_PD>; 687 domain-idle-states = <&BIG_CPU_SLEEP_0>; 688 }; 689 690 CPU_PD6: cpu6 { 691 #power-domain-cells = <0>; 692 power-domains = <&CLUSTER_PD>; 693 domain-idle-states = <&BIG_CPU_SLEEP_0>; 694 }; 695 696 CPU_PD7: cpu7 { 697 #power-domain-cells = <0>; 698 power-domains = <&CLUSTER_PD>; 699 domain-idle-states = <&BIG_CPU_SLEEP_0>; 700 }; 701 702 CLUSTER_PD: cpu-cluster0 { 703 #power-domain-cells = <0>; 704 domain-idle-states = <&CLUSTER_SLEEP_0>; 705 }; 706 }; 707 708 qup_opp_table: opp-table-qup { 709 compatible = "operating-points-v2"; 710 711 opp-50000000 { 712 opp-hz = /bits/ 64 <50000000>; 713 required-opps = <&rpmhpd_opp_min_svs>; 714 }; 715 716 opp-75000000 { 717 opp-hz = /bits/ 64 <75000000>; 718 required-opps = <&rpmhpd_opp_low_svs>; 719 }; 720 721 opp-120000000 { 722 opp-hz = /bits/ 64 <120000000>; 723 required-opps = <&rpmhpd_opp_svs>; 724 }; 725 }; 726 727 reserved-memory { 728 #address-cells = <2>; 729 #size-cells = <2>; 730 ranges; 731 732 hyp_mem: memory@80000000 { 733 reg = <0x0 0x80000000 0x0 0x600000>; 734 no-map; 735 }; 736 737 xbl_aop_mem: memory@80700000 { 738 reg = <0x0 0x80700000 0x0 0x160000>; 739 no-map; 740 }; 741 742 cmd_db: memory@80860000 { 743 compatible = "qcom,cmd-db"; 744 reg = <0x0 0x80860000 0x0 0x20000>; 745 no-map; 746 }; 747 748 smem_mem: memory@80900000 { 749 reg = <0x0 0x80900000 0x0 0x200000>; 750 no-map; 751 }; 752 753 removed_mem: memory@80b00000 { 754 reg = <0x0 0x80b00000 0x0 0x5300000>; 755 no-map; 756 }; 757 758 camera_mem: memory@86200000 { 759 reg = <0x0 0x86200000 0x0 0x500000>; 760 no-map; 761 }; 762 763 wlan_mem: memory@86700000 { 764 reg = <0x0 0x86700000 0x0 0x100000>; 765 no-map; 766 }; 767 768 ipa_fw_mem: memory@86800000 { 769 reg = <0x0 0x86800000 0x0 0x10000>; 770 no-map; 771 }; 772 773 ipa_gsi_mem: memory@86810000 { 774 reg = <0x0 0x86810000 0x0 0xa000>; 775 no-map; 776 }; 777 778 gpu_mem: memory@8681a000 { 779 reg = <0x0 0x8681a000 0x0 0x2000>; 780 no-map; 781 }; 782 783 npu_mem: memory@86900000 { 784 reg = <0x0 0x86900000 0x0 0x500000>; 785 no-map; 786 }; 787 788 video_mem: memory@86e00000 { 789 reg = <0x0 0x86e00000 0x0 0x500000>; 790 no-map; 791 }; 792 793 cvp_mem: memory@87300000 { 794 reg = <0x0 0x87300000 0x0 0x500000>; 795 no-map; 796 }; 797 798 cdsp_mem: memory@87800000 { 799 reg = <0x0 0x87800000 0x0 0x1400000>; 800 no-map; 801 }; 802 803 slpi_mem: memory@88c00000 { 804 reg = <0x0 0x88c00000 0x0 0x1500000>; 805 no-map; 806 }; 807 808 adsp_mem: memory@8a100000 { 809 reg = <0x0 0x8a100000 0x0 0x1d00000>; 810 no-map; 811 }; 812 813 spss_mem: memory@8be00000 { 814 reg = <0x0 0x8be00000 0x0 0x100000>; 815 no-map; 816 }; 817 818 cdsp_secure_heap: memory@8bf00000 { 819 reg = <0x0 0x8bf00000 0x0 0x4600000>; 820 no-map; 821 }; 822 }; 823 824 smem { 825 compatible = "qcom,smem"; 826 memory-region = <&smem_mem>; 827 hwlocks = <&tcsr_mutex 3>; 828 }; 829 830 smp2p-adsp { 831 compatible = "qcom,smp2p"; 832 qcom,smem = <443>, <429>; 833 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 834 IPCC_MPROC_SIGNAL_SMP2P 835 IRQ_TYPE_EDGE_RISING>; 836 mboxes = <&ipcc IPCC_CLIENT_LPASS 837 IPCC_MPROC_SIGNAL_SMP2P>; 838 839 qcom,local-pid = <0>; 840 qcom,remote-pid = <2>; 841 842 smp2p_adsp_out: master-kernel { 843 qcom,entry-name = "master-kernel"; 844 #qcom,smem-state-cells = <1>; 845 }; 846 847 smp2p_adsp_in: slave-kernel { 848 qcom,entry-name = "slave-kernel"; 849 interrupt-controller; 850 #interrupt-cells = <2>; 851 }; 852 }; 853 854 smp2p-cdsp { 855 compatible = "qcom,smp2p"; 856 qcom,smem = <94>, <432>; 857 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 858 IPCC_MPROC_SIGNAL_SMP2P 859 IRQ_TYPE_EDGE_RISING>; 860 mboxes = <&ipcc IPCC_CLIENT_CDSP 861 IPCC_MPROC_SIGNAL_SMP2P>; 862 863 qcom,local-pid = <0>; 864 qcom,remote-pid = <5>; 865 866 smp2p_cdsp_out: master-kernel { 867 qcom,entry-name = "master-kernel"; 868 #qcom,smem-state-cells = <1>; 869 }; 870 871 smp2p_cdsp_in: slave-kernel { 872 qcom,entry-name = "slave-kernel"; 873 interrupt-controller; 874 #interrupt-cells = <2>; 875 }; 876 }; 877 878 smp2p-slpi { 879 compatible = "qcom,smp2p"; 880 qcom,smem = <481>, <430>; 881 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 882 IPCC_MPROC_SIGNAL_SMP2P 883 IRQ_TYPE_EDGE_RISING>; 884 mboxes = <&ipcc IPCC_CLIENT_SLPI 885 IPCC_MPROC_SIGNAL_SMP2P>; 886 887 qcom,local-pid = <0>; 888 qcom,remote-pid = <3>; 889 890 smp2p_slpi_out: master-kernel { 891 qcom,entry-name = "master-kernel"; 892 #qcom,smem-state-cells = <1>; 893 }; 894 895 smp2p_slpi_in: slave-kernel { 896 qcom,entry-name = "slave-kernel"; 897 interrupt-controller; 898 #interrupt-cells = <2>; 899 }; 900 }; 901 902 soc: soc@0 { 903 #address-cells = <2>; 904 #size-cells = <2>; 905 ranges = <0 0 0 0 0x10 0>; 906 dma-ranges = <0 0 0 0 0x10 0>; 907 compatible = "simple-bus"; 908 909 gcc: clock-controller@100000 { 910 compatible = "qcom,gcc-sm8250"; 911 reg = <0x0 0x00100000 0x0 0x1f0000>; 912 #clock-cells = <1>; 913 #reset-cells = <1>; 914 #power-domain-cells = <1>; 915 clock-names = "bi_tcxo", 916 "bi_tcxo_ao", 917 "sleep_clk"; 918 clocks = <&rpmhcc RPMH_CXO_CLK>, 919 <&rpmhcc RPMH_CXO_CLK_A>, 920 <&sleep_clk>; 921 }; 922 923 ipcc: mailbox@408000 { 924 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 925 reg = <0 0x00408000 0 0x1000>; 926 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 927 interrupt-controller; 928 #interrupt-cells = <3>; 929 #mbox-cells = <2>; 930 }; 931 932 rng: rng@793000 { 933 compatible = "qcom,prng-ee"; 934 reg = <0 0x00793000 0 0x1000>; 935 clocks = <&gcc GCC_PRNG_AHB_CLK>; 936 clock-names = "core"; 937 }; 938 939 gpi_dma2: dma-controller@800000 { 940 compatible = "qcom,sm8250-gpi-dma"; 941 reg = <0 0x00800000 0 0x70000>; 942 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 952 dma-channels = <10>; 953 dma-channel-mask = <0x3f>; 954 iommus = <&apps_smmu 0x76 0x0>; 955 #dma-cells = <3>; 956 status = "disabled"; 957 }; 958 959 qupv3_id_2: geniqup@8c0000 { 960 compatible = "qcom,geni-se-qup"; 961 reg = <0x0 0x008c0000 0x0 0x6000>; 962 clock-names = "m-ahb", "s-ahb"; 963 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 964 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 965 #address-cells = <2>; 966 #size-cells = <2>; 967 iommus = <&apps_smmu 0x63 0x0>; 968 ranges; 969 status = "disabled"; 970 971 i2c14: i2c@880000 { 972 compatible = "qcom,geni-i2c"; 973 reg = <0 0x00880000 0 0x4000>; 974 clock-names = "se"; 975 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 976 pinctrl-names = "default"; 977 pinctrl-0 = <&qup_i2c14_default>; 978 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 979 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 980 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 981 dma-names = "tx", "rx"; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 status = "disabled"; 985 }; 986 987 spi14: spi@880000 { 988 compatible = "qcom,geni-spi"; 989 reg = <0 0x00880000 0 0x4000>; 990 clock-names = "se"; 991 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 992 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 993 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 994 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 995 dma-names = "tx", "rx"; 996 power-domains = <&rpmhpd SM8250_CX>; 997 operating-points-v2 = <&qup_opp_table>; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 status = "disabled"; 1001 }; 1002 1003 i2c15: i2c@884000 { 1004 compatible = "qcom,geni-i2c"; 1005 reg = <0 0x00884000 0 0x4000>; 1006 clock-names = "se"; 1007 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1008 pinctrl-names = "default"; 1009 pinctrl-0 = <&qup_i2c15_default>; 1010 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1011 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1012 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1013 dma-names = "tx", "rx"; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 status = "disabled"; 1017 }; 1018 1019 spi15: spi@884000 { 1020 compatible = "qcom,geni-spi"; 1021 reg = <0 0x00884000 0 0x4000>; 1022 clock-names = "se"; 1023 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1024 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1025 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1026 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1027 dma-names = "tx", "rx"; 1028 power-domains = <&rpmhpd SM8250_CX>; 1029 operating-points-v2 = <&qup_opp_table>; 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 status = "disabled"; 1033 }; 1034 1035 i2c16: i2c@888000 { 1036 compatible = "qcom,geni-i2c"; 1037 reg = <0 0x00888000 0 0x4000>; 1038 clock-names = "se"; 1039 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1040 pinctrl-names = "default"; 1041 pinctrl-0 = <&qup_i2c16_default>; 1042 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1043 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1044 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1045 dma-names = "tx", "rx"; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 status = "disabled"; 1049 }; 1050 1051 spi16: spi@888000 { 1052 compatible = "qcom,geni-spi"; 1053 reg = <0 0x00888000 0 0x4000>; 1054 clock-names = "se"; 1055 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1056 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1057 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1058 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1059 dma-names = "tx", "rx"; 1060 power-domains = <&rpmhpd SM8250_CX>; 1061 operating-points-v2 = <&qup_opp_table>; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 status = "disabled"; 1065 }; 1066 1067 i2c17: i2c@88c000 { 1068 compatible = "qcom,geni-i2c"; 1069 reg = <0 0x0088c000 0 0x4000>; 1070 clock-names = "se"; 1071 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1072 pinctrl-names = "default"; 1073 pinctrl-0 = <&qup_i2c17_default>; 1074 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1075 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1076 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1077 dma-names = "tx", "rx"; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 status = "disabled"; 1081 }; 1082 1083 spi17: spi@88c000 { 1084 compatible = "qcom,geni-spi"; 1085 reg = <0 0x0088c000 0 0x4000>; 1086 clock-names = "se"; 1087 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1088 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1089 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1090 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1091 dma-names = "tx", "rx"; 1092 power-domains = <&rpmhpd SM8250_CX>; 1093 operating-points-v2 = <&qup_opp_table>; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 status = "disabled"; 1097 }; 1098 1099 uart17: serial@88c000 { 1100 compatible = "qcom,geni-uart"; 1101 reg = <0 0x0088c000 0 0x4000>; 1102 clock-names = "se"; 1103 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1104 pinctrl-names = "default"; 1105 pinctrl-0 = <&qup_uart17_default>; 1106 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1107 power-domains = <&rpmhpd SM8250_CX>; 1108 operating-points-v2 = <&qup_opp_table>; 1109 status = "disabled"; 1110 }; 1111 1112 i2c18: i2c@890000 { 1113 compatible = "qcom,geni-i2c"; 1114 reg = <0 0x00890000 0 0x4000>; 1115 clock-names = "se"; 1116 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&qup_i2c18_default>; 1119 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1120 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1121 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1122 dma-names = "tx", "rx"; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 status = "disabled"; 1126 }; 1127 1128 spi18: spi@890000 { 1129 compatible = "qcom,geni-spi"; 1130 reg = <0 0x00890000 0 0x4000>; 1131 clock-names = "se"; 1132 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1133 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1134 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1135 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1136 dma-names = "tx", "rx"; 1137 power-domains = <&rpmhpd SM8250_CX>; 1138 operating-points-v2 = <&qup_opp_table>; 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 status = "disabled"; 1142 }; 1143 1144 uart18: serial@890000 { 1145 compatible = "qcom,geni-uart"; 1146 reg = <0 0x00890000 0 0x4000>; 1147 clock-names = "se"; 1148 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1149 pinctrl-names = "default"; 1150 pinctrl-0 = <&qup_uart18_default>; 1151 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1152 power-domains = <&rpmhpd SM8250_CX>; 1153 operating-points-v2 = <&qup_opp_table>; 1154 status = "disabled"; 1155 }; 1156 1157 i2c19: i2c@894000 { 1158 compatible = "qcom,geni-i2c"; 1159 reg = <0 0x00894000 0 0x4000>; 1160 clock-names = "se"; 1161 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&qup_i2c19_default>; 1164 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1165 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1166 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1167 dma-names = "tx", "rx"; 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 status = "disabled"; 1171 }; 1172 1173 spi19: spi@894000 { 1174 compatible = "qcom,geni-spi"; 1175 reg = <0 0x00894000 0 0x4000>; 1176 clock-names = "se"; 1177 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1178 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1179 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1180 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1181 dma-names = "tx", "rx"; 1182 power-domains = <&rpmhpd SM8250_CX>; 1183 operating-points-v2 = <&qup_opp_table>; 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 status = "disabled"; 1187 }; 1188 }; 1189 1190 gpi_dma0: dma-controller@900000 { 1191 compatible = "qcom,sm8250-gpi-dma"; 1192 reg = <0 0x00900000 0 0x70000>; 1193 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1206 dma-channels = <15>; 1207 dma-channel-mask = <0x7ff>; 1208 iommus = <&apps_smmu 0x5b6 0x0>; 1209 #dma-cells = <3>; 1210 status = "disabled"; 1211 }; 1212 1213 qupv3_id_0: geniqup@9c0000 { 1214 compatible = "qcom,geni-se-qup"; 1215 reg = <0x0 0x009c0000 0x0 0x6000>; 1216 clock-names = "m-ahb", "s-ahb"; 1217 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1218 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1219 #address-cells = <2>; 1220 #size-cells = <2>; 1221 iommus = <&apps_smmu 0x5a3 0x0>; 1222 ranges; 1223 status = "disabled"; 1224 1225 i2c0: i2c@980000 { 1226 compatible = "qcom,geni-i2c"; 1227 reg = <0 0x00980000 0 0x4000>; 1228 clock-names = "se"; 1229 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1230 pinctrl-names = "default"; 1231 pinctrl-0 = <&qup_i2c0_default>; 1232 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1233 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1234 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1235 dma-names = "tx", "rx"; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 status = "disabled"; 1239 }; 1240 1241 spi0: spi@980000 { 1242 compatible = "qcom,geni-spi"; 1243 reg = <0 0x00980000 0 0x4000>; 1244 clock-names = "se"; 1245 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1246 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1247 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1248 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1249 dma-names = "tx", "rx"; 1250 power-domains = <&rpmhpd SM8250_CX>; 1251 operating-points-v2 = <&qup_opp_table>; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 status = "disabled"; 1255 }; 1256 1257 i2c1: i2c@984000 { 1258 compatible = "qcom,geni-i2c"; 1259 reg = <0 0x00984000 0 0x4000>; 1260 clock-names = "se"; 1261 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1262 pinctrl-names = "default"; 1263 pinctrl-0 = <&qup_i2c1_default>; 1264 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1265 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1266 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1267 dma-names = "tx", "rx"; 1268 #address-cells = <1>; 1269 #size-cells = <0>; 1270 status = "disabled"; 1271 }; 1272 1273 spi1: spi@984000 { 1274 compatible = "qcom,geni-spi"; 1275 reg = <0 0x00984000 0 0x4000>; 1276 clock-names = "se"; 1277 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1278 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1279 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1280 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1281 dma-names = "tx", "rx"; 1282 power-domains = <&rpmhpd SM8250_CX>; 1283 operating-points-v2 = <&qup_opp_table>; 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 status = "disabled"; 1287 }; 1288 1289 i2c2: i2c@988000 { 1290 compatible = "qcom,geni-i2c"; 1291 reg = <0 0x00988000 0 0x4000>; 1292 clock-names = "se"; 1293 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1294 pinctrl-names = "default"; 1295 pinctrl-0 = <&qup_i2c2_default>; 1296 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1297 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1298 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1299 dma-names = "tx", "rx"; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 status = "disabled"; 1303 }; 1304 1305 spi2: spi@988000 { 1306 compatible = "qcom,geni-spi"; 1307 reg = <0 0x00988000 0 0x4000>; 1308 clock-names = "se"; 1309 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1310 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1311 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1312 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1313 dma-names = "tx", "rx"; 1314 power-domains = <&rpmhpd SM8250_CX>; 1315 operating-points-v2 = <&qup_opp_table>; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 status = "disabled"; 1319 }; 1320 1321 uart2: serial@988000 { 1322 compatible = "qcom,geni-debug-uart"; 1323 reg = <0 0x00988000 0 0x4000>; 1324 clock-names = "se"; 1325 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1326 pinctrl-names = "default"; 1327 pinctrl-0 = <&qup_uart2_default>; 1328 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1329 power-domains = <&rpmhpd SM8250_CX>; 1330 operating-points-v2 = <&qup_opp_table>; 1331 status = "disabled"; 1332 }; 1333 1334 i2c3: i2c@98c000 { 1335 compatible = "qcom,geni-i2c"; 1336 reg = <0 0x0098c000 0 0x4000>; 1337 clock-names = "se"; 1338 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1339 pinctrl-names = "default"; 1340 pinctrl-0 = <&qup_i2c3_default>; 1341 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1342 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1343 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1344 dma-names = "tx", "rx"; 1345 #address-cells = <1>; 1346 #size-cells = <0>; 1347 status = "disabled"; 1348 }; 1349 1350 spi3: spi@98c000 { 1351 compatible = "qcom,geni-spi"; 1352 reg = <0 0x0098c000 0 0x4000>; 1353 clock-names = "se"; 1354 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1355 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1356 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1357 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1358 dma-names = "tx", "rx"; 1359 power-domains = <&rpmhpd SM8250_CX>; 1360 operating-points-v2 = <&qup_opp_table>; 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 status = "disabled"; 1364 }; 1365 1366 i2c4: i2c@990000 { 1367 compatible = "qcom,geni-i2c"; 1368 reg = <0 0x00990000 0 0x4000>; 1369 clock-names = "se"; 1370 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1371 pinctrl-names = "default"; 1372 pinctrl-0 = <&qup_i2c4_default>; 1373 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1374 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1375 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1376 dma-names = "tx", "rx"; 1377 #address-cells = <1>; 1378 #size-cells = <0>; 1379 status = "disabled"; 1380 }; 1381 1382 spi4: spi@990000 { 1383 compatible = "qcom,geni-spi"; 1384 reg = <0 0x00990000 0 0x4000>; 1385 clock-names = "se"; 1386 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1387 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1388 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1389 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1390 dma-names = "tx", "rx"; 1391 power-domains = <&rpmhpd SM8250_CX>; 1392 operating-points-v2 = <&qup_opp_table>; 1393 #address-cells = <1>; 1394 #size-cells = <0>; 1395 status = "disabled"; 1396 }; 1397 1398 i2c5: i2c@994000 { 1399 compatible = "qcom,geni-i2c"; 1400 reg = <0 0x00994000 0 0x4000>; 1401 clock-names = "se"; 1402 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1403 pinctrl-names = "default"; 1404 pinctrl-0 = <&qup_i2c5_default>; 1405 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1406 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1407 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1408 dma-names = "tx", "rx"; 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 status = "disabled"; 1412 }; 1413 1414 spi5: spi@994000 { 1415 compatible = "qcom,geni-spi"; 1416 reg = <0 0x00994000 0 0x4000>; 1417 clock-names = "se"; 1418 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1419 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1420 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1421 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1422 dma-names = "tx", "rx"; 1423 power-domains = <&rpmhpd SM8250_CX>; 1424 operating-points-v2 = <&qup_opp_table>; 1425 #address-cells = <1>; 1426 #size-cells = <0>; 1427 status = "disabled"; 1428 }; 1429 1430 i2c6: i2c@998000 { 1431 compatible = "qcom,geni-i2c"; 1432 reg = <0 0x00998000 0 0x4000>; 1433 clock-names = "se"; 1434 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&qup_i2c6_default>; 1437 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1438 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1439 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1440 dma-names = "tx", "rx"; 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 status = "disabled"; 1444 }; 1445 1446 spi6: spi@998000 { 1447 compatible = "qcom,geni-spi"; 1448 reg = <0 0x00998000 0 0x4000>; 1449 clock-names = "se"; 1450 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1451 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1452 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1453 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1454 dma-names = "tx", "rx"; 1455 power-domains = <&rpmhpd SM8250_CX>; 1456 operating-points-v2 = <&qup_opp_table>; 1457 #address-cells = <1>; 1458 #size-cells = <0>; 1459 status = "disabled"; 1460 }; 1461 1462 uart6: serial@998000 { 1463 compatible = "qcom,geni-uart"; 1464 reg = <0 0x00998000 0 0x4000>; 1465 clock-names = "se"; 1466 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1467 pinctrl-names = "default"; 1468 pinctrl-0 = <&qup_uart6_default>; 1469 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1470 power-domains = <&rpmhpd SM8250_CX>; 1471 operating-points-v2 = <&qup_opp_table>; 1472 status = "disabled"; 1473 }; 1474 1475 i2c7: i2c@99c000 { 1476 compatible = "qcom,geni-i2c"; 1477 reg = <0 0x0099c000 0 0x4000>; 1478 clock-names = "se"; 1479 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1480 pinctrl-names = "default"; 1481 pinctrl-0 = <&qup_i2c7_default>; 1482 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1483 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1484 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1485 dma-names = "tx", "rx"; 1486 #address-cells = <1>; 1487 #size-cells = <0>; 1488 status = "disabled"; 1489 }; 1490 1491 spi7: spi@99c000 { 1492 compatible = "qcom,geni-spi"; 1493 reg = <0 0x0099c000 0 0x4000>; 1494 clock-names = "se"; 1495 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1496 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1497 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1498 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1499 dma-names = "tx", "rx"; 1500 power-domains = <&rpmhpd SM8250_CX>; 1501 operating-points-v2 = <&qup_opp_table>; 1502 #address-cells = <1>; 1503 #size-cells = <0>; 1504 status = "disabled"; 1505 }; 1506 }; 1507 1508 gpi_dma1: dma-controller@a00000 { 1509 compatible = "qcom,sm8250-gpi-dma"; 1510 reg = <0 0x00a00000 0 0x70000>; 1511 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1521 dma-channels = <10>; 1522 dma-channel-mask = <0x3f>; 1523 iommus = <&apps_smmu 0x56 0x0>; 1524 #dma-cells = <3>; 1525 status = "disabled"; 1526 }; 1527 1528 qupv3_id_1: geniqup@ac0000 { 1529 compatible = "qcom,geni-se-qup"; 1530 reg = <0x0 0x00ac0000 0x0 0x6000>; 1531 clock-names = "m-ahb", "s-ahb"; 1532 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1533 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1534 #address-cells = <2>; 1535 #size-cells = <2>; 1536 iommus = <&apps_smmu 0x43 0x0>; 1537 ranges; 1538 status = "disabled"; 1539 1540 i2c8: i2c@a80000 { 1541 compatible = "qcom,geni-i2c"; 1542 reg = <0 0x00a80000 0 0x4000>; 1543 clock-names = "se"; 1544 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1545 pinctrl-names = "default"; 1546 pinctrl-0 = <&qup_i2c8_default>; 1547 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1548 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1549 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1550 dma-names = "tx", "rx"; 1551 #address-cells = <1>; 1552 #size-cells = <0>; 1553 status = "disabled"; 1554 }; 1555 1556 spi8: spi@a80000 { 1557 compatible = "qcom,geni-spi"; 1558 reg = <0 0x00a80000 0 0x4000>; 1559 clock-names = "se"; 1560 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1561 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1562 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1563 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1564 dma-names = "tx", "rx"; 1565 power-domains = <&rpmhpd SM8250_CX>; 1566 operating-points-v2 = <&qup_opp_table>; 1567 #address-cells = <1>; 1568 #size-cells = <0>; 1569 status = "disabled"; 1570 }; 1571 1572 i2c9: i2c@a84000 { 1573 compatible = "qcom,geni-i2c"; 1574 reg = <0 0x00a84000 0 0x4000>; 1575 clock-names = "se"; 1576 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1577 pinctrl-names = "default"; 1578 pinctrl-0 = <&qup_i2c9_default>; 1579 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1580 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1581 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1582 dma-names = "tx", "rx"; 1583 #address-cells = <1>; 1584 #size-cells = <0>; 1585 status = "disabled"; 1586 }; 1587 1588 spi9: spi@a84000 { 1589 compatible = "qcom,geni-spi"; 1590 reg = <0 0x00a84000 0 0x4000>; 1591 clock-names = "se"; 1592 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1593 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1594 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1595 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1596 dma-names = "tx", "rx"; 1597 power-domains = <&rpmhpd SM8250_CX>; 1598 operating-points-v2 = <&qup_opp_table>; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 status = "disabled"; 1602 }; 1603 1604 i2c10: i2c@a88000 { 1605 compatible = "qcom,geni-i2c"; 1606 reg = <0 0x00a88000 0 0x4000>; 1607 clock-names = "se"; 1608 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1609 pinctrl-names = "default"; 1610 pinctrl-0 = <&qup_i2c10_default>; 1611 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1612 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1613 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1614 dma-names = "tx", "rx"; 1615 #address-cells = <1>; 1616 #size-cells = <0>; 1617 status = "disabled"; 1618 }; 1619 1620 spi10: spi@a88000 { 1621 compatible = "qcom,geni-spi"; 1622 reg = <0 0x00a88000 0 0x4000>; 1623 clock-names = "se"; 1624 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1625 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1626 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1627 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1628 dma-names = "tx", "rx"; 1629 power-domains = <&rpmhpd SM8250_CX>; 1630 operating-points-v2 = <&qup_opp_table>; 1631 #address-cells = <1>; 1632 #size-cells = <0>; 1633 status = "disabled"; 1634 }; 1635 1636 i2c11: i2c@a8c000 { 1637 compatible = "qcom,geni-i2c"; 1638 reg = <0 0x00a8c000 0 0x4000>; 1639 clock-names = "se"; 1640 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1641 pinctrl-names = "default"; 1642 pinctrl-0 = <&qup_i2c11_default>; 1643 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1644 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1645 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1646 dma-names = "tx", "rx"; 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 status = "disabled"; 1650 }; 1651 1652 spi11: spi@a8c000 { 1653 compatible = "qcom,geni-spi"; 1654 reg = <0 0x00a8c000 0 0x4000>; 1655 clock-names = "se"; 1656 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1657 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1658 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1659 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1660 dma-names = "tx", "rx"; 1661 power-domains = <&rpmhpd SM8250_CX>; 1662 operating-points-v2 = <&qup_opp_table>; 1663 #address-cells = <1>; 1664 #size-cells = <0>; 1665 status = "disabled"; 1666 }; 1667 1668 i2c12: i2c@a90000 { 1669 compatible = "qcom,geni-i2c"; 1670 reg = <0 0x00a90000 0 0x4000>; 1671 clock-names = "se"; 1672 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1673 pinctrl-names = "default"; 1674 pinctrl-0 = <&qup_i2c12_default>; 1675 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1676 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1677 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1678 dma-names = "tx", "rx"; 1679 #address-cells = <1>; 1680 #size-cells = <0>; 1681 status = "disabled"; 1682 }; 1683 1684 spi12: spi@a90000 { 1685 compatible = "qcom,geni-spi"; 1686 reg = <0 0x00a90000 0 0x4000>; 1687 clock-names = "se"; 1688 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1689 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1690 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1691 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1692 dma-names = "tx", "rx"; 1693 power-domains = <&rpmhpd SM8250_CX>; 1694 operating-points-v2 = <&qup_opp_table>; 1695 #address-cells = <1>; 1696 #size-cells = <0>; 1697 status = "disabled"; 1698 }; 1699 1700 uart12: serial@a90000 { 1701 compatible = "qcom,geni-debug-uart"; 1702 reg = <0x0 0x00a90000 0x0 0x4000>; 1703 clock-names = "se"; 1704 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1705 pinctrl-names = "default"; 1706 pinctrl-0 = <&qup_uart12_default>; 1707 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1708 power-domains = <&rpmhpd SM8250_CX>; 1709 operating-points-v2 = <&qup_opp_table>; 1710 status = "disabled"; 1711 }; 1712 1713 i2c13: i2c@a94000 { 1714 compatible = "qcom,geni-i2c"; 1715 reg = <0 0x00a94000 0 0x4000>; 1716 clock-names = "se"; 1717 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1718 pinctrl-names = "default"; 1719 pinctrl-0 = <&qup_i2c13_default>; 1720 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1721 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1722 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1723 dma-names = "tx", "rx"; 1724 #address-cells = <1>; 1725 #size-cells = <0>; 1726 status = "disabled"; 1727 }; 1728 1729 spi13: spi@a94000 { 1730 compatible = "qcom,geni-spi"; 1731 reg = <0 0x00a94000 0 0x4000>; 1732 clock-names = "se"; 1733 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1734 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1735 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1736 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1737 dma-names = "tx", "rx"; 1738 power-domains = <&rpmhpd SM8250_CX>; 1739 operating-points-v2 = <&qup_opp_table>; 1740 #address-cells = <1>; 1741 #size-cells = <0>; 1742 status = "disabled"; 1743 }; 1744 }; 1745 1746 config_noc: interconnect@1500000 { 1747 compatible = "qcom,sm8250-config-noc"; 1748 reg = <0 0x01500000 0 0xa580>; 1749 #interconnect-cells = <1>; 1750 qcom,bcm-voters = <&apps_bcm_voter>; 1751 }; 1752 1753 system_noc: interconnect@1620000 { 1754 compatible = "qcom,sm8250-system-noc"; 1755 reg = <0 0x01620000 0 0x1c200>; 1756 #interconnect-cells = <1>; 1757 qcom,bcm-voters = <&apps_bcm_voter>; 1758 }; 1759 1760 mc_virt: interconnect@163d000 { 1761 compatible = "qcom,sm8250-mc-virt"; 1762 reg = <0 0x0163d000 0 0x1000>; 1763 #interconnect-cells = <1>; 1764 qcom,bcm-voters = <&apps_bcm_voter>; 1765 }; 1766 1767 aggre1_noc: interconnect@16e0000 { 1768 compatible = "qcom,sm8250-aggre1-noc"; 1769 reg = <0 0x016e0000 0 0x1f180>; 1770 #interconnect-cells = <1>; 1771 qcom,bcm-voters = <&apps_bcm_voter>; 1772 }; 1773 1774 aggre2_noc: interconnect@1700000 { 1775 compatible = "qcom,sm8250-aggre2-noc"; 1776 reg = <0 0x01700000 0 0x33000>; 1777 #interconnect-cells = <1>; 1778 qcom,bcm-voters = <&apps_bcm_voter>; 1779 }; 1780 1781 compute_noc: interconnect@1733000 { 1782 compatible = "qcom,sm8250-compute-noc"; 1783 reg = <0 0x01733000 0 0xa180>; 1784 #interconnect-cells = <1>; 1785 qcom,bcm-voters = <&apps_bcm_voter>; 1786 }; 1787 1788 mmss_noc: interconnect@1740000 { 1789 compatible = "qcom,sm8250-mmss-noc"; 1790 reg = <0 0x01740000 0 0x1f080>; 1791 #interconnect-cells = <1>; 1792 qcom,bcm-voters = <&apps_bcm_voter>; 1793 }; 1794 1795 pcie0: pci@1c00000 { 1796 compatible = "qcom,pcie-sm8250"; 1797 reg = <0 0x01c00000 0 0x3000>, 1798 <0 0x60000000 0 0xf1d>, 1799 <0 0x60000f20 0 0xa8>, 1800 <0 0x60001000 0 0x1000>, 1801 <0 0x60100000 0 0x100000>; 1802 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1803 device_type = "pci"; 1804 linux,pci-domain = <0>; 1805 bus-range = <0x00 0xff>; 1806 num-lanes = <1>; 1807 1808 #address-cells = <3>; 1809 #size-cells = <2>; 1810 1811 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1812 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1813 1814 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1822 interrupt-names = "msi0", "msi1", "msi2", "msi3", 1823 "msi4", "msi5", "msi6", "msi7"; 1824 #interrupt-cells = <1>; 1825 interrupt-map-mask = <0 0 0 0x7>; 1826 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1827 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1828 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1829 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1830 1831 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1832 <&gcc GCC_PCIE_0_AUX_CLK>, 1833 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1834 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1835 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1836 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1837 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1838 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1839 clock-names = "pipe", 1840 "aux", 1841 "cfg", 1842 "bus_master", 1843 "bus_slave", 1844 "slave_q2a", 1845 "tbu", 1846 "ddrss_sf_tbu"; 1847 1848 iommus = <&apps_smmu 0x1c00 0x7f>; 1849 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1850 <0x100 &apps_smmu 0x1c01 0x1>; 1851 1852 resets = <&gcc GCC_PCIE_0_BCR>; 1853 reset-names = "pci"; 1854 1855 power-domains = <&gcc PCIE_0_GDSC>; 1856 1857 phys = <&pcie0_lane>; 1858 phy-names = "pciephy"; 1859 1860 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; 1861 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 1862 1863 pinctrl-names = "default"; 1864 pinctrl-0 = <&pcie0_default_state>; 1865 1866 status = "disabled"; 1867 }; 1868 1869 pcie0_phy: phy@1c06000 { 1870 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1871 reg = <0 0x01c06000 0 0x1c0>; 1872 #address-cells = <2>; 1873 #size-cells = <2>; 1874 ranges; 1875 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1876 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1877 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1878 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1879 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1880 1881 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1882 reset-names = "phy"; 1883 1884 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1885 assigned-clock-rates = <100000000>; 1886 1887 status = "disabled"; 1888 1889 pcie0_lane: phy@1c06200 { 1890 reg = <0 0x1c06200 0 0x170>, /* tx */ 1891 <0 0x1c06400 0 0x200>, /* rx */ 1892 <0 0x1c06800 0 0x1f0>, /* pcs */ 1893 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1894 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1895 clock-names = "pipe0"; 1896 1897 #phy-cells = <0>; 1898 1899 #clock-cells = <0>; 1900 clock-output-names = "pcie_0_pipe_clk"; 1901 }; 1902 }; 1903 1904 pcie1: pci@1c08000 { 1905 compatible = "qcom,pcie-sm8250"; 1906 reg = <0 0x01c08000 0 0x3000>, 1907 <0 0x40000000 0 0xf1d>, 1908 <0 0x40000f20 0 0xa8>, 1909 <0 0x40001000 0 0x1000>, 1910 <0 0x40100000 0 0x100000>; 1911 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1912 device_type = "pci"; 1913 linux,pci-domain = <1>; 1914 bus-range = <0x00 0xff>; 1915 num-lanes = <2>; 1916 1917 #address-cells = <3>; 1918 #size-cells = <2>; 1919 1920 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1921 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1922 1923 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1924 interrupt-names = "msi"; 1925 #interrupt-cells = <1>; 1926 interrupt-map-mask = <0 0 0 0x7>; 1927 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1928 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1929 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1930 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1931 1932 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1933 <&gcc GCC_PCIE_1_AUX_CLK>, 1934 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1935 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1936 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1937 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1938 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1939 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1940 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1941 clock-names = "pipe", 1942 "aux", 1943 "cfg", 1944 "bus_master", 1945 "bus_slave", 1946 "slave_q2a", 1947 "ref", 1948 "tbu", 1949 "ddrss_sf_tbu"; 1950 1951 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1952 assigned-clock-rates = <19200000>; 1953 1954 iommus = <&apps_smmu 0x1c80 0x7f>; 1955 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1956 <0x100 &apps_smmu 0x1c81 0x1>; 1957 1958 resets = <&gcc GCC_PCIE_1_BCR>; 1959 reset-names = "pci"; 1960 1961 power-domains = <&gcc PCIE_1_GDSC>; 1962 1963 phys = <&pcie1_lane>; 1964 phy-names = "pciephy"; 1965 1966 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; 1967 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; 1968 1969 pinctrl-names = "default"; 1970 pinctrl-0 = <&pcie1_default_state>; 1971 1972 status = "disabled"; 1973 }; 1974 1975 pcie1_phy: phy@1c0e000 { 1976 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1977 reg = <0 0x01c0e000 0 0x1c0>; 1978 #address-cells = <2>; 1979 #size-cells = <2>; 1980 ranges; 1981 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1982 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1983 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1984 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1985 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1986 1987 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1988 reset-names = "phy"; 1989 1990 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1991 assigned-clock-rates = <100000000>; 1992 1993 status = "disabled"; 1994 1995 pcie1_lane: phy@1c0e200 { 1996 reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1997 <0 0x1c0e400 0 0x200>, /* rx0 */ 1998 <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1999 <0 0x1c0e600 0 0x170>, /* tx1 */ 2000 <0 0x1c0e800 0 0x200>, /* rx1 */ 2001 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2002 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2003 clock-names = "pipe0"; 2004 2005 #phy-cells = <0>; 2006 2007 #clock-cells = <0>; 2008 clock-output-names = "pcie_1_pipe_clk"; 2009 }; 2010 }; 2011 2012 pcie2: pci@1c10000 { 2013 compatible = "qcom,pcie-sm8250"; 2014 reg = <0 0x01c10000 0 0x3000>, 2015 <0 0x64000000 0 0xf1d>, 2016 <0 0x64000f20 0 0xa8>, 2017 <0 0x64001000 0 0x1000>, 2018 <0 0x64100000 0 0x100000>; 2019 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2020 device_type = "pci"; 2021 linux,pci-domain = <2>; 2022 bus-range = <0x00 0xff>; 2023 num-lanes = <2>; 2024 2025 #address-cells = <3>; 2026 #size-cells = <2>; 2027 2028 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, 2029 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 2030 2031 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2032 interrupt-names = "msi"; 2033 #interrupt-cells = <1>; 2034 interrupt-map-mask = <0 0 0 0x7>; 2035 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2036 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2037 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2038 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2039 2040 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2041 <&gcc GCC_PCIE_2_AUX_CLK>, 2042 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2043 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2044 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2045 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2046 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2047 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2048 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2049 clock-names = "pipe", 2050 "aux", 2051 "cfg", 2052 "bus_master", 2053 "bus_slave", 2054 "slave_q2a", 2055 "ref", 2056 "tbu", 2057 "ddrss_sf_tbu"; 2058 2059 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2060 assigned-clock-rates = <19200000>; 2061 2062 iommus = <&apps_smmu 0x1d00 0x7f>; 2063 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2064 <0x100 &apps_smmu 0x1d01 0x1>; 2065 2066 resets = <&gcc GCC_PCIE_2_BCR>; 2067 reset-names = "pci"; 2068 2069 power-domains = <&gcc PCIE_2_GDSC>; 2070 2071 phys = <&pcie2_lane>; 2072 phy-names = "pciephy"; 2073 2074 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; 2075 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 2076 2077 pinctrl-names = "default"; 2078 pinctrl-0 = <&pcie2_default_state>; 2079 2080 status = "disabled"; 2081 }; 2082 2083 pcie2_phy: phy@1c16000 { 2084 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 2085 reg = <0 0x1c16000 0 0x1c0>; 2086 #address-cells = <2>; 2087 #size-cells = <2>; 2088 ranges; 2089 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2090 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2091 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2092 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2093 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2094 2095 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2096 reset-names = "phy"; 2097 2098 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2099 assigned-clock-rates = <100000000>; 2100 2101 status = "disabled"; 2102 2103 pcie2_lane: phy@1c16200 { 2104 reg = <0 0x1c16200 0 0x170>, /* tx0 */ 2105 <0 0x1c16400 0 0x200>, /* rx0 */ 2106 <0 0x1c16a00 0 0x1f0>, /* pcs */ 2107 <0 0x1c16600 0 0x170>, /* tx1 */ 2108 <0 0x1c16800 0 0x200>, /* rx1 */ 2109 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2110 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 2111 clock-names = "pipe0"; 2112 2113 #phy-cells = <0>; 2114 2115 #clock-cells = <0>; 2116 clock-output-names = "pcie_2_pipe_clk"; 2117 }; 2118 }; 2119 2120 ufs_mem_hc: ufshc@1d84000 { 2121 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 2122 "jedec,ufs-2.0"; 2123 reg = <0 0x01d84000 0 0x3000>; 2124 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2125 phys = <&ufs_mem_phy_lanes>; 2126 phy-names = "ufsphy"; 2127 lanes-per-direction = <2>; 2128 #reset-cells = <1>; 2129 resets = <&gcc GCC_UFS_PHY_BCR>; 2130 reset-names = "rst"; 2131 2132 power-domains = <&gcc UFS_PHY_GDSC>; 2133 2134 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 2135 2136 clock-names = 2137 "core_clk", 2138 "bus_aggr_clk", 2139 "iface_clk", 2140 "core_clk_unipro", 2141 "ref_clk", 2142 "tx_lane0_sync_clk", 2143 "rx_lane0_sync_clk", 2144 "rx_lane1_sync_clk"; 2145 clocks = 2146 <&gcc GCC_UFS_PHY_AXI_CLK>, 2147 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2148 <&gcc GCC_UFS_PHY_AHB_CLK>, 2149 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2150 <&rpmhcc RPMH_CXO_CLK>, 2151 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2152 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2153 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2154 freq-table-hz = 2155 <37500000 300000000>, 2156 <0 0>, 2157 <0 0>, 2158 <37500000 300000000>, 2159 <0 0>, 2160 <0 0>, 2161 <0 0>, 2162 <0 0>; 2163 2164 status = "disabled"; 2165 }; 2166 2167 ufs_mem_phy: phy@1d87000 { 2168 compatible = "qcom,sm8250-qmp-ufs-phy"; 2169 reg = <0 0x01d87000 0 0x1c0>; 2170 #address-cells = <2>; 2171 #size-cells = <2>; 2172 ranges; 2173 clock-names = "ref", 2174 "ref_aux"; 2175 clocks = <&rpmhcc RPMH_CXO_CLK>, 2176 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2177 2178 resets = <&ufs_mem_hc 0>; 2179 reset-names = "ufsphy"; 2180 status = "disabled"; 2181 2182 ufs_mem_phy_lanes: phy@1d87400 { 2183 reg = <0 0x01d87400 0 0x108>, 2184 <0 0x01d87600 0 0x1e0>, 2185 <0 0x01d87c00 0 0x1dc>, 2186 <0 0x01d87800 0 0x108>, 2187 <0 0x01d87a00 0 0x1e0>; 2188 #phy-cells = <0>; 2189 }; 2190 }; 2191 2192 ipa_virt: interconnect@1e00000 { 2193 compatible = "qcom,sm8250-ipa-virt"; 2194 reg = <0 0x01e00000 0 0x1000>; 2195 #interconnect-cells = <1>; 2196 qcom,bcm-voters = <&apps_bcm_voter>; 2197 }; 2198 2199 tcsr_mutex: hwlock@1f40000 { 2200 compatible = "qcom,tcsr-mutex"; 2201 reg = <0x0 0x01f40000 0x0 0x40000>; 2202 #hwlock-cells = <1>; 2203 }; 2204 2205 wsamacro: codec@3240000 { 2206 compatible = "qcom,sm8250-lpass-wsa-macro"; 2207 reg = <0 0x03240000 0 0x1000>; 2208 clocks = <&audiocc LPASS_CDC_WSA_MCLK>, 2209 <&audiocc LPASS_CDC_WSA_NPL>, 2210 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2211 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2212 <&aoncc LPASS_CDC_VA_MCLK>, 2213 <&vamacro>; 2214 2215 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 2216 2217 #clock-cells = <0>; 2218 clock-frequency = <9600000>; 2219 clock-output-names = "mclk"; 2220 #sound-dai-cells = <1>; 2221 2222 pinctrl-names = "default"; 2223 pinctrl-0 = <&wsa_swr_active>; 2224 }; 2225 2226 swr0: soundwire-controller@3250000 { 2227 reg = <0 0x03250000 0 0x2000>; 2228 compatible = "qcom,soundwire-v1.5.1"; 2229 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 2230 clocks = <&wsamacro>; 2231 clock-names = "iface"; 2232 2233 qcom,din-ports = <2>; 2234 qcom,dout-ports = <6>; 2235 2236 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2237 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2238 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2239 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 2240 2241 #sound-dai-cells = <1>; 2242 #address-cells = <2>; 2243 #size-cells = <0>; 2244 }; 2245 2246 audiocc: clock-controller@3300000 { 2247 compatible = "qcom,sm8250-lpass-audiocc"; 2248 reg = <0 0x03300000 0 0x30000>; 2249 #clock-cells = <1>; 2250 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2251 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2252 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2253 clock-names = "core", "audio", "bus"; 2254 }; 2255 2256 vamacro: codec@3370000 { 2257 compatible = "qcom,sm8250-lpass-va-macro"; 2258 reg = <0 0x03370000 0 0x1000>; 2259 clocks = <&aoncc LPASS_CDC_VA_MCLK>, 2260 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2261 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2262 2263 clock-names = "mclk", "macro", "dcodec"; 2264 2265 #clock-cells = <0>; 2266 clock-frequency = <9600000>; 2267 clock-output-names = "fsgen"; 2268 #sound-dai-cells = <1>; 2269 }; 2270 2271 rxmacro: rxmacro@3200000 { 2272 pinctrl-names = "default"; 2273 pinctrl-0 = <&rx_swr_active>; 2274 compatible = "qcom,sm8250-lpass-rx-macro"; 2275 reg = <0 0x3200000 0 0x1000>; 2276 status = "disabled"; 2277 2278 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2279 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2280 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2281 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2282 <&vamacro>; 2283 2284 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2285 2286 #clock-cells = <0>; 2287 clock-frequency = <9600000>; 2288 clock-output-names = "mclk"; 2289 #sound-dai-cells = <1>; 2290 }; 2291 2292 swr1: soundwire-controller@3210000 { 2293 reg = <0 0x3210000 0 0x2000>; 2294 compatible = "qcom,soundwire-v1.5.1"; 2295 status = "disabled"; 2296 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2297 clocks = <&rxmacro>; 2298 clock-names = "iface"; 2299 label = "RX"; 2300 qcom,din-ports = <0>; 2301 qcom,dout-ports = <5>; 2302 2303 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>; 2304 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 2305 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 2306 qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>; 2307 qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>; 2308 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>; 2309 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>; 2310 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2311 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>; 2312 2313 #sound-dai-cells = <1>; 2314 #address-cells = <2>; 2315 #size-cells = <0>; 2316 }; 2317 2318 txmacro: txmacro@3220000 { 2319 pinctrl-names = "default"; 2320 pinctrl-0 = <&tx_swr_active>; 2321 compatible = "qcom,sm8250-lpass-tx-macro"; 2322 reg = <0 0x3220000 0 0x1000>; 2323 status = "disabled"; 2324 2325 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2326 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2327 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2328 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2329 <&vamacro>; 2330 2331 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2332 2333 #clock-cells = <0>; 2334 clock-frequency = <9600000>; 2335 clock-output-names = "mclk"; 2336 #address-cells = <2>; 2337 #size-cells = <2>; 2338 #sound-dai-cells = <1>; 2339 }; 2340 2341 /* tx macro */ 2342 swr2: soundwire-controller@3230000 { 2343 reg = <0 0x3230000 0 0x2000>; 2344 compatible = "qcom,soundwire-v1.5.1"; 2345 interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 2346 interrupt-names = "core"; 2347 status = "disabled"; 2348 2349 clocks = <&txmacro>; 2350 clock-names = "iface"; 2351 label = "TX"; 2352 2353 qcom,din-ports = <5>; 2354 qcom,dout-ports = <0>; 2355 qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>; 2356 qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>; 2357 qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>; 2358 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2359 qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2360 qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2361 qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2362 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2363 qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>; 2364 qcom,port-offset = <1>; 2365 #sound-dai-cells = <1>; 2366 #address-cells = <2>; 2367 #size-cells = <0>; 2368 }; 2369 2370 aoncc: clock-controller@3380000 { 2371 compatible = "qcom,sm8250-lpass-aoncc"; 2372 reg = <0 0x03380000 0 0x40000>; 2373 #clock-cells = <1>; 2374 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2375 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2376 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2377 clock-names = "core", "audio", "bus"; 2378 }; 2379 2380 lpass_tlmm: pinctrl@33c0000{ 2381 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 2382 reg = <0 0x033c0000 0x0 0x20000>, 2383 <0 0x03550000 0x0 0x10000>; 2384 gpio-controller; 2385 #gpio-cells = <2>; 2386 gpio-ranges = <&lpass_tlmm 0 0 14>; 2387 2388 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2389 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2390 clock-names = "core", "audio"; 2391 2392 wsa_swr_active: wsa-swr-active-pins { 2393 clk { 2394 pins = "gpio10"; 2395 function = "wsa_swr_clk"; 2396 drive-strength = <2>; 2397 slew-rate = <1>; 2398 bias-disable; 2399 }; 2400 2401 data { 2402 pins = "gpio11"; 2403 function = "wsa_swr_data"; 2404 drive-strength = <2>; 2405 slew-rate = <1>; 2406 bias-bus-hold; 2407 2408 }; 2409 }; 2410 2411 wsa_swr_sleep: wsa-swr-sleep-pins { 2412 clk { 2413 pins = "gpio10"; 2414 function = "wsa_swr_clk"; 2415 drive-strength = <2>; 2416 input-enable; 2417 bias-pull-down; 2418 }; 2419 2420 data { 2421 pins = "gpio11"; 2422 function = "wsa_swr_data"; 2423 drive-strength = <2>; 2424 input-enable; 2425 bias-pull-down; 2426 2427 }; 2428 }; 2429 2430 dmic01_active: dmic01-active-pins { 2431 clk { 2432 pins = "gpio6"; 2433 function = "dmic1_clk"; 2434 drive-strength = <8>; 2435 output-high; 2436 }; 2437 data { 2438 pins = "gpio7"; 2439 function = "dmic1_data"; 2440 drive-strength = <8>; 2441 input-enable; 2442 }; 2443 }; 2444 2445 dmic01_sleep: dmic01-sleep-pins { 2446 clk { 2447 pins = "gpio6"; 2448 function = "dmic1_clk"; 2449 drive-strength = <2>; 2450 bias-disable; 2451 output-low; 2452 }; 2453 2454 data { 2455 pins = "gpio7"; 2456 function = "dmic1_data"; 2457 drive-strength = <2>; 2458 pull-down; 2459 input-enable; 2460 }; 2461 }; 2462 2463 rx_swr_active: rx_swr-active-pins { 2464 clk { 2465 pins = "gpio3"; 2466 function = "swr_rx_clk"; 2467 drive-strength = <2>; 2468 slew-rate = <1>; 2469 bias-disable; 2470 }; 2471 2472 data { 2473 pins = "gpio4", "gpio5"; 2474 function = "swr_rx_data"; 2475 drive-strength = <2>; 2476 slew-rate = <1>; 2477 bias-bus-hold; 2478 }; 2479 }; 2480 2481 tx_swr_active: tx_swr-active-pins { 2482 clk { 2483 pins = "gpio0"; 2484 function = "swr_tx_clk"; 2485 drive-strength = <2>; 2486 slew-rate = <1>; 2487 bias-disable; 2488 }; 2489 2490 data { 2491 pins = "gpio1", "gpio2"; 2492 function = "swr_tx_data"; 2493 drive-strength = <2>; 2494 slew-rate = <1>; 2495 bias-bus-hold; 2496 }; 2497 }; 2498 2499 tx_swr_sleep: tx_swr-sleep-pins { 2500 clk { 2501 pins = "gpio0"; 2502 function = "swr_tx_clk"; 2503 drive-strength = <2>; 2504 input-enable; 2505 bias-pull-down; 2506 }; 2507 2508 data1 { 2509 pins = "gpio1"; 2510 function = "swr_tx_data"; 2511 drive-strength = <2>; 2512 input-enable; 2513 bias-bus-hold; 2514 }; 2515 2516 data2 { 2517 pins = "gpio2"; 2518 function = "swr_tx_data"; 2519 drive-strength = <2>; 2520 input-enable; 2521 bias-pull-down; 2522 }; 2523 }; 2524 }; 2525 2526 gpu: gpu@3d00000 { 2527 compatible = "qcom,adreno-650.2", 2528 "qcom,adreno"; 2529 2530 reg = <0 0x03d00000 0 0x40000>; 2531 reg-names = "kgsl_3d0_reg_memory"; 2532 2533 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2534 2535 iommus = <&adreno_smmu 0 0x401>; 2536 2537 operating-points-v2 = <&gpu_opp_table>; 2538 2539 qcom,gmu = <&gmu>; 2540 2541 status = "disabled"; 2542 2543 zap-shader { 2544 memory-region = <&gpu_mem>; 2545 }; 2546 2547 /* note: downstream checks gpu binning for 670 Mhz */ 2548 gpu_opp_table: opp-table { 2549 compatible = "operating-points-v2"; 2550 2551 opp-670000000 { 2552 opp-hz = /bits/ 64 <670000000>; 2553 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2554 }; 2555 2556 opp-587000000 { 2557 opp-hz = /bits/ 64 <587000000>; 2558 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2559 }; 2560 2561 opp-525000000 { 2562 opp-hz = /bits/ 64 <525000000>; 2563 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2564 }; 2565 2566 opp-490000000 { 2567 opp-hz = /bits/ 64 <490000000>; 2568 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2569 }; 2570 2571 opp-441600000 { 2572 opp-hz = /bits/ 64 <441600000>; 2573 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2574 }; 2575 2576 opp-400000000 { 2577 opp-hz = /bits/ 64 <400000000>; 2578 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2579 }; 2580 2581 opp-305000000 { 2582 opp-hz = /bits/ 64 <305000000>; 2583 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2584 }; 2585 }; 2586 }; 2587 2588 gmu: gmu@3d6a000 { 2589 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2590 2591 reg = <0 0x03d6a000 0 0x30000>, 2592 <0 0x3de0000 0 0x10000>, 2593 <0 0xb290000 0 0x10000>, 2594 <0 0xb490000 0 0x10000>; 2595 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 2596 2597 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2598 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2599 interrupt-names = "hfi", "gmu"; 2600 2601 clocks = <&gpucc GPU_CC_AHB_CLK>, 2602 <&gpucc GPU_CC_CX_GMU_CLK>, 2603 <&gpucc GPU_CC_CXO_CLK>, 2604 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2605 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2606 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2607 2608 power-domains = <&gpucc GPU_CX_GDSC>, 2609 <&gpucc GPU_GX_GDSC>; 2610 power-domain-names = "cx", "gx"; 2611 2612 iommus = <&adreno_smmu 5 0x400>; 2613 2614 operating-points-v2 = <&gmu_opp_table>; 2615 2616 status = "disabled"; 2617 2618 gmu_opp_table: opp-table { 2619 compatible = "operating-points-v2"; 2620 2621 opp-200000000 { 2622 opp-hz = /bits/ 64 <200000000>; 2623 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2624 }; 2625 }; 2626 }; 2627 2628 gpucc: clock-controller@3d90000 { 2629 compatible = "qcom,sm8250-gpucc"; 2630 reg = <0 0x03d90000 0 0x9000>; 2631 clocks = <&rpmhcc RPMH_CXO_CLK>, 2632 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2633 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2634 clock-names = "bi_tcxo", 2635 "gcc_gpu_gpll0_clk_src", 2636 "gcc_gpu_gpll0_div_clk_src"; 2637 #clock-cells = <1>; 2638 #reset-cells = <1>; 2639 #power-domain-cells = <1>; 2640 }; 2641 2642 adreno_smmu: iommu@3da0000 { 2643 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2644 reg = <0 0x03da0000 0 0x10000>; 2645 #iommu-cells = <2>; 2646 #global-interrupts = <2>; 2647 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2648 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2649 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2650 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2651 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2652 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2653 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2654 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2655 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2656 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 2657 clocks = <&gpucc GPU_CC_AHB_CLK>, 2658 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2659 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2660 clock-names = "ahb", "bus", "iface"; 2661 2662 power-domains = <&gpucc GPU_CX_GDSC>; 2663 }; 2664 2665 slpi: remoteproc@5c00000 { 2666 compatible = "qcom,sm8250-slpi-pas"; 2667 reg = <0 0x05c00000 0 0x4000>; 2668 2669 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2670 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2671 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2672 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2673 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2674 interrupt-names = "wdog", "fatal", "ready", 2675 "handover", "stop-ack"; 2676 2677 clocks = <&rpmhcc RPMH_CXO_CLK>; 2678 clock-names = "xo"; 2679 2680 power-domains = <&rpmhpd SM8250_LCX>, 2681 <&rpmhpd SM8250_LMX>; 2682 power-domain-names = "lcx", "lmx"; 2683 2684 memory-region = <&slpi_mem>; 2685 2686 qcom,qmp = <&aoss_qmp>; 2687 2688 qcom,smem-states = <&smp2p_slpi_out 0>; 2689 qcom,smem-state-names = "stop"; 2690 2691 status = "disabled"; 2692 2693 glink-edge { 2694 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2695 IPCC_MPROC_SIGNAL_GLINK_QMP 2696 IRQ_TYPE_EDGE_RISING>; 2697 mboxes = <&ipcc IPCC_CLIENT_SLPI 2698 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2699 2700 label = "slpi"; 2701 qcom,remote-pid = <3>; 2702 2703 fastrpc { 2704 compatible = "qcom,fastrpc"; 2705 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2706 label = "sdsp"; 2707 qcom,non-secure-domain; 2708 #address-cells = <1>; 2709 #size-cells = <0>; 2710 2711 compute-cb@1 { 2712 compatible = "qcom,fastrpc-compute-cb"; 2713 reg = <1>; 2714 iommus = <&apps_smmu 0x0541 0x0>; 2715 }; 2716 2717 compute-cb@2 { 2718 compatible = "qcom,fastrpc-compute-cb"; 2719 reg = <2>; 2720 iommus = <&apps_smmu 0x0542 0x0>; 2721 }; 2722 2723 compute-cb@3 { 2724 compatible = "qcom,fastrpc-compute-cb"; 2725 reg = <3>; 2726 iommus = <&apps_smmu 0x0543 0x0>; 2727 /* note: shared-cb = <4> in downstream */ 2728 }; 2729 }; 2730 }; 2731 }; 2732 2733 cdsp: remoteproc@8300000 { 2734 compatible = "qcom,sm8250-cdsp-pas"; 2735 reg = <0 0x08300000 0 0x10000>; 2736 2737 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 2738 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2739 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2740 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2741 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2742 interrupt-names = "wdog", "fatal", "ready", 2743 "handover", "stop-ack"; 2744 2745 clocks = <&rpmhcc RPMH_CXO_CLK>; 2746 clock-names = "xo"; 2747 2748 power-domains = <&rpmhpd SM8250_CX>; 2749 2750 memory-region = <&cdsp_mem>; 2751 2752 qcom,qmp = <&aoss_qmp>; 2753 2754 qcom,smem-states = <&smp2p_cdsp_out 0>; 2755 qcom,smem-state-names = "stop"; 2756 2757 status = "disabled"; 2758 2759 glink-edge { 2760 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2761 IPCC_MPROC_SIGNAL_GLINK_QMP 2762 IRQ_TYPE_EDGE_RISING>; 2763 mboxes = <&ipcc IPCC_CLIENT_CDSP 2764 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2765 2766 label = "cdsp"; 2767 qcom,remote-pid = <5>; 2768 2769 fastrpc { 2770 compatible = "qcom,fastrpc"; 2771 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2772 label = "cdsp"; 2773 qcom,non-secure-domain; 2774 #address-cells = <1>; 2775 #size-cells = <0>; 2776 2777 compute-cb@1 { 2778 compatible = "qcom,fastrpc-compute-cb"; 2779 reg = <1>; 2780 iommus = <&apps_smmu 0x1001 0x0460>; 2781 }; 2782 2783 compute-cb@2 { 2784 compatible = "qcom,fastrpc-compute-cb"; 2785 reg = <2>; 2786 iommus = <&apps_smmu 0x1002 0x0460>; 2787 }; 2788 2789 compute-cb@3 { 2790 compatible = "qcom,fastrpc-compute-cb"; 2791 reg = <3>; 2792 iommus = <&apps_smmu 0x1003 0x0460>; 2793 }; 2794 2795 compute-cb@4 { 2796 compatible = "qcom,fastrpc-compute-cb"; 2797 reg = <4>; 2798 iommus = <&apps_smmu 0x1004 0x0460>; 2799 }; 2800 2801 compute-cb@5 { 2802 compatible = "qcom,fastrpc-compute-cb"; 2803 reg = <5>; 2804 iommus = <&apps_smmu 0x1005 0x0460>; 2805 }; 2806 2807 compute-cb@6 { 2808 compatible = "qcom,fastrpc-compute-cb"; 2809 reg = <6>; 2810 iommus = <&apps_smmu 0x1006 0x0460>; 2811 }; 2812 2813 compute-cb@7 { 2814 compatible = "qcom,fastrpc-compute-cb"; 2815 reg = <7>; 2816 iommus = <&apps_smmu 0x1007 0x0460>; 2817 }; 2818 2819 compute-cb@8 { 2820 compatible = "qcom,fastrpc-compute-cb"; 2821 reg = <8>; 2822 iommus = <&apps_smmu 0x1008 0x0460>; 2823 }; 2824 2825 /* note: secure cb9 in downstream */ 2826 }; 2827 }; 2828 }; 2829 2830 sound: sound { 2831 }; 2832 2833 usb_1_hsphy: phy@88e3000 { 2834 compatible = "qcom,sm8250-usb-hs-phy", 2835 "qcom,usb-snps-hs-7nm-phy"; 2836 reg = <0 0x088e3000 0 0x400>; 2837 status = "disabled"; 2838 #phy-cells = <0>; 2839 2840 clocks = <&rpmhcc RPMH_CXO_CLK>; 2841 clock-names = "ref"; 2842 2843 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2844 }; 2845 2846 usb_2_hsphy: phy@88e4000 { 2847 compatible = "qcom,sm8250-usb-hs-phy", 2848 "qcom,usb-snps-hs-7nm-phy"; 2849 reg = <0 0x088e4000 0 0x400>; 2850 status = "disabled"; 2851 #phy-cells = <0>; 2852 2853 clocks = <&rpmhcc RPMH_CXO_CLK>; 2854 clock-names = "ref"; 2855 2856 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2857 }; 2858 2859 usb_1_qmpphy: phy@88e9000 { 2860 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 2861 reg = <0 0x088e9000 0 0x200>, 2862 <0 0x088e8000 0 0x40>, 2863 <0 0x088ea000 0 0x200>; 2864 status = "disabled"; 2865 #address-cells = <2>; 2866 #size-cells = <2>; 2867 ranges; 2868 2869 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2870 <&rpmhcc RPMH_CXO_CLK>, 2871 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2872 clock-names = "aux", "ref_clk_src", "com_aux"; 2873 2874 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2875 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2876 reset-names = "phy", "common"; 2877 2878 usb_1_ssphy: usb3-phy@88e9200 { 2879 reg = <0 0x088e9200 0 0x200>, 2880 <0 0x088e9400 0 0x200>, 2881 <0 0x088e9c00 0 0x400>, 2882 <0 0x088e9600 0 0x200>, 2883 <0 0x088e9800 0 0x200>, 2884 <0 0x088e9a00 0 0x100>; 2885 #clock-cells = <0>; 2886 #phy-cells = <0>; 2887 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2888 clock-names = "pipe0"; 2889 clock-output-names = "usb3_phy_pipe_clk_src"; 2890 }; 2891 2892 dp_phy: dp-phy@88ea200 { 2893 reg = <0 0x088ea200 0 0x200>, 2894 <0 0x088ea400 0 0x200>, 2895 <0 0x088eac00 0 0x400>, 2896 <0 0x088ea600 0 0x200>, 2897 <0 0x088ea800 0 0x200>, 2898 <0 0x088eaa00 0 0x100>; 2899 #phy-cells = <0>; 2900 #clock-cells = <1>; 2901 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2902 clock-names = "pipe0"; 2903 clock-output-names = "usb3_phy_pipe_clk_src"; 2904 }; 2905 }; 2906 2907 usb_2_qmpphy: phy@88eb000 { 2908 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 2909 reg = <0 0x088eb000 0 0x200>; 2910 status = "disabled"; 2911 #address-cells = <2>; 2912 #size-cells = <2>; 2913 ranges; 2914 2915 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2916 <&rpmhcc RPMH_CXO_CLK>, 2917 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2918 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2919 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2920 2921 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2922 <&gcc GCC_USB3_PHY_SEC_BCR>; 2923 reset-names = "phy", "common"; 2924 2925 usb_2_ssphy: phy@88eb200 { 2926 reg = <0 0x088eb200 0 0x200>, 2927 <0 0x088eb400 0 0x200>, 2928 <0 0x088eb800 0 0x800>; 2929 #clock-cells = <0>; 2930 #phy-cells = <0>; 2931 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2932 clock-names = "pipe0"; 2933 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2934 }; 2935 }; 2936 2937 sdhc_2: mmc@8804000 { 2938 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 2939 reg = <0 0x08804000 0 0x1000>; 2940 2941 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2942 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2943 interrupt-names = "hc_irq", "pwr_irq"; 2944 2945 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2946 <&gcc GCC_SDCC2_APPS_CLK>, 2947 <&rpmhcc RPMH_CXO_CLK>; 2948 clock-names = "iface", "core", "xo"; 2949 iommus = <&apps_smmu 0x4a0 0x0>; 2950 qcom,dll-config = <0x0007642c>; 2951 qcom,ddr-config = <0x80040868>; 2952 power-domains = <&rpmhpd SM8250_CX>; 2953 operating-points-v2 = <&sdhc2_opp_table>; 2954 2955 status = "disabled"; 2956 2957 sdhc2_opp_table: opp-table { 2958 compatible = "operating-points-v2"; 2959 2960 opp-19200000 { 2961 opp-hz = /bits/ 64 <19200000>; 2962 required-opps = <&rpmhpd_opp_min_svs>; 2963 }; 2964 2965 opp-50000000 { 2966 opp-hz = /bits/ 64 <50000000>; 2967 required-opps = <&rpmhpd_opp_low_svs>; 2968 }; 2969 2970 opp-100000000 { 2971 opp-hz = /bits/ 64 <100000000>; 2972 required-opps = <&rpmhpd_opp_svs>; 2973 }; 2974 2975 opp-202000000 { 2976 opp-hz = /bits/ 64 <202000000>; 2977 required-opps = <&rpmhpd_opp_svs_l1>; 2978 }; 2979 }; 2980 }; 2981 2982 dc_noc: interconnect@90c0000 { 2983 compatible = "qcom,sm8250-dc-noc"; 2984 reg = <0 0x090c0000 0 0x4200>; 2985 #interconnect-cells = <1>; 2986 qcom,bcm-voters = <&apps_bcm_voter>; 2987 }; 2988 2989 gem_noc: interconnect@9100000 { 2990 compatible = "qcom,sm8250-gem-noc"; 2991 reg = <0 0x09100000 0 0xb4000>; 2992 #interconnect-cells = <1>; 2993 qcom,bcm-voters = <&apps_bcm_voter>; 2994 }; 2995 2996 npu_noc: interconnect@9990000 { 2997 compatible = "qcom,sm8250-npu-noc"; 2998 reg = <0 0x09990000 0 0x1600>; 2999 #interconnect-cells = <1>; 3000 qcom,bcm-voters = <&apps_bcm_voter>; 3001 }; 3002 3003 usb_1: usb@a6f8800 { 3004 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3005 reg = <0 0x0a6f8800 0 0x400>; 3006 status = "disabled"; 3007 #address-cells = <2>; 3008 #size-cells = <2>; 3009 ranges; 3010 dma-ranges; 3011 3012 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3013 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3014 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3015 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3016 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3017 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3018 clock-names = "cfg_noc", 3019 "core", 3020 "iface", 3021 "sleep", 3022 "mock_utmi", 3023 "xo"; 3024 3025 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3026 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3027 assigned-clock-rates = <19200000>, <200000000>; 3028 3029 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3030 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 3031 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3032 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 3033 interrupt-names = "hs_phy_irq", 3034 "ss_phy_irq", 3035 "dm_hs_phy_irq", 3036 "dp_hs_phy_irq"; 3037 3038 power-domains = <&gcc USB30_PRIM_GDSC>; 3039 3040 resets = <&gcc GCC_USB30_PRIM_BCR>; 3041 3042 usb_1_dwc3: usb@a600000 { 3043 compatible = "snps,dwc3"; 3044 reg = <0 0x0a600000 0 0xcd00>; 3045 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3046 iommus = <&apps_smmu 0x0 0x0>; 3047 snps,dis_u2_susphy_quirk; 3048 snps,dis_enblslpm_quirk; 3049 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3050 phy-names = "usb2-phy", "usb3-phy"; 3051 }; 3052 }; 3053 3054 system-cache-controller@9200000 { 3055 compatible = "qcom,sm8250-llcc"; 3056 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 3057 reg-names = "llcc_base", "llcc_broadcast_base"; 3058 }; 3059 3060 usb_2: usb@a8f8800 { 3061 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3062 reg = <0 0x0a8f8800 0 0x400>; 3063 status = "disabled"; 3064 #address-cells = <2>; 3065 #size-cells = <2>; 3066 ranges; 3067 dma-ranges; 3068 3069 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3070 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3071 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3072 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3073 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3074 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3075 clock-names = "cfg_noc", 3076 "core", 3077 "iface", 3078 "sleep", 3079 "mock_utmi", 3080 "xo"; 3081 3082 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3083 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3084 assigned-clock-rates = <19200000>, <200000000>; 3085 3086 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3087 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 3088 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3089 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 3090 interrupt-names = "hs_phy_irq", 3091 "ss_phy_irq", 3092 "dm_hs_phy_irq", 3093 "dp_hs_phy_irq"; 3094 3095 power-domains = <&gcc USB30_SEC_GDSC>; 3096 3097 resets = <&gcc GCC_USB30_SEC_BCR>; 3098 3099 usb_2_dwc3: usb@a800000 { 3100 compatible = "snps,dwc3"; 3101 reg = <0 0x0a800000 0 0xcd00>; 3102 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3103 iommus = <&apps_smmu 0x20 0>; 3104 snps,dis_u2_susphy_quirk; 3105 snps,dis_enblslpm_quirk; 3106 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3107 phy-names = "usb2-phy", "usb3-phy"; 3108 }; 3109 }; 3110 3111 venus: video-codec@aa00000 { 3112 compatible = "qcom,sm8250-venus"; 3113 reg = <0 0x0aa00000 0 0x100000>; 3114 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3115 power-domains = <&videocc MVS0C_GDSC>, 3116 <&videocc MVS0_GDSC>, 3117 <&rpmhpd SM8250_MX>; 3118 power-domain-names = "venus", "vcodec0", "mx"; 3119 operating-points-v2 = <&venus_opp_table>; 3120 3121 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 3122 <&videocc VIDEO_CC_MVS0C_CLK>, 3123 <&videocc VIDEO_CC_MVS0_CLK>; 3124 clock-names = "iface", "core", "vcodec0_core"; 3125 3126 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, 3127 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; 3128 interconnect-names = "cpu-cfg", "video-mem"; 3129 3130 iommus = <&apps_smmu 0x2100 0x0400>; 3131 memory-region = <&video_mem>; 3132 3133 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 3134 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 3135 reset-names = "bus", "core"; 3136 3137 status = "disabled"; 3138 3139 video-decoder { 3140 compatible = "venus-decoder"; 3141 }; 3142 3143 video-encoder { 3144 compatible = "venus-encoder"; 3145 }; 3146 3147 venus_opp_table: opp-table { 3148 compatible = "operating-points-v2"; 3149 3150 opp-720000000 { 3151 opp-hz = /bits/ 64 <720000000>; 3152 required-opps = <&rpmhpd_opp_low_svs>; 3153 }; 3154 3155 opp-1014000000 { 3156 opp-hz = /bits/ 64 <1014000000>; 3157 required-opps = <&rpmhpd_opp_svs>; 3158 }; 3159 3160 opp-1098000000 { 3161 opp-hz = /bits/ 64 <1098000000>; 3162 required-opps = <&rpmhpd_opp_svs_l1>; 3163 }; 3164 3165 opp-1332000000 { 3166 opp-hz = /bits/ 64 <1332000000>; 3167 required-opps = <&rpmhpd_opp_nom>; 3168 }; 3169 }; 3170 }; 3171 3172 videocc: clock-controller@abf0000 { 3173 compatible = "qcom,sm8250-videocc"; 3174 reg = <0 0x0abf0000 0 0x10000>; 3175 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 3176 <&rpmhcc RPMH_CXO_CLK>, 3177 <&rpmhcc RPMH_CXO_CLK_A>; 3178 power-domains = <&rpmhpd SM8250_MMCX>; 3179 required-opps = <&rpmhpd_opp_low_svs>; 3180 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 3181 #clock-cells = <1>; 3182 #reset-cells = <1>; 3183 #power-domain-cells = <1>; 3184 }; 3185 3186 cci0: cci@ac4f000 { 3187 compatible = "qcom,sm8250-cci"; 3188 #address-cells = <1>; 3189 #size-cells = <0>; 3190 3191 reg = <0 0x0ac4f000 0 0x1000>; 3192 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3193 power-domains = <&camcc TITAN_TOP_GDSC>; 3194 3195 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3196 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3197 <&camcc CAM_CC_CPAS_AHB_CLK>, 3198 <&camcc CAM_CC_CCI_0_CLK>, 3199 <&camcc CAM_CC_CCI_0_CLK_SRC>; 3200 clock-names = "camnoc_axi", 3201 "slow_ahb_src", 3202 "cpas_ahb", 3203 "cci", 3204 "cci_src"; 3205 3206 pinctrl-0 = <&cci0_default>; 3207 pinctrl-1 = <&cci0_sleep>; 3208 pinctrl-names = "default", "sleep"; 3209 3210 status = "disabled"; 3211 3212 cci0_i2c0: i2c-bus@0 { 3213 reg = <0>; 3214 clock-frequency = <1000000>; 3215 #address-cells = <1>; 3216 #size-cells = <0>; 3217 }; 3218 3219 cci0_i2c1: i2c-bus@1 { 3220 reg = <1>; 3221 clock-frequency = <1000000>; 3222 #address-cells = <1>; 3223 #size-cells = <0>; 3224 }; 3225 }; 3226 3227 cci1: cci@ac50000 { 3228 compatible = "qcom,sm8250-cci"; 3229 #address-cells = <1>; 3230 #size-cells = <0>; 3231 3232 reg = <0 0x0ac50000 0 0x1000>; 3233 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 3234 power-domains = <&camcc TITAN_TOP_GDSC>; 3235 3236 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3237 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3238 <&camcc CAM_CC_CPAS_AHB_CLK>, 3239 <&camcc CAM_CC_CCI_1_CLK>, 3240 <&camcc CAM_CC_CCI_1_CLK_SRC>; 3241 clock-names = "camnoc_axi", 3242 "slow_ahb_src", 3243 "cpas_ahb", 3244 "cci", 3245 "cci_src"; 3246 3247 pinctrl-0 = <&cci1_default>; 3248 pinctrl-1 = <&cci1_sleep>; 3249 pinctrl-names = "default", "sleep"; 3250 3251 status = "disabled"; 3252 3253 cci1_i2c0: i2c-bus@0 { 3254 reg = <0>; 3255 clock-frequency = <1000000>; 3256 #address-cells = <1>; 3257 #size-cells = <0>; 3258 }; 3259 3260 cci1_i2c1: i2c-bus@1 { 3261 reg = <1>; 3262 clock-frequency = <1000000>; 3263 #address-cells = <1>; 3264 #size-cells = <0>; 3265 }; 3266 }; 3267 3268 camss: camss@ac6a000 { 3269 compatible = "qcom,sm8250-camss"; 3270 status = "disabled"; 3271 3272 reg = <0 0xac6a000 0 0x2000>, 3273 <0 0xac6c000 0 0x2000>, 3274 <0 0xac6e000 0 0x1000>, 3275 <0 0xac70000 0 0x1000>, 3276 <0 0xac72000 0 0x1000>, 3277 <0 0xac74000 0 0x1000>, 3278 <0 0xacb4000 0 0xd000>, 3279 <0 0xacc3000 0 0xd000>, 3280 <0 0xacd9000 0 0x2200>, 3281 <0 0xacdb200 0 0x2200>; 3282 reg-names = "csiphy0", 3283 "csiphy1", 3284 "csiphy2", 3285 "csiphy3", 3286 "csiphy4", 3287 "csiphy5", 3288 "vfe0", 3289 "vfe1", 3290 "vfe_lite0", 3291 "vfe_lite1"; 3292 3293 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 3294 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 3295 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 3296 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 3297 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 3298 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 3299 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 3300 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 3301 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 3302 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 3303 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 3304 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 3305 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 3306 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 3307 interrupt-names = "csiphy0", 3308 "csiphy1", 3309 "csiphy2", 3310 "csiphy3", 3311 "csiphy4", 3312 "csiphy5", 3313 "csid0", 3314 "csid1", 3315 "csid2", 3316 "csid3", 3317 "vfe0", 3318 "vfe1", 3319 "vfe_lite0", 3320 "vfe_lite1"; 3321 3322 power-domains = <&camcc IFE_0_GDSC>, 3323 <&camcc IFE_1_GDSC>, 3324 <&camcc TITAN_TOP_GDSC>; 3325 3326 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3327 <&gcc GCC_CAMERA_HF_AXI_CLK>, 3328 <&gcc GCC_CAMERA_SF_AXI_CLK>, 3329 <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3330 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, 3331 <&camcc CAM_CC_CORE_AHB_CLK>, 3332 <&camcc CAM_CC_CPAS_AHB_CLK>, 3333 <&camcc CAM_CC_CSIPHY0_CLK>, 3334 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 3335 <&camcc CAM_CC_CSIPHY1_CLK>, 3336 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 3337 <&camcc CAM_CC_CSIPHY2_CLK>, 3338 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 3339 <&camcc CAM_CC_CSIPHY3_CLK>, 3340 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 3341 <&camcc CAM_CC_CSIPHY4_CLK>, 3342 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 3343 <&camcc CAM_CC_CSIPHY5_CLK>, 3344 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 3345 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3346 <&camcc CAM_CC_IFE_0_AHB_CLK>, 3347 <&camcc CAM_CC_IFE_0_AXI_CLK>, 3348 <&camcc CAM_CC_IFE_0_CLK>, 3349 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 3350 <&camcc CAM_CC_IFE_0_CSID_CLK>, 3351 <&camcc CAM_CC_IFE_0_AREG_CLK>, 3352 <&camcc CAM_CC_IFE_1_AHB_CLK>, 3353 <&camcc CAM_CC_IFE_1_AXI_CLK>, 3354 <&camcc CAM_CC_IFE_1_CLK>, 3355 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 3356 <&camcc CAM_CC_IFE_1_CSID_CLK>, 3357 <&camcc CAM_CC_IFE_1_AREG_CLK>, 3358 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 3359 <&camcc CAM_CC_IFE_LITE_AXI_CLK>, 3360 <&camcc CAM_CC_IFE_LITE_CLK>, 3361 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 3362 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 3363 3364 clock-names = "cam_ahb_clk", 3365 "cam_hf_axi", 3366 "cam_sf_axi", 3367 "camnoc_axi", 3368 "camnoc_axi_src", 3369 "core_ahb", 3370 "cpas_ahb", 3371 "csiphy0", 3372 "csiphy0_timer", 3373 "csiphy1", 3374 "csiphy1_timer", 3375 "csiphy2", 3376 "csiphy2_timer", 3377 "csiphy3", 3378 "csiphy3_timer", 3379 "csiphy4", 3380 "csiphy4_timer", 3381 "csiphy5", 3382 "csiphy5_timer", 3383 "slow_ahb_src", 3384 "vfe0_ahb", 3385 "vfe0_axi", 3386 "vfe0", 3387 "vfe0_cphy_rx", 3388 "vfe0_csid", 3389 "vfe0_areg", 3390 "vfe1_ahb", 3391 "vfe1_axi", 3392 "vfe1", 3393 "vfe1_cphy_rx", 3394 "vfe1_csid", 3395 "vfe1_areg", 3396 "vfe_lite_ahb", 3397 "vfe_lite_axi", 3398 "vfe_lite", 3399 "vfe_lite_cphy_rx", 3400 "vfe_lite_csid"; 3401 3402 iommus = <&apps_smmu 0x800 0x400>, 3403 <&apps_smmu 0x801 0x400>, 3404 <&apps_smmu 0x840 0x400>, 3405 <&apps_smmu 0x841 0x400>, 3406 <&apps_smmu 0xc00 0x400>, 3407 <&apps_smmu 0xc01 0x400>, 3408 <&apps_smmu 0xc40 0x400>, 3409 <&apps_smmu 0xc41 0x400>; 3410 3411 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>, 3412 <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>, 3413 <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>, 3414 <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>; 3415 interconnect-names = "cam_ahb", 3416 "cam_hf_0_mnoc", 3417 "cam_sf_0_mnoc", 3418 "cam_sf_icp_mnoc"; 3419 }; 3420 3421 camcc: clock-controller@ad00000 { 3422 compatible = "qcom,sm8250-camcc"; 3423 reg = <0 0x0ad00000 0 0x10000>; 3424 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3425 <&rpmhcc RPMH_CXO_CLK>, 3426 <&rpmhcc RPMH_CXO_CLK_A>, 3427 <&sleep_clk>; 3428 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3429 power-domains = <&rpmhpd SM8250_MMCX>; 3430 required-opps = <&rpmhpd_opp_low_svs>; 3431 status = "disabled"; 3432 #clock-cells = <1>; 3433 #reset-cells = <1>; 3434 #power-domain-cells = <1>; 3435 }; 3436 3437 mdss: mdss@ae00000 { 3438 compatible = "qcom,sm8250-mdss"; 3439 reg = <0 0x0ae00000 0 0x1000>; 3440 reg-names = "mdss"; 3441 3442 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 3443 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 3444 interconnect-names = "mdp0-mem", "mdp1-mem"; 3445 3446 power-domains = <&dispcc MDSS_GDSC>; 3447 3448 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3449 <&gcc GCC_DISP_HF_AXI_CLK>, 3450 <&gcc GCC_DISP_SF_AXI_CLK>, 3451 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3452 clock-names = "iface", "bus", "nrt_bus", "core"; 3453 3454 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3455 interrupt-controller; 3456 #interrupt-cells = <1>; 3457 3458 iommus = <&apps_smmu 0x820 0x402>; 3459 3460 status = "disabled"; 3461 3462 #address-cells = <2>; 3463 #size-cells = <2>; 3464 ranges; 3465 3466 mdss_mdp: display-controller@ae01000 { 3467 compatible = "qcom,sm8250-dpu"; 3468 reg = <0 0x0ae01000 0 0x8f000>, 3469 <0 0x0aeb0000 0 0x2008>; 3470 reg-names = "mdp", "vbif"; 3471 3472 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3473 <&gcc GCC_DISP_HF_AXI_CLK>, 3474 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3475 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3476 clock-names = "iface", "bus", "core", "vsync"; 3477 3478 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3479 assigned-clock-rates = <19200000>; 3480 3481 operating-points-v2 = <&mdp_opp_table>; 3482 power-domains = <&rpmhpd SM8250_MMCX>; 3483 3484 interrupt-parent = <&mdss>; 3485 interrupts = <0>; 3486 3487 ports { 3488 #address-cells = <1>; 3489 #size-cells = <0>; 3490 3491 port@0 { 3492 reg = <0>; 3493 dpu_intf1_out: endpoint { 3494 remote-endpoint = <&dsi0_in>; 3495 }; 3496 }; 3497 3498 port@1 { 3499 reg = <1>; 3500 dpu_intf2_out: endpoint { 3501 remote-endpoint = <&dsi1_in>; 3502 }; 3503 }; 3504 }; 3505 3506 mdp_opp_table: opp-table { 3507 compatible = "operating-points-v2"; 3508 3509 opp-200000000 { 3510 opp-hz = /bits/ 64 <200000000>; 3511 required-opps = <&rpmhpd_opp_low_svs>; 3512 }; 3513 3514 opp-300000000 { 3515 opp-hz = /bits/ 64 <300000000>; 3516 required-opps = <&rpmhpd_opp_svs>; 3517 }; 3518 3519 opp-345000000 { 3520 opp-hz = /bits/ 64 <345000000>; 3521 required-opps = <&rpmhpd_opp_svs_l1>; 3522 }; 3523 3524 opp-460000000 { 3525 opp-hz = /bits/ 64 <460000000>; 3526 required-opps = <&rpmhpd_opp_nom>; 3527 }; 3528 }; 3529 }; 3530 3531 dsi0: dsi@ae94000 { 3532 compatible = "qcom,mdss-dsi-ctrl"; 3533 reg = <0 0x0ae94000 0 0x400>; 3534 reg-names = "dsi_ctrl"; 3535 3536 interrupt-parent = <&mdss>; 3537 interrupts = <4>; 3538 3539 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3540 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3541 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3542 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3543 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3544 <&gcc GCC_DISP_HF_AXI_CLK>; 3545 clock-names = "byte", 3546 "byte_intf", 3547 "pixel", 3548 "core", 3549 "iface", 3550 "bus"; 3551 3552 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3553 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 3554 3555 operating-points-v2 = <&dsi_opp_table>; 3556 power-domains = <&rpmhpd SM8250_MMCX>; 3557 3558 phys = <&dsi0_phy>; 3559 phy-names = "dsi"; 3560 3561 status = "disabled"; 3562 3563 #address-cells = <1>; 3564 #size-cells = <0>; 3565 3566 ports { 3567 #address-cells = <1>; 3568 #size-cells = <0>; 3569 3570 port@0 { 3571 reg = <0>; 3572 dsi0_in: endpoint { 3573 remote-endpoint = <&dpu_intf1_out>; 3574 }; 3575 }; 3576 3577 port@1 { 3578 reg = <1>; 3579 dsi0_out: endpoint { 3580 }; 3581 }; 3582 }; 3583 3584 dsi_opp_table: opp-table { 3585 compatible = "operating-points-v2"; 3586 3587 opp-187500000 { 3588 opp-hz = /bits/ 64 <187500000>; 3589 required-opps = <&rpmhpd_opp_low_svs>; 3590 }; 3591 3592 opp-300000000 { 3593 opp-hz = /bits/ 64 <300000000>; 3594 required-opps = <&rpmhpd_opp_svs>; 3595 }; 3596 3597 opp-358000000 { 3598 opp-hz = /bits/ 64 <358000000>; 3599 required-opps = <&rpmhpd_opp_svs_l1>; 3600 }; 3601 }; 3602 }; 3603 3604 dsi0_phy: dsi-phy@ae94400 { 3605 compatible = "qcom,dsi-phy-7nm"; 3606 reg = <0 0x0ae94400 0 0x200>, 3607 <0 0x0ae94600 0 0x280>, 3608 <0 0x0ae94900 0 0x260>; 3609 reg-names = "dsi_phy", 3610 "dsi_phy_lane", 3611 "dsi_pll"; 3612 3613 #clock-cells = <1>; 3614 #phy-cells = <0>; 3615 3616 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3617 <&rpmhcc RPMH_CXO_CLK>; 3618 clock-names = "iface", "ref"; 3619 3620 status = "disabled"; 3621 }; 3622 3623 dsi1: dsi@ae96000 { 3624 compatible = "qcom,mdss-dsi-ctrl"; 3625 reg = <0 0x0ae96000 0 0x400>; 3626 reg-names = "dsi_ctrl"; 3627 3628 interrupt-parent = <&mdss>; 3629 interrupts = <5>; 3630 3631 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3632 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3633 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3634 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3635 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3636 <&gcc GCC_DISP_HF_AXI_CLK>; 3637 clock-names = "byte", 3638 "byte_intf", 3639 "pixel", 3640 "core", 3641 "iface", 3642 "bus"; 3643 3644 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3645 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 3646 3647 operating-points-v2 = <&dsi_opp_table>; 3648 power-domains = <&rpmhpd SM8250_MMCX>; 3649 3650 phys = <&dsi1_phy>; 3651 phy-names = "dsi"; 3652 3653 status = "disabled"; 3654 3655 #address-cells = <1>; 3656 #size-cells = <0>; 3657 3658 ports { 3659 #address-cells = <1>; 3660 #size-cells = <0>; 3661 3662 port@0 { 3663 reg = <0>; 3664 dsi1_in: endpoint { 3665 remote-endpoint = <&dpu_intf2_out>; 3666 }; 3667 }; 3668 3669 port@1 { 3670 reg = <1>; 3671 dsi1_out: endpoint { 3672 }; 3673 }; 3674 }; 3675 }; 3676 3677 dsi1_phy: dsi-phy@ae96400 { 3678 compatible = "qcom,dsi-phy-7nm"; 3679 reg = <0 0x0ae96400 0 0x200>, 3680 <0 0x0ae96600 0 0x280>, 3681 <0 0x0ae96900 0 0x260>; 3682 reg-names = "dsi_phy", 3683 "dsi_phy_lane", 3684 "dsi_pll"; 3685 3686 #clock-cells = <1>; 3687 #phy-cells = <0>; 3688 3689 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3690 <&rpmhcc RPMH_CXO_CLK>; 3691 clock-names = "iface", "ref"; 3692 3693 status = "disabled"; 3694 }; 3695 }; 3696 3697 dispcc: clock-controller@af00000 { 3698 compatible = "qcom,sm8250-dispcc"; 3699 reg = <0 0x0af00000 0 0x10000>; 3700 power-domains = <&rpmhpd SM8250_MMCX>; 3701 required-opps = <&rpmhpd_opp_low_svs>; 3702 clocks = <&rpmhcc RPMH_CXO_CLK>, 3703 <&dsi0_phy 0>, 3704 <&dsi0_phy 1>, 3705 <&dsi1_phy 0>, 3706 <&dsi1_phy 1>, 3707 <&dp_phy 0>, 3708 <&dp_phy 1>; 3709 clock-names = "bi_tcxo", 3710 "dsi0_phy_pll_out_byteclk", 3711 "dsi0_phy_pll_out_dsiclk", 3712 "dsi1_phy_pll_out_byteclk", 3713 "dsi1_phy_pll_out_dsiclk", 3714 "dp_phy_pll_link_clk", 3715 "dp_phy_pll_vco_div_clk"; 3716 #clock-cells = <1>; 3717 #reset-cells = <1>; 3718 #power-domain-cells = <1>; 3719 }; 3720 3721 pdc: interrupt-controller@b220000 { 3722 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 3723 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 3724 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3725 <125 63 1>, <126 716 12>; 3726 #interrupt-cells = <2>; 3727 interrupt-parent = <&intc>; 3728 interrupt-controller; 3729 }; 3730 3731 tsens0: thermal-sensor@c263000 { 3732 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 3733 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3734 <0 0x0c222000 0 0x1ff>; /* SROT */ 3735 #qcom,sensors = <16>; 3736 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3737 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3738 interrupt-names = "uplow", "critical"; 3739 #thermal-sensor-cells = <1>; 3740 }; 3741 3742 tsens1: thermal-sensor@c265000 { 3743 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 3744 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3745 <0 0x0c223000 0 0x1ff>; /* SROT */ 3746 #qcom,sensors = <9>; 3747 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3748 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3749 interrupt-names = "uplow", "critical"; 3750 #thermal-sensor-cells = <1>; 3751 }; 3752 3753 aoss_qmp: power-controller@c300000 { 3754 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; 3755 reg = <0 0x0c300000 0 0x400>; 3756 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3757 IPCC_MPROC_SIGNAL_GLINK_QMP 3758 IRQ_TYPE_EDGE_RISING>; 3759 mboxes = <&ipcc IPCC_CLIENT_AOP 3760 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3761 3762 #clock-cells = <0>; 3763 }; 3764 3765 sram@c3f0000 { 3766 compatible = "qcom,rpmh-stats"; 3767 reg = <0 0x0c3f0000 0 0x400>; 3768 }; 3769 3770 spmi_bus: spmi@c440000 { 3771 compatible = "qcom,spmi-pmic-arb"; 3772 reg = <0x0 0x0c440000 0x0 0x0001100>, 3773 <0x0 0x0c600000 0x0 0x2000000>, 3774 <0x0 0x0e600000 0x0 0x0100000>, 3775 <0x0 0x0e700000 0x0 0x00a0000>, 3776 <0x0 0x0c40a000 0x0 0x0026000>; 3777 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3778 interrupt-names = "periph_irq"; 3779 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3780 qcom,ee = <0>; 3781 qcom,channel = <0>; 3782 #address-cells = <2>; 3783 #size-cells = <0>; 3784 interrupt-controller; 3785 #interrupt-cells = <4>; 3786 }; 3787 3788 tlmm: pinctrl@f100000 { 3789 compatible = "qcom,sm8250-pinctrl"; 3790 reg = <0 0x0f100000 0 0x300000>, 3791 <0 0x0f500000 0 0x300000>, 3792 <0 0x0f900000 0 0x300000>; 3793 reg-names = "west", "south", "north"; 3794 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3795 gpio-controller; 3796 #gpio-cells = <2>; 3797 interrupt-controller; 3798 #interrupt-cells = <2>; 3799 gpio-ranges = <&tlmm 0 0 181>; 3800 wakeup-parent = <&pdc>; 3801 3802 cci0_default: cci0-default { 3803 cci0_i2c0_default: cci0-i2c0-default { 3804 /* SDA, SCL */ 3805 pins = "gpio101", "gpio102"; 3806 function = "cci_i2c"; 3807 3808 bias-pull-up; 3809 drive-strength = <2>; /* 2 mA */ 3810 }; 3811 3812 cci0_i2c1_default: cci0-i2c1-default { 3813 /* SDA, SCL */ 3814 pins = "gpio103", "gpio104"; 3815 function = "cci_i2c"; 3816 3817 bias-pull-up; 3818 drive-strength = <2>; /* 2 mA */ 3819 }; 3820 }; 3821 3822 cci0_sleep: cci0-sleep { 3823 cci0_i2c0_sleep: cci0-i2c0-sleep { 3824 /* SDA, SCL */ 3825 pins = "gpio101", "gpio102"; 3826 function = "cci_i2c"; 3827 3828 drive-strength = <2>; /* 2 mA */ 3829 bias-pull-down; 3830 }; 3831 3832 cci0_i2c1_sleep: cci0-i2c1-sleep { 3833 /* SDA, SCL */ 3834 pins = "gpio103", "gpio104"; 3835 function = "cci_i2c"; 3836 3837 drive-strength = <2>; /* 2 mA */ 3838 bias-pull-down; 3839 }; 3840 }; 3841 3842 cci1_default: cci1-default { 3843 cci1_i2c0_default: cci1-i2c0-default { 3844 /* SDA, SCL */ 3845 pins = "gpio105","gpio106"; 3846 function = "cci_i2c"; 3847 3848 bias-pull-up; 3849 drive-strength = <2>; /* 2 mA */ 3850 }; 3851 3852 cci1_i2c1_default: cci1-i2c1-default { 3853 /* SDA, SCL */ 3854 pins = "gpio107","gpio108"; 3855 function = "cci_i2c"; 3856 3857 bias-pull-up; 3858 drive-strength = <2>; /* 2 mA */ 3859 }; 3860 }; 3861 3862 cci1_sleep: cci1-sleep { 3863 cci1_i2c0_sleep: cci1-i2c0-sleep { 3864 /* SDA, SCL */ 3865 pins = "gpio105","gpio106"; 3866 function = "cci_i2c"; 3867 3868 bias-pull-down; 3869 drive-strength = <2>; /* 2 mA */ 3870 }; 3871 3872 cci1_i2c1_sleep: cci1-i2c1-sleep { 3873 /* SDA, SCL */ 3874 pins = "gpio107","gpio108"; 3875 function = "cci_i2c"; 3876 3877 bias-pull-down; 3878 drive-strength = <2>; /* 2 mA */ 3879 }; 3880 }; 3881 3882 pri_mi2s_active: pri-mi2s-active { 3883 sclk { 3884 pins = "gpio138"; 3885 function = "mi2s0_sck"; 3886 drive-strength = <8>; 3887 bias-disable; 3888 }; 3889 3890 ws { 3891 pins = "gpio141"; 3892 function = "mi2s0_ws"; 3893 drive-strength = <8>; 3894 output-high; 3895 }; 3896 3897 data0 { 3898 pins = "gpio139"; 3899 function = "mi2s0_data0"; 3900 drive-strength = <8>; 3901 bias-disable; 3902 output-high; 3903 }; 3904 3905 data1 { 3906 pins = "gpio140"; 3907 function = "mi2s0_data1"; 3908 drive-strength = <8>; 3909 output-high; 3910 }; 3911 }; 3912 3913 qup_i2c0_default: qup-i2c0-default { 3914 mux { 3915 pins = "gpio28", "gpio29"; 3916 function = "qup0"; 3917 }; 3918 3919 config { 3920 pins = "gpio28", "gpio29"; 3921 drive-strength = <2>; 3922 bias-disable; 3923 }; 3924 }; 3925 3926 qup_i2c1_default: qup-i2c1-default { 3927 pinmux { 3928 pins = "gpio4", "gpio5"; 3929 function = "qup1"; 3930 }; 3931 3932 config { 3933 pins = "gpio4", "gpio5"; 3934 drive-strength = <2>; 3935 bias-disable; 3936 }; 3937 }; 3938 3939 qup_i2c2_default: qup-i2c2-default { 3940 mux { 3941 pins = "gpio115", "gpio116"; 3942 function = "qup2"; 3943 }; 3944 3945 config { 3946 pins = "gpio115", "gpio116"; 3947 drive-strength = <2>; 3948 bias-disable; 3949 }; 3950 }; 3951 3952 qup_i2c3_default: qup-i2c3-default { 3953 mux { 3954 pins = "gpio119", "gpio120"; 3955 function = "qup3"; 3956 }; 3957 3958 config { 3959 pins = "gpio119", "gpio120"; 3960 drive-strength = <2>; 3961 bias-disable; 3962 }; 3963 }; 3964 3965 qup_i2c4_default: qup-i2c4-default { 3966 mux { 3967 pins = "gpio8", "gpio9"; 3968 function = "qup4"; 3969 }; 3970 3971 config { 3972 pins = "gpio8", "gpio9"; 3973 drive-strength = <2>; 3974 bias-disable; 3975 }; 3976 }; 3977 3978 qup_i2c5_default: qup-i2c5-default { 3979 mux { 3980 pins = "gpio12", "gpio13"; 3981 function = "qup5"; 3982 }; 3983 3984 config { 3985 pins = "gpio12", "gpio13"; 3986 drive-strength = <2>; 3987 bias-disable; 3988 }; 3989 }; 3990 3991 qup_i2c6_default: qup-i2c6-default { 3992 mux { 3993 pins = "gpio16", "gpio17"; 3994 function = "qup6"; 3995 }; 3996 3997 config { 3998 pins = "gpio16", "gpio17"; 3999 drive-strength = <2>; 4000 bias-disable; 4001 }; 4002 }; 4003 4004 qup_i2c7_default: qup-i2c7-default { 4005 mux { 4006 pins = "gpio20", "gpio21"; 4007 function = "qup7"; 4008 }; 4009 4010 config { 4011 pins = "gpio20", "gpio21"; 4012 drive-strength = <2>; 4013 bias-disable; 4014 }; 4015 }; 4016 4017 qup_i2c8_default: qup-i2c8-default { 4018 mux { 4019 pins = "gpio24", "gpio25"; 4020 function = "qup8"; 4021 }; 4022 4023 config { 4024 pins = "gpio24", "gpio25"; 4025 drive-strength = <2>; 4026 bias-disable; 4027 }; 4028 }; 4029 4030 qup_i2c9_default: qup-i2c9-default { 4031 mux { 4032 pins = "gpio125", "gpio126"; 4033 function = "qup9"; 4034 }; 4035 4036 config { 4037 pins = "gpio125", "gpio126"; 4038 drive-strength = <2>; 4039 bias-disable; 4040 }; 4041 }; 4042 4043 qup_i2c10_default: qup-i2c10-default { 4044 mux { 4045 pins = "gpio129", "gpio130"; 4046 function = "qup10"; 4047 }; 4048 4049 config { 4050 pins = "gpio129", "gpio130"; 4051 drive-strength = <2>; 4052 bias-disable; 4053 }; 4054 }; 4055 4056 qup_i2c11_default: qup-i2c11-default { 4057 mux { 4058 pins = "gpio60", "gpio61"; 4059 function = "qup11"; 4060 }; 4061 4062 config { 4063 pins = "gpio60", "gpio61"; 4064 drive-strength = <2>; 4065 bias-disable; 4066 }; 4067 }; 4068 4069 qup_i2c12_default: qup-i2c12-default { 4070 mux { 4071 pins = "gpio32", "gpio33"; 4072 function = "qup12"; 4073 }; 4074 4075 config { 4076 pins = "gpio32", "gpio33"; 4077 drive-strength = <2>; 4078 bias-disable; 4079 }; 4080 }; 4081 4082 qup_i2c13_default: qup-i2c13-default { 4083 mux { 4084 pins = "gpio36", "gpio37"; 4085 function = "qup13"; 4086 }; 4087 4088 config { 4089 pins = "gpio36", "gpio37"; 4090 drive-strength = <2>; 4091 bias-disable; 4092 }; 4093 }; 4094 4095 qup_i2c14_default: qup-i2c14-default { 4096 mux { 4097 pins = "gpio40", "gpio41"; 4098 function = "qup14"; 4099 }; 4100 4101 config { 4102 pins = "gpio40", "gpio41"; 4103 drive-strength = <2>; 4104 bias-disable; 4105 }; 4106 }; 4107 4108 qup_i2c15_default: qup-i2c15-default { 4109 mux { 4110 pins = "gpio44", "gpio45"; 4111 function = "qup15"; 4112 }; 4113 4114 config { 4115 pins = "gpio44", "gpio45"; 4116 drive-strength = <2>; 4117 bias-disable; 4118 }; 4119 }; 4120 4121 qup_i2c16_default: qup-i2c16-default { 4122 mux { 4123 pins = "gpio48", "gpio49"; 4124 function = "qup16"; 4125 }; 4126 4127 config { 4128 pins = "gpio48", "gpio49"; 4129 drive-strength = <2>; 4130 bias-disable; 4131 }; 4132 }; 4133 4134 qup_i2c17_default: qup-i2c17-default { 4135 mux { 4136 pins = "gpio52", "gpio53"; 4137 function = "qup17"; 4138 }; 4139 4140 config { 4141 pins = "gpio52", "gpio53"; 4142 drive-strength = <2>; 4143 bias-disable; 4144 }; 4145 }; 4146 4147 qup_i2c18_default: qup-i2c18-default { 4148 mux { 4149 pins = "gpio56", "gpio57"; 4150 function = "qup18"; 4151 }; 4152 4153 config { 4154 pins = "gpio56", "gpio57"; 4155 drive-strength = <2>; 4156 bias-disable; 4157 }; 4158 }; 4159 4160 qup_i2c19_default: qup-i2c19-default { 4161 mux { 4162 pins = "gpio0", "gpio1"; 4163 function = "qup19"; 4164 }; 4165 4166 config { 4167 pins = "gpio0", "gpio1"; 4168 drive-strength = <2>; 4169 bias-disable; 4170 }; 4171 }; 4172 4173 qup_spi0_cs: qup-spi0-cs { 4174 pins = "gpio31"; 4175 function = "qup0"; 4176 }; 4177 4178 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 4179 pins = "gpio31"; 4180 function = "gpio"; 4181 }; 4182 4183 qup_spi0_data_clk: qup-spi0-data-clk { 4184 pins = "gpio28", "gpio29", 4185 "gpio30"; 4186 function = "qup0"; 4187 }; 4188 4189 qup_spi1_cs: qup-spi1-cs { 4190 pins = "gpio7"; 4191 function = "qup1"; 4192 }; 4193 4194 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 4195 pins = "gpio7"; 4196 function = "gpio"; 4197 }; 4198 4199 qup_spi1_data_clk: qup-spi1-data-clk { 4200 pins = "gpio4", "gpio5", 4201 "gpio6"; 4202 function = "qup1"; 4203 }; 4204 4205 qup_spi2_cs: qup-spi2-cs { 4206 pins = "gpio118"; 4207 function = "qup2"; 4208 }; 4209 4210 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 4211 pins = "gpio118"; 4212 function = "gpio"; 4213 }; 4214 4215 qup_spi2_data_clk: qup-spi2-data-clk { 4216 pins = "gpio115", "gpio116", 4217 "gpio117"; 4218 function = "qup2"; 4219 }; 4220 4221 qup_spi3_cs: qup-spi3-cs { 4222 pins = "gpio122"; 4223 function = "qup3"; 4224 }; 4225 4226 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 4227 pins = "gpio122"; 4228 function = "gpio"; 4229 }; 4230 4231 qup_spi3_data_clk: qup-spi3-data-clk { 4232 pins = "gpio119", "gpio120", 4233 "gpio121"; 4234 function = "qup3"; 4235 }; 4236 4237 qup_spi4_cs: qup-spi4-cs { 4238 pins = "gpio11"; 4239 function = "qup4"; 4240 }; 4241 4242 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 4243 pins = "gpio11"; 4244 function = "gpio"; 4245 }; 4246 4247 qup_spi4_data_clk: qup-spi4-data-clk { 4248 pins = "gpio8", "gpio9", 4249 "gpio10"; 4250 function = "qup4"; 4251 }; 4252 4253 qup_spi5_cs: qup-spi5-cs { 4254 pins = "gpio15"; 4255 function = "qup5"; 4256 }; 4257 4258 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 4259 pins = "gpio15"; 4260 function = "gpio"; 4261 }; 4262 4263 qup_spi5_data_clk: qup-spi5-data-clk { 4264 pins = "gpio12", "gpio13", 4265 "gpio14"; 4266 function = "qup5"; 4267 }; 4268 4269 qup_spi6_cs: qup-spi6-cs { 4270 pins = "gpio19"; 4271 function = "qup6"; 4272 }; 4273 4274 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 4275 pins = "gpio19"; 4276 function = "gpio"; 4277 }; 4278 4279 qup_spi6_data_clk: qup-spi6-data-clk { 4280 pins = "gpio16", "gpio17", 4281 "gpio18"; 4282 function = "qup6"; 4283 }; 4284 4285 qup_spi7_cs: qup-spi7-cs { 4286 pins = "gpio23"; 4287 function = "qup7"; 4288 }; 4289 4290 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 4291 pins = "gpio23"; 4292 function = "gpio"; 4293 }; 4294 4295 qup_spi7_data_clk: qup-spi7-data-clk { 4296 pins = "gpio20", "gpio21", 4297 "gpio22"; 4298 function = "qup7"; 4299 }; 4300 4301 qup_spi8_cs: qup-spi8-cs { 4302 pins = "gpio27"; 4303 function = "qup8"; 4304 }; 4305 4306 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 4307 pins = "gpio27"; 4308 function = "gpio"; 4309 }; 4310 4311 qup_spi8_data_clk: qup-spi8-data-clk { 4312 pins = "gpio24", "gpio25", 4313 "gpio26"; 4314 function = "qup8"; 4315 }; 4316 4317 qup_spi9_cs: qup-spi9-cs { 4318 pins = "gpio128"; 4319 function = "qup9"; 4320 }; 4321 4322 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 4323 pins = "gpio128"; 4324 function = "gpio"; 4325 }; 4326 4327 qup_spi9_data_clk: qup-spi9-data-clk { 4328 pins = "gpio125", "gpio126", 4329 "gpio127"; 4330 function = "qup9"; 4331 }; 4332 4333 qup_spi10_cs: qup-spi10-cs { 4334 pins = "gpio132"; 4335 function = "qup10"; 4336 }; 4337 4338 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 4339 pins = "gpio132"; 4340 function = "gpio"; 4341 }; 4342 4343 qup_spi10_data_clk: qup-spi10-data-clk { 4344 pins = "gpio129", "gpio130", 4345 "gpio131"; 4346 function = "qup10"; 4347 }; 4348 4349 qup_spi11_cs: qup-spi11-cs { 4350 pins = "gpio63"; 4351 function = "qup11"; 4352 }; 4353 4354 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 4355 pins = "gpio63"; 4356 function = "gpio"; 4357 }; 4358 4359 qup_spi11_data_clk: qup-spi11-data-clk { 4360 pins = "gpio60", "gpio61", 4361 "gpio62"; 4362 function = "qup11"; 4363 }; 4364 4365 qup_spi12_cs: qup-spi12-cs { 4366 pins = "gpio35"; 4367 function = "qup12"; 4368 }; 4369 4370 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 4371 pins = "gpio35"; 4372 function = "gpio"; 4373 }; 4374 4375 qup_spi12_data_clk: qup-spi12-data-clk { 4376 pins = "gpio32", "gpio33", 4377 "gpio34"; 4378 function = "qup12"; 4379 }; 4380 4381 qup_spi13_cs: qup-spi13-cs { 4382 pins = "gpio39"; 4383 function = "qup13"; 4384 }; 4385 4386 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 4387 pins = "gpio39"; 4388 function = "gpio"; 4389 }; 4390 4391 qup_spi13_data_clk: qup-spi13-data-clk { 4392 pins = "gpio36", "gpio37", 4393 "gpio38"; 4394 function = "qup13"; 4395 }; 4396 4397 qup_spi14_cs: qup-spi14-cs { 4398 pins = "gpio43"; 4399 function = "qup14"; 4400 }; 4401 4402 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 4403 pins = "gpio43"; 4404 function = "gpio"; 4405 }; 4406 4407 qup_spi14_data_clk: qup-spi14-data-clk { 4408 pins = "gpio40", "gpio41", 4409 "gpio42"; 4410 function = "qup14"; 4411 }; 4412 4413 qup_spi15_cs: qup-spi15-cs { 4414 pins = "gpio47"; 4415 function = "qup15"; 4416 }; 4417 4418 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 4419 pins = "gpio47"; 4420 function = "gpio"; 4421 }; 4422 4423 qup_spi15_data_clk: qup-spi15-data-clk { 4424 pins = "gpio44", "gpio45", 4425 "gpio46"; 4426 function = "qup15"; 4427 }; 4428 4429 qup_spi16_cs: qup-spi16-cs { 4430 pins = "gpio51"; 4431 function = "qup16"; 4432 }; 4433 4434 qup_spi16_cs_gpio: qup-spi16-cs-gpio { 4435 pins = "gpio51"; 4436 function = "gpio"; 4437 }; 4438 4439 qup_spi16_data_clk: qup-spi16-data-clk { 4440 pins = "gpio48", "gpio49", 4441 "gpio50"; 4442 function = "qup16"; 4443 }; 4444 4445 qup_spi17_cs: qup-spi17-cs { 4446 pins = "gpio55"; 4447 function = "qup17"; 4448 }; 4449 4450 qup_spi17_cs_gpio: qup-spi17-cs-gpio { 4451 pins = "gpio55"; 4452 function = "gpio"; 4453 }; 4454 4455 qup_spi17_data_clk: qup-spi17-data-clk { 4456 pins = "gpio52", "gpio53", 4457 "gpio54"; 4458 function = "qup17"; 4459 }; 4460 4461 qup_spi18_cs: qup-spi18-cs { 4462 pins = "gpio59"; 4463 function = "qup18"; 4464 }; 4465 4466 qup_spi18_cs_gpio: qup-spi18-cs-gpio { 4467 pins = "gpio59"; 4468 function = "gpio"; 4469 }; 4470 4471 qup_spi18_data_clk: qup-spi18-data-clk { 4472 pins = "gpio56", "gpio57", 4473 "gpio58"; 4474 function = "qup18"; 4475 }; 4476 4477 qup_spi19_cs: qup-spi19-cs { 4478 pins = "gpio3"; 4479 function = "qup19"; 4480 }; 4481 4482 qup_spi19_cs_gpio: qup-spi19-cs-gpio { 4483 pins = "gpio3"; 4484 function = "gpio"; 4485 }; 4486 4487 qup_spi19_data_clk: qup-spi19-data-clk { 4488 pins = "gpio0", "gpio1", 4489 "gpio2"; 4490 function = "qup19"; 4491 }; 4492 4493 qup_uart2_default: qup-uart2-default { 4494 mux { 4495 pins = "gpio117", "gpio118"; 4496 function = "qup2"; 4497 }; 4498 }; 4499 4500 qup_uart6_default: qup-uart6-default { 4501 mux { 4502 pins = "gpio16", "gpio17", 4503 "gpio18", "gpio19"; 4504 function = "qup6"; 4505 }; 4506 }; 4507 4508 qup_uart12_default: qup-uart12-default { 4509 mux { 4510 pins = "gpio34", "gpio35"; 4511 function = "qup12"; 4512 }; 4513 }; 4514 4515 qup_uart17_default: qup-uart17-default { 4516 mux { 4517 pins = "gpio52", "gpio53", 4518 "gpio54", "gpio55"; 4519 function = "qup17"; 4520 }; 4521 }; 4522 4523 qup_uart18_default: qup-uart18-default { 4524 mux { 4525 pins = "gpio58", "gpio59"; 4526 function = "qup18"; 4527 }; 4528 }; 4529 4530 tert_mi2s_active: tert-mi2s-active { 4531 sck { 4532 pins = "gpio133"; 4533 function = "mi2s2_sck"; 4534 drive-strength = <8>; 4535 bias-disable; 4536 }; 4537 4538 data0 { 4539 pins = "gpio134"; 4540 function = "mi2s2_data0"; 4541 drive-strength = <8>; 4542 bias-disable; 4543 output-high; 4544 }; 4545 4546 ws { 4547 pins = "gpio135"; 4548 function = "mi2s2_ws"; 4549 drive-strength = <8>; 4550 output-high; 4551 }; 4552 }; 4553 4554 sdc2_sleep_state: sdc2-sleep { 4555 clk { 4556 pins = "sdc2_clk"; 4557 drive-strength = <2>; 4558 bias-disable; 4559 }; 4560 4561 cmd { 4562 pins = "sdc2_cmd"; 4563 drive-strength = <2>; 4564 bias-pull-up; 4565 }; 4566 4567 data { 4568 pins = "sdc2_data"; 4569 drive-strength = <2>; 4570 bias-pull-up; 4571 }; 4572 }; 4573 4574 pcie0_default_state: pcie0-default { 4575 perst { 4576 pins = "gpio79"; 4577 function = "gpio"; 4578 drive-strength = <2>; 4579 bias-pull-down; 4580 }; 4581 4582 clkreq { 4583 pins = "gpio80"; 4584 function = "pci_e0"; 4585 drive-strength = <2>; 4586 bias-pull-up; 4587 }; 4588 4589 wake { 4590 pins = "gpio81"; 4591 function = "gpio"; 4592 drive-strength = <2>; 4593 bias-pull-up; 4594 }; 4595 }; 4596 4597 pcie1_default_state: pcie1-default { 4598 perst { 4599 pins = "gpio82"; 4600 function = "gpio"; 4601 drive-strength = <2>; 4602 bias-pull-down; 4603 }; 4604 4605 clkreq { 4606 pins = "gpio83"; 4607 function = "pci_e1"; 4608 drive-strength = <2>; 4609 bias-pull-up; 4610 }; 4611 4612 wake { 4613 pins = "gpio84"; 4614 function = "gpio"; 4615 drive-strength = <2>; 4616 bias-pull-up; 4617 }; 4618 }; 4619 4620 pcie2_default_state: pcie2-default { 4621 perst { 4622 pins = "gpio85"; 4623 function = "gpio"; 4624 drive-strength = <2>; 4625 bias-pull-down; 4626 }; 4627 4628 clkreq { 4629 pins = "gpio86"; 4630 function = "pci_e2"; 4631 drive-strength = <2>; 4632 bias-pull-up; 4633 }; 4634 4635 wake { 4636 pins = "gpio87"; 4637 function = "gpio"; 4638 drive-strength = <2>; 4639 bias-pull-up; 4640 }; 4641 }; 4642 }; 4643 4644 apps_smmu: iommu@15000000 { 4645 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 4646 reg = <0 0x15000000 0 0x100000>; 4647 #iommu-cells = <2>; 4648 #global-interrupts = <2>; 4649 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 4650 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4651 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4652 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4653 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4654 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4655 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4656 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4657 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4658 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4659 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4660 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4661 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4662 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4663 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4664 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4665 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4666 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4667 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4668 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4669 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4670 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4671 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4672 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4673 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4674 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4675 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4676 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4677 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4678 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4679 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4680 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4681 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4682 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4683 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4684 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4685 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4686 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4687 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4688 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4689 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4690 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4691 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4692 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4693 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4694 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4695 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4696 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4697 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4698 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4699 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4700 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4701 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4702 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4703 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4704 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4705 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4706 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4707 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4708 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4709 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4710 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4711 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4712 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4713 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4714 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4715 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4716 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4717 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4718 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4719 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4720 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4721 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4722 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4723 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4724 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4725 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4726 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4727 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4728 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4729 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4730 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4731 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4732 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4733 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4734 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4735 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4736 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4737 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4738 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4739 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4740 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4741 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4742 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4743 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4744 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4745 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 4746 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 4747 }; 4748 4749 adsp: remoteproc@17300000 { 4750 compatible = "qcom,sm8250-adsp-pas"; 4751 reg = <0 0x17300000 0 0x100>; 4752 4753 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 4754 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4755 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4756 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4757 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4758 interrupt-names = "wdog", "fatal", "ready", 4759 "handover", "stop-ack"; 4760 4761 clocks = <&rpmhcc RPMH_CXO_CLK>; 4762 clock-names = "xo"; 4763 4764 power-domains = <&rpmhpd SM8250_LCX>, 4765 <&rpmhpd SM8250_LMX>; 4766 power-domain-names = "lcx", "lmx"; 4767 4768 memory-region = <&adsp_mem>; 4769 4770 qcom,qmp = <&aoss_qmp>; 4771 4772 qcom,smem-states = <&smp2p_adsp_out 0>; 4773 qcom,smem-state-names = "stop"; 4774 4775 status = "disabled"; 4776 4777 glink-edge { 4778 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4779 IPCC_MPROC_SIGNAL_GLINK_QMP 4780 IRQ_TYPE_EDGE_RISING>; 4781 mboxes = <&ipcc IPCC_CLIENT_LPASS 4782 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4783 4784 label = "lpass"; 4785 qcom,remote-pid = <2>; 4786 4787 apr { 4788 compatible = "qcom,apr-v2"; 4789 qcom,glink-channels = "apr_audio_svc"; 4790 qcom,domain = <APR_DOMAIN_ADSP>; 4791 #address-cells = <1>; 4792 #size-cells = <0>; 4793 4794 apr-service@3 { 4795 reg = <APR_SVC_ADSP_CORE>; 4796 compatible = "qcom,q6core"; 4797 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4798 }; 4799 4800 q6afe: apr-service@4 { 4801 compatible = "qcom,q6afe"; 4802 reg = <APR_SVC_AFE>; 4803 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4804 q6afedai: dais { 4805 compatible = "qcom,q6afe-dais"; 4806 #address-cells = <1>; 4807 #size-cells = <0>; 4808 #sound-dai-cells = <1>; 4809 }; 4810 4811 q6afecc: cc { 4812 compatible = "qcom,q6afe-clocks"; 4813 #clock-cells = <2>; 4814 }; 4815 }; 4816 4817 q6asm: apr-service@7 { 4818 compatible = "qcom,q6asm"; 4819 reg = <APR_SVC_ASM>; 4820 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4821 q6asmdai: dais { 4822 compatible = "qcom,q6asm-dais"; 4823 #address-cells = <1>; 4824 #size-cells = <0>; 4825 #sound-dai-cells = <1>; 4826 iommus = <&apps_smmu 0x1801 0x0>; 4827 }; 4828 }; 4829 4830 q6adm: apr-service@8 { 4831 compatible = "qcom,q6adm"; 4832 reg = <APR_SVC_ADM>; 4833 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4834 q6routing: routing { 4835 compatible = "qcom,q6adm-routing"; 4836 #sound-dai-cells = <0>; 4837 }; 4838 }; 4839 }; 4840 4841 fastrpc { 4842 compatible = "qcom,fastrpc"; 4843 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4844 label = "adsp"; 4845 qcom,non-secure-domain; 4846 #address-cells = <1>; 4847 #size-cells = <0>; 4848 4849 compute-cb@3 { 4850 compatible = "qcom,fastrpc-compute-cb"; 4851 reg = <3>; 4852 iommus = <&apps_smmu 0x1803 0x0>; 4853 }; 4854 4855 compute-cb@4 { 4856 compatible = "qcom,fastrpc-compute-cb"; 4857 reg = <4>; 4858 iommus = <&apps_smmu 0x1804 0x0>; 4859 }; 4860 4861 compute-cb@5 { 4862 compatible = "qcom,fastrpc-compute-cb"; 4863 reg = <5>; 4864 iommus = <&apps_smmu 0x1805 0x0>; 4865 }; 4866 }; 4867 }; 4868 }; 4869 4870 intc: interrupt-controller@17a00000 { 4871 compatible = "arm,gic-v3"; 4872 #interrupt-cells = <3>; 4873 interrupt-controller; 4874 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4875 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4876 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4877 }; 4878 4879 watchdog@17c10000 { 4880 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 4881 reg = <0 0x17c10000 0 0x1000>; 4882 clocks = <&sleep_clk>; 4883 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4884 }; 4885 4886 timer@17c20000 { 4887 #address-cells = <1>; 4888 #size-cells = <1>; 4889 ranges = <0 0 0 0x20000000>; 4890 compatible = "arm,armv7-timer-mem"; 4891 reg = <0x0 0x17c20000 0x0 0x1000>; 4892 clock-frequency = <19200000>; 4893 4894 frame@17c21000 { 4895 frame-number = <0>; 4896 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4897 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4898 reg = <0x17c21000 0x1000>, 4899 <0x17c22000 0x1000>; 4900 }; 4901 4902 frame@17c23000 { 4903 frame-number = <1>; 4904 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4905 reg = <0x17c23000 0x1000>; 4906 status = "disabled"; 4907 }; 4908 4909 frame@17c25000 { 4910 frame-number = <2>; 4911 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4912 reg = <0x17c25000 0x1000>; 4913 status = "disabled"; 4914 }; 4915 4916 frame@17c27000 { 4917 frame-number = <3>; 4918 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4919 reg = <0x17c27000 0x1000>; 4920 status = "disabled"; 4921 }; 4922 4923 frame@17c29000 { 4924 frame-number = <4>; 4925 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4926 reg = <0x17c29000 0x1000>; 4927 status = "disabled"; 4928 }; 4929 4930 frame@17c2b000 { 4931 frame-number = <5>; 4932 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4933 reg = <0x17c2b000 0x1000>; 4934 status = "disabled"; 4935 }; 4936 4937 frame@17c2d000 { 4938 frame-number = <6>; 4939 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4940 reg = <0x17c2d000 0x1000>; 4941 status = "disabled"; 4942 }; 4943 }; 4944 4945 apps_rsc: rsc@18200000 { 4946 label = "apps_rsc"; 4947 compatible = "qcom,rpmh-rsc"; 4948 reg = <0x0 0x18200000 0x0 0x10000>, 4949 <0x0 0x18210000 0x0 0x10000>, 4950 <0x0 0x18220000 0x0 0x10000>; 4951 reg-names = "drv-0", "drv-1", "drv-2"; 4952 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4953 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4954 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4955 qcom,tcs-offset = <0xd00>; 4956 qcom,drv-id = <2>; 4957 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 4958 <WAKE_TCS 3>, <CONTROL_TCS 1>; 4959 4960 rpmhcc: clock-controller { 4961 compatible = "qcom,sm8250-rpmh-clk"; 4962 #clock-cells = <1>; 4963 clock-names = "xo"; 4964 clocks = <&xo_board>; 4965 }; 4966 4967 rpmhpd: power-controller { 4968 compatible = "qcom,sm8250-rpmhpd"; 4969 #power-domain-cells = <1>; 4970 operating-points-v2 = <&rpmhpd_opp_table>; 4971 4972 rpmhpd_opp_table: opp-table { 4973 compatible = "operating-points-v2"; 4974 4975 rpmhpd_opp_ret: opp1 { 4976 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4977 }; 4978 4979 rpmhpd_opp_min_svs: opp2 { 4980 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4981 }; 4982 4983 rpmhpd_opp_low_svs: opp3 { 4984 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4985 }; 4986 4987 rpmhpd_opp_svs: opp4 { 4988 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4989 }; 4990 4991 rpmhpd_opp_svs_l1: opp5 { 4992 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4993 }; 4994 4995 rpmhpd_opp_nom: opp6 { 4996 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4997 }; 4998 4999 rpmhpd_opp_nom_l1: opp7 { 5000 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5001 }; 5002 5003 rpmhpd_opp_nom_l2: opp8 { 5004 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5005 }; 5006 5007 rpmhpd_opp_turbo: opp9 { 5008 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5009 }; 5010 5011 rpmhpd_opp_turbo_l1: opp10 { 5012 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5013 }; 5014 }; 5015 }; 5016 5017 apps_bcm_voter: bcm-voter { 5018 compatible = "qcom,bcm-voter"; 5019 }; 5020 }; 5021 5022 epss_l3: interconnect@18590000 { 5023 compatible = "qcom,sm8250-epss-l3"; 5024 reg = <0 0x18590000 0 0x1000>; 5025 5026 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5027 clock-names = "xo", "alternate"; 5028 5029 #interconnect-cells = <1>; 5030 }; 5031 5032 cpufreq_hw: cpufreq@18591000 { 5033 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 5034 reg = <0 0x18591000 0 0x1000>, 5035 <0 0x18592000 0 0x1000>, 5036 <0 0x18593000 0 0x1000>; 5037 reg-names = "freq-domain0", "freq-domain1", 5038 "freq-domain2"; 5039 5040 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5041 clock-names = "xo", "alternate"; 5042 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5043 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5044 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5045 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 5046 #freq-domain-cells = <1>; 5047 }; 5048 }; 5049 5050 timer { 5051 compatible = "arm,armv8-timer"; 5052 interrupts = <GIC_PPI 13 5053 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5054 <GIC_PPI 14 5055 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5056 <GIC_PPI 11 5057 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5058 <GIC_PPI 10 5059 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5060 }; 5061 5062 thermal-zones { 5063 cpu0-thermal { 5064 polling-delay-passive = <250>; 5065 polling-delay = <1000>; 5066 5067 thermal-sensors = <&tsens0 1>; 5068 5069 trips { 5070 cpu0_alert0: trip-point0 { 5071 temperature = <90000>; 5072 hysteresis = <2000>; 5073 type = "passive"; 5074 }; 5075 5076 cpu0_alert1: trip-point1 { 5077 temperature = <95000>; 5078 hysteresis = <2000>; 5079 type = "passive"; 5080 }; 5081 5082 cpu0_crit: cpu_crit { 5083 temperature = <110000>; 5084 hysteresis = <1000>; 5085 type = "critical"; 5086 }; 5087 }; 5088 5089 cooling-maps { 5090 map0 { 5091 trip = <&cpu0_alert0>; 5092 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5093 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5094 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5095 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5096 }; 5097 map1 { 5098 trip = <&cpu0_alert1>; 5099 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5100 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5101 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5102 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5103 }; 5104 }; 5105 }; 5106 5107 cpu1-thermal { 5108 polling-delay-passive = <250>; 5109 polling-delay = <1000>; 5110 5111 thermal-sensors = <&tsens0 2>; 5112 5113 trips { 5114 cpu1_alert0: trip-point0 { 5115 temperature = <90000>; 5116 hysteresis = <2000>; 5117 type = "passive"; 5118 }; 5119 5120 cpu1_alert1: trip-point1 { 5121 temperature = <95000>; 5122 hysteresis = <2000>; 5123 type = "passive"; 5124 }; 5125 5126 cpu1_crit: cpu_crit { 5127 temperature = <110000>; 5128 hysteresis = <1000>; 5129 type = "critical"; 5130 }; 5131 }; 5132 5133 cooling-maps { 5134 map0 { 5135 trip = <&cpu1_alert0>; 5136 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5137 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5138 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5139 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5140 }; 5141 map1 { 5142 trip = <&cpu1_alert1>; 5143 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5144 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5145 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5146 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5147 }; 5148 }; 5149 }; 5150 5151 cpu2-thermal { 5152 polling-delay-passive = <250>; 5153 polling-delay = <1000>; 5154 5155 thermal-sensors = <&tsens0 3>; 5156 5157 trips { 5158 cpu2_alert0: trip-point0 { 5159 temperature = <90000>; 5160 hysteresis = <2000>; 5161 type = "passive"; 5162 }; 5163 5164 cpu2_alert1: trip-point1 { 5165 temperature = <95000>; 5166 hysteresis = <2000>; 5167 type = "passive"; 5168 }; 5169 5170 cpu2_crit: cpu_crit { 5171 temperature = <110000>; 5172 hysteresis = <1000>; 5173 type = "critical"; 5174 }; 5175 }; 5176 5177 cooling-maps { 5178 map0 { 5179 trip = <&cpu2_alert0>; 5180 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5181 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5182 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5183 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5184 }; 5185 map1 { 5186 trip = <&cpu2_alert1>; 5187 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5188 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5189 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5190 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5191 }; 5192 }; 5193 }; 5194 5195 cpu3-thermal { 5196 polling-delay-passive = <250>; 5197 polling-delay = <1000>; 5198 5199 thermal-sensors = <&tsens0 4>; 5200 5201 trips { 5202 cpu3_alert0: trip-point0 { 5203 temperature = <90000>; 5204 hysteresis = <2000>; 5205 type = "passive"; 5206 }; 5207 5208 cpu3_alert1: trip-point1 { 5209 temperature = <95000>; 5210 hysteresis = <2000>; 5211 type = "passive"; 5212 }; 5213 5214 cpu3_crit: cpu_crit { 5215 temperature = <110000>; 5216 hysteresis = <1000>; 5217 type = "critical"; 5218 }; 5219 }; 5220 5221 cooling-maps { 5222 map0 { 5223 trip = <&cpu3_alert0>; 5224 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5225 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5226 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5227 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5228 }; 5229 map1 { 5230 trip = <&cpu3_alert1>; 5231 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5232 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5233 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5234 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5235 }; 5236 }; 5237 }; 5238 5239 cpu4-top-thermal { 5240 polling-delay-passive = <250>; 5241 polling-delay = <1000>; 5242 5243 thermal-sensors = <&tsens0 7>; 5244 5245 trips { 5246 cpu4_top_alert0: trip-point0 { 5247 temperature = <90000>; 5248 hysteresis = <2000>; 5249 type = "passive"; 5250 }; 5251 5252 cpu4_top_alert1: trip-point1 { 5253 temperature = <95000>; 5254 hysteresis = <2000>; 5255 type = "passive"; 5256 }; 5257 5258 cpu4_top_crit: cpu_crit { 5259 temperature = <110000>; 5260 hysteresis = <1000>; 5261 type = "critical"; 5262 }; 5263 }; 5264 5265 cooling-maps { 5266 map0 { 5267 trip = <&cpu4_top_alert0>; 5268 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5269 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5270 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5271 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5272 }; 5273 map1 { 5274 trip = <&cpu4_top_alert1>; 5275 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5276 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5277 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5278 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5279 }; 5280 }; 5281 }; 5282 5283 cpu5-top-thermal { 5284 polling-delay-passive = <250>; 5285 polling-delay = <1000>; 5286 5287 thermal-sensors = <&tsens0 8>; 5288 5289 trips { 5290 cpu5_top_alert0: trip-point0 { 5291 temperature = <90000>; 5292 hysteresis = <2000>; 5293 type = "passive"; 5294 }; 5295 5296 cpu5_top_alert1: trip-point1 { 5297 temperature = <95000>; 5298 hysteresis = <2000>; 5299 type = "passive"; 5300 }; 5301 5302 cpu5_top_crit: cpu_crit { 5303 temperature = <110000>; 5304 hysteresis = <1000>; 5305 type = "critical"; 5306 }; 5307 }; 5308 5309 cooling-maps { 5310 map0 { 5311 trip = <&cpu5_top_alert0>; 5312 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5313 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5314 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5315 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5316 }; 5317 map1 { 5318 trip = <&cpu5_top_alert1>; 5319 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5320 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5321 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5322 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5323 }; 5324 }; 5325 }; 5326 5327 cpu6-top-thermal { 5328 polling-delay-passive = <250>; 5329 polling-delay = <1000>; 5330 5331 thermal-sensors = <&tsens0 9>; 5332 5333 trips { 5334 cpu6_top_alert0: trip-point0 { 5335 temperature = <90000>; 5336 hysteresis = <2000>; 5337 type = "passive"; 5338 }; 5339 5340 cpu6_top_alert1: trip-point1 { 5341 temperature = <95000>; 5342 hysteresis = <2000>; 5343 type = "passive"; 5344 }; 5345 5346 cpu6_top_crit: cpu_crit { 5347 temperature = <110000>; 5348 hysteresis = <1000>; 5349 type = "critical"; 5350 }; 5351 }; 5352 5353 cooling-maps { 5354 map0 { 5355 trip = <&cpu6_top_alert0>; 5356 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5357 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5358 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5359 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5360 }; 5361 map1 { 5362 trip = <&cpu6_top_alert1>; 5363 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5364 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5365 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5366 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5367 }; 5368 }; 5369 }; 5370 5371 cpu7-top-thermal { 5372 polling-delay-passive = <250>; 5373 polling-delay = <1000>; 5374 5375 thermal-sensors = <&tsens0 10>; 5376 5377 trips { 5378 cpu7_top_alert0: trip-point0 { 5379 temperature = <90000>; 5380 hysteresis = <2000>; 5381 type = "passive"; 5382 }; 5383 5384 cpu7_top_alert1: trip-point1 { 5385 temperature = <95000>; 5386 hysteresis = <2000>; 5387 type = "passive"; 5388 }; 5389 5390 cpu7_top_crit: cpu_crit { 5391 temperature = <110000>; 5392 hysteresis = <1000>; 5393 type = "critical"; 5394 }; 5395 }; 5396 5397 cooling-maps { 5398 map0 { 5399 trip = <&cpu7_top_alert0>; 5400 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5401 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5402 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5403 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5404 }; 5405 map1 { 5406 trip = <&cpu7_top_alert1>; 5407 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5408 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5409 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5410 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5411 }; 5412 }; 5413 }; 5414 5415 cpu4-bottom-thermal { 5416 polling-delay-passive = <250>; 5417 polling-delay = <1000>; 5418 5419 thermal-sensors = <&tsens0 11>; 5420 5421 trips { 5422 cpu4_bottom_alert0: trip-point0 { 5423 temperature = <90000>; 5424 hysteresis = <2000>; 5425 type = "passive"; 5426 }; 5427 5428 cpu4_bottom_alert1: trip-point1 { 5429 temperature = <95000>; 5430 hysteresis = <2000>; 5431 type = "passive"; 5432 }; 5433 5434 cpu4_bottom_crit: cpu_crit { 5435 temperature = <110000>; 5436 hysteresis = <1000>; 5437 type = "critical"; 5438 }; 5439 }; 5440 5441 cooling-maps { 5442 map0 { 5443 trip = <&cpu4_bottom_alert0>; 5444 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5445 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5446 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5447 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5448 }; 5449 map1 { 5450 trip = <&cpu4_bottom_alert1>; 5451 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5452 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5453 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5454 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5455 }; 5456 }; 5457 }; 5458 5459 cpu5-bottom-thermal { 5460 polling-delay-passive = <250>; 5461 polling-delay = <1000>; 5462 5463 thermal-sensors = <&tsens0 12>; 5464 5465 trips { 5466 cpu5_bottom_alert0: trip-point0 { 5467 temperature = <90000>; 5468 hysteresis = <2000>; 5469 type = "passive"; 5470 }; 5471 5472 cpu5_bottom_alert1: trip-point1 { 5473 temperature = <95000>; 5474 hysteresis = <2000>; 5475 type = "passive"; 5476 }; 5477 5478 cpu5_bottom_crit: cpu_crit { 5479 temperature = <110000>; 5480 hysteresis = <1000>; 5481 type = "critical"; 5482 }; 5483 }; 5484 5485 cooling-maps { 5486 map0 { 5487 trip = <&cpu5_bottom_alert0>; 5488 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5489 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5490 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5491 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5492 }; 5493 map1 { 5494 trip = <&cpu5_bottom_alert1>; 5495 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5496 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5497 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5498 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5499 }; 5500 }; 5501 }; 5502 5503 cpu6-bottom-thermal { 5504 polling-delay-passive = <250>; 5505 polling-delay = <1000>; 5506 5507 thermal-sensors = <&tsens0 13>; 5508 5509 trips { 5510 cpu6_bottom_alert0: trip-point0 { 5511 temperature = <90000>; 5512 hysteresis = <2000>; 5513 type = "passive"; 5514 }; 5515 5516 cpu6_bottom_alert1: trip-point1 { 5517 temperature = <95000>; 5518 hysteresis = <2000>; 5519 type = "passive"; 5520 }; 5521 5522 cpu6_bottom_crit: cpu_crit { 5523 temperature = <110000>; 5524 hysteresis = <1000>; 5525 type = "critical"; 5526 }; 5527 }; 5528 5529 cooling-maps { 5530 map0 { 5531 trip = <&cpu6_bottom_alert0>; 5532 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5533 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5534 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5535 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5536 }; 5537 map1 { 5538 trip = <&cpu6_bottom_alert1>; 5539 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5540 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5541 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5542 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5543 }; 5544 }; 5545 }; 5546 5547 cpu7-bottom-thermal { 5548 polling-delay-passive = <250>; 5549 polling-delay = <1000>; 5550 5551 thermal-sensors = <&tsens0 14>; 5552 5553 trips { 5554 cpu7_bottom_alert0: trip-point0 { 5555 temperature = <90000>; 5556 hysteresis = <2000>; 5557 type = "passive"; 5558 }; 5559 5560 cpu7_bottom_alert1: trip-point1 { 5561 temperature = <95000>; 5562 hysteresis = <2000>; 5563 type = "passive"; 5564 }; 5565 5566 cpu7_bottom_crit: cpu_crit { 5567 temperature = <110000>; 5568 hysteresis = <1000>; 5569 type = "critical"; 5570 }; 5571 }; 5572 5573 cooling-maps { 5574 map0 { 5575 trip = <&cpu7_bottom_alert0>; 5576 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5577 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5578 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5579 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5580 }; 5581 map1 { 5582 trip = <&cpu7_bottom_alert1>; 5583 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5584 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5585 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5586 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5587 }; 5588 }; 5589 }; 5590 5591 aoss0-thermal { 5592 polling-delay-passive = <250>; 5593 polling-delay = <1000>; 5594 5595 thermal-sensors = <&tsens0 0>; 5596 5597 trips { 5598 aoss0_alert0: trip-point0 { 5599 temperature = <90000>; 5600 hysteresis = <2000>; 5601 type = "hot"; 5602 }; 5603 }; 5604 }; 5605 5606 cluster0-thermal { 5607 polling-delay-passive = <250>; 5608 polling-delay = <1000>; 5609 5610 thermal-sensors = <&tsens0 5>; 5611 5612 trips { 5613 cluster0_alert0: trip-point0 { 5614 temperature = <90000>; 5615 hysteresis = <2000>; 5616 type = "hot"; 5617 }; 5618 cluster0_crit: cluster0_crit { 5619 temperature = <110000>; 5620 hysteresis = <2000>; 5621 type = "critical"; 5622 }; 5623 }; 5624 }; 5625 5626 cluster1-thermal { 5627 polling-delay-passive = <250>; 5628 polling-delay = <1000>; 5629 5630 thermal-sensors = <&tsens0 6>; 5631 5632 trips { 5633 cluster1_alert0: trip-point0 { 5634 temperature = <90000>; 5635 hysteresis = <2000>; 5636 type = "hot"; 5637 }; 5638 cluster1_crit: cluster1_crit { 5639 temperature = <110000>; 5640 hysteresis = <2000>; 5641 type = "critical"; 5642 }; 5643 }; 5644 }; 5645 5646 gpu-top-thermal { 5647 polling-delay-passive = <250>; 5648 polling-delay = <1000>; 5649 5650 thermal-sensors = <&tsens0 15>; 5651 5652 trips { 5653 gpu1_alert0: trip-point0 { 5654 temperature = <90000>; 5655 hysteresis = <2000>; 5656 type = "hot"; 5657 }; 5658 }; 5659 }; 5660 5661 aoss1-thermal { 5662 polling-delay-passive = <250>; 5663 polling-delay = <1000>; 5664 5665 thermal-sensors = <&tsens1 0>; 5666 5667 trips { 5668 aoss1_alert0: trip-point0 { 5669 temperature = <90000>; 5670 hysteresis = <2000>; 5671 type = "hot"; 5672 }; 5673 }; 5674 }; 5675 5676 wlan-thermal { 5677 polling-delay-passive = <250>; 5678 polling-delay = <1000>; 5679 5680 thermal-sensors = <&tsens1 1>; 5681 5682 trips { 5683 wlan_alert0: trip-point0 { 5684 temperature = <90000>; 5685 hysteresis = <2000>; 5686 type = "hot"; 5687 }; 5688 }; 5689 }; 5690 5691 video-thermal { 5692 polling-delay-passive = <250>; 5693 polling-delay = <1000>; 5694 5695 thermal-sensors = <&tsens1 2>; 5696 5697 trips { 5698 video_alert0: trip-point0 { 5699 temperature = <90000>; 5700 hysteresis = <2000>; 5701 type = "hot"; 5702 }; 5703 }; 5704 }; 5705 5706 mem-thermal { 5707 polling-delay-passive = <250>; 5708 polling-delay = <1000>; 5709 5710 thermal-sensors = <&tsens1 3>; 5711 5712 trips { 5713 mem_alert0: trip-point0 { 5714 temperature = <90000>; 5715 hysteresis = <2000>; 5716 type = "hot"; 5717 }; 5718 }; 5719 }; 5720 5721 q6-hvx-thermal { 5722 polling-delay-passive = <250>; 5723 polling-delay = <1000>; 5724 5725 thermal-sensors = <&tsens1 4>; 5726 5727 trips { 5728 q6_hvx_alert0: trip-point0 { 5729 temperature = <90000>; 5730 hysteresis = <2000>; 5731 type = "hot"; 5732 }; 5733 }; 5734 }; 5735 5736 camera-thermal { 5737 polling-delay-passive = <250>; 5738 polling-delay = <1000>; 5739 5740 thermal-sensors = <&tsens1 5>; 5741 5742 trips { 5743 camera_alert0: trip-point0 { 5744 temperature = <90000>; 5745 hysteresis = <2000>; 5746 type = "hot"; 5747 }; 5748 }; 5749 }; 5750 5751 compute-thermal { 5752 polling-delay-passive = <250>; 5753 polling-delay = <1000>; 5754 5755 thermal-sensors = <&tsens1 6>; 5756 5757 trips { 5758 compute_alert0: trip-point0 { 5759 temperature = <90000>; 5760 hysteresis = <2000>; 5761 type = "hot"; 5762 }; 5763 }; 5764 }; 5765 5766 npu-thermal { 5767 polling-delay-passive = <250>; 5768 polling-delay = <1000>; 5769 5770 thermal-sensors = <&tsens1 7>; 5771 5772 trips { 5773 npu_alert0: trip-point0 { 5774 temperature = <90000>; 5775 hysteresis = <2000>; 5776 type = "hot"; 5777 }; 5778 }; 5779 }; 5780 5781 gpu-bottom-thermal { 5782 polling-delay-passive = <250>; 5783 polling-delay = <1000>; 5784 5785 thermal-sensors = <&tsens1 8>; 5786 5787 trips { 5788 gpu2_alert0: trip-point0 { 5789 temperature = <90000>; 5790 hysteresis = <2000>; 5791 type = "hot"; 5792 }; 5793 }; 5794 }; 5795 }; 5796}; 5797