1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sm8250.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/soc/qcom,apr.h> 18#include <dt-bindings/soc/qcom,rpmh-rsc.h> 19#include <dt-bindings/sound/qcom,q6afe.h> 20#include <dt-bindings/thermal/thermal.h> 21#include <dt-bindings/clock/qcom,videocc-sm8250.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 aliases { 30 i2c0 = &i2c0; 31 i2c1 = &i2c1; 32 i2c2 = &i2c2; 33 i2c3 = &i2c3; 34 i2c4 = &i2c4; 35 i2c5 = &i2c5; 36 i2c6 = &i2c6; 37 i2c7 = &i2c7; 38 i2c8 = &i2c8; 39 i2c9 = &i2c9; 40 i2c10 = &i2c10; 41 i2c11 = &i2c11; 42 i2c12 = &i2c12; 43 i2c13 = &i2c13; 44 i2c14 = &i2c14; 45 i2c15 = &i2c15; 46 i2c16 = &i2c16; 47 i2c17 = &i2c17; 48 i2c18 = &i2c18; 49 i2c19 = &i2c19; 50 spi0 = &spi0; 51 spi1 = &spi1; 52 spi2 = &spi2; 53 spi3 = &spi3; 54 spi4 = &spi4; 55 spi5 = &spi5; 56 spi6 = &spi6; 57 spi7 = &spi7; 58 spi8 = &spi8; 59 spi9 = &spi9; 60 spi10 = &spi10; 61 spi11 = &spi11; 62 spi12 = &spi12; 63 spi13 = &spi13; 64 spi14 = &spi14; 65 spi15 = &spi15; 66 spi16 = &spi16; 67 spi17 = &spi17; 68 spi18 = &spi18; 69 spi19 = &spi19; 70 }; 71 72 chosen { }; 73 74 clocks { 75 xo_board: xo-board { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <38400000>; 79 clock-output-names = "xo_board"; 80 }; 81 82 sleep_clk: sleep-clk { 83 compatible = "fixed-clock"; 84 clock-frequency = <32768>; 85 #clock-cells = <0>; 86 }; 87 }; 88 89 cpus { 90 #address-cells = <2>; 91 #size-cells = <0>; 92 93 CPU0: cpu@0 { 94 device_type = "cpu"; 95 compatible = "qcom,kryo485"; 96 reg = <0x0 0x0>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <448>; 99 dynamic-power-coefficient = <205>; 100 next-level-cache = <&L2_0>; 101 power-domains = <&CPU_PD0>; 102 power-domain-names = "psci"; 103 qcom,freq-domain = <&cpufreq_hw 0>; 104 operating-points-v2 = <&cpu0_opp_table>; 105 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 106 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 107 #cooling-cells = <2>; 108 L2_0: l2-cache { 109 compatible = "cache"; 110 next-level-cache = <&L3_0>; 111 L3_0: l3-cache { 112 compatible = "cache"; 113 }; 114 }; 115 }; 116 117 CPU1: cpu@100 { 118 device_type = "cpu"; 119 compatible = "qcom,kryo485"; 120 reg = <0x0 0x100>; 121 enable-method = "psci"; 122 capacity-dmips-mhz = <448>; 123 dynamic-power-coefficient = <205>; 124 next-level-cache = <&L2_100>; 125 power-domains = <&CPU_PD1>; 126 power-domain-names = "psci"; 127 qcom,freq-domain = <&cpufreq_hw 0>; 128 operating-points-v2 = <&cpu0_opp_table>; 129 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 130 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 131 #cooling-cells = <2>; 132 L2_100: l2-cache { 133 compatible = "cache"; 134 next-level-cache = <&L3_0>; 135 }; 136 }; 137 138 CPU2: cpu@200 { 139 device_type = "cpu"; 140 compatible = "qcom,kryo485"; 141 reg = <0x0 0x200>; 142 enable-method = "psci"; 143 capacity-dmips-mhz = <448>; 144 dynamic-power-coefficient = <205>; 145 next-level-cache = <&L2_200>; 146 power-domains = <&CPU_PD2>; 147 power-domain-names = "psci"; 148 qcom,freq-domain = <&cpufreq_hw 0>; 149 operating-points-v2 = <&cpu0_opp_table>; 150 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 151 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 152 #cooling-cells = <2>; 153 L2_200: l2-cache { 154 compatible = "cache"; 155 next-level-cache = <&L3_0>; 156 }; 157 }; 158 159 CPU3: cpu@300 { 160 device_type = "cpu"; 161 compatible = "qcom,kryo485"; 162 reg = <0x0 0x300>; 163 enable-method = "psci"; 164 capacity-dmips-mhz = <448>; 165 dynamic-power-coefficient = <205>; 166 next-level-cache = <&L2_300>; 167 power-domains = <&CPU_PD3>; 168 power-domain-names = "psci"; 169 qcom,freq-domain = <&cpufreq_hw 0>; 170 operating-points-v2 = <&cpu0_opp_table>; 171 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 172 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 173 #cooling-cells = <2>; 174 L2_300: l2-cache { 175 compatible = "cache"; 176 next-level-cache = <&L3_0>; 177 }; 178 }; 179 180 CPU4: cpu@400 { 181 device_type = "cpu"; 182 compatible = "qcom,kryo485"; 183 reg = <0x0 0x400>; 184 enable-method = "psci"; 185 capacity-dmips-mhz = <1024>; 186 dynamic-power-coefficient = <379>; 187 next-level-cache = <&L2_400>; 188 power-domains = <&CPU_PD4>; 189 power-domain-names = "psci"; 190 qcom,freq-domain = <&cpufreq_hw 1>; 191 operating-points-v2 = <&cpu4_opp_table>; 192 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 193 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 194 #cooling-cells = <2>; 195 L2_400: l2-cache { 196 compatible = "cache"; 197 next-level-cache = <&L3_0>; 198 }; 199 }; 200 201 CPU5: cpu@500 { 202 device_type = "cpu"; 203 compatible = "qcom,kryo485"; 204 reg = <0x0 0x500>; 205 enable-method = "psci"; 206 capacity-dmips-mhz = <1024>; 207 dynamic-power-coefficient = <379>; 208 next-level-cache = <&L2_500>; 209 power-domains = <&CPU_PD5>; 210 power-domain-names = "psci"; 211 qcom,freq-domain = <&cpufreq_hw 1>; 212 operating-points-v2 = <&cpu4_opp_table>; 213 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 214 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 215 #cooling-cells = <2>; 216 L2_500: l2-cache { 217 compatible = "cache"; 218 next-level-cache = <&L3_0>; 219 }; 220 221 }; 222 223 CPU6: cpu@600 { 224 device_type = "cpu"; 225 compatible = "qcom,kryo485"; 226 reg = <0x0 0x600>; 227 enable-method = "psci"; 228 capacity-dmips-mhz = <1024>; 229 dynamic-power-coefficient = <379>; 230 next-level-cache = <&L2_600>; 231 power-domains = <&CPU_PD6>; 232 power-domain-names = "psci"; 233 qcom,freq-domain = <&cpufreq_hw 1>; 234 operating-points-v2 = <&cpu4_opp_table>; 235 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 236 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 237 #cooling-cells = <2>; 238 L2_600: l2-cache { 239 compatible = "cache"; 240 next-level-cache = <&L3_0>; 241 }; 242 }; 243 244 CPU7: cpu@700 { 245 device_type = "cpu"; 246 compatible = "qcom,kryo485"; 247 reg = <0x0 0x700>; 248 enable-method = "psci"; 249 capacity-dmips-mhz = <1024>; 250 dynamic-power-coefficient = <444>; 251 next-level-cache = <&L2_700>; 252 power-domains = <&CPU_PD7>; 253 power-domain-names = "psci"; 254 qcom,freq-domain = <&cpufreq_hw 2>; 255 operating-points-v2 = <&cpu7_opp_table>; 256 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 257 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 258 #cooling-cells = <2>; 259 L2_700: l2-cache { 260 compatible = "cache"; 261 next-level-cache = <&L3_0>; 262 }; 263 }; 264 265 cpu-map { 266 cluster0 { 267 core0 { 268 cpu = <&CPU0>; 269 }; 270 271 core1 { 272 cpu = <&CPU1>; 273 }; 274 275 core2 { 276 cpu = <&CPU2>; 277 }; 278 279 core3 { 280 cpu = <&CPU3>; 281 }; 282 283 core4 { 284 cpu = <&CPU4>; 285 }; 286 287 core5 { 288 cpu = <&CPU5>; 289 }; 290 291 core6 { 292 cpu = <&CPU6>; 293 }; 294 295 core7 { 296 cpu = <&CPU7>; 297 }; 298 }; 299 }; 300 301 idle-states { 302 entry-method = "psci"; 303 304 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 305 compatible = "arm,idle-state"; 306 idle-state-name = "silver-rail-power-collapse"; 307 arm,psci-suspend-param = <0x40000004>; 308 entry-latency-us = <360>; 309 exit-latency-us = <531>; 310 min-residency-us = <3934>; 311 local-timer-stop; 312 }; 313 314 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 315 compatible = "arm,idle-state"; 316 idle-state-name = "gold-rail-power-collapse"; 317 arm,psci-suspend-param = <0x40000004>; 318 entry-latency-us = <702>; 319 exit-latency-us = <1061>; 320 min-residency-us = <4488>; 321 local-timer-stop; 322 }; 323 }; 324 325 domain-idle-states { 326 CLUSTER_SLEEP_0: cluster-sleep-0 { 327 compatible = "domain-idle-state"; 328 idle-state-name = "cluster-llcc-off"; 329 arm,psci-suspend-param = <0x4100c244>; 330 entry-latency-us = <3264>; 331 exit-latency-us = <6562>; 332 min-residency-us = <9987>; 333 local-timer-stop; 334 }; 335 }; 336 }; 337 338 cpu0_opp_table: cpu0_opp_table { 339 compatible = "operating-points-v2"; 340 opp-shared; 341 342 cpu0_opp1: opp-300000000 { 343 opp-hz = /bits/ 64 <300000000>; 344 opp-peak-kBps = <800000 9600000>; 345 }; 346 347 cpu0_opp2: opp-403200000 { 348 opp-hz = /bits/ 64 <403200000>; 349 opp-peak-kBps = <800000 9600000>; 350 }; 351 352 cpu0_opp3: opp-518400000 { 353 opp-hz = /bits/ 64 <518400000>; 354 opp-peak-kBps = <800000 16588800>; 355 }; 356 357 cpu0_opp4: opp-614400000 { 358 opp-hz = /bits/ 64 <614400000>; 359 opp-peak-kBps = <800000 16588800>; 360 }; 361 362 cpu0_opp5: opp-691200000 { 363 opp-hz = /bits/ 64 <691200000>; 364 opp-peak-kBps = <800000 19660800>; 365 }; 366 367 cpu0_opp6: opp-787200000 { 368 opp-hz = /bits/ 64 <787200000>; 369 opp-peak-kBps = <1804000 19660800>; 370 }; 371 372 cpu0_opp7: opp-883200000 { 373 opp-hz = /bits/ 64 <883200000>; 374 opp-peak-kBps = <1804000 23347200>; 375 }; 376 377 cpu0_opp8: opp-979200000 { 378 opp-hz = /bits/ 64 <979200000>; 379 opp-peak-kBps = <1804000 26419200>; 380 }; 381 382 cpu0_opp9: opp-1075200000 { 383 opp-hz = /bits/ 64 <1075200000>; 384 opp-peak-kBps = <1804000 29491200>; 385 }; 386 387 cpu0_opp10: opp-1171200000 { 388 opp-hz = /bits/ 64 <1171200000>; 389 opp-peak-kBps = <1804000 32563200>; 390 }; 391 392 cpu0_opp11: opp-1248000000 { 393 opp-hz = /bits/ 64 <1248000000>; 394 opp-peak-kBps = <1804000 36249600>; 395 }; 396 397 cpu0_opp12: opp-1344000000 { 398 opp-hz = /bits/ 64 <1344000000>; 399 opp-peak-kBps = <2188000 36249600>; 400 }; 401 402 cpu0_opp13: opp-1420800000 { 403 opp-hz = /bits/ 64 <1420800000>; 404 opp-peak-kBps = <2188000 39321600>; 405 }; 406 407 cpu0_opp14: opp-1516800000 { 408 opp-hz = /bits/ 64 <1516800000>; 409 opp-peak-kBps = <3072000 42393600>; 410 }; 411 412 cpu0_opp15: opp-1612800000 { 413 opp-hz = /bits/ 64 <1612800000>; 414 opp-peak-kBps = <3072000 42393600>; 415 }; 416 417 cpu0_opp16: opp-1708800000 { 418 opp-hz = /bits/ 64 <1708800000>; 419 opp-peak-kBps = <4068000 42393600>; 420 }; 421 422 cpu0_opp17: opp-1804800000 { 423 opp-hz = /bits/ 64 <1804800000>; 424 opp-peak-kBps = <4068000 42393600>; 425 }; 426 }; 427 428 cpu4_opp_table: cpu4_opp_table { 429 compatible = "operating-points-v2"; 430 opp-shared; 431 432 cpu4_opp1: opp-710400000 { 433 opp-hz = /bits/ 64 <710400000>; 434 opp-peak-kBps = <1804000 19660800>; 435 }; 436 437 cpu4_opp2: opp-825600000 { 438 opp-hz = /bits/ 64 <825600000>; 439 opp-peak-kBps = <2188000 23347200>; 440 }; 441 442 cpu4_opp3: opp-940800000 { 443 opp-hz = /bits/ 64 <940800000>; 444 opp-peak-kBps = <2188000 26419200>; 445 }; 446 447 cpu4_opp4: opp-1056000000 { 448 opp-hz = /bits/ 64 <1056000000>; 449 opp-peak-kBps = <3072000 26419200>; 450 }; 451 452 cpu4_opp5: opp-1171200000 { 453 opp-hz = /bits/ 64 <1171200000>; 454 opp-peak-kBps = <3072000 29491200>; 455 }; 456 457 cpu4_opp6: opp-1286400000 { 458 opp-hz = /bits/ 64 <1286400000>; 459 opp-peak-kBps = <4068000 29491200>; 460 }; 461 462 cpu4_opp7: opp-1382400000 { 463 opp-hz = /bits/ 64 <1382400000>; 464 opp-peak-kBps = <4068000 32563200>; 465 }; 466 467 cpu4_opp8: opp-1478400000 { 468 opp-hz = /bits/ 64 <1478400000>; 469 opp-peak-kBps = <4068000 32563200>; 470 }; 471 472 cpu4_opp9: opp-1574400000 { 473 opp-hz = /bits/ 64 <1574400000>; 474 opp-peak-kBps = <5412000 39321600>; 475 }; 476 477 cpu4_opp10: opp-1670400000 { 478 opp-hz = /bits/ 64 <1670400000>; 479 opp-peak-kBps = <5412000 42393600>; 480 }; 481 482 cpu4_opp11: opp-1766400000 { 483 opp-hz = /bits/ 64 <1766400000>; 484 opp-peak-kBps = <5412000 45465600>; 485 }; 486 487 cpu4_opp12: opp-1862400000 { 488 opp-hz = /bits/ 64 <1862400000>; 489 opp-peak-kBps = <6220000 45465600>; 490 }; 491 492 cpu4_opp13: opp-1958400000 { 493 opp-hz = /bits/ 64 <1958400000>; 494 opp-peak-kBps = <6220000 48537600>; 495 }; 496 497 cpu4_opp14: opp-2054400000 { 498 opp-hz = /bits/ 64 <2054400000>; 499 opp-peak-kBps = <7216000 48537600>; 500 }; 501 502 cpu4_opp15: opp-2150400000 { 503 opp-hz = /bits/ 64 <2150400000>; 504 opp-peak-kBps = <7216000 51609600>; 505 }; 506 507 cpu4_opp16: opp-2246400000 { 508 opp-hz = /bits/ 64 <2246400000>; 509 opp-peak-kBps = <7216000 51609600>; 510 }; 511 512 cpu4_opp17: opp-2342400000 { 513 opp-hz = /bits/ 64 <2342400000>; 514 opp-peak-kBps = <8368000 51609600>; 515 }; 516 517 cpu4_opp18: opp-2419200000 { 518 opp-hz = /bits/ 64 <2419200000>; 519 opp-peak-kBps = <8368000 51609600>; 520 }; 521 }; 522 523 cpu7_opp_table: cpu7_opp_table { 524 compatible = "operating-points-v2"; 525 opp-shared; 526 527 cpu7_opp1: opp-844800000 { 528 opp-hz = /bits/ 64 <844800000>; 529 opp-peak-kBps = <2188000 19660800>; 530 }; 531 532 cpu7_opp2: opp-960000000 { 533 opp-hz = /bits/ 64 <960000000>; 534 opp-peak-kBps = <2188000 26419200>; 535 }; 536 537 cpu7_opp3: opp-1075200000 { 538 opp-hz = /bits/ 64 <1075200000>; 539 opp-peak-kBps = <3072000 26419200>; 540 }; 541 542 cpu7_opp4: opp-1190400000 { 543 opp-hz = /bits/ 64 <1190400000>; 544 opp-peak-kBps = <3072000 29491200>; 545 }; 546 547 cpu7_opp5: opp-1305600000 { 548 opp-hz = /bits/ 64 <1305600000>; 549 opp-peak-kBps = <4068000 32563200>; 550 }; 551 552 cpu7_opp6: opp-1401600000 { 553 opp-hz = /bits/ 64 <1401600000>; 554 opp-peak-kBps = <4068000 32563200>; 555 }; 556 557 cpu7_opp7: opp-1516800000 { 558 opp-hz = /bits/ 64 <1516800000>; 559 opp-peak-kBps = <4068000 36249600>; 560 }; 561 562 cpu7_opp8: opp-1632000000 { 563 opp-hz = /bits/ 64 <1632000000>; 564 opp-peak-kBps = <5412000 39321600>; 565 }; 566 567 cpu7_opp9: opp-1747200000 { 568 opp-hz = /bits/ 64 <1708800000>; 569 opp-peak-kBps = <5412000 42393600>; 570 }; 571 572 cpu7_opp10: opp-1862400000 { 573 opp-hz = /bits/ 64 <1862400000>; 574 opp-peak-kBps = <6220000 45465600>; 575 }; 576 577 cpu7_opp11: opp-1977600000 { 578 opp-hz = /bits/ 64 <1977600000>; 579 opp-peak-kBps = <6220000 48537600>; 580 }; 581 582 cpu7_opp12: opp-2073600000 { 583 opp-hz = /bits/ 64 <2073600000>; 584 opp-peak-kBps = <7216000 48537600>; 585 }; 586 587 cpu7_opp13: opp-2169600000 { 588 opp-hz = /bits/ 64 <2169600000>; 589 opp-peak-kBps = <7216000 51609600>; 590 }; 591 592 cpu7_opp14: opp-2265600000 { 593 opp-hz = /bits/ 64 <2265600000>; 594 opp-peak-kBps = <7216000 51609600>; 595 }; 596 597 cpu7_opp15: opp-2361600000 { 598 opp-hz = /bits/ 64 <2361600000>; 599 opp-peak-kBps = <8368000 51609600>; 600 }; 601 602 cpu7_opp16: opp-2457600000 { 603 opp-hz = /bits/ 64 <2457600000>; 604 opp-peak-kBps = <8368000 51609600>; 605 }; 606 607 cpu7_opp17: opp-2553600000 { 608 opp-hz = /bits/ 64 <2553600000>; 609 opp-peak-kBps = <8368000 51609600>; 610 }; 611 612 cpu7_opp18: opp-2649600000 { 613 opp-hz = /bits/ 64 <2649600000>; 614 opp-peak-kBps = <8368000 51609600>; 615 }; 616 617 cpu7_opp19: opp-2745600000 { 618 opp-hz = /bits/ 64 <2745600000>; 619 opp-peak-kBps = <8368000 51609600>; 620 }; 621 622 cpu7_opp20: opp-2841600000 { 623 opp-hz = /bits/ 64 <2841600000>; 624 opp-peak-kBps = <8368000 51609600>; 625 }; 626 }; 627 628 firmware { 629 scm: scm { 630 compatible = "qcom,scm"; 631 #reset-cells = <1>; 632 }; 633 }; 634 635 memory@80000000 { 636 device_type = "memory"; 637 /* We expect the bootloader to fill in the size */ 638 reg = <0x0 0x80000000 0x0 0x0>; 639 }; 640 641 pmu { 642 compatible = "arm,armv8-pmuv3"; 643 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 644 }; 645 646 psci { 647 compatible = "arm,psci-1.0"; 648 method = "smc"; 649 650 CPU_PD0: cpu0 { 651 #power-domain-cells = <0>; 652 power-domains = <&CLUSTER_PD>; 653 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 654 }; 655 656 CPU_PD1: cpu1 { 657 #power-domain-cells = <0>; 658 power-domains = <&CLUSTER_PD>; 659 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 660 }; 661 662 CPU_PD2: cpu2 { 663 #power-domain-cells = <0>; 664 power-domains = <&CLUSTER_PD>; 665 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 666 }; 667 668 CPU_PD3: cpu3 { 669 #power-domain-cells = <0>; 670 power-domains = <&CLUSTER_PD>; 671 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 672 }; 673 674 CPU_PD4: cpu4 { 675 #power-domain-cells = <0>; 676 power-domains = <&CLUSTER_PD>; 677 domain-idle-states = <&BIG_CPU_SLEEP_0>; 678 }; 679 680 CPU_PD5: cpu5 { 681 #power-domain-cells = <0>; 682 power-domains = <&CLUSTER_PD>; 683 domain-idle-states = <&BIG_CPU_SLEEP_0>; 684 }; 685 686 CPU_PD6: cpu6 { 687 #power-domain-cells = <0>; 688 power-domains = <&CLUSTER_PD>; 689 domain-idle-states = <&BIG_CPU_SLEEP_0>; 690 }; 691 692 CPU_PD7: cpu7 { 693 #power-domain-cells = <0>; 694 power-domains = <&CLUSTER_PD>; 695 domain-idle-states = <&BIG_CPU_SLEEP_0>; 696 }; 697 698 CLUSTER_PD: cpu-cluster0 { 699 #power-domain-cells = <0>; 700 domain-idle-states = <&CLUSTER_SLEEP_0>; 701 }; 702 }; 703 704 reserved-memory { 705 #address-cells = <2>; 706 #size-cells = <2>; 707 ranges; 708 709 hyp_mem: memory@80000000 { 710 reg = <0x0 0x80000000 0x0 0x600000>; 711 no-map; 712 }; 713 714 xbl_aop_mem: memory@80700000 { 715 reg = <0x0 0x80700000 0x0 0x160000>; 716 no-map; 717 }; 718 719 cmd_db: memory@80860000 { 720 compatible = "qcom,cmd-db"; 721 reg = <0x0 0x80860000 0x0 0x20000>; 722 no-map; 723 }; 724 725 smem_mem: memory@80900000 { 726 reg = <0x0 0x80900000 0x0 0x200000>; 727 no-map; 728 }; 729 730 removed_mem: memory@80b00000 { 731 reg = <0x0 0x80b00000 0x0 0x5300000>; 732 no-map; 733 }; 734 735 camera_mem: memory@86200000 { 736 reg = <0x0 0x86200000 0x0 0x500000>; 737 no-map; 738 }; 739 740 wlan_mem: memory@86700000 { 741 reg = <0x0 0x86700000 0x0 0x100000>; 742 no-map; 743 }; 744 745 ipa_fw_mem: memory@86800000 { 746 reg = <0x0 0x86800000 0x0 0x10000>; 747 no-map; 748 }; 749 750 ipa_gsi_mem: memory@86810000 { 751 reg = <0x0 0x86810000 0x0 0xa000>; 752 no-map; 753 }; 754 755 gpu_mem: memory@8681a000 { 756 reg = <0x0 0x8681a000 0x0 0x2000>; 757 no-map; 758 }; 759 760 npu_mem: memory@86900000 { 761 reg = <0x0 0x86900000 0x0 0x500000>; 762 no-map; 763 }; 764 765 video_mem: memory@86e00000 { 766 reg = <0x0 0x86e00000 0x0 0x500000>; 767 no-map; 768 }; 769 770 cvp_mem: memory@87300000 { 771 reg = <0x0 0x87300000 0x0 0x500000>; 772 no-map; 773 }; 774 775 cdsp_mem: memory@87800000 { 776 reg = <0x0 0x87800000 0x0 0x1400000>; 777 no-map; 778 }; 779 780 slpi_mem: memory@88c00000 { 781 reg = <0x0 0x88c00000 0x0 0x1500000>; 782 no-map; 783 }; 784 785 adsp_mem: memory@8a100000 { 786 reg = <0x0 0x8a100000 0x0 0x1d00000>; 787 no-map; 788 }; 789 790 spss_mem: memory@8be00000 { 791 reg = <0x0 0x8be00000 0x0 0x100000>; 792 no-map; 793 }; 794 795 cdsp_secure_heap: memory@8bf00000 { 796 reg = <0x0 0x8bf00000 0x0 0x4600000>; 797 no-map; 798 }; 799 }; 800 801 smem { 802 compatible = "qcom,smem"; 803 memory-region = <&smem_mem>; 804 hwlocks = <&tcsr_mutex 3>; 805 }; 806 807 smp2p-adsp { 808 compatible = "qcom,smp2p"; 809 qcom,smem = <443>, <429>; 810 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 811 IPCC_MPROC_SIGNAL_SMP2P 812 IRQ_TYPE_EDGE_RISING>; 813 mboxes = <&ipcc IPCC_CLIENT_LPASS 814 IPCC_MPROC_SIGNAL_SMP2P>; 815 816 qcom,local-pid = <0>; 817 qcom,remote-pid = <2>; 818 819 smp2p_adsp_out: master-kernel { 820 qcom,entry-name = "master-kernel"; 821 #qcom,smem-state-cells = <1>; 822 }; 823 824 smp2p_adsp_in: slave-kernel { 825 qcom,entry-name = "slave-kernel"; 826 interrupt-controller; 827 #interrupt-cells = <2>; 828 }; 829 }; 830 831 smp2p-cdsp { 832 compatible = "qcom,smp2p"; 833 qcom,smem = <94>, <432>; 834 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 835 IPCC_MPROC_SIGNAL_SMP2P 836 IRQ_TYPE_EDGE_RISING>; 837 mboxes = <&ipcc IPCC_CLIENT_CDSP 838 IPCC_MPROC_SIGNAL_SMP2P>; 839 840 qcom,local-pid = <0>; 841 qcom,remote-pid = <5>; 842 843 smp2p_cdsp_out: master-kernel { 844 qcom,entry-name = "master-kernel"; 845 #qcom,smem-state-cells = <1>; 846 }; 847 848 smp2p_cdsp_in: slave-kernel { 849 qcom,entry-name = "slave-kernel"; 850 interrupt-controller; 851 #interrupt-cells = <2>; 852 }; 853 }; 854 855 smp2p-slpi { 856 compatible = "qcom,smp2p"; 857 qcom,smem = <481>, <430>; 858 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 859 IPCC_MPROC_SIGNAL_SMP2P 860 IRQ_TYPE_EDGE_RISING>; 861 mboxes = <&ipcc IPCC_CLIENT_SLPI 862 IPCC_MPROC_SIGNAL_SMP2P>; 863 864 qcom,local-pid = <0>; 865 qcom,remote-pid = <3>; 866 867 smp2p_slpi_out: master-kernel { 868 qcom,entry-name = "master-kernel"; 869 #qcom,smem-state-cells = <1>; 870 }; 871 872 smp2p_slpi_in: slave-kernel { 873 qcom,entry-name = "slave-kernel"; 874 interrupt-controller; 875 #interrupt-cells = <2>; 876 }; 877 }; 878 879 soc: soc@0 { 880 #address-cells = <2>; 881 #size-cells = <2>; 882 ranges = <0 0 0 0 0x10 0>; 883 dma-ranges = <0 0 0 0 0x10 0>; 884 compatible = "simple-bus"; 885 886 gcc: clock-controller@100000 { 887 compatible = "qcom,gcc-sm8250"; 888 reg = <0x0 0x00100000 0x0 0x1f0000>; 889 #clock-cells = <1>; 890 #reset-cells = <1>; 891 #power-domain-cells = <1>; 892 clock-names = "bi_tcxo", 893 "bi_tcxo_ao", 894 "sleep_clk"; 895 clocks = <&rpmhcc RPMH_CXO_CLK>, 896 <&rpmhcc RPMH_CXO_CLK_A>, 897 <&sleep_clk>; 898 }; 899 900 ipcc: mailbox@408000 { 901 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 902 reg = <0 0x00408000 0 0x1000>; 903 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 904 interrupt-controller; 905 #interrupt-cells = <3>; 906 #mbox-cells = <2>; 907 }; 908 909 rng: rng@793000 { 910 compatible = "qcom,prng-ee"; 911 reg = <0 0x00793000 0 0x1000>; 912 clocks = <&gcc GCC_PRNG_AHB_CLK>; 913 clock-names = "core"; 914 }; 915 916 qup_opp_table: qup-opp-table { 917 compatible = "operating-points-v2"; 918 919 opp-50000000 { 920 opp-hz = /bits/ 64 <50000000>; 921 required-opps = <&rpmhpd_opp_min_svs>; 922 }; 923 924 opp-75000000 { 925 opp-hz = /bits/ 64 <75000000>; 926 required-opps = <&rpmhpd_opp_low_svs>; 927 }; 928 929 opp-120000000 { 930 opp-hz = /bits/ 64 <120000000>; 931 required-opps = <&rpmhpd_opp_svs>; 932 }; 933 }; 934 935 gpi_dma2: dma-controller@800000 { 936 compatible = "qcom,sm8250-gpi-dma"; 937 reg = <0 0x00800000 0 0x70000>; 938 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 948 dma-channels = <10>; 949 dma-channel-mask = <0x3f>; 950 iommus = <&apps_smmu 0x76 0x0>; 951 #dma-cells = <3>; 952 status = "disabled"; 953 }; 954 955 qupv3_id_2: geniqup@8c0000 { 956 compatible = "qcom,geni-se-qup"; 957 reg = <0x0 0x008c0000 0x0 0x6000>; 958 clock-names = "m-ahb", "s-ahb"; 959 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 960 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 961 #address-cells = <2>; 962 #size-cells = <2>; 963 iommus = <&apps_smmu 0x63 0x0>; 964 ranges; 965 status = "disabled"; 966 967 i2c14: i2c@880000 { 968 compatible = "qcom,geni-i2c"; 969 reg = <0 0x00880000 0 0x4000>; 970 clock-names = "se"; 971 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&qup_i2c14_default>; 974 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 975 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 976 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 977 dma-names = "tx", "rx"; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 status = "disabled"; 981 }; 982 983 spi14: spi@880000 { 984 compatible = "qcom,geni-spi"; 985 reg = <0 0x00880000 0 0x4000>; 986 clock-names = "se"; 987 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 988 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 989 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 990 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 991 dma-names = "tx", "rx"; 992 power-domains = <&rpmhpd SM8250_CX>; 993 operating-points-v2 = <&qup_opp_table>; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 status = "disabled"; 997 }; 998 999 i2c15: i2c@884000 { 1000 compatible = "qcom,geni-i2c"; 1001 reg = <0 0x00884000 0 0x4000>; 1002 clock-names = "se"; 1003 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1004 pinctrl-names = "default"; 1005 pinctrl-0 = <&qup_i2c15_default>; 1006 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1007 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1008 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1009 dma-names = "tx", "rx"; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 status = "disabled"; 1013 }; 1014 1015 spi15: spi@884000 { 1016 compatible = "qcom,geni-spi"; 1017 reg = <0 0x00884000 0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1020 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1021 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1022 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1023 dma-names = "tx", "rx"; 1024 power-domains = <&rpmhpd SM8250_CX>; 1025 operating-points-v2 = <&qup_opp_table>; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 status = "disabled"; 1029 }; 1030 1031 i2c16: i2c@888000 { 1032 compatible = "qcom,geni-i2c"; 1033 reg = <0 0x00888000 0 0x4000>; 1034 clock-names = "se"; 1035 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1036 pinctrl-names = "default"; 1037 pinctrl-0 = <&qup_i2c16_default>; 1038 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1039 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1040 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1041 dma-names = "tx", "rx"; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 status = "disabled"; 1045 }; 1046 1047 spi16: spi@888000 { 1048 compatible = "qcom,geni-spi"; 1049 reg = <0 0x00888000 0 0x4000>; 1050 clock-names = "se"; 1051 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1052 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1053 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1054 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1055 dma-names = "tx", "rx"; 1056 power-domains = <&rpmhpd SM8250_CX>; 1057 operating-points-v2 = <&qup_opp_table>; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 status = "disabled"; 1061 }; 1062 1063 i2c17: i2c@88c000 { 1064 compatible = "qcom,geni-i2c"; 1065 reg = <0 0x0088c000 0 0x4000>; 1066 clock-names = "se"; 1067 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1068 pinctrl-names = "default"; 1069 pinctrl-0 = <&qup_i2c17_default>; 1070 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1071 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1072 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1073 dma-names = "tx", "rx"; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 status = "disabled"; 1077 }; 1078 1079 spi17: spi@88c000 { 1080 compatible = "qcom,geni-spi"; 1081 reg = <0 0x0088c000 0 0x4000>; 1082 clock-names = "se"; 1083 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1084 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1085 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1086 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1087 dma-names = "tx", "rx"; 1088 power-domains = <&rpmhpd SM8250_CX>; 1089 operating-points-v2 = <&qup_opp_table>; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 status = "disabled"; 1093 }; 1094 1095 uart17: serial@88c000 { 1096 compatible = "qcom,geni-uart"; 1097 reg = <0 0x0088c000 0 0x4000>; 1098 clock-names = "se"; 1099 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1100 pinctrl-names = "default"; 1101 pinctrl-0 = <&qup_uart17_default>; 1102 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1103 power-domains = <&rpmhpd SM8250_CX>; 1104 operating-points-v2 = <&qup_opp_table>; 1105 status = "disabled"; 1106 }; 1107 1108 i2c18: i2c@890000 { 1109 compatible = "qcom,geni-i2c"; 1110 reg = <0 0x00890000 0 0x4000>; 1111 clock-names = "se"; 1112 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1113 pinctrl-names = "default"; 1114 pinctrl-0 = <&qup_i2c18_default>; 1115 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1116 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1117 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1118 dma-names = "tx", "rx"; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 status = "disabled"; 1122 }; 1123 1124 spi18: spi@890000 { 1125 compatible = "qcom,geni-spi"; 1126 reg = <0 0x00890000 0 0x4000>; 1127 clock-names = "se"; 1128 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1129 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1130 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1131 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1132 dma-names = "tx", "rx"; 1133 power-domains = <&rpmhpd SM8250_CX>; 1134 operating-points-v2 = <&qup_opp_table>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 status = "disabled"; 1138 }; 1139 1140 uart18: serial@890000 { 1141 compatible = "qcom,geni-uart"; 1142 reg = <0 0x00890000 0 0x4000>; 1143 clock-names = "se"; 1144 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1145 pinctrl-names = "default"; 1146 pinctrl-0 = <&qup_uart18_default>; 1147 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1148 power-domains = <&rpmhpd SM8250_CX>; 1149 operating-points-v2 = <&qup_opp_table>; 1150 status = "disabled"; 1151 }; 1152 1153 i2c19: i2c@894000 { 1154 compatible = "qcom,geni-i2c"; 1155 reg = <0 0x00894000 0 0x4000>; 1156 clock-names = "se"; 1157 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1158 pinctrl-names = "default"; 1159 pinctrl-0 = <&qup_i2c19_default>; 1160 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1161 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1162 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1163 dma-names = "tx", "rx"; 1164 #address-cells = <1>; 1165 #size-cells = <0>; 1166 status = "disabled"; 1167 }; 1168 1169 spi19: spi@894000 { 1170 compatible = "qcom,geni-spi"; 1171 reg = <0 0x00894000 0 0x4000>; 1172 clock-names = "se"; 1173 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1174 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1175 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1176 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1177 dma-names = "tx", "rx"; 1178 power-domains = <&rpmhpd SM8250_CX>; 1179 operating-points-v2 = <&qup_opp_table>; 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 status = "disabled"; 1183 }; 1184 }; 1185 1186 gpi_dma0: dma-controller@900000 { 1187 compatible = "qcom,sm8250-gpi-dma"; 1188 reg = <0 0x00900000 0 0x70000>; 1189 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1202 dma-channels = <15>; 1203 dma-channel-mask = <0x7ff>; 1204 iommus = <&apps_smmu 0x5b6 0x0>; 1205 #dma-cells = <3>; 1206 status = "disabled"; 1207 }; 1208 1209 qupv3_id_0: geniqup@9c0000 { 1210 compatible = "qcom,geni-se-qup"; 1211 reg = <0x0 0x009c0000 0x0 0x6000>; 1212 clock-names = "m-ahb", "s-ahb"; 1213 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1214 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1215 #address-cells = <2>; 1216 #size-cells = <2>; 1217 iommus = <&apps_smmu 0x5a3 0x0>; 1218 ranges; 1219 status = "disabled"; 1220 1221 i2c0: i2c@980000 { 1222 compatible = "qcom,geni-i2c"; 1223 reg = <0 0x00980000 0 0x4000>; 1224 clock-names = "se"; 1225 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1226 pinctrl-names = "default"; 1227 pinctrl-0 = <&qup_i2c0_default>; 1228 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1229 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1230 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1231 dma-names = "tx", "rx"; 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 status = "disabled"; 1235 }; 1236 1237 spi0: spi@980000 { 1238 compatible = "qcom,geni-spi"; 1239 reg = <0 0x00980000 0 0x4000>; 1240 clock-names = "se"; 1241 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1242 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1243 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1244 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1245 dma-names = "tx", "rx"; 1246 power-domains = <&rpmhpd SM8250_CX>; 1247 operating-points-v2 = <&qup_opp_table>; 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 status = "disabled"; 1251 }; 1252 1253 i2c1: i2c@984000 { 1254 compatible = "qcom,geni-i2c"; 1255 reg = <0 0x00984000 0 0x4000>; 1256 clock-names = "se"; 1257 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1258 pinctrl-names = "default"; 1259 pinctrl-0 = <&qup_i2c1_default>; 1260 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1261 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1262 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1263 dma-names = "tx", "rx"; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 status = "disabled"; 1267 }; 1268 1269 spi1: spi@984000 { 1270 compatible = "qcom,geni-spi"; 1271 reg = <0 0x00984000 0 0x4000>; 1272 clock-names = "se"; 1273 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1274 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1275 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1276 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1277 dma-names = "tx", "rx"; 1278 power-domains = <&rpmhpd SM8250_CX>; 1279 operating-points-v2 = <&qup_opp_table>; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 status = "disabled"; 1283 }; 1284 1285 i2c2: i2c@988000 { 1286 compatible = "qcom,geni-i2c"; 1287 reg = <0 0x00988000 0 0x4000>; 1288 clock-names = "se"; 1289 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1290 pinctrl-names = "default"; 1291 pinctrl-0 = <&qup_i2c2_default>; 1292 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1293 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1294 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1295 dma-names = "tx", "rx"; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 status = "disabled"; 1299 }; 1300 1301 spi2: spi@988000 { 1302 compatible = "qcom,geni-spi"; 1303 reg = <0 0x00988000 0 0x4000>; 1304 clock-names = "se"; 1305 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1306 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1307 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1308 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1309 dma-names = "tx", "rx"; 1310 power-domains = <&rpmhpd SM8250_CX>; 1311 operating-points-v2 = <&qup_opp_table>; 1312 #address-cells = <1>; 1313 #size-cells = <0>; 1314 status = "disabled"; 1315 }; 1316 1317 uart2: serial@988000 { 1318 compatible = "qcom,geni-debug-uart"; 1319 reg = <0 0x00988000 0 0x4000>; 1320 clock-names = "se"; 1321 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1322 pinctrl-names = "default"; 1323 pinctrl-0 = <&qup_uart2_default>; 1324 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1325 power-domains = <&rpmhpd SM8250_CX>; 1326 operating-points-v2 = <&qup_opp_table>; 1327 status = "disabled"; 1328 }; 1329 1330 i2c3: i2c@98c000 { 1331 compatible = "qcom,geni-i2c"; 1332 reg = <0 0x0098c000 0 0x4000>; 1333 clock-names = "se"; 1334 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1335 pinctrl-names = "default"; 1336 pinctrl-0 = <&qup_i2c3_default>; 1337 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1338 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1339 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1340 dma-names = "tx", "rx"; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 status = "disabled"; 1344 }; 1345 1346 spi3: spi@98c000 { 1347 compatible = "qcom,geni-spi"; 1348 reg = <0 0x0098c000 0 0x4000>; 1349 clock-names = "se"; 1350 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1351 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1352 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1353 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1354 dma-names = "tx", "rx"; 1355 power-domains = <&rpmhpd SM8250_CX>; 1356 operating-points-v2 = <&qup_opp_table>; 1357 #address-cells = <1>; 1358 #size-cells = <0>; 1359 status = "disabled"; 1360 }; 1361 1362 i2c4: i2c@990000 { 1363 compatible = "qcom,geni-i2c"; 1364 reg = <0 0x00990000 0 0x4000>; 1365 clock-names = "se"; 1366 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1367 pinctrl-names = "default"; 1368 pinctrl-0 = <&qup_i2c4_default>; 1369 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1370 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1371 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1372 dma-names = "tx", "rx"; 1373 #address-cells = <1>; 1374 #size-cells = <0>; 1375 status = "disabled"; 1376 }; 1377 1378 spi4: spi@990000 { 1379 compatible = "qcom,geni-spi"; 1380 reg = <0 0x00990000 0 0x4000>; 1381 clock-names = "se"; 1382 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1383 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1384 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1385 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1386 dma-names = "tx", "rx"; 1387 power-domains = <&rpmhpd SM8250_CX>; 1388 operating-points-v2 = <&qup_opp_table>; 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 status = "disabled"; 1392 }; 1393 1394 i2c5: i2c@994000 { 1395 compatible = "qcom,geni-i2c"; 1396 reg = <0 0x00994000 0 0x4000>; 1397 clock-names = "se"; 1398 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1399 pinctrl-names = "default"; 1400 pinctrl-0 = <&qup_i2c5_default>; 1401 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1402 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1403 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1404 dma-names = "tx", "rx"; 1405 #address-cells = <1>; 1406 #size-cells = <0>; 1407 status = "disabled"; 1408 }; 1409 1410 spi5: spi@994000 { 1411 compatible = "qcom,geni-spi"; 1412 reg = <0 0x00994000 0 0x4000>; 1413 clock-names = "se"; 1414 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1415 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1416 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1417 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1418 dma-names = "tx", "rx"; 1419 power-domains = <&rpmhpd SM8250_CX>; 1420 operating-points-v2 = <&qup_opp_table>; 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 status = "disabled"; 1424 }; 1425 1426 i2c6: i2c@998000 { 1427 compatible = "qcom,geni-i2c"; 1428 reg = <0 0x00998000 0 0x4000>; 1429 clock-names = "se"; 1430 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1431 pinctrl-names = "default"; 1432 pinctrl-0 = <&qup_i2c6_default>; 1433 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1434 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1435 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1436 dma-names = "tx", "rx"; 1437 #address-cells = <1>; 1438 #size-cells = <0>; 1439 status = "disabled"; 1440 }; 1441 1442 spi6: spi@998000 { 1443 compatible = "qcom,geni-spi"; 1444 reg = <0 0x00998000 0 0x4000>; 1445 clock-names = "se"; 1446 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1447 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1448 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1449 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1450 dma-names = "tx", "rx"; 1451 power-domains = <&rpmhpd SM8250_CX>; 1452 operating-points-v2 = <&qup_opp_table>; 1453 #address-cells = <1>; 1454 #size-cells = <0>; 1455 status = "disabled"; 1456 }; 1457 1458 uart6: serial@998000 { 1459 compatible = "qcom,geni-uart"; 1460 reg = <0 0x00998000 0 0x4000>; 1461 clock-names = "se"; 1462 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&qup_uart6_default>; 1465 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1466 power-domains = <&rpmhpd SM8250_CX>; 1467 operating-points-v2 = <&qup_opp_table>; 1468 status = "disabled"; 1469 }; 1470 1471 i2c7: i2c@99c000 { 1472 compatible = "qcom,geni-i2c"; 1473 reg = <0 0x0099c000 0 0x4000>; 1474 clock-names = "se"; 1475 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1476 pinctrl-names = "default"; 1477 pinctrl-0 = <&qup_i2c7_default>; 1478 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1479 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1480 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1481 dma-names = "tx", "rx"; 1482 #address-cells = <1>; 1483 #size-cells = <0>; 1484 status = "disabled"; 1485 }; 1486 1487 spi7: spi@99c000 { 1488 compatible = "qcom,geni-spi"; 1489 reg = <0 0x0099c000 0 0x4000>; 1490 clock-names = "se"; 1491 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1492 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1493 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1494 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1495 dma-names = "tx", "rx"; 1496 power-domains = <&rpmhpd SM8250_CX>; 1497 operating-points-v2 = <&qup_opp_table>; 1498 #address-cells = <1>; 1499 #size-cells = <0>; 1500 status = "disabled"; 1501 }; 1502 }; 1503 1504 gpi_dma1: dma-controller@a00000 { 1505 compatible = "qcom,sm8250-gpi-dma"; 1506 reg = <0 0x00a00000 0 0x70000>; 1507 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1517 dma-channels = <10>; 1518 dma-channel-mask = <0x3f>; 1519 iommus = <&apps_smmu 0x56 0x0>; 1520 #dma-cells = <3>; 1521 status = "disabled"; 1522 }; 1523 1524 qupv3_id_1: geniqup@ac0000 { 1525 compatible = "qcom,geni-se-qup"; 1526 reg = <0x0 0x00ac0000 0x0 0x6000>; 1527 clock-names = "m-ahb", "s-ahb"; 1528 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1529 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1530 #address-cells = <2>; 1531 #size-cells = <2>; 1532 iommus = <&apps_smmu 0x43 0x0>; 1533 ranges; 1534 status = "disabled"; 1535 1536 i2c8: i2c@a80000 { 1537 compatible = "qcom,geni-i2c"; 1538 reg = <0 0x00a80000 0 0x4000>; 1539 clock-names = "se"; 1540 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1541 pinctrl-names = "default"; 1542 pinctrl-0 = <&qup_i2c8_default>; 1543 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1544 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1545 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1546 dma-names = "tx", "rx"; 1547 #address-cells = <1>; 1548 #size-cells = <0>; 1549 status = "disabled"; 1550 }; 1551 1552 spi8: spi@a80000 { 1553 compatible = "qcom,geni-spi"; 1554 reg = <0 0x00a80000 0 0x4000>; 1555 clock-names = "se"; 1556 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1557 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1558 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1559 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1560 dma-names = "tx", "rx"; 1561 power-domains = <&rpmhpd SM8250_CX>; 1562 operating-points-v2 = <&qup_opp_table>; 1563 #address-cells = <1>; 1564 #size-cells = <0>; 1565 status = "disabled"; 1566 }; 1567 1568 i2c9: i2c@a84000 { 1569 compatible = "qcom,geni-i2c"; 1570 reg = <0 0x00a84000 0 0x4000>; 1571 clock-names = "se"; 1572 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1573 pinctrl-names = "default"; 1574 pinctrl-0 = <&qup_i2c9_default>; 1575 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1576 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1577 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1578 dma-names = "tx", "rx"; 1579 #address-cells = <1>; 1580 #size-cells = <0>; 1581 status = "disabled"; 1582 }; 1583 1584 spi9: spi@a84000 { 1585 compatible = "qcom,geni-spi"; 1586 reg = <0 0x00a84000 0 0x4000>; 1587 clock-names = "se"; 1588 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1589 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1590 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1591 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1592 dma-names = "tx", "rx"; 1593 power-domains = <&rpmhpd SM8250_CX>; 1594 operating-points-v2 = <&qup_opp_table>; 1595 #address-cells = <1>; 1596 #size-cells = <0>; 1597 status = "disabled"; 1598 }; 1599 1600 i2c10: i2c@a88000 { 1601 compatible = "qcom,geni-i2c"; 1602 reg = <0 0x00a88000 0 0x4000>; 1603 clock-names = "se"; 1604 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1605 pinctrl-names = "default"; 1606 pinctrl-0 = <&qup_i2c10_default>; 1607 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1608 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1609 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1610 dma-names = "tx", "rx"; 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 status = "disabled"; 1614 }; 1615 1616 spi10: spi@a88000 { 1617 compatible = "qcom,geni-spi"; 1618 reg = <0 0x00a88000 0 0x4000>; 1619 clock-names = "se"; 1620 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1621 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1622 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1623 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1624 dma-names = "tx", "rx"; 1625 power-domains = <&rpmhpd SM8250_CX>; 1626 operating-points-v2 = <&qup_opp_table>; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 status = "disabled"; 1630 }; 1631 1632 i2c11: i2c@a8c000 { 1633 compatible = "qcom,geni-i2c"; 1634 reg = <0 0x00a8c000 0 0x4000>; 1635 clock-names = "se"; 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1637 pinctrl-names = "default"; 1638 pinctrl-0 = <&qup_i2c11_default>; 1639 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1640 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1641 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1642 dma-names = "tx", "rx"; 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 status = "disabled"; 1646 }; 1647 1648 spi11: spi@a8c000 { 1649 compatible = "qcom,geni-spi"; 1650 reg = <0 0x00a8c000 0 0x4000>; 1651 clock-names = "se"; 1652 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1653 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1654 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1655 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1656 dma-names = "tx", "rx"; 1657 power-domains = <&rpmhpd SM8250_CX>; 1658 operating-points-v2 = <&qup_opp_table>; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 status = "disabled"; 1662 }; 1663 1664 i2c12: i2c@a90000 { 1665 compatible = "qcom,geni-i2c"; 1666 reg = <0 0x00a90000 0 0x4000>; 1667 clock-names = "se"; 1668 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1669 pinctrl-names = "default"; 1670 pinctrl-0 = <&qup_i2c12_default>; 1671 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1672 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1673 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1674 dma-names = "tx", "rx"; 1675 #address-cells = <1>; 1676 #size-cells = <0>; 1677 status = "disabled"; 1678 }; 1679 1680 spi12: spi@a90000 { 1681 compatible = "qcom,geni-spi"; 1682 reg = <0 0x00a90000 0 0x4000>; 1683 clock-names = "se"; 1684 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1685 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1686 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1687 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1688 dma-names = "tx", "rx"; 1689 power-domains = <&rpmhpd SM8250_CX>; 1690 operating-points-v2 = <&qup_opp_table>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 status = "disabled"; 1694 }; 1695 1696 uart12: serial@a90000 { 1697 compatible = "qcom,geni-debug-uart"; 1698 reg = <0x0 0x00a90000 0x0 0x4000>; 1699 clock-names = "se"; 1700 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1701 pinctrl-names = "default"; 1702 pinctrl-0 = <&qup_uart12_default>; 1703 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1704 power-domains = <&rpmhpd SM8250_CX>; 1705 operating-points-v2 = <&qup_opp_table>; 1706 status = "disabled"; 1707 }; 1708 1709 i2c13: i2c@a94000 { 1710 compatible = "qcom,geni-i2c"; 1711 reg = <0 0x00a94000 0 0x4000>; 1712 clock-names = "se"; 1713 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1714 pinctrl-names = "default"; 1715 pinctrl-0 = <&qup_i2c13_default>; 1716 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1717 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1718 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1719 dma-names = "tx", "rx"; 1720 #address-cells = <1>; 1721 #size-cells = <0>; 1722 status = "disabled"; 1723 }; 1724 1725 spi13: spi@a94000 { 1726 compatible = "qcom,geni-spi"; 1727 reg = <0 0x00a94000 0 0x4000>; 1728 clock-names = "se"; 1729 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1730 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1731 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1732 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1733 dma-names = "tx", "rx"; 1734 power-domains = <&rpmhpd SM8250_CX>; 1735 operating-points-v2 = <&qup_opp_table>; 1736 #address-cells = <1>; 1737 #size-cells = <0>; 1738 status = "disabled"; 1739 }; 1740 }; 1741 1742 config_noc: interconnect@1500000 { 1743 compatible = "qcom,sm8250-config-noc"; 1744 reg = <0 0x01500000 0 0xa580>; 1745 #interconnect-cells = <1>; 1746 qcom,bcm-voters = <&apps_bcm_voter>; 1747 }; 1748 1749 system_noc: interconnect@1620000 { 1750 compatible = "qcom,sm8250-system-noc"; 1751 reg = <0 0x01620000 0 0x1c200>; 1752 #interconnect-cells = <1>; 1753 qcom,bcm-voters = <&apps_bcm_voter>; 1754 }; 1755 1756 mc_virt: interconnect@163d000 { 1757 compatible = "qcom,sm8250-mc-virt"; 1758 reg = <0 0x0163d000 0 0x1000>; 1759 #interconnect-cells = <1>; 1760 qcom,bcm-voters = <&apps_bcm_voter>; 1761 }; 1762 1763 aggre1_noc: interconnect@16e0000 { 1764 compatible = "qcom,sm8250-aggre1-noc"; 1765 reg = <0 0x016e0000 0 0x1f180>; 1766 #interconnect-cells = <1>; 1767 qcom,bcm-voters = <&apps_bcm_voter>; 1768 }; 1769 1770 aggre2_noc: interconnect@1700000 { 1771 compatible = "qcom,sm8250-aggre2-noc"; 1772 reg = <0 0x01700000 0 0x33000>; 1773 #interconnect-cells = <1>; 1774 qcom,bcm-voters = <&apps_bcm_voter>; 1775 }; 1776 1777 compute_noc: interconnect@1733000 { 1778 compatible = "qcom,sm8250-compute-noc"; 1779 reg = <0 0x01733000 0 0xa180>; 1780 #interconnect-cells = <1>; 1781 qcom,bcm-voters = <&apps_bcm_voter>; 1782 }; 1783 1784 mmss_noc: interconnect@1740000 { 1785 compatible = "qcom,sm8250-mmss-noc"; 1786 reg = <0 0x01740000 0 0x1f080>; 1787 #interconnect-cells = <1>; 1788 qcom,bcm-voters = <&apps_bcm_voter>; 1789 }; 1790 1791 pcie0: pci@1c00000 { 1792 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1793 reg = <0 0x01c00000 0 0x3000>, 1794 <0 0x60000000 0 0xf1d>, 1795 <0 0x60000f20 0 0xa8>, 1796 <0 0x60001000 0 0x1000>, 1797 <0 0x60100000 0 0x100000>; 1798 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1799 device_type = "pci"; 1800 linux,pci-domain = <0>; 1801 bus-range = <0x00 0xff>; 1802 num-lanes = <1>; 1803 1804 #address-cells = <3>; 1805 #size-cells = <2>; 1806 1807 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1808 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1809 1810 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1811 interrupt-names = "msi"; 1812 #interrupt-cells = <1>; 1813 interrupt-map-mask = <0 0 0 0x7>; 1814 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1815 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1816 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1817 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1818 1819 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1820 <&gcc GCC_PCIE_0_AUX_CLK>, 1821 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1822 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1823 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1824 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1825 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1826 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1827 clock-names = "pipe", 1828 "aux", 1829 "cfg", 1830 "bus_master", 1831 "bus_slave", 1832 "slave_q2a", 1833 "tbu", 1834 "ddrss_sf_tbu"; 1835 1836 iommus = <&apps_smmu 0x1c00 0x7f>; 1837 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1838 <0x100 &apps_smmu 0x1c01 0x1>; 1839 1840 resets = <&gcc GCC_PCIE_0_BCR>; 1841 reset-names = "pci"; 1842 1843 power-domains = <&gcc PCIE_0_GDSC>; 1844 1845 phys = <&pcie0_lane>; 1846 phy-names = "pciephy"; 1847 1848 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; 1849 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 1850 1851 pinctrl-names = "default"; 1852 pinctrl-0 = <&pcie0_default_state>; 1853 1854 status = "disabled"; 1855 }; 1856 1857 pcie0_phy: phy@1c06000 { 1858 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1859 reg = <0 0x01c06000 0 0x1c0>; 1860 #address-cells = <2>; 1861 #size-cells = <2>; 1862 ranges; 1863 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1864 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1865 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1866 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1867 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1868 1869 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1870 reset-names = "phy"; 1871 1872 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1873 assigned-clock-rates = <100000000>; 1874 1875 status = "disabled"; 1876 1877 pcie0_lane: phy@1c06200 { 1878 reg = <0 0x1c06200 0 0x170>, /* tx */ 1879 <0 0x1c06400 0 0x200>, /* rx */ 1880 <0 0x1c06800 0 0x1f0>, /* pcs */ 1881 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1882 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1883 clock-names = "pipe0"; 1884 1885 #phy-cells = <0>; 1886 clock-output-names = "pcie_0_pipe_clk"; 1887 }; 1888 }; 1889 1890 pcie1: pci@1c08000 { 1891 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1892 reg = <0 0x01c08000 0 0x3000>, 1893 <0 0x40000000 0 0xf1d>, 1894 <0 0x40000f20 0 0xa8>, 1895 <0 0x40001000 0 0x1000>, 1896 <0 0x40100000 0 0x100000>; 1897 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1898 device_type = "pci"; 1899 linux,pci-domain = <1>; 1900 bus-range = <0x00 0xff>; 1901 num-lanes = <2>; 1902 1903 #address-cells = <3>; 1904 #size-cells = <2>; 1905 1906 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1907 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1908 1909 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1910 interrupt-names = "msi"; 1911 #interrupt-cells = <1>; 1912 interrupt-map-mask = <0 0 0 0x7>; 1913 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1914 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1915 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1916 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1917 1918 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1919 <&gcc GCC_PCIE_1_AUX_CLK>, 1920 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1921 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1922 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1923 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1924 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1925 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1926 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1927 clock-names = "pipe", 1928 "aux", 1929 "cfg", 1930 "bus_master", 1931 "bus_slave", 1932 "slave_q2a", 1933 "ref", 1934 "tbu", 1935 "ddrss_sf_tbu"; 1936 1937 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1938 assigned-clock-rates = <19200000>; 1939 1940 iommus = <&apps_smmu 0x1c80 0x7f>; 1941 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1942 <0x100 &apps_smmu 0x1c81 0x1>; 1943 1944 resets = <&gcc GCC_PCIE_1_BCR>; 1945 reset-names = "pci"; 1946 1947 power-domains = <&gcc PCIE_1_GDSC>; 1948 1949 phys = <&pcie1_lane>; 1950 phy-names = "pciephy"; 1951 1952 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; 1953 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; 1954 1955 pinctrl-names = "default"; 1956 pinctrl-0 = <&pcie1_default_state>; 1957 1958 status = "disabled"; 1959 }; 1960 1961 pcie1_phy: phy@1c0e000 { 1962 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1963 reg = <0 0x01c0e000 0 0x1c0>; 1964 #address-cells = <2>; 1965 #size-cells = <2>; 1966 ranges; 1967 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1968 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1969 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1970 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1971 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1972 1973 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1974 reset-names = "phy"; 1975 1976 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1977 assigned-clock-rates = <100000000>; 1978 1979 status = "disabled"; 1980 1981 pcie1_lane: phy@1c0e200 { 1982 reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1983 <0 0x1c0e400 0 0x200>, /* rx0 */ 1984 <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1985 <0 0x1c0e600 0 0x170>, /* tx1 */ 1986 <0 0x1c0e800 0 0x200>, /* rx1 */ 1987 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1988 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1989 clock-names = "pipe0"; 1990 1991 #phy-cells = <0>; 1992 clock-output-names = "pcie_1_pipe_clk"; 1993 }; 1994 }; 1995 1996 pcie2: pci@1c10000 { 1997 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1998 reg = <0 0x01c10000 0 0x3000>, 1999 <0 0x64000000 0 0xf1d>, 2000 <0 0x64000f20 0 0xa8>, 2001 <0 0x64001000 0 0x1000>, 2002 <0 0x64100000 0 0x100000>; 2003 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2004 device_type = "pci"; 2005 linux,pci-domain = <2>; 2006 bus-range = <0x00 0xff>; 2007 num-lanes = <2>; 2008 2009 #address-cells = <3>; 2010 #size-cells = <2>; 2011 2012 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, 2013 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 2014 2015 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2016 interrupt-names = "msi"; 2017 #interrupt-cells = <1>; 2018 interrupt-map-mask = <0 0 0 0x7>; 2019 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2020 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2021 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2022 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2023 2024 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2025 <&gcc GCC_PCIE_2_AUX_CLK>, 2026 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2027 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2028 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2029 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2030 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2031 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2032 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2033 clock-names = "pipe", 2034 "aux", 2035 "cfg", 2036 "bus_master", 2037 "bus_slave", 2038 "slave_q2a", 2039 "ref", 2040 "tbu", 2041 "ddrss_sf_tbu"; 2042 2043 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2044 assigned-clock-rates = <19200000>; 2045 2046 iommus = <&apps_smmu 0x1d00 0x7f>; 2047 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2048 <0x100 &apps_smmu 0x1d01 0x1>; 2049 2050 resets = <&gcc GCC_PCIE_2_BCR>; 2051 reset-names = "pci"; 2052 2053 power-domains = <&gcc PCIE_2_GDSC>; 2054 2055 phys = <&pcie2_lane>; 2056 phy-names = "pciephy"; 2057 2058 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; 2059 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 2060 2061 pinctrl-names = "default"; 2062 pinctrl-0 = <&pcie2_default_state>; 2063 2064 status = "disabled"; 2065 }; 2066 2067 pcie2_phy: phy@1c16000 { 2068 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 2069 reg = <0 0x1c16000 0 0x1c0>; 2070 #address-cells = <2>; 2071 #size-cells = <2>; 2072 ranges; 2073 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2074 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2075 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2076 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2077 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2078 2079 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2080 reset-names = "phy"; 2081 2082 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2083 assigned-clock-rates = <100000000>; 2084 2085 status = "disabled"; 2086 2087 pcie2_lane: phy@1c16200 { 2088 reg = <0 0x1c16200 0 0x170>, /* tx0 */ 2089 <0 0x1c16400 0 0x200>, /* rx0 */ 2090 <0 0x1c16a00 0 0x1f0>, /* pcs */ 2091 <0 0x1c16600 0 0x170>, /* tx1 */ 2092 <0 0x1c16800 0 0x200>, /* rx1 */ 2093 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2094 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 2095 clock-names = "pipe0"; 2096 2097 #phy-cells = <0>; 2098 clock-output-names = "pcie_2_pipe_clk"; 2099 }; 2100 }; 2101 2102 ufs_mem_hc: ufshc@1d84000 { 2103 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 2104 "jedec,ufs-2.0"; 2105 reg = <0 0x01d84000 0 0x3000>; 2106 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2107 phys = <&ufs_mem_phy_lanes>; 2108 phy-names = "ufsphy"; 2109 lanes-per-direction = <2>; 2110 #reset-cells = <1>; 2111 resets = <&gcc GCC_UFS_PHY_BCR>; 2112 reset-names = "rst"; 2113 2114 power-domains = <&gcc UFS_PHY_GDSC>; 2115 2116 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 2117 2118 clock-names = 2119 "core_clk", 2120 "bus_aggr_clk", 2121 "iface_clk", 2122 "core_clk_unipro", 2123 "ref_clk", 2124 "tx_lane0_sync_clk", 2125 "rx_lane0_sync_clk", 2126 "rx_lane1_sync_clk"; 2127 clocks = 2128 <&gcc GCC_UFS_PHY_AXI_CLK>, 2129 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2130 <&gcc GCC_UFS_PHY_AHB_CLK>, 2131 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2132 <&rpmhcc RPMH_CXO_CLK>, 2133 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2134 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2135 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2136 freq-table-hz = 2137 <37500000 300000000>, 2138 <0 0>, 2139 <0 0>, 2140 <37500000 300000000>, 2141 <0 0>, 2142 <0 0>, 2143 <0 0>, 2144 <0 0>; 2145 2146 status = "disabled"; 2147 }; 2148 2149 ufs_mem_phy: phy@1d87000 { 2150 compatible = "qcom,sm8250-qmp-ufs-phy"; 2151 reg = <0 0x01d87000 0 0x1c0>; 2152 #address-cells = <2>; 2153 #size-cells = <2>; 2154 ranges; 2155 clock-names = "ref", 2156 "ref_aux"; 2157 clocks = <&rpmhcc RPMH_CXO_CLK>, 2158 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2159 2160 resets = <&ufs_mem_hc 0>; 2161 reset-names = "ufsphy"; 2162 status = "disabled"; 2163 2164 ufs_mem_phy_lanes: phy@1d87400 { 2165 reg = <0 0x01d87400 0 0x108>, 2166 <0 0x01d87600 0 0x1e0>, 2167 <0 0x01d87c00 0 0x1dc>, 2168 <0 0x01d87800 0 0x108>, 2169 <0 0x01d87a00 0 0x1e0>; 2170 #phy-cells = <0>; 2171 }; 2172 }; 2173 2174 ipa_virt: interconnect@1e00000 { 2175 compatible = "qcom,sm8250-ipa-virt"; 2176 reg = <0 0x01e00000 0 0x1000>; 2177 #interconnect-cells = <1>; 2178 qcom,bcm-voters = <&apps_bcm_voter>; 2179 }; 2180 2181 tcsr_mutex: hwlock@1f40000 { 2182 compatible = "qcom,tcsr-mutex"; 2183 reg = <0x0 0x01f40000 0x0 0x40000>; 2184 #hwlock-cells = <1>; 2185 }; 2186 2187 wsamacro: codec@3240000 { 2188 compatible = "qcom,sm8250-lpass-wsa-macro"; 2189 reg = <0 0x03240000 0 0x1000>; 2190 clocks = <&audiocc 1>, 2191 <&audiocc 0>, 2192 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2193 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2194 <&aoncc 0>, 2195 <&vamacro>; 2196 2197 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 2198 2199 #clock-cells = <0>; 2200 clock-frequency = <9600000>; 2201 clock-output-names = "mclk"; 2202 #sound-dai-cells = <1>; 2203 2204 pinctrl-names = "default"; 2205 pinctrl-0 = <&wsa_swr_active>; 2206 }; 2207 2208 swr0: soundwire-controller@3250000 { 2209 reg = <0 0x03250000 0 0x2000>; 2210 compatible = "qcom,soundwire-v1.5.1"; 2211 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 2212 clocks = <&wsamacro>; 2213 clock-names = "iface"; 2214 2215 qcom,din-ports = <2>; 2216 qcom,dout-ports = <6>; 2217 2218 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2219 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2220 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2221 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 2222 2223 #sound-dai-cells = <1>; 2224 #address-cells = <2>; 2225 #size-cells = <0>; 2226 }; 2227 2228 audiocc: clock-controller@3300000 { 2229 compatible = "qcom,sm8250-lpass-audiocc"; 2230 reg = <0 0x03300000 0 0x30000>; 2231 #clock-cells = <1>; 2232 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2233 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2234 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2235 clock-names = "core", "audio", "bus"; 2236 }; 2237 2238 vamacro: codec@3370000 { 2239 compatible = "qcom,sm8250-lpass-va-macro"; 2240 reg = <0 0x03370000 0 0x1000>; 2241 clocks = <&aoncc 0>, 2242 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2243 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2244 2245 clock-names = "mclk", "macro", "dcodec"; 2246 2247 #clock-cells = <0>; 2248 clock-frequency = <9600000>; 2249 clock-output-names = "fsgen"; 2250 #sound-dai-cells = <1>; 2251 }; 2252 2253 rxmacro: rxmacro@3200000 { 2254 pinctrl-names = "default"; 2255 pinctrl-0 = <&rx_swr_active>; 2256 compatible = "qcom,sm8250-lpass-rx-macro"; 2257 reg = <0 0x3200000 0 0x1000>; 2258 2259 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2260 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2261 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2262 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2263 <&vamacro>; 2264 2265 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2266 2267 #clock-cells = <0>; 2268 clock-frequency = <9600000>; 2269 clock-output-names = "mclk"; 2270 #sound-dai-cells = <1>; 2271 }; 2272 2273 swr1: soundwire-controller@3210000 { 2274 reg = <0 0x3210000 0 0x2000>; 2275 compatible = "qcom,soundwire-v1.5.1"; 2276 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2277 clocks = <&rxmacro>; 2278 clock-names = "iface"; 2279 label = "RX"; 2280 qcom,din-ports = <0>; 2281 qcom,dout-ports = <5>; 2282 2283 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>; 2284 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 2285 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 2286 qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>; 2287 qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>; 2288 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>; 2289 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>; 2290 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2291 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>; 2292 2293 #sound-dai-cells = <1>; 2294 #address-cells = <2>; 2295 #size-cells = <0>; 2296 }; 2297 2298 txmacro: txmacro@3220000 { 2299 pinctrl-names = "default"; 2300 pinctrl-0 = <&tx_swr_active>; 2301 compatible = "qcom,sm8250-lpass-tx-macro"; 2302 reg = <0 0x3220000 0 0x1000>; 2303 2304 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2305 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2306 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2307 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2308 <&vamacro>; 2309 2310 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2311 2312 #clock-cells = <0>; 2313 clock-frequency = <9600000>; 2314 clock-output-names = "mclk"; 2315 #address-cells = <2>; 2316 #size-cells = <2>; 2317 #sound-dai-cells = <1>; 2318 }; 2319 2320 /* tx macro */ 2321 swr2: soundwire-controller@3230000 { 2322 reg = <0 0x3230000 0 0x2000>; 2323 compatible = "qcom,soundwire-v1.5.1"; 2324 interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 2325 interrupt-names = "core"; 2326 2327 clocks = <&txmacro>; 2328 clock-names = "iface"; 2329 label = "TX"; 2330 2331 qcom,din-ports = <5>; 2332 qcom,dout-ports = <0>; 2333 qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>; 2334 qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>; 2335 qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>; 2336 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2337 qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2338 qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2339 qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2340 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2341 qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>; 2342 qcom,port-offset = <1>; 2343 #sound-dai-cells = <1>; 2344 #address-cells = <2>; 2345 #size-cells = <0>; 2346 }; 2347 2348 aoncc: clock-controller@3380000 { 2349 compatible = "qcom,sm8250-lpass-aoncc"; 2350 reg = <0 0x03380000 0 0x40000>; 2351 #clock-cells = <1>; 2352 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2353 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2354 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2355 clock-names = "core", "audio", "bus"; 2356 }; 2357 2358 lpass_tlmm: pinctrl@33c0000{ 2359 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 2360 reg = <0 0x033c0000 0x0 0x20000>, 2361 <0 0x03550000 0x0 0x10000>; 2362 gpio-controller; 2363 #gpio-cells = <2>; 2364 gpio-ranges = <&lpass_tlmm 0 0 14>; 2365 2366 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2367 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2368 clock-names = "core", "audio"; 2369 2370 wsa_swr_active: wsa-swr-active-pins { 2371 clk { 2372 pins = "gpio10"; 2373 function = "wsa_swr_clk"; 2374 drive-strength = <2>; 2375 slew-rate = <1>; 2376 bias-disable; 2377 }; 2378 2379 data { 2380 pins = "gpio11"; 2381 function = "wsa_swr_data"; 2382 drive-strength = <2>; 2383 slew-rate = <1>; 2384 bias-bus-hold; 2385 2386 }; 2387 }; 2388 2389 wsa_swr_sleep: wsa-swr-sleep-pins { 2390 clk { 2391 pins = "gpio10"; 2392 function = "wsa_swr_clk"; 2393 drive-strength = <2>; 2394 input-enable; 2395 bias-pull-down; 2396 }; 2397 2398 data { 2399 pins = "gpio11"; 2400 function = "wsa_swr_data"; 2401 drive-strength = <2>; 2402 input-enable; 2403 bias-pull-down; 2404 2405 }; 2406 }; 2407 2408 dmic01_active: dmic01-active-pins { 2409 clk { 2410 pins = "gpio6"; 2411 function = "dmic1_clk"; 2412 drive-strength = <8>; 2413 output-high; 2414 }; 2415 data { 2416 pins = "gpio7"; 2417 function = "dmic1_data"; 2418 drive-strength = <8>; 2419 input-enable; 2420 }; 2421 }; 2422 2423 dmic01_sleep: dmic01-sleep-pins { 2424 clk { 2425 pins = "gpio6"; 2426 function = "dmic1_clk"; 2427 drive-strength = <2>; 2428 bias-disable; 2429 output-low; 2430 }; 2431 2432 data { 2433 pins = "gpio7"; 2434 function = "dmic1_data"; 2435 drive-strength = <2>; 2436 pull-down; 2437 input-enable; 2438 }; 2439 }; 2440 2441 rx_swr_active: rx_swr-active-pins { 2442 clk { 2443 pins = "gpio3"; 2444 function = "swr_rx_clk"; 2445 drive-strength = <2>; 2446 slew-rate = <1>; 2447 bias-disable; 2448 }; 2449 2450 data { 2451 pins = "gpio4", "gpio5"; 2452 function = "swr_rx_data"; 2453 drive-strength = <2>; 2454 slew-rate = <1>; 2455 bias-bus-hold; 2456 }; 2457 }; 2458 2459 tx_swr_active: tx_swr-active-pins { 2460 clk { 2461 pins = "gpio0"; 2462 function = "swr_tx_clk"; 2463 drive-strength = <2>; 2464 slew-rate = <1>; 2465 bias-disable; 2466 }; 2467 2468 data { 2469 pins = "gpio1", "gpio2"; 2470 function = "swr_tx_data"; 2471 drive-strength = <2>; 2472 slew-rate = <1>; 2473 bias-bus-hold; 2474 }; 2475 }; 2476 2477 tx_swr_sleep: tx_swr-sleep-pins { 2478 clk { 2479 pins = "gpio0"; 2480 function = "swr_tx_clk"; 2481 drive-strength = <2>; 2482 input-enable; 2483 bias-pull-down; 2484 }; 2485 2486 data1 { 2487 pins = "gpio1"; 2488 function = "swr_tx_data"; 2489 drive-strength = <2>; 2490 input-enable; 2491 bias-bus-hold; 2492 }; 2493 2494 data2 { 2495 pins = "gpio2"; 2496 function = "swr_tx_data"; 2497 drive-strength = <2>; 2498 input-enable; 2499 bias-pull-down; 2500 }; 2501 }; 2502 }; 2503 2504 gpu: gpu@3d00000 { 2505 compatible = "qcom,adreno-650.2", 2506 "qcom,adreno"; 2507 2508 reg = <0 0x03d00000 0 0x40000>; 2509 reg-names = "kgsl_3d0_reg_memory"; 2510 2511 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2512 2513 iommus = <&adreno_smmu 0 0x401>; 2514 2515 operating-points-v2 = <&gpu_opp_table>; 2516 2517 qcom,gmu = <&gmu>; 2518 2519 status = "disabled"; 2520 2521 zap-shader { 2522 memory-region = <&gpu_mem>; 2523 }; 2524 2525 /* note: downstream checks gpu binning for 670 Mhz */ 2526 gpu_opp_table: opp-table { 2527 compatible = "operating-points-v2"; 2528 2529 opp-670000000 { 2530 opp-hz = /bits/ 64 <670000000>; 2531 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2532 }; 2533 2534 opp-587000000 { 2535 opp-hz = /bits/ 64 <587000000>; 2536 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2537 }; 2538 2539 opp-525000000 { 2540 opp-hz = /bits/ 64 <525000000>; 2541 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2542 }; 2543 2544 opp-490000000 { 2545 opp-hz = /bits/ 64 <490000000>; 2546 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2547 }; 2548 2549 opp-441600000 { 2550 opp-hz = /bits/ 64 <441600000>; 2551 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2552 }; 2553 2554 opp-400000000 { 2555 opp-hz = /bits/ 64 <400000000>; 2556 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2557 }; 2558 2559 opp-305000000 { 2560 opp-hz = /bits/ 64 <305000000>; 2561 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2562 }; 2563 }; 2564 }; 2565 2566 gmu: gmu@3d6a000 { 2567 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2568 2569 reg = <0 0x03d6a000 0 0x30000>, 2570 <0 0x3de0000 0 0x10000>, 2571 <0 0xb290000 0 0x10000>, 2572 <0 0xb490000 0 0x10000>; 2573 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 2574 2575 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2576 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2577 interrupt-names = "hfi", "gmu"; 2578 2579 clocks = <&gpucc GPU_CC_AHB_CLK>, 2580 <&gpucc GPU_CC_CX_GMU_CLK>, 2581 <&gpucc GPU_CC_CXO_CLK>, 2582 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2583 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2584 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2585 2586 power-domains = <&gpucc GPU_CX_GDSC>, 2587 <&gpucc GPU_GX_GDSC>; 2588 power-domain-names = "cx", "gx"; 2589 2590 iommus = <&adreno_smmu 5 0x400>; 2591 2592 operating-points-v2 = <&gmu_opp_table>; 2593 2594 status = "disabled"; 2595 2596 gmu_opp_table: opp-table { 2597 compatible = "operating-points-v2"; 2598 2599 opp-200000000 { 2600 opp-hz = /bits/ 64 <200000000>; 2601 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2602 }; 2603 }; 2604 }; 2605 2606 gpucc: clock-controller@3d90000 { 2607 compatible = "qcom,sm8250-gpucc"; 2608 reg = <0 0x03d90000 0 0x9000>; 2609 clocks = <&rpmhcc RPMH_CXO_CLK>, 2610 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2611 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2612 clock-names = "bi_tcxo", 2613 "gcc_gpu_gpll0_clk_src", 2614 "gcc_gpu_gpll0_div_clk_src"; 2615 #clock-cells = <1>; 2616 #reset-cells = <1>; 2617 #power-domain-cells = <1>; 2618 }; 2619 2620 adreno_smmu: iommu@3da0000 { 2621 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 2622 reg = <0 0x03da0000 0 0x10000>; 2623 #iommu-cells = <2>; 2624 #global-interrupts = <2>; 2625 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2626 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2627 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2628 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2629 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2630 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2631 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2632 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2633 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2634 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 2635 clocks = <&gpucc GPU_CC_AHB_CLK>, 2636 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2637 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2638 clock-names = "ahb", "bus", "iface"; 2639 2640 power-domains = <&gpucc GPU_CX_GDSC>; 2641 }; 2642 2643 slpi: remoteproc@5c00000 { 2644 compatible = "qcom,sm8250-slpi-pas"; 2645 reg = <0 0x05c00000 0 0x4000>; 2646 2647 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2648 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2649 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2650 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2651 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2652 interrupt-names = "wdog", "fatal", "ready", 2653 "handover", "stop-ack"; 2654 2655 clocks = <&rpmhcc RPMH_CXO_CLK>; 2656 clock-names = "xo"; 2657 2658 power-domains = <&rpmhpd SM8250_LCX>, 2659 <&rpmhpd SM8250_LMX>; 2660 power-domain-names = "lcx", "lmx"; 2661 2662 memory-region = <&slpi_mem>; 2663 2664 qcom,qmp = <&aoss_qmp>; 2665 2666 qcom,smem-states = <&smp2p_slpi_out 0>; 2667 qcom,smem-state-names = "stop"; 2668 2669 status = "disabled"; 2670 2671 glink-edge { 2672 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2673 IPCC_MPROC_SIGNAL_GLINK_QMP 2674 IRQ_TYPE_EDGE_RISING>; 2675 mboxes = <&ipcc IPCC_CLIENT_SLPI 2676 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2677 2678 label = "slpi"; 2679 qcom,remote-pid = <3>; 2680 2681 fastrpc { 2682 compatible = "qcom,fastrpc"; 2683 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2684 label = "sdsp"; 2685 qcom,non-secure-domain; 2686 #address-cells = <1>; 2687 #size-cells = <0>; 2688 2689 compute-cb@1 { 2690 compatible = "qcom,fastrpc-compute-cb"; 2691 reg = <1>; 2692 iommus = <&apps_smmu 0x0541 0x0>; 2693 }; 2694 2695 compute-cb@2 { 2696 compatible = "qcom,fastrpc-compute-cb"; 2697 reg = <2>; 2698 iommus = <&apps_smmu 0x0542 0x0>; 2699 }; 2700 2701 compute-cb@3 { 2702 compatible = "qcom,fastrpc-compute-cb"; 2703 reg = <3>; 2704 iommus = <&apps_smmu 0x0543 0x0>; 2705 /* note: shared-cb = <4> in downstream */ 2706 }; 2707 }; 2708 }; 2709 }; 2710 2711 cdsp: remoteproc@8300000 { 2712 compatible = "qcom,sm8250-cdsp-pas"; 2713 reg = <0 0x08300000 0 0x10000>; 2714 2715 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 2716 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2717 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2718 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2719 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2720 interrupt-names = "wdog", "fatal", "ready", 2721 "handover", "stop-ack"; 2722 2723 clocks = <&rpmhcc RPMH_CXO_CLK>; 2724 clock-names = "xo"; 2725 2726 power-domains = <&rpmhpd SM8250_CX>; 2727 2728 memory-region = <&cdsp_mem>; 2729 2730 qcom,qmp = <&aoss_qmp>; 2731 2732 qcom,smem-states = <&smp2p_cdsp_out 0>; 2733 qcom,smem-state-names = "stop"; 2734 2735 status = "disabled"; 2736 2737 glink-edge { 2738 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2739 IPCC_MPROC_SIGNAL_GLINK_QMP 2740 IRQ_TYPE_EDGE_RISING>; 2741 mboxes = <&ipcc IPCC_CLIENT_CDSP 2742 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2743 2744 label = "cdsp"; 2745 qcom,remote-pid = <5>; 2746 2747 fastrpc { 2748 compatible = "qcom,fastrpc"; 2749 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2750 label = "cdsp"; 2751 qcom,non-secure-domain; 2752 #address-cells = <1>; 2753 #size-cells = <0>; 2754 2755 compute-cb@1 { 2756 compatible = "qcom,fastrpc-compute-cb"; 2757 reg = <1>; 2758 iommus = <&apps_smmu 0x1001 0x0460>; 2759 }; 2760 2761 compute-cb@2 { 2762 compatible = "qcom,fastrpc-compute-cb"; 2763 reg = <2>; 2764 iommus = <&apps_smmu 0x1002 0x0460>; 2765 }; 2766 2767 compute-cb@3 { 2768 compatible = "qcom,fastrpc-compute-cb"; 2769 reg = <3>; 2770 iommus = <&apps_smmu 0x1003 0x0460>; 2771 }; 2772 2773 compute-cb@4 { 2774 compatible = "qcom,fastrpc-compute-cb"; 2775 reg = <4>; 2776 iommus = <&apps_smmu 0x1004 0x0460>; 2777 }; 2778 2779 compute-cb@5 { 2780 compatible = "qcom,fastrpc-compute-cb"; 2781 reg = <5>; 2782 iommus = <&apps_smmu 0x1005 0x0460>; 2783 }; 2784 2785 compute-cb@6 { 2786 compatible = "qcom,fastrpc-compute-cb"; 2787 reg = <6>; 2788 iommus = <&apps_smmu 0x1006 0x0460>; 2789 }; 2790 2791 compute-cb@7 { 2792 compatible = "qcom,fastrpc-compute-cb"; 2793 reg = <7>; 2794 iommus = <&apps_smmu 0x1007 0x0460>; 2795 }; 2796 2797 compute-cb@8 { 2798 compatible = "qcom,fastrpc-compute-cb"; 2799 reg = <8>; 2800 iommus = <&apps_smmu 0x1008 0x0460>; 2801 }; 2802 2803 /* note: secure cb9 in downstream */ 2804 }; 2805 }; 2806 }; 2807 2808 sound: sound { 2809 }; 2810 2811 usb_1_hsphy: phy@88e3000 { 2812 compatible = "qcom,sm8250-usb-hs-phy", 2813 "qcom,usb-snps-hs-7nm-phy"; 2814 reg = <0 0x088e3000 0 0x400>; 2815 status = "disabled"; 2816 #phy-cells = <0>; 2817 2818 clocks = <&rpmhcc RPMH_CXO_CLK>; 2819 clock-names = "ref"; 2820 2821 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2822 }; 2823 2824 usb_2_hsphy: phy@88e4000 { 2825 compatible = "qcom,sm8250-usb-hs-phy", 2826 "qcom,usb-snps-hs-7nm-phy"; 2827 reg = <0 0x088e4000 0 0x400>; 2828 status = "disabled"; 2829 #phy-cells = <0>; 2830 2831 clocks = <&rpmhcc RPMH_CXO_CLK>; 2832 clock-names = "ref"; 2833 2834 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2835 }; 2836 2837 usb_1_qmpphy: phy@88e9000 { 2838 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 2839 reg = <0 0x088e9000 0 0x200>, 2840 <0 0x088e8000 0 0x40>, 2841 <0 0x088ea000 0 0x200>; 2842 status = "disabled"; 2843 #address-cells = <2>; 2844 #size-cells = <2>; 2845 ranges; 2846 2847 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2848 <&rpmhcc RPMH_CXO_CLK>, 2849 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2850 clock-names = "aux", "ref_clk_src", "com_aux"; 2851 2852 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2853 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2854 reset-names = "phy", "common"; 2855 2856 usb_1_ssphy: usb3-phy@88e9200 { 2857 reg = <0 0x088e9200 0 0x200>, 2858 <0 0x088e9400 0 0x200>, 2859 <0 0x088e9c00 0 0x400>, 2860 <0 0x088e9600 0 0x200>, 2861 <0 0x088e9800 0 0x200>, 2862 <0 0x088e9a00 0 0x100>; 2863 #clock-cells = <0>; 2864 #phy-cells = <0>; 2865 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2866 clock-names = "pipe0"; 2867 clock-output-names = "usb3_phy_pipe_clk_src"; 2868 }; 2869 2870 dp_phy: dp-phy@88ea200 { 2871 reg = <0 0x088ea200 0 0x200>, 2872 <0 0x088ea400 0 0x200>, 2873 <0 0x088eac00 0 0x400>, 2874 <0 0x088ea600 0 0x200>, 2875 <0 0x088ea800 0 0x200>, 2876 <0 0x088eaa00 0 0x100>; 2877 #phy-cells = <0>; 2878 #clock-cells = <1>; 2879 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2880 clock-names = "pipe0"; 2881 clock-output-names = "usb3_phy_pipe_clk_src"; 2882 }; 2883 }; 2884 2885 usb_2_qmpphy: phy@88eb000 { 2886 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 2887 reg = <0 0x088eb000 0 0x200>; 2888 status = "disabled"; 2889 #address-cells = <2>; 2890 #size-cells = <2>; 2891 ranges; 2892 2893 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2894 <&rpmhcc RPMH_CXO_CLK>, 2895 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2896 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2897 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2898 2899 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2900 <&gcc GCC_USB3_PHY_SEC_BCR>; 2901 reset-names = "phy", "common"; 2902 2903 usb_2_ssphy: phy@88eb200 { 2904 reg = <0 0x088eb200 0 0x200>, 2905 <0 0x088eb400 0 0x200>, 2906 <0 0x088eb800 0 0x800>; 2907 #clock-cells = <0>; 2908 #phy-cells = <0>; 2909 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2910 clock-names = "pipe0"; 2911 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2912 }; 2913 }; 2914 2915 sdhc_2: sdhci@8804000 { 2916 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 2917 reg = <0 0x08804000 0 0x1000>; 2918 2919 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2920 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2921 interrupt-names = "hc_irq", "pwr_irq"; 2922 2923 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2924 <&gcc GCC_SDCC2_APPS_CLK>, 2925 <&rpmhcc RPMH_CXO_CLK>; 2926 clock-names = "iface", "core", "xo"; 2927 iommus = <&apps_smmu 0x4a0 0x0>; 2928 qcom,dll-config = <0x0007642c>; 2929 qcom,ddr-config = <0x80040868>; 2930 power-domains = <&rpmhpd SM8250_CX>; 2931 operating-points-v2 = <&sdhc2_opp_table>; 2932 2933 status = "disabled"; 2934 2935 sdhc2_opp_table: sdhc2-opp-table { 2936 compatible = "operating-points-v2"; 2937 2938 opp-19200000 { 2939 opp-hz = /bits/ 64 <19200000>; 2940 required-opps = <&rpmhpd_opp_min_svs>; 2941 }; 2942 2943 opp-50000000 { 2944 opp-hz = /bits/ 64 <50000000>; 2945 required-opps = <&rpmhpd_opp_low_svs>; 2946 }; 2947 2948 opp-100000000 { 2949 opp-hz = /bits/ 64 <100000000>; 2950 required-opps = <&rpmhpd_opp_svs>; 2951 }; 2952 2953 opp-202000000 { 2954 opp-hz = /bits/ 64 <202000000>; 2955 required-opps = <&rpmhpd_opp_svs_l1>; 2956 }; 2957 }; 2958 }; 2959 2960 dc_noc: interconnect@90c0000 { 2961 compatible = "qcom,sm8250-dc-noc"; 2962 reg = <0 0x090c0000 0 0x4200>; 2963 #interconnect-cells = <1>; 2964 qcom,bcm-voters = <&apps_bcm_voter>; 2965 }; 2966 2967 gem_noc: interconnect@9100000 { 2968 compatible = "qcom,sm8250-gem-noc"; 2969 reg = <0 0x09100000 0 0xb4000>; 2970 #interconnect-cells = <1>; 2971 qcom,bcm-voters = <&apps_bcm_voter>; 2972 }; 2973 2974 npu_noc: interconnect@9990000 { 2975 compatible = "qcom,sm8250-npu-noc"; 2976 reg = <0 0x09990000 0 0x1600>; 2977 #interconnect-cells = <1>; 2978 qcom,bcm-voters = <&apps_bcm_voter>; 2979 }; 2980 2981 usb_1: usb@a6f8800 { 2982 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 2983 reg = <0 0x0a6f8800 0 0x400>; 2984 status = "disabled"; 2985 #address-cells = <2>; 2986 #size-cells = <2>; 2987 ranges; 2988 dma-ranges; 2989 2990 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2991 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2992 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2993 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2994 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2995 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2996 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2997 "sleep", "xo"; 2998 2999 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3000 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3001 assigned-clock-rates = <19200000>, <200000000>; 3002 3003 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3004 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3005 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3006 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3007 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 3008 "dm_hs_phy_irq", "ss_phy_irq"; 3009 3010 power-domains = <&gcc USB30_PRIM_GDSC>; 3011 3012 resets = <&gcc GCC_USB30_PRIM_BCR>; 3013 3014 usb_1_dwc3: usb@a600000 { 3015 compatible = "snps,dwc3"; 3016 reg = <0 0x0a600000 0 0xcd00>; 3017 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3018 iommus = <&apps_smmu 0x0 0x0>; 3019 snps,dis_u2_susphy_quirk; 3020 snps,dis_enblslpm_quirk; 3021 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3022 phy-names = "usb2-phy", "usb3-phy"; 3023 }; 3024 }; 3025 3026 system-cache-controller@9200000 { 3027 compatible = "qcom,sm8250-llcc"; 3028 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 3029 reg-names = "llcc_base", "llcc_broadcast_base"; 3030 }; 3031 3032 usb_2: usb@a8f8800 { 3033 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3034 reg = <0 0x0a8f8800 0 0x400>; 3035 status = "disabled"; 3036 #address-cells = <2>; 3037 #size-cells = <2>; 3038 ranges; 3039 dma-ranges; 3040 3041 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3042 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3043 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3044 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3045 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3046 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3047 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3048 "sleep", "xo"; 3049 3050 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3051 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3052 assigned-clock-rates = <19200000>, <200000000>; 3053 3054 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3055 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3056 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3057 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 3058 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 3059 "dm_hs_phy_irq", "ss_phy_irq"; 3060 3061 power-domains = <&gcc USB30_SEC_GDSC>; 3062 3063 resets = <&gcc GCC_USB30_SEC_BCR>; 3064 3065 usb_2_dwc3: usb@a800000 { 3066 compatible = "snps,dwc3"; 3067 reg = <0 0x0a800000 0 0xcd00>; 3068 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3069 iommus = <&apps_smmu 0x20 0>; 3070 snps,dis_u2_susphy_quirk; 3071 snps,dis_enblslpm_quirk; 3072 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3073 phy-names = "usb2-phy", "usb3-phy"; 3074 }; 3075 }; 3076 3077 venus: video-codec@aa00000 { 3078 compatible = "qcom,sm8250-venus"; 3079 reg = <0 0x0aa00000 0 0x100000>; 3080 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3081 power-domains = <&videocc MVS0C_GDSC>, 3082 <&videocc MVS0_GDSC>, 3083 <&rpmhpd SM8250_MX>; 3084 power-domain-names = "venus", "vcodec0", "mx"; 3085 operating-points-v2 = <&venus_opp_table>; 3086 3087 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 3088 <&videocc VIDEO_CC_MVS0C_CLK>, 3089 <&videocc VIDEO_CC_MVS0_CLK>; 3090 clock-names = "iface", "core", "vcodec0_core"; 3091 3092 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, 3093 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; 3094 interconnect-names = "cpu-cfg", "video-mem"; 3095 3096 iommus = <&apps_smmu 0x2100 0x0400>; 3097 memory-region = <&video_mem>; 3098 3099 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 3100 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 3101 reset-names = "bus", "core"; 3102 3103 status = "disabled"; 3104 3105 video-decoder { 3106 compatible = "venus-decoder"; 3107 }; 3108 3109 video-encoder { 3110 compatible = "venus-encoder"; 3111 }; 3112 3113 venus_opp_table: venus-opp-table { 3114 compatible = "operating-points-v2"; 3115 3116 opp-720000000 { 3117 opp-hz = /bits/ 64 <720000000>; 3118 required-opps = <&rpmhpd_opp_low_svs>; 3119 }; 3120 3121 opp-1014000000 { 3122 opp-hz = /bits/ 64 <1014000000>; 3123 required-opps = <&rpmhpd_opp_svs>; 3124 }; 3125 3126 opp-1098000000 { 3127 opp-hz = /bits/ 64 <1098000000>; 3128 required-opps = <&rpmhpd_opp_svs_l1>; 3129 }; 3130 3131 opp-1332000000 { 3132 opp-hz = /bits/ 64 <1332000000>; 3133 required-opps = <&rpmhpd_opp_nom>; 3134 }; 3135 }; 3136 }; 3137 3138 videocc: clock-controller@abf0000 { 3139 compatible = "qcom,sm8250-videocc"; 3140 reg = <0 0x0abf0000 0 0x10000>; 3141 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 3142 <&rpmhcc RPMH_CXO_CLK>, 3143 <&rpmhcc RPMH_CXO_CLK_A>; 3144 power-domains = <&rpmhpd SM8250_MMCX>; 3145 required-opps = <&rpmhpd_opp_low_svs>; 3146 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 3147 #clock-cells = <1>; 3148 #reset-cells = <1>; 3149 #power-domain-cells = <1>; 3150 }; 3151 3152 mdss: mdss@ae00000 { 3153 compatible = "qcom,sm8250-mdss"; 3154 reg = <0 0x0ae00000 0 0x1000>; 3155 reg-names = "mdss"; 3156 3157 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 3158 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 3159 interconnect-names = "mdp0-mem", "mdp1-mem"; 3160 3161 power-domains = <&dispcc MDSS_GDSC>; 3162 3163 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3164 <&gcc GCC_DISP_HF_AXI_CLK>, 3165 <&gcc GCC_DISP_SF_AXI_CLK>, 3166 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3167 clock-names = "iface", "bus", "nrt_bus", "core"; 3168 3169 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 3170 assigned-clock-rates = <460000000>; 3171 3172 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3173 interrupt-controller; 3174 #interrupt-cells = <1>; 3175 3176 iommus = <&apps_smmu 0x820 0x402>; 3177 3178 status = "disabled"; 3179 3180 #address-cells = <2>; 3181 #size-cells = <2>; 3182 ranges; 3183 3184 mdss_mdp: mdp@ae01000 { 3185 compatible = "qcom,sm8250-dpu"; 3186 reg = <0 0x0ae01000 0 0x8f000>, 3187 <0 0x0aeb0000 0 0x2008>; 3188 reg-names = "mdp", "vbif"; 3189 3190 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3191 <&gcc GCC_DISP_HF_AXI_CLK>, 3192 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3193 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3194 clock-names = "iface", "bus", "core", "vsync"; 3195 3196 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3197 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3198 assigned-clock-rates = <460000000>, 3199 <19200000>; 3200 3201 operating-points-v2 = <&mdp_opp_table>; 3202 power-domains = <&rpmhpd SM8250_MMCX>; 3203 3204 interrupt-parent = <&mdss>; 3205 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 3206 3207 ports { 3208 #address-cells = <1>; 3209 #size-cells = <0>; 3210 3211 port@0 { 3212 reg = <0>; 3213 dpu_intf1_out: endpoint { 3214 remote-endpoint = <&dsi0_in>; 3215 }; 3216 }; 3217 3218 port@1 { 3219 reg = <1>; 3220 dpu_intf2_out: endpoint { 3221 remote-endpoint = <&dsi1_in>; 3222 }; 3223 }; 3224 }; 3225 3226 mdp_opp_table: mdp-opp-table { 3227 compatible = "operating-points-v2"; 3228 3229 opp-200000000 { 3230 opp-hz = /bits/ 64 <200000000>; 3231 required-opps = <&rpmhpd_opp_low_svs>; 3232 }; 3233 3234 opp-300000000 { 3235 opp-hz = /bits/ 64 <300000000>; 3236 required-opps = <&rpmhpd_opp_svs>; 3237 }; 3238 3239 opp-345000000 { 3240 opp-hz = /bits/ 64 <345000000>; 3241 required-opps = <&rpmhpd_opp_svs_l1>; 3242 }; 3243 3244 opp-460000000 { 3245 opp-hz = /bits/ 64 <460000000>; 3246 required-opps = <&rpmhpd_opp_nom>; 3247 }; 3248 }; 3249 }; 3250 3251 dsi0: dsi@ae94000 { 3252 compatible = "qcom,mdss-dsi-ctrl"; 3253 reg = <0 0x0ae94000 0 0x400>; 3254 reg-names = "dsi_ctrl"; 3255 3256 interrupt-parent = <&mdss>; 3257 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 3258 3259 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3260 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3261 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3262 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3263 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3264 <&gcc GCC_DISP_HF_AXI_CLK>; 3265 clock-names = "byte", 3266 "byte_intf", 3267 "pixel", 3268 "core", 3269 "iface", 3270 "bus"; 3271 3272 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3273 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 3274 3275 operating-points-v2 = <&dsi_opp_table>; 3276 power-domains = <&rpmhpd SM8250_MMCX>; 3277 3278 phys = <&dsi0_phy>; 3279 phy-names = "dsi"; 3280 3281 status = "disabled"; 3282 3283 #address-cells = <1>; 3284 #size-cells = <0>; 3285 3286 ports { 3287 #address-cells = <1>; 3288 #size-cells = <0>; 3289 3290 port@0 { 3291 reg = <0>; 3292 dsi0_in: endpoint { 3293 remote-endpoint = <&dpu_intf1_out>; 3294 }; 3295 }; 3296 3297 port@1 { 3298 reg = <1>; 3299 dsi0_out: endpoint { 3300 }; 3301 }; 3302 }; 3303 }; 3304 3305 dsi0_phy: dsi-phy@ae94400 { 3306 compatible = "qcom,dsi-phy-7nm"; 3307 reg = <0 0x0ae94400 0 0x200>, 3308 <0 0x0ae94600 0 0x280>, 3309 <0 0x0ae94900 0 0x260>; 3310 reg-names = "dsi_phy", 3311 "dsi_phy_lane", 3312 "dsi_pll"; 3313 3314 #clock-cells = <1>; 3315 #phy-cells = <0>; 3316 3317 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3318 <&rpmhcc RPMH_CXO_CLK>; 3319 clock-names = "iface", "ref"; 3320 3321 status = "disabled"; 3322 }; 3323 3324 dsi1: dsi@ae96000 { 3325 compatible = "qcom,mdss-dsi-ctrl"; 3326 reg = <0 0x0ae96000 0 0x400>; 3327 reg-names = "dsi_ctrl"; 3328 3329 interrupt-parent = <&mdss>; 3330 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 3331 3332 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3333 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3334 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3335 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3336 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3337 <&gcc GCC_DISP_HF_AXI_CLK>; 3338 clock-names = "byte", 3339 "byte_intf", 3340 "pixel", 3341 "core", 3342 "iface", 3343 "bus"; 3344 3345 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3346 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 3347 3348 operating-points-v2 = <&dsi_opp_table>; 3349 power-domains = <&rpmhpd SM8250_MMCX>; 3350 3351 phys = <&dsi1_phy>; 3352 phy-names = "dsi"; 3353 3354 status = "disabled"; 3355 3356 #address-cells = <1>; 3357 #size-cells = <0>; 3358 3359 ports { 3360 #address-cells = <1>; 3361 #size-cells = <0>; 3362 3363 port@0 { 3364 reg = <0>; 3365 dsi1_in: endpoint { 3366 remote-endpoint = <&dpu_intf2_out>; 3367 }; 3368 }; 3369 3370 port@1 { 3371 reg = <1>; 3372 dsi1_out: endpoint { 3373 }; 3374 }; 3375 }; 3376 }; 3377 3378 dsi1_phy: dsi-phy@ae96400 { 3379 compatible = "qcom,dsi-phy-7nm"; 3380 reg = <0 0x0ae96400 0 0x200>, 3381 <0 0x0ae96600 0 0x280>, 3382 <0 0x0ae96900 0 0x260>; 3383 reg-names = "dsi_phy", 3384 "dsi_phy_lane", 3385 "dsi_pll"; 3386 3387 #clock-cells = <1>; 3388 #phy-cells = <0>; 3389 3390 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3391 <&rpmhcc RPMH_CXO_CLK>; 3392 clock-names = "iface", "ref"; 3393 3394 status = "disabled"; 3395 3396 dsi_opp_table: dsi-opp-table { 3397 compatible = "operating-points-v2"; 3398 3399 opp-187500000 { 3400 opp-hz = /bits/ 64 <187500000>; 3401 required-opps = <&rpmhpd_opp_low_svs>; 3402 }; 3403 3404 opp-300000000 { 3405 opp-hz = /bits/ 64 <300000000>; 3406 required-opps = <&rpmhpd_opp_svs>; 3407 }; 3408 3409 opp-358000000 { 3410 opp-hz = /bits/ 64 <358000000>; 3411 required-opps = <&rpmhpd_opp_svs_l1>; 3412 }; 3413 }; 3414 }; 3415 }; 3416 3417 dispcc: clock-controller@af00000 { 3418 compatible = "qcom,sm8250-dispcc"; 3419 reg = <0 0x0af00000 0 0x10000>; 3420 power-domains = <&rpmhpd SM8250_MMCX>; 3421 required-opps = <&rpmhpd_opp_low_svs>; 3422 clocks = <&rpmhcc RPMH_CXO_CLK>, 3423 <&dsi0_phy 0>, 3424 <&dsi0_phy 1>, 3425 <&dsi1_phy 0>, 3426 <&dsi1_phy 1>, 3427 <&dp_phy 0>, 3428 <&dp_phy 1>; 3429 clock-names = "bi_tcxo", 3430 "dsi0_phy_pll_out_byteclk", 3431 "dsi0_phy_pll_out_dsiclk", 3432 "dsi1_phy_pll_out_byteclk", 3433 "dsi1_phy_pll_out_dsiclk", 3434 "dp_phy_pll_link_clk", 3435 "dp_phy_pll_vco_div_clk"; 3436 #clock-cells = <1>; 3437 #reset-cells = <1>; 3438 #power-domain-cells = <1>; 3439 }; 3440 3441 pdc: interrupt-controller@b220000 { 3442 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 3443 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 3444 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3445 <125 63 1>, <126 716 12>; 3446 #interrupt-cells = <2>; 3447 interrupt-parent = <&intc>; 3448 interrupt-controller; 3449 }; 3450 3451 tsens0: thermal-sensor@c263000 { 3452 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 3453 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3454 <0 0x0c222000 0 0x1ff>; /* SROT */ 3455 #qcom,sensors = <16>; 3456 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3457 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3458 interrupt-names = "uplow", "critical"; 3459 #thermal-sensor-cells = <1>; 3460 }; 3461 3462 tsens1: thermal-sensor@c265000 { 3463 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 3464 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3465 <0 0x0c223000 0 0x1ff>; /* SROT */ 3466 #qcom,sensors = <9>; 3467 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3468 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3469 interrupt-names = "uplow", "critical"; 3470 #thermal-sensor-cells = <1>; 3471 }; 3472 3473 aoss_qmp: power-controller@c300000 { 3474 compatible = "qcom,sm8250-aoss-qmp"; 3475 reg = <0 0x0c300000 0 0x400>; 3476 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3477 IPCC_MPROC_SIGNAL_GLINK_QMP 3478 IRQ_TYPE_EDGE_RISING>; 3479 mboxes = <&ipcc IPCC_CLIENT_AOP 3480 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3481 3482 #clock-cells = <0>; 3483 }; 3484 3485 sram@c3f0000 { 3486 compatible = "qcom,rpmh-stats"; 3487 reg = <0 0x0c3f0000 0 0x400>; 3488 }; 3489 3490 spmi_bus: spmi@c440000 { 3491 compatible = "qcom,spmi-pmic-arb"; 3492 reg = <0x0 0x0c440000 0x0 0x0001100>, 3493 <0x0 0x0c600000 0x0 0x2000000>, 3494 <0x0 0x0e600000 0x0 0x0100000>, 3495 <0x0 0x0e700000 0x0 0x00a0000>, 3496 <0x0 0x0c40a000 0x0 0x0026000>; 3497 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3498 interrupt-names = "periph_irq"; 3499 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3500 qcom,ee = <0>; 3501 qcom,channel = <0>; 3502 #address-cells = <2>; 3503 #size-cells = <0>; 3504 interrupt-controller; 3505 #interrupt-cells = <4>; 3506 }; 3507 3508 tlmm: pinctrl@f100000 { 3509 compatible = "qcom,sm8250-pinctrl"; 3510 reg = <0 0x0f100000 0 0x300000>, 3511 <0 0x0f500000 0 0x300000>, 3512 <0 0x0f900000 0 0x300000>; 3513 reg-names = "west", "south", "north"; 3514 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3515 gpio-controller; 3516 #gpio-cells = <2>; 3517 interrupt-controller; 3518 #interrupt-cells = <2>; 3519 gpio-ranges = <&tlmm 0 0 181>; 3520 wakeup-parent = <&pdc>; 3521 3522 pri_mi2s_active: pri-mi2s-active { 3523 sclk { 3524 pins = "gpio138"; 3525 function = "mi2s0_sck"; 3526 drive-strength = <8>; 3527 bias-disable; 3528 }; 3529 3530 ws { 3531 pins = "gpio141"; 3532 function = "mi2s0_ws"; 3533 drive-strength = <8>; 3534 output-high; 3535 }; 3536 3537 data0 { 3538 pins = "gpio139"; 3539 function = "mi2s0_data0"; 3540 drive-strength = <8>; 3541 bias-disable; 3542 output-high; 3543 }; 3544 3545 data1 { 3546 pins = "gpio140"; 3547 function = "mi2s0_data1"; 3548 drive-strength = <8>; 3549 output-high; 3550 }; 3551 }; 3552 3553 qup_i2c0_default: qup-i2c0-default { 3554 mux { 3555 pins = "gpio28", "gpio29"; 3556 function = "qup0"; 3557 }; 3558 3559 config { 3560 pins = "gpio28", "gpio29"; 3561 drive-strength = <2>; 3562 bias-disable; 3563 }; 3564 }; 3565 3566 qup_i2c1_default: qup-i2c1-default { 3567 pinmux { 3568 pins = "gpio4", "gpio5"; 3569 function = "qup1"; 3570 }; 3571 3572 config { 3573 pins = "gpio4", "gpio5"; 3574 drive-strength = <2>; 3575 bias-disable; 3576 }; 3577 }; 3578 3579 qup_i2c2_default: qup-i2c2-default { 3580 mux { 3581 pins = "gpio115", "gpio116"; 3582 function = "qup2"; 3583 }; 3584 3585 config { 3586 pins = "gpio115", "gpio116"; 3587 drive-strength = <2>; 3588 bias-disable; 3589 }; 3590 }; 3591 3592 qup_i2c3_default: qup-i2c3-default { 3593 mux { 3594 pins = "gpio119", "gpio120"; 3595 function = "qup3"; 3596 }; 3597 3598 config { 3599 pins = "gpio119", "gpio120"; 3600 drive-strength = <2>; 3601 bias-disable; 3602 }; 3603 }; 3604 3605 qup_i2c4_default: qup-i2c4-default { 3606 mux { 3607 pins = "gpio8", "gpio9"; 3608 function = "qup4"; 3609 }; 3610 3611 config { 3612 pins = "gpio8", "gpio9"; 3613 drive-strength = <2>; 3614 bias-disable; 3615 }; 3616 }; 3617 3618 qup_i2c5_default: qup-i2c5-default { 3619 mux { 3620 pins = "gpio12", "gpio13"; 3621 function = "qup5"; 3622 }; 3623 3624 config { 3625 pins = "gpio12", "gpio13"; 3626 drive-strength = <2>; 3627 bias-disable; 3628 }; 3629 }; 3630 3631 qup_i2c6_default: qup-i2c6-default { 3632 mux { 3633 pins = "gpio16", "gpio17"; 3634 function = "qup6"; 3635 }; 3636 3637 config { 3638 pins = "gpio16", "gpio17"; 3639 drive-strength = <2>; 3640 bias-disable; 3641 }; 3642 }; 3643 3644 qup_i2c7_default: qup-i2c7-default { 3645 mux { 3646 pins = "gpio20", "gpio21"; 3647 function = "qup7"; 3648 }; 3649 3650 config { 3651 pins = "gpio20", "gpio21"; 3652 drive-strength = <2>; 3653 bias-disable; 3654 }; 3655 }; 3656 3657 qup_i2c8_default: qup-i2c8-default { 3658 mux { 3659 pins = "gpio24", "gpio25"; 3660 function = "qup8"; 3661 }; 3662 3663 config { 3664 pins = "gpio24", "gpio25"; 3665 drive-strength = <2>; 3666 bias-disable; 3667 }; 3668 }; 3669 3670 qup_i2c9_default: qup-i2c9-default { 3671 mux { 3672 pins = "gpio125", "gpio126"; 3673 function = "qup9"; 3674 }; 3675 3676 config { 3677 pins = "gpio125", "gpio126"; 3678 drive-strength = <2>; 3679 bias-disable; 3680 }; 3681 }; 3682 3683 qup_i2c10_default: qup-i2c10-default { 3684 mux { 3685 pins = "gpio129", "gpio130"; 3686 function = "qup10"; 3687 }; 3688 3689 config { 3690 pins = "gpio129", "gpio130"; 3691 drive-strength = <2>; 3692 bias-disable; 3693 }; 3694 }; 3695 3696 qup_i2c11_default: qup-i2c11-default { 3697 mux { 3698 pins = "gpio60", "gpio61"; 3699 function = "qup11"; 3700 }; 3701 3702 config { 3703 pins = "gpio60", "gpio61"; 3704 drive-strength = <2>; 3705 bias-disable; 3706 }; 3707 }; 3708 3709 qup_i2c12_default: qup-i2c12-default { 3710 mux { 3711 pins = "gpio32", "gpio33"; 3712 function = "qup12"; 3713 }; 3714 3715 config { 3716 pins = "gpio32", "gpio33"; 3717 drive-strength = <2>; 3718 bias-disable; 3719 }; 3720 }; 3721 3722 qup_i2c13_default: qup-i2c13-default { 3723 mux { 3724 pins = "gpio36", "gpio37"; 3725 function = "qup13"; 3726 }; 3727 3728 config { 3729 pins = "gpio36", "gpio37"; 3730 drive-strength = <2>; 3731 bias-disable; 3732 }; 3733 }; 3734 3735 qup_i2c14_default: qup-i2c14-default { 3736 mux { 3737 pins = "gpio40", "gpio41"; 3738 function = "qup14"; 3739 }; 3740 3741 config { 3742 pins = "gpio40", "gpio41"; 3743 drive-strength = <2>; 3744 bias-disable; 3745 }; 3746 }; 3747 3748 qup_i2c15_default: qup-i2c15-default { 3749 mux { 3750 pins = "gpio44", "gpio45"; 3751 function = "qup15"; 3752 }; 3753 3754 config { 3755 pins = "gpio44", "gpio45"; 3756 drive-strength = <2>; 3757 bias-disable; 3758 }; 3759 }; 3760 3761 qup_i2c16_default: qup-i2c16-default { 3762 mux { 3763 pins = "gpio48", "gpio49"; 3764 function = "qup16"; 3765 }; 3766 3767 config { 3768 pins = "gpio48", "gpio49"; 3769 drive-strength = <2>; 3770 bias-disable; 3771 }; 3772 }; 3773 3774 qup_i2c17_default: qup-i2c17-default { 3775 mux { 3776 pins = "gpio52", "gpio53"; 3777 function = "qup17"; 3778 }; 3779 3780 config { 3781 pins = "gpio52", "gpio53"; 3782 drive-strength = <2>; 3783 bias-disable; 3784 }; 3785 }; 3786 3787 qup_i2c18_default: qup-i2c18-default { 3788 mux { 3789 pins = "gpio56", "gpio57"; 3790 function = "qup18"; 3791 }; 3792 3793 config { 3794 pins = "gpio56", "gpio57"; 3795 drive-strength = <2>; 3796 bias-disable; 3797 }; 3798 }; 3799 3800 qup_i2c19_default: qup-i2c19-default { 3801 mux { 3802 pins = "gpio0", "gpio1"; 3803 function = "qup19"; 3804 }; 3805 3806 config { 3807 pins = "gpio0", "gpio1"; 3808 drive-strength = <2>; 3809 bias-disable; 3810 }; 3811 }; 3812 3813 qup_spi0_cs: qup-spi0-cs { 3814 pins = "gpio31"; 3815 function = "qup0"; 3816 }; 3817 3818 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3819 pins = "gpio31"; 3820 function = "gpio"; 3821 }; 3822 3823 qup_spi0_data_clk: qup-spi0-data-clk { 3824 pins = "gpio28", "gpio29", 3825 "gpio30"; 3826 function = "qup0"; 3827 }; 3828 3829 qup_spi1_cs: qup-spi1-cs { 3830 pins = "gpio7"; 3831 function = "qup1"; 3832 }; 3833 3834 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3835 pins = "gpio7"; 3836 function = "gpio"; 3837 }; 3838 3839 qup_spi1_data_clk: qup-spi1-data-clk { 3840 pins = "gpio4", "gpio5", 3841 "gpio6"; 3842 function = "qup1"; 3843 }; 3844 3845 qup_spi2_cs: qup-spi2-cs { 3846 pins = "gpio118"; 3847 function = "qup2"; 3848 }; 3849 3850 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3851 pins = "gpio118"; 3852 function = "gpio"; 3853 }; 3854 3855 qup_spi2_data_clk: qup-spi2-data-clk { 3856 pins = "gpio115", "gpio116", 3857 "gpio117"; 3858 function = "qup2"; 3859 }; 3860 3861 qup_spi3_cs: qup-spi3-cs { 3862 pins = "gpio122"; 3863 function = "qup3"; 3864 }; 3865 3866 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3867 pins = "gpio122"; 3868 function = "gpio"; 3869 }; 3870 3871 qup_spi3_data_clk: qup-spi3-data-clk { 3872 pins = "gpio119", "gpio120", 3873 "gpio121"; 3874 function = "qup3"; 3875 }; 3876 3877 qup_spi4_cs: qup-spi4-cs { 3878 pins = "gpio11"; 3879 function = "qup4"; 3880 }; 3881 3882 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3883 pins = "gpio11"; 3884 function = "gpio"; 3885 }; 3886 3887 qup_spi4_data_clk: qup-spi4-data-clk { 3888 pins = "gpio8", "gpio9", 3889 "gpio10"; 3890 function = "qup4"; 3891 }; 3892 3893 qup_spi5_cs: qup-spi5-cs { 3894 pins = "gpio15"; 3895 function = "qup5"; 3896 }; 3897 3898 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3899 pins = "gpio15"; 3900 function = "gpio"; 3901 }; 3902 3903 qup_spi5_data_clk: qup-spi5-data-clk { 3904 pins = "gpio12", "gpio13", 3905 "gpio14"; 3906 function = "qup5"; 3907 }; 3908 3909 qup_spi6_cs: qup-spi6-cs { 3910 pins = "gpio19"; 3911 function = "qup6"; 3912 }; 3913 3914 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3915 pins = "gpio19"; 3916 function = "gpio"; 3917 }; 3918 3919 qup_spi6_data_clk: qup-spi6-data-clk { 3920 pins = "gpio16", "gpio17", 3921 "gpio18"; 3922 function = "qup6"; 3923 }; 3924 3925 qup_spi7_cs: qup-spi7-cs { 3926 pins = "gpio23"; 3927 function = "qup7"; 3928 }; 3929 3930 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3931 pins = "gpio23"; 3932 function = "gpio"; 3933 }; 3934 3935 qup_spi7_data_clk: qup-spi7-data-clk { 3936 pins = "gpio20", "gpio21", 3937 "gpio22"; 3938 function = "qup7"; 3939 }; 3940 3941 qup_spi8_cs: qup-spi8-cs { 3942 pins = "gpio27"; 3943 function = "qup8"; 3944 }; 3945 3946 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3947 pins = "gpio27"; 3948 function = "gpio"; 3949 }; 3950 3951 qup_spi8_data_clk: qup-spi8-data-clk { 3952 pins = "gpio24", "gpio25", 3953 "gpio26"; 3954 function = "qup8"; 3955 }; 3956 3957 qup_spi9_cs: qup-spi9-cs { 3958 pins = "gpio128"; 3959 function = "qup9"; 3960 }; 3961 3962 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3963 pins = "gpio128"; 3964 function = "gpio"; 3965 }; 3966 3967 qup_spi9_data_clk: qup-spi9-data-clk { 3968 pins = "gpio125", "gpio126", 3969 "gpio127"; 3970 function = "qup9"; 3971 }; 3972 3973 qup_spi10_cs: qup-spi10-cs { 3974 pins = "gpio132"; 3975 function = "qup10"; 3976 }; 3977 3978 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3979 pins = "gpio132"; 3980 function = "gpio"; 3981 }; 3982 3983 qup_spi10_data_clk: qup-spi10-data-clk { 3984 pins = "gpio129", "gpio130", 3985 "gpio131"; 3986 function = "qup10"; 3987 }; 3988 3989 qup_spi11_cs: qup-spi11-cs { 3990 pins = "gpio63"; 3991 function = "qup11"; 3992 }; 3993 3994 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3995 pins = "gpio63"; 3996 function = "gpio"; 3997 }; 3998 3999 qup_spi11_data_clk: qup-spi11-data-clk { 4000 pins = "gpio60", "gpio61", 4001 "gpio62"; 4002 function = "qup11"; 4003 }; 4004 4005 qup_spi12_cs: qup-spi12-cs { 4006 pins = "gpio35"; 4007 function = "qup12"; 4008 }; 4009 4010 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 4011 pins = "gpio35"; 4012 function = "gpio"; 4013 }; 4014 4015 qup_spi12_data_clk: qup-spi12-data-clk { 4016 pins = "gpio32", "gpio33", 4017 "gpio34"; 4018 function = "qup12"; 4019 }; 4020 4021 qup_spi13_cs: qup-spi13-cs { 4022 pins = "gpio39"; 4023 function = "qup13"; 4024 }; 4025 4026 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 4027 pins = "gpio39"; 4028 function = "gpio"; 4029 }; 4030 4031 qup_spi13_data_clk: qup-spi13-data-clk { 4032 pins = "gpio36", "gpio37", 4033 "gpio38"; 4034 function = "qup13"; 4035 }; 4036 4037 qup_spi14_cs: qup-spi14-cs { 4038 pins = "gpio43"; 4039 function = "qup14"; 4040 }; 4041 4042 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 4043 pins = "gpio43"; 4044 function = "gpio"; 4045 }; 4046 4047 qup_spi14_data_clk: qup-spi14-data-clk { 4048 pins = "gpio40", "gpio41", 4049 "gpio42"; 4050 function = "qup14"; 4051 }; 4052 4053 qup_spi15_cs: qup-spi15-cs { 4054 pins = "gpio47"; 4055 function = "qup15"; 4056 }; 4057 4058 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 4059 pins = "gpio47"; 4060 function = "gpio"; 4061 }; 4062 4063 qup_spi15_data_clk: qup-spi15-data-clk { 4064 pins = "gpio44", "gpio45", 4065 "gpio46"; 4066 function = "qup15"; 4067 }; 4068 4069 qup_spi16_cs: qup-spi16-cs { 4070 pins = "gpio51"; 4071 function = "qup16"; 4072 }; 4073 4074 qup_spi16_cs_gpio: qup-spi16-cs-gpio { 4075 pins = "gpio51"; 4076 function = "gpio"; 4077 }; 4078 4079 qup_spi16_data_clk: qup-spi16-data-clk { 4080 pins = "gpio48", "gpio49", 4081 "gpio50"; 4082 function = "qup16"; 4083 }; 4084 4085 qup_spi17_cs: qup-spi17-cs { 4086 pins = "gpio55"; 4087 function = "qup17"; 4088 }; 4089 4090 qup_spi17_cs_gpio: qup-spi17-cs-gpio { 4091 pins = "gpio55"; 4092 function = "gpio"; 4093 }; 4094 4095 qup_spi17_data_clk: qup-spi17-data-clk { 4096 pins = "gpio52", "gpio53", 4097 "gpio54"; 4098 function = "qup17"; 4099 }; 4100 4101 qup_spi18_cs: qup-spi18-cs { 4102 pins = "gpio59"; 4103 function = "qup18"; 4104 }; 4105 4106 qup_spi18_cs_gpio: qup-spi18-cs-gpio { 4107 pins = "gpio59"; 4108 function = "gpio"; 4109 }; 4110 4111 qup_spi18_data_clk: qup-spi18-data-clk { 4112 pins = "gpio56", "gpio57", 4113 "gpio58"; 4114 function = "qup18"; 4115 }; 4116 4117 qup_spi19_cs: qup-spi19-cs { 4118 pins = "gpio3"; 4119 function = "qup19"; 4120 }; 4121 4122 qup_spi19_cs_gpio: qup-spi19-cs-gpio { 4123 pins = "gpio3"; 4124 function = "gpio"; 4125 }; 4126 4127 qup_spi19_data_clk: qup-spi19-data-clk { 4128 pins = "gpio0", "gpio1", 4129 "gpio2"; 4130 function = "qup19"; 4131 }; 4132 4133 qup_uart2_default: qup-uart2-default { 4134 mux { 4135 pins = "gpio117", "gpio118"; 4136 function = "qup2"; 4137 }; 4138 }; 4139 4140 qup_uart6_default: qup-uart6-default { 4141 mux { 4142 pins = "gpio16", "gpio17", 4143 "gpio18", "gpio19"; 4144 function = "qup6"; 4145 }; 4146 }; 4147 4148 qup_uart12_default: qup-uart12-default { 4149 mux { 4150 pins = "gpio34", "gpio35"; 4151 function = "qup12"; 4152 }; 4153 }; 4154 4155 qup_uart17_default: qup-uart17-default { 4156 mux { 4157 pins = "gpio52", "gpio53", 4158 "gpio54", "gpio55"; 4159 function = "qup17"; 4160 }; 4161 }; 4162 4163 qup_uart18_default: qup-uart18-default { 4164 mux { 4165 pins = "gpio58", "gpio59"; 4166 function = "qup18"; 4167 }; 4168 }; 4169 4170 tert_mi2s_active: tert-mi2s-active { 4171 sck { 4172 pins = "gpio133"; 4173 function = "mi2s2_sck"; 4174 drive-strength = <8>; 4175 bias-disable; 4176 }; 4177 4178 data0 { 4179 pins = "gpio134"; 4180 function = "mi2s2_data0"; 4181 drive-strength = <8>; 4182 bias-disable; 4183 output-high; 4184 }; 4185 4186 ws { 4187 pins = "gpio135"; 4188 function = "mi2s2_ws"; 4189 drive-strength = <8>; 4190 output-high; 4191 }; 4192 }; 4193 4194 sdc2_sleep_state: sdc2-sleep { 4195 clk { 4196 pins = "sdc2_clk"; 4197 drive-strength = <2>; 4198 bias-disable; 4199 }; 4200 4201 cmd { 4202 pins = "sdc2_cmd"; 4203 drive-strength = <2>; 4204 bias-pull-up; 4205 }; 4206 4207 data { 4208 pins = "sdc2_data"; 4209 drive-strength = <2>; 4210 bias-pull-up; 4211 }; 4212 }; 4213 4214 pcie0_default_state: pcie0-default { 4215 perst { 4216 pins = "gpio79"; 4217 function = "gpio"; 4218 drive-strength = <2>; 4219 bias-pull-down; 4220 }; 4221 4222 clkreq { 4223 pins = "gpio80"; 4224 function = "pci_e0"; 4225 drive-strength = <2>; 4226 bias-pull-up; 4227 }; 4228 4229 wake { 4230 pins = "gpio81"; 4231 function = "gpio"; 4232 drive-strength = <2>; 4233 bias-pull-up; 4234 }; 4235 }; 4236 4237 pcie1_default_state: pcie1-default { 4238 perst { 4239 pins = "gpio82"; 4240 function = "gpio"; 4241 drive-strength = <2>; 4242 bias-pull-down; 4243 }; 4244 4245 clkreq { 4246 pins = "gpio83"; 4247 function = "pci_e1"; 4248 drive-strength = <2>; 4249 bias-pull-up; 4250 }; 4251 4252 wake { 4253 pins = "gpio84"; 4254 function = "gpio"; 4255 drive-strength = <2>; 4256 bias-pull-up; 4257 }; 4258 }; 4259 4260 pcie2_default_state: pcie2-default { 4261 perst { 4262 pins = "gpio85"; 4263 function = "gpio"; 4264 drive-strength = <2>; 4265 bias-pull-down; 4266 }; 4267 4268 clkreq { 4269 pins = "gpio86"; 4270 function = "pci_e2"; 4271 drive-strength = <2>; 4272 bias-pull-up; 4273 }; 4274 4275 wake { 4276 pins = "gpio87"; 4277 function = "gpio"; 4278 drive-strength = <2>; 4279 bias-pull-up; 4280 }; 4281 }; 4282 }; 4283 4284 apps_smmu: iommu@15000000 { 4285 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 4286 reg = <0 0x15000000 0 0x100000>; 4287 #iommu-cells = <2>; 4288 #global-interrupts = <2>; 4289 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 4290 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4291 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4292 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4293 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4294 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4295 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4296 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4297 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4298 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4299 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4300 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4301 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4302 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4303 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4304 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4305 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4306 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4307 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4308 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4309 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4310 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4311 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4312 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4313 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4314 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4315 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4316 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4317 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4318 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4319 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4320 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4321 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4322 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4323 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4324 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4325 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4326 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4327 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4328 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4329 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4330 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4331 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4332 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4333 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4334 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4335 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4336 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4337 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4338 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4339 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4340 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4341 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4342 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4343 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4344 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4345 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4346 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4347 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4348 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4349 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4350 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4351 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4352 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4353 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4354 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4355 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4356 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4357 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4358 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4359 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4360 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4361 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4362 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4363 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4364 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4365 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4366 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4367 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4368 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4369 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4370 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4371 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4372 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4373 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4374 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4375 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4376 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4377 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4378 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4379 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4380 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4381 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4382 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4383 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4384 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4385 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 4386 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 4387 }; 4388 4389 adsp: remoteproc@17300000 { 4390 compatible = "qcom,sm8250-adsp-pas"; 4391 reg = <0 0x17300000 0 0x100>; 4392 4393 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 4394 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4395 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4396 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4397 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4398 interrupt-names = "wdog", "fatal", "ready", 4399 "handover", "stop-ack"; 4400 4401 clocks = <&rpmhcc RPMH_CXO_CLK>; 4402 clock-names = "xo"; 4403 4404 power-domains = <&rpmhpd SM8250_LCX>, 4405 <&rpmhpd SM8250_LMX>; 4406 power-domain-names = "lcx", "lmx"; 4407 4408 memory-region = <&adsp_mem>; 4409 4410 qcom,qmp = <&aoss_qmp>; 4411 4412 qcom,smem-states = <&smp2p_adsp_out 0>; 4413 qcom,smem-state-names = "stop"; 4414 4415 status = "disabled"; 4416 4417 glink-edge { 4418 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4419 IPCC_MPROC_SIGNAL_GLINK_QMP 4420 IRQ_TYPE_EDGE_RISING>; 4421 mboxes = <&ipcc IPCC_CLIENT_LPASS 4422 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4423 4424 label = "lpass"; 4425 qcom,remote-pid = <2>; 4426 4427 apr { 4428 compatible = "qcom,apr-v2"; 4429 qcom,glink-channels = "apr_audio_svc"; 4430 qcom,domain = <APR_DOMAIN_ADSP>; 4431 #address-cells = <1>; 4432 #size-cells = <0>; 4433 4434 apr-service@3 { 4435 reg = <APR_SVC_ADSP_CORE>; 4436 compatible = "qcom,q6core"; 4437 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4438 }; 4439 4440 q6afe: apr-service@4 { 4441 compatible = "qcom,q6afe"; 4442 reg = <APR_SVC_AFE>; 4443 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4444 q6afedai: dais { 4445 compatible = "qcom,q6afe-dais"; 4446 #address-cells = <1>; 4447 #size-cells = <0>; 4448 #sound-dai-cells = <1>; 4449 }; 4450 4451 q6afecc: cc { 4452 compatible = "qcom,q6afe-clocks"; 4453 #clock-cells = <2>; 4454 }; 4455 }; 4456 4457 q6asm: apr-service@7 { 4458 compatible = "qcom,q6asm"; 4459 reg = <APR_SVC_ASM>; 4460 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4461 q6asmdai: dais { 4462 compatible = "qcom,q6asm-dais"; 4463 #address-cells = <1>; 4464 #size-cells = <0>; 4465 #sound-dai-cells = <1>; 4466 iommus = <&apps_smmu 0x1801 0x0>; 4467 }; 4468 }; 4469 4470 q6adm: apr-service@8 { 4471 compatible = "qcom,q6adm"; 4472 reg = <APR_SVC_ADM>; 4473 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4474 q6routing: routing { 4475 compatible = "qcom,q6adm-routing"; 4476 #sound-dai-cells = <0>; 4477 }; 4478 }; 4479 }; 4480 4481 fastrpc { 4482 compatible = "qcom,fastrpc"; 4483 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4484 label = "adsp"; 4485 qcom,non-secure-domain; 4486 #address-cells = <1>; 4487 #size-cells = <0>; 4488 4489 compute-cb@3 { 4490 compatible = "qcom,fastrpc-compute-cb"; 4491 reg = <3>; 4492 iommus = <&apps_smmu 0x1803 0x0>; 4493 }; 4494 4495 compute-cb@4 { 4496 compatible = "qcom,fastrpc-compute-cb"; 4497 reg = <4>; 4498 iommus = <&apps_smmu 0x1804 0x0>; 4499 }; 4500 4501 compute-cb@5 { 4502 compatible = "qcom,fastrpc-compute-cb"; 4503 reg = <5>; 4504 iommus = <&apps_smmu 0x1805 0x0>; 4505 }; 4506 }; 4507 }; 4508 }; 4509 4510 intc: interrupt-controller@17a00000 { 4511 compatible = "arm,gic-v3"; 4512 #interrupt-cells = <3>; 4513 interrupt-controller; 4514 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4515 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4516 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4517 }; 4518 4519 watchdog@17c10000 { 4520 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 4521 reg = <0 0x17c10000 0 0x1000>; 4522 clocks = <&sleep_clk>; 4523 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4524 }; 4525 4526 timer@17c20000 { 4527 #address-cells = <2>; 4528 #size-cells = <2>; 4529 ranges; 4530 compatible = "arm,armv7-timer-mem"; 4531 reg = <0x0 0x17c20000 0x0 0x1000>; 4532 clock-frequency = <19200000>; 4533 4534 frame@17c21000 { 4535 frame-number = <0>; 4536 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4537 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4538 reg = <0x0 0x17c21000 0x0 0x1000>, 4539 <0x0 0x17c22000 0x0 0x1000>; 4540 }; 4541 4542 frame@17c23000 { 4543 frame-number = <1>; 4544 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4545 reg = <0x0 0x17c23000 0x0 0x1000>; 4546 status = "disabled"; 4547 }; 4548 4549 frame@17c25000 { 4550 frame-number = <2>; 4551 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4552 reg = <0x0 0x17c25000 0x0 0x1000>; 4553 status = "disabled"; 4554 }; 4555 4556 frame@17c27000 { 4557 frame-number = <3>; 4558 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4559 reg = <0x0 0x17c27000 0x0 0x1000>; 4560 status = "disabled"; 4561 }; 4562 4563 frame@17c29000 { 4564 frame-number = <4>; 4565 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4566 reg = <0x0 0x17c29000 0x0 0x1000>; 4567 status = "disabled"; 4568 }; 4569 4570 frame@17c2b000 { 4571 frame-number = <5>; 4572 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4573 reg = <0x0 0x17c2b000 0x0 0x1000>; 4574 status = "disabled"; 4575 }; 4576 4577 frame@17c2d000 { 4578 frame-number = <6>; 4579 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4580 reg = <0x0 0x17c2d000 0x0 0x1000>; 4581 status = "disabled"; 4582 }; 4583 }; 4584 4585 apps_rsc: rsc@18200000 { 4586 label = "apps_rsc"; 4587 compatible = "qcom,rpmh-rsc"; 4588 reg = <0x0 0x18200000 0x0 0x10000>, 4589 <0x0 0x18210000 0x0 0x10000>, 4590 <0x0 0x18220000 0x0 0x10000>; 4591 reg-names = "drv-0", "drv-1", "drv-2"; 4592 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4593 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4594 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4595 qcom,tcs-offset = <0xd00>; 4596 qcom,drv-id = <2>; 4597 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 4598 <WAKE_TCS 3>, <CONTROL_TCS 1>; 4599 4600 rpmhcc: clock-controller { 4601 compatible = "qcom,sm8250-rpmh-clk"; 4602 #clock-cells = <1>; 4603 clock-names = "xo"; 4604 clocks = <&xo_board>; 4605 }; 4606 4607 rpmhpd: power-controller { 4608 compatible = "qcom,sm8250-rpmhpd"; 4609 #power-domain-cells = <1>; 4610 operating-points-v2 = <&rpmhpd_opp_table>; 4611 4612 rpmhpd_opp_table: opp-table { 4613 compatible = "operating-points-v2"; 4614 4615 rpmhpd_opp_ret: opp1 { 4616 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4617 }; 4618 4619 rpmhpd_opp_min_svs: opp2 { 4620 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4621 }; 4622 4623 rpmhpd_opp_low_svs: opp3 { 4624 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4625 }; 4626 4627 rpmhpd_opp_svs: opp4 { 4628 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4629 }; 4630 4631 rpmhpd_opp_svs_l1: opp5 { 4632 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4633 }; 4634 4635 rpmhpd_opp_nom: opp6 { 4636 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4637 }; 4638 4639 rpmhpd_opp_nom_l1: opp7 { 4640 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4641 }; 4642 4643 rpmhpd_opp_nom_l2: opp8 { 4644 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4645 }; 4646 4647 rpmhpd_opp_turbo: opp9 { 4648 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4649 }; 4650 4651 rpmhpd_opp_turbo_l1: opp10 { 4652 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4653 }; 4654 }; 4655 }; 4656 4657 apps_bcm_voter: bcm_voter { 4658 compatible = "qcom,bcm-voter"; 4659 }; 4660 }; 4661 4662 epss_l3: interconnect@18590000 { 4663 compatible = "qcom,sm8250-epss-l3"; 4664 reg = <0 0x18590000 0 0x1000>; 4665 4666 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4667 clock-names = "xo", "alternate"; 4668 4669 #interconnect-cells = <1>; 4670 }; 4671 4672 cpufreq_hw: cpufreq@18591000 { 4673 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 4674 reg = <0 0x18591000 0 0x1000>, 4675 <0 0x18592000 0 0x1000>, 4676 <0 0x18593000 0 0x1000>; 4677 reg-names = "freq-domain0", "freq-domain1", 4678 "freq-domain2"; 4679 4680 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4681 clock-names = "xo", "alternate"; 4682 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4683 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4684 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4685 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 4686 #freq-domain-cells = <1>; 4687 }; 4688 }; 4689 4690 timer { 4691 compatible = "arm,armv8-timer"; 4692 interrupts = <GIC_PPI 13 4693 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4694 <GIC_PPI 14 4695 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4696 <GIC_PPI 11 4697 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4698 <GIC_PPI 10 4699 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4700 }; 4701 4702 thermal-zones { 4703 cpu0-thermal { 4704 polling-delay-passive = <250>; 4705 polling-delay = <1000>; 4706 4707 thermal-sensors = <&tsens0 1>; 4708 4709 trips { 4710 cpu0_alert0: trip-point0 { 4711 temperature = <90000>; 4712 hysteresis = <2000>; 4713 type = "passive"; 4714 }; 4715 4716 cpu0_alert1: trip-point1 { 4717 temperature = <95000>; 4718 hysteresis = <2000>; 4719 type = "passive"; 4720 }; 4721 4722 cpu0_crit: cpu_crit { 4723 temperature = <110000>; 4724 hysteresis = <1000>; 4725 type = "critical"; 4726 }; 4727 }; 4728 4729 cooling-maps { 4730 map0 { 4731 trip = <&cpu0_alert0>; 4732 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4733 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4734 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4735 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4736 }; 4737 map1 { 4738 trip = <&cpu0_alert1>; 4739 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4740 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4741 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4742 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4743 }; 4744 }; 4745 }; 4746 4747 cpu1-thermal { 4748 polling-delay-passive = <250>; 4749 polling-delay = <1000>; 4750 4751 thermal-sensors = <&tsens0 2>; 4752 4753 trips { 4754 cpu1_alert0: trip-point0 { 4755 temperature = <90000>; 4756 hysteresis = <2000>; 4757 type = "passive"; 4758 }; 4759 4760 cpu1_alert1: trip-point1 { 4761 temperature = <95000>; 4762 hysteresis = <2000>; 4763 type = "passive"; 4764 }; 4765 4766 cpu1_crit: cpu_crit { 4767 temperature = <110000>; 4768 hysteresis = <1000>; 4769 type = "critical"; 4770 }; 4771 }; 4772 4773 cooling-maps { 4774 map0 { 4775 trip = <&cpu1_alert0>; 4776 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4777 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4778 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4779 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4780 }; 4781 map1 { 4782 trip = <&cpu1_alert1>; 4783 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4784 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4785 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4786 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4787 }; 4788 }; 4789 }; 4790 4791 cpu2-thermal { 4792 polling-delay-passive = <250>; 4793 polling-delay = <1000>; 4794 4795 thermal-sensors = <&tsens0 3>; 4796 4797 trips { 4798 cpu2_alert0: trip-point0 { 4799 temperature = <90000>; 4800 hysteresis = <2000>; 4801 type = "passive"; 4802 }; 4803 4804 cpu2_alert1: trip-point1 { 4805 temperature = <95000>; 4806 hysteresis = <2000>; 4807 type = "passive"; 4808 }; 4809 4810 cpu2_crit: cpu_crit { 4811 temperature = <110000>; 4812 hysteresis = <1000>; 4813 type = "critical"; 4814 }; 4815 }; 4816 4817 cooling-maps { 4818 map0 { 4819 trip = <&cpu2_alert0>; 4820 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4821 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4822 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4823 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4824 }; 4825 map1 { 4826 trip = <&cpu2_alert1>; 4827 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4828 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4829 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4830 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4831 }; 4832 }; 4833 }; 4834 4835 cpu3-thermal { 4836 polling-delay-passive = <250>; 4837 polling-delay = <1000>; 4838 4839 thermal-sensors = <&tsens0 4>; 4840 4841 trips { 4842 cpu3_alert0: trip-point0 { 4843 temperature = <90000>; 4844 hysteresis = <2000>; 4845 type = "passive"; 4846 }; 4847 4848 cpu3_alert1: trip-point1 { 4849 temperature = <95000>; 4850 hysteresis = <2000>; 4851 type = "passive"; 4852 }; 4853 4854 cpu3_crit: cpu_crit { 4855 temperature = <110000>; 4856 hysteresis = <1000>; 4857 type = "critical"; 4858 }; 4859 }; 4860 4861 cooling-maps { 4862 map0 { 4863 trip = <&cpu3_alert0>; 4864 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4865 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4866 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4867 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4868 }; 4869 map1 { 4870 trip = <&cpu3_alert1>; 4871 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4872 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4873 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4874 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4875 }; 4876 }; 4877 }; 4878 4879 cpu4-top-thermal { 4880 polling-delay-passive = <250>; 4881 polling-delay = <1000>; 4882 4883 thermal-sensors = <&tsens0 7>; 4884 4885 trips { 4886 cpu4_top_alert0: trip-point0 { 4887 temperature = <90000>; 4888 hysteresis = <2000>; 4889 type = "passive"; 4890 }; 4891 4892 cpu4_top_alert1: trip-point1 { 4893 temperature = <95000>; 4894 hysteresis = <2000>; 4895 type = "passive"; 4896 }; 4897 4898 cpu4_top_crit: cpu_crit { 4899 temperature = <110000>; 4900 hysteresis = <1000>; 4901 type = "critical"; 4902 }; 4903 }; 4904 4905 cooling-maps { 4906 map0 { 4907 trip = <&cpu4_top_alert0>; 4908 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4909 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4910 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4911 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4912 }; 4913 map1 { 4914 trip = <&cpu4_top_alert1>; 4915 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4916 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4917 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4918 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4919 }; 4920 }; 4921 }; 4922 4923 cpu5-top-thermal { 4924 polling-delay-passive = <250>; 4925 polling-delay = <1000>; 4926 4927 thermal-sensors = <&tsens0 8>; 4928 4929 trips { 4930 cpu5_top_alert0: trip-point0 { 4931 temperature = <90000>; 4932 hysteresis = <2000>; 4933 type = "passive"; 4934 }; 4935 4936 cpu5_top_alert1: trip-point1 { 4937 temperature = <95000>; 4938 hysteresis = <2000>; 4939 type = "passive"; 4940 }; 4941 4942 cpu5_top_crit: cpu_crit { 4943 temperature = <110000>; 4944 hysteresis = <1000>; 4945 type = "critical"; 4946 }; 4947 }; 4948 4949 cooling-maps { 4950 map0 { 4951 trip = <&cpu5_top_alert0>; 4952 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4953 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4954 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4955 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4956 }; 4957 map1 { 4958 trip = <&cpu5_top_alert1>; 4959 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4960 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4961 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4962 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4963 }; 4964 }; 4965 }; 4966 4967 cpu6-top-thermal { 4968 polling-delay-passive = <250>; 4969 polling-delay = <1000>; 4970 4971 thermal-sensors = <&tsens0 9>; 4972 4973 trips { 4974 cpu6_top_alert0: trip-point0 { 4975 temperature = <90000>; 4976 hysteresis = <2000>; 4977 type = "passive"; 4978 }; 4979 4980 cpu6_top_alert1: trip-point1 { 4981 temperature = <95000>; 4982 hysteresis = <2000>; 4983 type = "passive"; 4984 }; 4985 4986 cpu6_top_crit: cpu_crit { 4987 temperature = <110000>; 4988 hysteresis = <1000>; 4989 type = "critical"; 4990 }; 4991 }; 4992 4993 cooling-maps { 4994 map0 { 4995 trip = <&cpu6_top_alert0>; 4996 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4997 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4998 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4999 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5000 }; 5001 map1 { 5002 trip = <&cpu6_top_alert1>; 5003 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5004 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5005 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5006 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5007 }; 5008 }; 5009 }; 5010 5011 cpu7-top-thermal { 5012 polling-delay-passive = <250>; 5013 polling-delay = <1000>; 5014 5015 thermal-sensors = <&tsens0 10>; 5016 5017 trips { 5018 cpu7_top_alert0: trip-point0 { 5019 temperature = <90000>; 5020 hysteresis = <2000>; 5021 type = "passive"; 5022 }; 5023 5024 cpu7_top_alert1: trip-point1 { 5025 temperature = <95000>; 5026 hysteresis = <2000>; 5027 type = "passive"; 5028 }; 5029 5030 cpu7_top_crit: cpu_crit { 5031 temperature = <110000>; 5032 hysteresis = <1000>; 5033 type = "critical"; 5034 }; 5035 }; 5036 5037 cooling-maps { 5038 map0 { 5039 trip = <&cpu7_top_alert0>; 5040 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5041 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5042 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5043 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5044 }; 5045 map1 { 5046 trip = <&cpu7_top_alert1>; 5047 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5048 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5049 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5050 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5051 }; 5052 }; 5053 }; 5054 5055 cpu4-bottom-thermal { 5056 polling-delay-passive = <250>; 5057 polling-delay = <1000>; 5058 5059 thermal-sensors = <&tsens0 11>; 5060 5061 trips { 5062 cpu4_bottom_alert0: trip-point0 { 5063 temperature = <90000>; 5064 hysteresis = <2000>; 5065 type = "passive"; 5066 }; 5067 5068 cpu4_bottom_alert1: trip-point1 { 5069 temperature = <95000>; 5070 hysteresis = <2000>; 5071 type = "passive"; 5072 }; 5073 5074 cpu4_bottom_crit: cpu_crit { 5075 temperature = <110000>; 5076 hysteresis = <1000>; 5077 type = "critical"; 5078 }; 5079 }; 5080 5081 cooling-maps { 5082 map0 { 5083 trip = <&cpu4_bottom_alert0>; 5084 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5085 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5086 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5087 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5088 }; 5089 map1 { 5090 trip = <&cpu4_bottom_alert1>; 5091 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5092 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5093 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5094 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5095 }; 5096 }; 5097 }; 5098 5099 cpu5-bottom-thermal { 5100 polling-delay-passive = <250>; 5101 polling-delay = <1000>; 5102 5103 thermal-sensors = <&tsens0 12>; 5104 5105 trips { 5106 cpu5_bottom_alert0: trip-point0 { 5107 temperature = <90000>; 5108 hysteresis = <2000>; 5109 type = "passive"; 5110 }; 5111 5112 cpu5_bottom_alert1: trip-point1 { 5113 temperature = <95000>; 5114 hysteresis = <2000>; 5115 type = "passive"; 5116 }; 5117 5118 cpu5_bottom_crit: cpu_crit { 5119 temperature = <110000>; 5120 hysteresis = <1000>; 5121 type = "critical"; 5122 }; 5123 }; 5124 5125 cooling-maps { 5126 map0 { 5127 trip = <&cpu5_bottom_alert0>; 5128 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5129 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5130 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5131 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5132 }; 5133 map1 { 5134 trip = <&cpu5_bottom_alert1>; 5135 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5136 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5137 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5138 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5139 }; 5140 }; 5141 }; 5142 5143 cpu6-bottom-thermal { 5144 polling-delay-passive = <250>; 5145 polling-delay = <1000>; 5146 5147 thermal-sensors = <&tsens0 13>; 5148 5149 trips { 5150 cpu6_bottom_alert0: trip-point0 { 5151 temperature = <90000>; 5152 hysteresis = <2000>; 5153 type = "passive"; 5154 }; 5155 5156 cpu6_bottom_alert1: trip-point1 { 5157 temperature = <95000>; 5158 hysteresis = <2000>; 5159 type = "passive"; 5160 }; 5161 5162 cpu6_bottom_crit: cpu_crit { 5163 temperature = <110000>; 5164 hysteresis = <1000>; 5165 type = "critical"; 5166 }; 5167 }; 5168 5169 cooling-maps { 5170 map0 { 5171 trip = <&cpu6_bottom_alert0>; 5172 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5173 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5174 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5175 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5176 }; 5177 map1 { 5178 trip = <&cpu6_bottom_alert1>; 5179 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5180 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5181 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5182 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5183 }; 5184 }; 5185 }; 5186 5187 cpu7-bottom-thermal { 5188 polling-delay-passive = <250>; 5189 polling-delay = <1000>; 5190 5191 thermal-sensors = <&tsens0 14>; 5192 5193 trips { 5194 cpu7_bottom_alert0: trip-point0 { 5195 temperature = <90000>; 5196 hysteresis = <2000>; 5197 type = "passive"; 5198 }; 5199 5200 cpu7_bottom_alert1: trip-point1 { 5201 temperature = <95000>; 5202 hysteresis = <2000>; 5203 type = "passive"; 5204 }; 5205 5206 cpu7_bottom_crit: cpu_crit { 5207 temperature = <110000>; 5208 hysteresis = <1000>; 5209 type = "critical"; 5210 }; 5211 }; 5212 5213 cooling-maps { 5214 map0 { 5215 trip = <&cpu7_bottom_alert0>; 5216 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5217 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5218 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5219 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5220 }; 5221 map1 { 5222 trip = <&cpu7_bottom_alert1>; 5223 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5224 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5225 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5226 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5227 }; 5228 }; 5229 }; 5230 5231 aoss0-thermal { 5232 polling-delay-passive = <250>; 5233 polling-delay = <1000>; 5234 5235 thermal-sensors = <&tsens0 0>; 5236 5237 trips { 5238 aoss0_alert0: trip-point0 { 5239 temperature = <90000>; 5240 hysteresis = <2000>; 5241 type = "hot"; 5242 }; 5243 }; 5244 }; 5245 5246 cluster0-thermal { 5247 polling-delay-passive = <250>; 5248 polling-delay = <1000>; 5249 5250 thermal-sensors = <&tsens0 5>; 5251 5252 trips { 5253 cluster0_alert0: trip-point0 { 5254 temperature = <90000>; 5255 hysteresis = <2000>; 5256 type = "hot"; 5257 }; 5258 cluster0_crit: cluster0_crit { 5259 temperature = <110000>; 5260 hysteresis = <2000>; 5261 type = "critical"; 5262 }; 5263 }; 5264 }; 5265 5266 cluster1-thermal { 5267 polling-delay-passive = <250>; 5268 polling-delay = <1000>; 5269 5270 thermal-sensors = <&tsens0 6>; 5271 5272 trips { 5273 cluster1_alert0: trip-point0 { 5274 temperature = <90000>; 5275 hysteresis = <2000>; 5276 type = "hot"; 5277 }; 5278 cluster1_crit: cluster1_crit { 5279 temperature = <110000>; 5280 hysteresis = <2000>; 5281 type = "critical"; 5282 }; 5283 }; 5284 }; 5285 5286 gpu-top-thermal { 5287 polling-delay-passive = <250>; 5288 polling-delay = <1000>; 5289 5290 thermal-sensors = <&tsens0 15>; 5291 5292 trips { 5293 gpu1_alert0: trip-point0 { 5294 temperature = <90000>; 5295 hysteresis = <2000>; 5296 type = "hot"; 5297 }; 5298 }; 5299 }; 5300 5301 aoss1-thermal { 5302 polling-delay-passive = <250>; 5303 polling-delay = <1000>; 5304 5305 thermal-sensors = <&tsens1 0>; 5306 5307 trips { 5308 aoss1_alert0: trip-point0 { 5309 temperature = <90000>; 5310 hysteresis = <2000>; 5311 type = "hot"; 5312 }; 5313 }; 5314 }; 5315 5316 wlan-thermal { 5317 polling-delay-passive = <250>; 5318 polling-delay = <1000>; 5319 5320 thermal-sensors = <&tsens1 1>; 5321 5322 trips { 5323 wlan_alert0: trip-point0 { 5324 temperature = <90000>; 5325 hysteresis = <2000>; 5326 type = "hot"; 5327 }; 5328 }; 5329 }; 5330 5331 video-thermal { 5332 polling-delay-passive = <250>; 5333 polling-delay = <1000>; 5334 5335 thermal-sensors = <&tsens1 2>; 5336 5337 trips { 5338 video_alert0: trip-point0 { 5339 temperature = <90000>; 5340 hysteresis = <2000>; 5341 type = "hot"; 5342 }; 5343 }; 5344 }; 5345 5346 mem-thermal { 5347 polling-delay-passive = <250>; 5348 polling-delay = <1000>; 5349 5350 thermal-sensors = <&tsens1 3>; 5351 5352 trips { 5353 mem_alert0: trip-point0 { 5354 temperature = <90000>; 5355 hysteresis = <2000>; 5356 type = "hot"; 5357 }; 5358 }; 5359 }; 5360 5361 q6-hvx-thermal { 5362 polling-delay-passive = <250>; 5363 polling-delay = <1000>; 5364 5365 thermal-sensors = <&tsens1 4>; 5366 5367 trips { 5368 q6_hvx_alert0: trip-point0 { 5369 temperature = <90000>; 5370 hysteresis = <2000>; 5371 type = "hot"; 5372 }; 5373 }; 5374 }; 5375 5376 camera-thermal { 5377 polling-delay-passive = <250>; 5378 polling-delay = <1000>; 5379 5380 thermal-sensors = <&tsens1 5>; 5381 5382 trips { 5383 camera_alert0: trip-point0 { 5384 temperature = <90000>; 5385 hysteresis = <2000>; 5386 type = "hot"; 5387 }; 5388 }; 5389 }; 5390 5391 compute-thermal { 5392 polling-delay-passive = <250>; 5393 polling-delay = <1000>; 5394 5395 thermal-sensors = <&tsens1 6>; 5396 5397 trips { 5398 compute_alert0: trip-point0 { 5399 temperature = <90000>; 5400 hysteresis = <2000>; 5401 type = "hot"; 5402 }; 5403 }; 5404 }; 5405 5406 npu-thermal { 5407 polling-delay-passive = <250>; 5408 polling-delay = <1000>; 5409 5410 thermal-sensors = <&tsens1 7>; 5411 5412 trips { 5413 npu_alert0: trip-point0 { 5414 temperature = <90000>; 5415 hysteresis = <2000>; 5416 type = "hot"; 5417 }; 5418 }; 5419 }; 5420 5421 gpu-bottom-thermal { 5422 polling-delay-passive = <250>; 5423 polling-delay = <1000>; 5424 5425 thermal-sensors = <&tsens1 8>; 5426 5427 trips { 5428 gpu2_alert0: trip-point0 { 5429 temperature = <90000>; 5430 hysteresis = <2000>; 5431 type = "hot"; 5432 }; 5433 }; 5434 }; 5435 }; 5436}; 5437