1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h> 12#include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sm8250.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,apr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/sound/qcom,q6afe.h> 22#include <dt-bindings/thermal/thermal.h> 23#include <dt-bindings/clock/qcom,camcc-sm8250.h> 24#include <dt-bindings/clock/qcom,videocc-sm8250.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 aliases { 33 i2c0 = &i2c0; 34 i2c1 = &i2c1; 35 i2c2 = &i2c2; 36 i2c3 = &i2c3; 37 i2c4 = &i2c4; 38 i2c5 = &i2c5; 39 i2c6 = &i2c6; 40 i2c7 = &i2c7; 41 i2c8 = &i2c8; 42 i2c9 = &i2c9; 43 i2c10 = &i2c10; 44 i2c11 = &i2c11; 45 i2c12 = &i2c12; 46 i2c13 = &i2c13; 47 i2c14 = &i2c14; 48 i2c15 = &i2c15; 49 i2c16 = &i2c16; 50 i2c17 = &i2c17; 51 i2c18 = &i2c18; 52 i2c19 = &i2c19; 53 spi0 = &spi0; 54 spi1 = &spi1; 55 spi2 = &spi2; 56 spi3 = &spi3; 57 spi4 = &spi4; 58 spi5 = &spi5; 59 spi6 = &spi6; 60 spi7 = &spi7; 61 spi8 = &spi8; 62 spi9 = &spi9; 63 spi10 = &spi10; 64 spi11 = &spi11; 65 spi12 = &spi12; 66 spi13 = &spi13; 67 spi14 = &spi14; 68 spi15 = &spi15; 69 spi16 = &spi16; 70 spi17 = &spi17; 71 spi18 = &spi18; 72 spi19 = &spi19; 73 }; 74 75 chosen { }; 76 77 clocks { 78 xo_board: xo-board { 79 compatible = "fixed-clock"; 80 #clock-cells = <0>; 81 clock-frequency = <38400000>; 82 clock-output-names = "xo_board"; 83 }; 84 85 sleep_clk: sleep-clk { 86 compatible = "fixed-clock"; 87 clock-frequency = <32768>; 88 #clock-cells = <0>; 89 }; 90 }; 91 92 cpus { 93 #address-cells = <2>; 94 #size-cells = <0>; 95 96 CPU0: cpu@0 { 97 device_type = "cpu"; 98 compatible = "qcom,kryo485"; 99 reg = <0x0 0x0>; 100 clocks = <&cpufreq_hw 0>; 101 enable-method = "psci"; 102 capacity-dmips-mhz = <448>; 103 dynamic-power-coefficient = <205>; 104 next-level-cache = <&L2_0>; 105 power-domains = <&CPU_PD0>; 106 power-domain-names = "psci"; 107 qcom,freq-domain = <&cpufreq_hw 0>; 108 operating-points-v2 = <&cpu0_opp_table>; 109 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 110 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 111 #cooling-cells = <2>; 112 L2_0: l2-cache { 113 compatible = "cache"; 114 cache-level = <2>; 115 cache-size = <0x20000>; 116 cache-unified; 117 next-level-cache = <&L3_0>; 118 L3_0: l3-cache { 119 compatible = "cache"; 120 cache-level = <3>; 121 cache-size = <0x400000>; 122 cache-unified; 123 }; 124 }; 125 }; 126 127 CPU1: cpu@100 { 128 device_type = "cpu"; 129 compatible = "qcom,kryo485"; 130 reg = <0x0 0x100>; 131 clocks = <&cpufreq_hw 0>; 132 enable-method = "psci"; 133 capacity-dmips-mhz = <448>; 134 dynamic-power-coefficient = <205>; 135 next-level-cache = <&L2_100>; 136 power-domains = <&CPU_PD1>; 137 power-domain-names = "psci"; 138 qcom,freq-domain = <&cpufreq_hw 0>; 139 operating-points-v2 = <&cpu0_opp_table>; 140 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 141 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 142 #cooling-cells = <2>; 143 L2_100: l2-cache { 144 compatible = "cache"; 145 cache-level = <2>; 146 cache-size = <0x20000>; 147 cache-unified; 148 next-level-cache = <&L3_0>; 149 }; 150 }; 151 152 CPU2: cpu@200 { 153 device_type = "cpu"; 154 compatible = "qcom,kryo485"; 155 reg = <0x0 0x200>; 156 clocks = <&cpufreq_hw 0>; 157 enable-method = "psci"; 158 capacity-dmips-mhz = <448>; 159 dynamic-power-coefficient = <205>; 160 next-level-cache = <&L2_200>; 161 power-domains = <&CPU_PD2>; 162 power-domain-names = "psci"; 163 qcom,freq-domain = <&cpufreq_hw 0>; 164 operating-points-v2 = <&cpu0_opp_table>; 165 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 166 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 167 #cooling-cells = <2>; 168 L2_200: l2-cache { 169 compatible = "cache"; 170 cache-level = <2>; 171 cache-size = <0x20000>; 172 cache-unified; 173 next-level-cache = <&L3_0>; 174 }; 175 }; 176 177 CPU3: cpu@300 { 178 device_type = "cpu"; 179 compatible = "qcom,kryo485"; 180 reg = <0x0 0x300>; 181 clocks = <&cpufreq_hw 0>; 182 enable-method = "psci"; 183 capacity-dmips-mhz = <448>; 184 dynamic-power-coefficient = <205>; 185 next-level-cache = <&L2_300>; 186 power-domains = <&CPU_PD3>; 187 power-domain-names = "psci"; 188 qcom,freq-domain = <&cpufreq_hw 0>; 189 operating-points-v2 = <&cpu0_opp_table>; 190 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 191 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 192 #cooling-cells = <2>; 193 L2_300: l2-cache { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-size = <0x20000>; 197 cache-unified; 198 next-level-cache = <&L3_0>; 199 }; 200 }; 201 202 CPU4: cpu@400 { 203 device_type = "cpu"; 204 compatible = "qcom,kryo485"; 205 reg = <0x0 0x400>; 206 clocks = <&cpufreq_hw 1>; 207 enable-method = "psci"; 208 capacity-dmips-mhz = <1024>; 209 dynamic-power-coefficient = <379>; 210 next-level-cache = <&L2_400>; 211 power-domains = <&CPU_PD4>; 212 power-domain-names = "psci"; 213 qcom,freq-domain = <&cpufreq_hw 1>; 214 operating-points-v2 = <&cpu4_opp_table>; 215 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 216 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 217 #cooling-cells = <2>; 218 L2_400: l2-cache { 219 compatible = "cache"; 220 cache-level = <2>; 221 cache-size = <0x40000>; 222 cache-unified; 223 next-level-cache = <&L3_0>; 224 }; 225 }; 226 227 CPU5: cpu@500 { 228 device_type = "cpu"; 229 compatible = "qcom,kryo485"; 230 reg = <0x0 0x500>; 231 clocks = <&cpufreq_hw 1>; 232 enable-method = "psci"; 233 capacity-dmips-mhz = <1024>; 234 dynamic-power-coefficient = <379>; 235 next-level-cache = <&L2_500>; 236 power-domains = <&CPU_PD5>; 237 power-domain-names = "psci"; 238 qcom,freq-domain = <&cpufreq_hw 1>; 239 operating-points-v2 = <&cpu4_opp_table>; 240 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 241 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 242 #cooling-cells = <2>; 243 L2_500: l2-cache { 244 compatible = "cache"; 245 cache-level = <2>; 246 cache-size = <0x40000>; 247 cache-unified; 248 next-level-cache = <&L3_0>; 249 }; 250 }; 251 252 CPU6: cpu@600 { 253 device_type = "cpu"; 254 compatible = "qcom,kryo485"; 255 reg = <0x0 0x600>; 256 clocks = <&cpufreq_hw 1>; 257 enable-method = "psci"; 258 capacity-dmips-mhz = <1024>; 259 dynamic-power-coefficient = <379>; 260 next-level-cache = <&L2_600>; 261 power-domains = <&CPU_PD6>; 262 power-domain-names = "psci"; 263 qcom,freq-domain = <&cpufreq_hw 1>; 264 operating-points-v2 = <&cpu4_opp_table>; 265 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 266 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 267 #cooling-cells = <2>; 268 L2_600: l2-cache { 269 compatible = "cache"; 270 cache-level = <2>; 271 cache-size = <0x40000>; 272 cache-unified; 273 next-level-cache = <&L3_0>; 274 }; 275 }; 276 277 CPU7: cpu@700 { 278 device_type = "cpu"; 279 compatible = "qcom,kryo485"; 280 reg = <0x0 0x700>; 281 clocks = <&cpufreq_hw 2>; 282 enable-method = "psci"; 283 capacity-dmips-mhz = <1024>; 284 dynamic-power-coefficient = <444>; 285 next-level-cache = <&L2_700>; 286 power-domains = <&CPU_PD7>; 287 power-domain-names = "psci"; 288 qcom,freq-domain = <&cpufreq_hw 2>; 289 operating-points-v2 = <&cpu7_opp_table>; 290 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 291 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 292 #cooling-cells = <2>; 293 L2_700: l2-cache { 294 compatible = "cache"; 295 cache-level = <2>; 296 cache-size = <0x80000>; 297 cache-unified; 298 next-level-cache = <&L3_0>; 299 }; 300 }; 301 302 cpu-map { 303 cluster0 { 304 core0 { 305 cpu = <&CPU0>; 306 }; 307 308 core1 { 309 cpu = <&CPU1>; 310 }; 311 312 core2 { 313 cpu = <&CPU2>; 314 }; 315 316 core3 { 317 cpu = <&CPU3>; 318 }; 319 320 core4 { 321 cpu = <&CPU4>; 322 }; 323 324 core5 { 325 cpu = <&CPU5>; 326 }; 327 328 core6 { 329 cpu = <&CPU6>; 330 }; 331 332 core7 { 333 cpu = <&CPU7>; 334 }; 335 }; 336 }; 337 338 idle-states { 339 entry-method = "psci"; 340 341 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 342 compatible = "arm,idle-state"; 343 idle-state-name = "silver-rail-power-collapse"; 344 arm,psci-suspend-param = <0x40000004>; 345 entry-latency-us = <360>; 346 exit-latency-us = <531>; 347 min-residency-us = <3934>; 348 local-timer-stop; 349 }; 350 351 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 352 compatible = "arm,idle-state"; 353 idle-state-name = "gold-rail-power-collapse"; 354 arm,psci-suspend-param = <0x40000004>; 355 entry-latency-us = <702>; 356 exit-latency-us = <1061>; 357 min-residency-us = <4488>; 358 local-timer-stop; 359 }; 360 }; 361 362 domain-idle-states { 363 CLUSTER_SLEEP_0: cluster-sleep-0 { 364 compatible = "domain-idle-state"; 365 arm,psci-suspend-param = <0x4100c244>; 366 entry-latency-us = <3264>; 367 exit-latency-us = <6562>; 368 min-residency-us = <9987>; 369 }; 370 }; 371 }; 372 373 cpu0_opp_table: opp-table-cpu0 { 374 compatible = "operating-points-v2"; 375 opp-shared; 376 377 cpu0_opp1: opp-300000000 { 378 opp-hz = /bits/ 64 <300000000>; 379 opp-peak-kBps = <800000 9600000>; 380 }; 381 382 cpu0_opp2: opp-403200000 { 383 opp-hz = /bits/ 64 <403200000>; 384 opp-peak-kBps = <800000 9600000>; 385 }; 386 387 cpu0_opp3: opp-518400000 { 388 opp-hz = /bits/ 64 <518400000>; 389 opp-peak-kBps = <800000 16588800>; 390 }; 391 392 cpu0_opp4: opp-614400000 { 393 opp-hz = /bits/ 64 <614400000>; 394 opp-peak-kBps = <800000 16588800>; 395 }; 396 397 cpu0_opp5: opp-691200000 { 398 opp-hz = /bits/ 64 <691200000>; 399 opp-peak-kBps = <800000 19660800>; 400 }; 401 402 cpu0_opp6: opp-787200000 { 403 opp-hz = /bits/ 64 <787200000>; 404 opp-peak-kBps = <1804000 19660800>; 405 }; 406 407 cpu0_opp7: opp-883200000 { 408 opp-hz = /bits/ 64 <883200000>; 409 opp-peak-kBps = <1804000 23347200>; 410 }; 411 412 cpu0_opp8: opp-979200000 { 413 opp-hz = /bits/ 64 <979200000>; 414 opp-peak-kBps = <1804000 26419200>; 415 }; 416 417 cpu0_opp9: opp-1075200000 { 418 opp-hz = /bits/ 64 <1075200000>; 419 opp-peak-kBps = <1804000 29491200>; 420 }; 421 422 cpu0_opp10: opp-1171200000 { 423 opp-hz = /bits/ 64 <1171200000>; 424 opp-peak-kBps = <1804000 32563200>; 425 }; 426 427 cpu0_opp11: opp-1248000000 { 428 opp-hz = /bits/ 64 <1248000000>; 429 opp-peak-kBps = <1804000 36249600>; 430 }; 431 432 cpu0_opp12: opp-1344000000 { 433 opp-hz = /bits/ 64 <1344000000>; 434 opp-peak-kBps = <2188000 36249600>; 435 }; 436 437 cpu0_opp13: opp-1420800000 { 438 opp-hz = /bits/ 64 <1420800000>; 439 opp-peak-kBps = <2188000 39321600>; 440 }; 441 442 cpu0_opp14: opp-1516800000 { 443 opp-hz = /bits/ 64 <1516800000>; 444 opp-peak-kBps = <3072000 42393600>; 445 }; 446 447 cpu0_opp15: opp-1612800000 { 448 opp-hz = /bits/ 64 <1612800000>; 449 opp-peak-kBps = <3072000 42393600>; 450 }; 451 452 cpu0_opp16: opp-1708800000 { 453 opp-hz = /bits/ 64 <1708800000>; 454 opp-peak-kBps = <4068000 42393600>; 455 }; 456 457 cpu0_opp17: opp-1804800000 { 458 opp-hz = /bits/ 64 <1804800000>; 459 opp-peak-kBps = <4068000 42393600>; 460 }; 461 }; 462 463 cpu4_opp_table: opp-table-cpu4 { 464 compatible = "operating-points-v2"; 465 opp-shared; 466 467 cpu4_opp1: opp-710400000 { 468 opp-hz = /bits/ 64 <710400000>; 469 opp-peak-kBps = <1804000 19660800>; 470 }; 471 472 cpu4_opp2: opp-825600000 { 473 opp-hz = /bits/ 64 <825600000>; 474 opp-peak-kBps = <2188000 23347200>; 475 }; 476 477 cpu4_opp3: opp-940800000 { 478 opp-hz = /bits/ 64 <940800000>; 479 opp-peak-kBps = <2188000 26419200>; 480 }; 481 482 cpu4_opp4: opp-1056000000 { 483 opp-hz = /bits/ 64 <1056000000>; 484 opp-peak-kBps = <3072000 26419200>; 485 }; 486 487 cpu4_opp5: opp-1171200000 { 488 opp-hz = /bits/ 64 <1171200000>; 489 opp-peak-kBps = <3072000 29491200>; 490 }; 491 492 cpu4_opp6: opp-1286400000 { 493 opp-hz = /bits/ 64 <1286400000>; 494 opp-peak-kBps = <4068000 29491200>; 495 }; 496 497 cpu4_opp7: opp-1382400000 { 498 opp-hz = /bits/ 64 <1382400000>; 499 opp-peak-kBps = <4068000 32563200>; 500 }; 501 502 cpu4_opp8: opp-1478400000 { 503 opp-hz = /bits/ 64 <1478400000>; 504 opp-peak-kBps = <4068000 32563200>; 505 }; 506 507 cpu4_opp9: opp-1574400000 { 508 opp-hz = /bits/ 64 <1574400000>; 509 opp-peak-kBps = <5412000 39321600>; 510 }; 511 512 cpu4_opp10: opp-1670400000 { 513 opp-hz = /bits/ 64 <1670400000>; 514 opp-peak-kBps = <5412000 42393600>; 515 }; 516 517 cpu4_opp11: opp-1766400000 { 518 opp-hz = /bits/ 64 <1766400000>; 519 opp-peak-kBps = <5412000 45465600>; 520 }; 521 522 cpu4_opp12: opp-1862400000 { 523 opp-hz = /bits/ 64 <1862400000>; 524 opp-peak-kBps = <6220000 45465600>; 525 }; 526 527 cpu4_opp13: opp-1958400000 { 528 opp-hz = /bits/ 64 <1958400000>; 529 opp-peak-kBps = <6220000 48537600>; 530 }; 531 532 cpu4_opp14: opp-2054400000 { 533 opp-hz = /bits/ 64 <2054400000>; 534 opp-peak-kBps = <7216000 48537600>; 535 }; 536 537 cpu4_opp15: opp-2150400000 { 538 opp-hz = /bits/ 64 <2150400000>; 539 opp-peak-kBps = <7216000 51609600>; 540 }; 541 542 cpu4_opp16: opp-2246400000 { 543 opp-hz = /bits/ 64 <2246400000>; 544 opp-peak-kBps = <7216000 51609600>; 545 }; 546 547 cpu4_opp17: opp-2342400000 { 548 opp-hz = /bits/ 64 <2342400000>; 549 opp-peak-kBps = <8368000 51609600>; 550 }; 551 552 cpu4_opp18: opp-2419200000 { 553 opp-hz = /bits/ 64 <2419200000>; 554 opp-peak-kBps = <8368000 51609600>; 555 }; 556 }; 557 558 cpu7_opp_table: opp-table-cpu7 { 559 compatible = "operating-points-v2"; 560 opp-shared; 561 562 cpu7_opp1: opp-844800000 { 563 opp-hz = /bits/ 64 <844800000>; 564 opp-peak-kBps = <2188000 19660800>; 565 }; 566 567 cpu7_opp2: opp-960000000 { 568 opp-hz = /bits/ 64 <960000000>; 569 opp-peak-kBps = <2188000 26419200>; 570 }; 571 572 cpu7_opp3: opp-1075200000 { 573 opp-hz = /bits/ 64 <1075200000>; 574 opp-peak-kBps = <3072000 26419200>; 575 }; 576 577 cpu7_opp4: opp-1190400000 { 578 opp-hz = /bits/ 64 <1190400000>; 579 opp-peak-kBps = <3072000 29491200>; 580 }; 581 582 cpu7_opp5: opp-1305600000 { 583 opp-hz = /bits/ 64 <1305600000>; 584 opp-peak-kBps = <4068000 32563200>; 585 }; 586 587 cpu7_opp6: opp-1401600000 { 588 opp-hz = /bits/ 64 <1401600000>; 589 opp-peak-kBps = <4068000 32563200>; 590 }; 591 592 cpu7_opp7: opp-1516800000 { 593 opp-hz = /bits/ 64 <1516800000>; 594 opp-peak-kBps = <4068000 36249600>; 595 }; 596 597 cpu7_opp8: opp-1632000000 { 598 opp-hz = /bits/ 64 <1632000000>; 599 opp-peak-kBps = <5412000 39321600>; 600 }; 601 602 cpu7_opp9: opp-1747200000 { 603 opp-hz = /bits/ 64 <1708800000>; 604 opp-peak-kBps = <5412000 42393600>; 605 }; 606 607 cpu7_opp10: opp-1862400000 { 608 opp-hz = /bits/ 64 <1862400000>; 609 opp-peak-kBps = <6220000 45465600>; 610 }; 611 612 cpu7_opp11: opp-1977600000 { 613 opp-hz = /bits/ 64 <1977600000>; 614 opp-peak-kBps = <6220000 48537600>; 615 }; 616 617 cpu7_opp12: opp-2073600000 { 618 opp-hz = /bits/ 64 <2073600000>; 619 opp-peak-kBps = <7216000 48537600>; 620 }; 621 622 cpu7_opp13: opp-2169600000 { 623 opp-hz = /bits/ 64 <2169600000>; 624 opp-peak-kBps = <7216000 51609600>; 625 }; 626 627 cpu7_opp14: opp-2265600000 { 628 opp-hz = /bits/ 64 <2265600000>; 629 opp-peak-kBps = <7216000 51609600>; 630 }; 631 632 cpu7_opp15: opp-2361600000 { 633 opp-hz = /bits/ 64 <2361600000>; 634 opp-peak-kBps = <8368000 51609600>; 635 }; 636 637 cpu7_opp16: opp-2457600000 { 638 opp-hz = /bits/ 64 <2457600000>; 639 opp-peak-kBps = <8368000 51609600>; 640 }; 641 642 cpu7_opp17: opp-2553600000 { 643 opp-hz = /bits/ 64 <2553600000>; 644 opp-peak-kBps = <8368000 51609600>; 645 }; 646 647 cpu7_opp18: opp-2649600000 { 648 opp-hz = /bits/ 64 <2649600000>; 649 opp-peak-kBps = <8368000 51609600>; 650 }; 651 652 cpu7_opp19: opp-2745600000 { 653 opp-hz = /bits/ 64 <2745600000>; 654 opp-peak-kBps = <8368000 51609600>; 655 }; 656 657 cpu7_opp20: opp-2841600000 { 658 opp-hz = /bits/ 64 <2841600000>; 659 opp-peak-kBps = <8368000 51609600>; 660 }; 661 }; 662 663 firmware { 664 scm: scm { 665 compatible = "qcom,scm-sm8250", "qcom,scm"; 666 #reset-cells = <1>; 667 }; 668 }; 669 670 memory@80000000 { 671 device_type = "memory"; 672 /* We expect the bootloader to fill in the size */ 673 reg = <0x0 0x80000000 0x0 0x0>; 674 }; 675 676 pmu { 677 compatible = "arm,armv8-pmuv3"; 678 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 679 }; 680 681 psci { 682 compatible = "arm,psci-1.0"; 683 method = "smc"; 684 685 CPU_PD0: power-domain-cpu0 { 686 #power-domain-cells = <0>; 687 power-domains = <&CLUSTER_PD>; 688 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 689 }; 690 691 CPU_PD1: power-domain-cpu1 { 692 #power-domain-cells = <0>; 693 power-domains = <&CLUSTER_PD>; 694 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 695 }; 696 697 CPU_PD2: power-domain-cpu2 { 698 #power-domain-cells = <0>; 699 power-domains = <&CLUSTER_PD>; 700 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 701 }; 702 703 CPU_PD3: power-domain-cpu3 { 704 #power-domain-cells = <0>; 705 power-domains = <&CLUSTER_PD>; 706 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 707 }; 708 709 CPU_PD4: power-domain-cpu4 { 710 #power-domain-cells = <0>; 711 power-domains = <&CLUSTER_PD>; 712 domain-idle-states = <&BIG_CPU_SLEEP_0>; 713 }; 714 715 CPU_PD5: power-domain-cpu5 { 716 #power-domain-cells = <0>; 717 power-domains = <&CLUSTER_PD>; 718 domain-idle-states = <&BIG_CPU_SLEEP_0>; 719 }; 720 721 CPU_PD6: power-domain-cpu6 { 722 #power-domain-cells = <0>; 723 power-domains = <&CLUSTER_PD>; 724 domain-idle-states = <&BIG_CPU_SLEEP_0>; 725 }; 726 727 CPU_PD7: power-domain-cpu7 { 728 #power-domain-cells = <0>; 729 power-domains = <&CLUSTER_PD>; 730 domain-idle-states = <&BIG_CPU_SLEEP_0>; 731 }; 732 733 CLUSTER_PD: power-domain-cpu-cluster0 { 734 #power-domain-cells = <0>; 735 domain-idle-states = <&CLUSTER_SLEEP_0>; 736 }; 737 }; 738 739 qup_opp_table: opp-table-qup { 740 compatible = "operating-points-v2"; 741 742 opp-50000000 { 743 opp-hz = /bits/ 64 <50000000>; 744 required-opps = <&rpmhpd_opp_min_svs>; 745 }; 746 747 opp-75000000 { 748 opp-hz = /bits/ 64 <75000000>; 749 required-opps = <&rpmhpd_opp_low_svs>; 750 }; 751 752 opp-120000000 { 753 opp-hz = /bits/ 64 <120000000>; 754 required-opps = <&rpmhpd_opp_svs>; 755 }; 756 }; 757 758 reserved-memory { 759 #address-cells = <2>; 760 #size-cells = <2>; 761 ranges; 762 763 hyp_mem: memory@80000000 { 764 reg = <0x0 0x80000000 0x0 0x600000>; 765 no-map; 766 }; 767 768 xbl_aop_mem: memory@80700000 { 769 reg = <0x0 0x80700000 0x0 0x160000>; 770 no-map; 771 }; 772 773 cmd_db: memory@80860000 { 774 compatible = "qcom,cmd-db"; 775 reg = <0x0 0x80860000 0x0 0x20000>; 776 no-map; 777 }; 778 779 smem_mem: memory@80900000 { 780 reg = <0x0 0x80900000 0x0 0x200000>; 781 no-map; 782 }; 783 784 removed_mem: memory@80b00000 { 785 reg = <0x0 0x80b00000 0x0 0x5300000>; 786 no-map; 787 }; 788 789 camera_mem: memory@86200000 { 790 reg = <0x0 0x86200000 0x0 0x500000>; 791 no-map; 792 }; 793 794 wlan_mem: memory@86700000 { 795 reg = <0x0 0x86700000 0x0 0x100000>; 796 no-map; 797 }; 798 799 ipa_fw_mem: memory@86800000 { 800 reg = <0x0 0x86800000 0x0 0x10000>; 801 no-map; 802 }; 803 804 ipa_gsi_mem: memory@86810000 { 805 reg = <0x0 0x86810000 0x0 0xa000>; 806 no-map; 807 }; 808 809 gpu_mem: memory@8681a000 { 810 reg = <0x0 0x8681a000 0x0 0x2000>; 811 no-map; 812 }; 813 814 npu_mem: memory@86900000 { 815 reg = <0x0 0x86900000 0x0 0x500000>; 816 no-map; 817 }; 818 819 video_mem: memory@86e00000 { 820 reg = <0x0 0x86e00000 0x0 0x500000>; 821 no-map; 822 }; 823 824 cvp_mem: memory@87300000 { 825 reg = <0x0 0x87300000 0x0 0x500000>; 826 no-map; 827 }; 828 829 cdsp_mem: memory@87800000 { 830 reg = <0x0 0x87800000 0x0 0x1400000>; 831 no-map; 832 }; 833 834 slpi_mem: memory@88c00000 { 835 reg = <0x0 0x88c00000 0x0 0x1500000>; 836 no-map; 837 }; 838 839 adsp_mem: memory@8a100000 { 840 reg = <0x0 0x8a100000 0x0 0x1d00000>; 841 no-map; 842 }; 843 844 spss_mem: memory@8be00000 { 845 reg = <0x0 0x8be00000 0x0 0x100000>; 846 no-map; 847 }; 848 849 cdsp_secure_heap: memory@8bf00000 { 850 reg = <0x0 0x8bf00000 0x0 0x4600000>; 851 no-map; 852 }; 853 }; 854 855 smem { 856 compatible = "qcom,smem"; 857 memory-region = <&smem_mem>; 858 hwlocks = <&tcsr_mutex 3>; 859 }; 860 861 smp2p-adsp { 862 compatible = "qcom,smp2p"; 863 qcom,smem = <443>, <429>; 864 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 865 IPCC_MPROC_SIGNAL_SMP2P 866 IRQ_TYPE_EDGE_RISING>; 867 mboxes = <&ipcc IPCC_CLIENT_LPASS 868 IPCC_MPROC_SIGNAL_SMP2P>; 869 870 qcom,local-pid = <0>; 871 qcom,remote-pid = <2>; 872 873 smp2p_adsp_out: master-kernel { 874 qcom,entry-name = "master-kernel"; 875 #qcom,smem-state-cells = <1>; 876 }; 877 878 smp2p_adsp_in: slave-kernel { 879 qcom,entry-name = "slave-kernel"; 880 interrupt-controller; 881 #interrupt-cells = <2>; 882 }; 883 }; 884 885 smp2p-cdsp { 886 compatible = "qcom,smp2p"; 887 qcom,smem = <94>, <432>; 888 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 889 IPCC_MPROC_SIGNAL_SMP2P 890 IRQ_TYPE_EDGE_RISING>; 891 mboxes = <&ipcc IPCC_CLIENT_CDSP 892 IPCC_MPROC_SIGNAL_SMP2P>; 893 894 qcom,local-pid = <0>; 895 qcom,remote-pid = <5>; 896 897 smp2p_cdsp_out: master-kernel { 898 qcom,entry-name = "master-kernel"; 899 #qcom,smem-state-cells = <1>; 900 }; 901 902 smp2p_cdsp_in: slave-kernel { 903 qcom,entry-name = "slave-kernel"; 904 interrupt-controller; 905 #interrupt-cells = <2>; 906 }; 907 }; 908 909 smp2p-slpi { 910 compatible = "qcom,smp2p"; 911 qcom,smem = <481>, <430>; 912 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 913 IPCC_MPROC_SIGNAL_SMP2P 914 IRQ_TYPE_EDGE_RISING>; 915 mboxes = <&ipcc IPCC_CLIENT_SLPI 916 IPCC_MPROC_SIGNAL_SMP2P>; 917 918 qcom,local-pid = <0>; 919 qcom,remote-pid = <3>; 920 921 smp2p_slpi_out: master-kernel { 922 qcom,entry-name = "master-kernel"; 923 #qcom,smem-state-cells = <1>; 924 }; 925 926 smp2p_slpi_in: slave-kernel { 927 qcom,entry-name = "slave-kernel"; 928 interrupt-controller; 929 #interrupt-cells = <2>; 930 }; 931 }; 932 933 soc: soc@0 { 934 #address-cells = <2>; 935 #size-cells = <2>; 936 ranges = <0 0 0 0 0x10 0>; 937 dma-ranges = <0 0 0 0 0x10 0>; 938 compatible = "simple-bus"; 939 940 gcc: clock-controller@100000 { 941 compatible = "qcom,gcc-sm8250"; 942 reg = <0x0 0x00100000 0x0 0x1f0000>; 943 #clock-cells = <1>; 944 #reset-cells = <1>; 945 #power-domain-cells = <1>; 946 clock-names = "bi_tcxo", 947 "bi_tcxo_ao", 948 "sleep_clk"; 949 clocks = <&rpmhcc RPMH_CXO_CLK>, 950 <&rpmhcc RPMH_CXO_CLK_A>, 951 <&sleep_clk>; 952 }; 953 954 ipcc: mailbox@408000 { 955 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 956 reg = <0 0x00408000 0 0x1000>; 957 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 958 interrupt-controller; 959 #interrupt-cells = <3>; 960 #mbox-cells = <2>; 961 }; 962 963 qfprom: efuse@784000 { 964 compatible = "qcom,sm8250-qfprom", "qcom,qfprom"; 965 reg = <0 0x00784000 0 0x8ff>; 966 #address-cells = <1>; 967 #size-cells = <1>; 968 969 gpu_speed_bin: gpu_speed_bin@19b { 970 reg = <0x19b 0x1>; 971 bits = <5 3>; 972 }; 973 }; 974 975 rng: rng@793000 { 976 compatible = "qcom,prng-ee"; 977 reg = <0 0x00793000 0 0x1000>; 978 clocks = <&gcc GCC_PRNG_AHB_CLK>; 979 clock-names = "core"; 980 }; 981 982 gpi_dma2: dma-controller@800000 { 983 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 984 reg = <0 0x00800000 0 0x70000>; 985 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 995 dma-channels = <10>; 996 dma-channel-mask = <0x3f>; 997 iommus = <&apps_smmu 0x76 0x0>; 998 #dma-cells = <3>; 999 status = "disabled"; 1000 }; 1001 1002 qupv3_id_2: geniqup@8c0000 { 1003 compatible = "qcom,geni-se-qup"; 1004 reg = <0x0 0x008c0000 0x0 0x6000>; 1005 clock-names = "m-ahb", "s-ahb"; 1006 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1007 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1008 #address-cells = <2>; 1009 #size-cells = <2>; 1010 iommus = <&apps_smmu 0x63 0x0>; 1011 ranges; 1012 status = "disabled"; 1013 1014 i2c14: i2c@880000 { 1015 compatible = "qcom,geni-i2c"; 1016 reg = <0 0x00880000 0 0x4000>; 1017 clock-names = "se"; 1018 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&qup_i2c14_default>; 1021 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1022 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1023 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1024 dma-names = "tx", "rx"; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 status = "disabled"; 1028 }; 1029 1030 spi14: spi@880000 { 1031 compatible = "qcom,geni-spi"; 1032 reg = <0 0x00880000 0 0x4000>; 1033 clock-names = "se"; 1034 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1035 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1036 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1037 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1038 dma-names = "tx", "rx"; 1039 power-domains = <&rpmhpd SM8250_CX>; 1040 operating-points-v2 = <&qup_opp_table>; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 status = "disabled"; 1044 }; 1045 1046 i2c15: i2c@884000 { 1047 compatible = "qcom,geni-i2c"; 1048 reg = <0 0x00884000 0 0x4000>; 1049 clock-names = "se"; 1050 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1051 pinctrl-names = "default"; 1052 pinctrl-0 = <&qup_i2c15_default>; 1053 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1054 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1055 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1056 dma-names = "tx", "rx"; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 status = "disabled"; 1060 }; 1061 1062 spi15: spi@884000 { 1063 compatible = "qcom,geni-spi"; 1064 reg = <0 0x00884000 0 0x4000>; 1065 clock-names = "se"; 1066 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1067 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1068 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1069 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1070 dma-names = "tx", "rx"; 1071 power-domains = <&rpmhpd SM8250_CX>; 1072 operating-points-v2 = <&qup_opp_table>; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 status = "disabled"; 1076 }; 1077 1078 i2c16: i2c@888000 { 1079 compatible = "qcom,geni-i2c"; 1080 reg = <0 0x00888000 0 0x4000>; 1081 clock-names = "se"; 1082 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1083 pinctrl-names = "default"; 1084 pinctrl-0 = <&qup_i2c16_default>; 1085 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1086 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1087 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1088 dma-names = "tx", "rx"; 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 status = "disabled"; 1092 }; 1093 1094 spi16: spi@888000 { 1095 compatible = "qcom,geni-spi"; 1096 reg = <0 0x00888000 0 0x4000>; 1097 clock-names = "se"; 1098 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1099 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1100 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1101 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1102 dma-names = "tx", "rx"; 1103 power-domains = <&rpmhpd SM8250_CX>; 1104 operating-points-v2 = <&qup_opp_table>; 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 status = "disabled"; 1108 }; 1109 1110 i2c17: i2c@88c000 { 1111 compatible = "qcom,geni-i2c"; 1112 reg = <0 0x0088c000 0 0x4000>; 1113 clock-names = "se"; 1114 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1115 pinctrl-names = "default"; 1116 pinctrl-0 = <&qup_i2c17_default>; 1117 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1118 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1119 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1120 dma-names = "tx", "rx"; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 status = "disabled"; 1124 }; 1125 1126 spi17: spi@88c000 { 1127 compatible = "qcom,geni-spi"; 1128 reg = <0 0x0088c000 0 0x4000>; 1129 clock-names = "se"; 1130 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1131 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1132 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1133 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1134 dma-names = "tx", "rx"; 1135 power-domains = <&rpmhpd SM8250_CX>; 1136 operating-points-v2 = <&qup_opp_table>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 status = "disabled"; 1140 }; 1141 1142 uart17: serial@88c000 { 1143 compatible = "qcom,geni-uart"; 1144 reg = <0 0x0088c000 0 0x4000>; 1145 clock-names = "se"; 1146 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1147 pinctrl-names = "default"; 1148 pinctrl-0 = <&qup_uart17_default>; 1149 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1150 power-domains = <&rpmhpd SM8250_CX>; 1151 operating-points-v2 = <&qup_opp_table>; 1152 status = "disabled"; 1153 }; 1154 1155 i2c18: i2c@890000 { 1156 compatible = "qcom,geni-i2c"; 1157 reg = <0 0x00890000 0 0x4000>; 1158 clock-names = "se"; 1159 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1160 pinctrl-names = "default"; 1161 pinctrl-0 = <&qup_i2c18_default>; 1162 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1163 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1164 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1165 dma-names = "tx", "rx"; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 status = "disabled"; 1169 }; 1170 1171 spi18: spi@890000 { 1172 compatible = "qcom,geni-spi"; 1173 reg = <0 0x00890000 0 0x4000>; 1174 clock-names = "se"; 1175 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1176 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1177 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1178 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1179 dma-names = "tx", "rx"; 1180 power-domains = <&rpmhpd SM8250_CX>; 1181 operating-points-v2 = <&qup_opp_table>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 status = "disabled"; 1185 }; 1186 1187 uart18: serial@890000 { 1188 compatible = "qcom,geni-uart"; 1189 reg = <0 0x00890000 0 0x4000>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&qup_uart18_default>; 1194 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1195 power-domains = <&rpmhpd SM8250_CX>; 1196 operating-points-v2 = <&qup_opp_table>; 1197 status = "disabled"; 1198 }; 1199 1200 i2c19: i2c@894000 { 1201 compatible = "qcom,geni-i2c"; 1202 reg = <0 0x00894000 0 0x4000>; 1203 clock-names = "se"; 1204 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1205 pinctrl-names = "default"; 1206 pinctrl-0 = <&qup_i2c19_default>; 1207 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1208 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1209 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1210 dma-names = "tx", "rx"; 1211 #address-cells = <1>; 1212 #size-cells = <0>; 1213 status = "disabled"; 1214 }; 1215 1216 spi19: spi@894000 { 1217 compatible = "qcom,geni-spi"; 1218 reg = <0 0x00894000 0 0x4000>; 1219 clock-names = "se"; 1220 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1221 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1222 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1223 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1224 dma-names = "tx", "rx"; 1225 power-domains = <&rpmhpd SM8250_CX>; 1226 operating-points-v2 = <&qup_opp_table>; 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 status = "disabled"; 1230 }; 1231 }; 1232 1233 gpi_dma0: dma-controller@900000 { 1234 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1235 reg = <0 0x00900000 0 0x70000>; 1236 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1249 dma-channels = <15>; 1250 dma-channel-mask = <0x7ff>; 1251 iommus = <&apps_smmu 0x5b6 0x0>; 1252 #dma-cells = <3>; 1253 status = "disabled"; 1254 }; 1255 1256 qupv3_id_0: geniqup@9c0000 { 1257 compatible = "qcom,geni-se-qup"; 1258 reg = <0x0 0x009c0000 0x0 0x6000>; 1259 clock-names = "m-ahb", "s-ahb"; 1260 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1261 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1262 #address-cells = <2>; 1263 #size-cells = <2>; 1264 iommus = <&apps_smmu 0x5a3 0x0>; 1265 ranges; 1266 status = "disabled"; 1267 1268 i2c0: i2c@980000 { 1269 compatible = "qcom,geni-i2c"; 1270 reg = <0 0x00980000 0 0x4000>; 1271 clock-names = "se"; 1272 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1273 pinctrl-names = "default"; 1274 pinctrl-0 = <&qup_i2c0_default>; 1275 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1276 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1277 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1278 dma-names = "tx", "rx"; 1279 #address-cells = <1>; 1280 #size-cells = <0>; 1281 status = "disabled"; 1282 }; 1283 1284 spi0: spi@980000 { 1285 compatible = "qcom,geni-spi"; 1286 reg = <0 0x00980000 0 0x4000>; 1287 clock-names = "se"; 1288 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1289 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1290 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1291 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1292 dma-names = "tx", "rx"; 1293 power-domains = <&rpmhpd SM8250_CX>; 1294 operating-points-v2 = <&qup_opp_table>; 1295 #address-cells = <1>; 1296 #size-cells = <0>; 1297 status = "disabled"; 1298 }; 1299 1300 i2c1: i2c@984000 { 1301 compatible = "qcom,geni-i2c"; 1302 reg = <0 0x00984000 0 0x4000>; 1303 clock-names = "se"; 1304 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1305 pinctrl-names = "default"; 1306 pinctrl-0 = <&qup_i2c1_default>; 1307 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1308 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1309 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1310 dma-names = "tx", "rx"; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 status = "disabled"; 1314 }; 1315 1316 spi1: spi@984000 { 1317 compatible = "qcom,geni-spi"; 1318 reg = <0 0x00984000 0 0x4000>; 1319 clock-names = "se"; 1320 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1321 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1322 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1323 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1324 dma-names = "tx", "rx"; 1325 power-domains = <&rpmhpd SM8250_CX>; 1326 operating-points-v2 = <&qup_opp_table>; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 status = "disabled"; 1330 }; 1331 1332 i2c2: i2c@988000 { 1333 compatible = "qcom,geni-i2c"; 1334 reg = <0 0x00988000 0 0x4000>; 1335 clock-names = "se"; 1336 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1337 pinctrl-names = "default"; 1338 pinctrl-0 = <&qup_i2c2_default>; 1339 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1340 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1341 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1342 dma-names = "tx", "rx"; 1343 #address-cells = <1>; 1344 #size-cells = <0>; 1345 status = "disabled"; 1346 }; 1347 1348 spi2: spi@988000 { 1349 compatible = "qcom,geni-spi"; 1350 reg = <0 0x00988000 0 0x4000>; 1351 clock-names = "se"; 1352 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1353 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1354 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1355 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1356 dma-names = "tx", "rx"; 1357 power-domains = <&rpmhpd SM8250_CX>; 1358 operating-points-v2 = <&qup_opp_table>; 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 status = "disabled"; 1362 }; 1363 1364 uart2: serial@988000 { 1365 compatible = "qcom,geni-debug-uart"; 1366 reg = <0 0x00988000 0 0x4000>; 1367 clock-names = "se"; 1368 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1369 pinctrl-names = "default"; 1370 pinctrl-0 = <&qup_uart2_default>; 1371 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1372 power-domains = <&rpmhpd SM8250_CX>; 1373 operating-points-v2 = <&qup_opp_table>; 1374 status = "disabled"; 1375 }; 1376 1377 i2c3: i2c@98c000 { 1378 compatible = "qcom,geni-i2c"; 1379 reg = <0 0x0098c000 0 0x4000>; 1380 clock-names = "se"; 1381 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1382 pinctrl-names = "default"; 1383 pinctrl-0 = <&qup_i2c3_default>; 1384 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1385 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1386 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1387 dma-names = "tx", "rx"; 1388 #address-cells = <1>; 1389 #size-cells = <0>; 1390 status = "disabled"; 1391 }; 1392 1393 spi3: spi@98c000 { 1394 compatible = "qcom,geni-spi"; 1395 reg = <0 0x0098c000 0 0x4000>; 1396 clock-names = "se"; 1397 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1398 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1399 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1400 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1401 dma-names = "tx", "rx"; 1402 power-domains = <&rpmhpd SM8250_CX>; 1403 operating-points-v2 = <&qup_opp_table>; 1404 #address-cells = <1>; 1405 #size-cells = <0>; 1406 status = "disabled"; 1407 }; 1408 1409 i2c4: i2c@990000 { 1410 compatible = "qcom,geni-i2c"; 1411 reg = <0 0x00990000 0 0x4000>; 1412 clock-names = "se"; 1413 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1414 pinctrl-names = "default"; 1415 pinctrl-0 = <&qup_i2c4_default>; 1416 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1417 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1418 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1419 dma-names = "tx", "rx"; 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 status = "disabled"; 1423 }; 1424 1425 spi4: spi@990000 { 1426 compatible = "qcom,geni-spi"; 1427 reg = <0 0x00990000 0 0x4000>; 1428 clock-names = "se"; 1429 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1430 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1431 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1432 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1433 dma-names = "tx", "rx"; 1434 power-domains = <&rpmhpd SM8250_CX>; 1435 operating-points-v2 = <&qup_opp_table>; 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 status = "disabled"; 1439 }; 1440 1441 i2c5: i2c@994000 { 1442 compatible = "qcom,geni-i2c"; 1443 reg = <0 0x00994000 0 0x4000>; 1444 clock-names = "se"; 1445 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1446 pinctrl-names = "default"; 1447 pinctrl-0 = <&qup_i2c5_default>; 1448 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1449 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1450 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1451 dma-names = "tx", "rx"; 1452 #address-cells = <1>; 1453 #size-cells = <0>; 1454 status = "disabled"; 1455 }; 1456 1457 spi5: spi@994000 { 1458 compatible = "qcom,geni-spi"; 1459 reg = <0 0x00994000 0 0x4000>; 1460 clock-names = "se"; 1461 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1462 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1463 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1464 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1465 dma-names = "tx", "rx"; 1466 power-domains = <&rpmhpd SM8250_CX>; 1467 operating-points-v2 = <&qup_opp_table>; 1468 #address-cells = <1>; 1469 #size-cells = <0>; 1470 status = "disabled"; 1471 }; 1472 1473 i2c6: i2c@998000 { 1474 compatible = "qcom,geni-i2c"; 1475 reg = <0 0x00998000 0 0x4000>; 1476 clock-names = "se"; 1477 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1478 pinctrl-names = "default"; 1479 pinctrl-0 = <&qup_i2c6_default>; 1480 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1481 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1482 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1483 dma-names = "tx", "rx"; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 status = "disabled"; 1487 }; 1488 1489 spi6: spi@998000 { 1490 compatible = "qcom,geni-spi"; 1491 reg = <0 0x00998000 0 0x4000>; 1492 clock-names = "se"; 1493 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1494 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1495 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1496 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1497 dma-names = "tx", "rx"; 1498 power-domains = <&rpmhpd SM8250_CX>; 1499 operating-points-v2 = <&qup_opp_table>; 1500 #address-cells = <1>; 1501 #size-cells = <0>; 1502 status = "disabled"; 1503 }; 1504 1505 uart6: serial@998000 { 1506 compatible = "qcom,geni-uart"; 1507 reg = <0 0x00998000 0 0x4000>; 1508 clock-names = "se"; 1509 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1510 pinctrl-names = "default"; 1511 pinctrl-0 = <&qup_uart6_default>; 1512 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1513 power-domains = <&rpmhpd SM8250_CX>; 1514 operating-points-v2 = <&qup_opp_table>; 1515 status = "disabled"; 1516 }; 1517 1518 i2c7: i2c@99c000 { 1519 compatible = "qcom,geni-i2c"; 1520 reg = <0 0x0099c000 0 0x4000>; 1521 clock-names = "se"; 1522 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1523 pinctrl-names = "default"; 1524 pinctrl-0 = <&qup_i2c7_default>; 1525 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1526 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1527 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1528 dma-names = "tx", "rx"; 1529 #address-cells = <1>; 1530 #size-cells = <0>; 1531 status = "disabled"; 1532 }; 1533 1534 spi7: spi@99c000 { 1535 compatible = "qcom,geni-spi"; 1536 reg = <0 0x0099c000 0 0x4000>; 1537 clock-names = "se"; 1538 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1539 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1540 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1541 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1542 dma-names = "tx", "rx"; 1543 power-domains = <&rpmhpd SM8250_CX>; 1544 operating-points-v2 = <&qup_opp_table>; 1545 #address-cells = <1>; 1546 #size-cells = <0>; 1547 status = "disabled"; 1548 }; 1549 }; 1550 1551 gpi_dma1: dma-controller@a00000 { 1552 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1553 reg = <0 0x00a00000 0 0x70000>; 1554 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1564 dma-channels = <10>; 1565 dma-channel-mask = <0x3f>; 1566 iommus = <&apps_smmu 0x56 0x0>; 1567 #dma-cells = <3>; 1568 status = "disabled"; 1569 }; 1570 1571 qupv3_id_1: geniqup@ac0000 { 1572 compatible = "qcom,geni-se-qup"; 1573 reg = <0x0 0x00ac0000 0x0 0x6000>; 1574 clock-names = "m-ahb", "s-ahb"; 1575 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1576 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1577 #address-cells = <2>; 1578 #size-cells = <2>; 1579 iommus = <&apps_smmu 0x43 0x0>; 1580 ranges; 1581 status = "disabled"; 1582 1583 i2c8: i2c@a80000 { 1584 compatible = "qcom,geni-i2c"; 1585 reg = <0 0x00a80000 0 0x4000>; 1586 clock-names = "se"; 1587 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1588 pinctrl-names = "default"; 1589 pinctrl-0 = <&qup_i2c8_default>; 1590 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1591 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1592 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1593 dma-names = "tx", "rx"; 1594 #address-cells = <1>; 1595 #size-cells = <0>; 1596 status = "disabled"; 1597 }; 1598 1599 spi8: spi@a80000 { 1600 compatible = "qcom,geni-spi"; 1601 reg = <0 0x00a80000 0 0x4000>; 1602 clock-names = "se"; 1603 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1604 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1605 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1606 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1607 dma-names = "tx", "rx"; 1608 power-domains = <&rpmhpd SM8250_CX>; 1609 operating-points-v2 = <&qup_opp_table>; 1610 #address-cells = <1>; 1611 #size-cells = <0>; 1612 status = "disabled"; 1613 }; 1614 1615 i2c9: i2c@a84000 { 1616 compatible = "qcom,geni-i2c"; 1617 reg = <0 0x00a84000 0 0x4000>; 1618 clock-names = "se"; 1619 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1620 pinctrl-names = "default"; 1621 pinctrl-0 = <&qup_i2c9_default>; 1622 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1623 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1624 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1625 dma-names = "tx", "rx"; 1626 #address-cells = <1>; 1627 #size-cells = <0>; 1628 status = "disabled"; 1629 }; 1630 1631 spi9: spi@a84000 { 1632 compatible = "qcom,geni-spi"; 1633 reg = <0 0x00a84000 0 0x4000>; 1634 clock-names = "se"; 1635 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1636 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1637 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1638 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1639 dma-names = "tx", "rx"; 1640 power-domains = <&rpmhpd SM8250_CX>; 1641 operating-points-v2 = <&qup_opp_table>; 1642 #address-cells = <1>; 1643 #size-cells = <0>; 1644 status = "disabled"; 1645 }; 1646 1647 i2c10: i2c@a88000 { 1648 compatible = "qcom,geni-i2c"; 1649 reg = <0 0x00a88000 0 0x4000>; 1650 clock-names = "se"; 1651 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1652 pinctrl-names = "default"; 1653 pinctrl-0 = <&qup_i2c10_default>; 1654 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1655 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1656 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1657 dma-names = "tx", "rx"; 1658 #address-cells = <1>; 1659 #size-cells = <0>; 1660 status = "disabled"; 1661 }; 1662 1663 spi10: spi@a88000 { 1664 compatible = "qcom,geni-spi"; 1665 reg = <0 0x00a88000 0 0x4000>; 1666 clock-names = "se"; 1667 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1668 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1669 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1670 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1671 dma-names = "tx", "rx"; 1672 power-domains = <&rpmhpd SM8250_CX>; 1673 operating-points-v2 = <&qup_opp_table>; 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 status = "disabled"; 1677 }; 1678 1679 i2c11: i2c@a8c000 { 1680 compatible = "qcom,geni-i2c"; 1681 reg = <0 0x00a8c000 0 0x4000>; 1682 clock-names = "se"; 1683 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1684 pinctrl-names = "default"; 1685 pinctrl-0 = <&qup_i2c11_default>; 1686 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1687 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1688 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1689 dma-names = "tx", "rx"; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 status = "disabled"; 1693 }; 1694 1695 spi11: spi@a8c000 { 1696 compatible = "qcom,geni-spi"; 1697 reg = <0 0x00a8c000 0 0x4000>; 1698 clock-names = "se"; 1699 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1700 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1701 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1702 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1703 dma-names = "tx", "rx"; 1704 power-domains = <&rpmhpd SM8250_CX>; 1705 operating-points-v2 = <&qup_opp_table>; 1706 #address-cells = <1>; 1707 #size-cells = <0>; 1708 status = "disabled"; 1709 }; 1710 1711 i2c12: i2c@a90000 { 1712 compatible = "qcom,geni-i2c"; 1713 reg = <0 0x00a90000 0 0x4000>; 1714 clock-names = "se"; 1715 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1716 pinctrl-names = "default"; 1717 pinctrl-0 = <&qup_i2c12_default>; 1718 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1719 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1720 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1721 dma-names = "tx", "rx"; 1722 #address-cells = <1>; 1723 #size-cells = <0>; 1724 status = "disabled"; 1725 }; 1726 1727 spi12: spi@a90000 { 1728 compatible = "qcom,geni-spi"; 1729 reg = <0 0x00a90000 0 0x4000>; 1730 clock-names = "se"; 1731 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1732 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1733 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1734 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1735 dma-names = "tx", "rx"; 1736 power-domains = <&rpmhpd SM8250_CX>; 1737 operating-points-v2 = <&qup_opp_table>; 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 status = "disabled"; 1741 }; 1742 1743 uart12: serial@a90000 { 1744 compatible = "qcom,geni-debug-uart"; 1745 reg = <0x0 0x00a90000 0x0 0x4000>; 1746 clock-names = "se"; 1747 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1748 pinctrl-names = "default"; 1749 pinctrl-0 = <&qup_uart12_default>; 1750 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1751 power-domains = <&rpmhpd SM8250_CX>; 1752 operating-points-v2 = <&qup_opp_table>; 1753 status = "disabled"; 1754 }; 1755 1756 i2c13: i2c@a94000 { 1757 compatible = "qcom,geni-i2c"; 1758 reg = <0 0x00a94000 0 0x4000>; 1759 clock-names = "se"; 1760 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1761 pinctrl-names = "default"; 1762 pinctrl-0 = <&qup_i2c13_default>; 1763 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1764 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1765 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1766 dma-names = "tx", "rx"; 1767 #address-cells = <1>; 1768 #size-cells = <0>; 1769 status = "disabled"; 1770 }; 1771 1772 spi13: spi@a94000 { 1773 compatible = "qcom,geni-spi"; 1774 reg = <0 0x00a94000 0 0x4000>; 1775 clock-names = "se"; 1776 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1777 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1778 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1779 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1780 dma-names = "tx", "rx"; 1781 power-domains = <&rpmhpd SM8250_CX>; 1782 operating-points-v2 = <&qup_opp_table>; 1783 #address-cells = <1>; 1784 #size-cells = <0>; 1785 status = "disabled"; 1786 }; 1787 }; 1788 1789 config_noc: interconnect@1500000 { 1790 compatible = "qcom,sm8250-config-noc"; 1791 reg = <0 0x01500000 0 0xa580>; 1792 #interconnect-cells = <1>; 1793 qcom,bcm-voters = <&apps_bcm_voter>; 1794 }; 1795 1796 system_noc: interconnect@1620000 { 1797 compatible = "qcom,sm8250-system-noc"; 1798 reg = <0 0x01620000 0 0x1c200>; 1799 #interconnect-cells = <1>; 1800 qcom,bcm-voters = <&apps_bcm_voter>; 1801 }; 1802 1803 mc_virt: interconnect@163d000 { 1804 compatible = "qcom,sm8250-mc-virt"; 1805 reg = <0 0x0163d000 0 0x1000>; 1806 #interconnect-cells = <1>; 1807 qcom,bcm-voters = <&apps_bcm_voter>; 1808 }; 1809 1810 aggre1_noc: interconnect@16e0000 { 1811 compatible = "qcom,sm8250-aggre1-noc"; 1812 reg = <0 0x016e0000 0 0x1f180>; 1813 #interconnect-cells = <1>; 1814 qcom,bcm-voters = <&apps_bcm_voter>; 1815 }; 1816 1817 aggre2_noc: interconnect@1700000 { 1818 compatible = "qcom,sm8250-aggre2-noc"; 1819 reg = <0 0x01700000 0 0x33000>; 1820 #interconnect-cells = <1>; 1821 qcom,bcm-voters = <&apps_bcm_voter>; 1822 }; 1823 1824 compute_noc: interconnect@1733000 { 1825 compatible = "qcom,sm8250-compute-noc"; 1826 reg = <0 0x01733000 0 0xa180>; 1827 #interconnect-cells = <1>; 1828 qcom,bcm-voters = <&apps_bcm_voter>; 1829 }; 1830 1831 mmss_noc: interconnect@1740000 { 1832 compatible = "qcom,sm8250-mmss-noc"; 1833 reg = <0 0x01740000 0 0x1f080>; 1834 #interconnect-cells = <1>; 1835 qcom,bcm-voters = <&apps_bcm_voter>; 1836 }; 1837 1838 pcie0: pci@1c00000 { 1839 compatible = "qcom,pcie-sm8250"; 1840 reg = <0 0x01c00000 0 0x3000>, 1841 <0 0x60000000 0 0xf1d>, 1842 <0 0x60000f20 0 0xa8>, 1843 <0 0x60001000 0 0x1000>, 1844 <0 0x60100000 0 0x100000>, 1845 <0 0x01c03000 0 0x1000>; 1846 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1847 device_type = "pci"; 1848 linux,pci-domain = <0>; 1849 bus-range = <0x00 0xff>; 1850 num-lanes = <1>; 1851 1852 #address-cells = <3>; 1853 #size-cells = <2>; 1854 1855 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1856 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1857 1858 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1866 interrupt-names = "msi0", "msi1", "msi2", "msi3", 1867 "msi4", "msi5", "msi6", "msi7"; 1868 #interrupt-cells = <1>; 1869 interrupt-map-mask = <0 0 0 0x7>; 1870 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1871 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1872 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1873 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1874 1875 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1876 <&gcc GCC_PCIE_0_AUX_CLK>, 1877 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1878 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1879 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1880 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1881 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1882 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1883 clock-names = "pipe", 1884 "aux", 1885 "cfg", 1886 "bus_master", 1887 "bus_slave", 1888 "slave_q2a", 1889 "tbu", 1890 "ddrss_sf_tbu"; 1891 1892 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1893 <0x100 &apps_smmu 0x1c01 0x1>; 1894 1895 resets = <&gcc GCC_PCIE_0_BCR>; 1896 reset-names = "pci"; 1897 1898 power-domains = <&gcc PCIE_0_GDSC>; 1899 1900 phys = <&pcie0_lane>; 1901 phy-names = "pciephy"; 1902 1903 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; 1904 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 1905 1906 pinctrl-names = "default"; 1907 pinctrl-0 = <&pcie0_default_state>; 1908 1909 status = "disabled"; 1910 }; 1911 1912 pcie0_phy: phy@1c06000 { 1913 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1914 reg = <0 0x01c06000 0 0x1c0>; 1915 #address-cells = <2>; 1916 #size-cells = <2>; 1917 ranges; 1918 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1919 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1920 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1921 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1922 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1923 1924 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1925 reset-names = "phy"; 1926 1927 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1928 assigned-clock-rates = <100000000>; 1929 1930 status = "disabled"; 1931 1932 pcie0_lane: phy@1c06200 { 1933 reg = <0 0x01c06200 0 0x170>, /* tx */ 1934 <0 0x01c06400 0 0x200>, /* rx */ 1935 <0 0x01c06800 0 0x1f0>, /* pcs */ 1936 <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1937 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1938 clock-names = "pipe0"; 1939 1940 #phy-cells = <0>; 1941 1942 #clock-cells = <0>; 1943 clock-output-names = "pcie_0_pipe_clk"; 1944 }; 1945 }; 1946 1947 pcie1: pci@1c08000 { 1948 compatible = "qcom,pcie-sm8250"; 1949 reg = <0 0x01c08000 0 0x3000>, 1950 <0 0x40000000 0 0xf1d>, 1951 <0 0x40000f20 0 0xa8>, 1952 <0 0x40001000 0 0x1000>, 1953 <0 0x40100000 0 0x100000>, 1954 <0 0x01c0b000 0 0x1000>; 1955 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1956 device_type = "pci"; 1957 linux,pci-domain = <1>; 1958 bus-range = <0x00 0xff>; 1959 num-lanes = <2>; 1960 1961 #address-cells = <3>; 1962 #size-cells = <2>; 1963 1964 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1965 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1966 1967 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1968 interrupt-names = "msi"; 1969 #interrupt-cells = <1>; 1970 interrupt-map-mask = <0 0 0 0x7>; 1971 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1972 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1973 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1974 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1975 1976 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1977 <&gcc GCC_PCIE_1_AUX_CLK>, 1978 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1979 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1980 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1981 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1982 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1983 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1984 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1985 clock-names = "pipe", 1986 "aux", 1987 "cfg", 1988 "bus_master", 1989 "bus_slave", 1990 "slave_q2a", 1991 "ref", 1992 "tbu", 1993 "ddrss_sf_tbu"; 1994 1995 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1996 assigned-clock-rates = <19200000>; 1997 1998 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1999 <0x100 &apps_smmu 0x1c81 0x1>; 2000 2001 resets = <&gcc GCC_PCIE_1_BCR>; 2002 reset-names = "pci"; 2003 2004 power-domains = <&gcc PCIE_1_GDSC>; 2005 2006 phys = <&pcie1_lane>; 2007 phy-names = "pciephy"; 2008 2009 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; 2010 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; 2011 2012 pinctrl-names = "default"; 2013 pinctrl-0 = <&pcie1_default_state>; 2014 2015 status = "disabled"; 2016 }; 2017 2018 pcie1_phy: phy@1c0e000 { 2019 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2020 reg = <0 0x01c0e000 0 0x1c0>; 2021 #address-cells = <2>; 2022 #size-cells = <2>; 2023 ranges; 2024 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2025 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2026 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 2027 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2028 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2029 2030 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2031 reset-names = "phy"; 2032 2033 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2034 assigned-clock-rates = <100000000>; 2035 2036 status = "disabled"; 2037 2038 pcie1_lane: phy@1c0e200 { 2039 reg = <0 0x01c0e200 0 0x170>, /* tx0 */ 2040 <0 0x01c0e400 0 0x200>, /* rx0 */ 2041 <0 0x01c0ea00 0 0x1f0>, /* pcs */ 2042 <0 0x01c0e600 0 0x170>, /* tx1 */ 2043 <0 0x01c0e800 0 0x200>, /* rx1 */ 2044 <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2045 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2046 clock-names = "pipe0"; 2047 2048 #phy-cells = <0>; 2049 2050 #clock-cells = <0>; 2051 clock-output-names = "pcie_1_pipe_clk"; 2052 }; 2053 }; 2054 2055 pcie2: pci@1c10000 { 2056 compatible = "qcom,pcie-sm8250"; 2057 reg = <0 0x01c10000 0 0x3000>, 2058 <0 0x64000000 0 0xf1d>, 2059 <0 0x64000f20 0 0xa8>, 2060 <0 0x64001000 0 0x1000>, 2061 <0 0x64100000 0 0x100000>, 2062 <0 0x01c13000 0 0x1000>; 2063 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2064 device_type = "pci"; 2065 linux,pci-domain = <2>; 2066 bus-range = <0x00 0xff>; 2067 num-lanes = <2>; 2068 2069 #address-cells = <3>; 2070 #size-cells = <2>; 2071 2072 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>, 2073 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 2074 2075 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2076 interrupt-names = "msi"; 2077 #interrupt-cells = <1>; 2078 interrupt-map-mask = <0 0 0 0x7>; 2079 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2080 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2081 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2082 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2083 2084 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2085 <&gcc GCC_PCIE_2_AUX_CLK>, 2086 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2087 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2088 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2089 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2090 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2091 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2092 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2093 clock-names = "pipe", 2094 "aux", 2095 "cfg", 2096 "bus_master", 2097 "bus_slave", 2098 "slave_q2a", 2099 "ref", 2100 "tbu", 2101 "ddrss_sf_tbu"; 2102 2103 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2104 assigned-clock-rates = <19200000>; 2105 2106 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2107 <0x100 &apps_smmu 0x1d01 0x1>; 2108 2109 resets = <&gcc GCC_PCIE_2_BCR>; 2110 reset-names = "pci"; 2111 2112 power-domains = <&gcc PCIE_2_GDSC>; 2113 2114 phys = <&pcie2_lane>; 2115 phy-names = "pciephy"; 2116 2117 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; 2118 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 2119 2120 pinctrl-names = "default"; 2121 pinctrl-0 = <&pcie2_default_state>; 2122 2123 status = "disabled"; 2124 }; 2125 2126 pcie2_phy: phy@1c16000 { 2127 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 2128 reg = <0 0x01c16000 0 0x1c0>; 2129 #address-cells = <2>; 2130 #size-cells = <2>; 2131 ranges; 2132 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2133 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2134 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2135 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2136 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2137 2138 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2139 reset-names = "phy"; 2140 2141 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2142 assigned-clock-rates = <100000000>; 2143 2144 status = "disabled"; 2145 2146 pcie2_lane: phy@1c16200 { 2147 reg = <0 0x01c16200 0 0x170>, /* tx0 */ 2148 <0 0x01c16400 0 0x200>, /* rx0 */ 2149 <0 0x01c16a00 0 0x1f0>, /* pcs */ 2150 <0 0x01c16600 0 0x170>, /* tx1 */ 2151 <0 0x01c16800 0 0x200>, /* rx1 */ 2152 <0 0x01c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2153 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 2154 clock-names = "pipe0"; 2155 2156 #phy-cells = <0>; 2157 2158 #clock-cells = <0>; 2159 clock-output-names = "pcie_2_pipe_clk"; 2160 }; 2161 }; 2162 2163 ufs_mem_hc: ufshc@1d84000 { 2164 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 2165 "jedec,ufs-2.0"; 2166 reg = <0 0x01d84000 0 0x3000>; 2167 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2168 phys = <&ufs_mem_phy_lanes>; 2169 phy-names = "ufsphy"; 2170 lanes-per-direction = <2>; 2171 #reset-cells = <1>; 2172 resets = <&gcc GCC_UFS_PHY_BCR>; 2173 reset-names = "rst"; 2174 2175 power-domains = <&gcc UFS_PHY_GDSC>; 2176 2177 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 2178 2179 clock-names = 2180 "core_clk", 2181 "bus_aggr_clk", 2182 "iface_clk", 2183 "core_clk_unipro", 2184 "ref_clk", 2185 "tx_lane0_sync_clk", 2186 "rx_lane0_sync_clk", 2187 "rx_lane1_sync_clk"; 2188 clocks = 2189 <&gcc GCC_UFS_PHY_AXI_CLK>, 2190 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2191 <&gcc GCC_UFS_PHY_AHB_CLK>, 2192 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2193 <&rpmhcc RPMH_CXO_CLK>, 2194 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2195 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2196 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2197 freq-table-hz = 2198 <37500000 300000000>, 2199 <0 0>, 2200 <0 0>, 2201 <37500000 300000000>, 2202 <0 0>, 2203 <0 0>, 2204 <0 0>, 2205 <0 0>; 2206 2207 status = "disabled"; 2208 }; 2209 2210 ufs_mem_phy: phy@1d87000 { 2211 compatible = "qcom,sm8250-qmp-ufs-phy"; 2212 reg = <0 0x01d87000 0 0x1c0>; 2213 #address-cells = <2>; 2214 #size-cells = <2>; 2215 ranges; 2216 clock-names = "ref", 2217 "ref_aux"; 2218 clocks = <&rpmhcc RPMH_CXO_CLK>, 2219 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2220 2221 resets = <&ufs_mem_hc 0>; 2222 reset-names = "ufsphy"; 2223 status = "disabled"; 2224 2225 ufs_mem_phy_lanes: phy@1d87400 { 2226 reg = <0 0x01d87400 0 0x16c>, 2227 <0 0x01d87600 0 0x200>, 2228 <0 0x01d87c00 0 0x200>, 2229 <0 0x01d87800 0 0x16c>, 2230 <0 0x01d87a00 0 0x200>; 2231 #phy-cells = <0>; 2232 }; 2233 }; 2234 2235 cryptobam: dma-controller@1dc4000 { 2236 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2237 reg = <0 0x01dc4000 0 0x24000>; 2238 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2239 #dma-cells = <1>; 2240 qcom,ee = <0>; 2241 qcom,controlled-remotely; 2242 num-channels = <8>; 2243 qcom,num-ees = <2>; 2244 iommus = <&apps_smmu 0x592 0x0000>, 2245 <&apps_smmu 0x598 0x0000>, 2246 <&apps_smmu 0x599 0x0000>, 2247 <&apps_smmu 0x59f 0x0000>, 2248 <&apps_smmu 0x586 0x0011>, 2249 <&apps_smmu 0x596 0x0011>; 2250 }; 2251 2252 crypto: crypto@1dfa000 { 2253 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce"; 2254 reg = <0 0x01dfa000 0 0x6000>; 2255 dmas = <&cryptobam 4>, <&cryptobam 5>; 2256 dma-names = "rx", "tx"; 2257 iommus = <&apps_smmu 0x592 0x0000>, 2258 <&apps_smmu 0x598 0x0000>, 2259 <&apps_smmu 0x599 0x0000>, 2260 <&apps_smmu 0x59f 0x0000>, 2261 <&apps_smmu 0x586 0x0011>, 2262 <&apps_smmu 0x596 0x0011>; 2263 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; 2264 interconnect-names = "memory"; 2265 }; 2266 2267 tcsr_mutex: hwlock@1f40000 { 2268 compatible = "qcom,tcsr-mutex"; 2269 reg = <0x0 0x01f40000 0x0 0x40000>; 2270 #hwlock-cells = <1>; 2271 }; 2272 2273 wsamacro: codec@3240000 { 2274 compatible = "qcom,sm8250-lpass-wsa-macro"; 2275 reg = <0 0x03240000 0 0x1000>; 2276 clocks = <&audiocc LPASS_CDC_WSA_MCLK>, 2277 <&audiocc LPASS_CDC_WSA_NPL>, 2278 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2279 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2280 <&aoncc LPASS_CDC_VA_MCLK>, 2281 <&vamacro>; 2282 2283 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 2284 2285 #clock-cells = <0>; 2286 clock-output-names = "mclk"; 2287 #sound-dai-cells = <1>; 2288 2289 pinctrl-names = "default"; 2290 pinctrl-0 = <&wsa_swr_active>; 2291 2292 status = "disabled"; 2293 }; 2294 2295 swr0: soundwire-controller@3250000 { 2296 reg = <0 0x03250000 0 0x2000>; 2297 compatible = "qcom,soundwire-v1.5.1"; 2298 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 2299 clocks = <&wsamacro>; 2300 clock-names = "iface"; 2301 2302 qcom,din-ports = <2>; 2303 qcom,dout-ports = <6>; 2304 2305 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2306 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2307 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2308 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 2309 2310 #sound-dai-cells = <1>; 2311 #address-cells = <2>; 2312 #size-cells = <0>; 2313 2314 status = "disabled"; 2315 }; 2316 2317 audiocc: clock-controller@3300000 { 2318 compatible = "qcom,sm8250-lpass-audiocc"; 2319 reg = <0 0x03300000 0 0x30000>; 2320 #clock-cells = <1>; 2321 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2322 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2323 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2324 clock-names = "core", "audio", "bus"; 2325 }; 2326 2327 vamacro: codec@3370000 { 2328 compatible = "qcom,sm8250-lpass-va-macro"; 2329 reg = <0 0x03370000 0 0x1000>; 2330 clocks = <&aoncc LPASS_CDC_VA_MCLK>, 2331 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2332 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2333 2334 clock-names = "mclk", "macro", "dcodec"; 2335 2336 #clock-cells = <0>; 2337 clock-output-names = "fsgen"; 2338 #sound-dai-cells = <1>; 2339 }; 2340 2341 rxmacro: rxmacro@3200000 { 2342 pinctrl-names = "default"; 2343 pinctrl-0 = <&rx_swr_active>; 2344 compatible = "qcom,sm8250-lpass-rx-macro"; 2345 reg = <0 0x03200000 0 0x1000>; 2346 status = "disabled"; 2347 2348 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2349 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2350 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2351 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2352 <&vamacro>; 2353 2354 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2355 2356 #clock-cells = <0>; 2357 clock-output-names = "mclk"; 2358 #sound-dai-cells = <1>; 2359 }; 2360 2361 swr1: soundwire-controller@3210000 { 2362 reg = <0 0x03210000 0 0x2000>; 2363 compatible = "qcom,soundwire-v1.5.1"; 2364 status = "disabled"; 2365 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2366 clocks = <&rxmacro>; 2367 clock-names = "iface"; 2368 label = "RX"; 2369 qcom,din-ports = <0>; 2370 qcom,dout-ports = <5>; 2371 2372 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2373 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2374 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2375 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2376 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2377 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2378 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2379 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2380 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2381 2382 #sound-dai-cells = <1>; 2383 #address-cells = <2>; 2384 #size-cells = <0>; 2385 }; 2386 2387 txmacro: txmacro@3220000 { 2388 pinctrl-names = "default"; 2389 pinctrl-0 = <&tx_swr_active>; 2390 compatible = "qcom,sm8250-lpass-tx-macro"; 2391 reg = <0 0x03220000 0 0x1000>; 2392 status = "disabled"; 2393 2394 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2395 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2396 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2397 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2398 <&vamacro>; 2399 2400 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2401 2402 #clock-cells = <0>; 2403 clock-output-names = "mclk"; 2404 #sound-dai-cells = <1>; 2405 }; 2406 2407 /* tx macro */ 2408 swr2: soundwire-controller@3230000 { 2409 reg = <0 0x03230000 0 0x2000>; 2410 compatible = "qcom,soundwire-v1.5.1"; 2411 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 2412 interrupt-names = "core"; 2413 status = "disabled"; 2414 2415 clocks = <&txmacro>; 2416 clock-names = "iface"; 2417 label = "TX"; 2418 2419 qcom,din-ports = <5>; 2420 qcom,dout-ports = <0>; 2421 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>; 2422 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>; 2423 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>; 2424 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2425 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2426 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2427 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2428 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2429 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>; 2430 #sound-dai-cells = <1>; 2431 #address-cells = <2>; 2432 #size-cells = <0>; 2433 }; 2434 2435 aoncc: clock-controller@3380000 { 2436 compatible = "qcom,sm8250-lpass-aoncc"; 2437 reg = <0 0x03380000 0 0x40000>; 2438 #clock-cells = <1>; 2439 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2440 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2441 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2442 clock-names = "core", "audio", "bus"; 2443 }; 2444 2445 lpass_tlmm: pinctrl@33c0000 { 2446 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 2447 reg = <0 0x033c0000 0x0 0x20000>, 2448 <0 0x03550000 0x0 0x10000>; 2449 gpio-controller; 2450 #gpio-cells = <2>; 2451 gpio-ranges = <&lpass_tlmm 0 0 14>; 2452 2453 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2454 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2455 clock-names = "core", "audio"; 2456 2457 wsa_swr_active: wsa-swr-active-state { 2458 clk-pins { 2459 pins = "gpio10"; 2460 function = "wsa_swr_clk"; 2461 drive-strength = <2>; 2462 slew-rate = <1>; 2463 bias-disable; 2464 }; 2465 2466 data-pins { 2467 pins = "gpio11"; 2468 function = "wsa_swr_data"; 2469 drive-strength = <2>; 2470 slew-rate = <1>; 2471 bias-bus-hold; 2472 }; 2473 }; 2474 2475 wsa_swr_sleep: wsa-swr-sleep-state { 2476 clk-pins { 2477 pins = "gpio10"; 2478 function = "wsa_swr_clk"; 2479 drive-strength = <2>; 2480 bias-pull-down; 2481 }; 2482 2483 data-pins { 2484 pins = "gpio11"; 2485 function = "wsa_swr_data"; 2486 drive-strength = <2>; 2487 bias-pull-down; 2488 }; 2489 }; 2490 2491 dmic01_active: dmic01-active-state { 2492 clk-pins { 2493 pins = "gpio6"; 2494 function = "dmic1_clk"; 2495 drive-strength = <8>; 2496 output-high; 2497 }; 2498 data-pins { 2499 pins = "gpio7"; 2500 function = "dmic1_data"; 2501 drive-strength = <8>; 2502 }; 2503 }; 2504 2505 dmic01_sleep: dmic01-sleep-state { 2506 clk-pins { 2507 pins = "gpio6"; 2508 function = "dmic1_clk"; 2509 drive-strength = <2>; 2510 bias-disable; 2511 output-low; 2512 }; 2513 2514 data-pins { 2515 pins = "gpio7"; 2516 function = "dmic1_data"; 2517 drive-strength = <2>; 2518 bias-pull-down; 2519 }; 2520 }; 2521 2522 rx_swr_active: rx-swr-active-state { 2523 clk-pins { 2524 pins = "gpio3"; 2525 function = "swr_rx_clk"; 2526 drive-strength = <2>; 2527 slew-rate = <1>; 2528 bias-disable; 2529 }; 2530 2531 data-pins { 2532 pins = "gpio4", "gpio5"; 2533 function = "swr_rx_data"; 2534 drive-strength = <2>; 2535 slew-rate = <1>; 2536 bias-bus-hold; 2537 }; 2538 }; 2539 2540 tx_swr_active: tx-swr-active-state { 2541 clk-pins { 2542 pins = "gpio0"; 2543 function = "swr_tx_clk"; 2544 drive-strength = <2>; 2545 slew-rate = <1>; 2546 bias-disable; 2547 }; 2548 2549 data-pins { 2550 pins = "gpio1", "gpio2"; 2551 function = "swr_tx_data"; 2552 drive-strength = <2>; 2553 slew-rate = <1>; 2554 bias-bus-hold; 2555 }; 2556 }; 2557 2558 tx_swr_sleep: tx-swr-sleep-state { 2559 clk-pins { 2560 pins = "gpio0"; 2561 function = "swr_tx_clk"; 2562 drive-strength = <2>; 2563 bias-pull-down; 2564 }; 2565 2566 data1-pins { 2567 pins = "gpio1"; 2568 function = "swr_tx_data"; 2569 drive-strength = <2>; 2570 bias-bus-hold; 2571 }; 2572 2573 data2-pins { 2574 pins = "gpio2"; 2575 function = "swr_tx_data"; 2576 drive-strength = <2>; 2577 bias-pull-down; 2578 }; 2579 }; 2580 }; 2581 2582 gpu: gpu@3d00000 { 2583 compatible = "qcom,adreno-650.2", 2584 "qcom,adreno"; 2585 2586 reg = <0 0x03d00000 0 0x40000>; 2587 reg-names = "kgsl_3d0_reg_memory"; 2588 2589 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2590 2591 iommus = <&adreno_smmu 0 0x401>; 2592 2593 operating-points-v2 = <&gpu_opp_table>; 2594 2595 qcom,gmu = <&gmu>; 2596 2597 nvmem-cells = <&gpu_speed_bin>; 2598 nvmem-cell-names = "speed_bin"; 2599 2600 status = "disabled"; 2601 2602 zap-shader { 2603 memory-region = <&gpu_mem>; 2604 }; 2605 2606 gpu_opp_table: opp-table { 2607 compatible = "operating-points-v2"; 2608 2609 opp-670000000 { 2610 opp-hz = /bits/ 64 <670000000>; 2611 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2612 opp-supported-hw = <0xa>; 2613 }; 2614 2615 opp-587000000 { 2616 opp-hz = /bits/ 64 <587000000>; 2617 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2618 opp-supported-hw = <0xb>; 2619 }; 2620 2621 opp-525000000 { 2622 opp-hz = /bits/ 64 <525000000>; 2623 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2624 opp-supported-hw = <0xf>; 2625 }; 2626 2627 opp-490000000 { 2628 opp-hz = /bits/ 64 <490000000>; 2629 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2630 opp-supported-hw = <0xf>; 2631 }; 2632 2633 opp-441600000 { 2634 opp-hz = /bits/ 64 <441600000>; 2635 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2636 opp-supported-hw = <0xf>; 2637 }; 2638 2639 opp-400000000 { 2640 opp-hz = /bits/ 64 <400000000>; 2641 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2642 opp-supported-hw = <0xf>; 2643 }; 2644 2645 opp-305000000 { 2646 opp-hz = /bits/ 64 <305000000>; 2647 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2648 opp-supported-hw = <0xf>; 2649 }; 2650 }; 2651 }; 2652 2653 gmu: gmu@3d6a000 { 2654 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2655 2656 reg = <0 0x03d6a000 0 0x30000>, 2657 <0 0x3de0000 0 0x10000>, 2658 <0 0xb290000 0 0x10000>, 2659 <0 0xb490000 0 0x10000>; 2660 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 2661 2662 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2663 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2664 interrupt-names = "hfi", "gmu"; 2665 2666 clocks = <&gpucc GPU_CC_AHB_CLK>, 2667 <&gpucc GPU_CC_CX_GMU_CLK>, 2668 <&gpucc GPU_CC_CXO_CLK>, 2669 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2670 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2671 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2672 2673 power-domains = <&gpucc GPU_CX_GDSC>, 2674 <&gpucc GPU_GX_GDSC>; 2675 power-domain-names = "cx", "gx"; 2676 2677 iommus = <&adreno_smmu 5 0x400>; 2678 2679 operating-points-v2 = <&gmu_opp_table>; 2680 2681 status = "disabled"; 2682 2683 gmu_opp_table: opp-table { 2684 compatible = "operating-points-v2"; 2685 2686 opp-200000000 { 2687 opp-hz = /bits/ 64 <200000000>; 2688 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2689 }; 2690 }; 2691 }; 2692 2693 gpucc: clock-controller@3d90000 { 2694 compatible = "qcom,sm8250-gpucc"; 2695 reg = <0 0x03d90000 0 0x9000>; 2696 clocks = <&rpmhcc RPMH_CXO_CLK>, 2697 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2698 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2699 clock-names = "bi_tcxo", 2700 "gcc_gpu_gpll0_clk_src", 2701 "gcc_gpu_gpll0_div_clk_src"; 2702 #clock-cells = <1>; 2703 #reset-cells = <1>; 2704 #power-domain-cells = <1>; 2705 }; 2706 2707 adreno_smmu: iommu@3da0000 { 2708 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", 2709 "qcom,smmu-500", "arm,mmu-500"; 2710 reg = <0 0x03da0000 0 0x10000>; 2711 #iommu-cells = <2>; 2712 #global-interrupts = <2>; 2713 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2714 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2715 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2716 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2717 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2718 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2719 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2720 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2721 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2722 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 2723 clocks = <&gpucc GPU_CC_AHB_CLK>, 2724 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2725 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2726 clock-names = "ahb", "bus", "iface"; 2727 2728 power-domains = <&gpucc GPU_CX_GDSC>; 2729 }; 2730 2731 slpi: remoteproc@5c00000 { 2732 compatible = "qcom,sm8250-slpi-pas"; 2733 reg = <0 0x05c00000 0 0x4000>; 2734 2735 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2736 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2737 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2738 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2739 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2740 interrupt-names = "wdog", "fatal", "ready", 2741 "handover", "stop-ack"; 2742 2743 clocks = <&rpmhcc RPMH_CXO_CLK>; 2744 clock-names = "xo"; 2745 2746 power-domains = <&rpmhpd SM8250_LCX>, 2747 <&rpmhpd SM8250_LMX>; 2748 power-domain-names = "lcx", "lmx"; 2749 2750 memory-region = <&slpi_mem>; 2751 2752 qcom,qmp = <&aoss_qmp>; 2753 2754 qcom,smem-states = <&smp2p_slpi_out 0>; 2755 qcom,smem-state-names = "stop"; 2756 2757 status = "disabled"; 2758 2759 glink-edge { 2760 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2761 IPCC_MPROC_SIGNAL_GLINK_QMP 2762 IRQ_TYPE_EDGE_RISING>; 2763 mboxes = <&ipcc IPCC_CLIENT_SLPI 2764 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2765 2766 label = "slpi"; 2767 qcom,remote-pid = <3>; 2768 2769 fastrpc { 2770 compatible = "qcom,fastrpc"; 2771 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2772 label = "sdsp"; 2773 qcom,non-secure-domain; 2774 #address-cells = <1>; 2775 #size-cells = <0>; 2776 2777 compute-cb@1 { 2778 compatible = "qcom,fastrpc-compute-cb"; 2779 reg = <1>; 2780 iommus = <&apps_smmu 0x0541 0x0>; 2781 }; 2782 2783 compute-cb@2 { 2784 compatible = "qcom,fastrpc-compute-cb"; 2785 reg = <2>; 2786 iommus = <&apps_smmu 0x0542 0x0>; 2787 }; 2788 2789 compute-cb@3 { 2790 compatible = "qcom,fastrpc-compute-cb"; 2791 reg = <3>; 2792 iommus = <&apps_smmu 0x0543 0x0>; 2793 /* note: shared-cb = <4> in downstream */ 2794 }; 2795 }; 2796 }; 2797 }; 2798 2799 stm@6002000 { 2800 compatible = "arm,coresight-stm", "arm,primecell"; 2801 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>; 2802 reg-names = "stm-base", "stm-stimulus-base"; 2803 2804 clocks = <&aoss_qmp>; 2805 clock-names = "apb_pclk"; 2806 2807 out-ports { 2808 port { 2809 stm_out: endpoint { 2810 remote-endpoint = <&funnel0_in7>; 2811 }; 2812 }; 2813 }; 2814 }; 2815 2816 tpda@6004000 { 2817 compatible = "qcom,coresight-tpda", "arm,primecell"; 2818 reg = <0 0x06004000 0 0x1000>; 2819 2820 clocks = <&aoss_qmp>; 2821 clock-names = "apb_pclk"; 2822 2823 out-ports { 2824 #address-cells = <1>; 2825 #size-cells = <0>; 2826 2827 port@0 { 2828 reg = <0>; 2829 tpda_out_funnel_qatb: endpoint { 2830 remote-endpoint = <&funnel_qatb_in_tpda>; 2831 }; 2832 }; 2833 }; 2834 2835 in-ports { 2836 #address-cells = <1>; 2837 #size-cells = <0>; 2838 2839 port@9 { 2840 reg = <9>; 2841 tpda_9_in_tpdm_mm: endpoint { 2842 remote-endpoint = <&tpdm_mm_out_tpda9>; 2843 }; 2844 }; 2845 2846 port@17 { 2847 reg = <23>; 2848 tpda_23_in_tpdm_prng: endpoint { 2849 remote-endpoint = <&tpdm_prng_out_tpda_23>; 2850 }; 2851 }; 2852 }; 2853 }; 2854 2855 funnel@6005000 { 2856 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2857 reg = <0 0x06005000 0 0x1000>; 2858 2859 clocks = <&aoss_qmp>; 2860 clock-names = "apb_pclk"; 2861 2862 out-ports { 2863 port { 2864 funnel_qatb_out_funnel_in0: endpoint { 2865 remote-endpoint = <&funnel_in0_in_funnel_qatb>; 2866 }; 2867 }; 2868 }; 2869 2870 in-ports { 2871 #address-cells = <1>; 2872 #size-cells = <0>; 2873 2874 port@0 { 2875 reg = <0>; 2876 funnel_qatb_in_tpda: endpoint { 2877 remote-endpoint = <&tpda_out_funnel_qatb>; 2878 }; 2879 }; 2880 }; 2881 }; 2882 2883 funnel@6041000 { 2884 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2885 reg = <0 0x06041000 0 0x1000>; 2886 2887 clocks = <&aoss_qmp>; 2888 clock-names = "apb_pclk"; 2889 2890 out-ports { 2891 port { 2892 funnel_in0_out_funnel_merg: endpoint { 2893 remote-endpoint = <&funnel_merg_in_funnel_in0>; 2894 }; 2895 }; 2896 }; 2897 2898 in-ports { 2899 #address-cells = <1>; 2900 #size-cells = <0>; 2901 2902 port@6 { 2903 reg = <6>; 2904 funnel_in0_in_funnel_qatb: endpoint { 2905 remote-endpoint = <&funnel_qatb_out_funnel_in0>; 2906 }; 2907 }; 2908 2909 port@7 { 2910 reg = <7>; 2911 funnel0_in7: endpoint { 2912 remote-endpoint = <&stm_out>; 2913 }; 2914 }; 2915 }; 2916 }; 2917 2918 funnel@6042000 { 2919 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2920 reg = <0 0x06042000 0 0x1000>; 2921 2922 clocks = <&aoss_qmp>; 2923 clock-names = "apb_pclk"; 2924 2925 out-ports { 2926 port { 2927 funnel_in1_out_funnel_merg: endpoint { 2928 remote-endpoint = <&funnel_merg_in_funnel_in1>; 2929 }; 2930 }; 2931 }; 2932 2933 in-ports { 2934 #address-cells = <1>; 2935 #size-cells = <0>; 2936 2937 port@4 { 2938 reg = <4>; 2939 funnel_in1_in_funnel_apss_merg: endpoint { 2940 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>; 2941 }; 2942 }; 2943 }; 2944 }; 2945 2946 funnel@6045000 { 2947 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2948 reg = <0 0x06045000 0 0x1000>; 2949 2950 clocks = <&aoss_qmp>; 2951 clock-names = "apb_pclk"; 2952 2953 out-ports { 2954 port { 2955 funnel_merg_out_funnel_swao: endpoint { 2956 remote-endpoint = <&funnel_swao_in_funnel_merg>; 2957 }; 2958 }; 2959 }; 2960 2961 in-ports { 2962 #address-cells = <1>; 2963 #size-cells = <0>; 2964 2965 port@0 { 2966 reg = <0>; 2967 funnel_merg_in_funnel_in0: endpoint { 2968 remote-endpoint = <&funnel_in0_out_funnel_merg>; 2969 }; 2970 }; 2971 2972 port@1 { 2973 reg = <1>; 2974 funnel_merg_in_funnel_in1: endpoint { 2975 remote-endpoint = <&funnel_in1_out_funnel_merg>; 2976 }; 2977 }; 2978 }; 2979 }; 2980 2981 replicator@6046000 { 2982 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2983 reg = <0 0x06046000 0 0x1000>; 2984 2985 clocks = <&aoss_qmp>; 2986 clock-names = "apb_pclk"; 2987 2988 out-ports { 2989 port { 2990 replicator_out: endpoint { 2991 remote-endpoint = <&etr_in>; 2992 }; 2993 }; 2994 }; 2995 2996 in-ports { 2997 port { 2998 replicator_cx_in_swao_out: endpoint { 2999 remote-endpoint = <&replicator_swao_out_cx_in>; 3000 }; 3001 }; 3002 }; 3003 }; 3004 3005 etr@6048000 { 3006 compatible = "arm,coresight-tmc", "arm,primecell"; 3007 reg = <0 0x06048000 0 0x1000>; 3008 3009 clocks = <&aoss_qmp>; 3010 clock-names = "apb_pclk"; 3011 arm,scatter-gather; 3012 3013 in-ports { 3014 port { 3015 etr_in: endpoint { 3016 remote-endpoint = <&replicator_out>; 3017 }; 3018 }; 3019 }; 3020 }; 3021 3022 tpdm@684c000 { 3023 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3024 reg = <0 0x0684c000 0 0x1000>; 3025 3026 clocks = <&aoss_qmp>; 3027 clock-names = "apb_pclk"; 3028 3029 out-ports { 3030 port { 3031 tpdm_prng_out_tpda_23: endpoint { 3032 remote-endpoint = <&tpda_23_in_tpdm_prng>; 3033 }; 3034 }; 3035 }; 3036 }; 3037 3038 funnel@6b04000 { 3039 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3040 arm,primecell-periphid = <0x000bb908>; 3041 3042 reg = <0 0x06b04000 0 0x1000>; 3043 3044 clocks = <&aoss_qmp>; 3045 clock-names = "apb_pclk"; 3046 3047 out-ports { 3048 port { 3049 funnel_swao_out_etf: endpoint { 3050 remote-endpoint = <&etf_in_funnel_swao_out>; 3051 }; 3052 }; 3053 }; 3054 3055 in-ports { 3056 #address-cells = <1>; 3057 #size-cells = <0>; 3058 3059 port@7 { 3060 reg = <7>; 3061 funnel_swao_in_funnel_merg: endpoint { 3062 remote-endpoint= <&funnel_merg_out_funnel_swao>; 3063 }; 3064 }; 3065 }; 3066 }; 3067 3068 etf@6b05000 { 3069 compatible = "arm,coresight-tmc", "arm,primecell"; 3070 reg = <0 0x06b05000 0 0x1000>; 3071 3072 clocks = <&aoss_qmp>; 3073 clock-names = "apb_pclk"; 3074 3075 out-ports { 3076 port { 3077 etf_out: endpoint { 3078 remote-endpoint = <&replicator_in>; 3079 }; 3080 }; 3081 }; 3082 3083 in-ports { 3084 #address-cells = <1>; 3085 #size-cells = <0>; 3086 3087 port@0 { 3088 reg = <0>; 3089 etf_in_funnel_swao_out: endpoint { 3090 remote-endpoint = <&funnel_swao_out_etf>; 3091 }; 3092 }; 3093 }; 3094 }; 3095 3096 replicator@6b06000 { 3097 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3098 reg = <0 0x06b06000 0 0x1000>; 3099 3100 clocks = <&aoss_qmp>; 3101 clock-names = "apb_pclk"; 3102 3103 out-ports { 3104 port { 3105 replicator_swao_out_cx_in: endpoint { 3106 remote-endpoint = <&replicator_cx_in_swao_out>; 3107 }; 3108 }; 3109 }; 3110 3111 in-ports { 3112 port { 3113 replicator_in: endpoint { 3114 remote-endpoint = <&etf_out>; 3115 }; 3116 }; 3117 }; 3118 }; 3119 3120 tpdm@6c08000 { 3121 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3122 reg = <0 0x06c08000 0 0x1000>; 3123 3124 clocks = <&aoss_qmp>; 3125 clock-names = "apb_pclk"; 3126 3127 out-ports { 3128 port { 3129 tpdm_mm_out_funnel_dl_mm: endpoint { 3130 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>; 3131 }; 3132 }; 3133 }; 3134 }; 3135 3136 funnel@6c0b000 { 3137 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3138 reg = <0 0x06c0b000 0 0x1000>; 3139 3140 clocks = <&aoss_qmp>; 3141 clock-names = "apb_pclk"; 3142 3143 out-ports { 3144 port { 3145 funnel_dl_mm_out_funnel_dl_center: endpoint { 3146 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>; 3147 }; 3148 }; 3149 }; 3150 3151 in-ports { 3152 #address-cells = <1>; 3153 #size-cells = <0>; 3154 3155 port@3 { 3156 reg = <3>; 3157 funnel_dl_mm_in_tpdm_mm: endpoint { 3158 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>; 3159 }; 3160 }; 3161 }; 3162 }; 3163 3164 funnel@6c2d000 { 3165 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3166 reg = <0 0x06c2d000 0 0x1000>; 3167 3168 clocks = <&aoss_qmp>; 3169 clock-names = "apb_pclk"; 3170 3171 out-ports { 3172 #address-cells = <1>; 3173 #size-cells = <0>; 3174 port { 3175 tpdm_mm_out_tpda9: endpoint { 3176 remote-endpoint = <&tpda_9_in_tpdm_mm>; 3177 }; 3178 }; 3179 }; 3180 3181 in-ports { 3182 #address-cells = <1>; 3183 #size-cells = <0>; 3184 3185 port@2 { 3186 reg = <2>; 3187 funnel_dl_center_in_funnel_dl_mm: endpoint { 3188 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>; 3189 }; 3190 }; 3191 }; 3192 }; 3193 3194 etm@7040000 { 3195 compatible = "arm,coresight-etm4x", "arm,primecell"; 3196 reg = <0 0x07040000 0 0x1000>; 3197 3198 cpu = <&CPU0>; 3199 3200 clocks = <&aoss_qmp>; 3201 clock-names = "apb_pclk"; 3202 arm,coresight-loses-context-with-cpu; 3203 3204 out-ports { 3205 port { 3206 etm0_out: endpoint { 3207 remote-endpoint = <&apss_funnel_in0>; 3208 }; 3209 }; 3210 }; 3211 }; 3212 3213 etm@7140000 { 3214 compatible = "arm,coresight-etm4x", "arm,primecell"; 3215 reg = <0 0x07140000 0 0x1000>; 3216 3217 cpu = <&CPU1>; 3218 3219 clocks = <&aoss_qmp>; 3220 clock-names = "apb_pclk"; 3221 arm,coresight-loses-context-with-cpu; 3222 3223 out-ports { 3224 port { 3225 etm1_out: endpoint { 3226 remote-endpoint = <&apss_funnel_in1>; 3227 }; 3228 }; 3229 }; 3230 }; 3231 3232 etm@7240000 { 3233 compatible = "arm,coresight-etm4x", "arm,primecell"; 3234 reg = <0 0x07240000 0 0x1000>; 3235 3236 cpu = <&CPU2>; 3237 3238 clocks = <&aoss_qmp>; 3239 clock-names = "apb_pclk"; 3240 arm,coresight-loses-context-with-cpu; 3241 3242 out-ports { 3243 port { 3244 etm2_out: endpoint { 3245 remote-endpoint = <&apss_funnel_in2>; 3246 }; 3247 }; 3248 }; 3249 }; 3250 3251 etm@7340000 { 3252 compatible = "arm,coresight-etm4x", "arm,primecell"; 3253 reg = <0 0x07340000 0 0x1000>; 3254 3255 cpu = <&CPU3>; 3256 3257 clocks = <&aoss_qmp>; 3258 clock-names = "apb_pclk"; 3259 arm,coresight-loses-context-with-cpu; 3260 3261 out-ports { 3262 port { 3263 etm3_out: endpoint { 3264 remote-endpoint = <&apss_funnel_in3>; 3265 }; 3266 }; 3267 }; 3268 }; 3269 3270 etm@7440000 { 3271 compatible = "arm,coresight-etm4x", "arm,primecell"; 3272 reg = <0 0x07440000 0 0x1000>; 3273 3274 cpu = <&CPU4>; 3275 3276 clocks = <&aoss_qmp>; 3277 clock-names = "apb_pclk"; 3278 arm,coresight-loses-context-with-cpu; 3279 3280 out-ports { 3281 port { 3282 etm4_out: endpoint { 3283 remote-endpoint = <&apss_funnel_in4>; 3284 }; 3285 }; 3286 }; 3287 }; 3288 3289 etm@7540000 { 3290 compatible = "arm,coresight-etm4x", "arm,primecell"; 3291 reg = <0 0x07540000 0 0x1000>; 3292 3293 cpu = <&CPU5>; 3294 3295 clocks = <&aoss_qmp>; 3296 clock-names = "apb_pclk"; 3297 arm,coresight-loses-context-with-cpu; 3298 3299 out-ports { 3300 port { 3301 etm5_out: endpoint { 3302 remote-endpoint = <&apss_funnel_in5>; 3303 }; 3304 }; 3305 }; 3306 }; 3307 3308 etm@7640000 { 3309 compatible = "arm,coresight-etm4x", "arm,primecell"; 3310 reg = <0 0x07640000 0 0x1000>; 3311 3312 cpu = <&CPU6>; 3313 3314 clocks = <&aoss_qmp>; 3315 clock-names = "apb_pclk"; 3316 arm,coresight-loses-context-with-cpu; 3317 3318 out-ports { 3319 port { 3320 etm6_out: endpoint { 3321 remote-endpoint = <&apss_funnel_in6>; 3322 }; 3323 }; 3324 }; 3325 }; 3326 3327 etm@7740000 { 3328 compatible = "arm,coresight-etm4x", "arm,primecell"; 3329 reg = <0 0x07740000 0 0x1000>; 3330 3331 cpu = <&CPU7>; 3332 3333 clocks = <&aoss_qmp>; 3334 clock-names = "apb_pclk"; 3335 arm,coresight-loses-context-with-cpu; 3336 3337 out-ports { 3338 port { 3339 etm7_out: endpoint { 3340 remote-endpoint = <&apss_funnel_in7>; 3341 }; 3342 }; 3343 }; 3344 }; 3345 3346 funnel@7800000 { 3347 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3348 reg = <0 0x07800000 0 0x1000>; 3349 3350 clocks = <&aoss_qmp>; 3351 clock-names = "apb_pclk"; 3352 3353 out-ports { 3354 port { 3355 funnel_apss_out_funnel_apss_merg: endpoint { 3356 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>; 3357 }; 3358 }; 3359 }; 3360 3361 in-ports { 3362 #address-cells = <1>; 3363 #size-cells = <0>; 3364 3365 port@0 { 3366 reg = <0>; 3367 apss_funnel_in0: endpoint { 3368 remote-endpoint = <&etm0_out>; 3369 }; 3370 }; 3371 3372 port@1 { 3373 reg = <1>; 3374 apss_funnel_in1: endpoint { 3375 remote-endpoint = <&etm1_out>; 3376 }; 3377 }; 3378 3379 port@2 { 3380 reg = <2>; 3381 apss_funnel_in2: endpoint { 3382 remote-endpoint = <&etm2_out>; 3383 }; 3384 }; 3385 3386 port@3 { 3387 reg = <3>; 3388 apss_funnel_in3: endpoint { 3389 remote-endpoint = <&etm3_out>; 3390 }; 3391 }; 3392 3393 port@4 { 3394 reg = <4>; 3395 apss_funnel_in4: endpoint { 3396 remote-endpoint = <&etm4_out>; 3397 }; 3398 }; 3399 3400 port@5 { 3401 reg = <5>; 3402 apss_funnel_in5: endpoint { 3403 remote-endpoint = <&etm5_out>; 3404 }; 3405 }; 3406 3407 port@6 { 3408 reg = <6>; 3409 apss_funnel_in6: endpoint { 3410 remote-endpoint = <&etm6_out>; 3411 }; 3412 }; 3413 3414 port@7 { 3415 reg = <7>; 3416 apss_funnel_in7: endpoint { 3417 remote-endpoint = <&etm7_out>; 3418 }; 3419 }; 3420 }; 3421 }; 3422 3423 funnel@7810000 { 3424 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3425 reg = <0 0x07810000 0 0x1000>; 3426 3427 clocks = <&aoss_qmp>; 3428 clock-names = "apb_pclk"; 3429 3430 out-ports { 3431 port { 3432 funnel_apss_merg_out_funnel_in1: endpoint { 3433 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>; 3434 }; 3435 }; 3436 }; 3437 3438 in-ports { 3439 #address-cells = <1>; 3440 #size-cells = <0>; 3441 3442 port@0 { 3443 reg = <0>; 3444 funnel_apss_merg_in_funnel_apss: endpoint { 3445 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>; 3446 }; 3447 }; 3448 }; 3449 }; 3450 3451 cdsp: remoteproc@8300000 { 3452 compatible = "qcom,sm8250-cdsp-pas"; 3453 reg = <0 0x08300000 0 0x10000>; 3454 3455 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 3456 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3457 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3458 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3459 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3460 interrupt-names = "wdog", "fatal", "ready", 3461 "handover", "stop-ack"; 3462 3463 clocks = <&rpmhcc RPMH_CXO_CLK>; 3464 clock-names = "xo"; 3465 3466 power-domains = <&rpmhpd SM8250_CX>; 3467 3468 memory-region = <&cdsp_mem>; 3469 3470 qcom,qmp = <&aoss_qmp>; 3471 3472 qcom,smem-states = <&smp2p_cdsp_out 0>; 3473 qcom,smem-state-names = "stop"; 3474 3475 status = "disabled"; 3476 3477 glink-edge { 3478 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3479 IPCC_MPROC_SIGNAL_GLINK_QMP 3480 IRQ_TYPE_EDGE_RISING>; 3481 mboxes = <&ipcc IPCC_CLIENT_CDSP 3482 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3483 3484 label = "cdsp"; 3485 qcom,remote-pid = <5>; 3486 3487 fastrpc { 3488 compatible = "qcom,fastrpc"; 3489 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3490 label = "cdsp"; 3491 qcom,non-secure-domain; 3492 #address-cells = <1>; 3493 #size-cells = <0>; 3494 3495 compute-cb@1 { 3496 compatible = "qcom,fastrpc-compute-cb"; 3497 reg = <1>; 3498 iommus = <&apps_smmu 0x1001 0x0460>; 3499 }; 3500 3501 compute-cb@2 { 3502 compatible = "qcom,fastrpc-compute-cb"; 3503 reg = <2>; 3504 iommus = <&apps_smmu 0x1002 0x0460>; 3505 }; 3506 3507 compute-cb@3 { 3508 compatible = "qcom,fastrpc-compute-cb"; 3509 reg = <3>; 3510 iommus = <&apps_smmu 0x1003 0x0460>; 3511 }; 3512 3513 compute-cb@4 { 3514 compatible = "qcom,fastrpc-compute-cb"; 3515 reg = <4>; 3516 iommus = <&apps_smmu 0x1004 0x0460>; 3517 }; 3518 3519 compute-cb@5 { 3520 compatible = "qcom,fastrpc-compute-cb"; 3521 reg = <5>; 3522 iommus = <&apps_smmu 0x1005 0x0460>; 3523 }; 3524 3525 compute-cb@6 { 3526 compatible = "qcom,fastrpc-compute-cb"; 3527 reg = <6>; 3528 iommus = <&apps_smmu 0x1006 0x0460>; 3529 }; 3530 3531 compute-cb@7 { 3532 compatible = "qcom,fastrpc-compute-cb"; 3533 reg = <7>; 3534 iommus = <&apps_smmu 0x1007 0x0460>; 3535 }; 3536 3537 compute-cb@8 { 3538 compatible = "qcom,fastrpc-compute-cb"; 3539 reg = <8>; 3540 iommus = <&apps_smmu 0x1008 0x0460>; 3541 }; 3542 3543 /* note: secure cb9 in downstream */ 3544 }; 3545 }; 3546 }; 3547 3548 usb_1_hsphy: phy@88e3000 { 3549 compatible = "qcom,sm8250-usb-hs-phy", 3550 "qcom,usb-snps-hs-7nm-phy"; 3551 reg = <0 0x088e3000 0 0x400>; 3552 status = "disabled"; 3553 #phy-cells = <0>; 3554 3555 clocks = <&rpmhcc RPMH_CXO_CLK>; 3556 clock-names = "ref"; 3557 3558 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3559 }; 3560 3561 usb_2_hsphy: phy@88e4000 { 3562 compatible = "qcom,sm8250-usb-hs-phy", 3563 "qcom,usb-snps-hs-7nm-phy"; 3564 reg = <0 0x088e4000 0 0x400>; 3565 status = "disabled"; 3566 #phy-cells = <0>; 3567 3568 clocks = <&rpmhcc RPMH_CXO_CLK>; 3569 clock-names = "ref"; 3570 3571 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3572 }; 3573 3574 usb_1_qmpphy: phy@88e9000 { 3575 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 3576 reg = <0 0x088e9000 0 0x200>, 3577 <0 0x088e8000 0 0x40>, 3578 <0 0x088ea000 0 0x200>; 3579 status = "disabled"; 3580 #address-cells = <2>; 3581 #size-cells = <2>; 3582 ranges; 3583 3584 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3585 <&rpmhcc RPMH_CXO_CLK>, 3586 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3587 clock-names = "aux", "ref_clk_src", "com_aux"; 3588 3589 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3590 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3591 reset-names = "phy", "common"; 3592 3593 usb_1_ssphy: usb3-phy@88e9200 { 3594 reg = <0 0x088e9200 0 0x200>, 3595 <0 0x088e9400 0 0x200>, 3596 <0 0x088e9c00 0 0x400>, 3597 <0 0x088e9600 0 0x200>, 3598 <0 0x088e9800 0 0x200>, 3599 <0 0x088e9a00 0 0x100>; 3600 #clock-cells = <0>; 3601 #phy-cells = <0>; 3602 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3603 clock-names = "pipe0"; 3604 clock-output-names = "usb3_phy_pipe_clk_src"; 3605 }; 3606 3607 dp_phy: dp-phy@88ea200 { 3608 reg = <0 0x088ea200 0 0x200>, 3609 <0 0x088ea400 0 0x200>, 3610 <0 0x088eaa00 0 0x200>, 3611 <0 0x088ea600 0 0x200>, 3612 <0 0x088ea800 0 0x200>; 3613 #phy-cells = <0>; 3614 #clock-cells = <1>; 3615 }; 3616 }; 3617 3618 usb_2_qmpphy: phy@88eb000 { 3619 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 3620 reg = <0 0x088eb000 0 0x200>; 3621 status = "disabled"; 3622 #address-cells = <2>; 3623 #size-cells = <2>; 3624 ranges; 3625 3626 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3627 <&rpmhcc RPMH_CXO_CLK>, 3628 <&gcc GCC_USB3_SEC_CLKREF_EN>, 3629 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3630 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3631 3632 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3633 <&gcc GCC_USB3_PHY_SEC_BCR>; 3634 reset-names = "phy", "common"; 3635 3636 usb_2_ssphy: phy@88eb200 { 3637 reg = <0 0x088eb200 0 0x200>, 3638 <0 0x088eb400 0 0x200>, 3639 <0 0x088eb800 0 0x800>; 3640 #clock-cells = <0>; 3641 #phy-cells = <0>; 3642 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3643 clock-names = "pipe0"; 3644 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3645 }; 3646 }; 3647 3648 sdhc_2: mmc@8804000 { 3649 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 3650 reg = <0 0x08804000 0 0x1000>; 3651 3652 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3653 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3654 interrupt-names = "hc_irq", "pwr_irq"; 3655 3656 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3657 <&gcc GCC_SDCC2_APPS_CLK>, 3658 <&rpmhcc RPMH_CXO_CLK>; 3659 clock-names = "iface", "core", "xo"; 3660 iommus = <&apps_smmu 0x4a0 0x0>; 3661 qcom,dll-config = <0x0007642c>; 3662 qcom,ddr-config = <0x80040868>; 3663 power-domains = <&rpmhpd SM8250_CX>; 3664 operating-points-v2 = <&sdhc2_opp_table>; 3665 3666 status = "disabled"; 3667 3668 sdhc2_opp_table: opp-table { 3669 compatible = "operating-points-v2"; 3670 3671 opp-19200000 { 3672 opp-hz = /bits/ 64 <19200000>; 3673 required-opps = <&rpmhpd_opp_min_svs>; 3674 }; 3675 3676 opp-50000000 { 3677 opp-hz = /bits/ 64 <50000000>; 3678 required-opps = <&rpmhpd_opp_low_svs>; 3679 }; 3680 3681 opp-100000000 { 3682 opp-hz = /bits/ 64 <100000000>; 3683 required-opps = <&rpmhpd_opp_svs>; 3684 }; 3685 3686 opp-202000000 { 3687 opp-hz = /bits/ 64 <202000000>; 3688 required-opps = <&rpmhpd_opp_svs_l1>; 3689 }; 3690 }; 3691 }; 3692 3693 dc_noc: interconnect@90c0000 { 3694 compatible = "qcom,sm8250-dc-noc"; 3695 reg = <0 0x090c0000 0 0x4200>; 3696 #interconnect-cells = <1>; 3697 qcom,bcm-voters = <&apps_bcm_voter>; 3698 }; 3699 3700 gem_noc: interconnect@9100000 { 3701 compatible = "qcom,sm8250-gem-noc"; 3702 reg = <0 0x09100000 0 0xb4000>; 3703 #interconnect-cells = <1>; 3704 qcom,bcm-voters = <&apps_bcm_voter>; 3705 }; 3706 3707 npu_noc: interconnect@9990000 { 3708 compatible = "qcom,sm8250-npu-noc"; 3709 reg = <0 0x09990000 0 0x1600>; 3710 #interconnect-cells = <1>; 3711 qcom,bcm-voters = <&apps_bcm_voter>; 3712 }; 3713 3714 usb_1: usb@a6f8800 { 3715 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3716 reg = <0 0x0a6f8800 0 0x400>; 3717 status = "disabled"; 3718 #address-cells = <2>; 3719 #size-cells = <2>; 3720 ranges; 3721 dma-ranges; 3722 3723 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3724 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3725 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3726 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3727 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3728 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3729 clock-names = "cfg_noc", 3730 "core", 3731 "iface", 3732 "sleep", 3733 "mock_utmi", 3734 "xo"; 3735 3736 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3737 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3738 assigned-clock-rates = <19200000>, <200000000>; 3739 3740 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3741 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 3742 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3743 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 3744 interrupt-names = "hs_phy_irq", 3745 "ss_phy_irq", 3746 "dm_hs_phy_irq", 3747 "dp_hs_phy_irq"; 3748 3749 power-domains = <&gcc USB30_PRIM_GDSC>; 3750 3751 resets = <&gcc GCC_USB30_PRIM_BCR>; 3752 3753 usb_1_dwc3: usb@a600000 { 3754 compatible = "snps,dwc3"; 3755 reg = <0 0x0a600000 0 0xcd00>; 3756 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3757 iommus = <&apps_smmu 0x0 0x0>; 3758 snps,dis_u2_susphy_quirk; 3759 snps,dis_enblslpm_quirk; 3760 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3761 phy-names = "usb2-phy", "usb3-phy"; 3762 }; 3763 }; 3764 3765 system-cache-controller@9200000 { 3766 compatible = "qcom,sm8250-llcc"; 3767 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 3768 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 3769 <0 0x09600000 0 0x50000>; 3770 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3771 "llcc3_base", "llcc_broadcast_base"; 3772 }; 3773 3774 usb_2: usb@a8f8800 { 3775 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3776 reg = <0 0x0a8f8800 0 0x400>; 3777 status = "disabled"; 3778 #address-cells = <2>; 3779 #size-cells = <2>; 3780 ranges; 3781 dma-ranges; 3782 3783 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3784 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3785 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3786 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3787 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3788 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3789 clock-names = "cfg_noc", 3790 "core", 3791 "iface", 3792 "sleep", 3793 "mock_utmi", 3794 "xo"; 3795 3796 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3797 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3798 assigned-clock-rates = <19200000>, <200000000>; 3799 3800 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3801 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 3802 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3803 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 3804 interrupt-names = "hs_phy_irq", 3805 "ss_phy_irq", 3806 "dm_hs_phy_irq", 3807 "dp_hs_phy_irq"; 3808 3809 power-domains = <&gcc USB30_SEC_GDSC>; 3810 3811 resets = <&gcc GCC_USB30_SEC_BCR>; 3812 3813 usb_2_dwc3: usb@a800000 { 3814 compatible = "snps,dwc3"; 3815 reg = <0 0x0a800000 0 0xcd00>; 3816 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3817 iommus = <&apps_smmu 0x20 0>; 3818 snps,dis_u2_susphy_quirk; 3819 snps,dis_enblslpm_quirk; 3820 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3821 phy-names = "usb2-phy", "usb3-phy"; 3822 }; 3823 }; 3824 3825 venus: video-codec@aa00000 { 3826 compatible = "qcom,sm8250-venus"; 3827 reg = <0 0x0aa00000 0 0x100000>; 3828 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3829 power-domains = <&videocc MVS0C_GDSC>, 3830 <&videocc MVS0_GDSC>, 3831 <&rpmhpd SM8250_MX>; 3832 power-domain-names = "venus", "vcodec0", "mx"; 3833 operating-points-v2 = <&venus_opp_table>; 3834 3835 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 3836 <&videocc VIDEO_CC_MVS0C_CLK>, 3837 <&videocc VIDEO_CC_MVS0_CLK>; 3838 clock-names = "iface", "core", "vcodec0_core"; 3839 3840 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, 3841 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; 3842 interconnect-names = "cpu-cfg", "video-mem"; 3843 3844 iommus = <&apps_smmu 0x2100 0x0400>; 3845 memory-region = <&video_mem>; 3846 3847 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 3848 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 3849 reset-names = "bus", "core"; 3850 3851 status = "disabled"; 3852 3853 video-decoder { 3854 compatible = "venus-decoder"; 3855 }; 3856 3857 video-encoder { 3858 compatible = "venus-encoder"; 3859 }; 3860 3861 venus_opp_table: opp-table { 3862 compatible = "operating-points-v2"; 3863 3864 opp-720000000 { 3865 opp-hz = /bits/ 64 <720000000>; 3866 required-opps = <&rpmhpd_opp_low_svs>; 3867 }; 3868 3869 opp-1014000000 { 3870 opp-hz = /bits/ 64 <1014000000>; 3871 required-opps = <&rpmhpd_opp_svs>; 3872 }; 3873 3874 opp-1098000000 { 3875 opp-hz = /bits/ 64 <1098000000>; 3876 required-opps = <&rpmhpd_opp_svs_l1>; 3877 }; 3878 3879 opp-1332000000 { 3880 opp-hz = /bits/ 64 <1332000000>; 3881 required-opps = <&rpmhpd_opp_nom>; 3882 }; 3883 }; 3884 }; 3885 3886 videocc: clock-controller@abf0000 { 3887 compatible = "qcom,sm8250-videocc"; 3888 reg = <0 0x0abf0000 0 0x10000>; 3889 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 3890 <&rpmhcc RPMH_CXO_CLK>, 3891 <&rpmhcc RPMH_CXO_CLK_A>; 3892 power-domains = <&rpmhpd SM8250_MMCX>; 3893 required-opps = <&rpmhpd_opp_low_svs>; 3894 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 3895 #clock-cells = <1>; 3896 #reset-cells = <1>; 3897 #power-domain-cells = <1>; 3898 }; 3899 3900 cci0: cci@ac4f000 { 3901 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 3902 #address-cells = <1>; 3903 #size-cells = <0>; 3904 3905 reg = <0 0x0ac4f000 0 0x1000>; 3906 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3907 power-domains = <&camcc TITAN_TOP_GDSC>; 3908 3909 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3910 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3911 <&camcc CAM_CC_CPAS_AHB_CLK>, 3912 <&camcc CAM_CC_CCI_0_CLK>, 3913 <&camcc CAM_CC_CCI_0_CLK_SRC>; 3914 clock-names = "camnoc_axi", 3915 "slow_ahb_src", 3916 "cpas_ahb", 3917 "cci", 3918 "cci_src"; 3919 3920 pinctrl-0 = <&cci0_default>; 3921 pinctrl-1 = <&cci0_sleep>; 3922 pinctrl-names = "default", "sleep"; 3923 3924 status = "disabled"; 3925 3926 cci0_i2c0: i2c-bus@0 { 3927 reg = <0>; 3928 clock-frequency = <1000000>; 3929 #address-cells = <1>; 3930 #size-cells = <0>; 3931 }; 3932 3933 cci0_i2c1: i2c-bus@1 { 3934 reg = <1>; 3935 clock-frequency = <1000000>; 3936 #address-cells = <1>; 3937 #size-cells = <0>; 3938 }; 3939 }; 3940 3941 cci1: cci@ac50000 { 3942 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 3943 #address-cells = <1>; 3944 #size-cells = <0>; 3945 3946 reg = <0 0x0ac50000 0 0x1000>; 3947 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 3948 power-domains = <&camcc TITAN_TOP_GDSC>; 3949 3950 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3951 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3952 <&camcc CAM_CC_CPAS_AHB_CLK>, 3953 <&camcc CAM_CC_CCI_1_CLK>, 3954 <&camcc CAM_CC_CCI_1_CLK_SRC>; 3955 clock-names = "camnoc_axi", 3956 "slow_ahb_src", 3957 "cpas_ahb", 3958 "cci", 3959 "cci_src"; 3960 3961 pinctrl-0 = <&cci1_default>; 3962 pinctrl-1 = <&cci1_sleep>; 3963 pinctrl-names = "default", "sleep"; 3964 3965 status = "disabled"; 3966 3967 cci1_i2c0: i2c-bus@0 { 3968 reg = <0>; 3969 clock-frequency = <1000000>; 3970 #address-cells = <1>; 3971 #size-cells = <0>; 3972 }; 3973 3974 cci1_i2c1: i2c-bus@1 { 3975 reg = <1>; 3976 clock-frequency = <1000000>; 3977 #address-cells = <1>; 3978 #size-cells = <0>; 3979 }; 3980 }; 3981 3982 camss: camss@ac6a000 { 3983 compatible = "qcom,sm8250-camss"; 3984 status = "disabled"; 3985 3986 reg = <0 0x0ac6a000 0 0x2000>, 3987 <0 0x0ac6c000 0 0x2000>, 3988 <0 0x0ac6e000 0 0x1000>, 3989 <0 0x0ac70000 0 0x1000>, 3990 <0 0x0ac72000 0 0x1000>, 3991 <0 0x0ac74000 0 0x1000>, 3992 <0 0x0acb4000 0 0xd000>, 3993 <0 0x0acc3000 0 0xd000>, 3994 <0 0x0acd9000 0 0x2200>, 3995 <0 0x0acdb200 0 0x2200>; 3996 reg-names = "csiphy0", 3997 "csiphy1", 3998 "csiphy2", 3999 "csiphy3", 4000 "csiphy4", 4001 "csiphy5", 4002 "vfe0", 4003 "vfe1", 4004 "vfe_lite0", 4005 "vfe_lite1"; 4006 4007 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 4008 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 4009 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 4010 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 4011 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 4012 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 4013 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 4014 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 4015 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 4016 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 4017 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 4018 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 4019 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 4020 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 4021 interrupt-names = "csiphy0", 4022 "csiphy1", 4023 "csiphy2", 4024 "csiphy3", 4025 "csiphy4", 4026 "csiphy5", 4027 "csid0", 4028 "csid1", 4029 "csid2", 4030 "csid3", 4031 "vfe0", 4032 "vfe1", 4033 "vfe_lite0", 4034 "vfe_lite1"; 4035 4036 power-domains = <&camcc IFE_0_GDSC>, 4037 <&camcc IFE_1_GDSC>, 4038 <&camcc TITAN_TOP_GDSC>; 4039 4040 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4041 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4042 <&gcc GCC_CAMERA_SF_AXI_CLK>, 4043 <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4044 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, 4045 <&camcc CAM_CC_CORE_AHB_CLK>, 4046 <&camcc CAM_CC_CPAS_AHB_CLK>, 4047 <&camcc CAM_CC_CSIPHY0_CLK>, 4048 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4049 <&camcc CAM_CC_CSIPHY1_CLK>, 4050 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4051 <&camcc CAM_CC_CSIPHY2_CLK>, 4052 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4053 <&camcc CAM_CC_CSIPHY3_CLK>, 4054 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 4055 <&camcc CAM_CC_CSIPHY4_CLK>, 4056 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 4057 <&camcc CAM_CC_CSIPHY5_CLK>, 4058 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 4059 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4060 <&camcc CAM_CC_IFE_0_AHB_CLK>, 4061 <&camcc CAM_CC_IFE_0_AXI_CLK>, 4062 <&camcc CAM_CC_IFE_0_CLK>, 4063 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4064 <&camcc CAM_CC_IFE_0_CSID_CLK>, 4065 <&camcc CAM_CC_IFE_0_AREG_CLK>, 4066 <&camcc CAM_CC_IFE_1_AHB_CLK>, 4067 <&camcc CAM_CC_IFE_1_AXI_CLK>, 4068 <&camcc CAM_CC_IFE_1_CLK>, 4069 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4070 <&camcc CAM_CC_IFE_1_CSID_CLK>, 4071 <&camcc CAM_CC_IFE_1_AREG_CLK>, 4072 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 4073 <&camcc CAM_CC_IFE_LITE_AXI_CLK>, 4074 <&camcc CAM_CC_IFE_LITE_CLK>, 4075 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4076 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 4077 4078 clock-names = "cam_ahb_clk", 4079 "cam_hf_axi", 4080 "cam_sf_axi", 4081 "camnoc_axi", 4082 "camnoc_axi_src", 4083 "core_ahb", 4084 "cpas_ahb", 4085 "csiphy0", 4086 "csiphy0_timer", 4087 "csiphy1", 4088 "csiphy1_timer", 4089 "csiphy2", 4090 "csiphy2_timer", 4091 "csiphy3", 4092 "csiphy3_timer", 4093 "csiphy4", 4094 "csiphy4_timer", 4095 "csiphy5", 4096 "csiphy5_timer", 4097 "slow_ahb_src", 4098 "vfe0_ahb", 4099 "vfe0_axi", 4100 "vfe0", 4101 "vfe0_cphy_rx", 4102 "vfe0_csid", 4103 "vfe0_areg", 4104 "vfe1_ahb", 4105 "vfe1_axi", 4106 "vfe1", 4107 "vfe1_cphy_rx", 4108 "vfe1_csid", 4109 "vfe1_areg", 4110 "vfe_lite_ahb", 4111 "vfe_lite_axi", 4112 "vfe_lite", 4113 "vfe_lite_cphy_rx", 4114 "vfe_lite_csid"; 4115 4116 iommus = <&apps_smmu 0x800 0x400>, 4117 <&apps_smmu 0x801 0x400>, 4118 <&apps_smmu 0x840 0x400>, 4119 <&apps_smmu 0x841 0x400>, 4120 <&apps_smmu 0xc00 0x400>, 4121 <&apps_smmu 0xc01 0x400>, 4122 <&apps_smmu 0xc40 0x400>, 4123 <&apps_smmu 0xc41 0x400>; 4124 4125 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>, 4126 <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>, 4127 <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>, 4128 <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>; 4129 interconnect-names = "cam_ahb", 4130 "cam_hf_0_mnoc", 4131 "cam_sf_0_mnoc", 4132 "cam_sf_icp_mnoc"; 4133 4134 ports { 4135 #address-cells = <1>; 4136 #size-cells = <0>; 4137 4138 port@0 { 4139 reg = <0>; 4140 }; 4141 4142 port@1 { 4143 reg = <1>; 4144 }; 4145 4146 port@2 { 4147 reg = <2>; 4148 }; 4149 4150 port@3 { 4151 reg = <3>; 4152 }; 4153 4154 port@4 { 4155 reg = <4>; 4156 }; 4157 4158 port@5 { 4159 reg = <5>; 4160 }; 4161 }; 4162 }; 4163 4164 camcc: clock-controller@ad00000 { 4165 compatible = "qcom,sm8250-camcc"; 4166 reg = <0 0x0ad00000 0 0x10000>; 4167 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4168 <&rpmhcc RPMH_CXO_CLK>, 4169 <&rpmhcc RPMH_CXO_CLK_A>, 4170 <&sleep_clk>; 4171 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 4172 power-domains = <&rpmhpd SM8250_MMCX>; 4173 required-opps = <&rpmhpd_opp_low_svs>; 4174 status = "disabled"; 4175 #clock-cells = <1>; 4176 #reset-cells = <1>; 4177 #power-domain-cells = <1>; 4178 }; 4179 4180 mdss: display-subsystem@ae00000 { 4181 compatible = "qcom,sm8250-mdss"; 4182 reg = <0 0x0ae00000 0 0x1000>; 4183 reg-names = "mdss"; 4184 4185 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 4186 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 4187 interconnect-names = "mdp0-mem", "mdp1-mem"; 4188 4189 power-domains = <&dispcc MDSS_GDSC>; 4190 4191 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4192 <&gcc GCC_DISP_HF_AXI_CLK>, 4193 <&gcc GCC_DISP_SF_AXI_CLK>, 4194 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4195 clock-names = "iface", "bus", "nrt_bus", "core"; 4196 4197 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4198 interrupt-controller; 4199 #interrupt-cells = <1>; 4200 4201 iommus = <&apps_smmu 0x820 0x402>; 4202 4203 status = "disabled"; 4204 4205 #address-cells = <2>; 4206 #size-cells = <2>; 4207 ranges; 4208 4209 mdss_mdp: display-controller@ae01000 { 4210 compatible = "qcom,sm8250-dpu"; 4211 reg = <0 0x0ae01000 0 0x8f000>, 4212 <0 0x0aeb0000 0 0x2008>; 4213 reg-names = "mdp", "vbif"; 4214 4215 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4216 <&gcc GCC_DISP_HF_AXI_CLK>, 4217 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4218 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4219 clock-names = "iface", "bus", "core", "vsync"; 4220 4221 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4222 assigned-clock-rates = <19200000>; 4223 4224 operating-points-v2 = <&mdp_opp_table>; 4225 power-domains = <&rpmhpd SM8250_MMCX>; 4226 4227 interrupt-parent = <&mdss>; 4228 interrupts = <0>; 4229 4230 ports { 4231 #address-cells = <1>; 4232 #size-cells = <0>; 4233 4234 port@0 { 4235 reg = <0>; 4236 dpu_intf1_out: endpoint { 4237 remote-endpoint = <&dsi0_in>; 4238 }; 4239 }; 4240 4241 port@1 { 4242 reg = <1>; 4243 dpu_intf2_out: endpoint { 4244 remote-endpoint = <&dsi1_in>; 4245 }; 4246 }; 4247 }; 4248 4249 mdp_opp_table: opp-table { 4250 compatible = "operating-points-v2"; 4251 4252 opp-200000000 { 4253 opp-hz = /bits/ 64 <200000000>; 4254 required-opps = <&rpmhpd_opp_low_svs>; 4255 }; 4256 4257 opp-300000000 { 4258 opp-hz = /bits/ 64 <300000000>; 4259 required-opps = <&rpmhpd_opp_svs>; 4260 }; 4261 4262 opp-345000000 { 4263 opp-hz = /bits/ 64 <345000000>; 4264 required-opps = <&rpmhpd_opp_svs_l1>; 4265 }; 4266 4267 opp-460000000 { 4268 opp-hz = /bits/ 64 <460000000>; 4269 required-opps = <&rpmhpd_opp_nom>; 4270 }; 4271 }; 4272 }; 4273 4274 dsi0: dsi@ae94000 { 4275 compatible = "qcom,sm8250-dsi-ctrl", 4276 "qcom,mdss-dsi-ctrl"; 4277 reg = <0 0x0ae94000 0 0x400>; 4278 reg-names = "dsi_ctrl"; 4279 4280 interrupt-parent = <&mdss>; 4281 interrupts = <4>; 4282 4283 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4284 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4285 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4286 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4287 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4288 <&gcc GCC_DISP_HF_AXI_CLK>; 4289 clock-names = "byte", 4290 "byte_intf", 4291 "pixel", 4292 "core", 4293 "iface", 4294 "bus"; 4295 4296 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4297 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 4298 4299 operating-points-v2 = <&dsi_opp_table>; 4300 power-domains = <&rpmhpd SM8250_MMCX>; 4301 4302 phys = <&dsi0_phy>; 4303 4304 status = "disabled"; 4305 4306 #address-cells = <1>; 4307 #size-cells = <0>; 4308 4309 ports { 4310 #address-cells = <1>; 4311 #size-cells = <0>; 4312 4313 port@0 { 4314 reg = <0>; 4315 dsi0_in: endpoint { 4316 remote-endpoint = <&dpu_intf1_out>; 4317 }; 4318 }; 4319 4320 port@1 { 4321 reg = <1>; 4322 dsi0_out: endpoint { 4323 }; 4324 }; 4325 }; 4326 4327 dsi_opp_table: opp-table { 4328 compatible = "operating-points-v2"; 4329 4330 opp-187500000 { 4331 opp-hz = /bits/ 64 <187500000>; 4332 required-opps = <&rpmhpd_opp_low_svs>; 4333 }; 4334 4335 opp-300000000 { 4336 opp-hz = /bits/ 64 <300000000>; 4337 required-opps = <&rpmhpd_opp_svs>; 4338 }; 4339 4340 opp-358000000 { 4341 opp-hz = /bits/ 64 <358000000>; 4342 required-opps = <&rpmhpd_opp_svs_l1>; 4343 }; 4344 }; 4345 }; 4346 4347 dsi0_phy: phy@ae94400 { 4348 compatible = "qcom,dsi-phy-7nm"; 4349 reg = <0 0x0ae94400 0 0x200>, 4350 <0 0x0ae94600 0 0x280>, 4351 <0 0x0ae94900 0 0x260>; 4352 reg-names = "dsi_phy", 4353 "dsi_phy_lane", 4354 "dsi_pll"; 4355 4356 #clock-cells = <1>; 4357 #phy-cells = <0>; 4358 4359 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4360 <&rpmhcc RPMH_CXO_CLK>; 4361 clock-names = "iface", "ref"; 4362 4363 status = "disabled"; 4364 }; 4365 4366 dsi1: dsi@ae96000 { 4367 compatible = "qcom,sm8250-dsi-ctrl", 4368 "qcom,mdss-dsi-ctrl"; 4369 reg = <0 0x0ae96000 0 0x400>; 4370 reg-names = "dsi_ctrl"; 4371 4372 interrupt-parent = <&mdss>; 4373 interrupts = <5>; 4374 4375 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4376 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4377 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4378 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4379 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4380 <&gcc GCC_DISP_HF_AXI_CLK>; 4381 clock-names = "byte", 4382 "byte_intf", 4383 "pixel", 4384 "core", 4385 "iface", 4386 "bus"; 4387 4388 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4389 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 4390 4391 operating-points-v2 = <&dsi_opp_table>; 4392 power-domains = <&rpmhpd SM8250_MMCX>; 4393 4394 phys = <&dsi1_phy>; 4395 4396 status = "disabled"; 4397 4398 #address-cells = <1>; 4399 #size-cells = <0>; 4400 4401 ports { 4402 #address-cells = <1>; 4403 #size-cells = <0>; 4404 4405 port@0 { 4406 reg = <0>; 4407 dsi1_in: endpoint { 4408 remote-endpoint = <&dpu_intf2_out>; 4409 }; 4410 }; 4411 4412 port@1 { 4413 reg = <1>; 4414 dsi1_out: endpoint { 4415 }; 4416 }; 4417 }; 4418 }; 4419 4420 dsi1_phy: phy@ae96400 { 4421 compatible = "qcom,dsi-phy-7nm"; 4422 reg = <0 0x0ae96400 0 0x200>, 4423 <0 0x0ae96600 0 0x280>, 4424 <0 0x0ae96900 0 0x260>; 4425 reg-names = "dsi_phy", 4426 "dsi_phy_lane", 4427 "dsi_pll"; 4428 4429 #clock-cells = <1>; 4430 #phy-cells = <0>; 4431 4432 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4433 <&rpmhcc RPMH_CXO_CLK>; 4434 clock-names = "iface", "ref"; 4435 4436 status = "disabled"; 4437 }; 4438 }; 4439 4440 dispcc: clock-controller@af00000 { 4441 compatible = "qcom,sm8250-dispcc"; 4442 reg = <0 0x0af00000 0 0x10000>; 4443 power-domains = <&rpmhpd SM8250_MMCX>; 4444 required-opps = <&rpmhpd_opp_low_svs>; 4445 clocks = <&rpmhcc RPMH_CXO_CLK>, 4446 <&dsi0_phy 0>, 4447 <&dsi0_phy 1>, 4448 <&dsi1_phy 0>, 4449 <&dsi1_phy 1>, 4450 <&dp_phy 0>, 4451 <&dp_phy 1>; 4452 clock-names = "bi_tcxo", 4453 "dsi0_phy_pll_out_byteclk", 4454 "dsi0_phy_pll_out_dsiclk", 4455 "dsi1_phy_pll_out_byteclk", 4456 "dsi1_phy_pll_out_dsiclk", 4457 "dp_phy_pll_link_clk", 4458 "dp_phy_pll_vco_div_clk"; 4459 #clock-cells = <1>; 4460 #reset-cells = <1>; 4461 #power-domain-cells = <1>; 4462 }; 4463 4464 pdc: interrupt-controller@b220000 { 4465 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 4466 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 4467 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4468 <125 63 1>, <126 716 12>; 4469 #interrupt-cells = <2>; 4470 interrupt-parent = <&intc>; 4471 interrupt-controller; 4472 }; 4473 4474 tsens0: thermal-sensor@c263000 { 4475 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 4476 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4477 <0 0x0c222000 0 0x1ff>; /* SROT */ 4478 #qcom,sensors = <16>; 4479 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4480 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4481 interrupt-names = "uplow", "critical"; 4482 #thermal-sensor-cells = <1>; 4483 }; 4484 4485 tsens1: thermal-sensor@c265000 { 4486 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 4487 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4488 <0 0x0c223000 0 0x1ff>; /* SROT */ 4489 #qcom,sensors = <9>; 4490 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4491 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4492 interrupt-names = "uplow", "critical"; 4493 #thermal-sensor-cells = <1>; 4494 }; 4495 4496 aoss_qmp: power-management@c300000 { 4497 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; 4498 reg = <0 0x0c300000 0 0x400>; 4499 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4500 IPCC_MPROC_SIGNAL_GLINK_QMP 4501 IRQ_TYPE_EDGE_RISING>; 4502 mboxes = <&ipcc IPCC_CLIENT_AOP 4503 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4504 4505 #clock-cells = <0>; 4506 }; 4507 4508 sram@c3f0000 { 4509 compatible = "qcom,rpmh-stats"; 4510 reg = <0 0x0c3f0000 0 0x400>; 4511 }; 4512 4513 spmi_bus: spmi@c440000 { 4514 compatible = "qcom,spmi-pmic-arb"; 4515 reg = <0x0 0x0c440000 0x0 0x0001100>, 4516 <0x0 0x0c600000 0x0 0x2000000>, 4517 <0x0 0x0e600000 0x0 0x0100000>, 4518 <0x0 0x0e700000 0x0 0x00a0000>, 4519 <0x0 0x0c40a000 0x0 0x0026000>; 4520 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4521 interrupt-names = "periph_irq"; 4522 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4523 qcom,ee = <0>; 4524 qcom,channel = <0>; 4525 #address-cells = <2>; 4526 #size-cells = <0>; 4527 interrupt-controller; 4528 #interrupt-cells = <4>; 4529 }; 4530 4531 tlmm: pinctrl@f100000 { 4532 compatible = "qcom,sm8250-pinctrl"; 4533 reg = <0 0x0f100000 0 0x300000>, 4534 <0 0x0f500000 0 0x300000>, 4535 <0 0x0f900000 0 0x300000>; 4536 reg-names = "west", "south", "north"; 4537 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4538 gpio-controller; 4539 #gpio-cells = <2>; 4540 interrupt-controller; 4541 #interrupt-cells = <2>; 4542 gpio-ranges = <&tlmm 0 0 181>; 4543 wakeup-parent = <&pdc>; 4544 4545 cam2_default: cam2-default-state { 4546 rst-pins { 4547 pins = "gpio78"; 4548 function = "gpio"; 4549 drive-strength = <2>; 4550 bias-disable; 4551 }; 4552 4553 mclk-pins { 4554 pins = "gpio96"; 4555 function = "cam_mclk"; 4556 drive-strength = <16>; 4557 bias-disable; 4558 }; 4559 }; 4560 4561 cam2_suspend: cam2-suspend-state { 4562 rst-pins { 4563 pins = "gpio78"; 4564 function = "gpio"; 4565 drive-strength = <2>; 4566 bias-pull-down; 4567 output-low; 4568 }; 4569 4570 mclk-pins { 4571 pins = "gpio96"; 4572 function = "cam_mclk"; 4573 drive-strength = <2>; 4574 bias-disable; 4575 }; 4576 }; 4577 4578 cci0_default: cci0-default-state { 4579 cci0_i2c0_default: cci0-i2c0-default-pins { 4580 /* SDA, SCL */ 4581 pins = "gpio101", "gpio102"; 4582 function = "cci_i2c"; 4583 4584 bias-pull-up; 4585 drive-strength = <2>; /* 2 mA */ 4586 }; 4587 4588 cci0_i2c1_default: cci0-i2c1-default-pins { 4589 /* SDA, SCL */ 4590 pins = "gpio103", "gpio104"; 4591 function = "cci_i2c"; 4592 4593 bias-pull-up; 4594 drive-strength = <2>; /* 2 mA */ 4595 }; 4596 }; 4597 4598 cci0_sleep: cci0-sleep-state { 4599 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 4600 /* SDA, SCL */ 4601 pins = "gpio101", "gpio102"; 4602 function = "cci_i2c"; 4603 4604 drive-strength = <2>; /* 2 mA */ 4605 bias-pull-down; 4606 }; 4607 4608 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 4609 /* SDA, SCL */ 4610 pins = "gpio103", "gpio104"; 4611 function = "cci_i2c"; 4612 4613 drive-strength = <2>; /* 2 mA */ 4614 bias-pull-down; 4615 }; 4616 }; 4617 4618 cci1_default: cci1-default-state { 4619 cci1_i2c0_default: cci1-i2c0-default-pins { 4620 /* SDA, SCL */ 4621 pins = "gpio105","gpio106"; 4622 function = "cci_i2c"; 4623 4624 bias-pull-up; 4625 drive-strength = <2>; /* 2 mA */ 4626 }; 4627 4628 cci1_i2c1_default: cci1-i2c1-default-pins { 4629 /* SDA, SCL */ 4630 pins = "gpio107","gpio108"; 4631 function = "cci_i2c"; 4632 4633 bias-pull-up; 4634 drive-strength = <2>; /* 2 mA */ 4635 }; 4636 }; 4637 4638 cci1_sleep: cci1-sleep-state { 4639 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 4640 /* SDA, SCL */ 4641 pins = "gpio105","gpio106"; 4642 function = "cci_i2c"; 4643 4644 bias-pull-down; 4645 drive-strength = <2>; /* 2 mA */ 4646 }; 4647 4648 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 4649 /* SDA, SCL */ 4650 pins = "gpio107","gpio108"; 4651 function = "cci_i2c"; 4652 4653 bias-pull-down; 4654 drive-strength = <2>; /* 2 mA */ 4655 }; 4656 }; 4657 4658 pri_mi2s_active: pri-mi2s-active-state { 4659 sclk-pins { 4660 pins = "gpio138"; 4661 function = "mi2s0_sck"; 4662 drive-strength = <8>; 4663 bias-disable; 4664 }; 4665 4666 ws-pins { 4667 pins = "gpio141"; 4668 function = "mi2s0_ws"; 4669 drive-strength = <8>; 4670 output-high; 4671 }; 4672 4673 data0-pins { 4674 pins = "gpio139"; 4675 function = "mi2s0_data0"; 4676 drive-strength = <8>; 4677 bias-disable; 4678 output-high; 4679 }; 4680 4681 data1-pins { 4682 pins = "gpio140"; 4683 function = "mi2s0_data1"; 4684 drive-strength = <8>; 4685 output-high; 4686 }; 4687 }; 4688 4689 qup_i2c0_default: qup-i2c0-default-state { 4690 pins = "gpio28", "gpio29"; 4691 function = "qup0"; 4692 drive-strength = <2>; 4693 bias-disable; 4694 }; 4695 4696 qup_i2c1_default: qup-i2c1-default-state { 4697 pins = "gpio4", "gpio5"; 4698 function = "qup1"; 4699 drive-strength = <2>; 4700 bias-disable; 4701 }; 4702 4703 qup_i2c2_default: qup-i2c2-default-state { 4704 pins = "gpio115", "gpio116"; 4705 function = "qup2"; 4706 drive-strength = <2>; 4707 bias-disable; 4708 }; 4709 4710 qup_i2c3_default: qup-i2c3-default-state { 4711 pins = "gpio119", "gpio120"; 4712 function = "qup3"; 4713 drive-strength = <2>; 4714 bias-disable; 4715 }; 4716 4717 qup_i2c4_default: qup-i2c4-default-state { 4718 pins = "gpio8", "gpio9"; 4719 function = "qup4"; 4720 drive-strength = <2>; 4721 bias-disable; 4722 }; 4723 4724 qup_i2c5_default: qup-i2c5-default-state { 4725 pins = "gpio12", "gpio13"; 4726 function = "qup5"; 4727 drive-strength = <2>; 4728 bias-disable; 4729 }; 4730 4731 qup_i2c6_default: qup-i2c6-default-state { 4732 pins = "gpio16", "gpio17"; 4733 function = "qup6"; 4734 drive-strength = <2>; 4735 bias-disable; 4736 }; 4737 4738 qup_i2c7_default: qup-i2c7-default-state { 4739 pins = "gpio20", "gpio21"; 4740 function = "qup7"; 4741 drive-strength = <2>; 4742 bias-disable; 4743 }; 4744 4745 qup_i2c8_default: qup-i2c8-default-state { 4746 pins = "gpio24", "gpio25"; 4747 function = "qup8"; 4748 drive-strength = <2>; 4749 bias-disable; 4750 }; 4751 4752 qup_i2c9_default: qup-i2c9-default-state { 4753 pins = "gpio125", "gpio126"; 4754 function = "qup9"; 4755 drive-strength = <2>; 4756 bias-disable; 4757 }; 4758 4759 qup_i2c10_default: qup-i2c10-default-state { 4760 pins = "gpio129", "gpio130"; 4761 function = "qup10"; 4762 drive-strength = <2>; 4763 bias-disable; 4764 }; 4765 4766 qup_i2c11_default: qup-i2c11-default-state { 4767 pins = "gpio60", "gpio61"; 4768 function = "qup11"; 4769 drive-strength = <2>; 4770 bias-disable; 4771 }; 4772 4773 qup_i2c12_default: qup-i2c12-default-state { 4774 pins = "gpio32", "gpio33"; 4775 function = "qup12"; 4776 drive-strength = <2>; 4777 bias-disable; 4778 }; 4779 4780 qup_i2c13_default: qup-i2c13-default-state { 4781 pins = "gpio36", "gpio37"; 4782 function = "qup13"; 4783 drive-strength = <2>; 4784 bias-disable; 4785 }; 4786 4787 qup_i2c14_default: qup-i2c14-default-state { 4788 pins = "gpio40", "gpio41"; 4789 function = "qup14"; 4790 drive-strength = <2>; 4791 bias-disable; 4792 }; 4793 4794 qup_i2c15_default: qup-i2c15-default-state { 4795 pins = "gpio44", "gpio45"; 4796 function = "qup15"; 4797 drive-strength = <2>; 4798 bias-disable; 4799 }; 4800 4801 qup_i2c16_default: qup-i2c16-default-state { 4802 pins = "gpio48", "gpio49"; 4803 function = "qup16"; 4804 drive-strength = <2>; 4805 bias-disable; 4806 }; 4807 4808 qup_i2c17_default: qup-i2c17-default-state { 4809 pins = "gpio52", "gpio53"; 4810 function = "qup17"; 4811 drive-strength = <2>; 4812 bias-disable; 4813 }; 4814 4815 qup_i2c18_default: qup-i2c18-default-state { 4816 pins = "gpio56", "gpio57"; 4817 function = "qup18"; 4818 drive-strength = <2>; 4819 bias-disable; 4820 }; 4821 4822 qup_i2c19_default: qup-i2c19-default-state { 4823 pins = "gpio0", "gpio1"; 4824 function = "qup19"; 4825 drive-strength = <2>; 4826 bias-disable; 4827 }; 4828 4829 qup_spi0_cs: qup-spi0-cs-state { 4830 pins = "gpio31"; 4831 function = "qup0"; 4832 }; 4833 4834 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4835 pins = "gpio31"; 4836 function = "gpio"; 4837 }; 4838 4839 qup_spi0_data_clk: qup-spi0-data-clk-state { 4840 pins = "gpio28", "gpio29", 4841 "gpio30"; 4842 function = "qup0"; 4843 }; 4844 4845 qup_spi1_cs: qup-spi1-cs-state { 4846 pins = "gpio7"; 4847 function = "qup1"; 4848 }; 4849 4850 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4851 pins = "gpio7"; 4852 function = "gpio"; 4853 }; 4854 4855 qup_spi1_data_clk: qup-spi1-data-clk-state { 4856 pins = "gpio4", "gpio5", 4857 "gpio6"; 4858 function = "qup1"; 4859 }; 4860 4861 qup_spi2_cs: qup-spi2-cs-state { 4862 pins = "gpio118"; 4863 function = "qup2"; 4864 }; 4865 4866 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4867 pins = "gpio118"; 4868 function = "gpio"; 4869 }; 4870 4871 qup_spi2_data_clk: qup-spi2-data-clk-state { 4872 pins = "gpio115", "gpio116", 4873 "gpio117"; 4874 function = "qup2"; 4875 }; 4876 4877 qup_spi3_cs: qup-spi3-cs-state { 4878 pins = "gpio122"; 4879 function = "qup3"; 4880 }; 4881 4882 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4883 pins = "gpio122"; 4884 function = "gpio"; 4885 }; 4886 4887 qup_spi3_data_clk: qup-spi3-data-clk-state { 4888 pins = "gpio119", "gpio120", 4889 "gpio121"; 4890 function = "qup3"; 4891 }; 4892 4893 qup_spi4_cs: qup-spi4-cs-state { 4894 pins = "gpio11"; 4895 function = "qup4"; 4896 }; 4897 4898 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4899 pins = "gpio11"; 4900 function = "gpio"; 4901 }; 4902 4903 qup_spi4_data_clk: qup-spi4-data-clk-state { 4904 pins = "gpio8", "gpio9", 4905 "gpio10"; 4906 function = "qup4"; 4907 }; 4908 4909 qup_spi5_cs: qup-spi5-cs-state { 4910 pins = "gpio15"; 4911 function = "qup5"; 4912 }; 4913 4914 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4915 pins = "gpio15"; 4916 function = "gpio"; 4917 }; 4918 4919 qup_spi5_data_clk: qup-spi5-data-clk-state { 4920 pins = "gpio12", "gpio13", 4921 "gpio14"; 4922 function = "qup5"; 4923 }; 4924 4925 qup_spi6_cs: qup-spi6-cs-state { 4926 pins = "gpio19"; 4927 function = "qup6"; 4928 }; 4929 4930 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4931 pins = "gpio19"; 4932 function = "gpio"; 4933 }; 4934 4935 qup_spi6_data_clk: qup-spi6-data-clk-state { 4936 pins = "gpio16", "gpio17", 4937 "gpio18"; 4938 function = "qup6"; 4939 }; 4940 4941 qup_spi7_cs: qup-spi7-cs-state { 4942 pins = "gpio23"; 4943 function = "qup7"; 4944 }; 4945 4946 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4947 pins = "gpio23"; 4948 function = "gpio"; 4949 }; 4950 4951 qup_spi7_data_clk: qup-spi7-data-clk-state { 4952 pins = "gpio20", "gpio21", 4953 "gpio22"; 4954 function = "qup7"; 4955 }; 4956 4957 qup_spi8_cs: qup-spi8-cs-state { 4958 pins = "gpio27"; 4959 function = "qup8"; 4960 }; 4961 4962 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4963 pins = "gpio27"; 4964 function = "gpio"; 4965 }; 4966 4967 qup_spi8_data_clk: qup-spi8-data-clk-state { 4968 pins = "gpio24", "gpio25", 4969 "gpio26"; 4970 function = "qup8"; 4971 }; 4972 4973 qup_spi9_cs: qup-spi9-cs-state { 4974 pins = "gpio128"; 4975 function = "qup9"; 4976 }; 4977 4978 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4979 pins = "gpio128"; 4980 function = "gpio"; 4981 }; 4982 4983 qup_spi9_data_clk: qup-spi9-data-clk-state { 4984 pins = "gpio125", "gpio126", 4985 "gpio127"; 4986 function = "qup9"; 4987 }; 4988 4989 qup_spi10_cs: qup-spi10-cs-state { 4990 pins = "gpio132"; 4991 function = "qup10"; 4992 }; 4993 4994 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4995 pins = "gpio132"; 4996 function = "gpio"; 4997 }; 4998 4999 qup_spi10_data_clk: qup-spi10-data-clk-state { 5000 pins = "gpio129", "gpio130", 5001 "gpio131"; 5002 function = "qup10"; 5003 }; 5004 5005 qup_spi11_cs: qup-spi11-cs-state { 5006 pins = "gpio63"; 5007 function = "qup11"; 5008 }; 5009 5010 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 5011 pins = "gpio63"; 5012 function = "gpio"; 5013 }; 5014 5015 qup_spi11_data_clk: qup-spi11-data-clk-state { 5016 pins = "gpio60", "gpio61", 5017 "gpio62"; 5018 function = "qup11"; 5019 }; 5020 5021 qup_spi12_cs: qup-spi12-cs-state { 5022 pins = "gpio35"; 5023 function = "qup12"; 5024 }; 5025 5026 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 5027 pins = "gpio35"; 5028 function = "gpio"; 5029 }; 5030 5031 qup_spi12_data_clk: qup-spi12-data-clk-state { 5032 pins = "gpio32", "gpio33", 5033 "gpio34"; 5034 function = "qup12"; 5035 }; 5036 5037 qup_spi13_cs: qup-spi13-cs-state { 5038 pins = "gpio39"; 5039 function = "qup13"; 5040 }; 5041 5042 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 5043 pins = "gpio39"; 5044 function = "gpio"; 5045 }; 5046 5047 qup_spi13_data_clk: qup-spi13-data-clk-state { 5048 pins = "gpio36", "gpio37", 5049 "gpio38"; 5050 function = "qup13"; 5051 }; 5052 5053 qup_spi14_cs: qup-spi14-cs-state { 5054 pins = "gpio43"; 5055 function = "qup14"; 5056 }; 5057 5058 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 5059 pins = "gpio43"; 5060 function = "gpio"; 5061 }; 5062 5063 qup_spi14_data_clk: qup-spi14-data-clk-state { 5064 pins = "gpio40", "gpio41", 5065 "gpio42"; 5066 function = "qup14"; 5067 }; 5068 5069 qup_spi15_cs: qup-spi15-cs-state { 5070 pins = "gpio47"; 5071 function = "qup15"; 5072 }; 5073 5074 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 5075 pins = "gpio47"; 5076 function = "gpio"; 5077 }; 5078 5079 qup_spi15_data_clk: qup-spi15-data-clk-state { 5080 pins = "gpio44", "gpio45", 5081 "gpio46"; 5082 function = "qup15"; 5083 }; 5084 5085 qup_spi16_cs: qup-spi16-cs-state { 5086 pins = "gpio51"; 5087 function = "qup16"; 5088 }; 5089 5090 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 5091 pins = "gpio51"; 5092 function = "gpio"; 5093 }; 5094 5095 qup_spi16_data_clk: qup-spi16-data-clk-state { 5096 pins = "gpio48", "gpio49", 5097 "gpio50"; 5098 function = "qup16"; 5099 }; 5100 5101 qup_spi17_cs: qup-spi17-cs-state { 5102 pins = "gpio55"; 5103 function = "qup17"; 5104 }; 5105 5106 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state { 5107 pins = "gpio55"; 5108 function = "gpio"; 5109 }; 5110 5111 qup_spi17_data_clk: qup-spi17-data-clk-state { 5112 pins = "gpio52", "gpio53", 5113 "gpio54"; 5114 function = "qup17"; 5115 }; 5116 5117 qup_spi18_cs: qup-spi18-cs-state { 5118 pins = "gpio59"; 5119 function = "qup18"; 5120 }; 5121 5122 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state { 5123 pins = "gpio59"; 5124 function = "gpio"; 5125 }; 5126 5127 qup_spi18_data_clk: qup-spi18-data-clk-state { 5128 pins = "gpio56", "gpio57", 5129 "gpio58"; 5130 function = "qup18"; 5131 }; 5132 5133 qup_spi19_cs: qup-spi19-cs-state { 5134 pins = "gpio3"; 5135 function = "qup19"; 5136 }; 5137 5138 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state { 5139 pins = "gpio3"; 5140 function = "gpio"; 5141 }; 5142 5143 qup_spi19_data_clk: qup-spi19-data-clk-state { 5144 pins = "gpio0", "gpio1", 5145 "gpio2"; 5146 function = "qup19"; 5147 }; 5148 5149 qup_uart2_default: qup-uart2-default-state { 5150 pins = "gpio117", "gpio118"; 5151 function = "qup2"; 5152 }; 5153 5154 qup_uart6_default: qup-uart6-default-state { 5155 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 5156 function = "qup6"; 5157 }; 5158 5159 qup_uart12_default: qup-uart12-default-state { 5160 pins = "gpio34", "gpio35"; 5161 function = "qup12"; 5162 }; 5163 5164 qup_uart17_default: qup-uart17-default-state { 5165 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 5166 function = "qup17"; 5167 }; 5168 5169 qup_uart18_default: qup-uart18-default-state { 5170 pins = "gpio58", "gpio59"; 5171 function = "qup18"; 5172 }; 5173 5174 tert_mi2s_active: tert-mi2s-active-state { 5175 sck-pins { 5176 pins = "gpio133"; 5177 function = "mi2s2_sck"; 5178 drive-strength = <8>; 5179 bias-disable; 5180 }; 5181 5182 data0-pins { 5183 pins = "gpio134"; 5184 function = "mi2s2_data0"; 5185 drive-strength = <8>; 5186 bias-disable; 5187 output-high; 5188 }; 5189 5190 ws-pins { 5191 pins = "gpio135"; 5192 function = "mi2s2_ws"; 5193 drive-strength = <8>; 5194 output-high; 5195 }; 5196 }; 5197 5198 sdc2_sleep_state: sdc2-sleep-state { 5199 clk-pins { 5200 pins = "sdc2_clk"; 5201 drive-strength = <2>; 5202 bias-disable; 5203 }; 5204 5205 cmd-pins { 5206 pins = "sdc2_cmd"; 5207 drive-strength = <2>; 5208 bias-pull-up; 5209 }; 5210 5211 data-pins { 5212 pins = "sdc2_data"; 5213 drive-strength = <2>; 5214 bias-pull-up; 5215 }; 5216 }; 5217 5218 pcie0_default_state: pcie0-default-state { 5219 perst-pins { 5220 pins = "gpio79"; 5221 function = "gpio"; 5222 drive-strength = <2>; 5223 bias-pull-down; 5224 }; 5225 5226 clkreq-pins { 5227 pins = "gpio80"; 5228 function = "pci_e0"; 5229 drive-strength = <2>; 5230 bias-pull-up; 5231 }; 5232 5233 wake-pins { 5234 pins = "gpio81"; 5235 function = "gpio"; 5236 drive-strength = <2>; 5237 bias-pull-up; 5238 }; 5239 }; 5240 5241 pcie1_default_state: pcie1-default-state { 5242 perst-pins { 5243 pins = "gpio82"; 5244 function = "gpio"; 5245 drive-strength = <2>; 5246 bias-pull-down; 5247 }; 5248 5249 clkreq-pins { 5250 pins = "gpio83"; 5251 function = "pci_e1"; 5252 drive-strength = <2>; 5253 bias-pull-up; 5254 }; 5255 5256 wake-pins { 5257 pins = "gpio84"; 5258 function = "gpio"; 5259 drive-strength = <2>; 5260 bias-pull-up; 5261 }; 5262 }; 5263 5264 pcie2_default_state: pcie2-default-state { 5265 perst-pins { 5266 pins = "gpio85"; 5267 function = "gpio"; 5268 drive-strength = <2>; 5269 bias-pull-down; 5270 }; 5271 5272 clkreq-pins { 5273 pins = "gpio86"; 5274 function = "pci_e2"; 5275 drive-strength = <2>; 5276 bias-pull-up; 5277 }; 5278 5279 wake-pins { 5280 pins = "gpio87"; 5281 function = "gpio"; 5282 drive-strength = <2>; 5283 bias-pull-up; 5284 }; 5285 }; 5286 }; 5287 5288 apps_smmu: iommu@15000000 { 5289 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5290 reg = <0 0x15000000 0 0x100000>; 5291 #iommu-cells = <2>; 5292 #global-interrupts = <2>; 5293 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 5294 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5295 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5296 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5297 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5298 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5299 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5300 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5301 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5302 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5303 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5304 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5305 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5306 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5307 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5308 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5309 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5310 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5311 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5312 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5313 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5314 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5315 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5316 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5317 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5318 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5319 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5320 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5321 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5322 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5323 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5324 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5325 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5326 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5327 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5328 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5329 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5330 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5331 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5332 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5333 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5334 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5335 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5336 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5337 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5338 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5339 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5340 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5341 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5342 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5343 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5344 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5345 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5346 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5347 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5348 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5349 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5350 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5351 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5352 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5353 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5354 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5355 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5356 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5357 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5358 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5359 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5360 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5361 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5362 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5363 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5364 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5365 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5366 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5367 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5368 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5369 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5370 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5371 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5372 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5373 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5374 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5375 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5376 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5377 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5378 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5379 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5380 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5381 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5382 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5383 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5384 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5385 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5386 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5387 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5388 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5389 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 5390 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 5391 }; 5392 5393 adsp: remoteproc@17300000 { 5394 compatible = "qcom,sm8250-adsp-pas"; 5395 reg = <0 0x17300000 0 0x100>; 5396 5397 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 5398 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 5399 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 5400 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 5401 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 5402 interrupt-names = "wdog", "fatal", "ready", 5403 "handover", "stop-ack"; 5404 5405 clocks = <&rpmhcc RPMH_CXO_CLK>; 5406 clock-names = "xo"; 5407 5408 power-domains = <&rpmhpd SM8250_LCX>, 5409 <&rpmhpd SM8250_LMX>; 5410 power-domain-names = "lcx", "lmx"; 5411 5412 memory-region = <&adsp_mem>; 5413 5414 qcom,qmp = <&aoss_qmp>; 5415 5416 qcom,smem-states = <&smp2p_adsp_out 0>; 5417 qcom,smem-state-names = "stop"; 5418 5419 status = "disabled"; 5420 5421 glink-edge { 5422 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 5423 IPCC_MPROC_SIGNAL_GLINK_QMP 5424 IRQ_TYPE_EDGE_RISING>; 5425 mboxes = <&ipcc IPCC_CLIENT_LPASS 5426 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5427 5428 label = "lpass"; 5429 qcom,remote-pid = <2>; 5430 5431 apr { 5432 compatible = "qcom,apr-v2"; 5433 qcom,glink-channels = "apr_audio_svc"; 5434 qcom,domain = <APR_DOMAIN_ADSP>; 5435 #address-cells = <1>; 5436 #size-cells = <0>; 5437 5438 service@3 { 5439 reg = <APR_SVC_ADSP_CORE>; 5440 compatible = "qcom,q6core"; 5441 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5442 }; 5443 5444 q6afe: service@4 { 5445 compatible = "qcom,q6afe"; 5446 reg = <APR_SVC_AFE>; 5447 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5448 q6afedai: dais { 5449 compatible = "qcom,q6afe-dais"; 5450 #address-cells = <1>; 5451 #size-cells = <0>; 5452 #sound-dai-cells = <1>; 5453 }; 5454 5455 q6afecc: clock-controller { 5456 compatible = "qcom,q6afe-clocks"; 5457 #clock-cells = <2>; 5458 }; 5459 }; 5460 5461 q6asm: service@7 { 5462 compatible = "qcom,q6asm"; 5463 reg = <APR_SVC_ASM>; 5464 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5465 q6asmdai: dais { 5466 compatible = "qcom,q6asm-dais"; 5467 #address-cells = <1>; 5468 #size-cells = <0>; 5469 #sound-dai-cells = <1>; 5470 iommus = <&apps_smmu 0x1801 0x0>; 5471 }; 5472 }; 5473 5474 q6adm: service@8 { 5475 compatible = "qcom,q6adm"; 5476 reg = <APR_SVC_ADM>; 5477 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5478 q6routing: routing { 5479 compatible = "qcom,q6adm-routing"; 5480 #sound-dai-cells = <0>; 5481 }; 5482 }; 5483 }; 5484 5485 fastrpc { 5486 compatible = "qcom,fastrpc"; 5487 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5488 label = "adsp"; 5489 qcom,non-secure-domain; 5490 #address-cells = <1>; 5491 #size-cells = <0>; 5492 5493 compute-cb@3 { 5494 compatible = "qcom,fastrpc-compute-cb"; 5495 reg = <3>; 5496 iommus = <&apps_smmu 0x1803 0x0>; 5497 }; 5498 5499 compute-cb@4 { 5500 compatible = "qcom,fastrpc-compute-cb"; 5501 reg = <4>; 5502 iommus = <&apps_smmu 0x1804 0x0>; 5503 }; 5504 5505 compute-cb@5 { 5506 compatible = "qcom,fastrpc-compute-cb"; 5507 reg = <5>; 5508 iommus = <&apps_smmu 0x1805 0x0>; 5509 }; 5510 }; 5511 }; 5512 }; 5513 5514 intc: interrupt-controller@17a00000 { 5515 compatible = "arm,gic-v3"; 5516 #interrupt-cells = <3>; 5517 interrupt-controller; 5518 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 5519 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 5520 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5521 }; 5522 5523 watchdog@17c10000 { 5524 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 5525 reg = <0 0x17c10000 0 0x1000>; 5526 clocks = <&sleep_clk>; 5527 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5528 }; 5529 5530 timer@17c20000 { 5531 #address-cells = <1>; 5532 #size-cells = <1>; 5533 ranges = <0 0 0 0x20000000>; 5534 compatible = "arm,armv7-timer-mem"; 5535 reg = <0x0 0x17c20000 0x0 0x1000>; 5536 clock-frequency = <19200000>; 5537 5538 frame@17c21000 { 5539 frame-number = <0>; 5540 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5541 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5542 reg = <0x17c21000 0x1000>, 5543 <0x17c22000 0x1000>; 5544 }; 5545 5546 frame@17c23000 { 5547 frame-number = <1>; 5548 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5549 reg = <0x17c23000 0x1000>; 5550 status = "disabled"; 5551 }; 5552 5553 frame@17c25000 { 5554 frame-number = <2>; 5555 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5556 reg = <0x17c25000 0x1000>; 5557 status = "disabled"; 5558 }; 5559 5560 frame@17c27000 { 5561 frame-number = <3>; 5562 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5563 reg = <0x17c27000 0x1000>; 5564 status = "disabled"; 5565 }; 5566 5567 frame@17c29000 { 5568 frame-number = <4>; 5569 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5570 reg = <0x17c29000 0x1000>; 5571 status = "disabled"; 5572 }; 5573 5574 frame@17c2b000 { 5575 frame-number = <5>; 5576 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5577 reg = <0x17c2b000 0x1000>; 5578 status = "disabled"; 5579 }; 5580 5581 frame@17c2d000 { 5582 frame-number = <6>; 5583 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5584 reg = <0x17c2d000 0x1000>; 5585 status = "disabled"; 5586 }; 5587 }; 5588 5589 apps_rsc: rsc@18200000 { 5590 label = "apps_rsc"; 5591 compatible = "qcom,rpmh-rsc"; 5592 reg = <0x0 0x18200000 0x0 0x10000>, 5593 <0x0 0x18210000 0x0 0x10000>, 5594 <0x0 0x18220000 0x0 0x10000>; 5595 reg-names = "drv-0", "drv-1", "drv-2"; 5596 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5597 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5598 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5599 qcom,tcs-offset = <0xd00>; 5600 qcom,drv-id = <2>; 5601 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 5602 <WAKE_TCS 3>, <CONTROL_TCS 1>; 5603 power-domains = <&CLUSTER_PD>; 5604 5605 rpmhcc: clock-controller { 5606 compatible = "qcom,sm8250-rpmh-clk"; 5607 #clock-cells = <1>; 5608 clock-names = "xo"; 5609 clocks = <&xo_board>; 5610 }; 5611 5612 rpmhpd: power-controller { 5613 compatible = "qcom,sm8250-rpmhpd"; 5614 #power-domain-cells = <1>; 5615 operating-points-v2 = <&rpmhpd_opp_table>; 5616 5617 rpmhpd_opp_table: opp-table { 5618 compatible = "operating-points-v2"; 5619 5620 rpmhpd_opp_ret: opp1 { 5621 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5622 }; 5623 5624 rpmhpd_opp_min_svs: opp2 { 5625 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5626 }; 5627 5628 rpmhpd_opp_low_svs: opp3 { 5629 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5630 }; 5631 5632 rpmhpd_opp_svs: opp4 { 5633 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5634 }; 5635 5636 rpmhpd_opp_svs_l1: opp5 { 5637 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5638 }; 5639 5640 rpmhpd_opp_nom: opp6 { 5641 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5642 }; 5643 5644 rpmhpd_opp_nom_l1: opp7 { 5645 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5646 }; 5647 5648 rpmhpd_opp_nom_l2: opp8 { 5649 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5650 }; 5651 5652 rpmhpd_opp_turbo: opp9 { 5653 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5654 }; 5655 5656 rpmhpd_opp_turbo_l1: opp10 { 5657 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5658 }; 5659 }; 5660 }; 5661 5662 apps_bcm_voter: bcm-voter { 5663 compatible = "qcom,bcm-voter"; 5664 }; 5665 }; 5666 5667 epss_l3: interconnect@18590000 { 5668 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3"; 5669 reg = <0 0x18590000 0 0x1000>; 5670 5671 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5672 clock-names = "xo", "alternate"; 5673 5674 #interconnect-cells = <1>; 5675 }; 5676 5677 cpufreq_hw: cpufreq@18591000 { 5678 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 5679 reg = <0 0x18591000 0 0x1000>, 5680 <0 0x18592000 0 0x1000>, 5681 <0 0x18593000 0 0x1000>; 5682 reg-names = "freq-domain0", "freq-domain1", 5683 "freq-domain2"; 5684 5685 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5686 clock-names = "xo", "alternate"; 5687 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5688 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5689 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5690 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 5691 #freq-domain-cells = <1>; 5692 #clock-cells = <1>; 5693 }; 5694 }; 5695 5696 sound: sound { 5697 }; 5698 5699 timer { 5700 compatible = "arm,armv8-timer"; 5701 interrupts = <GIC_PPI 13 5702 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5703 <GIC_PPI 14 5704 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5705 <GIC_PPI 11 5706 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5707 <GIC_PPI 10 5708 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5709 }; 5710 5711 thermal-zones { 5712 cpu0-thermal { 5713 polling-delay-passive = <250>; 5714 polling-delay = <1000>; 5715 5716 thermal-sensors = <&tsens0 1>; 5717 5718 trips { 5719 cpu0_alert0: trip-point0 { 5720 temperature = <90000>; 5721 hysteresis = <2000>; 5722 type = "passive"; 5723 }; 5724 5725 cpu0_alert1: trip-point1 { 5726 temperature = <95000>; 5727 hysteresis = <2000>; 5728 type = "passive"; 5729 }; 5730 5731 cpu0_crit: cpu-crit { 5732 temperature = <110000>; 5733 hysteresis = <1000>; 5734 type = "critical"; 5735 }; 5736 }; 5737 5738 cooling-maps { 5739 map0 { 5740 trip = <&cpu0_alert0>; 5741 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5742 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5743 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5744 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5745 }; 5746 map1 { 5747 trip = <&cpu0_alert1>; 5748 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5749 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5750 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5751 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5752 }; 5753 }; 5754 }; 5755 5756 cpu1-thermal { 5757 polling-delay-passive = <250>; 5758 polling-delay = <1000>; 5759 5760 thermal-sensors = <&tsens0 2>; 5761 5762 trips { 5763 cpu1_alert0: trip-point0 { 5764 temperature = <90000>; 5765 hysteresis = <2000>; 5766 type = "passive"; 5767 }; 5768 5769 cpu1_alert1: trip-point1 { 5770 temperature = <95000>; 5771 hysteresis = <2000>; 5772 type = "passive"; 5773 }; 5774 5775 cpu1_crit: cpu-crit { 5776 temperature = <110000>; 5777 hysteresis = <1000>; 5778 type = "critical"; 5779 }; 5780 }; 5781 5782 cooling-maps { 5783 map0 { 5784 trip = <&cpu1_alert0>; 5785 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5786 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5787 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5788 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5789 }; 5790 map1 { 5791 trip = <&cpu1_alert1>; 5792 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5793 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5794 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5795 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5796 }; 5797 }; 5798 }; 5799 5800 cpu2-thermal { 5801 polling-delay-passive = <250>; 5802 polling-delay = <1000>; 5803 5804 thermal-sensors = <&tsens0 3>; 5805 5806 trips { 5807 cpu2_alert0: trip-point0 { 5808 temperature = <90000>; 5809 hysteresis = <2000>; 5810 type = "passive"; 5811 }; 5812 5813 cpu2_alert1: trip-point1 { 5814 temperature = <95000>; 5815 hysteresis = <2000>; 5816 type = "passive"; 5817 }; 5818 5819 cpu2_crit: cpu-crit { 5820 temperature = <110000>; 5821 hysteresis = <1000>; 5822 type = "critical"; 5823 }; 5824 }; 5825 5826 cooling-maps { 5827 map0 { 5828 trip = <&cpu2_alert0>; 5829 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5830 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5831 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5832 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5833 }; 5834 map1 { 5835 trip = <&cpu2_alert1>; 5836 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5837 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5838 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5839 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5840 }; 5841 }; 5842 }; 5843 5844 cpu3-thermal { 5845 polling-delay-passive = <250>; 5846 polling-delay = <1000>; 5847 5848 thermal-sensors = <&tsens0 4>; 5849 5850 trips { 5851 cpu3_alert0: trip-point0 { 5852 temperature = <90000>; 5853 hysteresis = <2000>; 5854 type = "passive"; 5855 }; 5856 5857 cpu3_alert1: trip-point1 { 5858 temperature = <95000>; 5859 hysteresis = <2000>; 5860 type = "passive"; 5861 }; 5862 5863 cpu3_crit: cpu-crit { 5864 temperature = <110000>; 5865 hysteresis = <1000>; 5866 type = "critical"; 5867 }; 5868 }; 5869 5870 cooling-maps { 5871 map0 { 5872 trip = <&cpu3_alert0>; 5873 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5874 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5875 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5876 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5877 }; 5878 map1 { 5879 trip = <&cpu3_alert1>; 5880 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5881 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5882 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5883 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5884 }; 5885 }; 5886 }; 5887 5888 cpu4-top-thermal { 5889 polling-delay-passive = <250>; 5890 polling-delay = <1000>; 5891 5892 thermal-sensors = <&tsens0 7>; 5893 5894 trips { 5895 cpu4_top_alert0: trip-point0 { 5896 temperature = <90000>; 5897 hysteresis = <2000>; 5898 type = "passive"; 5899 }; 5900 5901 cpu4_top_alert1: trip-point1 { 5902 temperature = <95000>; 5903 hysteresis = <2000>; 5904 type = "passive"; 5905 }; 5906 5907 cpu4_top_crit: cpu-crit { 5908 temperature = <110000>; 5909 hysteresis = <1000>; 5910 type = "critical"; 5911 }; 5912 }; 5913 5914 cooling-maps { 5915 map0 { 5916 trip = <&cpu4_top_alert0>; 5917 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5918 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5919 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5920 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5921 }; 5922 map1 { 5923 trip = <&cpu4_top_alert1>; 5924 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5925 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5926 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5927 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5928 }; 5929 }; 5930 }; 5931 5932 cpu5-top-thermal { 5933 polling-delay-passive = <250>; 5934 polling-delay = <1000>; 5935 5936 thermal-sensors = <&tsens0 8>; 5937 5938 trips { 5939 cpu5_top_alert0: trip-point0 { 5940 temperature = <90000>; 5941 hysteresis = <2000>; 5942 type = "passive"; 5943 }; 5944 5945 cpu5_top_alert1: trip-point1 { 5946 temperature = <95000>; 5947 hysteresis = <2000>; 5948 type = "passive"; 5949 }; 5950 5951 cpu5_top_crit: cpu-crit { 5952 temperature = <110000>; 5953 hysteresis = <1000>; 5954 type = "critical"; 5955 }; 5956 }; 5957 5958 cooling-maps { 5959 map0 { 5960 trip = <&cpu5_top_alert0>; 5961 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5962 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5963 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5964 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5965 }; 5966 map1 { 5967 trip = <&cpu5_top_alert1>; 5968 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5969 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5970 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5971 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5972 }; 5973 }; 5974 }; 5975 5976 cpu6-top-thermal { 5977 polling-delay-passive = <250>; 5978 polling-delay = <1000>; 5979 5980 thermal-sensors = <&tsens0 9>; 5981 5982 trips { 5983 cpu6_top_alert0: trip-point0 { 5984 temperature = <90000>; 5985 hysteresis = <2000>; 5986 type = "passive"; 5987 }; 5988 5989 cpu6_top_alert1: trip-point1 { 5990 temperature = <95000>; 5991 hysteresis = <2000>; 5992 type = "passive"; 5993 }; 5994 5995 cpu6_top_crit: cpu-crit { 5996 temperature = <110000>; 5997 hysteresis = <1000>; 5998 type = "critical"; 5999 }; 6000 }; 6001 6002 cooling-maps { 6003 map0 { 6004 trip = <&cpu6_top_alert0>; 6005 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6006 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6007 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6008 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6009 }; 6010 map1 { 6011 trip = <&cpu6_top_alert1>; 6012 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6013 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6014 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6015 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6016 }; 6017 }; 6018 }; 6019 6020 cpu7-top-thermal { 6021 polling-delay-passive = <250>; 6022 polling-delay = <1000>; 6023 6024 thermal-sensors = <&tsens0 10>; 6025 6026 trips { 6027 cpu7_top_alert0: trip-point0 { 6028 temperature = <90000>; 6029 hysteresis = <2000>; 6030 type = "passive"; 6031 }; 6032 6033 cpu7_top_alert1: trip-point1 { 6034 temperature = <95000>; 6035 hysteresis = <2000>; 6036 type = "passive"; 6037 }; 6038 6039 cpu7_top_crit: cpu-crit { 6040 temperature = <110000>; 6041 hysteresis = <1000>; 6042 type = "critical"; 6043 }; 6044 }; 6045 6046 cooling-maps { 6047 map0 { 6048 trip = <&cpu7_top_alert0>; 6049 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6050 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6051 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6052 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6053 }; 6054 map1 { 6055 trip = <&cpu7_top_alert1>; 6056 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6057 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6058 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6059 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6060 }; 6061 }; 6062 }; 6063 6064 cpu4-bottom-thermal { 6065 polling-delay-passive = <250>; 6066 polling-delay = <1000>; 6067 6068 thermal-sensors = <&tsens0 11>; 6069 6070 trips { 6071 cpu4_bottom_alert0: trip-point0 { 6072 temperature = <90000>; 6073 hysteresis = <2000>; 6074 type = "passive"; 6075 }; 6076 6077 cpu4_bottom_alert1: trip-point1 { 6078 temperature = <95000>; 6079 hysteresis = <2000>; 6080 type = "passive"; 6081 }; 6082 6083 cpu4_bottom_crit: cpu-crit { 6084 temperature = <110000>; 6085 hysteresis = <1000>; 6086 type = "critical"; 6087 }; 6088 }; 6089 6090 cooling-maps { 6091 map0 { 6092 trip = <&cpu4_bottom_alert0>; 6093 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6094 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6095 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6096 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6097 }; 6098 map1 { 6099 trip = <&cpu4_bottom_alert1>; 6100 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6101 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6102 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6103 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6104 }; 6105 }; 6106 }; 6107 6108 cpu5-bottom-thermal { 6109 polling-delay-passive = <250>; 6110 polling-delay = <1000>; 6111 6112 thermal-sensors = <&tsens0 12>; 6113 6114 trips { 6115 cpu5_bottom_alert0: trip-point0 { 6116 temperature = <90000>; 6117 hysteresis = <2000>; 6118 type = "passive"; 6119 }; 6120 6121 cpu5_bottom_alert1: trip-point1 { 6122 temperature = <95000>; 6123 hysteresis = <2000>; 6124 type = "passive"; 6125 }; 6126 6127 cpu5_bottom_crit: cpu-crit { 6128 temperature = <110000>; 6129 hysteresis = <1000>; 6130 type = "critical"; 6131 }; 6132 }; 6133 6134 cooling-maps { 6135 map0 { 6136 trip = <&cpu5_bottom_alert0>; 6137 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6138 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6139 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6140 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6141 }; 6142 map1 { 6143 trip = <&cpu5_bottom_alert1>; 6144 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6145 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6146 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6147 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6148 }; 6149 }; 6150 }; 6151 6152 cpu6-bottom-thermal { 6153 polling-delay-passive = <250>; 6154 polling-delay = <1000>; 6155 6156 thermal-sensors = <&tsens0 13>; 6157 6158 trips { 6159 cpu6_bottom_alert0: trip-point0 { 6160 temperature = <90000>; 6161 hysteresis = <2000>; 6162 type = "passive"; 6163 }; 6164 6165 cpu6_bottom_alert1: trip-point1 { 6166 temperature = <95000>; 6167 hysteresis = <2000>; 6168 type = "passive"; 6169 }; 6170 6171 cpu6_bottom_crit: cpu-crit { 6172 temperature = <110000>; 6173 hysteresis = <1000>; 6174 type = "critical"; 6175 }; 6176 }; 6177 6178 cooling-maps { 6179 map0 { 6180 trip = <&cpu6_bottom_alert0>; 6181 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6182 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6183 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6184 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6185 }; 6186 map1 { 6187 trip = <&cpu6_bottom_alert1>; 6188 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6189 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6190 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6191 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6192 }; 6193 }; 6194 }; 6195 6196 cpu7-bottom-thermal { 6197 polling-delay-passive = <250>; 6198 polling-delay = <1000>; 6199 6200 thermal-sensors = <&tsens0 14>; 6201 6202 trips { 6203 cpu7_bottom_alert0: trip-point0 { 6204 temperature = <90000>; 6205 hysteresis = <2000>; 6206 type = "passive"; 6207 }; 6208 6209 cpu7_bottom_alert1: trip-point1 { 6210 temperature = <95000>; 6211 hysteresis = <2000>; 6212 type = "passive"; 6213 }; 6214 6215 cpu7_bottom_crit: cpu-crit { 6216 temperature = <110000>; 6217 hysteresis = <1000>; 6218 type = "critical"; 6219 }; 6220 }; 6221 6222 cooling-maps { 6223 map0 { 6224 trip = <&cpu7_bottom_alert0>; 6225 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6226 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6227 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6228 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6229 }; 6230 map1 { 6231 trip = <&cpu7_bottom_alert1>; 6232 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6233 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6234 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6235 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6236 }; 6237 }; 6238 }; 6239 6240 aoss0-thermal { 6241 polling-delay-passive = <250>; 6242 polling-delay = <1000>; 6243 6244 thermal-sensors = <&tsens0 0>; 6245 6246 trips { 6247 aoss0_alert0: trip-point0 { 6248 temperature = <90000>; 6249 hysteresis = <2000>; 6250 type = "hot"; 6251 }; 6252 }; 6253 }; 6254 6255 cluster0-thermal { 6256 polling-delay-passive = <250>; 6257 polling-delay = <1000>; 6258 6259 thermal-sensors = <&tsens0 5>; 6260 6261 trips { 6262 cluster0_alert0: trip-point0 { 6263 temperature = <90000>; 6264 hysteresis = <2000>; 6265 type = "hot"; 6266 }; 6267 cluster0_crit: cluster0_crit { 6268 temperature = <110000>; 6269 hysteresis = <2000>; 6270 type = "critical"; 6271 }; 6272 }; 6273 }; 6274 6275 cluster1-thermal { 6276 polling-delay-passive = <250>; 6277 polling-delay = <1000>; 6278 6279 thermal-sensors = <&tsens0 6>; 6280 6281 trips { 6282 cluster1_alert0: trip-point0 { 6283 temperature = <90000>; 6284 hysteresis = <2000>; 6285 type = "hot"; 6286 }; 6287 cluster1_crit: cluster1_crit { 6288 temperature = <110000>; 6289 hysteresis = <2000>; 6290 type = "critical"; 6291 }; 6292 }; 6293 }; 6294 6295 gpu-top-thermal { 6296 polling-delay-passive = <250>; 6297 polling-delay = <1000>; 6298 6299 thermal-sensors = <&tsens0 15>; 6300 6301 trips { 6302 gpu1_alert0: trip-point0 { 6303 temperature = <90000>; 6304 hysteresis = <2000>; 6305 type = "hot"; 6306 }; 6307 }; 6308 }; 6309 6310 aoss1-thermal { 6311 polling-delay-passive = <250>; 6312 polling-delay = <1000>; 6313 6314 thermal-sensors = <&tsens1 0>; 6315 6316 trips { 6317 aoss1_alert0: trip-point0 { 6318 temperature = <90000>; 6319 hysteresis = <2000>; 6320 type = "hot"; 6321 }; 6322 }; 6323 }; 6324 6325 wlan-thermal { 6326 polling-delay-passive = <250>; 6327 polling-delay = <1000>; 6328 6329 thermal-sensors = <&tsens1 1>; 6330 6331 trips { 6332 wlan_alert0: trip-point0 { 6333 temperature = <90000>; 6334 hysteresis = <2000>; 6335 type = "hot"; 6336 }; 6337 }; 6338 }; 6339 6340 video-thermal { 6341 polling-delay-passive = <250>; 6342 polling-delay = <1000>; 6343 6344 thermal-sensors = <&tsens1 2>; 6345 6346 trips { 6347 video_alert0: trip-point0 { 6348 temperature = <90000>; 6349 hysteresis = <2000>; 6350 type = "hot"; 6351 }; 6352 }; 6353 }; 6354 6355 mem-thermal { 6356 polling-delay-passive = <250>; 6357 polling-delay = <1000>; 6358 6359 thermal-sensors = <&tsens1 3>; 6360 6361 trips { 6362 mem_alert0: trip-point0 { 6363 temperature = <90000>; 6364 hysteresis = <2000>; 6365 type = "hot"; 6366 }; 6367 }; 6368 }; 6369 6370 q6-hvx-thermal { 6371 polling-delay-passive = <250>; 6372 polling-delay = <1000>; 6373 6374 thermal-sensors = <&tsens1 4>; 6375 6376 trips { 6377 q6_hvx_alert0: trip-point0 { 6378 temperature = <90000>; 6379 hysteresis = <2000>; 6380 type = "hot"; 6381 }; 6382 }; 6383 }; 6384 6385 camera-thermal { 6386 polling-delay-passive = <250>; 6387 polling-delay = <1000>; 6388 6389 thermal-sensors = <&tsens1 5>; 6390 6391 trips { 6392 camera_alert0: trip-point0 { 6393 temperature = <90000>; 6394 hysteresis = <2000>; 6395 type = "hot"; 6396 }; 6397 }; 6398 }; 6399 6400 compute-thermal { 6401 polling-delay-passive = <250>; 6402 polling-delay = <1000>; 6403 6404 thermal-sensors = <&tsens1 6>; 6405 6406 trips { 6407 compute_alert0: trip-point0 { 6408 temperature = <90000>; 6409 hysteresis = <2000>; 6410 type = "hot"; 6411 }; 6412 }; 6413 }; 6414 6415 npu-thermal { 6416 polling-delay-passive = <250>; 6417 polling-delay = <1000>; 6418 6419 thermal-sensors = <&tsens1 7>; 6420 6421 trips { 6422 npu_alert0: trip-point0 { 6423 temperature = <90000>; 6424 hysteresis = <2000>; 6425 type = "hot"; 6426 }; 6427 }; 6428 }; 6429 6430 gpu-bottom-thermal { 6431 polling-delay-passive = <250>; 6432 polling-delay = <1000>; 6433 6434 thermal-sensors = <&tsens1 8>; 6435 6436 trips { 6437 gpu2_alert0: trip-point0 { 6438 temperature = <90000>; 6439 hysteresis = <2000>; 6440 type = "hot"; 6441 }; 6442 }; 6443 }; 6444 }; 6445}; 6446