160378f1aSVenkata Narendra Kumar Gutta// SPDX-License-Identifier: BSD-3-Clause 260378f1aSVenkata Narendra Kumar Gutta/* 360378f1aSVenkata Narendra Kumar Gutta * Copyright (c) 2020, The Linux Foundation. All rights reserved. 460378f1aSVenkata Narendra Kumar Gutta */ 560378f1aSVenkata Narendra Kumar Gutta 660378f1aSVenkata Narendra Kumar Gutta#include <dt-bindings/interrupt-controller/arm-gic.h> 77c1dffd4SDmitry Baryshkov#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8b7e2fba0SBryan O'Donoghue#include <dt-bindings/clock/qcom,gcc-sm8250.h> 90e6aa9dbSJonathan Marek#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 1060378f1aSVenkata Narendra Kumar Gutta#include <dt-bindings/clock/qcom,rpmh.h> 1115049bb5SKonrad Dybcio#include <dt-bindings/dma/qcom-gpi.h> 1275948800SKonrad Dybcio#include <dt-bindings/gpio/gpio.h> 1379a595bbSSibi Sankar#include <dt-bindings/interconnect/qcom,osm-l3.h> 147c1dffd4SDmitry Baryshkov#include <dt-bindings/interconnect/qcom,sm8250.h> 15e5361e75SBjorn Andersson#include <dt-bindings/mailbox/qcom-ipcc.h> 16b6f78e27SBjorn Andersson#include <dt-bindings/power/qcom-rpmpd.h> 1763e10791SSrinivas Kandagatla#include <dt-bindings/soc/qcom,apr.h> 1860378f1aSVenkata Narendra Kumar Gutta#include <dt-bindings/soc/qcom,rpmh-rsc.h> 1963e10791SSrinivas Kandagatla#include <dt-bindings/sound/qcom,q6afe.h> 20bac12f25SAmit Kucheria#include <dt-bindings/thermal/thermal.h> 21ca79a997SBryan O'Donoghue#include <dt-bindings/clock/qcom,camcc-sm8250.h> 225b9ec225Sjonathan@marek.ca#include <dt-bindings/clock/qcom,videocc-sm8250.h> 2360378f1aSVenkata Narendra Kumar Gutta 2460378f1aSVenkata Narendra Kumar Gutta/ { 2560378f1aSVenkata Narendra Kumar Gutta interrupt-parent = <&intc>; 2660378f1aSVenkata Narendra Kumar Gutta 2760378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 2860378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 2960378f1aSVenkata Narendra Kumar Gutta 30e5813b15SDmitry Baryshkov aliases { 31e5813b15SDmitry Baryshkov i2c0 = &i2c0; 32e5813b15SDmitry Baryshkov i2c1 = &i2c1; 33e5813b15SDmitry Baryshkov i2c2 = &i2c2; 34e5813b15SDmitry Baryshkov i2c3 = &i2c3; 35e5813b15SDmitry Baryshkov i2c4 = &i2c4; 36e5813b15SDmitry Baryshkov i2c5 = &i2c5; 37e5813b15SDmitry Baryshkov i2c6 = &i2c6; 38e5813b15SDmitry Baryshkov i2c7 = &i2c7; 39e5813b15SDmitry Baryshkov i2c8 = &i2c8; 40e5813b15SDmitry Baryshkov i2c9 = &i2c9; 41e5813b15SDmitry Baryshkov i2c10 = &i2c10; 42e5813b15SDmitry Baryshkov i2c11 = &i2c11; 43e5813b15SDmitry Baryshkov i2c12 = &i2c12; 44e5813b15SDmitry Baryshkov i2c13 = &i2c13; 45e5813b15SDmitry Baryshkov i2c14 = &i2c14; 46e5813b15SDmitry Baryshkov i2c15 = &i2c15; 47e5813b15SDmitry Baryshkov i2c16 = &i2c16; 48e5813b15SDmitry Baryshkov i2c17 = &i2c17; 49e5813b15SDmitry Baryshkov i2c18 = &i2c18; 50e5813b15SDmitry Baryshkov i2c19 = &i2c19; 51e5813b15SDmitry Baryshkov spi0 = &spi0; 52e5813b15SDmitry Baryshkov spi1 = &spi1; 53e5813b15SDmitry Baryshkov spi2 = &spi2; 54e5813b15SDmitry Baryshkov spi3 = &spi3; 55e5813b15SDmitry Baryshkov spi4 = &spi4; 56e5813b15SDmitry Baryshkov spi5 = &spi5; 57e5813b15SDmitry Baryshkov spi6 = &spi6; 58e5813b15SDmitry Baryshkov spi7 = &spi7; 59e5813b15SDmitry Baryshkov spi8 = &spi8; 60e5813b15SDmitry Baryshkov spi9 = &spi9; 61e5813b15SDmitry Baryshkov spi10 = &spi10; 62e5813b15SDmitry Baryshkov spi11 = &spi11; 63e5813b15SDmitry Baryshkov spi12 = &spi12; 64e5813b15SDmitry Baryshkov spi13 = &spi13; 65e5813b15SDmitry Baryshkov spi14 = &spi14; 66e5813b15SDmitry Baryshkov spi15 = &spi15; 67e5813b15SDmitry Baryshkov spi16 = &spi16; 68e5813b15SDmitry Baryshkov spi17 = &spi17; 69e5813b15SDmitry Baryshkov spi18 = &spi18; 70e5813b15SDmitry Baryshkov spi19 = &spi19; 71e5813b15SDmitry Baryshkov }; 72e5813b15SDmitry Baryshkov 7360378f1aSVenkata Narendra Kumar Gutta chosen { }; 7460378f1aSVenkata Narendra Kumar Gutta 7560378f1aSVenkata Narendra Kumar Gutta clocks { 7660378f1aSVenkata Narendra Kumar Gutta xo_board: xo-board { 7760378f1aSVenkata Narendra Kumar Gutta compatible = "fixed-clock"; 7860378f1aSVenkata Narendra Kumar Gutta #clock-cells = <0>; 7960378f1aSVenkata Narendra Kumar Gutta clock-frequency = <38400000>; 8060378f1aSVenkata Narendra Kumar Gutta clock-output-names = "xo_board"; 8160378f1aSVenkata Narendra Kumar Gutta }; 8260378f1aSVenkata Narendra Kumar Gutta 8360378f1aSVenkata Narendra Kumar Gutta sleep_clk: sleep-clk { 8460378f1aSVenkata Narendra Kumar Gutta compatible = "fixed-clock"; 859ff8b059SJonathan Marek clock-frequency = <32768>; 8660378f1aSVenkata Narendra Kumar Gutta #clock-cells = <0>; 8760378f1aSVenkata Narendra Kumar Gutta }; 8860378f1aSVenkata Narendra Kumar Gutta }; 8960378f1aSVenkata Narendra Kumar Gutta 9060378f1aSVenkata Narendra Kumar Gutta cpus { 9160378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 9260378f1aSVenkata Narendra Kumar Gutta #size-cells = <0>; 9360378f1aSVenkata Narendra Kumar Gutta 9460378f1aSVenkata Narendra Kumar Gutta CPU0: cpu@0 { 9560378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 9660378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 9760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x0>; 9860378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 996aabed55SDanny Lin capacity-dmips-mhz = <448>; 1006aabed55SDanny Lin dynamic-power-coefficient = <205>; 10160378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_0>; 10232bc936dSMaulik Shah power-domains = <&CPU_PD0>; 10332bc936dSMaulik Shah power-domain-names = "psci"; 10402ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 1058e0e8016SThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1068e0e8016SThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1078e0e8016SThara Gopinath <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 108bac12f25SAmit Kucheria #cooling-cells = <2>; 10960378f1aSVenkata Narendra Kumar Gutta L2_0: l2-cache { 11060378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 11160378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 11260378f1aSVenkata Narendra Kumar Gutta L3_0: l3-cache { 11360378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 11460378f1aSVenkata Narendra Kumar Gutta }; 11560378f1aSVenkata Narendra Kumar Gutta }; 11660378f1aSVenkata Narendra Kumar Gutta }; 11760378f1aSVenkata Narendra Kumar Gutta 11860378f1aSVenkata Narendra Kumar Gutta CPU1: cpu@100 { 11960378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 12060378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 12160378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x100>; 12260378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1236aabed55SDanny Lin capacity-dmips-mhz = <448>; 1246aabed55SDanny Lin dynamic-power-coefficient = <205>; 12560378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_100>; 12632bc936dSMaulik Shah power-domains = <&CPU_PD1>; 12732bc936dSMaulik Shah power-domain-names = "psci"; 12802ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 1298e0e8016SThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1308e0e8016SThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1318e0e8016SThara Gopinath <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 132bac12f25SAmit Kucheria #cooling-cells = <2>; 13360378f1aSVenkata Narendra Kumar Gutta L2_100: l2-cache { 13460378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 13560378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 13660378f1aSVenkata Narendra Kumar Gutta }; 13760378f1aSVenkata Narendra Kumar Gutta }; 13860378f1aSVenkata Narendra Kumar Gutta 13960378f1aSVenkata Narendra Kumar Gutta CPU2: cpu@200 { 14060378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 14160378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 14260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x200>; 14360378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1446aabed55SDanny Lin capacity-dmips-mhz = <448>; 1456aabed55SDanny Lin dynamic-power-coefficient = <205>; 14660378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_200>; 14732bc936dSMaulik Shah power-domains = <&CPU_PD2>; 14832bc936dSMaulik Shah power-domain-names = "psci"; 14902ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 1508e0e8016SThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1518e0e8016SThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1528e0e8016SThara Gopinath <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 153bac12f25SAmit Kucheria #cooling-cells = <2>; 15460378f1aSVenkata Narendra Kumar Gutta L2_200: l2-cache { 15560378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 15660378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 15760378f1aSVenkata Narendra Kumar Gutta }; 15860378f1aSVenkata Narendra Kumar Gutta }; 15960378f1aSVenkata Narendra Kumar Gutta 16060378f1aSVenkata Narendra Kumar Gutta CPU3: cpu@300 { 16160378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 16260378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 16360378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x300>; 16460378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1656aabed55SDanny Lin capacity-dmips-mhz = <448>; 1666aabed55SDanny Lin dynamic-power-coefficient = <205>; 16760378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_300>; 16832bc936dSMaulik Shah power-domains = <&CPU_PD3>; 16932bc936dSMaulik Shah power-domain-names = "psci"; 17002ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 1718e0e8016SThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1728e0e8016SThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1738e0e8016SThara Gopinath <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 174bac12f25SAmit Kucheria #cooling-cells = <2>; 17560378f1aSVenkata Narendra Kumar Gutta L2_300: l2-cache { 17660378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 17760378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 17860378f1aSVenkata Narendra Kumar Gutta }; 17960378f1aSVenkata Narendra Kumar Gutta }; 18060378f1aSVenkata Narendra Kumar Gutta 18160378f1aSVenkata Narendra Kumar Gutta CPU4: cpu@400 { 18260378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 18360378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 18460378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x400>; 18560378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1866aabed55SDanny Lin capacity-dmips-mhz = <1024>; 1876aabed55SDanny Lin dynamic-power-coefficient = <379>; 18860378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_400>; 18932bc936dSMaulik Shah power-domains = <&CPU_PD4>; 19032bc936dSMaulik Shah power-domain-names = "psci"; 19102ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 1>; 1928e0e8016SThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1938e0e8016SThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1948e0e8016SThara Gopinath <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 195bac12f25SAmit Kucheria #cooling-cells = <2>; 19660378f1aSVenkata Narendra Kumar Gutta L2_400: l2-cache { 19760378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 19860378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 19960378f1aSVenkata Narendra Kumar Gutta }; 20060378f1aSVenkata Narendra Kumar Gutta }; 20160378f1aSVenkata Narendra Kumar Gutta 20260378f1aSVenkata Narendra Kumar Gutta CPU5: cpu@500 { 20360378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 20460378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 20560378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x500>; 20660378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 2076aabed55SDanny Lin capacity-dmips-mhz = <1024>; 2086aabed55SDanny Lin dynamic-power-coefficient = <379>; 20960378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_500>; 21032bc936dSMaulik Shah power-domains = <&CPU_PD5>; 21132bc936dSMaulik Shah power-domain-names = "psci"; 21202ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 1>; 2138e0e8016SThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 2148e0e8016SThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 2158e0e8016SThara Gopinath <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 216bac12f25SAmit Kucheria #cooling-cells = <2>; 21760378f1aSVenkata Narendra Kumar Gutta L2_500: l2-cache { 21860378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 21960378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 22060378f1aSVenkata Narendra Kumar Gutta }; 22160378f1aSVenkata Narendra Kumar Gutta 22260378f1aSVenkata Narendra Kumar Gutta }; 22360378f1aSVenkata Narendra Kumar Gutta 22460378f1aSVenkata Narendra Kumar Gutta CPU6: cpu@600 { 22560378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 22660378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 22760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x600>; 22860378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 2296aabed55SDanny Lin capacity-dmips-mhz = <1024>; 2306aabed55SDanny Lin dynamic-power-coefficient = <379>; 23160378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_600>; 23232bc936dSMaulik Shah power-domains = <&CPU_PD6>; 23332bc936dSMaulik Shah power-domain-names = "psci"; 23402ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 1>; 2358e0e8016SThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 2368e0e8016SThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 2378e0e8016SThara Gopinath <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 238bac12f25SAmit Kucheria #cooling-cells = <2>; 23960378f1aSVenkata Narendra Kumar Gutta L2_600: l2-cache { 24060378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 24160378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 24260378f1aSVenkata Narendra Kumar Gutta }; 24360378f1aSVenkata Narendra Kumar Gutta }; 24460378f1aSVenkata Narendra Kumar Gutta 24560378f1aSVenkata Narendra Kumar Gutta CPU7: cpu@700 { 24660378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 24760378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 24860378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x700>; 24960378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 2506aabed55SDanny Lin capacity-dmips-mhz = <1024>; 2516aabed55SDanny Lin dynamic-power-coefficient = <444>; 25260378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_700>; 25332bc936dSMaulik Shah power-domains = <&CPU_PD7>; 25432bc936dSMaulik Shah power-domain-names = "psci"; 25502ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 2>; 2568e0e8016SThara Gopinath operating-points-v2 = <&cpu7_opp_table>; 2578e0e8016SThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 2588e0e8016SThara Gopinath <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 259bac12f25SAmit Kucheria #cooling-cells = <2>; 26060378f1aSVenkata Narendra Kumar Gutta L2_700: l2-cache { 26160378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 26260378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 26360378f1aSVenkata Narendra Kumar Gutta }; 26460378f1aSVenkata Narendra Kumar Gutta }; 265b4791e69SDanny Lin 266b4791e69SDanny Lin cpu-map { 267b4791e69SDanny Lin cluster0 { 268b4791e69SDanny Lin core0 { 269b4791e69SDanny Lin cpu = <&CPU0>; 270b4791e69SDanny Lin }; 271b4791e69SDanny Lin 272b4791e69SDanny Lin core1 { 273b4791e69SDanny Lin cpu = <&CPU1>; 274b4791e69SDanny Lin }; 275b4791e69SDanny Lin 276b4791e69SDanny Lin core2 { 277b4791e69SDanny Lin cpu = <&CPU2>; 278b4791e69SDanny Lin }; 279b4791e69SDanny Lin 280b4791e69SDanny Lin core3 { 281b4791e69SDanny Lin cpu = <&CPU3>; 282b4791e69SDanny Lin }; 283b4791e69SDanny Lin 284b4791e69SDanny Lin core4 { 285b4791e69SDanny Lin cpu = <&CPU4>; 286b4791e69SDanny Lin }; 287b4791e69SDanny Lin 288b4791e69SDanny Lin core5 { 289b4791e69SDanny Lin cpu = <&CPU5>; 290b4791e69SDanny Lin }; 291b4791e69SDanny Lin 292b4791e69SDanny Lin core6 { 293b4791e69SDanny Lin cpu = <&CPU6>; 294b4791e69SDanny Lin }; 295b4791e69SDanny Lin 296b4791e69SDanny Lin core7 { 297b4791e69SDanny Lin cpu = <&CPU7>; 298b4791e69SDanny Lin }; 299b4791e69SDanny Lin }; 300b4791e69SDanny Lin }; 30132bc936dSMaulik Shah 30232bc936dSMaulik Shah idle-states { 30332bc936dSMaulik Shah entry-method = "psci"; 30432bc936dSMaulik Shah 30532bc936dSMaulik Shah LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 30632bc936dSMaulik Shah compatible = "arm,idle-state"; 30732bc936dSMaulik Shah idle-state-name = "silver-rail-power-collapse"; 30832bc936dSMaulik Shah arm,psci-suspend-param = <0x40000004>; 30932bc936dSMaulik Shah entry-latency-us = <360>; 31032bc936dSMaulik Shah exit-latency-us = <531>; 31132bc936dSMaulik Shah min-residency-us = <3934>; 31232bc936dSMaulik Shah local-timer-stop; 31332bc936dSMaulik Shah }; 31432bc936dSMaulik Shah 31532bc936dSMaulik Shah BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 31632bc936dSMaulik Shah compatible = "arm,idle-state"; 31732bc936dSMaulik Shah idle-state-name = "gold-rail-power-collapse"; 31832bc936dSMaulik Shah arm,psci-suspend-param = <0x40000004>; 31932bc936dSMaulik Shah entry-latency-us = <702>; 32032bc936dSMaulik Shah exit-latency-us = <1061>; 32132bc936dSMaulik Shah min-residency-us = <4488>; 32232bc936dSMaulik Shah local-timer-stop; 32332bc936dSMaulik Shah }; 32432bc936dSMaulik Shah }; 32532bc936dSMaulik Shah 32632bc936dSMaulik Shah domain-idle-states { 32732bc936dSMaulik Shah CLUSTER_SLEEP_0: cluster-sleep-0 { 32832bc936dSMaulik Shah compatible = "domain-idle-state"; 32932bc936dSMaulik Shah idle-state-name = "cluster-llcc-off"; 33032bc936dSMaulik Shah arm,psci-suspend-param = <0x4100c244>; 33132bc936dSMaulik Shah entry-latency-us = <3264>; 33232bc936dSMaulik Shah exit-latency-us = <6562>; 33332bc936dSMaulik Shah min-residency-us = <9987>; 33432bc936dSMaulik Shah local-timer-stop; 33532bc936dSMaulik Shah }; 33632bc936dSMaulik Shah }; 33760378f1aSVenkata Narendra Kumar Gutta }; 33860378f1aSVenkata Narendra Kumar Gutta 3398e0e8016SThara Gopinath cpu0_opp_table: cpu0_opp_table { 3408e0e8016SThara Gopinath compatible = "operating-points-v2"; 3418e0e8016SThara Gopinath opp-shared; 3428e0e8016SThara Gopinath 3438e0e8016SThara Gopinath cpu0_opp1: opp-300000000 { 3448e0e8016SThara Gopinath opp-hz = /bits/ 64 <300000000>; 3458e0e8016SThara Gopinath opp-peak-kBps = <800000 9600000>; 3468e0e8016SThara Gopinath }; 3478e0e8016SThara Gopinath 3488e0e8016SThara Gopinath cpu0_opp2: opp-403200000 { 3498e0e8016SThara Gopinath opp-hz = /bits/ 64 <403200000>; 3508e0e8016SThara Gopinath opp-peak-kBps = <800000 9600000>; 3518e0e8016SThara Gopinath }; 3528e0e8016SThara Gopinath 3538e0e8016SThara Gopinath cpu0_opp3: opp-518400000 { 3548e0e8016SThara Gopinath opp-hz = /bits/ 64 <518400000>; 3558e0e8016SThara Gopinath opp-peak-kBps = <800000 16588800>; 3568e0e8016SThara Gopinath }; 3578e0e8016SThara Gopinath 3588e0e8016SThara Gopinath cpu0_opp4: opp-614400000 { 3598e0e8016SThara Gopinath opp-hz = /bits/ 64 <614400000>; 3608e0e8016SThara Gopinath opp-peak-kBps = <800000 16588800>; 3618e0e8016SThara Gopinath }; 3628e0e8016SThara Gopinath 3638e0e8016SThara Gopinath cpu0_opp5: opp-691200000 { 3648e0e8016SThara Gopinath opp-hz = /bits/ 64 <691200000>; 3658e0e8016SThara Gopinath opp-peak-kBps = <800000 19660800>; 3668e0e8016SThara Gopinath }; 3678e0e8016SThara Gopinath 3688e0e8016SThara Gopinath cpu0_opp6: opp-787200000 { 3698e0e8016SThara Gopinath opp-hz = /bits/ 64 <787200000>; 3708e0e8016SThara Gopinath opp-peak-kBps = <1804000 19660800>; 3718e0e8016SThara Gopinath }; 3728e0e8016SThara Gopinath 3738e0e8016SThara Gopinath cpu0_opp7: opp-883200000 { 3748e0e8016SThara Gopinath opp-hz = /bits/ 64 <883200000>; 3758e0e8016SThara Gopinath opp-peak-kBps = <1804000 23347200>; 3768e0e8016SThara Gopinath }; 3778e0e8016SThara Gopinath 3788e0e8016SThara Gopinath cpu0_opp8: opp-979200000 { 3798e0e8016SThara Gopinath opp-hz = /bits/ 64 <979200000>; 3808e0e8016SThara Gopinath opp-peak-kBps = <1804000 26419200>; 3818e0e8016SThara Gopinath }; 3828e0e8016SThara Gopinath 3838e0e8016SThara Gopinath cpu0_opp9: opp-1075200000 { 3848e0e8016SThara Gopinath opp-hz = /bits/ 64 <1075200000>; 3858e0e8016SThara Gopinath opp-peak-kBps = <1804000 29491200>; 3868e0e8016SThara Gopinath }; 3878e0e8016SThara Gopinath 3888e0e8016SThara Gopinath cpu0_opp10: opp-1171200000 { 3898e0e8016SThara Gopinath opp-hz = /bits/ 64 <1171200000>; 3908e0e8016SThara Gopinath opp-peak-kBps = <1804000 32563200>; 3918e0e8016SThara Gopinath }; 3928e0e8016SThara Gopinath 3938e0e8016SThara Gopinath cpu0_opp11: opp-1248000000 { 3948e0e8016SThara Gopinath opp-hz = /bits/ 64 <1248000000>; 3958e0e8016SThara Gopinath opp-peak-kBps = <1804000 36249600>; 3968e0e8016SThara Gopinath }; 3978e0e8016SThara Gopinath 3988e0e8016SThara Gopinath cpu0_opp12: opp-1344000000 { 3998e0e8016SThara Gopinath opp-hz = /bits/ 64 <1344000000>; 4008e0e8016SThara Gopinath opp-peak-kBps = <2188000 36249600>; 4018e0e8016SThara Gopinath }; 4028e0e8016SThara Gopinath 4038e0e8016SThara Gopinath cpu0_opp13: opp-1420800000 { 4048e0e8016SThara Gopinath opp-hz = /bits/ 64 <1420800000>; 4058e0e8016SThara Gopinath opp-peak-kBps = <2188000 39321600>; 4068e0e8016SThara Gopinath }; 4078e0e8016SThara Gopinath 4088e0e8016SThara Gopinath cpu0_opp14: opp-1516800000 { 4098e0e8016SThara Gopinath opp-hz = /bits/ 64 <1516800000>; 4108e0e8016SThara Gopinath opp-peak-kBps = <3072000 42393600>; 4118e0e8016SThara Gopinath }; 4128e0e8016SThara Gopinath 4138e0e8016SThara Gopinath cpu0_opp15: opp-1612800000 { 4148e0e8016SThara Gopinath opp-hz = /bits/ 64 <1612800000>; 4158e0e8016SThara Gopinath opp-peak-kBps = <3072000 42393600>; 4168e0e8016SThara Gopinath }; 4178e0e8016SThara Gopinath 4188e0e8016SThara Gopinath cpu0_opp16: opp-1708800000 { 4198e0e8016SThara Gopinath opp-hz = /bits/ 64 <1708800000>; 4208e0e8016SThara Gopinath opp-peak-kBps = <4068000 42393600>; 4218e0e8016SThara Gopinath }; 4228e0e8016SThara Gopinath 4238e0e8016SThara Gopinath cpu0_opp17: opp-1804800000 { 4248e0e8016SThara Gopinath opp-hz = /bits/ 64 <1804800000>; 4258e0e8016SThara Gopinath opp-peak-kBps = <4068000 42393600>; 4268e0e8016SThara Gopinath }; 4278e0e8016SThara Gopinath }; 4288e0e8016SThara Gopinath 4298e0e8016SThara Gopinath cpu4_opp_table: cpu4_opp_table { 4308e0e8016SThara Gopinath compatible = "operating-points-v2"; 4318e0e8016SThara Gopinath opp-shared; 4328e0e8016SThara Gopinath 4338e0e8016SThara Gopinath cpu4_opp1: opp-710400000 { 4348e0e8016SThara Gopinath opp-hz = /bits/ 64 <710400000>; 4358e0e8016SThara Gopinath opp-peak-kBps = <1804000 19660800>; 4368e0e8016SThara Gopinath }; 4378e0e8016SThara Gopinath 4388e0e8016SThara Gopinath cpu4_opp2: opp-825600000 { 4398e0e8016SThara Gopinath opp-hz = /bits/ 64 <825600000>; 4408e0e8016SThara Gopinath opp-peak-kBps = <2188000 23347200>; 4418e0e8016SThara Gopinath }; 4428e0e8016SThara Gopinath 4438e0e8016SThara Gopinath cpu4_opp3: opp-940800000 { 4448e0e8016SThara Gopinath opp-hz = /bits/ 64 <940800000>; 4458e0e8016SThara Gopinath opp-peak-kBps = <2188000 26419200>; 4468e0e8016SThara Gopinath }; 4478e0e8016SThara Gopinath 4488e0e8016SThara Gopinath cpu4_opp4: opp-1056000000 { 4498e0e8016SThara Gopinath opp-hz = /bits/ 64 <1056000000>; 4508e0e8016SThara Gopinath opp-peak-kBps = <3072000 26419200>; 4518e0e8016SThara Gopinath }; 4528e0e8016SThara Gopinath 4538e0e8016SThara Gopinath cpu4_opp5: opp-1171200000 { 4548e0e8016SThara Gopinath opp-hz = /bits/ 64 <1171200000>; 4558e0e8016SThara Gopinath opp-peak-kBps = <3072000 29491200>; 4568e0e8016SThara Gopinath }; 4578e0e8016SThara Gopinath 4588e0e8016SThara Gopinath cpu4_opp6: opp-1286400000 { 4598e0e8016SThara Gopinath opp-hz = /bits/ 64 <1286400000>; 4608e0e8016SThara Gopinath opp-peak-kBps = <4068000 29491200>; 4618e0e8016SThara Gopinath }; 4628e0e8016SThara Gopinath 4638e0e8016SThara Gopinath cpu4_opp7: opp-1382400000 { 4648e0e8016SThara Gopinath opp-hz = /bits/ 64 <1382400000>; 4658e0e8016SThara Gopinath opp-peak-kBps = <4068000 32563200>; 4668e0e8016SThara Gopinath }; 4678e0e8016SThara Gopinath 4688e0e8016SThara Gopinath cpu4_opp8: opp-1478400000 { 4698e0e8016SThara Gopinath opp-hz = /bits/ 64 <1478400000>; 4708e0e8016SThara Gopinath opp-peak-kBps = <4068000 32563200>; 4718e0e8016SThara Gopinath }; 4728e0e8016SThara Gopinath 4738e0e8016SThara Gopinath cpu4_opp9: opp-1574400000 { 4748e0e8016SThara Gopinath opp-hz = /bits/ 64 <1574400000>; 4758e0e8016SThara Gopinath opp-peak-kBps = <5412000 39321600>; 4768e0e8016SThara Gopinath }; 4778e0e8016SThara Gopinath 4788e0e8016SThara Gopinath cpu4_opp10: opp-1670400000 { 4798e0e8016SThara Gopinath opp-hz = /bits/ 64 <1670400000>; 4808e0e8016SThara Gopinath opp-peak-kBps = <5412000 42393600>; 4818e0e8016SThara Gopinath }; 4828e0e8016SThara Gopinath 4838e0e8016SThara Gopinath cpu4_opp11: opp-1766400000 { 4848e0e8016SThara Gopinath opp-hz = /bits/ 64 <1766400000>; 4858e0e8016SThara Gopinath opp-peak-kBps = <5412000 45465600>; 4868e0e8016SThara Gopinath }; 4878e0e8016SThara Gopinath 4888e0e8016SThara Gopinath cpu4_opp12: opp-1862400000 { 4898e0e8016SThara Gopinath opp-hz = /bits/ 64 <1862400000>; 4908e0e8016SThara Gopinath opp-peak-kBps = <6220000 45465600>; 4918e0e8016SThara Gopinath }; 4928e0e8016SThara Gopinath 4938e0e8016SThara Gopinath cpu4_opp13: opp-1958400000 { 4948e0e8016SThara Gopinath opp-hz = /bits/ 64 <1958400000>; 4958e0e8016SThara Gopinath opp-peak-kBps = <6220000 48537600>; 4968e0e8016SThara Gopinath }; 4978e0e8016SThara Gopinath 4988e0e8016SThara Gopinath cpu4_opp14: opp-2054400000 { 4998e0e8016SThara Gopinath opp-hz = /bits/ 64 <2054400000>; 5008e0e8016SThara Gopinath opp-peak-kBps = <7216000 48537600>; 5018e0e8016SThara Gopinath }; 5028e0e8016SThara Gopinath 5038e0e8016SThara Gopinath cpu4_opp15: opp-2150400000 { 5048e0e8016SThara Gopinath opp-hz = /bits/ 64 <2150400000>; 5058e0e8016SThara Gopinath opp-peak-kBps = <7216000 51609600>; 5068e0e8016SThara Gopinath }; 5078e0e8016SThara Gopinath 5088e0e8016SThara Gopinath cpu4_opp16: opp-2246400000 { 5098e0e8016SThara Gopinath opp-hz = /bits/ 64 <2246400000>; 5108e0e8016SThara Gopinath opp-peak-kBps = <7216000 51609600>; 5118e0e8016SThara Gopinath }; 5128e0e8016SThara Gopinath 5138e0e8016SThara Gopinath cpu4_opp17: opp-2342400000 { 5148e0e8016SThara Gopinath opp-hz = /bits/ 64 <2342400000>; 5158e0e8016SThara Gopinath opp-peak-kBps = <8368000 51609600>; 5168e0e8016SThara Gopinath }; 5178e0e8016SThara Gopinath 5188e0e8016SThara Gopinath cpu4_opp18: opp-2419200000 { 5198e0e8016SThara Gopinath opp-hz = /bits/ 64 <2419200000>; 5208e0e8016SThara Gopinath opp-peak-kBps = <8368000 51609600>; 5218e0e8016SThara Gopinath }; 5228e0e8016SThara Gopinath }; 5238e0e8016SThara Gopinath 5248e0e8016SThara Gopinath cpu7_opp_table: cpu7_opp_table { 5258e0e8016SThara Gopinath compatible = "operating-points-v2"; 5268e0e8016SThara Gopinath opp-shared; 5278e0e8016SThara Gopinath 5288e0e8016SThara Gopinath cpu7_opp1: opp-844800000 { 5298e0e8016SThara Gopinath opp-hz = /bits/ 64 <844800000>; 5308e0e8016SThara Gopinath opp-peak-kBps = <2188000 19660800>; 5318e0e8016SThara Gopinath }; 5328e0e8016SThara Gopinath 5338e0e8016SThara Gopinath cpu7_opp2: opp-960000000 { 5348e0e8016SThara Gopinath opp-hz = /bits/ 64 <960000000>; 5358e0e8016SThara Gopinath opp-peak-kBps = <2188000 26419200>; 5368e0e8016SThara Gopinath }; 5378e0e8016SThara Gopinath 5388e0e8016SThara Gopinath cpu7_opp3: opp-1075200000 { 5398e0e8016SThara Gopinath opp-hz = /bits/ 64 <1075200000>; 5408e0e8016SThara Gopinath opp-peak-kBps = <3072000 26419200>; 5418e0e8016SThara Gopinath }; 5428e0e8016SThara Gopinath 5438e0e8016SThara Gopinath cpu7_opp4: opp-1190400000 { 5448e0e8016SThara Gopinath opp-hz = /bits/ 64 <1190400000>; 5458e0e8016SThara Gopinath opp-peak-kBps = <3072000 29491200>; 5468e0e8016SThara Gopinath }; 5478e0e8016SThara Gopinath 5488e0e8016SThara Gopinath cpu7_opp5: opp-1305600000 { 5498e0e8016SThara Gopinath opp-hz = /bits/ 64 <1305600000>; 5508e0e8016SThara Gopinath opp-peak-kBps = <4068000 32563200>; 5518e0e8016SThara Gopinath }; 5528e0e8016SThara Gopinath 5538e0e8016SThara Gopinath cpu7_opp6: opp-1401600000 { 5548e0e8016SThara Gopinath opp-hz = /bits/ 64 <1401600000>; 5558e0e8016SThara Gopinath opp-peak-kBps = <4068000 32563200>; 5568e0e8016SThara Gopinath }; 5578e0e8016SThara Gopinath 5588e0e8016SThara Gopinath cpu7_opp7: opp-1516800000 { 5598e0e8016SThara Gopinath opp-hz = /bits/ 64 <1516800000>; 5608e0e8016SThara Gopinath opp-peak-kBps = <4068000 36249600>; 5618e0e8016SThara Gopinath }; 5628e0e8016SThara Gopinath 5638e0e8016SThara Gopinath cpu7_opp8: opp-1632000000 { 5648e0e8016SThara Gopinath opp-hz = /bits/ 64 <1632000000>; 5658e0e8016SThara Gopinath opp-peak-kBps = <5412000 39321600>; 5668e0e8016SThara Gopinath }; 5678e0e8016SThara Gopinath 5688e0e8016SThara Gopinath cpu7_opp9: opp-1747200000 { 5698e0e8016SThara Gopinath opp-hz = /bits/ 64 <1708800000>; 5708e0e8016SThara Gopinath opp-peak-kBps = <5412000 42393600>; 5718e0e8016SThara Gopinath }; 5728e0e8016SThara Gopinath 5738e0e8016SThara Gopinath cpu7_opp10: opp-1862400000 { 5748e0e8016SThara Gopinath opp-hz = /bits/ 64 <1862400000>; 5758e0e8016SThara Gopinath opp-peak-kBps = <6220000 45465600>; 5768e0e8016SThara Gopinath }; 5778e0e8016SThara Gopinath 5788e0e8016SThara Gopinath cpu7_opp11: opp-1977600000 { 5798e0e8016SThara Gopinath opp-hz = /bits/ 64 <1977600000>; 5808e0e8016SThara Gopinath opp-peak-kBps = <6220000 48537600>; 5818e0e8016SThara Gopinath }; 5828e0e8016SThara Gopinath 5838e0e8016SThara Gopinath cpu7_opp12: opp-2073600000 { 5848e0e8016SThara Gopinath opp-hz = /bits/ 64 <2073600000>; 5858e0e8016SThara Gopinath opp-peak-kBps = <7216000 48537600>; 5868e0e8016SThara Gopinath }; 5878e0e8016SThara Gopinath 5888e0e8016SThara Gopinath cpu7_opp13: opp-2169600000 { 5898e0e8016SThara Gopinath opp-hz = /bits/ 64 <2169600000>; 5908e0e8016SThara Gopinath opp-peak-kBps = <7216000 51609600>; 5918e0e8016SThara Gopinath }; 5928e0e8016SThara Gopinath 5938e0e8016SThara Gopinath cpu7_opp14: opp-2265600000 { 5948e0e8016SThara Gopinath opp-hz = /bits/ 64 <2265600000>; 5958e0e8016SThara Gopinath opp-peak-kBps = <7216000 51609600>; 5968e0e8016SThara Gopinath }; 5978e0e8016SThara Gopinath 5988e0e8016SThara Gopinath cpu7_opp15: opp-2361600000 { 5998e0e8016SThara Gopinath opp-hz = /bits/ 64 <2361600000>; 6008e0e8016SThara Gopinath opp-peak-kBps = <8368000 51609600>; 6018e0e8016SThara Gopinath }; 6028e0e8016SThara Gopinath 6038e0e8016SThara Gopinath cpu7_opp16: opp-2457600000 { 6048e0e8016SThara Gopinath opp-hz = /bits/ 64 <2457600000>; 6058e0e8016SThara Gopinath opp-peak-kBps = <8368000 51609600>; 6068e0e8016SThara Gopinath }; 6078e0e8016SThara Gopinath 6088e0e8016SThara Gopinath cpu7_opp17: opp-2553600000 { 6098e0e8016SThara Gopinath opp-hz = /bits/ 64 <2553600000>; 6108e0e8016SThara Gopinath opp-peak-kBps = <8368000 51609600>; 6118e0e8016SThara Gopinath }; 6128e0e8016SThara Gopinath 6138e0e8016SThara Gopinath cpu7_opp18: opp-2649600000 { 6148e0e8016SThara Gopinath opp-hz = /bits/ 64 <2649600000>; 6158e0e8016SThara Gopinath opp-peak-kBps = <8368000 51609600>; 6168e0e8016SThara Gopinath }; 6178e0e8016SThara Gopinath 6188e0e8016SThara Gopinath cpu7_opp19: opp-2745600000 { 6198e0e8016SThara Gopinath opp-hz = /bits/ 64 <2745600000>; 6208e0e8016SThara Gopinath opp-peak-kBps = <8368000 51609600>; 6218e0e8016SThara Gopinath }; 6228e0e8016SThara Gopinath 6238e0e8016SThara Gopinath cpu7_opp20: opp-2841600000 { 6248e0e8016SThara Gopinath opp-hz = /bits/ 64 <2841600000>; 6258e0e8016SThara Gopinath opp-peak-kBps = <8368000 51609600>; 6268e0e8016SThara Gopinath }; 6278e0e8016SThara Gopinath }; 6288e0e8016SThara Gopinath 62960378f1aSVenkata Narendra Kumar Gutta firmware { 63060378f1aSVenkata Narendra Kumar Gutta scm: scm { 63160378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,scm"; 63260378f1aSVenkata Narendra Kumar Gutta #reset-cells = <1>; 63360378f1aSVenkata Narendra Kumar Gutta }; 63460378f1aSVenkata Narendra Kumar Gutta }; 63560378f1aSVenkata Narendra Kumar Gutta 63660378f1aSVenkata Narendra Kumar Gutta memory@80000000 { 63760378f1aSVenkata Narendra Kumar Gutta device_type = "memory"; 63860378f1aSVenkata Narendra Kumar Gutta /* We expect the bootloader to fill in the size */ 63960378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80000000 0x0 0x0>; 64060378f1aSVenkata Narendra Kumar Gutta }; 64160378f1aSVenkata Narendra Kumar Gutta 64260378f1aSVenkata Narendra Kumar Gutta pmu { 64360378f1aSVenkata Narendra Kumar Gutta compatible = "arm,armv8-pmuv3"; 64493138ef5SSai Prakash Ranjan interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 64560378f1aSVenkata Narendra Kumar Gutta }; 64660378f1aSVenkata Narendra Kumar Gutta 64760378f1aSVenkata Narendra Kumar Gutta psci { 64860378f1aSVenkata Narendra Kumar Gutta compatible = "arm,psci-1.0"; 64960378f1aSVenkata Narendra Kumar Gutta method = "smc"; 65032bc936dSMaulik Shah 65132bc936dSMaulik Shah CPU_PD0: cpu0 { 65232bc936dSMaulik Shah #power-domain-cells = <0>; 65332bc936dSMaulik Shah power-domains = <&CLUSTER_PD>; 65432bc936dSMaulik Shah domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 65532bc936dSMaulik Shah }; 65632bc936dSMaulik Shah 65732bc936dSMaulik Shah CPU_PD1: cpu1 { 65832bc936dSMaulik Shah #power-domain-cells = <0>; 65932bc936dSMaulik Shah power-domains = <&CLUSTER_PD>; 66032bc936dSMaulik Shah domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 66132bc936dSMaulik Shah }; 66232bc936dSMaulik Shah 66332bc936dSMaulik Shah CPU_PD2: cpu2 { 66432bc936dSMaulik Shah #power-domain-cells = <0>; 66532bc936dSMaulik Shah power-domains = <&CLUSTER_PD>; 66632bc936dSMaulik Shah domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 66732bc936dSMaulik Shah }; 66832bc936dSMaulik Shah 66932bc936dSMaulik Shah CPU_PD3: cpu3 { 67032bc936dSMaulik Shah #power-domain-cells = <0>; 67132bc936dSMaulik Shah power-domains = <&CLUSTER_PD>; 67232bc936dSMaulik Shah domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 67332bc936dSMaulik Shah }; 67432bc936dSMaulik Shah 67532bc936dSMaulik Shah CPU_PD4: cpu4 { 67632bc936dSMaulik Shah #power-domain-cells = <0>; 67732bc936dSMaulik Shah power-domains = <&CLUSTER_PD>; 67832bc936dSMaulik Shah domain-idle-states = <&BIG_CPU_SLEEP_0>; 67932bc936dSMaulik Shah }; 68032bc936dSMaulik Shah 68132bc936dSMaulik Shah CPU_PD5: cpu5 { 68232bc936dSMaulik Shah #power-domain-cells = <0>; 68332bc936dSMaulik Shah power-domains = <&CLUSTER_PD>; 68432bc936dSMaulik Shah domain-idle-states = <&BIG_CPU_SLEEP_0>; 68532bc936dSMaulik Shah }; 68632bc936dSMaulik Shah 68732bc936dSMaulik Shah CPU_PD6: cpu6 { 68832bc936dSMaulik Shah #power-domain-cells = <0>; 68932bc936dSMaulik Shah power-domains = <&CLUSTER_PD>; 69032bc936dSMaulik Shah domain-idle-states = <&BIG_CPU_SLEEP_0>; 69132bc936dSMaulik Shah }; 69232bc936dSMaulik Shah 69332bc936dSMaulik Shah CPU_PD7: cpu7 { 69432bc936dSMaulik Shah #power-domain-cells = <0>; 69532bc936dSMaulik Shah power-domains = <&CLUSTER_PD>; 69632bc936dSMaulik Shah domain-idle-states = <&BIG_CPU_SLEEP_0>; 69732bc936dSMaulik Shah }; 69832bc936dSMaulik Shah 69932bc936dSMaulik Shah CLUSTER_PD: cpu-cluster0 { 70032bc936dSMaulik Shah #power-domain-cells = <0>; 70132bc936dSMaulik Shah domain-idle-states = <&CLUSTER_SLEEP_0>; 70232bc936dSMaulik Shah }; 70360378f1aSVenkata Narendra Kumar Gutta }; 70460378f1aSVenkata Narendra Kumar Gutta 70560378f1aSVenkata Narendra Kumar Gutta reserved-memory { 70660378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 70760378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 70860378f1aSVenkata Narendra Kumar Gutta ranges; 70960378f1aSVenkata Narendra Kumar Gutta 71060378f1aSVenkata Narendra Kumar Gutta hyp_mem: memory@80000000 { 71160378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80000000 0x0 0x600000>; 71260378f1aSVenkata Narendra Kumar Gutta no-map; 71360378f1aSVenkata Narendra Kumar Gutta }; 71460378f1aSVenkata Narendra Kumar Gutta 71560378f1aSVenkata Narendra Kumar Gutta xbl_aop_mem: memory@80700000 { 71660378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80700000 0x0 0x160000>; 71760378f1aSVenkata Narendra Kumar Gutta no-map; 71860378f1aSVenkata Narendra Kumar Gutta }; 71960378f1aSVenkata Narendra Kumar Gutta 72060378f1aSVenkata Narendra Kumar Gutta cmd_db: memory@80860000 { 72160378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,cmd-db"; 72260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80860000 0x0 0x20000>; 72360378f1aSVenkata Narendra Kumar Gutta no-map; 72460378f1aSVenkata Narendra Kumar Gutta }; 72560378f1aSVenkata Narendra Kumar Gutta 72660378f1aSVenkata Narendra Kumar Gutta smem_mem: memory@80900000 { 72760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80900000 0x0 0x200000>; 72860378f1aSVenkata Narendra Kumar Gutta no-map; 72960378f1aSVenkata Narendra Kumar Gutta }; 73060378f1aSVenkata Narendra Kumar Gutta 73160378f1aSVenkata Narendra Kumar Gutta removed_mem: memory@80b00000 { 73260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80b00000 0x0 0x5300000>; 73360378f1aSVenkata Narendra Kumar Gutta no-map; 73460378f1aSVenkata Narendra Kumar Gutta }; 73560378f1aSVenkata Narendra Kumar Gutta 73660378f1aSVenkata Narendra Kumar Gutta camera_mem: memory@86200000 { 73760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86200000 0x0 0x500000>; 73860378f1aSVenkata Narendra Kumar Gutta no-map; 73960378f1aSVenkata Narendra Kumar Gutta }; 74060378f1aSVenkata Narendra Kumar Gutta 74160378f1aSVenkata Narendra Kumar Gutta wlan_mem: memory@86700000 { 74260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86700000 0x0 0x100000>; 74360378f1aSVenkata Narendra Kumar Gutta no-map; 74460378f1aSVenkata Narendra Kumar Gutta }; 74560378f1aSVenkata Narendra Kumar Gutta 74660378f1aSVenkata Narendra Kumar Gutta ipa_fw_mem: memory@86800000 { 74760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86800000 0x0 0x10000>; 74860378f1aSVenkata Narendra Kumar Gutta no-map; 74960378f1aSVenkata Narendra Kumar Gutta }; 75060378f1aSVenkata Narendra Kumar Gutta 75160378f1aSVenkata Narendra Kumar Gutta ipa_gsi_mem: memory@86810000 { 75260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86810000 0x0 0xa000>; 75360378f1aSVenkata Narendra Kumar Gutta no-map; 75460378f1aSVenkata Narendra Kumar Gutta }; 75560378f1aSVenkata Narendra Kumar Gutta 75660378f1aSVenkata Narendra Kumar Gutta gpu_mem: memory@8681a000 { 75760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8681a000 0x0 0x2000>; 75860378f1aSVenkata Narendra Kumar Gutta no-map; 75960378f1aSVenkata Narendra Kumar Gutta }; 76060378f1aSVenkata Narendra Kumar Gutta 76160378f1aSVenkata Narendra Kumar Gutta npu_mem: memory@86900000 { 76260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86900000 0x0 0x500000>; 76360378f1aSVenkata Narendra Kumar Gutta no-map; 76460378f1aSVenkata Narendra Kumar Gutta }; 76560378f1aSVenkata Narendra Kumar Gutta 76660378f1aSVenkata Narendra Kumar Gutta video_mem: memory@86e00000 { 76760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86e00000 0x0 0x500000>; 76860378f1aSVenkata Narendra Kumar Gutta no-map; 76960378f1aSVenkata Narendra Kumar Gutta }; 77060378f1aSVenkata Narendra Kumar Gutta 77160378f1aSVenkata Narendra Kumar Gutta cvp_mem: memory@87300000 { 77260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x87300000 0x0 0x500000>; 77360378f1aSVenkata Narendra Kumar Gutta no-map; 77460378f1aSVenkata Narendra Kumar Gutta }; 77560378f1aSVenkata Narendra Kumar Gutta 77660378f1aSVenkata Narendra Kumar Gutta cdsp_mem: memory@87800000 { 77760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x87800000 0x0 0x1400000>; 77860378f1aSVenkata Narendra Kumar Gutta no-map; 77960378f1aSVenkata Narendra Kumar Gutta }; 78060378f1aSVenkata Narendra Kumar Gutta 78160378f1aSVenkata Narendra Kumar Gutta slpi_mem: memory@88c00000 { 78260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x88c00000 0x0 0x1500000>; 78360378f1aSVenkata Narendra Kumar Gutta no-map; 78460378f1aSVenkata Narendra Kumar Gutta }; 78560378f1aSVenkata Narendra Kumar Gutta 78660378f1aSVenkata Narendra Kumar Gutta adsp_mem: memory@8a100000 { 78760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8a100000 0x0 0x1d00000>; 78860378f1aSVenkata Narendra Kumar Gutta no-map; 78960378f1aSVenkata Narendra Kumar Gutta }; 79060378f1aSVenkata Narendra Kumar Gutta 79160378f1aSVenkata Narendra Kumar Gutta spss_mem: memory@8be00000 { 79260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8be00000 0x0 0x100000>; 79360378f1aSVenkata Narendra Kumar Gutta no-map; 79460378f1aSVenkata Narendra Kumar Gutta }; 79560378f1aSVenkata Narendra Kumar Gutta 79660378f1aSVenkata Narendra Kumar Gutta cdsp_secure_heap: memory@8bf00000 { 79760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8bf00000 0x0 0x4600000>; 79860378f1aSVenkata Narendra Kumar Gutta no-map; 79960378f1aSVenkata Narendra Kumar Gutta }; 80060378f1aSVenkata Narendra Kumar Gutta }; 80160378f1aSVenkata Narendra Kumar Gutta 80288b57bc3SDmitry Baryshkov smem { 80360378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,smem"; 80460378f1aSVenkata Narendra Kumar Gutta memory-region = <&smem_mem>; 80560378f1aSVenkata Narendra Kumar Gutta hwlocks = <&tcsr_mutex 3>; 80660378f1aSVenkata Narendra Kumar Gutta }; 80760378f1aSVenkata Narendra Kumar Gutta 8088770a2a8SBjorn Andersson smp2p-adsp { 8098770a2a8SBjorn Andersson compatible = "qcom,smp2p"; 8108770a2a8SBjorn Andersson qcom,smem = <443>, <429>; 8118770a2a8SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 8128770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P 8138770a2a8SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 8148770a2a8SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_LPASS 8158770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P>; 8168770a2a8SBjorn Andersson 8178770a2a8SBjorn Andersson qcom,local-pid = <0>; 8188770a2a8SBjorn Andersson qcom,remote-pid = <2>; 8198770a2a8SBjorn Andersson 8208770a2a8SBjorn Andersson smp2p_adsp_out: master-kernel { 8218770a2a8SBjorn Andersson qcom,entry-name = "master-kernel"; 8228770a2a8SBjorn Andersson #qcom,smem-state-cells = <1>; 8238770a2a8SBjorn Andersson }; 8248770a2a8SBjorn Andersson 8258770a2a8SBjorn Andersson smp2p_adsp_in: slave-kernel { 8268770a2a8SBjorn Andersson qcom,entry-name = "slave-kernel"; 8278770a2a8SBjorn Andersson interrupt-controller; 8288770a2a8SBjorn Andersson #interrupt-cells = <2>; 8298770a2a8SBjorn Andersson }; 8308770a2a8SBjorn Andersson }; 8318770a2a8SBjorn Andersson 8328770a2a8SBjorn Andersson smp2p-cdsp { 8338770a2a8SBjorn Andersson compatible = "qcom,smp2p"; 8348770a2a8SBjorn Andersson qcom,smem = <94>, <432>; 8358770a2a8SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 8368770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P 8378770a2a8SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 8388770a2a8SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_CDSP 8398770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P>; 8408770a2a8SBjorn Andersson 8418770a2a8SBjorn Andersson qcom,local-pid = <0>; 8428770a2a8SBjorn Andersson qcom,remote-pid = <5>; 8438770a2a8SBjorn Andersson 8448770a2a8SBjorn Andersson smp2p_cdsp_out: master-kernel { 8458770a2a8SBjorn Andersson qcom,entry-name = "master-kernel"; 8468770a2a8SBjorn Andersson #qcom,smem-state-cells = <1>; 8478770a2a8SBjorn Andersson }; 8488770a2a8SBjorn Andersson 8498770a2a8SBjorn Andersson smp2p_cdsp_in: slave-kernel { 8508770a2a8SBjorn Andersson qcom,entry-name = "slave-kernel"; 8518770a2a8SBjorn Andersson interrupt-controller; 8528770a2a8SBjorn Andersson #interrupt-cells = <2>; 8538770a2a8SBjorn Andersson }; 8548770a2a8SBjorn Andersson }; 8558770a2a8SBjorn Andersson 8568770a2a8SBjorn Andersson smp2p-slpi { 8578770a2a8SBjorn Andersson compatible = "qcom,smp2p"; 8588770a2a8SBjorn Andersson qcom,smem = <481>, <430>; 8598770a2a8SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 8608770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P 8618770a2a8SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 8628770a2a8SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_SLPI 8638770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P>; 8648770a2a8SBjorn Andersson 8658770a2a8SBjorn Andersson qcom,local-pid = <0>; 8668770a2a8SBjorn Andersson qcom,remote-pid = <3>; 8678770a2a8SBjorn Andersson 8688770a2a8SBjorn Andersson smp2p_slpi_out: master-kernel { 8698770a2a8SBjorn Andersson qcom,entry-name = "master-kernel"; 8708770a2a8SBjorn Andersson #qcom,smem-state-cells = <1>; 8718770a2a8SBjorn Andersson }; 8728770a2a8SBjorn Andersson 8738770a2a8SBjorn Andersson smp2p_slpi_in: slave-kernel { 8748770a2a8SBjorn Andersson qcom,entry-name = "slave-kernel"; 8758770a2a8SBjorn Andersson interrupt-controller; 8768770a2a8SBjorn Andersson #interrupt-cells = <2>; 8778770a2a8SBjorn Andersson }; 8788770a2a8SBjorn Andersson }; 8798770a2a8SBjorn Andersson 88060378f1aSVenkata Narendra Kumar Gutta soc: soc@0 { 88160378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 88260378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 88360378f1aSVenkata Narendra Kumar Gutta ranges = <0 0 0 0 0x10 0>; 88460378f1aSVenkata Narendra Kumar Gutta dma-ranges = <0 0 0 0 0x10 0>; 88560378f1aSVenkata Narendra Kumar Gutta compatible = "simple-bus"; 88660378f1aSVenkata Narendra Kumar Gutta 88760378f1aSVenkata Narendra Kumar Gutta gcc: clock-controller@100000 { 88860378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,gcc-sm8250"; 88960378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x00100000 0x0 0x1f0000>; 89060378f1aSVenkata Narendra Kumar Gutta #clock-cells = <1>; 89160378f1aSVenkata Narendra Kumar Gutta #reset-cells = <1>; 89260378f1aSVenkata Narendra Kumar Gutta #power-domain-cells = <1>; 89376bd127eSDmitry Baryshkov clock-names = "bi_tcxo", 89476bd127eSDmitry Baryshkov "bi_tcxo_ao", 89576bd127eSDmitry Baryshkov "sleep_clk"; 89676bd127eSDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>, 89776bd127eSDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK_A>, 89876bd127eSDmitry Baryshkov <&sleep_clk>; 89960378f1aSVenkata Narendra Kumar Gutta }; 90060378f1aSVenkata Narendra Kumar Gutta 901e5361e75SBjorn Andersson ipcc: mailbox@408000 { 902e5361e75SBjorn Andersson compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 903e5361e75SBjorn Andersson reg = <0 0x00408000 0 0x1000>; 904e5361e75SBjorn Andersson interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 905e5361e75SBjorn Andersson interrupt-controller; 906e5361e75SBjorn Andersson #interrupt-cells = <3>; 907e5361e75SBjorn Andersson #mbox-cells = <2>; 908e5361e75SBjorn Andersson }; 909e5361e75SBjorn Andersson 91065389ce6SManivannan Sadhasivam rng: rng@793000 { 91165389ce6SManivannan Sadhasivam compatible = "qcom,prng-ee"; 91265389ce6SManivannan Sadhasivam reg = <0 0x00793000 0 0x1000>; 91365389ce6SManivannan Sadhasivam clocks = <&gcc GCC_PRNG_AHB_CLK>; 91465389ce6SManivannan Sadhasivam clock-names = "core"; 91565389ce6SManivannan Sadhasivam }; 91665389ce6SManivannan Sadhasivam 91701e869ccSDmitry Baryshkov qup_opp_table: qup-opp-table { 91801e869ccSDmitry Baryshkov compatible = "operating-points-v2"; 91901e869ccSDmitry Baryshkov 92001e869ccSDmitry Baryshkov opp-50000000 { 92101e869ccSDmitry Baryshkov opp-hz = /bits/ 64 <50000000>; 92201e869ccSDmitry Baryshkov required-opps = <&rpmhpd_opp_min_svs>; 92301e869ccSDmitry Baryshkov }; 92401e869ccSDmitry Baryshkov 92501e869ccSDmitry Baryshkov opp-75000000 { 92601e869ccSDmitry Baryshkov opp-hz = /bits/ 64 <75000000>; 92701e869ccSDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 92801e869ccSDmitry Baryshkov }; 92901e869ccSDmitry Baryshkov 93001e869ccSDmitry Baryshkov opp-120000000 { 93101e869ccSDmitry Baryshkov opp-hz = /bits/ 64 <120000000>; 93201e869ccSDmitry Baryshkov required-opps = <&rpmhpd_opp_svs>; 93301e869ccSDmitry Baryshkov }; 93401e869ccSDmitry Baryshkov }; 93501e869ccSDmitry Baryshkov 93615049bb5SKonrad Dybcio gpi_dma2: dma-controller@800000 { 93715049bb5SKonrad Dybcio compatible = "qcom,sm8250-gpi-dma"; 93815049bb5SKonrad Dybcio reg = <0 0x00800000 0 0x70000>; 93915049bb5SKonrad Dybcio interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 94015049bb5SKonrad Dybcio <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 94115049bb5SKonrad Dybcio <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 94215049bb5SKonrad Dybcio <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 94315049bb5SKonrad Dybcio <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 94415049bb5SKonrad Dybcio <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 94515049bb5SKonrad Dybcio <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 94615049bb5SKonrad Dybcio <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 94715049bb5SKonrad Dybcio <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 94815049bb5SKonrad Dybcio <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 94915049bb5SKonrad Dybcio dma-channels = <10>; 95015049bb5SKonrad Dybcio dma-channel-mask = <0x3f>; 95115049bb5SKonrad Dybcio iommus = <&apps_smmu 0x76 0x0>; 95215049bb5SKonrad Dybcio #dma-cells = <3>; 95315049bb5SKonrad Dybcio status = "disabled"; 95415049bb5SKonrad Dybcio }; 95515049bb5SKonrad Dybcio 956e5813b15SDmitry Baryshkov qupv3_id_2: geniqup@8c0000 { 957e5813b15SDmitry Baryshkov compatible = "qcom,geni-se-qup"; 958e5813b15SDmitry Baryshkov reg = <0x0 0x008c0000 0x0 0x6000>; 959e5813b15SDmitry Baryshkov clock-names = "m-ahb", "s-ahb"; 960e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 961e5813b15SDmitry Baryshkov <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 962e5813b15SDmitry Baryshkov #address-cells = <2>; 963e5813b15SDmitry Baryshkov #size-cells = <2>; 96485309393SDmitry Baryshkov iommus = <&apps_smmu 0x63 0x0>; 965e5813b15SDmitry Baryshkov ranges; 966e5813b15SDmitry Baryshkov status = "disabled"; 967e5813b15SDmitry Baryshkov 968e5813b15SDmitry Baryshkov i2c14: i2c@880000 { 969e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 970e5813b15SDmitry Baryshkov reg = <0 0x00880000 0 0x4000>; 971e5813b15SDmitry Baryshkov clock-names = "se"; 972e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 973e5813b15SDmitry Baryshkov pinctrl-names = "default"; 974e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c14_default>; 975e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 97659983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 97759983a5cSKonrad Dybcio <&gpi_dma2 1 0 QCOM_GPI_I2C>; 97859983a5cSKonrad Dybcio dma-names = "tx", "rx"; 979e5813b15SDmitry Baryshkov #address-cells = <1>; 980e5813b15SDmitry Baryshkov #size-cells = <0>; 981e5813b15SDmitry Baryshkov status = "disabled"; 982e5813b15SDmitry Baryshkov }; 983e5813b15SDmitry Baryshkov 984e5813b15SDmitry Baryshkov spi14: spi@880000 { 985e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 986e5813b15SDmitry Baryshkov reg = <0 0x00880000 0 0x4000>; 987e5813b15SDmitry Baryshkov clock-names = "se"; 988e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 989e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 99059983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 99159983a5cSKonrad Dybcio <&gpi_dma2 1 0 QCOM_GPI_SPI>; 99259983a5cSKonrad Dybcio dma-names = "tx", "rx"; 99301e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 99401e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 99559983a5cSKonrad Dybcio #address-cells = <1>; 99659983a5cSKonrad Dybcio #size-cells = <0>; 997e5813b15SDmitry Baryshkov status = "disabled"; 998e5813b15SDmitry Baryshkov }; 999e5813b15SDmitry Baryshkov 1000e5813b15SDmitry Baryshkov i2c15: i2c@884000 { 1001e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1002e5813b15SDmitry Baryshkov reg = <0 0x00884000 0 0x4000>; 1003e5813b15SDmitry Baryshkov clock-names = "se"; 1004e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1005e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1006e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c15_default>; 1007e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 100859983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 100959983a5cSKonrad Dybcio <&gpi_dma2 1 1 QCOM_GPI_I2C>; 101059983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1011e5813b15SDmitry Baryshkov #address-cells = <1>; 1012e5813b15SDmitry Baryshkov #size-cells = <0>; 1013e5813b15SDmitry Baryshkov status = "disabled"; 1014e5813b15SDmitry Baryshkov }; 1015e5813b15SDmitry Baryshkov 1016e5813b15SDmitry Baryshkov spi15: spi@884000 { 1017e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1018e5813b15SDmitry Baryshkov reg = <0 0x00884000 0 0x4000>; 1019e5813b15SDmitry Baryshkov clock-names = "se"; 1020e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1021e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 102259983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 102359983a5cSKonrad Dybcio <&gpi_dma2 1 1 QCOM_GPI_SPI>; 102459983a5cSKonrad Dybcio dma-names = "tx", "rx"; 102501e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 102601e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 102759983a5cSKonrad Dybcio #address-cells = <1>; 102859983a5cSKonrad Dybcio #size-cells = <0>; 1029e5813b15SDmitry Baryshkov status = "disabled"; 1030e5813b15SDmitry Baryshkov }; 1031e5813b15SDmitry Baryshkov 1032e5813b15SDmitry Baryshkov i2c16: i2c@888000 { 1033e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1034e5813b15SDmitry Baryshkov reg = <0 0x00888000 0 0x4000>; 1035e5813b15SDmitry Baryshkov clock-names = "se"; 1036e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1037e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1038e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c16_default>; 1039e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 104059983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 104159983a5cSKonrad Dybcio <&gpi_dma2 1 2 QCOM_GPI_I2C>; 104259983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1043e5813b15SDmitry Baryshkov #address-cells = <1>; 1044e5813b15SDmitry Baryshkov #size-cells = <0>; 1045e5813b15SDmitry Baryshkov status = "disabled"; 1046e5813b15SDmitry Baryshkov }; 1047e5813b15SDmitry Baryshkov 1048e5813b15SDmitry Baryshkov spi16: spi@888000 { 1049e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1050e5813b15SDmitry Baryshkov reg = <0 0x00888000 0 0x4000>; 1051e5813b15SDmitry Baryshkov clock-names = "se"; 1052e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1053e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 105459983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 105559983a5cSKonrad Dybcio <&gpi_dma2 1 2 QCOM_GPI_SPI>; 105659983a5cSKonrad Dybcio dma-names = "tx", "rx"; 105701e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 105801e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 105959983a5cSKonrad Dybcio #address-cells = <1>; 106059983a5cSKonrad Dybcio #size-cells = <0>; 1061e5813b15SDmitry Baryshkov status = "disabled"; 1062e5813b15SDmitry Baryshkov }; 1063e5813b15SDmitry Baryshkov 1064e5813b15SDmitry Baryshkov i2c17: i2c@88c000 { 1065e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1066e5813b15SDmitry Baryshkov reg = <0 0x0088c000 0 0x4000>; 1067e5813b15SDmitry Baryshkov clock-names = "se"; 1068e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1069e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1070e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c17_default>; 1071e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 107259983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 107359983a5cSKonrad Dybcio <&gpi_dma2 1 3 QCOM_GPI_I2C>; 107459983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1075e5813b15SDmitry Baryshkov #address-cells = <1>; 1076e5813b15SDmitry Baryshkov #size-cells = <0>; 1077e5813b15SDmitry Baryshkov status = "disabled"; 1078e5813b15SDmitry Baryshkov }; 1079e5813b15SDmitry Baryshkov 1080e5813b15SDmitry Baryshkov spi17: spi@88c000 { 1081e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1082e5813b15SDmitry Baryshkov reg = <0 0x0088c000 0 0x4000>; 1083e5813b15SDmitry Baryshkov clock-names = "se"; 1084e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1085e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 108659983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 108759983a5cSKonrad Dybcio <&gpi_dma2 1 3 QCOM_GPI_SPI>; 108859983a5cSKonrad Dybcio dma-names = "tx", "rx"; 108901e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 109001e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 109159983a5cSKonrad Dybcio #address-cells = <1>; 109259983a5cSKonrad Dybcio #size-cells = <0>; 1093e5813b15SDmitry Baryshkov status = "disabled"; 1094e5813b15SDmitry Baryshkov }; 1095e5813b15SDmitry Baryshkov 109608a9ae2dSDmitry Baryshkov uart17: serial@88c000 { 109708a9ae2dSDmitry Baryshkov compatible = "qcom,geni-uart"; 109808a9ae2dSDmitry Baryshkov reg = <0 0x0088c000 0 0x4000>; 109908a9ae2dSDmitry Baryshkov clock-names = "se"; 110008a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 110108a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 110208a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart17_default>; 110308a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 110401e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 110501e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 110608a9ae2dSDmitry Baryshkov status = "disabled"; 110708a9ae2dSDmitry Baryshkov }; 110808a9ae2dSDmitry Baryshkov 1109e5813b15SDmitry Baryshkov i2c18: i2c@890000 { 1110e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1111e5813b15SDmitry Baryshkov reg = <0 0x00890000 0 0x4000>; 1112e5813b15SDmitry Baryshkov clock-names = "se"; 1113e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1114e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1115e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c18_default>; 1116e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 111759983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 111859983a5cSKonrad Dybcio <&gpi_dma2 1 4 QCOM_GPI_I2C>; 111959983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1120e5813b15SDmitry Baryshkov #address-cells = <1>; 1121e5813b15SDmitry Baryshkov #size-cells = <0>; 1122e5813b15SDmitry Baryshkov status = "disabled"; 1123e5813b15SDmitry Baryshkov }; 1124e5813b15SDmitry Baryshkov 1125e5813b15SDmitry Baryshkov spi18: spi@890000 { 1126e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1127e5813b15SDmitry Baryshkov reg = <0 0x00890000 0 0x4000>; 1128e5813b15SDmitry Baryshkov clock-names = "se"; 1129e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1130e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 113159983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 113259983a5cSKonrad Dybcio <&gpi_dma2 1 4 QCOM_GPI_SPI>; 113359983a5cSKonrad Dybcio dma-names = "tx", "rx"; 113401e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 113501e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 113659983a5cSKonrad Dybcio #address-cells = <1>; 113759983a5cSKonrad Dybcio #size-cells = <0>; 1138e5813b15SDmitry Baryshkov status = "disabled"; 1139e5813b15SDmitry Baryshkov }; 1140e5813b15SDmitry Baryshkov 114108a9ae2dSDmitry Baryshkov uart18: serial@890000 { 114208a9ae2dSDmitry Baryshkov compatible = "qcom,geni-uart"; 114308a9ae2dSDmitry Baryshkov reg = <0 0x00890000 0 0x4000>; 114408a9ae2dSDmitry Baryshkov clock-names = "se"; 114508a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 114608a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 114708a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart18_default>; 114808a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 114901e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 115001e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 115108a9ae2dSDmitry Baryshkov status = "disabled"; 115208a9ae2dSDmitry Baryshkov }; 115308a9ae2dSDmitry Baryshkov 1154e5813b15SDmitry Baryshkov i2c19: i2c@894000 { 1155e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1156e5813b15SDmitry Baryshkov reg = <0 0x00894000 0 0x4000>; 1157e5813b15SDmitry Baryshkov clock-names = "se"; 1158e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1159e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1160e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c19_default>; 1161e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 116259983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 116359983a5cSKonrad Dybcio <&gpi_dma2 1 5 QCOM_GPI_I2C>; 116459983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1165e5813b15SDmitry Baryshkov #address-cells = <1>; 1166e5813b15SDmitry Baryshkov #size-cells = <0>; 1167e5813b15SDmitry Baryshkov status = "disabled"; 1168e5813b15SDmitry Baryshkov }; 1169e5813b15SDmitry Baryshkov 1170e5813b15SDmitry Baryshkov spi19: spi@894000 { 1171e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1172e5813b15SDmitry Baryshkov reg = <0 0x00894000 0 0x4000>; 1173e5813b15SDmitry Baryshkov clock-names = "se"; 1174e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1175e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 117659983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 117759983a5cSKonrad Dybcio <&gpi_dma2 1 5 QCOM_GPI_SPI>; 117859983a5cSKonrad Dybcio dma-names = "tx", "rx"; 117901e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 118001e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 118159983a5cSKonrad Dybcio #address-cells = <1>; 118259983a5cSKonrad Dybcio #size-cells = <0>; 1183e5813b15SDmitry Baryshkov status = "disabled"; 1184e5813b15SDmitry Baryshkov }; 1185e5813b15SDmitry Baryshkov }; 1186e5813b15SDmitry Baryshkov 118715049bb5SKonrad Dybcio gpi_dma0: dma-controller@900000 { 118815049bb5SKonrad Dybcio compatible = "qcom,sm8250-gpi-dma"; 118915049bb5SKonrad Dybcio reg = <0 0x00900000 0 0x70000>; 119015049bb5SKonrad Dybcio interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 119115049bb5SKonrad Dybcio <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 119215049bb5SKonrad Dybcio <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 119315049bb5SKonrad Dybcio <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 119415049bb5SKonrad Dybcio <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 119515049bb5SKonrad Dybcio <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 119615049bb5SKonrad Dybcio <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 119715049bb5SKonrad Dybcio <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 119815049bb5SKonrad Dybcio <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 119915049bb5SKonrad Dybcio <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 120015049bb5SKonrad Dybcio <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 120115049bb5SKonrad Dybcio <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 120215049bb5SKonrad Dybcio <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 120315049bb5SKonrad Dybcio dma-channels = <15>; 120415049bb5SKonrad Dybcio dma-channel-mask = <0x7ff>; 120515049bb5SKonrad Dybcio iommus = <&apps_smmu 0x5b6 0x0>; 120615049bb5SKonrad Dybcio #dma-cells = <3>; 120715049bb5SKonrad Dybcio status = "disabled"; 120815049bb5SKonrad Dybcio }; 120915049bb5SKonrad Dybcio 1210e5813b15SDmitry Baryshkov qupv3_id_0: geniqup@9c0000 { 1211e5813b15SDmitry Baryshkov compatible = "qcom,geni-se-qup"; 1212e5813b15SDmitry Baryshkov reg = <0x0 0x009c0000 0x0 0x6000>; 1213e5813b15SDmitry Baryshkov clock-names = "m-ahb", "s-ahb"; 1214e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1215e5813b15SDmitry Baryshkov <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1216e5813b15SDmitry Baryshkov #address-cells = <2>; 1217e5813b15SDmitry Baryshkov #size-cells = <2>; 121885309393SDmitry Baryshkov iommus = <&apps_smmu 0x5a3 0x0>; 1219e5813b15SDmitry Baryshkov ranges; 1220e5813b15SDmitry Baryshkov status = "disabled"; 1221e5813b15SDmitry Baryshkov 1222e5813b15SDmitry Baryshkov i2c0: i2c@980000 { 1223e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1224e5813b15SDmitry Baryshkov reg = <0 0x00980000 0 0x4000>; 1225e5813b15SDmitry Baryshkov clock-names = "se"; 1226e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1227e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1228e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c0_default>; 1229e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 123059983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 123159983a5cSKonrad Dybcio <&gpi_dma0 1 0 QCOM_GPI_I2C>; 123259983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1233e5813b15SDmitry Baryshkov #address-cells = <1>; 1234e5813b15SDmitry Baryshkov #size-cells = <0>; 1235e5813b15SDmitry Baryshkov status = "disabled"; 1236e5813b15SDmitry Baryshkov }; 1237e5813b15SDmitry Baryshkov 1238e5813b15SDmitry Baryshkov spi0: spi@980000 { 1239e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1240e5813b15SDmitry Baryshkov reg = <0 0x00980000 0 0x4000>; 1241e5813b15SDmitry Baryshkov clock-names = "se"; 1242e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1243e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 124459983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 124559983a5cSKonrad Dybcio <&gpi_dma0 1 0 QCOM_GPI_SPI>; 124659983a5cSKonrad Dybcio dma-names = "tx", "rx"; 124701e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 124801e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 124959983a5cSKonrad Dybcio #address-cells = <1>; 125059983a5cSKonrad Dybcio #size-cells = <0>; 1251e5813b15SDmitry Baryshkov status = "disabled"; 1252e5813b15SDmitry Baryshkov }; 1253e5813b15SDmitry Baryshkov 1254e5813b15SDmitry Baryshkov i2c1: i2c@984000 { 1255e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1256e5813b15SDmitry Baryshkov reg = <0 0x00984000 0 0x4000>; 1257e5813b15SDmitry Baryshkov clock-names = "se"; 1258e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1259e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1260e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c1_default>; 1261e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 126259983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 126359983a5cSKonrad Dybcio <&gpi_dma0 1 1 QCOM_GPI_I2C>; 126459983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1265e5813b15SDmitry Baryshkov #address-cells = <1>; 1266e5813b15SDmitry Baryshkov #size-cells = <0>; 1267e5813b15SDmitry Baryshkov status = "disabled"; 1268e5813b15SDmitry Baryshkov }; 1269e5813b15SDmitry Baryshkov 1270e5813b15SDmitry Baryshkov spi1: spi@984000 { 1271e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1272e5813b15SDmitry Baryshkov reg = <0 0x00984000 0 0x4000>; 1273e5813b15SDmitry Baryshkov clock-names = "se"; 1274e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1275e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 127659983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 127759983a5cSKonrad Dybcio <&gpi_dma0 1 1 QCOM_GPI_SPI>; 127859983a5cSKonrad Dybcio dma-names = "tx", "rx"; 127901e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 128001e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 128159983a5cSKonrad Dybcio #address-cells = <1>; 128259983a5cSKonrad Dybcio #size-cells = <0>; 1283e5813b15SDmitry Baryshkov status = "disabled"; 1284e5813b15SDmitry Baryshkov }; 1285e5813b15SDmitry Baryshkov 1286e5813b15SDmitry Baryshkov i2c2: i2c@988000 { 1287e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1288e5813b15SDmitry Baryshkov reg = <0 0x00988000 0 0x4000>; 1289e5813b15SDmitry Baryshkov clock-names = "se"; 1290e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1291e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1292e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c2_default>; 1293e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 129459983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 129559983a5cSKonrad Dybcio <&gpi_dma0 1 2 QCOM_GPI_I2C>; 129659983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1297e5813b15SDmitry Baryshkov #address-cells = <1>; 1298e5813b15SDmitry Baryshkov #size-cells = <0>; 1299e5813b15SDmitry Baryshkov status = "disabled"; 1300e5813b15SDmitry Baryshkov }; 1301e5813b15SDmitry Baryshkov 1302e5813b15SDmitry Baryshkov spi2: spi@988000 { 1303e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1304e5813b15SDmitry Baryshkov reg = <0 0x00988000 0 0x4000>; 1305e5813b15SDmitry Baryshkov clock-names = "se"; 1306e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1307e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 130859983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 130959983a5cSKonrad Dybcio <&gpi_dma0 1 2 QCOM_GPI_SPI>; 131059983a5cSKonrad Dybcio dma-names = "tx", "rx"; 131101e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 131201e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 131359983a5cSKonrad Dybcio #address-cells = <1>; 131459983a5cSKonrad Dybcio #size-cells = <0>; 1315e5813b15SDmitry Baryshkov status = "disabled"; 1316e5813b15SDmitry Baryshkov }; 1317e5813b15SDmitry Baryshkov 131808a9ae2dSDmitry Baryshkov uart2: serial@988000 { 131908a9ae2dSDmitry Baryshkov compatible = "qcom,geni-debug-uart"; 132008a9ae2dSDmitry Baryshkov reg = <0 0x00988000 0 0x4000>; 132108a9ae2dSDmitry Baryshkov clock-names = "se"; 132208a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 132308a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 132408a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart2_default>; 132508a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 132601e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 132701e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 132808a9ae2dSDmitry Baryshkov status = "disabled"; 132908a9ae2dSDmitry Baryshkov }; 133008a9ae2dSDmitry Baryshkov 1331e5813b15SDmitry Baryshkov i2c3: i2c@98c000 { 1332e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1333e5813b15SDmitry Baryshkov reg = <0 0x0098c000 0 0x4000>; 1334e5813b15SDmitry Baryshkov clock-names = "se"; 1335e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1336e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1337e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c3_default>; 1338e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 133959983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 134059983a5cSKonrad Dybcio <&gpi_dma0 1 3 QCOM_GPI_I2C>; 134159983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1342e5813b15SDmitry Baryshkov #address-cells = <1>; 1343e5813b15SDmitry Baryshkov #size-cells = <0>; 1344e5813b15SDmitry Baryshkov status = "disabled"; 1345e5813b15SDmitry Baryshkov }; 1346e5813b15SDmitry Baryshkov 1347e5813b15SDmitry Baryshkov spi3: spi@98c000 { 1348e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1349e5813b15SDmitry Baryshkov reg = <0 0x0098c000 0 0x4000>; 1350e5813b15SDmitry Baryshkov clock-names = "se"; 1351e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1352e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 135359983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 135459983a5cSKonrad Dybcio <&gpi_dma0 1 3 QCOM_GPI_SPI>; 135559983a5cSKonrad Dybcio dma-names = "tx", "rx"; 135601e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 135701e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 135859983a5cSKonrad Dybcio #address-cells = <1>; 135959983a5cSKonrad Dybcio #size-cells = <0>; 1360e5813b15SDmitry Baryshkov status = "disabled"; 1361e5813b15SDmitry Baryshkov }; 1362e5813b15SDmitry Baryshkov 1363e5813b15SDmitry Baryshkov i2c4: i2c@990000 { 1364e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1365e5813b15SDmitry Baryshkov reg = <0 0x00990000 0 0x4000>; 1366e5813b15SDmitry Baryshkov clock-names = "se"; 1367e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1368e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1369e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c4_default>; 1370e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 137159983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 137259983a5cSKonrad Dybcio <&gpi_dma0 1 4 QCOM_GPI_I2C>; 137359983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1374e5813b15SDmitry Baryshkov #address-cells = <1>; 1375e5813b15SDmitry Baryshkov #size-cells = <0>; 1376e5813b15SDmitry Baryshkov status = "disabled"; 1377e5813b15SDmitry Baryshkov }; 1378e5813b15SDmitry Baryshkov 1379e5813b15SDmitry Baryshkov spi4: spi@990000 { 1380e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1381e5813b15SDmitry Baryshkov reg = <0 0x00990000 0 0x4000>; 1382e5813b15SDmitry Baryshkov clock-names = "se"; 1383e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1384e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 138559983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 138659983a5cSKonrad Dybcio <&gpi_dma0 1 4 QCOM_GPI_SPI>; 138759983a5cSKonrad Dybcio dma-names = "tx", "rx"; 138801e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 138901e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 139059983a5cSKonrad Dybcio #address-cells = <1>; 139159983a5cSKonrad Dybcio #size-cells = <0>; 1392e5813b15SDmitry Baryshkov status = "disabled"; 1393e5813b15SDmitry Baryshkov }; 1394e5813b15SDmitry Baryshkov 1395e5813b15SDmitry Baryshkov i2c5: i2c@994000 { 1396e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1397e5813b15SDmitry Baryshkov reg = <0 0x00994000 0 0x4000>; 1398e5813b15SDmitry Baryshkov clock-names = "se"; 1399e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1400e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1401e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c5_default>; 1402e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 140359983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 140459983a5cSKonrad Dybcio <&gpi_dma0 1 5 QCOM_GPI_I2C>; 140559983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1406e5813b15SDmitry Baryshkov #address-cells = <1>; 1407e5813b15SDmitry Baryshkov #size-cells = <0>; 1408e5813b15SDmitry Baryshkov status = "disabled"; 1409e5813b15SDmitry Baryshkov }; 1410e5813b15SDmitry Baryshkov 1411e5813b15SDmitry Baryshkov spi5: spi@994000 { 1412e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1413e5813b15SDmitry Baryshkov reg = <0 0x00994000 0 0x4000>; 1414e5813b15SDmitry Baryshkov clock-names = "se"; 1415e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1416e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 141759983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 141859983a5cSKonrad Dybcio <&gpi_dma0 1 5 QCOM_GPI_SPI>; 141959983a5cSKonrad Dybcio dma-names = "tx", "rx"; 142001e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 142101e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 142259983a5cSKonrad Dybcio #address-cells = <1>; 142359983a5cSKonrad Dybcio #size-cells = <0>; 1424e5813b15SDmitry Baryshkov status = "disabled"; 1425e5813b15SDmitry Baryshkov }; 1426e5813b15SDmitry Baryshkov 1427e5813b15SDmitry Baryshkov i2c6: i2c@998000 { 1428e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1429e5813b15SDmitry Baryshkov reg = <0 0x00998000 0 0x4000>; 1430e5813b15SDmitry Baryshkov clock-names = "se"; 1431e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1432e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1433e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c6_default>; 1434e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 143559983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 143659983a5cSKonrad Dybcio <&gpi_dma0 1 6 QCOM_GPI_I2C>; 143759983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1438e5813b15SDmitry Baryshkov #address-cells = <1>; 1439e5813b15SDmitry Baryshkov #size-cells = <0>; 1440e5813b15SDmitry Baryshkov status = "disabled"; 1441e5813b15SDmitry Baryshkov }; 1442e5813b15SDmitry Baryshkov 1443e5813b15SDmitry Baryshkov spi6: spi@998000 { 1444e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1445e5813b15SDmitry Baryshkov reg = <0 0x00998000 0 0x4000>; 1446e5813b15SDmitry Baryshkov clock-names = "se"; 1447e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1448e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 144959983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 145059983a5cSKonrad Dybcio <&gpi_dma0 1 6 QCOM_GPI_SPI>; 145159983a5cSKonrad Dybcio dma-names = "tx", "rx"; 145201e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 145301e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 145459983a5cSKonrad Dybcio #address-cells = <1>; 145559983a5cSKonrad Dybcio #size-cells = <0>; 1456e5813b15SDmitry Baryshkov status = "disabled"; 1457e5813b15SDmitry Baryshkov }; 1458e5813b15SDmitry Baryshkov 145908a9ae2dSDmitry Baryshkov uart6: serial@998000 { 146008a9ae2dSDmitry Baryshkov compatible = "qcom,geni-uart"; 146108a9ae2dSDmitry Baryshkov reg = <0 0x00998000 0 0x4000>; 146208a9ae2dSDmitry Baryshkov clock-names = "se"; 146308a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 146408a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 146508a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart6_default>; 146608a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 146701e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 146801e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 146908a9ae2dSDmitry Baryshkov status = "disabled"; 147008a9ae2dSDmitry Baryshkov }; 147108a9ae2dSDmitry Baryshkov 1472e5813b15SDmitry Baryshkov i2c7: i2c@99c000 { 1473e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1474e5813b15SDmitry Baryshkov reg = <0 0x0099c000 0 0x4000>; 1475e5813b15SDmitry Baryshkov clock-names = "se"; 1476e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1477e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1478e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c7_default>; 1479e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 148059983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 148159983a5cSKonrad Dybcio <&gpi_dma0 1 7 QCOM_GPI_I2C>; 148259983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1483e5813b15SDmitry Baryshkov #address-cells = <1>; 1484e5813b15SDmitry Baryshkov #size-cells = <0>; 1485e5813b15SDmitry Baryshkov status = "disabled"; 1486e5813b15SDmitry Baryshkov }; 1487e5813b15SDmitry Baryshkov 1488e5813b15SDmitry Baryshkov spi7: spi@99c000 { 1489e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1490e5813b15SDmitry Baryshkov reg = <0 0x0099c000 0 0x4000>; 1491e5813b15SDmitry Baryshkov clock-names = "se"; 1492e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1493e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 149459983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 149559983a5cSKonrad Dybcio <&gpi_dma0 1 7 QCOM_GPI_SPI>; 149659983a5cSKonrad Dybcio dma-names = "tx", "rx"; 149701e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 149801e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 149959983a5cSKonrad Dybcio #address-cells = <1>; 150059983a5cSKonrad Dybcio #size-cells = <0>; 1501e5813b15SDmitry Baryshkov status = "disabled"; 1502e5813b15SDmitry Baryshkov }; 1503e5813b15SDmitry Baryshkov }; 1504e5813b15SDmitry Baryshkov 150515049bb5SKonrad Dybcio gpi_dma1: dma-controller@a00000 { 150615049bb5SKonrad Dybcio compatible = "qcom,sm8250-gpi-dma"; 150715049bb5SKonrad Dybcio reg = <0 0x00a00000 0 0x70000>; 150815049bb5SKonrad Dybcio interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 150915049bb5SKonrad Dybcio <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 151015049bb5SKonrad Dybcio <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 151115049bb5SKonrad Dybcio <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 151215049bb5SKonrad Dybcio <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 151315049bb5SKonrad Dybcio <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 151415049bb5SKonrad Dybcio <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 151515049bb5SKonrad Dybcio <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 151615049bb5SKonrad Dybcio <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 151715049bb5SKonrad Dybcio <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 151815049bb5SKonrad Dybcio dma-channels = <10>; 151915049bb5SKonrad Dybcio dma-channel-mask = <0x3f>; 152015049bb5SKonrad Dybcio iommus = <&apps_smmu 0x56 0x0>; 152115049bb5SKonrad Dybcio #dma-cells = <3>; 152215049bb5SKonrad Dybcio status = "disabled"; 152315049bb5SKonrad Dybcio }; 152415049bb5SKonrad Dybcio 152560378f1aSVenkata Narendra Kumar Gutta qupv3_id_1: geniqup@ac0000 { 152660378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,geni-se-qup"; 152760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x00ac0000 0x0 0x6000>; 152860378f1aSVenkata Narendra Kumar Gutta clock-names = "m-ahb", "s-ahb"; 1529fe3dfc25SJonathan Marek clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1530fe3dfc25SJonathan Marek <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 153160378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 153260378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 153385309393SDmitry Baryshkov iommus = <&apps_smmu 0x43 0x0>; 153460378f1aSVenkata Narendra Kumar Gutta ranges; 153560378f1aSVenkata Narendra Kumar Gutta status = "disabled"; 153660378f1aSVenkata Narendra Kumar Gutta 1537e5813b15SDmitry Baryshkov i2c8: i2c@a80000 { 1538e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1539e5813b15SDmitry Baryshkov reg = <0 0x00a80000 0 0x4000>; 1540e5813b15SDmitry Baryshkov clock-names = "se"; 1541e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1542e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1543e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c8_default>; 1544e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 154559983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 154659983a5cSKonrad Dybcio <&gpi_dma1 1 0 QCOM_GPI_I2C>; 154759983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1548e5813b15SDmitry Baryshkov #address-cells = <1>; 1549e5813b15SDmitry Baryshkov #size-cells = <0>; 1550e5813b15SDmitry Baryshkov status = "disabled"; 1551e5813b15SDmitry Baryshkov }; 1552e5813b15SDmitry Baryshkov 1553e5813b15SDmitry Baryshkov spi8: spi@a80000 { 1554e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1555e5813b15SDmitry Baryshkov reg = <0 0x00a80000 0 0x4000>; 1556e5813b15SDmitry Baryshkov clock-names = "se"; 1557e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1558e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 155959983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 156059983a5cSKonrad Dybcio <&gpi_dma1 1 0 QCOM_GPI_SPI>; 156159983a5cSKonrad Dybcio dma-names = "tx", "rx"; 156201e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 156301e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 156459983a5cSKonrad Dybcio #address-cells = <1>; 156559983a5cSKonrad Dybcio #size-cells = <0>; 1566e5813b15SDmitry Baryshkov status = "disabled"; 1567e5813b15SDmitry Baryshkov }; 1568e5813b15SDmitry Baryshkov 1569e5813b15SDmitry Baryshkov i2c9: i2c@a84000 { 1570e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1571e5813b15SDmitry Baryshkov reg = <0 0x00a84000 0 0x4000>; 1572e5813b15SDmitry Baryshkov clock-names = "se"; 1573e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1574e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1575e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c9_default>; 1576e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 157759983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 157859983a5cSKonrad Dybcio <&gpi_dma1 1 1 QCOM_GPI_I2C>; 157959983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1580e5813b15SDmitry Baryshkov #address-cells = <1>; 1581e5813b15SDmitry Baryshkov #size-cells = <0>; 1582e5813b15SDmitry Baryshkov status = "disabled"; 1583e5813b15SDmitry Baryshkov }; 1584e5813b15SDmitry Baryshkov 1585e5813b15SDmitry Baryshkov spi9: spi@a84000 { 1586e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1587e5813b15SDmitry Baryshkov reg = <0 0x00a84000 0 0x4000>; 1588e5813b15SDmitry Baryshkov clock-names = "se"; 1589e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1590e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 159159983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 159259983a5cSKonrad Dybcio <&gpi_dma1 1 1 QCOM_GPI_SPI>; 159359983a5cSKonrad Dybcio dma-names = "tx", "rx"; 159401e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 159501e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 159659983a5cSKonrad Dybcio #address-cells = <1>; 159759983a5cSKonrad Dybcio #size-cells = <0>; 1598e5813b15SDmitry Baryshkov status = "disabled"; 1599e5813b15SDmitry Baryshkov }; 1600e5813b15SDmitry Baryshkov 1601e5813b15SDmitry Baryshkov i2c10: i2c@a88000 { 1602e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1603e5813b15SDmitry Baryshkov reg = <0 0x00a88000 0 0x4000>; 1604e5813b15SDmitry Baryshkov clock-names = "se"; 1605e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1606e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1607e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c10_default>; 1608e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 160959983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 161059983a5cSKonrad Dybcio <&gpi_dma1 1 2 QCOM_GPI_I2C>; 161159983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1612e5813b15SDmitry Baryshkov #address-cells = <1>; 1613e5813b15SDmitry Baryshkov #size-cells = <0>; 1614e5813b15SDmitry Baryshkov status = "disabled"; 1615e5813b15SDmitry Baryshkov }; 1616e5813b15SDmitry Baryshkov 1617e5813b15SDmitry Baryshkov spi10: spi@a88000 { 1618e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1619e5813b15SDmitry Baryshkov reg = <0 0x00a88000 0 0x4000>; 1620e5813b15SDmitry Baryshkov clock-names = "se"; 1621e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1622e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 162359983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 162459983a5cSKonrad Dybcio <&gpi_dma1 1 2 QCOM_GPI_SPI>; 162559983a5cSKonrad Dybcio dma-names = "tx", "rx"; 162601e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 162701e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 162859983a5cSKonrad Dybcio #address-cells = <1>; 162959983a5cSKonrad Dybcio #size-cells = <0>; 1630e5813b15SDmitry Baryshkov status = "disabled"; 1631e5813b15SDmitry Baryshkov }; 1632e5813b15SDmitry Baryshkov 1633e5813b15SDmitry Baryshkov i2c11: i2c@a8c000 { 1634e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1635e5813b15SDmitry Baryshkov reg = <0 0x00a8c000 0 0x4000>; 1636e5813b15SDmitry Baryshkov clock-names = "se"; 1637e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1638e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1639e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c11_default>; 1640e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 164159983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 164259983a5cSKonrad Dybcio <&gpi_dma1 1 3 QCOM_GPI_I2C>; 164359983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1644e5813b15SDmitry Baryshkov #address-cells = <1>; 1645e5813b15SDmitry Baryshkov #size-cells = <0>; 1646e5813b15SDmitry Baryshkov status = "disabled"; 1647e5813b15SDmitry Baryshkov }; 1648e5813b15SDmitry Baryshkov 1649e5813b15SDmitry Baryshkov spi11: spi@a8c000 { 1650e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1651e5813b15SDmitry Baryshkov reg = <0 0x00a8c000 0 0x4000>; 1652e5813b15SDmitry Baryshkov clock-names = "se"; 1653e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1654e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 165559983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 165659983a5cSKonrad Dybcio <&gpi_dma1 1 3 QCOM_GPI_SPI>; 165759983a5cSKonrad Dybcio dma-names = "tx", "rx"; 165801e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 165901e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 166059983a5cSKonrad Dybcio #address-cells = <1>; 166159983a5cSKonrad Dybcio #size-cells = <0>; 1662e5813b15SDmitry Baryshkov status = "disabled"; 1663e5813b15SDmitry Baryshkov }; 1664e5813b15SDmitry Baryshkov 1665e5813b15SDmitry Baryshkov i2c12: i2c@a90000 { 1666e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1667e5813b15SDmitry Baryshkov reg = <0 0x00a90000 0 0x4000>; 1668e5813b15SDmitry Baryshkov clock-names = "se"; 1669e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1670e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1671e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c12_default>; 1672e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 167359983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 167459983a5cSKonrad Dybcio <&gpi_dma1 1 4 QCOM_GPI_I2C>; 167559983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1676e5813b15SDmitry Baryshkov #address-cells = <1>; 1677e5813b15SDmitry Baryshkov #size-cells = <0>; 1678e5813b15SDmitry Baryshkov status = "disabled"; 1679e5813b15SDmitry Baryshkov }; 1680e5813b15SDmitry Baryshkov 1681e5813b15SDmitry Baryshkov spi12: spi@a90000 { 1682e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1683e5813b15SDmitry Baryshkov reg = <0 0x00a90000 0 0x4000>; 1684e5813b15SDmitry Baryshkov clock-names = "se"; 1685e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1686e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 168759983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 168859983a5cSKonrad Dybcio <&gpi_dma1 1 4 QCOM_GPI_SPI>; 168959983a5cSKonrad Dybcio dma-names = "tx", "rx"; 169001e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 169101e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 169259983a5cSKonrad Dybcio #address-cells = <1>; 169359983a5cSKonrad Dybcio #size-cells = <0>; 1694e5813b15SDmitry Baryshkov status = "disabled"; 1695e5813b15SDmitry Baryshkov }; 1696e5813b15SDmitry Baryshkov 1697bb1dfb4dSManivannan Sadhasivam uart12: serial@a90000 { 169860378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,geni-debug-uart"; 169960378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x00a90000 0x0 0x4000>; 170060378f1aSVenkata Narendra Kumar Gutta clock-names = "se"; 1701fe3dfc25SJonathan Marek clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1702bb1dfb4dSManivannan Sadhasivam pinctrl-names = "default"; 1703bb1dfb4dSManivannan Sadhasivam pinctrl-0 = <&qup_uart12_default>; 170460378f1aSVenkata Narendra Kumar Gutta interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 170501e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 170601e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 170760378f1aSVenkata Narendra Kumar Gutta status = "disabled"; 170860378f1aSVenkata Narendra Kumar Gutta }; 1709e5813b15SDmitry Baryshkov 1710e5813b15SDmitry Baryshkov i2c13: i2c@a94000 { 1711e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1712e5813b15SDmitry Baryshkov reg = <0 0x00a94000 0 0x4000>; 1713e5813b15SDmitry Baryshkov clock-names = "se"; 1714e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1715e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1716e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c13_default>; 1717e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 171859983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 171959983a5cSKonrad Dybcio <&gpi_dma1 1 5 QCOM_GPI_I2C>; 172059983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1721e5813b15SDmitry Baryshkov #address-cells = <1>; 1722e5813b15SDmitry Baryshkov #size-cells = <0>; 1723e5813b15SDmitry Baryshkov status = "disabled"; 1724e5813b15SDmitry Baryshkov }; 1725e5813b15SDmitry Baryshkov 1726e5813b15SDmitry Baryshkov spi13: spi@a94000 { 1727e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1728e5813b15SDmitry Baryshkov reg = <0 0x00a94000 0 0x4000>; 1729e5813b15SDmitry Baryshkov clock-names = "se"; 1730e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1731e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 173259983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 173359983a5cSKonrad Dybcio <&gpi_dma1 1 5 QCOM_GPI_SPI>; 173459983a5cSKonrad Dybcio dma-names = "tx", "rx"; 173501e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 173601e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 173759983a5cSKonrad Dybcio #address-cells = <1>; 173859983a5cSKonrad Dybcio #size-cells = <0>; 1739e5813b15SDmitry Baryshkov status = "disabled"; 1740e5813b15SDmitry Baryshkov }; 174160378f1aSVenkata Narendra Kumar Gutta }; 174260378f1aSVenkata Narendra Kumar Gutta 1743e7e41a20SJonathan Marek config_noc: interconnect@1500000 { 1744e7e41a20SJonathan Marek compatible = "qcom,sm8250-config-noc"; 1745e7e41a20SJonathan Marek reg = <0 0x01500000 0 0xa580>; 1746e7e41a20SJonathan Marek #interconnect-cells = <1>; 1747e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1748e7e41a20SJonathan Marek }; 1749e7e41a20SJonathan Marek 1750e7e41a20SJonathan Marek system_noc: interconnect@1620000 { 1751e7e41a20SJonathan Marek compatible = "qcom,sm8250-system-noc"; 1752e7e41a20SJonathan Marek reg = <0 0x01620000 0 0x1c200>; 1753e7e41a20SJonathan Marek #interconnect-cells = <1>; 1754e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1755e7e41a20SJonathan Marek }; 1756e7e41a20SJonathan Marek 1757e7e41a20SJonathan Marek mc_virt: interconnect@163d000 { 1758e7e41a20SJonathan Marek compatible = "qcom,sm8250-mc-virt"; 1759e7e41a20SJonathan Marek reg = <0 0x0163d000 0 0x1000>; 1760e7e41a20SJonathan Marek #interconnect-cells = <1>; 1761e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1762e7e41a20SJonathan Marek }; 1763e7e41a20SJonathan Marek 1764e7e41a20SJonathan Marek aggre1_noc: interconnect@16e0000 { 1765e7e41a20SJonathan Marek compatible = "qcom,sm8250-aggre1-noc"; 1766e7e41a20SJonathan Marek reg = <0 0x016e0000 0 0x1f180>; 1767e7e41a20SJonathan Marek #interconnect-cells = <1>; 1768e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1769e7e41a20SJonathan Marek }; 1770e7e41a20SJonathan Marek 1771e7e41a20SJonathan Marek aggre2_noc: interconnect@1700000 { 1772e7e41a20SJonathan Marek compatible = "qcom,sm8250-aggre2-noc"; 1773e7e41a20SJonathan Marek reg = <0 0x01700000 0 0x33000>; 1774e7e41a20SJonathan Marek #interconnect-cells = <1>; 1775e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1776e7e41a20SJonathan Marek }; 1777e7e41a20SJonathan Marek 1778e7e41a20SJonathan Marek compute_noc: interconnect@1733000 { 1779e7e41a20SJonathan Marek compatible = "qcom,sm8250-compute-noc"; 1780e7e41a20SJonathan Marek reg = <0 0x01733000 0 0xa180>; 1781e7e41a20SJonathan Marek #interconnect-cells = <1>; 1782e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1783e7e41a20SJonathan Marek }; 1784e7e41a20SJonathan Marek 1785e7e41a20SJonathan Marek mmss_noc: interconnect@1740000 { 1786e7e41a20SJonathan Marek compatible = "qcom,sm8250-mmss-noc"; 1787e7e41a20SJonathan Marek reg = <0 0x01740000 0 0x1f080>; 1788e7e41a20SJonathan Marek #interconnect-cells = <1>; 1789e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1790e7e41a20SJonathan Marek }; 1791e7e41a20SJonathan Marek 1792e53bdfc0SManivannan Sadhasivam pcie0: pci@1c00000 { 1793e53bdfc0SManivannan Sadhasivam compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1794e53bdfc0SManivannan Sadhasivam reg = <0 0x01c00000 0 0x3000>, 1795e53bdfc0SManivannan Sadhasivam <0 0x60000000 0 0xf1d>, 1796e53bdfc0SManivannan Sadhasivam <0 0x60000f20 0 0xa8>, 1797e53bdfc0SManivannan Sadhasivam <0 0x60001000 0 0x1000>, 1798e53bdfc0SManivannan Sadhasivam <0 0x60100000 0 0x100000>; 1799e53bdfc0SManivannan Sadhasivam reg-names = "parf", "dbi", "elbi", "atu", "config"; 1800e53bdfc0SManivannan Sadhasivam device_type = "pci"; 1801e53bdfc0SManivannan Sadhasivam linux,pci-domain = <0>; 1802e53bdfc0SManivannan Sadhasivam bus-range = <0x00 0xff>; 1803e53bdfc0SManivannan Sadhasivam num-lanes = <1>; 1804e53bdfc0SManivannan Sadhasivam 1805e53bdfc0SManivannan Sadhasivam #address-cells = <3>; 1806e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1807e53bdfc0SManivannan Sadhasivam 1808e53bdfc0SManivannan Sadhasivam ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1809e53bdfc0SManivannan Sadhasivam <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1810e53bdfc0SManivannan Sadhasivam 1811e53bdfc0SManivannan Sadhasivam interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1812e53bdfc0SManivannan Sadhasivam interrupt-names = "msi"; 1813e53bdfc0SManivannan Sadhasivam #interrupt-cells = <1>; 1814e53bdfc0SManivannan Sadhasivam interrupt-map-mask = <0 0 0 0x7>; 1815e53bdfc0SManivannan Sadhasivam interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1816e53bdfc0SManivannan Sadhasivam <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1817e53bdfc0SManivannan Sadhasivam <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1818e53bdfc0SManivannan Sadhasivam <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1819e53bdfc0SManivannan Sadhasivam 1820e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1821e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_AUX_CLK>, 1822e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1823e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1824e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1825e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1826e53bdfc0SManivannan Sadhasivam <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1827e53bdfc0SManivannan Sadhasivam <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1828e53bdfc0SManivannan Sadhasivam clock-names = "pipe", 1829e53bdfc0SManivannan Sadhasivam "aux", 1830e53bdfc0SManivannan Sadhasivam "cfg", 1831e53bdfc0SManivannan Sadhasivam "bus_master", 1832e53bdfc0SManivannan Sadhasivam "bus_slave", 1833e53bdfc0SManivannan Sadhasivam "slave_q2a", 1834e53bdfc0SManivannan Sadhasivam "tbu", 1835e53bdfc0SManivannan Sadhasivam "ddrss_sf_tbu"; 1836e53bdfc0SManivannan Sadhasivam 1837e53bdfc0SManivannan Sadhasivam iommus = <&apps_smmu 0x1c00 0x7f>; 1838e53bdfc0SManivannan Sadhasivam iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1839e53bdfc0SManivannan Sadhasivam <0x100 &apps_smmu 0x1c01 0x1>; 1840e53bdfc0SManivannan Sadhasivam 1841e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_0_BCR>; 1842e53bdfc0SManivannan Sadhasivam reset-names = "pci"; 1843e53bdfc0SManivannan Sadhasivam 1844e53bdfc0SManivannan Sadhasivam power-domains = <&gcc PCIE_0_GDSC>; 1845e53bdfc0SManivannan Sadhasivam 1846e53bdfc0SManivannan Sadhasivam phys = <&pcie0_lane>; 1847e53bdfc0SManivannan Sadhasivam phy-names = "pciephy"; 1848e53bdfc0SManivannan Sadhasivam 1849d6050720SDmitry Baryshkov perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; 1850d6050720SDmitry Baryshkov wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 185113e948a3SKonrad Dybcio 185213e948a3SKonrad Dybcio pinctrl-names = "default"; 185313e948a3SKonrad Dybcio pinctrl-0 = <&pcie0_default_state>; 185413e948a3SKonrad Dybcio 1855e53bdfc0SManivannan Sadhasivam status = "disabled"; 1856e53bdfc0SManivannan Sadhasivam }; 1857e53bdfc0SManivannan Sadhasivam 1858e53bdfc0SManivannan Sadhasivam pcie0_phy: phy@1c06000 { 1859e53bdfc0SManivannan Sadhasivam compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1860e53bdfc0SManivannan Sadhasivam reg = <0 0x01c06000 0 0x1c0>; 1861e53bdfc0SManivannan Sadhasivam #address-cells = <2>; 1862e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1863e53bdfc0SManivannan Sadhasivam ranges; 1864e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1865e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1866e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1867e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1868e53bdfc0SManivannan Sadhasivam clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1869e53bdfc0SManivannan Sadhasivam 1870e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1871e53bdfc0SManivannan Sadhasivam reset-names = "phy"; 1872e53bdfc0SManivannan Sadhasivam 1873e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1874e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <100000000>; 1875e53bdfc0SManivannan Sadhasivam 1876e53bdfc0SManivannan Sadhasivam status = "disabled"; 1877e53bdfc0SManivannan Sadhasivam 18781351512fSShawn Guo pcie0_lane: phy@1c06200 { 1879e53bdfc0SManivannan Sadhasivam reg = <0 0x1c06200 0 0x170>, /* tx */ 1880e53bdfc0SManivannan Sadhasivam <0 0x1c06400 0 0x200>, /* rx */ 1881e53bdfc0SManivannan Sadhasivam <0 0x1c06800 0 0x1f0>, /* pcs */ 1882e53bdfc0SManivannan Sadhasivam <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1883e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1884e53bdfc0SManivannan Sadhasivam clock-names = "pipe0"; 1885e53bdfc0SManivannan Sadhasivam 1886e53bdfc0SManivannan Sadhasivam #phy-cells = <0>; 1887e53bdfc0SManivannan Sadhasivam clock-output-names = "pcie_0_pipe_clk"; 1888e53bdfc0SManivannan Sadhasivam }; 1889e53bdfc0SManivannan Sadhasivam }; 1890e53bdfc0SManivannan Sadhasivam 1891e53bdfc0SManivannan Sadhasivam pcie1: pci@1c08000 { 1892e53bdfc0SManivannan Sadhasivam compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1893e53bdfc0SManivannan Sadhasivam reg = <0 0x01c08000 0 0x3000>, 1894e53bdfc0SManivannan Sadhasivam <0 0x40000000 0 0xf1d>, 1895e53bdfc0SManivannan Sadhasivam <0 0x40000f20 0 0xa8>, 1896e53bdfc0SManivannan Sadhasivam <0 0x40001000 0 0x1000>, 1897e53bdfc0SManivannan Sadhasivam <0 0x40100000 0 0x100000>; 1898e53bdfc0SManivannan Sadhasivam reg-names = "parf", "dbi", "elbi", "atu", "config"; 1899e53bdfc0SManivannan Sadhasivam device_type = "pci"; 1900e53bdfc0SManivannan Sadhasivam linux,pci-domain = <1>; 1901e53bdfc0SManivannan Sadhasivam bus-range = <0x00 0xff>; 1902e53bdfc0SManivannan Sadhasivam num-lanes = <2>; 1903e53bdfc0SManivannan Sadhasivam 1904e53bdfc0SManivannan Sadhasivam #address-cells = <3>; 1905e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1906e53bdfc0SManivannan Sadhasivam 1907e53bdfc0SManivannan Sadhasivam ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1908e53bdfc0SManivannan Sadhasivam <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1909e53bdfc0SManivannan Sadhasivam 19101b7101e8SManivannan Sadhasivam interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1911e53bdfc0SManivannan Sadhasivam interrupt-names = "msi"; 1912e53bdfc0SManivannan Sadhasivam #interrupt-cells = <1>; 1913e53bdfc0SManivannan Sadhasivam interrupt-map-mask = <0 0 0 0x7>; 1914e53bdfc0SManivannan Sadhasivam interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1915e53bdfc0SManivannan Sadhasivam <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1916e53bdfc0SManivannan Sadhasivam <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1917e53bdfc0SManivannan Sadhasivam <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1918e53bdfc0SManivannan Sadhasivam 1919e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1920e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_AUX_CLK>, 1921e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1922e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1923e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1924e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1925e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1926e53bdfc0SManivannan Sadhasivam <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1927e53bdfc0SManivannan Sadhasivam <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1928e53bdfc0SManivannan Sadhasivam clock-names = "pipe", 1929e53bdfc0SManivannan Sadhasivam "aux", 1930e53bdfc0SManivannan Sadhasivam "cfg", 1931e53bdfc0SManivannan Sadhasivam "bus_master", 1932e53bdfc0SManivannan Sadhasivam "bus_slave", 1933e53bdfc0SManivannan Sadhasivam "slave_q2a", 1934e53bdfc0SManivannan Sadhasivam "ref", 1935e53bdfc0SManivannan Sadhasivam "tbu", 1936e53bdfc0SManivannan Sadhasivam "ddrss_sf_tbu"; 1937e53bdfc0SManivannan Sadhasivam 1938e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1939e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <19200000>; 1940e53bdfc0SManivannan Sadhasivam 1941e53bdfc0SManivannan Sadhasivam iommus = <&apps_smmu 0x1c80 0x7f>; 1942e53bdfc0SManivannan Sadhasivam iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1943e53bdfc0SManivannan Sadhasivam <0x100 &apps_smmu 0x1c81 0x1>; 1944e53bdfc0SManivannan Sadhasivam 1945e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_1_BCR>; 1946e53bdfc0SManivannan Sadhasivam reset-names = "pci"; 1947e53bdfc0SManivannan Sadhasivam 1948e53bdfc0SManivannan Sadhasivam power-domains = <&gcc PCIE_1_GDSC>; 1949e53bdfc0SManivannan Sadhasivam 1950e53bdfc0SManivannan Sadhasivam phys = <&pcie1_lane>; 1951e53bdfc0SManivannan Sadhasivam phy-names = "pciephy"; 1952e53bdfc0SManivannan Sadhasivam 1953d6050720SDmitry Baryshkov perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; 1954d6050720SDmitry Baryshkov wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; 195513e948a3SKonrad Dybcio 195613e948a3SKonrad Dybcio pinctrl-names = "default"; 195713e948a3SKonrad Dybcio pinctrl-0 = <&pcie1_default_state>; 195813e948a3SKonrad Dybcio 1959e53bdfc0SManivannan Sadhasivam status = "disabled"; 1960e53bdfc0SManivannan Sadhasivam }; 1961e53bdfc0SManivannan Sadhasivam 1962e53bdfc0SManivannan Sadhasivam pcie1_phy: phy@1c0e000 { 1963e53bdfc0SManivannan Sadhasivam compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1964e53bdfc0SManivannan Sadhasivam reg = <0 0x01c0e000 0 0x1c0>; 1965e53bdfc0SManivannan Sadhasivam #address-cells = <2>; 1966e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1967e53bdfc0SManivannan Sadhasivam ranges; 1968e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1969e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1970e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1971e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1972e53bdfc0SManivannan Sadhasivam clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1973e53bdfc0SManivannan Sadhasivam 1974e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1975e53bdfc0SManivannan Sadhasivam reset-names = "phy"; 1976e53bdfc0SManivannan Sadhasivam 1977e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1978e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <100000000>; 1979e53bdfc0SManivannan Sadhasivam 1980e53bdfc0SManivannan Sadhasivam status = "disabled"; 1981e53bdfc0SManivannan Sadhasivam 19821351512fSShawn Guo pcie1_lane: phy@1c0e200 { 1983e53bdfc0SManivannan Sadhasivam reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1984e53bdfc0SManivannan Sadhasivam <0 0x1c0e400 0 0x200>, /* rx0 */ 1985e53bdfc0SManivannan Sadhasivam <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1986e53bdfc0SManivannan Sadhasivam <0 0x1c0e600 0 0x170>, /* tx1 */ 1987e53bdfc0SManivannan Sadhasivam <0 0x1c0e800 0 0x200>, /* rx1 */ 1988e53bdfc0SManivannan Sadhasivam <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1989e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1990e53bdfc0SManivannan Sadhasivam clock-names = "pipe0"; 1991e53bdfc0SManivannan Sadhasivam 1992e53bdfc0SManivannan Sadhasivam #phy-cells = <0>; 1993e53bdfc0SManivannan Sadhasivam clock-output-names = "pcie_1_pipe_clk"; 1994e53bdfc0SManivannan Sadhasivam }; 1995e53bdfc0SManivannan Sadhasivam }; 1996e53bdfc0SManivannan Sadhasivam 1997e53bdfc0SManivannan Sadhasivam pcie2: pci@1c10000 { 1998e53bdfc0SManivannan Sadhasivam compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1999e53bdfc0SManivannan Sadhasivam reg = <0 0x01c10000 0 0x3000>, 2000e53bdfc0SManivannan Sadhasivam <0 0x64000000 0 0xf1d>, 2001e53bdfc0SManivannan Sadhasivam <0 0x64000f20 0 0xa8>, 2002e53bdfc0SManivannan Sadhasivam <0 0x64001000 0 0x1000>, 2003e53bdfc0SManivannan Sadhasivam <0 0x64100000 0 0x100000>; 2004e53bdfc0SManivannan Sadhasivam reg-names = "parf", "dbi", "elbi", "atu", "config"; 2005e53bdfc0SManivannan Sadhasivam device_type = "pci"; 2006e53bdfc0SManivannan Sadhasivam linux,pci-domain = <2>; 2007e53bdfc0SManivannan Sadhasivam bus-range = <0x00 0xff>; 2008e53bdfc0SManivannan Sadhasivam num-lanes = <2>; 2009e53bdfc0SManivannan Sadhasivam 2010e53bdfc0SManivannan Sadhasivam #address-cells = <3>; 2011e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 2012e53bdfc0SManivannan Sadhasivam 2013e53bdfc0SManivannan Sadhasivam ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, 2014e53bdfc0SManivannan Sadhasivam <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 2015e53bdfc0SManivannan Sadhasivam 20161b7101e8SManivannan Sadhasivam interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2017e53bdfc0SManivannan Sadhasivam interrupt-names = "msi"; 2018e53bdfc0SManivannan Sadhasivam #interrupt-cells = <1>; 2019e53bdfc0SManivannan Sadhasivam interrupt-map-mask = <0 0 0 0x7>; 2020e53bdfc0SManivannan Sadhasivam interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2021e53bdfc0SManivannan Sadhasivam <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2022e53bdfc0SManivannan Sadhasivam <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2023e53bdfc0SManivannan Sadhasivam <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2024e53bdfc0SManivannan Sadhasivam 2025e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2026e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_AUX_CLK>, 2027e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2028e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2029e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2030e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2031e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2032e53bdfc0SManivannan Sadhasivam <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2033e53bdfc0SManivannan Sadhasivam <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2034e53bdfc0SManivannan Sadhasivam clock-names = "pipe", 2035e53bdfc0SManivannan Sadhasivam "aux", 2036e53bdfc0SManivannan Sadhasivam "cfg", 2037e53bdfc0SManivannan Sadhasivam "bus_master", 2038e53bdfc0SManivannan Sadhasivam "bus_slave", 2039e53bdfc0SManivannan Sadhasivam "slave_q2a", 2040e53bdfc0SManivannan Sadhasivam "ref", 2041e53bdfc0SManivannan Sadhasivam "tbu", 2042e53bdfc0SManivannan Sadhasivam "ddrss_sf_tbu"; 2043e53bdfc0SManivannan Sadhasivam 2044e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2045e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <19200000>; 2046e53bdfc0SManivannan Sadhasivam 2047e53bdfc0SManivannan Sadhasivam iommus = <&apps_smmu 0x1d00 0x7f>; 2048e53bdfc0SManivannan Sadhasivam iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2049e53bdfc0SManivannan Sadhasivam <0x100 &apps_smmu 0x1d01 0x1>; 2050e53bdfc0SManivannan Sadhasivam 2051e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_2_BCR>; 2052e53bdfc0SManivannan Sadhasivam reset-names = "pci"; 2053e53bdfc0SManivannan Sadhasivam 2054e53bdfc0SManivannan Sadhasivam power-domains = <&gcc PCIE_2_GDSC>; 2055e53bdfc0SManivannan Sadhasivam 2056e53bdfc0SManivannan Sadhasivam phys = <&pcie2_lane>; 2057e53bdfc0SManivannan Sadhasivam phy-names = "pciephy"; 2058e53bdfc0SManivannan Sadhasivam 2059d6050720SDmitry Baryshkov perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; 2060d6050720SDmitry Baryshkov wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 206113e948a3SKonrad Dybcio 206213e948a3SKonrad Dybcio pinctrl-names = "default"; 206313e948a3SKonrad Dybcio pinctrl-0 = <&pcie2_default_state>; 206413e948a3SKonrad Dybcio 2065e53bdfc0SManivannan Sadhasivam status = "disabled"; 2066e53bdfc0SManivannan Sadhasivam }; 2067e53bdfc0SManivannan Sadhasivam 2068e53bdfc0SManivannan Sadhasivam pcie2_phy: phy@1c16000 { 2069e53bdfc0SManivannan Sadhasivam compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 2070e53bdfc0SManivannan Sadhasivam reg = <0 0x1c16000 0 0x1c0>; 2071e53bdfc0SManivannan Sadhasivam #address-cells = <2>; 2072e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 2073e53bdfc0SManivannan Sadhasivam ranges; 2074e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2075e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2076e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2077e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2078e53bdfc0SManivannan Sadhasivam clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2079e53bdfc0SManivannan Sadhasivam 2080e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2081e53bdfc0SManivannan Sadhasivam reset-names = "phy"; 2082e53bdfc0SManivannan Sadhasivam 2083e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2084e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <100000000>; 2085e53bdfc0SManivannan Sadhasivam 2086e53bdfc0SManivannan Sadhasivam status = "disabled"; 2087e53bdfc0SManivannan Sadhasivam 20881351512fSShawn Guo pcie2_lane: phy@1c16200 { 2089e53bdfc0SManivannan Sadhasivam reg = <0 0x1c16200 0 0x170>, /* tx0 */ 2090e53bdfc0SManivannan Sadhasivam <0 0x1c16400 0 0x200>, /* rx0 */ 2091e53bdfc0SManivannan Sadhasivam <0 0x1c16a00 0 0x1f0>, /* pcs */ 2092e53bdfc0SManivannan Sadhasivam <0 0x1c16600 0 0x170>, /* tx1 */ 2093e53bdfc0SManivannan Sadhasivam <0 0x1c16800 0 0x200>, /* rx1 */ 2094e53bdfc0SManivannan Sadhasivam <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2095e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 2096e53bdfc0SManivannan Sadhasivam clock-names = "pipe0"; 2097e53bdfc0SManivannan Sadhasivam 2098e53bdfc0SManivannan Sadhasivam #phy-cells = <0>; 2099e53bdfc0SManivannan Sadhasivam clock-output-names = "pcie_2_pipe_clk"; 2100e53bdfc0SManivannan Sadhasivam }; 2101e53bdfc0SManivannan Sadhasivam }; 2102e53bdfc0SManivannan Sadhasivam 21036b9afd8fSJonathan Marek ufs_mem_hc: ufshc@1d84000 { 2104b7e2fba0SBryan O'Donoghue compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 2105b7e2fba0SBryan O'Donoghue "jedec,ufs-2.0"; 2106b7e2fba0SBryan O'Donoghue reg = <0 0x01d84000 0 0x3000>; 2107b7e2fba0SBryan O'Donoghue interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2108b7e2fba0SBryan O'Donoghue phys = <&ufs_mem_phy_lanes>; 2109b7e2fba0SBryan O'Donoghue phy-names = "ufsphy"; 2110b7e2fba0SBryan O'Donoghue lanes-per-direction = <2>; 2111b7e2fba0SBryan O'Donoghue #reset-cells = <1>; 2112b7e2fba0SBryan O'Donoghue resets = <&gcc GCC_UFS_PHY_BCR>; 2113b7e2fba0SBryan O'Donoghue reset-names = "rst"; 2114b7e2fba0SBryan O'Donoghue 2115b7e2fba0SBryan O'Donoghue power-domains = <&gcc UFS_PHY_GDSC>; 2116b7e2fba0SBryan O'Donoghue 2117a89441fcSJonathan Marek iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 2118a89441fcSJonathan Marek 2119b7e2fba0SBryan O'Donoghue clock-names = 2120b7e2fba0SBryan O'Donoghue "core_clk", 2121b7e2fba0SBryan O'Donoghue "bus_aggr_clk", 2122b7e2fba0SBryan O'Donoghue "iface_clk", 2123b7e2fba0SBryan O'Donoghue "core_clk_unipro", 2124b7e2fba0SBryan O'Donoghue "ref_clk", 2125b7e2fba0SBryan O'Donoghue "tx_lane0_sync_clk", 2126b7e2fba0SBryan O'Donoghue "rx_lane0_sync_clk", 2127b7e2fba0SBryan O'Donoghue "rx_lane1_sync_clk"; 2128b7e2fba0SBryan O'Donoghue clocks = 2129b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_AXI_CLK>, 2130b7e2fba0SBryan O'Donoghue <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2131b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_AHB_CLK>, 2132b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2133b7e2fba0SBryan O'Donoghue <&rpmhcc RPMH_CXO_CLK>, 2134b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2135b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2136b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2137b7e2fba0SBryan O'Donoghue freq-table-hz = 2138b7e2fba0SBryan O'Donoghue <37500000 300000000>, 2139b7e2fba0SBryan O'Donoghue <0 0>, 2140b7e2fba0SBryan O'Donoghue <0 0>, 2141b7e2fba0SBryan O'Donoghue <37500000 300000000>, 2142b7e2fba0SBryan O'Donoghue <0 0>, 2143b7e2fba0SBryan O'Donoghue <0 0>, 2144b7e2fba0SBryan O'Donoghue <0 0>, 2145b7e2fba0SBryan O'Donoghue <0 0>; 2146b7e2fba0SBryan O'Donoghue 2147b7e2fba0SBryan O'Donoghue status = "disabled"; 2148b7e2fba0SBryan O'Donoghue }; 2149b7e2fba0SBryan O'Donoghue 2150b7e2fba0SBryan O'Donoghue ufs_mem_phy: phy@1d87000 { 2151b7e2fba0SBryan O'Donoghue compatible = "qcom,sm8250-qmp-ufs-phy"; 2152b7e2fba0SBryan O'Donoghue reg = <0 0x01d87000 0 0x1c0>; 2153b7e2fba0SBryan O'Donoghue #address-cells = <2>; 2154b7e2fba0SBryan O'Donoghue #size-cells = <2>; 2155b7e2fba0SBryan O'Donoghue ranges; 2156b7e2fba0SBryan O'Donoghue clock-names = "ref", 2157b7e2fba0SBryan O'Donoghue "ref_aux"; 2158b7e2fba0SBryan O'Donoghue clocks = <&rpmhcc RPMH_CXO_CLK>, 2159b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2160b7e2fba0SBryan O'Donoghue 2161b7e2fba0SBryan O'Donoghue resets = <&ufs_mem_hc 0>; 2162b7e2fba0SBryan O'Donoghue reset-names = "ufsphy"; 2163b7e2fba0SBryan O'Donoghue status = "disabled"; 2164b7e2fba0SBryan O'Donoghue 21651351512fSShawn Guo ufs_mem_phy_lanes: phy@1d87400 { 2166b7e2fba0SBryan O'Donoghue reg = <0 0x01d87400 0 0x108>, 2167b7e2fba0SBryan O'Donoghue <0 0x01d87600 0 0x1e0>, 2168b7e2fba0SBryan O'Donoghue <0 0x01d87c00 0 0x1dc>, 2169b7e2fba0SBryan O'Donoghue <0 0x01d87800 0 0x108>, 2170b7e2fba0SBryan O'Donoghue <0 0x01d87a00 0 0x1e0>; 2171b7e2fba0SBryan O'Donoghue #phy-cells = <0>; 2172b7e2fba0SBryan O'Donoghue }; 2173b7e2fba0SBryan O'Donoghue }; 2174b7e2fba0SBryan O'Donoghue 2175e7e41a20SJonathan Marek ipa_virt: interconnect@1e00000 { 2176e7e41a20SJonathan Marek compatible = "qcom,sm8250-ipa-virt"; 2177e7e41a20SJonathan Marek reg = <0 0x01e00000 0 0x1000>; 2178e7e41a20SJonathan Marek #interconnect-cells = <1>; 2179e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 2180e7e41a20SJonathan Marek }; 2181e7e41a20SJonathan Marek 2182dff0f49cSBjorn Andersson tcsr_mutex: hwlock@1f40000 { 2183dff0f49cSBjorn Andersson compatible = "qcom,tcsr-mutex"; 2184b9ec8cbcSJonathan Marek reg = <0x0 0x01f40000 0x0 0x40000>; 2185dff0f49cSBjorn Andersson #hwlock-cells = <1>; 218660378f1aSVenkata Narendra Kumar Gutta }; 218760378f1aSVenkata Narendra Kumar Gutta 2188768270caSSrinivas Kandagatla wsamacro: codec@3240000 { 2189768270caSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-wsa-macro"; 2190768270caSSrinivas Kandagatla reg = <0 0x03240000 0 0x1000>; 2191768270caSSrinivas Kandagatla clocks = <&audiocc 1>, 2192768270caSSrinivas Kandagatla <&audiocc 0>, 2193768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2194768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2195768270caSSrinivas Kandagatla <&aoncc 0>, 2196768270caSSrinivas Kandagatla <&vamacro>; 2197768270caSSrinivas Kandagatla 2198768270caSSrinivas Kandagatla clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 2199768270caSSrinivas Kandagatla 2200768270caSSrinivas Kandagatla #clock-cells = <0>; 2201768270caSSrinivas Kandagatla clock-frequency = <9600000>; 2202768270caSSrinivas Kandagatla clock-output-names = "mclk"; 2203768270caSSrinivas Kandagatla #sound-dai-cells = <1>; 2204768270caSSrinivas Kandagatla 2205768270caSSrinivas Kandagatla pinctrl-names = "default"; 2206768270caSSrinivas Kandagatla pinctrl-0 = <&wsa_swr_active>; 2207768270caSSrinivas Kandagatla }; 2208768270caSSrinivas Kandagatla 2209768270caSSrinivas Kandagatla swr0: soundwire-controller@3250000 { 2210768270caSSrinivas Kandagatla reg = <0 0x03250000 0 0x2000>; 2211768270caSSrinivas Kandagatla compatible = "qcom,soundwire-v1.5.1"; 2212768270caSSrinivas Kandagatla interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 2213768270caSSrinivas Kandagatla clocks = <&wsamacro>; 2214768270caSSrinivas Kandagatla clock-names = "iface"; 2215768270caSSrinivas Kandagatla 2216768270caSSrinivas Kandagatla qcom,din-ports = <2>; 2217768270caSSrinivas Kandagatla qcom,dout-ports = <6>; 2218768270caSSrinivas Kandagatla 2219768270caSSrinivas Kandagatla qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2220768270caSSrinivas Kandagatla qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2221768270caSSrinivas Kandagatla qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2222768270caSSrinivas Kandagatla qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 2223768270caSSrinivas Kandagatla 2224768270caSSrinivas Kandagatla #sound-dai-cells = <1>; 2225768270caSSrinivas Kandagatla #address-cells = <2>; 2226768270caSSrinivas Kandagatla #size-cells = <0>; 2227768270caSSrinivas Kandagatla }; 2228768270caSSrinivas Kandagatla 2229793bbd2dSSrinivas Kandagatla audiocc: clock-controller@3300000 { 2230793bbd2dSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-audiocc"; 2231793bbd2dSSrinivas Kandagatla reg = <0 0x03300000 0 0x30000>; 2232793bbd2dSSrinivas Kandagatla #clock-cells = <1>; 2233793bbd2dSSrinivas Kandagatla clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2234793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2235793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2236793bbd2dSSrinivas Kandagatla clock-names = "core", "audio", "bus"; 2237793bbd2dSSrinivas Kandagatla }; 2238793bbd2dSSrinivas Kandagatla 2239768270caSSrinivas Kandagatla vamacro: codec@3370000 { 2240768270caSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-va-macro"; 2241768270caSSrinivas Kandagatla reg = <0 0x03370000 0 0x1000>; 2242768270caSSrinivas Kandagatla clocks = <&aoncc 0>, 2243768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2244768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2245768270caSSrinivas Kandagatla 2246768270caSSrinivas Kandagatla clock-names = "mclk", "macro", "dcodec"; 2247768270caSSrinivas Kandagatla 2248768270caSSrinivas Kandagatla #clock-cells = <0>; 2249768270caSSrinivas Kandagatla clock-frequency = <9600000>; 2250768270caSSrinivas Kandagatla clock-output-names = "fsgen"; 2251768270caSSrinivas Kandagatla #sound-dai-cells = <1>; 2252768270caSSrinivas Kandagatla }; 2253768270caSSrinivas Kandagatla 225424f52ef0SSrinivas Kandagatla rxmacro: rxmacro@3200000 { 225524f52ef0SSrinivas Kandagatla pinctrl-names = "default"; 225624f52ef0SSrinivas Kandagatla pinctrl-0 = <&rx_swr_active>; 225724f52ef0SSrinivas Kandagatla compatible = "qcom,sm8250-lpass-rx-macro"; 225824f52ef0SSrinivas Kandagatla reg = <0 0x3200000 0 0x1000>; 225924f52ef0SSrinivas Kandagatla 226024f52ef0SSrinivas Kandagatla clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 226124f52ef0SSrinivas Kandagatla <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 226224f52ef0SSrinivas Kandagatla <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 226324f52ef0SSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 226424f52ef0SSrinivas Kandagatla <&vamacro>; 226524f52ef0SSrinivas Kandagatla 226624f52ef0SSrinivas Kandagatla clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 226724f52ef0SSrinivas Kandagatla 226824f52ef0SSrinivas Kandagatla #clock-cells = <0>; 226924f52ef0SSrinivas Kandagatla clock-frequency = <9600000>; 227024f52ef0SSrinivas Kandagatla clock-output-names = "mclk"; 227124f52ef0SSrinivas Kandagatla #sound-dai-cells = <1>; 227224f52ef0SSrinivas Kandagatla }; 227324f52ef0SSrinivas Kandagatla 227424f52ef0SSrinivas Kandagatla swr1: soundwire-controller@3210000 { 227524f52ef0SSrinivas Kandagatla reg = <0 0x3210000 0 0x2000>; 227624f52ef0SSrinivas Kandagatla compatible = "qcom,soundwire-v1.5.1"; 227724f52ef0SSrinivas Kandagatla interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 227824f52ef0SSrinivas Kandagatla clocks = <&rxmacro>; 227924f52ef0SSrinivas Kandagatla clock-names = "iface"; 228024f52ef0SSrinivas Kandagatla label = "RX"; 228124f52ef0SSrinivas Kandagatla qcom,din-ports = <0>; 228224f52ef0SSrinivas Kandagatla qcom,dout-ports = <5>; 228324f52ef0SSrinivas Kandagatla 228424f52ef0SSrinivas Kandagatla qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>; 228524f52ef0SSrinivas Kandagatla qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 228624f52ef0SSrinivas Kandagatla qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 228724f52ef0SSrinivas Kandagatla qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>; 228824f52ef0SSrinivas Kandagatla qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>; 228924f52ef0SSrinivas Kandagatla qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>; 229024f52ef0SSrinivas Kandagatla qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>; 229124f52ef0SSrinivas Kandagatla qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 229224f52ef0SSrinivas Kandagatla qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>; 229324f52ef0SSrinivas Kandagatla 229424f52ef0SSrinivas Kandagatla #sound-dai-cells = <1>; 229524f52ef0SSrinivas Kandagatla #address-cells = <2>; 229624f52ef0SSrinivas Kandagatla #size-cells = <0>; 229724f52ef0SSrinivas Kandagatla }; 229824f52ef0SSrinivas Kandagatla 229924f52ef0SSrinivas Kandagatla txmacro: txmacro@3220000 { 230024f52ef0SSrinivas Kandagatla pinctrl-names = "default"; 230124f52ef0SSrinivas Kandagatla pinctrl-0 = <&tx_swr_active>; 230224f52ef0SSrinivas Kandagatla compatible = "qcom,sm8250-lpass-tx-macro"; 230324f52ef0SSrinivas Kandagatla reg = <0 0x3220000 0 0x1000>; 230424f52ef0SSrinivas Kandagatla 230524f52ef0SSrinivas Kandagatla clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 230624f52ef0SSrinivas Kandagatla <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 230724f52ef0SSrinivas Kandagatla <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 230824f52ef0SSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 230924f52ef0SSrinivas Kandagatla <&vamacro>; 231024f52ef0SSrinivas Kandagatla 231124f52ef0SSrinivas Kandagatla clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 231224f52ef0SSrinivas Kandagatla 231324f52ef0SSrinivas Kandagatla #clock-cells = <0>; 231424f52ef0SSrinivas Kandagatla clock-frequency = <9600000>; 231524f52ef0SSrinivas Kandagatla clock-output-names = "mclk"; 231624f52ef0SSrinivas Kandagatla #address-cells = <2>; 231724f52ef0SSrinivas Kandagatla #size-cells = <2>; 231824f52ef0SSrinivas Kandagatla #sound-dai-cells = <1>; 231924f52ef0SSrinivas Kandagatla }; 232024f52ef0SSrinivas Kandagatla 232124f52ef0SSrinivas Kandagatla /* tx macro */ 232224f52ef0SSrinivas Kandagatla swr2: soundwire-controller@3230000 { 232324f52ef0SSrinivas Kandagatla reg = <0 0x3230000 0 0x2000>; 232424f52ef0SSrinivas Kandagatla compatible = "qcom,soundwire-v1.5.1"; 232524f52ef0SSrinivas Kandagatla interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 232624f52ef0SSrinivas Kandagatla interrupt-names = "core"; 232724f52ef0SSrinivas Kandagatla 232824f52ef0SSrinivas Kandagatla clocks = <&txmacro>; 232924f52ef0SSrinivas Kandagatla clock-names = "iface"; 233024f52ef0SSrinivas Kandagatla label = "TX"; 233124f52ef0SSrinivas Kandagatla 233224f52ef0SSrinivas Kandagatla qcom,din-ports = <5>; 233324f52ef0SSrinivas Kandagatla qcom,dout-ports = <0>; 233424f52ef0SSrinivas Kandagatla qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>; 233524f52ef0SSrinivas Kandagatla qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>; 233624f52ef0SSrinivas Kandagatla qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>; 233724f52ef0SSrinivas Kandagatla qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 233824f52ef0SSrinivas Kandagatla qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 233924f52ef0SSrinivas Kandagatla qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 234024f52ef0SSrinivas Kandagatla qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 234124f52ef0SSrinivas Kandagatla qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 234224f52ef0SSrinivas Kandagatla qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>; 234324f52ef0SSrinivas Kandagatla qcom,port-offset = <1>; 234424f52ef0SSrinivas Kandagatla #sound-dai-cells = <1>; 234524f52ef0SSrinivas Kandagatla #address-cells = <2>; 234624f52ef0SSrinivas Kandagatla #size-cells = <0>; 234724f52ef0SSrinivas Kandagatla }; 234824f52ef0SSrinivas Kandagatla 2349793bbd2dSSrinivas Kandagatla aoncc: clock-controller@3380000 { 2350793bbd2dSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-aoncc"; 2351793bbd2dSSrinivas Kandagatla reg = <0 0x03380000 0 0x40000>; 2352793bbd2dSSrinivas Kandagatla #clock-cells = <1>; 2353793bbd2dSSrinivas Kandagatla clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2354793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2355793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2356793bbd2dSSrinivas Kandagatla clock-names = "core", "audio", "bus"; 2357793bbd2dSSrinivas Kandagatla }; 2358793bbd2dSSrinivas Kandagatla 23593160c1b8SSrinivas Kandagatla lpass_tlmm: pinctrl@33c0000{ 23603160c1b8SSrinivas Kandagatla compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 23613160c1b8SSrinivas Kandagatla reg = <0 0x033c0000 0x0 0x20000>, 23623160c1b8SSrinivas Kandagatla <0 0x03550000 0x0 0x10000>; 23633160c1b8SSrinivas Kandagatla gpio-controller; 23643160c1b8SSrinivas Kandagatla #gpio-cells = <2>; 23653160c1b8SSrinivas Kandagatla gpio-ranges = <&lpass_tlmm 0 0 14>; 23663160c1b8SSrinivas Kandagatla 23673160c1b8SSrinivas Kandagatla clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 23683160c1b8SSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 23693160c1b8SSrinivas Kandagatla clock-names = "core", "audio"; 23703160c1b8SSrinivas Kandagatla 23713160c1b8SSrinivas Kandagatla wsa_swr_active: wsa-swr-active-pins { 23723160c1b8SSrinivas Kandagatla clk { 23733160c1b8SSrinivas Kandagatla pins = "gpio10"; 23743160c1b8SSrinivas Kandagatla function = "wsa_swr_clk"; 23753160c1b8SSrinivas Kandagatla drive-strength = <2>; 23763160c1b8SSrinivas Kandagatla slew-rate = <1>; 23773160c1b8SSrinivas Kandagatla bias-disable; 23783160c1b8SSrinivas Kandagatla }; 23793160c1b8SSrinivas Kandagatla 23803160c1b8SSrinivas Kandagatla data { 23813160c1b8SSrinivas Kandagatla pins = "gpio11"; 23823160c1b8SSrinivas Kandagatla function = "wsa_swr_data"; 23833160c1b8SSrinivas Kandagatla drive-strength = <2>; 23843160c1b8SSrinivas Kandagatla slew-rate = <1>; 23853160c1b8SSrinivas Kandagatla bias-bus-hold; 23863160c1b8SSrinivas Kandagatla 23873160c1b8SSrinivas Kandagatla }; 23883160c1b8SSrinivas Kandagatla }; 23893160c1b8SSrinivas Kandagatla 23903160c1b8SSrinivas Kandagatla wsa_swr_sleep: wsa-swr-sleep-pins { 23913160c1b8SSrinivas Kandagatla clk { 23923160c1b8SSrinivas Kandagatla pins = "gpio10"; 23933160c1b8SSrinivas Kandagatla function = "wsa_swr_clk"; 23943160c1b8SSrinivas Kandagatla drive-strength = <2>; 23953160c1b8SSrinivas Kandagatla input-enable; 23963160c1b8SSrinivas Kandagatla bias-pull-down; 23973160c1b8SSrinivas Kandagatla }; 23983160c1b8SSrinivas Kandagatla 23993160c1b8SSrinivas Kandagatla data { 24003160c1b8SSrinivas Kandagatla pins = "gpio11"; 24013160c1b8SSrinivas Kandagatla function = "wsa_swr_data"; 24023160c1b8SSrinivas Kandagatla drive-strength = <2>; 24033160c1b8SSrinivas Kandagatla input-enable; 24043160c1b8SSrinivas Kandagatla bias-pull-down; 24053160c1b8SSrinivas Kandagatla 24063160c1b8SSrinivas Kandagatla }; 24073160c1b8SSrinivas Kandagatla }; 24083160c1b8SSrinivas Kandagatla 24093160c1b8SSrinivas Kandagatla dmic01_active: dmic01-active-pins { 24103160c1b8SSrinivas Kandagatla clk { 24113160c1b8SSrinivas Kandagatla pins = "gpio6"; 24123160c1b8SSrinivas Kandagatla function = "dmic1_clk"; 24133160c1b8SSrinivas Kandagatla drive-strength = <8>; 24143160c1b8SSrinivas Kandagatla output-high; 24153160c1b8SSrinivas Kandagatla }; 24163160c1b8SSrinivas Kandagatla data { 24173160c1b8SSrinivas Kandagatla pins = "gpio7"; 24183160c1b8SSrinivas Kandagatla function = "dmic1_data"; 24193160c1b8SSrinivas Kandagatla drive-strength = <8>; 24203160c1b8SSrinivas Kandagatla input-enable; 24213160c1b8SSrinivas Kandagatla }; 24223160c1b8SSrinivas Kandagatla }; 24233160c1b8SSrinivas Kandagatla 24243160c1b8SSrinivas Kandagatla dmic01_sleep: dmic01-sleep-pins { 24253160c1b8SSrinivas Kandagatla clk { 24263160c1b8SSrinivas Kandagatla pins = "gpio6"; 24273160c1b8SSrinivas Kandagatla function = "dmic1_clk"; 24283160c1b8SSrinivas Kandagatla drive-strength = <2>; 24293160c1b8SSrinivas Kandagatla bias-disable; 24303160c1b8SSrinivas Kandagatla output-low; 24313160c1b8SSrinivas Kandagatla }; 24323160c1b8SSrinivas Kandagatla 24333160c1b8SSrinivas Kandagatla data { 24343160c1b8SSrinivas Kandagatla pins = "gpio7"; 24353160c1b8SSrinivas Kandagatla function = "dmic1_data"; 24363160c1b8SSrinivas Kandagatla drive-strength = <2>; 24373160c1b8SSrinivas Kandagatla pull-down; 24383160c1b8SSrinivas Kandagatla input-enable; 24393160c1b8SSrinivas Kandagatla }; 24403160c1b8SSrinivas Kandagatla }; 244124f52ef0SSrinivas Kandagatla 244224f52ef0SSrinivas Kandagatla rx_swr_active: rx_swr-active-pins { 244324f52ef0SSrinivas Kandagatla clk { 244424f52ef0SSrinivas Kandagatla pins = "gpio3"; 244524f52ef0SSrinivas Kandagatla function = "swr_rx_clk"; 244624f52ef0SSrinivas Kandagatla drive-strength = <2>; 244724f52ef0SSrinivas Kandagatla slew-rate = <1>; 244824f52ef0SSrinivas Kandagatla bias-disable; 244924f52ef0SSrinivas Kandagatla }; 245024f52ef0SSrinivas Kandagatla 245124f52ef0SSrinivas Kandagatla data { 245224f52ef0SSrinivas Kandagatla pins = "gpio4", "gpio5"; 245324f52ef0SSrinivas Kandagatla function = "swr_rx_data"; 245424f52ef0SSrinivas Kandagatla drive-strength = <2>; 245524f52ef0SSrinivas Kandagatla slew-rate = <1>; 245624f52ef0SSrinivas Kandagatla bias-bus-hold; 245724f52ef0SSrinivas Kandagatla }; 245824f52ef0SSrinivas Kandagatla }; 245924f52ef0SSrinivas Kandagatla 246024f52ef0SSrinivas Kandagatla tx_swr_active: tx_swr-active-pins { 246124f52ef0SSrinivas Kandagatla clk { 246224f52ef0SSrinivas Kandagatla pins = "gpio0"; 246324f52ef0SSrinivas Kandagatla function = "swr_tx_clk"; 246424f52ef0SSrinivas Kandagatla drive-strength = <2>; 246524f52ef0SSrinivas Kandagatla slew-rate = <1>; 246624f52ef0SSrinivas Kandagatla bias-disable; 246724f52ef0SSrinivas Kandagatla }; 246824f52ef0SSrinivas Kandagatla 246924f52ef0SSrinivas Kandagatla data { 247024f52ef0SSrinivas Kandagatla pins = "gpio1", "gpio2"; 247124f52ef0SSrinivas Kandagatla function = "swr_tx_data"; 247224f52ef0SSrinivas Kandagatla drive-strength = <2>; 247324f52ef0SSrinivas Kandagatla slew-rate = <1>; 247424f52ef0SSrinivas Kandagatla bias-bus-hold; 247524f52ef0SSrinivas Kandagatla }; 247624f52ef0SSrinivas Kandagatla }; 247724f52ef0SSrinivas Kandagatla 247824f52ef0SSrinivas Kandagatla tx_swr_sleep: tx_swr-sleep-pins { 247924f52ef0SSrinivas Kandagatla clk { 248024f52ef0SSrinivas Kandagatla pins = "gpio0"; 248124f52ef0SSrinivas Kandagatla function = "swr_tx_clk"; 248224f52ef0SSrinivas Kandagatla drive-strength = <2>; 248324f52ef0SSrinivas Kandagatla input-enable; 248424f52ef0SSrinivas Kandagatla bias-pull-down; 248524f52ef0SSrinivas Kandagatla }; 248624f52ef0SSrinivas Kandagatla 248724f52ef0SSrinivas Kandagatla data1 { 248824f52ef0SSrinivas Kandagatla pins = "gpio1"; 248924f52ef0SSrinivas Kandagatla function = "swr_tx_data"; 249024f52ef0SSrinivas Kandagatla drive-strength = <2>; 249124f52ef0SSrinivas Kandagatla input-enable; 249224f52ef0SSrinivas Kandagatla bias-bus-hold; 249324f52ef0SSrinivas Kandagatla }; 249424f52ef0SSrinivas Kandagatla 249524f52ef0SSrinivas Kandagatla data2 { 249624f52ef0SSrinivas Kandagatla pins = "gpio2"; 249724f52ef0SSrinivas Kandagatla function = "swr_tx_data"; 249824f52ef0SSrinivas Kandagatla drive-strength = <2>; 249924f52ef0SSrinivas Kandagatla input-enable; 250024f52ef0SSrinivas Kandagatla bias-pull-down; 250124f52ef0SSrinivas Kandagatla }; 250224f52ef0SSrinivas Kandagatla }; 25033160c1b8SSrinivas Kandagatla }; 25043160c1b8SSrinivas Kandagatla 250504a3605bSJonathan Marek gpu: gpu@3d00000 { 250604a3605bSJonathan Marek compatible = "qcom,adreno-650.2", 25077c1dffd4SDmitry Baryshkov "qcom,adreno"; 250804a3605bSJonathan Marek 250904a3605bSJonathan Marek reg = <0 0x03d00000 0 0x40000>; 251004a3605bSJonathan Marek reg-names = "kgsl_3d0_reg_memory"; 251104a3605bSJonathan Marek 251204a3605bSJonathan Marek interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 251304a3605bSJonathan Marek 251404a3605bSJonathan Marek iommus = <&adreno_smmu 0 0x401>; 251504a3605bSJonathan Marek 251604a3605bSJonathan Marek operating-points-v2 = <&gpu_opp_table>; 251704a3605bSJonathan Marek 251804a3605bSJonathan Marek qcom,gmu = <&gmu>; 251904a3605bSJonathan Marek 2520ece28cb5SKonrad Dybcio status = "disabled"; 2521ece28cb5SKonrad Dybcio 252204a3605bSJonathan Marek zap-shader { 252304a3605bSJonathan Marek memory-region = <&gpu_mem>; 252404a3605bSJonathan Marek }; 252504a3605bSJonathan Marek 252604a3605bSJonathan Marek /* note: downstream checks gpu binning for 670 Mhz */ 252704a3605bSJonathan Marek gpu_opp_table: opp-table { 252804a3605bSJonathan Marek compatible = "operating-points-v2"; 252904a3605bSJonathan Marek 253004a3605bSJonathan Marek opp-670000000 { 253104a3605bSJonathan Marek opp-hz = /bits/ 64 <670000000>; 253204a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 253304a3605bSJonathan Marek }; 253404a3605bSJonathan Marek 253504a3605bSJonathan Marek opp-587000000 { 253604a3605bSJonathan Marek opp-hz = /bits/ 64 <587000000>; 253704a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 253804a3605bSJonathan Marek }; 253904a3605bSJonathan Marek 254004a3605bSJonathan Marek opp-525000000 { 254104a3605bSJonathan Marek opp-hz = /bits/ 64 <525000000>; 254204a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 254304a3605bSJonathan Marek }; 254404a3605bSJonathan Marek 254504a3605bSJonathan Marek opp-490000000 { 254604a3605bSJonathan Marek opp-hz = /bits/ 64 <490000000>; 254704a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 254804a3605bSJonathan Marek }; 254904a3605bSJonathan Marek 255004a3605bSJonathan Marek opp-441600000 { 255104a3605bSJonathan Marek opp-hz = /bits/ 64 <441600000>; 255204a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 255304a3605bSJonathan Marek }; 255404a3605bSJonathan Marek 255504a3605bSJonathan Marek opp-400000000 { 255604a3605bSJonathan Marek opp-hz = /bits/ 64 <400000000>; 255704a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 255804a3605bSJonathan Marek }; 255904a3605bSJonathan Marek 256004a3605bSJonathan Marek opp-305000000 { 256104a3605bSJonathan Marek opp-hz = /bits/ 64 <305000000>; 256204a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 256304a3605bSJonathan Marek }; 256404a3605bSJonathan Marek }; 256504a3605bSJonathan Marek }; 256604a3605bSJonathan Marek 256704a3605bSJonathan Marek gmu: gmu@3d6a000 { 256804a3605bSJonathan Marek compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 256904a3605bSJonathan Marek 257004a3605bSJonathan Marek reg = <0 0x03d6a000 0 0x30000>, 257104a3605bSJonathan Marek <0 0x3de0000 0 0x10000>, 257204a3605bSJonathan Marek <0 0xb290000 0 0x10000>, 257304a3605bSJonathan Marek <0 0xb490000 0 0x10000>; 257404a3605bSJonathan Marek reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 257504a3605bSJonathan Marek 257604a3605bSJonathan Marek interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 257704a3605bSJonathan Marek <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 257804a3605bSJonathan Marek interrupt-names = "hfi", "gmu"; 257904a3605bSJonathan Marek 25800e6aa9dbSJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 25810e6aa9dbSJonathan Marek <&gpucc GPU_CC_CX_GMU_CLK>, 25820e6aa9dbSJonathan Marek <&gpucc GPU_CC_CXO_CLK>, 258304a3605bSJonathan Marek <&gcc GCC_DDRSS_GPU_AXI_CLK>, 258404a3605bSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 258504a3605bSJonathan Marek clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 258604a3605bSJonathan Marek 25870e6aa9dbSJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>, 25880e6aa9dbSJonathan Marek <&gpucc GPU_GX_GDSC>; 258904a3605bSJonathan Marek power-domain-names = "cx", "gx"; 259004a3605bSJonathan Marek 259104a3605bSJonathan Marek iommus = <&adreno_smmu 5 0x400>; 259204a3605bSJonathan Marek 259304a3605bSJonathan Marek operating-points-v2 = <&gmu_opp_table>; 259404a3605bSJonathan Marek 2595ece28cb5SKonrad Dybcio status = "disabled"; 2596ece28cb5SKonrad Dybcio 259704a3605bSJonathan Marek gmu_opp_table: opp-table { 259804a3605bSJonathan Marek compatible = "operating-points-v2"; 259904a3605bSJonathan Marek 260004a3605bSJonathan Marek opp-200000000 { 260104a3605bSJonathan Marek opp-hz = /bits/ 64 <200000000>; 260204a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 260304a3605bSJonathan Marek }; 260404a3605bSJonathan Marek }; 260504a3605bSJonathan Marek }; 260604a3605bSJonathan Marek 260704a3605bSJonathan Marek gpucc: clock-controller@3d90000 { 260804a3605bSJonathan Marek compatible = "qcom,sm8250-gpucc"; 260904a3605bSJonathan Marek reg = <0 0x03d90000 0 0x9000>; 261004a3605bSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>, 261104a3605bSJonathan Marek <&gcc GCC_GPU_GPLL0_CLK_SRC>, 261204a3605bSJonathan Marek <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 261304a3605bSJonathan Marek clock-names = "bi_tcxo", 261404a3605bSJonathan Marek "gcc_gpu_gpll0_clk_src", 261504a3605bSJonathan Marek "gcc_gpu_gpll0_div_clk_src"; 261604a3605bSJonathan Marek #clock-cells = <1>; 261704a3605bSJonathan Marek #reset-cells = <1>; 261804a3605bSJonathan Marek #power-domain-cells = <1>; 261904a3605bSJonathan Marek }; 262004a3605bSJonathan Marek 262104a3605bSJonathan Marek adreno_smmu: iommu@3da0000 { 262204a3605bSJonathan Marek compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 262304a3605bSJonathan Marek reg = <0 0x03da0000 0 0x10000>; 262404a3605bSJonathan Marek #iommu-cells = <2>; 262504a3605bSJonathan Marek #global-interrupts = <2>; 262604a3605bSJonathan Marek interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 262704a3605bSJonathan Marek <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 262804a3605bSJonathan Marek <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 262904a3605bSJonathan Marek <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 263004a3605bSJonathan Marek <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 263104a3605bSJonathan Marek <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 263204a3605bSJonathan Marek <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 263304a3605bSJonathan Marek <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 263404a3605bSJonathan Marek <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 263504a3605bSJonathan Marek <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 26360e6aa9dbSJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 263704a3605bSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 263804a3605bSJonathan Marek <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 263904a3605bSJonathan Marek clock-names = "ahb", "bus", "iface"; 264004a3605bSJonathan Marek 26410e6aa9dbSJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>; 264204a3605bSJonathan Marek }; 264304a3605bSJonathan Marek 264423a89037SBjorn Andersson slpi: remoteproc@5c00000 { 264523a89037SBjorn Andersson compatible = "qcom,sm8250-slpi-pas"; 264623a89037SBjorn Andersson reg = <0 0x05c00000 0 0x4000>; 264723a89037SBjorn Andersson 264823a89037SBjorn Andersson interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 264923a89037SBjorn Andersson <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 265023a89037SBjorn Andersson <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 265123a89037SBjorn Andersson <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 265223a89037SBjorn Andersson <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 265323a89037SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 265423a89037SBjorn Andersson "handover", "stop-ack"; 265523a89037SBjorn Andersson 265623a89037SBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>; 265723a89037SBjorn Andersson clock-names = "xo"; 265823a89037SBjorn Andersson 2659b74ee2d7SSibi Sankar power-domains = <&rpmhpd SM8250_LCX>, 266023a89037SBjorn Andersson <&rpmhpd SM8250_LMX>; 2661b74ee2d7SSibi Sankar power-domain-names = "lcx", "lmx"; 266223a89037SBjorn Andersson 266323a89037SBjorn Andersson memory-region = <&slpi_mem>; 266423a89037SBjorn Andersson 2665b74ee2d7SSibi Sankar qcom,qmp = <&aoss_qmp>; 2666b74ee2d7SSibi Sankar 266723a89037SBjorn Andersson qcom,smem-states = <&smp2p_slpi_out 0>; 266823a89037SBjorn Andersson qcom,smem-state-names = "stop"; 266923a89037SBjorn Andersson 267023a89037SBjorn Andersson status = "disabled"; 267123a89037SBjorn Andersson 267223a89037SBjorn Andersson glink-edge { 267323a89037SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 267423a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 267523a89037SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 267623a89037SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_SLPI 267723a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 267823a89037SBjorn Andersson 267925695808SJonathan Marek label = "slpi"; 268023a89037SBjorn Andersson qcom,remote-pid = <3>; 268125695808SJonathan Marek 268225695808SJonathan Marek fastrpc { 268325695808SJonathan Marek compatible = "qcom,fastrpc"; 268425695808SJonathan Marek qcom,glink-channels = "fastrpcglink-apps-dsp"; 268525695808SJonathan Marek label = "sdsp"; 26868c8ce95bSJeya R qcom,non-secure-domain; 268725695808SJonathan Marek #address-cells = <1>; 268825695808SJonathan Marek #size-cells = <0>; 268925695808SJonathan Marek 269025695808SJonathan Marek compute-cb@1 { 269125695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 269225695808SJonathan Marek reg = <1>; 269325695808SJonathan Marek iommus = <&apps_smmu 0x0541 0x0>; 269425695808SJonathan Marek }; 269525695808SJonathan Marek 269625695808SJonathan Marek compute-cb@2 { 269725695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 269825695808SJonathan Marek reg = <2>; 269925695808SJonathan Marek iommus = <&apps_smmu 0x0542 0x0>; 270025695808SJonathan Marek }; 270125695808SJonathan Marek 270225695808SJonathan Marek compute-cb@3 { 270325695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 270425695808SJonathan Marek reg = <3>; 270525695808SJonathan Marek iommus = <&apps_smmu 0x0543 0x0>; 270625695808SJonathan Marek /* note: shared-cb = <4> in downstream */ 270725695808SJonathan Marek }; 270825695808SJonathan Marek }; 270923a89037SBjorn Andersson }; 271023a89037SBjorn Andersson }; 271123a89037SBjorn Andersson 271223a89037SBjorn Andersson cdsp: remoteproc@8300000 { 271323a89037SBjorn Andersson compatible = "qcom,sm8250-cdsp-pas"; 271423a89037SBjorn Andersson reg = <0 0x08300000 0 0x10000>; 271523a89037SBjorn Andersson 271623a89037SBjorn Andersson interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 271723a89037SBjorn Andersson <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 271823a89037SBjorn Andersson <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 271923a89037SBjorn Andersson <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 272023a89037SBjorn Andersson <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 272123a89037SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 272223a89037SBjorn Andersson "handover", "stop-ack"; 272323a89037SBjorn Andersson 272423a89037SBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>; 272523a89037SBjorn Andersson clock-names = "xo"; 272623a89037SBjorn Andersson 2727b74ee2d7SSibi Sankar power-domains = <&rpmhpd SM8250_CX>; 272823a89037SBjorn Andersson 272923a89037SBjorn Andersson memory-region = <&cdsp_mem>; 273023a89037SBjorn Andersson 2731b74ee2d7SSibi Sankar qcom,qmp = <&aoss_qmp>; 2732b74ee2d7SSibi Sankar 273323a89037SBjorn Andersson qcom,smem-states = <&smp2p_cdsp_out 0>; 273423a89037SBjorn Andersson qcom,smem-state-names = "stop"; 273523a89037SBjorn Andersson 273623a89037SBjorn Andersson status = "disabled"; 273723a89037SBjorn Andersson 273823a89037SBjorn Andersson glink-edge { 273923a89037SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 274023a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 274123a89037SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 274223a89037SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_CDSP 274323a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 274423a89037SBjorn Andersson 274525695808SJonathan Marek label = "cdsp"; 274623a89037SBjorn Andersson qcom,remote-pid = <5>; 274725695808SJonathan Marek 274825695808SJonathan Marek fastrpc { 274925695808SJonathan Marek compatible = "qcom,fastrpc"; 275025695808SJonathan Marek qcom,glink-channels = "fastrpcglink-apps-dsp"; 275125695808SJonathan Marek label = "cdsp"; 27528c8ce95bSJeya R qcom,non-secure-domain; 275325695808SJonathan Marek #address-cells = <1>; 275425695808SJonathan Marek #size-cells = <0>; 275525695808SJonathan Marek 275625695808SJonathan Marek compute-cb@1 { 275725695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 275825695808SJonathan Marek reg = <1>; 275925695808SJonathan Marek iommus = <&apps_smmu 0x1001 0x0460>; 276025695808SJonathan Marek }; 276125695808SJonathan Marek 276225695808SJonathan Marek compute-cb@2 { 276325695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 276425695808SJonathan Marek reg = <2>; 276525695808SJonathan Marek iommus = <&apps_smmu 0x1002 0x0460>; 276625695808SJonathan Marek }; 276725695808SJonathan Marek 276825695808SJonathan Marek compute-cb@3 { 276925695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 277025695808SJonathan Marek reg = <3>; 277125695808SJonathan Marek iommus = <&apps_smmu 0x1003 0x0460>; 277225695808SJonathan Marek }; 277325695808SJonathan Marek 277425695808SJonathan Marek compute-cb@4 { 277525695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 277625695808SJonathan Marek reg = <4>; 277725695808SJonathan Marek iommus = <&apps_smmu 0x1004 0x0460>; 277825695808SJonathan Marek }; 277925695808SJonathan Marek 278025695808SJonathan Marek compute-cb@5 { 278125695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 278225695808SJonathan Marek reg = <5>; 278325695808SJonathan Marek iommus = <&apps_smmu 0x1005 0x0460>; 278425695808SJonathan Marek }; 278525695808SJonathan Marek 278625695808SJonathan Marek compute-cb@6 { 278725695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 278825695808SJonathan Marek reg = <6>; 278925695808SJonathan Marek iommus = <&apps_smmu 0x1006 0x0460>; 279025695808SJonathan Marek }; 279125695808SJonathan Marek 279225695808SJonathan Marek compute-cb@7 { 279325695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 279425695808SJonathan Marek reg = <7>; 279525695808SJonathan Marek iommus = <&apps_smmu 0x1007 0x0460>; 279625695808SJonathan Marek }; 279725695808SJonathan Marek 279825695808SJonathan Marek compute-cb@8 { 279925695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 280025695808SJonathan Marek reg = <8>; 280125695808SJonathan Marek iommus = <&apps_smmu 0x1008 0x0460>; 280225695808SJonathan Marek }; 280325695808SJonathan Marek 280425695808SJonathan Marek /* note: secure cb9 in downstream */ 280525695808SJonathan Marek }; 280623a89037SBjorn Andersson }; 280723a89037SBjorn Andersson }; 280823a89037SBjorn Andersson 2809590a135eSSrinivas Kandagatla sound: sound { 2810590a135eSSrinivas Kandagatla }; 2811590a135eSSrinivas Kandagatla 281246a6f297SJonathan Marek usb_1_hsphy: phy@88e3000 { 281346a6f297SJonathan Marek compatible = "qcom,sm8250-usb-hs-phy", 281446a6f297SJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 281546a6f297SJonathan Marek reg = <0 0x088e3000 0 0x400>; 281646a6f297SJonathan Marek status = "disabled"; 281746a6f297SJonathan Marek #phy-cells = <0>; 281846a6f297SJonathan Marek 281946a6f297SJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 282046a6f297SJonathan Marek clock-names = "ref"; 282146a6f297SJonathan Marek 282246a6f297SJonathan Marek resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 282346a6f297SJonathan Marek }; 282446a6f297SJonathan Marek 282546a6f297SJonathan Marek usb_2_hsphy: phy@88e4000 { 282646a6f297SJonathan Marek compatible = "qcom,sm8250-usb-hs-phy", 282746a6f297SJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 282846a6f297SJonathan Marek reg = <0 0x088e4000 0 0x400>; 282946a6f297SJonathan Marek status = "disabled"; 283046a6f297SJonathan Marek #phy-cells = <0>; 283146a6f297SJonathan Marek 283246a6f297SJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 283346a6f297SJonathan Marek clock-names = "ref"; 283446a6f297SJonathan Marek 283546a6f297SJonathan Marek resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 283646a6f297SJonathan Marek }; 283746a6f297SJonathan Marek 283846a6f297SJonathan Marek usb_1_qmpphy: phy@88e9000 { 28395aa0d1beSDmitry Baryshkov compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 284046a6f297SJonathan Marek reg = <0 0x088e9000 0 0x200>, 28415aa0d1beSDmitry Baryshkov <0 0x088e8000 0 0x40>, 28425aa0d1beSDmitry Baryshkov <0 0x088ea000 0 0x200>; 284346a6f297SJonathan Marek status = "disabled"; 284446a6f297SJonathan Marek #address-cells = <2>; 284546a6f297SJonathan Marek #size-cells = <2>; 284646a6f297SJonathan Marek ranges; 284746a6f297SJonathan Marek 284846a6f297SJonathan Marek clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 284946a6f297SJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 285046a6f297SJonathan Marek <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 285146a6f297SJonathan Marek clock-names = "aux", "ref_clk_src", "com_aux"; 285246a6f297SJonathan Marek 285346a6f297SJonathan Marek resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 285446a6f297SJonathan Marek <&gcc GCC_USB3_PHY_PRIM_BCR>; 285546a6f297SJonathan Marek reset-names = "phy", "common"; 285646a6f297SJonathan Marek 28575aa0d1beSDmitry Baryshkov usb_1_ssphy: usb3-phy@88e9200 { 285846a6f297SJonathan Marek reg = <0 0x088e9200 0 0x200>, 285946a6f297SJonathan Marek <0 0x088e9400 0 0x200>, 286046a6f297SJonathan Marek <0 0x088e9c00 0 0x400>, 286146a6f297SJonathan Marek <0 0x088e9600 0 0x200>, 286246a6f297SJonathan Marek <0 0x088e9800 0 0x200>, 286346a6f297SJonathan Marek <0 0x088e9a00 0 0x100>; 28647178d4ccSJonathan Marek #clock-cells = <0>; 286546a6f297SJonathan Marek #phy-cells = <0>; 286646a6f297SJonathan Marek clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 286746a6f297SJonathan Marek clock-names = "pipe0"; 286846a6f297SJonathan Marek clock-output-names = "usb3_phy_pipe_clk_src"; 286946a6f297SJonathan Marek }; 28705aa0d1beSDmitry Baryshkov 28715aa0d1beSDmitry Baryshkov dp_phy: dp-phy@88ea200 { 28725aa0d1beSDmitry Baryshkov reg = <0 0x088ea200 0 0x200>, 28735aa0d1beSDmitry Baryshkov <0 0x088ea400 0 0x200>, 28745aa0d1beSDmitry Baryshkov <0 0x088eac00 0 0x400>, 28755aa0d1beSDmitry Baryshkov <0 0x088ea600 0 0x200>, 28765aa0d1beSDmitry Baryshkov <0 0x088ea800 0 0x200>, 28775aa0d1beSDmitry Baryshkov <0 0x088eaa00 0 0x100>; 28785aa0d1beSDmitry Baryshkov #phy-cells = <0>; 28795aa0d1beSDmitry Baryshkov #clock-cells = <1>; 28805aa0d1beSDmitry Baryshkov clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 28815aa0d1beSDmitry Baryshkov clock-names = "pipe0"; 28825aa0d1beSDmitry Baryshkov clock-output-names = "usb3_phy_pipe_clk_src"; 28835aa0d1beSDmitry Baryshkov }; 288446a6f297SJonathan Marek }; 288546a6f297SJonathan Marek 288646a6f297SJonathan Marek usb_2_qmpphy: phy@88eb000 { 288746a6f297SJonathan Marek compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 288846a6f297SJonathan Marek reg = <0 0x088eb000 0 0x200>; 288946a6f297SJonathan Marek status = "disabled"; 289046a6f297SJonathan Marek #address-cells = <2>; 289146a6f297SJonathan Marek #size-cells = <2>; 289246a6f297SJonathan Marek ranges; 289346a6f297SJonathan Marek 289446a6f297SJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 289546a6f297SJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 289646a6f297SJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_EN>, 289746a6f297SJonathan Marek <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 289846a6f297SJonathan Marek clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 289946a6f297SJonathan Marek 290046a6f297SJonathan Marek resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 290146a6f297SJonathan Marek <&gcc GCC_USB3_PHY_SEC_BCR>; 290246a6f297SJonathan Marek reset-names = "phy", "common"; 290346a6f297SJonathan Marek 29041351512fSShawn Guo usb_2_ssphy: phy@88eb200 { 290546a6f297SJonathan Marek reg = <0 0x088eb200 0 0x200>, 290646a6f297SJonathan Marek <0 0x088eb400 0 0x200>, 290746a6f297SJonathan Marek <0 0x088eb800 0 0x800>; 29087178d4ccSJonathan Marek #clock-cells = <0>; 290946a6f297SJonathan Marek #phy-cells = <0>; 291046a6f297SJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 291146a6f297SJonathan Marek clock-names = "pipe0"; 291246a6f297SJonathan Marek clock-output-names = "usb3_uni_phy_pipe_clk_src"; 291346a6f297SJonathan Marek }; 291446a6f297SJonathan Marek }; 291546a6f297SJonathan Marek 2916c4cf0300SManivannan Sadhasivam sdhc_2: sdhci@8804000 { 2917c4cf0300SManivannan Sadhasivam compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 2918c4cf0300SManivannan Sadhasivam reg = <0 0x08804000 0 0x1000>; 2919c4cf0300SManivannan Sadhasivam 2920c4cf0300SManivannan Sadhasivam interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2921c4cf0300SManivannan Sadhasivam <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2922c4cf0300SManivannan Sadhasivam interrupt-names = "hc_irq", "pwr_irq"; 2923c4cf0300SManivannan Sadhasivam 2924c4cf0300SManivannan Sadhasivam clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2925c4cf0300SManivannan Sadhasivam <&gcc GCC_SDCC2_APPS_CLK>, 292674097d80SDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK>; 2927c4cf0300SManivannan Sadhasivam clock-names = "iface", "core", "xo"; 2928c4cf0300SManivannan Sadhasivam iommus = <&apps_smmu 0x4a0 0x0>; 2929c4cf0300SManivannan Sadhasivam qcom,dll-config = <0x0007642c>; 2930c4cf0300SManivannan Sadhasivam qcom,ddr-config = <0x80040868>; 2931c4cf0300SManivannan Sadhasivam power-domains = <&rpmhpd SM8250_CX>; 2932c4cf0300SManivannan Sadhasivam operating-points-v2 = <&sdhc2_opp_table>; 2933c4cf0300SManivannan Sadhasivam 2934c4cf0300SManivannan Sadhasivam status = "disabled"; 2935c4cf0300SManivannan Sadhasivam 2936c4cf0300SManivannan Sadhasivam sdhc2_opp_table: sdhc2-opp-table { 2937c4cf0300SManivannan Sadhasivam compatible = "operating-points-v2"; 2938c4cf0300SManivannan Sadhasivam 2939c4cf0300SManivannan Sadhasivam opp-19200000 { 2940c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <19200000>; 2941c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_min_svs>; 2942c4cf0300SManivannan Sadhasivam }; 2943c4cf0300SManivannan Sadhasivam 2944c4cf0300SManivannan Sadhasivam opp-50000000 { 2945c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <50000000>; 2946c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_low_svs>; 2947c4cf0300SManivannan Sadhasivam }; 2948c4cf0300SManivannan Sadhasivam 2949c4cf0300SManivannan Sadhasivam opp-100000000 { 2950c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <100000000>; 2951c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_svs>; 2952c4cf0300SManivannan Sadhasivam }; 2953c4cf0300SManivannan Sadhasivam 2954c4cf0300SManivannan Sadhasivam opp-202000000 { 2955c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <202000000>; 2956c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_svs_l1>; 2957c4cf0300SManivannan Sadhasivam }; 2958c4cf0300SManivannan Sadhasivam }; 2959c4cf0300SManivannan Sadhasivam }; 2960c4cf0300SManivannan Sadhasivam 2961e7e41a20SJonathan Marek dc_noc: interconnect@90c0000 { 2962e7e41a20SJonathan Marek compatible = "qcom,sm8250-dc-noc"; 2963e7e41a20SJonathan Marek reg = <0 0x090c0000 0 0x4200>; 2964e7e41a20SJonathan Marek #interconnect-cells = <1>; 2965e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 2966e7e41a20SJonathan Marek }; 2967e7e41a20SJonathan Marek 2968e7e41a20SJonathan Marek gem_noc: interconnect@9100000 { 2969e7e41a20SJonathan Marek compatible = "qcom,sm8250-gem-noc"; 2970e7e41a20SJonathan Marek reg = <0 0x09100000 0 0xb4000>; 2971e7e41a20SJonathan Marek #interconnect-cells = <1>; 2972e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 2973e7e41a20SJonathan Marek }; 2974e7e41a20SJonathan Marek 2975e7e41a20SJonathan Marek npu_noc: interconnect@9990000 { 2976e7e41a20SJonathan Marek compatible = "qcom,sm8250-npu-noc"; 2977e7e41a20SJonathan Marek reg = <0 0x09990000 0 0x1600>; 2978e7e41a20SJonathan Marek #interconnect-cells = <1>; 2979e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 2980e7e41a20SJonathan Marek }; 2981e7e41a20SJonathan Marek 298246a6f297SJonathan Marek usb_1: usb@a6f8800 { 298346a6f297SJonathan Marek compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 298446a6f297SJonathan Marek reg = <0 0x0a6f8800 0 0x400>; 298546a6f297SJonathan Marek status = "disabled"; 298646a6f297SJonathan Marek #address-cells = <2>; 298746a6f297SJonathan Marek #size-cells = <2>; 298846a6f297SJonathan Marek ranges; 298946a6f297SJonathan Marek dma-ranges; 299046a6f297SJonathan Marek 299146a6f297SJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 299246a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_MASTER_CLK>, 299346a6f297SJonathan Marek <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 299446a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 299546a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 299646a6f297SJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_EN>; 299746a6f297SJonathan Marek clock-names = "cfg_noc", "core", "iface", "mock_utmi", 299846a6f297SJonathan Marek "sleep", "xo"; 299946a6f297SJonathan Marek 300046a6f297SJonathan Marek assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 300146a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_MASTER_CLK>; 300246a6f297SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 300346a6f297SJonathan Marek 300446a6f297SJonathan Marek interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 300546a6f297SJonathan Marek <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 300646a6f297SJonathan Marek <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 300746a6f297SJonathan Marek <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 300846a6f297SJonathan Marek interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 300946a6f297SJonathan Marek "dm_hs_phy_irq", "ss_phy_irq"; 301046a6f297SJonathan Marek 301146a6f297SJonathan Marek power-domains = <&gcc USB30_PRIM_GDSC>; 301246a6f297SJonathan Marek 301346a6f297SJonathan Marek resets = <&gcc GCC_USB30_PRIM_BCR>; 301446a6f297SJonathan Marek 30152aa2b50dSBhupesh Sharma usb_1_dwc3: usb@a600000 { 301646a6f297SJonathan Marek compatible = "snps,dwc3"; 301746a6f297SJonathan Marek reg = <0 0x0a600000 0 0xcd00>; 301846a6f297SJonathan Marek interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 301946a6f297SJonathan Marek iommus = <&apps_smmu 0x0 0x0>; 302046a6f297SJonathan Marek snps,dis_u2_susphy_quirk; 302146a6f297SJonathan Marek snps,dis_enblslpm_quirk; 302246a6f297SJonathan Marek phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 302346a6f297SJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 302446a6f297SJonathan Marek }; 302546a6f297SJonathan Marek }; 302646a6f297SJonathan Marek 30270085a33aSManivannan Sadhasivam system-cache-controller@9200000 { 30280085a33aSManivannan Sadhasivam compatible = "qcom,sm8250-llcc"; 30290085a33aSManivannan Sadhasivam reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 30300085a33aSManivannan Sadhasivam reg-names = "llcc_base", "llcc_broadcast_base"; 30310085a33aSManivannan Sadhasivam }; 30320085a33aSManivannan Sadhasivam 303346a6f297SJonathan Marek usb_2: usb@a8f8800 { 303446a6f297SJonathan Marek compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 303546a6f297SJonathan Marek reg = <0 0x0a8f8800 0 0x400>; 303646a6f297SJonathan Marek status = "disabled"; 303746a6f297SJonathan Marek #address-cells = <2>; 303846a6f297SJonathan Marek #size-cells = <2>; 303946a6f297SJonathan Marek ranges; 304046a6f297SJonathan Marek dma-ranges; 304146a6f297SJonathan Marek 304246a6f297SJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 304346a6f297SJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>, 304446a6f297SJonathan Marek <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 304546a6f297SJonathan Marek <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 304646a6f297SJonathan Marek <&gcc GCC_USB30_SEC_SLEEP_CLK>, 304746a6f297SJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_EN>; 304846a6f297SJonathan Marek clock-names = "cfg_noc", "core", "iface", "mock_utmi", 304946a6f297SJonathan Marek "sleep", "xo"; 305046a6f297SJonathan Marek 305146a6f297SJonathan Marek assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 305246a6f297SJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>; 305346a6f297SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 305446a6f297SJonathan Marek 305546a6f297SJonathan Marek interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 305646a6f297SJonathan Marek <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 305746a6f297SJonathan Marek <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 305846a6f297SJonathan Marek <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 305946a6f297SJonathan Marek interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 306046a6f297SJonathan Marek "dm_hs_phy_irq", "ss_phy_irq"; 306146a6f297SJonathan Marek 306246a6f297SJonathan Marek power-domains = <&gcc USB30_SEC_GDSC>; 306346a6f297SJonathan Marek 306446a6f297SJonathan Marek resets = <&gcc GCC_USB30_SEC_BCR>; 306546a6f297SJonathan Marek 30662aa2b50dSBhupesh Sharma usb_2_dwc3: usb@a800000 { 306746a6f297SJonathan Marek compatible = "snps,dwc3"; 306846a6f297SJonathan Marek reg = <0 0x0a800000 0 0xcd00>; 306946a6f297SJonathan Marek interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 307046a6f297SJonathan Marek iommus = <&apps_smmu 0x20 0>; 307146a6f297SJonathan Marek snps,dis_u2_susphy_quirk; 307246a6f297SJonathan Marek snps,dis_enblslpm_quirk; 307346a6f297SJonathan Marek phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 307446a6f297SJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 307546a6f297SJonathan Marek }; 307646a6f297SJonathan Marek }; 307746a6f297SJonathan Marek 3078fa245b3fSBryan O'Donoghue venus: video-codec@aa00000 { 3079fa245b3fSBryan O'Donoghue compatible = "qcom,sm8250-venus"; 3080fa245b3fSBryan O'Donoghue reg = <0 0x0aa00000 0 0x100000>; 3081fa245b3fSBryan O'Donoghue interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3082fa245b3fSBryan O'Donoghue power-domains = <&videocc MVS0C_GDSC>, 3083fa245b3fSBryan O'Donoghue <&videocc MVS0_GDSC>, 3084fa245b3fSBryan O'Donoghue <&rpmhpd SM8250_MX>; 3085fa245b3fSBryan O'Donoghue power-domain-names = "venus", "vcodec0", "mx"; 3086fa245b3fSBryan O'Donoghue operating-points-v2 = <&venus_opp_table>; 3087fa245b3fSBryan O'Donoghue 3088fa245b3fSBryan O'Donoghue clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 3089fa245b3fSBryan O'Donoghue <&videocc VIDEO_CC_MVS0C_CLK>, 3090fa245b3fSBryan O'Donoghue <&videocc VIDEO_CC_MVS0_CLK>; 3091fa245b3fSBryan O'Donoghue clock-names = "iface", "core", "vcodec0_core"; 3092fa245b3fSBryan O'Donoghue 3093fa245b3fSBryan O'Donoghue interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, 3094fa245b3fSBryan O'Donoghue <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; 3095fa245b3fSBryan O'Donoghue interconnect-names = "cpu-cfg", "video-mem"; 3096fa245b3fSBryan O'Donoghue 3097fa245b3fSBryan O'Donoghue iommus = <&apps_smmu 0x2100 0x0400>; 3098fa245b3fSBryan O'Donoghue memory-region = <&video_mem>; 3099fa245b3fSBryan O'Donoghue 3100fa245b3fSBryan O'Donoghue resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 3101fa245b3fSBryan O'Donoghue <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 3102fa245b3fSBryan O'Donoghue reset-names = "bus", "core"; 3103fa245b3fSBryan O'Donoghue 3104ece28cb5SKonrad Dybcio status = "disabled"; 3105ece28cb5SKonrad Dybcio 3106fa245b3fSBryan O'Donoghue video-decoder { 3107fa245b3fSBryan O'Donoghue compatible = "venus-decoder"; 3108fa245b3fSBryan O'Donoghue }; 3109fa245b3fSBryan O'Donoghue 3110fa245b3fSBryan O'Donoghue video-encoder { 3111fa245b3fSBryan O'Donoghue compatible = "venus-encoder"; 3112fa245b3fSBryan O'Donoghue }; 3113fa245b3fSBryan O'Donoghue 3114fa245b3fSBryan O'Donoghue venus_opp_table: venus-opp-table { 3115fa245b3fSBryan O'Donoghue compatible = "operating-points-v2"; 3116fa245b3fSBryan O'Donoghue 3117fa245b3fSBryan O'Donoghue opp-720000000 { 3118fa245b3fSBryan O'Donoghue opp-hz = /bits/ 64 <720000000>; 3119fa245b3fSBryan O'Donoghue required-opps = <&rpmhpd_opp_low_svs>; 3120fa245b3fSBryan O'Donoghue }; 3121fa245b3fSBryan O'Donoghue 3122fa245b3fSBryan O'Donoghue opp-1014000000 { 3123fa245b3fSBryan O'Donoghue opp-hz = /bits/ 64 <1014000000>; 3124fa245b3fSBryan O'Donoghue required-opps = <&rpmhpd_opp_svs>; 3125fa245b3fSBryan O'Donoghue }; 3126fa245b3fSBryan O'Donoghue 3127fa245b3fSBryan O'Donoghue opp-1098000000 { 3128fa245b3fSBryan O'Donoghue opp-hz = /bits/ 64 <1098000000>; 3129fa245b3fSBryan O'Donoghue required-opps = <&rpmhpd_opp_svs_l1>; 3130fa245b3fSBryan O'Donoghue }; 3131fa245b3fSBryan O'Donoghue 3132fa245b3fSBryan O'Donoghue opp-1332000000 { 3133fa245b3fSBryan O'Donoghue opp-hz = /bits/ 64 <1332000000>; 3134fa245b3fSBryan O'Donoghue required-opps = <&rpmhpd_opp_nom>; 3135fa245b3fSBryan O'Donoghue }; 3136fa245b3fSBryan O'Donoghue }; 3137fa245b3fSBryan O'Donoghue }; 3138fa245b3fSBryan O'Donoghue 31395b9ec225Sjonathan@marek.ca videocc: clock-controller@abf0000 { 31405b9ec225Sjonathan@marek.ca compatible = "qcom,sm8250-videocc"; 31415b9ec225Sjonathan@marek.ca reg = <0 0x0abf0000 0 0x10000>; 31425b9ec225Sjonathan@marek.ca clocks = <&gcc GCC_VIDEO_AHB_CLK>, 31435b9ec225Sjonathan@marek.ca <&rpmhcc RPMH_CXO_CLK>, 31445b9ec225Sjonathan@marek.ca <&rpmhcc RPMH_CXO_CLK_A>; 3145266e5cf3SDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 3146266e5cf3SDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 31475b9ec225Sjonathan@marek.ca clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 31485b9ec225Sjonathan@marek.ca #clock-cells = <1>; 31495b9ec225Sjonathan@marek.ca #reset-cells = <1>; 31505b9ec225Sjonathan@marek.ca #power-domain-cells = <1>; 31515b9ec225Sjonathan@marek.ca }; 31525b9ec225Sjonathan@marek.ca 3153*e7173009SBryan O'Donoghue cci0: cci@ac4f000 { 3154*e7173009SBryan O'Donoghue compatible = "qcom,sm8250-cci"; 3155*e7173009SBryan O'Donoghue #address-cells = <1>; 3156*e7173009SBryan O'Donoghue #size-cells = <0>; 3157*e7173009SBryan O'Donoghue 3158*e7173009SBryan O'Donoghue reg = <0 0x0ac4f000 0 0x1000>; 3159*e7173009SBryan O'Donoghue interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3160*e7173009SBryan O'Donoghue power-domains = <&camcc TITAN_TOP_GDSC>; 3161*e7173009SBryan O'Donoghue 3162*e7173009SBryan O'Donoghue clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3163*e7173009SBryan O'Donoghue <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3164*e7173009SBryan O'Donoghue <&camcc CAM_CC_CPAS_AHB_CLK>, 3165*e7173009SBryan O'Donoghue <&camcc CAM_CC_CCI_0_CLK>, 3166*e7173009SBryan O'Donoghue <&camcc CAM_CC_CCI_0_CLK_SRC>; 3167*e7173009SBryan O'Donoghue clock-names = "camnoc_axi", 3168*e7173009SBryan O'Donoghue "slow_ahb_src", 3169*e7173009SBryan O'Donoghue "cpas_ahb", 3170*e7173009SBryan O'Donoghue "cci", 3171*e7173009SBryan O'Donoghue "cci_src"; 3172*e7173009SBryan O'Donoghue 3173*e7173009SBryan O'Donoghue pinctrl-0 = <&cci0_default>; 3174*e7173009SBryan O'Donoghue pinctrl-1 = <&cci0_sleep>; 3175*e7173009SBryan O'Donoghue pinctrl-names = "default", "sleep"; 3176*e7173009SBryan O'Donoghue 3177*e7173009SBryan O'Donoghue status = "disabled"; 3178*e7173009SBryan O'Donoghue 3179*e7173009SBryan O'Donoghue cci0_i2c0: i2c-bus@0 { 3180*e7173009SBryan O'Donoghue reg = <0>; 3181*e7173009SBryan O'Donoghue clock-frequency = <1000000>; 3182*e7173009SBryan O'Donoghue #address-cells = <1>; 3183*e7173009SBryan O'Donoghue #size-cells = <0>; 3184*e7173009SBryan O'Donoghue }; 3185*e7173009SBryan O'Donoghue 3186*e7173009SBryan O'Donoghue cci0_i2c1: i2c-bus@1 { 3187*e7173009SBryan O'Donoghue reg = <1>; 3188*e7173009SBryan O'Donoghue clock-frequency = <1000000>; 3189*e7173009SBryan O'Donoghue #address-cells = <1>; 3190*e7173009SBryan O'Donoghue #size-cells = <0>; 3191*e7173009SBryan O'Donoghue }; 3192*e7173009SBryan O'Donoghue }; 3193*e7173009SBryan O'Donoghue 3194*e7173009SBryan O'Donoghue cci1: cci@ac50000 { 3195*e7173009SBryan O'Donoghue compatible = "qcom,sm8250-cci"; 3196*e7173009SBryan O'Donoghue #address-cells = <1>; 3197*e7173009SBryan O'Donoghue #size-cells = <0>; 3198*e7173009SBryan O'Donoghue 3199*e7173009SBryan O'Donoghue reg = <0 0x0ac50000 0 0x1000>; 3200*e7173009SBryan O'Donoghue interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 3201*e7173009SBryan O'Donoghue power-domains = <&camcc TITAN_TOP_GDSC>; 3202*e7173009SBryan O'Donoghue 3203*e7173009SBryan O'Donoghue clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3204*e7173009SBryan O'Donoghue <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3205*e7173009SBryan O'Donoghue <&camcc CAM_CC_CPAS_AHB_CLK>, 3206*e7173009SBryan O'Donoghue <&camcc CAM_CC_CCI_1_CLK>, 3207*e7173009SBryan O'Donoghue <&camcc CAM_CC_CCI_1_CLK_SRC>; 3208*e7173009SBryan O'Donoghue clock-names = "camnoc_axi", 3209*e7173009SBryan O'Donoghue "slow_ahb_src", 3210*e7173009SBryan O'Donoghue "cpas_ahb", 3211*e7173009SBryan O'Donoghue "cci", 3212*e7173009SBryan O'Donoghue "cci_src"; 3213*e7173009SBryan O'Donoghue 3214*e7173009SBryan O'Donoghue pinctrl-0 = <&cci1_default>; 3215*e7173009SBryan O'Donoghue pinctrl-1 = <&cci1_sleep>; 3216*e7173009SBryan O'Donoghue pinctrl-names = "default", "sleep"; 3217*e7173009SBryan O'Donoghue 3218*e7173009SBryan O'Donoghue status = "disabled"; 3219*e7173009SBryan O'Donoghue 3220*e7173009SBryan O'Donoghue cci1_i2c0: i2c-bus@0 { 3221*e7173009SBryan O'Donoghue reg = <0>; 3222*e7173009SBryan O'Donoghue clock-frequency = <1000000>; 3223*e7173009SBryan O'Donoghue #address-cells = <1>; 3224*e7173009SBryan O'Donoghue #size-cells = <0>; 3225*e7173009SBryan O'Donoghue }; 3226*e7173009SBryan O'Donoghue 3227*e7173009SBryan O'Donoghue cci1_i2c1: i2c-bus@1 { 3228*e7173009SBryan O'Donoghue reg = <1>; 3229*e7173009SBryan O'Donoghue clock-frequency = <1000000>; 3230*e7173009SBryan O'Donoghue #address-cells = <1>; 3231*e7173009SBryan O'Donoghue #size-cells = <0>; 3232*e7173009SBryan O'Donoghue }; 3233*e7173009SBryan O'Donoghue }; 3234*e7173009SBryan O'Donoghue 323530325603SBryan O'Donoghue camss: camss@ac6a000 { 323630325603SBryan O'Donoghue compatible = "qcom,sm8250-camss"; 323730325603SBryan O'Donoghue status = "disabled"; 323830325603SBryan O'Donoghue 323930325603SBryan O'Donoghue reg = <0 0xac6a000 0 0x2000>, 324030325603SBryan O'Donoghue <0 0xac6c000 0 0x2000>, 324130325603SBryan O'Donoghue <0 0xac6e000 0 0x1000>, 324230325603SBryan O'Donoghue <0 0xac70000 0 0x1000>, 324330325603SBryan O'Donoghue <0 0xac72000 0 0x1000>, 324430325603SBryan O'Donoghue <0 0xac74000 0 0x1000>, 324530325603SBryan O'Donoghue <0 0xacb4000 0 0xd000>, 324630325603SBryan O'Donoghue <0 0xacc3000 0 0xd000>, 324730325603SBryan O'Donoghue <0 0xacd9000 0 0x2200>, 324830325603SBryan O'Donoghue <0 0xacdb200 0 0x2200>; 324930325603SBryan O'Donoghue reg-names = "csiphy0", 325030325603SBryan O'Donoghue "csiphy1", 325130325603SBryan O'Donoghue "csiphy2", 325230325603SBryan O'Donoghue "csiphy3", 325330325603SBryan O'Donoghue "csiphy4", 325430325603SBryan O'Donoghue "csiphy5", 325530325603SBryan O'Donoghue "vfe0", 325630325603SBryan O'Donoghue "vfe1", 325730325603SBryan O'Donoghue "vfe_lite0", 325830325603SBryan O'Donoghue "vfe_lite1"; 325930325603SBryan O'Donoghue 326030325603SBryan O'Donoghue interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 326130325603SBryan O'Donoghue <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 326230325603SBryan O'Donoghue <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 326330325603SBryan O'Donoghue <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 326430325603SBryan O'Donoghue <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 326530325603SBryan O'Donoghue <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 326630325603SBryan O'Donoghue <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 326730325603SBryan O'Donoghue <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 326830325603SBryan O'Donoghue <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 326930325603SBryan O'Donoghue <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 327030325603SBryan O'Donoghue <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 327130325603SBryan O'Donoghue <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 327230325603SBryan O'Donoghue <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 327330325603SBryan O'Donoghue <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 327430325603SBryan O'Donoghue interrupt-names = "csiphy0", 327530325603SBryan O'Donoghue "csiphy1", 327630325603SBryan O'Donoghue "csiphy2", 327730325603SBryan O'Donoghue "csiphy3", 327830325603SBryan O'Donoghue "csiphy4", 327930325603SBryan O'Donoghue "csiphy5", 328030325603SBryan O'Donoghue "csid0", 328130325603SBryan O'Donoghue "csid1", 328230325603SBryan O'Donoghue "csid2", 328330325603SBryan O'Donoghue "csid3", 328430325603SBryan O'Donoghue "vfe0", 328530325603SBryan O'Donoghue "vfe1", 328630325603SBryan O'Donoghue "vfe_lite0", 328730325603SBryan O'Donoghue "vfe_lite1"; 328830325603SBryan O'Donoghue 328930325603SBryan O'Donoghue power-domains = <&camcc IFE_0_GDSC>, 329030325603SBryan O'Donoghue <&camcc IFE_1_GDSC>, 329130325603SBryan O'Donoghue <&camcc TITAN_TOP_GDSC>; 329230325603SBryan O'Donoghue 329330325603SBryan O'Donoghue clocks = <&gcc GCC_CAMERA_AHB_CLK>, 329430325603SBryan O'Donoghue <&gcc GCC_CAMERA_HF_AXI_CLK>, 329530325603SBryan O'Donoghue <&gcc GCC_CAMERA_SF_AXI_CLK>, 329630325603SBryan O'Donoghue <&camcc CAM_CC_CAMNOC_AXI_CLK>, 329730325603SBryan O'Donoghue <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, 329830325603SBryan O'Donoghue <&camcc CAM_CC_CORE_AHB_CLK>, 329930325603SBryan O'Donoghue <&camcc CAM_CC_CPAS_AHB_CLK>, 330030325603SBryan O'Donoghue <&camcc CAM_CC_CSIPHY0_CLK>, 330130325603SBryan O'Donoghue <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 330230325603SBryan O'Donoghue <&camcc CAM_CC_CSIPHY1_CLK>, 330330325603SBryan O'Donoghue <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 330430325603SBryan O'Donoghue <&camcc CAM_CC_CSIPHY2_CLK>, 330530325603SBryan O'Donoghue <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 330630325603SBryan O'Donoghue <&camcc CAM_CC_CSIPHY3_CLK>, 330730325603SBryan O'Donoghue <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 330830325603SBryan O'Donoghue <&camcc CAM_CC_CSIPHY4_CLK>, 330930325603SBryan O'Donoghue <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 331030325603SBryan O'Donoghue <&camcc CAM_CC_CSIPHY5_CLK>, 331130325603SBryan O'Donoghue <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 331230325603SBryan O'Donoghue <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 331330325603SBryan O'Donoghue <&camcc CAM_CC_IFE_0_AHB_CLK>, 331430325603SBryan O'Donoghue <&camcc CAM_CC_IFE_0_AXI_CLK>, 331530325603SBryan O'Donoghue <&camcc CAM_CC_IFE_0_CLK>, 331630325603SBryan O'Donoghue <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 331730325603SBryan O'Donoghue <&camcc CAM_CC_IFE_0_CSID_CLK>, 331830325603SBryan O'Donoghue <&camcc CAM_CC_IFE_0_AREG_CLK>, 331930325603SBryan O'Donoghue <&camcc CAM_CC_IFE_1_AHB_CLK>, 332030325603SBryan O'Donoghue <&camcc CAM_CC_IFE_1_AXI_CLK>, 332130325603SBryan O'Donoghue <&camcc CAM_CC_IFE_1_CLK>, 332230325603SBryan O'Donoghue <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 332330325603SBryan O'Donoghue <&camcc CAM_CC_IFE_1_CSID_CLK>, 332430325603SBryan O'Donoghue <&camcc CAM_CC_IFE_1_AREG_CLK>, 332530325603SBryan O'Donoghue <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 332630325603SBryan O'Donoghue <&camcc CAM_CC_IFE_LITE_AXI_CLK>, 332730325603SBryan O'Donoghue <&camcc CAM_CC_IFE_LITE_CLK>, 332830325603SBryan O'Donoghue <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 332930325603SBryan O'Donoghue <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 333030325603SBryan O'Donoghue 333130325603SBryan O'Donoghue clock-names = "cam_ahb_clk", 333230325603SBryan O'Donoghue "cam_hf_axi", 333330325603SBryan O'Donoghue "cam_sf_axi", 333430325603SBryan O'Donoghue "camnoc_axi", 333530325603SBryan O'Donoghue "camnoc_axi_src", 333630325603SBryan O'Donoghue "core_ahb", 333730325603SBryan O'Donoghue "cpas_ahb", 333830325603SBryan O'Donoghue "csiphy0", 333930325603SBryan O'Donoghue "csiphy0_timer", 334030325603SBryan O'Donoghue "csiphy1", 334130325603SBryan O'Donoghue "csiphy1_timer", 334230325603SBryan O'Donoghue "csiphy2", 334330325603SBryan O'Donoghue "csiphy2_timer", 334430325603SBryan O'Donoghue "csiphy3", 334530325603SBryan O'Donoghue "csiphy3_timer", 334630325603SBryan O'Donoghue "csiphy4", 334730325603SBryan O'Donoghue "csiphy4_timer", 334830325603SBryan O'Donoghue "csiphy5", 334930325603SBryan O'Donoghue "csiphy5_timer", 335030325603SBryan O'Donoghue "slow_ahb_src", 335130325603SBryan O'Donoghue "vfe0_ahb", 335230325603SBryan O'Donoghue "vfe0_axi", 335330325603SBryan O'Donoghue "vfe0", 335430325603SBryan O'Donoghue "vfe0_cphy_rx", 335530325603SBryan O'Donoghue "vfe0_csid", 335630325603SBryan O'Donoghue "vfe0_areg", 335730325603SBryan O'Donoghue "vfe1_ahb", 335830325603SBryan O'Donoghue "vfe1_axi", 335930325603SBryan O'Donoghue "vfe1", 336030325603SBryan O'Donoghue "vfe1_cphy_rx", 336130325603SBryan O'Donoghue "vfe1_csid", 336230325603SBryan O'Donoghue "vfe1_areg", 336330325603SBryan O'Donoghue "vfe_lite_ahb", 336430325603SBryan O'Donoghue "vfe_lite_axi", 336530325603SBryan O'Donoghue "vfe_lite", 336630325603SBryan O'Donoghue "vfe_lite_cphy_rx", 336730325603SBryan O'Donoghue "vfe_lite_csid"; 336830325603SBryan O'Donoghue 336930325603SBryan O'Donoghue iommus = <&apps_smmu 0x800 0x400>, 337030325603SBryan O'Donoghue <&apps_smmu 0x801 0x400>, 337130325603SBryan O'Donoghue <&apps_smmu 0x840 0x400>, 337230325603SBryan O'Donoghue <&apps_smmu 0x841 0x400>, 337330325603SBryan O'Donoghue <&apps_smmu 0xc00 0x400>, 337430325603SBryan O'Donoghue <&apps_smmu 0xc01 0x400>, 337530325603SBryan O'Donoghue <&apps_smmu 0xc40 0x400>, 337630325603SBryan O'Donoghue <&apps_smmu 0xc41 0x400>; 337730325603SBryan O'Donoghue 337830325603SBryan O'Donoghue interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>, 337930325603SBryan O'Donoghue <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>, 338030325603SBryan O'Donoghue <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>, 338130325603SBryan O'Donoghue <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>; 338230325603SBryan O'Donoghue interconnect-names = "cam_ahb", 338330325603SBryan O'Donoghue "cam_hf_0_mnoc", 338430325603SBryan O'Donoghue "cam_sf_0_mnoc", 338530325603SBryan O'Donoghue "cam_sf_icp_mnoc"; 338630325603SBryan O'Donoghue }; 338730325603SBryan O'Donoghue 3388ca79a997SBryan O'Donoghue camcc: clock-controller@ad00000 { 3389ca79a997SBryan O'Donoghue compatible = "qcom,sm8250-camcc"; 3390ca79a997SBryan O'Donoghue reg = <0 0x0ad00000 0 0x10000>; 3391ca79a997SBryan O'Donoghue clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3392ca79a997SBryan O'Donoghue <&rpmhcc RPMH_CXO_CLK>, 3393ca79a997SBryan O'Donoghue <&rpmhcc RPMH_CXO_CLK_A>, 3394ca79a997SBryan O'Donoghue <&sleep_clk>; 3395ca79a997SBryan O'Donoghue clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3396ca79a997SBryan O'Donoghue power-domains = <&rpmhpd SM8250_MMCX>; 3397ca79a997SBryan O'Donoghue required-opps = <&rpmhpd_opp_low_svs>; 3398ca79a997SBryan O'Donoghue #clock-cells = <1>; 3399ca79a997SBryan O'Donoghue #reset-cells = <1>; 3400ca79a997SBryan O'Donoghue #power-domain-cells = <1>; 3401ca79a997SBryan O'Donoghue }; 3402ca79a997SBryan O'Donoghue 34037c1dffd4SDmitry Baryshkov mdss: mdss@ae00000 { 3404dc5d9125SJonathan Marek compatible = "qcom,sm8250-mdss"; 34057c1dffd4SDmitry Baryshkov reg = <0 0x0ae00000 0 0x1000>; 34067c1dffd4SDmitry Baryshkov reg-names = "mdss"; 34077c1dffd4SDmitry Baryshkov 3408888771a9SJonathan Marek interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 34097c1dffd4SDmitry Baryshkov <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 3410888771a9SJonathan Marek interconnect-names = "mdp0-mem", "mdp1-mem"; 34117c1dffd4SDmitry Baryshkov 34127c1dffd4SDmitry Baryshkov power-domains = <&dispcc MDSS_GDSC>; 34137c1dffd4SDmitry Baryshkov 34147c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3415e091b836SAmit Pundir <&gcc GCC_DISP_HF_AXI_CLK>, 34167c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_SF_AXI_CLK>, 34177c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_MDP_CLK>; 3418e091b836SAmit Pundir clock-names = "iface", "bus", "nrt_bus", "core"; 34197c1dffd4SDmitry Baryshkov 34207c1dffd4SDmitry Baryshkov assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 34217c1dffd4SDmitry Baryshkov assigned-clock-rates = <460000000>; 34227c1dffd4SDmitry Baryshkov 34237c1dffd4SDmitry Baryshkov interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 34247c1dffd4SDmitry Baryshkov interrupt-controller; 34257c1dffd4SDmitry Baryshkov #interrupt-cells = <1>; 34267c1dffd4SDmitry Baryshkov 34277c1dffd4SDmitry Baryshkov iommus = <&apps_smmu 0x820 0x402>; 34287c1dffd4SDmitry Baryshkov 34297c1dffd4SDmitry Baryshkov status = "disabled"; 34307c1dffd4SDmitry Baryshkov 34317c1dffd4SDmitry Baryshkov #address-cells = <2>; 34327c1dffd4SDmitry Baryshkov #size-cells = <2>; 34337c1dffd4SDmitry Baryshkov ranges; 34347c1dffd4SDmitry Baryshkov 34357c1dffd4SDmitry Baryshkov mdss_mdp: mdp@ae01000 { 3436dc5d9125SJonathan Marek compatible = "qcom,sm8250-dpu"; 34377c1dffd4SDmitry Baryshkov reg = <0 0x0ae01000 0 0x8f000>, 34387c1dffd4SDmitry Baryshkov <0 0x0aeb0000 0 0x2008>; 34397c1dffd4SDmitry Baryshkov reg-names = "mdp", "vbif"; 34407c1dffd4SDmitry Baryshkov 34417c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 34427c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_HF_AXI_CLK>, 34437c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_MDP_CLK>, 34447c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 34457c1dffd4SDmitry Baryshkov clock-names = "iface", "bus", "core", "vsync"; 34467c1dffd4SDmitry Baryshkov 34477c1dffd4SDmitry Baryshkov assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 34487c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 34497c1dffd4SDmitry Baryshkov assigned-clock-rates = <460000000>, 34507c1dffd4SDmitry Baryshkov <19200000>; 34517c1dffd4SDmitry Baryshkov 34527c1dffd4SDmitry Baryshkov operating-points-v2 = <&mdp_opp_table>; 34537c1dffd4SDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 34547c1dffd4SDmitry Baryshkov 34557c1dffd4SDmitry Baryshkov interrupt-parent = <&mdss>; 3456be633329SDmitry Baryshkov interrupts = <0>; 34577c1dffd4SDmitry Baryshkov 34587c1dffd4SDmitry Baryshkov ports { 34597c1dffd4SDmitry Baryshkov #address-cells = <1>; 34607c1dffd4SDmitry Baryshkov #size-cells = <0>; 34617c1dffd4SDmitry Baryshkov 34627c1dffd4SDmitry Baryshkov port@0 { 34637c1dffd4SDmitry Baryshkov reg = <0>; 34647c1dffd4SDmitry Baryshkov dpu_intf1_out: endpoint { 34657c1dffd4SDmitry Baryshkov remote-endpoint = <&dsi0_in>; 34667c1dffd4SDmitry Baryshkov }; 34677c1dffd4SDmitry Baryshkov }; 34687c1dffd4SDmitry Baryshkov 34697c1dffd4SDmitry Baryshkov port@1 { 34707c1dffd4SDmitry Baryshkov reg = <1>; 34717c1dffd4SDmitry Baryshkov dpu_intf2_out: endpoint { 34727c1dffd4SDmitry Baryshkov remote-endpoint = <&dsi1_in>; 34737c1dffd4SDmitry Baryshkov }; 34747c1dffd4SDmitry Baryshkov }; 34757c1dffd4SDmitry Baryshkov }; 34767c1dffd4SDmitry Baryshkov 34777c1dffd4SDmitry Baryshkov mdp_opp_table: mdp-opp-table { 34787c1dffd4SDmitry Baryshkov compatible = "operating-points-v2"; 34797c1dffd4SDmitry Baryshkov 34807c1dffd4SDmitry Baryshkov opp-200000000 { 34817c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <200000000>; 34827c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 34837c1dffd4SDmitry Baryshkov }; 34847c1dffd4SDmitry Baryshkov 34857c1dffd4SDmitry Baryshkov opp-300000000 { 34867c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <300000000>; 34877c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs>; 34887c1dffd4SDmitry Baryshkov }; 34897c1dffd4SDmitry Baryshkov 34907c1dffd4SDmitry Baryshkov opp-345000000 { 34917c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <345000000>; 34927c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs_l1>; 34937c1dffd4SDmitry Baryshkov }; 34947c1dffd4SDmitry Baryshkov 34957c1dffd4SDmitry Baryshkov opp-460000000 { 34967c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <460000000>; 34977c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_nom>; 34987c1dffd4SDmitry Baryshkov }; 34997c1dffd4SDmitry Baryshkov }; 35007c1dffd4SDmitry Baryshkov }; 35017c1dffd4SDmitry Baryshkov 35027c1dffd4SDmitry Baryshkov dsi0: dsi@ae94000 { 35037c1dffd4SDmitry Baryshkov compatible = "qcom,mdss-dsi-ctrl"; 35047c1dffd4SDmitry Baryshkov reg = <0 0x0ae94000 0 0x400>; 35057c1dffd4SDmitry Baryshkov reg-names = "dsi_ctrl"; 35067c1dffd4SDmitry Baryshkov 35077c1dffd4SDmitry Baryshkov interrupt-parent = <&mdss>; 3508be633329SDmitry Baryshkov interrupts = <4>; 35097c1dffd4SDmitry Baryshkov 35107c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 35117c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 35127c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 35137c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_ESC0_CLK>, 35147c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_AHB_CLK>, 35157c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_HF_AXI_CLK>; 35167c1dffd4SDmitry Baryshkov clock-names = "byte", 35177c1dffd4SDmitry Baryshkov "byte_intf", 35187c1dffd4SDmitry Baryshkov "pixel", 35197c1dffd4SDmitry Baryshkov "core", 35207c1dffd4SDmitry Baryshkov "iface", 35217c1dffd4SDmitry Baryshkov "bus"; 35227c1dffd4SDmitry Baryshkov 352397ec669dSDmitry Baryshkov assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 352497ec669dSDmitry Baryshkov assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 352597ec669dSDmitry Baryshkov 35267c1dffd4SDmitry Baryshkov operating-points-v2 = <&dsi_opp_table>; 35277c1dffd4SDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 35287c1dffd4SDmitry Baryshkov 35297c1dffd4SDmitry Baryshkov phys = <&dsi0_phy>; 35307c1dffd4SDmitry Baryshkov phy-names = "dsi"; 35317c1dffd4SDmitry Baryshkov 35327c1dffd4SDmitry Baryshkov status = "disabled"; 35337c1dffd4SDmitry Baryshkov 353440f7d36dSKonrad Dybcio #address-cells = <1>; 353540f7d36dSKonrad Dybcio #size-cells = <0>; 353640f7d36dSKonrad Dybcio 35377c1dffd4SDmitry Baryshkov ports { 35387c1dffd4SDmitry Baryshkov #address-cells = <1>; 35397c1dffd4SDmitry Baryshkov #size-cells = <0>; 35407c1dffd4SDmitry Baryshkov 35417c1dffd4SDmitry Baryshkov port@0 { 35427c1dffd4SDmitry Baryshkov reg = <0>; 35437c1dffd4SDmitry Baryshkov dsi0_in: endpoint { 35447c1dffd4SDmitry Baryshkov remote-endpoint = <&dpu_intf1_out>; 35457c1dffd4SDmitry Baryshkov }; 35467c1dffd4SDmitry Baryshkov }; 35477c1dffd4SDmitry Baryshkov 35487c1dffd4SDmitry Baryshkov port@1 { 35497c1dffd4SDmitry Baryshkov reg = <1>; 35507c1dffd4SDmitry Baryshkov dsi0_out: endpoint { 35517c1dffd4SDmitry Baryshkov }; 35527c1dffd4SDmitry Baryshkov }; 35537c1dffd4SDmitry Baryshkov }; 35547c1dffd4SDmitry Baryshkov }; 35557c1dffd4SDmitry Baryshkov 35567c1dffd4SDmitry Baryshkov dsi0_phy: dsi-phy@ae94400 { 35577c1dffd4SDmitry Baryshkov compatible = "qcom,dsi-phy-7nm"; 35587c1dffd4SDmitry Baryshkov reg = <0 0x0ae94400 0 0x200>, 35597c1dffd4SDmitry Baryshkov <0 0x0ae94600 0 0x280>, 35607c1dffd4SDmitry Baryshkov <0 0x0ae94900 0 0x260>; 35617c1dffd4SDmitry Baryshkov reg-names = "dsi_phy", 35627c1dffd4SDmitry Baryshkov "dsi_phy_lane", 35637c1dffd4SDmitry Baryshkov "dsi_pll"; 35647c1dffd4SDmitry Baryshkov 35657c1dffd4SDmitry Baryshkov #clock-cells = <1>; 35667c1dffd4SDmitry Baryshkov #phy-cells = <0>; 35677c1dffd4SDmitry Baryshkov 35687c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 35697c1dffd4SDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK>; 35707c1dffd4SDmitry Baryshkov clock-names = "iface", "ref"; 35717c1dffd4SDmitry Baryshkov 35727c1dffd4SDmitry Baryshkov status = "disabled"; 35737c1dffd4SDmitry Baryshkov }; 35747c1dffd4SDmitry Baryshkov 35757c1dffd4SDmitry Baryshkov dsi1: dsi@ae96000 { 35767c1dffd4SDmitry Baryshkov compatible = "qcom,mdss-dsi-ctrl"; 35777c1dffd4SDmitry Baryshkov reg = <0 0x0ae96000 0 0x400>; 35787c1dffd4SDmitry Baryshkov reg-names = "dsi_ctrl"; 35797c1dffd4SDmitry Baryshkov 35807c1dffd4SDmitry Baryshkov interrupt-parent = <&mdss>; 3581be633329SDmitry Baryshkov interrupts = <5>; 35827c1dffd4SDmitry Baryshkov 35837c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 35847c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 35857c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 35867c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_ESC1_CLK>, 35877c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_AHB_CLK>, 35887c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_HF_AXI_CLK>; 35897c1dffd4SDmitry Baryshkov clock-names = "byte", 35907c1dffd4SDmitry Baryshkov "byte_intf", 35917c1dffd4SDmitry Baryshkov "pixel", 35927c1dffd4SDmitry Baryshkov "core", 35937c1dffd4SDmitry Baryshkov "iface", 35947c1dffd4SDmitry Baryshkov "bus"; 35957c1dffd4SDmitry Baryshkov 359697ec669dSDmitry Baryshkov assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 359797ec669dSDmitry Baryshkov assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 359897ec669dSDmitry Baryshkov 35997c1dffd4SDmitry Baryshkov operating-points-v2 = <&dsi_opp_table>; 36007c1dffd4SDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 36017c1dffd4SDmitry Baryshkov 36027c1dffd4SDmitry Baryshkov phys = <&dsi1_phy>; 36037c1dffd4SDmitry Baryshkov phy-names = "dsi"; 36047c1dffd4SDmitry Baryshkov 36057c1dffd4SDmitry Baryshkov status = "disabled"; 36067c1dffd4SDmitry Baryshkov 360740f7d36dSKonrad Dybcio #address-cells = <1>; 360840f7d36dSKonrad Dybcio #size-cells = <0>; 360940f7d36dSKonrad Dybcio 36107c1dffd4SDmitry Baryshkov ports { 36117c1dffd4SDmitry Baryshkov #address-cells = <1>; 36127c1dffd4SDmitry Baryshkov #size-cells = <0>; 36137c1dffd4SDmitry Baryshkov 36147c1dffd4SDmitry Baryshkov port@0 { 36157c1dffd4SDmitry Baryshkov reg = <0>; 36167c1dffd4SDmitry Baryshkov dsi1_in: endpoint { 36177c1dffd4SDmitry Baryshkov remote-endpoint = <&dpu_intf2_out>; 36187c1dffd4SDmitry Baryshkov }; 36197c1dffd4SDmitry Baryshkov }; 36207c1dffd4SDmitry Baryshkov 36217c1dffd4SDmitry Baryshkov port@1 { 36227c1dffd4SDmitry Baryshkov reg = <1>; 36237c1dffd4SDmitry Baryshkov dsi1_out: endpoint { 36247c1dffd4SDmitry Baryshkov }; 36257c1dffd4SDmitry Baryshkov }; 36267c1dffd4SDmitry Baryshkov }; 36277c1dffd4SDmitry Baryshkov }; 36287c1dffd4SDmitry Baryshkov 36297c1dffd4SDmitry Baryshkov dsi1_phy: dsi-phy@ae96400 { 36307c1dffd4SDmitry Baryshkov compatible = "qcom,dsi-phy-7nm"; 36317c1dffd4SDmitry Baryshkov reg = <0 0x0ae96400 0 0x200>, 36327c1dffd4SDmitry Baryshkov <0 0x0ae96600 0 0x280>, 36337c1dffd4SDmitry Baryshkov <0 0x0ae96900 0 0x260>; 36347c1dffd4SDmitry Baryshkov reg-names = "dsi_phy", 36357c1dffd4SDmitry Baryshkov "dsi_phy_lane", 36367c1dffd4SDmitry Baryshkov "dsi_pll"; 36377c1dffd4SDmitry Baryshkov 36387c1dffd4SDmitry Baryshkov #clock-cells = <1>; 36397c1dffd4SDmitry Baryshkov #phy-cells = <0>; 36407c1dffd4SDmitry Baryshkov 36417c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 36427c1dffd4SDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK>; 36437c1dffd4SDmitry Baryshkov clock-names = "iface", "ref"; 36447c1dffd4SDmitry Baryshkov 36457c1dffd4SDmitry Baryshkov status = "disabled"; 36467c1dffd4SDmitry Baryshkov 36477c1dffd4SDmitry Baryshkov dsi_opp_table: dsi-opp-table { 36487c1dffd4SDmitry Baryshkov compatible = "operating-points-v2"; 36497c1dffd4SDmitry Baryshkov 36507c1dffd4SDmitry Baryshkov opp-187500000 { 36517c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <187500000>; 36527c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 36537c1dffd4SDmitry Baryshkov }; 36547c1dffd4SDmitry Baryshkov 36557c1dffd4SDmitry Baryshkov opp-300000000 { 36567c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <300000000>; 36577c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs>; 36587c1dffd4SDmitry Baryshkov }; 36597c1dffd4SDmitry Baryshkov 36607c1dffd4SDmitry Baryshkov opp-358000000 { 36617c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <358000000>; 36627c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs_l1>; 36637c1dffd4SDmitry Baryshkov }; 36647c1dffd4SDmitry Baryshkov }; 36657c1dffd4SDmitry Baryshkov }; 36667c1dffd4SDmitry Baryshkov }; 36677c1dffd4SDmitry Baryshkov 36687c1dffd4SDmitry Baryshkov dispcc: clock-controller@af00000 { 36697c1dffd4SDmitry Baryshkov compatible = "qcom,sm8250-dispcc"; 3670888771a9SJonathan Marek reg = <0 0x0af00000 0 0x10000>; 3671266e5cf3SDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 3672266e5cf3SDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 36737c1dffd4SDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>, 36747c1dffd4SDmitry Baryshkov <&dsi0_phy 0>, 36757c1dffd4SDmitry Baryshkov <&dsi0_phy 1>, 36767c1dffd4SDmitry Baryshkov <&dsi1_phy 0>, 36777c1dffd4SDmitry Baryshkov <&dsi1_phy 1>, 36789b315324SDmitry Baryshkov <&dp_phy 0>, 36799b315324SDmitry Baryshkov <&dp_phy 1>; 36807c1dffd4SDmitry Baryshkov clock-names = "bi_tcxo", 36817c1dffd4SDmitry Baryshkov "dsi0_phy_pll_out_byteclk", 36827c1dffd4SDmitry Baryshkov "dsi0_phy_pll_out_dsiclk", 36837c1dffd4SDmitry Baryshkov "dsi1_phy_pll_out_byteclk", 36847c1dffd4SDmitry Baryshkov "dsi1_phy_pll_out_dsiclk", 3685888771a9SJonathan Marek "dp_phy_pll_link_clk", 3686888771a9SJonathan Marek "dp_phy_pll_vco_div_clk"; 36877c1dffd4SDmitry Baryshkov #clock-cells = <1>; 36887c1dffd4SDmitry Baryshkov #reset-cells = <1>; 36897c1dffd4SDmitry Baryshkov #power-domain-cells = <1>; 36907c1dffd4SDmitry Baryshkov }; 36917c1dffd4SDmitry Baryshkov 369260378f1aSVenkata Narendra Kumar Gutta pdc: interrupt-controller@b220000 { 369324003196SBjorn Andersson compatible = "qcom,sm8250-pdc", "qcom,pdc"; 369424003196SBjorn Andersson reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 369560378f1aSVenkata Narendra Kumar Gutta qcom,pdc-ranges = <0 480 94>, <94 609 31>, 369660378f1aSVenkata Narendra Kumar Gutta <125 63 1>, <126 716 12>; 369760378f1aSVenkata Narendra Kumar Gutta #interrupt-cells = <2>; 369860378f1aSVenkata Narendra Kumar Gutta interrupt-parent = <&intc>; 369960378f1aSVenkata Narendra Kumar Gutta interrupt-controller; 370060378f1aSVenkata Narendra Kumar Gutta }; 370160378f1aSVenkata Narendra Kumar Gutta 3702bac12f25SAmit Kucheria tsens0: thermal-sensor@c263000 { 3703bac12f25SAmit Kucheria compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 3704bac12f25SAmit Kucheria reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3705bac12f25SAmit Kucheria <0 0x0c222000 0 0x1ff>; /* SROT */ 3706bac12f25SAmit Kucheria #qcom,sensors = <16>; 3707bac12f25SAmit Kucheria interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3708bac12f25SAmit Kucheria <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3709bac12f25SAmit Kucheria interrupt-names = "uplow", "critical"; 3710bac12f25SAmit Kucheria #thermal-sensor-cells = <1>; 3711bac12f25SAmit Kucheria }; 3712bac12f25SAmit Kucheria 3713bac12f25SAmit Kucheria tsens1: thermal-sensor@c265000 { 3714bac12f25SAmit Kucheria compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 3715bac12f25SAmit Kucheria reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3716bac12f25SAmit Kucheria <0 0x0c223000 0 0x1ff>; /* SROT */ 3717bac12f25SAmit Kucheria #qcom,sensors = <9>; 3718bac12f25SAmit Kucheria interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3719bac12f25SAmit Kucheria <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3720bac12f25SAmit Kucheria interrupt-names = "uplow", "critical"; 3721bac12f25SAmit Kucheria #thermal-sensor-cells = <1>; 3722bac12f25SAmit Kucheria }; 3723bac12f25SAmit Kucheria 372443f14a0bSSai Prakash Ranjan aoss_qmp: power-controller@c300000 { 3725087d537aSBjorn Andersson compatible = "qcom,sm8250-aoss-qmp"; 372647cb6a06SMaulik Shah reg = <0 0x0c300000 0 0x400>; 3727087d537aSBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3728087d537aSBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 3729087d537aSBjorn Andersson IRQ_TYPE_EDGE_RISING>; 3730087d537aSBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_AOP 3731087d537aSBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 3732087d537aSBjorn Andersson 3733087d537aSBjorn Andersson #clock-cells = <0>; 3734087d537aSBjorn Andersson }; 3735087d537aSBjorn Andersson 373647cb6a06SMaulik Shah sram@c3f0000 { 373747cb6a06SMaulik Shah compatible = "qcom,rpmh-stats"; 373847cb6a06SMaulik Shah reg = <0 0x0c3f0000 0 0x400>; 373960378f1aSVenkata Narendra Kumar Gutta }; 374060378f1aSVenkata Narendra Kumar Gutta 374160378f1aSVenkata Narendra Kumar Gutta spmi_bus: spmi@c440000 { 374260378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,spmi-pmic-arb"; 374360378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x0c440000 0x0 0x0001100>, 374460378f1aSVenkata Narendra Kumar Gutta <0x0 0x0c600000 0x0 0x2000000>, 374516951b49SBjorn Andersson <0x0 0x0e600000 0x0 0x0100000>, 374616951b49SBjorn Andersson <0x0 0x0e700000 0x0 0x00a0000>, 374716951b49SBjorn Andersson <0x0 0x0c40a000 0x0 0x0026000>; 374816951b49SBjorn Andersson reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 374916951b49SBjorn Andersson interrupt-names = "periph_irq"; 375016951b49SBjorn Andersson interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 375116951b49SBjorn Andersson qcom,ee = <0>; 375216951b49SBjorn Andersson qcom,channel = <0>; 375316951b49SBjorn Andersson #address-cells = <2>; 375416951b49SBjorn Andersson #size-cells = <0>; 375516951b49SBjorn Andersson interrupt-controller; 375616951b49SBjorn Andersson #interrupt-cells = <4>; 375716951b49SBjorn Andersson }; 3758e5813b15SDmitry Baryshkov 3759e5813b15SDmitry Baryshkov tlmm: pinctrl@f100000 { 3760e5813b15SDmitry Baryshkov compatible = "qcom,sm8250-pinctrl"; 3761e5813b15SDmitry Baryshkov reg = <0 0x0f100000 0 0x300000>, 3762e5813b15SDmitry Baryshkov <0 0x0f500000 0 0x300000>, 3763e5813b15SDmitry Baryshkov <0 0x0f900000 0 0x300000>; 3764e5813b15SDmitry Baryshkov reg-names = "west", "south", "north"; 3765e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3766e5813b15SDmitry Baryshkov gpio-controller; 3767e5813b15SDmitry Baryshkov #gpio-cells = <2>; 3768e5813b15SDmitry Baryshkov interrupt-controller; 3769e5813b15SDmitry Baryshkov #interrupt-cells = <2>; 3770e526cb03SShawn Guo gpio-ranges = <&tlmm 0 0 181>; 377116951b49SBjorn Andersson wakeup-parent = <&pdc>; 3772e5813b15SDmitry Baryshkov 3773*e7173009SBryan O'Donoghue cci0_default: cci0-default { 3774*e7173009SBryan O'Donoghue cci0_i2c0_default: cci0-i2c0-default { 3775*e7173009SBryan O'Donoghue /* SDA, SCL */ 3776*e7173009SBryan O'Donoghue pins = "gpio101", "gpio102"; 3777*e7173009SBryan O'Donoghue function = "cci_i2c"; 3778*e7173009SBryan O'Donoghue 3779*e7173009SBryan O'Donoghue bias-pull-up; 3780*e7173009SBryan O'Donoghue drive-strength = <2>; /* 2 mA */ 3781*e7173009SBryan O'Donoghue }; 3782*e7173009SBryan O'Donoghue 3783*e7173009SBryan O'Donoghue cci0_i2c1_default: cci0-i2c1-default { 3784*e7173009SBryan O'Donoghue /* SDA, SCL */ 3785*e7173009SBryan O'Donoghue pins = "gpio103", "gpio104"; 3786*e7173009SBryan O'Donoghue function = "cci_i2c"; 3787*e7173009SBryan O'Donoghue 3788*e7173009SBryan O'Donoghue bias-pull-up; 3789*e7173009SBryan O'Donoghue drive-strength = <2>; /* 2 mA */ 3790*e7173009SBryan O'Donoghue }; 3791*e7173009SBryan O'Donoghue }; 3792*e7173009SBryan O'Donoghue 3793*e7173009SBryan O'Donoghue cci0_sleep: cci0-sleep { 3794*e7173009SBryan O'Donoghue cci0_i2c0_sleep: cci0-i2c0-sleep { 3795*e7173009SBryan O'Donoghue /* SDA, SCL */ 3796*e7173009SBryan O'Donoghue pins = "gpio101", "gpio102"; 3797*e7173009SBryan O'Donoghue function = "cci_i2c"; 3798*e7173009SBryan O'Donoghue 3799*e7173009SBryan O'Donoghue drive-strength = <2>; /* 2 mA */ 3800*e7173009SBryan O'Donoghue bias-pull-down; 3801*e7173009SBryan O'Donoghue }; 3802*e7173009SBryan O'Donoghue 3803*e7173009SBryan O'Donoghue cci0_i2c1_sleep: cci0-i2c1-sleep { 3804*e7173009SBryan O'Donoghue /* SDA, SCL */ 3805*e7173009SBryan O'Donoghue pins = "gpio103", "gpio104"; 3806*e7173009SBryan O'Donoghue function = "cci_i2c"; 3807*e7173009SBryan O'Donoghue 3808*e7173009SBryan O'Donoghue drive-strength = <2>; /* 2 mA */ 3809*e7173009SBryan O'Donoghue bias-pull-down; 3810*e7173009SBryan O'Donoghue }; 3811*e7173009SBryan O'Donoghue }; 3812*e7173009SBryan O'Donoghue 3813*e7173009SBryan O'Donoghue cci1_default: cci1-default { 3814*e7173009SBryan O'Donoghue cci1_i2c0_default: cci1-i2c0-default { 3815*e7173009SBryan O'Donoghue /* SDA, SCL */ 3816*e7173009SBryan O'Donoghue pins = "gpio105","gpio106"; 3817*e7173009SBryan O'Donoghue function = "cci_i2c"; 3818*e7173009SBryan O'Donoghue 3819*e7173009SBryan O'Donoghue bias-pull-up; 3820*e7173009SBryan O'Donoghue drive-strength = <2>; /* 2 mA */ 3821*e7173009SBryan O'Donoghue }; 3822*e7173009SBryan O'Donoghue 3823*e7173009SBryan O'Donoghue cci1_i2c1_default: cci1-i2c1-default { 3824*e7173009SBryan O'Donoghue /* SDA, SCL */ 3825*e7173009SBryan O'Donoghue pins = "gpio107","gpio108"; 3826*e7173009SBryan O'Donoghue function = "cci_i2c"; 3827*e7173009SBryan O'Donoghue 3828*e7173009SBryan O'Donoghue bias-pull-up; 3829*e7173009SBryan O'Donoghue drive-strength = <2>; /* 2 mA */ 3830*e7173009SBryan O'Donoghue }; 3831*e7173009SBryan O'Donoghue }; 3832*e7173009SBryan O'Donoghue 3833*e7173009SBryan O'Donoghue cci1_sleep: cci1-sleep { 3834*e7173009SBryan O'Donoghue cci1_i2c0_sleep: cci1-i2c0-sleep { 3835*e7173009SBryan O'Donoghue /* SDA, SCL */ 3836*e7173009SBryan O'Donoghue pins = "gpio105","gpio106"; 3837*e7173009SBryan O'Donoghue function = "cci_i2c"; 3838*e7173009SBryan O'Donoghue 3839*e7173009SBryan O'Donoghue bias-pull-down; 3840*e7173009SBryan O'Donoghue drive-strength = <2>; /* 2 mA */ 3841*e7173009SBryan O'Donoghue }; 3842*e7173009SBryan O'Donoghue 3843*e7173009SBryan O'Donoghue cci1_i2c1_sleep: cci1-i2c1-sleep { 3844*e7173009SBryan O'Donoghue /* SDA, SCL */ 3845*e7173009SBryan O'Donoghue pins = "gpio107","gpio108"; 3846*e7173009SBryan O'Donoghue function = "cci_i2c"; 3847*e7173009SBryan O'Donoghue 3848*e7173009SBryan O'Donoghue bias-pull-down; 3849*e7173009SBryan O'Donoghue drive-strength = <2>; /* 2 mA */ 3850*e7173009SBryan O'Donoghue }; 3851*e7173009SBryan O'Donoghue }; 3852*e7173009SBryan O'Donoghue 3853b657d372SSrinivas Kandagatla pri_mi2s_active: pri-mi2s-active { 3854b657d372SSrinivas Kandagatla sclk { 3855b657d372SSrinivas Kandagatla pins = "gpio138"; 3856b657d372SSrinivas Kandagatla function = "mi2s0_sck"; 3857b657d372SSrinivas Kandagatla drive-strength = <8>; 3858b657d372SSrinivas Kandagatla bias-disable; 3859b657d372SSrinivas Kandagatla }; 3860b657d372SSrinivas Kandagatla 3861b657d372SSrinivas Kandagatla ws { 3862b657d372SSrinivas Kandagatla pins = "gpio141"; 3863b657d372SSrinivas Kandagatla function = "mi2s0_ws"; 3864b657d372SSrinivas Kandagatla drive-strength = <8>; 3865b657d372SSrinivas Kandagatla output-high; 3866b657d372SSrinivas Kandagatla }; 3867b657d372SSrinivas Kandagatla 3868b657d372SSrinivas Kandagatla data0 { 3869b657d372SSrinivas Kandagatla pins = "gpio139"; 3870b657d372SSrinivas Kandagatla function = "mi2s0_data0"; 3871b657d372SSrinivas Kandagatla drive-strength = <8>; 3872b657d372SSrinivas Kandagatla bias-disable; 3873b657d372SSrinivas Kandagatla output-high; 3874b657d372SSrinivas Kandagatla }; 3875b657d372SSrinivas Kandagatla 3876b657d372SSrinivas Kandagatla data1 { 3877b657d372SSrinivas Kandagatla pins = "gpio140"; 3878b657d372SSrinivas Kandagatla function = "mi2s0_data1"; 3879b657d372SSrinivas Kandagatla drive-strength = <8>; 3880b657d372SSrinivas Kandagatla output-high; 3881b657d372SSrinivas Kandagatla }; 3882b657d372SSrinivas Kandagatla }; 3883b657d372SSrinivas Kandagatla 3884e5813b15SDmitry Baryshkov qup_i2c0_default: qup-i2c0-default { 3885e5813b15SDmitry Baryshkov mux { 3886e5813b15SDmitry Baryshkov pins = "gpio28", "gpio29"; 3887e5813b15SDmitry Baryshkov function = "qup0"; 3888e5813b15SDmitry Baryshkov }; 3889e5813b15SDmitry Baryshkov 3890e5813b15SDmitry Baryshkov config { 3891e5813b15SDmitry Baryshkov pins = "gpio28", "gpio29"; 3892e5813b15SDmitry Baryshkov drive-strength = <2>; 3893e5813b15SDmitry Baryshkov bias-disable; 3894e5813b15SDmitry Baryshkov }; 3895e5813b15SDmitry Baryshkov }; 3896e5813b15SDmitry Baryshkov 3897e5813b15SDmitry Baryshkov qup_i2c1_default: qup-i2c1-default { 3898e5813b15SDmitry Baryshkov pinmux { 3899e5813b15SDmitry Baryshkov pins = "gpio4", "gpio5"; 3900e5813b15SDmitry Baryshkov function = "qup1"; 3901e5813b15SDmitry Baryshkov }; 3902e5813b15SDmitry Baryshkov 3903e5813b15SDmitry Baryshkov config { 3904e5813b15SDmitry Baryshkov pins = "gpio4", "gpio5"; 3905e5813b15SDmitry Baryshkov drive-strength = <2>; 3906e5813b15SDmitry Baryshkov bias-disable; 3907e5813b15SDmitry Baryshkov }; 3908e5813b15SDmitry Baryshkov }; 3909e5813b15SDmitry Baryshkov 3910e5813b15SDmitry Baryshkov qup_i2c2_default: qup-i2c2-default { 3911e5813b15SDmitry Baryshkov mux { 3912e5813b15SDmitry Baryshkov pins = "gpio115", "gpio116"; 3913e5813b15SDmitry Baryshkov function = "qup2"; 3914e5813b15SDmitry Baryshkov }; 3915e5813b15SDmitry Baryshkov 3916e5813b15SDmitry Baryshkov config { 3917e5813b15SDmitry Baryshkov pins = "gpio115", "gpio116"; 3918e5813b15SDmitry Baryshkov drive-strength = <2>; 3919e5813b15SDmitry Baryshkov bias-disable; 3920e5813b15SDmitry Baryshkov }; 3921e5813b15SDmitry Baryshkov }; 3922e5813b15SDmitry Baryshkov 3923e5813b15SDmitry Baryshkov qup_i2c3_default: qup-i2c3-default { 3924e5813b15SDmitry Baryshkov mux { 3925e5813b15SDmitry Baryshkov pins = "gpio119", "gpio120"; 3926e5813b15SDmitry Baryshkov function = "qup3"; 3927e5813b15SDmitry Baryshkov }; 3928e5813b15SDmitry Baryshkov 3929e5813b15SDmitry Baryshkov config { 3930e5813b15SDmitry Baryshkov pins = "gpio119", "gpio120"; 3931e5813b15SDmitry Baryshkov drive-strength = <2>; 3932e5813b15SDmitry Baryshkov bias-disable; 3933e5813b15SDmitry Baryshkov }; 3934e5813b15SDmitry Baryshkov }; 3935e5813b15SDmitry Baryshkov 3936e5813b15SDmitry Baryshkov qup_i2c4_default: qup-i2c4-default { 3937e5813b15SDmitry Baryshkov mux { 3938e5813b15SDmitry Baryshkov pins = "gpio8", "gpio9"; 3939e5813b15SDmitry Baryshkov function = "qup4"; 3940e5813b15SDmitry Baryshkov }; 3941e5813b15SDmitry Baryshkov 3942e5813b15SDmitry Baryshkov config { 3943e5813b15SDmitry Baryshkov pins = "gpio8", "gpio9"; 3944e5813b15SDmitry Baryshkov drive-strength = <2>; 3945e5813b15SDmitry Baryshkov bias-disable; 3946e5813b15SDmitry Baryshkov }; 3947e5813b15SDmitry Baryshkov }; 3948e5813b15SDmitry Baryshkov 3949e5813b15SDmitry Baryshkov qup_i2c5_default: qup-i2c5-default { 3950e5813b15SDmitry Baryshkov mux { 3951e5813b15SDmitry Baryshkov pins = "gpio12", "gpio13"; 3952e5813b15SDmitry Baryshkov function = "qup5"; 3953e5813b15SDmitry Baryshkov }; 3954e5813b15SDmitry Baryshkov 3955e5813b15SDmitry Baryshkov config { 3956e5813b15SDmitry Baryshkov pins = "gpio12", "gpio13"; 3957e5813b15SDmitry Baryshkov drive-strength = <2>; 3958e5813b15SDmitry Baryshkov bias-disable; 3959e5813b15SDmitry Baryshkov }; 3960e5813b15SDmitry Baryshkov }; 3961e5813b15SDmitry Baryshkov 3962e5813b15SDmitry Baryshkov qup_i2c6_default: qup-i2c6-default { 3963e5813b15SDmitry Baryshkov mux { 3964e5813b15SDmitry Baryshkov pins = "gpio16", "gpio17"; 3965e5813b15SDmitry Baryshkov function = "qup6"; 3966e5813b15SDmitry Baryshkov }; 3967e5813b15SDmitry Baryshkov 3968e5813b15SDmitry Baryshkov config { 3969e5813b15SDmitry Baryshkov pins = "gpio16", "gpio17"; 3970e5813b15SDmitry Baryshkov drive-strength = <2>; 3971e5813b15SDmitry Baryshkov bias-disable; 3972e5813b15SDmitry Baryshkov }; 3973e5813b15SDmitry Baryshkov }; 3974e5813b15SDmitry Baryshkov 3975e5813b15SDmitry Baryshkov qup_i2c7_default: qup-i2c7-default { 3976e5813b15SDmitry Baryshkov mux { 3977e5813b15SDmitry Baryshkov pins = "gpio20", "gpio21"; 3978e5813b15SDmitry Baryshkov function = "qup7"; 3979e5813b15SDmitry Baryshkov }; 3980e5813b15SDmitry Baryshkov 3981e5813b15SDmitry Baryshkov config { 3982e5813b15SDmitry Baryshkov pins = "gpio20", "gpio21"; 3983e5813b15SDmitry Baryshkov drive-strength = <2>; 3984e5813b15SDmitry Baryshkov bias-disable; 3985e5813b15SDmitry Baryshkov }; 3986e5813b15SDmitry Baryshkov }; 3987e5813b15SDmitry Baryshkov 3988e5813b15SDmitry Baryshkov qup_i2c8_default: qup-i2c8-default { 3989e5813b15SDmitry Baryshkov mux { 3990e5813b15SDmitry Baryshkov pins = "gpio24", "gpio25"; 3991e5813b15SDmitry Baryshkov function = "qup8"; 3992e5813b15SDmitry Baryshkov }; 3993e5813b15SDmitry Baryshkov 3994e5813b15SDmitry Baryshkov config { 3995e5813b15SDmitry Baryshkov pins = "gpio24", "gpio25"; 3996e5813b15SDmitry Baryshkov drive-strength = <2>; 3997e5813b15SDmitry Baryshkov bias-disable; 3998e5813b15SDmitry Baryshkov }; 3999e5813b15SDmitry Baryshkov }; 4000e5813b15SDmitry Baryshkov 4001e5813b15SDmitry Baryshkov qup_i2c9_default: qup-i2c9-default { 4002e5813b15SDmitry Baryshkov mux { 4003e5813b15SDmitry Baryshkov pins = "gpio125", "gpio126"; 4004e5813b15SDmitry Baryshkov function = "qup9"; 4005e5813b15SDmitry Baryshkov }; 4006e5813b15SDmitry Baryshkov 4007e5813b15SDmitry Baryshkov config { 4008e5813b15SDmitry Baryshkov pins = "gpio125", "gpio126"; 4009e5813b15SDmitry Baryshkov drive-strength = <2>; 4010e5813b15SDmitry Baryshkov bias-disable; 4011e5813b15SDmitry Baryshkov }; 4012e5813b15SDmitry Baryshkov }; 4013e5813b15SDmitry Baryshkov 4014e5813b15SDmitry Baryshkov qup_i2c10_default: qup-i2c10-default { 4015e5813b15SDmitry Baryshkov mux { 4016e5813b15SDmitry Baryshkov pins = "gpio129", "gpio130"; 4017e5813b15SDmitry Baryshkov function = "qup10"; 4018e5813b15SDmitry Baryshkov }; 4019e5813b15SDmitry Baryshkov 4020e5813b15SDmitry Baryshkov config { 4021e5813b15SDmitry Baryshkov pins = "gpio129", "gpio130"; 4022e5813b15SDmitry Baryshkov drive-strength = <2>; 4023e5813b15SDmitry Baryshkov bias-disable; 4024e5813b15SDmitry Baryshkov }; 4025e5813b15SDmitry Baryshkov }; 4026e5813b15SDmitry Baryshkov 4027e5813b15SDmitry Baryshkov qup_i2c11_default: qup-i2c11-default { 4028e5813b15SDmitry Baryshkov mux { 4029e5813b15SDmitry Baryshkov pins = "gpio60", "gpio61"; 4030e5813b15SDmitry Baryshkov function = "qup11"; 4031e5813b15SDmitry Baryshkov }; 4032e5813b15SDmitry Baryshkov 4033e5813b15SDmitry Baryshkov config { 4034e5813b15SDmitry Baryshkov pins = "gpio60", "gpio61"; 4035e5813b15SDmitry Baryshkov drive-strength = <2>; 4036e5813b15SDmitry Baryshkov bias-disable; 4037e5813b15SDmitry Baryshkov }; 4038e5813b15SDmitry Baryshkov }; 4039e5813b15SDmitry Baryshkov 4040e5813b15SDmitry Baryshkov qup_i2c12_default: qup-i2c12-default { 4041e5813b15SDmitry Baryshkov mux { 4042e5813b15SDmitry Baryshkov pins = "gpio32", "gpio33"; 4043e5813b15SDmitry Baryshkov function = "qup12"; 4044e5813b15SDmitry Baryshkov }; 4045e5813b15SDmitry Baryshkov 4046e5813b15SDmitry Baryshkov config { 4047e5813b15SDmitry Baryshkov pins = "gpio32", "gpio33"; 4048e5813b15SDmitry Baryshkov drive-strength = <2>; 4049e5813b15SDmitry Baryshkov bias-disable; 4050e5813b15SDmitry Baryshkov }; 4051e5813b15SDmitry Baryshkov }; 4052e5813b15SDmitry Baryshkov 4053e5813b15SDmitry Baryshkov qup_i2c13_default: qup-i2c13-default { 4054e5813b15SDmitry Baryshkov mux { 4055e5813b15SDmitry Baryshkov pins = "gpio36", "gpio37"; 4056e5813b15SDmitry Baryshkov function = "qup13"; 4057e5813b15SDmitry Baryshkov }; 4058e5813b15SDmitry Baryshkov 4059e5813b15SDmitry Baryshkov config { 4060e5813b15SDmitry Baryshkov pins = "gpio36", "gpio37"; 4061e5813b15SDmitry Baryshkov drive-strength = <2>; 4062e5813b15SDmitry Baryshkov bias-disable; 4063e5813b15SDmitry Baryshkov }; 4064e5813b15SDmitry Baryshkov }; 4065e5813b15SDmitry Baryshkov 4066e5813b15SDmitry Baryshkov qup_i2c14_default: qup-i2c14-default { 4067e5813b15SDmitry Baryshkov mux { 4068e5813b15SDmitry Baryshkov pins = "gpio40", "gpio41"; 4069e5813b15SDmitry Baryshkov function = "qup14"; 4070e5813b15SDmitry Baryshkov }; 4071e5813b15SDmitry Baryshkov 4072e5813b15SDmitry Baryshkov config { 4073e5813b15SDmitry Baryshkov pins = "gpio40", "gpio41"; 4074e5813b15SDmitry Baryshkov drive-strength = <2>; 4075e5813b15SDmitry Baryshkov bias-disable; 4076e5813b15SDmitry Baryshkov }; 4077e5813b15SDmitry Baryshkov }; 4078e5813b15SDmitry Baryshkov 4079e5813b15SDmitry Baryshkov qup_i2c15_default: qup-i2c15-default { 4080e5813b15SDmitry Baryshkov mux { 4081e5813b15SDmitry Baryshkov pins = "gpio44", "gpio45"; 4082e5813b15SDmitry Baryshkov function = "qup15"; 4083e5813b15SDmitry Baryshkov }; 4084e5813b15SDmitry Baryshkov 4085e5813b15SDmitry Baryshkov config { 4086e5813b15SDmitry Baryshkov pins = "gpio44", "gpio45"; 4087e5813b15SDmitry Baryshkov drive-strength = <2>; 4088e5813b15SDmitry Baryshkov bias-disable; 4089e5813b15SDmitry Baryshkov }; 4090e5813b15SDmitry Baryshkov }; 4091e5813b15SDmitry Baryshkov 4092e5813b15SDmitry Baryshkov qup_i2c16_default: qup-i2c16-default { 4093e5813b15SDmitry Baryshkov mux { 4094e5813b15SDmitry Baryshkov pins = "gpio48", "gpio49"; 4095e5813b15SDmitry Baryshkov function = "qup16"; 4096e5813b15SDmitry Baryshkov }; 4097e5813b15SDmitry Baryshkov 4098e5813b15SDmitry Baryshkov config { 4099e5813b15SDmitry Baryshkov pins = "gpio48", "gpio49"; 4100e5813b15SDmitry Baryshkov drive-strength = <2>; 4101e5813b15SDmitry Baryshkov bias-disable; 4102e5813b15SDmitry Baryshkov }; 4103e5813b15SDmitry Baryshkov }; 4104e5813b15SDmitry Baryshkov 4105e5813b15SDmitry Baryshkov qup_i2c17_default: qup-i2c17-default { 4106e5813b15SDmitry Baryshkov mux { 4107e5813b15SDmitry Baryshkov pins = "gpio52", "gpio53"; 4108e5813b15SDmitry Baryshkov function = "qup17"; 4109e5813b15SDmitry Baryshkov }; 4110e5813b15SDmitry Baryshkov 4111e5813b15SDmitry Baryshkov config { 4112e5813b15SDmitry Baryshkov pins = "gpio52", "gpio53"; 4113e5813b15SDmitry Baryshkov drive-strength = <2>; 4114e5813b15SDmitry Baryshkov bias-disable; 4115e5813b15SDmitry Baryshkov }; 4116e5813b15SDmitry Baryshkov }; 4117e5813b15SDmitry Baryshkov 4118e5813b15SDmitry Baryshkov qup_i2c18_default: qup-i2c18-default { 4119e5813b15SDmitry Baryshkov mux { 4120e5813b15SDmitry Baryshkov pins = "gpio56", "gpio57"; 4121e5813b15SDmitry Baryshkov function = "qup18"; 4122e5813b15SDmitry Baryshkov }; 4123e5813b15SDmitry Baryshkov 4124e5813b15SDmitry Baryshkov config { 4125e5813b15SDmitry Baryshkov pins = "gpio56", "gpio57"; 4126e5813b15SDmitry Baryshkov drive-strength = <2>; 4127e5813b15SDmitry Baryshkov bias-disable; 4128e5813b15SDmitry Baryshkov }; 4129e5813b15SDmitry Baryshkov }; 4130e5813b15SDmitry Baryshkov 4131e5813b15SDmitry Baryshkov qup_i2c19_default: qup-i2c19-default { 4132e5813b15SDmitry Baryshkov mux { 4133e5813b15SDmitry Baryshkov pins = "gpio0", "gpio1"; 4134e5813b15SDmitry Baryshkov function = "qup19"; 4135e5813b15SDmitry Baryshkov }; 4136e5813b15SDmitry Baryshkov 4137e5813b15SDmitry Baryshkov config { 4138e5813b15SDmitry Baryshkov pins = "gpio0", "gpio1"; 4139e5813b15SDmitry Baryshkov drive-strength = <2>; 4140e5813b15SDmitry Baryshkov bias-disable; 4141e5813b15SDmitry Baryshkov }; 4142e5813b15SDmitry Baryshkov }; 4143e5813b15SDmitry Baryshkov 4144c88f9eccSDmitry Baryshkov qup_spi0_cs: qup-spi0-cs { 4145c88f9eccSDmitry Baryshkov pins = "gpio31"; 4146e5813b15SDmitry Baryshkov function = "qup0"; 4147e5813b15SDmitry Baryshkov }; 4148e5813b15SDmitry Baryshkov 4149eb97ccbbSDmitry Baryshkov qup_spi0_cs_gpio: qup-spi0-cs-gpio { 4150eb97ccbbSDmitry Baryshkov pins = "gpio31"; 4151eb97ccbbSDmitry Baryshkov function = "gpio"; 4152eb97ccbbSDmitry Baryshkov }; 4153eb97ccbbSDmitry Baryshkov 4154c88f9eccSDmitry Baryshkov qup_spi0_data_clk: qup-spi0-data-clk { 4155c88f9eccSDmitry Baryshkov pins = "gpio28", "gpio29", 4156c88f9eccSDmitry Baryshkov "gpio30"; 4157c88f9eccSDmitry Baryshkov function = "qup0"; 4158c88f9eccSDmitry Baryshkov }; 4159c88f9eccSDmitry Baryshkov 4160c88f9eccSDmitry Baryshkov qup_spi1_cs: qup-spi1-cs { 4161c88f9eccSDmitry Baryshkov pins = "gpio7"; 4162e5813b15SDmitry Baryshkov function = "qup1"; 4163e5813b15SDmitry Baryshkov }; 4164e5813b15SDmitry Baryshkov 4165eb97ccbbSDmitry Baryshkov qup_spi1_cs_gpio: qup-spi1-cs-gpio { 4166eb97ccbbSDmitry Baryshkov pins = "gpio7"; 4167eb97ccbbSDmitry Baryshkov function = "gpio"; 4168eb97ccbbSDmitry Baryshkov }; 4169eb97ccbbSDmitry Baryshkov 4170c88f9eccSDmitry Baryshkov qup_spi1_data_clk: qup-spi1-data-clk { 4171c88f9eccSDmitry Baryshkov pins = "gpio4", "gpio5", 4172c88f9eccSDmitry Baryshkov "gpio6"; 4173c88f9eccSDmitry Baryshkov function = "qup1"; 4174c88f9eccSDmitry Baryshkov }; 4175c88f9eccSDmitry Baryshkov 4176c88f9eccSDmitry Baryshkov qup_spi2_cs: qup-spi2-cs { 4177c88f9eccSDmitry Baryshkov pins = "gpio118"; 4178e5813b15SDmitry Baryshkov function = "qup2"; 4179e5813b15SDmitry Baryshkov }; 4180e5813b15SDmitry Baryshkov 4181eb97ccbbSDmitry Baryshkov qup_spi2_cs_gpio: qup-spi2-cs-gpio { 4182eb97ccbbSDmitry Baryshkov pins = "gpio118"; 4183eb97ccbbSDmitry Baryshkov function = "gpio"; 4184eb97ccbbSDmitry Baryshkov }; 4185eb97ccbbSDmitry Baryshkov 4186c88f9eccSDmitry Baryshkov qup_spi2_data_clk: qup-spi2-data-clk { 4187c88f9eccSDmitry Baryshkov pins = "gpio115", "gpio116", 4188c88f9eccSDmitry Baryshkov "gpio117"; 4189c88f9eccSDmitry Baryshkov function = "qup2"; 4190c88f9eccSDmitry Baryshkov }; 4191c88f9eccSDmitry Baryshkov 4192c88f9eccSDmitry Baryshkov qup_spi3_cs: qup-spi3-cs { 4193c88f9eccSDmitry Baryshkov pins = "gpio122"; 4194e5813b15SDmitry Baryshkov function = "qup3"; 4195e5813b15SDmitry Baryshkov }; 4196e5813b15SDmitry Baryshkov 4197eb97ccbbSDmitry Baryshkov qup_spi3_cs_gpio: qup-spi3-cs-gpio { 4198eb97ccbbSDmitry Baryshkov pins = "gpio122"; 4199eb97ccbbSDmitry Baryshkov function = "gpio"; 4200eb97ccbbSDmitry Baryshkov }; 4201eb97ccbbSDmitry Baryshkov 4202c88f9eccSDmitry Baryshkov qup_spi3_data_clk: qup-spi3-data-clk { 4203c88f9eccSDmitry Baryshkov pins = "gpio119", "gpio120", 4204c88f9eccSDmitry Baryshkov "gpio121"; 4205c88f9eccSDmitry Baryshkov function = "qup3"; 4206c88f9eccSDmitry Baryshkov }; 4207c88f9eccSDmitry Baryshkov 4208c88f9eccSDmitry Baryshkov qup_spi4_cs: qup-spi4-cs { 4209c88f9eccSDmitry Baryshkov pins = "gpio11"; 4210e5813b15SDmitry Baryshkov function = "qup4"; 4211e5813b15SDmitry Baryshkov }; 4212e5813b15SDmitry Baryshkov 4213eb97ccbbSDmitry Baryshkov qup_spi4_cs_gpio: qup-spi4-cs-gpio { 4214eb97ccbbSDmitry Baryshkov pins = "gpio11"; 4215eb97ccbbSDmitry Baryshkov function = "gpio"; 4216eb97ccbbSDmitry Baryshkov }; 4217eb97ccbbSDmitry Baryshkov 4218c88f9eccSDmitry Baryshkov qup_spi4_data_clk: qup-spi4-data-clk { 4219c88f9eccSDmitry Baryshkov pins = "gpio8", "gpio9", 4220c88f9eccSDmitry Baryshkov "gpio10"; 4221c88f9eccSDmitry Baryshkov function = "qup4"; 4222c88f9eccSDmitry Baryshkov }; 4223c88f9eccSDmitry Baryshkov 4224c88f9eccSDmitry Baryshkov qup_spi5_cs: qup-spi5-cs { 4225c88f9eccSDmitry Baryshkov pins = "gpio15"; 4226e5813b15SDmitry Baryshkov function = "qup5"; 4227e5813b15SDmitry Baryshkov }; 4228e5813b15SDmitry Baryshkov 4229eb97ccbbSDmitry Baryshkov qup_spi5_cs_gpio: qup-spi5-cs-gpio { 4230eb97ccbbSDmitry Baryshkov pins = "gpio15"; 4231eb97ccbbSDmitry Baryshkov function = "gpio"; 4232eb97ccbbSDmitry Baryshkov }; 4233eb97ccbbSDmitry Baryshkov 4234c88f9eccSDmitry Baryshkov qup_spi5_data_clk: qup-spi5-data-clk { 4235c88f9eccSDmitry Baryshkov pins = "gpio12", "gpio13", 4236c88f9eccSDmitry Baryshkov "gpio14"; 4237c88f9eccSDmitry Baryshkov function = "qup5"; 4238c88f9eccSDmitry Baryshkov }; 4239c88f9eccSDmitry Baryshkov 4240c88f9eccSDmitry Baryshkov qup_spi6_cs: qup-spi6-cs { 4241c88f9eccSDmitry Baryshkov pins = "gpio19"; 4242e5813b15SDmitry Baryshkov function = "qup6"; 4243e5813b15SDmitry Baryshkov }; 4244e5813b15SDmitry Baryshkov 4245eb97ccbbSDmitry Baryshkov qup_spi6_cs_gpio: qup-spi6-cs-gpio { 4246eb97ccbbSDmitry Baryshkov pins = "gpio19"; 4247eb97ccbbSDmitry Baryshkov function = "gpio"; 4248eb97ccbbSDmitry Baryshkov }; 4249eb97ccbbSDmitry Baryshkov 4250c88f9eccSDmitry Baryshkov qup_spi6_data_clk: qup-spi6-data-clk { 4251c88f9eccSDmitry Baryshkov pins = "gpio16", "gpio17", 4252c88f9eccSDmitry Baryshkov "gpio18"; 4253c88f9eccSDmitry Baryshkov function = "qup6"; 4254c88f9eccSDmitry Baryshkov }; 4255c88f9eccSDmitry Baryshkov 4256c88f9eccSDmitry Baryshkov qup_spi7_cs: qup-spi7-cs { 4257c88f9eccSDmitry Baryshkov pins = "gpio23"; 4258e5813b15SDmitry Baryshkov function = "qup7"; 4259e5813b15SDmitry Baryshkov }; 4260e5813b15SDmitry Baryshkov 4261eb97ccbbSDmitry Baryshkov qup_spi7_cs_gpio: qup-spi7-cs-gpio { 4262eb97ccbbSDmitry Baryshkov pins = "gpio23"; 4263eb97ccbbSDmitry Baryshkov function = "gpio"; 4264eb97ccbbSDmitry Baryshkov }; 4265eb97ccbbSDmitry Baryshkov 4266c88f9eccSDmitry Baryshkov qup_spi7_data_clk: qup-spi7-data-clk { 4267c88f9eccSDmitry Baryshkov pins = "gpio20", "gpio21", 4268c88f9eccSDmitry Baryshkov "gpio22"; 4269c88f9eccSDmitry Baryshkov function = "qup7"; 4270c88f9eccSDmitry Baryshkov }; 4271c88f9eccSDmitry Baryshkov 4272c88f9eccSDmitry Baryshkov qup_spi8_cs: qup-spi8-cs { 4273c88f9eccSDmitry Baryshkov pins = "gpio27"; 4274e5813b15SDmitry Baryshkov function = "qup8"; 4275e5813b15SDmitry Baryshkov }; 4276e5813b15SDmitry Baryshkov 4277eb97ccbbSDmitry Baryshkov qup_spi8_cs_gpio: qup-spi8-cs-gpio { 4278eb97ccbbSDmitry Baryshkov pins = "gpio27"; 4279eb97ccbbSDmitry Baryshkov function = "gpio"; 4280eb97ccbbSDmitry Baryshkov }; 4281eb97ccbbSDmitry Baryshkov 4282c88f9eccSDmitry Baryshkov qup_spi8_data_clk: qup-spi8-data-clk { 4283c88f9eccSDmitry Baryshkov pins = "gpio24", "gpio25", 4284c88f9eccSDmitry Baryshkov "gpio26"; 4285c88f9eccSDmitry Baryshkov function = "qup8"; 4286c88f9eccSDmitry Baryshkov }; 4287c88f9eccSDmitry Baryshkov 4288c88f9eccSDmitry Baryshkov qup_spi9_cs: qup-spi9-cs { 4289c88f9eccSDmitry Baryshkov pins = "gpio128"; 4290e5813b15SDmitry Baryshkov function = "qup9"; 4291e5813b15SDmitry Baryshkov }; 4292e5813b15SDmitry Baryshkov 4293eb97ccbbSDmitry Baryshkov qup_spi9_cs_gpio: qup-spi9-cs-gpio { 4294eb97ccbbSDmitry Baryshkov pins = "gpio128"; 4295eb97ccbbSDmitry Baryshkov function = "gpio"; 4296eb97ccbbSDmitry Baryshkov }; 4297eb97ccbbSDmitry Baryshkov 4298c88f9eccSDmitry Baryshkov qup_spi9_data_clk: qup-spi9-data-clk { 4299c88f9eccSDmitry Baryshkov pins = "gpio125", "gpio126", 4300c88f9eccSDmitry Baryshkov "gpio127"; 4301c88f9eccSDmitry Baryshkov function = "qup9"; 4302c88f9eccSDmitry Baryshkov }; 4303c88f9eccSDmitry Baryshkov 4304c88f9eccSDmitry Baryshkov qup_spi10_cs: qup-spi10-cs { 4305c88f9eccSDmitry Baryshkov pins = "gpio132"; 4306e5813b15SDmitry Baryshkov function = "qup10"; 4307e5813b15SDmitry Baryshkov }; 4308e5813b15SDmitry Baryshkov 4309eb97ccbbSDmitry Baryshkov qup_spi10_cs_gpio: qup-spi10-cs-gpio { 4310eb97ccbbSDmitry Baryshkov pins = "gpio132"; 4311eb97ccbbSDmitry Baryshkov function = "gpio"; 4312eb97ccbbSDmitry Baryshkov }; 4313eb97ccbbSDmitry Baryshkov 4314c88f9eccSDmitry Baryshkov qup_spi10_data_clk: qup-spi10-data-clk { 4315c88f9eccSDmitry Baryshkov pins = "gpio129", "gpio130", 4316c88f9eccSDmitry Baryshkov "gpio131"; 4317c88f9eccSDmitry Baryshkov function = "qup10"; 4318c88f9eccSDmitry Baryshkov }; 4319c88f9eccSDmitry Baryshkov 4320c88f9eccSDmitry Baryshkov qup_spi11_cs: qup-spi11-cs { 4321c88f9eccSDmitry Baryshkov pins = "gpio63"; 4322e5813b15SDmitry Baryshkov function = "qup11"; 4323e5813b15SDmitry Baryshkov }; 4324e5813b15SDmitry Baryshkov 4325eb97ccbbSDmitry Baryshkov qup_spi11_cs_gpio: qup-spi11-cs-gpio { 4326eb97ccbbSDmitry Baryshkov pins = "gpio63"; 4327eb97ccbbSDmitry Baryshkov function = "gpio"; 4328eb97ccbbSDmitry Baryshkov }; 4329eb97ccbbSDmitry Baryshkov 4330c88f9eccSDmitry Baryshkov qup_spi11_data_clk: qup-spi11-data-clk { 4331c88f9eccSDmitry Baryshkov pins = "gpio60", "gpio61", 4332c88f9eccSDmitry Baryshkov "gpio62"; 4333c88f9eccSDmitry Baryshkov function = "qup11"; 4334c88f9eccSDmitry Baryshkov }; 4335c88f9eccSDmitry Baryshkov 4336c88f9eccSDmitry Baryshkov qup_spi12_cs: qup-spi12-cs { 4337c88f9eccSDmitry Baryshkov pins = "gpio35"; 4338e5813b15SDmitry Baryshkov function = "qup12"; 4339e5813b15SDmitry Baryshkov }; 4340e5813b15SDmitry Baryshkov 4341eb97ccbbSDmitry Baryshkov qup_spi12_cs_gpio: qup-spi12-cs-gpio { 4342eb97ccbbSDmitry Baryshkov pins = "gpio35"; 4343eb97ccbbSDmitry Baryshkov function = "gpio"; 4344eb97ccbbSDmitry Baryshkov }; 4345eb97ccbbSDmitry Baryshkov 4346c88f9eccSDmitry Baryshkov qup_spi12_data_clk: qup-spi12-data-clk { 4347c88f9eccSDmitry Baryshkov pins = "gpio32", "gpio33", 4348c88f9eccSDmitry Baryshkov "gpio34"; 4349c88f9eccSDmitry Baryshkov function = "qup12"; 4350c88f9eccSDmitry Baryshkov }; 4351c88f9eccSDmitry Baryshkov 4352c88f9eccSDmitry Baryshkov qup_spi13_cs: qup-spi13-cs { 4353c88f9eccSDmitry Baryshkov pins = "gpio39"; 4354e5813b15SDmitry Baryshkov function = "qup13"; 4355e5813b15SDmitry Baryshkov }; 4356e5813b15SDmitry Baryshkov 4357eb97ccbbSDmitry Baryshkov qup_spi13_cs_gpio: qup-spi13-cs-gpio { 4358eb97ccbbSDmitry Baryshkov pins = "gpio39"; 4359eb97ccbbSDmitry Baryshkov function = "gpio"; 4360eb97ccbbSDmitry Baryshkov }; 4361eb97ccbbSDmitry Baryshkov 4362c88f9eccSDmitry Baryshkov qup_spi13_data_clk: qup-spi13-data-clk { 4363c88f9eccSDmitry Baryshkov pins = "gpio36", "gpio37", 4364c88f9eccSDmitry Baryshkov "gpio38"; 4365c88f9eccSDmitry Baryshkov function = "qup13"; 4366c88f9eccSDmitry Baryshkov }; 4367c88f9eccSDmitry Baryshkov 4368c88f9eccSDmitry Baryshkov qup_spi14_cs: qup-spi14-cs { 4369c88f9eccSDmitry Baryshkov pins = "gpio43"; 4370e5813b15SDmitry Baryshkov function = "qup14"; 4371e5813b15SDmitry Baryshkov }; 4372e5813b15SDmitry Baryshkov 4373eb97ccbbSDmitry Baryshkov qup_spi14_cs_gpio: qup-spi14-cs-gpio { 4374eb97ccbbSDmitry Baryshkov pins = "gpio43"; 4375eb97ccbbSDmitry Baryshkov function = "gpio"; 4376eb97ccbbSDmitry Baryshkov }; 4377eb97ccbbSDmitry Baryshkov 4378c88f9eccSDmitry Baryshkov qup_spi14_data_clk: qup-spi14-data-clk { 4379c88f9eccSDmitry Baryshkov pins = "gpio40", "gpio41", 4380c88f9eccSDmitry Baryshkov "gpio42"; 4381c88f9eccSDmitry Baryshkov function = "qup14"; 4382c88f9eccSDmitry Baryshkov }; 4383c88f9eccSDmitry Baryshkov 4384c88f9eccSDmitry Baryshkov qup_spi15_cs: qup-spi15-cs { 4385c88f9eccSDmitry Baryshkov pins = "gpio47"; 4386e5813b15SDmitry Baryshkov function = "qup15"; 4387e5813b15SDmitry Baryshkov }; 4388e5813b15SDmitry Baryshkov 4389eb97ccbbSDmitry Baryshkov qup_spi15_cs_gpio: qup-spi15-cs-gpio { 4390eb97ccbbSDmitry Baryshkov pins = "gpio47"; 4391eb97ccbbSDmitry Baryshkov function = "gpio"; 4392eb97ccbbSDmitry Baryshkov }; 4393eb97ccbbSDmitry Baryshkov 4394c88f9eccSDmitry Baryshkov qup_spi15_data_clk: qup-spi15-data-clk { 4395c88f9eccSDmitry Baryshkov pins = "gpio44", "gpio45", 4396c88f9eccSDmitry Baryshkov "gpio46"; 4397c88f9eccSDmitry Baryshkov function = "qup15"; 4398c88f9eccSDmitry Baryshkov }; 4399c88f9eccSDmitry Baryshkov 4400c88f9eccSDmitry Baryshkov qup_spi16_cs: qup-spi16-cs { 4401c88f9eccSDmitry Baryshkov pins = "gpio51"; 4402e5813b15SDmitry Baryshkov function = "qup16"; 4403e5813b15SDmitry Baryshkov }; 4404e5813b15SDmitry Baryshkov 4405eb97ccbbSDmitry Baryshkov qup_spi16_cs_gpio: qup-spi16-cs-gpio { 4406eb97ccbbSDmitry Baryshkov pins = "gpio51"; 4407eb97ccbbSDmitry Baryshkov function = "gpio"; 4408eb97ccbbSDmitry Baryshkov }; 4409eb97ccbbSDmitry Baryshkov 4410c88f9eccSDmitry Baryshkov qup_spi16_data_clk: qup-spi16-data-clk { 4411c88f9eccSDmitry Baryshkov pins = "gpio48", "gpio49", 4412c88f9eccSDmitry Baryshkov "gpio50"; 4413c88f9eccSDmitry Baryshkov function = "qup16"; 4414c88f9eccSDmitry Baryshkov }; 4415c88f9eccSDmitry Baryshkov 4416c88f9eccSDmitry Baryshkov qup_spi17_cs: qup-spi17-cs { 4417c88f9eccSDmitry Baryshkov pins = "gpio55"; 4418e5813b15SDmitry Baryshkov function = "qup17"; 4419e5813b15SDmitry Baryshkov }; 4420e5813b15SDmitry Baryshkov 4421eb97ccbbSDmitry Baryshkov qup_spi17_cs_gpio: qup-spi17-cs-gpio { 4422eb97ccbbSDmitry Baryshkov pins = "gpio55"; 4423eb97ccbbSDmitry Baryshkov function = "gpio"; 4424eb97ccbbSDmitry Baryshkov }; 4425eb97ccbbSDmitry Baryshkov 4426c88f9eccSDmitry Baryshkov qup_spi17_data_clk: qup-spi17-data-clk { 4427c88f9eccSDmitry Baryshkov pins = "gpio52", "gpio53", 4428c88f9eccSDmitry Baryshkov "gpio54"; 4429c88f9eccSDmitry Baryshkov function = "qup17"; 4430c88f9eccSDmitry Baryshkov }; 4431c88f9eccSDmitry Baryshkov 4432c88f9eccSDmitry Baryshkov qup_spi18_cs: qup-spi18-cs { 4433c88f9eccSDmitry Baryshkov pins = "gpio59"; 4434e5813b15SDmitry Baryshkov function = "qup18"; 4435e5813b15SDmitry Baryshkov }; 4436e5813b15SDmitry Baryshkov 4437eb97ccbbSDmitry Baryshkov qup_spi18_cs_gpio: qup-spi18-cs-gpio { 4438eb97ccbbSDmitry Baryshkov pins = "gpio59"; 4439eb97ccbbSDmitry Baryshkov function = "gpio"; 4440eb97ccbbSDmitry Baryshkov }; 4441eb97ccbbSDmitry Baryshkov 4442c88f9eccSDmitry Baryshkov qup_spi18_data_clk: qup-spi18-data-clk { 4443c88f9eccSDmitry Baryshkov pins = "gpio56", "gpio57", 4444c88f9eccSDmitry Baryshkov "gpio58"; 4445c88f9eccSDmitry Baryshkov function = "qup18"; 4446c88f9eccSDmitry Baryshkov }; 4447c88f9eccSDmitry Baryshkov 4448c88f9eccSDmitry Baryshkov qup_spi19_cs: qup-spi19-cs { 4449c88f9eccSDmitry Baryshkov pins = "gpio3"; 4450c88f9eccSDmitry Baryshkov function = "qup19"; 4451c88f9eccSDmitry Baryshkov }; 4452c88f9eccSDmitry Baryshkov 4453eb97ccbbSDmitry Baryshkov qup_spi19_cs_gpio: qup-spi19-cs-gpio { 4454eb97ccbbSDmitry Baryshkov pins = "gpio3"; 4455eb97ccbbSDmitry Baryshkov function = "gpio"; 4456eb97ccbbSDmitry Baryshkov }; 4457eb97ccbbSDmitry Baryshkov 4458c88f9eccSDmitry Baryshkov qup_spi19_data_clk: qup-spi19-data-clk { 4459e5813b15SDmitry Baryshkov pins = "gpio0", "gpio1", 4460c88f9eccSDmitry Baryshkov "gpio2"; 4461e5813b15SDmitry Baryshkov function = "qup19"; 4462e5813b15SDmitry Baryshkov }; 4463e5813b15SDmitry Baryshkov 446408a9ae2dSDmitry Baryshkov qup_uart2_default: qup-uart2-default { 446508a9ae2dSDmitry Baryshkov mux { 446608a9ae2dSDmitry Baryshkov pins = "gpio117", "gpio118"; 446708a9ae2dSDmitry Baryshkov function = "qup2"; 446808a9ae2dSDmitry Baryshkov }; 446908a9ae2dSDmitry Baryshkov }; 447008a9ae2dSDmitry Baryshkov 447108a9ae2dSDmitry Baryshkov qup_uart6_default: qup-uart6-default { 447208a9ae2dSDmitry Baryshkov mux { 447308a9ae2dSDmitry Baryshkov pins = "gpio16", "gpio17", 447408a9ae2dSDmitry Baryshkov "gpio18", "gpio19"; 447508a9ae2dSDmitry Baryshkov function = "qup6"; 447608a9ae2dSDmitry Baryshkov }; 447708a9ae2dSDmitry Baryshkov }; 447808a9ae2dSDmitry Baryshkov 4479bb1dfb4dSManivannan Sadhasivam qup_uart12_default: qup-uart12-default { 4480bb1dfb4dSManivannan Sadhasivam mux { 4481bb1dfb4dSManivannan Sadhasivam pins = "gpio34", "gpio35"; 4482bb1dfb4dSManivannan Sadhasivam function = "qup12"; 4483bb1dfb4dSManivannan Sadhasivam }; 4484bb1dfb4dSManivannan Sadhasivam }; 448508a9ae2dSDmitry Baryshkov 448608a9ae2dSDmitry Baryshkov qup_uart17_default: qup-uart17-default { 448708a9ae2dSDmitry Baryshkov mux { 448808a9ae2dSDmitry Baryshkov pins = "gpio52", "gpio53", 448908a9ae2dSDmitry Baryshkov "gpio54", "gpio55"; 449008a9ae2dSDmitry Baryshkov function = "qup17"; 449108a9ae2dSDmitry Baryshkov }; 449208a9ae2dSDmitry Baryshkov }; 449308a9ae2dSDmitry Baryshkov 449408a9ae2dSDmitry Baryshkov qup_uart18_default: qup-uart18-default { 449508a9ae2dSDmitry Baryshkov mux { 449608a9ae2dSDmitry Baryshkov pins = "gpio58", "gpio59"; 449708a9ae2dSDmitry Baryshkov function = "qup18"; 449808a9ae2dSDmitry Baryshkov }; 449908a9ae2dSDmitry Baryshkov }; 4500b657d372SSrinivas Kandagatla 4501b657d372SSrinivas Kandagatla tert_mi2s_active: tert-mi2s-active { 4502b657d372SSrinivas Kandagatla sck { 4503b657d372SSrinivas Kandagatla pins = "gpio133"; 4504b657d372SSrinivas Kandagatla function = "mi2s2_sck"; 4505b657d372SSrinivas Kandagatla drive-strength = <8>; 4506b657d372SSrinivas Kandagatla bias-disable; 4507b657d372SSrinivas Kandagatla }; 4508b657d372SSrinivas Kandagatla 4509b657d372SSrinivas Kandagatla data0 { 4510b657d372SSrinivas Kandagatla pins = "gpio134"; 4511b657d372SSrinivas Kandagatla function = "mi2s2_data0"; 4512b657d372SSrinivas Kandagatla drive-strength = <8>; 4513b657d372SSrinivas Kandagatla bias-disable; 4514b657d372SSrinivas Kandagatla output-high; 4515b657d372SSrinivas Kandagatla }; 4516b657d372SSrinivas Kandagatla 4517b657d372SSrinivas Kandagatla ws { 4518b657d372SSrinivas Kandagatla pins = "gpio135"; 4519b657d372SSrinivas Kandagatla function = "mi2s2_ws"; 4520b657d372SSrinivas Kandagatla drive-strength = <8>; 4521b657d372SSrinivas Kandagatla output-high; 4522b657d372SSrinivas Kandagatla }; 4523b657d372SSrinivas Kandagatla }; 45248eaa6501SKonrad Dybcio 45258eaa6501SKonrad Dybcio sdc2_sleep_state: sdc2-sleep { 45268eaa6501SKonrad Dybcio clk { 45278eaa6501SKonrad Dybcio pins = "sdc2_clk"; 45288eaa6501SKonrad Dybcio drive-strength = <2>; 45298eaa6501SKonrad Dybcio bias-disable; 45308eaa6501SKonrad Dybcio }; 45318eaa6501SKonrad Dybcio 45328eaa6501SKonrad Dybcio cmd { 45338eaa6501SKonrad Dybcio pins = "sdc2_cmd"; 45348eaa6501SKonrad Dybcio drive-strength = <2>; 45358eaa6501SKonrad Dybcio bias-pull-up; 45368eaa6501SKonrad Dybcio }; 45378eaa6501SKonrad Dybcio 45388eaa6501SKonrad Dybcio data { 45398eaa6501SKonrad Dybcio pins = "sdc2_data"; 45408eaa6501SKonrad Dybcio drive-strength = <2>; 45418eaa6501SKonrad Dybcio bias-pull-up; 45428eaa6501SKonrad Dybcio }; 45438eaa6501SKonrad Dybcio }; 454413e948a3SKonrad Dybcio 454513e948a3SKonrad Dybcio pcie0_default_state: pcie0-default { 454613e948a3SKonrad Dybcio perst { 454713e948a3SKonrad Dybcio pins = "gpio79"; 454813e948a3SKonrad Dybcio function = "gpio"; 454913e948a3SKonrad Dybcio drive-strength = <2>; 455013e948a3SKonrad Dybcio bias-pull-down; 455113e948a3SKonrad Dybcio }; 455213e948a3SKonrad Dybcio 455313e948a3SKonrad Dybcio clkreq { 455413e948a3SKonrad Dybcio pins = "gpio80"; 455513e948a3SKonrad Dybcio function = "pci_e0"; 455613e948a3SKonrad Dybcio drive-strength = <2>; 455713e948a3SKonrad Dybcio bias-pull-up; 455813e948a3SKonrad Dybcio }; 455913e948a3SKonrad Dybcio 456013e948a3SKonrad Dybcio wake { 456113e948a3SKonrad Dybcio pins = "gpio81"; 456213e948a3SKonrad Dybcio function = "gpio"; 456313e948a3SKonrad Dybcio drive-strength = <2>; 456413e948a3SKonrad Dybcio bias-pull-up; 456513e948a3SKonrad Dybcio }; 456613e948a3SKonrad Dybcio }; 456713e948a3SKonrad Dybcio 456813e948a3SKonrad Dybcio pcie1_default_state: pcie1-default { 456913e948a3SKonrad Dybcio perst { 457013e948a3SKonrad Dybcio pins = "gpio82"; 457113e948a3SKonrad Dybcio function = "gpio"; 457213e948a3SKonrad Dybcio drive-strength = <2>; 457313e948a3SKonrad Dybcio bias-pull-down; 457413e948a3SKonrad Dybcio }; 457513e948a3SKonrad Dybcio 457613e948a3SKonrad Dybcio clkreq { 457713e948a3SKonrad Dybcio pins = "gpio83"; 457813e948a3SKonrad Dybcio function = "pci_e1"; 457913e948a3SKonrad Dybcio drive-strength = <2>; 458013e948a3SKonrad Dybcio bias-pull-up; 458113e948a3SKonrad Dybcio }; 458213e948a3SKonrad Dybcio 458313e948a3SKonrad Dybcio wake { 458413e948a3SKonrad Dybcio pins = "gpio84"; 458513e948a3SKonrad Dybcio function = "gpio"; 458613e948a3SKonrad Dybcio drive-strength = <2>; 458713e948a3SKonrad Dybcio bias-pull-up; 458813e948a3SKonrad Dybcio }; 458913e948a3SKonrad Dybcio }; 459013e948a3SKonrad Dybcio 459113e948a3SKonrad Dybcio pcie2_default_state: pcie2-default { 459213e948a3SKonrad Dybcio perst { 459313e948a3SKonrad Dybcio pins = "gpio85"; 459413e948a3SKonrad Dybcio function = "gpio"; 459513e948a3SKonrad Dybcio drive-strength = <2>; 459613e948a3SKonrad Dybcio bias-pull-down; 459713e948a3SKonrad Dybcio }; 459813e948a3SKonrad Dybcio 459913e948a3SKonrad Dybcio clkreq { 460013e948a3SKonrad Dybcio pins = "gpio86"; 460113e948a3SKonrad Dybcio function = "pci_e2"; 460213e948a3SKonrad Dybcio drive-strength = <2>; 460313e948a3SKonrad Dybcio bias-pull-up; 460413e948a3SKonrad Dybcio }; 460513e948a3SKonrad Dybcio 460613e948a3SKonrad Dybcio wake { 460713e948a3SKonrad Dybcio pins = "gpio87"; 460813e948a3SKonrad Dybcio function = "gpio"; 460913e948a3SKonrad Dybcio drive-strength = <2>; 461013e948a3SKonrad Dybcio bias-pull-up; 461113e948a3SKonrad Dybcio }; 461213e948a3SKonrad Dybcio }; 461316951b49SBjorn Andersson }; 461416951b49SBjorn Andersson 4615a89441fcSJonathan Marek apps_smmu: iommu@15000000 { 4616a89441fcSJonathan Marek compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 4617a89441fcSJonathan Marek reg = <0 0x15000000 0 0x100000>; 4618a89441fcSJonathan Marek #iommu-cells = <2>; 4619a89441fcSJonathan Marek #global-interrupts = <2>; 4620a89441fcSJonathan Marek interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 4621a89441fcSJonathan Marek <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4622a89441fcSJonathan Marek <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4623a89441fcSJonathan Marek <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4624a89441fcSJonathan Marek <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4625a89441fcSJonathan Marek <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4626a89441fcSJonathan Marek <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4627a89441fcSJonathan Marek <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4628a89441fcSJonathan Marek <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4629a89441fcSJonathan Marek <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4630a89441fcSJonathan Marek <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4631a89441fcSJonathan Marek <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4632a89441fcSJonathan Marek <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4633a89441fcSJonathan Marek <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4634a89441fcSJonathan Marek <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4635a89441fcSJonathan Marek <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4636a89441fcSJonathan Marek <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4637a89441fcSJonathan Marek <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4638a89441fcSJonathan Marek <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4639a89441fcSJonathan Marek <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4640a89441fcSJonathan Marek <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4641a89441fcSJonathan Marek <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4642a89441fcSJonathan Marek <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4643a89441fcSJonathan Marek <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4644a89441fcSJonathan Marek <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4645a89441fcSJonathan Marek <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4646a89441fcSJonathan Marek <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4647a89441fcSJonathan Marek <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4648a89441fcSJonathan Marek <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4649a89441fcSJonathan Marek <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4650a89441fcSJonathan Marek <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4651a89441fcSJonathan Marek <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4652a89441fcSJonathan Marek <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4653a89441fcSJonathan Marek <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4654a89441fcSJonathan Marek <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4655a89441fcSJonathan Marek <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4656a89441fcSJonathan Marek <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4657a89441fcSJonathan Marek <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4658a89441fcSJonathan Marek <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4659a89441fcSJonathan Marek <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4660a89441fcSJonathan Marek <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4661a89441fcSJonathan Marek <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4662a89441fcSJonathan Marek <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4663a89441fcSJonathan Marek <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4664a89441fcSJonathan Marek <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4665a89441fcSJonathan Marek <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4666a89441fcSJonathan Marek <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4667a89441fcSJonathan Marek <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4668a89441fcSJonathan Marek <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4669a89441fcSJonathan Marek <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4670a89441fcSJonathan Marek <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4671a89441fcSJonathan Marek <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4672a89441fcSJonathan Marek <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4673a89441fcSJonathan Marek <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4674a89441fcSJonathan Marek <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4675a89441fcSJonathan Marek <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4676a89441fcSJonathan Marek <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4677a89441fcSJonathan Marek <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4678a89441fcSJonathan Marek <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4679a89441fcSJonathan Marek <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4680a89441fcSJonathan Marek <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4681a89441fcSJonathan Marek <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4682a89441fcSJonathan Marek <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4683a89441fcSJonathan Marek <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4684a89441fcSJonathan Marek <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4685a89441fcSJonathan Marek <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4686a89441fcSJonathan Marek <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4687a89441fcSJonathan Marek <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4688a89441fcSJonathan Marek <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4689a89441fcSJonathan Marek <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4690a89441fcSJonathan Marek <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4691a89441fcSJonathan Marek <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4692a89441fcSJonathan Marek <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4693a89441fcSJonathan Marek <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4694a89441fcSJonathan Marek <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4695a89441fcSJonathan Marek <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4696a89441fcSJonathan Marek <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4697a89441fcSJonathan Marek <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4698a89441fcSJonathan Marek <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4699a89441fcSJonathan Marek <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4700a89441fcSJonathan Marek <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4701a89441fcSJonathan Marek <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4702a89441fcSJonathan Marek <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4703a89441fcSJonathan Marek <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4704a89441fcSJonathan Marek <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4705a89441fcSJonathan Marek <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4706a89441fcSJonathan Marek <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4707a89441fcSJonathan Marek <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4708a89441fcSJonathan Marek <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4709a89441fcSJonathan Marek <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4710a89441fcSJonathan Marek <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4711a89441fcSJonathan Marek <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4712a89441fcSJonathan Marek <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4713a89441fcSJonathan Marek <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4714a89441fcSJonathan Marek <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4715a89441fcSJonathan Marek <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4716a89441fcSJonathan Marek <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 4717a89441fcSJonathan Marek <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 4718a89441fcSJonathan Marek }; 4719a89441fcSJonathan Marek 472023a89037SBjorn Andersson adsp: remoteproc@17300000 { 472123a89037SBjorn Andersson compatible = "qcom,sm8250-adsp-pas"; 472223a89037SBjorn Andersson reg = <0 0x17300000 0 0x100>; 472323a89037SBjorn Andersson 472423a89037SBjorn Andersson interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 472523a89037SBjorn Andersson <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 472623a89037SBjorn Andersson <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 472723a89037SBjorn Andersson <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 472823a89037SBjorn Andersson <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 472923a89037SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 473023a89037SBjorn Andersson "handover", "stop-ack"; 473123a89037SBjorn Andersson 473223a89037SBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>; 473323a89037SBjorn Andersson clock-names = "xo"; 473423a89037SBjorn Andersson 4735b74ee2d7SSibi Sankar power-domains = <&rpmhpd SM8250_LCX>, 473623a89037SBjorn Andersson <&rpmhpd SM8250_LMX>; 4737b74ee2d7SSibi Sankar power-domain-names = "lcx", "lmx"; 473823a89037SBjorn Andersson 473923a89037SBjorn Andersson memory-region = <&adsp_mem>; 474023a89037SBjorn Andersson 4741b74ee2d7SSibi Sankar qcom,qmp = <&aoss_qmp>; 4742b74ee2d7SSibi Sankar 474323a89037SBjorn Andersson qcom,smem-states = <&smp2p_adsp_out 0>; 474423a89037SBjorn Andersson qcom,smem-state-names = "stop"; 474523a89037SBjorn Andersson 474623a89037SBjorn Andersson status = "disabled"; 474723a89037SBjorn Andersson 474823a89037SBjorn Andersson glink-edge { 474923a89037SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 475023a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 475123a89037SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 475223a89037SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_LPASS 475323a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 475423a89037SBjorn Andersson 475523a89037SBjorn Andersson label = "lpass"; 475623a89037SBjorn Andersson qcom,remote-pid = <2>; 475725695808SJonathan Marek 475863e10791SSrinivas Kandagatla apr { 475963e10791SSrinivas Kandagatla compatible = "qcom,apr-v2"; 476063e10791SSrinivas Kandagatla qcom,glink-channels = "apr_audio_svc"; 47612f114511SDavid Heidelberg qcom,domain = <APR_DOMAIN_ADSP>; 476263e10791SSrinivas Kandagatla #address-cells = <1>; 476363e10791SSrinivas Kandagatla #size-cells = <0>; 476463e10791SSrinivas Kandagatla 476563e10791SSrinivas Kandagatla apr-service@3 { 476663e10791SSrinivas Kandagatla reg = <APR_SVC_ADSP_CORE>; 476763e10791SSrinivas Kandagatla compatible = "qcom,q6core"; 476863e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 476963e10791SSrinivas Kandagatla }; 477063e10791SSrinivas Kandagatla 477163e10791SSrinivas Kandagatla q6afe: apr-service@4 { 477263e10791SSrinivas Kandagatla compatible = "qcom,q6afe"; 477363e10791SSrinivas Kandagatla reg = <APR_SVC_AFE>; 477463e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 477563e10791SSrinivas Kandagatla q6afedai: dais { 477663e10791SSrinivas Kandagatla compatible = "qcom,q6afe-dais"; 477763e10791SSrinivas Kandagatla #address-cells = <1>; 477863e10791SSrinivas Kandagatla #size-cells = <0>; 477963e10791SSrinivas Kandagatla #sound-dai-cells = <1>; 478063e10791SSrinivas Kandagatla }; 478163e10791SSrinivas Kandagatla 478263e10791SSrinivas Kandagatla q6afecc: cc { 478363e10791SSrinivas Kandagatla compatible = "qcom,q6afe-clocks"; 478463e10791SSrinivas Kandagatla #clock-cells = <2>; 478563e10791SSrinivas Kandagatla }; 478663e10791SSrinivas Kandagatla }; 478763e10791SSrinivas Kandagatla 478863e10791SSrinivas Kandagatla q6asm: apr-service@7 { 478963e10791SSrinivas Kandagatla compatible = "qcom,q6asm"; 479063e10791SSrinivas Kandagatla reg = <APR_SVC_ASM>; 479163e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 479263e10791SSrinivas Kandagatla q6asmdai: dais { 479363e10791SSrinivas Kandagatla compatible = "qcom,q6asm-dais"; 479463e10791SSrinivas Kandagatla #address-cells = <1>; 479563e10791SSrinivas Kandagatla #size-cells = <0>; 479663e10791SSrinivas Kandagatla #sound-dai-cells = <1>; 479763e10791SSrinivas Kandagatla iommus = <&apps_smmu 0x1801 0x0>; 479863e10791SSrinivas Kandagatla }; 479963e10791SSrinivas Kandagatla }; 480063e10791SSrinivas Kandagatla 480163e10791SSrinivas Kandagatla q6adm: apr-service@8 { 480263e10791SSrinivas Kandagatla compatible = "qcom,q6adm"; 480363e10791SSrinivas Kandagatla reg = <APR_SVC_ADM>; 480463e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 480563e10791SSrinivas Kandagatla q6routing: routing { 480663e10791SSrinivas Kandagatla compatible = "qcom,q6adm-routing"; 480763e10791SSrinivas Kandagatla #sound-dai-cells = <0>; 480863e10791SSrinivas Kandagatla }; 480963e10791SSrinivas Kandagatla }; 481063e10791SSrinivas Kandagatla }; 481163e10791SSrinivas Kandagatla 481225695808SJonathan Marek fastrpc { 481325695808SJonathan Marek compatible = "qcom,fastrpc"; 481425695808SJonathan Marek qcom,glink-channels = "fastrpcglink-apps-dsp"; 481525695808SJonathan Marek label = "adsp"; 48168c8ce95bSJeya R qcom,non-secure-domain; 481725695808SJonathan Marek #address-cells = <1>; 481825695808SJonathan Marek #size-cells = <0>; 481925695808SJonathan Marek 482025695808SJonathan Marek compute-cb@3 { 482125695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 482225695808SJonathan Marek reg = <3>; 482325695808SJonathan Marek iommus = <&apps_smmu 0x1803 0x0>; 482425695808SJonathan Marek }; 482525695808SJonathan Marek 482625695808SJonathan Marek compute-cb@4 { 482725695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 482825695808SJonathan Marek reg = <4>; 482925695808SJonathan Marek iommus = <&apps_smmu 0x1804 0x0>; 483025695808SJonathan Marek }; 483125695808SJonathan Marek 483225695808SJonathan Marek compute-cb@5 { 483325695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 483425695808SJonathan Marek reg = <5>; 483525695808SJonathan Marek iommus = <&apps_smmu 0x1805 0x0>; 483625695808SJonathan Marek }; 483725695808SJonathan Marek }; 483823a89037SBjorn Andersson }; 483923a89037SBjorn Andersson }; 484023a89037SBjorn Andersson 4841b9ec8cbcSJonathan Marek intc: interrupt-controller@17a00000 { 4842b9ec8cbcSJonathan Marek compatible = "arm,gic-v3"; 4843b9ec8cbcSJonathan Marek #interrupt-cells = <3>; 4844b9ec8cbcSJonathan Marek interrupt-controller; 4845b9ec8cbcSJonathan Marek reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4846b9ec8cbcSJonathan Marek <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4847b9ec8cbcSJonathan Marek interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4848b9ec8cbcSJonathan Marek }; 4849b9ec8cbcSJonathan Marek 4850e0d9acceSDmitry Baryshkov watchdog@17c10000 { 4851e0d9acceSDmitry Baryshkov compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 4852e0d9acceSDmitry Baryshkov reg = <0 0x17c10000 0 0x1000>; 4853e0d9acceSDmitry Baryshkov clocks = <&sleep_clk>; 485446a4359fSSai Prakash Ranjan interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4855e0d9acceSDmitry Baryshkov }; 4856e0d9acceSDmitry Baryshkov 4857b9ec8cbcSJonathan Marek timer@17c20000 { 4858b9ec8cbcSJonathan Marek #address-cells = <2>; 4859b9ec8cbcSJonathan Marek #size-cells = <2>; 4860b9ec8cbcSJonathan Marek ranges; 4861b9ec8cbcSJonathan Marek compatible = "arm,armv7-timer-mem"; 4862b9ec8cbcSJonathan Marek reg = <0x0 0x17c20000 0x0 0x1000>; 4863b9ec8cbcSJonathan Marek clock-frequency = <19200000>; 4864b9ec8cbcSJonathan Marek 4865b9ec8cbcSJonathan Marek frame@17c21000 { 4866b9ec8cbcSJonathan Marek frame-number = <0>; 4867b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4868b9ec8cbcSJonathan Marek <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4869b9ec8cbcSJonathan Marek reg = <0x0 0x17c21000 0x0 0x1000>, 4870b9ec8cbcSJonathan Marek <0x0 0x17c22000 0x0 0x1000>; 4871b9ec8cbcSJonathan Marek }; 4872b9ec8cbcSJonathan Marek 4873b9ec8cbcSJonathan Marek frame@17c23000 { 4874b9ec8cbcSJonathan Marek frame-number = <1>; 4875b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4876b9ec8cbcSJonathan Marek reg = <0x0 0x17c23000 0x0 0x1000>; 4877b9ec8cbcSJonathan Marek status = "disabled"; 4878b9ec8cbcSJonathan Marek }; 4879b9ec8cbcSJonathan Marek 4880b9ec8cbcSJonathan Marek frame@17c25000 { 4881b9ec8cbcSJonathan Marek frame-number = <2>; 4882b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4883b9ec8cbcSJonathan Marek reg = <0x0 0x17c25000 0x0 0x1000>; 4884b9ec8cbcSJonathan Marek status = "disabled"; 4885b9ec8cbcSJonathan Marek }; 4886b9ec8cbcSJonathan Marek 4887b9ec8cbcSJonathan Marek frame@17c27000 { 4888b9ec8cbcSJonathan Marek frame-number = <3>; 4889b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4890b9ec8cbcSJonathan Marek reg = <0x0 0x17c27000 0x0 0x1000>; 4891b9ec8cbcSJonathan Marek status = "disabled"; 4892b9ec8cbcSJonathan Marek }; 4893b9ec8cbcSJonathan Marek 4894b9ec8cbcSJonathan Marek frame@17c29000 { 4895b9ec8cbcSJonathan Marek frame-number = <4>; 4896b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4897b9ec8cbcSJonathan Marek reg = <0x0 0x17c29000 0x0 0x1000>; 4898b9ec8cbcSJonathan Marek status = "disabled"; 4899b9ec8cbcSJonathan Marek }; 4900b9ec8cbcSJonathan Marek 4901b9ec8cbcSJonathan Marek frame@17c2b000 { 4902b9ec8cbcSJonathan Marek frame-number = <5>; 4903b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4904b9ec8cbcSJonathan Marek reg = <0x0 0x17c2b000 0x0 0x1000>; 4905b9ec8cbcSJonathan Marek status = "disabled"; 4906b9ec8cbcSJonathan Marek }; 4907b9ec8cbcSJonathan Marek 4908b9ec8cbcSJonathan Marek frame@17c2d000 { 4909b9ec8cbcSJonathan Marek frame-number = <6>; 4910b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4911b9ec8cbcSJonathan Marek reg = <0x0 0x17c2d000 0x0 0x1000>; 4912b9ec8cbcSJonathan Marek status = "disabled"; 4913b9ec8cbcSJonathan Marek }; 4914b9ec8cbcSJonathan Marek }; 4915b9ec8cbcSJonathan Marek 491660378f1aSVenkata Narendra Kumar Gutta apps_rsc: rsc@18200000 { 491760378f1aSVenkata Narendra Kumar Gutta label = "apps_rsc"; 491860378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,rpmh-rsc"; 491960378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x18200000 0x0 0x10000>, 492060378f1aSVenkata Narendra Kumar Gutta <0x0 0x18210000 0x0 0x10000>, 492160378f1aSVenkata Narendra Kumar Gutta <0x0 0x18220000 0x0 0x10000>; 492260378f1aSVenkata Narendra Kumar Gutta reg-names = "drv-0", "drv-1", "drv-2"; 492360378f1aSVenkata Narendra Kumar Gutta interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 492460378f1aSVenkata Narendra Kumar Gutta <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 492560378f1aSVenkata Narendra Kumar Gutta <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 492660378f1aSVenkata Narendra Kumar Gutta qcom,tcs-offset = <0xd00>; 492760378f1aSVenkata Narendra Kumar Gutta qcom,drv-id = <2>; 492860378f1aSVenkata Narendra Kumar Gutta qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 492960378f1aSVenkata Narendra Kumar Gutta <WAKE_TCS 3>, <CONTROL_TCS 1>; 493060378f1aSVenkata Narendra Kumar Gutta 493160378f1aSVenkata Narendra Kumar Gutta rpmhcc: clock-controller { 493260378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,sm8250-rpmh-clk"; 493360378f1aSVenkata Narendra Kumar Gutta #clock-cells = <1>; 493460378f1aSVenkata Narendra Kumar Gutta clock-names = "xo"; 493560378f1aSVenkata Narendra Kumar Gutta clocks = <&xo_board>; 493660378f1aSVenkata Narendra Kumar Gutta }; 4937b6f78e27SBjorn Andersson 4938b6f78e27SBjorn Andersson rpmhpd: power-controller { 4939b6f78e27SBjorn Andersson compatible = "qcom,sm8250-rpmhpd"; 4940b6f78e27SBjorn Andersson #power-domain-cells = <1>; 4941b6f78e27SBjorn Andersson operating-points-v2 = <&rpmhpd_opp_table>; 4942b6f78e27SBjorn Andersson 4943b6f78e27SBjorn Andersson rpmhpd_opp_table: opp-table { 4944b6f78e27SBjorn Andersson compatible = "operating-points-v2"; 4945b6f78e27SBjorn Andersson 4946b6f78e27SBjorn Andersson rpmhpd_opp_ret: opp1 { 4947b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4948b6f78e27SBjorn Andersson }; 4949b6f78e27SBjorn Andersson 4950b6f78e27SBjorn Andersson rpmhpd_opp_min_svs: opp2 { 4951b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4952b6f78e27SBjorn Andersson }; 4953b6f78e27SBjorn Andersson 4954b6f78e27SBjorn Andersson rpmhpd_opp_low_svs: opp3 { 4955b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4956b6f78e27SBjorn Andersson }; 4957b6f78e27SBjorn Andersson 4958b6f78e27SBjorn Andersson rpmhpd_opp_svs: opp4 { 4959b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4960b6f78e27SBjorn Andersson }; 4961b6f78e27SBjorn Andersson 4962b6f78e27SBjorn Andersson rpmhpd_opp_svs_l1: opp5 { 4963b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4964b6f78e27SBjorn Andersson }; 4965b6f78e27SBjorn Andersson 4966b6f78e27SBjorn Andersson rpmhpd_opp_nom: opp6 { 4967b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4968b6f78e27SBjorn Andersson }; 4969b6f78e27SBjorn Andersson 4970b6f78e27SBjorn Andersson rpmhpd_opp_nom_l1: opp7 { 4971b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4972b6f78e27SBjorn Andersson }; 4973b6f78e27SBjorn Andersson 4974b6f78e27SBjorn Andersson rpmhpd_opp_nom_l2: opp8 { 4975b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4976b6f78e27SBjorn Andersson }; 4977b6f78e27SBjorn Andersson 4978b6f78e27SBjorn Andersson rpmhpd_opp_turbo: opp9 { 4979b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4980b6f78e27SBjorn Andersson }; 4981b6f78e27SBjorn Andersson 4982b6f78e27SBjorn Andersson rpmhpd_opp_turbo_l1: opp10 { 4983b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4984b6f78e27SBjorn Andersson }; 4985b6f78e27SBjorn Andersson }; 4986b6f78e27SBjorn Andersson }; 4987e7e41a20SJonathan Marek 4988fc0e7dd6SKrzysztof Kozlowski apps_bcm_voter: bcm-voter { 4989e7e41a20SJonathan Marek compatible = "qcom,bcm-voter"; 4990e7e41a20SJonathan Marek }; 499160378f1aSVenkata Narendra Kumar Gutta }; 499279a595bbSSibi Sankar 499377b53d65SGeorgi Djakov epss_l3: interconnect@18590000 { 499479a595bbSSibi Sankar compatible = "qcom,sm8250-epss-l3"; 499579a595bbSSibi Sankar reg = <0 0x18590000 0 0x1000>; 499679a595bbSSibi Sankar 499779a595bbSSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 499879a595bbSSibi Sankar clock-names = "xo", "alternate"; 499979a595bbSSibi Sankar 500079a595bbSSibi Sankar #interconnect-cells = <1>; 500179a595bbSSibi Sankar }; 500202ae4a0eSBjorn Andersson 500302ae4a0eSBjorn Andersson cpufreq_hw: cpufreq@18591000 { 500402ae4a0eSBjorn Andersson compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 500502ae4a0eSBjorn Andersson reg = <0 0x18591000 0 0x1000>, 500602ae4a0eSBjorn Andersson <0 0x18592000 0 0x1000>, 500702ae4a0eSBjorn Andersson <0 0x18593000 0 0x1000>; 500802ae4a0eSBjorn Andersson reg-names = "freq-domain0", "freq-domain1", 500902ae4a0eSBjorn Andersson "freq-domain2"; 501002ae4a0eSBjorn Andersson 501102ae4a0eSBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 501202ae4a0eSBjorn Andersson clock-names = "xo", "alternate"; 5013ffd6cc92SVladimir Zapolskiy interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5014ffd6cc92SVladimir Zapolskiy <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5015ffd6cc92SVladimir Zapolskiy <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5016ffd6cc92SVladimir Zapolskiy interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 501702ae4a0eSBjorn Andersson #freq-domain-cells = <1>; 501802ae4a0eSBjorn Andersson }; 501960378f1aSVenkata Narendra Kumar Gutta }; 502060378f1aSVenkata Narendra Kumar Gutta 502160378f1aSVenkata Narendra Kumar Gutta timer { 502260378f1aSVenkata Narendra Kumar Gutta compatible = "arm,armv8-timer"; 502360378f1aSVenkata Narendra Kumar Gutta interrupts = <GIC_PPI 13 502460378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 502560378f1aSVenkata Narendra Kumar Gutta <GIC_PPI 14 502660378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 502760378f1aSVenkata Narendra Kumar Gutta <GIC_PPI 11 502860378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 502929a33495SSai Prakash Ranjan <GIC_PPI 10 503060378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 503160378f1aSVenkata Narendra Kumar Gutta }; 5032bac12f25SAmit Kucheria 5033bac12f25SAmit Kucheria thermal-zones { 5034bac12f25SAmit Kucheria cpu0-thermal { 5035bac12f25SAmit Kucheria polling-delay-passive = <250>; 5036bac12f25SAmit Kucheria polling-delay = <1000>; 5037bac12f25SAmit Kucheria 5038bac12f25SAmit Kucheria thermal-sensors = <&tsens0 1>; 5039bac12f25SAmit Kucheria 5040bac12f25SAmit Kucheria trips { 5041bac12f25SAmit Kucheria cpu0_alert0: trip-point0 { 5042bac12f25SAmit Kucheria temperature = <90000>; 5043bac12f25SAmit Kucheria hysteresis = <2000>; 5044bac12f25SAmit Kucheria type = "passive"; 5045bac12f25SAmit Kucheria }; 5046bac12f25SAmit Kucheria 5047bac12f25SAmit Kucheria cpu0_alert1: trip-point1 { 5048bac12f25SAmit Kucheria temperature = <95000>; 5049bac12f25SAmit Kucheria hysteresis = <2000>; 5050bac12f25SAmit Kucheria type = "passive"; 5051bac12f25SAmit Kucheria }; 5052bac12f25SAmit Kucheria 5053bac12f25SAmit Kucheria cpu0_crit: cpu_crit { 5054bac12f25SAmit Kucheria temperature = <110000>; 5055bac12f25SAmit Kucheria hysteresis = <1000>; 5056bac12f25SAmit Kucheria type = "critical"; 5057bac12f25SAmit Kucheria }; 5058bac12f25SAmit Kucheria }; 5059bac12f25SAmit Kucheria 5060bac12f25SAmit Kucheria cooling-maps { 5061bac12f25SAmit Kucheria map0 { 5062bac12f25SAmit Kucheria trip = <&cpu0_alert0>; 5063bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5064bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5065bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5066bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5067bac12f25SAmit Kucheria }; 5068bac12f25SAmit Kucheria map1 { 5069bac12f25SAmit Kucheria trip = <&cpu0_alert1>; 5070bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5071bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5072bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5073bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5074bac12f25SAmit Kucheria }; 5075bac12f25SAmit Kucheria }; 5076bac12f25SAmit Kucheria }; 5077bac12f25SAmit Kucheria 5078bac12f25SAmit Kucheria cpu1-thermal { 5079bac12f25SAmit Kucheria polling-delay-passive = <250>; 5080bac12f25SAmit Kucheria polling-delay = <1000>; 5081bac12f25SAmit Kucheria 5082bac12f25SAmit Kucheria thermal-sensors = <&tsens0 2>; 5083bac12f25SAmit Kucheria 5084bac12f25SAmit Kucheria trips { 5085bac12f25SAmit Kucheria cpu1_alert0: trip-point0 { 5086bac12f25SAmit Kucheria temperature = <90000>; 5087bac12f25SAmit Kucheria hysteresis = <2000>; 5088bac12f25SAmit Kucheria type = "passive"; 5089bac12f25SAmit Kucheria }; 5090bac12f25SAmit Kucheria 5091bac12f25SAmit Kucheria cpu1_alert1: trip-point1 { 5092bac12f25SAmit Kucheria temperature = <95000>; 5093bac12f25SAmit Kucheria hysteresis = <2000>; 5094bac12f25SAmit Kucheria type = "passive"; 5095bac12f25SAmit Kucheria }; 5096bac12f25SAmit Kucheria 5097bac12f25SAmit Kucheria cpu1_crit: cpu_crit { 5098bac12f25SAmit Kucheria temperature = <110000>; 5099bac12f25SAmit Kucheria hysteresis = <1000>; 5100bac12f25SAmit Kucheria type = "critical"; 5101bac12f25SAmit Kucheria }; 5102bac12f25SAmit Kucheria }; 5103bac12f25SAmit Kucheria 5104bac12f25SAmit Kucheria cooling-maps { 5105bac12f25SAmit Kucheria map0 { 5106bac12f25SAmit Kucheria trip = <&cpu1_alert0>; 5107bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5108bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5109bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5110bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5111bac12f25SAmit Kucheria }; 5112bac12f25SAmit Kucheria map1 { 5113bac12f25SAmit Kucheria trip = <&cpu1_alert1>; 5114bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5115bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5116bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5117bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5118bac12f25SAmit Kucheria }; 5119bac12f25SAmit Kucheria }; 5120bac12f25SAmit Kucheria }; 5121bac12f25SAmit Kucheria 5122bac12f25SAmit Kucheria cpu2-thermal { 5123bac12f25SAmit Kucheria polling-delay-passive = <250>; 5124bac12f25SAmit Kucheria polling-delay = <1000>; 5125bac12f25SAmit Kucheria 5126bac12f25SAmit Kucheria thermal-sensors = <&tsens0 3>; 5127bac12f25SAmit Kucheria 5128bac12f25SAmit Kucheria trips { 5129bac12f25SAmit Kucheria cpu2_alert0: trip-point0 { 5130bac12f25SAmit Kucheria temperature = <90000>; 5131bac12f25SAmit Kucheria hysteresis = <2000>; 5132bac12f25SAmit Kucheria type = "passive"; 5133bac12f25SAmit Kucheria }; 5134bac12f25SAmit Kucheria 5135bac12f25SAmit Kucheria cpu2_alert1: trip-point1 { 5136bac12f25SAmit Kucheria temperature = <95000>; 5137bac12f25SAmit Kucheria hysteresis = <2000>; 5138bac12f25SAmit Kucheria type = "passive"; 5139bac12f25SAmit Kucheria }; 5140bac12f25SAmit Kucheria 5141bac12f25SAmit Kucheria cpu2_crit: cpu_crit { 5142bac12f25SAmit Kucheria temperature = <110000>; 5143bac12f25SAmit Kucheria hysteresis = <1000>; 5144bac12f25SAmit Kucheria type = "critical"; 5145bac12f25SAmit Kucheria }; 5146bac12f25SAmit Kucheria }; 5147bac12f25SAmit Kucheria 5148bac12f25SAmit Kucheria cooling-maps { 5149bac12f25SAmit Kucheria map0 { 5150bac12f25SAmit Kucheria trip = <&cpu2_alert0>; 5151bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5152bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5153bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5154bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5155bac12f25SAmit Kucheria }; 5156bac12f25SAmit Kucheria map1 { 5157bac12f25SAmit Kucheria trip = <&cpu2_alert1>; 5158bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5159bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5160bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5161bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5162bac12f25SAmit Kucheria }; 5163bac12f25SAmit Kucheria }; 5164bac12f25SAmit Kucheria }; 5165bac12f25SAmit Kucheria 5166bac12f25SAmit Kucheria cpu3-thermal { 5167bac12f25SAmit Kucheria polling-delay-passive = <250>; 5168bac12f25SAmit Kucheria polling-delay = <1000>; 5169bac12f25SAmit Kucheria 5170bac12f25SAmit Kucheria thermal-sensors = <&tsens0 4>; 5171bac12f25SAmit Kucheria 5172bac12f25SAmit Kucheria trips { 5173bac12f25SAmit Kucheria cpu3_alert0: trip-point0 { 5174bac12f25SAmit Kucheria temperature = <90000>; 5175bac12f25SAmit Kucheria hysteresis = <2000>; 5176bac12f25SAmit Kucheria type = "passive"; 5177bac12f25SAmit Kucheria }; 5178bac12f25SAmit Kucheria 5179bac12f25SAmit Kucheria cpu3_alert1: trip-point1 { 5180bac12f25SAmit Kucheria temperature = <95000>; 5181bac12f25SAmit Kucheria hysteresis = <2000>; 5182bac12f25SAmit Kucheria type = "passive"; 5183bac12f25SAmit Kucheria }; 5184bac12f25SAmit Kucheria 5185bac12f25SAmit Kucheria cpu3_crit: cpu_crit { 5186bac12f25SAmit Kucheria temperature = <110000>; 5187bac12f25SAmit Kucheria hysteresis = <1000>; 5188bac12f25SAmit Kucheria type = "critical"; 5189bac12f25SAmit Kucheria }; 5190bac12f25SAmit Kucheria }; 5191bac12f25SAmit Kucheria 5192bac12f25SAmit Kucheria cooling-maps { 5193bac12f25SAmit Kucheria map0 { 5194bac12f25SAmit Kucheria trip = <&cpu3_alert0>; 5195bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5196bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5197bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5198bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5199bac12f25SAmit Kucheria }; 5200bac12f25SAmit Kucheria map1 { 5201bac12f25SAmit Kucheria trip = <&cpu3_alert1>; 5202bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5203bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5204bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5205bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5206bac12f25SAmit Kucheria }; 5207bac12f25SAmit Kucheria }; 5208bac12f25SAmit Kucheria }; 5209bac12f25SAmit Kucheria 5210bac12f25SAmit Kucheria cpu4-top-thermal { 5211bac12f25SAmit Kucheria polling-delay-passive = <250>; 5212bac12f25SAmit Kucheria polling-delay = <1000>; 5213bac12f25SAmit Kucheria 5214bac12f25SAmit Kucheria thermal-sensors = <&tsens0 7>; 5215bac12f25SAmit Kucheria 5216bac12f25SAmit Kucheria trips { 5217bac12f25SAmit Kucheria cpu4_top_alert0: trip-point0 { 5218bac12f25SAmit Kucheria temperature = <90000>; 5219bac12f25SAmit Kucheria hysteresis = <2000>; 5220bac12f25SAmit Kucheria type = "passive"; 5221bac12f25SAmit Kucheria }; 5222bac12f25SAmit Kucheria 5223bac12f25SAmit Kucheria cpu4_top_alert1: trip-point1 { 5224bac12f25SAmit Kucheria temperature = <95000>; 5225bac12f25SAmit Kucheria hysteresis = <2000>; 5226bac12f25SAmit Kucheria type = "passive"; 5227bac12f25SAmit Kucheria }; 5228bac12f25SAmit Kucheria 5229bac12f25SAmit Kucheria cpu4_top_crit: cpu_crit { 5230bac12f25SAmit Kucheria temperature = <110000>; 5231bac12f25SAmit Kucheria hysteresis = <1000>; 5232bac12f25SAmit Kucheria type = "critical"; 5233bac12f25SAmit Kucheria }; 5234bac12f25SAmit Kucheria }; 5235bac12f25SAmit Kucheria 5236bac12f25SAmit Kucheria cooling-maps { 5237bac12f25SAmit Kucheria map0 { 5238bac12f25SAmit Kucheria trip = <&cpu4_top_alert0>; 5239bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5240bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5241bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5242bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5243bac12f25SAmit Kucheria }; 5244bac12f25SAmit Kucheria map1 { 5245bac12f25SAmit Kucheria trip = <&cpu4_top_alert1>; 5246bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5247bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5248bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5249bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5250bac12f25SAmit Kucheria }; 5251bac12f25SAmit Kucheria }; 5252bac12f25SAmit Kucheria }; 5253bac12f25SAmit Kucheria 5254bac12f25SAmit Kucheria cpu5-top-thermal { 5255bac12f25SAmit Kucheria polling-delay-passive = <250>; 5256bac12f25SAmit Kucheria polling-delay = <1000>; 5257bac12f25SAmit Kucheria 5258bac12f25SAmit Kucheria thermal-sensors = <&tsens0 8>; 5259bac12f25SAmit Kucheria 5260bac12f25SAmit Kucheria trips { 5261bac12f25SAmit Kucheria cpu5_top_alert0: trip-point0 { 5262bac12f25SAmit Kucheria temperature = <90000>; 5263bac12f25SAmit Kucheria hysteresis = <2000>; 5264bac12f25SAmit Kucheria type = "passive"; 5265bac12f25SAmit Kucheria }; 5266bac12f25SAmit Kucheria 5267bac12f25SAmit Kucheria cpu5_top_alert1: trip-point1 { 5268bac12f25SAmit Kucheria temperature = <95000>; 5269bac12f25SAmit Kucheria hysteresis = <2000>; 5270bac12f25SAmit Kucheria type = "passive"; 5271bac12f25SAmit Kucheria }; 5272bac12f25SAmit Kucheria 5273bac12f25SAmit Kucheria cpu5_top_crit: cpu_crit { 5274bac12f25SAmit Kucheria temperature = <110000>; 5275bac12f25SAmit Kucheria hysteresis = <1000>; 5276bac12f25SAmit Kucheria type = "critical"; 5277bac12f25SAmit Kucheria }; 5278bac12f25SAmit Kucheria }; 5279bac12f25SAmit Kucheria 5280bac12f25SAmit Kucheria cooling-maps { 5281bac12f25SAmit Kucheria map0 { 5282bac12f25SAmit Kucheria trip = <&cpu5_top_alert0>; 5283bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5284bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5285bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5286bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5287bac12f25SAmit Kucheria }; 5288bac12f25SAmit Kucheria map1 { 5289bac12f25SAmit Kucheria trip = <&cpu5_top_alert1>; 5290bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5291bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5292bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5293bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5294bac12f25SAmit Kucheria }; 5295bac12f25SAmit Kucheria }; 5296bac12f25SAmit Kucheria }; 5297bac12f25SAmit Kucheria 5298bac12f25SAmit Kucheria cpu6-top-thermal { 5299bac12f25SAmit Kucheria polling-delay-passive = <250>; 5300bac12f25SAmit Kucheria polling-delay = <1000>; 5301bac12f25SAmit Kucheria 5302bac12f25SAmit Kucheria thermal-sensors = <&tsens0 9>; 5303bac12f25SAmit Kucheria 5304bac12f25SAmit Kucheria trips { 5305bac12f25SAmit Kucheria cpu6_top_alert0: trip-point0 { 5306bac12f25SAmit Kucheria temperature = <90000>; 5307bac12f25SAmit Kucheria hysteresis = <2000>; 5308bac12f25SAmit Kucheria type = "passive"; 5309bac12f25SAmit Kucheria }; 5310bac12f25SAmit Kucheria 5311bac12f25SAmit Kucheria cpu6_top_alert1: trip-point1 { 5312bac12f25SAmit Kucheria temperature = <95000>; 5313bac12f25SAmit Kucheria hysteresis = <2000>; 5314bac12f25SAmit Kucheria type = "passive"; 5315bac12f25SAmit Kucheria }; 5316bac12f25SAmit Kucheria 5317bac12f25SAmit Kucheria cpu6_top_crit: cpu_crit { 5318bac12f25SAmit Kucheria temperature = <110000>; 5319bac12f25SAmit Kucheria hysteresis = <1000>; 5320bac12f25SAmit Kucheria type = "critical"; 5321bac12f25SAmit Kucheria }; 5322bac12f25SAmit Kucheria }; 5323bac12f25SAmit Kucheria 5324bac12f25SAmit Kucheria cooling-maps { 5325bac12f25SAmit Kucheria map0 { 5326bac12f25SAmit Kucheria trip = <&cpu6_top_alert0>; 5327bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5328bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5329bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5330bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5331bac12f25SAmit Kucheria }; 5332bac12f25SAmit Kucheria map1 { 5333bac12f25SAmit Kucheria trip = <&cpu6_top_alert1>; 5334bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5335bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5336bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5337bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5338bac12f25SAmit Kucheria }; 5339bac12f25SAmit Kucheria }; 5340bac12f25SAmit Kucheria }; 5341bac12f25SAmit Kucheria 5342bac12f25SAmit Kucheria cpu7-top-thermal { 5343bac12f25SAmit Kucheria polling-delay-passive = <250>; 5344bac12f25SAmit Kucheria polling-delay = <1000>; 5345bac12f25SAmit Kucheria 5346bac12f25SAmit Kucheria thermal-sensors = <&tsens0 10>; 5347bac12f25SAmit Kucheria 5348bac12f25SAmit Kucheria trips { 5349bac12f25SAmit Kucheria cpu7_top_alert0: trip-point0 { 5350bac12f25SAmit Kucheria temperature = <90000>; 5351bac12f25SAmit Kucheria hysteresis = <2000>; 5352bac12f25SAmit Kucheria type = "passive"; 5353bac12f25SAmit Kucheria }; 5354bac12f25SAmit Kucheria 5355bac12f25SAmit Kucheria cpu7_top_alert1: trip-point1 { 5356bac12f25SAmit Kucheria temperature = <95000>; 5357bac12f25SAmit Kucheria hysteresis = <2000>; 5358bac12f25SAmit Kucheria type = "passive"; 5359bac12f25SAmit Kucheria }; 5360bac12f25SAmit Kucheria 5361bac12f25SAmit Kucheria cpu7_top_crit: cpu_crit { 5362bac12f25SAmit Kucheria temperature = <110000>; 5363bac12f25SAmit Kucheria hysteresis = <1000>; 5364bac12f25SAmit Kucheria type = "critical"; 5365bac12f25SAmit Kucheria }; 5366bac12f25SAmit Kucheria }; 5367bac12f25SAmit Kucheria 5368bac12f25SAmit Kucheria cooling-maps { 5369bac12f25SAmit Kucheria map0 { 5370bac12f25SAmit Kucheria trip = <&cpu7_top_alert0>; 5371bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5372bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5373bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5374bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5375bac12f25SAmit Kucheria }; 5376bac12f25SAmit Kucheria map1 { 5377bac12f25SAmit Kucheria trip = <&cpu7_top_alert1>; 5378bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5379bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5380bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5381bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5382bac12f25SAmit Kucheria }; 5383bac12f25SAmit Kucheria }; 5384bac12f25SAmit Kucheria }; 5385bac12f25SAmit Kucheria 5386bac12f25SAmit Kucheria cpu4-bottom-thermal { 5387bac12f25SAmit Kucheria polling-delay-passive = <250>; 5388bac12f25SAmit Kucheria polling-delay = <1000>; 5389bac12f25SAmit Kucheria 5390bac12f25SAmit Kucheria thermal-sensors = <&tsens0 11>; 5391bac12f25SAmit Kucheria 5392bac12f25SAmit Kucheria trips { 5393bac12f25SAmit Kucheria cpu4_bottom_alert0: trip-point0 { 5394bac12f25SAmit Kucheria temperature = <90000>; 5395bac12f25SAmit Kucheria hysteresis = <2000>; 5396bac12f25SAmit Kucheria type = "passive"; 5397bac12f25SAmit Kucheria }; 5398bac12f25SAmit Kucheria 5399bac12f25SAmit Kucheria cpu4_bottom_alert1: trip-point1 { 5400bac12f25SAmit Kucheria temperature = <95000>; 5401bac12f25SAmit Kucheria hysteresis = <2000>; 5402bac12f25SAmit Kucheria type = "passive"; 5403bac12f25SAmit Kucheria }; 5404bac12f25SAmit Kucheria 5405bac12f25SAmit Kucheria cpu4_bottom_crit: cpu_crit { 5406bac12f25SAmit Kucheria temperature = <110000>; 5407bac12f25SAmit Kucheria hysteresis = <1000>; 5408bac12f25SAmit Kucheria type = "critical"; 5409bac12f25SAmit Kucheria }; 5410bac12f25SAmit Kucheria }; 5411bac12f25SAmit Kucheria 5412bac12f25SAmit Kucheria cooling-maps { 5413bac12f25SAmit Kucheria map0 { 5414bac12f25SAmit Kucheria trip = <&cpu4_bottom_alert0>; 5415bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5416bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5417bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5418bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5419bac12f25SAmit Kucheria }; 5420bac12f25SAmit Kucheria map1 { 5421bac12f25SAmit Kucheria trip = <&cpu4_bottom_alert1>; 5422bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5423bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5424bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5425bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5426bac12f25SAmit Kucheria }; 5427bac12f25SAmit Kucheria }; 5428bac12f25SAmit Kucheria }; 5429bac12f25SAmit Kucheria 5430bac12f25SAmit Kucheria cpu5-bottom-thermal { 5431bac12f25SAmit Kucheria polling-delay-passive = <250>; 5432bac12f25SAmit Kucheria polling-delay = <1000>; 5433bac12f25SAmit Kucheria 5434bac12f25SAmit Kucheria thermal-sensors = <&tsens0 12>; 5435bac12f25SAmit Kucheria 5436bac12f25SAmit Kucheria trips { 5437bac12f25SAmit Kucheria cpu5_bottom_alert0: trip-point0 { 5438bac12f25SAmit Kucheria temperature = <90000>; 5439bac12f25SAmit Kucheria hysteresis = <2000>; 5440bac12f25SAmit Kucheria type = "passive"; 5441bac12f25SAmit Kucheria }; 5442bac12f25SAmit Kucheria 5443bac12f25SAmit Kucheria cpu5_bottom_alert1: trip-point1 { 5444bac12f25SAmit Kucheria temperature = <95000>; 5445bac12f25SAmit Kucheria hysteresis = <2000>; 5446bac12f25SAmit Kucheria type = "passive"; 5447bac12f25SAmit Kucheria }; 5448bac12f25SAmit Kucheria 5449bac12f25SAmit Kucheria cpu5_bottom_crit: cpu_crit { 5450bac12f25SAmit Kucheria temperature = <110000>; 5451bac12f25SAmit Kucheria hysteresis = <1000>; 5452bac12f25SAmit Kucheria type = "critical"; 5453bac12f25SAmit Kucheria }; 5454bac12f25SAmit Kucheria }; 5455bac12f25SAmit Kucheria 5456bac12f25SAmit Kucheria cooling-maps { 5457bac12f25SAmit Kucheria map0 { 5458bac12f25SAmit Kucheria trip = <&cpu5_bottom_alert0>; 5459bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5460bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5461bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5462bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5463bac12f25SAmit Kucheria }; 5464bac12f25SAmit Kucheria map1 { 5465bac12f25SAmit Kucheria trip = <&cpu5_bottom_alert1>; 5466bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5467bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5468bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5469bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5470bac12f25SAmit Kucheria }; 5471bac12f25SAmit Kucheria }; 5472bac12f25SAmit Kucheria }; 5473bac12f25SAmit Kucheria 5474bac12f25SAmit Kucheria cpu6-bottom-thermal { 5475bac12f25SAmit Kucheria polling-delay-passive = <250>; 5476bac12f25SAmit Kucheria polling-delay = <1000>; 5477bac12f25SAmit Kucheria 5478bac12f25SAmit Kucheria thermal-sensors = <&tsens0 13>; 5479bac12f25SAmit Kucheria 5480bac12f25SAmit Kucheria trips { 5481bac12f25SAmit Kucheria cpu6_bottom_alert0: trip-point0 { 5482bac12f25SAmit Kucheria temperature = <90000>; 5483bac12f25SAmit Kucheria hysteresis = <2000>; 5484bac12f25SAmit Kucheria type = "passive"; 5485bac12f25SAmit Kucheria }; 5486bac12f25SAmit Kucheria 5487bac12f25SAmit Kucheria cpu6_bottom_alert1: trip-point1 { 5488bac12f25SAmit Kucheria temperature = <95000>; 5489bac12f25SAmit Kucheria hysteresis = <2000>; 5490bac12f25SAmit Kucheria type = "passive"; 5491bac12f25SAmit Kucheria }; 5492bac12f25SAmit Kucheria 5493bac12f25SAmit Kucheria cpu6_bottom_crit: cpu_crit { 5494bac12f25SAmit Kucheria temperature = <110000>; 5495bac12f25SAmit Kucheria hysteresis = <1000>; 5496bac12f25SAmit Kucheria type = "critical"; 5497bac12f25SAmit Kucheria }; 5498bac12f25SAmit Kucheria }; 5499bac12f25SAmit Kucheria 5500bac12f25SAmit Kucheria cooling-maps { 5501bac12f25SAmit Kucheria map0 { 5502bac12f25SAmit Kucheria trip = <&cpu6_bottom_alert0>; 5503bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5504bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5505bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5506bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5507bac12f25SAmit Kucheria }; 5508bac12f25SAmit Kucheria map1 { 5509bac12f25SAmit Kucheria trip = <&cpu6_bottom_alert1>; 5510bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5511bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5512bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5513bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5514bac12f25SAmit Kucheria }; 5515bac12f25SAmit Kucheria }; 5516bac12f25SAmit Kucheria }; 5517bac12f25SAmit Kucheria 5518bac12f25SAmit Kucheria cpu7-bottom-thermal { 5519bac12f25SAmit Kucheria polling-delay-passive = <250>; 5520bac12f25SAmit Kucheria polling-delay = <1000>; 5521bac12f25SAmit Kucheria 5522bac12f25SAmit Kucheria thermal-sensors = <&tsens0 14>; 5523bac12f25SAmit Kucheria 5524bac12f25SAmit Kucheria trips { 5525bac12f25SAmit Kucheria cpu7_bottom_alert0: trip-point0 { 5526bac12f25SAmit Kucheria temperature = <90000>; 5527bac12f25SAmit Kucheria hysteresis = <2000>; 5528bac12f25SAmit Kucheria type = "passive"; 5529bac12f25SAmit Kucheria }; 5530bac12f25SAmit Kucheria 5531bac12f25SAmit Kucheria cpu7_bottom_alert1: trip-point1 { 5532bac12f25SAmit Kucheria temperature = <95000>; 5533bac12f25SAmit Kucheria hysteresis = <2000>; 5534bac12f25SAmit Kucheria type = "passive"; 5535bac12f25SAmit Kucheria }; 5536bac12f25SAmit Kucheria 5537bac12f25SAmit Kucheria cpu7_bottom_crit: cpu_crit { 5538bac12f25SAmit Kucheria temperature = <110000>; 5539bac12f25SAmit Kucheria hysteresis = <1000>; 5540bac12f25SAmit Kucheria type = "critical"; 5541bac12f25SAmit Kucheria }; 5542bac12f25SAmit Kucheria }; 5543bac12f25SAmit Kucheria 5544bac12f25SAmit Kucheria cooling-maps { 5545bac12f25SAmit Kucheria map0 { 5546bac12f25SAmit Kucheria trip = <&cpu7_bottom_alert0>; 5547bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5548bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5549bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5550bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5551bac12f25SAmit Kucheria }; 5552bac12f25SAmit Kucheria map1 { 5553bac12f25SAmit Kucheria trip = <&cpu7_bottom_alert1>; 5554bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5555bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5556bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5557bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5558bac12f25SAmit Kucheria }; 5559bac12f25SAmit Kucheria }; 5560bac12f25SAmit Kucheria }; 5561bac12f25SAmit Kucheria 5562bac12f25SAmit Kucheria aoss0-thermal { 5563bac12f25SAmit Kucheria polling-delay-passive = <250>; 5564bac12f25SAmit Kucheria polling-delay = <1000>; 5565bac12f25SAmit Kucheria 5566bac12f25SAmit Kucheria thermal-sensors = <&tsens0 0>; 5567bac12f25SAmit Kucheria 5568bac12f25SAmit Kucheria trips { 5569bac12f25SAmit Kucheria aoss0_alert0: trip-point0 { 5570bac12f25SAmit Kucheria temperature = <90000>; 5571bac12f25SAmit Kucheria hysteresis = <2000>; 5572bac12f25SAmit Kucheria type = "hot"; 5573bac12f25SAmit Kucheria }; 5574bac12f25SAmit Kucheria }; 5575bac12f25SAmit Kucheria }; 5576bac12f25SAmit Kucheria 5577bac12f25SAmit Kucheria cluster0-thermal { 5578bac12f25SAmit Kucheria polling-delay-passive = <250>; 5579bac12f25SAmit Kucheria polling-delay = <1000>; 5580bac12f25SAmit Kucheria 5581bac12f25SAmit Kucheria thermal-sensors = <&tsens0 5>; 5582bac12f25SAmit Kucheria 5583bac12f25SAmit Kucheria trips { 5584bac12f25SAmit Kucheria cluster0_alert0: trip-point0 { 5585bac12f25SAmit Kucheria temperature = <90000>; 5586bac12f25SAmit Kucheria hysteresis = <2000>; 5587bac12f25SAmit Kucheria type = "hot"; 5588bac12f25SAmit Kucheria }; 5589bac12f25SAmit Kucheria cluster0_crit: cluster0_crit { 5590bac12f25SAmit Kucheria temperature = <110000>; 5591bac12f25SAmit Kucheria hysteresis = <2000>; 5592bac12f25SAmit Kucheria type = "critical"; 5593bac12f25SAmit Kucheria }; 5594bac12f25SAmit Kucheria }; 5595bac12f25SAmit Kucheria }; 5596bac12f25SAmit Kucheria 5597bac12f25SAmit Kucheria cluster1-thermal { 5598bac12f25SAmit Kucheria polling-delay-passive = <250>; 5599bac12f25SAmit Kucheria polling-delay = <1000>; 5600bac12f25SAmit Kucheria 5601bac12f25SAmit Kucheria thermal-sensors = <&tsens0 6>; 5602bac12f25SAmit Kucheria 5603bac12f25SAmit Kucheria trips { 5604bac12f25SAmit Kucheria cluster1_alert0: trip-point0 { 5605bac12f25SAmit Kucheria temperature = <90000>; 5606bac12f25SAmit Kucheria hysteresis = <2000>; 5607bac12f25SAmit Kucheria type = "hot"; 5608bac12f25SAmit Kucheria }; 5609bac12f25SAmit Kucheria cluster1_crit: cluster1_crit { 5610bac12f25SAmit Kucheria temperature = <110000>; 5611bac12f25SAmit Kucheria hysteresis = <2000>; 5612bac12f25SAmit Kucheria type = "critical"; 5613bac12f25SAmit Kucheria }; 5614bac12f25SAmit Kucheria }; 5615bac12f25SAmit Kucheria }; 5616bac12f25SAmit Kucheria 56177be1c395SDavid Heidelberg gpu-top-thermal { 5618bac12f25SAmit Kucheria polling-delay-passive = <250>; 5619bac12f25SAmit Kucheria polling-delay = <1000>; 5620bac12f25SAmit Kucheria 5621bac12f25SAmit Kucheria thermal-sensors = <&tsens0 15>; 5622bac12f25SAmit Kucheria 5623bac12f25SAmit Kucheria trips { 5624bac12f25SAmit Kucheria gpu1_alert0: trip-point0 { 5625bac12f25SAmit Kucheria temperature = <90000>; 5626bac12f25SAmit Kucheria hysteresis = <2000>; 5627bac12f25SAmit Kucheria type = "hot"; 5628bac12f25SAmit Kucheria }; 5629bac12f25SAmit Kucheria }; 5630bac12f25SAmit Kucheria }; 5631bac12f25SAmit Kucheria 5632bac12f25SAmit Kucheria aoss1-thermal { 5633bac12f25SAmit Kucheria polling-delay-passive = <250>; 5634bac12f25SAmit Kucheria polling-delay = <1000>; 5635bac12f25SAmit Kucheria 5636bac12f25SAmit Kucheria thermal-sensors = <&tsens1 0>; 5637bac12f25SAmit Kucheria 5638bac12f25SAmit Kucheria trips { 5639bac12f25SAmit Kucheria aoss1_alert0: trip-point0 { 5640bac12f25SAmit Kucheria temperature = <90000>; 5641bac12f25SAmit Kucheria hysteresis = <2000>; 5642bac12f25SAmit Kucheria type = "hot"; 5643bac12f25SAmit Kucheria }; 5644bac12f25SAmit Kucheria }; 5645bac12f25SAmit Kucheria }; 5646bac12f25SAmit Kucheria 5647bac12f25SAmit Kucheria wlan-thermal { 5648bac12f25SAmit Kucheria polling-delay-passive = <250>; 5649bac12f25SAmit Kucheria polling-delay = <1000>; 5650bac12f25SAmit Kucheria 5651bac12f25SAmit Kucheria thermal-sensors = <&tsens1 1>; 5652bac12f25SAmit Kucheria 5653bac12f25SAmit Kucheria trips { 5654bac12f25SAmit Kucheria wlan_alert0: trip-point0 { 5655bac12f25SAmit Kucheria temperature = <90000>; 5656bac12f25SAmit Kucheria hysteresis = <2000>; 5657bac12f25SAmit Kucheria type = "hot"; 5658bac12f25SAmit Kucheria }; 5659bac12f25SAmit Kucheria }; 5660bac12f25SAmit Kucheria }; 5661bac12f25SAmit Kucheria 5662bac12f25SAmit Kucheria video-thermal { 5663bac12f25SAmit Kucheria polling-delay-passive = <250>; 5664bac12f25SAmit Kucheria polling-delay = <1000>; 5665bac12f25SAmit Kucheria 5666bac12f25SAmit Kucheria thermal-sensors = <&tsens1 2>; 5667bac12f25SAmit Kucheria 5668bac12f25SAmit Kucheria trips { 5669bac12f25SAmit Kucheria video_alert0: trip-point0 { 5670bac12f25SAmit Kucheria temperature = <90000>; 5671bac12f25SAmit Kucheria hysteresis = <2000>; 5672bac12f25SAmit Kucheria type = "hot"; 5673bac12f25SAmit Kucheria }; 5674bac12f25SAmit Kucheria }; 5675bac12f25SAmit Kucheria }; 5676bac12f25SAmit Kucheria 5677bac12f25SAmit Kucheria mem-thermal { 5678bac12f25SAmit Kucheria polling-delay-passive = <250>; 5679bac12f25SAmit Kucheria polling-delay = <1000>; 5680bac12f25SAmit Kucheria 5681bac12f25SAmit Kucheria thermal-sensors = <&tsens1 3>; 5682bac12f25SAmit Kucheria 5683bac12f25SAmit Kucheria trips { 5684bac12f25SAmit Kucheria mem_alert0: trip-point0 { 5685bac12f25SAmit Kucheria temperature = <90000>; 5686bac12f25SAmit Kucheria hysteresis = <2000>; 5687bac12f25SAmit Kucheria type = "hot"; 5688bac12f25SAmit Kucheria }; 5689bac12f25SAmit Kucheria }; 5690bac12f25SAmit Kucheria }; 5691bac12f25SAmit Kucheria 5692bac12f25SAmit Kucheria q6-hvx-thermal { 5693bac12f25SAmit Kucheria polling-delay-passive = <250>; 5694bac12f25SAmit Kucheria polling-delay = <1000>; 5695bac12f25SAmit Kucheria 5696bac12f25SAmit Kucheria thermal-sensors = <&tsens1 4>; 5697bac12f25SAmit Kucheria 5698bac12f25SAmit Kucheria trips { 5699bac12f25SAmit Kucheria q6_hvx_alert0: trip-point0 { 5700bac12f25SAmit Kucheria temperature = <90000>; 5701bac12f25SAmit Kucheria hysteresis = <2000>; 5702bac12f25SAmit Kucheria type = "hot"; 5703bac12f25SAmit Kucheria }; 5704bac12f25SAmit Kucheria }; 5705bac12f25SAmit Kucheria }; 5706bac12f25SAmit Kucheria 5707bac12f25SAmit Kucheria camera-thermal { 5708bac12f25SAmit Kucheria polling-delay-passive = <250>; 5709bac12f25SAmit Kucheria polling-delay = <1000>; 5710bac12f25SAmit Kucheria 5711bac12f25SAmit Kucheria thermal-sensors = <&tsens1 5>; 5712bac12f25SAmit Kucheria 5713bac12f25SAmit Kucheria trips { 5714bac12f25SAmit Kucheria camera_alert0: trip-point0 { 5715bac12f25SAmit Kucheria temperature = <90000>; 5716bac12f25SAmit Kucheria hysteresis = <2000>; 5717bac12f25SAmit Kucheria type = "hot"; 5718bac12f25SAmit Kucheria }; 5719bac12f25SAmit Kucheria }; 5720bac12f25SAmit Kucheria }; 5721bac12f25SAmit Kucheria 5722bac12f25SAmit Kucheria compute-thermal { 5723bac12f25SAmit Kucheria polling-delay-passive = <250>; 5724bac12f25SAmit Kucheria polling-delay = <1000>; 5725bac12f25SAmit Kucheria 5726bac12f25SAmit Kucheria thermal-sensors = <&tsens1 6>; 5727bac12f25SAmit Kucheria 5728bac12f25SAmit Kucheria trips { 5729bac12f25SAmit Kucheria compute_alert0: trip-point0 { 5730bac12f25SAmit Kucheria temperature = <90000>; 5731bac12f25SAmit Kucheria hysteresis = <2000>; 5732bac12f25SAmit Kucheria type = "hot"; 5733bac12f25SAmit Kucheria }; 5734bac12f25SAmit Kucheria }; 5735bac12f25SAmit Kucheria }; 5736bac12f25SAmit Kucheria 5737bac12f25SAmit Kucheria npu-thermal { 5738bac12f25SAmit Kucheria polling-delay-passive = <250>; 5739bac12f25SAmit Kucheria polling-delay = <1000>; 5740bac12f25SAmit Kucheria 5741bac12f25SAmit Kucheria thermal-sensors = <&tsens1 7>; 5742bac12f25SAmit Kucheria 5743bac12f25SAmit Kucheria trips { 5744bac12f25SAmit Kucheria npu_alert0: trip-point0 { 5745bac12f25SAmit Kucheria temperature = <90000>; 5746bac12f25SAmit Kucheria hysteresis = <2000>; 5747bac12f25SAmit Kucheria type = "hot"; 5748bac12f25SAmit Kucheria }; 5749bac12f25SAmit Kucheria }; 5750bac12f25SAmit Kucheria }; 5751bac12f25SAmit Kucheria 57527be1c395SDavid Heidelberg gpu-bottom-thermal { 5753bac12f25SAmit Kucheria polling-delay-passive = <250>; 5754bac12f25SAmit Kucheria polling-delay = <1000>; 5755bac12f25SAmit Kucheria 5756bac12f25SAmit Kucheria thermal-sensors = <&tsens1 8>; 5757bac12f25SAmit Kucheria 5758bac12f25SAmit Kucheria trips { 5759bac12f25SAmit Kucheria gpu2_alert0: trip-point0 { 5760bac12f25SAmit Kucheria temperature = <90000>; 5761bac12f25SAmit Kucheria hysteresis = <2000>; 5762bac12f25SAmit Kucheria type = "hot"; 5763bac12f25SAmit Kucheria }; 5764bac12f25SAmit Kucheria }; 5765bac12f25SAmit Kucheria }; 5766bac12f25SAmit Kucheria }; 576760378f1aSVenkata Narendra Kumar Gutta}; 5768