160378f1aSVenkata Narendra Kumar Gutta// SPDX-License-Identifier: BSD-3-Clause 260378f1aSVenkata Narendra Kumar Gutta/* 360378f1aSVenkata Narendra Kumar Gutta * Copyright (c) 2020, The Linux Foundation. All rights reserved. 460378f1aSVenkata Narendra Kumar Gutta */ 560378f1aSVenkata Narendra Kumar Gutta 660378f1aSVenkata Narendra Kumar Gutta#include <dt-bindings/interrupt-controller/arm-gic.h> 77c1dffd4SDmitry Baryshkov#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8b7e2fba0SBryan O'Donoghue#include <dt-bindings/clock/qcom,gcc-sm8250.h> 90e6aa9dbSJonathan Marek#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 1060378f1aSVenkata Narendra Kumar Gutta#include <dt-bindings/clock/qcom,rpmh.h> 1179a595bbSSibi Sankar#include <dt-bindings/interconnect/qcom,osm-l3.h> 127c1dffd4SDmitry Baryshkov#include <dt-bindings/interconnect/qcom,sm8250.h> 13e5361e75SBjorn Andersson#include <dt-bindings/mailbox/qcom-ipcc.h> 14087d537aSBjorn Andersson#include <dt-bindings/power/qcom-aoss-qmp.h> 15b6f78e27SBjorn Andersson#include <dt-bindings/power/qcom-rpmpd.h> 1663e10791SSrinivas Kandagatla#include <dt-bindings/soc/qcom,apr.h> 1760378f1aSVenkata Narendra Kumar Gutta#include <dt-bindings/soc/qcom,rpmh-rsc.h> 1863e10791SSrinivas Kandagatla#include <dt-bindings/sound/qcom,q6afe.h> 19bac12f25SAmit Kucheria#include <dt-bindings/thermal/thermal.h> 205b9ec225Sjonathan@marek.ca#include <dt-bindings/clock/qcom,videocc-sm8250.h> 2160378f1aSVenkata Narendra Kumar Gutta 2260378f1aSVenkata Narendra Kumar Gutta/ { 2360378f1aSVenkata Narendra Kumar Gutta interrupt-parent = <&intc>; 2460378f1aSVenkata Narendra Kumar Gutta 2560378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 2660378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 2760378f1aSVenkata Narendra Kumar Gutta 28e5813b15SDmitry Baryshkov aliases { 29e5813b15SDmitry Baryshkov i2c0 = &i2c0; 30e5813b15SDmitry Baryshkov i2c1 = &i2c1; 31e5813b15SDmitry Baryshkov i2c2 = &i2c2; 32e5813b15SDmitry Baryshkov i2c3 = &i2c3; 33e5813b15SDmitry Baryshkov i2c4 = &i2c4; 34e5813b15SDmitry Baryshkov i2c5 = &i2c5; 35e5813b15SDmitry Baryshkov i2c6 = &i2c6; 36e5813b15SDmitry Baryshkov i2c7 = &i2c7; 37e5813b15SDmitry Baryshkov i2c8 = &i2c8; 38e5813b15SDmitry Baryshkov i2c9 = &i2c9; 39e5813b15SDmitry Baryshkov i2c10 = &i2c10; 40e5813b15SDmitry Baryshkov i2c11 = &i2c11; 41e5813b15SDmitry Baryshkov i2c12 = &i2c12; 42e5813b15SDmitry Baryshkov i2c13 = &i2c13; 43e5813b15SDmitry Baryshkov i2c14 = &i2c14; 44e5813b15SDmitry Baryshkov i2c15 = &i2c15; 45e5813b15SDmitry Baryshkov i2c16 = &i2c16; 46e5813b15SDmitry Baryshkov i2c17 = &i2c17; 47e5813b15SDmitry Baryshkov i2c18 = &i2c18; 48e5813b15SDmitry Baryshkov i2c19 = &i2c19; 49e5813b15SDmitry Baryshkov spi0 = &spi0; 50e5813b15SDmitry Baryshkov spi1 = &spi1; 51e5813b15SDmitry Baryshkov spi2 = &spi2; 52e5813b15SDmitry Baryshkov spi3 = &spi3; 53e5813b15SDmitry Baryshkov spi4 = &spi4; 54e5813b15SDmitry Baryshkov spi5 = &spi5; 55e5813b15SDmitry Baryshkov spi6 = &spi6; 56e5813b15SDmitry Baryshkov spi7 = &spi7; 57e5813b15SDmitry Baryshkov spi8 = &spi8; 58e5813b15SDmitry Baryshkov spi9 = &spi9; 59e5813b15SDmitry Baryshkov spi10 = &spi10; 60e5813b15SDmitry Baryshkov spi11 = &spi11; 61e5813b15SDmitry Baryshkov spi12 = &spi12; 62e5813b15SDmitry Baryshkov spi13 = &spi13; 63e5813b15SDmitry Baryshkov spi14 = &spi14; 64e5813b15SDmitry Baryshkov spi15 = &spi15; 65e5813b15SDmitry Baryshkov spi16 = &spi16; 66e5813b15SDmitry Baryshkov spi17 = &spi17; 67e5813b15SDmitry Baryshkov spi18 = &spi18; 68e5813b15SDmitry Baryshkov spi19 = &spi19; 69e5813b15SDmitry Baryshkov }; 70e5813b15SDmitry Baryshkov 7160378f1aSVenkata Narendra Kumar Gutta chosen { }; 7260378f1aSVenkata Narendra Kumar Gutta 7360378f1aSVenkata Narendra Kumar Gutta clocks { 7460378f1aSVenkata Narendra Kumar Gutta xo_board: xo-board { 7560378f1aSVenkata Narendra Kumar Gutta compatible = "fixed-clock"; 7660378f1aSVenkata Narendra Kumar Gutta #clock-cells = <0>; 7760378f1aSVenkata Narendra Kumar Gutta clock-frequency = <38400000>; 7860378f1aSVenkata Narendra Kumar Gutta clock-output-names = "xo_board"; 7960378f1aSVenkata Narendra Kumar Gutta }; 8060378f1aSVenkata Narendra Kumar Gutta 8160378f1aSVenkata Narendra Kumar Gutta sleep_clk: sleep-clk { 8260378f1aSVenkata Narendra Kumar Gutta compatible = "fixed-clock"; 839ff8b059SJonathan Marek clock-frequency = <32768>; 8460378f1aSVenkata Narendra Kumar Gutta #clock-cells = <0>; 8560378f1aSVenkata Narendra Kumar Gutta }; 8660378f1aSVenkata Narendra Kumar Gutta }; 8760378f1aSVenkata Narendra Kumar Gutta 8860378f1aSVenkata Narendra Kumar Gutta cpus { 8960378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 9060378f1aSVenkata Narendra Kumar Gutta #size-cells = <0>; 9160378f1aSVenkata Narendra Kumar Gutta 9260378f1aSVenkata Narendra Kumar Gutta CPU0: cpu@0 { 9360378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 9460378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 9560378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x0>; 9660378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 976aabed55SDanny Lin capacity-dmips-mhz = <448>; 986aabed55SDanny Lin dynamic-power-coefficient = <205>; 9960378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_0>; 10002ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 101bac12f25SAmit Kucheria #cooling-cells = <2>; 10260378f1aSVenkata Narendra Kumar Gutta L2_0: l2-cache { 10360378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 10460378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 10560378f1aSVenkata Narendra Kumar Gutta L3_0: l3-cache { 10660378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 10760378f1aSVenkata Narendra Kumar Gutta }; 10860378f1aSVenkata Narendra Kumar Gutta }; 10960378f1aSVenkata Narendra Kumar Gutta }; 11060378f1aSVenkata Narendra Kumar Gutta 11160378f1aSVenkata Narendra Kumar Gutta CPU1: cpu@100 { 11260378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 11360378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 11460378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x100>; 11560378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1166aabed55SDanny Lin capacity-dmips-mhz = <448>; 1176aabed55SDanny Lin dynamic-power-coefficient = <205>; 11860378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_100>; 11902ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 120bac12f25SAmit Kucheria #cooling-cells = <2>; 12160378f1aSVenkata Narendra Kumar Gutta L2_100: l2-cache { 12260378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 12360378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 12460378f1aSVenkata Narendra Kumar Gutta }; 12560378f1aSVenkata Narendra Kumar Gutta }; 12660378f1aSVenkata Narendra Kumar Gutta 12760378f1aSVenkata Narendra Kumar Gutta CPU2: cpu@200 { 12860378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 12960378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 13060378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x200>; 13160378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1326aabed55SDanny Lin capacity-dmips-mhz = <448>; 1336aabed55SDanny Lin dynamic-power-coefficient = <205>; 13460378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_200>; 13502ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 136bac12f25SAmit Kucheria #cooling-cells = <2>; 13760378f1aSVenkata Narendra Kumar Gutta L2_200: l2-cache { 13860378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 13960378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 14060378f1aSVenkata Narendra Kumar Gutta }; 14160378f1aSVenkata Narendra Kumar Gutta }; 14260378f1aSVenkata Narendra Kumar Gutta 14360378f1aSVenkata Narendra Kumar Gutta CPU3: cpu@300 { 14460378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 14560378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 14660378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x300>; 14760378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1486aabed55SDanny Lin capacity-dmips-mhz = <448>; 1496aabed55SDanny Lin dynamic-power-coefficient = <205>; 15060378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_300>; 15102ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 152bac12f25SAmit Kucheria #cooling-cells = <2>; 15360378f1aSVenkata Narendra Kumar Gutta L2_300: l2-cache { 15460378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 15560378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 15660378f1aSVenkata Narendra Kumar Gutta }; 15760378f1aSVenkata Narendra Kumar Gutta }; 15860378f1aSVenkata Narendra Kumar Gutta 15960378f1aSVenkata Narendra Kumar Gutta CPU4: cpu@400 { 16060378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 16160378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 16260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x400>; 16360378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1646aabed55SDanny Lin capacity-dmips-mhz = <1024>; 1656aabed55SDanny Lin dynamic-power-coefficient = <379>; 16660378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_400>; 16702ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 1>; 168bac12f25SAmit Kucheria #cooling-cells = <2>; 16960378f1aSVenkata Narendra Kumar Gutta L2_400: l2-cache { 17060378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 17160378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 17260378f1aSVenkata Narendra Kumar Gutta }; 17360378f1aSVenkata Narendra Kumar Gutta }; 17460378f1aSVenkata Narendra Kumar Gutta 17560378f1aSVenkata Narendra Kumar Gutta CPU5: cpu@500 { 17660378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 17760378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 17860378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x500>; 17960378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1806aabed55SDanny Lin capacity-dmips-mhz = <1024>; 1816aabed55SDanny Lin dynamic-power-coefficient = <379>; 18260378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_500>; 18302ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 1>; 184bac12f25SAmit Kucheria #cooling-cells = <2>; 18560378f1aSVenkata Narendra Kumar Gutta L2_500: l2-cache { 18660378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 18760378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 18860378f1aSVenkata Narendra Kumar Gutta }; 18960378f1aSVenkata Narendra Kumar Gutta 19060378f1aSVenkata Narendra Kumar Gutta }; 19160378f1aSVenkata Narendra Kumar Gutta 19260378f1aSVenkata Narendra Kumar Gutta CPU6: cpu@600 { 19360378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 19460378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 19560378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x600>; 19660378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1976aabed55SDanny Lin capacity-dmips-mhz = <1024>; 1986aabed55SDanny Lin dynamic-power-coefficient = <379>; 19960378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_600>; 20002ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 1>; 201bac12f25SAmit Kucheria #cooling-cells = <2>; 20260378f1aSVenkata Narendra Kumar Gutta L2_600: l2-cache { 20360378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 20460378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 20560378f1aSVenkata Narendra Kumar Gutta }; 20660378f1aSVenkata Narendra Kumar Gutta }; 20760378f1aSVenkata Narendra Kumar Gutta 20860378f1aSVenkata Narendra Kumar Gutta CPU7: cpu@700 { 20960378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 21060378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 21160378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x700>; 21260378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 2136aabed55SDanny Lin capacity-dmips-mhz = <1024>; 2146aabed55SDanny Lin dynamic-power-coefficient = <444>; 21560378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_700>; 21602ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 2>; 217bac12f25SAmit Kucheria #cooling-cells = <2>; 21860378f1aSVenkata Narendra Kumar Gutta L2_700: l2-cache { 21960378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 22060378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 22160378f1aSVenkata Narendra Kumar Gutta }; 22260378f1aSVenkata Narendra Kumar Gutta }; 223b4791e69SDanny Lin 224b4791e69SDanny Lin cpu-map { 225b4791e69SDanny Lin cluster0 { 226b4791e69SDanny Lin core0 { 227b4791e69SDanny Lin cpu = <&CPU0>; 228b4791e69SDanny Lin }; 229b4791e69SDanny Lin 230b4791e69SDanny Lin core1 { 231b4791e69SDanny Lin cpu = <&CPU1>; 232b4791e69SDanny Lin }; 233b4791e69SDanny Lin 234b4791e69SDanny Lin core2 { 235b4791e69SDanny Lin cpu = <&CPU2>; 236b4791e69SDanny Lin }; 237b4791e69SDanny Lin 238b4791e69SDanny Lin core3 { 239b4791e69SDanny Lin cpu = <&CPU3>; 240b4791e69SDanny Lin }; 241b4791e69SDanny Lin 242b4791e69SDanny Lin core4 { 243b4791e69SDanny Lin cpu = <&CPU4>; 244b4791e69SDanny Lin }; 245b4791e69SDanny Lin 246b4791e69SDanny Lin core5 { 247b4791e69SDanny Lin cpu = <&CPU5>; 248b4791e69SDanny Lin }; 249b4791e69SDanny Lin 250b4791e69SDanny Lin core6 { 251b4791e69SDanny Lin cpu = <&CPU6>; 252b4791e69SDanny Lin }; 253b4791e69SDanny Lin 254b4791e69SDanny Lin core7 { 255b4791e69SDanny Lin cpu = <&CPU7>; 256b4791e69SDanny Lin }; 257b4791e69SDanny Lin }; 258b4791e69SDanny Lin }; 25960378f1aSVenkata Narendra Kumar Gutta }; 26060378f1aSVenkata Narendra Kumar Gutta 26160378f1aSVenkata Narendra Kumar Gutta firmware { 26260378f1aSVenkata Narendra Kumar Gutta scm: scm { 26360378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,scm"; 26460378f1aSVenkata Narendra Kumar Gutta #reset-cells = <1>; 26560378f1aSVenkata Narendra Kumar Gutta }; 26660378f1aSVenkata Narendra Kumar Gutta }; 26760378f1aSVenkata Narendra Kumar Gutta 26860378f1aSVenkata Narendra Kumar Gutta memory@80000000 { 26960378f1aSVenkata Narendra Kumar Gutta device_type = "memory"; 27060378f1aSVenkata Narendra Kumar Gutta /* We expect the bootloader to fill in the size */ 27160378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80000000 0x0 0x0>; 27260378f1aSVenkata Narendra Kumar Gutta }; 27360378f1aSVenkata Narendra Kumar Gutta 2743f2094dfSDmitry Baryshkov mmcx_reg: mmcx-reg { 2753f2094dfSDmitry Baryshkov compatible = "regulator-fixed-domain"; 2763f2094dfSDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 2773f2094dfSDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 2783f2094dfSDmitry Baryshkov regulator-name = "MMCX"; 2793f2094dfSDmitry Baryshkov }; 2803f2094dfSDmitry Baryshkov 28160378f1aSVenkata Narendra Kumar Gutta pmu { 28260378f1aSVenkata Narendra Kumar Gutta compatible = "arm,armv8-pmuv3"; 28393138ef5SSai Prakash Ranjan interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 28460378f1aSVenkata Narendra Kumar Gutta }; 28560378f1aSVenkata Narendra Kumar Gutta 28660378f1aSVenkata Narendra Kumar Gutta psci { 28760378f1aSVenkata Narendra Kumar Gutta compatible = "arm,psci-1.0"; 28860378f1aSVenkata Narendra Kumar Gutta method = "smc"; 28960378f1aSVenkata Narendra Kumar Gutta }; 29060378f1aSVenkata Narendra Kumar Gutta 29160378f1aSVenkata Narendra Kumar Gutta reserved-memory { 29260378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 29360378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 29460378f1aSVenkata Narendra Kumar Gutta ranges; 29560378f1aSVenkata Narendra Kumar Gutta 29660378f1aSVenkata Narendra Kumar Gutta hyp_mem: memory@80000000 { 29760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80000000 0x0 0x600000>; 29860378f1aSVenkata Narendra Kumar Gutta no-map; 29960378f1aSVenkata Narendra Kumar Gutta }; 30060378f1aSVenkata Narendra Kumar Gutta 30160378f1aSVenkata Narendra Kumar Gutta xbl_aop_mem: memory@80700000 { 30260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80700000 0x0 0x160000>; 30360378f1aSVenkata Narendra Kumar Gutta no-map; 30460378f1aSVenkata Narendra Kumar Gutta }; 30560378f1aSVenkata Narendra Kumar Gutta 30660378f1aSVenkata Narendra Kumar Gutta cmd_db: memory@80860000 { 30760378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,cmd-db"; 30860378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80860000 0x0 0x20000>; 30960378f1aSVenkata Narendra Kumar Gutta no-map; 31060378f1aSVenkata Narendra Kumar Gutta }; 31160378f1aSVenkata Narendra Kumar Gutta 31260378f1aSVenkata Narendra Kumar Gutta smem_mem: memory@80900000 { 31360378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80900000 0x0 0x200000>; 31460378f1aSVenkata Narendra Kumar Gutta no-map; 31560378f1aSVenkata Narendra Kumar Gutta }; 31660378f1aSVenkata Narendra Kumar Gutta 31760378f1aSVenkata Narendra Kumar Gutta removed_mem: memory@80b00000 { 31860378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80b00000 0x0 0x5300000>; 31960378f1aSVenkata Narendra Kumar Gutta no-map; 32060378f1aSVenkata Narendra Kumar Gutta }; 32160378f1aSVenkata Narendra Kumar Gutta 32260378f1aSVenkata Narendra Kumar Gutta camera_mem: memory@86200000 { 32360378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86200000 0x0 0x500000>; 32460378f1aSVenkata Narendra Kumar Gutta no-map; 32560378f1aSVenkata Narendra Kumar Gutta }; 32660378f1aSVenkata Narendra Kumar Gutta 32760378f1aSVenkata Narendra Kumar Gutta wlan_mem: memory@86700000 { 32860378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86700000 0x0 0x100000>; 32960378f1aSVenkata Narendra Kumar Gutta no-map; 33060378f1aSVenkata Narendra Kumar Gutta }; 33160378f1aSVenkata Narendra Kumar Gutta 33260378f1aSVenkata Narendra Kumar Gutta ipa_fw_mem: memory@86800000 { 33360378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86800000 0x0 0x10000>; 33460378f1aSVenkata Narendra Kumar Gutta no-map; 33560378f1aSVenkata Narendra Kumar Gutta }; 33660378f1aSVenkata Narendra Kumar Gutta 33760378f1aSVenkata Narendra Kumar Gutta ipa_gsi_mem: memory@86810000 { 33860378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86810000 0x0 0xa000>; 33960378f1aSVenkata Narendra Kumar Gutta no-map; 34060378f1aSVenkata Narendra Kumar Gutta }; 34160378f1aSVenkata Narendra Kumar Gutta 34260378f1aSVenkata Narendra Kumar Gutta gpu_mem: memory@8681a000 { 34360378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8681a000 0x0 0x2000>; 34460378f1aSVenkata Narendra Kumar Gutta no-map; 34560378f1aSVenkata Narendra Kumar Gutta }; 34660378f1aSVenkata Narendra Kumar Gutta 34760378f1aSVenkata Narendra Kumar Gutta npu_mem: memory@86900000 { 34860378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86900000 0x0 0x500000>; 34960378f1aSVenkata Narendra Kumar Gutta no-map; 35060378f1aSVenkata Narendra Kumar Gutta }; 35160378f1aSVenkata Narendra Kumar Gutta 35260378f1aSVenkata Narendra Kumar Gutta video_mem: memory@86e00000 { 35360378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86e00000 0x0 0x500000>; 35460378f1aSVenkata Narendra Kumar Gutta no-map; 35560378f1aSVenkata Narendra Kumar Gutta }; 35660378f1aSVenkata Narendra Kumar Gutta 35760378f1aSVenkata Narendra Kumar Gutta cvp_mem: memory@87300000 { 35860378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x87300000 0x0 0x500000>; 35960378f1aSVenkata Narendra Kumar Gutta no-map; 36060378f1aSVenkata Narendra Kumar Gutta }; 36160378f1aSVenkata Narendra Kumar Gutta 36260378f1aSVenkata Narendra Kumar Gutta cdsp_mem: memory@87800000 { 36360378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x87800000 0x0 0x1400000>; 36460378f1aSVenkata Narendra Kumar Gutta no-map; 36560378f1aSVenkata Narendra Kumar Gutta }; 36660378f1aSVenkata Narendra Kumar Gutta 36760378f1aSVenkata Narendra Kumar Gutta slpi_mem: memory@88c00000 { 36860378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x88c00000 0x0 0x1500000>; 36960378f1aSVenkata Narendra Kumar Gutta no-map; 37060378f1aSVenkata Narendra Kumar Gutta }; 37160378f1aSVenkata Narendra Kumar Gutta 37260378f1aSVenkata Narendra Kumar Gutta adsp_mem: memory@8a100000 { 37360378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8a100000 0x0 0x1d00000>; 37460378f1aSVenkata Narendra Kumar Gutta no-map; 37560378f1aSVenkata Narendra Kumar Gutta }; 37660378f1aSVenkata Narendra Kumar Gutta 37760378f1aSVenkata Narendra Kumar Gutta spss_mem: memory@8be00000 { 37860378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8be00000 0x0 0x100000>; 37960378f1aSVenkata Narendra Kumar Gutta no-map; 38060378f1aSVenkata Narendra Kumar Gutta }; 38160378f1aSVenkata Narendra Kumar Gutta 38260378f1aSVenkata Narendra Kumar Gutta cdsp_secure_heap: memory@8bf00000 { 38360378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8bf00000 0x0 0x4600000>; 38460378f1aSVenkata Narendra Kumar Gutta no-map; 38560378f1aSVenkata Narendra Kumar Gutta }; 38660378f1aSVenkata Narendra Kumar Gutta }; 38760378f1aSVenkata Narendra Kumar Gutta 38888b57bc3SDmitry Baryshkov smem { 38960378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,smem"; 39060378f1aSVenkata Narendra Kumar Gutta memory-region = <&smem_mem>; 39160378f1aSVenkata Narendra Kumar Gutta hwlocks = <&tcsr_mutex 3>; 39260378f1aSVenkata Narendra Kumar Gutta }; 39360378f1aSVenkata Narendra Kumar Gutta 3948770a2a8SBjorn Andersson smp2p-adsp { 3958770a2a8SBjorn Andersson compatible = "qcom,smp2p"; 3968770a2a8SBjorn Andersson qcom,smem = <443>, <429>; 3978770a2a8SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3988770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P 3998770a2a8SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 4008770a2a8SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_LPASS 4018770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P>; 4028770a2a8SBjorn Andersson 4038770a2a8SBjorn Andersson qcom,local-pid = <0>; 4048770a2a8SBjorn Andersson qcom,remote-pid = <2>; 4058770a2a8SBjorn Andersson 4068770a2a8SBjorn Andersson smp2p_adsp_out: master-kernel { 4078770a2a8SBjorn Andersson qcom,entry-name = "master-kernel"; 4088770a2a8SBjorn Andersson #qcom,smem-state-cells = <1>; 4098770a2a8SBjorn Andersson }; 4108770a2a8SBjorn Andersson 4118770a2a8SBjorn Andersson smp2p_adsp_in: slave-kernel { 4128770a2a8SBjorn Andersson qcom,entry-name = "slave-kernel"; 4138770a2a8SBjorn Andersson interrupt-controller; 4148770a2a8SBjorn Andersson #interrupt-cells = <2>; 4158770a2a8SBjorn Andersson }; 4168770a2a8SBjorn Andersson }; 4178770a2a8SBjorn Andersson 4188770a2a8SBjorn Andersson smp2p-cdsp { 4198770a2a8SBjorn Andersson compatible = "qcom,smp2p"; 4208770a2a8SBjorn Andersson qcom,smem = <94>, <432>; 4218770a2a8SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4228770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P 4238770a2a8SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 4248770a2a8SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_CDSP 4258770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P>; 4268770a2a8SBjorn Andersson 4278770a2a8SBjorn Andersson qcom,local-pid = <0>; 4288770a2a8SBjorn Andersson qcom,remote-pid = <5>; 4298770a2a8SBjorn Andersson 4308770a2a8SBjorn Andersson smp2p_cdsp_out: master-kernel { 4318770a2a8SBjorn Andersson qcom,entry-name = "master-kernel"; 4328770a2a8SBjorn Andersson #qcom,smem-state-cells = <1>; 4338770a2a8SBjorn Andersson }; 4348770a2a8SBjorn Andersson 4358770a2a8SBjorn Andersson smp2p_cdsp_in: slave-kernel { 4368770a2a8SBjorn Andersson qcom,entry-name = "slave-kernel"; 4378770a2a8SBjorn Andersson interrupt-controller; 4388770a2a8SBjorn Andersson #interrupt-cells = <2>; 4398770a2a8SBjorn Andersson }; 4408770a2a8SBjorn Andersson }; 4418770a2a8SBjorn Andersson 4428770a2a8SBjorn Andersson smp2p-slpi { 4438770a2a8SBjorn Andersson compatible = "qcom,smp2p"; 4448770a2a8SBjorn Andersson qcom,smem = <481>, <430>; 4458770a2a8SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 4468770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P 4478770a2a8SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 4488770a2a8SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_SLPI 4498770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P>; 4508770a2a8SBjorn Andersson 4518770a2a8SBjorn Andersson qcom,local-pid = <0>; 4528770a2a8SBjorn Andersson qcom,remote-pid = <3>; 4538770a2a8SBjorn Andersson 4548770a2a8SBjorn Andersson smp2p_slpi_out: master-kernel { 4558770a2a8SBjorn Andersson qcom,entry-name = "master-kernel"; 4568770a2a8SBjorn Andersson #qcom,smem-state-cells = <1>; 4578770a2a8SBjorn Andersson }; 4588770a2a8SBjorn Andersson 4598770a2a8SBjorn Andersson smp2p_slpi_in: slave-kernel { 4608770a2a8SBjorn Andersson qcom,entry-name = "slave-kernel"; 4618770a2a8SBjorn Andersson interrupt-controller; 4628770a2a8SBjorn Andersson #interrupt-cells = <2>; 4638770a2a8SBjorn Andersson }; 4648770a2a8SBjorn Andersson }; 4658770a2a8SBjorn Andersson 46660378f1aSVenkata Narendra Kumar Gutta soc: soc@0 { 46760378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 46860378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 46960378f1aSVenkata Narendra Kumar Gutta ranges = <0 0 0 0 0x10 0>; 47060378f1aSVenkata Narendra Kumar Gutta dma-ranges = <0 0 0 0 0x10 0>; 47160378f1aSVenkata Narendra Kumar Gutta compatible = "simple-bus"; 47260378f1aSVenkata Narendra Kumar Gutta 47360378f1aSVenkata Narendra Kumar Gutta gcc: clock-controller@100000 { 47460378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,gcc-sm8250"; 47560378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x00100000 0x0 0x1f0000>; 47660378f1aSVenkata Narendra Kumar Gutta #clock-cells = <1>; 47760378f1aSVenkata Narendra Kumar Gutta #reset-cells = <1>; 47860378f1aSVenkata Narendra Kumar Gutta #power-domain-cells = <1>; 47976bd127eSDmitry Baryshkov clock-names = "bi_tcxo", 48076bd127eSDmitry Baryshkov "bi_tcxo_ao", 48176bd127eSDmitry Baryshkov "sleep_clk"; 48276bd127eSDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>, 48376bd127eSDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK_A>, 48476bd127eSDmitry Baryshkov <&sleep_clk>; 48560378f1aSVenkata Narendra Kumar Gutta }; 48660378f1aSVenkata Narendra Kumar Gutta 487e5361e75SBjorn Andersson ipcc: mailbox@408000 { 488e5361e75SBjorn Andersson compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 489e5361e75SBjorn Andersson reg = <0 0x00408000 0 0x1000>; 490e5361e75SBjorn Andersson interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 491e5361e75SBjorn Andersson interrupt-controller; 492e5361e75SBjorn Andersson #interrupt-cells = <3>; 493e5361e75SBjorn Andersson #mbox-cells = <2>; 494e5361e75SBjorn Andersson }; 495e5361e75SBjorn Andersson 49665389ce6SManivannan Sadhasivam rng: rng@793000 { 49765389ce6SManivannan Sadhasivam compatible = "qcom,prng-ee"; 49865389ce6SManivannan Sadhasivam reg = <0 0x00793000 0 0x1000>; 49965389ce6SManivannan Sadhasivam clocks = <&gcc GCC_PRNG_AHB_CLK>; 50065389ce6SManivannan Sadhasivam clock-names = "core"; 50165389ce6SManivannan Sadhasivam }; 50265389ce6SManivannan Sadhasivam 50301e869ccSDmitry Baryshkov qup_opp_table: qup-opp-table { 50401e869ccSDmitry Baryshkov compatible = "operating-points-v2"; 50501e869ccSDmitry Baryshkov 50601e869ccSDmitry Baryshkov opp-50000000 { 50701e869ccSDmitry Baryshkov opp-hz = /bits/ 64 <50000000>; 50801e869ccSDmitry Baryshkov required-opps = <&rpmhpd_opp_min_svs>; 50901e869ccSDmitry Baryshkov }; 51001e869ccSDmitry Baryshkov 51101e869ccSDmitry Baryshkov opp-75000000 { 51201e869ccSDmitry Baryshkov opp-hz = /bits/ 64 <75000000>; 51301e869ccSDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 51401e869ccSDmitry Baryshkov }; 51501e869ccSDmitry Baryshkov 51601e869ccSDmitry Baryshkov opp-120000000 { 51701e869ccSDmitry Baryshkov opp-hz = /bits/ 64 <120000000>; 51801e869ccSDmitry Baryshkov required-opps = <&rpmhpd_opp_svs>; 51901e869ccSDmitry Baryshkov }; 52001e869ccSDmitry Baryshkov }; 52101e869ccSDmitry Baryshkov 522e5813b15SDmitry Baryshkov qupv3_id_2: geniqup@8c0000 { 523e5813b15SDmitry Baryshkov compatible = "qcom,geni-se-qup"; 524e5813b15SDmitry Baryshkov reg = <0x0 0x008c0000 0x0 0x6000>; 525e5813b15SDmitry Baryshkov clock-names = "m-ahb", "s-ahb"; 526e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 527e5813b15SDmitry Baryshkov <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 528e5813b15SDmitry Baryshkov #address-cells = <2>; 529e5813b15SDmitry Baryshkov #size-cells = <2>; 53085309393SDmitry Baryshkov iommus = <&apps_smmu 0x63 0x0>; 531e5813b15SDmitry Baryshkov ranges; 532e5813b15SDmitry Baryshkov status = "disabled"; 533e5813b15SDmitry Baryshkov 534e5813b15SDmitry Baryshkov i2c14: i2c@880000 { 535e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 536e5813b15SDmitry Baryshkov reg = <0 0x00880000 0 0x4000>; 537e5813b15SDmitry Baryshkov clock-names = "se"; 538e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 539e5813b15SDmitry Baryshkov pinctrl-names = "default"; 540e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c14_default>; 541e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 542e5813b15SDmitry Baryshkov #address-cells = <1>; 543e5813b15SDmitry Baryshkov #size-cells = <0>; 544e5813b15SDmitry Baryshkov status = "disabled"; 545e5813b15SDmitry Baryshkov }; 546e5813b15SDmitry Baryshkov 547e5813b15SDmitry Baryshkov spi14: spi@880000 { 548e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 549e5813b15SDmitry Baryshkov reg = <0 0x00880000 0 0x4000>; 550e5813b15SDmitry Baryshkov clock-names = "se"; 551e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 552e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 553e5813b15SDmitry Baryshkov #address-cells = <1>; 554e5813b15SDmitry Baryshkov #size-cells = <0>; 55501e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 55601e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 557e5813b15SDmitry Baryshkov status = "disabled"; 558e5813b15SDmitry Baryshkov }; 559e5813b15SDmitry Baryshkov 560e5813b15SDmitry Baryshkov i2c15: i2c@884000 { 561e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 562e5813b15SDmitry Baryshkov reg = <0 0x00884000 0 0x4000>; 563e5813b15SDmitry Baryshkov clock-names = "se"; 564e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 565e5813b15SDmitry Baryshkov pinctrl-names = "default"; 566e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c15_default>; 567e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 568e5813b15SDmitry Baryshkov #address-cells = <1>; 569e5813b15SDmitry Baryshkov #size-cells = <0>; 570e5813b15SDmitry Baryshkov status = "disabled"; 571e5813b15SDmitry Baryshkov }; 572e5813b15SDmitry Baryshkov 573e5813b15SDmitry Baryshkov spi15: spi@884000 { 574e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 575e5813b15SDmitry Baryshkov reg = <0 0x00884000 0 0x4000>; 576e5813b15SDmitry Baryshkov clock-names = "se"; 577e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 578e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 579e5813b15SDmitry Baryshkov #address-cells = <1>; 580e5813b15SDmitry Baryshkov #size-cells = <0>; 58101e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 58201e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 583e5813b15SDmitry Baryshkov status = "disabled"; 584e5813b15SDmitry Baryshkov }; 585e5813b15SDmitry Baryshkov 586e5813b15SDmitry Baryshkov i2c16: i2c@888000 { 587e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 588e5813b15SDmitry Baryshkov reg = <0 0x00888000 0 0x4000>; 589e5813b15SDmitry Baryshkov clock-names = "se"; 590e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 591e5813b15SDmitry Baryshkov pinctrl-names = "default"; 592e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c16_default>; 593e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 594e5813b15SDmitry Baryshkov #address-cells = <1>; 595e5813b15SDmitry Baryshkov #size-cells = <0>; 596e5813b15SDmitry Baryshkov status = "disabled"; 597e5813b15SDmitry Baryshkov }; 598e5813b15SDmitry Baryshkov 599e5813b15SDmitry Baryshkov spi16: spi@888000 { 600e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 601e5813b15SDmitry Baryshkov reg = <0 0x00888000 0 0x4000>; 602e5813b15SDmitry Baryshkov clock-names = "se"; 603e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 604e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 605e5813b15SDmitry Baryshkov #address-cells = <1>; 606e5813b15SDmitry Baryshkov #size-cells = <0>; 60701e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 60801e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 609e5813b15SDmitry Baryshkov status = "disabled"; 610e5813b15SDmitry Baryshkov }; 611e5813b15SDmitry Baryshkov 612e5813b15SDmitry Baryshkov i2c17: i2c@88c000 { 613e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 614e5813b15SDmitry Baryshkov reg = <0 0x0088c000 0 0x4000>; 615e5813b15SDmitry Baryshkov clock-names = "se"; 616e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 617e5813b15SDmitry Baryshkov pinctrl-names = "default"; 618e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c17_default>; 619e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 620e5813b15SDmitry Baryshkov #address-cells = <1>; 621e5813b15SDmitry Baryshkov #size-cells = <0>; 622e5813b15SDmitry Baryshkov status = "disabled"; 623e5813b15SDmitry Baryshkov }; 624e5813b15SDmitry Baryshkov 625e5813b15SDmitry Baryshkov spi17: spi@88c000 { 626e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 627e5813b15SDmitry Baryshkov reg = <0 0x0088c000 0 0x4000>; 628e5813b15SDmitry Baryshkov clock-names = "se"; 629e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 630e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 631e5813b15SDmitry Baryshkov #address-cells = <1>; 632e5813b15SDmitry Baryshkov #size-cells = <0>; 63301e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 63401e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 635e5813b15SDmitry Baryshkov status = "disabled"; 636e5813b15SDmitry Baryshkov }; 637e5813b15SDmitry Baryshkov 63808a9ae2dSDmitry Baryshkov uart17: serial@88c000 { 63908a9ae2dSDmitry Baryshkov compatible = "qcom,geni-uart"; 64008a9ae2dSDmitry Baryshkov reg = <0 0x0088c000 0 0x4000>; 64108a9ae2dSDmitry Baryshkov clock-names = "se"; 64208a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 64308a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 64408a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart17_default>; 64508a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 64601e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 64701e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 64808a9ae2dSDmitry Baryshkov status = "disabled"; 64908a9ae2dSDmitry Baryshkov }; 65008a9ae2dSDmitry Baryshkov 651e5813b15SDmitry Baryshkov i2c18: i2c@890000 { 652e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 653e5813b15SDmitry Baryshkov reg = <0 0x00890000 0 0x4000>; 654e5813b15SDmitry Baryshkov clock-names = "se"; 655e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 656e5813b15SDmitry Baryshkov pinctrl-names = "default"; 657e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c18_default>; 658e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 659e5813b15SDmitry Baryshkov #address-cells = <1>; 660e5813b15SDmitry Baryshkov #size-cells = <0>; 661e5813b15SDmitry Baryshkov status = "disabled"; 662e5813b15SDmitry Baryshkov }; 663e5813b15SDmitry Baryshkov 664e5813b15SDmitry Baryshkov spi18: spi@890000 { 665e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 666e5813b15SDmitry Baryshkov reg = <0 0x00890000 0 0x4000>; 667e5813b15SDmitry Baryshkov clock-names = "se"; 668e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 669e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 670e5813b15SDmitry Baryshkov #address-cells = <1>; 671e5813b15SDmitry Baryshkov #size-cells = <0>; 67201e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 67301e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 674e5813b15SDmitry Baryshkov status = "disabled"; 675e5813b15SDmitry Baryshkov }; 676e5813b15SDmitry Baryshkov 67708a9ae2dSDmitry Baryshkov uart18: serial@890000 { 67808a9ae2dSDmitry Baryshkov compatible = "qcom,geni-uart"; 67908a9ae2dSDmitry Baryshkov reg = <0 0x00890000 0 0x4000>; 68008a9ae2dSDmitry Baryshkov clock-names = "se"; 68108a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 68208a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 68308a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart18_default>; 68408a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 68501e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 68601e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 68708a9ae2dSDmitry Baryshkov status = "disabled"; 68808a9ae2dSDmitry Baryshkov }; 68908a9ae2dSDmitry Baryshkov 690e5813b15SDmitry Baryshkov i2c19: i2c@894000 { 691e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 692e5813b15SDmitry Baryshkov reg = <0 0x00894000 0 0x4000>; 693e5813b15SDmitry Baryshkov clock-names = "se"; 694e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 695e5813b15SDmitry Baryshkov pinctrl-names = "default"; 696e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c19_default>; 697e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 698e5813b15SDmitry Baryshkov #address-cells = <1>; 699e5813b15SDmitry Baryshkov #size-cells = <0>; 700e5813b15SDmitry Baryshkov status = "disabled"; 701e5813b15SDmitry Baryshkov }; 702e5813b15SDmitry Baryshkov 703e5813b15SDmitry Baryshkov spi19: spi@894000 { 704e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 705e5813b15SDmitry Baryshkov reg = <0 0x00894000 0 0x4000>; 706e5813b15SDmitry Baryshkov clock-names = "se"; 707e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 708e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 709e5813b15SDmitry Baryshkov #address-cells = <1>; 710e5813b15SDmitry Baryshkov #size-cells = <0>; 71101e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 71201e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 713e5813b15SDmitry Baryshkov status = "disabled"; 714e5813b15SDmitry Baryshkov }; 715e5813b15SDmitry Baryshkov }; 716e5813b15SDmitry Baryshkov 717e5813b15SDmitry Baryshkov qupv3_id_0: geniqup@9c0000 { 718e5813b15SDmitry Baryshkov compatible = "qcom,geni-se-qup"; 719e5813b15SDmitry Baryshkov reg = <0x0 0x009c0000 0x0 0x6000>; 720e5813b15SDmitry Baryshkov clock-names = "m-ahb", "s-ahb"; 721e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 722e5813b15SDmitry Baryshkov <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 723e5813b15SDmitry Baryshkov #address-cells = <2>; 724e5813b15SDmitry Baryshkov #size-cells = <2>; 72585309393SDmitry Baryshkov iommus = <&apps_smmu 0x5a3 0x0>; 726e5813b15SDmitry Baryshkov ranges; 727e5813b15SDmitry Baryshkov status = "disabled"; 728e5813b15SDmitry Baryshkov 729e5813b15SDmitry Baryshkov i2c0: i2c@980000 { 730e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 731e5813b15SDmitry Baryshkov reg = <0 0x00980000 0 0x4000>; 732e5813b15SDmitry Baryshkov clock-names = "se"; 733e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 734e5813b15SDmitry Baryshkov pinctrl-names = "default"; 735e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c0_default>; 736e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 737e5813b15SDmitry Baryshkov #address-cells = <1>; 738e5813b15SDmitry Baryshkov #size-cells = <0>; 739e5813b15SDmitry Baryshkov status = "disabled"; 740e5813b15SDmitry Baryshkov }; 741e5813b15SDmitry Baryshkov 742e5813b15SDmitry Baryshkov spi0: spi@980000 { 743e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 744e5813b15SDmitry Baryshkov reg = <0 0x00980000 0 0x4000>; 745e5813b15SDmitry Baryshkov clock-names = "se"; 746e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 747e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 748e5813b15SDmitry Baryshkov #address-cells = <1>; 749e5813b15SDmitry Baryshkov #size-cells = <0>; 75001e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 75101e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 752e5813b15SDmitry Baryshkov status = "disabled"; 753e5813b15SDmitry Baryshkov }; 754e5813b15SDmitry Baryshkov 755e5813b15SDmitry Baryshkov i2c1: i2c@984000 { 756e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 757e5813b15SDmitry Baryshkov reg = <0 0x00984000 0 0x4000>; 758e5813b15SDmitry Baryshkov clock-names = "se"; 759e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 760e5813b15SDmitry Baryshkov pinctrl-names = "default"; 761e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c1_default>; 762e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 763e5813b15SDmitry Baryshkov #address-cells = <1>; 764e5813b15SDmitry Baryshkov #size-cells = <0>; 765e5813b15SDmitry Baryshkov status = "disabled"; 766e5813b15SDmitry Baryshkov }; 767e5813b15SDmitry Baryshkov 768e5813b15SDmitry Baryshkov spi1: spi@984000 { 769e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 770e5813b15SDmitry Baryshkov reg = <0 0x00984000 0 0x4000>; 771e5813b15SDmitry Baryshkov clock-names = "se"; 772e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 773e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 774e5813b15SDmitry Baryshkov #address-cells = <1>; 775e5813b15SDmitry Baryshkov #size-cells = <0>; 77601e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 77701e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 778e5813b15SDmitry Baryshkov status = "disabled"; 779e5813b15SDmitry Baryshkov }; 780e5813b15SDmitry Baryshkov 781e5813b15SDmitry Baryshkov i2c2: i2c@988000 { 782e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 783e5813b15SDmitry Baryshkov reg = <0 0x00988000 0 0x4000>; 784e5813b15SDmitry Baryshkov clock-names = "se"; 785e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 786e5813b15SDmitry Baryshkov pinctrl-names = "default"; 787e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c2_default>; 788e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 789e5813b15SDmitry Baryshkov #address-cells = <1>; 790e5813b15SDmitry Baryshkov #size-cells = <0>; 791e5813b15SDmitry Baryshkov status = "disabled"; 792e5813b15SDmitry Baryshkov }; 793e5813b15SDmitry Baryshkov 794e5813b15SDmitry Baryshkov spi2: spi@988000 { 795e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 796e5813b15SDmitry Baryshkov reg = <0 0x00988000 0 0x4000>; 797e5813b15SDmitry Baryshkov clock-names = "se"; 798e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 799e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 800e5813b15SDmitry Baryshkov #address-cells = <1>; 801e5813b15SDmitry Baryshkov #size-cells = <0>; 80201e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 80301e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 804e5813b15SDmitry Baryshkov status = "disabled"; 805e5813b15SDmitry Baryshkov }; 806e5813b15SDmitry Baryshkov 80708a9ae2dSDmitry Baryshkov uart2: serial@988000 { 80808a9ae2dSDmitry Baryshkov compatible = "qcom,geni-debug-uart"; 80908a9ae2dSDmitry Baryshkov reg = <0 0x00988000 0 0x4000>; 81008a9ae2dSDmitry Baryshkov clock-names = "se"; 81108a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 81208a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 81308a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart2_default>; 81408a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 81501e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 81601e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 81708a9ae2dSDmitry Baryshkov status = "disabled"; 81808a9ae2dSDmitry Baryshkov }; 81908a9ae2dSDmitry Baryshkov 820e5813b15SDmitry Baryshkov i2c3: i2c@98c000 { 821e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 822e5813b15SDmitry Baryshkov reg = <0 0x0098c000 0 0x4000>; 823e5813b15SDmitry Baryshkov clock-names = "se"; 824e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 825e5813b15SDmitry Baryshkov pinctrl-names = "default"; 826e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c3_default>; 827e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 828e5813b15SDmitry Baryshkov #address-cells = <1>; 829e5813b15SDmitry Baryshkov #size-cells = <0>; 830e5813b15SDmitry Baryshkov status = "disabled"; 831e5813b15SDmitry Baryshkov }; 832e5813b15SDmitry Baryshkov 833e5813b15SDmitry Baryshkov spi3: spi@98c000 { 834e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 835e5813b15SDmitry Baryshkov reg = <0 0x0098c000 0 0x4000>; 836e5813b15SDmitry Baryshkov clock-names = "se"; 837e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 838e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 839e5813b15SDmitry Baryshkov #address-cells = <1>; 840e5813b15SDmitry Baryshkov #size-cells = <0>; 84101e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 84201e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 843e5813b15SDmitry Baryshkov status = "disabled"; 844e5813b15SDmitry Baryshkov }; 845e5813b15SDmitry Baryshkov 846e5813b15SDmitry Baryshkov i2c4: i2c@990000 { 847e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 848e5813b15SDmitry Baryshkov reg = <0 0x00990000 0 0x4000>; 849e5813b15SDmitry Baryshkov clock-names = "se"; 850e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 851e5813b15SDmitry Baryshkov pinctrl-names = "default"; 852e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c4_default>; 853e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 854e5813b15SDmitry Baryshkov #address-cells = <1>; 855e5813b15SDmitry Baryshkov #size-cells = <0>; 856e5813b15SDmitry Baryshkov status = "disabled"; 857e5813b15SDmitry Baryshkov }; 858e5813b15SDmitry Baryshkov 859e5813b15SDmitry Baryshkov spi4: spi@990000 { 860e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 861e5813b15SDmitry Baryshkov reg = <0 0x00990000 0 0x4000>; 862e5813b15SDmitry Baryshkov clock-names = "se"; 863e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 864e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 865e5813b15SDmitry Baryshkov #address-cells = <1>; 866e5813b15SDmitry Baryshkov #size-cells = <0>; 86701e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 86801e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 869e5813b15SDmitry Baryshkov status = "disabled"; 870e5813b15SDmitry Baryshkov }; 871e5813b15SDmitry Baryshkov 872e5813b15SDmitry Baryshkov i2c5: i2c@994000 { 873e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 874e5813b15SDmitry Baryshkov reg = <0 0x00994000 0 0x4000>; 875e5813b15SDmitry Baryshkov clock-names = "se"; 876e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 877e5813b15SDmitry Baryshkov pinctrl-names = "default"; 878e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c5_default>; 879e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 880e5813b15SDmitry Baryshkov #address-cells = <1>; 881e5813b15SDmitry Baryshkov #size-cells = <0>; 882e5813b15SDmitry Baryshkov status = "disabled"; 883e5813b15SDmitry Baryshkov }; 884e5813b15SDmitry Baryshkov 885e5813b15SDmitry Baryshkov spi5: spi@994000 { 886e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 887e5813b15SDmitry Baryshkov reg = <0 0x00994000 0 0x4000>; 888e5813b15SDmitry Baryshkov clock-names = "se"; 889e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 890e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 891e5813b15SDmitry Baryshkov #address-cells = <1>; 892e5813b15SDmitry Baryshkov #size-cells = <0>; 89301e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 89401e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 895e5813b15SDmitry Baryshkov status = "disabled"; 896e5813b15SDmitry Baryshkov }; 897e5813b15SDmitry Baryshkov 898e5813b15SDmitry Baryshkov i2c6: i2c@998000 { 899e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 900e5813b15SDmitry Baryshkov reg = <0 0x00998000 0 0x4000>; 901e5813b15SDmitry Baryshkov clock-names = "se"; 902e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 903e5813b15SDmitry Baryshkov pinctrl-names = "default"; 904e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c6_default>; 905e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 906e5813b15SDmitry Baryshkov #address-cells = <1>; 907e5813b15SDmitry Baryshkov #size-cells = <0>; 908e5813b15SDmitry Baryshkov status = "disabled"; 909e5813b15SDmitry Baryshkov }; 910e5813b15SDmitry Baryshkov 911e5813b15SDmitry Baryshkov spi6: spi@998000 { 912e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 913e5813b15SDmitry Baryshkov reg = <0 0x00998000 0 0x4000>; 914e5813b15SDmitry Baryshkov clock-names = "se"; 915e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 916e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 917e5813b15SDmitry Baryshkov #address-cells = <1>; 918e5813b15SDmitry Baryshkov #size-cells = <0>; 91901e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 92001e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 921e5813b15SDmitry Baryshkov status = "disabled"; 922e5813b15SDmitry Baryshkov }; 923e5813b15SDmitry Baryshkov 92408a9ae2dSDmitry Baryshkov uart6: serial@998000 { 92508a9ae2dSDmitry Baryshkov compatible = "qcom,geni-uart"; 92608a9ae2dSDmitry Baryshkov reg = <0 0x00998000 0 0x4000>; 92708a9ae2dSDmitry Baryshkov clock-names = "se"; 92808a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 92908a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 93008a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart6_default>; 93108a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 93201e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 93301e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 93408a9ae2dSDmitry Baryshkov status = "disabled"; 93508a9ae2dSDmitry Baryshkov }; 93608a9ae2dSDmitry Baryshkov 937e5813b15SDmitry Baryshkov i2c7: i2c@99c000 { 938e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 939e5813b15SDmitry Baryshkov reg = <0 0x0099c000 0 0x4000>; 940e5813b15SDmitry Baryshkov clock-names = "se"; 941e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 942e5813b15SDmitry Baryshkov pinctrl-names = "default"; 943e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c7_default>; 944e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 945e5813b15SDmitry Baryshkov #address-cells = <1>; 946e5813b15SDmitry Baryshkov #size-cells = <0>; 947e5813b15SDmitry Baryshkov status = "disabled"; 948e5813b15SDmitry Baryshkov }; 949e5813b15SDmitry Baryshkov 950e5813b15SDmitry Baryshkov spi7: spi@99c000 { 951e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 952e5813b15SDmitry Baryshkov reg = <0 0x0099c000 0 0x4000>; 953e5813b15SDmitry Baryshkov clock-names = "se"; 954e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 955e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 956e5813b15SDmitry Baryshkov #address-cells = <1>; 957e5813b15SDmitry Baryshkov #size-cells = <0>; 95801e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 95901e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 960e5813b15SDmitry Baryshkov status = "disabled"; 961e5813b15SDmitry Baryshkov }; 962e5813b15SDmitry Baryshkov }; 963e5813b15SDmitry Baryshkov 96460378f1aSVenkata Narendra Kumar Gutta qupv3_id_1: geniqup@ac0000 { 96560378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,geni-se-qup"; 96660378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x00ac0000 0x0 0x6000>; 96760378f1aSVenkata Narendra Kumar Gutta clock-names = "m-ahb", "s-ahb"; 968fe3dfc25SJonathan Marek clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 969fe3dfc25SJonathan Marek <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 97060378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 97160378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 97285309393SDmitry Baryshkov iommus = <&apps_smmu 0x43 0x0>; 97360378f1aSVenkata Narendra Kumar Gutta ranges; 97460378f1aSVenkata Narendra Kumar Gutta status = "disabled"; 97560378f1aSVenkata Narendra Kumar Gutta 976e5813b15SDmitry Baryshkov i2c8: i2c@a80000 { 977e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 978e5813b15SDmitry Baryshkov reg = <0 0x00a80000 0 0x4000>; 979e5813b15SDmitry Baryshkov clock-names = "se"; 980e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 981e5813b15SDmitry Baryshkov pinctrl-names = "default"; 982e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c8_default>; 983e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 984e5813b15SDmitry Baryshkov #address-cells = <1>; 985e5813b15SDmitry Baryshkov #size-cells = <0>; 986e5813b15SDmitry Baryshkov status = "disabled"; 987e5813b15SDmitry Baryshkov }; 988e5813b15SDmitry Baryshkov 989e5813b15SDmitry Baryshkov spi8: spi@a80000 { 990e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 991e5813b15SDmitry Baryshkov reg = <0 0x00a80000 0 0x4000>; 992e5813b15SDmitry Baryshkov clock-names = "se"; 993e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 994e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 995e5813b15SDmitry Baryshkov #address-cells = <1>; 996e5813b15SDmitry Baryshkov #size-cells = <0>; 99701e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 99801e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 999e5813b15SDmitry Baryshkov status = "disabled"; 1000e5813b15SDmitry Baryshkov }; 1001e5813b15SDmitry Baryshkov 1002e5813b15SDmitry Baryshkov i2c9: i2c@a84000 { 1003e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1004e5813b15SDmitry Baryshkov reg = <0 0x00a84000 0 0x4000>; 1005e5813b15SDmitry Baryshkov clock-names = "se"; 1006e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1007e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1008e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c9_default>; 1009e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1010e5813b15SDmitry Baryshkov #address-cells = <1>; 1011e5813b15SDmitry Baryshkov #size-cells = <0>; 1012e5813b15SDmitry Baryshkov status = "disabled"; 1013e5813b15SDmitry Baryshkov }; 1014e5813b15SDmitry Baryshkov 1015e5813b15SDmitry Baryshkov spi9: spi@a84000 { 1016e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1017e5813b15SDmitry Baryshkov reg = <0 0x00a84000 0 0x4000>; 1018e5813b15SDmitry Baryshkov clock-names = "se"; 1019e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1020e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1021e5813b15SDmitry Baryshkov #address-cells = <1>; 1022e5813b15SDmitry Baryshkov #size-cells = <0>; 102301e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 102401e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 1025e5813b15SDmitry Baryshkov status = "disabled"; 1026e5813b15SDmitry Baryshkov }; 1027e5813b15SDmitry Baryshkov 1028e5813b15SDmitry Baryshkov i2c10: i2c@a88000 { 1029e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1030e5813b15SDmitry Baryshkov reg = <0 0x00a88000 0 0x4000>; 1031e5813b15SDmitry Baryshkov clock-names = "se"; 1032e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1033e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1034e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c10_default>; 1035e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1036e5813b15SDmitry Baryshkov #address-cells = <1>; 1037e5813b15SDmitry Baryshkov #size-cells = <0>; 1038e5813b15SDmitry Baryshkov status = "disabled"; 1039e5813b15SDmitry Baryshkov }; 1040e5813b15SDmitry Baryshkov 1041e5813b15SDmitry Baryshkov spi10: spi@a88000 { 1042e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1043e5813b15SDmitry Baryshkov reg = <0 0x00a88000 0 0x4000>; 1044e5813b15SDmitry Baryshkov clock-names = "se"; 1045e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1046e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1047e5813b15SDmitry Baryshkov #address-cells = <1>; 1048e5813b15SDmitry Baryshkov #size-cells = <0>; 104901e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 105001e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 1051e5813b15SDmitry Baryshkov status = "disabled"; 1052e5813b15SDmitry Baryshkov }; 1053e5813b15SDmitry Baryshkov 1054e5813b15SDmitry Baryshkov i2c11: i2c@a8c000 { 1055e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1056e5813b15SDmitry Baryshkov reg = <0 0x00a8c000 0 0x4000>; 1057e5813b15SDmitry Baryshkov clock-names = "se"; 1058e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1059e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1060e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c11_default>; 1061e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1062e5813b15SDmitry Baryshkov #address-cells = <1>; 1063e5813b15SDmitry Baryshkov #size-cells = <0>; 1064e5813b15SDmitry Baryshkov status = "disabled"; 1065e5813b15SDmitry Baryshkov }; 1066e5813b15SDmitry Baryshkov 1067e5813b15SDmitry Baryshkov spi11: spi@a8c000 { 1068e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1069e5813b15SDmitry Baryshkov reg = <0 0x00a8c000 0 0x4000>; 1070e5813b15SDmitry Baryshkov clock-names = "se"; 1071e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1072e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1073e5813b15SDmitry Baryshkov #address-cells = <1>; 1074e5813b15SDmitry Baryshkov #size-cells = <0>; 107501e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 107601e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 1077e5813b15SDmitry Baryshkov status = "disabled"; 1078e5813b15SDmitry Baryshkov }; 1079e5813b15SDmitry Baryshkov 1080e5813b15SDmitry Baryshkov i2c12: i2c@a90000 { 1081e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1082e5813b15SDmitry Baryshkov reg = <0 0x00a90000 0 0x4000>; 1083e5813b15SDmitry Baryshkov clock-names = "se"; 1084e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1085e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1086e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c12_default>; 1087e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1088e5813b15SDmitry Baryshkov #address-cells = <1>; 1089e5813b15SDmitry Baryshkov #size-cells = <0>; 1090e5813b15SDmitry Baryshkov status = "disabled"; 1091e5813b15SDmitry Baryshkov }; 1092e5813b15SDmitry Baryshkov 1093e5813b15SDmitry Baryshkov spi12: spi@a90000 { 1094e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1095e5813b15SDmitry Baryshkov reg = <0 0x00a90000 0 0x4000>; 1096e5813b15SDmitry Baryshkov clock-names = "se"; 1097e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1098e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1099e5813b15SDmitry Baryshkov #address-cells = <1>; 1100e5813b15SDmitry Baryshkov #size-cells = <0>; 110101e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 110201e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 1103e5813b15SDmitry Baryshkov status = "disabled"; 1104e5813b15SDmitry Baryshkov }; 1105e5813b15SDmitry Baryshkov 1106bb1dfb4dSManivannan Sadhasivam uart12: serial@a90000 { 110760378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,geni-debug-uart"; 110860378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x00a90000 0x0 0x4000>; 110960378f1aSVenkata Narendra Kumar Gutta clock-names = "se"; 1110fe3dfc25SJonathan Marek clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1111bb1dfb4dSManivannan Sadhasivam pinctrl-names = "default"; 1112bb1dfb4dSManivannan Sadhasivam pinctrl-0 = <&qup_uart12_default>; 111360378f1aSVenkata Narendra Kumar Gutta interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 111401e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 111501e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 111660378f1aSVenkata Narendra Kumar Gutta status = "disabled"; 111760378f1aSVenkata Narendra Kumar Gutta }; 1118e5813b15SDmitry Baryshkov 1119e5813b15SDmitry Baryshkov i2c13: i2c@a94000 { 1120e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1121e5813b15SDmitry Baryshkov reg = <0 0x00a94000 0 0x4000>; 1122e5813b15SDmitry Baryshkov clock-names = "se"; 1123e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1124e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1125e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c13_default>; 1126e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1127e5813b15SDmitry Baryshkov #address-cells = <1>; 1128e5813b15SDmitry Baryshkov #size-cells = <0>; 1129e5813b15SDmitry Baryshkov status = "disabled"; 1130e5813b15SDmitry Baryshkov }; 1131e5813b15SDmitry Baryshkov 1132e5813b15SDmitry Baryshkov spi13: spi@a94000 { 1133e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1134e5813b15SDmitry Baryshkov reg = <0 0x00a94000 0 0x4000>; 1135e5813b15SDmitry Baryshkov clock-names = "se"; 1136e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1137e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1138e5813b15SDmitry Baryshkov #address-cells = <1>; 1139e5813b15SDmitry Baryshkov #size-cells = <0>; 114001e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 114101e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 1142e5813b15SDmitry Baryshkov status = "disabled"; 1143e5813b15SDmitry Baryshkov }; 114460378f1aSVenkata Narendra Kumar Gutta }; 114560378f1aSVenkata Narendra Kumar Gutta 1146e7e41a20SJonathan Marek config_noc: interconnect@1500000 { 1147e7e41a20SJonathan Marek compatible = "qcom,sm8250-config-noc"; 1148e7e41a20SJonathan Marek reg = <0 0x01500000 0 0xa580>; 1149e7e41a20SJonathan Marek #interconnect-cells = <1>; 1150e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1151e7e41a20SJonathan Marek }; 1152e7e41a20SJonathan Marek 1153e7e41a20SJonathan Marek system_noc: interconnect@1620000 { 1154e7e41a20SJonathan Marek compatible = "qcom,sm8250-system-noc"; 1155e7e41a20SJonathan Marek reg = <0 0x01620000 0 0x1c200>; 1156e7e41a20SJonathan Marek #interconnect-cells = <1>; 1157e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1158e7e41a20SJonathan Marek }; 1159e7e41a20SJonathan Marek 1160e7e41a20SJonathan Marek mc_virt: interconnect@163d000 { 1161e7e41a20SJonathan Marek compatible = "qcom,sm8250-mc-virt"; 1162e7e41a20SJonathan Marek reg = <0 0x0163d000 0 0x1000>; 1163e7e41a20SJonathan Marek #interconnect-cells = <1>; 1164e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1165e7e41a20SJonathan Marek }; 1166e7e41a20SJonathan Marek 1167e7e41a20SJonathan Marek aggre1_noc: interconnect@16e0000 { 1168e7e41a20SJonathan Marek compatible = "qcom,sm8250-aggre1-noc"; 1169e7e41a20SJonathan Marek reg = <0 0x016e0000 0 0x1f180>; 1170e7e41a20SJonathan Marek #interconnect-cells = <1>; 1171e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1172e7e41a20SJonathan Marek }; 1173e7e41a20SJonathan Marek 1174e7e41a20SJonathan Marek aggre2_noc: interconnect@1700000 { 1175e7e41a20SJonathan Marek compatible = "qcom,sm8250-aggre2-noc"; 1176e7e41a20SJonathan Marek reg = <0 0x01700000 0 0x33000>; 1177e7e41a20SJonathan Marek #interconnect-cells = <1>; 1178e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1179e7e41a20SJonathan Marek }; 1180e7e41a20SJonathan Marek 1181e7e41a20SJonathan Marek compute_noc: interconnect@1733000 { 1182e7e41a20SJonathan Marek compatible = "qcom,sm8250-compute-noc"; 1183e7e41a20SJonathan Marek reg = <0 0x01733000 0 0xa180>; 1184e7e41a20SJonathan Marek #interconnect-cells = <1>; 1185e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1186e7e41a20SJonathan Marek }; 1187e7e41a20SJonathan Marek 1188e7e41a20SJonathan Marek mmss_noc: interconnect@1740000 { 1189e7e41a20SJonathan Marek compatible = "qcom,sm8250-mmss-noc"; 1190e7e41a20SJonathan Marek reg = <0 0x01740000 0 0x1f080>; 1191e7e41a20SJonathan Marek #interconnect-cells = <1>; 1192e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1193e7e41a20SJonathan Marek }; 1194e7e41a20SJonathan Marek 1195e53bdfc0SManivannan Sadhasivam pcie0: pci@1c00000 { 1196e53bdfc0SManivannan Sadhasivam compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1197e53bdfc0SManivannan Sadhasivam reg = <0 0x01c00000 0 0x3000>, 1198e53bdfc0SManivannan Sadhasivam <0 0x60000000 0 0xf1d>, 1199e53bdfc0SManivannan Sadhasivam <0 0x60000f20 0 0xa8>, 1200e53bdfc0SManivannan Sadhasivam <0 0x60001000 0 0x1000>, 1201e53bdfc0SManivannan Sadhasivam <0 0x60100000 0 0x100000>; 1202e53bdfc0SManivannan Sadhasivam reg-names = "parf", "dbi", "elbi", "atu", "config"; 1203e53bdfc0SManivannan Sadhasivam device_type = "pci"; 1204e53bdfc0SManivannan Sadhasivam linux,pci-domain = <0>; 1205e53bdfc0SManivannan Sadhasivam bus-range = <0x00 0xff>; 1206e53bdfc0SManivannan Sadhasivam num-lanes = <1>; 1207e53bdfc0SManivannan Sadhasivam 1208e53bdfc0SManivannan Sadhasivam #address-cells = <3>; 1209e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1210e53bdfc0SManivannan Sadhasivam 1211e53bdfc0SManivannan Sadhasivam ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1212e53bdfc0SManivannan Sadhasivam <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1213e53bdfc0SManivannan Sadhasivam 1214e53bdfc0SManivannan Sadhasivam interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1215e53bdfc0SManivannan Sadhasivam interrupt-names = "msi"; 1216e53bdfc0SManivannan Sadhasivam #interrupt-cells = <1>; 1217e53bdfc0SManivannan Sadhasivam interrupt-map-mask = <0 0 0 0x7>; 1218e53bdfc0SManivannan Sadhasivam interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1219e53bdfc0SManivannan Sadhasivam <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1220e53bdfc0SManivannan Sadhasivam <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1221e53bdfc0SManivannan Sadhasivam <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1222e53bdfc0SManivannan Sadhasivam 1223e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1224e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_AUX_CLK>, 1225e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1226e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1227e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1228e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1229e53bdfc0SManivannan Sadhasivam <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1230e53bdfc0SManivannan Sadhasivam <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1231e53bdfc0SManivannan Sadhasivam clock-names = "pipe", 1232e53bdfc0SManivannan Sadhasivam "aux", 1233e53bdfc0SManivannan Sadhasivam "cfg", 1234e53bdfc0SManivannan Sadhasivam "bus_master", 1235e53bdfc0SManivannan Sadhasivam "bus_slave", 1236e53bdfc0SManivannan Sadhasivam "slave_q2a", 1237e53bdfc0SManivannan Sadhasivam "tbu", 1238e53bdfc0SManivannan Sadhasivam "ddrss_sf_tbu"; 1239e53bdfc0SManivannan Sadhasivam 1240e53bdfc0SManivannan Sadhasivam iommus = <&apps_smmu 0x1c00 0x7f>; 1241e53bdfc0SManivannan Sadhasivam iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1242e53bdfc0SManivannan Sadhasivam <0x100 &apps_smmu 0x1c01 0x1>; 1243e53bdfc0SManivannan Sadhasivam 1244e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_0_BCR>; 1245e53bdfc0SManivannan Sadhasivam reset-names = "pci"; 1246e53bdfc0SManivannan Sadhasivam 1247e53bdfc0SManivannan Sadhasivam power-domains = <&gcc PCIE_0_GDSC>; 1248e53bdfc0SManivannan Sadhasivam 1249e53bdfc0SManivannan Sadhasivam phys = <&pcie0_lane>; 1250e53bdfc0SManivannan Sadhasivam phy-names = "pciephy"; 1251e53bdfc0SManivannan Sadhasivam 1252e53bdfc0SManivannan Sadhasivam status = "disabled"; 1253e53bdfc0SManivannan Sadhasivam }; 1254e53bdfc0SManivannan Sadhasivam 1255e53bdfc0SManivannan Sadhasivam pcie0_phy: phy@1c06000 { 1256e53bdfc0SManivannan Sadhasivam compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1257e53bdfc0SManivannan Sadhasivam reg = <0 0x01c06000 0 0x1c0>; 1258e53bdfc0SManivannan Sadhasivam #address-cells = <2>; 1259e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1260e53bdfc0SManivannan Sadhasivam ranges; 1261e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1262e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1263e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1264e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1265e53bdfc0SManivannan Sadhasivam clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1266e53bdfc0SManivannan Sadhasivam 1267e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1268e53bdfc0SManivannan Sadhasivam reset-names = "phy"; 1269e53bdfc0SManivannan Sadhasivam 1270e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1271e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <100000000>; 1272e53bdfc0SManivannan Sadhasivam 1273e53bdfc0SManivannan Sadhasivam status = "disabled"; 1274e53bdfc0SManivannan Sadhasivam 1275e53bdfc0SManivannan Sadhasivam pcie0_lane: lanes@1c06200 { 1276e53bdfc0SManivannan Sadhasivam reg = <0 0x1c06200 0 0x170>, /* tx */ 1277e53bdfc0SManivannan Sadhasivam <0 0x1c06400 0 0x200>, /* rx */ 1278e53bdfc0SManivannan Sadhasivam <0 0x1c06800 0 0x1f0>, /* pcs */ 1279e53bdfc0SManivannan Sadhasivam <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1280e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1281e53bdfc0SManivannan Sadhasivam clock-names = "pipe0"; 1282e53bdfc0SManivannan Sadhasivam 1283e53bdfc0SManivannan Sadhasivam #phy-cells = <0>; 1284e53bdfc0SManivannan Sadhasivam clock-output-names = "pcie_0_pipe_clk"; 1285e53bdfc0SManivannan Sadhasivam }; 1286e53bdfc0SManivannan Sadhasivam }; 1287e53bdfc0SManivannan Sadhasivam 1288e53bdfc0SManivannan Sadhasivam pcie1: pci@1c08000 { 1289e53bdfc0SManivannan Sadhasivam compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1290e53bdfc0SManivannan Sadhasivam reg = <0 0x01c08000 0 0x3000>, 1291e53bdfc0SManivannan Sadhasivam <0 0x40000000 0 0xf1d>, 1292e53bdfc0SManivannan Sadhasivam <0 0x40000f20 0 0xa8>, 1293e53bdfc0SManivannan Sadhasivam <0 0x40001000 0 0x1000>, 1294e53bdfc0SManivannan Sadhasivam <0 0x40100000 0 0x100000>; 1295e53bdfc0SManivannan Sadhasivam reg-names = "parf", "dbi", "elbi", "atu", "config"; 1296e53bdfc0SManivannan Sadhasivam device_type = "pci"; 1297e53bdfc0SManivannan Sadhasivam linux,pci-domain = <1>; 1298e53bdfc0SManivannan Sadhasivam bus-range = <0x00 0xff>; 1299e53bdfc0SManivannan Sadhasivam num-lanes = <2>; 1300e53bdfc0SManivannan Sadhasivam 1301e53bdfc0SManivannan Sadhasivam #address-cells = <3>; 1302e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1303e53bdfc0SManivannan Sadhasivam 1304e53bdfc0SManivannan Sadhasivam ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1305e53bdfc0SManivannan Sadhasivam <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1306e53bdfc0SManivannan Sadhasivam 1307e53bdfc0SManivannan Sadhasivam interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>; 1308e53bdfc0SManivannan Sadhasivam interrupt-names = "msi"; 1309e53bdfc0SManivannan Sadhasivam #interrupt-cells = <1>; 1310e53bdfc0SManivannan Sadhasivam interrupt-map-mask = <0 0 0 0x7>; 1311e53bdfc0SManivannan Sadhasivam interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1312e53bdfc0SManivannan Sadhasivam <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1313e53bdfc0SManivannan Sadhasivam <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1314e53bdfc0SManivannan Sadhasivam <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1315e53bdfc0SManivannan Sadhasivam 1316e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1317e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_AUX_CLK>, 1318e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1319e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1320e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1321e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1322e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1323e53bdfc0SManivannan Sadhasivam <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1324e53bdfc0SManivannan Sadhasivam <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1325e53bdfc0SManivannan Sadhasivam clock-names = "pipe", 1326e53bdfc0SManivannan Sadhasivam "aux", 1327e53bdfc0SManivannan Sadhasivam "cfg", 1328e53bdfc0SManivannan Sadhasivam "bus_master", 1329e53bdfc0SManivannan Sadhasivam "bus_slave", 1330e53bdfc0SManivannan Sadhasivam "slave_q2a", 1331e53bdfc0SManivannan Sadhasivam "ref", 1332e53bdfc0SManivannan Sadhasivam "tbu", 1333e53bdfc0SManivannan Sadhasivam "ddrss_sf_tbu"; 1334e53bdfc0SManivannan Sadhasivam 1335e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1336e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <19200000>; 1337e53bdfc0SManivannan Sadhasivam 1338e53bdfc0SManivannan Sadhasivam iommus = <&apps_smmu 0x1c80 0x7f>; 1339e53bdfc0SManivannan Sadhasivam iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1340e53bdfc0SManivannan Sadhasivam <0x100 &apps_smmu 0x1c81 0x1>; 1341e53bdfc0SManivannan Sadhasivam 1342e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_1_BCR>; 1343e53bdfc0SManivannan Sadhasivam reset-names = "pci"; 1344e53bdfc0SManivannan Sadhasivam 1345e53bdfc0SManivannan Sadhasivam power-domains = <&gcc PCIE_1_GDSC>; 1346e53bdfc0SManivannan Sadhasivam 1347e53bdfc0SManivannan Sadhasivam phys = <&pcie1_lane>; 1348e53bdfc0SManivannan Sadhasivam phy-names = "pciephy"; 1349e53bdfc0SManivannan Sadhasivam 1350e53bdfc0SManivannan Sadhasivam status = "disabled"; 1351e53bdfc0SManivannan Sadhasivam }; 1352e53bdfc0SManivannan Sadhasivam 1353e53bdfc0SManivannan Sadhasivam pcie1_phy: phy@1c0e000 { 1354e53bdfc0SManivannan Sadhasivam compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1355e53bdfc0SManivannan Sadhasivam reg = <0 0x01c0e000 0 0x1c0>; 1356e53bdfc0SManivannan Sadhasivam #address-cells = <2>; 1357e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1358e53bdfc0SManivannan Sadhasivam ranges; 1359e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1360e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1361e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1362e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1363e53bdfc0SManivannan Sadhasivam clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1364e53bdfc0SManivannan Sadhasivam 1365e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1366e53bdfc0SManivannan Sadhasivam reset-names = "phy"; 1367e53bdfc0SManivannan Sadhasivam 1368e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1369e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <100000000>; 1370e53bdfc0SManivannan Sadhasivam 1371e53bdfc0SManivannan Sadhasivam status = "disabled"; 1372e53bdfc0SManivannan Sadhasivam 1373e53bdfc0SManivannan Sadhasivam pcie1_lane: lanes@1c0e200 { 1374e53bdfc0SManivannan Sadhasivam reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1375e53bdfc0SManivannan Sadhasivam <0 0x1c0e400 0 0x200>, /* rx0 */ 1376e53bdfc0SManivannan Sadhasivam <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1377e53bdfc0SManivannan Sadhasivam <0 0x1c0e600 0 0x170>, /* tx1 */ 1378e53bdfc0SManivannan Sadhasivam <0 0x1c0e800 0 0x200>, /* rx1 */ 1379e53bdfc0SManivannan Sadhasivam <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1380e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1381e53bdfc0SManivannan Sadhasivam clock-names = "pipe0"; 1382e53bdfc0SManivannan Sadhasivam 1383e53bdfc0SManivannan Sadhasivam #phy-cells = <0>; 1384e53bdfc0SManivannan Sadhasivam clock-output-names = "pcie_1_pipe_clk"; 1385e53bdfc0SManivannan Sadhasivam }; 1386e53bdfc0SManivannan Sadhasivam }; 1387e53bdfc0SManivannan Sadhasivam 1388e53bdfc0SManivannan Sadhasivam pcie2: pci@1c10000 { 1389e53bdfc0SManivannan Sadhasivam compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1390e53bdfc0SManivannan Sadhasivam reg = <0 0x01c10000 0 0x3000>, 1391e53bdfc0SManivannan Sadhasivam <0 0x64000000 0 0xf1d>, 1392e53bdfc0SManivannan Sadhasivam <0 0x64000f20 0 0xa8>, 1393e53bdfc0SManivannan Sadhasivam <0 0x64001000 0 0x1000>, 1394e53bdfc0SManivannan Sadhasivam <0 0x64100000 0 0x100000>; 1395e53bdfc0SManivannan Sadhasivam reg-names = "parf", "dbi", "elbi", "atu", "config"; 1396e53bdfc0SManivannan Sadhasivam device_type = "pci"; 1397e53bdfc0SManivannan Sadhasivam linux,pci-domain = <2>; 1398e53bdfc0SManivannan Sadhasivam bus-range = <0x00 0xff>; 1399e53bdfc0SManivannan Sadhasivam num-lanes = <2>; 1400e53bdfc0SManivannan Sadhasivam 1401e53bdfc0SManivannan Sadhasivam #address-cells = <3>; 1402e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1403e53bdfc0SManivannan Sadhasivam 1404e53bdfc0SManivannan Sadhasivam ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, 1405e53bdfc0SManivannan Sadhasivam <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 1406e53bdfc0SManivannan Sadhasivam 1407e53bdfc0SManivannan Sadhasivam interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; 1408e53bdfc0SManivannan Sadhasivam interrupt-names = "msi"; 1409e53bdfc0SManivannan Sadhasivam #interrupt-cells = <1>; 1410e53bdfc0SManivannan Sadhasivam interrupt-map-mask = <0 0 0 0x7>; 1411e53bdfc0SManivannan Sadhasivam interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1412e53bdfc0SManivannan Sadhasivam <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1413e53bdfc0SManivannan Sadhasivam <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1414e53bdfc0SManivannan Sadhasivam <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1415e53bdfc0SManivannan Sadhasivam 1416e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1417e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_AUX_CLK>, 1418e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1419e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1420e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 1421e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 1422e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1423e53bdfc0SManivannan Sadhasivam <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1424e53bdfc0SManivannan Sadhasivam <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1425e53bdfc0SManivannan Sadhasivam clock-names = "pipe", 1426e53bdfc0SManivannan Sadhasivam "aux", 1427e53bdfc0SManivannan Sadhasivam "cfg", 1428e53bdfc0SManivannan Sadhasivam "bus_master", 1429e53bdfc0SManivannan Sadhasivam "bus_slave", 1430e53bdfc0SManivannan Sadhasivam "slave_q2a", 1431e53bdfc0SManivannan Sadhasivam "ref", 1432e53bdfc0SManivannan Sadhasivam "tbu", 1433e53bdfc0SManivannan Sadhasivam "ddrss_sf_tbu"; 1434e53bdfc0SManivannan Sadhasivam 1435e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 1436e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <19200000>; 1437e53bdfc0SManivannan Sadhasivam 1438e53bdfc0SManivannan Sadhasivam iommus = <&apps_smmu 0x1d00 0x7f>; 1439e53bdfc0SManivannan Sadhasivam iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 1440e53bdfc0SManivannan Sadhasivam <0x100 &apps_smmu 0x1d01 0x1>; 1441e53bdfc0SManivannan Sadhasivam 1442e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_2_BCR>; 1443e53bdfc0SManivannan Sadhasivam reset-names = "pci"; 1444e53bdfc0SManivannan Sadhasivam 1445e53bdfc0SManivannan Sadhasivam power-domains = <&gcc PCIE_2_GDSC>; 1446e53bdfc0SManivannan Sadhasivam 1447e53bdfc0SManivannan Sadhasivam phys = <&pcie2_lane>; 1448e53bdfc0SManivannan Sadhasivam phy-names = "pciephy"; 1449e53bdfc0SManivannan Sadhasivam 1450e53bdfc0SManivannan Sadhasivam status = "disabled"; 1451e53bdfc0SManivannan Sadhasivam }; 1452e53bdfc0SManivannan Sadhasivam 1453e53bdfc0SManivannan Sadhasivam pcie2_phy: phy@1c16000 { 1454e53bdfc0SManivannan Sadhasivam compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 1455e53bdfc0SManivannan Sadhasivam reg = <0 0x1c16000 0 0x1c0>; 1456e53bdfc0SManivannan Sadhasivam #address-cells = <2>; 1457e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1458e53bdfc0SManivannan Sadhasivam ranges; 1459e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1460e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1461e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1462e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1463e53bdfc0SManivannan Sadhasivam clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1464e53bdfc0SManivannan Sadhasivam 1465e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_2_PHY_BCR>; 1466e53bdfc0SManivannan Sadhasivam reset-names = "phy"; 1467e53bdfc0SManivannan Sadhasivam 1468e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1469e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <100000000>; 1470e53bdfc0SManivannan Sadhasivam 1471e53bdfc0SManivannan Sadhasivam status = "disabled"; 1472e53bdfc0SManivannan Sadhasivam 1473*dc2f8636SKonrad Dybcio pcie2_lane: lanes@1c16200 { 1474e53bdfc0SManivannan Sadhasivam reg = <0 0x1c16200 0 0x170>, /* tx0 */ 1475e53bdfc0SManivannan Sadhasivam <0 0x1c16400 0 0x200>, /* rx0 */ 1476e53bdfc0SManivannan Sadhasivam <0 0x1c16a00 0 0x1f0>, /* pcs */ 1477e53bdfc0SManivannan Sadhasivam <0 0x1c16600 0 0x170>, /* tx1 */ 1478e53bdfc0SManivannan Sadhasivam <0 0x1c16800 0 0x200>, /* rx1 */ 1479e53bdfc0SManivannan Sadhasivam <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1480e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 1481e53bdfc0SManivannan Sadhasivam clock-names = "pipe0"; 1482e53bdfc0SManivannan Sadhasivam 1483e53bdfc0SManivannan Sadhasivam #phy-cells = <0>; 1484e53bdfc0SManivannan Sadhasivam clock-output-names = "pcie_2_pipe_clk"; 1485e53bdfc0SManivannan Sadhasivam }; 1486e53bdfc0SManivannan Sadhasivam }; 1487e53bdfc0SManivannan Sadhasivam 14886b9afd8fSJonathan Marek ufs_mem_hc: ufshc@1d84000 { 1489b7e2fba0SBryan O'Donoghue compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 1490b7e2fba0SBryan O'Donoghue "jedec,ufs-2.0"; 1491b7e2fba0SBryan O'Donoghue reg = <0 0x01d84000 0 0x3000>; 1492b7e2fba0SBryan O'Donoghue interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1493b7e2fba0SBryan O'Donoghue phys = <&ufs_mem_phy_lanes>; 1494b7e2fba0SBryan O'Donoghue phy-names = "ufsphy"; 1495b7e2fba0SBryan O'Donoghue lanes-per-direction = <2>; 1496b7e2fba0SBryan O'Donoghue #reset-cells = <1>; 1497b7e2fba0SBryan O'Donoghue resets = <&gcc GCC_UFS_PHY_BCR>; 1498b7e2fba0SBryan O'Donoghue reset-names = "rst"; 1499b7e2fba0SBryan O'Donoghue 1500b7e2fba0SBryan O'Donoghue power-domains = <&gcc UFS_PHY_GDSC>; 1501b7e2fba0SBryan O'Donoghue 1502a89441fcSJonathan Marek iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 1503a89441fcSJonathan Marek 1504b7e2fba0SBryan O'Donoghue clock-names = 1505b7e2fba0SBryan O'Donoghue "core_clk", 1506b7e2fba0SBryan O'Donoghue "bus_aggr_clk", 1507b7e2fba0SBryan O'Donoghue "iface_clk", 1508b7e2fba0SBryan O'Donoghue "core_clk_unipro", 1509b7e2fba0SBryan O'Donoghue "ref_clk", 1510b7e2fba0SBryan O'Donoghue "tx_lane0_sync_clk", 1511b7e2fba0SBryan O'Donoghue "rx_lane0_sync_clk", 1512b7e2fba0SBryan O'Donoghue "rx_lane1_sync_clk"; 1513b7e2fba0SBryan O'Donoghue clocks = 1514b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_AXI_CLK>, 1515b7e2fba0SBryan O'Donoghue <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1516b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_AHB_CLK>, 1517b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1518b7e2fba0SBryan O'Donoghue <&rpmhcc RPMH_CXO_CLK>, 1519b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1520b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1521b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1522b7e2fba0SBryan O'Donoghue freq-table-hz = 1523b7e2fba0SBryan O'Donoghue <37500000 300000000>, 1524b7e2fba0SBryan O'Donoghue <0 0>, 1525b7e2fba0SBryan O'Donoghue <0 0>, 1526b7e2fba0SBryan O'Donoghue <37500000 300000000>, 1527b7e2fba0SBryan O'Donoghue <0 0>, 1528b7e2fba0SBryan O'Donoghue <0 0>, 1529b7e2fba0SBryan O'Donoghue <0 0>, 1530b7e2fba0SBryan O'Donoghue <0 0>; 1531b7e2fba0SBryan O'Donoghue 1532b7e2fba0SBryan O'Donoghue status = "disabled"; 1533b7e2fba0SBryan O'Donoghue }; 1534b7e2fba0SBryan O'Donoghue 1535b7e2fba0SBryan O'Donoghue ufs_mem_phy: phy@1d87000 { 1536b7e2fba0SBryan O'Donoghue compatible = "qcom,sm8250-qmp-ufs-phy"; 1537b7e2fba0SBryan O'Donoghue reg = <0 0x01d87000 0 0x1c0>; 1538b7e2fba0SBryan O'Donoghue #address-cells = <2>; 1539b7e2fba0SBryan O'Donoghue #size-cells = <2>; 1540b7e2fba0SBryan O'Donoghue ranges; 1541b7e2fba0SBryan O'Donoghue clock-names = "ref", 1542b7e2fba0SBryan O'Donoghue "ref_aux"; 1543b7e2fba0SBryan O'Donoghue clocks = <&rpmhcc RPMH_CXO_CLK>, 1544b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1545b7e2fba0SBryan O'Donoghue 1546b7e2fba0SBryan O'Donoghue resets = <&ufs_mem_hc 0>; 1547b7e2fba0SBryan O'Donoghue reset-names = "ufsphy"; 1548b7e2fba0SBryan O'Donoghue status = "disabled"; 1549b7e2fba0SBryan O'Donoghue 1550b7e2fba0SBryan O'Donoghue ufs_mem_phy_lanes: lanes@1d87400 { 1551b7e2fba0SBryan O'Donoghue reg = <0 0x01d87400 0 0x108>, 1552b7e2fba0SBryan O'Donoghue <0 0x01d87600 0 0x1e0>, 1553b7e2fba0SBryan O'Donoghue <0 0x01d87c00 0 0x1dc>, 1554b7e2fba0SBryan O'Donoghue <0 0x01d87800 0 0x108>, 1555b7e2fba0SBryan O'Donoghue <0 0x01d87a00 0 0x1e0>; 1556b7e2fba0SBryan O'Donoghue #phy-cells = <0>; 1557b7e2fba0SBryan O'Donoghue }; 1558b7e2fba0SBryan O'Donoghue }; 1559b7e2fba0SBryan O'Donoghue 1560e7e41a20SJonathan Marek ipa_virt: interconnect@1e00000 { 1561e7e41a20SJonathan Marek compatible = "qcom,sm8250-ipa-virt"; 1562e7e41a20SJonathan Marek reg = <0 0x01e00000 0 0x1000>; 1563e7e41a20SJonathan Marek #interconnect-cells = <1>; 1564e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1565e7e41a20SJonathan Marek }; 1566e7e41a20SJonathan Marek 1567dff0f49cSBjorn Andersson tcsr_mutex: hwlock@1f40000 { 1568dff0f49cSBjorn Andersson compatible = "qcom,tcsr-mutex"; 1569b9ec8cbcSJonathan Marek reg = <0x0 0x01f40000 0x0 0x40000>; 1570dff0f49cSBjorn Andersson #hwlock-cells = <1>; 157160378f1aSVenkata Narendra Kumar Gutta }; 157260378f1aSVenkata Narendra Kumar Gutta 1573768270caSSrinivas Kandagatla wsamacro: codec@3240000 { 1574768270caSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-wsa-macro"; 1575768270caSSrinivas Kandagatla reg = <0 0x03240000 0 0x1000>; 1576768270caSSrinivas Kandagatla clocks = <&audiocc 1>, 1577768270caSSrinivas Kandagatla <&audiocc 0>, 1578768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1579768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1580768270caSSrinivas Kandagatla <&aoncc 0>, 1581768270caSSrinivas Kandagatla <&vamacro>; 1582768270caSSrinivas Kandagatla 1583768270caSSrinivas Kandagatla clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 1584768270caSSrinivas Kandagatla 1585768270caSSrinivas Kandagatla #clock-cells = <0>; 1586768270caSSrinivas Kandagatla clock-frequency = <9600000>; 1587768270caSSrinivas Kandagatla clock-output-names = "mclk"; 1588768270caSSrinivas Kandagatla #sound-dai-cells = <1>; 1589768270caSSrinivas Kandagatla 1590768270caSSrinivas Kandagatla pinctrl-names = "default"; 1591768270caSSrinivas Kandagatla pinctrl-0 = <&wsa_swr_active>; 1592768270caSSrinivas Kandagatla }; 1593768270caSSrinivas Kandagatla 1594768270caSSrinivas Kandagatla swr0: soundwire-controller@3250000 { 1595768270caSSrinivas Kandagatla reg = <0 0x03250000 0 0x2000>; 1596768270caSSrinivas Kandagatla compatible = "qcom,soundwire-v1.5.1"; 1597768270caSSrinivas Kandagatla interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1598768270caSSrinivas Kandagatla clocks = <&wsamacro>; 1599768270caSSrinivas Kandagatla clock-names = "iface"; 1600768270caSSrinivas Kandagatla 1601768270caSSrinivas Kandagatla qcom,din-ports = <2>; 1602768270caSSrinivas Kandagatla qcom,dout-ports = <6>; 1603768270caSSrinivas Kandagatla 1604768270caSSrinivas Kandagatla qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 1605768270caSSrinivas Kandagatla qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 1606768270caSSrinivas Kandagatla qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 1607768270caSSrinivas Kandagatla qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 1608768270caSSrinivas Kandagatla 1609768270caSSrinivas Kandagatla #sound-dai-cells = <1>; 1610768270caSSrinivas Kandagatla #address-cells = <2>; 1611768270caSSrinivas Kandagatla #size-cells = <0>; 1612768270caSSrinivas Kandagatla }; 1613768270caSSrinivas Kandagatla 1614793bbd2dSSrinivas Kandagatla audiocc: clock-controller@3300000 { 1615793bbd2dSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-audiocc"; 1616793bbd2dSSrinivas Kandagatla reg = <0 0x03300000 0 0x30000>; 1617793bbd2dSSrinivas Kandagatla #clock-cells = <1>; 1618793bbd2dSSrinivas Kandagatla clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1619793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1620793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1621793bbd2dSSrinivas Kandagatla clock-names = "core", "audio", "bus"; 1622793bbd2dSSrinivas Kandagatla }; 1623793bbd2dSSrinivas Kandagatla 1624768270caSSrinivas Kandagatla vamacro: codec@3370000 { 1625768270caSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-va-macro"; 1626768270caSSrinivas Kandagatla reg = <0 0x03370000 0 0x1000>; 1627768270caSSrinivas Kandagatla clocks = <&aoncc 0>, 1628768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1629768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1630768270caSSrinivas Kandagatla 1631768270caSSrinivas Kandagatla clock-names = "mclk", "macro", "dcodec"; 1632768270caSSrinivas Kandagatla 1633768270caSSrinivas Kandagatla #clock-cells = <0>; 1634768270caSSrinivas Kandagatla clock-frequency = <9600000>; 1635768270caSSrinivas Kandagatla clock-output-names = "fsgen"; 1636768270caSSrinivas Kandagatla #sound-dai-cells = <1>; 1637768270caSSrinivas Kandagatla }; 1638768270caSSrinivas Kandagatla 1639793bbd2dSSrinivas Kandagatla aoncc: clock-controller@3380000 { 1640793bbd2dSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-aoncc"; 1641793bbd2dSSrinivas Kandagatla reg = <0 0x03380000 0 0x40000>; 1642793bbd2dSSrinivas Kandagatla #clock-cells = <1>; 1643793bbd2dSSrinivas Kandagatla clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1644793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1645793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1646793bbd2dSSrinivas Kandagatla clock-names = "core", "audio", "bus"; 1647793bbd2dSSrinivas Kandagatla }; 1648793bbd2dSSrinivas Kandagatla 16493160c1b8SSrinivas Kandagatla lpass_tlmm: pinctrl@33c0000{ 16503160c1b8SSrinivas Kandagatla compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 16513160c1b8SSrinivas Kandagatla reg = <0 0x033c0000 0x0 0x20000>, 16523160c1b8SSrinivas Kandagatla <0 0x03550000 0x0 0x10000>; 16533160c1b8SSrinivas Kandagatla gpio-controller; 16543160c1b8SSrinivas Kandagatla #gpio-cells = <2>; 16553160c1b8SSrinivas Kandagatla gpio-ranges = <&lpass_tlmm 0 0 14>; 16563160c1b8SSrinivas Kandagatla 16573160c1b8SSrinivas Kandagatla clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 16583160c1b8SSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 16593160c1b8SSrinivas Kandagatla clock-names = "core", "audio"; 16603160c1b8SSrinivas Kandagatla 16613160c1b8SSrinivas Kandagatla wsa_swr_active: wsa-swr-active-pins { 16623160c1b8SSrinivas Kandagatla clk { 16633160c1b8SSrinivas Kandagatla pins = "gpio10"; 16643160c1b8SSrinivas Kandagatla function = "wsa_swr_clk"; 16653160c1b8SSrinivas Kandagatla drive-strength = <2>; 16663160c1b8SSrinivas Kandagatla slew-rate = <1>; 16673160c1b8SSrinivas Kandagatla bias-disable; 16683160c1b8SSrinivas Kandagatla }; 16693160c1b8SSrinivas Kandagatla 16703160c1b8SSrinivas Kandagatla data { 16713160c1b8SSrinivas Kandagatla pins = "gpio11"; 16723160c1b8SSrinivas Kandagatla function = "wsa_swr_data"; 16733160c1b8SSrinivas Kandagatla drive-strength = <2>; 16743160c1b8SSrinivas Kandagatla slew-rate = <1>; 16753160c1b8SSrinivas Kandagatla bias-bus-hold; 16763160c1b8SSrinivas Kandagatla 16773160c1b8SSrinivas Kandagatla }; 16783160c1b8SSrinivas Kandagatla }; 16793160c1b8SSrinivas Kandagatla 16803160c1b8SSrinivas Kandagatla wsa_swr_sleep: wsa-swr-sleep-pins { 16813160c1b8SSrinivas Kandagatla clk { 16823160c1b8SSrinivas Kandagatla pins = "gpio10"; 16833160c1b8SSrinivas Kandagatla function = "wsa_swr_clk"; 16843160c1b8SSrinivas Kandagatla drive-strength = <2>; 16853160c1b8SSrinivas Kandagatla input-enable; 16863160c1b8SSrinivas Kandagatla bias-pull-down; 16873160c1b8SSrinivas Kandagatla }; 16883160c1b8SSrinivas Kandagatla 16893160c1b8SSrinivas Kandagatla data { 16903160c1b8SSrinivas Kandagatla pins = "gpio11"; 16913160c1b8SSrinivas Kandagatla function = "wsa_swr_data"; 16923160c1b8SSrinivas Kandagatla drive-strength = <2>; 16933160c1b8SSrinivas Kandagatla input-enable; 16943160c1b8SSrinivas Kandagatla bias-pull-down; 16953160c1b8SSrinivas Kandagatla 16963160c1b8SSrinivas Kandagatla }; 16973160c1b8SSrinivas Kandagatla }; 16983160c1b8SSrinivas Kandagatla 16993160c1b8SSrinivas Kandagatla dmic01_active: dmic01-active-pins { 17003160c1b8SSrinivas Kandagatla clk { 17013160c1b8SSrinivas Kandagatla pins = "gpio6"; 17023160c1b8SSrinivas Kandagatla function = "dmic1_clk"; 17033160c1b8SSrinivas Kandagatla drive-strength = <8>; 17043160c1b8SSrinivas Kandagatla output-high; 17053160c1b8SSrinivas Kandagatla }; 17063160c1b8SSrinivas Kandagatla data { 17073160c1b8SSrinivas Kandagatla pins = "gpio7"; 17083160c1b8SSrinivas Kandagatla function = "dmic1_data"; 17093160c1b8SSrinivas Kandagatla drive-strength = <8>; 17103160c1b8SSrinivas Kandagatla input-enable; 17113160c1b8SSrinivas Kandagatla }; 17123160c1b8SSrinivas Kandagatla }; 17133160c1b8SSrinivas Kandagatla 17143160c1b8SSrinivas Kandagatla dmic01_sleep: dmic01-sleep-pins { 17153160c1b8SSrinivas Kandagatla clk { 17163160c1b8SSrinivas Kandagatla pins = "gpio6"; 17173160c1b8SSrinivas Kandagatla function = "dmic1_clk"; 17183160c1b8SSrinivas Kandagatla drive-strength = <2>; 17193160c1b8SSrinivas Kandagatla bias-disable; 17203160c1b8SSrinivas Kandagatla output-low; 17213160c1b8SSrinivas Kandagatla }; 17223160c1b8SSrinivas Kandagatla 17233160c1b8SSrinivas Kandagatla data { 17243160c1b8SSrinivas Kandagatla pins = "gpio7"; 17253160c1b8SSrinivas Kandagatla function = "dmic1_data"; 17263160c1b8SSrinivas Kandagatla drive-strength = <2>; 17273160c1b8SSrinivas Kandagatla pull-down; 17283160c1b8SSrinivas Kandagatla input-enable; 17293160c1b8SSrinivas Kandagatla }; 17303160c1b8SSrinivas Kandagatla }; 17313160c1b8SSrinivas Kandagatla }; 17323160c1b8SSrinivas Kandagatla 173304a3605bSJonathan Marek gpu: gpu@3d00000 { 173404a3605bSJonathan Marek compatible = "qcom,adreno-650.2", 17357c1dffd4SDmitry Baryshkov "qcom,adreno"; 173604a3605bSJonathan Marek #stream-id-cells = <16>; 173704a3605bSJonathan Marek 173804a3605bSJonathan Marek reg = <0 0x03d00000 0 0x40000>; 173904a3605bSJonathan Marek reg-names = "kgsl_3d0_reg_memory"; 174004a3605bSJonathan Marek 174104a3605bSJonathan Marek interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 174204a3605bSJonathan Marek 174304a3605bSJonathan Marek iommus = <&adreno_smmu 0 0x401>; 174404a3605bSJonathan Marek 174504a3605bSJonathan Marek operating-points-v2 = <&gpu_opp_table>; 174604a3605bSJonathan Marek 174704a3605bSJonathan Marek qcom,gmu = <&gmu>; 174804a3605bSJonathan Marek 174904a3605bSJonathan Marek zap-shader { 175004a3605bSJonathan Marek memory-region = <&gpu_mem>; 175104a3605bSJonathan Marek }; 175204a3605bSJonathan Marek 175304a3605bSJonathan Marek /* note: downstream checks gpu binning for 670 Mhz */ 175404a3605bSJonathan Marek gpu_opp_table: opp-table { 175504a3605bSJonathan Marek compatible = "operating-points-v2"; 175604a3605bSJonathan Marek 175704a3605bSJonathan Marek opp-670000000 { 175804a3605bSJonathan Marek opp-hz = /bits/ 64 <670000000>; 175904a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 176004a3605bSJonathan Marek }; 176104a3605bSJonathan Marek 176204a3605bSJonathan Marek opp-587000000 { 176304a3605bSJonathan Marek opp-hz = /bits/ 64 <587000000>; 176404a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 176504a3605bSJonathan Marek }; 176604a3605bSJonathan Marek 176704a3605bSJonathan Marek opp-525000000 { 176804a3605bSJonathan Marek opp-hz = /bits/ 64 <525000000>; 176904a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 177004a3605bSJonathan Marek }; 177104a3605bSJonathan Marek 177204a3605bSJonathan Marek opp-490000000 { 177304a3605bSJonathan Marek opp-hz = /bits/ 64 <490000000>; 177404a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 177504a3605bSJonathan Marek }; 177604a3605bSJonathan Marek 177704a3605bSJonathan Marek opp-441600000 { 177804a3605bSJonathan Marek opp-hz = /bits/ 64 <441600000>; 177904a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 178004a3605bSJonathan Marek }; 178104a3605bSJonathan Marek 178204a3605bSJonathan Marek opp-400000000 { 178304a3605bSJonathan Marek opp-hz = /bits/ 64 <400000000>; 178404a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 178504a3605bSJonathan Marek }; 178604a3605bSJonathan Marek 178704a3605bSJonathan Marek opp-305000000 { 178804a3605bSJonathan Marek opp-hz = /bits/ 64 <305000000>; 178904a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 179004a3605bSJonathan Marek }; 179104a3605bSJonathan Marek }; 179204a3605bSJonathan Marek }; 179304a3605bSJonathan Marek 179404a3605bSJonathan Marek gmu: gmu@3d6a000 { 179504a3605bSJonathan Marek compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 179604a3605bSJonathan Marek 179704a3605bSJonathan Marek reg = <0 0x03d6a000 0 0x30000>, 179804a3605bSJonathan Marek <0 0x3de0000 0 0x10000>, 179904a3605bSJonathan Marek <0 0xb290000 0 0x10000>, 180004a3605bSJonathan Marek <0 0xb490000 0 0x10000>; 180104a3605bSJonathan Marek reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 180204a3605bSJonathan Marek 180304a3605bSJonathan Marek interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 180404a3605bSJonathan Marek <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 180504a3605bSJonathan Marek interrupt-names = "hfi", "gmu"; 180604a3605bSJonathan Marek 18070e6aa9dbSJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 18080e6aa9dbSJonathan Marek <&gpucc GPU_CC_CX_GMU_CLK>, 18090e6aa9dbSJonathan Marek <&gpucc GPU_CC_CXO_CLK>, 181004a3605bSJonathan Marek <&gcc GCC_DDRSS_GPU_AXI_CLK>, 181104a3605bSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 181204a3605bSJonathan Marek clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 181304a3605bSJonathan Marek 18140e6aa9dbSJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>, 18150e6aa9dbSJonathan Marek <&gpucc GPU_GX_GDSC>; 181604a3605bSJonathan Marek power-domain-names = "cx", "gx"; 181704a3605bSJonathan Marek 181804a3605bSJonathan Marek iommus = <&adreno_smmu 5 0x400>; 181904a3605bSJonathan Marek 182004a3605bSJonathan Marek operating-points-v2 = <&gmu_opp_table>; 182104a3605bSJonathan Marek 182204a3605bSJonathan Marek gmu_opp_table: opp-table { 182304a3605bSJonathan Marek compatible = "operating-points-v2"; 182404a3605bSJonathan Marek 182504a3605bSJonathan Marek opp-200000000 { 182604a3605bSJonathan Marek opp-hz = /bits/ 64 <200000000>; 182704a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 182804a3605bSJonathan Marek }; 182904a3605bSJonathan Marek }; 183004a3605bSJonathan Marek }; 183104a3605bSJonathan Marek 183204a3605bSJonathan Marek gpucc: clock-controller@3d90000 { 183304a3605bSJonathan Marek compatible = "qcom,sm8250-gpucc"; 183404a3605bSJonathan Marek reg = <0 0x03d90000 0 0x9000>; 183504a3605bSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>, 183604a3605bSJonathan Marek <&gcc GCC_GPU_GPLL0_CLK_SRC>, 183704a3605bSJonathan Marek <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 183804a3605bSJonathan Marek clock-names = "bi_tcxo", 183904a3605bSJonathan Marek "gcc_gpu_gpll0_clk_src", 184004a3605bSJonathan Marek "gcc_gpu_gpll0_div_clk_src"; 184104a3605bSJonathan Marek #clock-cells = <1>; 184204a3605bSJonathan Marek #reset-cells = <1>; 184304a3605bSJonathan Marek #power-domain-cells = <1>; 184404a3605bSJonathan Marek }; 184504a3605bSJonathan Marek 184604a3605bSJonathan Marek adreno_smmu: iommu@3da0000 { 184704a3605bSJonathan Marek compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 184804a3605bSJonathan Marek reg = <0 0x03da0000 0 0x10000>; 184904a3605bSJonathan Marek #iommu-cells = <2>; 185004a3605bSJonathan Marek #global-interrupts = <2>; 185104a3605bSJonathan Marek interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 185204a3605bSJonathan Marek <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 185304a3605bSJonathan Marek <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 185404a3605bSJonathan Marek <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 185504a3605bSJonathan Marek <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 185604a3605bSJonathan Marek <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 185704a3605bSJonathan Marek <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 185804a3605bSJonathan Marek <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 185904a3605bSJonathan Marek <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 186004a3605bSJonathan Marek <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 18610e6aa9dbSJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 186204a3605bSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 186304a3605bSJonathan Marek <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 186404a3605bSJonathan Marek clock-names = "ahb", "bus", "iface"; 186504a3605bSJonathan Marek 18660e6aa9dbSJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>; 186704a3605bSJonathan Marek }; 186804a3605bSJonathan Marek 186923a89037SBjorn Andersson slpi: remoteproc@5c00000 { 187023a89037SBjorn Andersson compatible = "qcom,sm8250-slpi-pas"; 187123a89037SBjorn Andersson reg = <0 0x05c00000 0 0x4000>; 187223a89037SBjorn Andersson 187323a89037SBjorn Andersson interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 187423a89037SBjorn Andersson <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 187523a89037SBjorn Andersson <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 187623a89037SBjorn Andersson <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 187723a89037SBjorn Andersson <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 187823a89037SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 187923a89037SBjorn Andersson "handover", "stop-ack"; 188023a89037SBjorn Andersson 188123a89037SBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>; 188223a89037SBjorn Andersson clock-names = "xo"; 188323a89037SBjorn Andersson 188423a89037SBjorn Andersson power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, 188523a89037SBjorn Andersson <&rpmhpd SM8250_LCX>, 188623a89037SBjorn Andersson <&rpmhpd SM8250_LMX>; 188723a89037SBjorn Andersson power-domain-names = "load_state", "lcx", "lmx"; 188823a89037SBjorn Andersson 188923a89037SBjorn Andersson memory-region = <&slpi_mem>; 189023a89037SBjorn Andersson 189123a89037SBjorn Andersson qcom,smem-states = <&smp2p_slpi_out 0>; 189223a89037SBjorn Andersson qcom,smem-state-names = "stop"; 189323a89037SBjorn Andersson 189423a89037SBjorn Andersson status = "disabled"; 189523a89037SBjorn Andersson 189623a89037SBjorn Andersson glink-edge { 189723a89037SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 189823a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 189923a89037SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 190023a89037SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_SLPI 190123a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 190223a89037SBjorn Andersson 190325695808SJonathan Marek label = "slpi"; 190423a89037SBjorn Andersson qcom,remote-pid = <3>; 190525695808SJonathan Marek 190625695808SJonathan Marek fastrpc { 190725695808SJonathan Marek compatible = "qcom,fastrpc"; 190825695808SJonathan Marek qcom,glink-channels = "fastrpcglink-apps-dsp"; 190925695808SJonathan Marek label = "sdsp"; 191025695808SJonathan Marek #address-cells = <1>; 191125695808SJonathan Marek #size-cells = <0>; 191225695808SJonathan Marek 191325695808SJonathan Marek compute-cb@1 { 191425695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 191525695808SJonathan Marek reg = <1>; 191625695808SJonathan Marek iommus = <&apps_smmu 0x0541 0x0>; 191725695808SJonathan Marek }; 191825695808SJonathan Marek 191925695808SJonathan Marek compute-cb@2 { 192025695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 192125695808SJonathan Marek reg = <2>; 192225695808SJonathan Marek iommus = <&apps_smmu 0x0542 0x0>; 192325695808SJonathan Marek }; 192425695808SJonathan Marek 192525695808SJonathan Marek compute-cb@3 { 192625695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 192725695808SJonathan Marek reg = <3>; 192825695808SJonathan Marek iommus = <&apps_smmu 0x0543 0x0>; 192925695808SJonathan Marek /* note: shared-cb = <4> in downstream */ 193025695808SJonathan Marek }; 193125695808SJonathan Marek }; 193223a89037SBjorn Andersson }; 193323a89037SBjorn Andersson }; 193423a89037SBjorn Andersson 193523a89037SBjorn Andersson cdsp: remoteproc@8300000 { 193623a89037SBjorn Andersson compatible = "qcom,sm8250-cdsp-pas"; 193723a89037SBjorn Andersson reg = <0 0x08300000 0 0x10000>; 193823a89037SBjorn Andersson 193923a89037SBjorn Andersson interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 194023a89037SBjorn Andersson <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 194123a89037SBjorn Andersson <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 194223a89037SBjorn Andersson <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 194323a89037SBjorn Andersson <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 194423a89037SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 194523a89037SBjorn Andersson "handover", "stop-ack"; 194623a89037SBjorn Andersson 194723a89037SBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>; 194823a89037SBjorn Andersson clock-names = "xo"; 194923a89037SBjorn Andersson 195023a89037SBjorn Andersson power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, 195123a89037SBjorn Andersson <&rpmhpd SM8250_CX>; 195223a89037SBjorn Andersson power-domain-names = "load_state", "cx"; 195323a89037SBjorn Andersson 195423a89037SBjorn Andersson memory-region = <&cdsp_mem>; 195523a89037SBjorn Andersson 195623a89037SBjorn Andersson qcom,smem-states = <&smp2p_cdsp_out 0>; 195723a89037SBjorn Andersson qcom,smem-state-names = "stop"; 195823a89037SBjorn Andersson 195923a89037SBjorn Andersson status = "disabled"; 196023a89037SBjorn Andersson 196123a89037SBjorn Andersson glink-edge { 196223a89037SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 196323a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 196423a89037SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 196523a89037SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_CDSP 196623a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 196723a89037SBjorn Andersson 196825695808SJonathan Marek label = "cdsp"; 196923a89037SBjorn Andersson qcom,remote-pid = <5>; 197025695808SJonathan Marek 197125695808SJonathan Marek fastrpc { 197225695808SJonathan Marek compatible = "qcom,fastrpc"; 197325695808SJonathan Marek qcom,glink-channels = "fastrpcglink-apps-dsp"; 197425695808SJonathan Marek label = "cdsp"; 197525695808SJonathan Marek #address-cells = <1>; 197625695808SJonathan Marek #size-cells = <0>; 197725695808SJonathan Marek 197825695808SJonathan Marek compute-cb@1 { 197925695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 198025695808SJonathan Marek reg = <1>; 198125695808SJonathan Marek iommus = <&apps_smmu 0x1001 0x0460>; 198225695808SJonathan Marek }; 198325695808SJonathan Marek 198425695808SJonathan Marek compute-cb@2 { 198525695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 198625695808SJonathan Marek reg = <2>; 198725695808SJonathan Marek iommus = <&apps_smmu 0x1002 0x0460>; 198825695808SJonathan Marek }; 198925695808SJonathan Marek 199025695808SJonathan Marek compute-cb@3 { 199125695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 199225695808SJonathan Marek reg = <3>; 199325695808SJonathan Marek iommus = <&apps_smmu 0x1003 0x0460>; 199425695808SJonathan Marek }; 199525695808SJonathan Marek 199625695808SJonathan Marek compute-cb@4 { 199725695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 199825695808SJonathan Marek reg = <4>; 199925695808SJonathan Marek iommus = <&apps_smmu 0x1004 0x0460>; 200025695808SJonathan Marek }; 200125695808SJonathan Marek 200225695808SJonathan Marek compute-cb@5 { 200325695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 200425695808SJonathan Marek reg = <5>; 200525695808SJonathan Marek iommus = <&apps_smmu 0x1005 0x0460>; 200625695808SJonathan Marek }; 200725695808SJonathan Marek 200825695808SJonathan Marek compute-cb@6 { 200925695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 201025695808SJonathan Marek reg = <6>; 201125695808SJonathan Marek iommus = <&apps_smmu 0x1006 0x0460>; 201225695808SJonathan Marek }; 201325695808SJonathan Marek 201425695808SJonathan Marek compute-cb@7 { 201525695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 201625695808SJonathan Marek reg = <7>; 201725695808SJonathan Marek iommus = <&apps_smmu 0x1007 0x0460>; 201825695808SJonathan Marek }; 201925695808SJonathan Marek 202025695808SJonathan Marek compute-cb@8 { 202125695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 202225695808SJonathan Marek reg = <8>; 202325695808SJonathan Marek iommus = <&apps_smmu 0x1008 0x0460>; 202425695808SJonathan Marek }; 202525695808SJonathan Marek 202625695808SJonathan Marek /* note: secure cb9 in downstream */ 202725695808SJonathan Marek }; 202823a89037SBjorn Andersson }; 202923a89037SBjorn Andersson }; 203023a89037SBjorn Andersson 2031590a135eSSrinivas Kandagatla sound: sound { 2032590a135eSSrinivas Kandagatla }; 2033590a135eSSrinivas Kandagatla 203446a6f297SJonathan Marek usb_1_hsphy: phy@88e3000 { 203546a6f297SJonathan Marek compatible = "qcom,sm8250-usb-hs-phy", 203646a6f297SJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 203746a6f297SJonathan Marek reg = <0 0x088e3000 0 0x400>; 203846a6f297SJonathan Marek status = "disabled"; 203946a6f297SJonathan Marek #phy-cells = <0>; 204046a6f297SJonathan Marek 204146a6f297SJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 204246a6f297SJonathan Marek clock-names = "ref"; 204346a6f297SJonathan Marek 204446a6f297SJonathan Marek resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 204546a6f297SJonathan Marek }; 204646a6f297SJonathan Marek 204746a6f297SJonathan Marek usb_2_hsphy: phy@88e4000 { 204846a6f297SJonathan Marek compatible = "qcom,sm8250-usb-hs-phy", 204946a6f297SJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 205046a6f297SJonathan Marek reg = <0 0x088e4000 0 0x400>; 205146a6f297SJonathan Marek status = "disabled"; 205246a6f297SJonathan Marek #phy-cells = <0>; 205346a6f297SJonathan Marek 205446a6f297SJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 205546a6f297SJonathan Marek clock-names = "ref"; 205646a6f297SJonathan Marek 205746a6f297SJonathan Marek resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 205846a6f297SJonathan Marek }; 205946a6f297SJonathan Marek 206046a6f297SJonathan Marek usb_1_qmpphy: phy@88e9000 { 20615aa0d1beSDmitry Baryshkov compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 206246a6f297SJonathan Marek reg = <0 0x088e9000 0 0x200>, 20635aa0d1beSDmitry Baryshkov <0 0x088e8000 0 0x40>, 20645aa0d1beSDmitry Baryshkov <0 0x088ea000 0 0x200>; 206546a6f297SJonathan Marek status = "disabled"; 206646a6f297SJonathan Marek #address-cells = <2>; 206746a6f297SJonathan Marek #size-cells = <2>; 206846a6f297SJonathan Marek ranges; 206946a6f297SJonathan Marek 207046a6f297SJonathan Marek clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 207146a6f297SJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 207246a6f297SJonathan Marek <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 207346a6f297SJonathan Marek clock-names = "aux", "ref_clk_src", "com_aux"; 207446a6f297SJonathan Marek 207546a6f297SJonathan Marek resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 207646a6f297SJonathan Marek <&gcc GCC_USB3_PHY_PRIM_BCR>; 207746a6f297SJonathan Marek reset-names = "phy", "common"; 207846a6f297SJonathan Marek 20795aa0d1beSDmitry Baryshkov usb_1_ssphy: usb3-phy@88e9200 { 208046a6f297SJonathan Marek reg = <0 0x088e9200 0 0x200>, 208146a6f297SJonathan Marek <0 0x088e9400 0 0x200>, 208246a6f297SJonathan Marek <0 0x088e9c00 0 0x400>, 208346a6f297SJonathan Marek <0 0x088e9600 0 0x200>, 208446a6f297SJonathan Marek <0 0x088e9800 0 0x200>, 208546a6f297SJonathan Marek <0 0x088e9a00 0 0x100>; 20867178d4ccSJonathan Marek #clock-cells = <0>; 208746a6f297SJonathan Marek #phy-cells = <0>; 208846a6f297SJonathan Marek clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 208946a6f297SJonathan Marek clock-names = "pipe0"; 209046a6f297SJonathan Marek clock-output-names = "usb3_phy_pipe_clk_src"; 209146a6f297SJonathan Marek }; 20925aa0d1beSDmitry Baryshkov 20935aa0d1beSDmitry Baryshkov dp_phy: dp-phy@88ea200 { 20945aa0d1beSDmitry Baryshkov reg = <0 0x088ea200 0 0x200>, 20955aa0d1beSDmitry Baryshkov <0 0x088ea400 0 0x200>, 20965aa0d1beSDmitry Baryshkov <0 0x088eac00 0 0x400>, 20975aa0d1beSDmitry Baryshkov <0 0x088ea600 0 0x200>, 20985aa0d1beSDmitry Baryshkov <0 0x088ea800 0 0x200>, 20995aa0d1beSDmitry Baryshkov <0 0x088eaa00 0 0x100>; 21005aa0d1beSDmitry Baryshkov #phy-cells = <0>; 21015aa0d1beSDmitry Baryshkov #clock-cells = <1>; 21025aa0d1beSDmitry Baryshkov clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 21035aa0d1beSDmitry Baryshkov clock-names = "pipe0"; 21045aa0d1beSDmitry Baryshkov clock-output-names = "usb3_phy_pipe_clk_src"; 21055aa0d1beSDmitry Baryshkov }; 210646a6f297SJonathan Marek }; 210746a6f297SJonathan Marek 210846a6f297SJonathan Marek usb_2_qmpphy: phy@88eb000 { 210946a6f297SJonathan Marek compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 211046a6f297SJonathan Marek reg = <0 0x088eb000 0 0x200>; 211146a6f297SJonathan Marek status = "disabled"; 211246a6f297SJonathan Marek #address-cells = <2>; 211346a6f297SJonathan Marek #size-cells = <2>; 211446a6f297SJonathan Marek ranges; 211546a6f297SJonathan Marek 211646a6f297SJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 211746a6f297SJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 211846a6f297SJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_EN>, 211946a6f297SJonathan Marek <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 212046a6f297SJonathan Marek clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 212146a6f297SJonathan Marek 212246a6f297SJonathan Marek resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 212346a6f297SJonathan Marek <&gcc GCC_USB3_PHY_SEC_BCR>; 212446a6f297SJonathan Marek reset-names = "phy", "common"; 212546a6f297SJonathan Marek 212646a6f297SJonathan Marek usb_2_ssphy: lane@88eb200 { 212746a6f297SJonathan Marek reg = <0 0x088eb200 0 0x200>, 212846a6f297SJonathan Marek <0 0x088eb400 0 0x200>, 212946a6f297SJonathan Marek <0 0x088eb800 0 0x800>; 21307178d4ccSJonathan Marek #clock-cells = <0>; 213146a6f297SJonathan Marek #phy-cells = <0>; 213246a6f297SJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 213346a6f297SJonathan Marek clock-names = "pipe0"; 213446a6f297SJonathan Marek clock-output-names = "usb3_uni_phy_pipe_clk_src"; 213546a6f297SJonathan Marek }; 213646a6f297SJonathan Marek }; 213746a6f297SJonathan Marek 2138c4cf0300SManivannan Sadhasivam sdhc_2: sdhci@8804000 { 2139c4cf0300SManivannan Sadhasivam compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 2140c4cf0300SManivannan Sadhasivam reg = <0 0x08804000 0 0x1000>; 2141c4cf0300SManivannan Sadhasivam 2142c4cf0300SManivannan Sadhasivam interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2143c4cf0300SManivannan Sadhasivam <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2144c4cf0300SManivannan Sadhasivam interrupt-names = "hc_irq", "pwr_irq"; 2145c4cf0300SManivannan Sadhasivam 2146c4cf0300SManivannan Sadhasivam clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2147c4cf0300SManivannan Sadhasivam <&gcc GCC_SDCC2_APPS_CLK>, 214874097d80SDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK>; 2149c4cf0300SManivannan Sadhasivam clock-names = "iface", "core", "xo"; 2150c4cf0300SManivannan Sadhasivam iommus = <&apps_smmu 0x4a0 0x0>; 2151c4cf0300SManivannan Sadhasivam qcom,dll-config = <0x0007642c>; 2152c4cf0300SManivannan Sadhasivam qcom,ddr-config = <0x80040868>; 2153c4cf0300SManivannan Sadhasivam power-domains = <&rpmhpd SM8250_CX>; 2154c4cf0300SManivannan Sadhasivam operating-points-v2 = <&sdhc2_opp_table>; 2155c4cf0300SManivannan Sadhasivam 2156c4cf0300SManivannan Sadhasivam status = "disabled"; 2157c4cf0300SManivannan Sadhasivam 2158c4cf0300SManivannan Sadhasivam sdhc2_opp_table: sdhc2-opp-table { 2159c4cf0300SManivannan Sadhasivam compatible = "operating-points-v2"; 2160c4cf0300SManivannan Sadhasivam 2161c4cf0300SManivannan Sadhasivam opp-19200000 { 2162c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <19200000>; 2163c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_min_svs>; 2164c4cf0300SManivannan Sadhasivam }; 2165c4cf0300SManivannan Sadhasivam 2166c4cf0300SManivannan Sadhasivam opp-50000000 { 2167c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <50000000>; 2168c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_low_svs>; 2169c4cf0300SManivannan Sadhasivam }; 2170c4cf0300SManivannan Sadhasivam 2171c4cf0300SManivannan Sadhasivam opp-100000000 { 2172c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <100000000>; 2173c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_svs>; 2174c4cf0300SManivannan Sadhasivam }; 2175c4cf0300SManivannan Sadhasivam 2176c4cf0300SManivannan Sadhasivam opp-202000000 { 2177c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <202000000>; 2178c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_svs_l1>; 2179c4cf0300SManivannan Sadhasivam }; 2180c4cf0300SManivannan Sadhasivam }; 2181c4cf0300SManivannan Sadhasivam }; 2182c4cf0300SManivannan Sadhasivam 2183e7e41a20SJonathan Marek dc_noc: interconnect@90c0000 { 2184e7e41a20SJonathan Marek compatible = "qcom,sm8250-dc-noc"; 2185e7e41a20SJonathan Marek reg = <0 0x090c0000 0 0x4200>; 2186e7e41a20SJonathan Marek #interconnect-cells = <1>; 2187e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 2188e7e41a20SJonathan Marek }; 2189e7e41a20SJonathan Marek 2190e7e41a20SJonathan Marek gem_noc: interconnect@9100000 { 2191e7e41a20SJonathan Marek compatible = "qcom,sm8250-gem-noc"; 2192e7e41a20SJonathan Marek reg = <0 0x09100000 0 0xb4000>; 2193e7e41a20SJonathan Marek #interconnect-cells = <1>; 2194e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 2195e7e41a20SJonathan Marek }; 2196e7e41a20SJonathan Marek 2197e7e41a20SJonathan Marek npu_noc: interconnect@9990000 { 2198e7e41a20SJonathan Marek compatible = "qcom,sm8250-npu-noc"; 2199e7e41a20SJonathan Marek reg = <0 0x09990000 0 0x1600>; 2200e7e41a20SJonathan Marek #interconnect-cells = <1>; 2201e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 2202e7e41a20SJonathan Marek }; 2203e7e41a20SJonathan Marek 220446a6f297SJonathan Marek usb_1: usb@a6f8800 { 220546a6f297SJonathan Marek compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 220646a6f297SJonathan Marek reg = <0 0x0a6f8800 0 0x400>; 220746a6f297SJonathan Marek status = "disabled"; 220846a6f297SJonathan Marek #address-cells = <2>; 220946a6f297SJonathan Marek #size-cells = <2>; 221046a6f297SJonathan Marek ranges; 221146a6f297SJonathan Marek dma-ranges; 221246a6f297SJonathan Marek 221346a6f297SJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 221446a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_MASTER_CLK>, 221546a6f297SJonathan Marek <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 221646a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 221746a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 221846a6f297SJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_EN>; 221946a6f297SJonathan Marek clock-names = "cfg_noc", "core", "iface", "mock_utmi", 222046a6f297SJonathan Marek "sleep", "xo"; 222146a6f297SJonathan Marek 222246a6f297SJonathan Marek assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 222346a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_MASTER_CLK>; 222446a6f297SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 222546a6f297SJonathan Marek 222646a6f297SJonathan Marek interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 222746a6f297SJonathan Marek <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 222846a6f297SJonathan Marek <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 222946a6f297SJonathan Marek <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 223046a6f297SJonathan Marek interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 223146a6f297SJonathan Marek "dm_hs_phy_irq", "ss_phy_irq"; 223246a6f297SJonathan Marek 223346a6f297SJonathan Marek power-domains = <&gcc USB30_PRIM_GDSC>; 223446a6f297SJonathan Marek 223546a6f297SJonathan Marek resets = <&gcc GCC_USB30_PRIM_BCR>; 223646a6f297SJonathan Marek 223746a6f297SJonathan Marek usb_1_dwc3: dwc3@a600000 { 223846a6f297SJonathan Marek compatible = "snps,dwc3"; 223946a6f297SJonathan Marek reg = <0 0x0a600000 0 0xcd00>; 224046a6f297SJonathan Marek interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 224146a6f297SJonathan Marek iommus = <&apps_smmu 0x0 0x0>; 224246a6f297SJonathan Marek snps,dis_u2_susphy_quirk; 224346a6f297SJonathan Marek snps,dis_enblslpm_quirk; 224446a6f297SJonathan Marek phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 224546a6f297SJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 224646a6f297SJonathan Marek }; 224746a6f297SJonathan Marek }; 224846a6f297SJonathan Marek 22490085a33aSManivannan Sadhasivam system-cache-controller@9200000 { 22500085a33aSManivannan Sadhasivam compatible = "qcom,sm8250-llcc"; 22510085a33aSManivannan Sadhasivam reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 22520085a33aSManivannan Sadhasivam reg-names = "llcc_base", "llcc_broadcast_base"; 22530085a33aSManivannan Sadhasivam }; 22540085a33aSManivannan Sadhasivam 225546a6f297SJonathan Marek usb_2: usb@a8f8800 { 225646a6f297SJonathan Marek compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 225746a6f297SJonathan Marek reg = <0 0x0a8f8800 0 0x400>; 225846a6f297SJonathan Marek status = "disabled"; 225946a6f297SJonathan Marek #address-cells = <2>; 226046a6f297SJonathan Marek #size-cells = <2>; 226146a6f297SJonathan Marek ranges; 226246a6f297SJonathan Marek dma-ranges; 226346a6f297SJonathan Marek 226446a6f297SJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 226546a6f297SJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>, 226646a6f297SJonathan Marek <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 226746a6f297SJonathan Marek <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 226846a6f297SJonathan Marek <&gcc GCC_USB30_SEC_SLEEP_CLK>, 226946a6f297SJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_EN>; 227046a6f297SJonathan Marek clock-names = "cfg_noc", "core", "iface", "mock_utmi", 227146a6f297SJonathan Marek "sleep", "xo"; 227246a6f297SJonathan Marek 227346a6f297SJonathan Marek assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 227446a6f297SJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>; 227546a6f297SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 227646a6f297SJonathan Marek 227746a6f297SJonathan Marek interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 227846a6f297SJonathan Marek <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 227946a6f297SJonathan Marek <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 228046a6f297SJonathan Marek <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 228146a6f297SJonathan Marek interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 228246a6f297SJonathan Marek "dm_hs_phy_irq", "ss_phy_irq"; 228346a6f297SJonathan Marek 228446a6f297SJonathan Marek power-domains = <&gcc USB30_SEC_GDSC>; 228546a6f297SJonathan Marek 228646a6f297SJonathan Marek resets = <&gcc GCC_USB30_SEC_BCR>; 228746a6f297SJonathan Marek 228846a6f297SJonathan Marek usb_2_dwc3: dwc3@a800000 { 228946a6f297SJonathan Marek compatible = "snps,dwc3"; 229046a6f297SJonathan Marek reg = <0 0x0a800000 0 0xcd00>; 229146a6f297SJonathan Marek interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 229246a6f297SJonathan Marek iommus = <&apps_smmu 0x20 0>; 229346a6f297SJonathan Marek snps,dis_u2_susphy_quirk; 229446a6f297SJonathan Marek snps,dis_enblslpm_quirk; 229546a6f297SJonathan Marek phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 229646a6f297SJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 229746a6f297SJonathan Marek }; 229846a6f297SJonathan Marek }; 229946a6f297SJonathan Marek 2300fa245b3fSBryan O'Donoghue venus: video-codec@aa00000 { 2301fa245b3fSBryan O'Donoghue compatible = "qcom,sm8250-venus"; 2302fa245b3fSBryan O'Donoghue reg = <0 0x0aa00000 0 0x100000>; 2303fa245b3fSBryan O'Donoghue interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2304fa245b3fSBryan O'Donoghue power-domains = <&videocc MVS0C_GDSC>, 2305fa245b3fSBryan O'Donoghue <&videocc MVS0_GDSC>, 2306fa245b3fSBryan O'Donoghue <&rpmhpd SM8250_MX>; 2307fa245b3fSBryan O'Donoghue power-domain-names = "venus", "vcodec0", "mx"; 2308fa245b3fSBryan O'Donoghue operating-points-v2 = <&venus_opp_table>; 2309fa245b3fSBryan O'Donoghue 2310fa245b3fSBryan O'Donoghue clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 2311fa245b3fSBryan O'Donoghue <&videocc VIDEO_CC_MVS0C_CLK>, 2312fa245b3fSBryan O'Donoghue <&videocc VIDEO_CC_MVS0_CLK>; 2313fa245b3fSBryan O'Donoghue clock-names = "iface", "core", "vcodec0_core"; 2314fa245b3fSBryan O'Donoghue 2315fa245b3fSBryan O'Donoghue interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, 2316fa245b3fSBryan O'Donoghue <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; 2317fa245b3fSBryan O'Donoghue interconnect-names = "cpu-cfg", "video-mem"; 2318fa245b3fSBryan O'Donoghue 2319fa245b3fSBryan O'Donoghue iommus = <&apps_smmu 0x2100 0x0400>; 2320fa245b3fSBryan O'Donoghue memory-region = <&video_mem>; 2321fa245b3fSBryan O'Donoghue 2322fa245b3fSBryan O'Donoghue resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 2323fa245b3fSBryan O'Donoghue <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 2324fa245b3fSBryan O'Donoghue reset-names = "bus", "core"; 2325fa245b3fSBryan O'Donoghue 2326fa245b3fSBryan O'Donoghue video-decoder { 2327fa245b3fSBryan O'Donoghue compatible = "venus-decoder"; 2328fa245b3fSBryan O'Donoghue }; 2329fa245b3fSBryan O'Donoghue 2330fa245b3fSBryan O'Donoghue video-encoder { 2331fa245b3fSBryan O'Donoghue compatible = "venus-encoder"; 2332fa245b3fSBryan O'Donoghue }; 2333fa245b3fSBryan O'Donoghue 2334fa245b3fSBryan O'Donoghue venus_opp_table: venus-opp-table { 2335fa245b3fSBryan O'Donoghue compatible = "operating-points-v2"; 2336fa245b3fSBryan O'Donoghue 2337fa245b3fSBryan O'Donoghue opp-720000000 { 2338fa245b3fSBryan O'Donoghue opp-hz = /bits/ 64 <720000000>; 2339fa245b3fSBryan O'Donoghue required-opps = <&rpmhpd_opp_low_svs>; 2340fa245b3fSBryan O'Donoghue }; 2341fa245b3fSBryan O'Donoghue 2342fa245b3fSBryan O'Donoghue opp-1014000000 { 2343fa245b3fSBryan O'Donoghue opp-hz = /bits/ 64 <1014000000>; 2344fa245b3fSBryan O'Donoghue required-opps = <&rpmhpd_opp_svs>; 2345fa245b3fSBryan O'Donoghue }; 2346fa245b3fSBryan O'Donoghue 2347fa245b3fSBryan O'Donoghue opp-1098000000 { 2348fa245b3fSBryan O'Donoghue opp-hz = /bits/ 64 <1098000000>; 2349fa245b3fSBryan O'Donoghue required-opps = <&rpmhpd_opp_svs_l1>; 2350fa245b3fSBryan O'Donoghue }; 2351fa245b3fSBryan O'Donoghue 2352fa245b3fSBryan O'Donoghue opp-1332000000 { 2353fa245b3fSBryan O'Donoghue opp-hz = /bits/ 64 <1332000000>; 2354fa245b3fSBryan O'Donoghue required-opps = <&rpmhpd_opp_nom>; 2355fa245b3fSBryan O'Donoghue }; 2356fa245b3fSBryan O'Donoghue }; 2357fa245b3fSBryan O'Donoghue }; 2358fa245b3fSBryan O'Donoghue 23595b9ec225Sjonathan@marek.ca videocc: clock-controller@abf0000 { 23605b9ec225Sjonathan@marek.ca compatible = "qcom,sm8250-videocc"; 23615b9ec225Sjonathan@marek.ca reg = <0 0x0abf0000 0 0x10000>; 23625b9ec225Sjonathan@marek.ca clocks = <&gcc GCC_VIDEO_AHB_CLK>, 23635b9ec225Sjonathan@marek.ca <&rpmhcc RPMH_CXO_CLK>, 23645b9ec225Sjonathan@marek.ca <&rpmhcc RPMH_CXO_CLK_A>; 23655b9ec225Sjonathan@marek.ca mmcx-supply = <&mmcx_reg>; 23665b9ec225Sjonathan@marek.ca clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 23675b9ec225Sjonathan@marek.ca #clock-cells = <1>; 23685b9ec225Sjonathan@marek.ca #reset-cells = <1>; 23695b9ec225Sjonathan@marek.ca #power-domain-cells = <1>; 23705b9ec225Sjonathan@marek.ca }; 23715b9ec225Sjonathan@marek.ca 23727c1dffd4SDmitry Baryshkov mdss: mdss@ae00000 { 2373dc5d9125SJonathan Marek compatible = "qcom,sm8250-mdss"; 23747c1dffd4SDmitry Baryshkov reg = <0 0x0ae00000 0 0x1000>; 23757c1dffd4SDmitry Baryshkov reg-names = "mdss"; 23767c1dffd4SDmitry Baryshkov 2377888771a9SJonathan Marek interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 23787c1dffd4SDmitry Baryshkov <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 2379888771a9SJonathan Marek interconnect-names = "mdp0-mem", "mdp1-mem"; 23807c1dffd4SDmitry Baryshkov 23817c1dffd4SDmitry Baryshkov power-domains = <&dispcc MDSS_GDSC>; 23827c1dffd4SDmitry Baryshkov 23837c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 23847c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_HF_AXI_CLK>, 23857c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_SF_AXI_CLK>, 23867c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_MDP_CLK>; 23877c1dffd4SDmitry Baryshkov clock-names = "iface", "bus", "nrt_bus", "core"; 23887c1dffd4SDmitry Baryshkov 23897c1dffd4SDmitry Baryshkov assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 23907c1dffd4SDmitry Baryshkov assigned-clock-rates = <460000000>; 23917c1dffd4SDmitry Baryshkov 23927c1dffd4SDmitry Baryshkov interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 23937c1dffd4SDmitry Baryshkov interrupt-controller; 23947c1dffd4SDmitry Baryshkov #interrupt-cells = <1>; 23957c1dffd4SDmitry Baryshkov 23967c1dffd4SDmitry Baryshkov iommus = <&apps_smmu 0x820 0x402>; 23977c1dffd4SDmitry Baryshkov 23987c1dffd4SDmitry Baryshkov status = "disabled"; 23997c1dffd4SDmitry Baryshkov 24007c1dffd4SDmitry Baryshkov #address-cells = <2>; 24017c1dffd4SDmitry Baryshkov #size-cells = <2>; 24027c1dffd4SDmitry Baryshkov ranges; 24037c1dffd4SDmitry Baryshkov 24047c1dffd4SDmitry Baryshkov mdss_mdp: mdp@ae01000 { 2405dc5d9125SJonathan Marek compatible = "qcom,sm8250-dpu"; 24067c1dffd4SDmitry Baryshkov reg = <0 0x0ae01000 0 0x8f000>, 24077c1dffd4SDmitry Baryshkov <0 0x0aeb0000 0 0x2008>; 24087c1dffd4SDmitry Baryshkov reg-names = "mdp", "vbif"; 24097c1dffd4SDmitry Baryshkov 24107c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 24117c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_HF_AXI_CLK>, 24127c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_MDP_CLK>, 24137c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 24147c1dffd4SDmitry Baryshkov clock-names = "iface", "bus", "core", "vsync"; 24157c1dffd4SDmitry Baryshkov 24167c1dffd4SDmitry Baryshkov assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 24177c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 24187c1dffd4SDmitry Baryshkov assigned-clock-rates = <460000000>, 24197c1dffd4SDmitry Baryshkov <19200000>; 24207c1dffd4SDmitry Baryshkov 24217c1dffd4SDmitry Baryshkov operating-points-v2 = <&mdp_opp_table>; 24227c1dffd4SDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 24237c1dffd4SDmitry Baryshkov 24247c1dffd4SDmitry Baryshkov interrupt-parent = <&mdss>; 24257c1dffd4SDmitry Baryshkov interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 24267c1dffd4SDmitry Baryshkov 24277c1dffd4SDmitry Baryshkov ports { 24287c1dffd4SDmitry Baryshkov #address-cells = <1>; 24297c1dffd4SDmitry Baryshkov #size-cells = <0>; 24307c1dffd4SDmitry Baryshkov 24317c1dffd4SDmitry Baryshkov port@0 { 24327c1dffd4SDmitry Baryshkov reg = <0>; 24337c1dffd4SDmitry Baryshkov dpu_intf1_out: endpoint { 24347c1dffd4SDmitry Baryshkov remote-endpoint = <&dsi0_in>; 24357c1dffd4SDmitry Baryshkov }; 24367c1dffd4SDmitry Baryshkov }; 24377c1dffd4SDmitry Baryshkov 24387c1dffd4SDmitry Baryshkov port@1 { 24397c1dffd4SDmitry Baryshkov reg = <1>; 24407c1dffd4SDmitry Baryshkov dpu_intf2_out: endpoint { 24417c1dffd4SDmitry Baryshkov remote-endpoint = <&dsi1_in>; 24427c1dffd4SDmitry Baryshkov }; 24437c1dffd4SDmitry Baryshkov }; 24447c1dffd4SDmitry Baryshkov }; 24457c1dffd4SDmitry Baryshkov 24467c1dffd4SDmitry Baryshkov mdp_opp_table: mdp-opp-table { 24477c1dffd4SDmitry Baryshkov compatible = "operating-points-v2"; 24487c1dffd4SDmitry Baryshkov 24497c1dffd4SDmitry Baryshkov opp-200000000 { 24507c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <200000000>; 24517c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 24527c1dffd4SDmitry Baryshkov }; 24537c1dffd4SDmitry Baryshkov 24547c1dffd4SDmitry Baryshkov opp-300000000 { 24557c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <300000000>; 24567c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs>; 24577c1dffd4SDmitry Baryshkov }; 24587c1dffd4SDmitry Baryshkov 24597c1dffd4SDmitry Baryshkov opp-345000000 { 24607c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <345000000>; 24617c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs_l1>; 24627c1dffd4SDmitry Baryshkov }; 24637c1dffd4SDmitry Baryshkov 24647c1dffd4SDmitry Baryshkov opp-460000000 { 24657c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <460000000>; 24667c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_nom>; 24677c1dffd4SDmitry Baryshkov }; 24687c1dffd4SDmitry Baryshkov }; 24697c1dffd4SDmitry Baryshkov }; 24707c1dffd4SDmitry Baryshkov 24717c1dffd4SDmitry Baryshkov dsi0: dsi@ae94000 { 24727c1dffd4SDmitry Baryshkov compatible = "qcom,mdss-dsi-ctrl"; 24737c1dffd4SDmitry Baryshkov reg = <0 0x0ae94000 0 0x400>; 24747c1dffd4SDmitry Baryshkov reg-names = "dsi_ctrl"; 24757c1dffd4SDmitry Baryshkov 24767c1dffd4SDmitry Baryshkov interrupt-parent = <&mdss>; 24777c1dffd4SDmitry Baryshkov interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 24787c1dffd4SDmitry Baryshkov 24797c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 24807c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 24817c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 24827c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_ESC0_CLK>, 24837c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_AHB_CLK>, 24847c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_HF_AXI_CLK>; 24857c1dffd4SDmitry Baryshkov clock-names = "byte", 24867c1dffd4SDmitry Baryshkov "byte_intf", 24877c1dffd4SDmitry Baryshkov "pixel", 24887c1dffd4SDmitry Baryshkov "core", 24897c1dffd4SDmitry Baryshkov "iface", 24907c1dffd4SDmitry Baryshkov "bus"; 24917c1dffd4SDmitry Baryshkov 24927c1dffd4SDmitry Baryshkov operating-points-v2 = <&dsi_opp_table>; 24937c1dffd4SDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 24947c1dffd4SDmitry Baryshkov 24957c1dffd4SDmitry Baryshkov phys = <&dsi0_phy>; 24967c1dffd4SDmitry Baryshkov phy-names = "dsi"; 24977c1dffd4SDmitry Baryshkov 24987c1dffd4SDmitry Baryshkov status = "disabled"; 24997c1dffd4SDmitry Baryshkov 250040f7d36dSKonrad Dybcio #address-cells = <1>; 250140f7d36dSKonrad Dybcio #size-cells = <0>; 250240f7d36dSKonrad Dybcio 25037c1dffd4SDmitry Baryshkov ports { 25047c1dffd4SDmitry Baryshkov #address-cells = <1>; 25057c1dffd4SDmitry Baryshkov #size-cells = <0>; 25067c1dffd4SDmitry Baryshkov 25077c1dffd4SDmitry Baryshkov port@0 { 25087c1dffd4SDmitry Baryshkov reg = <0>; 25097c1dffd4SDmitry Baryshkov dsi0_in: endpoint { 25107c1dffd4SDmitry Baryshkov remote-endpoint = <&dpu_intf1_out>; 25117c1dffd4SDmitry Baryshkov }; 25127c1dffd4SDmitry Baryshkov }; 25137c1dffd4SDmitry Baryshkov 25147c1dffd4SDmitry Baryshkov port@1 { 25157c1dffd4SDmitry Baryshkov reg = <1>; 25167c1dffd4SDmitry Baryshkov dsi0_out: endpoint { 25177c1dffd4SDmitry Baryshkov }; 25187c1dffd4SDmitry Baryshkov }; 25197c1dffd4SDmitry Baryshkov }; 25207c1dffd4SDmitry Baryshkov }; 25217c1dffd4SDmitry Baryshkov 25227c1dffd4SDmitry Baryshkov dsi0_phy: dsi-phy@ae94400 { 25237c1dffd4SDmitry Baryshkov compatible = "qcom,dsi-phy-7nm"; 25247c1dffd4SDmitry Baryshkov reg = <0 0x0ae94400 0 0x200>, 25257c1dffd4SDmitry Baryshkov <0 0x0ae94600 0 0x280>, 25267c1dffd4SDmitry Baryshkov <0 0x0ae94900 0 0x260>; 25277c1dffd4SDmitry Baryshkov reg-names = "dsi_phy", 25287c1dffd4SDmitry Baryshkov "dsi_phy_lane", 25297c1dffd4SDmitry Baryshkov "dsi_pll"; 25307c1dffd4SDmitry Baryshkov 25317c1dffd4SDmitry Baryshkov #clock-cells = <1>; 25327c1dffd4SDmitry Baryshkov #phy-cells = <0>; 25337c1dffd4SDmitry Baryshkov 25347c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 25357c1dffd4SDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK>; 25367c1dffd4SDmitry Baryshkov clock-names = "iface", "ref"; 25377c1dffd4SDmitry Baryshkov 25387c1dffd4SDmitry Baryshkov status = "disabled"; 25397c1dffd4SDmitry Baryshkov }; 25407c1dffd4SDmitry Baryshkov 25417c1dffd4SDmitry Baryshkov dsi1: dsi@ae96000 { 25427c1dffd4SDmitry Baryshkov compatible = "qcom,mdss-dsi-ctrl"; 25437c1dffd4SDmitry Baryshkov reg = <0 0x0ae96000 0 0x400>; 25447c1dffd4SDmitry Baryshkov reg-names = "dsi_ctrl"; 25457c1dffd4SDmitry Baryshkov 25467c1dffd4SDmitry Baryshkov interrupt-parent = <&mdss>; 25477c1dffd4SDmitry Baryshkov interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 25487c1dffd4SDmitry Baryshkov 25497c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 25507c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 25517c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 25527c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_ESC1_CLK>, 25537c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_AHB_CLK>, 25547c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_HF_AXI_CLK>; 25557c1dffd4SDmitry Baryshkov clock-names = "byte", 25567c1dffd4SDmitry Baryshkov "byte_intf", 25577c1dffd4SDmitry Baryshkov "pixel", 25587c1dffd4SDmitry Baryshkov "core", 25597c1dffd4SDmitry Baryshkov "iface", 25607c1dffd4SDmitry Baryshkov "bus"; 25617c1dffd4SDmitry Baryshkov 25627c1dffd4SDmitry Baryshkov operating-points-v2 = <&dsi_opp_table>; 25637c1dffd4SDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 25647c1dffd4SDmitry Baryshkov 25657c1dffd4SDmitry Baryshkov phys = <&dsi1_phy>; 25667c1dffd4SDmitry Baryshkov phy-names = "dsi"; 25677c1dffd4SDmitry Baryshkov 25687c1dffd4SDmitry Baryshkov status = "disabled"; 25697c1dffd4SDmitry Baryshkov 257040f7d36dSKonrad Dybcio #address-cells = <1>; 257140f7d36dSKonrad Dybcio #size-cells = <0>; 257240f7d36dSKonrad Dybcio 25737c1dffd4SDmitry Baryshkov ports { 25747c1dffd4SDmitry Baryshkov #address-cells = <1>; 25757c1dffd4SDmitry Baryshkov #size-cells = <0>; 25767c1dffd4SDmitry Baryshkov 25777c1dffd4SDmitry Baryshkov port@0 { 25787c1dffd4SDmitry Baryshkov reg = <0>; 25797c1dffd4SDmitry Baryshkov dsi1_in: endpoint { 25807c1dffd4SDmitry Baryshkov remote-endpoint = <&dpu_intf2_out>; 25817c1dffd4SDmitry Baryshkov }; 25827c1dffd4SDmitry Baryshkov }; 25837c1dffd4SDmitry Baryshkov 25847c1dffd4SDmitry Baryshkov port@1 { 25857c1dffd4SDmitry Baryshkov reg = <1>; 25867c1dffd4SDmitry Baryshkov dsi1_out: endpoint { 25877c1dffd4SDmitry Baryshkov }; 25887c1dffd4SDmitry Baryshkov }; 25897c1dffd4SDmitry Baryshkov }; 25907c1dffd4SDmitry Baryshkov }; 25917c1dffd4SDmitry Baryshkov 25927c1dffd4SDmitry Baryshkov dsi1_phy: dsi-phy@ae96400 { 25937c1dffd4SDmitry Baryshkov compatible = "qcom,dsi-phy-7nm"; 25947c1dffd4SDmitry Baryshkov reg = <0 0x0ae96400 0 0x200>, 25957c1dffd4SDmitry Baryshkov <0 0x0ae96600 0 0x280>, 25967c1dffd4SDmitry Baryshkov <0 0x0ae96900 0 0x260>; 25977c1dffd4SDmitry Baryshkov reg-names = "dsi_phy", 25987c1dffd4SDmitry Baryshkov "dsi_phy_lane", 25997c1dffd4SDmitry Baryshkov "dsi_pll"; 26007c1dffd4SDmitry Baryshkov 26017c1dffd4SDmitry Baryshkov #clock-cells = <1>; 26027c1dffd4SDmitry Baryshkov #phy-cells = <0>; 26037c1dffd4SDmitry Baryshkov 26047c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 26057c1dffd4SDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK>; 26067c1dffd4SDmitry Baryshkov clock-names = "iface", "ref"; 26077c1dffd4SDmitry Baryshkov 26087c1dffd4SDmitry Baryshkov status = "disabled"; 26097c1dffd4SDmitry Baryshkov 26107c1dffd4SDmitry Baryshkov dsi_opp_table: dsi-opp-table { 26117c1dffd4SDmitry Baryshkov compatible = "operating-points-v2"; 26127c1dffd4SDmitry Baryshkov 26137c1dffd4SDmitry Baryshkov opp-187500000 { 26147c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <187500000>; 26157c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 26167c1dffd4SDmitry Baryshkov }; 26177c1dffd4SDmitry Baryshkov 26187c1dffd4SDmitry Baryshkov opp-300000000 { 26197c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <300000000>; 26207c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs>; 26217c1dffd4SDmitry Baryshkov }; 26227c1dffd4SDmitry Baryshkov 26237c1dffd4SDmitry Baryshkov opp-358000000 { 26247c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <358000000>; 26257c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs_l1>; 26267c1dffd4SDmitry Baryshkov }; 26277c1dffd4SDmitry Baryshkov }; 26287c1dffd4SDmitry Baryshkov }; 26297c1dffd4SDmitry Baryshkov }; 26307c1dffd4SDmitry Baryshkov 26317c1dffd4SDmitry Baryshkov dispcc: clock-controller@af00000 { 26327c1dffd4SDmitry Baryshkov compatible = "qcom,sm8250-dispcc"; 2633888771a9SJonathan Marek reg = <0 0x0af00000 0 0x10000>; 26343f2094dfSDmitry Baryshkov mmcx-supply = <&mmcx_reg>; 26357c1dffd4SDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>, 26367c1dffd4SDmitry Baryshkov <&dsi0_phy 0>, 26377c1dffd4SDmitry Baryshkov <&dsi0_phy 1>, 26387c1dffd4SDmitry Baryshkov <&dsi1_phy 0>, 26397c1dffd4SDmitry Baryshkov <&dsi1_phy 1>, 26409b315324SDmitry Baryshkov <&dp_phy 0>, 26419b315324SDmitry Baryshkov <&dp_phy 1>; 26427c1dffd4SDmitry Baryshkov clock-names = "bi_tcxo", 26437c1dffd4SDmitry Baryshkov "dsi0_phy_pll_out_byteclk", 26447c1dffd4SDmitry Baryshkov "dsi0_phy_pll_out_dsiclk", 26457c1dffd4SDmitry Baryshkov "dsi1_phy_pll_out_byteclk", 26467c1dffd4SDmitry Baryshkov "dsi1_phy_pll_out_dsiclk", 2647888771a9SJonathan Marek "dp_phy_pll_link_clk", 2648888771a9SJonathan Marek "dp_phy_pll_vco_div_clk"; 26497c1dffd4SDmitry Baryshkov #clock-cells = <1>; 26507c1dffd4SDmitry Baryshkov #reset-cells = <1>; 26517c1dffd4SDmitry Baryshkov #power-domain-cells = <1>; 26527c1dffd4SDmitry Baryshkov }; 26537c1dffd4SDmitry Baryshkov 265460378f1aSVenkata Narendra Kumar Gutta pdc: interrupt-controller@b220000 { 265524003196SBjorn Andersson compatible = "qcom,sm8250-pdc", "qcom,pdc"; 265624003196SBjorn Andersson reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 265760378f1aSVenkata Narendra Kumar Gutta qcom,pdc-ranges = <0 480 94>, <94 609 31>, 265860378f1aSVenkata Narendra Kumar Gutta <125 63 1>, <126 716 12>; 265960378f1aSVenkata Narendra Kumar Gutta #interrupt-cells = <2>; 266060378f1aSVenkata Narendra Kumar Gutta interrupt-parent = <&intc>; 266160378f1aSVenkata Narendra Kumar Gutta interrupt-controller; 266260378f1aSVenkata Narendra Kumar Gutta }; 266360378f1aSVenkata Narendra Kumar Gutta 2664bac12f25SAmit Kucheria tsens0: thermal-sensor@c263000 { 2665bac12f25SAmit Kucheria compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 2666bac12f25SAmit Kucheria reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2667bac12f25SAmit Kucheria <0 0x0c222000 0 0x1ff>; /* SROT */ 2668bac12f25SAmit Kucheria #qcom,sensors = <16>; 2669bac12f25SAmit Kucheria interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2670bac12f25SAmit Kucheria <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2671bac12f25SAmit Kucheria interrupt-names = "uplow", "critical"; 2672bac12f25SAmit Kucheria #thermal-sensor-cells = <1>; 2673bac12f25SAmit Kucheria }; 2674bac12f25SAmit Kucheria 2675bac12f25SAmit Kucheria tsens1: thermal-sensor@c265000 { 2676bac12f25SAmit Kucheria compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 2677bac12f25SAmit Kucheria reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2678bac12f25SAmit Kucheria <0 0x0c223000 0 0x1ff>; /* SROT */ 2679bac12f25SAmit Kucheria #qcom,sensors = <9>; 2680bac12f25SAmit Kucheria interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2681bac12f25SAmit Kucheria <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2682bac12f25SAmit Kucheria interrupt-names = "uplow", "critical"; 2683bac12f25SAmit Kucheria #thermal-sensor-cells = <1>; 2684bac12f25SAmit Kucheria }; 2685bac12f25SAmit Kucheria 268643f14a0bSSai Prakash Ranjan aoss_qmp: power-controller@c300000 { 2687087d537aSBjorn Andersson compatible = "qcom,sm8250-aoss-qmp"; 2688087d537aSBjorn Andersson reg = <0 0x0c300000 0 0x100000>; 2689087d537aSBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2690087d537aSBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 2691087d537aSBjorn Andersson IRQ_TYPE_EDGE_RISING>; 2692087d537aSBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_AOP 2693087d537aSBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 2694087d537aSBjorn Andersson 2695087d537aSBjorn Andersson #clock-cells = <0>; 2696087d537aSBjorn Andersson #power-domain-cells = <1>; 2697087d537aSBjorn Andersson }; 2698087d537aSBjorn Andersson 2699bccc7dd2SJonathan Marek spmi_bus: spmi@c440000 { 270060378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,spmi-pmic-arb"; 270160378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x0c440000 0x0 0x0001100>, 270260378f1aSVenkata Narendra Kumar Gutta <0x0 0x0c600000 0x0 0x2000000>, 270360378f1aSVenkata Narendra Kumar Gutta <0x0 0x0e600000 0x0 0x0100000>, 270460378f1aSVenkata Narendra Kumar Gutta <0x0 0x0e700000 0x0 0x00a0000>, 270560378f1aSVenkata Narendra Kumar Gutta <0x0 0x0c40a000 0x0 0x0026000>; 270660378f1aSVenkata Narendra Kumar Gutta reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 270760378f1aSVenkata Narendra Kumar Gutta interrupt-names = "periph_irq"; 270860378f1aSVenkata Narendra Kumar Gutta interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 270960378f1aSVenkata Narendra Kumar Gutta qcom,ee = <0>; 271060378f1aSVenkata Narendra Kumar Gutta qcom,channel = <0>; 271160378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 271260378f1aSVenkata Narendra Kumar Gutta #size-cells = <0>; 271360378f1aSVenkata Narendra Kumar Gutta interrupt-controller; 271460378f1aSVenkata Narendra Kumar Gutta #interrupt-cells = <4>; 271560378f1aSVenkata Narendra Kumar Gutta }; 271660378f1aSVenkata Narendra Kumar Gutta 271716951b49SBjorn Andersson tlmm: pinctrl@f100000 { 271816951b49SBjorn Andersson compatible = "qcom,sm8250-pinctrl"; 271916951b49SBjorn Andersson reg = <0 0x0f100000 0 0x300000>, 272016951b49SBjorn Andersson <0 0x0f500000 0 0x300000>, 272116951b49SBjorn Andersson <0 0x0f900000 0 0x300000>; 272216951b49SBjorn Andersson reg-names = "west", "south", "north"; 272316951b49SBjorn Andersson interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 272416951b49SBjorn Andersson gpio-controller; 272516951b49SBjorn Andersson #gpio-cells = <2>; 272616951b49SBjorn Andersson interrupt-controller; 272716951b49SBjorn Andersson #interrupt-cells = <2>; 2728e526cb03SShawn Guo gpio-ranges = <&tlmm 0 0 181>; 272916951b49SBjorn Andersson wakeup-parent = <&pdc>; 2730e5813b15SDmitry Baryshkov 2731b657d372SSrinivas Kandagatla pri_mi2s_active: pri-mi2s-active { 2732b657d372SSrinivas Kandagatla sclk { 2733b657d372SSrinivas Kandagatla pins = "gpio138"; 2734b657d372SSrinivas Kandagatla function = "mi2s0_sck"; 2735b657d372SSrinivas Kandagatla drive-strength = <8>; 2736b657d372SSrinivas Kandagatla bias-disable; 2737b657d372SSrinivas Kandagatla }; 2738b657d372SSrinivas Kandagatla 2739b657d372SSrinivas Kandagatla ws { 2740b657d372SSrinivas Kandagatla pins = "gpio141"; 2741b657d372SSrinivas Kandagatla function = "mi2s0_ws"; 2742b657d372SSrinivas Kandagatla drive-strength = <8>; 2743b657d372SSrinivas Kandagatla output-high; 2744b657d372SSrinivas Kandagatla }; 2745b657d372SSrinivas Kandagatla 2746b657d372SSrinivas Kandagatla data0 { 2747b657d372SSrinivas Kandagatla pins = "gpio139"; 2748b657d372SSrinivas Kandagatla function = "mi2s0_data0"; 2749b657d372SSrinivas Kandagatla drive-strength = <8>; 2750b657d372SSrinivas Kandagatla bias-disable; 2751b657d372SSrinivas Kandagatla output-high; 2752b657d372SSrinivas Kandagatla }; 2753b657d372SSrinivas Kandagatla 2754b657d372SSrinivas Kandagatla data1 { 2755b657d372SSrinivas Kandagatla pins = "gpio140"; 2756b657d372SSrinivas Kandagatla function = "mi2s0_data1"; 2757b657d372SSrinivas Kandagatla drive-strength = <8>; 2758b657d372SSrinivas Kandagatla output-high; 2759b657d372SSrinivas Kandagatla }; 2760b657d372SSrinivas Kandagatla }; 2761b657d372SSrinivas Kandagatla 2762e5813b15SDmitry Baryshkov qup_i2c0_default: qup-i2c0-default { 2763e5813b15SDmitry Baryshkov mux { 2764e5813b15SDmitry Baryshkov pins = "gpio28", "gpio29"; 2765e5813b15SDmitry Baryshkov function = "qup0"; 2766e5813b15SDmitry Baryshkov }; 2767e5813b15SDmitry Baryshkov 2768e5813b15SDmitry Baryshkov config { 2769e5813b15SDmitry Baryshkov pins = "gpio28", "gpio29"; 2770e5813b15SDmitry Baryshkov drive-strength = <2>; 2771e5813b15SDmitry Baryshkov bias-disable; 2772e5813b15SDmitry Baryshkov }; 2773e5813b15SDmitry Baryshkov }; 2774e5813b15SDmitry Baryshkov 2775e5813b15SDmitry Baryshkov qup_i2c1_default: qup-i2c1-default { 2776e5813b15SDmitry Baryshkov pinmux { 2777e5813b15SDmitry Baryshkov pins = "gpio4", "gpio5"; 2778e5813b15SDmitry Baryshkov function = "qup1"; 2779e5813b15SDmitry Baryshkov }; 2780e5813b15SDmitry Baryshkov 2781e5813b15SDmitry Baryshkov config { 2782e5813b15SDmitry Baryshkov pins = "gpio4", "gpio5"; 2783e5813b15SDmitry Baryshkov drive-strength = <2>; 2784e5813b15SDmitry Baryshkov bias-disable; 2785e5813b15SDmitry Baryshkov }; 2786e5813b15SDmitry Baryshkov }; 2787e5813b15SDmitry Baryshkov 2788e5813b15SDmitry Baryshkov qup_i2c2_default: qup-i2c2-default { 2789e5813b15SDmitry Baryshkov mux { 2790e5813b15SDmitry Baryshkov pins = "gpio115", "gpio116"; 2791e5813b15SDmitry Baryshkov function = "qup2"; 2792e5813b15SDmitry Baryshkov }; 2793e5813b15SDmitry Baryshkov 2794e5813b15SDmitry Baryshkov config { 2795e5813b15SDmitry Baryshkov pins = "gpio115", "gpio116"; 2796e5813b15SDmitry Baryshkov drive-strength = <2>; 2797e5813b15SDmitry Baryshkov bias-disable; 2798e5813b15SDmitry Baryshkov }; 2799e5813b15SDmitry Baryshkov }; 2800e5813b15SDmitry Baryshkov 2801e5813b15SDmitry Baryshkov qup_i2c3_default: qup-i2c3-default { 2802e5813b15SDmitry Baryshkov mux { 2803e5813b15SDmitry Baryshkov pins = "gpio119", "gpio120"; 2804e5813b15SDmitry Baryshkov function = "qup3"; 2805e5813b15SDmitry Baryshkov }; 2806e5813b15SDmitry Baryshkov 2807e5813b15SDmitry Baryshkov config { 2808e5813b15SDmitry Baryshkov pins = "gpio119", "gpio120"; 2809e5813b15SDmitry Baryshkov drive-strength = <2>; 2810e5813b15SDmitry Baryshkov bias-disable; 2811e5813b15SDmitry Baryshkov }; 2812e5813b15SDmitry Baryshkov }; 2813e5813b15SDmitry Baryshkov 2814e5813b15SDmitry Baryshkov qup_i2c4_default: qup-i2c4-default { 2815e5813b15SDmitry Baryshkov mux { 2816e5813b15SDmitry Baryshkov pins = "gpio8", "gpio9"; 2817e5813b15SDmitry Baryshkov function = "qup4"; 2818e5813b15SDmitry Baryshkov }; 2819e5813b15SDmitry Baryshkov 2820e5813b15SDmitry Baryshkov config { 2821e5813b15SDmitry Baryshkov pins = "gpio8", "gpio9"; 2822e5813b15SDmitry Baryshkov drive-strength = <2>; 2823e5813b15SDmitry Baryshkov bias-disable; 2824e5813b15SDmitry Baryshkov }; 2825e5813b15SDmitry Baryshkov }; 2826e5813b15SDmitry Baryshkov 2827e5813b15SDmitry Baryshkov qup_i2c5_default: qup-i2c5-default { 2828e5813b15SDmitry Baryshkov mux { 2829e5813b15SDmitry Baryshkov pins = "gpio12", "gpio13"; 2830e5813b15SDmitry Baryshkov function = "qup5"; 2831e5813b15SDmitry Baryshkov }; 2832e5813b15SDmitry Baryshkov 2833e5813b15SDmitry Baryshkov config { 2834e5813b15SDmitry Baryshkov pins = "gpio12", "gpio13"; 2835e5813b15SDmitry Baryshkov drive-strength = <2>; 2836e5813b15SDmitry Baryshkov bias-disable; 2837e5813b15SDmitry Baryshkov }; 2838e5813b15SDmitry Baryshkov }; 2839e5813b15SDmitry Baryshkov 2840e5813b15SDmitry Baryshkov qup_i2c6_default: qup-i2c6-default { 2841e5813b15SDmitry Baryshkov mux { 2842e5813b15SDmitry Baryshkov pins = "gpio16", "gpio17"; 2843e5813b15SDmitry Baryshkov function = "qup6"; 2844e5813b15SDmitry Baryshkov }; 2845e5813b15SDmitry Baryshkov 2846e5813b15SDmitry Baryshkov config { 2847e5813b15SDmitry Baryshkov pins = "gpio16", "gpio17"; 2848e5813b15SDmitry Baryshkov drive-strength = <2>; 2849e5813b15SDmitry Baryshkov bias-disable; 2850e5813b15SDmitry Baryshkov }; 2851e5813b15SDmitry Baryshkov }; 2852e5813b15SDmitry Baryshkov 2853e5813b15SDmitry Baryshkov qup_i2c7_default: qup-i2c7-default { 2854e5813b15SDmitry Baryshkov mux { 2855e5813b15SDmitry Baryshkov pins = "gpio20", "gpio21"; 2856e5813b15SDmitry Baryshkov function = "qup7"; 2857e5813b15SDmitry Baryshkov }; 2858e5813b15SDmitry Baryshkov 2859e5813b15SDmitry Baryshkov config { 2860e5813b15SDmitry Baryshkov pins = "gpio20", "gpio21"; 2861e5813b15SDmitry Baryshkov drive-strength = <2>; 2862e5813b15SDmitry Baryshkov bias-disable; 2863e5813b15SDmitry Baryshkov }; 2864e5813b15SDmitry Baryshkov }; 2865e5813b15SDmitry Baryshkov 2866e5813b15SDmitry Baryshkov qup_i2c8_default: qup-i2c8-default { 2867e5813b15SDmitry Baryshkov mux { 2868e5813b15SDmitry Baryshkov pins = "gpio24", "gpio25"; 2869e5813b15SDmitry Baryshkov function = "qup8"; 2870e5813b15SDmitry Baryshkov }; 2871e5813b15SDmitry Baryshkov 2872e5813b15SDmitry Baryshkov config { 2873e5813b15SDmitry Baryshkov pins = "gpio24", "gpio25"; 2874e5813b15SDmitry Baryshkov drive-strength = <2>; 2875e5813b15SDmitry Baryshkov bias-disable; 2876e5813b15SDmitry Baryshkov }; 2877e5813b15SDmitry Baryshkov }; 2878e5813b15SDmitry Baryshkov 2879e5813b15SDmitry Baryshkov qup_i2c9_default: qup-i2c9-default { 2880e5813b15SDmitry Baryshkov mux { 2881e5813b15SDmitry Baryshkov pins = "gpio125", "gpio126"; 2882e5813b15SDmitry Baryshkov function = "qup9"; 2883e5813b15SDmitry Baryshkov }; 2884e5813b15SDmitry Baryshkov 2885e5813b15SDmitry Baryshkov config { 2886e5813b15SDmitry Baryshkov pins = "gpio125", "gpio126"; 2887e5813b15SDmitry Baryshkov drive-strength = <2>; 2888e5813b15SDmitry Baryshkov bias-disable; 2889e5813b15SDmitry Baryshkov }; 2890e5813b15SDmitry Baryshkov }; 2891e5813b15SDmitry Baryshkov 2892e5813b15SDmitry Baryshkov qup_i2c10_default: qup-i2c10-default { 2893e5813b15SDmitry Baryshkov mux { 2894e5813b15SDmitry Baryshkov pins = "gpio129", "gpio130"; 2895e5813b15SDmitry Baryshkov function = "qup10"; 2896e5813b15SDmitry Baryshkov }; 2897e5813b15SDmitry Baryshkov 2898e5813b15SDmitry Baryshkov config { 2899e5813b15SDmitry Baryshkov pins = "gpio129", "gpio130"; 2900e5813b15SDmitry Baryshkov drive-strength = <2>; 2901e5813b15SDmitry Baryshkov bias-disable; 2902e5813b15SDmitry Baryshkov }; 2903e5813b15SDmitry Baryshkov }; 2904e5813b15SDmitry Baryshkov 2905e5813b15SDmitry Baryshkov qup_i2c11_default: qup-i2c11-default { 2906e5813b15SDmitry Baryshkov mux { 2907e5813b15SDmitry Baryshkov pins = "gpio60", "gpio61"; 2908e5813b15SDmitry Baryshkov function = "qup11"; 2909e5813b15SDmitry Baryshkov }; 2910e5813b15SDmitry Baryshkov 2911e5813b15SDmitry Baryshkov config { 2912e5813b15SDmitry Baryshkov pins = "gpio60", "gpio61"; 2913e5813b15SDmitry Baryshkov drive-strength = <2>; 2914e5813b15SDmitry Baryshkov bias-disable; 2915e5813b15SDmitry Baryshkov }; 2916e5813b15SDmitry Baryshkov }; 2917e5813b15SDmitry Baryshkov 2918e5813b15SDmitry Baryshkov qup_i2c12_default: qup-i2c12-default { 2919e5813b15SDmitry Baryshkov mux { 2920e5813b15SDmitry Baryshkov pins = "gpio32", "gpio33"; 2921e5813b15SDmitry Baryshkov function = "qup12"; 2922e5813b15SDmitry Baryshkov }; 2923e5813b15SDmitry Baryshkov 2924e5813b15SDmitry Baryshkov config { 2925e5813b15SDmitry Baryshkov pins = "gpio32", "gpio33"; 2926e5813b15SDmitry Baryshkov drive-strength = <2>; 2927e5813b15SDmitry Baryshkov bias-disable; 2928e5813b15SDmitry Baryshkov }; 2929e5813b15SDmitry Baryshkov }; 2930e5813b15SDmitry Baryshkov 2931e5813b15SDmitry Baryshkov qup_i2c13_default: qup-i2c13-default { 2932e5813b15SDmitry Baryshkov mux { 2933e5813b15SDmitry Baryshkov pins = "gpio36", "gpio37"; 2934e5813b15SDmitry Baryshkov function = "qup13"; 2935e5813b15SDmitry Baryshkov }; 2936e5813b15SDmitry Baryshkov 2937e5813b15SDmitry Baryshkov config { 2938e5813b15SDmitry Baryshkov pins = "gpio36", "gpio37"; 2939e5813b15SDmitry Baryshkov drive-strength = <2>; 2940e5813b15SDmitry Baryshkov bias-disable; 2941e5813b15SDmitry Baryshkov }; 2942e5813b15SDmitry Baryshkov }; 2943e5813b15SDmitry Baryshkov 2944e5813b15SDmitry Baryshkov qup_i2c14_default: qup-i2c14-default { 2945e5813b15SDmitry Baryshkov mux { 2946e5813b15SDmitry Baryshkov pins = "gpio40", "gpio41"; 2947e5813b15SDmitry Baryshkov function = "qup14"; 2948e5813b15SDmitry Baryshkov }; 2949e5813b15SDmitry Baryshkov 2950e5813b15SDmitry Baryshkov config { 2951e5813b15SDmitry Baryshkov pins = "gpio40", "gpio41"; 2952e5813b15SDmitry Baryshkov drive-strength = <2>; 2953e5813b15SDmitry Baryshkov bias-disable; 2954e5813b15SDmitry Baryshkov }; 2955e5813b15SDmitry Baryshkov }; 2956e5813b15SDmitry Baryshkov 2957e5813b15SDmitry Baryshkov qup_i2c15_default: qup-i2c15-default { 2958e5813b15SDmitry Baryshkov mux { 2959e5813b15SDmitry Baryshkov pins = "gpio44", "gpio45"; 2960e5813b15SDmitry Baryshkov function = "qup15"; 2961e5813b15SDmitry Baryshkov }; 2962e5813b15SDmitry Baryshkov 2963e5813b15SDmitry Baryshkov config { 2964e5813b15SDmitry Baryshkov pins = "gpio44", "gpio45"; 2965e5813b15SDmitry Baryshkov drive-strength = <2>; 2966e5813b15SDmitry Baryshkov bias-disable; 2967e5813b15SDmitry Baryshkov }; 2968e5813b15SDmitry Baryshkov }; 2969e5813b15SDmitry Baryshkov 2970e5813b15SDmitry Baryshkov qup_i2c16_default: qup-i2c16-default { 2971e5813b15SDmitry Baryshkov mux { 2972e5813b15SDmitry Baryshkov pins = "gpio48", "gpio49"; 2973e5813b15SDmitry Baryshkov function = "qup16"; 2974e5813b15SDmitry Baryshkov }; 2975e5813b15SDmitry Baryshkov 2976e5813b15SDmitry Baryshkov config { 2977e5813b15SDmitry Baryshkov pins = "gpio48", "gpio49"; 2978e5813b15SDmitry Baryshkov drive-strength = <2>; 2979e5813b15SDmitry Baryshkov bias-disable; 2980e5813b15SDmitry Baryshkov }; 2981e5813b15SDmitry Baryshkov }; 2982e5813b15SDmitry Baryshkov 2983e5813b15SDmitry Baryshkov qup_i2c17_default: qup-i2c17-default { 2984e5813b15SDmitry Baryshkov mux { 2985e5813b15SDmitry Baryshkov pins = "gpio52", "gpio53"; 2986e5813b15SDmitry Baryshkov function = "qup17"; 2987e5813b15SDmitry Baryshkov }; 2988e5813b15SDmitry Baryshkov 2989e5813b15SDmitry Baryshkov config { 2990e5813b15SDmitry Baryshkov pins = "gpio52", "gpio53"; 2991e5813b15SDmitry Baryshkov drive-strength = <2>; 2992e5813b15SDmitry Baryshkov bias-disable; 2993e5813b15SDmitry Baryshkov }; 2994e5813b15SDmitry Baryshkov }; 2995e5813b15SDmitry Baryshkov 2996e5813b15SDmitry Baryshkov qup_i2c18_default: qup-i2c18-default { 2997e5813b15SDmitry Baryshkov mux { 2998e5813b15SDmitry Baryshkov pins = "gpio56", "gpio57"; 2999e5813b15SDmitry Baryshkov function = "qup18"; 3000e5813b15SDmitry Baryshkov }; 3001e5813b15SDmitry Baryshkov 3002e5813b15SDmitry Baryshkov config { 3003e5813b15SDmitry Baryshkov pins = "gpio56", "gpio57"; 3004e5813b15SDmitry Baryshkov drive-strength = <2>; 3005e5813b15SDmitry Baryshkov bias-disable; 3006e5813b15SDmitry Baryshkov }; 3007e5813b15SDmitry Baryshkov }; 3008e5813b15SDmitry Baryshkov 3009e5813b15SDmitry Baryshkov qup_i2c19_default: qup-i2c19-default { 3010e5813b15SDmitry Baryshkov mux { 3011e5813b15SDmitry Baryshkov pins = "gpio0", "gpio1"; 3012e5813b15SDmitry Baryshkov function = "qup19"; 3013e5813b15SDmitry Baryshkov }; 3014e5813b15SDmitry Baryshkov 3015e5813b15SDmitry Baryshkov config { 3016e5813b15SDmitry Baryshkov pins = "gpio0", "gpio1"; 3017e5813b15SDmitry Baryshkov drive-strength = <2>; 3018e5813b15SDmitry Baryshkov bias-disable; 3019e5813b15SDmitry Baryshkov }; 3020e5813b15SDmitry Baryshkov }; 3021e5813b15SDmitry Baryshkov 3022c88f9eccSDmitry Baryshkov qup_spi0_cs: qup-spi0-cs { 3023c88f9eccSDmitry Baryshkov pins = "gpio31"; 3024e5813b15SDmitry Baryshkov function = "qup0"; 3025e5813b15SDmitry Baryshkov }; 3026e5813b15SDmitry Baryshkov 3027eb97ccbbSDmitry Baryshkov qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3028eb97ccbbSDmitry Baryshkov pins = "gpio31"; 3029eb97ccbbSDmitry Baryshkov function = "gpio"; 3030eb97ccbbSDmitry Baryshkov }; 3031eb97ccbbSDmitry Baryshkov 3032c88f9eccSDmitry Baryshkov qup_spi0_data_clk: qup-spi0-data-clk { 3033c88f9eccSDmitry Baryshkov pins = "gpio28", "gpio29", 3034c88f9eccSDmitry Baryshkov "gpio30"; 3035c88f9eccSDmitry Baryshkov function = "qup0"; 3036c88f9eccSDmitry Baryshkov }; 3037c88f9eccSDmitry Baryshkov 3038c88f9eccSDmitry Baryshkov qup_spi1_cs: qup-spi1-cs { 3039c88f9eccSDmitry Baryshkov pins = "gpio7"; 3040e5813b15SDmitry Baryshkov function = "qup1"; 3041e5813b15SDmitry Baryshkov }; 3042e5813b15SDmitry Baryshkov 3043eb97ccbbSDmitry Baryshkov qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3044eb97ccbbSDmitry Baryshkov pins = "gpio7"; 3045eb97ccbbSDmitry Baryshkov function = "gpio"; 3046eb97ccbbSDmitry Baryshkov }; 3047eb97ccbbSDmitry Baryshkov 3048c88f9eccSDmitry Baryshkov qup_spi1_data_clk: qup-spi1-data-clk { 3049c88f9eccSDmitry Baryshkov pins = "gpio4", "gpio5", 3050c88f9eccSDmitry Baryshkov "gpio6"; 3051c88f9eccSDmitry Baryshkov function = "qup1"; 3052c88f9eccSDmitry Baryshkov }; 3053c88f9eccSDmitry Baryshkov 3054c88f9eccSDmitry Baryshkov qup_spi2_cs: qup-spi2-cs { 3055c88f9eccSDmitry Baryshkov pins = "gpio118"; 3056e5813b15SDmitry Baryshkov function = "qup2"; 3057e5813b15SDmitry Baryshkov }; 3058e5813b15SDmitry Baryshkov 3059eb97ccbbSDmitry Baryshkov qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3060eb97ccbbSDmitry Baryshkov pins = "gpio118"; 3061eb97ccbbSDmitry Baryshkov function = "gpio"; 3062eb97ccbbSDmitry Baryshkov }; 3063eb97ccbbSDmitry Baryshkov 3064c88f9eccSDmitry Baryshkov qup_spi2_data_clk: qup-spi2-data-clk { 3065c88f9eccSDmitry Baryshkov pins = "gpio115", "gpio116", 3066c88f9eccSDmitry Baryshkov "gpio117"; 3067c88f9eccSDmitry Baryshkov function = "qup2"; 3068c88f9eccSDmitry Baryshkov }; 3069c88f9eccSDmitry Baryshkov 3070c88f9eccSDmitry Baryshkov qup_spi3_cs: qup-spi3-cs { 3071c88f9eccSDmitry Baryshkov pins = "gpio122"; 3072e5813b15SDmitry Baryshkov function = "qup3"; 3073e5813b15SDmitry Baryshkov }; 3074e5813b15SDmitry Baryshkov 3075eb97ccbbSDmitry Baryshkov qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3076eb97ccbbSDmitry Baryshkov pins = "gpio122"; 3077eb97ccbbSDmitry Baryshkov function = "gpio"; 3078eb97ccbbSDmitry Baryshkov }; 3079eb97ccbbSDmitry Baryshkov 3080c88f9eccSDmitry Baryshkov qup_spi3_data_clk: qup-spi3-data-clk { 3081c88f9eccSDmitry Baryshkov pins = "gpio119", "gpio120", 3082c88f9eccSDmitry Baryshkov "gpio121"; 3083c88f9eccSDmitry Baryshkov function = "qup3"; 3084c88f9eccSDmitry Baryshkov }; 3085c88f9eccSDmitry Baryshkov 3086c88f9eccSDmitry Baryshkov qup_spi4_cs: qup-spi4-cs { 3087c88f9eccSDmitry Baryshkov pins = "gpio11"; 3088e5813b15SDmitry Baryshkov function = "qup4"; 3089e5813b15SDmitry Baryshkov }; 3090e5813b15SDmitry Baryshkov 3091eb97ccbbSDmitry Baryshkov qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3092eb97ccbbSDmitry Baryshkov pins = "gpio11"; 3093eb97ccbbSDmitry Baryshkov function = "gpio"; 3094eb97ccbbSDmitry Baryshkov }; 3095eb97ccbbSDmitry Baryshkov 3096c88f9eccSDmitry Baryshkov qup_spi4_data_clk: qup-spi4-data-clk { 3097c88f9eccSDmitry Baryshkov pins = "gpio8", "gpio9", 3098c88f9eccSDmitry Baryshkov "gpio10"; 3099c88f9eccSDmitry Baryshkov function = "qup4"; 3100c88f9eccSDmitry Baryshkov }; 3101c88f9eccSDmitry Baryshkov 3102c88f9eccSDmitry Baryshkov qup_spi5_cs: qup-spi5-cs { 3103c88f9eccSDmitry Baryshkov pins = "gpio15"; 3104e5813b15SDmitry Baryshkov function = "qup5"; 3105e5813b15SDmitry Baryshkov }; 3106e5813b15SDmitry Baryshkov 3107eb97ccbbSDmitry Baryshkov qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3108eb97ccbbSDmitry Baryshkov pins = "gpio15"; 3109eb97ccbbSDmitry Baryshkov function = "gpio"; 3110eb97ccbbSDmitry Baryshkov }; 3111eb97ccbbSDmitry Baryshkov 3112c88f9eccSDmitry Baryshkov qup_spi5_data_clk: qup-spi5-data-clk { 3113c88f9eccSDmitry Baryshkov pins = "gpio12", "gpio13", 3114c88f9eccSDmitry Baryshkov "gpio14"; 3115c88f9eccSDmitry Baryshkov function = "qup5"; 3116c88f9eccSDmitry Baryshkov }; 3117c88f9eccSDmitry Baryshkov 3118c88f9eccSDmitry Baryshkov qup_spi6_cs: qup-spi6-cs { 3119c88f9eccSDmitry Baryshkov pins = "gpio19"; 3120e5813b15SDmitry Baryshkov function = "qup6"; 3121e5813b15SDmitry Baryshkov }; 3122e5813b15SDmitry Baryshkov 3123eb97ccbbSDmitry Baryshkov qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3124eb97ccbbSDmitry Baryshkov pins = "gpio19"; 3125eb97ccbbSDmitry Baryshkov function = "gpio"; 3126eb97ccbbSDmitry Baryshkov }; 3127eb97ccbbSDmitry Baryshkov 3128c88f9eccSDmitry Baryshkov qup_spi6_data_clk: qup-spi6-data-clk { 3129c88f9eccSDmitry Baryshkov pins = "gpio16", "gpio17", 3130c88f9eccSDmitry Baryshkov "gpio18"; 3131c88f9eccSDmitry Baryshkov function = "qup6"; 3132c88f9eccSDmitry Baryshkov }; 3133c88f9eccSDmitry Baryshkov 3134c88f9eccSDmitry Baryshkov qup_spi7_cs: qup-spi7-cs { 3135c88f9eccSDmitry Baryshkov pins = "gpio23"; 3136e5813b15SDmitry Baryshkov function = "qup7"; 3137e5813b15SDmitry Baryshkov }; 3138e5813b15SDmitry Baryshkov 3139eb97ccbbSDmitry Baryshkov qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3140eb97ccbbSDmitry Baryshkov pins = "gpio23"; 3141eb97ccbbSDmitry Baryshkov function = "gpio"; 3142eb97ccbbSDmitry Baryshkov }; 3143eb97ccbbSDmitry Baryshkov 3144c88f9eccSDmitry Baryshkov qup_spi7_data_clk: qup-spi7-data-clk { 3145c88f9eccSDmitry Baryshkov pins = "gpio20", "gpio21", 3146c88f9eccSDmitry Baryshkov "gpio22"; 3147c88f9eccSDmitry Baryshkov function = "qup7"; 3148c88f9eccSDmitry Baryshkov }; 3149c88f9eccSDmitry Baryshkov 3150c88f9eccSDmitry Baryshkov qup_spi8_cs: qup-spi8-cs { 3151c88f9eccSDmitry Baryshkov pins = "gpio27"; 3152e5813b15SDmitry Baryshkov function = "qup8"; 3153e5813b15SDmitry Baryshkov }; 3154e5813b15SDmitry Baryshkov 3155eb97ccbbSDmitry Baryshkov qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3156eb97ccbbSDmitry Baryshkov pins = "gpio27"; 3157eb97ccbbSDmitry Baryshkov function = "gpio"; 3158eb97ccbbSDmitry Baryshkov }; 3159eb97ccbbSDmitry Baryshkov 3160c88f9eccSDmitry Baryshkov qup_spi8_data_clk: qup-spi8-data-clk { 3161c88f9eccSDmitry Baryshkov pins = "gpio24", "gpio25", 3162c88f9eccSDmitry Baryshkov "gpio26"; 3163c88f9eccSDmitry Baryshkov function = "qup8"; 3164c88f9eccSDmitry Baryshkov }; 3165c88f9eccSDmitry Baryshkov 3166c88f9eccSDmitry Baryshkov qup_spi9_cs: qup-spi9-cs { 3167c88f9eccSDmitry Baryshkov pins = "gpio128"; 3168e5813b15SDmitry Baryshkov function = "qup9"; 3169e5813b15SDmitry Baryshkov }; 3170e5813b15SDmitry Baryshkov 3171eb97ccbbSDmitry Baryshkov qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3172eb97ccbbSDmitry Baryshkov pins = "gpio128"; 3173eb97ccbbSDmitry Baryshkov function = "gpio"; 3174eb97ccbbSDmitry Baryshkov }; 3175eb97ccbbSDmitry Baryshkov 3176c88f9eccSDmitry Baryshkov qup_spi9_data_clk: qup-spi9-data-clk { 3177c88f9eccSDmitry Baryshkov pins = "gpio125", "gpio126", 3178c88f9eccSDmitry Baryshkov "gpio127"; 3179c88f9eccSDmitry Baryshkov function = "qup9"; 3180c88f9eccSDmitry Baryshkov }; 3181c88f9eccSDmitry Baryshkov 3182c88f9eccSDmitry Baryshkov qup_spi10_cs: qup-spi10-cs { 3183c88f9eccSDmitry Baryshkov pins = "gpio132"; 3184e5813b15SDmitry Baryshkov function = "qup10"; 3185e5813b15SDmitry Baryshkov }; 3186e5813b15SDmitry Baryshkov 3187eb97ccbbSDmitry Baryshkov qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3188eb97ccbbSDmitry Baryshkov pins = "gpio132"; 3189eb97ccbbSDmitry Baryshkov function = "gpio"; 3190eb97ccbbSDmitry Baryshkov }; 3191eb97ccbbSDmitry Baryshkov 3192c88f9eccSDmitry Baryshkov qup_spi10_data_clk: qup-spi10-data-clk { 3193c88f9eccSDmitry Baryshkov pins = "gpio129", "gpio130", 3194c88f9eccSDmitry Baryshkov "gpio131"; 3195c88f9eccSDmitry Baryshkov function = "qup10"; 3196c88f9eccSDmitry Baryshkov }; 3197c88f9eccSDmitry Baryshkov 3198c88f9eccSDmitry Baryshkov qup_spi11_cs: qup-spi11-cs { 3199c88f9eccSDmitry Baryshkov pins = "gpio63"; 3200e5813b15SDmitry Baryshkov function = "qup11"; 3201e5813b15SDmitry Baryshkov }; 3202e5813b15SDmitry Baryshkov 3203eb97ccbbSDmitry Baryshkov qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3204eb97ccbbSDmitry Baryshkov pins = "gpio63"; 3205eb97ccbbSDmitry Baryshkov function = "gpio"; 3206eb97ccbbSDmitry Baryshkov }; 3207eb97ccbbSDmitry Baryshkov 3208c88f9eccSDmitry Baryshkov qup_spi11_data_clk: qup-spi11-data-clk { 3209c88f9eccSDmitry Baryshkov pins = "gpio60", "gpio61", 3210c88f9eccSDmitry Baryshkov "gpio62"; 3211c88f9eccSDmitry Baryshkov function = "qup11"; 3212c88f9eccSDmitry Baryshkov }; 3213c88f9eccSDmitry Baryshkov 3214c88f9eccSDmitry Baryshkov qup_spi12_cs: qup-spi12-cs { 3215c88f9eccSDmitry Baryshkov pins = "gpio35"; 3216e5813b15SDmitry Baryshkov function = "qup12"; 3217e5813b15SDmitry Baryshkov }; 3218e5813b15SDmitry Baryshkov 3219eb97ccbbSDmitry Baryshkov qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3220eb97ccbbSDmitry Baryshkov pins = "gpio35"; 3221eb97ccbbSDmitry Baryshkov function = "gpio"; 3222eb97ccbbSDmitry Baryshkov }; 3223eb97ccbbSDmitry Baryshkov 3224c88f9eccSDmitry Baryshkov qup_spi12_data_clk: qup-spi12-data-clk { 3225c88f9eccSDmitry Baryshkov pins = "gpio32", "gpio33", 3226c88f9eccSDmitry Baryshkov "gpio34"; 3227c88f9eccSDmitry Baryshkov function = "qup12"; 3228c88f9eccSDmitry Baryshkov }; 3229c88f9eccSDmitry Baryshkov 3230c88f9eccSDmitry Baryshkov qup_spi13_cs: qup-spi13-cs { 3231c88f9eccSDmitry Baryshkov pins = "gpio39"; 3232e5813b15SDmitry Baryshkov function = "qup13"; 3233e5813b15SDmitry Baryshkov }; 3234e5813b15SDmitry Baryshkov 3235eb97ccbbSDmitry Baryshkov qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3236eb97ccbbSDmitry Baryshkov pins = "gpio39"; 3237eb97ccbbSDmitry Baryshkov function = "gpio"; 3238eb97ccbbSDmitry Baryshkov }; 3239eb97ccbbSDmitry Baryshkov 3240c88f9eccSDmitry Baryshkov qup_spi13_data_clk: qup-spi13-data-clk { 3241c88f9eccSDmitry Baryshkov pins = "gpio36", "gpio37", 3242c88f9eccSDmitry Baryshkov "gpio38"; 3243c88f9eccSDmitry Baryshkov function = "qup13"; 3244c88f9eccSDmitry Baryshkov }; 3245c88f9eccSDmitry Baryshkov 3246c88f9eccSDmitry Baryshkov qup_spi14_cs: qup-spi14-cs { 3247c88f9eccSDmitry Baryshkov pins = "gpio43"; 3248e5813b15SDmitry Baryshkov function = "qup14"; 3249e5813b15SDmitry Baryshkov }; 3250e5813b15SDmitry Baryshkov 3251eb97ccbbSDmitry Baryshkov qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3252eb97ccbbSDmitry Baryshkov pins = "gpio43"; 3253eb97ccbbSDmitry Baryshkov function = "gpio"; 3254eb97ccbbSDmitry Baryshkov }; 3255eb97ccbbSDmitry Baryshkov 3256c88f9eccSDmitry Baryshkov qup_spi14_data_clk: qup-spi14-data-clk { 3257c88f9eccSDmitry Baryshkov pins = "gpio40", "gpio41", 3258c88f9eccSDmitry Baryshkov "gpio42"; 3259c88f9eccSDmitry Baryshkov function = "qup14"; 3260c88f9eccSDmitry Baryshkov }; 3261c88f9eccSDmitry Baryshkov 3262c88f9eccSDmitry Baryshkov qup_spi15_cs: qup-spi15-cs { 3263c88f9eccSDmitry Baryshkov pins = "gpio47"; 3264e5813b15SDmitry Baryshkov function = "qup15"; 3265e5813b15SDmitry Baryshkov }; 3266e5813b15SDmitry Baryshkov 3267eb97ccbbSDmitry Baryshkov qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3268eb97ccbbSDmitry Baryshkov pins = "gpio47"; 3269eb97ccbbSDmitry Baryshkov function = "gpio"; 3270eb97ccbbSDmitry Baryshkov }; 3271eb97ccbbSDmitry Baryshkov 3272c88f9eccSDmitry Baryshkov qup_spi15_data_clk: qup-spi15-data-clk { 3273c88f9eccSDmitry Baryshkov pins = "gpio44", "gpio45", 3274c88f9eccSDmitry Baryshkov "gpio46"; 3275c88f9eccSDmitry Baryshkov function = "qup15"; 3276c88f9eccSDmitry Baryshkov }; 3277c88f9eccSDmitry Baryshkov 3278c88f9eccSDmitry Baryshkov qup_spi16_cs: qup-spi16-cs { 3279c88f9eccSDmitry Baryshkov pins = "gpio51"; 3280e5813b15SDmitry Baryshkov function = "qup16"; 3281e5813b15SDmitry Baryshkov }; 3282e5813b15SDmitry Baryshkov 3283eb97ccbbSDmitry Baryshkov qup_spi16_cs_gpio: qup-spi16-cs-gpio { 3284eb97ccbbSDmitry Baryshkov pins = "gpio51"; 3285eb97ccbbSDmitry Baryshkov function = "gpio"; 3286eb97ccbbSDmitry Baryshkov }; 3287eb97ccbbSDmitry Baryshkov 3288c88f9eccSDmitry Baryshkov qup_spi16_data_clk: qup-spi16-data-clk { 3289c88f9eccSDmitry Baryshkov pins = "gpio48", "gpio49", 3290c88f9eccSDmitry Baryshkov "gpio50"; 3291c88f9eccSDmitry Baryshkov function = "qup16"; 3292c88f9eccSDmitry Baryshkov }; 3293c88f9eccSDmitry Baryshkov 3294c88f9eccSDmitry Baryshkov qup_spi17_cs: qup-spi17-cs { 3295c88f9eccSDmitry Baryshkov pins = "gpio55"; 3296e5813b15SDmitry Baryshkov function = "qup17"; 3297e5813b15SDmitry Baryshkov }; 3298e5813b15SDmitry Baryshkov 3299eb97ccbbSDmitry Baryshkov qup_spi17_cs_gpio: qup-spi17-cs-gpio { 3300eb97ccbbSDmitry Baryshkov pins = "gpio55"; 3301eb97ccbbSDmitry Baryshkov function = "gpio"; 3302eb97ccbbSDmitry Baryshkov }; 3303eb97ccbbSDmitry Baryshkov 3304c88f9eccSDmitry Baryshkov qup_spi17_data_clk: qup-spi17-data-clk { 3305c88f9eccSDmitry Baryshkov pins = "gpio52", "gpio53", 3306c88f9eccSDmitry Baryshkov "gpio54"; 3307c88f9eccSDmitry Baryshkov function = "qup17"; 3308c88f9eccSDmitry Baryshkov }; 3309c88f9eccSDmitry Baryshkov 3310c88f9eccSDmitry Baryshkov qup_spi18_cs: qup-spi18-cs { 3311c88f9eccSDmitry Baryshkov pins = "gpio59"; 3312e5813b15SDmitry Baryshkov function = "qup18"; 3313e5813b15SDmitry Baryshkov }; 3314e5813b15SDmitry Baryshkov 3315eb97ccbbSDmitry Baryshkov qup_spi18_cs_gpio: qup-spi18-cs-gpio { 3316eb97ccbbSDmitry Baryshkov pins = "gpio59"; 3317eb97ccbbSDmitry Baryshkov function = "gpio"; 3318eb97ccbbSDmitry Baryshkov }; 3319eb97ccbbSDmitry Baryshkov 3320c88f9eccSDmitry Baryshkov qup_spi18_data_clk: qup-spi18-data-clk { 3321c88f9eccSDmitry Baryshkov pins = "gpio56", "gpio57", 3322c88f9eccSDmitry Baryshkov "gpio58"; 3323c88f9eccSDmitry Baryshkov function = "qup18"; 3324c88f9eccSDmitry Baryshkov }; 3325c88f9eccSDmitry Baryshkov 3326c88f9eccSDmitry Baryshkov qup_spi19_cs: qup-spi19-cs { 3327c88f9eccSDmitry Baryshkov pins = "gpio3"; 3328c88f9eccSDmitry Baryshkov function = "qup19"; 3329c88f9eccSDmitry Baryshkov }; 3330c88f9eccSDmitry Baryshkov 3331eb97ccbbSDmitry Baryshkov qup_spi19_cs_gpio: qup-spi19-cs-gpio { 3332eb97ccbbSDmitry Baryshkov pins = "gpio3"; 3333eb97ccbbSDmitry Baryshkov function = "gpio"; 3334eb97ccbbSDmitry Baryshkov }; 3335eb97ccbbSDmitry Baryshkov 3336c88f9eccSDmitry Baryshkov qup_spi19_data_clk: qup-spi19-data-clk { 3337e5813b15SDmitry Baryshkov pins = "gpio0", "gpio1", 3338c88f9eccSDmitry Baryshkov "gpio2"; 3339e5813b15SDmitry Baryshkov function = "qup19"; 3340e5813b15SDmitry Baryshkov }; 3341e5813b15SDmitry Baryshkov 334208a9ae2dSDmitry Baryshkov qup_uart2_default: qup-uart2-default { 334308a9ae2dSDmitry Baryshkov mux { 334408a9ae2dSDmitry Baryshkov pins = "gpio117", "gpio118"; 334508a9ae2dSDmitry Baryshkov function = "qup2"; 334608a9ae2dSDmitry Baryshkov }; 334708a9ae2dSDmitry Baryshkov }; 334808a9ae2dSDmitry Baryshkov 334908a9ae2dSDmitry Baryshkov qup_uart6_default: qup-uart6-default { 335008a9ae2dSDmitry Baryshkov mux { 335108a9ae2dSDmitry Baryshkov pins = "gpio16", "gpio17", 335208a9ae2dSDmitry Baryshkov "gpio18", "gpio19"; 335308a9ae2dSDmitry Baryshkov function = "qup6"; 335408a9ae2dSDmitry Baryshkov }; 335508a9ae2dSDmitry Baryshkov }; 335608a9ae2dSDmitry Baryshkov 3357bb1dfb4dSManivannan Sadhasivam qup_uart12_default: qup-uart12-default { 3358bb1dfb4dSManivannan Sadhasivam mux { 3359bb1dfb4dSManivannan Sadhasivam pins = "gpio34", "gpio35"; 3360bb1dfb4dSManivannan Sadhasivam function = "qup12"; 3361bb1dfb4dSManivannan Sadhasivam }; 3362bb1dfb4dSManivannan Sadhasivam }; 336308a9ae2dSDmitry Baryshkov 336408a9ae2dSDmitry Baryshkov qup_uart17_default: qup-uart17-default { 336508a9ae2dSDmitry Baryshkov mux { 336608a9ae2dSDmitry Baryshkov pins = "gpio52", "gpio53", 336708a9ae2dSDmitry Baryshkov "gpio54", "gpio55"; 336808a9ae2dSDmitry Baryshkov function = "qup17"; 336908a9ae2dSDmitry Baryshkov }; 337008a9ae2dSDmitry Baryshkov }; 337108a9ae2dSDmitry Baryshkov 337208a9ae2dSDmitry Baryshkov qup_uart18_default: qup-uart18-default { 337308a9ae2dSDmitry Baryshkov mux { 337408a9ae2dSDmitry Baryshkov pins = "gpio58", "gpio59"; 337508a9ae2dSDmitry Baryshkov function = "qup18"; 337608a9ae2dSDmitry Baryshkov }; 337708a9ae2dSDmitry Baryshkov }; 3378b657d372SSrinivas Kandagatla 3379b657d372SSrinivas Kandagatla tert_mi2s_active: tert-mi2s-active { 3380b657d372SSrinivas Kandagatla sck { 3381b657d372SSrinivas Kandagatla pins = "gpio133"; 3382b657d372SSrinivas Kandagatla function = "mi2s2_sck"; 3383b657d372SSrinivas Kandagatla drive-strength = <8>; 3384b657d372SSrinivas Kandagatla bias-disable; 3385b657d372SSrinivas Kandagatla }; 3386b657d372SSrinivas Kandagatla 3387b657d372SSrinivas Kandagatla data0 { 3388b657d372SSrinivas Kandagatla pins = "gpio134"; 3389b657d372SSrinivas Kandagatla function = "mi2s2_data0"; 3390b657d372SSrinivas Kandagatla drive-strength = <8>; 3391b657d372SSrinivas Kandagatla bias-disable; 3392b657d372SSrinivas Kandagatla output-high; 3393b657d372SSrinivas Kandagatla }; 3394b657d372SSrinivas Kandagatla 3395b657d372SSrinivas Kandagatla ws { 3396b657d372SSrinivas Kandagatla pins = "gpio135"; 3397b657d372SSrinivas Kandagatla function = "mi2s2_ws"; 3398b657d372SSrinivas Kandagatla drive-strength = <8>; 3399b657d372SSrinivas Kandagatla output-high; 3400b657d372SSrinivas Kandagatla }; 3401b657d372SSrinivas Kandagatla }; 340216951b49SBjorn Andersson }; 340316951b49SBjorn Andersson 3404a89441fcSJonathan Marek apps_smmu: iommu@15000000 { 3405a89441fcSJonathan Marek compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 3406a89441fcSJonathan Marek reg = <0 0x15000000 0 0x100000>; 3407a89441fcSJonathan Marek #iommu-cells = <2>; 3408a89441fcSJonathan Marek #global-interrupts = <2>; 3409a89441fcSJonathan Marek interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3410a89441fcSJonathan Marek <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3411a89441fcSJonathan Marek <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3412a89441fcSJonathan Marek <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3413a89441fcSJonathan Marek <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3414a89441fcSJonathan Marek <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3415a89441fcSJonathan Marek <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3416a89441fcSJonathan Marek <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3417a89441fcSJonathan Marek <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3418a89441fcSJonathan Marek <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3419a89441fcSJonathan Marek <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3420a89441fcSJonathan Marek <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3421a89441fcSJonathan Marek <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3422a89441fcSJonathan Marek <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3423a89441fcSJonathan Marek <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3424a89441fcSJonathan Marek <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3425a89441fcSJonathan Marek <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3426a89441fcSJonathan Marek <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3427a89441fcSJonathan Marek <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3428a89441fcSJonathan Marek <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3429a89441fcSJonathan Marek <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3430a89441fcSJonathan Marek <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3431a89441fcSJonathan Marek <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3432a89441fcSJonathan Marek <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3433a89441fcSJonathan Marek <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3434a89441fcSJonathan Marek <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3435a89441fcSJonathan Marek <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3436a89441fcSJonathan Marek <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3437a89441fcSJonathan Marek <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3438a89441fcSJonathan Marek <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3439a89441fcSJonathan Marek <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3440a89441fcSJonathan Marek <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3441a89441fcSJonathan Marek <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3442a89441fcSJonathan Marek <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3443a89441fcSJonathan Marek <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3444a89441fcSJonathan Marek <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3445a89441fcSJonathan Marek <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3446a89441fcSJonathan Marek <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3447a89441fcSJonathan Marek <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3448a89441fcSJonathan Marek <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3449a89441fcSJonathan Marek <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3450a89441fcSJonathan Marek <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3451a89441fcSJonathan Marek <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3452a89441fcSJonathan Marek <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3453a89441fcSJonathan Marek <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3454a89441fcSJonathan Marek <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3455a89441fcSJonathan Marek <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3456a89441fcSJonathan Marek <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3457a89441fcSJonathan Marek <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3458a89441fcSJonathan Marek <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3459a89441fcSJonathan Marek <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3460a89441fcSJonathan Marek <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3461a89441fcSJonathan Marek <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3462a89441fcSJonathan Marek <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3463a89441fcSJonathan Marek <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3464a89441fcSJonathan Marek <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3465a89441fcSJonathan Marek <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3466a89441fcSJonathan Marek <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3467a89441fcSJonathan Marek <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3468a89441fcSJonathan Marek <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3469a89441fcSJonathan Marek <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3470a89441fcSJonathan Marek <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3471a89441fcSJonathan Marek <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3472a89441fcSJonathan Marek <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3473a89441fcSJonathan Marek <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3474a89441fcSJonathan Marek <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3475a89441fcSJonathan Marek <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3476a89441fcSJonathan Marek <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3477a89441fcSJonathan Marek <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3478a89441fcSJonathan Marek <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3479a89441fcSJonathan Marek <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3480a89441fcSJonathan Marek <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3481a89441fcSJonathan Marek <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3482a89441fcSJonathan Marek <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3483a89441fcSJonathan Marek <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3484a89441fcSJonathan Marek <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3485a89441fcSJonathan Marek <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3486a89441fcSJonathan Marek <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3487a89441fcSJonathan Marek <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3488a89441fcSJonathan Marek <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3489a89441fcSJonathan Marek <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3490a89441fcSJonathan Marek <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3491a89441fcSJonathan Marek <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3492a89441fcSJonathan Marek <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3493a89441fcSJonathan Marek <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3494a89441fcSJonathan Marek <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3495a89441fcSJonathan Marek <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3496a89441fcSJonathan Marek <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3497a89441fcSJonathan Marek <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3498a89441fcSJonathan Marek <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3499a89441fcSJonathan Marek <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3500a89441fcSJonathan Marek <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3501a89441fcSJonathan Marek <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3502a89441fcSJonathan Marek <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3503a89441fcSJonathan Marek <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3504a89441fcSJonathan Marek <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3505a89441fcSJonathan Marek <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3506a89441fcSJonathan Marek <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3507a89441fcSJonathan Marek }; 3508a89441fcSJonathan Marek 350923a89037SBjorn Andersson adsp: remoteproc@17300000 { 351023a89037SBjorn Andersson compatible = "qcom,sm8250-adsp-pas"; 351123a89037SBjorn Andersson reg = <0 0x17300000 0 0x100>; 351223a89037SBjorn Andersson 351323a89037SBjorn Andersson interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 351423a89037SBjorn Andersson <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 351523a89037SBjorn Andersson <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 351623a89037SBjorn Andersson <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 351723a89037SBjorn Andersson <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 351823a89037SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 351923a89037SBjorn Andersson "handover", "stop-ack"; 352023a89037SBjorn Andersson 352123a89037SBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>; 352223a89037SBjorn Andersson clock-names = "xo"; 352323a89037SBjorn Andersson 352423a89037SBjorn Andersson power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, 352523a89037SBjorn Andersson <&rpmhpd SM8250_LCX>, 352623a89037SBjorn Andersson <&rpmhpd SM8250_LMX>; 352723a89037SBjorn Andersson power-domain-names = "load_state", "lcx", "lmx"; 352823a89037SBjorn Andersson 352923a89037SBjorn Andersson memory-region = <&adsp_mem>; 353023a89037SBjorn Andersson 353123a89037SBjorn Andersson qcom,smem-states = <&smp2p_adsp_out 0>; 353223a89037SBjorn Andersson qcom,smem-state-names = "stop"; 353323a89037SBjorn Andersson 353423a89037SBjorn Andersson status = "disabled"; 353523a89037SBjorn Andersson 353623a89037SBjorn Andersson glink-edge { 353723a89037SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 353823a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 353923a89037SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 354023a89037SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_LPASS 354123a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 354223a89037SBjorn Andersson 354323a89037SBjorn Andersson label = "lpass"; 354423a89037SBjorn Andersson qcom,remote-pid = <2>; 354525695808SJonathan Marek 354663e10791SSrinivas Kandagatla apr { 354763e10791SSrinivas Kandagatla compatible = "qcom,apr-v2"; 354863e10791SSrinivas Kandagatla qcom,glink-channels = "apr_audio_svc"; 354963e10791SSrinivas Kandagatla qcom,apr-domain = <APR_DOMAIN_ADSP>; 355063e10791SSrinivas Kandagatla #address-cells = <1>; 355163e10791SSrinivas Kandagatla #size-cells = <0>; 355263e10791SSrinivas Kandagatla 355363e10791SSrinivas Kandagatla apr-service@3 { 355463e10791SSrinivas Kandagatla reg = <APR_SVC_ADSP_CORE>; 355563e10791SSrinivas Kandagatla compatible = "qcom,q6core"; 355663e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 355763e10791SSrinivas Kandagatla }; 355863e10791SSrinivas Kandagatla 355963e10791SSrinivas Kandagatla q6afe: apr-service@4 { 356063e10791SSrinivas Kandagatla compatible = "qcom,q6afe"; 356163e10791SSrinivas Kandagatla reg = <APR_SVC_AFE>; 356263e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 356363e10791SSrinivas Kandagatla q6afedai: dais { 356463e10791SSrinivas Kandagatla compatible = "qcom,q6afe-dais"; 356563e10791SSrinivas Kandagatla #address-cells = <1>; 356663e10791SSrinivas Kandagatla #size-cells = <0>; 356763e10791SSrinivas Kandagatla #sound-dai-cells = <1>; 356863e10791SSrinivas Kandagatla }; 356963e10791SSrinivas Kandagatla 357063e10791SSrinivas Kandagatla q6afecc: cc { 357163e10791SSrinivas Kandagatla compatible = "qcom,q6afe-clocks"; 357263e10791SSrinivas Kandagatla #clock-cells = <2>; 357363e10791SSrinivas Kandagatla }; 357463e10791SSrinivas Kandagatla }; 357563e10791SSrinivas Kandagatla 357663e10791SSrinivas Kandagatla q6asm: apr-service@7 { 357763e10791SSrinivas Kandagatla compatible = "qcom,q6asm"; 357863e10791SSrinivas Kandagatla reg = <APR_SVC_ASM>; 357963e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 358063e10791SSrinivas Kandagatla q6asmdai: dais { 358163e10791SSrinivas Kandagatla compatible = "qcom,q6asm-dais"; 358263e10791SSrinivas Kandagatla #address-cells = <1>; 358363e10791SSrinivas Kandagatla #size-cells = <0>; 358463e10791SSrinivas Kandagatla #sound-dai-cells = <1>; 358563e10791SSrinivas Kandagatla iommus = <&apps_smmu 0x1801 0x0>; 358663e10791SSrinivas Kandagatla }; 358763e10791SSrinivas Kandagatla }; 358863e10791SSrinivas Kandagatla 358963e10791SSrinivas Kandagatla q6adm: apr-service@8 { 359063e10791SSrinivas Kandagatla compatible = "qcom,q6adm"; 359163e10791SSrinivas Kandagatla reg = <APR_SVC_ADM>; 359263e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 359363e10791SSrinivas Kandagatla q6routing: routing { 359463e10791SSrinivas Kandagatla compatible = "qcom,q6adm-routing"; 359563e10791SSrinivas Kandagatla #sound-dai-cells = <0>; 359663e10791SSrinivas Kandagatla }; 359763e10791SSrinivas Kandagatla }; 359863e10791SSrinivas Kandagatla }; 359963e10791SSrinivas Kandagatla 360025695808SJonathan Marek fastrpc { 360125695808SJonathan Marek compatible = "qcom,fastrpc"; 360225695808SJonathan Marek qcom,glink-channels = "fastrpcglink-apps-dsp"; 360325695808SJonathan Marek label = "adsp"; 360425695808SJonathan Marek #address-cells = <1>; 360525695808SJonathan Marek #size-cells = <0>; 360625695808SJonathan Marek 360725695808SJonathan Marek compute-cb@3 { 360825695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 360925695808SJonathan Marek reg = <3>; 361025695808SJonathan Marek iommus = <&apps_smmu 0x1803 0x0>; 361125695808SJonathan Marek }; 361225695808SJonathan Marek 361325695808SJonathan Marek compute-cb@4 { 361425695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 361525695808SJonathan Marek reg = <4>; 361625695808SJonathan Marek iommus = <&apps_smmu 0x1804 0x0>; 361725695808SJonathan Marek }; 361825695808SJonathan Marek 361925695808SJonathan Marek compute-cb@5 { 362025695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 362125695808SJonathan Marek reg = <5>; 362225695808SJonathan Marek iommus = <&apps_smmu 0x1805 0x0>; 362325695808SJonathan Marek }; 362425695808SJonathan Marek }; 362523a89037SBjorn Andersson }; 362623a89037SBjorn Andersson }; 362723a89037SBjorn Andersson 3628b9ec8cbcSJonathan Marek intc: interrupt-controller@17a00000 { 3629b9ec8cbcSJonathan Marek compatible = "arm,gic-v3"; 3630b9ec8cbcSJonathan Marek #interrupt-cells = <3>; 3631b9ec8cbcSJonathan Marek interrupt-controller; 3632b9ec8cbcSJonathan Marek reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3633b9ec8cbcSJonathan Marek <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3634b9ec8cbcSJonathan Marek interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3635b9ec8cbcSJonathan Marek }; 3636b9ec8cbcSJonathan Marek 3637e0d9acceSDmitry Baryshkov watchdog@17c10000 { 3638e0d9acceSDmitry Baryshkov compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 3639e0d9acceSDmitry Baryshkov reg = <0 0x17c10000 0 0x1000>; 3640e0d9acceSDmitry Baryshkov clocks = <&sleep_clk>; 364146a4359fSSai Prakash Ranjan interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3642e0d9acceSDmitry Baryshkov }; 3643e0d9acceSDmitry Baryshkov 3644b9ec8cbcSJonathan Marek timer@17c20000 { 3645b9ec8cbcSJonathan Marek #address-cells = <2>; 3646b9ec8cbcSJonathan Marek #size-cells = <2>; 3647b9ec8cbcSJonathan Marek ranges; 3648b9ec8cbcSJonathan Marek compatible = "arm,armv7-timer-mem"; 3649b9ec8cbcSJonathan Marek reg = <0x0 0x17c20000 0x0 0x1000>; 3650b9ec8cbcSJonathan Marek clock-frequency = <19200000>; 3651b9ec8cbcSJonathan Marek 3652b9ec8cbcSJonathan Marek frame@17c21000 { 3653b9ec8cbcSJonathan Marek frame-number = <0>; 3654b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3655b9ec8cbcSJonathan Marek <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3656b9ec8cbcSJonathan Marek reg = <0x0 0x17c21000 0x0 0x1000>, 3657b9ec8cbcSJonathan Marek <0x0 0x17c22000 0x0 0x1000>; 3658b9ec8cbcSJonathan Marek }; 3659b9ec8cbcSJonathan Marek 3660b9ec8cbcSJonathan Marek frame@17c23000 { 3661b9ec8cbcSJonathan Marek frame-number = <1>; 3662b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3663b9ec8cbcSJonathan Marek reg = <0x0 0x17c23000 0x0 0x1000>; 3664b9ec8cbcSJonathan Marek status = "disabled"; 3665b9ec8cbcSJonathan Marek }; 3666b9ec8cbcSJonathan Marek 3667b9ec8cbcSJonathan Marek frame@17c25000 { 3668b9ec8cbcSJonathan Marek frame-number = <2>; 3669b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3670b9ec8cbcSJonathan Marek reg = <0x0 0x17c25000 0x0 0x1000>; 3671b9ec8cbcSJonathan Marek status = "disabled"; 3672b9ec8cbcSJonathan Marek }; 3673b9ec8cbcSJonathan Marek 3674b9ec8cbcSJonathan Marek frame@17c27000 { 3675b9ec8cbcSJonathan Marek frame-number = <3>; 3676b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3677b9ec8cbcSJonathan Marek reg = <0x0 0x17c27000 0x0 0x1000>; 3678b9ec8cbcSJonathan Marek status = "disabled"; 3679b9ec8cbcSJonathan Marek }; 3680b9ec8cbcSJonathan Marek 3681b9ec8cbcSJonathan Marek frame@17c29000 { 3682b9ec8cbcSJonathan Marek frame-number = <4>; 3683b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3684b9ec8cbcSJonathan Marek reg = <0x0 0x17c29000 0x0 0x1000>; 3685b9ec8cbcSJonathan Marek status = "disabled"; 3686b9ec8cbcSJonathan Marek }; 3687b9ec8cbcSJonathan Marek 3688b9ec8cbcSJonathan Marek frame@17c2b000 { 3689b9ec8cbcSJonathan Marek frame-number = <5>; 3690b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3691b9ec8cbcSJonathan Marek reg = <0x0 0x17c2b000 0x0 0x1000>; 3692b9ec8cbcSJonathan Marek status = "disabled"; 3693b9ec8cbcSJonathan Marek }; 3694b9ec8cbcSJonathan Marek 3695b9ec8cbcSJonathan Marek frame@17c2d000 { 3696b9ec8cbcSJonathan Marek frame-number = <6>; 3697b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3698b9ec8cbcSJonathan Marek reg = <0x0 0x17c2d000 0x0 0x1000>; 3699b9ec8cbcSJonathan Marek status = "disabled"; 3700b9ec8cbcSJonathan Marek }; 3701b9ec8cbcSJonathan Marek }; 3702b9ec8cbcSJonathan Marek 370360378f1aSVenkata Narendra Kumar Gutta apps_rsc: rsc@18200000 { 370460378f1aSVenkata Narendra Kumar Gutta label = "apps_rsc"; 370560378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,rpmh-rsc"; 370660378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x18200000 0x0 0x10000>, 370760378f1aSVenkata Narendra Kumar Gutta <0x0 0x18210000 0x0 0x10000>, 370860378f1aSVenkata Narendra Kumar Gutta <0x0 0x18220000 0x0 0x10000>; 370960378f1aSVenkata Narendra Kumar Gutta reg-names = "drv-0", "drv-1", "drv-2"; 371060378f1aSVenkata Narendra Kumar Gutta interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 371160378f1aSVenkata Narendra Kumar Gutta <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 371260378f1aSVenkata Narendra Kumar Gutta <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 371360378f1aSVenkata Narendra Kumar Gutta qcom,tcs-offset = <0xd00>; 371460378f1aSVenkata Narendra Kumar Gutta qcom,drv-id = <2>; 371560378f1aSVenkata Narendra Kumar Gutta qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 371660378f1aSVenkata Narendra Kumar Gutta <WAKE_TCS 3>, <CONTROL_TCS 1>; 371760378f1aSVenkata Narendra Kumar Gutta 371860378f1aSVenkata Narendra Kumar Gutta rpmhcc: clock-controller { 371960378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,sm8250-rpmh-clk"; 372060378f1aSVenkata Narendra Kumar Gutta #clock-cells = <1>; 372160378f1aSVenkata Narendra Kumar Gutta clock-names = "xo"; 372260378f1aSVenkata Narendra Kumar Gutta clocks = <&xo_board>; 372360378f1aSVenkata Narendra Kumar Gutta }; 3724b6f78e27SBjorn Andersson 3725b6f78e27SBjorn Andersson rpmhpd: power-controller { 3726b6f78e27SBjorn Andersson compatible = "qcom,sm8250-rpmhpd"; 3727b6f78e27SBjorn Andersson #power-domain-cells = <1>; 3728b6f78e27SBjorn Andersson operating-points-v2 = <&rpmhpd_opp_table>; 3729b6f78e27SBjorn Andersson 3730b6f78e27SBjorn Andersson rpmhpd_opp_table: opp-table { 3731b6f78e27SBjorn Andersson compatible = "operating-points-v2"; 3732b6f78e27SBjorn Andersson 3733b6f78e27SBjorn Andersson rpmhpd_opp_ret: opp1 { 3734b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3735b6f78e27SBjorn Andersson }; 3736b6f78e27SBjorn Andersson 3737b6f78e27SBjorn Andersson rpmhpd_opp_min_svs: opp2 { 3738b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3739b6f78e27SBjorn Andersson }; 3740b6f78e27SBjorn Andersson 3741b6f78e27SBjorn Andersson rpmhpd_opp_low_svs: opp3 { 3742b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3743b6f78e27SBjorn Andersson }; 3744b6f78e27SBjorn Andersson 3745b6f78e27SBjorn Andersson rpmhpd_opp_svs: opp4 { 3746b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3747b6f78e27SBjorn Andersson }; 3748b6f78e27SBjorn Andersson 3749b6f78e27SBjorn Andersson rpmhpd_opp_svs_l1: opp5 { 3750b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3751b6f78e27SBjorn Andersson }; 3752b6f78e27SBjorn Andersson 3753b6f78e27SBjorn Andersson rpmhpd_opp_nom: opp6 { 3754b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3755b6f78e27SBjorn Andersson }; 3756b6f78e27SBjorn Andersson 3757b6f78e27SBjorn Andersson rpmhpd_opp_nom_l1: opp7 { 3758b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3759b6f78e27SBjorn Andersson }; 3760b6f78e27SBjorn Andersson 3761b6f78e27SBjorn Andersson rpmhpd_opp_nom_l2: opp8 { 3762b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3763b6f78e27SBjorn Andersson }; 3764b6f78e27SBjorn Andersson 3765b6f78e27SBjorn Andersson rpmhpd_opp_turbo: opp9 { 3766b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3767b6f78e27SBjorn Andersson }; 3768b6f78e27SBjorn Andersson 3769b6f78e27SBjorn Andersson rpmhpd_opp_turbo_l1: opp10 { 3770b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3771b6f78e27SBjorn Andersson }; 3772b6f78e27SBjorn Andersson }; 3773b6f78e27SBjorn Andersson }; 3774e7e41a20SJonathan Marek 3775e7e41a20SJonathan Marek apps_bcm_voter: bcm_voter { 3776e7e41a20SJonathan Marek compatible = "qcom,bcm-voter"; 3777e7e41a20SJonathan Marek }; 377860378f1aSVenkata Narendra Kumar Gutta }; 377979a595bbSSibi Sankar 378079a595bbSSibi Sankar epss_l3: interconnect@18591000 { 378179a595bbSSibi Sankar compatible = "qcom,sm8250-epss-l3"; 378279a595bbSSibi Sankar reg = <0 0x18590000 0 0x1000>; 378379a595bbSSibi Sankar 378479a595bbSSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 378579a595bbSSibi Sankar clock-names = "xo", "alternate"; 378679a595bbSSibi Sankar 378779a595bbSSibi Sankar #interconnect-cells = <1>; 378879a595bbSSibi Sankar }; 378902ae4a0eSBjorn Andersson 379002ae4a0eSBjorn Andersson cpufreq_hw: cpufreq@18591000 { 379102ae4a0eSBjorn Andersson compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 379202ae4a0eSBjorn Andersson reg = <0 0x18591000 0 0x1000>, 379302ae4a0eSBjorn Andersson <0 0x18592000 0 0x1000>, 379402ae4a0eSBjorn Andersson <0 0x18593000 0 0x1000>; 379502ae4a0eSBjorn Andersson reg-names = "freq-domain0", "freq-domain1", 379602ae4a0eSBjorn Andersson "freq-domain2"; 379702ae4a0eSBjorn Andersson 379802ae4a0eSBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 379902ae4a0eSBjorn Andersson clock-names = "xo", "alternate"; 380002ae4a0eSBjorn Andersson 380102ae4a0eSBjorn Andersson #freq-domain-cells = <1>; 380202ae4a0eSBjorn Andersson }; 380360378f1aSVenkata Narendra Kumar Gutta }; 380460378f1aSVenkata Narendra Kumar Gutta 380560378f1aSVenkata Narendra Kumar Gutta timer { 380660378f1aSVenkata Narendra Kumar Gutta compatible = "arm,armv8-timer"; 380760378f1aSVenkata Narendra Kumar Gutta interrupts = <GIC_PPI 13 380860378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 380960378f1aSVenkata Narendra Kumar Gutta <GIC_PPI 14 381060378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 381160378f1aSVenkata Narendra Kumar Gutta <GIC_PPI 11 381260378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 381329a33495SSai Prakash Ranjan <GIC_PPI 10 381460378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 381560378f1aSVenkata Narendra Kumar Gutta }; 3816bac12f25SAmit Kucheria 3817bac12f25SAmit Kucheria thermal-zones { 3818bac12f25SAmit Kucheria cpu0-thermal { 3819bac12f25SAmit Kucheria polling-delay-passive = <250>; 3820bac12f25SAmit Kucheria polling-delay = <1000>; 3821bac12f25SAmit Kucheria 3822bac12f25SAmit Kucheria thermal-sensors = <&tsens0 1>; 3823bac12f25SAmit Kucheria 3824bac12f25SAmit Kucheria trips { 3825bac12f25SAmit Kucheria cpu0_alert0: trip-point0 { 3826bac12f25SAmit Kucheria temperature = <90000>; 3827bac12f25SAmit Kucheria hysteresis = <2000>; 3828bac12f25SAmit Kucheria type = "passive"; 3829bac12f25SAmit Kucheria }; 3830bac12f25SAmit Kucheria 3831bac12f25SAmit Kucheria cpu0_alert1: trip-point1 { 3832bac12f25SAmit Kucheria temperature = <95000>; 3833bac12f25SAmit Kucheria hysteresis = <2000>; 3834bac12f25SAmit Kucheria type = "passive"; 3835bac12f25SAmit Kucheria }; 3836bac12f25SAmit Kucheria 3837bac12f25SAmit Kucheria cpu0_crit: cpu_crit { 3838bac12f25SAmit Kucheria temperature = <110000>; 3839bac12f25SAmit Kucheria hysteresis = <1000>; 3840bac12f25SAmit Kucheria type = "critical"; 3841bac12f25SAmit Kucheria }; 3842bac12f25SAmit Kucheria }; 3843bac12f25SAmit Kucheria 3844bac12f25SAmit Kucheria cooling-maps { 3845bac12f25SAmit Kucheria map0 { 3846bac12f25SAmit Kucheria trip = <&cpu0_alert0>; 3847bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3848bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3849bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3850bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3851bac12f25SAmit Kucheria }; 3852bac12f25SAmit Kucheria map1 { 3853bac12f25SAmit Kucheria trip = <&cpu0_alert1>; 3854bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3855bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3856bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3857bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3858bac12f25SAmit Kucheria }; 3859bac12f25SAmit Kucheria }; 3860bac12f25SAmit Kucheria }; 3861bac12f25SAmit Kucheria 3862bac12f25SAmit Kucheria cpu1-thermal { 3863bac12f25SAmit Kucheria polling-delay-passive = <250>; 3864bac12f25SAmit Kucheria polling-delay = <1000>; 3865bac12f25SAmit Kucheria 3866bac12f25SAmit Kucheria thermal-sensors = <&tsens0 2>; 3867bac12f25SAmit Kucheria 3868bac12f25SAmit Kucheria trips { 3869bac12f25SAmit Kucheria cpu1_alert0: trip-point0 { 3870bac12f25SAmit Kucheria temperature = <90000>; 3871bac12f25SAmit Kucheria hysteresis = <2000>; 3872bac12f25SAmit Kucheria type = "passive"; 3873bac12f25SAmit Kucheria }; 3874bac12f25SAmit Kucheria 3875bac12f25SAmit Kucheria cpu1_alert1: trip-point1 { 3876bac12f25SAmit Kucheria temperature = <95000>; 3877bac12f25SAmit Kucheria hysteresis = <2000>; 3878bac12f25SAmit Kucheria type = "passive"; 3879bac12f25SAmit Kucheria }; 3880bac12f25SAmit Kucheria 3881bac12f25SAmit Kucheria cpu1_crit: cpu_crit { 3882bac12f25SAmit Kucheria temperature = <110000>; 3883bac12f25SAmit Kucheria hysteresis = <1000>; 3884bac12f25SAmit Kucheria type = "critical"; 3885bac12f25SAmit Kucheria }; 3886bac12f25SAmit Kucheria }; 3887bac12f25SAmit Kucheria 3888bac12f25SAmit Kucheria cooling-maps { 3889bac12f25SAmit Kucheria map0 { 3890bac12f25SAmit Kucheria trip = <&cpu1_alert0>; 3891bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3892bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3893bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3894bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3895bac12f25SAmit Kucheria }; 3896bac12f25SAmit Kucheria map1 { 3897bac12f25SAmit Kucheria trip = <&cpu1_alert1>; 3898bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3899bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3900bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3901bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3902bac12f25SAmit Kucheria }; 3903bac12f25SAmit Kucheria }; 3904bac12f25SAmit Kucheria }; 3905bac12f25SAmit Kucheria 3906bac12f25SAmit Kucheria cpu2-thermal { 3907bac12f25SAmit Kucheria polling-delay-passive = <250>; 3908bac12f25SAmit Kucheria polling-delay = <1000>; 3909bac12f25SAmit Kucheria 3910bac12f25SAmit Kucheria thermal-sensors = <&tsens0 3>; 3911bac12f25SAmit Kucheria 3912bac12f25SAmit Kucheria trips { 3913bac12f25SAmit Kucheria cpu2_alert0: trip-point0 { 3914bac12f25SAmit Kucheria temperature = <90000>; 3915bac12f25SAmit Kucheria hysteresis = <2000>; 3916bac12f25SAmit Kucheria type = "passive"; 3917bac12f25SAmit Kucheria }; 3918bac12f25SAmit Kucheria 3919bac12f25SAmit Kucheria cpu2_alert1: trip-point1 { 3920bac12f25SAmit Kucheria temperature = <95000>; 3921bac12f25SAmit Kucheria hysteresis = <2000>; 3922bac12f25SAmit Kucheria type = "passive"; 3923bac12f25SAmit Kucheria }; 3924bac12f25SAmit Kucheria 3925bac12f25SAmit Kucheria cpu2_crit: cpu_crit { 3926bac12f25SAmit Kucheria temperature = <110000>; 3927bac12f25SAmit Kucheria hysteresis = <1000>; 3928bac12f25SAmit Kucheria type = "critical"; 3929bac12f25SAmit Kucheria }; 3930bac12f25SAmit Kucheria }; 3931bac12f25SAmit Kucheria 3932bac12f25SAmit Kucheria cooling-maps { 3933bac12f25SAmit Kucheria map0 { 3934bac12f25SAmit Kucheria trip = <&cpu2_alert0>; 3935bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3936bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3937bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3938bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3939bac12f25SAmit Kucheria }; 3940bac12f25SAmit Kucheria map1 { 3941bac12f25SAmit Kucheria trip = <&cpu2_alert1>; 3942bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3943bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3944bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3945bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3946bac12f25SAmit Kucheria }; 3947bac12f25SAmit Kucheria }; 3948bac12f25SAmit Kucheria }; 3949bac12f25SAmit Kucheria 3950bac12f25SAmit Kucheria cpu3-thermal { 3951bac12f25SAmit Kucheria polling-delay-passive = <250>; 3952bac12f25SAmit Kucheria polling-delay = <1000>; 3953bac12f25SAmit Kucheria 3954bac12f25SAmit Kucheria thermal-sensors = <&tsens0 4>; 3955bac12f25SAmit Kucheria 3956bac12f25SAmit Kucheria trips { 3957bac12f25SAmit Kucheria cpu3_alert0: trip-point0 { 3958bac12f25SAmit Kucheria temperature = <90000>; 3959bac12f25SAmit Kucheria hysteresis = <2000>; 3960bac12f25SAmit Kucheria type = "passive"; 3961bac12f25SAmit Kucheria }; 3962bac12f25SAmit Kucheria 3963bac12f25SAmit Kucheria cpu3_alert1: trip-point1 { 3964bac12f25SAmit Kucheria temperature = <95000>; 3965bac12f25SAmit Kucheria hysteresis = <2000>; 3966bac12f25SAmit Kucheria type = "passive"; 3967bac12f25SAmit Kucheria }; 3968bac12f25SAmit Kucheria 3969bac12f25SAmit Kucheria cpu3_crit: cpu_crit { 3970bac12f25SAmit Kucheria temperature = <110000>; 3971bac12f25SAmit Kucheria hysteresis = <1000>; 3972bac12f25SAmit Kucheria type = "critical"; 3973bac12f25SAmit Kucheria }; 3974bac12f25SAmit Kucheria }; 3975bac12f25SAmit Kucheria 3976bac12f25SAmit Kucheria cooling-maps { 3977bac12f25SAmit Kucheria map0 { 3978bac12f25SAmit Kucheria trip = <&cpu3_alert0>; 3979bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3980bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3981bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3982bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3983bac12f25SAmit Kucheria }; 3984bac12f25SAmit Kucheria map1 { 3985bac12f25SAmit Kucheria trip = <&cpu3_alert1>; 3986bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3987bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3988bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3989bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3990bac12f25SAmit Kucheria }; 3991bac12f25SAmit Kucheria }; 3992bac12f25SAmit Kucheria }; 3993bac12f25SAmit Kucheria 3994bac12f25SAmit Kucheria cpu4-top-thermal { 3995bac12f25SAmit Kucheria polling-delay-passive = <250>; 3996bac12f25SAmit Kucheria polling-delay = <1000>; 3997bac12f25SAmit Kucheria 3998bac12f25SAmit Kucheria thermal-sensors = <&tsens0 7>; 3999bac12f25SAmit Kucheria 4000bac12f25SAmit Kucheria trips { 4001bac12f25SAmit Kucheria cpu4_top_alert0: trip-point0 { 4002bac12f25SAmit Kucheria temperature = <90000>; 4003bac12f25SAmit Kucheria hysteresis = <2000>; 4004bac12f25SAmit Kucheria type = "passive"; 4005bac12f25SAmit Kucheria }; 4006bac12f25SAmit Kucheria 4007bac12f25SAmit Kucheria cpu4_top_alert1: trip-point1 { 4008bac12f25SAmit Kucheria temperature = <95000>; 4009bac12f25SAmit Kucheria hysteresis = <2000>; 4010bac12f25SAmit Kucheria type = "passive"; 4011bac12f25SAmit Kucheria }; 4012bac12f25SAmit Kucheria 4013bac12f25SAmit Kucheria cpu4_top_crit: cpu_crit { 4014bac12f25SAmit Kucheria temperature = <110000>; 4015bac12f25SAmit Kucheria hysteresis = <1000>; 4016bac12f25SAmit Kucheria type = "critical"; 4017bac12f25SAmit Kucheria }; 4018bac12f25SAmit Kucheria }; 4019bac12f25SAmit Kucheria 4020bac12f25SAmit Kucheria cooling-maps { 4021bac12f25SAmit Kucheria map0 { 4022bac12f25SAmit Kucheria trip = <&cpu4_top_alert0>; 4023bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4024bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4025bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4026bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4027bac12f25SAmit Kucheria }; 4028bac12f25SAmit Kucheria map1 { 4029bac12f25SAmit Kucheria trip = <&cpu4_top_alert1>; 4030bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4031bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4032bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4033bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4034bac12f25SAmit Kucheria }; 4035bac12f25SAmit Kucheria }; 4036bac12f25SAmit Kucheria }; 4037bac12f25SAmit Kucheria 4038bac12f25SAmit Kucheria cpu5-top-thermal { 4039bac12f25SAmit Kucheria polling-delay-passive = <250>; 4040bac12f25SAmit Kucheria polling-delay = <1000>; 4041bac12f25SAmit Kucheria 4042bac12f25SAmit Kucheria thermal-sensors = <&tsens0 8>; 4043bac12f25SAmit Kucheria 4044bac12f25SAmit Kucheria trips { 4045bac12f25SAmit Kucheria cpu5_top_alert0: trip-point0 { 4046bac12f25SAmit Kucheria temperature = <90000>; 4047bac12f25SAmit Kucheria hysteresis = <2000>; 4048bac12f25SAmit Kucheria type = "passive"; 4049bac12f25SAmit Kucheria }; 4050bac12f25SAmit Kucheria 4051bac12f25SAmit Kucheria cpu5_top_alert1: trip-point1 { 4052bac12f25SAmit Kucheria temperature = <95000>; 4053bac12f25SAmit Kucheria hysteresis = <2000>; 4054bac12f25SAmit Kucheria type = "passive"; 4055bac12f25SAmit Kucheria }; 4056bac12f25SAmit Kucheria 4057bac12f25SAmit Kucheria cpu5_top_crit: cpu_crit { 4058bac12f25SAmit Kucheria temperature = <110000>; 4059bac12f25SAmit Kucheria hysteresis = <1000>; 4060bac12f25SAmit Kucheria type = "critical"; 4061bac12f25SAmit Kucheria }; 4062bac12f25SAmit Kucheria }; 4063bac12f25SAmit Kucheria 4064bac12f25SAmit Kucheria cooling-maps { 4065bac12f25SAmit Kucheria map0 { 4066bac12f25SAmit Kucheria trip = <&cpu5_top_alert0>; 4067bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4068bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4069bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4070bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4071bac12f25SAmit Kucheria }; 4072bac12f25SAmit Kucheria map1 { 4073bac12f25SAmit Kucheria trip = <&cpu5_top_alert1>; 4074bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4075bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4076bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4077bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4078bac12f25SAmit Kucheria }; 4079bac12f25SAmit Kucheria }; 4080bac12f25SAmit Kucheria }; 4081bac12f25SAmit Kucheria 4082bac12f25SAmit Kucheria cpu6-top-thermal { 4083bac12f25SAmit Kucheria polling-delay-passive = <250>; 4084bac12f25SAmit Kucheria polling-delay = <1000>; 4085bac12f25SAmit Kucheria 4086bac12f25SAmit Kucheria thermal-sensors = <&tsens0 9>; 4087bac12f25SAmit Kucheria 4088bac12f25SAmit Kucheria trips { 4089bac12f25SAmit Kucheria cpu6_top_alert0: trip-point0 { 4090bac12f25SAmit Kucheria temperature = <90000>; 4091bac12f25SAmit Kucheria hysteresis = <2000>; 4092bac12f25SAmit Kucheria type = "passive"; 4093bac12f25SAmit Kucheria }; 4094bac12f25SAmit Kucheria 4095bac12f25SAmit Kucheria cpu6_top_alert1: trip-point1 { 4096bac12f25SAmit Kucheria temperature = <95000>; 4097bac12f25SAmit Kucheria hysteresis = <2000>; 4098bac12f25SAmit Kucheria type = "passive"; 4099bac12f25SAmit Kucheria }; 4100bac12f25SAmit Kucheria 4101bac12f25SAmit Kucheria cpu6_top_crit: cpu_crit { 4102bac12f25SAmit Kucheria temperature = <110000>; 4103bac12f25SAmit Kucheria hysteresis = <1000>; 4104bac12f25SAmit Kucheria type = "critical"; 4105bac12f25SAmit Kucheria }; 4106bac12f25SAmit Kucheria }; 4107bac12f25SAmit Kucheria 4108bac12f25SAmit Kucheria cooling-maps { 4109bac12f25SAmit Kucheria map0 { 4110bac12f25SAmit Kucheria trip = <&cpu6_top_alert0>; 4111bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4112bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4113bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4114bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4115bac12f25SAmit Kucheria }; 4116bac12f25SAmit Kucheria map1 { 4117bac12f25SAmit Kucheria trip = <&cpu6_top_alert1>; 4118bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4119bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4120bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4121bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4122bac12f25SAmit Kucheria }; 4123bac12f25SAmit Kucheria }; 4124bac12f25SAmit Kucheria }; 4125bac12f25SAmit Kucheria 4126bac12f25SAmit Kucheria cpu7-top-thermal { 4127bac12f25SAmit Kucheria polling-delay-passive = <250>; 4128bac12f25SAmit Kucheria polling-delay = <1000>; 4129bac12f25SAmit Kucheria 4130bac12f25SAmit Kucheria thermal-sensors = <&tsens0 10>; 4131bac12f25SAmit Kucheria 4132bac12f25SAmit Kucheria trips { 4133bac12f25SAmit Kucheria cpu7_top_alert0: trip-point0 { 4134bac12f25SAmit Kucheria temperature = <90000>; 4135bac12f25SAmit Kucheria hysteresis = <2000>; 4136bac12f25SAmit Kucheria type = "passive"; 4137bac12f25SAmit Kucheria }; 4138bac12f25SAmit Kucheria 4139bac12f25SAmit Kucheria cpu7_top_alert1: trip-point1 { 4140bac12f25SAmit Kucheria temperature = <95000>; 4141bac12f25SAmit Kucheria hysteresis = <2000>; 4142bac12f25SAmit Kucheria type = "passive"; 4143bac12f25SAmit Kucheria }; 4144bac12f25SAmit Kucheria 4145bac12f25SAmit Kucheria cpu7_top_crit: cpu_crit { 4146bac12f25SAmit Kucheria temperature = <110000>; 4147bac12f25SAmit Kucheria hysteresis = <1000>; 4148bac12f25SAmit Kucheria type = "critical"; 4149bac12f25SAmit Kucheria }; 4150bac12f25SAmit Kucheria }; 4151bac12f25SAmit Kucheria 4152bac12f25SAmit Kucheria cooling-maps { 4153bac12f25SAmit Kucheria map0 { 4154bac12f25SAmit Kucheria trip = <&cpu7_top_alert0>; 4155bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4156bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4157bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4158bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4159bac12f25SAmit Kucheria }; 4160bac12f25SAmit Kucheria map1 { 4161bac12f25SAmit Kucheria trip = <&cpu7_top_alert1>; 4162bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4163bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4164bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4165bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4166bac12f25SAmit Kucheria }; 4167bac12f25SAmit Kucheria }; 4168bac12f25SAmit Kucheria }; 4169bac12f25SAmit Kucheria 4170bac12f25SAmit Kucheria cpu4-bottom-thermal { 4171bac12f25SAmit Kucheria polling-delay-passive = <250>; 4172bac12f25SAmit Kucheria polling-delay = <1000>; 4173bac12f25SAmit Kucheria 4174bac12f25SAmit Kucheria thermal-sensors = <&tsens0 11>; 4175bac12f25SAmit Kucheria 4176bac12f25SAmit Kucheria trips { 4177bac12f25SAmit Kucheria cpu4_bottom_alert0: trip-point0 { 4178bac12f25SAmit Kucheria temperature = <90000>; 4179bac12f25SAmit Kucheria hysteresis = <2000>; 4180bac12f25SAmit Kucheria type = "passive"; 4181bac12f25SAmit Kucheria }; 4182bac12f25SAmit Kucheria 4183bac12f25SAmit Kucheria cpu4_bottom_alert1: trip-point1 { 4184bac12f25SAmit Kucheria temperature = <95000>; 4185bac12f25SAmit Kucheria hysteresis = <2000>; 4186bac12f25SAmit Kucheria type = "passive"; 4187bac12f25SAmit Kucheria }; 4188bac12f25SAmit Kucheria 4189bac12f25SAmit Kucheria cpu4_bottom_crit: cpu_crit { 4190bac12f25SAmit Kucheria temperature = <110000>; 4191bac12f25SAmit Kucheria hysteresis = <1000>; 4192bac12f25SAmit Kucheria type = "critical"; 4193bac12f25SAmit Kucheria }; 4194bac12f25SAmit Kucheria }; 4195bac12f25SAmit Kucheria 4196bac12f25SAmit Kucheria cooling-maps { 4197bac12f25SAmit Kucheria map0 { 4198bac12f25SAmit Kucheria trip = <&cpu4_bottom_alert0>; 4199bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4200bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4201bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4202bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4203bac12f25SAmit Kucheria }; 4204bac12f25SAmit Kucheria map1 { 4205bac12f25SAmit Kucheria trip = <&cpu4_bottom_alert1>; 4206bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4207bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4208bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4209bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4210bac12f25SAmit Kucheria }; 4211bac12f25SAmit Kucheria }; 4212bac12f25SAmit Kucheria }; 4213bac12f25SAmit Kucheria 4214bac12f25SAmit Kucheria cpu5-bottom-thermal { 4215bac12f25SAmit Kucheria polling-delay-passive = <250>; 4216bac12f25SAmit Kucheria polling-delay = <1000>; 4217bac12f25SAmit Kucheria 4218bac12f25SAmit Kucheria thermal-sensors = <&tsens0 12>; 4219bac12f25SAmit Kucheria 4220bac12f25SAmit Kucheria trips { 4221bac12f25SAmit Kucheria cpu5_bottom_alert0: trip-point0 { 4222bac12f25SAmit Kucheria temperature = <90000>; 4223bac12f25SAmit Kucheria hysteresis = <2000>; 4224bac12f25SAmit Kucheria type = "passive"; 4225bac12f25SAmit Kucheria }; 4226bac12f25SAmit Kucheria 4227bac12f25SAmit Kucheria cpu5_bottom_alert1: trip-point1 { 4228bac12f25SAmit Kucheria temperature = <95000>; 4229bac12f25SAmit Kucheria hysteresis = <2000>; 4230bac12f25SAmit Kucheria type = "passive"; 4231bac12f25SAmit Kucheria }; 4232bac12f25SAmit Kucheria 4233bac12f25SAmit Kucheria cpu5_bottom_crit: cpu_crit { 4234bac12f25SAmit Kucheria temperature = <110000>; 4235bac12f25SAmit Kucheria hysteresis = <1000>; 4236bac12f25SAmit Kucheria type = "critical"; 4237bac12f25SAmit Kucheria }; 4238bac12f25SAmit Kucheria }; 4239bac12f25SAmit Kucheria 4240bac12f25SAmit Kucheria cooling-maps { 4241bac12f25SAmit Kucheria map0 { 4242bac12f25SAmit Kucheria trip = <&cpu5_bottom_alert0>; 4243bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4244bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4245bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4246bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4247bac12f25SAmit Kucheria }; 4248bac12f25SAmit Kucheria map1 { 4249bac12f25SAmit Kucheria trip = <&cpu5_bottom_alert1>; 4250bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4251bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4252bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4253bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4254bac12f25SAmit Kucheria }; 4255bac12f25SAmit Kucheria }; 4256bac12f25SAmit Kucheria }; 4257bac12f25SAmit Kucheria 4258bac12f25SAmit Kucheria cpu6-bottom-thermal { 4259bac12f25SAmit Kucheria polling-delay-passive = <250>; 4260bac12f25SAmit Kucheria polling-delay = <1000>; 4261bac12f25SAmit Kucheria 4262bac12f25SAmit Kucheria thermal-sensors = <&tsens0 13>; 4263bac12f25SAmit Kucheria 4264bac12f25SAmit Kucheria trips { 4265bac12f25SAmit Kucheria cpu6_bottom_alert0: trip-point0 { 4266bac12f25SAmit Kucheria temperature = <90000>; 4267bac12f25SAmit Kucheria hysteresis = <2000>; 4268bac12f25SAmit Kucheria type = "passive"; 4269bac12f25SAmit Kucheria }; 4270bac12f25SAmit Kucheria 4271bac12f25SAmit Kucheria cpu6_bottom_alert1: trip-point1 { 4272bac12f25SAmit Kucheria temperature = <95000>; 4273bac12f25SAmit Kucheria hysteresis = <2000>; 4274bac12f25SAmit Kucheria type = "passive"; 4275bac12f25SAmit Kucheria }; 4276bac12f25SAmit Kucheria 4277bac12f25SAmit Kucheria cpu6_bottom_crit: cpu_crit { 4278bac12f25SAmit Kucheria temperature = <110000>; 4279bac12f25SAmit Kucheria hysteresis = <1000>; 4280bac12f25SAmit Kucheria type = "critical"; 4281bac12f25SAmit Kucheria }; 4282bac12f25SAmit Kucheria }; 4283bac12f25SAmit Kucheria 4284bac12f25SAmit Kucheria cooling-maps { 4285bac12f25SAmit Kucheria map0 { 4286bac12f25SAmit Kucheria trip = <&cpu6_bottom_alert0>; 4287bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4288bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4289bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4290bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4291bac12f25SAmit Kucheria }; 4292bac12f25SAmit Kucheria map1 { 4293bac12f25SAmit Kucheria trip = <&cpu6_bottom_alert1>; 4294bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4295bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4296bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4297bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4298bac12f25SAmit Kucheria }; 4299bac12f25SAmit Kucheria }; 4300bac12f25SAmit Kucheria }; 4301bac12f25SAmit Kucheria 4302bac12f25SAmit Kucheria cpu7-bottom-thermal { 4303bac12f25SAmit Kucheria polling-delay-passive = <250>; 4304bac12f25SAmit Kucheria polling-delay = <1000>; 4305bac12f25SAmit Kucheria 4306bac12f25SAmit Kucheria thermal-sensors = <&tsens0 14>; 4307bac12f25SAmit Kucheria 4308bac12f25SAmit Kucheria trips { 4309bac12f25SAmit Kucheria cpu7_bottom_alert0: trip-point0 { 4310bac12f25SAmit Kucheria temperature = <90000>; 4311bac12f25SAmit Kucheria hysteresis = <2000>; 4312bac12f25SAmit Kucheria type = "passive"; 4313bac12f25SAmit Kucheria }; 4314bac12f25SAmit Kucheria 4315bac12f25SAmit Kucheria cpu7_bottom_alert1: trip-point1 { 4316bac12f25SAmit Kucheria temperature = <95000>; 4317bac12f25SAmit Kucheria hysteresis = <2000>; 4318bac12f25SAmit Kucheria type = "passive"; 4319bac12f25SAmit Kucheria }; 4320bac12f25SAmit Kucheria 4321bac12f25SAmit Kucheria cpu7_bottom_crit: cpu_crit { 4322bac12f25SAmit Kucheria temperature = <110000>; 4323bac12f25SAmit Kucheria hysteresis = <1000>; 4324bac12f25SAmit Kucheria type = "critical"; 4325bac12f25SAmit Kucheria }; 4326bac12f25SAmit Kucheria }; 4327bac12f25SAmit Kucheria 4328bac12f25SAmit Kucheria cooling-maps { 4329bac12f25SAmit Kucheria map0 { 4330bac12f25SAmit Kucheria trip = <&cpu7_bottom_alert0>; 4331bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4332bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4333bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4334bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4335bac12f25SAmit Kucheria }; 4336bac12f25SAmit Kucheria map1 { 4337bac12f25SAmit Kucheria trip = <&cpu7_bottom_alert1>; 4338bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4339bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4340bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4341bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4342bac12f25SAmit Kucheria }; 4343bac12f25SAmit Kucheria }; 4344bac12f25SAmit Kucheria }; 4345bac12f25SAmit Kucheria 4346bac12f25SAmit Kucheria aoss0-thermal { 4347bac12f25SAmit Kucheria polling-delay-passive = <250>; 4348bac12f25SAmit Kucheria polling-delay = <1000>; 4349bac12f25SAmit Kucheria 4350bac12f25SAmit Kucheria thermal-sensors = <&tsens0 0>; 4351bac12f25SAmit Kucheria 4352bac12f25SAmit Kucheria trips { 4353bac12f25SAmit Kucheria aoss0_alert0: trip-point0 { 4354bac12f25SAmit Kucheria temperature = <90000>; 4355bac12f25SAmit Kucheria hysteresis = <2000>; 4356bac12f25SAmit Kucheria type = "hot"; 4357bac12f25SAmit Kucheria }; 4358bac12f25SAmit Kucheria }; 4359bac12f25SAmit Kucheria }; 4360bac12f25SAmit Kucheria 4361bac12f25SAmit Kucheria cluster0-thermal { 4362bac12f25SAmit Kucheria polling-delay-passive = <250>; 4363bac12f25SAmit Kucheria polling-delay = <1000>; 4364bac12f25SAmit Kucheria 4365bac12f25SAmit Kucheria thermal-sensors = <&tsens0 5>; 4366bac12f25SAmit Kucheria 4367bac12f25SAmit Kucheria trips { 4368bac12f25SAmit Kucheria cluster0_alert0: trip-point0 { 4369bac12f25SAmit Kucheria temperature = <90000>; 4370bac12f25SAmit Kucheria hysteresis = <2000>; 4371bac12f25SAmit Kucheria type = "hot"; 4372bac12f25SAmit Kucheria }; 4373bac12f25SAmit Kucheria cluster0_crit: cluster0_crit { 4374bac12f25SAmit Kucheria temperature = <110000>; 4375bac12f25SAmit Kucheria hysteresis = <2000>; 4376bac12f25SAmit Kucheria type = "critical"; 4377bac12f25SAmit Kucheria }; 4378bac12f25SAmit Kucheria }; 4379bac12f25SAmit Kucheria }; 4380bac12f25SAmit Kucheria 4381bac12f25SAmit Kucheria cluster1-thermal { 4382bac12f25SAmit Kucheria polling-delay-passive = <250>; 4383bac12f25SAmit Kucheria polling-delay = <1000>; 4384bac12f25SAmit Kucheria 4385bac12f25SAmit Kucheria thermal-sensors = <&tsens0 6>; 4386bac12f25SAmit Kucheria 4387bac12f25SAmit Kucheria trips { 4388bac12f25SAmit Kucheria cluster1_alert0: trip-point0 { 4389bac12f25SAmit Kucheria temperature = <90000>; 4390bac12f25SAmit Kucheria hysteresis = <2000>; 4391bac12f25SAmit Kucheria type = "hot"; 4392bac12f25SAmit Kucheria }; 4393bac12f25SAmit Kucheria cluster1_crit: cluster1_crit { 4394bac12f25SAmit Kucheria temperature = <110000>; 4395bac12f25SAmit Kucheria hysteresis = <2000>; 4396bac12f25SAmit Kucheria type = "critical"; 4397bac12f25SAmit Kucheria }; 4398bac12f25SAmit Kucheria }; 4399bac12f25SAmit Kucheria }; 4400bac12f25SAmit Kucheria 4401bac12f25SAmit Kucheria gpu-thermal-top { 4402bac12f25SAmit Kucheria polling-delay-passive = <250>; 4403bac12f25SAmit Kucheria polling-delay = <1000>; 4404bac12f25SAmit Kucheria 4405bac12f25SAmit Kucheria thermal-sensors = <&tsens0 15>; 4406bac12f25SAmit Kucheria 4407bac12f25SAmit Kucheria trips { 4408bac12f25SAmit Kucheria gpu1_alert0: trip-point0 { 4409bac12f25SAmit Kucheria temperature = <90000>; 4410bac12f25SAmit Kucheria hysteresis = <2000>; 4411bac12f25SAmit Kucheria type = "hot"; 4412bac12f25SAmit Kucheria }; 4413bac12f25SAmit Kucheria }; 4414bac12f25SAmit Kucheria }; 4415bac12f25SAmit Kucheria 4416bac12f25SAmit Kucheria aoss1-thermal { 4417bac12f25SAmit Kucheria polling-delay-passive = <250>; 4418bac12f25SAmit Kucheria polling-delay = <1000>; 4419bac12f25SAmit Kucheria 4420bac12f25SAmit Kucheria thermal-sensors = <&tsens1 0>; 4421bac12f25SAmit Kucheria 4422bac12f25SAmit Kucheria trips { 4423bac12f25SAmit Kucheria aoss1_alert0: trip-point0 { 4424bac12f25SAmit Kucheria temperature = <90000>; 4425bac12f25SAmit Kucheria hysteresis = <2000>; 4426bac12f25SAmit Kucheria type = "hot"; 4427bac12f25SAmit Kucheria }; 4428bac12f25SAmit Kucheria }; 4429bac12f25SAmit Kucheria }; 4430bac12f25SAmit Kucheria 4431bac12f25SAmit Kucheria wlan-thermal { 4432bac12f25SAmit Kucheria polling-delay-passive = <250>; 4433bac12f25SAmit Kucheria polling-delay = <1000>; 4434bac12f25SAmit Kucheria 4435bac12f25SAmit Kucheria thermal-sensors = <&tsens1 1>; 4436bac12f25SAmit Kucheria 4437bac12f25SAmit Kucheria trips { 4438bac12f25SAmit Kucheria wlan_alert0: trip-point0 { 4439bac12f25SAmit Kucheria temperature = <90000>; 4440bac12f25SAmit Kucheria hysteresis = <2000>; 4441bac12f25SAmit Kucheria type = "hot"; 4442bac12f25SAmit Kucheria }; 4443bac12f25SAmit Kucheria }; 4444bac12f25SAmit Kucheria }; 4445bac12f25SAmit Kucheria 4446bac12f25SAmit Kucheria video-thermal { 4447bac12f25SAmit Kucheria polling-delay-passive = <250>; 4448bac12f25SAmit Kucheria polling-delay = <1000>; 4449bac12f25SAmit Kucheria 4450bac12f25SAmit Kucheria thermal-sensors = <&tsens1 2>; 4451bac12f25SAmit Kucheria 4452bac12f25SAmit Kucheria trips { 4453bac12f25SAmit Kucheria video_alert0: trip-point0 { 4454bac12f25SAmit Kucheria temperature = <90000>; 4455bac12f25SAmit Kucheria hysteresis = <2000>; 4456bac12f25SAmit Kucheria type = "hot"; 4457bac12f25SAmit Kucheria }; 4458bac12f25SAmit Kucheria }; 4459bac12f25SAmit Kucheria }; 4460bac12f25SAmit Kucheria 4461bac12f25SAmit Kucheria mem-thermal { 4462bac12f25SAmit Kucheria polling-delay-passive = <250>; 4463bac12f25SAmit Kucheria polling-delay = <1000>; 4464bac12f25SAmit Kucheria 4465bac12f25SAmit Kucheria thermal-sensors = <&tsens1 3>; 4466bac12f25SAmit Kucheria 4467bac12f25SAmit Kucheria trips { 4468bac12f25SAmit Kucheria mem_alert0: trip-point0 { 4469bac12f25SAmit Kucheria temperature = <90000>; 4470bac12f25SAmit Kucheria hysteresis = <2000>; 4471bac12f25SAmit Kucheria type = "hot"; 4472bac12f25SAmit Kucheria }; 4473bac12f25SAmit Kucheria }; 4474bac12f25SAmit Kucheria }; 4475bac12f25SAmit Kucheria 4476bac12f25SAmit Kucheria q6-hvx-thermal { 4477bac12f25SAmit Kucheria polling-delay-passive = <250>; 4478bac12f25SAmit Kucheria polling-delay = <1000>; 4479bac12f25SAmit Kucheria 4480bac12f25SAmit Kucheria thermal-sensors = <&tsens1 4>; 4481bac12f25SAmit Kucheria 4482bac12f25SAmit Kucheria trips { 4483bac12f25SAmit Kucheria q6_hvx_alert0: trip-point0 { 4484bac12f25SAmit Kucheria temperature = <90000>; 4485bac12f25SAmit Kucheria hysteresis = <2000>; 4486bac12f25SAmit Kucheria type = "hot"; 4487bac12f25SAmit Kucheria }; 4488bac12f25SAmit Kucheria }; 4489bac12f25SAmit Kucheria }; 4490bac12f25SAmit Kucheria 4491bac12f25SAmit Kucheria camera-thermal { 4492bac12f25SAmit Kucheria polling-delay-passive = <250>; 4493bac12f25SAmit Kucheria polling-delay = <1000>; 4494bac12f25SAmit Kucheria 4495bac12f25SAmit Kucheria thermal-sensors = <&tsens1 5>; 4496bac12f25SAmit Kucheria 4497bac12f25SAmit Kucheria trips { 4498bac12f25SAmit Kucheria camera_alert0: trip-point0 { 4499bac12f25SAmit Kucheria temperature = <90000>; 4500bac12f25SAmit Kucheria hysteresis = <2000>; 4501bac12f25SAmit Kucheria type = "hot"; 4502bac12f25SAmit Kucheria }; 4503bac12f25SAmit Kucheria }; 4504bac12f25SAmit Kucheria }; 4505bac12f25SAmit Kucheria 4506bac12f25SAmit Kucheria compute-thermal { 4507bac12f25SAmit Kucheria polling-delay-passive = <250>; 4508bac12f25SAmit Kucheria polling-delay = <1000>; 4509bac12f25SAmit Kucheria 4510bac12f25SAmit Kucheria thermal-sensors = <&tsens1 6>; 4511bac12f25SAmit Kucheria 4512bac12f25SAmit Kucheria trips { 4513bac12f25SAmit Kucheria compute_alert0: trip-point0 { 4514bac12f25SAmit Kucheria temperature = <90000>; 4515bac12f25SAmit Kucheria hysteresis = <2000>; 4516bac12f25SAmit Kucheria type = "hot"; 4517bac12f25SAmit Kucheria }; 4518bac12f25SAmit Kucheria }; 4519bac12f25SAmit Kucheria }; 4520bac12f25SAmit Kucheria 4521bac12f25SAmit Kucheria npu-thermal { 4522bac12f25SAmit Kucheria polling-delay-passive = <250>; 4523bac12f25SAmit Kucheria polling-delay = <1000>; 4524bac12f25SAmit Kucheria 4525bac12f25SAmit Kucheria thermal-sensors = <&tsens1 7>; 4526bac12f25SAmit Kucheria 4527bac12f25SAmit Kucheria trips { 4528bac12f25SAmit Kucheria npu_alert0: trip-point0 { 4529bac12f25SAmit Kucheria temperature = <90000>; 4530bac12f25SAmit Kucheria hysteresis = <2000>; 4531bac12f25SAmit Kucheria type = "hot"; 4532bac12f25SAmit Kucheria }; 4533bac12f25SAmit Kucheria }; 4534bac12f25SAmit Kucheria }; 4535bac12f25SAmit Kucheria 4536bac12f25SAmit Kucheria gpu-thermal-bottom { 4537bac12f25SAmit Kucheria polling-delay-passive = <250>; 4538bac12f25SAmit Kucheria polling-delay = <1000>; 4539bac12f25SAmit Kucheria 4540bac12f25SAmit Kucheria thermal-sensors = <&tsens1 8>; 4541bac12f25SAmit Kucheria 4542bac12f25SAmit Kucheria trips { 4543bac12f25SAmit Kucheria gpu2_alert0: trip-point0 { 4544bac12f25SAmit Kucheria temperature = <90000>; 4545bac12f25SAmit Kucheria hysteresis = <2000>; 4546bac12f25SAmit Kucheria type = "hot"; 4547bac12f25SAmit Kucheria }; 4548bac12f25SAmit Kucheria }; 4549bac12f25SAmit Kucheria }; 4550bac12f25SAmit Kucheria }; 455160378f1aSVenkata Narendra Kumar Gutta}; 4552