160378f1aSVenkata Narendra Kumar Gutta// SPDX-License-Identifier: BSD-3-Clause 260378f1aSVenkata Narendra Kumar Gutta/* 360378f1aSVenkata Narendra Kumar Gutta * Copyright (c) 2020, The Linux Foundation. All rights reserved. 460378f1aSVenkata Narendra Kumar Gutta */ 560378f1aSVenkata Narendra Kumar Gutta 660378f1aSVenkata Narendra Kumar Gutta#include <dt-bindings/interrupt-controller/arm-gic.h> 77c1dffd4SDmitry Baryshkov#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8b7e2fba0SBryan O'Donoghue#include <dt-bindings/clock/qcom,gcc-sm8250.h> 90e6aa9dbSJonathan Marek#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 1060378f1aSVenkata Narendra Kumar Gutta#include <dt-bindings/clock/qcom,rpmh.h> 1179a595bbSSibi Sankar#include <dt-bindings/interconnect/qcom,osm-l3.h> 127c1dffd4SDmitry Baryshkov#include <dt-bindings/interconnect/qcom,sm8250.h> 13e5361e75SBjorn Andersson#include <dt-bindings/mailbox/qcom-ipcc.h> 14087d537aSBjorn Andersson#include <dt-bindings/power/qcom-aoss-qmp.h> 15b6f78e27SBjorn Andersson#include <dt-bindings/power/qcom-rpmpd.h> 1663e10791SSrinivas Kandagatla#include <dt-bindings/soc/qcom,apr.h> 1760378f1aSVenkata Narendra Kumar Gutta#include <dt-bindings/soc/qcom,rpmh-rsc.h> 1863e10791SSrinivas Kandagatla#include <dt-bindings/sound/qcom,q6afe.h> 19bac12f25SAmit Kucheria#include <dt-bindings/thermal/thermal.h> 2060378f1aSVenkata Narendra Kumar Gutta 2160378f1aSVenkata Narendra Kumar Gutta/ { 2260378f1aSVenkata Narendra Kumar Gutta interrupt-parent = <&intc>; 2360378f1aSVenkata Narendra Kumar Gutta 2460378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 2560378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 2660378f1aSVenkata Narendra Kumar Gutta 27e5813b15SDmitry Baryshkov aliases { 28e5813b15SDmitry Baryshkov i2c0 = &i2c0; 29e5813b15SDmitry Baryshkov i2c1 = &i2c1; 30e5813b15SDmitry Baryshkov i2c2 = &i2c2; 31e5813b15SDmitry Baryshkov i2c3 = &i2c3; 32e5813b15SDmitry Baryshkov i2c4 = &i2c4; 33e5813b15SDmitry Baryshkov i2c5 = &i2c5; 34e5813b15SDmitry Baryshkov i2c6 = &i2c6; 35e5813b15SDmitry Baryshkov i2c7 = &i2c7; 36e5813b15SDmitry Baryshkov i2c8 = &i2c8; 37e5813b15SDmitry Baryshkov i2c9 = &i2c9; 38e5813b15SDmitry Baryshkov i2c10 = &i2c10; 39e5813b15SDmitry Baryshkov i2c11 = &i2c11; 40e5813b15SDmitry Baryshkov i2c12 = &i2c12; 41e5813b15SDmitry Baryshkov i2c13 = &i2c13; 42e5813b15SDmitry Baryshkov i2c14 = &i2c14; 43e5813b15SDmitry Baryshkov i2c15 = &i2c15; 44e5813b15SDmitry Baryshkov i2c16 = &i2c16; 45e5813b15SDmitry Baryshkov i2c17 = &i2c17; 46e5813b15SDmitry Baryshkov i2c18 = &i2c18; 47e5813b15SDmitry Baryshkov i2c19 = &i2c19; 48e5813b15SDmitry Baryshkov spi0 = &spi0; 49e5813b15SDmitry Baryshkov spi1 = &spi1; 50e5813b15SDmitry Baryshkov spi2 = &spi2; 51e5813b15SDmitry Baryshkov spi3 = &spi3; 52e5813b15SDmitry Baryshkov spi4 = &spi4; 53e5813b15SDmitry Baryshkov spi5 = &spi5; 54e5813b15SDmitry Baryshkov spi6 = &spi6; 55e5813b15SDmitry Baryshkov spi7 = &spi7; 56e5813b15SDmitry Baryshkov spi8 = &spi8; 57e5813b15SDmitry Baryshkov spi9 = &spi9; 58e5813b15SDmitry Baryshkov spi10 = &spi10; 59e5813b15SDmitry Baryshkov spi11 = &spi11; 60e5813b15SDmitry Baryshkov spi12 = &spi12; 61e5813b15SDmitry Baryshkov spi13 = &spi13; 62e5813b15SDmitry Baryshkov spi14 = &spi14; 63e5813b15SDmitry Baryshkov spi15 = &spi15; 64e5813b15SDmitry Baryshkov spi16 = &spi16; 65e5813b15SDmitry Baryshkov spi17 = &spi17; 66e5813b15SDmitry Baryshkov spi18 = &spi18; 67e5813b15SDmitry Baryshkov spi19 = &spi19; 68e5813b15SDmitry Baryshkov }; 69e5813b15SDmitry Baryshkov 7060378f1aSVenkata Narendra Kumar Gutta chosen { }; 7160378f1aSVenkata Narendra Kumar Gutta 7260378f1aSVenkata Narendra Kumar Gutta clocks { 7360378f1aSVenkata Narendra Kumar Gutta xo_board: xo-board { 7460378f1aSVenkata Narendra Kumar Gutta compatible = "fixed-clock"; 7560378f1aSVenkata Narendra Kumar Gutta #clock-cells = <0>; 7660378f1aSVenkata Narendra Kumar Gutta clock-frequency = <38400000>; 7760378f1aSVenkata Narendra Kumar Gutta clock-output-names = "xo_board"; 7860378f1aSVenkata Narendra Kumar Gutta }; 7960378f1aSVenkata Narendra Kumar Gutta 8060378f1aSVenkata Narendra Kumar Gutta sleep_clk: sleep-clk { 8160378f1aSVenkata Narendra Kumar Gutta compatible = "fixed-clock"; 829ff8b059SJonathan Marek clock-frequency = <32768>; 8360378f1aSVenkata Narendra Kumar Gutta #clock-cells = <0>; 8460378f1aSVenkata Narendra Kumar Gutta }; 8560378f1aSVenkata Narendra Kumar Gutta }; 8660378f1aSVenkata Narendra Kumar Gutta 8760378f1aSVenkata Narendra Kumar Gutta cpus { 8860378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 8960378f1aSVenkata Narendra Kumar Gutta #size-cells = <0>; 9060378f1aSVenkata Narendra Kumar Gutta 9160378f1aSVenkata Narendra Kumar Gutta CPU0: cpu@0 { 9260378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 9360378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 9460378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x0>; 9560378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 966aabed55SDanny Lin capacity-dmips-mhz = <448>; 976aabed55SDanny Lin dynamic-power-coefficient = <205>; 9860378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_0>; 9902ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 100bac12f25SAmit Kucheria #cooling-cells = <2>; 10160378f1aSVenkata Narendra Kumar Gutta L2_0: l2-cache { 10260378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 10360378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 10460378f1aSVenkata Narendra Kumar Gutta L3_0: l3-cache { 10560378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 10660378f1aSVenkata Narendra Kumar Gutta }; 10760378f1aSVenkata Narendra Kumar Gutta }; 10860378f1aSVenkata Narendra Kumar Gutta }; 10960378f1aSVenkata Narendra Kumar Gutta 11060378f1aSVenkata Narendra Kumar Gutta CPU1: cpu@100 { 11160378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 11260378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 11360378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x100>; 11460378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1156aabed55SDanny Lin capacity-dmips-mhz = <448>; 1166aabed55SDanny Lin dynamic-power-coefficient = <205>; 11760378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_100>; 11802ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 119bac12f25SAmit Kucheria #cooling-cells = <2>; 12060378f1aSVenkata Narendra Kumar Gutta L2_100: l2-cache { 12160378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 12260378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 12360378f1aSVenkata Narendra Kumar Gutta }; 12460378f1aSVenkata Narendra Kumar Gutta }; 12560378f1aSVenkata Narendra Kumar Gutta 12660378f1aSVenkata Narendra Kumar Gutta CPU2: cpu@200 { 12760378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 12860378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 12960378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x200>; 13060378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1316aabed55SDanny Lin capacity-dmips-mhz = <448>; 1326aabed55SDanny Lin dynamic-power-coefficient = <205>; 13360378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_200>; 13402ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 135bac12f25SAmit Kucheria #cooling-cells = <2>; 13660378f1aSVenkata Narendra Kumar Gutta L2_200: l2-cache { 13760378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 13860378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 13960378f1aSVenkata Narendra Kumar Gutta }; 14060378f1aSVenkata Narendra Kumar Gutta }; 14160378f1aSVenkata Narendra Kumar Gutta 14260378f1aSVenkata Narendra Kumar Gutta CPU3: cpu@300 { 14360378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 14460378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 14560378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x300>; 14660378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1476aabed55SDanny Lin capacity-dmips-mhz = <448>; 1486aabed55SDanny Lin dynamic-power-coefficient = <205>; 14960378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_300>; 15002ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 151bac12f25SAmit Kucheria #cooling-cells = <2>; 15260378f1aSVenkata Narendra Kumar Gutta L2_300: l2-cache { 15360378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 15460378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 15560378f1aSVenkata Narendra Kumar Gutta }; 15660378f1aSVenkata Narendra Kumar Gutta }; 15760378f1aSVenkata Narendra Kumar Gutta 15860378f1aSVenkata Narendra Kumar Gutta CPU4: cpu@400 { 15960378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 16060378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 16160378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x400>; 16260378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1636aabed55SDanny Lin capacity-dmips-mhz = <1024>; 1646aabed55SDanny Lin dynamic-power-coefficient = <379>; 16560378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_400>; 16602ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 1>; 167bac12f25SAmit Kucheria #cooling-cells = <2>; 16860378f1aSVenkata Narendra Kumar Gutta L2_400: l2-cache { 16960378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 17060378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 17160378f1aSVenkata Narendra Kumar Gutta }; 17260378f1aSVenkata Narendra Kumar Gutta }; 17360378f1aSVenkata Narendra Kumar Gutta 17460378f1aSVenkata Narendra Kumar Gutta CPU5: cpu@500 { 17560378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 17660378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 17760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x500>; 17860378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1796aabed55SDanny Lin capacity-dmips-mhz = <1024>; 1806aabed55SDanny Lin dynamic-power-coefficient = <379>; 18160378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_500>; 18202ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 1>; 183bac12f25SAmit Kucheria #cooling-cells = <2>; 18460378f1aSVenkata Narendra Kumar Gutta L2_500: l2-cache { 18560378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 18660378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 18760378f1aSVenkata Narendra Kumar Gutta }; 18860378f1aSVenkata Narendra Kumar Gutta 18960378f1aSVenkata Narendra Kumar Gutta }; 19060378f1aSVenkata Narendra Kumar Gutta 19160378f1aSVenkata Narendra Kumar Gutta CPU6: cpu@600 { 19260378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 19360378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 19460378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x600>; 19560378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1966aabed55SDanny Lin capacity-dmips-mhz = <1024>; 1976aabed55SDanny Lin dynamic-power-coefficient = <379>; 19860378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_600>; 19902ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 1>; 200bac12f25SAmit Kucheria #cooling-cells = <2>; 20160378f1aSVenkata Narendra Kumar Gutta L2_600: l2-cache { 20260378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 20360378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 20460378f1aSVenkata Narendra Kumar Gutta }; 20560378f1aSVenkata Narendra Kumar Gutta }; 20660378f1aSVenkata Narendra Kumar Gutta 20760378f1aSVenkata Narendra Kumar Gutta CPU7: cpu@700 { 20860378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 20960378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 21060378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x700>; 21160378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 2126aabed55SDanny Lin capacity-dmips-mhz = <1024>; 2136aabed55SDanny Lin dynamic-power-coefficient = <444>; 21460378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_700>; 21502ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 2>; 216bac12f25SAmit Kucheria #cooling-cells = <2>; 21760378f1aSVenkata Narendra Kumar Gutta L2_700: l2-cache { 21860378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 21960378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 22060378f1aSVenkata Narendra Kumar Gutta }; 22160378f1aSVenkata Narendra Kumar Gutta }; 222b4791e69SDanny Lin 223b4791e69SDanny Lin cpu-map { 224b4791e69SDanny Lin cluster0 { 225b4791e69SDanny Lin core0 { 226b4791e69SDanny Lin cpu = <&CPU0>; 227b4791e69SDanny Lin }; 228b4791e69SDanny Lin 229b4791e69SDanny Lin core1 { 230b4791e69SDanny Lin cpu = <&CPU1>; 231b4791e69SDanny Lin }; 232b4791e69SDanny Lin 233b4791e69SDanny Lin core2 { 234b4791e69SDanny Lin cpu = <&CPU2>; 235b4791e69SDanny Lin }; 236b4791e69SDanny Lin 237b4791e69SDanny Lin core3 { 238b4791e69SDanny Lin cpu = <&CPU3>; 239b4791e69SDanny Lin }; 240b4791e69SDanny Lin 241b4791e69SDanny Lin core4 { 242b4791e69SDanny Lin cpu = <&CPU4>; 243b4791e69SDanny Lin }; 244b4791e69SDanny Lin 245b4791e69SDanny Lin core5 { 246b4791e69SDanny Lin cpu = <&CPU5>; 247b4791e69SDanny Lin }; 248b4791e69SDanny Lin 249b4791e69SDanny Lin core6 { 250b4791e69SDanny Lin cpu = <&CPU6>; 251b4791e69SDanny Lin }; 252b4791e69SDanny Lin 253b4791e69SDanny Lin core7 { 254b4791e69SDanny Lin cpu = <&CPU7>; 255b4791e69SDanny Lin }; 256b4791e69SDanny Lin }; 257b4791e69SDanny Lin }; 25860378f1aSVenkata Narendra Kumar Gutta }; 25960378f1aSVenkata Narendra Kumar Gutta 26060378f1aSVenkata Narendra Kumar Gutta firmware { 26160378f1aSVenkata Narendra Kumar Gutta scm: scm { 26260378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,scm"; 26360378f1aSVenkata Narendra Kumar Gutta #reset-cells = <1>; 26460378f1aSVenkata Narendra Kumar Gutta }; 26560378f1aSVenkata Narendra Kumar Gutta }; 26660378f1aSVenkata Narendra Kumar Gutta 26760378f1aSVenkata Narendra Kumar Gutta memory@80000000 { 26860378f1aSVenkata Narendra Kumar Gutta device_type = "memory"; 26960378f1aSVenkata Narendra Kumar Gutta /* We expect the bootloader to fill in the size */ 27060378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80000000 0x0 0x0>; 27160378f1aSVenkata Narendra Kumar Gutta }; 27260378f1aSVenkata Narendra Kumar Gutta 2733f2094dfSDmitry Baryshkov mmcx_reg: mmcx-reg { 2743f2094dfSDmitry Baryshkov compatible = "regulator-fixed-domain"; 2753f2094dfSDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 2763f2094dfSDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 2773f2094dfSDmitry Baryshkov regulator-name = "MMCX"; 2783f2094dfSDmitry Baryshkov }; 2793f2094dfSDmitry Baryshkov 28060378f1aSVenkata Narendra Kumar Gutta pmu { 28160378f1aSVenkata Narendra Kumar Gutta compatible = "arm,armv8-pmuv3"; 28293138ef5SSai Prakash Ranjan interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 28360378f1aSVenkata Narendra Kumar Gutta }; 28460378f1aSVenkata Narendra Kumar Gutta 28560378f1aSVenkata Narendra Kumar Gutta psci { 28660378f1aSVenkata Narendra Kumar Gutta compatible = "arm,psci-1.0"; 28760378f1aSVenkata Narendra Kumar Gutta method = "smc"; 28860378f1aSVenkata Narendra Kumar Gutta }; 28960378f1aSVenkata Narendra Kumar Gutta 29060378f1aSVenkata Narendra Kumar Gutta reserved-memory { 29160378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 29260378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 29360378f1aSVenkata Narendra Kumar Gutta ranges; 29460378f1aSVenkata Narendra Kumar Gutta 29560378f1aSVenkata Narendra Kumar Gutta hyp_mem: memory@80000000 { 29660378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80000000 0x0 0x600000>; 29760378f1aSVenkata Narendra Kumar Gutta no-map; 29860378f1aSVenkata Narendra Kumar Gutta }; 29960378f1aSVenkata Narendra Kumar Gutta 30060378f1aSVenkata Narendra Kumar Gutta xbl_aop_mem: memory@80700000 { 30160378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80700000 0x0 0x160000>; 30260378f1aSVenkata Narendra Kumar Gutta no-map; 30360378f1aSVenkata Narendra Kumar Gutta }; 30460378f1aSVenkata Narendra Kumar Gutta 30560378f1aSVenkata Narendra Kumar Gutta cmd_db: memory@80860000 { 30660378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,cmd-db"; 30760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80860000 0x0 0x20000>; 30860378f1aSVenkata Narendra Kumar Gutta no-map; 30960378f1aSVenkata Narendra Kumar Gutta }; 31060378f1aSVenkata Narendra Kumar Gutta 31160378f1aSVenkata Narendra Kumar Gutta smem_mem: memory@80900000 { 31260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80900000 0x0 0x200000>; 31360378f1aSVenkata Narendra Kumar Gutta no-map; 31460378f1aSVenkata Narendra Kumar Gutta }; 31560378f1aSVenkata Narendra Kumar Gutta 31660378f1aSVenkata Narendra Kumar Gutta removed_mem: memory@80b00000 { 31760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80b00000 0x0 0x5300000>; 31860378f1aSVenkata Narendra Kumar Gutta no-map; 31960378f1aSVenkata Narendra Kumar Gutta }; 32060378f1aSVenkata Narendra Kumar Gutta 32160378f1aSVenkata Narendra Kumar Gutta camera_mem: memory@86200000 { 32260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86200000 0x0 0x500000>; 32360378f1aSVenkata Narendra Kumar Gutta no-map; 32460378f1aSVenkata Narendra Kumar Gutta }; 32560378f1aSVenkata Narendra Kumar Gutta 32660378f1aSVenkata Narendra Kumar Gutta wlan_mem: memory@86700000 { 32760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86700000 0x0 0x100000>; 32860378f1aSVenkata Narendra Kumar Gutta no-map; 32960378f1aSVenkata Narendra Kumar Gutta }; 33060378f1aSVenkata Narendra Kumar Gutta 33160378f1aSVenkata Narendra Kumar Gutta ipa_fw_mem: memory@86800000 { 33260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86800000 0x0 0x10000>; 33360378f1aSVenkata Narendra Kumar Gutta no-map; 33460378f1aSVenkata Narendra Kumar Gutta }; 33560378f1aSVenkata Narendra Kumar Gutta 33660378f1aSVenkata Narendra Kumar Gutta ipa_gsi_mem: memory@86810000 { 33760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86810000 0x0 0xa000>; 33860378f1aSVenkata Narendra Kumar Gutta no-map; 33960378f1aSVenkata Narendra Kumar Gutta }; 34060378f1aSVenkata Narendra Kumar Gutta 34160378f1aSVenkata Narendra Kumar Gutta gpu_mem: memory@8681a000 { 34260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8681a000 0x0 0x2000>; 34360378f1aSVenkata Narendra Kumar Gutta no-map; 34460378f1aSVenkata Narendra Kumar Gutta }; 34560378f1aSVenkata Narendra Kumar Gutta 34660378f1aSVenkata Narendra Kumar Gutta npu_mem: memory@86900000 { 34760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86900000 0x0 0x500000>; 34860378f1aSVenkata Narendra Kumar Gutta no-map; 34960378f1aSVenkata Narendra Kumar Gutta }; 35060378f1aSVenkata Narendra Kumar Gutta 35160378f1aSVenkata Narendra Kumar Gutta video_mem: memory@86e00000 { 35260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86e00000 0x0 0x500000>; 35360378f1aSVenkata Narendra Kumar Gutta no-map; 35460378f1aSVenkata Narendra Kumar Gutta }; 35560378f1aSVenkata Narendra Kumar Gutta 35660378f1aSVenkata Narendra Kumar Gutta cvp_mem: memory@87300000 { 35760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x87300000 0x0 0x500000>; 35860378f1aSVenkata Narendra Kumar Gutta no-map; 35960378f1aSVenkata Narendra Kumar Gutta }; 36060378f1aSVenkata Narendra Kumar Gutta 36160378f1aSVenkata Narendra Kumar Gutta cdsp_mem: memory@87800000 { 36260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x87800000 0x0 0x1400000>; 36360378f1aSVenkata Narendra Kumar Gutta no-map; 36460378f1aSVenkata Narendra Kumar Gutta }; 36560378f1aSVenkata Narendra Kumar Gutta 36660378f1aSVenkata Narendra Kumar Gutta slpi_mem: memory@88c00000 { 36760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x88c00000 0x0 0x1500000>; 36860378f1aSVenkata Narendra Kumar Gutta no-map; 36960378f1aSVenkata Narendra Kumar Gutta }; 37060378f1aSVenkata Narendra Kumar Gutta 37160378f1aSVenkata Narendra Kumar Gutta adsp_mem: memory@8a100000 { 37260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8a100000 0x0 0x1d00000>; 37360378f1aSVenkata Narendra Kumar Gutta no-map; 37460378f1aSVenkata Narendra Kumar Gutta }; 37560378f1aSVenkata Narendra Kumar Gutta 37660378f1aSVenkata Narendra Kumar Gutta spss_mem: memory@8be00000 { 37760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8be00000 0x0 0x100000>; 37860378f1aSVenkata Narendra Kumar Gutta no-map; 37960378f1aSVenkata Narendra Kumar Gutta }; 38060378f1aSVenkata Narendra Kumar Gutta 38160378f1aSVenkata Narendra Kumar Gutta cdsp_secure_heap: memory@8bf00000 { 38260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8bf00000 0x0 0x4600000>; 38360378f1aSVenkata Narendra Kumar Gutta no-map; 38460378f1aSVenkata Narendra Kumar Gutta }; 38560378f1aSVenkata Narendra Kumar Gutta }; 38660378f1aSVenkata Narendra Kumar Gutta 38788b57bc3SDmitry Baryshkov smem { 38860378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,smem"; 38960378f1aSVenkata Narendra Kumar Gutta memory-region = <&smem_mem>; 39060378f1aSVenkata Narendra Kumar Gutta hwlocks = <&tcsr_mutex 3>; 39160378f1aSVenkata Narendra Kumar Gutta }; 39260378f1aSVenkata Narendra Kumar Gutta 3938770a2a8SBjorn Andersson smp2p-adsp { 3948770a2a8SBjorn Andersson compatible = "qcom,smp2p"; 3958770a2a8SBjorn Andersson qcom,smem = <443>, <429>; 3968770a2a8SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3978770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P 3988770a2a8SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 3998770a2a8SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_LPASS 4008770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P>; 4018770a2a8SBjorn Andersson 4028770a2a8SBjorn Andersson qcom,local-pid = <0>; 4038770a2a8SBjorn Andersson qcom,remote-pid = <2>; 4048770a2a8SBjorn Andersson 4058770a2a8SBjorn Andersson smp2p_adsp_out: master-kernel { 4068770a2a8SBjorn Andersson qcom,entry-name = "master-kernel"; 4078770a2a8SBjorn Andersson #qcom,smem-state-cells = <1>; 4088770a2a8SBjorn Andersson }; 4098770a2a8SBjorn Andersson 4108770a2a8SBjorn Andersson smp2p_adsp_in: slave-kernel { 4118770a2a8SBjorn Andersson qcom,entry-name = "slave-kernel"; 4128770a2a8SBjorn Andersson interrupt-controller; 4138770a2a8SBjorn Andersson #interrupt-cells = <2>; 4148770a2a8SBjorn Andersson }; 4158770a2a8SBjorn Andersson }; 4168770a2a8SBjorn Andersson 4178770a2a8SBjorn Andersson smp2p-cdsp { 4188770a2a8SBjorn Andersson compatible = "qcom,smp2p"; 4198770a2a8SBjorn Andersson qcom,smem = <94>, <432>; 4208770a2a8SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4218770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P 4228770a2a8SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 4238770a2a8SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_CDSP 4248770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P>; 4258770a2a8SBjorn Andersson 4268770a2a8SBjorn Andersson qcom,local-pid = <0>; 4278770a2a8SBjorn Andersson qcom,remote-pid = <5>; 4288770a2a8SBjorn Andersson 4298770a2a8SBjorn Andersson smp2p_cdsp_out: master-kernel { 4308770a2a8SBjorn Andersson qcom,entry-name = "master-kernel"; 4318770a2a8SBjorn Andersson #qcom,smem-state-cells = <1>; 4328770a2a8SBjorn Andersson }; 4338770a2a8SBjorn Andersson 4348770a2a8SBjorn Andersson smp2p_cdsp_in: slave-kernel { 4358770a2a8SBjorn Andersson qcom,entry-name = "slave-kernel"; 4368770a2a8SBjorn Andersson interrupt-controller; 4378770a2a8SBjorn Andersson #interrupt-cells = <2>; 4388770a2a8SBjorn Andersson }; 4398770a2a8SBjorn Andersson }; 4408770a2a8SBjorn Andersson 4418770a2a8SBjorn Andersson smp2p-slpi { 4428770a2a8SBjorn Andersson compatible = "qcom,smp2p"; 4438770a2a8SBjorn Andersson qcom,smem = <481>, <430>; 4448770a2a8SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 4458770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P 4468770a2a8SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 4478770a2a8SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_SLPI 4488770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P>; 4498770a2a8SBjorn Andersson 4508770a2a8SBjorn Andersson qcom,local-pid = <0>; 4518770a2a8SBjorn Andersson qcom,remote-pid = <3>; 4528770a2a8SBjorn Andersson 4538770a2a8SBjorn Andersson smp2p_slpi_out: master-kernel { 4548770a2a8SBjorn Andersson qcom,entry-name = "master-kernel"; 4558770a2a8SBjorn Andersson #qcom,smem-state-cells = <1>; 4568770a2a8SBjorn Andersson }; 4578770a2a8SBjorn Andersson 4588770a2a8SBjorn Andersson smp2p_slpi_in: slave-kernel { 4598770a2a8SBjorn Andersson qcom,entry-name = "slave-kernel"; 4608770a2a8SBjorn Andersson interrupt-controller; 4618770a2a8SBjorn Andersson #interrupt-cells = <2>; 4628770a2a8SBjorn Andersson }; 4638770a2a8SBjorn Andersson }; 4648770a2a8SBjorn Andersson 46560378f1aSVenkata Narendra Kumar Gutta soc: soc@0 { 46660378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 46760378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 46860378f1aSVenkata Narendra Kumar Gutta ranges = <0 0 0 0 0x10 0>; 46960378f1aSVenkata Narendra Kumar Gutta dma-ranges = <0 0 0 0 0x10 0>; 47060378f1aSVenkata Narendra Kumar Gutta compatible = "simple-bus"; 47160378f1aSVenkata Narendra Kumar Gutta 47260378f1aSVenkata Narendra Kumar Gutta gcc: clock-controller@100000 { 47360378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,gcc-sm8250"; 47460378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x00100000 0x0 0x1f0000>; 47560378f1aSVenkata Narendra Kumar Gutta #clock-cells = <1>; 47660378f1aSVenkata Narendra Kumar Gutta #reset-cells = <1>; 47760378f1aSVenkata Narendra Kumar Gutta #power-domain-cells = <1>; 47876bd127eSDmitry Baryshkov clock-names = "bi_tcxo", 47976bd127eSDmitry Baryshkov "bi_tcxo_ao", 48076bd127eSDmitry Baryshkov "sleep_clk"; 48176bd127eSDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>, 48276bd127eSDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK_A>, 48376bd127eSDmitry Baryshkov <&sleep_clk>; 48460378f1aSVenkata Narendra Kumar Gutta }; 48560378f1aSVenkata Narendra Kumar Gutta 486e5361e75SBjorn Andersson ipcc: mailbox@408000 { 487e5361e75SBjorn Andersson compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 488e5361e75SBjorn Andersson reg = <0 0x00408000 0 0x1000>; 489e5361e75SBjorn Andersson interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 490e5361e75SBjorn Andersson interrupt-controller; 491e5361e75SBjorn Andersson #interrupt-cells = <3>; 492e5361e75SBjorn Andersson #mbox-cells = <2>; 493e5361e75SBjorn Andersson }; 494e5361e75SBjorn Andersson 49565389ce6SManivannan Sadhasivam rng: rng@793000 { 49665389ce6SManivannan Sadhasivam compatible = "qcom,prng-ee"; 49765389ce6SManivannan Sadhasivam reg = <0 0x00793000 0 0x1000>; 49865389ce6SManivannan Sadhasivam clocks = <&gcc GCC_PRNG_AHB_CLK>; 49965389ce6SManivannan Sadhasivam clock-names = "core"; 50065389ce6SManivannan Sadhasivam }; 50165389ce6SManivannan Sadhasivam 50201e869ccSDmitry Baryshkov qup_opp_table: qup-opp-table { 50301e869ccSDmitry Baryshkov compatible = "operating-points-v2"; 50401e869ccSDmitry Baryshkov 50501e869ccSDmitry Baryshkov opp-50000000 { 50601e869ccSDmitry Baryshkov opp-hz = /bits/ 64 <50000000>; 50701e869ccSDmitry Baryshkov required-opps = <&rpmhpd_opp_min_svs>; 50801e869ccSDmitry Baryshkov }; 50901e869ccSDmitry Baryshkov 51001e869ccSDmitry Baryshkov opp-75000000 { 51101e869ccSDmitry Baryshkov opp-hz = /bits/ 64 <75000000>; 51201e869ccSDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 51301e869ccSDmitry Baryshkov }; 51401e869ccSDmitry Baryshkov 51501e869ccSDmitry Baryshkov opp-120000000 { 51601e869ccSDmitry Baryshkov opp-hz = /bits/ 64 <120000000>; 51701e869ccSDmitry Baryshkov required-opps = <&rpmhpd_opp_svs>; 51801e869ccSDmitry Baryshkov }; 51901e869ccSDmitry Baryshkov }; 52001e869ccSDmitry Baryshkov 521e5813b15SDmitry Baryshkov qupv3_id_2: geniqup@8c0000 { 522e5813b15SDmitry Baryshkov compatible = "qcom,geni-se-qup"; 523e5813b15SDmitry Baryshkov reg = <0x0 0x008c0000 0x0 0x6000>; 524e5813b15SDmitry Baryshkov clock-names = "m-ahb", "s-ahb"; 525e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 526e5813b15SDmitry Baryshkov <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 527e5813b15SDmitry Baryshkov #address-cells = <2>; 528e5813b15SDmitry Baryshkov #size-cells = <2>; 52985309393SDmitry Baryshkov iommus = <&apps_smmu 0x63 0x0>; 530e5813b15SDmitry Baryshkov ranges; 531e5813b15SDmitry Baryshkov status = "disabled"; 532e5813b15SDmitry Baryshkov 533e5813b15SDmitry Baryshkov i2c14: i2c@880000 { 534e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 535e5813b15SDmitry Baryshkov reg = <0 0x00880000 0 0x4000>; 536e5813b15SDmitry Baryshkov clock-names = "se"; 537e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 538e5813b15SDmitry Baryshkov pinctrl-names = "default"; 539e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c14_default>; 540e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 541e5813b15SDmitry Baryshkov #address-cells = <1>; 542e5813b15SDmitry Baryshkov #size-cells = <0>; 543e5813b15SDmitry Baryshkov status = "disabled"; 544e5813b15SDmitry Baryshkov }; 545e5813b15SDmitry Baryshkov 546e5813b15SDmitry Baryshkov spi14: spi@880000 { 547e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 548e5813b15SDmitry Baryshkov reg = <0 0x00880000 0 0x4000>; 549e5813b15SDmitry Baryshkov clock-names = "se"; 550e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 551e5813b15SDmitry Baryshkov pinctrl-names = "default"; 552e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi14_default>; 553e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 554e5813b15SDmitry Baryshkov #address-cells = <1>; 555e5813b15SDmitry Baryshkov #size-cells = <0>; 55601e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 55701e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 558e5813b15SDmitry Baryshkov status = "disabled"; 559e5813b15SDmitry Baryshkov }; 560e5813b15SDmitry Baryshkov 561e5813b15SDmitry Baryshkov i2c15: i2c@884000 { 562e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 563e5813b15SDmitry Baryshkov reg = <0 0x00884000 0 0x4000>; 564e5813b15SDmitry Baryshkov clock-names = "se"; 565e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 566e5813b15SDmitry Baryshkov pinctrl-names = "default"; 567e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c15_default>; 568e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 569e5813b15SDmitry Baryshkov #address-cells = <1>; 570e5813b15SDmitry Baryshkov #size-cells = <0>; 571e5813b15SDmitry Baryshkov status = "disabled"; 572e5813b15SDmitry Baryshkov }; 573e5813b15SDmitry Baryshkov 574e5813b15SDmitry Baryshkov spi15: spi@884000 { 575e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 576e5813b15SDmitry Baryshkov reg = <0 0x00884000 0 0x4000>; 577e5813b15SDmitry Baryshkov clock-names = "se"; 578e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 579e5813b15SDmitry Baryshkov pinctrl-names = "default"; 580e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi15_default>; 581e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 582e5813b15SDmitry Baryshkov #address-cells = <1>; 583e5813b15SDmitry Baryshkov #size-cells = <0>; 58401e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 58501e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 586e5813b15SDmitry Baryshkov status = "disabled"; 587e5813b15SDmitry Baryshkov }; 588e5813b15SDmitry Baryshkov 589e5813b15SDmitry Baryshkov i2c16: i2c@888000 { 590e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 591e5813b15SDmitry Baryshkov reg = <0 0x00888000 0 0x4000>; 592e5813b15SDmitry Baryshkov clock-names = "se"; 593e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 594e5813b15SDmitry Baryshkov pinctrl-names = "default"; 595e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c16_default>; 596e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 597e5813b15SDmitry Baryshkov #address-cells = <1>; 598e5813b15SDmitry Baryshkov #size-cells = <0>; 599e5813b15SDmitry Baryshkov status = "disabled"; 600e5813b15SDmitry Baryshkov }; 601e5813b15SDmitry Baryshkov 602e5813b15SDmitry Baryshkov spi16: spi@888000 { 603e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 604e5813b15SDmitry Baryshkov reg = <0 0x00888000 0 0x4000>; 605e5813b15SDmitry Baryshkov clock-names = "se"; 606e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 607e5813b15SDmitry Baryshkov pinctrl-names = "default"; 608e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi16_default>; 609e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 610e5813b15SDmitry Baryshkov #address-cells = <1>; 611e5813b15SDmitry Baryshkov #size-cells = <0>; 61201e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 61301e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 614e5813b15SDmitry Baryshkov status = "disabled"; 615e5813b15SDmitry Baryshkov }; 616e5813b15SDmitry Baryshkov 617e5813b15SDmitry Baryshkov i2c17: i2c@88c000 { 618e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 619e5813b15SDmitry Baryshkov reg = <0 0x0088c000 0 0x4000>; 620e5813b15SDmitry Baryshkov clock-names = "se"; 621e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 622e5813b15SDmitry Baryshkov pinctrl-names = "default"; 623e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c17_default>; 624e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 625e5813b15SDmitry Baryshkov #address-cells = <1>; 626e5813b15SDmitry Baryshkov #size-cells = <0>; 627e5813b15SDmitry Baryshkov status = "disabled"; 628e5813b15SDmitry Baryshkov }; 629e5813b15SDmitry Baryshkov 630e5813b15SDmitry Baryshkov spi17: spi@88c000 { 631e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 632e5813b15SDmitry Baryshkov reg = <0 0x0088c000 0 0x4000>; 633e5813b15SDmitry Baryshkov clock-names = "se"; 634e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 635e5813b15SDmitry Baryshkov pinctrl-names = "default"; 636e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi17_default>; 637e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 638e5813b15SDmitry Baryshkov #address-cells = <1>; 639e5813b15SDmitry Baryshkov #size-cells = <0>; 64001e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 64101e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 642e5813b15SDmitry Baryshkov status = "disabled"; 643e5813b15SDmitry Baryshkov }; 644e5813b15SDmitry Baryshkov 64508a9ae2dSDmitry Baryshkov uart17: serial@88c000 { 64608a9ae2dSDmitry Baryshkov compatible = "qcom,geni-uart"; 64708a9ae2dSDmitry Baryshkov reg = <0 0x0088c000 0 0x4000>; 64808a9ae2dSDmitry Baryshkov clock-names = "se"; 64908a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 65008a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 65108a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart17_default>; 65208a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 65301e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 65401e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 65508a9ae2dSDmitry Baryshkov status = "disabled"; 65608a9ae2dSDmitry Baryshkov }; 65708a9ae2dSDmitry Baryshkov 658e5813b15SDmitry Baryshkov i2c18: i2c@890000 { 659e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 660e5813b15SDmitry Baryshkov reg = <0 0x00890000 0 0x4000>; 661e5813b15SDmitry Baryshkov clock-names = "se"; 662e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 663e5813b15SDmitry Baryshkov pinctrl-names = "default"; 664e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c18_default>; 665e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 666e5813b15SDmitry Baryshkov #address-cells = <1>; 667e5813b15SDmitry Baryshkov #size-cells = <0>; 668e5813b15SDmitry Baryshkov status = "disabled"; 669e5813b15SDmitry Baryshkov }; 670e5813b15SDmitry Baryshkov 671e5813b15SDmitry Baryshkov spi18: spi@890000 { 672e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 673e5813b15SDmitry Baryshkov reg = <0 0x00890000 0 0x4000>; 674e5813b15SDmitry Baryshkov clock-names = "se"; 675e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 676e5813b15SDmitry Baryshkov pinctrl-names = "default"; 677e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi18_default>; 678e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 679e5813b15SDmitry Baryshkov #address-cells = <1>; 680e5813b15SDmitry Baryshkov #size-cells = <0>; 68101e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 68201e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 683e5813b15SDmitry Baryshkov status = "disabled"; 684e5813b15SDmitry Baryshkov }; 685e5813b15SDmitry Baryshkov 68608a9ae2dSDmitry Baryshkov uart18: serial@890000 { 68708a9ae2dSDmitry Baryshkov compatible = "qcom,geni-uart"; 68808a9ae2dSDmitry Baryshkov reg = <0 0x00890000 0 0x4000>; 68908a9ae2dSDmitry Baryshkov clock-names = "se"; 69008a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 69108a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 69208a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart18_default>; 69308a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 69401e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 69501e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 69608a9ae2dSDmitry Baryshkov status = "disabled"; 69708a9ae2dSDmitry Baryshkov }; 69808a9ae2dSDmitry Baryshkov 699e5813b15SDmitry Baryshkov i2c19: i2c@894000 { 700e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 701e5813b15SDmitry Baryshkov reg = <0 0x00894000 0 0x4000>; 702e5813b15SDmitry Baryshkov clock-names = "se"; 703e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 704e5813b15SDmitry Baryshkov pinctrl-names = "default"; 705e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c19_default>; 706e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 707e5813b15SDmitry Baryshkov #address-cells = <1>; 708e5813b15SDmitry Baryshkov #size-cells = <0>; 709e5813b15SDmitry Baryshkov status = "disabled"; 710e5813b15SDmitry Baryshkov }; 711e5813b15SDmitry Baryshkov 712e5813b15SDmitry Baryshkov spi19: spi@894000 { 713e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 714e5813b15SDmitry Baryshkov reg = <0 0x00894000 0 0x4000>; 715e5813b15SDmitry Baryshkov clock-names = "se"; 716e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 717e5813b15SDmitry Baryshkov pinctrl-names = "default"; 718e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi19_default>; 719e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 720e5813b15SDmitry Baryshkov #address-cells = <1>; 721e5813b15SDmitry Baryshkov #size-cells = <0>; 72201e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 72301e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 724e5813b15SDmitry Baryshkov status = "disabled"; 725e5813b15SDmitry Baryshkov }; 726e5813b15SDmitry Baryshkov }; 727e5813b15SDmitry Baryshkov 728e5813b15SDmitry Baryshkov qupv3_id_0: geniqup@9c0000 { 729e5813b15SDmitry Baryshkov compatible = "qcom,geni-se-qup"; 730e5813b15SDmitry Baryshkov reg = <0x0 0x009c0000 0x0 0x6000>; 731e5813b15SDmitry Baryshkov clock-names = "m-ahb", "s-ahb"; 732e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 733e5813b15SDmitry Baryshkov <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 734e5813b15SDmitry Baryshkov #address-cells = <2>; 735e5813b15SDmitry Baryshkov #size-cells = <2>; 73685309393SDmitry Baryshkov iommus = <&apps_smmu 0x5a3 0x0>; 737e5813b15SDmitry Baryshkov ranges; 738e5813b15SDmitry Baryshkov status = "disabled"; 739e5813b15SDmitry Baryshkov 740e5813b15SDmitry Baryshkov i2c0: i2c@980000 { 741e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 742e5813b15SDmitry Baryshkov reg = <0 0x00980000 0 0x4000>; 743e5813b15SDmitry Baryshkov clock-names = "se"; 744e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 745e5813b15SDmitry Baryshkov pinctrl-names = "default"; 746e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c0_default>; 747e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 748e5813b15SDmitry Baryshkov #address-cells = <1>; 749e5813b15SDmitry Baryshkov #size-cells = <0>; 750e5813b15SDmitry Baryshkov status = "disabled"; 751e5813b15SDmitry Baryshkov }; 752e5813b15SDmitry Baryshkov 753e5813b15SDmitry Baryshkov spi0: spi@980000 { 754e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 755e5813b15SDmitry Baryshkov reg = <0 0x00980000 0 0x4000>; 756e5813b15SDmitry Baryshkov clock-names = "se"; 757e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 758e5813b15SDmitry Baryshkov pinctrl-names = "default"; 759e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi0_default>; 760e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 761e5813b15SDmitry Baryshkov #address-cells = <1>; 762e5813b15SDmitry Baryshkov #size-cells = <0>; 76301e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 76401e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 765e5813b15SDmitry Baryshkov status = "disabled"; 766e5813b15SDmitry Baryshkov }; 767e5813b15SDmitry Baryshkov 768e5813b15SDmitry Baryshkov i2c1: i2c@984000 { 769e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 770e5813b15SDmitry Baryshkov reg = <0 0x00984000 0 0x4000>; 771e5813b15SDmitry Baryshkov clock-names = "se"; 772e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 773e5813b15SDmitry Baryshkov pinctrl-names = "default"; 774e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c1_default>; 775e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 776e5813b15SDmitry Baryshkov #address-cells = <1>; 777e5813b15SDmitry Baryshkov #size-cells = <0>; 778e5813b15SDmitry Baryshkov status = "disabled"; 779e5813b15SDmitry Baryshkov }; 780e5813b15SDmitry Baryshkov 781e5813b15SDmitry Baryshkov spi1: spi@984000 { 782e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 783e5813b15SDmitry Baryshkov reg = <0 0x00984000 0 0x4000>; 784e5813b15SDmitry Baryshkov clock-names = "se"; 785e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 786e5813b15SDmitry Baryshkov pinctrl-names = "default"; 787e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi1_default>; 788e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 789e5813b15SDmitry Baryshkov #address-cells = <1>; 790e5813b15SDmitry Baryshkov #size-cells = <0>; 79101e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 79201e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 793e5813b15SDmitry Baryshkov status = "disabled"; 794e5813b15SDmitry Baryshkov }; 795e5813b15SDmitry Baryshkov 796e5813b15SDmitry Baryshkov i2c2: i2c@988000 { 797e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 798e5813b15SDmitry Baryshkov reg = <0 0x00988000 0 0x4000>; 799e5813b15SDmitry Baryshkov clock-names = "se"; 800e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 801e5813b15SDmitry Baryshkov pinctrl-names = "default"; 802e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c2_default>; 803e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 804e5813b15SDmitry Baryshkov #address-cells = <1>; 805e5813b15SDmitry Baryshkov #size-cells = <0>; 806e5813b15SDmitry Baryshkov status = "disabled"; 807e5813b15SDmitry Baryshkov }; 808e5813b15SDmitry Baryshkov 809e5813b15SDmitry Baryshkov spi2: spi@988000 { 810e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 811e5813b15SDmitry Baryshkov reg = <0 0x00988000 0 0x4000>; 812e5813b15SDmitry Baryshkov clock-names = "se"; 813e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 814e5813b15SDmitry Baryshkov pinctrl-names = "default"; 815e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi2_default>; 816e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 817e5813b15SDmitry Baryshkov #address-cells = <1>; 818e5813b15SDmitry Baryshkov #size-cells = <0>; 81901e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 82001e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 821e5813b15SDmitry Baryshkov status = "disabled"; 822e5813b15SDmitry Baryshkov }; 823e5813b15SDmitry Baryshkov 82408a9ae2dSDmitry Baryshkov uart2: serial@988000 { 82508a9ae2dSDmitry Baryshkov compatible = "qcom,geni-debug-uart"; 82608a9ae2dSDmitry Baryshkov reg = <0 0x00988000 0 0x4000>; 82708a9ae2dSDmitry Baryshkov clock-names = "se"; 82808a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 82908a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 83008a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart2_default>; 83108a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 83201e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 83301e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 83408a9ae2dSDmitry Baryshkov status = "disabled"; 83508a9ae2dSDmitry Baryshkov }; 83608a9ae2dSDmitry Baryshkov 837e5813b15SDmitry Baryshkov i2c3: i2c@98c000 { 838e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 839e5813b15SDmitry Baryshkov reg = <0 0x0098c000 0 0x4000>; 840e5813b15SDmitry Baryshkov clock-names = "se"; 841e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 842e5813b15SDmitry Baryshkov pinctrl-names = "default"; 843e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c3_default>; 844e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 845e5813b15SDmitry Baryshkov #address-cells = <1>; 846e5813b15SDmitry Baryshkov #size-cells = <0>; 847e5813b15SDmitry Baryshkov status = "disabled"; 848e5813b15SDmitry Baryshkov }; 849e5813b15SDmitry Baryshkov 850e5813b15SDmitry Baryshkov spi3: spi@98c000 { 851e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 852e5813b15SDmitry Baryshkov reg = <0 0x0098c000 0 0x4000>; 853e5813b15SDmitry Baryshkov clock-names = "se"; 854e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 855e5813b15SDmitry Baryshkov pinctrl-names = "default"; 856e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi3_default>; 857e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 858e5813b15SDmitry Baryshkov #address-cells = <1>; 859e5813b15SDmitry Baryshkov #size-cells = <0>; 86001e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 86101e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 862e5813b15SDmitry Baryshkov status = "disabled"; 863e5813b15SDmitry Baryshkov }; 864e5813b15SDmitry Baryshkov 865e5813b15SDmitry Baryshkov i2c4: i2c@990000 { 866e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 867e5813b15SDmitry Baryshkov reg = <0 0x00990000 0 0x4000>; 868e5813b15SDmitry Baryshkov clock-names = "se"; 869e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 870e5813b15SDmitry Baryshkov pinctrl-names = "default"; 871e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c4_default>; 872e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 873e5813b15SDmitry Baryshkov #address-cells = <1>; 874e5813b15SDmitry Baryshkov #size-cells = <0>; 875e5813b15SDmitry Baryshkov status = "disabled"; 876e5813b15SDmitry Baryshkov }; 877e5813b15SDmitry Baryshkov 878e5813b15SDmitry Baryshkov spi4: spi@990000 { 879e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 880e5813b15SDmitry Baryshkov reg = <0 0x00990000 0 0x4000>; 881e5813b15SDmitry Baryshkov clock-names = "se"; 882e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 883e5813b15SDmitry Baryshkov pinctrl-names = "default"; 884e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi4_default>; 885e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 886e5813b15SDmitry Baryshkov #address-cells = <1>; 887e5813b15SDmitry Baryshkov #size-cells = <0>; 88801e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 88901e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 890e5813b15SDmitry Baryshkov status = "disabled"; 891e5813b15SDmitry Baryshkov }; 892e5813b15SDmitry Baryshkov 893e5813b15SDmitry Baryshkov i2c5: i2c@994000 { 894e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 895e5813b15SDmitry Baryshkov reg = <0 0x00994000 0 0x4000>; 896e5813b15SDmitry Baryshkov clock-names = "se"; 897e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 898e5813b15SDmitry Baryshkov pinctrl-names = "default"; 899e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c5_default>; 900e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 901e5813b15SDmitry Baryshkov #address-cells = <1>; 902e5813b15SDmitry Baryshkov #size-cells = <0>; 903e5813b15SDmitry Baryshkov status = "disabled"; 904e5813b15SDmitry Baryshkov }; 905e5813b15SDmitry Baryshkov 906e5813b15SDmitry Baryshkov spi5: spi@994000 { 907e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 908e5813b15SDmitry Baryshkov reg = <0 0x00994000 0 0x4000>; 909e5813b15SDmitry Baryshkov clock-names = "se"; 910e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 911e5813b15SDmitry Baryshkov pinctrl-names = "default"; 912e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi5_default>; 913e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 914e5813b15SDmitry Baryshkov #address-cells = <1>; 915e5813b15SDmitry Baryshkov #size-cells = <0>; 91601e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 91701e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 918e5813b15SDmitry Baryshkov status = "disabled"; 919e5813b15SDmitry Baryshkov }; 920e5813b15SDmitry Baryshkov 921e5813b15SDmitry Baryshkov i2c6: i2c@998000 { 922e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 923e5813b15SDmitry Baryshkov reg = <0 0x00998000 0 0x4000>; 924e5813b15SDmitry Baryshkov clock-names = "se"; 925e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 926e5813b15SDmitry Baryshkov pinctrl-names = "default"; 927e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c6_default>; 928e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 929e5813b15SDmitry Baryshkov #address-cells = <1>; 930e5813b15SDmitry Baryshkov #size-cells = <0>; 931e5813b15SDmitry Baryshkov status = "disabled"; 932e5813b15SDmitry Baryshkov }; 933e5813b15SDmitry Baryshkov 934e5813b15SDmitry Baryshkov spi6: spi@998000 { 935e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 936e5813b15SDmitry Baryshkov reg = <0 0x00998000 0 0x4000>; 937e5813b15SDmitry Baryshkov clock-names = "se"; 938e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 939e5813b15SDmitry Baryshkov pinctrl-names = "default"; 940e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi6_default>; 941e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 942e5813b15SDmitry Baryshkov #address-cells = <1>; 943e5813b15SDmitry Baryshkov #size-cells = <0>; 94401e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 94501e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 946e5813b15SDmitry Baryshkov status = "disabled"; 947e5813b15SDmitry Baryshkov }; 948e5813b15SDmitry Baryshkov 94908a9ae2dSDmitry Baryshkov uart6: serial@998000 { 95008a9ae2dSDmitry Baryshkov compatible = "qcom,geni-uart"; 95108a9ae2dSDmitry Baryshkov reg = <0 0x00998000 0 0x4000>; 95208a9ae2dSDmitry Baryshkov clock-names = "se"; 95308a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 95408a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 95508a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart6_default>; 95608a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 95701e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 95801e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 95908a9ae2dSDmitry Baryshkov status = "disabled"; 96008a9ae2dSDmitry Baryshkov }; 96108a9ae2dSDmitry Baryshkov 962e5813b15SDmitry Baryshkov i2c7: i2c@99c000 { 963e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 964e5813b15SDmitry Baryshkov reg = <0 0x0099c000 0 0x4000>; 965e5813b15SDmitry Baryshkov clock-names = "se"; 966e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 967e5813b15SDmitry Baryshkov pinctrl-names = "default"; 968e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c7_default>; 969e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 970e5813b15SDmitry Baryshkov #address-cells = <1>; 971e5813b15SDmitry Baryshkov #size-cells = <0>; 972e5813b15SDmitry Baryshkov status = "disabled"; 973e5813b15SDmitry Baryshkov }; 974e5813b15SDmitry Baryshkov 975e5813b15SDmitry Baryshkov spi7: spi@99c000 { 976e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 977e5813b15SDmitry Baryshkov reg = <0 0x0099c000 0 0x4000>; 978e5813b15SDmitry Baryshkov clock-names = "se"; 979e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 980e5813b15SDmitry Baryshkov pinctrl-names = "default"; 981e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi7_default>; 982e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 983e5813b15SDmitry Baryshkov #address-cells = <1>; 984e5813b15SDmitry Baryshkov #size-cells = <0>; 98501e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 98601e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 987e5813b15SDmitry Baryshkov status = "disabled"; 988e5813b15SDmitry Baryshkov }; 989e5813b15SDmitry Baryshkov }; 990e5813b15SDmitry Baryshkov 99160378f1aSVenkata Narendra Kumar Gutta qupv3_id_1: geniqup@ac0000 { 99260378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,geni-se-qup"; 99360378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x00ac0000 0x0 0x6000>; 99460378f1aSVenkata Narendra Kumar Gutta clock-names = "m-ahb", "s-ahb"; 995fe3dfc25SJonathan Marek clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 996fe3dfc25SJonathan Marek <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 99760378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 99860378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 99985309393SDmitry Baryshkov iommus = <&apps_smmu 0x43 0x0>; 100060378f1aSVenkata Narendra Kumar Gutta ranges; 100160378f1aSVenkata Narendra Kumar Gutta status = "disabled"; 100260378f1aSVenkata Narendra Kumar Gutta 1003e5813b15SDmitry Baryshkov i2c8: i2c@a80000 { 1004e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1005e5813b15SDmitry Baryshkov reg = <0 0x00a80000 0 0x4000>; 1006e5813b15SDmitry Baryshkov clock-names = "se"; 1007e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1008e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1009e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c8_default>; 1010e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1011e5813b15SDmitry Baryshkov #address-cells = <1>; 1012e5813b15SDmitry Baryshkov #size-cells = <0>; 1013e5813b15SDmitry Baryshkov status = "disabled"; 1014e5813b15SDmitry Baryshkov }; 1015e5813b15SDmitry Baryshkov 1016e5813b15SDmitry Baryshkov spi8: spi@a80000 { 1017e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1018e5813b15SDmitry Baryshkov reg = <0 0x00a80000 0 0x4000>; 1019e5813b15SDmitry Baryshkov clock-names = "se"; 1020e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1021e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1022e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi8_default>; 1023e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1024e5813b15SDmitry Baryshkov #address-cells = <1>; 1025e5813b15SDmitry Baryshkov #size-cells = <0>; 102601e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 102701e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 1028e5813b15SDmitry Baryshkov status = "disabled"; 1029e5813b15SDmitry Baryshkov }; 1030e5813b15SDmitry Baryshkov 1031e5813b15SDmitry Baryshkov i2c9: i2c@a84000 { 1032e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1033e5813b15SDmitry Baryshkov reg = <0 0x00a84000 0 0x4000>; 1034e5813b15SDmitry Baryshkov clock-names = "se"; 1035e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1036e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1037e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c9_default>; 1038e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1039e5813b15SDmitry Baryshkov #address-cells = <1>; 1040e5813b15SDmitry Baryshkov #size-cells = <0>; 1041e5813b15SDmitry Baryshkov status = "disabled"; 1042e5813b15SDmitry Baryshkov }; 1043e5813b15SDmitry Baryshkov 1044e5813b15SDmitry Baryshkov spi9: spi@a84000 { 1045e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1046e5813b15SDmitry Baryshkov reg = <0 0x00a84000 0 0x4000>; 1047e5813b15SDmitry Baryshkov clock-names = "se"; 1048e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1049e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1050e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi9_default>; 1051e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1052e5813b15SDmitry Baryshkov #address-cells = <1>; 1053e5813b15SDmitry Baryshkov #size-cells = <0>; 105401e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 105501e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 1056e5813b15SDmitry Baryshkov status = "disabled"; 1057e5813b15SDmitry Baryshkov }; 1058e5813b15SDmitry Baryshkov 1059e5813b15SDmitry Baryshkov i2c10: i2c@a88000 { 1060e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1061e5813b15SDmitry Baryshkov reg = <0 0x00a88000 0 0x4000>; 1062e5813b15SDmitry Baryshkov clock-names = "se"; 1063e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1064e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1065e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c10_default>; 1066e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1067e5813b15SDmitry Baryshkov #address-cells = <1>; 1068e5813b15SDmitry Baryshkov #size-cells = <0>; 1069e5813b15SDmitry Baryshkov status = "disabled"; 1070e5813b15SDmitry Baryshkov }; 1071e5813b15SDmitry Baryshkov 1072e5813b15SDmitry Baryshkov spi10: spi@a88000 { 1073e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1074e5813b15SDmitry Baryshkov reg = <0 0x00a88000 0 0x4000>; 1075e5813b15SDmitry Baryshkov clock-names = "se"; 1076e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1077e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1078e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi10_default>; 1079e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1080e5813b15SDmitry Baryshkov #address-cells = <1>; 1081e5813b15SDmitry Baryshkov #size-cells = <0>; 108201e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 108301e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 1084e5813b15SDmitry Baryshkov status = "disabled"; 1085e5813b15SDmitry Baryshkov }; 1086e5813b15SDmitry Baryshkov 1087e5813b15SDmitry Baryshkov i2c11: i2c@a8c000 { 1088e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1089e5813b15SDmitry Baryshkov reg = <0 0x00a8c000 0 0x4000>; 1090e5813b15SDmitry Baryshkov clock-names = "se"; 1091e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1092e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1093e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c11_default>; 1094e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1095e5813b15SDmitry Baryshkov #address-cells = <1>; 1096e5813b15SDmitry Baryshkov #size-cells = <0>; 1097e5813b15SDmitry Baryshkov status = "disabled"; 1098e5813b15SDmitry Baryshkov }; 1099e5813b15SDmitry Baryshkov 1100e5813b15SDmitry Baryshkov spi11: spi@a8c000 { 1101e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1102e5813b15SDmitry Baryshkov reg = <0 0x00a8c000 0 0x4000>; 1103e5813b15SDmitry Baryshkov clock-names = "se"; 1104e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1105e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1106e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi11_default>; 1107e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1108e5813b15SDmitry Baryshkov #address-cells = <1>; 1109e5813b15SDmitry Baryshkov #size-cells = <0>; 111001e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 111101e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 1112e5813b15SDmitry Baryshkov status = "disabled"; 1113e5813b15SDmitry Baryshkov }; 1114e5813b15SDmitry Baryshkov 1115e5813b15SDmitry Baryshkov i2c12: i2c@a90000 { 1116e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1117e5813b15SDmitry Baryshkov reg = <0 0x00a90000 0 0x4000>; 1118e5813b15SDmitry Baryshkov clock-names = "se"; 1119e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1120e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1121e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c12_default>; 1122e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1123e5813b15SDmitry Baryshkov #address-cells = <1>; 1124e5813b15SDmitry Baryshkov #size-cells = <0>; 1125e5813b15SDmitry Baryshkov status = "disabled"; 1126e5813b15SDmitry Baryshkov }; 1127e5813b15SDmitry Baryshkov 1128e5813b15SDmitry Baryshkov spi12: spi@a90000 { 1129e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1130e5813b15SDmitry Baryshkov reg = <0 0x00a90000 0 0x4000>; 1131e5813b15SDmitry Baryshkov clock-names = "se"; 1132e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1133e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1134e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi12_default>; 1135e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1136e5813b15SDmitry Baryshkov #address-cells = <1>; 1137e5813b15SDmitry Baryshkov #size-cells = <0>; 113801e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 113901e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 1140e5813b15SDmitry Baryshkov status = "disabled"; 1141e5813b15SDmitry Baryshkov }; 1142e5813b15SDmitry Baryshkov 1143bb1dfb4dSManivannan Sadhasivam uart12: serial@a90000 { 114460378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,geni-debug-uart"; 114560378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x00a90000 0x0 0x4000>; 114660378f1aSVenkata Narendra Kumar Gutta clock-names = "se"; 1147fe3dfc25SJonathan Marek clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1148bb1dfb4dSManivannan Sadhasivam pinctrl-names = "default"; 1149bb1dfb4dSManivannan Sadhasivam pinctrl-0 = <&qup_uart12_default>; 115060378f1aSVenkata Narendra Kumar Gutta interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 115101e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 115201e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 115360378f1aSVenkata Narendra Kumar Gutta status = "disabled"; 115460378f1aSVenkata Narendra Kumar Gutta }; 1155e5813b15SDmitry Baryshkov 1156e5813b15SDmitry Baryshkov i2c13: i2c@a94000 { 1157e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1158e5813b15SDmitry Baryshkov reg = <0 0x00a94000 0 0x4000>; 1159e5813b15SDmitry Baryshkov clock-names = "se"; 1160e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1161e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1162e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c13_default>; 1163e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1164e5813b15SDmitry Baryshkov #address-cells = <1>; 1165e5813b15SDmitry Baryshkov #size-cells = <0>; 1166e5813b15SDmitry Baryshkov status = "disabled"; 1167e5813b15SDmitry Baryshkov }; 1168e5813b15SDmitry Baryshkov 1169e5813b15SDmitry Baryshkov spi13: spi@a94000 { 1170e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1171e5813b15SDmitry Baryshkov reg = <0 0x00a94000 0 0x4000>; 1172e5813b15SDmitry Baryshkov clock-names = "se"; 1173e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1174e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1175e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_spi13_default>; 1176e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1177e5813b15SDmitry Baryshkov #address-cells = <1>; 1178e5813b15SDmitry Baryshkov #size-cells = <0>; 117901e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 118001e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 1181e5813b15SDmitry Baryshkov status = "disabled"; 1182e5813b15SDmitry Baryshkov }; 118360378f1aSVenkata Narendra Kumar Gutta }; 118460378f1aSVenkata Narendra Kumar Gutta 1185e7e41a20SJonathan Marek config_noc: interconnect@1500000 { 1186e7e41a20SJonathan Marek compatible = "qcom,sm8250-config-noc"; 1187e7e41a20SJonathan Marek reg = <0 0x01500000 0 0xa580>; 1188e7e41a20SJonathan Marek #interconnect-cells = <1>; 1189e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1190e7e41a20SJonathan Marek }; 1191e7e41a20SJonathan Marek 1192e7e41a20SJonathan Marek system_noc: interconnect@1620000 { 1193e7e41a20SJonathan Marek compatible = "qcom,sm8250-system-noc"; 1194e7e41a20SJonathan Marek reg = <0 0x01620000 0 0x1c200>; 1195e7e41a20SJonathan Marek #interconnect-cells = <1>; 1196e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1197e7e41a20SJonathan Marek }; 1198e7e41a20SJonathan Marek 1199e7e41a20SJonathan Marek mc_virt: interconnect@163d000 { 1200e7e41a20SJonathan Marek compatible = "qcom,sm8250-mc-virt"; 1201e7e41a20SJonathan Marek reg = <0 0x0163d000 0 0x1000>; 1202e7e41a20SJonathan Marek #interconnect-cells = <1>; 1203e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1204e7e41a20SJonathan Marek }; 1205e7e41a20SJonathan Marek 1206e7e41a20SJonathan Marek aggre1_noc: interconnect@16e0000 { 1207e7e41a20SJonathan Marek compatible = "qcom,sm8250-aggre1-noc"; 1208e7e41a20SJonathan Marek reg = <0 0x016e0000 0 0x1f180>; 1209e7e41a20SJonathan Marek #interconnect-cells = <1>; 1210e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1211e7e41a20SJonathan Marek }; 1212e7e41a20SJonathan Marek 1213e7e41a20SJonathan Marek aggre2_noc: interconnect@1700000 { 1214e7e41a20SJonathan Marek compatible = "qcom,sm8250-aggre2-noc"; 1215e7e41a20SJonathan Marek reg = <0 0x01700000 0 0x33000>; 1216e7e41a20SJonathan Marek #interconnect-cells = <1>; 1217e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1218e7e41a20SJonathan Marek }; 1219e7e41a20SJonathan Marek 1220e7e41a20SJonathan Marek compute_noc: interconnect@1733000 { 1221e7e41a20SJonathan Marek compatible = "qcom,sm8250-compute-noc"; 1222e7e41a20SJonathan Marek reg = <0 0x01733000 0 0xa180>; 1223e7e41a20SJonathan Marek #interconnect-cells = <1>; 1224e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1225e7e41a20SJonathan Marek }; 1226e7e41a20SJonathan Marek 1227e7e41a20SJonathan Marek mmss_noc: interconnect@1740000 { 1228e7e41a20SJonathan Marek compatible = "qcom,sm8250-mmss-noc"; 1229e7e41a20SJonathan Marek reg = <0 0x01740000 0 0x1f080>; 1230e7e41a20SJonathan Marek #interconnect-cells = <1>; 1231e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1232e7e41a20SJonathan Marek }; 1233e7e41a20SJonathan Marek 1234e53bdfc0SManivannan Sadhasivam pcie0: pci@1c00000 { 1235e53bdfc0SManivannan Sadhasivam compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1236e53bdfc0SManivannan Sadhasivam reg = <0 0x01c00000 0 0x3000>, 1237e53bdfc0SManivannan Sadhasivam <0 0x60000000 0 0xf1d>, 1238e53bdfc0SManivannan Sadhasivam <0 0x60000f20 0 0xa8>, 1239e53bdfc0SManivannan Sadhasivam <0 0x60001000 0 0x1000>, 1240e53bdfc0SManivannan Sadhasivam <0 0x60100000 0 0x100000>; 1241e53bdfc0SManivannan Sadhasivam reg-names = "parf", "dbi", "elbi", "atu", "config"; 1242e53bdfc0SManivannan Sadhasivam device_type = "pci"; 1243e53bdfc0SManivannan Sadhasivam linux,pci-domain = <0>; 1244e53bdfc0SManivannan Sadhasivam bus-range = <0x00 0xff>; 1245e53bdfc0SManivannan Sadhasivam num-lanes = <1>; 1246e53bdfc0SManivannan Sadhasivam 1247e53bdfc0SManivannan Sadhasivam #address-cells = <3>; 1248e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1249e53bdfc0SManivannan Sadhasivam 1250e53bdfc0SManivannan Sadhasivam ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1251e53bdfc0SManivannan Sadhasivam <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1252e53bdfc0SManivannan Sadhasivam 1253e53bdfc0SManivannan Sadhasivam interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1254e53bdfc0SManivannan Sadhasivam interrupt-names = "msi"; 1255e53bdfc0SManivannan Sadhasivam #interrupt-cells = <1>; 1256e53bdfc0SManivannan Sadhasivam interrupt-map-mask = <0 0 0 0x7>; 1257e53bdfc0SManivannan Sadhasivam interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1258e53bdfc0SManivannan Sadhasivam <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1259e53bdfc0SManivannan Sadhasivam <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1260e53bdfc0SManivannan Sadhasivam <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1261e53bdfc0SManivannan Sadhasivam 1262e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1263e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_AUX_CLK>, 1264e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1265e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1266e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1267e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1268e53bdfc0SManivannan Sadhasivam <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1269e53bdfc0SManivannan Sadhasivam <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1270e53bdfc0SManivannan Sadhasivam clock-names = "pipe", 1271e53bdfc0SManivannan Sadhasivam "aux", 1272e53bdfc0SManivannan Sadhasivam "cfg", 1273e53bdfc0SManivannan Sadhasivam "bus_master", 1274e53bdfc0SManivannan Sadhasivam "bus_slave", 1275e53bdfc0SManivannan Sadhasivam "slave_q2a", 1276e53bdfc0SManivannan Sadhasivam "tbu", 1277e53bdfc0SManivannan Sadhasivam "ddrss_sf_tbu"; 1278e53bdfc0SManivannan Sadhasivam 1279e53bdfc0SManivannan Sadhasivam iommus = <&apps_smmu 0x1c00 0x7f>; 1280e53bdfc0SManivannan Sadhasivam iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1281e53bdfc0SManivannan Sadhasivam <0x100 &apps_smmu 0x1c01 0x1>; 1282e53bdfc0SManivannan Sadhasivam 1283e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_0_BCR>; 1284e53bdfc0SManivannan Sadhasivam reset-names = "pci"; 1285e53bdfc0SManivannan Sadhasivam 1286e53bdfc0SManivannan Sadhasivam power-domains = <&gcc PCIE_0_GDSC>; 1287e53bdfc0SManivannan Sadhasivam 1288e53bdfc0SManivannan Sadhasivam phys = <&pcie0_lane>; 1289e53bdfc0SManivannan Sadhasivam phy-names = "pciephy"; 1290e53bdfc0SManivannan Sadhasivam 1291e53bdfc0SManivannan Sadhasivam status = "disabled"; 1292e53bdfc0SManivannan Sadhasivam }; 1293e53bdfc0SManivannan Sadhasivam 1294e53bdfc0SManivannan Sadhasivam pcie0_phy: phy@1c06000 { 1295e53bdfc0SManivannan Sadhasivam compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1296e53bdfc0SManivannan Sadhasivam reg = <0 0x01c06000 0 0x1c0>; 1297e53bdfc0SManivannan Sadhasivam #address-cells = <2>; 1298e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1299e53bdfc0SManivannan Sadhasivam ranges; 1300e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1301e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1302e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1303e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1304e53bdfc0SManivannan Sadhasivam clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1305e53bdfc0SManivannan Sadhasivam 1306e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1307e53bdfc0SManivannan Sadhasivam reset-names = "phy"; 1308e53bdfc0SManivannan Sadhasivam 1309e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1310e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <100000000>; 1311e53bdfc0SManivannan Sadhasivam 1312e53bdfc0SManivannan Sadhasivam status = "disabled"; 1313e53bdfc0SManivannan Sadhasivam 1314e53bdfc0SManivannan Sadhasivam pcie0_lane: lanes@1c06200 { 1315e53bdfc0SManivannan Sadhasivam reg = <0 0x1c06200 0 0x170>, /* tx */ 1316e53bdfc0SManivannan Sadhasivam <0 0x1c06400 0 0x200>, /* rx */ 1317e53bdfc0SManivannan Sadhasivam <0 0x1c06800 0 0x1f0>, /* pcs */ 1318e53bdfc0SManivannan Sadhasivam <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1319e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1320e53bdfc0SManivannan Sadhasivam clock-names = "pipe0"; 1321e53bdfc0SManivannan Sadhasivam 1322e53bdfc0SManivannan Sadhasivam #phy-cells = <0>; 1323e53bdfc0SManivannan Sadhasivam clock-output-names = "pcie_0_pipe_clk"; 1324e53bdfc0SManivannan Sadhasivam }; 1325e53bdfc0SManivannan Sadhasivam }; 1326e53bdfc0SManivannan Sadhasivam 1327e53bdfc0SManivannan Sadhasivam pcie1: pci@1c08000 { 1328e53bdfc0SManivannan Sadhasivam compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1329e53bdfc0SManivannan Sadhasivam reg = <0 0x01c08000 0 0x3000>, 1330e53bdfc0SManivannan Sadhasivam <0 0x40000000 0 0xf1d>, 1331e53bdfc0SManivannan Sadhasivam <0 0x40000f20 0 0xa8>, 1332e53bdfc0SManivannan Sadhasivam <0 0x40001000 0 0x1000>, 1333e53bdfc0SManivannan Sadhasivam <0 0x40100000 0 0x100000>; 1334e53bdfc0SManivannan Sadhasivam reg-names = "parf", "dbi", "elbi", "atu", "config"; 1335e53bdfc0SManivannan Sadhasivam device_type = "pci"; 1336e53bdfc0SManivannan Sadhasivam linux,pci-domain = <1>; 1337e53bdfc0SManivannan Sadhasivam bus-range = <0x00 0xff>; 1338e53bdfc0SManivannan Sadhasivam num-lanes = <2>; 1339e53bdfc0SManivannan Sadhasivam 1340e53bdfc0SManivannan Sadhasivam #address-cells = <3>; 1341e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1342e53bdfc0SManivannan Sadhasivam 1343e53bdfc0SManivannan Sadhasivam ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1344e53bdfc0SManivannan Sadhasivam <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1345e53bdfc0SManivannan Sadhasivam 1346e53bdfc0SManivannan Sadhasivam interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>; 1347e53bdfc0SManivannan Sadhasivam interrupt-names = "msi"; 1348e53bdfc0SManivannan Sadhasivam #interrupt-cells = <1>; 1349e53bdfc0SManivannan Sadhasivam interrupt-map-mask = <0 0 0 0x7>; 1350e53bdfc0SManivannan Sadhasivam interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1351e53bdfc0SManivannan Sadhasivam <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1352e53bdfc0SManivannan Sadhasivam <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1353e53bdfc0SManivannan Sadhasivam <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1354e53bdfc0SManivannan Sadhasivam 1355e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1356e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_AUX_CLK>, 1357e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1358e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1359e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1360e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1361e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1362e53bdfc0SManivannan Sadhasivam <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1363e53bdfc0SManivannan Sadhasivam <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1364e53bdfc0SManivannan Sadhasivam clock-names = "pipe", 1365e53bdfc0SManivannan Sadhasivam "aux", 1366e53bdfc0SManivannan Sadhasivam "cfg", 1367e53bdfc0SManivannan Sadhasivam "bus_master", 1368e53bdfc0SManivannan Sadhasivam "bus_slave", 1369e53bdfc0SManivannan Sadhasivam "slave_q2a", 1370e53bdfc0SManivannan Sadhasivam "ref", 1371e53bdfc0SManivannan Sadhasivam "tbu", 1372e53bdfc0SManivannan Sadhasivam "ddrss_sf_tbu"; 1373e53bdfc0SManivannan Sadhasivam 1374e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1375e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <19200000>; 1376e53bdfc0SManivannan Sadhasivam 1377e53bdfc0SManivannan Sadhasivam iommus = <&apps_smmu 0x1c80 0x7f>; 1378e53bdfc0SManivannan Sadhasivam iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1379e53bdfc0SManivannan Sadhasivam <0x100 &apps_smmu 0x1c81 0x1>; 1380e53bdfc0SManivannan Sadhasivam 1381e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_1_BCR>; 1382e53bdfc0SManivannan Sadhasivam reset-names = "pci"; 1383e53bdfc0SManivannan Sadhasivam 1384e53bdfc0SManivannan Sadhasivam power-domains = <&gcc PCIE_1_GDSC>; 1385e53bdfc0SManivannan Sadhasivam 1386e53bdfc0SManivannan Sadhasivam phys = <&pcie1_lane>; 1387e53bdfc0SManivannan Sadhasivam phy-names = "pciephy"; 1388e53bdfc0SManivannan Sadhasivam 1389e53bdfc0SManivannan Sadhasivam status = "disabled"; 1390e53bdfc0SManivannan Sadhasivam }; 1391e53bdfc0SManivannan Sadhasivam 1392e53bdfc0SManivannan Sadhasivam pcie1_phy: phy@1c0e000 { 1393e53bdfc0SManivannan Sadhasivam compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1394e53bdfc0SManivannan Sadhasivam reg = <0 0x01c0e000 0 0x1c0>; 1395e53bdfc0SManivannan Sadhasivam #address-cells = <2>; 1396e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1397e53bdfc0SManivannan Sadhasivam ranges; 1398e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1399e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1400e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1401e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1402e53bdfc0SManivannan Sadhasivam clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1403e53bdfc0SManivannan Sadhasivam 1404e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1405e53bdfc0SManivannan Sadhasivam reset-names = "phy"; 1406e53bdfc0SManivannan Sadhasivam 1407e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1408e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <100000000>; 1409e53bdfc0SManivannan Sadhasivam 1410e53bdfc0SManivannan Sadhasivam status = "disabled"; 1411e53bdfc0SManivannan Sadhasivam 1412e53bdfc0SManivannan Sadhasivam pcie1_lane: lanes@1c0e200 { 1413e53bdfc0SManivannan Sadhasivam reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1414e53bdfc0SManivannan Sadhasivam <0 0x1c0e400 0 0x200>, /* rx0 */ 1415e53bdfc0SManivannan Sadhasivam <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1416e53bdfc0SManivannan Sadhasivam <0 0x1c0e600 0 0x170>, /* tx1 */ 1417e53bdfc0SManivannan Sadhasivam <0 0x1c0e800 0 0x200>, /* rx1 */ 1418e53bdfc0SManivannan Sadhasivam <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1419e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1420e53bdfc0SManivannan Sadhasivam clock-names = "pipe0"; 1421e53bdfc0SManivannan Sadhasivam 1422e53bdfc0SManivannan Sadhasivam #phy-cells = <0>; 1423e53bdfc0SManivannan Sadhasivam clock-output-names = "pcie_1_pipe_clk"; 1424e53bdfc0SManivannan Sadhasivam }; 1425e53bdfc0SManivannan Sadhasivam }; 1426e53bdfc0SManivannan Sadhasivam 1427e53bdfc0SManivannan Sadhasivam pcie2: pci@1c10000 { 1428e53bdfc0SManivannan Sadhasivam compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1429e53bdfc0SManivannan Sadhasivam reg = <0 0x01c10000 0 0x3000>, 1430e53bdfc0SManivannan Sadhasivam <0 0x64000000 0 0xf1d>, 1431e53bdfc0SManivannan Sadhasivam <0 0x64000f20 0 0xa8>, 1432e53bdfc0SManivannan Sadhasivam <0 0x64001000 0 0x1000>, 1433e53bdfc0SManivannan Sadhasivam <0 0x64100000 0 0x100000>; 1434e53bdfc0SManivannan Sadhasivam reg-names = "parf", "dbi", "elbi", "atu", "config"; 1435e53bdfc0SManivannan Sadhasivam device_type = "pci"; 1436e53bdfc0SManivannan Sadhasivam linux,pci-domain = <2>; 1437e53bdfc0SManivannan Sadhasivam bus-range = <0x00 0xff>; 1438e53bdfc0SManivannan Sadhasivam num-lanes = <2>; 1439e53bdfc0SManivannan Sadhasivam 1440e53bdfc0SManivannan Sadhasivam #address-cells = <3>; 1441e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1442e53bdfc0SManivannan Sadhasivam 1443e53bdfc0SManivannan Sadhasivam ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, 1444e53bdfc0SManivannan Sadhasivam <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 1445e53bdfc0SManivannan Sadhasivam 1446e53bdfc0SManivannan Sadhasivam interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; 1447e53bdfc0SManivannan Sadhasivam interrupt-names = "msi"; 1448e53bdfc0SManivannan Sadhasivam #interrupt-cells = <1>; 1449e53bdfc0SManivannan Sadhasivam interrupt-map-mask = <0 0 0 0x7>; 1450e53bdfc0SManivannan Sadhasivam interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1451e53bdfc0SManivannan Sadhasivam <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1452e53bdfc0SManivannan Sadhasivam <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1453e53bdfc0SManivannan Sadhasivam <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1454e53bdfc0SManivannan Sadhasivam 1455e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1456e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_AUX_CLK>, 1457e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1458e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1459e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 1460e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 1461e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1462e53bdfc0SManivannan Sadhasivam <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1463e53bdfc0SManivannan Sadhasivam <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1464e53bdfc0SManivannan Sadhasivam clock-names = "pipe", 1465e53bdfc0SManivannan Sadhasivam "aux", 1466e53bdfc0SManivannan Sadhasivam "cfg", 1467e53bdfc0SManivannan Sadhasivam "bus_master", 1468e53bdfc0SManivannan Sadhasivam "bus_slave", 1469e53bdfc0SManivannan Sadhasivam "slave_q2a", 1470e53bdfc0SManivannan Sadhasivam "ref", 1471e53bdfc0SManivannan Sadhasivam "tbu", 1472e53bdfc0SManivannan Sadhasivam "ddrss_sf_tbu"; 1473e53bdfc0SManivannan Sadhasivam 1474e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 1475e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <19200000>; 1476e53bdfc0SManivannan Sadhasivam 1477e53bdfc0SManivannan Sadhasivam iommus = <&apps_smmu 0x1d00 0x7f>; 1478e53bdfc0SManivannan Sadhasivam iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 1479e53bdfc0SManivannan Sadhasivam <0x100 &apps_smmu 0x1d01 0x1>; 1480e53bdfc0SManivannan Sadhasivam 1481e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_2_BCR>; 1482e53bdfc0SManivannan Sadhasivam reset-names = "pci"; 1483e53bdfc0SManivannan Sadhasivam 1484e53bdfc0SManivannan Sadhasivam power-domains = <&gcc PCIE_2_GDSC>; 1485e53bdfc0SManivannan Sadhasivam 1486e53bdfc0SManivannan Sadhasivam phys = <&pcie2_lane>; 1487e53bdfc0SManivannan Sadhasivam phy-names = "pciephy"; 1488e53bdfc0SManivannan Sadhasivam 1489e53bdfc0SManivannan Sadhasivam status = "disabled"; 1490e53bdfc0SManivannan Sadhasivam }; 1491e53bdfc0SManivannan Sadhasivam 1492e53bdfc0SManivannan Sadhasivam pcie2_phy: phy@1c16000 { 1493e53bdfc0SManivannan Sadhasivam compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 1494e53bdfc0SManivannan Sadhasivam reg = <0 0x1c16000 0 0x1c0>; 1495e53bdfc0SManivannan Sadhasivam #address-cells = <2>; 1496e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1497e53bdfc0SManivannan Sadhasivam ranges; 1498e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1499e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1500e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1501e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1502e53bdfc0SManivannan Sadhasivam clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1503e53bdfc0SManivannan Sadhasivam 1504e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_2_PHY_BCR>; 1505e53bdfc0SManivannan Sadhasivam reset-names = "phy"; 1506e53bdfc0SManivannan Sadhasivam 1507e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1508e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <100000000>; 1509e53bdfc0SManivannan Sadhasivam 1510e53bdfc0SManivannan Sadhasivam status = "disabled"; 1511e53bdfc0SManivannan Sadhasivam 1512e53bdfc0SManivannan Sadhasivam pcie2_lane: lanes@1c0e200 { 1513e53bdfc0SManivannan Sadhasivam reg = <0 0x1c16200 0 0x170>, /* tx0 */ 1514e53bdfc0SManivannan Sadhasivam <0 0x1c16400 0 0x200>, /* rx0 */ 1515e53bdfc0SManivannan Sadhasivam <0 0x1c16a00 0 0x1f0>, /* pcs */ 1516e53bdfc0SManivannan Sadhasivam <0 0x1c16600 0 0x170>, /* tx1 */ 1517e53bdfc0SManivannan Sadhasivam <0 0x1c16800 0 0x200>, /* rx1 */ 1518e53bdfc0SManivannan Sadhasivam <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1519e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 1520e53bdfc0SManivannan Sadhasivam clock-names = "pipe0"; 1521e53bdfc0SManivannan Sadhasivam 1522e53bdfc0SManivannan Sadhasivam #phy-cells = <0>; 1523e53bdfc0SManivannan Sadhasivam clock-output-names = "pcie_2_pipe_clk"; 1524e53bdfc0SManivannan Sadhasivam }; 1525e53bdfc0SManivannan Sadhasivam }; 1526e53bdfc0SManivannan Sadhasivam 15276b9afd8fSJonathan Marek ufs_mem_hc: ufshc@1d84000 { 1528b7e2fba0SBryan O'Donoghue compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 1529b7e2fba0SBryan O'Donoghue "jedec,ufs-2.0"; 1530b7e2fba0SBryan O'Donoghue reg = <0 0x01d84000 0 0x3000>; 1531b7e2fba0SBryan O'Donoghue interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1532b7e2fba0SBryan O'Donoghue phys = <&ufs_mem_phy_lanes>; 1533b7e2fba0SBryan O'Donoghue phy-names = "ufsphy"; 1534b7e2fba0SBryan O'Donoghue lanes-per-direction = <2>; 1535b7e2fba0SBryan O'Donoghue #reset-cells = <1>; 1536b7e2fba0SBryan O'Donoghue resets = <&gcc GCC_UFS_PHY_BCR>; 1537b7e2fba0SBryan O'Donoghue reset-names = "rst"; 1538b7e2fba0SBryan O'Donoghue 1539b7e2fba0SBryan O'Donoghue power-domains = <&gcc UFS_PHY_GDSC>; 1540b7e2fba0SBryan O'Donoghue 1541a89441fcSJonathan Marek iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 1542a89441fcSJonathan Marek 1543b7e2fba0SBryan O'Donoghue clock-names = 1544b7e2fba0SBryan O'Donoghue "core_clk", 1545b7e2fba0SBryan O'Donoghue "bus_aggr_clk", 1546b7e2fba0SBryan O'Donoghue "iface_clk", 1547b7e2fba0SBryan O'Donoghue "core_clk_unipro", 1548b7e2fba0SBryan O'Donoghue "ref_clk", 1549b7e2fba0SBryan O'Donoghue "tx_lane0_sync_clk", 1550b7e2fba0SBryan O'Donoghue "rx_lane0_sync_clk", 1551b7e2fba0SBryan O'Donoghue "rx_lane1_sync_clk"; 1552b7e2fba0SBryan O'Donoghue clocks = 1553b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_AXI_CLK>, 1554b7e2fba0SBryan O'Donoghue <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1555b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_AHB_CLK>, 1556b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1557b7e2fba0SBryan O'Donoghue <&rpmhcc RPMH_CXO_CLK>, 1558b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1559b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1560b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1561b7e2fba0SBryan O'Donoghue freq-table-hz = 1562b7e2fba0SBryan O'Donoghue <37500000 300000000>, 1563b7e2fba0SBryan O'Donoghue <0 0>, 1564b7e2fba0SBryan O'Donoghue <0 0>, 1565b7e2fba0SBryan O'Donoghue <37500000 300000000>, 1566b7e2fba0SBryan O'Donoghue <0 0>, 1567b7e2fba0SBryan O'Donoghue <0 0>, 1568b7e2fba0SBryan O'Donoghue <0 0>, 1569b7e2fba0SBryan O'Donoghue <0 0>; 1570b7e2fba0SBryan O'Donoghue 1571b7e2fba0SBryan O'Donoghue status = "disabled"; 1572b7e2fba0SBryan O'Donoghue }; 1573b7e2fba0SBryan O'Donoghue 1574b7e2fba0SBryan O'Donoghue ufs_mem_phy: phy@1d87000 { 1575b7e2fba0SBryan O'Donoghue compatible = "qcom,sm8250-qmp-ufs-phy"; 1576b7e2fba0SBryan O'Donoghue reg = <0 0x01d87000 0 0x1c0>; 1577b7e2fba0SBryan O'Donoghue #address-cells = <2>; 1578b7e2fba0SBryan O'Donoghue #size-cells = <2>; 1579b7e2fba0SBryan O'Donoghue ranges; 1580b7e2fba0SBryan O'Donoghue clock-names = "ref", 1581b7e2fba0SBryan O'Donoghue "ref_aux"; 1582b7e2fba0SBryan O'Donoghue clocks = <&rpmhcc RPMH_CXO_CLK>, 1583b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1584b7e2fba0SBryan O'Donoghue 1585b7e2fba0SBryan O'Donoghue resets = <&ufs_mem_hc 0>; 1586b7e2fba0SBryan O'Donoghue reset-names = "ufsphy"; 1587b7e2fba0SBryan O'Donoghue status = "disabled"; 1588b7e2fba0SBryan O'Donoghue 1589b7e2fba0SBryan O'Donoghue ufs_mem_phy_lanes: lanes@1d87400 { 1590b7e2fba0SBryan O'Donoghue reg = <0 0x01d87400 0 0x108>, 1591b7e2fba0SBryan O'Donoghue <0 0x01d87600 0 0x1e0>, 1592b7e2fba0SBryan O'Donoghue <0 0x01d87c00 0 0x1dc>, 1593b7e2fba0SBryan O'Donoghue <0 0x01d87800 0 0x108>, 1594b7e2fba0SBryan O'Donoghue <0 0x01d87a00 0 0x1e0>; 1595b7e2fba0SBryan O'Donoghue #phy-cells = <0>; 1596b7e2fba0SBryan O'Donoghue }; 1597b7e2fba0SBryan O'Donoghue }; 1598b7e2fba0SBryan O'Donoghue 1599e7e41a20SJonathan Marek ipa_virt: interconnect@1e00000 { 1600e7e41a20SJonathan Marek compatible = "qcom,sm8250-ipa-virt"; 1601e7e41a20SJonathan Marek reg = <0 0x01e00000 0 0x1000>; 1602e7e41a20SJonathan Marek #interconnect-cells = <1>; 1603e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1604e7e41a20SJonathan Marek }; 1605e7e41a20SJonathan Marek 1606dff0f49cSBjorn Andersson tcsr_mutex: hwlock@1f40000 { 1607dff0f49cSBjorn Andersson compatible = "qcom,tcsr-mutex"; 1608b9ec8cbcSJonathan Marek reg = <0x0 0x01f40000 0x0 0x40000>; 1609dff0f49cSBjorn Andersson #hwlock-cells = <1>; 161060378f1aSVenkata Narendra Kumar Gutta }; 161160378f1aSVenkata Narendra Kumar Gutta 1612768270caSSrinivas Kandagatla wsamacro: codec@3240000 { 1613768270caSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-wsa-macro"; 1614768270caSSrinivas Kandagatla reg = <0 0x03240000 0 0x1000>; 1615768270caSSrinivas Kandagatla clocks = <&audiocc 1>, 1616768270caSSrinivas Kandagatla <&audiocc 0>, 1617768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1618768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1619768270caSSrinivas Kandagatla <&aoncc 0>, 1620768270caSSrinivas Kandagatla <&vamacro>; 1621768270caSSrinivas Kandagatla 1622768270caSSrinivas Kandagatla clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 1623768270caSSrinivas Kandagatla 1624768270caSSrinivas Kandagatla #clock-cells = <0>; 1625768270caSSrinivas Kandagatla clock-frequency = <9600000>; 1626768270caSSrinivas Kandagatla clock-output-names = "mclk"; 1627768270caSSrinivas Kandagatla #sound-dai-cells = <1>; 1628768270caSSrinivas Kandagatla 1629768270caSSrinivas Kandagatla pinctrl-names = "default"; 1630768270caSSrinivas Kandagatla pinctrl-0 = <&wsa_swr_active>; 1631768270caSSrinivas Kandagatla }; 1632768270caSSrinivas Kandagatla 1633768270caSSrinivas Kandagatla swr0: soundwire-controller@3250000 { 1634768270caSSrinivas Kandagatla reg = <0 0x03250000 0 0x2000>; 1635768270caSSrinivas Kandagatla compatible = "qcom,soundwire-v1.5.1"; 1636768270caSSrinivas Kandagatla interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1637768270caSSrinivas Kandagatla clocks = <&wsamacro>; 1638768270caSSrinivas Kandagatla clock-names = "iface"; 1639768270caSSrinivas Kandagatla 1640768270caSSrinivas Kandagatla qcom,din-ports = <2>; 1641768270caSSrinivas Kandagatla qcom,dout-ports = <6>; 1642768270caSSrinivas Kandagatla 1643768270caSSrinivas Kandagatla qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 1644768270caSSrinivas Kandagatla qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 1645768270caSSrinivas Kandagatla qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 1646768270caSSrinivas Kandagatla qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 1647768270caSSrinivas Kandagatla 1648768270caSSrinivas Kandagatla #sound-dai-cells = <1>; 1649768270caSSrinivas Kandagatla #address-cells = <2>; 1650768270caSSrinivas Kandagatla #size-cells = <0>; 1651768270caSSrinivas Kandagatla }; 1652768270caSSrinivas Kandagatla 1653793bbd2dSSrinivas Kandagatla audiocc: clock-controller@3300000 { 1654793bbd2dSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-audiocc"; 1655793bbd2dSSrinivas Kandagatla reg = <0 0x03300000 0 0x30000>; 1656793bbd2dSSrinivas Kandagatla #clock-cells = <1>; 1657793bbd2dSSrinivas Kandagatla clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1658793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1659793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1660793bbd2dSSrinivas Kandagatla clock-names = "core", "audio", "bus"; 1661793bbd2dSSrinivas Kandagatla }; 1662793bbd2dSSrinivas Kandagatla 1663768270caSSrinivas Kandagatla vamacro: codec@3370000 { 1664768270caSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-va-macro"; 1665768270caSSrinivas Kandagatla reg = <0 0x03370000 0 0x1000>; 1666768270caSSrinivas Kandagatla clocks = <&aoncc 0>, 1667768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1668768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1669768270caSSrinivas Kandagatla 1670768270caSSrinivas Kandagatla clock-names = "mclk", "macro", "dcodec"; 1671768270caSSrinivas Kandagatla 1672768270caSSrinivas Kandagatla #clock-cells = <0>; 1673768270caSSrinivas Kandagatla clock-frequency = <9600000>; 1674768270caSSrinivas Kandagatla clock-output-names = "fsgen"; 1675768270caSSrinivas Kandagatla #sound-dai-cells = <1>; 1676768270caSSrinivas Kandagatla }; 1677768270caSSrinivas Kandagatla 1678793bbd2dSSrinivas Kandagatla aoncc: clock-controller@3380000 { 1679793bbd2dSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-aoncc"; 1680793bbd2dSSrinivas Kandagatla reg = <0 0x03380000 0 0x40000>; 1681793bbd2dSSrinivas Kandagatla #clock-cells = <1>; 1682793bbd2dSSrinivas Kandagatla clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1683793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1684793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1685793bbd2dSSrinivas Kandagatla clock-names = "core", "audio", "bus"; 1686793bbd2dSSrinivas Kandagatla }; 1687793bbd2dSSrinivas Kandagatla 16883160c1b8SSrinivas Kandagatla lpass_tlmm: pinctrl@33c0000{ 16893160c1b8SSrinivas Kandagatla compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 16903160c1b8SSrinivas Kandagatla reg = <0 0x033c0000 0x0 0x20000>, 16913160c1b8SSrinivas Kandagatla <0 0x03550000 0x0 0x10000>; 16923160c1b8SSrinivas Kandagatla gpio-controller; 16933160c1b8SSrinivas Kandagatla #gpio-cells = <2>; 16943160c1b8SSrinivas Kandagatla gpio-ranges = <&lpass_tlmm 0 0 14>; 16953160c1b8SSrinivas Kandagatla 16963160c1b8SSrinivas Kandagatla clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 16973160c1b8SSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 16983160c1b8SSrinivas Kandagatla clock-names = "core", "audio"; 16993160c1b8SSrinivas Kandagatla 17003160c1b8SSrinivas Kandagatla wsa_swr_active: wsa-swr-active-pins { 17013160c1b8SSrinivas Kandagatla clk { 17023160c1b8SSrinivas Kandagatla pins = "gpio10"; 17033160c1b8SSrinivas Kandagatla function = "wsa_swr_clk"; 17043160c1b8SSrinivas Kandagatla drive-strength = <2>; 17053160c1b8SSrinivas Kandagatla slew-rate = <1>; 17063160c1b8SSrinivas Kandagatla bias-disable; 17073160c1b8SSrinivas Kandagatla }; 17083160c1b8SSrinivas Kandagatla 17093160c1b8SSrinivas Kandagatla data { 17103160c1b8SSrinivas Kandagatla pins = "gpio11"; 17113160c1b8SSrinivas Kandagatla function = "wsa_swr_data"; 17123160c1b8SSrinivas Kandagatla drive-strength = <2>; 17133160c1b8SSrinivas Kandagatla slew-rate = <1>; 17143160c1b8SSrinivas Kandagatla bias-bus-hold; 17153160c1b8SSrinivas Kandagatla 17163160c1b8SSrinivas Kandagatla }; 17173160c1b8SSrinivas Kandagatla }; 17183160c1b8SSrinivas Kandagatla 17193160c1b8SSrinivas Kandagatla wsa_swr_sleep: wsa-swr-sleep-pins { 17203160c1b8SSrinivas Kandagatla clk { 17213160c1b8SSrinivas Kandagatla pins = "gpio10"; 17223160c1b8SSrinivas Kandagatla function = "wsa_swr_clk"; 17233160c1b8SSrinivas Kandagatla drive-strength = <2>; 17243160c1b8SSrinivas Kandagatla input-enable; 17253160c1b8SSrinivas Kandagatla bias-pull-down; 17263160c1b8SSrinivas Kandagatla }; 17273160c1b8SSrinivas Kandagatla 17283160c1b8SSrinivas Kandagatla data { 17293160c1b8SSrinivas Kandagatla pins = "gpio11"; 17303160c1b8SSrinivas Kandagatla function = "wsa_swr_data"; 17313160c1b8SSrinivas Kandagatla drive-strength = <2>; 17323160c1b8SSrinivas Kandagatla input-enable; 17333160c1b8SSrinivas Kandagatla bias-pull-down; 17343160c1b8SSrinivas Kandagatla 17353160c1b8SSrinivas Kandagatla }; 17363160c1b8SSrinivas Kandagatla }; 17373160c1b8SSrinivas Kandagatla 17383160c1b8SSrinivas Kandagatla dmic01_active: dmic01-active-pins { 17393160c1b8SSrinivas Kandagatla clk { 17403160c1b8SSrinivas Kandagatla pins = "gpio6"; 17413160c1b8SSrinivas Kandagatla function = "dmic1_clk"; 17423160c1b8SSrinivas Kandagatla drive-strength = <8>; 17433160c1b8SSrinivas Kandagatla output-high; 17443160c1b8SSrinivas Kandagatla }; 17453160c1b8SSrinivas Kandagatla data { 17463160c1b8SSrinivas Kandagatla pins = "gpio7"; 17473160c1b8SSrinivas Kandagatla function = "dmic1_data"; 17483160c1b8SSrinivas Kandagatla drive-strength = <8>; 17493160c1b8SSrinivas Kandagatla input-enable; 17503160c1b8SSrinivas Kandagatla }; 17513160c1b8SSrinivas Kandagatla }; 17523160c1b8SSrinivas Kandagatla 17533160c1b8SSrinivas Kandagatla dmic01_sleep: dmic01-sleep-pins { 17543160c1b8SSrinivas Kandagatla clk { 17553160c1b8SSrinivas Kandagatla pins = "gpio6"; 17563160c1b8SSrinivas Kandagatla function = "dmic1_clk"; 17573160c1b8SSrinivas Kandagatla drive-strength = <2>; 17583160c1b8SSrinivas Kandagatla bias-disable; 17593160c1b8SSrinivas Kandagatla output-low; 17603160c1b8SSrinivas Kandagatla }; 17613160c1b8SSrinivas Kandagatla 17623160c1b8SSrinivas Kandagatla data { 17633160c1b8SSrinivas Kandagatla pins = "gpio7"; 17643160c1b8SSrinivas Kandagatla function = "dmic1_data"; 17653160c1b8SSrinivas Kandagatla drive-strength = <2>; 17663160c1b8SSrinivas Kandagatla pull-down; 17673160c1b8SSrinivas Kandagatla input-enable; 17683160c1b8SSrinivas Kandagatla }; 17693160c1b8SSrinivas Kandagatla }; 17703160c1b8SSrinivas Kandagatla }; 17713160c1b8SSrinivas Kandagatla 177204a3605bSJonathan Marek gpu: gpu@3d00000 { 177304a3605bSJonathan Marek compatible = "qcom,adreno-650.2", 17747c1dffd4SDmitry Baryshkov "qcom,adreno"; 177504a3605bSJonathan Marek #stream-id-cells = <16>; 177604a3605bSJonathan Marek 177704a3605bSJonathan Marek reg = <0 0x03d00000 0 0x40000>; 177804a3605bSJonathan Marek reg-names = "kgsl_3d0_reg_memory"; 177904a3605bSJonathan Marek 178004a3605bSJonathan Marek interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 178104a3605bSJonathan Marek 178204a3605bSJonathan Marek iommus = <&adreno_smmu 0 0x401>; 178304a3605bSJonathan Marek 178404a3605bSJonathan Marek operating-points-v2 = <&gpu_opp_table>; 178504a3605bSJonathan Marek 178604a3605bSJonathan Marek qcom,gmu = <&gmu>; 178704a3605bSJonathan Marek 178804a3605bSJonathan Marek zap-shader { 178904a3605bSJonathan Marek memory-region = <&gpu_mem>; 179004a3605bSJonathan Marek }; 179104a3605bSJonathan Marek 179204a3605bSJonathan Marek /* note: downstream checks gpu binning for 670 Mhz */ 179304a3605bSJonathan Marek gpu_opp_table: opp-table { 179404a3605bSJonathan Marek compatible = "operating-points-v2"; 179504a3605bSJonathan Marek 179604a3605bSJonathan Marek opp-670000000 { 179704a3605bSJonathan Marek opp-hz = /bits/ 64 <670000000>; 179804a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 179904a3605bSJonathan Marek }; 180004a3605bSJonathan Marek 180104a3605bSJonathan Marek opp-587000000 { 180204a3605bSJonathan Marek opp-hz = /bits/ 64 <587000000>; 180304a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 180404a3605bSJonathan Marek }; 180504a3605bSJonathan Marek 180604a3605bSJonathan Marek opp-525000000 { 180704a3605bSJonathan Marek opp-hz = /bits/ 64 <525000000>; 180804a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 180904a3605bSJonathan Marek }; 181004a3605bSJonathan Marek 181104a3605bSJonathan Marek opp-490000000 { 181204a3605bSJonathan Marek opp-hz = /bits/ 64 <490000000>; 181304a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 181404a3605bSJonathan Marek }; 181504a3605bSJonathan Marek 181604a3605bSJonathan Marek opp-441600000 { 181704a3605bSJonathan Marek opp-hz = /bits/ 64 <441600000>; 181804a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 181904a3605bSJonathan Marek }; 182004a3605bSJonathan Marek 182104a3605bSJonathan Marek opp-400000000 { 182204a3605bSJonathan Marek opp-hz = /bits/ 64 <400000000>; 182304a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 182404a3605bSJonathan Marek }; 182504a3605bSJonathan Marek 182604a3605bSJonathan Marek opp-305000000 { 182704a3605bSJonathan Marek opp-hz = /bits/ 64 <305000000>; 182804a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 182904a3605bSJonathan Marek }; 183004a3605bSJonathan Marek }; 183104a3605bSJonathan Marek }; 183204a3605bSJonathan Marek 183304a3605bSJonathan Marek gmu: gmu@3d6a000 { 183404a3605bSJonathan Marek compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 183504a3605bSJonathan Marek 183604a3605bSJonathan Marek reg = <0 0x03d6a000 0 0x30000>, 183704a3605bSJonathan Marek <0 0x3de0000 0 0x10000>, 183804a3605bSJonathan Marek <0 0xb290000 0 0x10000>, 183904a3605bSJonathan Marek <0 0xb490000 0 0x10000>; 184004a3605bSJonathan Marek reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 184104a3605bSJonathan Marek 184204a3605bSJonathan Marek interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 184304a3605bSJonathan Marek <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 184404a3605bSJonathan Marek interrupt-names = "hfi", "gmu"; 184504a3605bSJonathan Marek 18460e6aa9dbSJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 18470e6aa9dbSJonathan Marek <&gpucc GPU_CC_CX_GMU_CLK>, 18480e6aa9dbSJonathan Marek <&gpucc GPU_CC_CXO_CLK>, 184904a3605bSJonathan Marek <&gcc GCC_DDRSS_GPU_AXI_CLK>, 185004a3605bSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 185104a3605bSJonathan Marek clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 185204a3605bSJonathan Marek 18530e6aa9dbSJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>, 18540e6aa9dbSJonathan Marek <&gpucc GPU_GX_GDSC>; 185504a3605bSJonathan Marek power-domain-names = "cx", "gx"; 185604a3605bSJonathan Marek 185704a3605bSJonathan Marek iommus = <&adreno_smmu 5 0x400>; 185804a3605bSJonathan Marek 185904a3605bSJonathan Marek operating-points-v2 = <&gmu_opp_table>; 186004a3605bSJonathan Marek 186104a3605bSJonathan Marek gmu_opp_table: opp-table { 186204a3605bSJonathan Marek compatible = "operating-points-v2"; 186304a3605bSJonathan Marek 186404a3605bSJonathan Marek opp-200000000 { 186504a3605bSJonathan Marek opp-hz = /bits/ 64 <200000000>; 186604a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 186704a3605bSJonathan Marek }; 186804a3605bSJonathan Marek }; 186904a3605bSJonathan Marek }; 187004a3605bSJonathan Marek 187104a3605bSJonathan Marek gpucc: clock-controller@3d90000 { 187204a3605bSJonathan Marek compatible = "qcom,sm8250-gpucc"; 187304a3605bSJonathan Marek reg = <0 0x03d90000 0 0x9000>; 187404a3605bSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>, 187504a3605bSJonathan Marek <&gcc GCC_GPU_GPLL0_CLK_SRC>, 187604a3605bSJonathan Marek <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 187704a3605bSJonathan Marek clock-names = "bi_tcxo", 187804a3605bSJonathan Marek "gcc_gpu_gpll0_clk_src", 187904a3605bSJonathan Marek "gcc_gpu_gpll0_div_clk_src"; 188004a3605bSJonathan Marek #clock-cells = <1>; 188104a3605bSJonathan Marek #reset-cells = <1>; 188204a3605bSJonathan Marek #power-domain-cells = <1>; 188304a3605bSJonathan Marek }; 188404a3605bSJonathan Marek 188504a3605bSJonathan Marek adreno_smmu: iommu@3da0000 { 188604a3605bSJonathan Marek compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 188704a3605bSJonathan Marek reg = <0 0x03da0000 0 0x10000>; 188804a3605bSJonathan Marek #iommu-cells = <2>; 188904a3605bSJonathan Marek #global-interrupts = <2>; 189004a3605bSJonathan Marek interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 189104a3605bSJonathan Marek <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 189204a3605bSJonathan Marek <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 189304a3605bSJonathan Marek <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 189404a3605bSJonathan Marek <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 189504a3605bSJonathan Marek <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 189604a3605bSJonathan Marek <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 189704a3605bSJonathan Marek <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 189804a3605bSJonathan Marek <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 189904a3605bSJonathan Marek <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 19000e6aa9dbSJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 190104a3605bSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 190204a3605bSJonathan Marek <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 190304a3605bSJonathan Marek clock-names = "ahb", "bus", "iface"; 190404a3605bSJonathan Marek 19050e6aa9dbSJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>; 190604a3605bSJonathan Marek }; 190704a3605bSJonathan Marek 190823a89037SBjorn Andersson slpi: remoteproc@5c00000 { 190923a89037SBjorn Andersson compatible = "qcom,sm8250-slpi-pas"; 191023a89037SBjorn Andersson reg = <0 0x05c00000 0 0x4000>; 191123a89037SBjorn Andersson 191223a89037SBjorn Andersson interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 191323a89037SBjorn Andersson <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 191423a89037SBjorn Andersson <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 191523a89037SBjorn Andersson <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 191623a89037SBjorn Andersson <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 191723a89037SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 191823a89037SBjorn Andersson "handover", "stop-ack"; 191923a89037SBjorn Andersson 192023a89037SBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>; 192123a89037SBjorn Andersson clock-names = "xo"; 192223a89037SBjorn Andersson 192323a89037SBjorn Andersson power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, 192423a89037SBjorn Andersson <&rpmhpd SM8250_LCX>, 192523a89037SBjorn Andersson <&rpmhpd SM8250_LMX>; 192623a89037SBjorn Andersson power-domain-names = "load_state", "lcx", "lmx"; 192723a89037SBjorn Andersson 192823a89037SBjorn Andersson memory-region = <&slpi_mem>; 192923a89037SBjorn Andersson 193023a89037SBjorn Andersson qcom,smem-states = <&smp2p_slpi_out 0>; 193123a89037SBjorn Andersson qcom,smem-state-names = "stop"; 193223a89037SBjorn Andersson 193323a89037SBjorn Andersson status = "disabled"; 193423a89037SBjorn Andersson 193523a89037SBjorn Andersson glink-edge { 193623a89037SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 193723a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 193823a89037SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 193923a89037SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_SLPI 194023a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 194123a89037SBjorn Andersson 194225695808SJonathan Marek label = "slpi"; 194323a89037SBjorn Andersson qcom,remote-pid = <3>; 194425695808SJonathan Marek 194525695808SJonathan Marek fastrpc { 194625695808SJonathan Marek compatible = "qcom,fastrpc"; 194725695808SJonathan Marek qcom,glink-channels = "fastrpcglink-apps-dsp"; 194825695808SJonathan Marek label = "sdsp"; 194925695808SJonathan Marek #address-cells = <1>; 195025695808SJonathan Marek #size-cells = <0>; 195125695808SJonathan Marek 195225695808SJonathan Marek compute-cb@1 { 195325695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 195425695808SJonathan Marek reg = <1>; 195525695808SJonathan Marek iommus = <&apps_smmu 0x0541 0x0>; 195625695808SJonathan Marek }; 195725695808SJonathan Marek 195825695808SJonathan Marek compute-cb@2 { 195925695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 196025695808SJonathan Marek reg = <2>; 196125695808SJonathan Marek iommus = <&apps_smmu 0x0542 0x0>; 196225695808SJonathan Marek }; 196325695808SJonathan Marek 196425695808SJonathan Marek compute-cb@3 { 196525695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 196625695808SJonathan Marek reg = <3>; 196725695808SJonathan Marek iommus = <&apps_smmu 0x0543 0x0>; 196825695808SJonathan Marek /* note: shared-cb = <4> in downstream */ 196925695808SJonathan Marek }; 197025695808SJonathan Marek }; 197123a89037SBjorn Andersson }; 197223a89037SBjorn Andersson }; 197323a89037SBjorn Andersson 197423a89037SBjorn Andersson cdsp: remoteproc@8300000 { 197523a89037SBjorn Andersson compatible = "qcom,sm8250-cdsp-pas"; 197623a89037SBjorn Andersson reg = <0 0x08300000 0 0x10000>; 197723a89037SBjorn Andersson 197823a89037SBjorn Andersson interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 197923a89037SBjorn Andersson <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 198023a89037SBjorn Andersson <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 198123a89037SBjorn Andersson <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 198223a89037SBjorn Andersson <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 198323a89037SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 198423a89037SBjorn Andersson "handover", "stop-ack"; 198523a89037SBjorn Andersson 198623a89037SBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>; 198723a89037SBjorn Andersson clock-names = "xo"; 198823a89037SBjorn Andersson 198923a89037SBjorn Andersson power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, 199023a89037SBjorn Andersson <&rpmhpd SM8250_CX>; 199123a89037SBjorn Andersson power-domain-names = "load_state", "cx"; 199223a89037SBjorn Andersson 199323a89037SBjorn Andersson memory-region = <&cdsp_mem>; 199423a89037SBjorn Andersson 199523a89037SBjorn Andersson qcom,smem-states = <&smp2p_cdsp_out 0>; 199623a89037SBjorn Andersson qcom,smem-state-names = "stop"; 199723a89037SBjorn Andersson 199823a89037SBjorn Andersson status = "disabled"; 199923a89037SBjorn Andersson 200023a89037SBjorn Andersson glink-edge { 200123a89037SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 200223a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 200323a89037SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 200423a89037SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_CDSP 200523a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 200623a89037SBjorn Andersson 200725695808SJonathan Marek label = "cdsp"; 200823a89037SBjorn Andersson qcom,remote-pid = <5>; 200925695808SJonathan Marek 201025695808SJonathan Marek fastrpc { 201125695808SJonathan Marek compatible = "qcom,fastrpc"; 201225695808SJonathan Marek qcom,glink-channels = "fastrpcglink-apps-dsp"; 201325695808SJonathan Marek label = "cdsp"; 201425695808SJonathan Marek #address-cells = <1>; 201525695808SJonathan Marek #size-cells = <0>; 201625695808SJonathan Marek 201725695808SJonathan Marek compute-cb@1 { 201825695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 201925695808SJonathan Marek reg = <1>; 202025695808SJonathan Marek iommus = <&apps_smmu 0x1001 0x0460>; 202125695808SJonathan Marek }; 202225695808SJonathan Marek 202325695808SJonathan Marek compute-cb@2 { 202425695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 202525695808SJonathan Marek reg = <2>; 202625695808SJonathan Marek iommus = <&apps_smmu 0x1002 0x0460>; 202725695808SJonathan Marek }; 202825695808SJonathan Marek 202925695808SJonathan Marek compute-cb@3 { 203025695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 203125695808SJonathan Marek reg = <3>; 203225695808SJonathan Marek iommus = <&apps_smmu 0x1003 0x0460>; 203325695808SJonathan Marek }; 203425695808SJonathan Marek 203525695808SJonathan Marek compute-cb@4 { 203625695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 203725695808SJonathan Marek reg = <4>; 203825695808SJonathan Marek iommus = <&apps_smmu 0x1004 0x0460>; 203925695808SJonathan Marek }; 204025695808SJonathan Marek 204125695808SJonathan Marek compute-cb@5 { 204225695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 204325695808SJonathan Marek reg = <5>; 204425695808SJonathan Marek iommus = <&apps_smmu 0x1005 0x0460>; 204525695808SJonathan Marek }; 204625695808SJonathan Marek 204725695808SJonathan Marek compute-cb@6 { 204825695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 204925695808SJonathan Marek reg = <6>; 205025695808SJonathan Marek iommus = <&apps_smmu 0x1006 0x0460>; 205125695808SJonathan Marek }; 205225695808SJonathan Marek 205325695808SJonathan Marek compute-cb@7 { 205425695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 205525695808SJonathan Marek reg = <7>; 205625695808SJonathan Marek iommus = <&apps_smmu 0x1007 0x0460>; 205725695808SJonathan Marek }; 205825695808SJonathan Marek 205925695808SJonathan Marek compute-cb@8 { 206025695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 206125695808SJonathan Marek reg = <8>; 206225695808SJonathan Marek iommus = <&apps_smmu 0x1008 0x0460>; 206325695808SJonathan Marek }; 206425695808SJonathan Marek 206525695808SJonathan Marek /* note: secure cb9 in downstream */ 206625695808SJonathan Marek }; 206723a89037SBjorn Andersson }; 206823a89037SBjorn Andersson }; 206923a89037SBjorn Andersson 2070590a135eSSrinivas Kandagatla sound: sound { 2071590a135eSSrinivas Kandagatla }; 2072590a135eSSrinivas Kandagatla 207346a6f297SJonathan Marek usb_1_hsphy: phy@88e3000 { 207446a6f297SJonathan Marek compatible = "qcom,sm8250-usb-hs-phy", 207546a6f297SJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 207646a6f297SJonathan Marek reg = <0 0x088e3000 0 0x400>; 207746a6f297SJonathan Marek status = "disabled"; 207846a6f297SJonathan Marek #phy-cells = <0>; 207946a6f297SJonathan Marek 208046a6f297SJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 208146a6f297SJonathan Marek clock-names = "ref"; 208246a6f297SJonathan Marek 208346a6f297SJonathan Marek resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 208446a6f297SJonathan Marek }; 208546a6f297SJonathan Marek 208646a6f297SJonathan Marek usb_2_hsphy: phy@88e4000 { 208746a6f297SJonathan Marek compatible = "qcom,sm8250-usb-hs-phy", 208846a6f297SJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 208946a6f297SJonathan Marek reg = <0 0x088e4000 0 0x400>; 209046a6f297SJonathan Marek status = "disabled"; 209146a6f297SJonathan Marek #phy-cells = <0>; 209246a6f297SJonathan Marek 209346a6f297SJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 209446a6f297SJonathan Marek clock-names = "ref"; 209546a6f297SJonathan Marek 209646a6f297SJonathan Marek resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 209746a6f297SJonathan Marek }; 209846a6f297SJonathan Marek 209946a6f297SJonathan Marek usb_1_qmpphy: phy@88e9000 { 210046a6f297SJonathan Marek compatible = "qcom,sm8250-qmp-usb3-phy"; 210146a6f297SJonathan Marek reg = <0 0x088e9000 0 0x200>, 210246a6f297SJonathan Marek <0 0x088e8000 0 0x20>; 210346a6f297SJonathan Marek reg-names = "reg-base", "dp_com"; 210446a6f297SJonathan Marek status = "disabled"; 210546a6f297SJonathan Marek #clock-cells = <1>; 210646a6f297SJonathan Marek #address-cells = <2>; 210746a6f297SJonathan Marek #size-cells = <2>; 210846a6f297SJonathan Marek ranges; 210946a6f297SJonathan Marek 211046a6f297SJonathan Marek clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 211146a6f297SJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 211246a6f297SJonathan Marek <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 211346a6f297SJonathan Marek clock-names = "aux", "ref_clk_src", "com_aux"; 211446a6f297SJonathan Marek 211546a6f297SJonathan Marek resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 211646a6f297SJonathan Marek <&gcc GCC_USB3_PHY_PRIM_BCR>; 211746a6f297SJonathan Marek reset-names = "phy", "common"; 211846a6f297SJonathan Marek 211946a6f297SJonathan Marek usb_1_ssphy: lanes@88e9200 { 212046a6f297SJonathan Marek reg = <0 0x088e9200 0 0x200>, 212146a6f297SJonathan Marek <0 0x088e9400 0 0x200>, 212246a6f297SJonathan Marek <0 0x088e9c00 0 0x400>, 212346a6f297SJonathan Marek <0 0x088e9600 0 0x200>, 212446a6f297SJonathan Marek <0 0x088e9800 0 0x200>, 212546a6f297SJonathan Marek <0 0x088e9a00 0 0x100>; 212646a6f297SJonathan Marek #phy-cells = <0>; 212746a6f297SJonathan Marek clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 212846a6f297SJonathan Marek clock-names = "pipe0"; 212946a6f297SJonathan Marek clock-output-names = "usb3_phy_pipe_clk_src"; 213046a6f297SJonathan Marek }; 213146a6f297SJonathan Marek }; 213246a6f297SJonathan Marek 213346a6f297SJonathan Marek usb_2_qmpphy: phy@88eb000 { 213446a6f297SJonathan Marek compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 213546a6f297SJonathan Marek reg = <0 0x088eb000 0 0x200>; 213646a6f297SJonathan Marek status = "disabled"; 213746a6f297SJonathan Marek #clock-cells = <1>; 213846a6f297SJonathan Marek #address-cells = <2>; 213946a6f297SJonathan Marek #size-cells = <2>; 214046a6f297SJonathan Marek ranges; 214146a6f297SJonathan Marek 214246a6f297SJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 214346a6f297SJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 214446a6f297SJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_EN>, 214546a6f297SJonathan Marek <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 214646a6f297SJonathan Marek clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 214746a6f297SJonathan Marek 214846a6f297SJonathan Marek resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 214946a6f297SJonathan Marek <&gcc GCC_USB3_PHY_SEC_BCR>; 215046a6f297SJonathan Marek reset-names = "phy", "common"; 215146a6f297SJonathan Marek 215246a6f297SJonathan Marek usb_2_ssphy: lane@88eb200 { 215346a6f297SJonathan Marek reg = <0 0x088eb200 0 0x200>, 215446a6f297SJonathan Marek <0 0x088eb400 0 0x200>, 215546a6f297SJonathan Marek <0 0x088eb800 0 0x800>; 215646a6f297SJonathan Marek #phy-cells = <0>; 215746a6f297SJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 215846a6f297SJonathan Marek clock-names = "pipe0"; 215946a6f297SJonathan Marek clock-output-names = "usb3_uni_phy_pipe_clk_src"; 216046a6f297SJonathan Marek }; 216146a6f297SJonathan Marek }; 216246a6f297SJonathan Marek 2163c4cf0300SManivannan Sadhasivam sdhc_2: sdhci@8804000 { 2164c4cf0300SManivannan Sadhasivam compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 2165c4cf0300SManivannan Sadhasivam reg = <0 0x08804000 0 0x1000>; 2166c4cf0300SManivannan Sadhasivam 2167c4cf0300SManivannan Sadhasivam interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2168c4cf0300SManivannan Sadhasivam <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2169c4cf0300SManivannan Sadhasivam interrupt-names = "hc_irq", "pwr_irq"; 2170c4cf0300SManivannan Sadhasivam 2171c4cf0300SManivannan Sadhasivam clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2172c4cf0300SManivannan Sadhasivam <&gcc GCC_SDCC2_APPS_CLK>, 217374097d80SDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK>; 2174c4cf0300SManivannan Sadhasivam clock-names = "iface", "core", "xo"; 2175c4cf0300SManivannan Sadhasivam iommus = <&apps_smmu 0x4a0 0x0>; 2176c4cf0300SManivannan Sadhasivam qcom,dll-config = <0x0007642c>; 2177c4cf0300SManivannan Sadhasivam qcom,ddr-config = <0x80040868>; 2178c4cf0300SManivannan Sadhasivam power-domains = <&rpmhpd SM8250_CX>; 2179c4cf0300SManivannan Sadhasivam operating-points-v2 = <&sdhc2_opp_table>; 2180c4cf0300SManivannan Sadhasivam 2181c4cf0300SManivannan Sadhasivam status = "disabled"; 2182c4cf0300SManivannan Sadhasivam 2183c4cf0300SManivannan Sadhasivam sdhc2_opp_table: sdhc2-opp-table { 2184c4cf0300SManivannan Sadhasivam compatible = "operating-points-v2"; 2185c4cf0300SManivannan Sadhasivam 2186c4cf0300SManivannan Sadhasivam opp-19200000 { 2187c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <19200000>; 2188c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_min_svs>; 2189c4cf0300SManivannan Sadhasivam }; 2190c4cf0300SManivannan Sadhasivam 2191c4cf0300SManivannan Sadhasivam opp-50000000 { 2192c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <50000000>; 2193c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_low_svs>; 2194c4cf0300SManivannan Sadhasivam }; 2195c4cf0300SManivannan Sadhasivam 2196c4cf0300SManivannan Sadhasivam opp-100000000 { 2197c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <100000000>; 2198c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_svs>; 2199c4cf0300SManivannan Sadhasivam }; 2200c4cf0300SManivannan Sadhasivam 2201c4cf0300SManivannan Sadhasivam opp-202000000 { 2202c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <202000000>; 2203c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_svs_l1>; 2204c4cf0300SManivannan Sadhasivam }; 2205c4cf0300SManivannan Sadhasivam }; 2206c4cf0300SManivannan Sadhasivam }; 2207c4cf0300SManivannan Sadhasivam 2208e7e41a20SJonathan Marek dc_noc: interconnect@90c0000 { 2209e7e41a20SJonathan Marek compatible = "qcom,sm8250-dc-noc"; 2210e7e41a20SJonathan Marek reg = <0 0x090c0000 0 0x4200>; 2211e7e41a20SJonathan Marek #interconnect-cells = <1>; 2212e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 2213e7e41a20SJonathan Marek }; 2214e7e41a20SJonathan Marek 2215e7e41a20SJonathan Marek gem_noc: interconnect@9100000 { 2216e7e41a20SJonathan Marek compatible = "qcom,sm8250-gem-noc"; 2217e7e41a20SJonathan Marek reg = <0 0x09100000 0 0xb4000>; 2218e7e41a20SJonathan Marek #interconnect-cells = <1>; 2219e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 2220e7e41a20SJonathan Marek }; 2221e7e41a20SJonathan Marek 2222e7e41a20SJonathan Marek npu_noc: interconnect@9990000 { 2223e7e41a20SJonathan Marek compatible = "qcom,sm8250-npu-noc"; 2224e7e41a20SJonathan Marek reg = <0 0x09990000 0 0x1600>; 2225e7e41a20SJonathan Marek #interconnect-cells = <1>; 2226e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 2227e7e41a20SJonathan Marek }; 2228e7e41a20SJonathan Marek 222946a6f297SJonathan Marek usb_1: usb@a6f8800 { 223046a6f297SJonathan Marek compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 223146a6f297SJonathan Marek reg = <0 0x0a6f8800 0 0x400>; 223246a6f297SJonathan Marek status = "disabled"; 223346a6f297SJonathan Marek #address-cells = <2>; 223446a6f297SJonathan Marek #size-cells = <2>; 223546a6f297SJonathan Marek ranges; 223646a6f297SJonathan Marek dma-ranges; 223746a6f297SJonathan Marek 223846a6f297SJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 223946a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_MASTER_CLK>, 224046a6f297SJonathan Marek <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 224146a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 224246a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 224346a6f297SJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_EN>; 224446a6f297SJonathan Marek clock-names = "cfg_noc", "core", "iface", "mock_utmi", 224546a6f297SJonathan Marek "sleep", "xo"; 224646a6f297SJonathan Marek 224746a6f297SJonathan Marek assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 224846a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_MASTER_CLK>; 224946a6f297SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 225046a6f297SJonathan Marek 225146a6f297SJonathan Marek interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 225246a6f297SJonathan Marek <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 225346a6f297SJonathan Marek <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 225446a6f297SJonathan Marek <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 225546a6f297SJonathan Marek interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 225646a6f297SJonathan Marek "dm_hs_phy_irq", "ss_phy_irq"; 225746a6f297SJonathan Marek 225846a6f297SJonathan Marek power-domains = <&gcc USB30_PRIM_GDSC>; 225946a6f297SJonathan Marek 226046a6f297SJonathan Marek resets = <&gcc GCC_USB30_PRIM_BCR>; 226146a6f297SJonathan Marek 226246a6f297SJonathan Marek usb_1_dwc3: dwc3@a600000 { 226346a6f297SJonathan Marek compatible = "snps,dwc3"; 226446a6f297SJonathan Marek reg = <0 0x0a600000 0 0xcd00>; 226546a6f297SJonathan Marek interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 226646a6f297SJonathan Marek iommus = <&apps_smmu 0x0 0x0>; 226746a6f297SJonathan Marek snps,dis_u2_susphy_quirk; 226846a6f297SJonathan Marek snps,dis_enblslpm_quirk; 226946a6f297SJonathan Marek phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 227046a6f297SJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 227146a6f297SJonathan Marek }; 227246a6f297SJonathan Marek }; 227346a6f297SJonathan Marek 22740085a33aSManivannan Sadhasivam system-cache-controller@9200000 { 22750085a33aSManivannan Sadhasivam compatible = "qcom,sm8250-llcc"; 22760085a33aSManivannan Sadhasivam reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 22770085a33aSManivannan Sadhasivam reg-names = "llcc_base", "llcc_broadcast_base"; 22780085a33aSManivannan Sadhasivam }; 22790085a33aSManivannan Sadhasivam 228046a6f297SJonathan Marek usb_2: usb@a8f8800 { 228146a6f297SJonathan Marek compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 228246a6f297SJonathan Marek reg = <0 0x0a8f8800 0 0x400>; 228346a6f297SJonathan Marek status = "disabled"; 228446a6f297SJonathan Marek #address-cells = <2>; 228546a6f297SJonathan Marek #size-cells = <2>; 228646a6f297SJonathan Marek ranges; 228746a6f297SJonathan Marek dma-ranges; 228846a6f297SJonathan Marek 228946a6f297SJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 229046a6f297SJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>, 229146a6f297SJonathan Marek <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 229246a6f297SJonathan Marek <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 229346a6f297SJonathan Marek <&gcc GCC_USB30_SEC_SLEEP_CLK>, 229446a6f297SJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_EN>; 229546a6f297SJonathan Marek clock-names = "cfg_noc", "core", "iface", "mock_utmi", 229646a6f297SJonathan Marek "sleep", "xo"; 229746a6f297SJonathan Marek 229846a6f297SJonathan Marek assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 229946a6f297SJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>; 230046a6f297SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 230146a6f297SJonathan Marek 230246a6f297SJonathan Marek interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 230346a6f297SJonathan Marek <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 230446a6f297SJonathan Marek <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 230546a6f297SJonathan Marek <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 230646a6f297SJonathan Marek interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 230746a6f297SJonathan Marek "dm_hs_phy_irq", "ss_phy_irq"; 230846a6f297SJonathan Marek 230946a6f297SJonathan Marek power-domains = <&gcc USB30_SEC_GDSC>; 231046a6f297SJonathan Marek 231146a6f297SJonathan Marek resets = <&gcc GCC_USB30_SEC_BCR>; 231246a6f297SJonathan Marek 231346a6f297SJonathan Marek usb_2_dwc3: dwc3@a800000 { 231446a6f297SJonathan Marek compatible = "snps,dwc3"; 231546a6f297SJonathan Marek reg = <0 0x0a800000 0 0xcd00>; 231646a6f297SJonathan Marek interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 231746a6f297SJonathan Marek iommus = <&apps_smmu 0x20 0>; 231846a6f297SJonathan Marek snps,dis_u2_susphy_quirk; 231946a6f297SJonathan Marek snps,dis_enblslpm_quirk; 232046a6f297SJonathan Marek phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 232146a6f297SJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 232246a6f297SJonathan Marek }; 232346a6f297SJonathan Marek }; 232446a6f297SJonathan Marek 23257c1dffd4SDmitry Baryshkov mdss: mdss@ae00000 { 23267c1dffd4SDmitry Baryshkov compatible = "qcom,sdm845-mdss"; 23277c1dffd4SDmitry Baryshkov reg = <0 0x0ae00000 0 0x1000>; 23287c1dffd4SDmitry Baryshkov reg-names = "mdss"; 23297c1dffd4SDmitry Baryshkov 23307c1dffd4SDmitry Baryshkov interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>, 23317c1dffd4SDmitry Baryshkov <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 23327c1dffd4SDmitry Baryshkov <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 23337c1dffd4SDmitry Baryshkov interconnect-names = "notused", "mdp0-mem", "mdp1-mem"; 23347c1dffd4SDmitry Baryshkov 23357c1dffd4SDmitry Baryshkov power-domains = <&dispcc MDSS_GDSC>; 23367c1dffd4SDmitry Baryshkov 23377c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 23387c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_HF_AXI_CLK>, 23397c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_SF_AXI_CLK>, 23407c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_MDP_CLK>; 23417c1dffd4SDmitry Baryshkov clock-names = "iface", "bus", "nrt_bus", "core"; 23427c1dffd4SDmitry Baryshkov 23437c1dffd4SDmitry Baryshkov assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 23447c1dffd4SDmitry Baryshkov assigned-clock-rates = <460000000>; 23457c1dffd4SDmitry Baryshkov 23467c1dffd4SDmitry Baryshkov interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 23477c1dffd4SDmitry Baryshkov interrupt-controller; 23487c1dffd4SDmitry Baryshkov #interrupt-cells = <1>; 23497c1dffd4SDmitry Baryshkov 23507c1dffd4SDmitry Baryshkov iommus = <&apps_smmu 0x820 0x402>; 23517c1dffd4SDmitry Baryshkov 23527c1dffd4SDmitry Baryshkov status = "disabled"; 23537c1dffd4SDmitry Baryshkov 23547c1dffd4SDmitry Baryshkov #address-cells = <2>; 23557c1dffd4SDmitry Baryshkov #size-cells = <2>; 23567c1dffd4SDmitry Baryshkov ranges; 23577c1dffd4SDmitry Baryshkov 23587c1dffd4SDmitry Baryshkov mdss_mdp: mdp@ae01000 { 23597c1dffd4SDmitry Baryshkov compatible = "qcom,sdm845-dpu"; 23607c1dffd4SDmitry Baryshkov reg = <0 0x0ae01000 0 0x8f000>, 23617c1dffd4SDmitry Baryshkov <0 0x0aeb0000 0 0x2008>; 23627c1dffd4SDmitry Baryshkov reg-names = "mdp", "vbif"; 23637c1dffd4SDmitry Baryshkov 23647c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 23657c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_HF_AXI_CLK>, 23667c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_MDP_CLK>, 23677c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 23687c1dffd4SDmitry Baryshkov clock-names = "iface", "bus", "core", "vsync"; 23697c1dffd4SDmitry Baryshkov 23707c1dffd4SDmitry Baryshkov assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 23717c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 23727c1dffd4SDmitry Baryshkov assigned-clock-rates = <460000000>, 23737c1dffd4SDmitry Baryshkov <19200000>; 23747c1dffd4SDmitry Baryshkov 23757c1dffd4SDmitry Baryshkov operating-points-v2 = <&mdp_opp_table>; 23767c1dffd4SDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 23777c1dffd4SDmitry Baryshkov 23787c1dffd4SDmitry Baryshkov interrupt-parent = <&mdss>; 23797c1dffd4SDmitry Baryshkov interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 23807c1dffd4SDmitry Baryshkov 23817c1dffd4SDmitry Baryshkov status = "disabled"; 23827c1dffd4SDmitry Baryshkov 23837c1dffd4SDmitry Baryshkov ports { 23847c1dffd4SDmitry Baryshkov #address-cells = <1>; 23857c1dffd4SDmitry Baryshkov #size-cells = <0>; 23867c1dffd4SDmitry Baryshkov 23877c1dffd4SDmitry Baryshkov port@0 { 23887c1dffd4SDmitry Baryshkov reg = <0>; 23897c1dffd4SDmitry Baryshkov dpu_intf1_out: endpoint { 23907c1dffd4SDmitry Baryshkov remote-endpoint = <&dsi0_in>; 23917c1dffd4SDmitry Baryshkov }; 23927c1dffd4SDmitry Baryshkov }; 23937c1dffd4SDmitry Baryshkov 23947c1dffd4SDmitry Baryshkov port@1 { 23957c1dffd4SDmitry Baryshkov reg = <1>; 23967c1dffd4SDmitry Baryshkov dpu_intf2_out: endpoint { 23977c1dffd4SDmitry Baryshkov remote-endpoint = <&dsi1_in>; 23987c1dffd4SDmitry Baryshkov }; 23997c1dffd4SDmitry Baryshkov }; 24007c1dffd4SDmitry Baryshkov }; 24017c1dffd4SDmitry Baryshkov 24027c1dffd4SDmitry Baryshkov mdp_opp_table: mdp-opp-table { 24037c1dffd4SDmitry Baryshkov compatible = "operating-points-v2"; 24047c1dffd4SDmitry Baryshkov 24057c1dffd4SDmitry Baryshkov opp-200000000 { 24067c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <200000000>; 24077c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 24087c1dffd4SDmitry Baryshkov }; 24097c1dffd4SDmitry Baryshkov 24107c1dffd4SDmitry Baryshkov opp-300000000 { 24117c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <300000000>; 24127c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs>; 24137c1dffd4SDmitry Baryshkov }; 24147c1dffd4SDmitry Baryshkov 24157c1dffd4SDmitry Baryshkov opp-345000000 { 24167c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <345000000>; 24177c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs_l1>; 24187c1dffd4SDmitry Baryshkov }; 24197c1dffd4SDmitry Baryshkov 24207c1dffd4SDmitry Baryshkov opp-460000000 { 24217c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <460000000>; 24227c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_nom>; 24237c1dffd4SDmitry Baryshkov }; 24247c1dffd4SDmitry Baryshkov }; 24257c1dffd4SDmitry Baryshkov }; 24267c1dffd4SDmitry Baryshkov 24277c1dffd4SDmitry Baryshkov dsi0: dsi@ae94000 { 24287c1dffd4SDmitry Baryshkov compatible = "qcom,mdss-dsi-ctrl"; 24297c1dffd4SDmitry Baryshkov reg = <0 0x0ae94000 0 0x400>; 24307c1dffd4SDmitry Baryshkov reg-names = "dsi_ctrl"; 24317c1dffd4SDmitry Baryshkov 24327c1dffd4SDmitry Baryshkov interrupt-parent = <&mdss>; 24337c1dffd4SDmitry Baryshkov interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 24347c1dffd4SDmitry Baryshkov 24357c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 24367c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 24377c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 24387c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_ESC0_CLK>, 24397c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_AHB_CLK>, 24407c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_HF_AXI_CLK>; 24417c1dffd4SDmitry Baryshkov clock-names = "byte", 24427c1dffd4SDmitry Baryshkov "byte_intf", 24437c1dffd4SDmitry Baryshkov "pixel", 24447c1dffd4SDmitry Baryshkov "core", 24457c1dffd4SDmitry Baryshkov "iface", 24467c1dffd4SDmitry Baryshkov "bus"; 24477c1dffd4SDmitry Baryshkov 24487c1dffd4SDmitry Baryshkov operating-points-v2 = <&dsi_opp_table>; 24497c1dffd4SDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 24507c1dffd4SDmitry Baryshkov 24517c1dffd4SDmitry Baryshkov phys = <&dsi0_phy>; 24527c1dffd4SDmitry Baryshkov phy-names = "dsi"; 24537c1dffd4SDmitry Baryshkov 24547c1dffd4SDmitry Baryshkov status = "disabled"; 24557c1dffd4SDmitry Baryshkov 24567c1dffd4SDmitry Baryshkov ports { 24577c1dffd4SDmitry Baryshkov #address-cells = <1>; 24587c1dffd4SDmitry Baryshkov #size-cells = <0>; 24597c1dffd4SDmitry Baryshkov 24607c1dffd4SDmitry Baryshkov port@0 { 24617c1dffd4SDmitry Baryshkov reg = <0>; 24627c1dffd4SDmitry Baryshkov dsi0_in: endpoint { 24637c1dffd4SDmitry Baryshkov remote-endpoint = <&dpu_intf1_out>; 24647c1dffd4SDmitry Baryshkov }; 24657c1dffd4SDmitry Baryshkov }; 24667c1dffd4SDmitry Baryshkov 24677c1dffd4SDmitry Baryshkov port@1 { 24687c1dffd4SDmitry Baryshkov reg = <1>; 24697c1dffd4SDmitry Baryshkov dsi0_out: endpoint { 24707c1dffd4SDmitry Baryshkov }; 24717c1dffd4SDmitry Baryshkov }; 24727c1dffd4SDmitry Baryshkov }; 24737c1dffd4SDmitry Baryshkov }; 24747c1dffd4SDmitry Baryshkov 24757c1dffd4SDmitry Baryshkov dsi0_phy: dsi-phy@ae94400 { 24767c1dffd4SDmitry Baryshkov compatible = "qcom,dsi-phy-7nm"; 24777c1dffd4SDmitry Baryshkov reg = <0 0x0ae94400 0 0x200>, 24787c1dffd4SDmitry Baryshkov <0 0x0ae94600 0 0x280>, 24797c1dffd4SDmitry Baryshkov <0 0x0ae94900 0 0x260>; 24807c1dffd4SDmitry Baryshkov reg-names = "dsi_phy", 24817c1dffd4SDmitry Baryshkov "dsi_phy_lane", 24827c1dffd4SDmitry Baryshkov "dsi_pll"; 24837c1dffd4SDmitry Baryshkov 24847c1dffd4SDmitry Baryshkov #clock-cells = <1>; 24857c1dffd4SDmitry Baryshkov #phy-cells = <0>; 24867c1dffd4SDmitry Baryshkov 24877c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 24887c1dffd4SDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK>; 24897c1dffd4SDmitry Baryshkov clock-names = "iface", "ref"; 24907c1dffd4SDmitry Baryshkov 24917c1dffd4SDmitry Baryshkov status = "disabled"; 24927c1dffd4SDmitry Baryshkov }; 24937c1dffd4SDmitry Baryshkov 24947c1dffd4SDmitry Baryshkov dsi1: dsi@ae96000 { 24957c1dffd4SDmitry Baryshkov compatible = "qcom,mdss-dsi-ctrl"; 24967c1dffd4SDmitry Baryshkov reg = <0 0x0ae96000 0 0x400>; 24977c1dffd4SDmitry Baryshkov reg-names = "dsi_ctrl"; 24987c1dffd4SDmitry Baryshkov 24997c1dffd4SDmitry Baryshkov interrupt-parent = <&mdss>; 25007c1dffd4SDmitry Baryshkov interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 25017c1dffd4SDmitry Baryshkov 25027c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 25037c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 25047c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 25057c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_ESC1_CLK>, 25067c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_AHB_CLK>, 25077c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_HF_AXI_CLK>; 25087c1dffd4SDmitry Baryshkov clock-names = "byte", 25097c1dffd4SDmitry Baryshkov "byte_intf", 25107c1dffd4SDmitry Baryshkov "pixel", 25117c1dffd4SDmitry Baryshkov "core", 25127c1dffd4SDmitry Baryshkov "iface", 25137c1dffd4SDmitry Baryshkov "bus"; 25147c1dffd4SDmitry Baryshkov 25157c1dffd4SDmitry Baryshkov operating-points-v2 = <&dsi_opp_table>; 25167c1dffd4SDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 25177c1dffd4SDmitry Baryshkov 25187c1dffd4SDmitry Baryshkov phys = <&dsi1_phy>; 25197c1dffd4SDmitry Baryshkov phy-names = "dsi"; 25207c1dffd4SDmitry Baryshkov 25217c1dffd4SDmitry Baryshkov status = "disabled"; 25227c1dffd4SDmitry Baryshkov 25237c1dffd4SDmitry Baryshkov ports { 25247c1dffd4SDmitry Baryshkov #address-cells = <1>; 25257c1dffd4SDmitry Baryshkov #size-cells = <0>; 25267c1dffd4SDmitry Baryshkov 25277c1dffd4SDmitry Baryshkov port@0 { 25287c1dffd4SDmitry Baryshkov reg = <0>; 25297c1dffd4SDmitry Baryshkov dsi1_in: endpoint { 25307c1dffd4SDmitry Baryshkov remote-endpoint = <&dpu_intf2_out>; 25317c1dffd4SDmitry Baryshkov }; 25327c1dffd4SDmitry Baryshkov }; 25337c1dffd4SDmitry Baryshkov 25347c1dffd4SDmitry Baryshkov port@1 { 25357c1dffd4SDmitry Baryshkov reg = <1>; 25367c1dffd4SDmitry Baryshkov dsi1_out: endpoint { 25377c1dffd4SDmitry Baryshkov }; 25387c1dffd4SDmitry Baryshkov }; 25397c1dffd4SDmitry Baryshkov }; 25407c1dffd4SDmitry Baryshkov }; 25417c1dffd4SDmitry Baryshkov 25427c1dffd4SDmitry Baryshkov dsi1_phy: dsi-phy@ae96400 { 25437c1dffd4SDmitry Baryshkov compatible = "qcom,dsi-phy-7nm"; 25447c1dffd4SDmitry Baryshkov reg = <0 0x0ae96400 0 0x200>, 25457c1dffd4SDmitry Baryshkov <0 0x0ae96600 0 0x280>, 25467c1dffd4SDmitry Baryshkov <0 0x0ae96900 0 0x260>; 25477c1dffd4SDmitry Baryshkov reg-names = "dsi_phy", 25487c1dffd4SDmitry Baryshkov "dsi_phy_lane", 25497c1dffd4SDmitry Baryshkov "dsi_pll"; 25507c1dffd4SDmitry Baryshkov 25517c1dffd4SDmitry Baryshkov #clock-cells = <1>; 25527c1dffd4SDmitry Baryshkov #phy-cells = <0>; 25537c1dffd4SDmitry Baryshkov 25547c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 25557c1dffd4SDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK>; 25567c1dffd4SDmitry Baryshkov clock-names = "iface", "ref"; 25577c1dffd4SDmitry Baryshkov 25587c1dffd4SDmitry Baryshkov status = "disabled"; 25597c1dffd4SDmitry Baryshkov 25607c1dffd4SDmitry Baryshkov dsi_opp_table: dsi-opp-table { 25617c1dffd4SDmitry Baryshkov compatible = "operating-points-v2"; 25627c1dffd4SDmitry Baryshkov 25637c1dffd4SDmitry Baryshkov opp-187500000 { 25647c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <187500000>; 25657c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 25667c1dffd4SDmitry Baryshkov }; 25677c1dffd4SDmitry Baryshkov 25687c1dffd4SDmitry Baryshkov opp-300000000 { 25697c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <300000000>; 25707c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs>; 25717c1dffd4SDmitry Baryshkov }; 25727c1dffd4SDmitry Baryshkov 25737c1dffd4SDmitry Baryshkov opp-358000000 { 25747c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <358000000>; 25757c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs_l1>; 25767c1dffd4SDmitry Baryshkov }; 25777c1dffd4SDmitry Baryshkov }; 25787c1dffd4SDmitry Baryshkov }; 25797c1dffd4SDmitry Baryshkov }; 25807c1dffd4SDmitry Baryshkov 25817c1dffd4SDmitry Baryshkov dispcc: clock-controller@af00000 { 25827c1dffd4SDmitry Baryshkov compatible = "qcom,sm8250-dispcc"; 25837c1dffd4SDmitry Baryshkov reg = <0 0x0af00000 0 0x20000>; 25843f2094dfSDmitry Baryshkov mmcx-supply = <&mmcx_reg>; 25857c1dffd4SDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>, 25867c1dffd4SDmitry Baryshkov <&dsi0_phy 0>, 25877c1dffd4SDmitry Baryshkov <&dsi0_phy 1>, 25887c1dffd4SDmitry Baryshkov <&dsi1_phy 0>, 25897c1dffd4SDmitry Baryshkov <&dsi1_phy 1>, 25907c1dffd4SDmitry Baryshkov <0>, 25917c1dffd4SDmitry Baryshkov <0>, 25927c1dffd4SDmitry Baryshkov <0>, 25937c1dffd4SDmitry Baryshkov <0>, 25947c1dffd4SDmitry Baryshkov <0>, 25957c1dffd4SDmitry Baryshkov <0>, 25967c1dffd4SDmitry Baryshkov <0>, 25977c1dffd4SDmitry Baryshkov <0>, 25987c1dffd4SDmitry Baryshkov <&sleep_clk>; 25997c1dffd4SDmitry Baryshkov clock-names = "bi_tcxo", 26007c1dffd4SDmitry Baryshkov "dsi0_phy_pll_out_byteclk", 26017c1dffd4SDmitry Baryshkov "dsi0_phy_pll_out_dsiclk", 26027c1dffd4SDmitry Baryshkov "dsi1_phy_pll_out_byteclk", 26037c1dffd4SDmitry Baryshkov "dsi1_phy_pll_out_dsiclk", 26047c1dffd4SDmitry Baryshkov "dp_link_clk_divsel_ten", 26057c1dffd4SDmitry Baryshkov "dp_vco_divided_clk_src_mux", 26067c1dffd4SDmitry Baryshkov "dptx1_phy_pll_link_clk", 26077c1dffd4SDmitry Baryshkov "dptx1_phy_pll_vco_div_clk", 26087c1dffd4SDmitry Baryshkov "dptx2_phy_pll_link_clk", 26097c1dffd4SDmitry Baryshkov "dptx2_phy_pll_vco_div_clk", 26107c1dffd4SDmitry Baryshkov "edp_phy_pll_link_clk", 26117c1dffd4SDmitry Baryshkov "edp_phy_pll_vco_div_clk", 26127c1dffd4SDmitry Baryshkov "sleep_clk"; 26137c1dffd4SDmitry Baryshkov #clock-cells = <1>; 26147c1dffd4SDmitry Baryshkov #reset-cells = <1>; 26157c1dffd4SDmitry Baryshkov #power-domain-cells = <1>; 26167c1dffd4SDmitry Baryshkov }; 26177c1dffd4SDmitry Baryshkov 261860378f1aSVenkata Narendra Kumar Gutta pdc: interrupt-controller@b220000 { 261924003196SBjorn Andersson compatible = "qcom,sm8250-pdc", "qcom,pdc"; 262024003196SBjorn Andersson reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 262160378f1aSVenkata Narendra Kumar Gutta qcom,pdc-ranges = <0 480 94>, <94 609 31>, 262260378f1aSVenkata Narendra Kumar Gutta <125 63 1>, <126 716 12>; 262360378f1aSVenkata Narendra Kumar Gutta #interrupt-cells = <2>; 262460378f1aSVenkata Narendra Kumar Gutta interrupt-parent = <&intc>; 262560378f1aSVenkata Narendra Kumar Gutta interrupt-controller; 262660378f1aSVenkata Narendra Kumar Gutta }; 262760378f1aSVenkata Narendra Kumar Gutta 2628bac12f25SAmit Kucheria tsens0: thermal-sensor@c263000 { 2629bac12f25SAmit Kucheria compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 2630bac12f25SAmit Kucheria reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2631bac12f25SAmit Kucheria <0 0x0c222000 0 0x1ff>; /* SROT */ 2632bac12f25SAmit Kucheria #qcom,sensors = <16>; 2633bac12f25SAmit Kucheria interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2634bac12f25SAmit Kucheria <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2635bac12f25SAmit Kucheria interrupt-names = "uplow", "critical"; 2636bac12f25SAmit Kucheria #thermal-sensor-cells = <1>; 2637bac12f25SAmit Kucheria }; 2638bac12f25SAmit Kucheria 2639bac12f25SAmit Kucheria tsens1: thermal-sensor@c265000 { 2640bac12f25SAmit Kucheria compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 2641bac12f25SAmit Kucheria reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2642bac12f25SAmit Kucheria <0 0x0c223000 0 0x1ff>; /* SROT */ 2643bac12f25SAmit Kucheria #qcom,sensors = <9>; 2644bac12f25SAmit Kucheria interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2645bac12f25SAmit Kucheria <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2646bac12f25SAmit Kucheria interrupt-names = "uplow", "critical"; 2647bac12f25SAmit Kucheria #thermal-sensor-cells = <1>; 2648bac12f25SAmit Kucheria }; 2649bac12f25SAmit Kucheria 265043f14a0bSSai Prakash Ranjan aoss_qmp: power-controller@c300000 { 2651087d537aSBjorn Andersson compatible = "qcom,sm8250-aoss-qmp"; 2652087d537aSBjorn Andersson reg = <0 0x0c300000 0 0x100000>; 2653087d537aSBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2654087d537aSBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 2655087d537aSBjorn Andersson IRQ_TYPE_EDGE_RISING>; 2656087d537aSBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_AOP 2657087d537aSBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 2658087d537aSBjorn Andersson 2659087d537aSBjorn Andersson #clock-cells = <0>; 2660087d537aSBjorn Andersson #power-domain-cells = <1>; 2661087d537aSBjorn Andersson }; 2662087d537aSBjorn Andersson 2663bccc7dd2SJonathan Marek spmi_bus: spmi@c440000 { 266460378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,spmi-pmic-arb"; 266560378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x0c440000 0x0 0x0001100>, 266660378f1aSVenkata Narendra Kumar Gutta <0x0 0x0c600000 0x0 0x2000000>, 266760378f1aSVenkata Narendra Kumar Gutta <0x0 0x0e600000 0x0 0x0100000>, 266860378f1aSVenkata Narendra Kumar Gutta <0x0 0x0e700000 0x0 0x00a0000>, 266960378f1aSVenkata Narendra Kumar Gutta <0x0 0x0c40a000 0x0 0x0026000>; 267060378f1aSVenkata Narendra Kumar Gutta reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 267160378f1aSVenkata Narendra Kumar Gutta interrupt-names = "periph_irq"; 267260378f1aSVenkata Narendra Kumar Gutta interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 267360378f1aSVenkata Narendra Kumar Gutta qcom,ee = <0>; 267460378f1aSVenkata Narendra Kumar Gutta qcom,channel = <0>; 267560378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 267660378f1aSVenkata Narendra Kumar Gutta #size-cells = <0>; 267760378f1aSVenkata Narendra Kumar Gutta interrupt-controller; 267860378f1aSVenkata Narendra Kumar Gutta #interrupt-cells = <4>; 267960378f1aSVenkata Narendra Kumar Gutta }; 268060378f1aSVenkata Narendra Kumar Gutta 268116951b49SBjorn Andersson tlmm: pinctrl@f100000 { 268216951b49SBjorn Andersson compatible = "qcom,sm8250-pinctrl"; 268316951b49SBjorn Andersson reg = <0 0x0f100000 0 0x300000>, 268416951b49SBjorn Andersson <0 0x0f500000 0 0x300000>, 268516951b49SBjorn Andersson <0 0x0f900000 0 0x300000>; 268616951b49SBjorn Andersson reg-names = "west", "south", "north"; 268716951b49SBjorn Andersson interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 268816951b49SBjorn Andersson gpio-controller; 268916951b49SBjorn Andersson #gpio-cells = <2>; 269016951b49SBjorn Andersson interrupt-controller; 269116951b49SBjorn Andersson #interrupt-cells = <2>; 269216951b49SBjorn Andersson gpio-ranges = <&tlmm 0 0 180>; 269316951b49SBjorn Andersson wakeup-parent = <&pdc>; 2694e5813b15SDmitry Baryshkov 2695b657d372SSrinivas Kandagatla pri_mi2s_active: pri-mi2s-active { 2696b657d372SSrinivas Kandagatla sclk { 2697b657d372SSrinivas Kandagatla pins = "gpio138"; 2698b657d372SSrinivas Kandagatla function = "mi2s0_sck"; 2699b657d372SSrinivas Kandagatla drive-strength = <8>; 2700b657d372SSrinivas Kandagatla bias-disable; 2701b657d372SSrinivas Kandagatla }; 2702b657d372SSrinivas Kandagatla 2703b657d372SSrinivas Kandagatla ws { 2704b657d372SSrinivas Kandagatla pins = "gpio141"; 2705b657d372SSrinivas Kandagatla function = "mi2s0_ws"; 2706b657d372SSrinivas Kandagatla drive-strength = <8>; 2707b657d372SSrinivas Kandagatla output-high; 2708b657d372SSrinivas Kandagatla }; 2709b657d372SSrinivas Kandagatla 2710b657d372SSrinivas Kandagatla data0 { 2711b657d372SSrinivas Kandagatla pins = "gpio139"; 2712b657d372SSrinivas Kandagatla function = "mi2s0_data0"; 2713b657d372SSrinivas Kandagatla drive-strength = <8>; 2714b657d372SSrinivas Kandagatla bias-disable; 2715b657d372SSrinivas Kandagatla output-high; 2716b657d372SSrinivas Kandagatla }; 2717b657d372SSrinivas Kandagatla 2718b657d372SSrinivas Kandagatla data1 { 2719b657d372SSrinivas Kandagatla pins = "gpio140"; 2720b657d372SSrinivas Kandagatla function = "mi2s0_data1"; 2721b657d372SSrinivas Kandagatla drive-strength = <8>; 2722b657d372SSrinivas Kandagatla output-high; 2723b657d372SSrinivas Kandagatla }; 2724b657d372SSrinivas Kandagatla }; 2725b657d372SSrinivas Kandagatla 2726e5813b15SDmitry Baryshkov qup_i2c0_default: qup-i2c0-default { 2727e5813b15SDmitry Baryshkov mux { 2728e5813b15SDmitry Baryshkov pins = "gpio28", "gpio29"; 2729e5813b15SDmitry Baryshkov function = "qup0"; 2730e5813b15SDmitry Baryshkov }; 2731e5813b15SDmitry Baryshkov 2732e5813b15SDmitry Baryshkov config { 2733e5813b15SDmitry Baryshkov pins = "gpio28", "gpio29"; 2734e5813b15SDmitry Baryshkov drive-strength = <2>; 2735e5813b15SDmitry Baryshkov bias-disable; 2736e5813b15SDmitry Baryshkov }; 2737e5813b15SDmitry Baryshkov }; 2738e5813b15SDmitry Baryshkov 2739e5813b15SDmitry Baryshkov qup_i2c1_default: qup-i2c1-default { 2740e5813b15SDmitry Baryshkov pinmux { 2741e5813b15SDmitry Baryshkov pins = "gpio4", "gpio5"; 2742e5813b15SDmitry Baryshkov function = "qup1"; 2743e5813b15SDmitry Baryshkov }; 2744e5813b15SDmitry Baryshkov 2745e5813b15SDmitry Baryshkov config { 2746e5813b15SDmitry Baryshkov pins = "gpio4", "gpio5"; 2747e5813b15SDmitry Baryshkov drive-strength = <2>; 2748e5813b15SDmitry Baryshkov bias-disable; 2749e5813b15SDmitry Baryshkov }; 2750e5813b15SDmitry Baryshkov }; 2751e5813b15SDmitry Baryshkov 2752e5813b15SDmitry Baryshkov qup_i2c2_default: qup-i2c2-default { 2753e5813b15SDmitry Baryshkov mux { 2754e5813b15SDmitry Baryshkov pins = "gpio115", "gpio116"; 2755e5813b15SDmitry Baryshkov function = "qup2"; 2756e5813b15SDmitry Baryshkov }; 2757e5813b15SDmitry Baryshkov 2758e5813b15SDmitry Baryshkov config { 2759e5813b15SDmitry Baryshkov pins = "gpio115", "gpio116"; 2760e5813b15SDmitry Baryshkov drive-strength = <2>; 2761e5813b15SDmitry Baryshkov bias-disable; 2762e5813b15SDmitry Baryshkov }; 2763e5813b15SDmitry Baryshkov }; 2764e5813b15SDmitry Baryshkov 2765e5813b15SDmitry Baryshkov qup_i2c3_default: qup-i2c3-default { 2766e5813b15SDmitry Baryshkov mux { 2767e5813b15SDmitry Baryshkov pins = "gpio119", "gpio120"; 2768e5813b15SDmitry Baryshkov function = "qup3"; 2769e5813b15SDmitry Baryshkov }; 2770e5813b15SDmitry Baryshkov 2771e5813b15SDmitry Baryshkov config { 2772e5813b15SDmitry Baryshkov pins = "gpio119", "gpio120"; 2773e5813b15SDmitry Baryshkov drive-strength = <2>; 2774e5813b15SDmitry Baryshkov bias-disable; 2775e5813b15SDmitry Baryshkov }; 2776e5813b15SDmitry Baryshkov }; 2777e5813b15SDmitry Baryshkov 2778e5813b15SDmitry Baryshkov qup_i2c4_default: qup-i2c4-default { 2779e5813b15SDmitry Baryshkov mux { 2780e5813b15SDmitry Baryshkov pins = "gpio8", "gpio9"; 2781e5813b15SDmitry Baryshkov function = "qup4"; 2782e5813b15SDmitry Baryshkov }; 2783e5813b15SDmitry Baryshkov 2784e5813b15SDmitry Baryshkov config { 2785e5813b15SDmitry Baryshkov pins = "gpio8", "gpio9"; 2786e5813b15SDmitry Baryshkov drive-strength = <2>; 2787e5813b15SDmitry Baryshkov bias-disable; 2788e5813b15SDmitry Baryshkov }; 2789e5813b15SDmitry Baryshkov }; 2790e5813b15SDmitry Baryshkov 2791e5813b15SDmitry Baryshkov qup_i2c5_default: qup-i2c5-default { 2792e5813b15SDmitry Baryshkov mux { 2793e5813b15SDmitry Baryshkov pins = "gpio12", "gpio13"; 2794e5813b15SDmitry Baryshkov function = "qup5"; 2795e5813b15SDmitry Baryshkov }; 2796e5813b15SDmitry Baryshkov 2797e5813b15SDmitry Baryshkov config { 2798e5813b15SDmitry Baryshkov pins = "gpio12", "gpio13"; 2799e5813b15SDmitry Baryshkov drive-strength = <2>; 2800e5813b15SDmitry Baryshkov bias-disable; 2801e5813b15SDmitry Baryshkov }; 2802e5813b15SDmitry Baryshkov }; 2803e5813b15SDmitry Baryshkov 2804e5813b15SDmitry Baryshkov qup_i2c6_default: qup-i2c6-default { 2805e5813b15SDmitry Baryshkov mux { 2806e5813b15SDmitry Baryshkov pins = "gpio16", "gpio17"; 2807e5813b15SDmitry Baryshkov function = "qup6"; 2808e5813b15SDmitry Baryshkov }; 2809e5813b15SDmitry Baryshkov 2810e5813b15SDmitry Baryshkov config { 2811e5813b15SDmitry Baryshkov pins = "gpio16", "gpio17"; 2812e5813b15SDmitry Baryshkov drive-strength = <2>; 2813e5813b15SDmitry Baryshkov bias-disable; 2814e5813b15SDmitry Baryshkov }; 2815e5813b15SDmitry Baryshkov }; 2816e5813b15SDmitry Baryshkov 2817e5813b15SDmitry Baryshkov qup_i2c7_default: qup-i2c7-default { 2818e5813b15SDmitry Baryshkov mux { 2819e5813b15SDmitry Baryshkov pins = "gpio20", "gpio21"; 2820e5813b15SDmitry Baryshkov function = "qup7"; 2821e5813b15SDmitry Baryshkov }; 2822e5813b15SDmitry Baryshkov 2823e5813b15SDmitry Baryshkov config { 2824e5813b15SDmitry Baryshkov pins = "gpio20", "gpio21"; 2825e5813b15SDmitry Baryshkov drive-strength = <2>; 2826e5813b15SDmitry Baryshkov bias-disable; 2827e5813b15SDmitry Baryshkov }; 2828e5813b15SDmitry Baryshkov }; 2829e5813b15SDmitry Baryshkov 2830e5813b15SDmitry Baryshkov qup_i2c8_default: qup-i2c8-default { 2831e5813b15SDmitry Baryshkov mux { 2832e5813b15SDmitry Baryshkov pins = "gpio24", "gpio25"; 2833e5813b15SDmitry Baryshkov function = "qup8"; 2834e5813b15SDmitry Baryshkov }; 2835e5813b15SDmitry Baryshkov 2836e5813b15SDmitry Baryshkov config { 2837e5813b15SDmitry Baryshkov pins = "gpio24", "gpio25"; 2838e5813b15SDmitry Baryshkov drive-strength = <2>; 2839e5813b15SDmitry Baryshkov bias-disable; 2840e5813b15SDmitry Baryshkov }; 2841e5813b15SDmitry Baryshkov }; 2842e5813b15SDmitry Baryshkov 2843e5813b15SDmitry Baryshkov qup_i2c9_default: qup-i2c9-default { 2844e5813b15SDmitry Baryshkov mux { 2845e5813b15SDmitry Baryshkov pins = "gpio125", "gpio126"; 2846e5813b15SDmitry Baryshkov function = "qup9"; 2847e5813b15SDmitry Baryshkov }; 2848e5813b15SDmitry Baryshkov 2849e5813b15SDmitry Baryshkov config { 2850e5813b15SDmitry Baryshkov pins = "gpio125", "gpio126"; 2851e5813b15SDmitry Baryshkov drive-strength = <2>; 2852e5813b15SDmitry Baryshkov bias-disable; 2853e5813b15SDmitry Baryshkov }; 2854e5813b15SDmitry Baryshkov }; 2855e5813b15SDmitry Baryshkov 2856e5813b15SDmitry Baryshkov qup_i2c10_default: qup-i2c10-default { 2857e5813b15SDmitry Baryshkov mux { 2858e5813b15SDmitry Baryshkov pins = "gpio129", "gpio130"; 2859e5813b15SDmitry Baryshkov function = "qup10"; 2860e5813b15SDmitry Baryshkov }; 2861e5813b15SDmitry Baryshkov 2862e5813b15SDmitry Baryshkov config { 2863e5813b15SDmitry Baryshkov pins = "gpio129", "gpio130"; 2864e5813b15SDmitry Baryshkov drive-strength = <2>; 2865e5813b15SDmitry Baryshkov bias-disable; 2866e5813b15SDmitry Baryshkov }; 2867e5813b15SDmitry Baryshkov }; 2868e5813b15SDmitry Baryshkov 2869e5813b15SDmitry Baryshkov qup_i2c11_default: qup-i2c11-default { 2870e5813b15SDmitry Baryshkov mux { 2871e5813b15SDmitry Baryshkov pins = "gpio60", "gpio61"; 2872e5813b15SDmitry Baryshkov function = "qup11"; 2873e5813b15SDmitry Baryshkov }; 2874e5813b15SDmitry Baryshkov 2875e5813b15SDmitry Baryshkov config { 2876e5813b15SDmitry Baryshkov pins = "gpio60", "gpio61"; 2877e5813b15SDmitry Baryshkov drive-strength = <2>; 2878e5813b15SDmitry Baryshkov bias-disable; 2879e5813b15SDmitry Baryshkov }; 2880e5813b15SDmitry Baryshkov }; 2881e5813b15SDmitry Baryshkov 2882e5813b15SDmitry Baryshkov qup_i2c12_default: qup-i2c12-default { 2883e5813b15SDmitry Baryshkov mux { 2884e5813b15SDmitry Baryshkov pins = "gpio32", "gpio33"; 2885e5813b15SDmitry Baryshkov function = "qup12"; 2886e5813b15SDmitry Baryshkov }; 2887e5813b15SDmitry Baryshkov 2888e5813b15SDmitry Baryshkov config { 2889e5813b15SDmitry Baryshkov pins = "gpio32", "gpio33"; 2890e5813b15SDmitry Baryshkov drive-strength = <2>; 2891e5813b15SDmitry Baryshkov bias-disable; 2892e5813b15SDmitry Baryshkov }; 2893e5813b15SDmitry Baryshkov }; 2894e5813b15SDmitry Baryshkov 2895e5813b15SDmitry Baryshkov qup_i2c13_default: qup-i2c13-default { 2896e5813b15SDmitry Baryshkov mux { 2897e5813b15SDmitry Baryshkov pins = "gpio36", "gpio37"; 2898e5813b15SDmitry Baryshkov function = "qup13"; 2899e5813b15SDmitry Baryshkov }; 2900e5813b15SDmitry Baryshkov 2901e5813b15SDmitry Baryshkov config { 2902e5813b15SDmitry Baryshkov pins = "gpio36", "gpio37"; 2903e5813b15SDmitry Baryshkov drive-strength = <2>; 2904e5813b15SDmitry Baryshkov bias-disable; 2905e5813b15SDmitry Baryshkov }; 2906e5813b15SDmitry Baryshkov }; 2907e5813b15SDmitry Baryshkov 2908e5813b15SDmitry Baryshkov qup_i2c14_default: qup-i2c14-default { 2909e5813b15SDmitry Baryshkov mux { 2910e5813b15SDmitry Baryshkov pins = "gpio40", "gpio41"; 2911e5813b15SDmitry Baryshkov function = "qup14"; 2912e5813b15SDmitry Baryshkov }; 2913e5813b15SDmitry Baryshkov 2914e5813b15SDmitry Baryshkov config { 2915e5813b15SDmitry Baryshkov pins = "gpio40", "gpio41"; 2916e5813b15SDmitry Baryshkov drive-strength = <2>; 2917e5813b15SDmitry Baryshkov bias-disable; 2918e5813b15SDmitry Baryshkov }; 2919e5813b15SDmitry Baryshkov }; 2920e5813b15SDmitry Baryshkov 2921e5813b15SDmitry Baryshkov qup_i2c15_default: qup-i2c15-default { 2922e5813b15SDmitry Baryshkov mux { 2923e5813b15SDmitry Baryshkov pins = "gpio44", "gpio45"; 2924e5813b15SDmitry Baryshkov function = "qup15"; 2925e5813b15SDmitry Baryshkov }; 2926e5813b15SDmitry Baryshkov 2927e5813b15SDmitry Baryshkov config { 2928e5813b15SDmitry Baryshkov pins = "gpio44", "gpio45"; 2929e5813b15SDmitry Baryshkov drive-strength = <2>; 2930e5813b15SDmitry Baryshkov bias-disable; 2931e5813b15SDmitry Baryshkov }; 2932e5813b15SDmitry Baryshkov }; 2933e5813b15SDmitry Baryshkov 2934e5813b15SDmitry Baryshkov qup_i2c16_default: qup-i2c16-default { 2935e5813b15SDmitry Baryshkov mux { 2936e5813b15SDmitry Baryshkov pins = "gpio48", "gpio49"; 2937e5813b15SDmitry Baryshkov function = "qup16"; 2938e5813b15SDmitry Baryshkov }; 2939e5813b15SDmitry Baryshkov 2940e5813b15SDmitry Baryshkov config { 2941e5813b15SDmitry Baryshkov pins = "gpio48", "gpio49"; 2942e5813b15SDmitry Baryshkov drive-strength = <2>; 2943e5813b15SDmitry Baryshkov bias-disable; 2944e5813b15SDmitry Baryshkov }; 2945e5813b15SDmitry Baryshkov }; 2946e5813b15SDmitry Baryshkov 2947e5813b15SDmitry Baryshkov qup_i2c17_default: qup-i2c17-default { 2948e5813b15SDmitry Baryshkov mux { 2949e5813b15SDmitry Baryshkov pins = "gpio52", "gpio53"; 2950e5813b15SDmitry Baryshkov function = "qup17"; 2951e5813b15SDmitry Baryshkov }; 2952e5813b15SDmitry Baryshkov 2953e5813b15SDmitry Baryshkov config { 2954e5813b15SDmitry Baryshkov pins = "gpio52", "gpio53"; 2955e5813b15SDmitry Baryshkov drive-strength = <2>; 2956e5813b15SDmitry Baryshkov bias-disable; 2957e5813b15SDmitry Baryshkov }; 2958e5813b15SDmitry Baryshkov }; 2959e5813b15SDmitry Baryshkov 2960e5813b15SDmitry Baryshkov qup_i2c18_default: qup-i2c18-default { 2961e5813b15SDmitry Baryshkov mux { 2962e5813b15SDmitry Baryshkov pins = "gpio56", "gpio57"; 2963e5813b15SDmitry Baryshkov function = "qup18"; 2964e5813b15SDmitry Baryshkov }; 2965e5813b15SDmitry Baryshkov 2966e5813b15SDmitry Baryshkov config { 2967e5813b15SDmitry Baryshkov pins = "gpio56", "gpio57"; 2968e5813b15SDmitry Baryshkov drive-strength = <2>; 2969e5813b15SDmitry Baryshkov bias-disable; 2970e5813b15SDmitry Baryshkov }; 2971e5813b15SDmitry Baryshkov }; 2972e5813b15SDmitry Baryshkov 2973e5813b15SDmitry Baryshkov qup_i2c19_default: qup-i2c19-default { 2974e5813b15SDmitry Baryshkov mux { 2975e5813b15SDmitry Baryshkov pins = "gpio0", "gpio1"; 2976e5813b15SDmitry Baryshkov function = "qup19"; 2977e5813b15SDmitry Baryshkov }; 2978e5813b15SDmitry Baryshkov 2979e5813b15SDmitry Baryshkov config { 2980e5813b15SDmitry Baryshkov pins = "gpio0", "gpio1"; 2981e5813b15SDmitry Baryshkov drive-strength = <2>; 2982e5813b15SDmitry Baryshkov bias-disable; 2983e5813b15SDmitry Baryshkov }; 2984e5813b15SDmitry Baryshkov }; 2985e5813b15SDmitry Baryshkov 2986e5813b15SDmitry Baryshkov qup_spi0_default: qup-spi0-default { 2987e5813b15SDmitry Baryshkov mux { 2988e5813b15SDmitry Baryshkov pins = "gpio28", "gpio29", 2989e5813b15SDmitry Baryshkov "gpio30", "gpio31"; 2990e5813b15SDmitry Baryshkov function = "qup0"; 2991e5813b15SDmitry Baryshkov }; 2992e5813b15SDmitry Baryshkov 2993e5813b15SDmitry Baryshkov config { 2994e5813b15SDmitry Baryshkov pins = "gpio28", "gpio29", 2995e5813b15SDmitry Baryshkov "gpio30", "gpio31"; 2996e5813b15SDmitry Baryshkov drive-strength = <6>; 2997e5813b15SDmitry Baryshkov bias-disable; 2998e5813b15SDmitry Baryshkov }; 2999e5813b15SDmitry Baryshkov }; 3000e5813b15SDmitry Baryshkov 3001e5813b15SDmitry Baryshkov qup_spi1_default: qup-spi1-default { 3002e5813b15SDmitry Baryshkov mux { 3003e5813b15SDmitry Baryshkov pins = "gpio4", "gpio5", 3004e5813b15SDmitry Baryshkov "gpio6", "gpio7"; 3005e5813b15SDmitry Baryshkov function = "qup1"; 3006e5813b15SDmitry Baryshkov }; 3007e5813b15SDmitry Baryshkov 3008e5813b15SDmitry Baryshkov config { 3009e5813b15SDmitry Baryshkov pins = "gpio4", "gpio5", 3010e5813b15SDmitry Baryshkov "gpio6", "gpio7"; 3011e5813b15SDmitry Baryshkov drive-strength = <6>; 3012e5813b15SDmitry Baryshkov bias-disable; 3013e5813b15SDmitry Baryshkov }; 3014e5813b15SDmitry Baryshkov }; 3015e5813b15SDmitry Baryshkov 3016e5813b15SDmitry Baryshkov qup_spi2_default: qup-spi2-default { 3017e5813b15SDmitry Baryshkov mux { 3018e5813b15SDmitry Baryshkov pins = "gpio115", "gpio116", 3019e5813b15SDmitry Baryshkov "gpio117", "gpio118"; 3020e5813b15SDmitry Baryshkov function = "qup2"; 3021e5813b15SDmitry Baryshkov }; 3022e5813b15SDmitry Baryshkov 3023e5813b15SDmitry Baryshkov config { 3024e5813b15SDmitry Baryshkov pins = "gpio115", "gpio116", 3025e5813b15SDmitry Baryshkov "gpio117", "gpio118"; 3026e5813b15SDmitry Baryshkov drive-strength = <6>; 3027e5813b15SDmitry Baryshkov bias-disable; 3028e5813b15SDmitry Baryshkov }; 3029e5813b15SDmitry Baryshkov }; 3030e5813b15SDmitry Baryshkov 3031e5813b15SDmitry Baryshkov qup_spi3_default: qup-spi3-default { 3032e5813b15SDmitry Baryshkov mux { 3033e5813b15SDmitry Baryshkov pins = "gpio119", "gpio120", 3034e5813b15SDmitry Baryshkov "gpio121", "gpio122"; 3035e5813b15SDmitry Baryshkov function = "qup3"; 3036e5813b15SDmitry Baryshkov }; 3037e5813b15SDmitry Baryshkov 3038e5813b15SDmitry Baryshkov config { 3039e5813b15SDmitry Baryshkov pins = "gpio119", "gpio120", 3040e5813b15SDmitry Baryshkov "gpio121", "gpio122"; 3041e5813b15SDmitry Baryshkov drive-strength = <6>; 3042e5813b15SDmitry Baryshkov bias-disable; 3043e5813b15SDmitry Baryshkov }; 3044e5813b15SDmitry Baryshkov }; 3045e5813b15SDmitry Baryshkov 3046e5813b15SDmitry Baryshkov qup_spi4_default: qup-spi4-default { 3047e5813b15SDmitry Baryshkov mux { 3048e5813b15SDmitry Baryshkov pins = "gpio8", "gpio9", 3049e5813b15SDmitry Baryshkov "gpio10", "gpio11"; 3050e5813b15SDmitry Baryshkov function = "qup4"; 3051e5813b15SDmitry Baryshkov }; 3052e5813b15SDmitry Baryshkov 3053e5813b15SDmitry Baryshkov config { 3054e5813b15SDmitry Baryshkov pins = "gpio8", "gpio9", 3055e5813b15SDmitry Baryshkov "gpio10", "gpio11"; 3056e5813b15SDmitry Baryshkov drive-strength = <6>; 3057e5813b15SDmitry Baryshkov bias-disable; 3058e5813b15SDmitry Baryshkov }; 3059e5813b15SDmitry Baryshkov }; 3060e5813b15SDmitry Baryshkov 3061e5813b15SDmitry Baryshkov qup_spi5_default: qup-spi5-default { 3062e5813b15SDmitry Baryshkov mux { 3063e5813b15SDmitry Baryshkov pins = "gpio12", "gpio13", 3064e5813b15SDmitry Baryshkov "gpio14", "gpio15"; 3065e5813b15SDmitry Baryshkov function = "qup5"; 3066e5813b15SDmitry Baryshkov }; 3067e5813b15SDmitry Baryshkov 3068e5813b15SDmitry Baryshkov config { 3069e5813b15SDmitry Baryshkov pins = "gpio12", "gpio13", 3070e5813b15SDmitry Baryshkov "gpio14", "gpio15"; 3071e5813b15SDmitry Baryshkov drive-strength = <6>; 3072e5813b15SDmitry Baryshkov bias-disable; 3073e5813b15SDmitry Baryshkov }; 3074e5813b15SDmitry Baryshkov }; 3075e5813b15SDmitry Baryshkov 3076e5813b15SDmitry Baryshkov qup_spi6_default: qup-spi6-default { 3077e5813b15SDmitry Baryshkov mux { 3078e5813b15SDmitry Baryshkov pins = "gpio16", "gpio17", 3079e5813b15SDmitry Baryshkov "gpio18", "gpio19"; 3080e5813b15SDmitry Baryshkov function = "qup6"; 3081e5813b15SDmitry Baryshkov }; 3082e5813b15SDmitry Baryshkov 3083e5813b15SDmitry Baryshkov config { 3084e5813b15SDmitry Baryshkov pins = "gpio16", "gpio17", 3085e5813b15SDmitry Baryshkov "gpio18", "gpio19"; 3086e5813b15SDmitry Baryshkov drive-strength = <6>; 3087e5813b15SDmitry Baryshkov bias-disable; 3088e5813b15SDmitry Baryshkov }; 3089e5813b15SDmitry Baryshkov }; 3090e5813b15SDmitry Baryshkov 3091e5813b15SDmitry Baryshkov qup_spi7_default: qup-spi7-default { 3092e5813b15SDmitry Baryshkov mux { 3093e5813b15SDmitry Baryshkov pins = "gpio20", "gpio21", 3094e5813b15SDmitry Baryshkov "gpio22", "gpio23"; 3095e5813b15SDmitry Baryshkov function = "qup7"; 3096e5813b15SDmitry Baryshkov }; 3097e5813b15SDmitry Baryshkov 3098e5813b15SDmitry Baryshkov config { 3099e5813b15SDmitry Baryshkov pins = "gpio20", "gpio21", 3100e5813b15SDmitry Baryshkov "gpio22", "gpio23"; 3101e5813b15SDmitry Baryshkov drive-strength = <6>; 3102e5813b15SDmitry Baryshkov bias-disable; 3103e5813b15SDmitry Baryshkov }; 3104e5813b15SDmitry Baryshkov }; 3105e5813b15SDmitry Baryshkov 3106e5813b15SDmitry Baryshkov qup_spi8_default: qup-spi8-default { 3107e5813b15SDmitry Baryshkov mux { 3108e5813b15SDmitry Baryshkov pins = "gpio24", "gpio25", 3109e5813b15SDmitry Baryshkov "gpio26", "gpio27"; 3110e5813b15SDmitry Baryshkov function = "qup8"; 3111e5813b15SDmitry Baryshkov }; 3112e5813b15SDmitry Baryshkov 3113e5813b15SDmitry Baryshkov config { 3114e5813b15SDmitry Baryshkov pins = "gpio24", "gpio25", 3115e5813b15SDmitry Baryshkov "gpio26", "gpio27"; 3116e5813b15SDmitry Baryshkov drive-strength = <6>; 3117e5813b15SDmitry Baryshkov bias-disable; 3118e5813b15SDmitry Baryshkov }; 3119e5813b15SDmitry Baryshkov }; 3120e5813b15SDmitry Baryshkov 3121e5813b15SDmitry Baryshkov qup_spi9_default: qup-spi9-default { 3122e5813b15SDmitry Baryshkov mux { 3123e5813b15SDmitry Baryshkov pins = "gpio125", "gpio126", 3124e5813b15SDmitry Baryshkov "gpio127", "gpio128"; 3125e5813b15SDmitry Baryshkov function = "qup9"; 3126e5813b15SDmitry Baryshkov }; 3127e5813b15SDmitry Baryshkov 3128e5813b15SDmitry Baryshkov config { 3129e5813b15SDmitry Baryshkov pins = "gpio125", "gpio126", 3130e5813b15SDmitry Baryshkov "gpio127", "gpio128"; 3131e5813b15SDmitry Baryshkov drive-strength = <6>; 3132e5813b15SDmitry Baryshkov bias-disable; 3133e5813b15SDmitry Baryshkov }; 3134e5813b15SDmitry Baryshkov }; 3135e5813b15SDmitry Baryshkov 3136e5813b15SDmitry Baryshkov qup_spi10_default: qup-spi10-default { 3137e5813b15SDmitry Baryshkov mux { 3138e5813b15SDmitry Baryshkov pins = "gpio129", "gpio130", 3139e5813b15SDmitry Baryshkov "gpio131", "gpio132"; 3140e5813b15SDmitry Baryshkov function = "qup10"; 3141e5813b15SDmitry Baryshkov }; 3142e5813b15SDmitry Baryshkov 3143e5813b15SDmitry Baryshkov config { 3144e5813b15SDmitry Baryshkov pins = "gpio129", "gpio130", 3145e5813b15SDmitry Baryshkov "gpio131", "gpio132"; 3146e5813b15SDmitry Baryshkov drive-strength = <6>; 3147e5813b15SDmitry Baryshkov bias-disable; 3148e5813b15SDmitry Baryshkov }; 3149e5813b15SDmitry Baryshkov }; 3150e5813b15SDmitry Baryshkov 3151e5813b15SDmitry Baryshkov qup_spi11_default: qup-spi11-default { 3152e5813b15SDmitry Baryshkov mux { 3153e5813b15SDmitry Baryshkov pins = "gpio60", "gpio61", 3154e5813b15SDmitry Baryshkov "gpio62", "gpio63"; 3155e5813b15SDmitry Baryshkov function = "qup11"; 3156e5813b15SDmitry Baryshkov }; 3157e5813b15SDmitry Baryshkov 3158e5813b15SDmitry Baryshkov config { 3159e5813b15SDmitry Baryshkov pins = "gpio60", "gpio61", 3160e5813b15SDmitry Baryshkov "gpio62", "gpio63"; 3161e5813b15SDmitry Baryshkov drive-strength = <6>; 3162e5813b15SDmitry Baryshkov bias-disable; 3163e5813b15SDmitry Baryshkov }; 3164e5813b15SDmitry Baryshkov }; 3165e5813b15SDmitry Baryshkov 3166e5813b15SDmitry Baryshkov qup_spi12_default: qup-spi12-default { 3167e5813b15SDmitry Baryshkov mux { 3168e5813b15SDmitry Baryshkov pins = "gpio32", "gpio33", 3169e5813b15SDmitry Baryshkov "gpio34", "gpio35"; 3170e5813b15SDmitry Baryshkov function = "qup12"; 3171e5813b15SDmitry Baryshkov }; 3172e5813b15SDmitry Baryshkov 3173e5813b15SDmitry Baryshkov config { 3174e5813b15SDmitry Baryshkov pins = "gpio32", "gpio33", 3175e5813b15SDmitry Baryshkov "gpio34", "gpio35"; 3176e5813b15SDmitry Baryshkov drive-strength = <6>; 3177e5813b15SDmitry Baryshkov bias-disable; 3178e5813b15SDmitry Baryshkov }; 3179e5813b15SDmitry Baryshkov }; 3180e5813b15SDmitry Baryshkov 3181e5813b15SDmitry Baryshkov qup_spi13_default: qup-spi13-default { 3182e5813b15SDmitry Baryshkov mux { 3183e5813b15SDmitry Baryshkov pins = "gpio36", "gpio37", 3184e5813b15SDmitry Baryshkov "gpio38", "gpio39"; 3185e5813b15SDmitry Baryshkov function = "qup13"; 3186e5813b15SDmitry Baryshkov }; 3187e5813b15SDmitry Baryshkov 3188e5813b15SDmitry Baryshkov config { 3189e5813b15SDmitry Baryshkov pins = "gpio36", "gpio37", 3190e5813b15SDmitry Baryshkov "gpio38", "gpio39"; 3191e5813b15SDmitry Baryshkov drive-strength = <6>; 3192e5813b15SDmitry Baryshkov bias-disable; 3193e5813b15SDmitry Baryshkov }; 3194e5813b15SDmitry Baryshkov }; 3195e5813b15SDmitry Baryshkov 3196e5813b15SDmitry Baryshkov qup_spi14_default: qup-spi14-default { 3197e5813b15SDmitry Baryshkov mux { 3198e5813b15SDmitry Baryshkov pins = "gpio40", "gpio41", 3199e5813b15SDmitry Baryshkov "gpio42", "gpio43"; 3200e5813b15SDmitry Baryshkov function = "qup14"; 3201e5813b15SDmitry Baryshkov }; 3202e5813b15SDmitry Baryshkov 3203e5813b15SDmitry Baryshkov config { 3204e5813b15SDmitry Baryshkov pins = "gpio40", "gpio41", 3205e5813b15SDmitry Baryshkov "gpio42", "gpio43"; 3206e5813b15SDmitry Baryshkov drive-strength = <6>; 3207e5813b15SDmitry Baryshkov bias-disable; 3208e5813b15SDmitry Baryshkov }; 3209e5813b15SDmitry Baryshkov }; 3210e5813b15SDmitry Baryshkov 3211e5813b15SDmitry Baryshkov qup_spi15_default: qup-spi15-default { 3212e5813b15SDmitry Baryshkov mux { 3213e5813b15SDmitry Baryshkov pins = "gpio44", "gpio45", 3214e5813b15SDmitry Baryshkov "gpio46", "gpio47"; 3215e5813b15SDmitry Baryshkov function = "qup15"; 3216e5813b15SDmitry Baryshkov }; 3217e5813b15SDmitry Baryshkov 3218e5813b15SDmitry Baryshkov config { 3219e5813b15SDmitry Baryshkov pins = "gpio44", "gpio45", 3220e5813b15SDmitry Baryshkov "gpio46", "gpio47"; 3221e5813b15SDmitry Baryshkov drive-strength = <6>; 3222e5813b15SDmitry Baryshkov bias-disable; 3223e5813b15SDmitry Baryshkov }; 3224e5813b15SDmitry Baryshkov }; 3225e5813b15SDmitry Baryshkov 3226e5813b15SDmitry Baryshkov qup_spi16_default: qup-spi16-default { 3227e5813b15SDmitry Baryshkov mux { 3228e5813b15SDmitry Baryshkov pins = "gpio48", "gpio49", 3229e5813b15SDmitry Baryshkov "gpio50", "gpio51"; 3230e5813b15SDmitry Baryshkov function = "qup16"; 3231e5813b15SDmitry Baryshkov }; 3232e5813b15SDmitry Baryshkov 3233e5813b15SDmitry Baryshkov config { 3234e5813b15SDmitry Baryshkov pins = "gpio48", "gpio49", 3235e5813b15SDmitry Baryshkov "gpio50", "gpio51"; 3236e5813b15SDmitry Baryshkov drive-strength = <6>; 3237e5813b15SDmitry Baryshkov bias-disable; 3238e5813b15SDmitry Baryshkov }; 3239e5813b15SDmitry Baryshkov }; 3240e5813b15SDmitry Baryshkov 3241e5813b15SDmitry Baryshkov qup_spi17_default: qup-spi17-default { 3242e5813b15SDmitry Baryshkov mux { 3243e5813b15SDmitry Baryshkov pins = "gpio52", "gpio53", 3244e5813b15SDmitry Baryshkov "gpio54", "gpio55"; 3245e5813b15SDmitry Baryshkov function = "qup17"; 3246e5813b15SDmitry Baryshkov }; 3247e5813b15SDmitry Baryshkov 3248e5813b15SDmitry Baryshkov config { 3249e5813b15SDmitry Baryshkov pins = "gpio52", "gpio53", 3250e5813b15SDmitry Baryshkov "gpio54", "gpio55"; 3251e5813b15SDmitry Baryshkov drive-strength = <6>; 3252e5813b15SDmitry Baryshkov bias-disable; 3253e5813b15SDmitry Baryshkov }; 3254e5813b15SDmitry Baryshkov }; 3255e5813b15SDmitry Baryshkov 3256e5813b15SDmitry Baryshkov qup_spi18_default: qup-spi18-default { 3257e5813b15SDmitry Baryshkov mux { 3258e5813b15SDmitry Baryshkov pins = "gpio56", "gpio57", 3259e5813b15SDmitry Baryshkov "gpio58", "gpio59"; 3260e5813b15SDmitry Baryshkov function = "qup18"; 3261e5813b15SDmitry Baryshkov }; 3262e5813b15SDmitry Baryshkov 3263e5813b15SDmitry Baryshkov config { 3264e5813b15SDmitry Baryshkov pins = "gpio56", "gpio57", 3265e5813b15SDmitry Baryshkov "gpio58", "gpio59"; 3266e5813b15SDmitry Baryshkov drive-strength = <6>; 3267e5813b15SDmitry Baryshkov bias-disable; 3268e5813b15SDmitry Baryshkov }; 3269e5813b15SDmitry Baryshkov }; 3270e5813b15SDmitry Baryshkov 3271e5813b15SDmitry Baryshkov qup_spi19_default: qup-spi19-default { 3272e5813b15SDmitry Baryshkov mux { 3273e5813b15SDmitry Baryshkov pins = "gpio0", "gpio1", 3274e5813b15SDmitry Baryshkov "gpio2", "gpio3"; 3275e5813b15SDmitry Baryshkov function = "qup19"; 3276e5813b15SDmitry Baryshkov }; 3277e5813b15SDmitry Baryshkov 3278e5813b15SDmitry Baryshkov config { 3279e5813b15SDmitry Baryshkov pins = "gpio0", "gpio1", 3280e5813b15SDmitry Baryshkov "gpio2", "gpio3"; 3281e5813b15SDmitry Baryshkov drive-strength = <6>; 3282e5813b15SDmitry Baryshkov bias-disable; 3283e5813b15SDmitry Baryshkov }; 3284e5813b15SDmitry Baryshkov }; 3285bb1dfb4dSManivannan Sadhasivam 328608a9ae2dSDmitry Baryshkov qup_uart2_default: qup-uart2-default { 328708a9ae2dSDmitry Baryshkov mux { 328808a9ae2dSDmitry Baryshkov pins = "gpio117", "gpio118"; 328908a9ae2dSDmitry Baryshkov function = "qup2"; 329008a9ae2dSDmitry Baryshkov }; 329108a9ae2dSDmitry Baryshkov }; 329208a9ae2dSDmitry Baryshkov 329308a9ae2dSDmitry Baryshkov qup_uart6_default: qup-uart6-default { 329408a9ae2dSDmitry Baryshkov mux { 329508a9ae2dSDmitry Baryshkov pins = "gpio16", "gpio17", 329608a9ae2dSDmitry Baryshkov "gpio18", "gpio19"; 329708a9ae2dSDmitry Baryshkov function = "qup6"; 329808a9ae2dSDmitry Baryshkov }; 329908a9ae2dSDmitry Baryshkov }; 330008a9ae2dSDmitry Baryshkov 3301bb1dfb4dSManivannan Sadhasivam qup_uart12_default: qup-uart12-default { 3302bb1dfb4dSManivannan Sadhasivam mux { 3303bb1dfb4dSManivannan Sadhasivam pins = "gpio34", "gpio35"; 3304bb1dfb4dSManivannan Sadhasivam function = "qup12"; 3305bb1dfb4dSManivannan Sadhasivam }; 3306bb1dfb4dSManivannan Sadhasivam }; 330708a9ae2dSDmitry Baryshkov 330808a9ae2dSDmitry Baryshkov qup_uart17_default: qup-uart17-default { 330908a9ae2dSDmitry Baryshkov mux { 331008a9ae2dSDmitry Baryshkov pins = "gpio52", "gpio53", 331108a9ae2dSDmitry Baryshkov "gpio54", "gpio55"; 331208a9ae2dSDmitry Baryshkov function = "qup17"; 331308a9ae2dSDmitry Baryshkov }; 331408a9ae2dSDmitry Baryshkov }; 331508a9ae2dSDmitry Baryshkov 331608a9ae2dSDmitry Baryshkov qup_uart18_default: qup-uart18-default { 331708a9ae2dSDmitry Baryshkov mux { 331808a9ae2dSDmitry Baryshkov pins = "gpio58", "gpio59"; 331908a9ae2dSDmitry Baryshkov function = "qup18"; 332008a9ae2dSDmitry Baryshkov }; 332108a9ae2dSDmitry Baryshkov }; 3322b657d372SSrinivas Kandagatla 3323b657d372SSrinivas Kandagatla tert_mi2s_active: tert-mi2s-active { 3324b657d372SSrinivas Kandagatla sck { 3325b657d372SSrinivas Kandagatla pins = "gpio133"; 3326b657d372SSrinivas Kandagatla function = "mi2s2_sck"; 3327b657d372SSrinivas Kandagatla drive-strength = <8>; 3328b657d372SSrinivas Kandagatla bias-disable; 3329b657d372SSrinivas Kandagatla }; 3330b657d372SSrinivas Kandagatla 3331b657d372SSrinivas Kandagatla data0 { 3332b657d372SSrinivas Kandagatla pins = "gpio134"; 3333b657d372SSrinivas Kandagatla function = "mi2s2_data0"; 3334b657d372SSrinivas Kandagatla drive-strength = <8>; 3335b657d372SSrinivas Kandagatla bias-disable; 3336b657d372SSrinivas Kandagatla output-high; 3337b657d372SSrinivas Kandagatla }; 3338b657d372SSrinivas Kandagatla 3339b657d372SSrinivas Kandagatla ws { 3340b657d372SSrinivas Kandagatla pins = "gpio135"; 3341b657d372SSrinivas Kandagatla function = "mi2s2_ws"; 3342b657d372SSrinivas Kandagatla drive-strength = <8>; 3343b657d372SSrinivas Kandagatla output-high; 3344b657d372SSrinivas Kandagatla }; 3345b657d372SSrinivas Kandagatla }; 334616951b49SBjorn Andersson }; 334716951b49SBjorn Andersson 3348a89441fcSJonathan Marek apps_smmu: iommu@15000000 { 3349a89441fcSJonathan Marek compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 3350a89441fcSJonathan Marek reg = <0 0x15000000 0 0x100000>; 3351a89441fcSJonathan Marek #iommu-cells = <2>; 3352a89441fcSJonathan Marek #global-interrupts = <2>; 3353a89441fcSJonathan Marek interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3354a89441fcSJonathan Marek <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3355a89441fcSJonathan Marek <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3356a89441fcSJonathan Marek <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3357a89441fcSJonathan Marek <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3358a89441fcSJonathan Marek <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3359a89441fcSJonathan Marek <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3360a89441fcSJonathan Marek <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3361a89441fcSJonathan Marek <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3362a89441fcSJonathan Marek <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3363a89441fcSJonathan Marek <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3364a89441fcSJonathan Marek <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3365a89441fcSJonathan Marek <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3366a89441fcSJonathan Marek <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3367a89441fcSJonathan Marek <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3368a89441fcSJonathan Marek <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3369a89441fcSJonathan Marek <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3370a89441fcSJonathan Marek <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3371a89441fcSJonathan Marek <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3372a89441fcSJonathan Marek <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3373a89441fcSJonathan Marek <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3374a89441fcSJonathan Marek <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3375a89441fcSJonathan Marek <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3376a89441fcSJonathan Marek <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3377a89441fcSJonathan Marek <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3378a89441fcSJonathan Marek <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3379a89441fcSJonathan Marek <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3380a89441fcSJonathan Marek <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3381a89441fcSJonathan Marek <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3382a89441fcSJonathan Marek <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3383a89441fcSJonathan Marek <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3384a89441fcSJonathan Marek <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3385a89441fcSJonathan Marek <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3386a89441fcSJonathan Marek <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3387a89441fcSJonathan Marek <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3388a89441fcSJonathan Marek <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3389a89441fcSJonathan Marek <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3390a89441fcSJonathan Marek <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3391a89441fcSJonathan Marek <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3392a89441fcSJonathan Marek <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3393a89441fcSJonathan Marek <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3394a89441fcSJonathan Marek <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3395a89441fcSJonathan Marek <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3396a89441fcSJonathan Marek <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3397a89441fcSJonathan Marek <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3398a89441fcSJonathan Marek <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3399a89441fcSJonathan Marek <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3400a89441fcSJonathan Marek <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3401a89441fcSJonathan Marek <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3402a89441fcSJonathan Marek <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3403a89441fcSJonathan Marek <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3404a89441fcSJonathan Marek <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3405a89441fcSJonathan Marek <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3406a89441fcSJonathan Marek <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3407a89441fcSJonathan Marek <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3408a89441fcSJonathan Marek <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3409a89441fcSJonathan Marek <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3410a89441fcSJonathan Marek <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3411a89441fcSJonathan Marek <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3412a89441fcSJonathan Marek <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3413a89441fcSJonathan Marek <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3414a89441fcSJonathan Marek <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3415a89441fcSJonathan Marek <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3416a89441fcSJonathan Marek <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3417a89441fcSJonathan Marek <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3418a89441fcSJonathan Marek <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3419a89441fcSJonathan Marek <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3420a89441fcSJonathan Marek <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3421a89441fcSJonathan Marek <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3422a89441fcSJonathan Marek <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3423a89441fcSJonathan Marek <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3424a89441fcSJonathan Marek <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3425a89441fcSJonathan Marek <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3426a89441fcSJonathan Marek <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3427a89441fcSJonathan Marek <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3428a89441fcSJonathan Marek <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3429a89441fcSJonathan Marek <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3430a89441fcSJonathan Marek <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3431a89441fcSJonathan Marek <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3432a89441fcSJonathan Marek <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3433a89441fcSJonathan Marek <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3434a89441fcSJonathan Marek <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3435a89441fcSJonathan Marek <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3436a89441fcSJonathan Marek <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3437a89441fcSJonathan Marek <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3438a89441fcSJonathan Marek <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3439a89441fcSJonathan Marek <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3440a89441fcSJonathan Marek <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3441a89441fcSJonathan Marek <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3442a89441fcSJonathan Marek <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3443a89441fcSJonathan Marek <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3444a89441fcSJonathan Marek <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3445a89441fcSJonathan Marek <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3446a89441fcSJonathan Marek <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3447a89441fcSJonathan Marek <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3448a89441fcSJonathan Marek <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3449a89441fcSJonathan Marek <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3450a89441fcSJonathan Marek <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3451a89441fcSJonathan Marek }; 3452a89441fcSJonathan Marek 345323a89037SBjorn Andersson adsp: remoteproc@17300000 { 345423a89037SBjorn Andersson compatible = "qcom,sm8250-adsp-pas"; 345523a89037SBjorn Andersson reg = <0 0x17300000 0 0x100>; 345623a89037SBjorn Andersson 345723a89037SBjorn Andersson interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 345823a89037SBjorn Andersson <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 345923a89037SBjorn Andersson <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 346023a89037SBjorn Andersson <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 346123a89037SBjorn Andersson <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 346223a89037SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 346323a89037SBjorn Andersson "handover", "stop-ack"; 346423a89037SBjorn Andersson 346523a89037SBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>; 346623a89037SBjorn Andersson clock-names = "xo"; 346723a89037SBjorn Andersson 346823a89037SBjorn Andersson power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, 346923a89037SBjorn Andersson <&rpmhpd SM8250_LCX>, 347023a89037SBjorn Andersson <&rpmhpd SM8250_LMX>; 347123a89037SBjorn Andersson power-domain-names = "load_state", "lcx", "lmx"; 347223a89037SBjorn Andersson 347323a89037SBjorn Andersson memory-region = <&adsp_mem>; 347423a89037SBjorn Andersson 347523a89037SBjorn Andersson qcom,smem-states = <&smp2p_adsp_out 0>; 347623a89037SBjorn Andersson qcom,smem-state-names = "stop"; 347723a89037SBjorn Andersson 347823a89037SBjorn Andersson status = "disabled"; 347923a89037SBjorn Andersson 348023a89037SBjorn Andersson glink-edge { 348123a89037SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 348223a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 348323a89037SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 348423a89037SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_LPASS 348523a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 348623a89037SBjorn Andersson 348723a89037SBjorn Andersson label = "lpass"; 348823a89037SBjorn Andersson qcom,remote-pid = <2>; 348925695808SJonathan Marek 349063e10791SSrinivas Kandagatla apr { 349163e10791SSrinivas Kandagatla compatible = "qcom,apr-v2"; 349263e10791SSrinivas Kandagatla qcom,glink-channels = "apr_audio_svc"; 349363e10791SSrinivas Kandagatla qcom,apr-domain = <APR_DOMAIN_ADSP>; 349463e10791SSrinivas Kandagatla #address-cells = <1>; 349563e10791SSrinivas Kandagatla #size-cells = <0>; 349663e10791SSrinivas Kandagatla 349763e10791SSrinivas Kandagatla apr-service@3 { 349863e10791SSrinivas Kandagatla reg = <APR_SVC_ADSP_CORE>; 349963e10791SSrinivas Kandagatla compatible = "qcom,q6core"; 350063e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 350163e10791SSrinivas Kandagatla }; 350263e10791SSrinivas Kandagatla 350363e10791SSrinivas Kandagatla q6afe: apr-service@4 { 350463e10791SSrinivas Kandagatla compatible = "qcom,q6afe"; 350563e10791SSrinivas Kandagatla reg = <APR_SVC_AFE>; 350663e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 350763e10791SSrinivas Kandagatla q6afedai: dais { 350863e10791SSrinivas Kandagatla compatible = "qcom,q6afe-dais"; 350963e10791SSrinivas Kandagatla #address-cells = <1>; 351063e10791SSrinivas Kandagatla #size-cells = <0>; 351163e10791SSrinivas Kandagatla #sound-dai-cells = <1>; 351263e10791SSrinivas Kandagatla }; 351363e10791SSrinivas Kandagatla 351463e10791SSrinivas Kandagatla q6afecc: cc { 351563e10791SSrinivas Kandagatla compatible = "qcom,q6afe-clocks"; 351663e10791SSrinivas Kandagatla #clock-cells = <2>; 351763e10791SSrinivas Kandagatla }; 351863e10791SSrinivas Kandagatla }; 351963e10791SSrinivas Kandagatla 352063e10791SSrinivas Kandagatla q6asm: apr-service@7 { 352163e10791SSrinivas Kandagatla compatible = "qcom,q6asm"; 352263e10791SSrinivas Kandagatla reg = <APR_SVC_ASM>; 352363e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 352463e10791SSrinivas Kandagatla q6asmdai: dais { 352563e10791SSrinivas Kandagatla compatible = "qcom,q6asm-dais"; 352663e10791SSrinivas Kandagatla #address-cells = <1>; 352763e10791SSrinivas Kandagatla #size-cells = <0>; 352863e10791SSrinivas Kandagatla #sound-dai-cells = <1>; 352963e10791SSrinivas Kandagatla iommus = <&apps_smmu 0x1801 0x0>; 353063e10791SSrinivas Kandagatla }; 353163e10791SSrinivas Kandagatla }; 353263e10791SSrinivas Kandagatla 353363e10791SSrinivas Kandagatla q6adm: apr-service@8 { 353463e10791SSrinivas Kandagatla compatible = "qcom,q6adm"; 353563e10791SSrinivas Kandagatla reg = <APR_SVC_ADM>; 353663e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 353763e10791SSrinivas Kandagatla q6routing: routing { 353863e10791SSrinivas Kandagatla compatible = "qcom,q6adm-routing"; 353963e10791SSrinivas Kandagatla #sound-dai-cells = <0>; 354063e10791SSrinivas Kandagatla }; 354163e10791SSrinivas Kandagatla }; 354263e10791SSrinivas Kandagatla }; 354363e10791SSrinivas Kandagatla 354425695808SJonathan Marek fastrpc { 354525695808SJonathan Marek compatible = "qcom,fastrpc"; 354625695808SJonathan Marek qcom,glink-channels = "fastrpcglink-apps-dsp"; 354725695808SJonathan Marek label = "adsp"; 354825695808SJonathan Marek #address-cells = <1>; 354925695808SJonathan Marek #size-cells = <0>; 355025695808SJonathan Marek 355125695808SJonathan Marek compute-cb@3 { 355225695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 355325695808SJonathan Marek reg = <3>; 355425695808SJonathan Marek iommus = <&apps_smmu 0x1803 0x0>; 355525695808SJonathan Marek }; 355625695808SJonathan Marek 355725695808SJonathan Marek compute-cb@4 { 355825695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 355925695808SJonathan Marek reg = <4>; 356025695808SJonathan Marek iommus = <&apps_smmu 0x1804 0x0>; 356125695808SJonathan Marek }; 356225695808SJonathan Marek 356325695808SJonathan Marek compute-cb@5 { 356425695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 356525695808SJonathan Marek reg = <5>; 356625695808SJonathan Marek iommus = <&apps_smmu 0x1805 0x0>; 356725695808SJonathan Marek }; 356825695808SJonathan Marek }; 356923a89037SBjorn Andersson }; 357023a89037SBjorn Andersson }; 357123a89037SBjorn Andersson 3572b9ec8cbcSJonathan Marek intc: interrupt-controller@17a00000 { 3573b9ec8cbcSJonathan Marek compatible = "arm,gic-v3"; 3574b9ec8cbcSJonathan Marek #interrupt-cells = <3>; 3575b9ec8cbcSJonathan Marek interrupt-controller; 3576b9ec8cbcSJonathan Marek reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3577b9ec8cbcSJonathan Marek <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3578b9ec8cbcSJonathan Marek interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3579b9ec8cbcSJonathan Marek }; 3580b9ec8cbcSJonathan Marek 3581e0d9acceSDmitry Baryshkov watchdog@17c10000 { 3582e0d9acceSDmitry Baryshkov compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 3583e0d9acceSDmitry Baryshkov reg = <0 0x17c10000 0 0x1000>; 3584e0d9acceSDmitry Baryshkov clocks = <&sleep_clk>; 358546a4359fSSai Prakash Ranjan interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3586e0d9acceSDmitry Baryshkov }; 3587e0d9acceSDmitry Baryshkov 3588b9ec8cbcSJonathan Marek timer@17c20000 { 3589b9ec8cbcSJonathan Marek #address-cells = <2>; 3590b9ec8cbcSJonathan Marek #size-cells = <2>; 3591b9ec8cbcSJonathan Marek ranges; 3592b9ec8cbcSJonathan Marek compatible = "arm,armv7-timer-mem"; 3593b9ec8cbcSJonathan Marek reg = <0x0 0x17c20000 0x0 0x1000>; 3594b9ec8cbcSJonathan Marek clock-frequency = <19200000>; 3595b9ec8cbcSJonathan Marek 3596b9ec8cbcSJonathan Marek frame@17c21000 { 3597b9ec8cbcSJonathan Marek frame-number = <0>; 3598b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3599b9ec8cbcSJonathan Marek <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3600b9ec8cbcSJonathan Marek reg = <0x0 0x17c21000 0x0 0x1000>, 3601b9ec8cbcSJonathan Marek <0x0 0x17c22000 0x0 0x1000>; 3602b9ec8cbcSJonathan Marek }; 3603b9ec8cbcSJonathan Marek 3604b9ec8cbcSJonathan Marek frame@17c23000 { 3605b9ec8cbcSJonathan Marek frame-number = <1>; 3606b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3607b9ec8cbcSJonathan Marek reg = <0x0 0x17c23000 0x0 0x1000>; 3608b9ec8cbcSJonathan Marek status = "disabled"; 3609b9ec8cbcSJonathan Marek }; 3610b9ec8cbcSJonathan Marek 3611b9ec8cbcSJonathan Marek frame@17c25000 { 3612b9ec8cbcSJonathan Marek frame-number = <2>; 3613b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3614b9ec8cbcSJonathan Marek reg = <0x0 0x17c25000 0x0 0x1000>; 3615b9ec8cbcSJonathan Marek status = "disabled"; 3616b9ec8cbcSJonathan Marek }; 3617b9ec8cbcSJonathan Marek 3618b9ec8cbcSJonathan Marek frame@17c27000 { 3619b9ec8cbcSJonathan Marek frame-number = <3>; 3620b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3621b9ec8cbcSJonathan Marek reg = <0x0 0x17c27000 0x0 0x1000>; 3622b9ec8cbcSJonathan Marek status = "disabled"; 3623b9ec8cbcSJonathan Marek }; 3624b9ec8cbcSJonathan Marek 3625b9ec8cbcSJonathan Marek frame@17c29000 { 3626b9ec8cbcSJonathan Marek frame-number = <4>; 3627b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3628b9ec8cbcSJonathan Marek reg = <0x0 0x17c29000 0x0 0x1000>; 3629b9ec8cbcSJonathan Marek status = "disabled"; 3630b9ec8cbcSJonathan Marek }; 3631b9ec8cbcSJonathan Marek 3632b9ec8cbcSJonathan Marek frame@17c2b000 { 3633b9ec8cbcSJonathan Marek frame-number = <5>; 3634b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3635b9ec8cbcSJonathan Marek reg = <0x0 0x17c2b000 0x0 0x1000>; 3636b9ec8cbcSJonathan Marek status = "disabled"; 3637b9ec8cbcSJonathan Marek }; 3638b9ec8cbcSJonathan Marek 3639b9ec8cbcSJonathan Marek frame@17c2d000 { 3640b9ec8cbcSJonathan Marek frame-number = <6>; 3641b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3642b9ec8cbcSJonathan Marek reg = <0x0 0x17c2d000 0x0 0x1000>; 3643b9ec8cbcSJonathan Marek status = "disabled"; 3644b9ec8cbcSJonathan Marek }; 3645b9ec8cbcSJonathan Marek }; 3646b9ec8cbcSJonathan Marek 364760378f1aSVenkata Narendra Kumar Gutta apps_rsc: rsc@18200000 { 364860378f1aSVenkata Narendra Kumar Gutta label = "apps_rsc"; 364960378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,rpmh-rsc"; 365060378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x18200000 0x0 0x10000>, 365160378f1aSVenkata Narendra Kumar Gutta <0x0 0x18210000 0x0 0x10000>, 365260378f1aSVenkata Narendra Kumar Gutta <0x0 0x18220000 0x0 0x10000>; 365360378f1aSVenkata Narendra Kumar Gutta reg-names = "drv-0", "drv-1", "drv-2"; 365460378f1aSVenkata Narendra Kumar Gutta interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 365560378f1aSVenkata Narendra Kumar Gutta <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 365660378f1aSVenkata Narendra Kumar Gutta <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 365760378f1aSVenkata Narendra Kumar Gutta qcom,tcs-offset = <0xd00>; 365860378f1aSVenkata Narendra Kumar Gutta qcom,drv-id = <2>; 365960378f1aSVenkata Narendra Kumar Gutta qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 366060378f1aSVenkata Narendra Kumar Gutta <WAKE_TCS 3>, <CONTROL_TCS 1>; 366160378f1aSVenkata Narendra Kumar Gutta 366260378f1aSVenkata Narendra Kumar Gutta rpmhcc: clock-controller { 366360378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,sm8250-rpmh-clk"; 366460378f1aSVenkata Narendra Kumar Gutta #clock-cells = <1>; 366560378f1aSVenkata Narendra Kumar Gutta clock-names = "xo"; 366660378f1aSVenkata Narendra Kumar Gutta clocks = <&xo_board>; 366760378f1aSVenkata Narendra Kumar Gutta }; 3668b6f78e27SBjorn Andersson 3669b6f78e27SBjorn Andersson rpmhpd: power-controller { 3670b6f78e27SBjorn Andersson compatible = "qcom,sm8250-rpmhpd"; 3671b6f78e27SBjorn Andersson #power-domain-cells = <1>; 3672b6f78e27SBjorn Andersson operating-points-v2 = <&rpmhpd_opp_table>; 3673b6f78e27SBjorn Andersson 3674b6f78e27SBjorn Andersson rpmhpd_opp_table: opp-table { 3675b6f78e27SBjorn Andersson compatible = "operating-points-v2"; 3676b6f78e27SBjorn Andersson 3677b6f78e27SBjorn Andersson rpmhpd_opp_ret: opp1 { 3678b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3679b6f78e27SBjorn Andersson }; 3680b6f78e27SBjorn Andersson 3681b6f78e27SBjorn Andersson rpmhpd_opp_min_svs: opp2 { 3682b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3683b6f78e27SBjorn Andersson }; 3684b6f78e27SBjorn Andersson 3685b6f78e27SBjorn Andersson rpmhpd_opp_low_svs: opp3 { 3686b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3687b6f78e27SBjorn Andersson }; 3688b6f78e27SBjorn Andersson 3689b6f78e27SBjorn Andersson rpmhpd_opp_svs: opp4 { 3690b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3691b6f78e27SBjorn Andersson }; 3692b6f78e27SBjorn Andersson 3693b6f78e27SBjorn Andersson rpmhpd_opp_svs_l1: opp5 { 3694b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3695b6f78e27SBjorn Andersson }; 3696b6f78e27SBjorn Andersson 3697b6f78e27SBjorn Andersson rpmhpd_opp_nom: opp6 { 3698b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3699b6f78e27SBjorn Andersson }; 3700b6f78e27SBjorn Andersson 3701b6f78e27SBjorn Andersson rpmhpd_opp_nom_l1: opp7 { 3702b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3703b6f78e27SBjorn Andersson }; 3704b6f78e27SBjorn Andersson 3705b6f78e27SBjorn Andersson rpmhpd_opp_nom_l2: opp8 { 3706b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3707b6f78e27SBjorn Andersson }; 3708b6f78e27SBjorn Andersson 3709b6f78e27SBjorn Andersson rpmhpd_opp_turbo: opp9 { 3710b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3711b6f78e27SBjorn Andersson }; 3712b6f78e27SBjorn Andersson 3713b6f78e27SBjorn Andersson rpmhpd_opp_turbo_l1: opp10 { 3714b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3715b6f78e27SBjorn Andersson }; 3716b6f78e27SBjorn Andersson }; 3717b6f78e27SBjorn Andersson }; 3718e7e41a20SJonathan Marek 3719e7e41a20SJonathan Marek apps_bcm_voter: bcm_voter { 3720e7e41a20SJonathan Marek compatible = "qcom,bcm-voter"; 3721e7e41a20SJonathan Marek }; 372260378f1aSVenkata Narendra Kumar Gutta }; 372379a595bbSSibi Sankar 372479a595bbSSibi Sankar epss_l3: interconnect@18591000 { 372579a595bbSSibi Sankar compatible = "qcom,sm8250-epss-l3"; 372679a595bbSSibi Sankar reg = <0 0x18590000 0 0x1000>; 372779a595bbSSibi Sankar 372879a595bbSSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 372979a595bbSSibi Sankar clock-names = "xo", "alternate"; 373079a595bbSSibi Sankar 373179a595bbSSibi Sankar #interconnect-cells = <1>; 373279a595bbSSibi Sankar }; 373302ae4a0eSBjorn Andersson 373402ae4a0eSBjorn Andersson cpufreq_hw: cpufreq@18591000 { 373502ae4a0eSBjorn Andersson compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 373602ae4a0eSBjorn Andersson reg = <0 0x18591000 0 0x1000>, 373702ae4a0eSBjorn Andersson <0 0x18592000 0 0x1000>, 373802ae4a0eSBjorn Andersson <0 0x18593000 0 0x1000>; 373902ae4a0eSBjorn Andersson reg-names = "freq-domain0", "freq-domain1", 374002ae4a0eSBjorn Andersson "freq-domain2"; 374102ae4a0eSBjorn Andersson 374202ae4a0eSBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 374302ae4a0eSBjorn Andersson clock-names = "xo", "alternate"; 374402ae4a0eSBjorn Andersson 374502ae4a0eSBjorn Andersson #freq-domain-cells = <1>; 374602ae4a0eSBjorn Andersson }; 374760378f1aSVenkata Narendra Kumar Gutta }; 374860378f1aSVenkata Narendra Kumar Gutta 374960378f1aSVenkata Narendra Kumar Gutta timer { 375060378f1aSVenkata Narendra Kumar Gutta compatible = "arm,armv8-timer"; 375160378f1aSVenkata Narendra Kumar Gutta interrupts = <GIC_PPI 13 375260378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 375360378f1aSVenkata Narendra Kumar Gutta <GIC_PPI 14 375460378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 375560378f1aSVenkata Narendra Kumar Gutta <GIC_PPI 11 375660378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3757*29a33495SSai Prakash Ranjan <GIC_PPI 10 375860378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 375960378f1aSVenkata Narendra Kumar Gutta }; 3760bac12f25SAmit Kucheria 3761bac12f25SAmit Kucheria thermal-zones { 3762bac12f25SAmit Kucheria cpu0-thermal { 3763bac12f25SAmit Kucheria polling-delay-passive = <250>; 3764bac12f25SAmit Kucheria polling-delay = <1000>; 3765bac12f25SAmit Kucheria 3766bac12f25SAmit Kucheria thermal-sensors = <&tsens0 1>; 3767bac12f25SAmit Kucheria 3768bac12f25SAmit Kucheria trips { 3769bac12f25SAmit Kucheria cpu0_alert0: trip-point0 { 3770bac12f25SAmit Kucheria temperature = <90000>; 3771bac12f25SAmit Kucheria hysteresis = <2000>; 3772bac12f25SAmit Kucheria type = "passive"; 3773bac12f25SAmit Kucheria }; 3774bac12f25SAmit Kucheria 3775bac12f25SAmit Kucheria cpu0_alert1: trip-point1 { 3776bac12f25SAmit Kucheria temperature = <95000>; 3777bac12f25SAmit Kucheria hysteresis = <2000>; 3778bac12f25SAmit Kucheria type = "passive"; 3779bac12f25SAmit Kucheria }; 3780bac12f25SAmit Kucheria 3781bac12f25SAmit Kucheria cpu0_crit: cpu_crit { 3782bac12f25SAmit Kucheria temperature = <110000>; 3783bac12f25SAmit Kucheria hysteresis = <1000>; 3784bac12f25SAmit Kucheria type = "critical"; 3785bac12f25SAmit Kucheria }; 3786bac12f25SAmit Kucheria }; 3787bac12f25SAmit Kucheria 3788bac12f25SAmit Kucheria cooling-maps { 3789bac12f25SAmit Kucheria map0 { 3790bac12f25SAmit Kucheria trip = <&cpu0_alert0>; 3791bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3792bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3793bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3794bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3795bac12f25SAmit Kucheria }; 3796bac12f25SAmit Kucheria map1 { 3797bac12f25SAmit Kucheria trip = <&cpu0_alert1>; 3798bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3799bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3800bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3801bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3802bac12f25SAmit Kucheria }; 3803bac12f25SAmit Kucheria }; 3804bac12f25SAmit Kucheria }; 3805bac12f25SAmit Kucheria 3806bac12f25SAmit Kucheria cpu1-thermal { 3807bac12f25SAmit Kucheria polling-delay-passive = <250>; 3808bac12f25SAmit Kucheria polling-delay = <1000>; 3809bac12f25SAmit Kucheria 3810bac12f25SAmit Kucheria thermal-sensors = <&tsens0 2>; 3811bac12f25SAmit Kucheria 3812bac12f25SAmit Kucheria trips { 3813bac12f25SAmit Kucheria cpu1_alert0: trip-point0 { 3814bac12f25SAmit Kucheria temperature = <90000>; 3815bac12f25SAmit Kucheria hysteresis = <2000>; 3816bac12f25SAmit Kucheria type = "passive"; 3817bac12f25SAmit Kucheria }; 3818bac12f25SAmit Kucheria 3819bac12f25SAmit Kucheria cpu1_alert1: trip-point1 { 3820bac12f25SAmit Kucheria temperature = <95000>; 3821bac12f25SAmit Kucheria hysteresis = <2000>; 3822bac12f25SAmit Kucheria type = "passive"; 3823bac12f25SAmit Kucheria }; 3824bac12f25SAmit Kucheria 3825bac12f25SAmit Kucheria cpu1_crit: cpu_crit { 3826bac12f25SAmit Kucheria temperature = <110000>; 3827bac12f25SAmit Kucheria hysteresis = <1000>; 3828bac12f25SAmit Kucheria type = "critical"; 3829bac12f25SAmit Kucheria }; 3830bac12f25SAmit Kucheria }; 3831bac12f25SAmit Kucheria 3832bac12f25SAmit Kucheria cooling-maps { 3833bac12f25SAmit Kucheria map0 { 3834bac12f25SAmit Kucheria trip = <&cpu1_alert0>; 3835bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3836bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3837bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3838bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3839bac12f25SAmit Kucheria }; 3840bac12f25SAmit Kucheria map1 { 3841bac12f25SAmit Kucheria trip = <&cpu1_alert1>; 3842bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3843bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3844bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3845bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3846bac12f25SAmit Kucheria }; 3847bac12f25SAmit Kucheria }; 3848bac12f25SAmit Kucheria }; 3849bac12f25SAmit Kucheria 3850bac12f25SAmit Kucheria cpu2-thermal { 3851bac12f25SAmit Kucheria polling-delay-passive = <250>; 3852bac12f25SAmit Kucheria polling-delay = <1000>; 3853bac12f25SAmit Kucheria 3854bac12f25SAmit Kucheria thermal-sensors = <&tsens0 3>; 3855bac12f25SAmit Kucheria 3856bac12f25SAmit Kucheria trips { 3857bac12f25SAmit Kucheria cpu2_alert0: trip-point0 { 3858bac12f25SAmit Kucheria temperature = <90000>; 3859bac12f25SAmit Kucheria hysteresis = <2000>; 3860bac12f25SAmit Kucheria type = "passive"; 3861bac12f25SAmit Kucheria }; 3862bac12f25SAmit Kucheria 3863bac12f25SAmit Kucheria cpu2_alert1: trip-point1 { 3864bac12f25SAmit Kucheria temperature = <95000>; 3865bac12f25SAmit Kucheria hysteresis = <2000>; 3866bac12f25SAmit Kucheria type = "passive"; 3867bac12f25SAmit Kucheria }; 3868bac12f25SAmit Kucheria 3869bac12f25SAmit Kucheria cpu2_crit: cpu_crit { 3870bac12f25SAmit Kucheria temperature = <110000>; 3871bac12f25SAmit Kucheria hysteresis = <1000>; 3872bac12f25SAmit Kucheria type = "critical"; 3873bac12f25SAmit Kucheria }; 3874bac12f25SAmit Kucheria }; 3875bac12f25SAmit Kucheria 3876bac12f25SAmit Kucheria cooling-maps { 3877bac12f25SAmit Kucheria map0 { 3878bac12f25SAmit Kucheria trip = <&cpu2_alert0>; 3879bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3880bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3881bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3882bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3883bac12f25SAmit Kucheria }; 3884bac12f25SAmit Kucheria map1 { 3885bac12f25SAmit Kucheria trip = <&cpu2_alert1>; 3886bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3887bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3888bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3889bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3890bac12f25SAmit Kucheria }; 3891bac12f25SAmit Kucheria }; 3892bac12f25SAmit Kucheria }; 3893bac12f25SAmit Kucheria 3894bac12f25SAmit Kucheria cpu3-thermal { 3895bac12f25SAmit Kucheria polling-delay-passive = <250>; 3896bac12f25SAmit Kucheria polling-delay = <1000>; 3897bac12f25SAmit Kucheria 3898bac12f25SAmit Kucheria thermal-sensors = <&tsens0 4>; 3899bac12f25SAmit Kucheria 3900bac12f25SAmit Kucheria trips { 3901bac12f25SAmit Kucheria cpu3_alert0: trip-point0 { 3902bac12f25SAmit Kucheria temperature = <90000>; 3903bac12f25SAmit Kucheria hysteresis = <2000>; 3904bac12f25SAmit Kucheria type = "passive"; 3905bac12f25SAmit Kucheria }; 3906bac12f25SAmit Kucheria 3907bac12f25SAmit Kucheria cpu3_alert1: trip-point1 { 3908bac12f25SAmit Kucheria temperature = <95000>; 3909bac12f25SAmit Kucheria hysteresis = <2000>; 3910bac12f25SAmit Kucheria type = "passive"; 3911bac12f25SAmit Kucheria }; 3912bac12f25SAmit Kucheria 3913bac12f25SAmit Kucheria cpu3_crit: cpu_crit { 3914bac12f25SAmit Kucheria temperature = <110000>; 3915bac12f25SAmit Kucheria hysteresis = <1000>; 3916bac12f25SAmit Kucheria type = "critical"; 3917bac12f25SAmit Kucheria }; 3918bac12f25SAmit Kucheria }; 3919bac12f25SAmit Kucheria 3920bac12f25SAmit Kucheria cooling-maps { 3921bac12f25SAmit Kucheria map0 { 3922bac12f25SAmit Kucheria trip = <&cpu3_alert0>; 3923bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3924bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3925bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3926bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3927bac12f25SAmit Kucheria }; 3928bac12f25SAmit Kucheria map1 { 3929bac12f25SAmit Kucheria trip = <&cpu3_alert1>; 3930bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3931bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3932bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3933bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3934bac12f25SAmit Kucheria }; 3935bac12f25SAmit Kucheria }; 3936bac12f25SAmit Kucheria }; 3937bac12f25SAmit Kucheria 3938bac12f25SAmit Kucheria cpu4-top-thermal { 3939bac12f25SAmit Kucheria polling-delay-passive = <250>; 3940bac12f25SAmit Kucheria polling-delay = <1000>; 3941bac12f25SAmit Kucheria 3942bac12f25SAmit Kucheria thermal-sensors = <&tsens0 7>; 3943bac12f25SAmit Kucheria 3944bac12f25SAmit Kucheria trips { 3945bac12f25SAmit Kucheria cpu4_top_alert0: trip-point0 { 3946bac12f25SAmit Kucheria temperature = <90000>; 3947bac12f25SAmit Kucheria hysteresis = <2000>; 3948bac12f25SAmit Kucheria type = "passive"; 3949bac12f25SAmit Kucheria }; 3950bac12f25SAmit Kucheria 3951bac12f25SAmit Kucheria cpu4_top_alert1: trip-point1 { 3952bac12f25SAmit Kucheria temperature = <95000>; 3953bac12f25SAmit Kucheria hysteresis = <2000>; 3954bac12f25SAmit Kucheria type = "passive"; 3955bac12f25SAmit Kucheria }; 3956bac12f25SAmit Kucheria 3957bac12f25SAmit Kucheria cpu4_top_crit: cpu_crit { 3958bac12f25SAmit Kucheria temperature = <110000>; 3959bac12f25SAmit Kucheria hysteresis = <1000>; 3960bac12f25SAmit Kucheria type = "critical"; 3961bac12f25SAmit Kucheria }; 3962bac12f25SAmit Kucheria }; 3963bac12f25SAmit Kucheria 3964bac12f25SAmit Kucheria cooling-maps { 3965bac12f25SAmit Kucheria map0 { 3966bac12f25SAmit Kucheria trip = <&cpu4_top_alert0>; 3967bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3968bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3969bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3970bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3971bac12f25SAmit Kucheria }; 3972bac12f25SAmit Kucheria map1 { 3973bac12f25SAmit Kucheria trip = <&cpu4_top_alert1>; 3974bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3975bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3976bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3977bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3978bac12f25SAmit Kucheria }; 3979bac12f25SAmit Kucheria }; 3980bac12f25SAmit Kucheria }; 3981bac12f25SAmit Kucheria 3982bac12f25SAmit Kucheria cpu5-top-thermal { 3983bac12f25SAmit Kucheria polling-delay-passive = <250>; 3984bac12f25SAmit Kucheria polling-delay = <1000>; 3985bac12f25SAmit Kucheria 3986bac12f25SAmit Kucheria thermal-sensors = <&tsens0 8>; 3987bac12f25SAmit Kucheria 3988bac12f25SAmit Kucheria trips { 3989bac12f25SAmit Kucheria cpu5_top_alert0: trip-point0 { 3990bac12f25SAmit Kucheria temperature = <90000>; 3991bac12f25SAmit Kucheria hysteresis = <2000>; 3992bac12f25SAmit Kucheria type = "passive"; 3993bac12f25SAmit Kucheria }; 3994bac12f25SAmit Kucheria 3995bac12f25SAmit Kucheria cpu5_top_alert1: trip-point1 { 3996bac12f25SAmit Kucheria temperature = <95000>; 3997bac12f25SAmit Kucheria hysteresis = <2000>; 3998bac12f25SAmit Kucheria type = "passive"; 3999bac12f25SAmit Kucheria }; 4000bac12f25SAmit Kucheria 4001bac12f25SAmit Kucheria cpu5_top_crit: cpu_crit { 4002bac12f25SAmit Kucheria temperature = <110000>; 4003bac12f25SAmit Kucheria hysteresis = <1000>; 4004bac12f25SAmit Kucheria type = "critical"; 4005bac12f25SAmit Kucheria }; 4006bac12f25SAmit Kucheria }; 4007bac12f25SAmit Kucheria 4008bac12f25SAmit Kucheria cooling-maps { 4009bac12f25SAmit Kucheria map0 { 4010bac12f25SAmit Kucheria trip = <&cpu5_top_alert0>; 4011bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4012bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4013bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4014bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4015bac12f25SAmit Kucheria }; 4016bac12f25SAmit Kucheria map1 { 4017bac12f25SAmit Kucheria trip = <&cpu5_top_alert1>; 4018bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4019bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4020bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4021bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4022bac12f25SAmit Kucheria }; 4023bac12f25SAmit Kucheria }; 4024bac12f25SAmit Kucheria }; 4025bac12f25SAmit Kucheria 4026bac12f25SAmit Kucheria cpu6-top-thermal { 4027bac12f25SAmit Kucheria polling-delay-passive = <250>; 4028bac12f25SAmit Kucheria polling-delay = <1000>; 4029bac12f25SAmit Kucheria 4030bac12f25SAmit Kucheria thermal-sensors = <&tsens0 9>; 4031bac12f25SAmit Kucheria 4032bac12f25SAmit Kucheria trips { 4033bac12f25SAmit Kucheria cpu6_top_alert0: trip-point0 { 4034bac12f25SAmit Kucheria temperature = <90000>; 4035bac12f25SAmit Kucheria hysteresis = <2000>; 4036bac12f25SAmit Kucheria type = "passive"; 4037bac12f25SAmit Kucheria }; 4038bac12f25SAmit Kucheria 4039bac12f25SAmit Kucheria cpu6_top_alert1: trip-point1 { 4040bac12f25SAmit Kucheria temperature = <95000>; 4041bac12f25SAmit Kucheria hysteresis = <2000>; 4042bac12f25SAmit Kucheria type = "passive"; 4043bac12f25SAmit Kucheria }; 4044bac12f25SAmit Kucheria 4045bac12f25SAmit Kucheria cpu6_top_crit: cpu_crit { 4046bac12f25SAmit Kucheria temperature = <110000>; 4047bac12f25SAmit Kucheria hysteresis = <1000>; 4048bac12f25SAmit Kucheria type = "critical"; 4049bac12f25SAmit Kucheria }; 4050bac12f25SAmit Kucheria }; 4051bac12f25SAmit Kucheria 4052bac12f25SAmit Kucheria cooling-maps { 4053bac12f25SAmit Kucheria map0 { 4054bac12f25SAmit Kucheria trip = <&cpu6_top_alert0>; 4055bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4056bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4057bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4058bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4059bac12f25SAmit Kucheria }; 4060bac12f25SAmit Kucheria map1 { 4061bac12f25SAmit Kucheria trip = <&cpu6_top_alert1>; 4062bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4063bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4064bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4065bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4066bac12f25SAmit Kucheria }; 4067bac12f25SAmit Kucheria }; 4068bac12f25SAmit Kucheria }; 4069bac12f25SAmit Kucheria 4070bac12f25SAmit Kucheria cpu7-top-thermal { 4071bac12f25SAmit Kucheria polling-delay-passive = <250>; 4072bac12f25SAmit Kucheria polling-delay = <1000>; 4073bac12f25SAmit Kucheria 4074bac12f25SAmit Kucheria thermal-sensors = <&tsens0 10>; 4075bac12f25SAmit Kucheria 4076bac12f25SAmit Kucheria trips { 4077bac12f25SAmit Kucheria cpu7_top_alert0: trip-point0 { 4078bac12f25SAmit Kucheria temperature = <90000>; 4079bac12f25SAmit Kucheria hysteresis = <2000>; 4080bac12f25SAmit Kucheria type = "passive"; 4081bac12f25SAmit Kucheria }; 4082bac12f25SAmit Kucheria 4083bac12f25SAmit Kucheria cpu7_top_alert1: trip-point1 { 4084bac12f25SAmit Kucheria temperature = <95000>; 4085bac12f25SAmit Kucheria hysteresis = <2000>; 4086bac12f25SAmit Kucheria type = "passive"; 4087bac12f25SAmit Kucheria }; 4088bac12f25SAmit Kucheria 4089bac12f25SAmit Kucheria cpu7_top_crit: cpu_crit { 4090bac12f25SAmit Kucheria temperature = <110000>; 4091bac12f25SAmit Kucheria hysteresis = <1000>; 4092bac12f25SAmit Kucheria type = "critical"; 4093bac12f25SAmit Kucheria }; 4094bac12f25SAmit Kucheria }; 4095bac12f25SAmit Kucheria 4096bac12f25SAmit Kucheria cooling-maps { 4097bac12f25SAmit Kucheria map0 { 4098bac12f25SAmit Kucheria trip = <&cpu7_top_alert0>; 4099bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4100bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4101bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4102bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4103bac12f25SAmit Kucheria }; 4104bac12f25SAmit Kucheria map1 { 4105bac12f25SAmit Kucheria trip = <&cpu7_top_alert1>; 4106bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4107bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4108bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4109bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4110bac12f25SAmit Kucheria }; 4111bac12f25SAmit Kucheria }; 4112bac12f25SAmit Kucheria }; 4113bac12f25SAmit Kucheria 4114bac12f25SAmit Kucheria cpu4-bottom-thermal { 4115bac12f25SAmit Kucheria polling-delay-passive = <250>; 4116bac12f25SAmit Kucheria polling-delay = <1000>; 4117bac12f25SAmit Kucheria 4118bac12f25SAmit Kucheria thermal-sensors = <&tsens0 11>; 4119bac12f25SAmit Kucheria 4120bac12f25SAmit Kucheria trips { 4121bac12f25SAmit Kucheria cpu4_bottom_alert0: trip-point0 { 4122bac12f25SAmit Kucheria temperature = <90000>; 4123bac12f25SAmit Kucheria hysteresis = <2000>; 4124bac12f25SAmit Kucheria type = "passive"; 4125bac12f25SAmit Kucheria }; 4126bac12f25SAmit Kucheria 4127bac12f25SAmit Kucheria cpu4_bottom_alert1: trip-point1 { 4128bac12f25SAmit Kucheria temperature = <95000>; 4129bac12f25SAmit Kucheria hysteresis = <2000>; 4130bac12f25SAmit Kucheria type = "passive"; 4131bac12f25SAmit Kucheria }; 4132bac12f25SAmit Kucheria 4133bac12f25SAmit Kucheria cpu4_bottom_crit: cpu_crit { 4134bac12f25SAmit Kucheria temperature = <110000>; 4135bac12f25SAmit Kucheria hysteresis = <1000>; 4136bac12f25SAmit Kucheria type = "critical"; 4137bac12f25SAmit Kucheria }; 4138bac12f25SAmit Kucheria }; 4139bac12f25SAmit Kucheria 4140bac12f25SAmit Kucheria cooling-maps { 4141bac12f25SAmit Kucheria map0 { 4142bac12f25SAmit Kucheria trip = <&cpu4_bottom_alert0>; 4143bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4144bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4145bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4146bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4147bac12f25SAmit Kucheria }; 4148bac12f25SAmit Kucheria map1 { 4149bac12f25SAmit Kucheria trip = <&cpu4_bottom_alert1>; 4150bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4151bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4152bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4153bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4154bac12f25SAmit Kucheria }; 4155bac12f25SAmit Kucheria }; 4156bac12f25SAmit Kucheria }; 4157bac12f25SAmit Kucheria 4158bac12f25SAmit Kucheria cpu5-bottom-thermal { 4159bac12f25SAmit Kucheria polling-delay-passive = <250>; 4160bac12f25SAmit Kucheria polling-delay = <1000>; 4161bac12f25SAmit Kucheria 4162bac12f25SAmit Kucheria thermal-sensors = <&tsens0 12>; 4163bac12f25SAmit Kucheria 4164bac12f25SAmit Kucheria trips { 4165bac12f25SAmit Kucheria cpu5_bottom_alert0: trip-point0 { 4166bac12f25SAmit Kucheria temperature = <90000>; 4167bac12f25SAmit Kucheria hysteresis = <2000>; 4168bac12f25SAmit Kucheria type = "passive"; 4169bac12f25SAmit Kucheria }; 4170bac12f25SAmit Kucheria 4171bac12f25SAmit Kucheria cpu5_bottom_alert1: trip-point1 { 4172bac12f25SAmit Kucheria temperature = <95000>; 4173bac12f25SAmit Kucheria hysteresis = <2000>; 4174bac12f25SAmit Kucheria type = "passive"; 4175bac12f25SAmit Kucheria }; 4176bac12f25SAmit Kucheria 4177bac12f25SAmit Kucheria cpu5_bottom_crit: cpu_crit { 4178bac12f25SAmit Kucheria temperature = <110000>; 4179bac12f25SAmit Kucheria hysteresis = <1000>; 4180bac12f25SAmit Kucheria type = "critical"; 4181bac12f25SAmit Kucheria }; 4182bac12f25SAmit Kucheria }; 4183bac12f25SAmit Kucheria 4184bac12f25SAmit Kucheria cooling-maps { 4185bac12f25SAmit Kucheria map0 { 4186bac12f25SAmit Kucheria trip = <&cpu5_bottom_alert0>; 4187bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4188bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4189bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4190bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4191bac12f25SAmit Kucheria }; 4192bac12f25SAmit Kucheria map1 { 4193bac12f25SAmit Kucheria trip = <&cpu5_bottom_alert1>; 4194bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4195bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4196bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4197bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4198bac12f25SAmit Kucheria }; 4199bac12f25SAmit Kucheria }; 4200bac12f25SAmit Kucheria }; 4201bac12f25SAmit Kucheria 4202bac12f25SAmit Kucheria cpu6-bottom-thermal { 4203bac12f25SAmit Kucheria polling-delay-passive = <250>; 4204bac12f25SAmit Kucheria polling-delay = <1000>; 4205bac12f25SAmit Kucheria 4206bac12f25SAmit Kucheria thermal-sensors = <&tsens0 13>; 4207bac12f25SAmit Kucheria 4208bac12f25SAmit Kucheria trips { 4209bac12f25SAmit Kucheria cpu6_bottom_alert0: trip-point0 { 4210bac12f25SAmit Kucheria temperature = <90000>; 4211bac12f25SAmit Kucheria hysteresis = <2000>; 4212bac12f25SAmit Kucheria type = "passive"; 4213bac12f25SAmit Kucheria }; 4214bac12f25SAmit Kucheria 4215bac12f25SAmit Kucheria cpu6_bottom_alert1: trip-point1 { 4216bac12f25SAmit Kucheria temperature = <95000>; 4217bac12f25SAmit Kucheria hysteresis = <2000>; 4218bac12f25SAmit Kucheria type = "passive"; 4219bac12f25SAmit Kucheria }; 4220bac12f25SAmit Kucheria 4221bac12f25SAmit Kucheria cpu6_bottom_crit: cpu_crit { 4222bac12f25SAmit Kucheria temperature = <110000>; 4223bac12f25SAmit Kucheria hysteresis = <1000>; 4224bac12f25SAmit Kucheria type = "critical"; 4225bac12f25SAmit Kucheria }; 4226bac12f25SAmit Kucheria }; 4227bac12f25SAmit Kucheria 4228bac12f25SAmit Kucheria cooling-maps { 4229bac12f25SAmit Kucheria map0 { 4230bac12f25SAmit Kucheria trip = <&cpu6_bottom_alert0>; 4231bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4232bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4233bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4234bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4235bac12f25SAmit Kucheria }; 4236bac12f25SAmit Kucheria map1 { 4237bac12f25SAmit Kucheria trip = <&cpu6_bottom_alert1>; 4238bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4239bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4240bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4241bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4242bac12f25SAmit Kucheria }; 4243bac12f25SAmit Kucheria }; 4244bac12f25SAmit Kucheria }; 4245bac12f25SAmit Kucheria 4246bac12f25SAmit Kucheria cpu7-bottom-thermal { 4247bac12f25SAmit Kucheria polling-delay-passive = <250>; 4248bac12f25SAmit Kucheria polling-delay = <1000>; 4249bac12f25SAmit Kucheria 4250bac12f25SAmit Kucheria thermal-sensors = <&tsens0 14>; 4251bac12f25SAmit Kucheria 4252bac12f25SAmit Kucheria trips { 4253bac12f25SAmit Kucheria cpu7_bottom_alert0: trip-point0 { 4254bac12f25SAmit Kucheria temperature = <90000>; 4255bac12f25SAmit Kucheria hysteresis = <2000>; 4256bac12f25SAmit Kucheria type = "passive"; 4257bac12f25SAmit Kucheria }; 4258bac12f25SAmit Kucheria 4259bac12f25SAmit Kucheria cpu7_bottom_alert1: trip-point1 { 4260bac12f25SAmit Kucheria temperature = <95000>; 4261bac12f25SAmit Kucheria hysteresis = <2000>; 4262bac12f25SAmit Kucheria type = "passive"; 4263bac12f25SAmit Kucheria }; 4264bac12f25SAmit Kucheria 4265bac12f25SAmit Kucheria cpu7_bottom_crit: cpu_crit { 4266bac12f25SAmit Kucheria temperature = <110000>; 4267bac12f25SAmit Kucheria hysteresis = <1000>; 4268bac12f25SAmit Kucheria type = "critical"; 4269bac12f25SAmit Kucheria }; 4270bac12f25SAmit Kucheria }; 4271bac12f25SAmit Kucheria 4272bac12f25SAmit Kucheria cooling-maps { 4273bac12f25SAmit Kucheria map0 { 4274bac12f25SAmit Kucheria trip = <&cpu7_bottom_alert0>; 4275bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4276bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4277bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4278bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4279bac12f25SAmit Kucheria }; 4280bac12f25SAmit Kucheria map1 { 4281bac12f25SAmit Kucheria trip = <&cpu7_bottom_alert1>; 4282bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4283bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4284bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4285bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4286bac12f25SAmit Kucheria }; 4287bac12f25SAmit Kucheria }; 4288bac12f25SAmit Kucheria }; 4289bac12f25SAmit Kucheria 4290bac12f25SAmit Kucheria aoss0-thermal { 4291bac12f25SAmit Kucheria polling-delay-passive = <250>; 4292bac12f25SAmit Kucheria polling-delay = <1000>; 4293bac12f25SAmit Kucheria 4294bac12f25SAmit Kucheria thermal-sensors = <&tsens0 0>; 4295bac12f25SAmit Kucheria 4296bac12f25SAmit Kucheria trips { 4297bac12f25SAmit Kucheria aoss0_alert0: trip-point0 { 4298bac12f25SAmit Kucheria temperature = <90000>; 4299bac12f25SAmit Kucheria hysteresis = <2000>; 4300bac12f25SAmit Kucheria type = "hot"; 4301bac12f25SAmit Kucheria }; 4302bac12f25SAmit Kucheria }; 4303bac12f25SAmit Kucheria }; 4304bac12f25SAmit Kucheria 4305bac12f25SAmit Kucheria cluster0-thermal { 4306bac12f25SAmit Kucheria polling-delay-passive = <250>; 4307bac12f25SAmit Kucheria polling-delay = <1000>; 4308bac12f25SAmit Kucheria 4309bac12f25SAmit Kucheria thermal-sensors = <&tsens0 5>; 4310bac12f25SAmit Kucheria 4311bac12f25SAmit Kucheria trips { 4312bac12f25SAmit Kucheria cluster0_alert0: trip-point0 { 4313bac12f25SAmit Kucheria temperature = <90000>; 4314bac12f25SAmit Kucheria hysteresis = <2000>; 4315bac12f25SAmit Kucheria type = "hot"; 4316bac12f25SAmit Kucheria }; 4317bac12f25SAmit Kucheria cluster0_crit: cluster0_crit { 4318bac12f25SAmit Kucheria temperature = <110000>; 4319bac12f25SAmit Kucheria hysteresis = <2000>; 4320bac12f25SAmit Kucheria type = "critical"; 4321bac12f25SAmit Kucheria }; 4322bac12f25SAmit Kucheria }; 4323bac12f25SAmit Kucheria }; 4324bac12f25SAmit Kucheria 4325bac12f25SAmit Kucheria cluster1-thermal { 4326bac12f25SAmit Kucheria polling-delay-passive = <250>; 4327bac12f25SAmit Kucheria polling-delay = <1000>; 4328bac12f25SAmit Kucheria 4329bac12f25SAmit Kucheria thermal-sensors = <&tsens0 6>; 4330bac12f25SAmit Kucheria 4331bac12f25SAmit Kucheria trips { 4332bac12f25SAmit Kucheria cluster1_alert0: trip-point0 { 4333bac12f25SAmit Kucheria temperature = <90000>; 4334bac12f25SAmit Kucheria hysteresis = <2000>; 4335bac12f25SAmit Kucheria type = "hot"; 4336bac12f25SAmit Kucheria }; 4337bac12f25SAmit Kucheria cluster1_crit: cluster1_crit { 4338bac12f25SAmit Kucheria temperature = <110000>; 4339bac12f25SAmit Kucheria hysteresis = <2000>; 4340bac12f25SAmit Kucheria type = "critical"; 4341bac12f25SAmit Kucheria }; 4342bac12f25SAmit Kucheria }; 4343bac12f25SAmit Kucheria }; 4344bac12f25SAmit Kucheria 4345bac12f25SAmit Kucheria gpu-thermal-top { 4346bac12f25SAmit Kucheria polling-delay-passive = <250>; 4347bac12f25SAmit Kucheria polling-delay = <1000>; 4348bac12f25SAmit Kucheria 4349bac12f25SAmit Kucheria thermal-sensors = <&tsens0 15>; 4350bac12f25SAmit Kucheria 4351bac12f25SAmit Kucheria trips { 4352bac12f25SAmit Kucheria gpu1_alert0: trip-point0 { 4353bac12f25SAmit Kucheria temperature = <90000>; 4354bac12f25SAmit Kucheria hysteresis = <2000>; 4355bac12f25SAmit Kucheria type = "hot"; 4356bac12f25SAmit Kucheria }; 4357bac12f25SAmit Kucheria }; 4358bac12f25SAmit Kucheria }; 4359bac12f25SAmit Kucheria 4360bac12f25SAmit Kucheria aoss1-thermal { 4361bac12f25SAmit Kucheria polling-delay-passive = <250>; 4362bac12f25SAmit Kucheria polling-delay = <1000>; 4363bac12f25SAmit Kucheria 4364bac12f25SAmit Kucheria thermal-sensors = <&tsens1 0>; 4365bac12f25SAmit Kucheria 4366bac12f25SAmit Kucheria trips { 4367bac12f25SAmit Kucheria aoss1_alert0: trip-point0 { 4368bac12f25SAmit Kucheria temperature = <90000>; 4369bac12f25SAmit Kucheria hysteresis = <2000>; 4370bac12f25SAmit Kucheria type = "hot"; 4371bac12f25SAmit Kucheria }; 4372bac12f25SAmit Kucheria }; 4373bac12f25SAmit Kucheria }; 4374bac12f25SAmit Kucheria 4375bac12f25SAmit Kucheria wlan-thermal { 4376bac12f25SAmit Kucheria polling-delay-passive = <250>; 4377bac12f25SAmit Kucheria polling-delay = <1000>; 4378bac12f25SAmit Kucheria 4379bac12f25SAmit Kucheria thermal-sensors = <&tsens1 1>; 4380bac12f25SAmit Kucheria 4381bac12f25SAmit Kucheria trips { 4382bac12f25SAmit Kucheria wlan_alert0: trip-point0 { 4383bac12f25SAmit Kucheria temperature = <90000>; 4384bac12f25SAmit Kucheria hysteresis = <2000>; 4385bac12f25SAmit Kucheria type = "hot"; 4386bac12f25SAmit Kucheria }; 4387bac12f25SAmit Kucheria }; 4388bac12f25SAmit Kucheria }; 4389bac12f25SAmit Kucheria 4390bac12f25SAmit Kucheria video-thermal { 4391bac12f25SAmit Kucheria polling-delay-passive = <250>; 4392bac12f25SAmit Kucheria polling-delay = <1000>; 4393bac12f25SAmit Kucheria 4394bac12f25SAmit Kucheria thermal-sensors = <&tsens1 2>; 4395bac12f25SAmit Kucheria 4396bac12f25SAmit Kucheria trips { 4397bac12f25SAmit Kucheria video_alert0: trip-point0 { 4398bac12f25SAmit Kucheria temperature = <90000>; 4399bac12f25SAmit Kucheria hysteresis = <2000>; 4400bac12f25SAmit Kucheria type = "hot"; 4401bac12f25SAmit Kucheria }; 4402bac12f25SAmit Kucheria }; 4403bac12f25SAmit Kucheria }; 4404bac12f25SAmit Kucheria 4405bac12f25SAmit Kucheria mem-thermal { 4406bac12f25SAmit Kucheria polling-delay-passive = <250>; 4407bac12f25SAmit Kucheria polling-delay = <1000>; 4408bac12f25SAmit Kucheria 4409bac12f25SAmit Kucheria thermal-sensors = <&tsens1 3>; 4410bac12f25SAmit Kucheria 4411bac12f25SAmit Kucheria trips { 4412bac12f25SAmit Kucheria mem_alert0: trip-point0 { 4413bac12f25SAmit Kucheria temperature = <90000>; 4414bac12f25SAmit Kucheria hysteresis = <2000>; 4415bac12f25SAmit Kucheria type = "hot"; 4416bac12f25SAmit Kucheria }; 4417bac12f25SAmit Kucheria }; 4418bac12f25SAmit Kucheria }; 4419bac12f25SAmit Kucheria 4420bac12f25SAmit Kucheria q6-hvx-thermal { 4421bac12f25SAmit Kucheria polling-delay-passive = <250>; 4422bac12f25SAmit Kucheria polling-delay = <1000>; 4423bac12f25SAmit Kucheria 4424bac12f25SAmit Kucheria thermal-sensors = <&tsens1 4>; 4425bac12f25SAmit Kucheria 4426bac12f25SAmit Kucheria trips { 4427bac12f25SAmit Kucheria q6_hvx_alert0: trip-point0 { 4428bac12f25SAmit Kucheria temperature = <90000>; 4429bac12f25SAmit Kucheria hysteresis = <2000>; 4430bac12f25SAmit Kucheria type = "hot"; 4431bac12f25SAmit Kucheria }; 4432bac12f25SAmit Kucheria }; 4433bac12f25SAmit Kucheria }; 4434bac12f25SAmit Kucheria 4435bac12f25SAmit Kucheria camera-thermal { 4436bac12f25SAmit Kucheria polling-delay-passive = <250>; 4437bac12f25SAmit Kucheria polling-delay = <1000>; 4438bac12f25SAmit Kucheria 4439bac12f25SAmit Kucheria thermal-sensors = <&tsens1 5>; 4440bac12f25SAmit Kucheria 4441bac12f25SAmit Kucheria trips { 4442bac12f25SAmit Kucheria camera_alert0: trip-point0 { 4443bac12f25SAmit Kucheria temperature = <90000>; 4444bac12f25SAmit Kucheria hysteresis = <2000>; 4445bac12f25SAmit Kucheria type = "hot"; 4446bac12f25SAmit Kucheria }; 4447bac12f25SAmit Kucheria }; 4448bac12f25SAmit Kucheria }; 4449bac12f25SAmit Kucheria 4450bac12f25SAmit Kucheria compute-thermal { 4451bac12f25SAmit Kucheria polling-delay-passive = <250>; 4452bac12f25SAmit Kucheria polling-delay = <1000>; 4453bac12f25SAmit Kucheria 4454bac12f25SAmit Kucheria thermal-sensors = <&tsens1 6>; 4455bac12f25SAmit Kucheria 4456bac12f25SAmit Kucheria trips { 4457bac12f25SAmit Kucheria compute_alert0: trip-point0 { 4458bac12f25SAmit Kucheria temperature = <90000>; 4459bac12f25SAmit Kucheria hysteresis = <2000>; 4460bac12f25SAmit Kucheria type = "hot"; 4461bac12f25SAmit Kucheria }; 4462bac12f25SAmit Kucheria }; 4463bac12f25SAmit Kucheria }; 4464bac12f25SAmit Kucheria 4465bac12f25SAmit Kucheria npu-thermal { 4466bac12f25SAmit Kucheria polling-delay-passive = <250>; 4467bac12f25SAmit Kucheria polling-delay = <1000>; 4468bac12f25SAmit Kucheria 4469bac12f25SAmit Kucheria thermal-sensors = <&tsens1 7>; 4470bac12f25SAmit Kucheria 4471bac12f25SAmit Kucheria trips { 4472bac12f25SAmit Kucheria npu_alert0: trip-point0 { 4473bac12f25SAmit Kucheria temperature = <90000>; 4474bac12f25SAmit Kucheria hysteresis = <2000>; 4475bac12f25SAmit Kucheria type = "hot"; 4476bac12f25SAmit Kucheria }; 4477bac12f25SAmit Kucheria }; 4478bac12f25SAmit Kucheria }; 4479bac12f25SAmit Kucheria 4480bac12f25SAmit Kucheria gpu-thermal-bottom { 4481bac12f25SAmit Kucheria polling-delay-passive = <250>; 4482bac12f25SAmit Kucheria polling-delay = <1000>; 4483bac12f25SAmit Kucheria 4484bac12f25SAmit Kucheria thermal-sensors = <&tsens1 8>; 4485bac12f25SAmit Kucheria 4486bac12f25SAmit Kucheria trips { 4487bac12f25SAmit Kucheria gpu2_alert0: trip-point0 { 4488bac12f25SAmit Kucheria temperature = <90000>; 4489bac12f25SAmit Kucheria hysteresis = <2000>; 4490bac12f25SAmit Kucheria type = "hot"; 4491bac12f25SAmit Kucheria }; 4492bac12f25SAmit Kucheria }; 4493bac12f25SAmit Kucheria }; 4494bac12f25SAmit Kucheria }; 449560378f1aSVenkata Narendra Kumar Gutta}; 4496