160378f1aSVenkata Narendra Kumar Gutta// SPDX-License-Identifier: BSD-3-Clause 260378f1aSVenkata Narendra Kumar Gutta/* 360378f1aSVenkata Narendra Kumar Gutta * Copyright (c) 2020, The Linux Foundation. All rights reserved. 460378f1aSVenkata Narendra Kumar Gutta */ 560378f1aSVenkata Narendra Kumar Gutta 660378f1aSVenkata Narendra Kumar Gutta#include <dt-bindings/interrupt-controller/arm-gic.h> 77c1dffd4SDmitry Baryshkov#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8b7e2fba0SBryan O'Donoghue#include <dt-bindings/clock/qcom,gcc-sm8250.h> 90e6aa9dbSJonathan Marek#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 1060378f1aSVenkata Narendra Kumar Gutta#include <dt-bindings/clock/qcom,rpmh.h> 1115049bb5SKonrad Dybcio#include <dt-bindings/dma/qcom-gpi.h> 1275948800SKonrad Dybcio#include <dt-bindings/gpio/gpio.h> 1379a595bbSSibi Sankar#include <dt-bindings/interconnect/qcom,osm-l3.h> 147c1dffd4SDmitry Baryshkov#include <dt-bindings/interconnect/qcom,sm8250.h> 15e5361e75SBjorn Andersson#include <dt-bindings/mailbox/qcom-ipcc.h> 16b6f78e27SBjorn Andersson#include <dt-bindings/power/qcom-rpmpd.h> 1763e10791SSrinivas Kandagatla#include <dt-bindings/soc/qcom,apr.h> 1860378f1aSVenkata Narendra Kumar Gutta#include <dt-bindings/soc/qcom,rpmh-rsc.h> 1963e10791SSrinivas Kandagatla#include <dt-bindings/sound/qcom,q6afe.h> 20bac12f25SAmit Kucheria#include <dt-bindings/thermal/thermal.h> 215b9ec225Sjonathan@marek.ca#include <dt-bindings/clock/qcom,videocc-sm8250.h> 2260378f1aSVenkata Narendra Kumar Gutta 2360378f1aSVenkata Narendra Kumar Gutta/ { 2460378f1aSVenkata Narendra Kumar Gutta interrupt-parent = <&intc>; 2560378f1aSVenkata Narendra Kumar Gutta 2660378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 2760378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 2860378f1aSVenkata Narendra Kumar Gutta 29e5813b15SDmitry Baryshkov aliases { 30e5813b15SDmitry Baryshkov i2c0 = &i2c0; 31e5813b15SDmitry Baryshkov i2c1 = &i2c1; 32e5813b15SDmitry Baryshkov i2c2 = &i2c2; 33e5813b15SDmitry Baryshkov i2c3 = &i2c3; 34e5813b15SDmitry Baryshkov i2c4 = &i2c4; 35e5813b15SDmitry Baryshkov i2c5 = &i2c5; 36e5813b15SDmitry Baryshkov i2c6 = &i2c6; 37e5813b15SDmitry Baryshkov i2c7 = &i2c7; 38e5813b15SDmitry Baryshkov i2c8 = &i2c8; 39e5813b15SDmitry Baryshkov i2c9 = &i2c9; 40e5813b15SDmitry Baryshkov i2c10 = &i2c10; 41e5813b15SDmitry Baryshkov i2c11 = &i2c11; 42e5813b15SDmitry Baryshkov i2c12 = &i2c12; 43e5813b15SDmitry Baryshkov i2c13 = &i2c13; 44e5813b15SDmitry Baryshkov i2c14 = &i2c14; 45e5813b15SDmitry Baryshkov i2c15 = &i2c15; 46e5813b15SDmitry Baryshkov i2c16 = &i2c16; 47e5813b15SDmitry Baryshkov i2c17 = &i2c17; 48e5813b15SDmitry Baryshkov i2c18 = &i2c18; 49e5813b15SDmitry Baryshkov i2c19 = &i2c19; 50e5813b15SDmitry Baryshkov spi0 = &spi0; 51e5813b15SDmitry Baryshkov spi1 = &spi1; 52e5813b15SDmitry Baryshkov spi2 = &spi2; 53e5813b15SDmitry Baryshkov spi3 = &spi3; 54e5813b15SDmitry Baryshkov spi4 = &spi4; 55e5813b15SDmitry Baryshkov spi5 = &spi5; 56e5813b15SDmitry Baryshkov spi6 = &spi6; 57e5813b15SDmitry Baryshkov spi7 = &spi7; 58e5813b15SDmitry Baryshkov spi8 = &spi8; 59e5813b15SDmitry Baryshkov spi9 = &spi9; 60e5813b15SDmitry Baryshkov spi10 = &spi10; 61e5813b15SDmitry Baryshkov spi11 = &spi11; 62e5813b15SDmitry Baryshkov spi12 = &spi12; 63e5813b15SDmitry Baryshkov spi13 = &spi13; 64e5813b15SDmitry Baryshkov spi14 = &spi14; 65e5813b15SDmitry Baryshkov spi15 = &spi15; 66e5813b15SDmitry Baryshkov spi16 = &spi16; 67e5813b15SDmitry Baryshkov spi17 = &spi17; 68e5813b15SDmitry Baryshkov spi18 = &spi18; 69e5813b15SDmitry Baryshkov spi19 = &spi19; 70e5813b15SDmitry Baryshkov }; 71e5813b15SDmitry Baryshkov 7260378f1aSVenkata Narendra Kumar Gutta chosen { }; 7360378f1aSVenkata Narendra Kumar Gutta 7460378f1aSVenkata Narendra Kumar Gutta clocks { 7560378f1aSVenkata Narendra Kumar Gutta xo_board: xo-board { 7660378f1aSVenkata Narendra Kumar Gutta compatible = "fixed-clock"; 7760378f1aSVenkata Narendra Kumar Gutta #clock-cells = <0>; 7860378f1aSVenkata Narendra Kumar Gutta clock-frequency = <38400000>; 7960378f1aSVenkata Narendra Kumar Gutta clock-output-names = "xo_board"; 8060378f1aSVenkata Narendra Kumar Gutta }; 8160378f1aSVenkata Narendra Kumar Gutta 8260378f1aSVenkata Narendra Kumar Gutta sleep_clk: sleep-clk { 8360378f1aSVenkata Narendra Kumar Gutta compatible = "fixed-clock"; 849ff8b059SJonathan Marek clock-frequency = <32768>; 8560378f1aSVenkata Narendra Kumar Gutta #clock-cells = <0>; 8660378f1aSVenkata Narendra Kumar Gutta }; 8760378f1aSVenkata Narendra Kumar Gutta }; 8860378f1aSVenkata Narendra Kumar Gutta 8960378f1aSVenkata Narendra Kumar Gutta cpus { 9060378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 9160378f1aSVenkata Narendra Kumar Gutta #size-cells = <0>; 9260378f1aSVenkata Narendra Kumar Gutta 9360378f1aSVenkata Narendra Kumar Gutta CPU0: cpu@0 { 9460378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 9560378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 9660378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x0>; 9760378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 986aabed55SDanny Lin capacity-dmips-mhz = <448>; 996aabed55SDanny Lin dynamic-power-coefficient = <205>; 10060378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_0>; 10102ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 102bac12f25SAmit Kucheria #cooling-cells = <2>; 10360378f1aSVenkata Narendra Kumar Gutta L2_0: l2-cache { 10460378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 10560378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 10660378f1aSVenkata Narendra Kumar Gutta L3_0: l3-cache { 10760378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 10860378f1aSVenkata Narendra Kumar Gutta }; 10960378f1aSVenkata Narendra Kumar Gutta }; 11060378f1aSVenkata Narendra Kumar Gutta }; 11160378f1aSVenkata Narendra Kumar Gutta 11260378f1aSVenkata Narendra Kumar Gutta CPU1: cpu@100 { 11360378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 11460378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 11560378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x100>; 11660378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1176aabed55SDanny Lin capacity-dmips-mhz = <448>; 1186aabed55SDanny Lin dynamic-power-coefficient = <205>; 11960378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_100>; 12002ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 121bac12f25SAmit Kucheria #cooling-cells = <2>; 12260378f1aSVenkata Narendra Kumar Gutta L2_100: l2-cache { 12360378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 12460378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 12560378f1aSVenkata Narendra Kumar Gutta }; 12660378f1aSVenkata Narendra Kumar Gutta }; 12760378f1aSVenkata Narendra Kumar Gutta 12860378f1aSVenkata Narendra Kumar Gutta CPU2: cpu@200 { 12960378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 13060378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 13160378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x200>; 13260378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1336aabed55SDanny Lin capacity-dmips-mhz = <448>; 1346aabed55SDanny Lin dynamic-power-coefficient = <205>; 13560378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_200>; 13602ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 137bac12f25SAmit Kucheria #cooling-cells = <2>; 13860378f1aSVenkata Narendra Kumar Gutta L2_200: l2-cache { 13960378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 14060378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 14160378f1aSVenkata Narendra Kumar Gutta }; 14260378f1aSVenkata Narendra Kumar Gutta }; 14360378f1aSVenkata Narendra Kumar Gutta 14460378f1aSVenkata Narendra Kumar Gutta CPU3: cpu@300 { 14560378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 14660378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 14760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x300>; 14860378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1496aabed55SDanny Lin capacity-dmips-mhz = <448>; 1506aabed55SDanny Lin dynamic-power-coefficient = <205>; 15160378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_300>; 15202ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 153bac12f25SAmit Kucheria #cooling-cells = <2>; 15460378f1aSVenkata Narendra Kumar Gutta L2_300: l2-cache { 15560378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 15660378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 15760378f1aSVenkata Narendra Kumar Gutta }; 15860378f1aSVenkata Narendra Kumar Gutta }; 15960378f1aSVenkata Narendra Kumar Gutta 16060378f1aSVenkata Narendra Kumar Gutta CPU4: cpu@400 { 16160378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 16260378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 16360378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x400>; 16460378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1656aabed55SDanny Lin capacity-dmips-mhz = <1024>; 1666aabed55SDanny Lin dynamic-power-coefficient = <379>; 16760378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_400>; 16802ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 1>; 169bac12f25SAmit Kucheria #cooling-cells = <2>; 17060378f1aSVenkata Narendra Kumar Gutta L2_400: l2-cache { 17160378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 17260378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 17360378f1aSVenkata Narendra Kumar Gutta }; 17460378f1aSVenkata Narendra Kumar Gutta }; 17560378f1aSVenkata Narendra Kumar Gutta 17660378f1aSVenkata Narendra Kumar Gutta CPU5: cpu@500 { 17760378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 17860378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 17960378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x500>; 18060378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1816aabed55SDanny Lin capacity-dmips-mhz = <1024>; 1826aabed55SDanny Lin dynamic-power-coefficient = <379>; 18360378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_500>; 18402ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 1>; 185bac12f25SAmit Kucheria #cooling-cells = <2>; 18660378f1aSVenkata Narendra Kumar Gutta L2_500: l2-cache { 18760378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 18860378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 18960378f1aSVenkata Narendra Kumar Gutta }; 19060378f1aSVenkata Narendra Kumar Gutta 19160378f1aSVenkata Narendra Kumar Gutta }; 19260378f1aSVenkata Narendra Kumar Gutta 19360378f1aSVenkata Narendra Kumar Gutta CPU6: cpu@600 { 19460378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 19560378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 19660378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x600>; 19760378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1986aabed55SDanny Lin capacity-dmips-mhz = <1024>; 1996aabed55SDanny Lin dynamic-power-coefficient = <379>; 20060378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_600>; 20102ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 1>; 202bac12f25SAmit Kucheria #cooling-cells = <2>; 20360378f1aSVenkata Narendra Kumar Gutta L2_600: l2-cache { 20460378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 20560378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 20660378f1aSVenkata Narendra Kumar Gutta }; 20760378f1aSVenkata Narendra Kumar Gutta }; 20860378f1aSVenkata Narendra Kumar Gutta 20960378f1aSVenkata Narendra Kumar Gutta CPU7: cpu@700 { 21060378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 21160378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 21260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x700>; 21360378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 2146aabed55SDanny Lin capacity-dmips-mhz = <1024>; 2156aabed55SDanny Lin dynamic-power-coefficient = <444>; 21660378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_700>; 21702ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 2>; 218bac12f25SAmit Kucheria #cooling-cells = <2>; 21960378f1aSVenkata Narendra Kumar Gutta L2_700: l2-cache { 22060378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 22160378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 22260378f1aSVenkata Narendra Kumar Gutta }; 22360378f1aSVenkata Narendra Kumar Gutta }; 224b4791e69SDanny Lin 225b4791e69SDanny Lin cpu-map { 226b4791e69SDanny Lin cluster0 { 227b4791e69SDanny Lin core0 { 228b4791e69SDanny Lin cpu = <&CPU0>; 229b4791e69SDanny Lin }; 230b4791e69SDanny Lin 231b4791e69SDanny Lin core1 { 232b4791e69SDanny Lin cpu = <&CPU1>; 233b4791e69SDanny Lin }; 234b4791e69SDanny Lin 235b4791e69SDanny Lin core2 { 236b4791e69SDanny Lin cpu = <&CPU2>; 237b4791e69SDanny Lin }; 238b4791e69SDanny Lin 239b4791e69SDanny Lin core3 { 240b4791e69SDanny Lin cpu = <&CPU3>; 241b4791e69SDanny Lin }; 242b4791e69SDanny Lin 243b4791e69SDanny Lin core4 { 244b4791e69SDanny Lin cpu = <&CPU4>; 245b4791e69SDanny Lin }; 246b4791e69SDanny Lin 247b4791e69SDanny Lin core5 { 248b4791e69SDanny Lin cpu = <&CPU5>; 249b4791e69SDanny Lin }; 250b4791e69SDanny Lin 251b4791e69SDanny Lin core6 { 252b4791e69SDanny Lin cpu = <&CPU6>; 253b4791e69SDanny Lin }; 254b4791e69SDanny Lin 255b4791e69SDanny Lin core7 { 256b4791e69SDanny Lin cpu = <&CPU7>; 257b4791e69SDanny Lin }; 258b4791e69SDanny Lin }; 259b4791e69SDanny Lin }; 26060378f1aSVenkata Narendra Kumar Gutta }; 26160378f1aSVenkata Narendra Kumar Gutta 26260378f1aSVenkata Narendra Kumar Gutta firmware { 26360378f1aSVenkata Narendra Kumar Gutta scm: scm { 26460378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,scm"; 26560378f1aSVenkata Narendra Kumar Gutta #reset-cells = <1>; 26660378f1aSVenkata Narendra Kumar Gutta }; 26760378f1aSVenkata Narendra Kumar Gutta }; 26860378f1aSVenkata Narendra Kumar Gutta 26960378f1aSVenkata Narendra Kumar Gutta memory@80000000 { 27060378f1aSVenkata Narendra Kumar Gutta device_type = "memory"; 27160378f1aSVenkata Narendra Kumar Gutta /* We expect the bootloader to fill in the size */ 27260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80000000 0x0 0x0>; 27360378f1aSVenkata Narendra Kumar Gutta }; 27460378f1aSVenkata Narendra Kumar Gutta 27560378f1aSVenkata Narendra Kumar Gutta pmu { 27660378f1aSVenkata Narendra Kumar Gutta compatible = "arm,armv8-pmuv3"; 27793138ef5SSai Prakash Ranjan interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 27860378f1aSVenkata Narendra Kumar Gutta }; 27960378f1aSVenkata Narendra Kumar Gutta 28060378f1aSVenkata Narendra Kumar Gutta psci { 28160378f1aSVenkata Narendra Kumar Gutta compatible = "arm,psci-1.0"; 28260378f1aSVenkata Narendra Kumar Gutta method = "smc"; 28360378f1aSVenkata Narendra Kumar Gutta }; 28460378f1aSVenkata Narendra Kumar Gutta 28560378f1aSVenkata Narendra Kumar Gutta reserved-memory { 28660378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 28760378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 28860378f1aSVenkata Narendra Kumar Gutta ranges; 28960378f1aSVenkata Narendra Kumar Gutta 29060378f1aSVenkata Narendra Kumar Gutta hyp_mem: memory@80000000 { 29160378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80000000 0x0 0x600000>; 29260378f1aSVenkata Narendra Kumar Gutta no-map; 29360378f1aSVenkata Narendra Kumar Gutta }; 29460378f1aSVenkata Narendra Kumar Gutta 29560378f1aSVenkata Narendra Kumar Gutta xbl_aop_mem: memory@80700000 { 29660378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80700000 0x0 0x160000>; 29760378f1aSVenkata Narendra Kumar Gutta no-map; 29860378f1aSVenkata Narendra Kumar Gutta }; 29960378f1aSVenkata Narendra Kumar Gutta 30060378f1aSVenkata Narendra Kumar Gutta cmd_db: memory@80860000 { 30160378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,cmd-db"; 30260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80860000 0x0 0x20000>; 30360378f1aSVenkata Narendra Kumar Gutta no-map; 30460378f1aSVenkata Narendra Kumar Gutta }; 30560378f1aSVenkata Narendra Kumar Gutta 30660378f1aSVenkata Narendra Kumar Gutta smem_mem: memory@80900000 { 30760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80900000 0x0 0x200000>; 30860378f1aSVenkata Narendra Kumar Gutta no-map; 30960378f1aSVenkata Narendra Kumar Gutta }; 31060378f1aSVenkata Narendra Kumar Gutta 31160378f1aSVenkata Narendra Kumar Gutta removed_mem: memory@80b00000 { 31260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80b00000 0x0 0x5300000>; 31360378f1aSVenkata Narendra Kumar Gutta no-map; 31460378f1aSVenkata Narendra Kumar Gutta }; 31560378f1aSVenkata Narendra Kumar Gutta 31660378f1aSVenkata Narendra Kumar Gutta camera_mem: memory@86200000 { 31760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86200000 0x0 0x500000>; 31860378f1aSVenkata Narendra Kumar Gutta no-map; 31960378f1aSVenkata Narendra Kumar Gutta }; 32060378f1aSVenkata Narendra Kumar Gutta 32160378f1aSVenkata Narendra Kumar Gutta wlan_mem: memory@86700000 { 32260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86700000 0x0 0x100000>; 32360378f1aSVenkata Narendra Kumar Gutta no-map; 32460378f1aSVenkata Narendra Kumar Gutta }; 32560378f1aSVenkata Narendra Kumar Gutta 32660378f1aSVenkata Narendra Kumar Gutta ipa_fw_mem: memory@86800000 { 32760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86800000 0x0 0x10000>; 32860378f1aSVenkata Narendra Kumar Gutta no-map; 32960378f1aSVenkata Narendra Kumar Gutta }; 33060378f1aSVenkata Narendra Kumar Gutta 33160378f1aSVenkata Narendra Kumar Gutta ipa_gsi_mem: memory@86810000 { 33260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86810000 0x0 0xa000>; 33360378f1aSVenkata Narendra Kumar Gutta no-map; 33460378f1aSVenkata Narendra Kumar Gutta }; 33560378f1aSVenkata Narendra Kumar Gutta 33660378f1aSVenkata Narendra Kumar Gutta gpu_mem: memory@8681a000 { 33760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8681a000 0x0 0x2000>; 33860378f1aSVenkata Narendra Kumar Gutta no-map; 33960378f1aSVenkata Narendra Kumar Gutta }; 34060378f1aSVenkata Narendra Kumar Gutta 34160378f1aSVenkata Narendra Kumar Gutta npu_mem: memory@86900000 { 34260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86900000 0x0 0x500000>; 34360378f1aSVenkata Narendra Kumar Gutta no-map; 34460378f1aSVenkata Narendra Kumar Gutta }; 34560378f1aSVenkata Narendra Kumar Gutta 34660378f1aSVenkata Narendra Kumar Gutta video_mem: memory@86e00000 { 34760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86e00000 0x0 0x500000>; 34860378f1aSVenkata Narendra Kumar Gutta no-map; 34960378f1aSVenkata Narendra Kumar Gutta }; 35060378f1aSVenkata Narendra Kumar Gutta 35160378f1aSVenkata Narendra Kumar Gutta cvp_mem: memory@87300000 { 35260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x87300000 0x0 0x500000>; 35360378f1aSVenkata Narendra Kumar Gutta no-map; 35460378f1aSVenkata Narendra Kumar Gutta }; 35560378f1aSVenkata Narendra Kumar Gutta 35660378f1aSVenkata Narendra Kumar Gutta cdsp_mem: memory@87800000 { 35760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x87800000 0x0 0x1400000>; 35860378f1aSVenkata Narendra Kumar Gutta no-map; 35960378f1aSVenkata Narendra Kumar Gutta }; 36060378f1aSVenkata Narendra Kumar Gutta 36160378f1aSVenkata Narendra Kumar Gutta slpi_mem: memory@88c00000 { 36260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x88c00000 0x0 0x1500000>; 36360378f1aSVenkata Narendra Kumar Gutta no-map; 36460378f1aSVenkata Narendra Kumar Gutta }; 36560378f1aSVenkata Narendra Kumar Gutta 36660378f1aSVenkata Narendra Kumar Gutta adsp_mem: memory@8a100000 { 36760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8a100000 0x0 0x1d00000>; 36860378f1aSVenkata Narendra Kumar Gutta no-map; 36960378f1aSVenkata Narendra Kumar Gutta }; 37060378f1aSVenkata Narendra Kumar Gutta 37160378f1aSVenkata Narendra Kumar Gutta spss_mem: memory@8be00000 { 37260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8be00000 0x0 0x100000>; 37360378f1aSVenkata Narendra Kumar Gutta no-map; 37460378f1aSVenkata Narendra Kumar Gutta }; 37560378f1aSVenkata Narendra Kumar Gutta 37660378f1aSVenkata Narendra Kumar Gutta cdsp_secure_heap: memory@8bf00000 { 37760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8bf00000 0x0 0x4600000>; 37860378f1aSVenkata Narendra Kumar Gutta no-map; 37960378f1aSVenkata Narendra Kumar Gutta }; 38060378f1aSVenkata Narendra Kumar Gutta }; 38160378f1aSVenkata Narendra Kumar Gutta 38288b57bc3SDmitry Baryshkov smem { 38360378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,smem"; 38460378f1aSVenkata Narendra Kumar Gutta memory-region = <&smem_mem>; 38560378f1aSVenkata Narendra Kumar Gutta hwlocks = <&tcsr_mutex 3>; 38660378f1aSVenkata Narendra Kumar Gutta }; 38760378f1aSVenkata Narendra Kumar Gutta 3888770a2a8SBjorn Andersson smp2p-adsp { 3898770a2a8SBjorn Andersson compatible = "qcom,smp2p"; 3908770a2a8SBjorn Andersson qcom,smem = <443>, <429>; 3918770a2a8SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3928770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P 3938770a2a8SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 3948770a2a8SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_LPASS 3958770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P>; 3968770a2a8SBjorn Andersson 3978770a2a8SBjorn Andersson qcom,local-pid = <0>; 3988770a2a8SBjorn Andersson qcom,remote-pid = <2>; 3998770a2a8SBjorn Andersson 4008770a2a8SBjorn Andersson smp2p_adsp_out: master-kernel { 4018770a2a8SBjorn Andersson qcom,entry-name = "master-kernel"; 4028770a2a8SBjorn Andersson #qcom,smem-state-cells = <1>; 4038770a2a8SBjorn Andersson }; 4048770a2a8SBjorn Andersson 4058770a2a8SBjorn Andersson smp2p_adsp_in: slave-kernel { 4068770a2a8SBjorn Andersson qcom,entry-name = "slave-kernel"; 4078770a2a8SBjorn Andersson interrupt-controller; 4088770a2a8SBjorn Andersson #interrupt-cells = <2>; 4098770a2a8SBjorn Andersson }; 4108770a2a8SBjorn Andersson }; 4118770a2a8SBjorn Andersson 4128770a2a8SBjorn Andersson smp2p-cdsp { 4138770a2a8SBjorn Andersson compatible = "qcom,smp2p"; 4148770a2a8SBjorn Andersson qcom,smem = <94>, <432>; 4158770a2a8SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4168770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P 4178770a2a8SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 4188770a2a8SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_CDSP 4198770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P>; 4208770a2a8SBjorn Andersson 4218770a2a8SBjorn Andersson qcom,local-pid = <0>; 4228770a2a8SBjorn Andersson qcom,remote-pid = <5>; 4238770a2a8SBjorn Andersson 4248770a2a8SBjorn Andersson smp2p_cdsp_out: master-kernel { 4258770a2a8SBjorn Andersson qcom,entry-name = "master-kernel"; 4268770a2a8SBjorn Andersson #qcom,smem-state-cells = <1>; 4278770a2a8SBjorn Andersson }; 4288770a2a8SBjorn Andersson 4298770a2a8SBjorn Andersson smp2p_cdsp_in: slave-kernel { 4308770a2a8SBjorn Andersson qcom,entry-name = "slave-kernel"; 4318770a2a8SBjorn Andersson interrupt-controller; 4328770a2a8SBjorn Andersson #interrupt-cells = <2>; 4338770a2a8SBjorn Andersson }; 4348770a2a8SBjorn Andersson }; 4358770a2a8SBjorn Andersson 4368770a2a8SBjorn Andersson smp2p-slpi { 4378770a2a8SBjorn Andersson compatible = "qcom,smp2p"; 4388770a2a8SBjorn Andersson qcom,smem = <481>, <430>; 4398770a2a8SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 4408770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P 4418770a2a8SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 4428770a2a8SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_SLPI 4438770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P>; 4448770a2a8SBjorn Andersson 4458770a2a8SBjorn Andersson qcom,local-pid = <0>; 4468770a2a8SBjorn Andersson qcom,remote-pid = <3>; 4478770a2a8SBjorn Andersson 4488770a2a8SBjorn Andersson smp2p_slpi_out: master-kernel { 4498770a2a8SBjorn Andersson qcom,entry-name = "master-kernel"; 4508770a2a8SBjorn Andersson #qcom,smem-state-cells = <1>; 4518770a2a8SBjorn Andersson }; 4528770a2a8SBjorn Andersson 4538770a2a8SBjorn Andersson smp2p_slpi_in: slave-kernel { 4548770a2a8SBjorn Andersson qcom,entry-name = "slave-kernel"; 4558770a2a8SBjorn Andersson interrupt-controller; 4568770a2a8SBjorn Andersson #interrupt-cells = <2>; 4578770a2a8SBjorn Andersson }; 4588770a2a8SBjorn Andersson }; 4598770a2a8SBjorn Andersson 46060378f1aSVenkata Narendra Kumar Gutta soc: soc@0 { 46160378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 46260378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 46360378f1aSVenkata Narendra Kumar Gutta ranges = <0 0 0 0 0x10 0>; 46460378f1aSVenkata Narendra Kumar Gutta dma-ranges = <0 0 0 0 0x10 0>; 46560378f1aSVenkata Narendra Kumar Gutta compatible = "simple-bus"; 46660378f1aSVenkata Narendra Kumar Gutta 46760378f1aSVenkata Narendra Kumar Gutta gcc: clock-controller@100000 { 46860378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,gcc-sm8250"; 46960378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x00100000 0x0 0x1f0000>; 47060378f1aSVenkata Narendra Kumar Gutta #clock-cells = <1>; 47160378f1aSVenkata Narendra Kumar Gutta #reset-cells = <1>; 47260378f1aSVenkata Narendra Kumar Gutta #power-domain-cells = <1>; 47376bd127eSDmitry Baryshkov clock-names = "bi_tcxo", 47476bd127eSDmitry Baryshkov "bi_tcxo_ao", 47576bd127eSDmitry Baryshkov "sleep_clk"; 47676bd127eSDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>, 47776bd127eSDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK_A>, 47876bd127eSDmitry Baryshkov <&sleep_clk>; 47960378f1aSVenkata Narendra Kumar Gutta }; 48060378f1aSVenkata Narendra Kumar Gutta 481e5361e75SBjorn Andersson ipcc: mailbox@408000 { 482e5361e75SBjorn Andersson compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 483e5361e75SBjorn Andersson reg = <0 0x00408000 0 0x1000>; 484e5361e75SBjorn Andersson interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 485e5361e75SBjorn Andersson interrupt-controller; 486e5361e75SBjorn Andersson #interrupt-cells = <3>; 487e5361e75SBjorn Andersson #mbox-cells = <2>; 488e5361e75SBjorn Andersson }; 489e5361e75SBjorn Andersson 49065389ce6SManivannan Sadhasivam rng: rng@793000 { 49165389ce6SManivannan Sadhasivam compatible = "qcom,prng-ee"; 49265389ce6SManivannan Sadhasivam reg = <0 0x00793000 0 0x1000>; 49365389ce6SManivannan Sadhasivam clocks = <&gcc GCC_PRNG_AHB_CLK>; 49465389ce6SManivannan Sadhasivam clock-names = "core"; 49565389ce6SManivannan Sadhasivam }; 49665389ce6SManivannan Sadhasivam 49701e869ccSDmitry Baryshkov qup_opp_table: qup-opp-table { 49801e869ccSDmitry Baryshkov compatible = "operating-points-v2"; 49901e869ccSDmitry Baryshkov 50001e869ccSDmitry Baryshkov opp-50000000 { 50101e869ccSDmitry Baryshkov opp-hz = /bits/ 64 <50000000>; 50201e869ccSDmitry Baryshkov required-opps = <&rpmhpd_opp_min_svs>; 50301e869ccSDmitry Baryshkov }; 50401e869ccSDmitry Baryshkov 50501e869ccSDmitry Baryshkov opp-75000000 { 50601e869ccSDmitry Baryshkov opp-hz = /bits/ 64 <75000000>; 50701e869ccSDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 50801e869ccSDmitry Baryshkov }; 50901e869ccSDmitry Baryshkov 51001e869ccSDmitry Baryshkov opp-120000000 { 51101e869ccSDmitry Baryshkov opp-hz = /bits/ 64 <120000000>; 51201e869ccSDmitry Baryshkov required-opps = <&rpmhpd_opp_svs>; 51301e869ccSDmitry Baryshkov }; 51401e869ccSDmitry Baryshkov }; 51501e869ccSDmitry Baryshkov 51615049bb5SKonrad Dybcio gpi_dma2: dma-controller@800000 { 51715049bb5SKonrad Dybcio compatible = "qcom,sm8250-gpi-dma"; 51815049bb5SKonrad Dybcio reg = <0 0x00800000 0 0x70000>; 51915049bb5SKonrad Dybcio interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 52015049bb5SKonrad Dybcio <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 52115049bb5SKonrad Dybcio <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 52215049bb5SKonrad Dybcio <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 52315049bb5SKonrad Dybcio <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 52415049bb5SKonrad Dybcio <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 52515049bb5SKonrad Dybcio <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 52615049bb5SKonrad Dybcio <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 52715049bb5SKonrad Dybcio <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 52815049bb5SKonrad Dybcio <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 52915049bb5SKonrad Dybcio dma-channels = <10>; 53015049bb5SKonrad Dybcio dma-channel-mask = <0x3f>; 53115049bb5SKonrad Dybcio iommus = <&apps_smmu 0x76 0x0>; 53215049bb5SKonrad Dybcio #dma-cells = <3>; 53315049bb5SKonrad Dybcio status = "disabled"; 53415049bb5SKonrad Dybcio }; 53515049bb5SKonrad Dybcio 536e5813b15SDmitry Baryshkov qupv3_id_2: geniqup@8c0000 { 537e5813b15SDmitry Baryshkov compatible = "qcom,geni-se-qup"; 538e5813b15SDmitry Baryshkov reg = <0x0 0x008c0000 0x0 0x6000>; 539e5813b15SDmitry Baryshkov clock-names = "m-ahb", "s-ahb"; 540e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 541e5813b15SDmitry Baryshkov <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 542e5813b15SDmitry Baryshkov #address-cells = <2>; 543e5813b15SDmitry Baryshkov #size-cells = <2>; 54485309393SDmitry Baryshkov iommus = <&apps_smmu 0x63 0x0>; 545e5813b15SDmitry Baryshkov ranges; 546e5813b15SDmitry Baryshkov status = "disabled"; 547e5813b15SDmitry Baryshkov 548e5813b15SDmitry Baryshkov i2c14: i2c@880000 { 549e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 550e5813b15SDmitry Baryshkov reg = <0 0x00880000 0 0x4000>; 551e5813b15SDmitry Baryshkov clock-names = "se"; 552e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 553e5813b15SDmitry Baryshkov pinctrl-names = "default"; 554e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c14_default>; 555e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 55659983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 55759983a5cSKonrad Dybcio <&gpi_dma2 1 0 QCOM_GPI_I2C>; 55859983a5cSKonrad Dybcio dma-names = "tx", "rx"; 559e5813b15SDmitry Baryshkov #address-cells = <1>; 560e5813b15SDmitry Baryshkov #size-cells = <0>; 561e5813b15SDmitry Baryshkov status = "disabled"; 562e5813b15SDmitry Baryshkov }; 563e5813b15SDmitry Baryshkov 564e5813b15SDmitry Baryshkov spi14: spi@880000 { 565e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 566e5813b15SDmitry Baryshkov reg = <0 0x00880000 0 0x4000>; 567e5813b15SDmitry Baryshkov clock-names = "se"; 568e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 569e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 57059983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 57159983a5cSKonrad Dybcio <&gpi_dma2 1 0 QCOM_GPI_SPI>; 57259983a5cSKonrad Dybcio dma-names = "tx", "rx"; 57301e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 57401e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 57559983a5cSKonrad Dybcio #address-cells = <1>; 57659983a5cSKonrad Dybcio #size-cells = <0>; 577e5813b15SDmitry Baryshkov status = "disabled"; 578e5813b15SDmitry Baryshkov }; 579e5813b15SDmitry Baryshkov 580e5813b15SDmitry Baryshkov i2c15: i2c@884000 { 581e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 582e5813b15SDmitry Baryshkov reg = <0 0x00884000 0 0x4000>; 583e5813b15SDmitry Baryshkov clock-names = "se"; 584e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 585e5813b15SDmitry Baryshkov pinctrl-names = "default"; 586e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c15_default>; 587e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 58859983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 58959983a5cSKonrad Dybcio <&gpi_dma2 1 1 QCOM_GPI_I2C>; 59059983a5cSKonrad Dybcio dma-names = "tx", "rx"; 591e5813b15SDmitry Baryshkov #address-cells = <1>; 592e5813b15SDmitry Baryshkov #size-cells = <0>; 593e5813b15SDmitry Baryshkov status = "disabled"; 594e5813b15SDmitry Baryshkov }; 595e5813b15SDmitry Baryshkov 596e5813b15SDmitry Baryshkov spi15: spi@884000 { 597e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 598e5813b15SDmitry Baryshkov reg = <0 0x00884000 0 0x4000>; 599e5813b15SDmitry Baryshkov clock-names = "se"; 600e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 601e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 60259983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 60359983a5cSKonrad Dybcio <&gpi_dma2 1 1 QCOM_GPI_SPI>; 60459983a5cSKonrad Dybcio dma-names = "tx", "rx"; 60501e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 60601e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 60759983a5cSKonrad Dybcio #address-cells = <1>; 60859983a5cSKonrad Dybcio #size-cells = <0>; 609e5813b15SDmitry Baryshkov status = "disabled"; 610e5813b15SDmitry Baryshkov }; 611e5813b15SDmitry Baryshkov 612e5813b15SDmitry Baryshkov i2c16: i2c@888000 { 613e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 614e5813b15SDmitry Baryshkov reg = <0 0x00888000 0 0x4000>; 615e5813b15SDmitry Baryshkov clock-names = "se"; 616e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 617e5813b15SDmitry Baryshkov pinctrl-names = "default"; 618e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c16_default>; 619e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 62059983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 62159983a5cSKonrad Dybcio <&gpi_dma2 1 2 QCOM_GPI_I2C>; 62259983a5cSKonrad Dybcio dma-names = "tx", "rx"; 623e5813b15SDmitry Baryshkov #address-cells = <1>; 624e5813b15SDmitry Baryshkov #size-cells = <0>; 625e5813b15SDmitry Baryshkov status = "disabled"; 626e5813b15SDmitry Baryshkov }; 627e5813b15SDmitry Baryshkov 628e5813b15SDmitry Baryshkov spi16: spi@888000 { 629e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 630e5813b15SDmitry Baryshkov reg = <0 0x00888000 0 0x4000>; 631e5813b15SDmitry Baryshkov clock-names = "se"; 632e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 633e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 63459983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 63559983a5cSKonrad Dybcio <&gpi_dma2 1 2 QCOM_GPI_SPI>; 63659983a5cSKonrad Dybcio dma-names = "tx", "rx"; 63701e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 63801e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 63959983a5cSKonrad Dybcio #address-cells = <1>; 64059983a5cSKonrad Dybcio #size-cells = <0>; 641e5813b15SDmitry Baryshkov status = "disabled"; 642e5813b15SDmitry Baryshkov }; 643e5813b15SDmitry Baryshkov 644e5813b15SDmitry Baryshkov i2c17: i2c@88c000 { 645e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 646e5813b15SDmitry Baryshkov reg = <0 0x0088c000 0 0x4000>; 647e5813b15SDmitry Baryshkov clock-names = "se"; 648e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 649e5813b15SDmitry Baryshkov pinctrl-names = "default"; 650e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c17_default>; 651e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 65259983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 65359983a5cSKonrad Dybcio <&gpi_dma2 1 3 QCOM_GPI_I2C>; 65459983a5cSKonrad Dybcio dma-names = "tx", "rx"; 655e5813b15SDmitry Baryshkov #address-cells = <1>; 656e5813b15SDmitry Baryshkov #size-cells = <0>; 657e5813b15SDmitry Baryshkov status = "disabled"; 658e5813b15SDmitry Baryshkov }; 659e5813b15SDmitry Baryshkov 660e5813b15SDmitry Baryshkov spi17: spi@88c000 { 661e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 662e5813b15SDmitry Baryshkov reg = <0 0x0088c000 0 0x4000>; 663e5813b15SDmitry Baryshkov clock-names = "se"; 664e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 665e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 66659983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 66759983a5cSKonrad Dybcio <&gpi_dma2 1 3 QCOM_GPI_SPI>; 66859983a5cSKonrad Dybcio dma-names = "tx", "rx"; 66901e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 67001e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 67159983a5cSKonrad Dybcio #address-cells = <1>; 67259983a5cSKonrad Dybcio #size-cells = <0>; 673e5813b15SDmitry Baryshkov status = "disabled"; 674e5813b15SDmitry Baryshkov }; 675e5813b15SDmitry Baryshkov 67608a9ae2dSDmitry Baryshkov uart17: serial@88c000 { 67708a9ae2dSDmitry Baryshkov compatible = "qcom,geni-uart"; 67808a9ae2dSDmitry Baryshkov reg = <0 0x0088c000 0 0x4000>; 67908a9ae2dSDmitry Baryshkov clock-names = "se"; 68008a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 68108a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 68208a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart17_default>; 68308a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 68401e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 68501e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 68608a9ae2dSDmitry Baryshkov status = "disabled"; 68708a9ae2dSDmitry Baryshkov }; 68808a9ae2dSDmitry Baryshkov 689e5813b15SDmitry Baryshkov i2c18: i2c@890000 { 690e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 691e5813b15SDmitry Baryshkov reg = <0 0x00890000 0 0x4000>; 692e5813b15SDmitry Baryshkov clock-names = "se"; 693e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 694e5813b15SDmitry Baryshkov pinctrl-names = "default"; 695e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c18_default>; 696e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 69759983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 69859983a5cSKonrad Dybcio <&gpi_dma2 1 4 QCOM_GPI_I2C>; 69959983a5cSKonrad Dybcio dma-names = "tx", "rx"; 700e5813b15SDmitry Baryshkov #address-cells = <1>; 701e5813b15SDmitry Baryshkov #size-cells = <0>; 702e5813b15SDmitry Baryshkov status = "disabled"; 703e5813b15SDmitry Baryshkov }; 704e5813b15SDmitry Baryshkov 705e5813b15SDmitry Baryshkov spi18: spi@890000 { 706e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 707e5813b15SDmitry Baryshkov reg = <0 0x00890000 0 0x4000>; 708e5813b15SDmitry Baryshkov clock-names = "se"; 709e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 710e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 71159983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 71259983a5cSKonrad Dybcio <&gpi_dma2 1 4 QCOM_GPI_SPI>; 71359983a5cSKonrad Dybcio dma-names = "tx", "rx"; 71401e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 71501e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 71659983a5cSKonrad Dybcio #address-cells = <1>; 71759983a5cSKonrad Dybcio #size-cells = <0>; 718e5813b15SDmitry Baryshkov status = "disabled"; 719e5813b15SDmitry Baryshkov }; 720e5813b15SDmitry Baryshkov 72108a9ae2dSDmitry Baryshkov uart18: serial@890000 { 72208a9ae2dSDmitry Baryshkov compatible = "qcom,geni-uart"; 72308a9ae2dSDmitry Baryshkov reg = <0 0x00890000 0 0x4000>; 72408a9ae2dSDmitry Baryshkov clock-names = "se"; 72508a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 72608a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 72708a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart18_default>; 72808a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 72901e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 73001e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 73108a9ae2dSDmitry Baryshkov status = "disabled"; 73208a9ae2dSDmitry Baryshkov }; 73308a9ae2dSDmitry Baryshkov 734e5813b15SDmitry Baryshkov i2c19: i2c@894000 { 735e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 736e5813b15SDmitry Baryshkov reg = <0 0x00894000 0 0x4000>; 737e5813b15SDmitry Baryshkov clock-names = "se"; 738e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 739e5813b15SDmitry Baryshkov pinctrl-names = "default"; 740e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c19_default>; 741e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 74259983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 74359983a5cSKonrad Dybcio <&gpi_dma2 1 5 QCOM_GPI_I2C>; 74459983a5cSKonrad Dybcio dma-names = "tx", "rx"; 745e5813b15SDmitry Baryshkov #address-cells = <1>; 746e5813b15SDmitry Baryshkov #size-cells = <0>; 747e5813b15SDmitry Baryshkov status = "disabled"; 748e5813b15SDmitry Baryshkov }; 749e5813b15SDmitry Baryshkov 750e5813b15SDmitry Baryshkov spi19: spi@894000 { 751e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 752e5813b15SDmitry Baryshkov reg = <0 0x00894000 0 0x4000>; 753e5813b15SDmitry Baryshkov clock-names = "se"; 754e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 755e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 75659983a5cSKonrad Dybcio dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 75759983a5cSKonrad Dybcio <&gpi_dma2 1 5 QCOM_GPI_SPI>; 75859983a5cSKonrad Dybcio dma-names = "tx", "rx"; 75901e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 76001e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 76159983a5cSKonrad Dybcio #address-cells = <1>; 76259983a5cSKonrad Dybcio #size-cells = <0>; 763e5813b15SDmitry Baryshkov status = "disabled"; 764e5813b15SDmitry Baryshkov }; 765e5813b15SDmitry Baryshkov }; 766e5813b15SDmitry Baryshkov 76715049bb5SKonrad Dybcio gpi_dma0: dma-controller@900000 { 76815049bb5SKonrad Dybcio compatible = "qcom,sm8250-gpi-dma"; 76915049bb5SKonrad Dybcio reg = <0 0x00900000 0 0x70000>; 77015049bb5SKonrad Dybcio interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 77115049bb5SKonrad Dybcio <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 77215049bb5SKonrad Dybcio <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 77315049bb5SKonrad Dybcio <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 77415049bb5SKonrad Dybcio <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 77515049bb5SKonrad Dybcio <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 77615049bb5SKonrad Dybcio <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 77715049bb5SKonrad Dybcio <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 77815049bb5SKonrad Dybcio <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 77915049bb5SKonrad Dybcio <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 78015049bb5SKonrad Dybcio <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 78115049bb5SKonrad Dybcio <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 78215049bb5SKonrad Dybcio <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 78315049bb5SKonrad Dybcio dma-channels = <15>; 78415049bb5SKonrad Dybcio dma-channel-mask = <0x7ff>; 78515049bb5SKonrad Dybcio iommus = <&apps_smmu 0x5b6 0x0>; 78615049bb5SKonrad Dybcio #dma-cells = <3>; 78715049bb5SKonrad Dybcio status = "disabled"; 78815049bb5SKonrad Dybcio }; 78915049bb5SKonrad Dybcio 790e5813b15SDmitry Baryshkov qupv3_id_0: geniqup@9c0000 { 791e5813b15SDmitry Baryshkov compatible = "qcom,geni-se-qup"; 792e5813b15SDmitry Baryshkov reg = <0x0 0x009c0000 0x0 0x6000>; 793e5813b15SDmitry Baryshkov clock-names = "m-ahb", "s-ahb"; 794e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 795e5813b15SDmitry Baryshkov <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 796e5813b15SDmitry Baryshkov #address-cells = <2>; 797e5813b15SDmitry Baryshkov #size-cells = <2>; 79885309393SDmitry Baryshkov iommus = <&apps_smmu 0x5a3 0x0>; 799e5813b15SDmitry Baryshkov ranges; 800e5813b15SDmitry Baryshkov status = "disabled"; 801e5813b15SDmitry Baryshkov 802e5813b15SDmitry Baryshkov i2c0: i2c@980000 { 803e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 804e5813b15SDmitry Baryshkov reg = <0 0x00980000 0 0x4000>; 805e5813b15SDmitry Baryshkov clock-names = "se"; 806e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 807e5813b15SDmitry Baryshkov pinctrl-names = "default"; 808e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c0_default>; 809e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 81059983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 81159983a5cSKonrad Dybcio <&gpi_dma0 1 0 QCOM_GPI_I2C>; 81259983a5cSKonrad Dybcio dma-names = "tx", "rx"; 813e5813b15SDmitry Baryshkov #address-cells = <1>; 814e5813b15SDmitry Baryshkov #size-cells = <0>; 815e5813b15SDmitry Baryshkov status = "disabled"; 816e5813b15SDmitry Baryshkov }; 817e5813b15SDmitry Baryshkov 818e5813b15SDmitry Baryshkov spi0: spi@980000 { 819e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 820e5813b15SDmitry Baryshkov reg = <0 0x00980000 0 0x4000>; 821e5813b15SDmitry Baryshkov clock-names = "se"; 822e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 823e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 82459983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 82559983a5cSKonrad Dybcio <&gpi_dma0 1 0 QCOM_GPI_SPI>; 82659983a5cSKonrad Dybcio dma-names = "tx", "rx"; 82701e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 82801e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 82959983a5cSKonrad Dybcio #address-cells = <1>; 83059983a5cSKonrad Dybcio #size-cells = <0>; 831e5813b15SDmitry Baryshkov status = "disabled"; 832e5813b15SDmitry Baryshkov }; 833e5813b15SDmitry Baryshkov 834e5813b15SDmitry Baryshkov i2c1: i2c@984000 { 835e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 836e5813b15SDmitry Baryshkov reg = <0 0x00984000 0 0x4000>; 837e5813b15SDmitry Baryshkov clock-names = "se"; 838e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 839e5813b15SDmitry Baryshkov pinctrl-names = "default"; 840e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c1_default>; 841e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 84259983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 84359983a5cSKonrad Dybcio <&gpi_dma0 1 1 QCOM_GPI_I2C>; 84459983a5cSKonrad Dybcio dma-names = "tx", "rx"; 845e5813b15SDmitry Baryshkov #address-cells = <1>; 846e5813b15SDmitry Baryshkov #size-cells = <0>; 847e5813b15SDmitry Baryshkov status = "disabled"; 848e5813b15SDmitry Baryshkov }; 849e5813b15SDmitry Baryshkov 850e5813b15SDmitry Baryshkov spi1: spi@984000 { 851e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 852e5813b15SDmitry Baryshkov reg = <0 0x00984000 0 0x4000>; 853e5813b15SDmitry Baryshkov clock-names = "se"; 854e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 855e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 85659983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 85759983a5cSKonrad Dybcio <&gpi_dma0 1 1 QCOM_GPI_SPI>; 85859983a5cSKonrad Dybcio dma-names = "tx", "rx"; 85901e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 86001e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 86159983a5cSKonrad Dybcio #address-cells = <1>; 86259983a5cSKonrad Dybcio #size-cells = <0>; 863e5813b15SDmitry Baryshkov status = "disabled"; 864e5813b15SDmitry Baryshkov }; 865e5813b15SDmitry Baryshkov 866e5813b15SDmitry Baryshkov i2c2: i2c@988000 { 867e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 868e5813b15SDmitry Baryshkov reg = <0 0x00988000 0 0x4000>; 869e5813b15SDmitry Baryshkov clock-names = "se"; 870e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 871e5813b15SDmitry Baryshkov pinctrl-names = "default"; 872e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c2_default>; 873e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 87459983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 87559983a5cSKonrad Dybcio <&gpi_dma0 1 2 QCOM_GPI_I2C>; 87659983a5cSKonrad Dybcio dma-names = "tx", "rx"; 877e5813b15SDmitry Baryshkov #address-cells = <1>; 878e5813b15SDmitry Baryshkov #size-cells = <0>; 879e5813b15SDmitry Baryshkov status = "disabled"; 880e5813b15SDmitry Baryshkov }; 881e5813b15SDmitry Baryshkov 882e5813b15SDmitry Baryshkov spi2: spi@988000 { 883e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 884e5813b15SDmitry Baryshkov reg = <0 0x00988000 0 0x4000>; 885e5813b15SDmitry Baryshkov clock-names = "se"; 886e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 887e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 88859983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 88959983a5cSKonrad Dybcio <&gpi_dma0 1 2 QCOM_GPI_SPI>; 89059983a5cSKonrad Dybcio dma-names = "tx", "rx"; 89101e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 89201e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 89359983a5cSKonrad Dybcio #address-cells = <1>; 89459983a5cSKonrad Dybcio #size-cells = <0>; 895e5813b15SDmitry Baryshkov status = "disabled"; 896e5813b15SDmitry Baryshkov }; 897e5813b15SDmitry Baryshkov 89808a9ae2dSDmitry Baryshkov uart2: serial@988000 { 89908a9ae2dSDmitry Baryshkov compatible = "qcom,geni-debug-uart"; 90008a9ae2dSDmitry Baryshkov reg = <0 0x00988000 0 0x4000>; 90108a9ae2dSDmitry Baryshkov clock-names = "se"; 90208a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 90308a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 90408a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart2_default>; 90508a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 90601e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 90701e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 90808a9ae2dSDmitry Baryshkov status = "disabled"; 90908a9ae2dSDmitry Baryshkov }; 91008a9ae2dSDmitry Baryshkov 911e5813b15SDmitry Baryshkov i2c3: i2c@98c000 { 912e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 913e5813b15SDmitry Baryshkov reg = <0 0x0098c000 0 0x4000>; 914e5813b15SDmitry Baryshkov clock-names = "se"; 915e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 916e5813b15SDmitry Baryshkov pinctrl-names = "default"; 917e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c3_default>; 918e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 91959983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 92059983a5cSKonrad Dybcio <&gpi_dma0 1 3 QCOM_GPI_I2C>; 92159983a5cSKonrad Dybcio dma-names = "tx", "rx"; 922e5813b15SDmitry Baryshkov #address-cells = <1>; 923e5813b15SDmitry Baryshkov #size-cells = <0>; 924e5813b15SDmitry Baryshkov status = "disabled"; 925e5813b15SDmitry Baryshkov }; 926e5813b15SDmitry Baryshkov 927e5813b15SDmitry Baryshkov spi3: spi@98c000 { 928e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 929e5813b15SDmitry Baryshkov reg = <0 0x0098c000 0 0x4000>; 930e5813b15SDmitry Baryshkov clock-names = "se"; 931e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 932e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 93359983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 93459983a5cSKonrad Dybcio <&gpi_dma0 1 3 QCOM_GPI_SPI>; 93559983a5cSKonrad Dybcio dma-names = "tx", "rx"; 93601e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 93701e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 93859983a5cSKonrad Dybcio #address-cells = <1>; 93959983a5cSKonrad Dybcio #size-cells = <0>; 940e5813b15SDmitry Baryshkov status = "disabled"; 941e5813b15SDmitry Baryshkov }; 942e5813b15SDmitry Baryshkov 943e5813b15SDmitry Baryshkov i2c4: i2c@990000 { 944e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 945e5813b15SDmitry Baryshkov reg = <0 0x00990000 0 0x4000>; 946e5813b15SDmitry Baryshkov clock-names = "se"; 947e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 948e5813b15SDmitry Baryshkov pinctrl-names = "default"; 949e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c4_default>; 950e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 95159983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 95259983a5cSKonrad Dybcio <&gpi_dma0 1 4 QCOM_GPI_I2C>; 95359983a5cSKonrad Dybcio dma-names = "tx", "rx"; 954e5813b15SDmitry Baryshkov #address-cells = <1>; 955e5813b15SDmitry Baryshkov #size-cells = <0>; 956e5813b15SDmitry Baryshkov status = "disabled"; 957e5813b15SDmitry Baryshkov }; 958e5813b15SDmitry Baryshkov 959e5813b15SDmitry Baryshkov spi4: spi@990000 { 960e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 961e5813b15SDmitry Baryshkov reg = <0 0x00990000 0 0x4000>; 962e5813b15SDmitry Baryshkov clock-names = "se"; 963e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 964e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 96559983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 96659983a5cSKonrad Dybcio <&gpi_dma0 1 4 QCOM_GPI_SPI>; 96759983a5cSKonrad Dybcio dma-names = "tx", "rx"; 96801e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 96901e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 97059983a5cSKonrad Dybcio #address-cells = <1>; 97159983a5cSKonrad Dybcio #size-cells = <0>; 972e5813b15SDmitry Baryshkov status = "disabled"; 973e5813b15SDmitry Baryshkov }; 974e5813b15SDmitry Baryshkov 975e5813b15SDmitry Baryshkov i2c5: i2c@994000 { 976e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 977e5813b15SDmitry Baryshkov reg = <0 0x00994000 0 0x4000>; 978e5813b15SDmitry Baryshkov clock-names = "se"; 979e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 980e5813b15SDmitry Baryshkov pinctrl-names = "default"; 981e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c5_default>; 982e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 98359983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 98459983a5cSKonrad Dybcio <&gpi_dma0 1 5 QCOM_GPI_I2C>; 98559983a5cSKonrad Dybcio dma-names = "tx", "rx"; 986e5813b15SDmitry Baryshkov #address-cells = <1>; 987e5813b15SDmitry Baryshkov #size-cells = <0>; 988e5813b15SDmitry Baryshkov status = "disabled"; 989e5813b15SDmitry Baryshkov }; 990e5813b15SDmitry Baryshkov 991e5813b15SDmitry Baryshkov spi5: spi@994000 { 992e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 993e5813b15SDmitry Baryshkov reg = <0 0x00994000 0 0x4000>; 994e5813b15SDmitry Baryshkov clock-names = "se"; 995e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 996e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 99759983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 99859983a5cSKonrad Dybcio <&gpi_dma0 1 5 QCOM_GPI_SPI>; 99959983a5cSKonrad Dybcio dma-names = "tx", "rx"; 100001e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 100101e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 100259983a5cSKonrad Dybcio #address-cells = <1>; 100359983a5cSKonrad Dybcio #size-cells = <0>; 1004e5813b15SDmitry Baryshkov status = "disabled"; 1005e5813b15SDmitry Baryshkov }; 1006e5813b15SDmitry Baryshkov 1007e5813b15SDmitry Baryshkov i2c6: i2c@998000 { 1008e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1009e5813b15SDmitry Baryshkov reg = <0 0x00998000 0 0x4000>; 1010e5813b15SDmitry Baryshkov clock-names = "se"; 1011e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1012e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1013e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c6_default>; 1014e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 101559983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 101659983a5cSKonrad Dybcio <&gpi_dma0 1 6 QCOM_GPI_I2C>; 101759983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1018e5813b15SDmitry Baryshkov #address-cells = <1>; 1019e5813b15SDmitry Baryshkov #size-cells = <0>; 1020e5813b15SDmitry Baryshkov status = "disabled"; 1021e5813b15SDmitry Baryshkov }; 1022e5813b15SDmitry Baryshkov 1023e5813b15SDmitry Baryshkov spi6: spi@998000 { 1024e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1025e5813b15SDmitry Baryshkov reg = <0 0x00998000 0 0x4000>; 1026e5813b15SDmitry Baryshkov clock-names = "se"; 1027e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1028e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 102959983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 103059983a5cSKonrad Dybcio <&gpi_dma0 1 6 QCOM_GPI_SPI>; 103159983a5cSKonrad Dybcio dma-names = "tx", "rx"; 103201e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 103301e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 103459983a5cSKonrad Dybcio #address-cells = <1>; 103559983a5cSKonrad Dybcio #size-cells = <0>; 1036e5813b15SDmitry Baryshkov status = "disabled"; 1037e5813b15SDmitry Baryshkov }; 1038e5813b15SDmitry Baryshkov 103908a9ae2dSDmitry Baryshkov uart6: serial@998000 { 104008a9ae2dSDmitry Baryshkov compatible = "qcom,geni-uart"; 104108a9ae2dSDmitry Baryshkov reg = <0 0x00998000 0 0x4000>; 104208a9ae2dSDmitry Baryshkov clock-names = "se"; 104308a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 104408a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 104508a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart6_default>; 104608a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 104701e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 104801e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 104908a9ae2dSDmitry Baryshkov status = "disabled"; 105008a9ae2dSDmitry Baryshkov }; 105108a9ae2dSDmitry Baryshkov 1052e5813b15SDmitry Baryshkov i2c7: i2c@99c000 { 1053e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1054e5813b15SDmitry Baryshkov reg = <0 0x0099c000 0 0x4000>; 1055e5813b15SDmitry Baryshkov clock-names = "se"; 1056e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1057e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1058e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c7_default>; 1059e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 106059983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 106159983a5cSKonrad Dybcio <&gpi_dma0 1 7 QCOM_GPI_I2C>; 106259983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1063e5813b15SDmitry Baryshkov #address-cells = <1>; 1064e5813b15SDmitry Baryshkov #size-cells = <0>; 1065e5813b15SDmitry Baryshkov status = "disabled"; 1066e5813b15SDmitry Baryshkov }; 1067e5813b15SDmitry Baryshkov 1068e5813b15SDmitry Baryshkov spi7: spi@99c000 { 1069e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1070e5813b15SDmitry Baryshkov reg = <0 0x0099c000 0 0x4000>; 1071e5813b15SDmitry Baryshkov clock-names = "se"; 1072e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1073e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 107459983a5cSKonrad Dybcio dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 107559983a5cSKonrad Dybcio <&gpi_dma0 1 7 QCOM_GPI_SPI>; 107659983a5cSKonrad Dybcio dma-names = "tx", "rx"; 107701e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 107801e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 107959983a5cSKonrad Dybcio #address-cells = <1>; 108059983a5cSKonrad Dybcio #size-cells = <0>; 1081e5813b15SDmitry Baryshkov status = "disabled"; 1082e5813b15SDmitry Baryshkov }; 1083e5813b15SDmitry Baryshkov }; 1084e5813b15SDmitry Baryshkov 108515049bb5SKonrad Dybcio gpi_dma1: dma-controller@a00000 { 108615049bb5SKonrad Dybcio compatible = "qcom,sm8250-gpi-dma"; 108715049bb5SKonrad Dybcio reg = <0 0x00a00000 0 0x70000>; 108815049bb5SKonrad Dybcio interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 108915049bb5SKonrad Dybcio <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 109015049bb5SKonrad Dybcio <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 109115049bb5SKonrad Dybcio <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 109215049bb5SKonrad Dybcio <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 109315049bb5SKonrad Dybcio <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 109415049bb5SKonrad Dybcio <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 109515049bb5SKonrad Dybcio <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 109615049bb5SKonrad Dybcio <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 109715049bb5SKonrad Dybcio <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 109815049bb5SKonrad Dybcio dma-channels = <10>; 109915049bb5SKonrad Dybcio dma-channel-mask = <0x3f>; 110015049bb5SKonrad Dybcio iommus = <&apps_smmu 0x56 0x0>; 110115049bb5SKonrad Dybcio #dma-cells = <3>; 110215049bb5SKonrad Dybcio status = "disabled"; 110315049bb5SKonrad Dybcio }; 110415049bb5SKonrad Dybcio 110560378f1aSVenkata Narendra Kumar Gutta qupv3_id_1: geniqup@ac0000 { 110660378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,geni-se-qup"; 110760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x00ac0000 0x0 0x6000>; 110860378f1aSVenkata Narendra Kumar Gutta clock-names = "m-ahb", "s-ahb"; 1109fe3dfc25SJonathan Marek clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1110fe3dfc25SJonathan Marek <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 111160378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 111260378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 111385309393SDmitry Baryshkov iommus = <&apps_smmu 0x43 0x0>; 111460378f1aSVenkata Narendra Kumar Gutta ranges; 111560378f1aSVenkata Narendra Kumar Gutta status = "disabled"; 111660378f1aSVenkata Narendra Kumar Gutta 1117e5813b15SDmitry Baryshkov i2c8: i2c@a80000 { 1118e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1119e5813b15SDmitry Baryshkov reg = <0 0x00a80000 0 0x4000>; 1120e5813b15SDmitry Baryshkov clock-names = "se"; 1121e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1122e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1123e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c8_default>; 1124e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 112559983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 112659983a5cSKonrad Dybcio <&gpi_dma1 1 0 QCOM_GPI_I2C>; 112759983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1128e5813b15SDmitry Baryshkov #address-cells = <1>; 1129e5813b15SDmitry Baryshkov #size-cells = <0>; 1130e5813b15SDmitry Baryshkov status = "disabled"; 1131e5813b15SDmitry Baryshkov }; 1132e5813b15SDmitry Baryshkov 1133e5813b15SDmitry Baryshkov spi8: spi@a80000 { 1134e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1135e5813b15SDmitry Baryshkov reg = <0 0x00a80000 0 0x4000>; 1136e5813b15SDmitry Baryshkov clock-names = "se"; 1137e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1138e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 113959983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 114059983a5cSKonrad Dybcio <&gpi_dma1 1 0 QCOM_GPI_SPI>; 114159983a5cSKonrad Dybcio dma-names = "tx", "rx"; 114201e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 114301e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 114459983a5cSKonrad Dybcio #address-cells = <1>; 114559983a5cSKonrad Dybcio #size-cells = <0>; 1146e5813b15SDmitry Baryshkov status = "disabled"; 1147e5813b15SDmitry Baryshkov }; 1148e5813b15SDmitry Baryshkov 1149e5813b15SDmitry Baryshkov i2c9: i2c@a84000 { 1150e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1151e5813b15SDmitry Baryshkov reg = <0 0x00a84000 0 0x4000>; 1152e5813b15SDmitry Baryshkov clock-names = "se"; 1153e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1154e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1155e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c9_default>; 1156e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 115759983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 115859983a5cSKonrad Dybcio <&gpi_dma1 1 1 QCOM_GPI_I2C>; 115959983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1160e5813b15SDmitry Baryshkov #address-cells = <1>; 1161e5813b15SDmitry Baryshkov #size-cells = <0>; 1162e5813b15SDmitry Baryshkov status = "disabled"; 1163e5813b15SDmitry Baryshkov }; 1164e5813b15SDmitry Baryshkov 1165e5813b15SDmitry Baryshkov spi9: spi@a84000 { 1166e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1167e5813b15SDmitry Baryshkov reg = <0 0x00a84000 0 0x4000>; 1168e5813b15SDmitry Baryshkov clock-names = "se"; 1169e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1170e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 117159983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 117259983a5cSKonrad Dybcio <&gpi_dma1 1 1 QCOM_GPI_SPI>; 117359983a5cSKonrad Dybcio dma-names = "tx", "rx"; 117401e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 117501e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 117659983a5cSKonrad Dybcio #address-cells = <1>; 117759983a5cSKonrad Dybcio #size-cells = <0>; 1178e5813b15SDmitry Baryshkov status = "disabled"; 1179e5813b15SDmitry Baryshkov }; 1180e5813b15SDmitry Baryshkov 1181e5813b15SDmitry Baryshkov i2c10: i2c@a88000 { 1182e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1183e5813b15SDmitry Baryshkov reg = <0 0x00a88000 0 0x4000>; 1184e5813b15SDmitry Baryshkov clock-names = "se"; 1185e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1186e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1187e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c10_default>; 1188e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 118959983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 119059983a5cSKonrad Dybcio <&gpi_dma1 1 2 QCOM_GPI_I2C>; 119159983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1192e5813b15SDmitry Baryshkov #address-cells = <1>; 1193e5813b15SDmitry Baryshkov #size-cells = <0>; 1194e5813b15SDmitry Baryshkov status = "disabled"; 1195e5813b15SDmitry Baryshkov }; 1196e5813b15SDmitry Baryshkov 1197e5813b15SDmitry Baryshkov spi10: spi@a88000 { 1198e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1199e5813b15SDmitry Baryshkov reg = <0 0x00a88000 0 0x4000>; 1200e5813b15SDmitry Baryshkov clock-names = "se"; 1201e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1202e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 120359983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 120459983a5cSKonrad Dybcio <&gpi_dma1 1 2 QCOM_GPI_SPI>; 120559983a5cSKonrad Dybcio dma-names = "tx", "rx"; 120601e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 120701e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 120859983a5cSKonrad Dybcio #address-cells = <1>; 120959983a5cSKonrad Dybcio #size-cells = <0>; 1210e5813b15SDmitry Baryshkov status = "disabled"; 1211e5813b15SDmitry Baryshkov }; 1212e5813b15SDmitry Baryshkov 1213e5813b15SDmitry Baryshkov i2c11: i2c@a8c000 { 1214e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1215e5813b15SDmitry Baryshkov reg = <0 0x00a8c000 0 0x4000>; 1216e5813b15SDmitry Baryshkov clock-names = "se"; 1217e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1218e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1219e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c11_default>; 1220e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 122159983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 122259983a5cSKonrad Dybcio <&gpi_dma1 1 3 QCOM_GPI_I2C>; 122359983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1224e5813b15SDmitry Baryshkov #address-cells = <1>; 1225e5813b15SDmitry Baryshkov #size-cells = <0>; 1226e5813b15SDmitry Baryshkov status = "disabled"; 1227e5813b15SDmitry Baryshkov }; 1228e5813b15SDmitry Baryshkov 1229e5813b15SDmitry Baryshkov spi11: spi@a8c000 { 1230e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1231e5813b15SDmitry Baryshkov reg = <0 0x00a8c000 0 0x4000>; 1232e5813b15SDmitry Baryshkov clock-names = "se"; 1233e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1234e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 123559983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 123659983a5cSKonrad Dybcio <&gpi_dma1 1 3 QCOM_GPI_SPI>; 123759983a5cSKonrad Dybcio dma-names = "tx", "rx"; 123801e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 123901e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 124059983a5cSKonrad Dybcio #address-cells = <1>; 124159983a5cSKonrad Dybcio #size-cells = <0>; 1242e5813b15SDmitry Baryshkov status = "disabled"; 1243e5813b15SDmitry Baryshkov }; 1244e5813b15SDmitry Baryshkov 1245e5813b15SDmitry Baryshkov i2c12: i2c@a90000 { 1246e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1247e5813b15SDmitry Baryshkov reg = <0 0x00a90000 0 0x4000>; 1248e5813b15SDmitry Baryshkov clock-names = "se"; 1249e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1250e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1251e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c12_default>; 1252e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 125359983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 125459983a5cSKonrad Dybcio <&gpi_dma1 1 4 QCOM_GPI_I2C>; 125559983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1256e5813b15SDmitry Baryshkov #address-cells = <1>; 1257e5813b15SDmitry Baryshkov #size-cells = <0>; 1258e5813b15SDmitry Baryshkov status = "disabled"; 1259e5813b15SDmitry Baryshkov }; 1260e5813b15SDmitry Baryshkov 1261e5813b15SDmitry Baryshkov spi12: spi@a90000 { 1262e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1263e5813b15SDmitry Baryshkov reg = <0 0x00a90000 0 0x4000>; 1264e5813b15SDmitry Baryshkov clock-names = "se"; 1265e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1266e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 126759983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 126859983a5cSKonrad Dybcio <&gpi_dma1 1 4 QCOM_GPI_SPI>; 126959983a5cSKonrad Dybcio dma-names = "tx", "rx"; 127001e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 127101e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 127259983a5cSKonrad Dybcio #address-cells = <1>; 127359983a5cSKonrad Dybcio #size-cells = <0>; 1274e5813b15SDmitry Baryshkov status = "disabled"; 1275e5813b15SDmitry Baryshkov }; 1276e5813b15SDmitry Baryshkov 1277bb1dfb4dSManivannan Sadhasivam uart12: serial@a90000 { 127860378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,geni-debug-uart"; 127960378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x00a90000 0x0 0x4000>; 128060378f1aSVenkata Narendra Kumar Gutta clock-names = "se"; 1281fe3dfc25SJonathan Marek clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1282bb1dfb4dSManivannan Sadhasivam pinctrl-names = "default"; 1283bb1dfb4dSManivannan Sadhasivam pinctrl-0 = <&qup_uart12_default>; 128460378f1aSVenkata Narendra Kumar Gutta interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 128501e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 128601e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 128760378f1aSVenkata Narendra Kumar Gutta status = "disabled"; 128860378f1aSVenkata Narendra Kumar Gutta }; 1289e5813b15SDmitry Baryshkov 1290e5813b15SDmitry Baryshkov i2c13: i2c@a94000 { 1291e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1292e5813b15SDmitry Baryshkov reg = <0 0x00a94000 0 0x4000>; 1293e5813b15SDmitry Baryshkov clock-names = "se"; 1294e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1295e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1296e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c13_default>; 1297e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 129859983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 129959983a5cSKonrad Dybcio <&gpi_dma1 1 5 QCOM_GPI_I2C>; 130059983a5cSKonrad Dybcio dma-names = "tx", "rx"; 1301e5813b15SDmitry Baryshkov #address-cells = <1>; 1302e5813b15SDmitry Baryshkov #size-cells = <0>; 1303e5813b15SDmitry Baryshkov status = "disabled"; 1304e5813b15SDmitry Baryshkov }; 1305e5813b15SDmitry Baryshkov 1306e5813b15SDmitry Baryshkov spi13: spi@a94000 { 1307e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1308e5813b15SDmitry Baryshkov reg = <0 0x00a94000 0 0x4000>; 1309e5813b15SDmitry Baryshkov clock-names = "se"; 1310e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1311e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 131259983a5cSKonrad Dybcio dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 131359983a5cSKonrad Dybcio <&gpi_dma1 1 5 QCOM_GPI_SPI>; 131459983a5cSKonrad Dybcio dma-names = "tx", "rx"; 131501e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 131601e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 131759983a5cSKonrad Dybcio #address-cells = <1>; 131859983a5cSKonrad Dybcio #size-cells = <0>; 1319e5813b15SDmitry Baryshkov status = "disabled"; 1320e5813b15SDmitry Baryshkov }; 132160378f1aSVenkata Narendra Kumar Gutta }; 132260378f1aSVenkata Narendra Kumar Gutta 1323e7e41a20SJonathan Marek config_noc: interconnect@1500000 { 1324e7e41a20SJonathan Marek compatible = "qcom,sm8250-config-noc"; 1325e7e41a20SJonathan Marek reg = <0 0x01500000 0 0xa580>; 1326e7e41a20SJonathan Marek #interconnect-cells = <1>; 1327e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1328e7e41a20SJonathan Marek }; 1329e7e41a20SJonathan Marek 1330e7e41a20SJonathan Marek system_noc: interconnect@1620000 { 1331e7e41a20SJonathan Marek compatible = "qcom,sm8250-system-noc"; 1332e7e41a20SJonathan Marek reg = <0 0x01620000 0 0x1c200>; 1333e7e41a20SJonathan Marek #interconnect-cells = <1>; 1334e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1335e7e41a20SJonathan Marek }; 1336e7e41a20SJonathan Marek 1337e7e41a20SJonathan Marek mc_virt: interconnect@163d000 { 1338e7e41a20SJonathan Marek compatible = "qcom,sm8250-mc-virt"; 1339e7e41a20SJonathan Marek reg = <0 0x0163d000 0 0x1000>; 1340e7e41a20SJonathan Marek #interconnect-cells = <1>; 1341e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1342e7e41a20SJonathan Marek }; 1343e7e41a20SJonathan Marek 1344e7e41a20SJonathan Marek aggre1_noc: interconnect@16e0000 { 1345e7e41a20SJonathan Marek compatible = "qcom,sm8250-aggre1-noc"; 1346e7e41a20SJonathan Marek reg = <0 0x016e0000 0 0x1f180>; 1347e7e41a20SJonathan Marek #interconnect-cells = <1>; 1348e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1349e7e41a20SJonathan Marek }; 1350e7e41a20SJonathan Marek 1351e7e41a20SJonathan Marek aggre2_noc: interconnect@1700000 { 1352e7e41a20SJonathan Marek compatible = "qcom,sm8250-aggre2-noc"; 1353e7e41a20SJonathan Marek reg = <0 0x01700000 0 0x33000>; 1354e7e41a20SJonathan Marek #interconnect-cells = <1>; 1355e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1356e7e41a20SJonathan Marek }; 1357e7e41a20SJonathan Marek 1358e7e41a20SJonathan Marek compute_noc: interconnect@1733000 { 1359e7e41a20SJonathan Marek compatible = "qcom,sm8250-compute-noc"; 1360e7e41a20SJonathan Marek reg = <0 0x01733000 0 0xa180>; 1361e7e41a20SJonathan Marek #interconnect-cells = <1>; 1362e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1363e7e41a20SJonathan Marek }; 1364e7e41a20SJonathan Marek 1365e7e41a20SJonathan Marek mmss_noc: interconnect@1740000 { 1366e7e41a20SJonathan Marek compatible = "qcom,sm8250-mmss-noc"; 1367e7e41a20SJonathan Marek reg = <0 0x01740000 0 0x1f080>; 1368e7e41a20SJonathan Marek #interconnect-cells = <1>; 1369e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1370e7e41a20SJonathan Marek }; 1371e7e41a20SJonathan Marek 1372e53bdfc0SManivannan Sadhasivam pcie0: pci@1c00000 { 1373e53bdfc0SManivannan Sadhasivam compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1374e53bdfc0SManivannan Sadhasivam reg = <0 0x01c00000 0 0x3000>, 1375e53bdfc0SManivannan Sadhasivam <0 0x60000000 0 0xf1d>, 1376e53bdfc0SManivannan Sadhasivam <0 0x60000f20 0 0xa8>, 1377e53bdfc0SManivannan Sadhasivam <0 0x60001000 0 0x1000>, 1378e53bdfc0SManivannan Sadhasivam <0 0x60100000 0 0x100000>; 1379e53bdfc0SManivannan Sadhasivam reg-names = "parf", "dbi", "elbi", "atu", "config"; 1380e53bdfc0SManivannan Sadhasivam device_type = "pci"; 1381e53bdfc0SManivannan Sadhasivam linux,pci-domain = <0>; 1382e53bdfc0SManivannan Sadhasivam bus-range = <0x00 0xff>; 1383e53bdfc0SManivannan Sadhasivam num-lanes = <1>; 1384e53bdfc0SManivannan Sadhasivam 1385e53bdfc0SManivannan Sadhasivam #address-cells = <3>; 1386e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1387e53bdfc0SManivannan Sadhasivam 1388e53bdfc0SManivannan Sadhasivam ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1389e53bdfc0SManivannan Sadhasivam <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1390e53bdfc0SManivannan Sadhasivam 1391e53bdfc0SManivannan Sadhasivam interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1392e53bdfc0SManivannan Sadhasivam interrupt-names = "msi"; 1393e53bdfc0SManivannan Sadhasivam #interrupt-cells = <1>; 1394e53bdfc0SManivannan Sadhasivam interrupt-map-mask = <0 0 0 0x7>; 1395e53bdfc0SManivannan Sadhasivam interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1396e53bdfc0SManivannan Sadhasivam <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1397e53bdfc0SManivannan Sadhasivam <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1398e53bdfc0SManivannan Sadhasivam <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1399e53bdfc0SManivannan Sadhasivam 1400e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1401e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_AUX_CLK>, 1402e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1403e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1404e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1405e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1406e53bdfc0SManivannan Sadhasivam <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1407e53bdfc0SManivannan Sadhasivam <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1408e53bdfc0SManivannan Sadhasivam clock-names = "pipe", 1409e53bdfc0SManivannan Sadhasivam "aux", 1410e53bdfc0SManivannan Sadhasivam "cfg", 1411e53bdfc0SManivannan Sadhasivam "bus_master", 1412e53bdfc0SManivannan Sadhasivam "bus_slave", 1413e53bdfc0SManivannan Sadhasivam "slave_q2a", 1414e53bdfc0SManivannan Sadhasivam "tbu", 1415e53bdfc0SManivannan Sadhasivam "ddrss_sf_tbu"; 1416e53bdfc0SManivannan Sadhasivam 1417e53bdfc0SManivannan Sadhasivam iommus = <&apps_smmu 0x1c00 0x7f>; 1418e53bdfc0SManivannan Sadhasivam iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1419e53bdfc0SManivannan Sadhasivam <0x100 &apps_smmu 0x1c01 0x1>; 1420e53bdfc0SManivannan Sadhasivam 1421e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_0_BCR>; 1422e53bdfc0SManivannan Sadhasivam reset-names = "pci"; 1423e53bdfc0SManivannan Sadhasivam 1424e53bdfc0SManivannan Sadhasivam power-domains = <&gcc PCIE_0_GDSC>; 1425e53bdfc0SManivannan Sadhasivam 1426e53bdfc0SManivannan Sadhasivam phys = <&pcie0_lane>; 1427e53bdfc0SManivannan Sadhasivam phy-names = "pciephy"; 1428e53bdfc0SManivannan Sadhasivam 142913e948a3SKonrad Dybcio perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; 143013e948a3SKonrad Dybcio enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; 143113e948a3SKonrad Dybcio 143213e948a3SKonrad Dybcio pinctrl-names = "default"; 143313e948a3SKonrad Dybcio pinctrl-0 = <&pcie0_default_state>; 143413e948a3SKonrad Dybcio 1435e53bdfc0SManivannan Sadhasivam status = "disabled"; 1436e53bdfc0SManivannan Sadhasivam }; 1437e53bdfc0SManivannan Sadhasivam 1438e53bdfc0SManivannan Sadhasivam pcie0_phy: phy@1c06000 { 1439e53bdfc0SManivannan Sadhasivam compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1440e53bdfc0SManivannan Sadhasivam reg = <0 0x01c06000 0 0x1c0>; 1441e53bdfc0SManivannan Sadhasivam #address-cells = <2>; 1442e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1443e53bdfc0SManivannan Sadhasivam ranges; 1444e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1445e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1446e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1447e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1448e53bdfc0SManivannan Sadhasivam clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1449e53bdfc0SManivannan Sadhasivam 1450e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1451e53bdfc0SManivannan Sadhasivam reset-names = "phy"; 1452e53bdfc0SManivannan Sadhasivam 1453e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1454e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <100000000>; 1455e53bdfc0SManivannan Sadhasivam 1456e53bdfc0SManivannan Sadhasivam status = "disabled"; 1457e53bdfc0SManivannan Sadhasivam 14581351512fSShawn Guo pcie0_lane: phy@1c06200 { 1459e53bdfc0SManivannan Sadhasivam reg = <0 0x1c06200 0 0x170>, /* tx */ 1460e53bdfc0SManivannan Sadhasivam <0 0x1c06400 0 0x200>, /* rx */ 1461e53bdfc0SManivannan Sadhasivam <0 0x1c06800 0 0x1f0>, /* pcs */ 1462e53bdfc0SManivannan Sadhasivam <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1463e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1464e53bdfc0SManivannan Sadhasivam clock-names = "pipe0"; 1465e53bdfc0SManivannan Sadhasivam 1466e53bdfc0SManivannan Sadhasivam #phy-cells = <0>; 1467e53bdfc0SManivannan Sadhasivam clock-output-names = "pcie_0_pipe_clk"; 1468e53bdfc0SManivannan Sadhasivam }; 1469e53bdfc0SManivannan Sadhasivam }; 1470e53bdfc0SManivannan Sadhasivam 1471e53bdfc0SManivannan Sadhasivam pcie1: pci@1c08000 { 1472e53bdfc0SManivannan Sadhasivam compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1473e53bdfc0SManivannan Sadhasivam reg = <0 0x01c08000 0 0x3000>, 1474e53bdfc0SManivannan Sadhasivam <0 0x40000000 0 0xf1d>, 1475e53bdfc0SManivannan Sadhasivam <0 0x40000f20 0 0xa8>, 1476e53bdfc0SManivannan Sadhasivam <0 0x40001000 0 0x1000>, 1477e53bdfc0SManivannan Sadhasivam <0 0x40100000 0 0x100000>; 1478e53bdfc0SManivannan Sadhasivam reg-names = "parf", "dbi", "elbi", "atu", "config"; 1479e53bdfc0SManivannan Sadhasivam device_type = "pci"; 1480e53bdfc0SManivannan Sadhasivam linux,pci-domain = <1>; 1481e53bdfc0SManivannan Sadhasivam bus-range = <0x00 0xff>; 1482e53bdfc0SManivannan Sadhasivam num-lanes = <2>; 1483e53bdfc0SManivannan Sadhasivam 1484e53bdfc0SManivannan Sadhasivam #address-cells = <3>; 1485e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1486e53bdfc0SManivannan Sadhasivam 1487e53bdfc0SManivannan Sadhasivam ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1488e53bdfc0SManivannan Sadhasivam <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1489e53bdfc0SManivannan Sadhasivam 1490e53bdfc0SManivannan Sadhasivam interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>; 1491e53bdfc0SManivannan Sadhasivam interrupt-names = "msi"; 1492e53bdfc0SManivannan Sadhasivam #interrupt-cells = <1>; 1493e53bdfc0SManivannan Sadhasivam interrupt-map-mask = <0 0 0 0x7>; 1494e53bdfc0SManivannan Sadhasivam interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1495e53bdfc0SManivannan Sadhasivam <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1496e53bdfc0SManivannan Sadhasivam <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1497e53bdfc0SManivannan Sadhasivam <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1498e53bdfc0SManivannan Sadhasivam 1499e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1500e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_AUX_CLK>, 1501e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1502e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1503e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1504e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1505e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1506e53bdfc0SManivannan Sadhasivam <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1507e53bdfc0SManivannan Sadhasivam <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1508e53bdfc0SManivannan Sadhasivam clock-names = "pipe", 1509e53bdfc0SManivannan Sadhasivam "aux", 1510e53bdfc0SManivannan Sadhasivam "cfg", 1511e53bdfc0SManivannan Sadhasivam "bus_master", 1512e53bdfc0SManivannan Sadhasivam "bus_slave", 1513e53bdfc0SManivannan Sadhasivam "slave_q2a", 1514e53bdfc0SManivannan Sadhasivam "ref", 1515e53bdfc0SManivannan Sadhasivam "tbu", 1516e53bdfc0SManivannan Sadhasivam "ddrss_sf_tbu"; 1517e53bdfc0SManivannan Sadhasivam 1518e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1519e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <19200000>; 1520e53bdfc0SManivannan Sadhasivam 1521e53bdfc0SManivannan Sadhasivam iommus = <&apps_smmu 0x1c80 0x7f>; 1522e53bdfc0SManivannan Sadhasivam iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1523e53bdfc0SManivannan Sadhasivam <0x100 &apps_smmu 0x1c81 0x1>; 1524e53bdfc0SManivannan Sadhasivam 1525e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_1_BCR>; 1526e53bdfc0SManivannan Sadhasivam reset-names = "pci"; 1527e53bdfc0SManivannan Sadhasivam 1528e53bdfc0SManivannan Sadhasivam power-domains = <&gcc PCIE_1_GDSC>; 1529e53bdfc0SManivannan Sadhasivam 1530e53bdfc0SManivannan Sadhasivam phys = <&pcie1_lane>; 1531e53bdfc0SManivannan Sadhasivam phy-names = "pciephy"; 1532e53bdfc0SManivannan Sadhasivam 153313e948a3SKonrad Dybcio perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>; 153413e948a3SKonrad Dybcio enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; 153513e948a3SKonrad Dybcio 153613e948a3SKonrad Dybcio pinctrl-names = "default"; 153713e948a3SKonrad Dybcio pinctrl-0 = <&pcie1_default_state>; 153813e948a3SKonrad Dybcio 1539e53bdfc0SManivannan Sadhasivam status = "disabled"; 1540e53bdfc0SManivannan Sadhasivam }; 1541e53bdfc0SManivannan Sadhasivam 1542e53bdfc0SManivannan Sadhasivam pcie1_phy: phy@1c0e000 { 1543e53bdfc0SManivannan Sadhasivam compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1544e53bdfc0SManivannan Sadhasivam reg = <0 0x01c0e000 0 0x1c0>; 1545e53bdfc0SManivannan Sadhasivam #address-cells = <2>; 1546e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1547e53bdfc0SManivannan Sadhasivam ranges; 1548e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1549e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1550e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1551e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1552e53bdfc0SManivannan Sadhasivam clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1553e53bdfc0SManivannan Sadhasivam 1554e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1555e53bdfc0SManivannan Sadhasivam reset-names = "phy"; 1556e53bdfc0SManivannan Sadhasivam 1557e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1558e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <100000000>; 1559e53bdfc0SManivannan Sadhasivam 1560e53bdfc0SManivannan Sadhasivam status = "disabled"; 1561e53bdfc0SManivannan Sadhasivam 15621351512fSShawn Guo pcie1_lane: phy@1c0e200 { 1563e53bdfc0SManivannan Sadhasivam reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1564e53bdfc0SManivannan Sadhasivam <0 0x1c0e400 0 0x200>, /* rx0 */ 1565e53bdfc0SManivannan Sadhasivam <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1566e53bdfc0SManivannan Sadhasivam <0 0x1c0e600 0 0x170>, /* tx1 */ 1567e53bdfc0SManivannan Sadhasivam <0 0x1c0e800 0 0x200>, /* rx1 */ 1568e53bdfc0SManivannan Sadhasivam <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1569e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1570e53bdfc0SManivannan Sadhasivam clock-names = "pipe0"; 1571e53bdfc0SManivannan Sadhasivam 1572e53bdfc0SManivannan Sadhasivam #phy-cells = <0>; 1573e53bdfc0SManivannan Sadhasivam clock-output-names = "pcie_1_pipe_clk"; 1574e53bdfc0SManivannan Sadhasivam }; 1575e53bdfc0SManivannan Sadhasivam }; 1576e53bdfc0SManivannan Sadhasivam 1577e53bdfc0SManivannan Sadhasivam pcie2: pci@1c10000 { 1578e53bdfc0SManivannan Sadhasivam compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1579e53bdfc0SManivannan Sadhasivam reg = <0 0x01c10000 0 0x3000>, 1580e53bdfc0SManivannan Sadhasivam <0 0x64000000 0 0xf1d>, 1581e53bdfc0SManivannan Sadhasivam <0 0x64000f20 0 0xa8>, 1582e53bdfc0SManivannan Sadhasivam <0 0x64001000 0 0x1000>, 1583e53bdfc0SManivannan Sadhasivam <0 0x64100000 0 0x100000>; 1584e53bdfc0SManivannan Sadhasivam reg-names = "parf", "dbi", "elbi", "atu", "config"; 1585e53bdfc0SManivannan Sadhasivam device_type = "pci"; 1586e53bdfc0SManivannan Sadhasivam linux,pci-domain = <2>; 1587e53bdfc0SManivannan Sadhasivam bus-range = <0x00 0xff>; 1588e53bdfc0SManivannan Sadhasivam num-lanes = <2>; 1589e53bdfc0SManivannan Sadhasivam 1590e53bdfc0SManivannan Sadhasivam #address-cells = <3>; 1591e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1592e53bdfc0SManivannan Sadhasivam 1593e53bdfc0SManivannan Sadhasivam ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, 1594e53bdfc0SManivannan Sadhasivam <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 1595e53bdfc0SManivannan Sadhasivam 1596e53bdfc0SManivannan Sadhasivam interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; 1597e53bdfc0SManivannan Sadhasivam interrupt-names = "msi"; 1598e53bdfc0SManivannan Sadhasivam #interrupt-cells = <1>; 1599e53bdfc0SManivannan Sadhasivam interrupt-map-mask = <0 0 0 0x7>; 1600e53bdfc0SManivannan Sadhasivam interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1601e53bdfc0SManivannan Sadhasivam <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1602e53bdfc0SManivannan Sadhasivam <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1603e53bdfc0SManivannan Sadhasivam <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1604e53bdfc0SManivannan Sadhasivam 1605e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1606e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_AUX_CLK>, 1607e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1608e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1609e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 1610e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 1611e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1612e53bdfc0SManivannan Sadhasivam <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1613e53bdfc0SManivannan Sadhasivam <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1614e53bdfc0SManivannan Sadhasivam clock-names = "pipe", 1615e53bdfc0SManivannan Sadhasivam "aux", 1616e53bdfc0SManivannan Sadhasivam "cfg", 1617e53bdfc0SManivannan Sadhasivam "bus_master", 1618e53bdfc0SManivannan Sadhasivam "bus_slave", 1619e53bdfc0SManivannan Sadhasivam "slave_q2a", 1620e53bdfc0SManivannan Sadhasivam "ref", 1621e53bdfc0SManivannan Sadhasivam "tbu", 1622e53bdfc0SManivannan Sadhasivam "ddrss_sf_tbu"; 1623e53bdfc0SManivannan Sadhasivam 1624e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 1625e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <19200000>; 1626e53bdfc0SManivannan Sadhasivam 1627e53bdfc0SManivannan Sadhasivam iommus = <&apps_smmu 0x1d00 0x7f>; 1628e53bdfc0SManivannan Sadhasivam iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 1629e53bdfc0SManivannan Sadhasivam <0x100 &apps_smmu 0x1d01 0x1>; 1630e53bdfc0SManivannan Sadhasivam 1631e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_2_BCR>; 1632e53bdfc0SManivannan Sadhasivam reset-names = "pci"; 1633e53bdfc0SManivannan Sadhasivam 1634e53bdfc0SManivannan Sadhasivam power-domains = <&gcc PCIE_2_GDSC>; 1635e53bdfc0SManivannan Sadhasivam 1636e53bdfc0SManivannan Sadhasivam phys = <&pcie2_lane>; 1637e53bdfc0SManivannan Sadhasivam phy-names = "pciephy"; 1638e53bdfc0SManivannan Sadhasivam 163913e948a3SKonrad Dybcio perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>; 164013e948a3SKonrad Dybcio enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; 164113e948a3SKonrad Dybcio 164213e948a3SKonrad Dybcio pinctrl-names = "default"; 164313e948a3SKonrad Dybcio pinctrl-0 = <&pcie2_default_state>; 164413e948a3SKonrad Dybcio 1645e53bdfc0SManivannan Sadhasivam status = "disabled"; 1646e53bdfc0SManivannan Sadhasivam }; 1647e53bdfc0SManivannan Sadhasivam 1648e53bdfc0SManivannan Sadhasivam pcie2_phy: phy@1c16000 { 1649e53bdfc0SManivannan Sadhasivam compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 1650e53bdfc0SManivannan Sadhasivam reg = <0 0x1c16000 0 0x1c0>; 1651e53bdfc0SManivannan Sadhasivam #address-cells = <2>; 1652e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1653e53bdfc0SManivannan Sadhasivam ranges; 1654e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1655e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1656e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1657e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1658e53bdfc0SManivannan Sadhasivam clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1659e53bdfc0SManivannan Sadhasivam 1660e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_2_PHY_BCR>; 1661e53bdfc0SManivannan Sadhasivam reset-names = "phy"; 1662e53bdfc0SManivannan Sadhasivam 1663e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1664e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <100000000>; 1665e53bdfc0SManivannan Sadhasivam 1666e53bdfc0SManivannan Sadhasivam status = "disabled"; 1667e53bdfc0SManivannan Sadhasivam 16681351512fSShawn Guo pcie2_lane: phy@1c16200 { 1669e53bdfc0SManivannan Sadhasivam reg = <0 0x1c16200 0 0x170>, /* tx0 */ 1670e53bdfc0SManivannan Sadhasivam <0 0x1c16400 0 0x200>, /* rx0 */ 1671e53bdfc0SManivannan Sadhasivam <0 0x1c16a00 0 0x1f0>, /* pcs */ 1672e53bdfc0SManivannan Sadhasivam <0 0x1c16600 0 0x170>, /* tx1 */ 1673e53bdfc0SManivannan Sadhasivam <0 0x1c16800 0 0x200>, /* rx1 */ 1674e53bdfc0SManivannan Sadhasivam <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1675e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 1676e53bdfc0SManivannan Sadhasivam clock-names = "pipe0"; 1677e53bdfc0SManivannan Sadhasivam 1678e53bdfc0SManivannan Sadhasivam #phy-cells = <0>; 1679e53bdfc0SManivannan Sadhasivam clock-output-names = "pcie_2_pipe_clk"; 1680e53bdfc0SManivannan Sadhasivam }; 1681e53bdfc0SManivannan Sadhasivam }; 1682e53bdfc0SManivannan Sadhasivam 16836b9afd8fSJonathan Marek ufs_mem_hc: ufshc@1d84000 { 1684b7e2fba0SBryan O'Donoghue compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 1685b7e2fba0SBryan O'Donoghue "jedec,ufs-2.0"; 1686b7e2fba0SBryan O'Donoghue reg = <0 0x01d84000 0 0x3000>; 1687b7e2fba0SBryan O'Donoghue interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1688b7e2fba0SBryan O'Donoghue phys = <&ufs_mem_phy_lanes>; 1689b7e2fba0SBryan O'Donoghue phy-names = "ufsphy"; 1690b7e2fba0SBryan O'Donoghue lanes-per-direction = <2>; 1691b7e2fba0SBryan O'Donoghue #reset-cells = <1>; 1692b7e2fba0SBryan O'Donoghue resets = <&gcc GCC_UFS_PHY_BCR>; 1693b7e2fba0SBryan O'Donoghue reset-names = "rst"; 1694b7e2fba0SBryan O'Donoghue 1695b7e2fba0SBryan O'Donoghue power-domains = <&gcc UFS_PHY_GDSC>; 1696b7e2fba0SBryan O'Donoghue 1697a89441fcSJonathan Marek iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 1698a89441fcSJonathan Marek 1699b7e2fba0SBryan O'Donoghue clock-names = 1700b7e2fba0SBryan O'Donoghue "core_clk", 1701b7e2fba0SBryan O'Donoghue "bus_aggr_clk", 1702b7e2fba0SBryan O'Donoghue "iface_clk", 1703b7e2fba0SBryan O'Donoghue "core_clk_unipro", 1704b7e2fba0SBryan O'Donoghue "ref_clk", 1705b7e2fba0SBryan O'Donoghue "tx_lane0_sync_clk", 1706b7e2fba0SBryan O'Donoghue "rx_lane0_sync_clk", 1707b7e2fba0SBryan O'Donoghue "rx_lane1_sync_clk"; 1708b7e2fba0SBryan O'Donoghue clocks = 1709b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_AXI_CLK>, 1710b7e2fba0SBryan O'Donoghue <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1711b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_AHB_CLK>, 1712b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1713b7e2fba0SBryan O'Donoghue <&rpmhcc RPMH_CXO_CLK>, 1714b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1715b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1716b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1717b7e2fba0SBryan O'Donoghue freq-table-hz = 1718b7e2fba0SBryan O'Donoghue <37500000 300000000>, 1719b7e2fba0SBryan O'Donoghue <0 0>, 1720b7e2fba0SBryan O'Donoghue <0 0>, 1721b7e2fba0SBryan O'Donoghue <37500000 300000000>, 1722b7e2fba0SBryan O'Donoghue <0 0>, 1723b7e2fba0SBryan O'Donoghue <0 0>, 1724b7e2fba0SBryan O'Donoghue <0 0>, 1725b7e2fba0SBryan O'Donoghue <0 0>; 1726b7e2fba0SBryan O'Donoghue 1727b7e2fba0SBryan O'Donoghue status = "disabled"; 1728b7e2fba0SBryan O'Donoghue }; 1729b7e2fba0SBryan O'Donoghue 1730b7e2fba0SBryan O'Donoghue ufs_mem_phy: phy@1d87000 { 1731b7e2fba0SBryan O'Donoghue compatible = "qcom,sm8250-qmp-ufs-phy"; 1732b7e2fba0SBryan O'Donoghue reg = <0 0x01d87000 0 0x1c0>; 1733b7e2fba0SBryan O'Donoghue #address-cells = <2>; 1734b7e2fba0SBryan O'Donoghue #size-cells = <2>; 1735b7e2fba0SBryan O'Donoghue ranges; 1736b7e2fba0SBryan O'Donoghue clock-names = "ref", 1737b7e2fba0SBryan O'Donoghue "ref_aux"; 1738b7e2fba0SBryan O'Donoghue clocks = <&rpmhcc RPMH_CXO_CLK>, 1739b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1740b7e2fba0SBryan O'Donoghue 1741b7e2fba0SBryan O'Donoghue resets = <&ufs_mem_hc 0>; 1742b7e2fba0SBryan O'Donoghue reset-names = "ufsphy"; 1743b7e2fba0SBryan O'Donoghue status = "disabled"; 1744b7e2fba0SBryan O'Donoghue 17451351512fSShawn Guo ufs_mem_phy_lanes: phy@1d87400 { 1746b7e2fba0SBryan O'Donoghue reg = <0 0x01d87400 0 0x108>, 1747b7e2fba0SBryan O'Donoghue <0 0x01d87600 0 0x1e0>, 1748b7e2fba0SBryan O'Donoghue <0 0x01d87c00 0 0x1dc>, 1749b7e2fba0SBryan O'Donoghue <0 0x01d87800 0 0x108>, 1750b7e2fba0SBryan O'Donoghue <0 0x01d87a00 0 0x1e0>; 1751b7e2fba0SBryan O'Donoghue #phy-cells = <0>; 1752b7e2fba0SBryan O'Donoghue }; 1753b7e2fba0SBryan O'Donoghue }; 1754b7e2fba0SBryan O'Donoghue 1755e7e41a20SJonathan Marek ipa_virt: interconnect@1e00000 { 1756e7e41a20SJonathan Marek compatible = "qcom,sm8250-ipa-virt"; 1757e7e41a20SJonathan Marek reg = <0 0x01e00000 0 0x1000>; 1758e7e41a20SJonathan Marek #interconnect-cells = <1>; 1759e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1760e7e41a20SJonathan Marek }; 1761e7e41a20SJonathan Marek 1762dff0f49cSBjorn Andersson tcsr_mutex: hwlock@1f40000 { 1763dff0f49cSBjorn Andersson compatible = "qcom,tcsr-mutex"; 1764b9ec8cbcSJonathan Marek reg = <0x0 0x01f40000 0x0 0x40000>; 1765dff0f49cSBjorn Andersson #hwlock-cells = <1>; 176660378f1aSVenkata Narendra Kumar Gutta }; 176760378f1aSVenkata Narendra Kumar Gutta 1768768270caSSrinivas Kandagatla wsamacro: codec@3240000 { 1769768270caSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-wsa-macro"; 1770768270caSSrinivas Kandagatla reg = <0 0x03240000 0 0x1000>; 1771768270caSSrinivas Kandagatla clocks = <&audiocc 1>, 1772768270caSSrinivas Kandagatla <&audiocc 0>, 1773768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1774768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1775768270caSSrinivas Kandagatla <&aoncc 0>, 1776768270caSSrinivas Kandagatla <&vamacro>; 1777768270caSSrinivas Kandagatla 1778768270caSSrinivas Kandagatla clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 1779768270caSSrinivas Kandagatla 1780768270caSSrinivas Kandagatla #clock-cells = <0>; 1781768270caSSrinivas Kandagatla clock-frequency = <9600000>; 1782768270caSSrinivas Kandagatla clock-output-names = "mclk"; 1783768270caSSrinivas Kandagatla #sound-dai-cells = <1>; 1784768270caSSrinivas Kandagatla 1785768270caSSrinivas Kandagatla pinctrl-names = "default"; 1786768270caSSrinivas Kandagatla pinctrl-0 = <&wsa_swr_active>; 1787768270caSSrinivas Kandagatla }; 1788768270caSSrinivas Kandagatla 1789768270caSSrinivas Kandagatla swr0: soundwire-controller@3250000 { 1790768270caSSrinivas Kandagatla reg = <0 0x03250000 0 0x2000>; 1791768270caSSrinivas Kandagatla compatible = "qcom,soundwire-v1.5.1"; 1792768270caSSrinivas Kandagatla interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1793768270caSSrinivas Kandagatla clocks = <&wsamacro>; 1794768270caSSrinivas Kandagatla clock-names = "iface"; 1795768270caSSrinivas Kandagatla 1796768270caSSrinivas Kandagatla qcom,din-ports = <2>; 1797768270caSSrinivas Kandagatla qcom,dout-ports = <6>; 1798768270caSSrinivas Kandagatla 1799768270caSSrinivas Kandagatla qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 1800768270caSSrinivas Kandagatla qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 1801768270caSSrinivas Kandagatla qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 1802768270caSSrinivas Kandagatla qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 1803768270caSSrinivas Kandagatla 1804768270caSSrinivas Kandagatla #sound-dai-cells = <1>; 1805768270caSSrinivas Kandagatla #address-cells = <2>; 1806768270caSSrinivas Kandagatla #size-cells = <0>; 1807768270caSSrinivas Kandagatla }; 1808768270caSSrinivas Kandagatla 1809793bbd2dSSrinivas Kandagatla audiocc: clock-controller@3300000 { 1810793bbd2dSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-audiocc"; 1811793bbd2dSSrinivas Kandagatla reg = <0 0x03300000 0 0x30000>; 1812793bbd2dSSrinivas Kandagatla #clock-cells = <1>; 1813793bbd2dSSrinivas Kandagatla clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1814793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1815793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1816793bbd2dSSrinivas Kandagatla clock-names = "core", "audio", "bus"; 1817793bbd2dSSrinivas Kandagatla }; 1818793bbd2dSSrinivas Kandagatla 1819768270caSSrinivas Kandagatla vamacro: codec@3370000 { 1820768270caSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-va-macro"; 1821768270caSSrinivas Kandagatla reg = <0 0x03370000 0 0x1000>; 1822768270caSSrinivas Kandagatla clocks = <&aoncc 0>, 1823768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1824768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1825768270caSSrinivas Kandagatla 1826768270caSSrinivas Kandagatla clock-names = "mclk", "macro", "dcodec"; 1827768270caSSrinivas Kandagatla 1828768270caSSrinivas Kandagatla #clock-cells = <0>; 1829768270caSSrinivas Kandagatla clock-frequency = <9600000>; 1830768270caSSrinivas Kandagatla clock-output-names = "fsgen"; 1831768270caSSrinivas Kandagatla #sound-dai-cells = <1>; 1832768270caSSrinivas Kandagatla }; 1833768270caSSrinivas Kandagatla 1834*24f52ef0SSrinivas Kandagatla rxmacro: rxmacro@3200000 { 1835*24f52ef0SSrinivas Kandagatla pinctrl-names = "default"; 1836*24f52ef0SSrinivas Kandagatla pinctrl-0 = <&rx_swr_active>; 1837*24f52ef0SSrinivas Kandagatla compatible = "qcom,sm8250-lpass-rx-macro"; 1838*24f52ef0SSrinivas Kandagatla reg = <0 0x3200000 0 0x1000>; 1839*24f52ef0SSrinivas Kandagatla 1840*24f52ef0SSrinivas Kandagatla clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1841*24f52ef0SSrinivas Kandagatla <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1842*24f52ef0SSrinivas Kandagatla <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1843*24f52ef0SSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1844*24f52ef0SSrinivas Kandagatla <&vamacro>; 1845*24f52ef0SSrinivas Kandagatla 1846*24f52ef0SSrinivas Kandagatla clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 1847*24f52ef0SSrinivas Kandagatla 1848*24f52ef0SSrinivas Kandagatla #clock-cells = <0>; 1849*24f52ef0SSrinivas Kandagatla clock-frequency = <9600000>; 1850*24f52ef0SSrinivas Kandagatla clock-output-names = "mclk"; 1851*24f52ef0SSrinivas Kandagatla #sound-dai-cells = <1>; 1852*24f52ef0SSrinivas Kandagatla }; 1853*24f52ef0SSrinivas Kandagatla 1854*24f52ef0SSrinivas Kandagatla swr1: soundwire-controller@3210000 { 1855*24f52ef0SSrinivas Kandagatla reg = <0 0x3210000 0 0x2000>; 1856*24f52ef0SSrinivas Kandagatla compatible = "qcom,soundwire-v1.5.1"; 1857*24f52ef0SSrinivas Kandagatla interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1858*24f52ef0SSrinivas Kandagatla clocks = <&rxmacro>; 1859*24f52ef0SSrinivas Kandagatla clock-names = "iface"; 1860*24f52ef0SSrinivas Kandagatla label = "RX"; 1861*24f52ef0SSrinivas Kandagatla qcom,din-ports = <0>; 1862*24f52ef0SSrinivas Kandagatla qcom,dout-ports = <5>; 1863*24f52ef0SSrinivas Kandagatla 1864*24f52ef0SSrinivas Kandagatla qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>; 1865*24f52ef0SSrinivas Kandagatla qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 1866*24f52ef0SSrinivas Kandagatla qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 1867*24f52ef0SSrinivas Kandagatla qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>; 1868*24f52ef0SSrinivas Kandagatla qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>; 1869*24f52ef0SSrinivas Kandagatla qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>; 1870*24f52ef0SSrinivas Kandagatla qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>; 1871*24f52ef0SSrinivas Kandagatla qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 1872*24f52ef0SSrinivas Kandagatla qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>; 1873*24f52ef0SSrinivas Kandagatla 1874*24f52ef0SSrinivas Kandagatla #sound-dai-cells = <1>; 1875*24f52ef0SSrinivas Kandagatla #address-cells = <2>; 1876*24f52ef0SSrinivas Kandagatla #size-cells = <0>; 1877*24f52ef0SSrinivas Kandagatla }; 1878*24f52ef0SSrinivas Kandagatla 1879*24f52ef0SSrinivas Kandagatla txmacro: txmacro@3220000 { 1880*24f52ef0SSrinivas Kandagatla pinctrl-names = "default"; 1881*24f52ef0SSrinivas Kandagatla pinctrl-0 = <&tx_swr_active>; 1882*24f52ef0SSrinivas Kandagatla compatible = "qcom,sm8250-lpass-tx-macro"; 1883*24f52ef0SSrinivas Kandagatla reg = <0 0x3220000 0 0x1000>; 1884*24f52ef0SSrinivas Kandagatla 1885*24f52ef0SSrinivas Kandagatla clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1886*24f52ef0SSrinivas Kandagatla <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1887*24f52ef0SSrinivas Kandagatla <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1888*24f52ef0SSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1889*24f52ef0SSrinivas Kandagatla <&vamacro>; 1890*24f52ef0SSrinivas Kandagatla 1891*24f52ef0SSrinivas Kandagatla clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 1892*24f52ef0SSrinivas Kandagatla 1893*24f52ef0SSrinivas Kandagatla #clock-cells = <0>; 1894*24f52ef0SSrinivas Kandagatla clock-frequency = <9600000>; 1895*24f52ef0SSrinivas Kandagatla clock-output-names = "mclk"; 1896*24f52ef0SSrinivas Kandagatla #address-cells = <2>; 1897*24f52ef0SSrinivas Kandagatla #size-cells = <2>; 1898*24f52ef0SSrinivas Kandagatla #sound-dai-cells = <1>; 1899*24f52ef0SSrinivas Kandagatla }; 1900*24f52ef0SSrinivas Kandagatla 1901*24f52ef0SSrinivas Kandagatla /* tx macro */ 1902*24f52ef0SSrinivas Kandagatla swr2: soundwire-controller@3230000 { 1903*24f52ef0SSrinivas Kandagatla reg = <0 0x3230000 0 0x2000>; 1904*24f52ef0SSrinivas Kandagatla compatible = "qcom,soundwire-v1.5.1"; 1905*24f52ef0SSrinivas Kandagatla interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 1906*24f52ef0SSrinivas Kandagatla interrupt-names = "core"; 1907*24f52ef0SSrinivas Kandagatla 1908*24f52ef0SSrinivas Kandagatla clocks = <&txmacro>; 1909*24f52ef0SSrinivas Kandagatla clock-names = "iface"; 1910*24f52ef0SSrinivas Kandagatla label = "TX"; 1911*24f52ef0SSrinivas Kandagatla 1912*24f52ef0SSrinivas Kandagatla qcom,din-ports = <5>; 1913*24f52ef0SSrinivas Kandagatla qcom,dout-ports = <0>; 1914*24f52ef0SSrinivas Kandagatla qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>; 1915*24f52ef0SSrinivas Kandagatla qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>; 1916*24f52ef0SSrinivas Kandagatla qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>; 1917*24f52ef0SSrinivas Kandagatla qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 1918*24f52ef0SSrinivas Kandagatla qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 1919*24f52ef0SSrinivas Kandagatla qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 1920*24f52ef0SSrinivas Kandagatla qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 1921*24f52ef0SSrinivas Kandagatla qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 1922*24f52ef0SSrinivas Kandagatla qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>; 1923*24f52ef0SSrinivas Kandagatla qcom,port-offset = <1>; 1924*24f52ef0SSrinivas Kandagatla #sound-dai-cells = <1>; 1925*24f52ef0SSrinivas Kandagatla #address-cells = <2>; 1926*24f52ef0SSrinivas Kandagatla #size-cells = <0>; 1927*24f52ef0SSrinivas Kandagatla }; 1928*24f52ef0SSrinivas Kandagatla 1929793bbd2dSSrinivas Kandagatla aoncc: clock-controller@3380000 { 1930793bbd2dSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-aoncc"; 1931793bbd2dSSrinivas Kandagatla reg = <0 0x03380000 0 0x40000>; 1932793bbd2dSSrinivas Kandagatla #clock-cells = <1>; 1933793bbd2dSSrinivas Kandagatla clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1934793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1935793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1936793bbd2dSSrinivas Kandagatla clock-names = "core", "audio", "bus"; 1937793bbd2dSSrinivas Kandagatla }; 1938793bbd2dSSrinivas Kandagatla 19393160c1b8SSrinivas Kandagatla lpass_tlmm: pinctrl@33c0000{ 19403160c1b8SSrinivas Kandagatla compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 19413160c1b8SSrinivas Kandagatla reg = <0 0x033c0000 0x0 0x20000>, 19423160c1b8SSrinivas Kandagatla <0 0x03550000 0x0 0x10000>; 19433160c1b8SSrinivas Kandagatla gpio-controller; 19443160c1b8SSrinivas Kandagatla #gpio-cells = <2>; 19453160c1b8SSrinivas Kandagatla gpio-ranges = <&lpass_tlmm 0 0 14>; 19463160c1b8SSrinivas Kandagatla 19473160c1b8SSrinivas Kandagatla clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 19483160c1b8SSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 19493160c1b8SSrinivas Kandagatla clock-names = "core", "audio"; 19503160c1b8SSrinivas Kandagatla 19513160c1b8SSrinivas Kandagatla wsa_swr_active: wsa-swr-active-pins { 19523160c1b8SSrinivas Kandagatla clk { 19533160c1b8SSrinivas Kandagatla pins = "gpio10"; 19543160c1b8SSrinivas Kandagatla function = "wsa_swr_clk"; 19553160c1b8SSrinivas Kandagatla drive-strength = <2>; 19563160c1b8SSrinivas Kandagatla slew-rate = <1>; 19573160c1b8SSrinivas Kandagatla bias-disable; 19583160c1b8SSrinivas Kandagatla }; 19593160c1b8SSrinivas Kandagatla 19603160c1b8SSrinivas Kandagatla data { 19613160c1b8SSrinivas Kandagatla pins = "gpio11"; 19623160c1b8SSrinivas Kandagatla function = "wsa_swr_data"; 19633160c1b8SSrinivas Kandagatla drive-strength = <2>; 19643160c1b8SSrinivas Kandagatla slew-rate = <1>; 19653160c1b8SSrinivas Kandagatla bias-bus-hold; 19663160c1b8SSrinivas Kandagatla 19673160c1b8SSrinivas Kandagatla }; 19683160c1b8SSrinivas Kandagatla }; 19693160c1b8SSrinivas Kandagatla 19703160c1b8SSrinivas Kandagatla wsa_swr_sleep: wsa-swr-sleep-pins { 19713160c1b8SSrinivas Kandagatla clk { 19723160c1b8SSrinivas Kandagatla pins = "gpio10"; 19733160c1b8SSrinivas Kandagatla function = "wsa_swr_clk"; 19743160c1b8SSrinivas Kandagatla drive-strength = <2>; 19753160c1b8SSrinivas Kandagatla input-enable; 19763160c1b8SSrinivas Kandagatla bias-pull-down; 19773160c1b8SSrinivas Kandagatla }; 19783160c1b8SSrinivas Kandagatla 19793160c1b8SSrinivas Kandagatla data { 19803160c1b8SSrinivas Kandagatla pins = "gpio11"; 19813160c1b8SSrinivas Kandagatla function = "wsa_swr_data"; 19823160c1b8SSrinivas Kandagatla drive-strength = <2>; 19833160c1b8SSrinivas Kandagatla input-enable; 19843160c1b8SSrinivas Kandagatla bias-pull-down; 19853160c1b8SSrinivas Kandagatla 19863160c1b8SSrinivas Kandagatla }; 19873160c1b8SSrinivas Kandagatla }; 19883160c1b8SSrinivas Kandagatla 19893160c1b8SSrinivas Kandagatla dmic01_active: dmic01-active-pins { 19903160c1b8SSrinivas Kandagatla clk { 19913160c1b8SSrinivas Kandagatla pins = "gpio6"; 19923160c1b8SSrinivas Kandagatla function = "dmic1_clk"; 19933160c1b8SSrinivas Kandagatla drive-strength = <8>; 19943160c1b8SSrinivas Kandagatla output-high; 19953160c1b8SSrinivas Kandagatla }; 19963160c1b8SSrinivas Kandagatla data { 19973160c1b8SSrinivas Kandagatla pins = "gpio7"; 19983160c1b8SSrinivas Kandagatla function = "dmic1_data"; 19993160c1b8SSrinivas Kandagatla drive-strength = <8>; 20003160c1b8SSrinivas Kandagatla input-enable; 20013160c1b8SSrinivas Kandagatla }; 20023160c1b8SSrinivas Kandagatla }; 20033160c1b8SSrinivas Kandagatla 20043160c1b8SSrinivas Kandagatla dmic01_sleep: dmic01-sleep-pins { 20053160c1b8SSrinivas Kandagatla clk { 20063160c1b8SSrinivas Kandagatla pins = "gpio6"; 20073160c1b8SSrinivas Kandagatla function = "dmic1_clk"; 20083160c1b8SSrinivas Kandagatla drive-strength = <2>; 20093160c1b8SSrinivas Kandagatla bias-disable; 20103160c1b8SSrinivas Kandagatla output-low; 20113160c1b8SSrinivas Kandagatla }; 20123160c1b8SSrinivas Kandagatla 20133160c1b8SSrinivas Kandagatla data { 20143160c1b8SSrinivas Kandagatla pins = "gpio7"; 20153160c1b8SSrinivas Kandagatla function = "dmic1_data"; 20163160c1b8SSrinivas Kandagatla drive-strength = <2>; 20173160c1b8SSrinivas Kandagatla pull-down; 20183160c1b8SSrinivas Kandagatla input-enable; 20193160c1b8SSrinivas Kandagatla }; 20203160c1b8SSrinivas Kandagatla }; 2021*24f52ef0SSrinivas Kandagatla 2022*24f52ef0SSrinivas Kandagatla rx_swr_active: rx_swr-active-pins { 2023*24f52ef0SSrinivas Kandagatla clk { 2024*24f52ef0SSrinivas Kandagatla pins = "gpio3"; 2025*24f52ef0SSrinivas Kandagatla function = "swr_rx_clk"; 2026*24f52ef0SSrinivas Kandagatla drive-strength = <2>; 2027*24f52ef0SSrinivas Kandagatla slew-rate = <1>; 2028*24f52ef0SSrinivas Kandagatla bias-disable; 2029*24f52ef0SSrinivas Kandagatla }; 2030*24f52ef0SSrinivas Kandagatla 2031*24f52ef0SSrinivas Kandagatla data { 2032*24f52ef0SSrinivas Kandagatla pins = "gpio4", "gpio5"; 2033*24f52ef0SSrinivas Kandagatla function = "swr_rx_data"; 2034*24f52ef0SSrinivas Kandagatla drive-strength = <2>; 2035*24f52ef0SSrinivas Kandagatla slew-rate = <1>; 2036*24f52ef0SSrinivas Kandagatla bias-bus-hold; 2037*24f52ef0SSrinivas Kandagatla }; 2038*24f52ef0SSrinivas Kandagatla }; 2039*24f52ef0SSrinivas Kandagatla 2040*24f52ef0SSrinivas Kandagatla tx_swr_active: tx_swr-active-pins { 2041*24f52ef0SSrinivas Kandagatla clk { 2042*24f52ef0SSrinivas Kandagatla pins = "gpio0"; 2043*24f52ef0SSrinivas Kandagatla function = "swr_tx_clk"; 2044*24f52ef0SSrinivas Kandagatla drive-strength = <2>; 2045*24f52ef0SSrinivas Kandagatla slew-rate = <1>; 2046*24f52ef0SSrinivas Kandagatla bias-disable; 2047*24f52ef0SSrinivas Kandagatla }; 2048*24f52ef0SSrinivas Kandagatla 2049*24f52ef0SSrinivas Kandagatla data { 2050*24f52ef0SSrinivas Kandagatla pins = "gpio1", "gpio2"; 2051*24f52ef0SSrinivas Kandagatla function = "swr_tx_data"; 2052*24f52ef0SSrinivas Kandagatla drive-strength = <2>; 2053*24f52ef0SSrinivas Kandagatla slew-rate = <1>; 2054*24f52ef0SSrinivas Kandagatla bias-bus-hold; 2055*24f52ef0SSrinivas Kandagatla }; 2056*24f52ef0SSrinivas Kandagatla }; 2057*24f52ef0SSrinivas Kandagatla 2058*24f52ef0SSrinivas Kandagatla tx_swr_sleep: tx_swr-sleep-pins { 2059*24f52ef0SSrinivas Kandagatla clk { 2060*24f52ef0SSrinivas Kandagatla pins = "gpio0"; 2061*24f52ef0SSrinivas Kandagatla function = "swr_tx_clk"; 2062*24f52ef0SSrinivas Kandagatla drive-strength = <2>; 2063*24f52ef0SSrinivas Kandagatla input-enable; 2064*24f52ef0SSrinivas Kandagatla bias-pull-down; 2065*24f52ef0SSrinivas Kandagatla }; 2066*24f52ef0SSrinivas Kandagatla 2067*24f52ef0SSrinivas Kandagatla data1 { 2068*24f52ef0SSrinivas Kandagatla pins = "gpio1"; 2069*24f52ef0SSrinivas Kandagatla function = "swr_tx_data"; 2070*24f52ef0SSrinivas Kandagatla drive-strength = <2>; 2071*24f52ef0SSrinivas Kandagatla input-enable; 2072*24f52ef0SSrinivas Kandagatla bias-bus-hold; 2073*24f52ef0SSrinivas Kandagatla }; 2074*24f52ef0SSrinivas Kandagatla 2075*24f52ef0SSrinivas Kandagatla data2 { 2076*24f52ef0SSrinivas Kandagatla pins = "gpio2"; 2077*24f52ef0SSrinivas Kandagatla function = "swr_tx_data"; 2078*24f52ef0SSrinivas Kandagatla drive-strength = <2>; 2079*24f52ef0SSrinivas Kandagatla input-enable; 2080*24f52ef0SSrinivas Kandagatla bias-pull-down; 2081*24f52ef0SSrinivas Kandagatla }; 2082*24f52ef0SSrinivas Kandagatla }; 20833160c1b8SSrinivas Kandagatla }; 20843160c1b8SSrinivas Kandagatla 208504a3605bSJonathan Marek gpu: gpu@3d00000 { 208604a3605bSJonathan Marek compatible = "qcom,adreno-650.2", 20877c1dffd4SDmitry Baryshkov "qcom,adreno"; 208804a3605bSJonathan Marek #stream-id-cells = <16>; 208904a3605bSJonathan Marek 209004a3605bSJonathan Marek reg = <0 0x03d00000 0 0x40000>; 209104a3605bSJonathan Marek reg-names = "kgsl_3d0_reg_memory"; 209204a3605bSJonathan Marek 209304a3605bSJonathan Marek interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 209404a3605bSJonathan Marek 209504a3605bSJonathan Marek iommus = <&adreno_smmu 0 0x401>; 209604a3605bSJonathan Marek 209704a3605bSJonathan Marek operating-points-v2 = <&gpu_opp_table>; 209804a3605bSJonathan Marek 209904a3605bSJonathan Marek qcom,gmu = <&gmu>; 210004a3605bSJonathan Marek 2101ece28cb5SKonrad Dybcio status = "disabled"; 2102ece28cb5SKonrad Dybcio 210304a3605bSJonathan Marek zap-shader { 210404a3605bSJonathan Marek memory-region = <&gpu_mem>; 210504a3605bSJonathan Marek }; 210604a3605bSJonathan Marek 210704a3605bSJonathan Marek /* note: downstream checks gpu binning for 670 Mhz */ 210804a3605bSJonathan Marek gpu_opp_table: opp-table { 210904a3605bSJonathan Marek compatible = "operating-points-v2"; 211004a3605bSJonathan Marek 211104a3605bSJonathan Marek opp-670000000 { 211204a3605bSJonathan Marek opp-hz = /bits/ 64 <670000000>; 211304a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 211404a3605bSJonathan Marek }; 211504a3605bSJonathan Marek 211604a3605bSJonathan Marek opp-587000000 { 211704a3605bSJonathan Marek opp-hz = /bits/ 64 <587000000>; 211804a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 211904a3605bSJonathan Marek }; 212004a3605bSJonathan Marek 212104a3605bSJonathan Marek opp-525000000 { 212204a3605bSJonathan Marek opp-hz = /bits/ 64 <525000000>; 212304a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 212404a3605bSJonathan Marek }; 212504a3605bSJonathan Marek 212604a3605bSJonathan Marek opp-490000000 { 212704a3605bSJonathan Marek opp-hz = /bits/ 64 <490000000>; 212804a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 212904a3605bSJonathan Marek }; 213004a3605bSJonathan Marek 213104a3605bSJonathan Marek opp-441600000 { 213204a3605bSJonathan Marek opp-hz = /bits/ 64 <441600000>; 213304a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 213404a3605bSJonathan Marek }; 213504a3605bSJonathan Marek 213604a3605bSJonathan Marek opp-400000000 { 213704a3605bSJonathan Marek opp-hz = /bits/ 64 <400000000>; 213804a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 213904a3605bSJonathan Marek }; 214004a3605bSJonathan Marek 214104a3605bSJonathan Marek opp-305000000 { 214204a3605bSJonathan Marek opp-hz = /bits/ 64 <305000000>; 214304a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 214404a3605bSJonathan Marek }; 214504a3605bSJonathan Marek }; 214604a3605bSJonathan Marek }; 214704a3605bSJonathan Marek 214804a3605bSJonathan Marek gmu: gmu@3d6a000 { 214904a3605bSJonathan Marek compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 215004a3605bSJonathan Marek 215104a3605bSJonathan Marek reg = <0 0x03d6a000 0 0x30000>, 215204a3605bSJonathan Marek <0 0x3de0000 0 0x10000>, 215304a3605bSJonathan Marek <0 0xb290000 0 0x10000>, 215404a3605bSJonathan Marek <0 0xb490000 0 0x10000>; 215504a3605bSJonathan Marek reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 215604a3605bSJonathan Marek 215704a3605bSJonathan Marek interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 215804a3605bSJonathan Marek <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 215904a3605bSJonathan Marek interrupt-names = "hfi", "gmu"; 216004a3605bSJonathan Marek 21610e6aa9dbSJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 21620e6aa9dbSJonathan Marek <&gpucc GPU_CC_CX_GMU_CLK>, 21630e6aa9dbSJonathan Marek <&gpucc GPU_CC_CXO_CLK>, 216404a3605bSJonathan Marek <&gcc GCC_DDRSS_GPU_AXI_CLK>, 216504a3605bSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 216604a3605bSJonathan Marek clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 216704a3605bSJonathan Marek 21680e6aa9dbSJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>, 21690e6aa9dbSJonathan Marek <&gpucc GPU_GX_GDSC>; 217004a3605bSJonathan Marek power-domain-names = "cx", "gx"; 217104a3605bSJonathan Marek 217204a3605bSJonathan Marek iommus = <&adreno_smmu 5 0x400>; 217304a3605bSJonathan Marek 217404a3605bSJonathan Marek operating-points-v2 = <&gmu_opp_table>; 217504a3605bSJonathan Marek 2176ece28cb5SKonrad Dybcio status = "disabled"; 2177ece28cb5SKonrad Dybcio 217804a3605bSJonathan Marek gmu_opp_table: opp-table { 217904a3605bSJonathan Marek compatible = "operating-points-v2"; 218004a3605bSJonathan Marek 218104a3605bSJonathan Marek opp-200000000 { 218204a3605bSJonathan Marek opp-hz = /bits/ 64 <200000000>; 218304a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 218404a3605bSJonathan Marek }; 218504a3605bSJonathan Marek }; 218604a3605bSJonathan Marek }; 218704a3605bSJonathan Marek 218804a3605bSJonathan Marek gpucc: clock-controller@3d90000 { 218904a3605bSJonathan Marek compatible = "qcom,sm8250-gpucc"; 219004a3605bSJonathan Marek reg = <0 0x03d90000 0 0x9000>; 219104a3605bSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>, 219204a3605bSJonathan Marek <&gcc GCC_GPU_GPLL0_CLK_SRC>, 219304a3605bSJonathan Marek <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 219404a3605bSJonathan Marek clock-names = "bi_tcxo", 219504a3605bSJonathan Marek "gcc_gpu_gpll0_clk_src", 219604a3605bSJonathan Marek "gcc_gpu_gpll0_div_clk_src"; 219704a3605bSJonathan Marek #clock-cells = <1>; 219804a3605bSJonathan Marek #reset-cells = <1>; 219904a3605bSJonathan Marek #power-domain-cells = <1>; 220004a3605bSJonathan Marek }; 220104a3605bSJonathan Marek 220204a3605bSJonathan Marek adreno_smmu: iommu@3da0000 { 220304a3605bSJonathan Marek compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 220404a3605bSJonathan Marek reg = <0 0x03da0000 0 0x10000>; 220504a3605bSJonathan Marek #iommu-cells = <2>; 220604a3605bSJonathan Marek #global-interrupts = <2>; 220704a3605bSJonathan Marek interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 220804a3605bSJonathan Marek <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 220904a3605bSJonathan Marek <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 221004a3605bSJonathan Marek <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 221104a3605bSJonathan Marek <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 221204a3605bSJonathan Marek <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 221304a3605bSJonathan Marek <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 221404a3605bSJonathan Marek <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 221504a3605bSJonathan Marek <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 221604a3605bSJonathan Marek <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 22170e6aa9dbSJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 221804a3605bSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 221904a3605bSJonathan Marek <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 222004a3605bSJonathan Marek clock-names = "ahb", "bus", "iface"; 222104a3605bSJonathan Marek 22220e6aa9dbSJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>; 222304a3605bSJonathan Marek }; 222404a3605bSJonathan Marek 222523a89037SBjorn Andersson slpi: remoteproc@5c00000 { 222623a89037SBjorn Andersson compatible = "qcom,sm8250-slpi-pas"; 222723a89037SBjorn Andersson reg = <0 0x05c00000 0 0x4000>; 222823a89037SBjorn Andersson 222923a89037SBjorn Andersson interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 223023a89037SBjorn Andersson <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 223123a89037SBjorn Andersson <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 223223a89037SBjorn Andersson <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 223323a89037SBjorn Andersson <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 223423a89037SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 223523a89037SBjorn Andersson "handover", "stop-ack"; 223623a89037SBjorn Andersson 223723a89037SBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>; 223823a89037SBjorn Andersson clock-names = "xo"; 223923a89037SBjorn Andersson 2240b74ee2d7SSibi Sankar power-domains = <&rpmhpd SM8250_LCX>, 224123a89037SBjorn Andersson <&rpmhpd SM8250_LMX>; 2242b74ee2d7SSibi Sankar power-domain-names = "lcx", "lmx"; 224323a89037SBjorn Andersson 224423a89037SBjorn Andersson memory-region = <&slpi_mem>; 224523a89037SBjorn Andersson 2246b74ee2d7SSibi Sankar qcom,qmp = <&aoss_qmp>; 2247b74ee2d7SSibi Sankar 224823a89037SBjorn Andersson qcom,smem-states = <&smp2p_slpi_out 0>; 224923a89037SBjorn Andersson qcom,smem-state-names = "stop"; 225023a89037SBjorn Andersson 225123a89037SBjorn Andersson status = "disabled"; 225223a89037SBjorn Andersson 225323a89037SBjorn Andersson glink-edge { 225423a89037SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 225523a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 225623a89037SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 225723a89037SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_SLPI 225823a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 225923a89037SBjorn Andersson 226025695808SJonathan Marek label = "slpi"; 226123a89037SBjorn Andersson qcom,remote-pid = <3>; 226225695808SJonathan Marek 226325695808SJonathan Marek fastrpc { 226425695808SJonathan Marek compatible = "qcom,fastrpc"; 226525695808SJonathan Marek qcom,glink-channels = "fastrpcglink-apps-dsp"; 226625695808SJonathan Marek label = "sdsp"; 226725695808SJonathan Marek #address-cells = <1>; 226825695808SJonathan Marek #size-cells = <0>; 226925695808SJonathan Marek 227025695808SJonathan Marek compute-cb@1 { 227125695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 227225695808SJonathan Marek reg = <1>; 227325695808SJonathan Marek iommus = <&apps_smmu 0x0541 0x0>; 227425695808SJonathan Marek }; 227525695808SJonathan Marek 227625695808SJonathan Marek compute-cb@2 { 227725695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 227825695808SJonathan Marek reg = <2>; 227925695808SJonathan Marek iommus = <&apps_smmu 0x0542 0x0>; 228025695808SJonathan Marek }; 228125695808SJonathan Marek 228225695808SJonathan Marek compute-cb@3 { 228325695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 228425695808SJonathan Marek reg = <3>; 228525695808SJonathan Marek iommus = <&apps_smmu 0x0543 0x0>; 228625695808SJonathan Marek /* note: shared-cb = <4> in downstream */ 228725695808SJonathan Marek }; 228825695808SJonathan Marek }; 228923a89037SBjorn Andersson }; 229023a89037SBjorn Andersson }; 229123a89037SBjorn Andersson 229223a89037SBjorn Andersson cdsp: remoteproc@8300000 { 229323a89037SBjorn Andersson compatible = "qcom,sm8250-cdsp-pas"; 229423a89037SBjorn Andersson reg = <0 0x08300000 0 0x10000>; 229523a89037SBjorn Andersson 229623a89037SBjorn Andersson interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 229723a89037SBjorn Andersson <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 229823a89037SBjorn Andersson <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 229923a89037SBjorn Andersson <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 230023a89037SBjorn Andersson <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 230123a89037SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 230223a89037SBjorn Andersson "handover", "stop-ack"; 230323a89037SBjorn Andersson 230423a89037SBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>; 230523a89037SBjorn Andersson clock-names = "xo"; 230623a89037SBjorn Andersson 2307b74ee2d7SSibi Sankar power-domains = <&rpmhpd SM8250_CX>; 230823a89037SBjorn Andersson 230923a89037SBjorn Andersson memory-region = <&cdsp_mem>; 231023a89037SBjorn Andersson 2311b74ee2d7SSibi Sankar qcom,qmp = <&aoss_qmp>; 2312b74ee2d7SSibi Sankar 231323a89037SBjorn Andersson qcom,smem-states = <&smp2p_cdsp_out 0>; 231423a89037SBjorn Andersson qcom,smem-state-names = "stop"; 231523a89037SBjorn Andersson 231623a89037SBjorn Andersson status = "disabled"; 231723a89037SBjorn Andersson 231823a89037SBjorn Andersson glink-edge { 231923a89037SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 232023a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 232123a89037SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 232223a89037SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_CDSP 232323a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 232423a89037SBjorn Andersson 232525695808SJonathan Marek label = "cdsp"; 232623a89037SBjorn Andersson qcom,remote-pid = <5>; 232725695808SJonathan Marek 232825695808SJonathan Marek fastrpc { 232925695808SJonathan Marek compatible = "qcom,fastrpc"; 233025695808SJonathan Marek qcom,glink-channels = "fastrpcglink-apps-dsp"; 233125695808SJonathan Marek label = "cdsp"; 233225695808SJonathan Marek #address-cells = <1>; 233325695808SJonathan Marek #size-cells = <0>; 233425695808SJonathan Marek 233525695808SJonathan Marek compute-cb@1 { 233625695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 233725695808SJonathan Marek reg = <1>; 233825695808SJonathan Marek iommus = <&apps_smmu 0x1001 0x0460>; 233925695808SJonathan Marek }; 234025695808SJonathan Marek 234125695808SJonathan Marek compute-cb@2 { 234225695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 234325695808SJonathan Marek reg = <2>; 234425695808SJonathan Marek iommus = <&apps_smmu 0x1002 0x0460>; 234525695808SJonathan Marek }; 234625695808SJonathan Marek 234725695808SJonathan Marek compute-cb@3 { 234825695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 234925695808SJonathan Marek reg = <3>; 235025695808SJonathan Marek iommus = <&apps_smmu 0x1003 0x0460>; 235125695808SJonathan Marek }; 235225695808SJonathan Marek 235325695808SJonathan Marek compute-cb@4 { 235425695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 235525695808SJonathan Marek reg = <4>; 235625695808SJonathan Marek iommus = <&apps_smmu 0x1004 0x0460>; 235725695808SJonathan Marek }; 235825695808SJonathan Marek 235925695808SJonathan Marek compute-cb@5 { 236025695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 236125695808SJonathan Marek reg = <5>; 236225695808SJonathan Marek iommus = <&apps_smmu 0x1005 0x0460>; 236325695808SJonathan Marek }; 236425695808SJonathan Marek 236525695808SJonathan Marek compute-cb@6 { 236625695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 236725695808SJonathan Marek reg = <6>; 236825695808SJonathan Marek iommus = <&apps_smmu 0x1006 0x0460>; 236925695808SJonathan Marek }; 237025695808SJonathan Marek 237125695808SJonathan Marek compute-cb@7 { 237225695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 237325695808SJonathan Marek reg = <7>; 237425695808SJonathan Marek iommus = <&apps_smmu 0x1007 0x0460>; 237525695808SJonathan Marek }; 237625695808SJonathan Marek 237725695808SJonathan Marek compute-cb@8 { 237825695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 237925695808SJonathan Marek reg = <8>; 238025695808SJonathan Marek iommus = <&apps_smmu 0x1008 0x0460>; 238125695808SJonathan Marek }; 238225695808SJonathan Marek 238325695808SJonathan Marek /* note: secure cb9 in downstream */ 238425695808SJonathan Marek }; 238523a89037SBjorn Andersson }; 238623a89037SBjorn Andersson }; 238723a89037SBjorn Andersson 2388590a135eSSrinivas Kandagatla sound: sound { 2389590a135eSSrinivas Kandagatla }; 2390590a135eSSrinivas Kandagatla 239146a6f297SJonathan Marek usb_1_hsphy: phy@88e3000 { 239246a6f297SJonathan Marek compatible = "qcom,sm8250-usb-hs-phy", 239346a6f297SJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 239446a6f297SJonathan Marek reg = <0 0x088e3000 0 0x400>; 239546a6f297SJonathan Marek status = "disabled"; 239646a6f297SJonathan Marek #phy-cells = <0>; 239746a6f297SJonathan Marek 239846a6f297SJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 239946a6f297SJonathan Marek clock-names = "ref"; 240046a6f297SJonathan Marek 240146a6f297SJonathan Marek resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 240246a6f297SJonathan Marek }; 240346a6f297SJonathan Marek 240446a6f297SJonathan Marek usb_2_hsphy: phy@88e4000 { 240546a6f297SJonathan Marek compatible = "qcom,sm8250-usb-hs-phy", 240646a6f297SJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 240746a6f297SJonathan Marek reg = <0 0x088e4000 0 0x400>; 240846a6f297SJonathan Marek status = "disabled"; 240946a6f297SJonathan Marek #phy-cells = <0>; 241046a6f297SJonathan Marek 241146a6f297SJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 241246a6f297SJonathan Marek clock-names = "ref"; 241346a6f297SJonathan Marek 241446a6f297SJonathan Marek resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 241546a6f297SJonathan Marek }; 241646a6f297SJonathan Marek 241746a6f297SJonathan Marek usb_1_qmpphy: phy@88e9000 { 24185aa0d1beSDmitry Baryshkov compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 241946a6f297SJonathan Marek reg = <0 0x088e9000 0 0x200>, 24205aa0d1beSDmitry Baryshkov <0 0x088e8000 0 0x40>, 24215aa0d1beSDmitry Baryshkov <0 0x088ea000 0 0x200>; 242246a6f297SJonathan Marek status = "disabled"; 242346a6f297SJonathan Marek #address-cells = <2>; 242446a6f297SJonathan Marek #size-cells = <2>; 242546a6f297SJonathan Marek ranges; 242646a6f297SJonathan Marek 242746a6f297SJonathan Marek clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 242846a6f297SJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 242946a6f297SJonathan Marek <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 243046a6f297SJonathan Marek clock-names = "aux", "ref_clk_src", "com_aux"; 243146a6f297SJonathan Marek 243246a6f297SJonathan Marek resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 243346a6f297SJonathan Marek <&gcc GCC_USB3_PHY_PRIM_BCR>; 243446a6f297SJonathan Marek reset-names = "phy", "common"; 243546a6f297SJonathan Marek 24365aa0d1beSDmitry Baryshkov usb_1_ssphy: usb3-phy@88e9200 { 243746a6f297SJonathan Marek reg = <0 0x088e9200 0 0x200>, 243846a6f297SJonathan Marek <0 0x088e9400 0 0x200>, 243946a6f297SJonathan Marek <0 0x088e9c00 0 0x400>, 244046a6f297SJonathan Marek <0 0x088e9600 0 0x200>, 244146a6f297SJonathan Marek <0 0x088e9800 0 0x200>, 244246a6f297SJonathan Marek <0 0x088e9a00 0 0x100>; 24437178d4ccSJonathan Marek #clock-cells = <0>; 244446a6f297SJonathan Marek #phy-cells = <0>; 244546a6f297SJonathan Marek clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 244646a6f297SJonathan Marek clock-names = "pipe0"; 244746a6f297SJonathan Marek clock-output-names = "usb3_phy_pipe_clk_src"; 244846a6f297SJonathan Marek }; 24495aa0d1beSDmitry Baryshkov 24505aa0d1beSDmitry Baryshkov dp_phy: dp-phy@88ea200 { 24515aa0d1beSDmitry Baryshkov reg = <0 0x088ea200 0 0x200>, 24525aa0d1beSDmitry Baryshkov <0 0x088ea400 0 0x200>, 24535aa0d1beSDmitry Baryshkov <0 0x088eac00 0 0x400>, 24545aa0d1beSDmitry Baryshkov <0 0x088ea600 0 0x200>, 24555aa0d1beSDmitry Baryshkov <0 0x088ea800 0 0x200>, 24565aa0d1beSDmitry Baryshkov <0 0x088eaa00 0 0x100>; 24575aa0d1beSDmitry Baryshkov #phy-cells = <0>; 24585aa0d1beSDmitry Baryshkov #clock-cells = <1>; 24595aa0d1beSDmitry Baryshkov clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 24605aa0d1beSDmitry Baryshkov clock-names = "pipe0"; 24615aa0d1beSDmitry Baryshkov clock-output-names = "usb3_phy_pipe_clk_src"; 24625aa0d1beSDmitry Baryshkov }; 246346a6f297SJonathan Marek }; 246446a6f297SJonathan Marek 246546a6f297SJonathan Marek usb_2_qmpphy: phy@88eb000 { 246646a6f297SJonathan Marek compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 246746a6f297SJonathan Marek reg = <0 0x088eb000 0 0x200>; 246846a6f297SJonathan Marek status = "disabled"; 246946a6f297SJonathan Marek #address-cells = <2>; 247046a6f297SJonathan Marek #size-cells = <2>; 247146a6f297SJonathan Marek ranges; 247246a6f297SJonathan Marek 247346a6f297SJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 247446a6f297SJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 247546a6f297SJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_EN>, 247646a6f297SJonathan Marek <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 247746a6f297SJonathan Marek clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 247846a6f297SJonathan Marek 247946a6f297SJonathan Marek resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 248046a6f297SJonathan Marek <&gcc GCC_USB3_PHY_SEC_BCR>; 248146a6f297SJonathan Marek reset-names = "phy", "common"; 248246a6f297SJonathan Marek 24831351512fSShawn Guo usb_2_ssphy: phy@88eb200 { 248446a6f297SJonathan Marek reg = <0 0x088eb200 0 0x200>, 248546a6f297SJonathan Marek <0 0x088eb400 0 0x200>, 248646a6f297SJonathan Marek <0 0x088eb800 0 0x800>; 24877178d4ccSJonathan Marek #clock-cells = <0>; 248846a6f297SJonathan Marek #phy-cells = <0>; 248946a6f297SJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 249046a6f297SJonathan Marek clock-names = "pipe0"; 249146a6f297SJonathan Marek clock-output-names = "usb3_uni_phy_pipe_clk_src"; 249246a6f297SJonathan Marek }; 249346a6f297SJonathan Marek }; 249446a6f297SJonathan Marek 2495c4cf0300SManivannan Sadhasivam sdhc_2: sdhci@8804000 { 2496c4cf0300SManivannan Sadhasivam compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 2497c4cf0300SManivannan Sadhasivam reg = <0 0x08804000 0 0x1000>; 2498c4cf0300SManivannan Sadhasivam 2499c4cf0300SManivannan Sadhasivam interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2500c4cf0300SManivannan Sadhasivam <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2501c4cf0300SManivannan Sadhasivam interrupt-names = "hc_irq", "pwr_irq"; 2502c4cf0300SManivannan Sadhasivam 2503c4cf0300SManivannan Sadhasivam clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2504c4cf0300SManivannan Sadhasivam <&gcc GCC_SDCC2_APPS_CLK>, 250574097d80SDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK>; 2506c4cf0300SManivannan Sadhasivam clock-names = "iface", "core", "xo"; 2507c4cf0300SManivannan Sadhasivam iommus = <&apps_smmu 0x4a0 0x0>; 2508c4cf0300SManivannan Sadhasivam qcom,dll-config = <0x0007642c>; 2509c4cf0300SManivannan Sadhasivam qcom,ddr-config = <0x80040868>; 2510c4cf0300SManivannan Sadhasivam power-domains = <&rpmhpd SM8250_CX>; 2511c4cf0300SManivannan Sadhasivam operating-points-v2 = <&sdhc2_opp_table>; 2512c4cf0300SManivannan Sadhasivam 2513c4cf0300SManivannan Sadhasivam status = "disabled"; 2514c4cf0300SManivannan Sadhasivam 2515c4cf0300SManivannan Sadhasivam sdhc2_opp_table: sdhc2-opp-table { 2516c4cf0300SManivannan Sadhasivam compatible = "operating-points-v2"; 2517c4cf0300SManivannan Sadhasivam 2518c4cf0300SManivannan Sadhasivam opp-19200000 { 2519c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <19200000>; 2520c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_min_svs>; 2521c4cf0300SManivannan Sadhasivam }; 2522c4cf0300SManivannan Sadhasivam 2523c4cf0300SManivannan Sadhasivam opp-50000000 { 2524c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <50000000>; 2525c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_low_svs>; 2526c4cf0300SManivannan Sadhasivam }; 2527c4cf0300SManivannan Sadhasivam 2528c4cf0300SManivannan Sadhasivam opp-100000000 { 2529c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <100000000>; 2530c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_svs>; 2531c4cf0300SManivannan Sadhasivam }; 2532c4cf0300SManivannan Sadhasivam 2533c4cf0300SManivannan Sadhasivam opp-202000000 { 2534c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <202000000>; 2535c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_svs_l1>; 2536c4cf0300SManivannan Sadhasivam }; 2537c4cf0300SManivannan Sadhasivam }; 2538c4cf0300SManivannan Sadhasivam }; 2539c4cf0300SManivannan Sadhasivam 2540e7e41a20SJonathan Marek dc_noc: interconnect@90c0000 { 2541e7e41a20SJonathan Marek compatible = "qcom,sm8250-dc-noc"; 2542e7e41a20SJonathan Marek reg = <0 0x090c0000 0 0x4200>; 2543e7e41a20SJonathan Marek #interconnect-cells = <1>; 2544e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 2545e7e41a20SJonathan Marek }; 2546e7e41a20SJonathan Marek 2547e7e41a20SJonathan Marek gem_noc: interconnect@9100000 { 2548e7e41a20SJonathan Marek compatible = "qcom,sm8250-gem-noc"; 2549e7e41a20SJonathan Marek reg = <0 0x09100000 0 0xb4000>; 2550e7e41a20SJonathan Marek #interconnect-cells = <1>; 2551e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 2552e7e41a20SJonathan Marek }; 2553e7e41a20SJonathan Marek 2554e7e41a20SJonathan Marek npu_noc: interconnect@9990000 { 2555e7e41a20SJonathan Marek compatible = "qcom,sm8250-npu-noc"; 2556e7e41a20SJonathan Marek reg = <0 0x09990000 0 0x1600>; 2557e7e41a20SJonathan Marek #interconnect-cells = <1>; 2558e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 2559e7e41a20SJonathan Marek }; 2560e7e41a20SJonathan Marek 256146a6f297SJonathan Marek usb_1: usb@a6f8800 { 256246a6f297SJonathan Marek compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 256346a6f297SJonathan Marek reg = <0 0x0a6f8800 0 0x400>; 256446a6f297SJonathan Marek status = "disabled"; 256546a6f297SJonathan Marek #address-cells = <2>; 256646a6f297SJonathan Marek #size-cells = <2>; 256746a6f297SJonathan Marek ranges; 256846a6f297SJonathan Marek dma-ranges; 256946a6f297SJonathan Marek 257046a6f297SJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 257146a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_MASTER_CLK>, 257246a6f297SJonathan Marek <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 257346a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 257446a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 257546a6f297SJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_EN>; 257646a6f297SJonathan Marek clock-names = "cfg_noc", "core", "iface", "mock_utmi", 257746a6f297SJonathan Marek "sleep", "xo"; 257846a6f297SJonathan Marek 257946a6f297SJonathan Marek assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 258046a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_MASTER_CLK>; 258146a6f297SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 258246a6f297SJonathan Marek 258346a6f297SJonathan Marek interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 258446a6f297SJonathan Marek <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 258546a6f297SJonathan Marek <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 258646a6f297SJonathan Marek <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 258746a6f297SJonathan Marek interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 258846a6f297SJonathan Marek "dm_hs_phy_irq", "ss_phy_irq"; 258946a6f297SJonathan Marek 259046a6f297SJonathan Marek power-domains = <&gcc USB30_PRIM_GDSC>; 259146a6f297SJonathan Marek 259246a6f297SJonathan Marek resets = <&gcc GCC_USB30_PRIM_BCR>; 259346a6f297SJonathan Marek 25942aa2b50dSBhupesh Sharma usb_1_dwc3: usb@a600000 { 259546a6f297SJonathan Marek compatible = "snps,dwc3"; 259646a6f297SJonathan Marek reg = <0 0x0a600000 0 0xcd00>; 259746a6f297SJonathan Marek interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 259846a6f297SJonathan Marek iommus = <&apps_smmu 0x0 0x0>; 259946a6f297SJonathan Marek snps,dis_u2_susphy_quirk; 260046a6f297SJonathan Marek snps,dis_enblslpm_quirk; 260146a6f297SJonathan Marek phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 260246a6f297SJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 260346a6f297SJonathan Marek }; 260446a6f297SJonathan Marek }; 260546a6f297SJonathan Marek 26060085a33aSManivannan Sadhasivam system-cache-controller@9200000 { 26070085a33aSManivannan Sadhasivam compatible = "qcom,sm8250-llcc"; 26080085a33aSManivannan Sadhasivam reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 26090085a33aSManivannan Sadhasivam reg-names = "llcc_base", "llcc_broadcast_base"; 26100085a33aSManivannan Sadhasivam }; 26110085a33aSManivannan Sadhasivam 261246a6f297SJonathan Marek usb_2: usb@a8f8800 { 261346a6f297SJonathan Marek compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 261446a6f297SJonathan Marek reg = <0 0x0a8f8800 0 0x400>; 261546a6f297SJonathan Marek status = "disabled"; 261646a6f297SJonathan Marek #address-cells = <2>; 261746a6f297SJonathan Marek #size-cells = <2>; 261846a6f297SJonathan Marek ranges; 261946a6f297SJonathan Marek dma-ranges; 262046a6f297SJonathan Marek 262146a6f297SJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 262246a6f297SJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>, 262346a6f297SJonathan Marek <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 262446a6f297SJonathan Marek <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 262546a6f297SJonathan Marek <&gcc GCC_USB30_SEC_SLEEP_CLK>, 262646a6f297SJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_EN>; 262746a6f297SJonathan Marek clock-names = "cfg_noc", "core", "iface", "mock_utmi", 262846a6f297SJonathan Marek "sleep", "xo"; 262946a6f297SJonathan Marek 263046a6f297SJonathan Marek assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 263146a6f297SJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>; 263246a6f297SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 263346a6f297SJonathan Marek 263446a6f297SJonathan Marek interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 263546a6f297SJonathan Marek <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 263646a6f297SJonathan Marek <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 263746a6f297SJonathan Marek <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 263846a6f297SJonathan Marek interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 263946a6f297SJonathan Marek "dm_hs_phy_irq", "ss_phy_irq"; 264046a6f297SJonathan Marek 264146a6f297SJonathan Marek power-domains = <&gcc USB30_SEC_GDSC>; 264246a6f297SJonathan Marek 264346a6f297SJonathan Marek resets = <&gcc GCC_USB30_SEC_BCR>; 264446a6f297SJonathan Marek 26452aa2b50dSBhupesh Sharma usb_2_dwc3: usb@a800000 { 264646a6f297SJonathan Marek compatible = "snps,dwc3"; 264746a6f297SJonathan Marek reg = <0 0x0a800000 0 0xcd00>; 264846a6f297SJonathan Marek interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 264946a6f297SJonathan Marek iommus = <&apps_smmu 0x20 0>; 265046a6f297SJonathan Marek snps,dis_u2_susphy_quirk; 265146a6f297SJonathan Marek snps,dis_enblslpm_quirk; 265246a6f297SJonathan Marek phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 265346a6f297SJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 265446a6f297SJonathan Marek }; 265546a6f297SJonathan Marek }; 265646a6f297SJonathan Marek 2657fa245b3fSBryan O'Donoghue venus: video-codec@aa00000 { 2658fa245b3fSBryan O'Donoghue compatible = "qcom,sm8250-venus"; 2659fa245b3fSBryan O'Donoghue reg = <0 0x0aa00000 0 0x100000>; 2660fa245b3fSBryan O'Donoghue interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2661fa245b3fSBryan O'Donoghue power-domains = <&videocc MVS0C_GDSC>, 2662fa245b3fSBryan O'Donoghue <&videocc MVS0_GDSC>, 2663fa245b3fSBryan O'Donoghue <&rpmhpd SM8250_MX>; 2664fa245b3fSBryan O'Donoghue power-domain-names = "venus", "vcodec0", "mx"; 2665fa245b3fSBryan O'Donoghue operating-points-v2 = <&venus_opp_table>; 2666fa245b3fSBryan O'Donoghue 2667fa245b3fSBryan O'Donoghue clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 2668fa245b3fSBryan O'Donoghue <&videocc VIDEO_CC_MVS0C_CLK>, 2669fa245b3fSBryan O'Donoghue <&videocc VIDEO_CC_MVS0_CLK>; 2670fa245b3fSBryan O'Donoghue clock-names = "iface", "core", "vcodec0_core"; 2671fa245b3fSBryan O'Donoghue 2672fa245b3fSBryan O'Donoghue interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, 2673fa245b3fSBryan O'Donoghue <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; 2674fa245b3fSBryan O'Donoghue interconnect-names = "cpu-cfg", "video-mem"; 2675fa245b3fSBryan O'Donoghue 2676fa245b3fSBryan O'Donoghue iommus = <&apps_smmu 0x2100 0x0400>; 2677fa245b3fSBryan O'Donoghue memory-region = <&video_mem>; 2678fa245b3fSBryan O'Donoghue 2679fa245b3fSBryan O'Donoghue resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 2680fa245b3fSBryan O'Donoghue <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 2681fa245b3fSBryan O'Donoghue reset-names = "bus", "core"; 2682fa245b3fSBryan O'Donoghue 2683ece28cb5SKonrad Dybcio status = "disabled"; 2684ece28cb5SKonrad Dybcio 2685fa245b3fSBryan O'Donoghue video-decoder { 2686fa245b3fSBryan O'Donoghue compatible = "venus-decoder"; 2687fa245b3fSBryan O'Donoghue }; 2688fa245b3fSBryan O'Donoghue 2689fa245b3fSBryan O'Donoghue video-encoder { 2690fa245b3fSBryan O'Donoghue compatible = "venus-encoder"; 2691fa245b3fSBryan O'Donoghue }; 2692fa245b3fSBryan O'Donoghue 2693fa245b3fSBryan O'Donoghue venus_opp_table: venus-opp-table { 2694fa245b3fSBryan O'Donoghue compatible = "operating-points-v2"; 2695fa245b3fSBryan O'Donoghue 2696fa245b3fSBryan O'Donoghue opp-720000000 { 2697fa245b3fSBryan O'Donoghue opp-hz = /bits/ 64 <720000000>; 2698fa245b3fSBryan O'Donoghue required-opps = <&rpmhpd_opp_low_svs>; 2699fa245b3fSBryan O'Donoghue }; 2700fa245b3fSBryan O'Donoghue 2701fa245b3fSBryan O'Donoghue opp-1014000000 { 2702fa245b3fSBryan O'Donoghue opp-hz = /bits/ 64 <1014000000>; 2703fa245b3fSBryan O'Donoghue required-opps = <&rpmhpd_opp_svs>; 2704fa245b3fSBryan O'Donoghue }; 2705fa245b3fSBryan O'Donoghue 2706fa245b3fSBryan O'Donoghue opp-1098000000 { 2707fa245b3fSBryan O'Donoghue opp-hz = /bits/ 64 <1098000000>; 2708fa245b3fSBryan O'Donoghue required-opps = <&rpmhpd_opp_svs_l1>; 2709fa245b3fSBryan O'Donoghue }; 2710fa245b3fSBryan O'Donoghue 2711fa245b3fSBryan O'Donoghue opp-1332000000 { 2712fa245b3fSBryan O'Donoghue opp-hz = /bits/ 64 <1332000000>; 2713fa245b3fSBryan O'Donoghue required-opps = <&rpmhpd_opp_nom>; 2714fa245b3fSBryan O'Donoghue }; 2715fa245b3fSBryan O'Donoghue }; 2716fa245b3fSBryan O'Donoghue }; 2717fa245b3fSBryan O'Donoghue 27185b9ec225Sjonathan@marek.ca videocc: clock-controller@abf0000 { 27195b9ec225Sjonathan@marek.ca compatible = "qcom,sm8250-videocc"; 27205b9ec225Sjonathan@marek.ca reg = <0 0x0abf0000 0 0x10000>; 27215b9ec225Sjonathan@marek.ca clocks = <&gcc GCC_VIDEO_AHB_CLK>, 27225b9ec225Sjonathan@marek.ca <&rpmhcc RPMH_CXO_CLK>, 27235b9ec225Sjonathan@marek.ca <&rpmhcc RPMH_CXO_CLK_A>; 2724266e5cf3SDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 2725266e5cf3SDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 27265b9ec225Sjonathan@marek.ca clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 27275b9ec225Sjonathan@marek.ca #clock-cells = <1>; 27285b9ec225Sjonathan@marek.ca #reset-cells = <1>; 27295b9ec225Sjonathan@marek.ca #power-domain-cells = <1>; 27305b9ec225Sjonathan@marek.ca }; 27315b9ec225Sjonathan@marek.ca 27327c1dffd4SDmitry Baryshkov mdss: mdss@ae00000 { 2733dc5d9125SJonathan Marek compatible = "qcom,sm8250-mdss"; 27347c1dffd4SDmitry Baryshkov reg = <0 0x0ae00000 0 0x1000>; 27357c1dffd4SDmitry Baryshkov reg-names = "mdss"; 27367c1dffd4SDmitry Baryshkov 2737888771a9SJonathan Marek interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 27387c1dffd4SDmitry Baryshkov <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 2739888771a9SJonathan Marek interconnect-names = "mdp0-mem", "mdp1-mem"; 27407c1dffd4SDmitry Baryshkov 27417c1dffd4SDmitry Baryshkov power-domains = <&dispcc MDSS_GDSC>; 27427c1dffd4SDmitry Baryshkov 27437c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2744e091b836SAmit Pundir <&gcc GCC_DISP_HF_AXI_CLK>, 27457c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_SF_AXI_CLK>, 27467c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_MDP_CLK>; 2747e091b836SAmit Pundir clock-names = "iface", "bus", "nrt_bus", "core"; 27487c1dffd4SDmitry Baryshkov 27497c1dffd4SDmitry Baryshkov assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 27507c1dffd4SDmitry Baryshkov assigned-clock-rates = <460000000>; 27517c1dffd4SDmitry Baryshkov 27527c1dffd4SDmitry Baryshkov interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 27537c1dffd4SDmitry Baryshkov interrupt-controller; 27547c1dffd4SDmitry Baryshkov #interrupt-cells = <1>; 27557c1dffd4SDmitry Baryshkov 27567c1dffd4SDmitry Baryshkov iommus = <&apps_smmu 0x820 0x402>; 27577c1dffd4SDmitry Baryshkov 27587c1dffd4SDmitry Baryshkov status = "disabled"; 27597c1dffd4SDmitry Baryshkov 27607c1dffd4SDmitry Baryshkov #address-cells = <2>; 27617c1dffd4SDmitry Baryshkov #size-cells = <2>; 27627c1dffd4SDmitry Baryshkov ranges; 27637c1dffd4SDmitry Baryshkov 27647c1dffd4SDmitry Baryshkov mdss_mdp: mdp@ae01000 { 2765dc5d9125SJonathan Marek compatible = "qcom,sm8250-dpu"; 27667c1dffd4SDmitry Baryshkov reg = <0 0x0ae01000 0 0x8f000>, 27677c1dffd4SDmitry Baryshkov <0 0x0aeb0000 0 0x2008>; 27687c1dffd4SDmitry Baryshkov reg-names = "mdp", "vbif"; 27697c1dffd4SDmitry Baryshkov 27707c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 27717c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_HF_AXI_CLK>, 27727c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_MDP_CLK>, 27737c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 27747c1dffd4SDmitry Baryshkov clock-names = "iface", "bus", "core", "vsync"; 27757c1dffd4SDmitry Baryshkov 27767c1dffd4SDmitry Baryshkov assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 27777c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 27787c1dffd4SDmitry Baryshkov assigned-clock-rates = <460000000>, 27797c1dffd4SDmitry Baryshkov <19200000>; 27807c1dffd4SDmitry Baryshkov 27817c1dffd4SDmitry Baryshkov operating-points-v2 = <&mdp_opp_table>; 27827c1dffd4SDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 27837c1dffd4SDmitry Baryshkov 27847c1dffd4SDmitry Baryshkov interrupt-parent = <&mdss>; 27857c1dffd4SDmitry Baryshkov interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 27867c1dffd4SDmitry Baryshkov 27877c1dffd4SDmitry Baryshkov ports { 27887c1dffd4SDmitry Baryshkov #address-cells = <1>; 27897c1dffd4SDmitry Baryshkov #size-cells = <0>; 27907c1dffd4SDmitry Baryshkov 27917c1dffd4SDmitry Baryshkov port@0 { 27927c1dffd4SDmitry Baryshkov reg = <0>; 27937c1dffd4SDmitry Baryshkov dpu_intf1_out: endpoint { 27947c1dffd4SDmitry Baryshkov remote-endpoint = <&dsi0_in>; 27957c1dffd4SDmitry Baryshkov }; 27967c1dffd4SDmitry Baryshkov }; 27977c1dffd4SDmitry Baryshkov 27987c1dffd4SDmitry Baryshkov port@1 { 27997c1dffd4SDmitry Baryshkov reg = <1>; 28007c1dffd4SDmitry Baryshkov dpu_intf2_out: endpoint { 28017c1dffd4SDmitry Baryshkov remote-endpoint = <&dsi1_in>; 28027c1dffd4SDmitry Baryshkov }; 28037c1dffd4SDmitry Baryshkov }; 28047c1dffd4SDmitry Baryshkov }; 28057c1dffd4SDmitry Baryshkov 28067c1dffd4SDmitry Baryshkov mdp_opp_table: mdp-opp-table { 28077c1dffd4SDmitry Baryshkov compatible = "operating-points-v2"; 28087c1dffd4SDmitry Baryshkov 28097c1dffd4SDmitry Baryshkov opp-200000000 { 28107c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <200000000>; 28117c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 28127c1dffd4SDmitry Baryshkov }; 28137c1dffd4SDmitry Baryshkov 28147c1dffd4SDmitry Baryshkov opp-300000000 { 28157c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <300000000>; 28167c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs>; 28177c1dffd4SDmitry Baryshkov }; 28187c1dffd4SDmitry Baryshkov 28197c1dffd4SDmitry Baryshkov opp-345000000 { 28207c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <345000000>; 28217c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs_l1>; 28227c1dffd4SDmitry Baryshkov }; 28237c1dffd4SDmitry Baryshkov 28247c1dffd4SDmitry Baryshkov opp-460000000 { 28257c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <460000000>; 28267c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_nom>; 28277c1dffd4SDmitry Baryshkov }; 28287c1dffd4SDmitry Baryshkov }; 28297c1dffd4SDmitry Baryshkov }; 28307c1dffd4SDmitry Baryshkov 28317c1dffd4SDmitry Baryshkov dsi0: dsi@ae94000 { 28327c1dffd4SDmitry Baryshkov compatible = "qcom,mdss-dsi-ctrl"; 28337c1dffd4SDmitry Baryshkov reg = <0 0x0ae94000 0 0x400>; 28347c1dffd4SDmitry Baryshkov reg-names = "dsi_ctrl"; 28357c1dffd4SDmitry Baryshkov 28367c1dffd4SDmitry Baryshkov interrupt-parent = <&mdss>; 28377c1dffd4SDmitry Baryshkov interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 28387c1dffd4SDmitry Baryshkov 28397c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 28407c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 28417c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 28427c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_ESC0_CLK>, 28437c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_AHB_CLK>, 28447c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_HF_AXI_CLK>; 28457c1dffd4SDmitry Baryshkov clock-names = "byte", 28467c1dffd4SDmitry Baryshkov "byte_intf", 28477c1dffd4SDmitry Baryshkov "pixel", 28487c1dffd4SDmitry Baryshkov "core", 28497c1dffd4SDmitry Baryshkov "iface", 28507c1dffd4SDmitry Baryshkov "bus"; 28517c1dffd4SDmitry Baryshkov 285297ec669dSDmitry Baryshkov assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 285397ec669dSDmitry Baryshkov assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 285497ec669dSDmitry Baryshkov 28557c1dffd4SDmitry Baryshkov operating-points-v2 = <&dsi_opp_table>; 28567c1dffd4SDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 28577c1dffd4SDmitry Baryshkov 28587c1dffd4SDmitry Baryshkov phys = <&dsi0_phy>; 28597c1dffd4SDmitry Baryshkov phy-names = "dsi"; 28607c1dffd4SDmitry Baryshkov 28617c1dffd4SDmitry Baryshkov status = "disabled"; 28627c1dffd4SDmitry Baryshkov 286340f7d36dSKonrad Dybcio #address-cells = <1>; 286440f7d36dSKonrad Dybcio #size-cells = <0>; 286540f7d36dSKonrad Dybcio 28667c1dffd4SDmitry Baryshkov ports { 28677c1dffd4SDmitry Baryshkov #address-cells = <1>; 28687c1dffd4SDmitry Baryshkov #size-cells = <0>; 28697c1dffd4SDmitry Baryshkov 28707c1dffd4SDmitry Baryshkov port@0 { 28717c1dffd4SDmitry Baryshkov reg = <0>; 28727c1dffd4SDmitry Baryshkov dsi0_in: endpoint { 28737c1dffd4SDmitry Baryshkov remote-endpoint = <&dpu_intf1_out>; 28747c1dffd4SDmitry Baryshkov }; 28757c1dffd4SDmitry Baryshkov }; 28767c1dffd4SDmitry Baryshkov 28777c1dffd4SDmitry Baryshkov port@1 { 28787c1dffd4SDmitry Baryshkov reg = <1>; 28797c1dffd4SDmitry Baryshkov dsi0_out: endpoint { 28807c1dffd4SDmitry Baryshkov }; 28817c1dffd4SDmitry Baryshkov }; 28827c1dffd4SDmitry Baryshkov }; 28837c1dffd4SDmitry Baryshkov }; 28847c1dffd4SDmitry Baryshkov 28857c1dffd4SDmitry Baryshkov dsi0_phy: dsi-phy@ae94400 { 28867c1dffd4SDmitry Baryshkov compatible = "qcom,dsi-phy-7nm"; 28877c1dffd4SDmitry Baryshkov reg = <0 0x0ae94400 0 0x200>, 28887c1dffd4SDmitry Baryshkov <0 0x0ae94600 0 0x280>, 28897c1dffd4SDmitry Baryshkov <0 0x0ae94900 0 0x260>; 28907c1dffd4SDmitry Baryshkov reg-names = "dsi_phy", 28917c1dffd4SDmitry Baryshkov "dsi_phy_lane", 28927c1dffd4SDmitry Baryshkov "dsi_pll"; 28937c1dffd4SDmitry Baryshkov 28947c1dffd4SDmitry Baryshkov #clock-cells = <1>; 28957c1dffd4SDmitry Baryshkov #phy-cells = <0>; 28967c1dffd4SDmitry Baryshkov 28977c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 28987c1dffd4SDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK>; 28997c1dffd4SDmitry Baryshkov clock-names = "iface", "ref"; 29007c1dffd4SDmitry Baryshkov 29017c1dffd4SDmitry Baryshkov status = "disabled"; 29027c1dffd4SDmitry Baryshkov }; 29037c1dffd4SDmitry Baryshkov 29047c1dffd4SDmitry Baryshkov dsi1: dsi@ae96000 { 29057c1dffd4SDmitry Baryshkov compatible = "qcom,mdss-dsi-ctrl"; 29067c1dffd4SDmitry Baryshkov reg = <0 0x0ae96000 0 0x400>; 29077c1dffd4SDmitry Baryshkov reg-names = "dsi_ctrl"; 29087c1dffd4SDmitry Baryshkov 29097c1dffd4SDmitry Baryshkov interrupt-parent = <&mdss>; 29107c1dffd4SDmitry Baryshkov interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 29117c1dffd4SDmitry Baryshkov 29127c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 29137c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 29147c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 29157c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_ESC1_CLK>, 29167c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_AHB_CLK>, 29177c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_HF_AXI_CLK>; 29187c1dffd4SDmitry Baryshkov clock-names = "byte", 29197c1dffd4SDmitry Baryshkov "byte_intf", 29207c1dffd4SDmitry Baryshkov "pixel", 29217c1dffd4SDmitry Baryshkov "core", 29227c1dffd4SDmitry Baryshkov "iface", 29237c1dffd4SDmitry Baryshkov "bus"; 29247c1dffd4SDmitry Baryshkov 292597ec669dSDmitry Baryshkov assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 292697ec669dSDmitry Baryshkov assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 292797ec669dSDmitry Baryshkov 29287c1dffd4SDmitry Baryshkov operating-points-v2 = <&dsi_opp_table>; 29297c1dffd4SDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 29307c1dffd4SDmitry Baryshkov 29317c1dffd4SDmitry Baryshkov phys = <&dsi1_phy>; 29327c1dffd4SDmitry Baryshkov phy-names = "dsi"; 29337c1dffd4SDmitry Baryshkov 29347c1dffd4SDmitry Baryshkov status = "disabled"; 29357c1dffd4SDmitry Baryshkov 293640f7d36dSKonrad Dybcio #address-cells = <1>; 293740f7d36dSKonrad Dybcio #size-cells = <0>; 293840f7d36dSKonrad Dybcio 29397c1dffd4SDmitry Baryshkov ports { 29407c1dffd4SDmitry Baryshkov #address-cells = <1>; 29417c1dffd4SDmitry Baryshkov #size-cells = <0>; 29427c1dffd4SDmitry Baryshkov 29437c1dffd4SDmitry Baryshkov port@0 { 29447c1dffd4SDmitry Baryshkov reg = <0>; 29457c1dffd4SDmitry Baryshkov dsi1_in: endpoint { 29467c1dffd4SDmitry Baryshkov remote-endpoint = <&dpu_intf2_out>; 29477c1dffd4SDmitry Baryshkov }; 29487c1dffd4SDmitry Baryshkov }; 29497c1dffd4SDmitry Baryshkov 29507c1dffd4SDmitry Baryshkov port@1 { 29517c1dffd4SDmitry Baryshkov reg = <1>; 29527c1dffd4SDmitry Baryshkov dsi1_out: endpoint { 29537c1dffd4SDmitry Baryshkov }; 29547c1dffd4SDmitry Baryshkov }; 29557c1dffd4SDmitry Baryshkov }; 29567c1dffd4SDmitry Baryshkov }; 29577c1dffd4SDmitry Baryshkov 29587c1dffd4SDmitry Baryshkov dsi1_phy: dsi-phy@ae96400 { 29597c1dffd4SDmitry Baryshkov compatible = "qcom,dsi-phy-7nm"; 29607c1dffd4SDmitry Baryshkov reg = <0 0x0ae96400 0 0x200>, 29617c1dffd4SDmitry Baryshkov <0 0x0ae96600 0 0x280>, 29627c1dffd4SDmitry Baryshkov <0 0x0ae96900 0 0x260>; 29637c1dffd4SDmitry Baryshkov reg-names = "dsi_phy", 29647c1dffd4SDmitry Baryshkov "dsi_phy_lane", 29657c1dffd4SDmitry Baryshkov "dsi_pll"; 29667c1dffd4SDmitry Baryshkov 29677c1dffd4SDmitry Baryshkov #clock-cells = <1>; 29687c1dffd4SDmitry Baryshkov #phy-cells = <0>; 29697c1dffd4SDmitry Baryshkov 29707c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 29717c1dffd4SDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK>; 29727c1dffd4SDmitry Baryshkov clock-names = "iface", "ref"; 29737c1dffd4SDmitry Baryshkov 29747c1dffd4SDmitry Baryshkov status = "disabled"; 29757c1dffd4SDmitry Baryshkov 29767c1dffd4SDmitry Baryshkov dsi_opp_table: dsi-opp-table { 29777c1dffd4SDmitry Baryshkov compatible = "operating-points-v2"; 29787c1dffd4SDmitry Baryshkov 29797c1dffd4SDmitry Baryshkov opp-187500000 { 29807c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <187500000>; 29817c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 29827c1dffd4SDmitry Baryshkov }; 29837c1dffd4SDmitry Baryshkov 29847c1dffd4SDmitry Baryshkov opp-300000000 { 29857c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <300000000>; 29867c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs>; 29877c1dffd4SDmitry Baryshkov }; 29887c1dffd4SDmitry Baryshkov 29897c1dffd4SDmitry Baryshkov opp-358000000 { 29907c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <358000000>; 29917c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs_l1>; 29927c1dffd4SDmitry Baryshkov }; 29937c1dffd4SDmitry Baryshkov }; 29947c1dffd4SDmitry Baryshkov }; 29957c1dffd4SDmitry Baryshkov }; 29967c1dffd4SDmitry Baryshkov 29977c1dffd4SDmitry Baryshkov dispcc: clock-controller@af00000 { 29987c1dffd4SDmitry Baryshkov compatible = "qcom,sm8250-dispcc"; 2999888771a9SJonathan Marek reg = <0 0x0af00000 0 0x10000>; 3000266e5cf3SDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 3001266e5cf3SDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 30027c1dffd4SDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>, 30037c1dffd4SDmitry Baryshkov <&dsi0_phy 0>, 30047c1dffd4SDmitry Baryshkov <&dsi0_phy 1>, 30057c1dffd4SDmitry Baryshkov <&dsi1_phy 0>, 30067c1dffd4SDmitry Baryshkov <&dsi1_phy 1>, 30079b315324SDmitry Baryshkov <&dp_phy 0>, 30089b315324SDmitry Baryshkov <&dp_phy 1>; 30097c1dffd4SDmitry Baryshkov clock-names = "bi_tcxo", 30107c1dffd4SDmitry Baryshkov "dsi0_phy_pll_out_byteclk", 30117c1dffd4SDmitry Baryshkov "dsi0_phy_pll_out_dsiclk", 30127c1dffd4SDmitry Baryshkov "dsi1_phy_pll_out_byteclk", 30137c1dffd4SDmitry Baryshkov "dsi1_phy_pll_out_dsiclk", 3014888771a9SJonathan Marek "dp_phy_pll_link_clk", 3015888771a9SJonathan Marek "dp_phy_pll_vco_div_clk"; 30167c1dffd4SDmitry Baryshkov #clock-cells = <1>; 30177c1dffd4SDmitry Baryshkov #reset-cells = <1>; 30187c1dffd4SDmitry Baryshkov #power-domain-cells = <1>; 30197c1dffd4SDmitry Baryshkov }; 30207c1dffd4SDmitry Baryshkov 302160378f1aSVenkata Narendra Kumar Gutta pdc: interrupt-controller@b220000 { 302224003196SBjorn Andersson compatible = "qcom,sm8250-pdc", "qcom,pdc"; 302324003196SBjorn Andersson reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 302460378f1aSVenkata Narendra Kumar Gutta qcom,pdc-ranges = <0 480 94>, <94 609 31>, 302560378f1aSVenkata Narendra Kumar Gutta <125 63 1>, <126 716 12>; 302660378f1aSVenkata Narendra Kumar Gutta #interrupt-cells = <2>; 302760378f1aSVenkata Narendra Kumar Gutta interrupt-parent = <&intc>; 302860378f1aSVenkata Narendra Kumar Gutta interrupt-controller; 302960378f1aSVenkata Narendra Kumar Gutta }; 303060378f1aSVenkata Narendra Kumar Gutta 3031bac12f25SAmit Kucheria tsens0: thermal-sensor@c263000 { 3032bac12f25SAmit Kucheria compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 3033bac12f25SAmit Kucheria reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3034bac12f25SAmit Kucheria <0 0x0c222000 0 0x1ff>; /* SROT */ 3035bac12f25SAmit Kucheria #qcom,sensors = <16>; 3036bac12f25SAmit Kucheria interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3037bac12f25SAmit Kucheria <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3038bac12f25SAmit Kucheria interrupt-names = "uplow", "critical"; 3039bac12f25SAmit Kucheria #thermal-sensor-cells = <1>; 3040bac12f25SAmit Kucheria }; 3041bac12f25SAmit Kucheria 3042bac12f25SAmit Kucheria tsens1: thermal-sensor@c265000 { 3043bac12f25SAmit Kucheria compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 3044bac12f25SAmit Kucheria reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3045bac12f25SAmit Kucheria <0 0x0c223000 0 0x1ff>; /* SROT */ 3046bac12f25SAmit Kucheria #qcom,sensors = <9>; 3047bac12f25SAmit Kucheria interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3048bac12f25SAmit Kucheria <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3049bac12f25SAmit Kucheria interrupt-names = "uplow", "critical"; 3050bac12f25SAmit Kucheria #thermal-sensor-cells = <1>; 3051bac12f25SAmit Kucheria }; 3052bac12f25SAmit Kucheria 305343f14a0bSSai Prakash Ranjan aoss_qmp: power-controller@c300000 { 3054087d537aSBjorn Andersson compatible = "qcom,sm8250-aoss-qmp"; 305547cb6a06SMaulik Shah reg = <0 0x0c300000 0 0x400>; 3056087d537aSBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3057087d537aSBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 3058087d537aSBjorn Andersson IRQ_TYPE_EDGE_RISING>; 3059087d537aSBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_AOP 3060087d537aSBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 3061087d537aSBjorn Andersson 3062087d537aSBjorn Andersson #clock-cells = <0>; 3063087d537aSBjorn Andersson }; 3064087d537aSBjorn Andersson 306547cb6a06SMaulik Shah sram@c3f0000 { 306647cb6a06SMaulik Shah compatible = "qcom,rpmh-stats"; 306747cb6a06SMaulik Shah reg = <0 0x0c3f0000 0 0x400>; 306860378f1aSVenkata Narendra Kumar Gutta }; 306960378f1aSVenkata Narendra Kumar Gutta 307060378f1aSVenkata Narendra Kumar Gutta spmi_bus: spmi@c440000 { 307160378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,spmi-pmic-arb"; 307260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x0c440000 0x0 0x0001100>, 307360378f1aSVenkata Narendra Kumar Gutta <0x0 0x0c600000 0x0 0x2000000>, 307416951b49SBjorn Andersson <0x0 0x0e600000 0x0 0x0100000>, 307516951b49SBjorn Andersson <0x0 0x0e700000 0x0 0x00a0000>, 307616951b49SBjorn Andersson <0x0 0x0c40a000 0x0 0x0026000>; 307716951b49SBjorn Andersson reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 307816951b49SBjorn Andersson interrupt-names = "periph_irq"; 307916951b49SBjorn Andersson interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 308016951b49SBjorn Andersson qcom,ee = <0>; 308116951b49SBjorn Andersson qcom,channel = <0>; 308216951b49SBjorn Andersson #address-cells = <2>; 308316951b49SBjorn Andersson #size-cells = <0>; 308416951b49SBjorn Andersson interrupt-controller; 308516951b49SBjorn Andersson #interrupt-cells = <4>; 308616951b49SBjorn Andersson }; 3087e5813b15SDmitry Baryshkov 3088e5813b15SDmitry Baryshkov tlmm: pinctrl@f100000 { 3089e5813b15SDmitry Baryshkov compatible = "qcom,sm8250-pinctrl"; 3090e5813b15SDmitry Baryshkov reg = <0 0x0f100000 0 0x300000>, 3091e5813b15SDmitry Baryshkov <0 0x0f500000 0 0x300000>, 3092e5813b15SDmitry Baryshkov <0 0x0f900000 0 0x300000>; 3093e5813b15SDmitry Baryshkov reg-names = "west", "south", "north"; 3094e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3095e5813b15SDmitry Baryshkov gpio-controller; 3096e5813b15SDmitry Baryshkov #gpio-cells = <2>; 3097e5813b15SDmitry Baryshkov interrupt-controller; 3098e5813b15SDmitry Baryshkov #interrupt-cells = <2>; 3099e526cb03SShawn Guo gpio-ranges = <&tlmm 0 0 181>; 310016951b49SBjorn Andersson wakeup-parent = <&pdc>; 3101e5813b15SDmitry Baryshkov 3102b657d372SSrinivas Kandagatla pri_mi2s_active: pri-mi2s-active { 3103b657d372SSrinivas Kandagatla sclk { 3104b657d372SSrinivas Kandagatla pins = "gpio138"; 3105b657d372SSrinivas Kandagatla function = "mi2s0_sck"; 3106b657d372SSrinivas Kandagatla drive-strength = <8>; 3107b657d372SSrinivas Kandagatla bias-disable; 3108b657d372SSrinivas Kandagatla }; 3109b657d372SSrinivas Kandagatla 3110b657d372SSrinivas Kandagatla ws { 3111b657d372SSrinivas Kandagatla pins = "gpio141"; 3112b657d372SSrinivas Kandagatla function = "mi2s0_ws"; 3113b657d372SSrinivas Kandagatla drive-strength = <8>; 3114b657d372SSrinivas Kandagatla output-high; 3115b657d372SSrinivas Kandagatla }; 3116b657d372SSrinivas Kandagatla 3117b657d372SSrinivas Kandagatla data0 { 3118b657d372SSrinivas Kandagatla pins = "gpio139"; 3119b657d372SSrinivas Kandagatla function = "mi2s0_data0"; 3120b657d372SSrinivas Kandagatla drive-strength = <8>; 3121b657d372SSrinivas Kandagatla bias-disable; 3122b657d372SSrinivas Kandagatla output-high; 3123b657d372SSrinivas Kandagatla }; 3124b657d372SSrinivas Kandagatla 3125b657d372SSrinivas Kandagatla data1 { 3126b657d372SSrinivas Kandagatla pins = "gpio140"; 3127b657d372SSrinivas Kandagatla function = "mi2s0_data1"; 3128b657d372SSrinivas Kandagatla drive-strength = <8>; 3129b657d372SSrinivas Kandagatla output-high; 3130b657d372SSrinivas Kandagatla }; 3131b657d372SSrinivas Kandagatla }; 3132b657d372SSrinivas Kandagatla 3133e5813b15SDmitry Baryshkov qup_i2c0_default: qup-i2c0-default { 3134e5813b15SDmitry Baryshkov mux { 3135e5813b15SDmitry Baryshkov pins = "gpio28", "gpio29"; 3136e5813b15SDmitry Baryshkov function = "qup0"; 3137e5813b15SDmitry Baryshkov }; 3138e5813b15SDmitry Baryshkov 3139e5813b15SDmitry Baryshkov config { 3140e5813b15SDmitry Baryshkov pins = "gpio28", "gpio29"; 3141e5813b15SDmitry Baryshkov drive-strength = <2>; 3142e5813b15SDmitry Baryshkov bias-disable; 3143e5813b15SDmitry Baryshkov }; 3144e5813b15SDmitry Baryshkov }; 3145e5813b15SDmitry Baryshkov 3146e5813b15SDmitry Baryshkov qup_i2c1_default: qup-i2c1-default { 3147e5813b15SDmitry Baryshkov pinmux { 3148e5813b15SDmitry Baryshkov pins = "gpio4", "gpio5"; 3149e5813b15SDmitry Baryshkov function = "qup1"; 3150e5813b15SDmitry Baryshkov }; 3151e5813b15SDmitry Baryshkov 3152e5813b15SDmitry Baryshkov config { 3153e5813b15SDmitry Baryshkov pins = "gpio4", "gpio5"; 3154e5813b15SDmitry Baryshkov drive-strength = <2>; 3155e5813b15SDmitry Baryshkov bias-disable; 3156e5813b15SDmitry Baryshkov }; 3157e5813b15SDmitry Baryshkov }; 3158e5813b15SDmitry Baryshkov 3159e5813b15SDmitry Baryshkov qup_i2c2_default: qup-i2c2-default { 3160e5813b15SDmitry Baryshkov mux { 3161e5813b15SDmitry Baryshkov pins = "gpio115", "gpio116"; 3162e5813b15SDmitry Baryshkov function = "qup2"; 3163e5813b15SDmitry Baryshkov }; 3164e5813b15SDmitry Baryshkov 3165e5813b15SDmitry Baryshkov config { 3166e5813b15SDmitry Baryshkov pins = "gpio115", "gpio116"; 3167e5813b15SDmitry Baryshkov drive-strength = <2>; 3168e5813b15SDmitry Baryshkov bias-disable; 3169e5813b15SDmitry Baryshkov }; 3170e5813b15SDmitry Baryshkov }; 3171e5813b15SDmitry Baryshkov 3172e5813b15SDmitry Baryshkov qup_i2c3_default: qup-i2c3-default { 3173e5813b15SDmitry Baryshkov mux { 3174e5813b15SDmitry Baryshkov pins = "gpio119", "gpio120"; 3175e5813b15SDmitry Baryshkov function = "qup3"; 3176e5813b15SDmitry Baryshkov }; 3177e5813b15SDmitry Baryshkov 3178e5813b15SDmitry Baryshkov config { 3179e5813b15SDmitry Baryshkov pins = "gpio119", "gpio120"; 3180e5813b15SDmitry Baryshkov drive-strength = <2>; 3181e5813b15SDmitry Baryshkov bias-disable; 3182e5813b15SDmitry Baryshkov }; 3183e5813b15SDmitry Baryshkov }; 3184e5813b15SDmitry Baryshkov 3185e5813b15SDmitry Baryshkov qup_i2c4_default: qup-i2c4-default { 3186e5813b15SDmitry Baryshkov mux { 3187e5813b15SDmitry Baryshkov pins = "gpio8", "gpio9"; 3188e5813b15SDmitry Baryshkov function = "qup4"; 3189e5813b15SDmitry Baryshkov }; 3190e5813b15SDmitry Baryshkov 3191e5813b15SDmitry Baryshkov config { 3192e5813b15SDmitry Baryshkov pins = "gpio8", "gpio9"; 3193e5813b15SDmitry Baryshkov drive-strength = <2>; 3194e5813b15SDmitry Baryshkov bias-disable; 3195e5813b15SDmitry Baryshkov }; 3196e5813b15SDmitry Baryshkov }; 3197e5813b15SDmitry Baryshkov 3198e5813b15SDmitry Baryshkov qup_i2c5_default: qup-i2c5-default { 3199e5813b15SDmitry Baryshkov mux { 3200e5813b15SDmitry Baryshkov pins = "gpio12", "gpio13"; 3201e5813b15SDmitry Baryshkov function = "qup5"; 3202e5813b15SDmitry Baryshkov }; 3203e5813b15SDmitry Baryshkov 3204e5813b15SDmitry Baryshkov config { 3205e5813b15SDmitry Baryshkov pins = "gpio12", "gpio13"; 3206e5813b15SDmitry Baryshkov drive-strength = <2>; 3207e5813b15SDmitry Baryshkov bias-disable; 3208e5813b15SDmitry Baryshkov }; 3209e5813b15SDmitry Baryshkov }; 3210e5813b15SDmitry Baryshkov 3211e5813b15SDmitry Baryshkov qup_i2c6_default: qup-i2c6-default { 3212e5813b15SDmitry Baryshkov mux { 3213e5813b15SDmitry Baryshkov pins = "gpio16", "gpio17"; 3214e5813b15SDmitry Baryshkov function = "qup6"; 3215e5813b15SDmitry Baryshkov }; 3216e5813b15SDmitry Baryshkov 3217e5813b15SDmitry Baryshkov config { 3218e5813b15SDmitry Baryshkov pins = "gpio16", "gpio17"; 3219e5813b15SDmitry Baryshkov drive-strength = <2>; 3220e5813b15SDmitry Baryshkov bias-disable; 3221e5813b15SDmitry Baryshkov }; 3222e5813b15SDmitry Baryshkov }; 3223e5813b15SDmitry Baryshkov 3224e5813b15SDmitry Baryshkov qup_i2c7_default: qup-i2c7-default { 3225e5813b15SDmitry Baryshkov mux { 3226e5813b15SDmitry Baryshkov pins = "gpio20", "gpio21"; 3227e5813b15SDmitry Baryshkov function = "qup7"; 3228e5813b15SDmitry Baryshkov }; 3229e5813b15SDmitry Baryshkov 3230e5813b15SDmitry Baryshkov config { 3231e5813b15SDmitry Baryshkov pins = "gpio20", "gpio21"; 3232e5813b15SDmitry Baryshkov drive-strength = <2>; 3233e5813b15SDmitry Baryshkov bias-disable; 3234e5813b15SDmitry Baryshkov }; 3235e5813b15SDmitry Baryshkov }; 3236e5813b15SDmitry Baryshkov 3237e5813b15SDmitry Baryshkov qup_i2c8_default: qup-i2c8-default { 3238e5813b15SDmitry Baryshkov mux { 3239e5813b15SDmitry Baryshkov pins = "gpio24", "gpio25"; 3240e5813b15SDmitry Baryshkov function = "qup8"; 3241e5813b15SDmitry Baryshkov }; 3242e5813b15SDmitry Baryshkov 3243e5813b15SDmitry Baryshkov config { 3244e5813b15SDmitry Baryshkov pins = "gpio24", "gpio25"; 3245e5813b15SDmitry Baryshkov drive-strength = <2>; 3246e5813b15SDmitry Baryshkov bias-disable; 3247e5813b15SDmitry Baryshkov }; 3248e5813b15SDmitry Baryshkov }; 3249e5813b15SDmitry Baryshkov 3250e5813b15SDmitry Baryshkov qup_i2c9_default: qup-i2c9-default { 3251e5813b15SDmitry Baryshkov mux { 3252e5813b15SDmitry Baryshkov pins = "gpio125", "gpio126"; 3253e5813b15SDmitry Baryshkov function = "qup9"; 3254e5813b15SDmitry Baryshkov }; 3255e5813b15SDmitry Baryshkov 3256e5813b15SDmitry Baryshkov config { 3257e5813b15SDmitry Baryshkov pins = "gpio125", "gpio126"; 3258e5813b15SDmitry Baryshkov drive-strength = <2>; 3259e5813b15SDmitry Baryshkov bias-disable; 3260e5813b15SDmitry Baryshkov }; 3261e5813b15SDmitry Baryshkov }; 3262e5813b15SDmitry Baryshkov 3263e5813b15SDmitry Baryshkov qup_i2c10_default: qup-i2c10-default { 3264e5813b15SDmitry Baryshkov mux { 3265e5813b15SDmitry Baryshkov pins = "gpio129", "gpio130"; 3266e5813b15SDmitry Baryshkov function = "qup10"; 3267e5813b15SDmitry Baryshkov }; 3268e5813b15SDmitry Baryshkov 3269e5813b15SDmitry Baryshkov config { 3270e5813b15SDmitry Baryshkov pins = "gpio129", "gpio130"; 3271e5813b15SDmitry Baryshkov drive-strength = <2>; 3272e5813b15SDmitry Baryshkov bias-disable; 3273e5813b15SDmitry Baryshkov }; 3274e5813b15SDmitry Baryshkov }; 3275e5813b15SDmitry Baryshkov 3276e5813b15SDmitry Baryshkov qup_i2c11_default: qup-i2c11-default { 3277e5813b15SDmitry Baryshkov mux { 3278e5813b15SDmitry Baryshkov pins = "gpio60", "gpio61"; 3279e5813b15SDmitry Baryshkov function = "qup11"; 3280e5813b15SDmitry Baryshkov }; 3281e5813b15SDmitry Baryshkov 3282e5813b15SDmitry Baryshkov config { 3283e5813b15SDmitry Baryshkov pins = "gpio60", "gpio61"; 3284e5813b15SDmitry Baryshkov drive-strength = <2>; 3285e5813b15SDmitry Baryshkov bias-disable; 3286e5813b15SDmitry Baryshkov }; 3287e5813b15SDmitry Baryshkov }; 3288e5813b15SDmitry Baryshkov 3289e5813b15SDmitry Baryshkov qup_i2c12_default: qup-i2c12-default { 3290e5813b15SDmitry Baryshkov mux { 3291e5813b15SDmitry Baryshkov pins = "gpio32", "gpio33"; 3292e5813b15SDmitry Baryshkov function = "qup12"; 3293e5813b15SDmitry Baryshkov }; 3294e5813b15SDmitry Baryshkov 3295e5813b15SDmitry Baryshkov config { 3296e5813b15SDmitry Baryshkov pins = "gpio32", "gpio33"; 3297e5813b15SDmitry Baryshkov drive-strength = <2>; 3298e5813b15SDmitry Baryshkov bias-disable; 3299e5813b15SDmitry Baryshkov }; 3300e5813b15SDmitry Baryshkov }; 3301e5813b15SDmitry Baryshkov 3302e5813b15SDmitry Baryshkov qup_i2c13_default: qup-i2c13-default { 3303e5813b15SDmitry Baryshkov mux { 3304e5813b15SDmitry Baryshkov pins = "gpio36", "gpio37"; 3305e5813b15SDmitry Baryshkov function = "qup13"; 3306e5813b15SDmitry Baryshkov }; 3307e5813b15SDmitry Baryshkov 3308e5813b15SDmitry Baryshkov config { 3309e5813b15SDmitry Baryshkov pins = "gpio36", "gpio37"; 3310e5813b15SDmitry Baryshkov drive-strength = <2>; 3311e5813b15SDmitry Baryshkov bias-disable; 3312e5813b15SDmitry Baryshkov }; 3313e5813b15SDmitry Baryshkov }; 3314e5813b15SDmitry Baryshkov 3315e5813b15SDmitry Baryshkov qup_i2c14_default: qup-i2c14-default { 3316e5813b15SDmitry Baryshkov mux { 3317e5813b15SDmitry Baryshkov pins = "gpio40", "gpio41"; 3318e5813b15SDmitry Baryshkov function = "qup14"; 3319e5813b15SDmitry Baryshkov }; 3320e5813b15SDmitry Baryshkov 3321e5813b15SDmitry Baryshkov config { 3322e5813b15SDmitry Baryshkov pins = "gpio40", "gpio41"; 3323e5813b15SDmitry Baryshkov drive-strength = <2>; 3324e5813b15SDmitry Baryshkov bias-disable; 3325e5813b15SDmitry Baryshkov }; 3326e5813b15SDmitry Baryshkov }; 3327e5813b15SDmitry Baryshkov 3328e5813b15SDmitry Baryshkov qup_i2c15_default: qup-i2c15-default { 3329e5813b15SDmitry Baryshkov mux { 3330e5813b15SDmitry Baryshkov pins = "gpio44", "gpio45"; 3331e5813b15SDmitry Baryshkov function = "qup15"; 3332e5813b15SDmitry Baryshkov }; 3333e5813b15SDmitry Baryshkov 3334e5813b15SDmitry Baryshkov config { 3335e5813b15SDmitry Baryshkov pins = "gpio44", "gpio45"; 3336e5813b15SDmitry Baryshkov drive-strength = <2>; 3337e5813b15SDmitry Baryshkov bias-disable; 3338e5813b15SDmitry Baryshkov }; 3339e5813b15SDmitry Baryshkov }; 3340e5813b15SDmitry Baryshkov 3341e5813b15SDmitry Baryshkov qup_i2c16_default: qup-i2c16-default { 3342e5813b15SDmitry Baryshkov mux { 3343e5813b15SDmitry Baryshkov pins = "gpio48", "gpio49"; 3344e5813b15SDmitry Baryshkov function = "qup16"; 3345e5813b15SDmitry Baryshkov }; 3346e5813b15SDmitry Baryshkov 3347e5813b15SDmitry Baryshkov config { 3348e5813b15SDmitry Baryshkov pins = "gpio48", "gpio49"; 3349e5813b15SDmitry Baryshkov drive-strength = <2>; 3350e5813b15SDmitry Baryshkov bias-disable; 3351e5813b15SDmitry Baryshkov }; 3352e5813b15SDmitry Baryshkov }; 3353e5813b15SDmitry Baryshkov 3354e5813b15SDmitry Baryshkov qup_i2c17_default: qup-i2c17-default { 3355e5813b15SDmitry Baryshkov mux { 3356e5813b15SDmitry Baryshkov pins = "gpio52", "gpio53"; 3357e5813b15SDmitry Baryshkov function = "qup17"; 3358e5813b15SDmitry Baryshkov }; 3359e5813b15SDmitry Baryshkov 3360e5813b15SDmitry Baryshkov config { 3361e5813b15SDmitry Baryshkov pins = "gpio52", "gpio53"; 3362e5813b15SDmitry Baryshkov drive-strength = <2>; 3363e5813b15SDmitry Baryshkov bias-disable; 3364e5813b15SDmitry Baryshkov }; 3365e5813b15SDmitry Baryshkov }; 3366e5813b15SDmitry Baryshkov 3367e5813b15SDmitry Baryshkov qup_i2c18_default: qup-i2c18-default { 3368e5813b15SDmitry Baryshkov mux { 3369e5813b15SDmitry Baryshkov pins = "gpio56", "gpio57"; 3370e5813b15SDmitry Baryshkov function = "qup18"; 3371e5813b15SDmitry Baryshkov }; 3372e5813b15SDmitry Baryshkov 3373e5813b15SDmitry Baryshkov config { 3374e5813b15SDmitry Baryshkov pins = "gpio56", "gpio57"; 3375e5813b15SDmitry Baryshkov drive-strength = <2>; 3376e5813b15SDmitry Baryshkov bias-disable; 3377e5813b15SDmitry Baryshkov }; 3378e5813b15SDmitry Baryshkov }; 3379e5813b15SDmitry Baryshkov 3380e5813b15SDmitry Baryshkov qup_i2c19_default: qup-i2c19-default { 3381e5813b15SDmitry Baryshkov mux { 3382e5813b15SDmitry Baryshkov pins = "gpio0", "gpio1"; 3383e5813b15SDmitry Baryshkov function = "qup19"; 3384e5813b15SDmitry Baryshkov }; 3385e5813b15SDmitry Baryshkov 3386e5813b15SDmitry Baryshkov config { 3387e5813b15SDmitry Baryshkov pins = "gpio0", "gpio1"; 3388e5813b15SDmitry Baryshkov drive-strength = <2>; 3389e5813b15SDmitry Baryshkov bias-disable; 3390e5813b15SDmitry Baryshkov }; 3391e5813b15SDmitry Baryshkov }; 3392e5813b15SDmitry Baryshkov 3393c88f9eccSDmitry Baryshkov qup_spi0_cs: qup-spi0-cs { 3394c88f9eccSDmitry Baryshkov pins = "gpio31"; 3395e5813b15SDmitry Baryshkov function = "qup0"; 3396e5813b15SDmitry Baryshkov }; 3397e5813b15SDmitry Baryshkov 3398eb97ccbbSDmitry Baryshkov qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3399eb97ccbbSDmitry Baryshkov pins = "gpio31"; 3400eb97ccbbSDmitry Baryshkov function = "gpio"; 3401eb97ccbbSDmitry Baryshkov }; 3402eb97ccbbSDmitry Baryshkov 3403c88f9eccSDmitry Baryshkov qup_spi0_data_clk: qup-spi0-data-clk { 3404c88f9eccSDmitry Baryshkov pins = "gpio28", "gpio29", 3405c88f9eccSDmitry Baryshkov "gpio30"; 3406c88f9eccSDmitry Baryshkov function = "qup0"; 3407c88f9eccSDmitry Baryshkov }; 3408c88f9eccSDmitry Baryshkov 3409c88f9eccSDmitry Baryshkov qup_spi1_cs: qup-spi1-cs { 3410c88f9eccSDmitry Baryshkov pins = "gpio7"; 3411e5813b15SDmitry Baryshkov function = "qup1"; 3412e5813b15SDmitry Baryshkov }; 3413e5813b15SDmitry Baryshkov 3414eb97ccbbSDmitry Baryshkov qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3415eb97ccbbSDmitry Baryshkov pins = "gpio7"; 3416eb97ccbbSDmitry Baryshkov function = "gpio"; 3417eb97ccbbSDmitry Baryshkov }; 3418eb97ccbbSDmitry Baryshkov 3419c88f9eccSDmitry Baryshkov qup_spi1_data_clk: qup-spi1-data-clk { 3420c88f9eccSDmitry Baryshkov pins = "gpio4", "gpio5", 3421c88f9eccSDmitry Baryshkov "gpio6"; 3422c88f9eccSDmitry Baryshkov function = "qup1"; 3423c88f9eccSDmitry Baryshkov }; 3424c88f9eccSDmitry Baryshkov 3425c88f9eccSDmitry Baryshkov qup_spi2_cs: qup-spi2-cs { 3426c88f9eccSDmitry Baryshkov pins = "gpio118"; 3427e5813b15SDmitry Baryshkov function = "qup2"; 3428e5813b15SDmitry Baryshkov }; 3429e5813b15SDmitry Baryshkov 3430eb97ccbbSDmitry Baryshkov qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3431eb97ccbbSDmitry Baryshkov pins = "gpio118"; 3432eb97ccbbSDmitry Baryshkov function = "gpio"; 3433eb97ccbbSDmitry Baryshkov }; 3434eb97ccbbSDmitry Baryshkov 3435c88f9eccSDmitry Baryshkov qup_spi2_data_clk: qup-spi2-data-clk { 3436c88f9eccSDmitry Baryshkov pins = "gpio115", "gpio116", 3437c88f9eccSDmitry Baryshkov "gpio117"; 3438c88f9eccSDmitry Baryshkov function = "qup2"; 3439c88f9eccSDmitry Baryshkov }; 3440c88f9eccSDmitry Baryshkov 3441c88f9eccSDmitry Baryshkov qup_spi3_cs: qup-spi3-cs { 3442c88f9eccSDmitry Baryshkov pins = "gpio122"; 3443e5813b15SDmitry Baryshkov function = "qup3"; 3444e5813b15SDmitry Baryshkov }; 3445e5813b15SDmitry Baryshkov 3446eb97ccbbSDmitry Baryshkov qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3447eb97ccbbSDmitry Baryshkov pins = "gpio122"; 3448eb97ccbbSDmitry Baryshkov function = "gpio"; 3449eb97ccbbSDmitry Baryshkov }; 3450eb97ccbbSDmitry Baryshkov 3451c88f9eccSDmitry Baryshkov qup_spi3_data_clk: qup-spi3-data-clk { 3452c88f9eccSDmitry Baryshkov pins = "gpio119", "gpio120", 3453c88f9eccSDmitry Baryshkov "gpio121"; 3454c88f9eccSDmitry Baryshkov function = "qup3"; 3455c88f9eccSDmitry Baryshkov }; 3456c88f9eccSDmitry Baryshkov 3457c88f9eccSDmitry Baryshkov qup_spi4_cs: qup-spi4-cs { 3458c88f9eccSDmitry Baryshkov pins = "gpio11"; 3459e5813b15SDmitry Baryshkov function = "qup4"; 3460e5813b15SDmitry Baryshkov }; 3461e5813b15SDmitry Baryshkov 3462eb97ccbbSDmitry Baryshkov qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3463eb97ccbbSDmitry Baryshkov pins = "gpio11"; 3464eb97ccbbSDmitry Baryshkov function = "gpio"; 3465eb97ccbbSDmitry Baryshkov }; 3466eb97ccbbSDmitry Baryshkov 3467c88f9eccSDmitry Baryshkov qup_spi4_data_clk: qup-spi4-data-clk { 3468c88f9eccSDmitry Baryshkov pins = "gpio8", "gpio9", 3469c88f9eccSDmitry Baryshkov "gpio10"; 3470c88f9eccSDmitry Baryshkov function = "qup4"; 3471c88f9eccSDmitry Baryshkov }; 3472c88f9eccSDmitry Baryshkov 3473c88f9eccSDmitry Baryshkov qup_spi5_cs: qup-spi5-cs { 3474c88f9eccSDmitry Baryshkov pins = "gpio15"; 3475e5813b15SDmitry Baryshkov function = "qup5"; 3476e5813b15SDmitry Baryshkov }; 3477e5813b15SDmitry Baryshkov 3478eb97ccbbSDmitry Baryshkov qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3479eb97ccbbSDmitry Baryshkov pins = "gpio15"; 3480eb97ccbbSDmitry Baryshkov function = "gpio"; 3481eb97ccbbSDmitry Baryshkov }; 3482eb97ccbbSDmitry Baryshkov 3483c88f9eccSDmitry Baryshkov qup_spi5_data_clk: qup-spi5-data-clk { 3484c88f9eccSDmitry Baryshkov pins = "gpio12", "gpio13", 3485c88f9eccSDmitry Baryshkov "gpio14"; 3486c88f9eccSDmitry Baryshkov function = "qup5"; 3487c88f9eccSDmitry Baryshkov }; 3488c88f9eccSDmitry Baryshkov 3489c88f9eccSDmitry Baryshkov qup_spi6_cs: qup-spi6-cs { 3490c88f9eccSDmitry Baryshkov pins = "gpio19"; 3491e5813b15SDmitry Baryshkov function = "qup6"; 3492e5813b15SDmitry Baryshkov }; 3493e5813b15SDmitry Baryshkov 3494eb97ccbbSDmitry Baryshkov qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3495eb97ccbbSDmitry Baryshkov pins = "gpio19"; 3496eb97ccbbSDmitry Baryshkov function = "gpio"; 3497eb97ccbbSDmitry Baryshkov }; 3498eb97ccbbSDmitry Baryshkov 3499c88f9eccSDmitry Baryshkov qup_spi6_data_clk: qup-spi6-data-clk { 3500c88f9eccSDmitry Baryshkov pins = "gpio16", "gpio17", 3501c88f9eccSDmitry Baryshkov "gpio18"; 3502c88f9eccSDmitry Baryshkov function = "qup6"; 3503c88f9eccSDmitry Baryshkov }; 3504c88f9eccSDmitry Baryshkov 3505c88f9eccSDmitry Baryshkov qup_spi7_cs: qup-spi7-cs { 3506c88f9eccSDmitry Baryshkov pins = "gpio23"; 3507e5813b15SDmitry Baryshkov function = "qup7"; 3508e5813b15SDmitry Baryshkov }; 3509e5813b15SDmitry Baryshkov 3510eb97ccbbSDmitry Baryshkov qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3511eb97ccbbSDmitry Baryshkov pins = "gpio23"; 3512eb97ccbbSDmitry Baryshkov function = "gpio"; 3513eb97ccbbSDmitry Baryshkov }; 3514eb97ccbbSDmitry Baryshkov 3515c88f9eccSDmitry Baryshkov qup_spi7_data_clk: qup-spi7-data-clk { 3516c88f9eccSDmitry Baryshkov pins = "gpio20", "gpio21", 3517c88f9eccSDmitry Baryshkov "gpio22"; 3518c88f9eccSDmitry Baryshkov function = "qup7"; 3519c88f9eccSDmitry Baryshkov }; 3520c88f9eccSDmitry Baryshkov 3521c88f9eccSDmitry Baryshkov qup_spi8_cs: qup-spi8-cs { 3522c88f9eccSDmitry Baryshkov pins = "gpio27"; 3523e5813b15SDmitry Baryshkov function = "qup8"; 3524e5813b15SDmitry Baryshkov }; 3525e5813b15SDmitry Baryshkov 3526eb97ccbbSDmitry Baryshkov qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3527eb97ccbbSDmitry Baryshkov pins = "gpio27"; 3528eb97ccbbSDmitry Baryshkov function = "gpio"; 3529eb97ccbbSDmitry Baryshkov }; 3530eb97ccbbSDmitry Baryshkov 3531c88f9eccSDmitry Baryshkov qup_spi8_data_clk: qup-spi8-data-clk { 3532c88f9eccSDmitry Baryshkov pins = "gpio24", "gpio25", 3533c88f9eccSDmitry Baryshkov "gpio26"; 3534c88f9eccSDmitry Baryshkov function = "qup8"; 3535c88f9eccSDmitry Baryshkov }; 3536c88f9eccSDmitry Baryshkov 3537c88f9eccSDmitry Baryshkov qup_spi9_cs: qup-spi9-cs { 3538c88f9eccSDmitry Baryshkov pins = "gpio128"; 3539e5813b15SDmitry Baryshkov function = "qup9"; 3540e5813b15SDmitry Baryshkov }; 3541e5813b15SDmitry Baryshkov 3542eb97ccbbSDmitry Baryshkov qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3543eb97ccbbSDmitry Baryshkov pins = "gpio128"; 3544eb97ccbbSDmitry Baryshkov function = "gpio"; 3545eb97ccbbSDmitry Baryshkov }; 3546eb97ccbbSDmitry Baryshkov 3547c88f9eccSDmitry Baryshkov qup_spi9_data_clk: qup-spi9-data-clk { 3548c88f9eccSDmitry Baryshkov pins = "gpio125", "gpio126", 3549c88f9eccSDmitry Baryshkov "gpio127"; 3550c88f9eccSDmitry Baryshkov function = "qup9"; 3551c88f9eccSDmitry Baryshkov }; 3552c88f9eccSDmitry Baryshkov 3553c88f9eccSDmitry Baryshkov qup_spi10_cs: qup-spi10-cs { 3554c88f9eccSDmitry Baryshkov pins = "gpio132"; 3555e5813b15SDmitry Baryshkov function = "qup10"; 3556e5813b15SDmitry Baryshkov }; 3557e5813b15SDmitry Baryshkov 3558eb97ccbbSDmitry Baryshkov qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3559eb97ccbbSDmitry Baryshkov pins = "gpio132"; 3560eb97ccbbSDmitry Baryshkov function = "gpio"; 3561eb97ccbbSDmitry Baryshkov }; 3562eb97ccbbSDmitry Baryshkov 3563c88f9eccSDmitry Baryshkov qup_spi10_data_clk: qup-spi10-data-clk { 3564c88f9eccSDmitry Baryshkov pins = "gpio129", "gpio130", 3565c88f9eccSDmitry Baryshkov "gpio131"; 3566c88f9eccSDmitry Baryshkov function = "qup10"; 3567c88f9eccSDmitry Baryshkov }; 3568c88f9eccSDmitry Baryshkov 3569c88f9eccSDmitry Baryshkov qup_spi11_cs: qup-spi11-cs { 3570c88f9eccSDmitry Baryshkov pins = "gpio63"; 3571e5813b15SDmitry Baryshkov function = "qup11"; 3572e5813b15SDmitry Baryshkov }; 3573e5813b15SDmitry Baryshkov 3574eb97ccbbSDmitry Baryshkov qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3575eb97ccbbSDmitry Baryshkov pins = "gpio63"; 3576eb97ccbbSDmitry Baryshkov function = "gpio"; 3577eb97ccbbSDmitry Baryshkov }; 3578eb97ccbbSDmitry Baryshkov 3579c88f9eccSDmitry Baryshkov qup_spi11_data_clk: qup-spi11-data-clk { 3580c88f9eccSDmitry Baryshkov pins = "gpio60", "gpio61", 3581c88f9eccSDmitry Baryshkov "gpio62"; 3582c88f9eccSDmitry Baryshkov function = "qup11"; 3583c88f9eccSDmitry Baryshkov }; 3584c88f9eccSDmitry Baryshkov 3585c88f9eccSDmitry Baryshkov qup_spi12_cs: qup-spi12-cs { 3586c88f9eccSDmitry Baryshkov pins = "gpio35"; 3587e5813b15SDmitry Baryshkov function = "qup12"; 3588e5813b15SDmitry Baryshkov }; 3589e5813b15SDmitry Baryshkov 3590eb97ccbbSDmitry Baryshkov qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3591eb97ccbbSDmitry Baryshkov pins = "gpio35"; 3592eb97ccbbSDmitry Baryshkov function = "gpio"; 3593eb97ccbbSDmitry Baryshkov }; 3594eb97ccbbSDmitry Baryshkov 3595c88f9eccSDmitry Baryshkov qup_spi12_data_clk: qup-spi12-data-clk { 3596c88f9eccSDmitry Baryshkov pins = "gpio32", "gpio33", 3597c88f9eccSDmitry Baryshkov "gpio34"; 3598c88f9eccSDmitry Baryshkov function = "qup12"; 3599c88f9eccSDmitry Baryshkov }; 3600c88f9eccSDmitry Baryshkov 3601c88f9eccSDmitry Baryshkov qup_spi13_cs: qup-spi13-cs { 3602c88f9eccSDmitry Baryshkov pins = "gpio39"; 3603e5813b15SDmitry Baryshkov function = "qup13"; 3604e5813b15SDmitry Baryshkov }; 3605e5813b15SDmitry Baryshkov 3606eb97ccbbSDmitry Baryshkov qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3607eb97ccbbSDmitry Baryshkov pins = "gpio39"; 3608eb97ccbbSDmitry Baryshkov function = "gpio"; 3609eb97ccbbSDmitry Baryshkov }; 3610eb97ccbbSDmitry Baryshkov 3611c88f9eccSDmitry Baryshkov qup_spi13_data_clk: qup-spi13-data-clk { 3612c88f9eccSDmitry Baryshkov pins = "gpio36", "gpio37", 3613c88f9eccSDmitry Baryshkov "gpio38"; 3614c88f9eccSDmitry Baryshkov function = "qup13"; 3615c88f9eccSDmitry Baryshkov }; 3616c88f9eccSDmitry Baryshkov 3617c88f9eccSDmitry Baryshkov qup_spi14_cs: qup-spi14-cs { 3618c88f9eccSDmitry Baryshkov pins = "gpio43"; 3619e5813b15SDmitry Baryshkov function = "qup14"; 3620e5813b15SDmitry Baryshkov }; 3621e5813b15SDmitry Baryshkov 3622eb97ccbbSDmitry Baryshkov qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3623eb97ccbbSDmitry Baryshkov pins = "gpio43"; 3624eb97ccbbSDmitry Baryshkov function = "gpio"; 3625eb97ccbbSDmitry Baryshkov }; 3626eb97ccbbSDmitry Baryshkov 3627c88f9eccSDmitry Baryshkov qup_spi14_data_clk: qup-spi14-data-clk { 3628c88f9eccSDmitry Baryshkov pins = "gpio40", "gpio41", 3629c88f9eccSDmitry Baryshkov "gpio42"; 3630c88f9eccSDmitry Baryshkov function = "qup14"; 3631c88f9eccSDmitry Baryshkov }; 3632c88f9eccSDmitry Baryshkov 3633c88f9eccSDmitry Baryshkov qup_spi15_cs: qup-spi15-cs { 3634c88f9eccSDmitry Baryshkov pins = "gpio47"; 3635e5813b15SDmitry Baryshkov function = "qup15"; 3636e5813b15SDmitry Baryshkov }; 3637e5813b15SDmitry Baryshkov 3638eb97ccbbSDmitry Baryshkov qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3639eb97ccbbSDmitry Baryshkov pins = "gpio47"; 3640eb97ccbbSDmitry Baryshkov function = "gpio"; 3641eb97ccbbSDmitry Baryshkov }; 3642eb97ccbbSDmitry Baryshkov 3643c88f9eccSDmitry Baryshkov qup_spi15_data_clk: qup-spi15-data-clk { 3644c88f9eccSDmitry Baryshkov pins = "gpio44", "gpio45", 3645c88f9eccSDmitry Baryshkov "gpio46"; 3646c88f9eccSDmitry Baryshkov function = "qup15"; 3647c88f9eccSDmitry Baryshkov }; 3648c88f9eccSDmitry Baryshkov 3649c88f9eccSDmitry Baryshkov qup_spi16_cs: qup-spi16-cs { 3650c88f9eccSDmitry Baryshkov pins = "gpio51"; 3651e5813b15SDmitry Baryshkov function = "qup16"; 3652e5813b15SDmitry Baryshkov }; 3653e5813b15SDmitry Baryshkov 3654eb97ccbbSDmitry Baryshkov qup_spi16_cs_gpio: qup-spi16-cs-gpio { 3655eb97ccbbSDmitry Baryshkov pins = "gpio51"; 3656eb97ccbbSDmitry Baryshkov function = "gpio"; 3657eb97ccbbSDmitry Baryshkov }; 3658eb97ccbbSDmitry Baryshkov 3659c88f9eccSDmitry Baryshkov qup_spi16_data_clk: qup-spi16-data-clk { 3660c88f9eccSDmitry Baryshkov pins = "gpio48", "gpio49", 3661c88f9eccSDmitry Baryshkov "gpio50"; 3662c88f9eccSDmitry Baryshkov function = "qup16"; 3663c88f9eccSDmitry Baryshkov }; 3664c88f9eccSDmitry Baryshkov 3665c88f9eccSDmitry Baryshkov qup_spi17_cs: qup-spi17-cs { 3666c88f9eccSDmitry Baryshkov pins = "gpio55"; 3667e5813b15SDmitry Baryshkov function = "qup17"; 3668e5813b15SDmitry Baryshkov }; 3669e5813b15SDmitry Baryshkov 3670eb97ccbbSDmitry Baryshkov qup_spi17_cs_gpio: qup-spi17-cs-gpio { 3671eb97ccbbSDmitry Baryshkov pins = "gpio55"; 3672eb97ccbbSDmitry Baryshkov function = "gpio"; 3673eb97ccbbSDmitry Baryshkov }; 3674eb97ccbbSDmitry Baryshkov 3675c88f9eccSDmitry Baryshkov qup_spi17_data_clk: qup-spi17-data-clk { 3676c88f9eccSDmitry Baryshkov pins = "gpio52", "gpio53", 3677c88f9eccSDmitry Baryshkov "gpio54"; 3678c88f9eccSDmitry Baryshkov function = "qup17"; 3679c88f9eccSDmitry Baryshkov }; 3680c88f9eccSDmitry Baryshkov 3681c88f9eccSDmitry Baryshkov qup_spi18_cs: qup-spi18-cs { 3682c88f9eccSDmitry Baryshkov pins = "gpio59"; 3683e5813b15SDmitry Baryshkov function = "qup18"; 3684e5813b15SDmitry Baryshkov }; 3685e5813b15SDmitry Baryshkov 3686eb97ccbbSDmitry Baryshkov qup_spi18_cs_gpio: qup-spi18-cs-gpio { 3687eb97ccbbSDmitry Baryshkov pins = "gpio59"; 3688eb97ccbbSDmitry Baryshkov function = "gpio"; 3689eb97ccbbSDmitry Baryshkov }; 3690eb97ccbbSDmitry Baryshkov 3691c88f9eccSDmitry Baryshkov qup_spi18_data_clk: qup-spi18-data-clk { 3692c88f9eccSDmitry Baryshkov pins = "gpio56", "gpio57", 3693c88f9eccSDmitry Baryshkov "gpio58"; 3694c88f9eccSDmitry Baryshkov function = "qup18"; 3695c88f9eccSDmitry Baryshkov }; 3696c88f9eccSDmitry Baryshkov 3697c88f9eccSDmitry Baryshkov qup_spi19_cs: qup-spi19-cs { 3698c88f9eccSDmitry Baryshkov pins = "gpio3"; 3699c88f9eccSDmitry Baryshkov function = "qup19"; 3700c88f9eccSDmitry Baryshkov }; 3701c88f9eccSDmitry Baryshkov 3702eb97ccbbSDmitry Baryshkov qup_spi19_cs_gpio: qup-spi19-cs-gpio { 3703eb97ccbbSDmitry Baryshkov pins = "gpio3"; 3704eb97ccbbSDmitry Baryshkov function = "gpio"; 3705eb97ccbbSDmitry Baryshkov }; 3706eb97ccbbSDmitry Baryshkov 3707c88f9eccSDmitry Baryshkov qup_spi19_data_clk: qup-spi19-data-clk { 3708e5813b15SDmitry Baryshkov pins = "gpio0", "gpio1", 3709c88f9eccSDmitry Baryshkov "gpio2"; 3710e5813b15SDmitry Baryshkov function = "qup19"; 3711e5813b15SDmitry Baryshkov }; 3712e5813b15SDmitry Baryshkov 371308a9ae2dSDmitry Baryshkov qup_uart2_default: qup-uart2-default { 371408a9ae2dSDmitry Baryshkov mux { 371508a9ae2dSDmitry Baryshkov pins = "gpio117", "gpio118"; 371608a9ae2dSDmitry Baryshkov function = "qup2"; 371708a9ae2dSDmitry Baryshkov }; 371808a9ae2dSDmitry Baryshkov }; 371908a9ae2dSDmitry Baryshkov 372008a9ae2dSDmitry Baryshkov qup_uart6_default: qup-uart6-default { 372108a9ae2dSDmitry Baryshkov mux { 372208a9ae2dSDmitry Baryshkov pins = "gpio16", "gpio17", 372308a9ae2dSDmitry Baryshkov "gpio18", "gpio19"; 372408a9ae2dSDmitry Baryshkov function = "qup6"; 372508a9ae2dSDmitry Baryshkov }; 372608a9ae2dSDmitry Baryshkov }; 372708a9ae2dSDmitry Baryshkov 3728bb1dfb4dSManivannan Sadhasivam qup_uart12_default: qup-uart12-default { 3729bb1dfb4dSManivannan Sadhasivam mux { 3730bb1dfb4dSManivannan Sadhasivam pins = "gpio34", "gpio35"; 3731bb1dfb4dSManivannan Sadhasivam function = "qup12"; 3732bb1dfb4dSManivannan Sadhasivam }; 3733bb1dfb4dSManivannan Sadhasivam }; 373408a9ae2dSDmitry Baryshkov 373508a9ae2dSDmitry Baryshkov qup_uart17_default: qup-uart17-default { 373608a9ae2dSDmitry Baryshkov mux { 373708a9ae2dSDmitry Baryshkov pins = "gpio52", "gpio53", 373808a9ae2dSDmitry Baryshkov "gpio54", "gpio55"; 373908a9ae2dSDmitry Baryshkov function = "qup17"; 374008a9ae2dSDmitry Baryshkov }; 374108a9ae2dSDmitry Baryshkov }; 374208a9ae2dSDmitry Baryshkov 374308a9ae2dSDmitry Baryshkov qup_uart18_default: qup-uart18-default { 374408a9ae2dSDmitry Baryshkov mux { 374508a9ae2dSDmitry Baryshkov pins = "gpio58", "gpio59"; 374608a9ae2dSDmitry Baryshkov function = "qup18"; 374708a9ae2dSDmitry Baryshkov }; 374808a9ae2dSDmitry Baryshkov }; 3749b657d372SSrinivas Kandagatla 3750b657d372SSrinivas Kandagatla tert_mi2s_active: tert-mi2s-active { 3751b657d372SSrinivas Kandagatla sck { 3752b657d372SSrinivas Kandagatla pins = "gpio133"; 3753b657d372SSrinivas Kandagatla function = "mi2s2_sck"; 3754b657d372SSrinivas Kandagatla drive-strength = <8>; 3755b657d372SSrinivas Kandagatla bias-disable; 3756b657d372SSrinivas Kandagatla }; 3757b657d372SSrinivas Kandagatla 3758b657d372SSrinivas Kandagatla data0 { 3759b657d372SSrinivas Kandagatla pins = "gpio134"; 3760b657d372SSrinivas Kandagatla function = "mi2s2_data0"; 3761b657d372SSrinivas Kandagatla drive-strength = <8>; 3762b657d372SSrinivas Kandagatla bias-disable; 3763b657d372SSrinivas Kandagatla output-high; 3764b657d372SSrinivas Kandagatla }; 3765b657d372SSrinivas Kandagatla 3766b657d372SSrinivas Kandagatla ws { 3767b657d372SSrinivas Kandagatla pins = "gpio135"; 3768b657d372SSrinivas Kandagatla function = "mi2s2_ws"; 3769b657d372SSrinivas Kandagatla drive-strength = <8>; 3770b657d372SSrinivas Kandagatla output-high; 3771b657d372SSrinivas Kandagatla }; 3772b657d372SSrinivas Kandagatla }; 37738eaa6501SKonrad Dybcio 37748eaa6501SKonrad Dybcio sdc2_sleep_state: sdc2-sleep { 37758eaa6501SKonrad Dybcio clk { 37768eaa6501SKonrad Dybcio pins = "sdc2_clk"; 37778eaa6501SKonrad Dybcio drive-strength = <2>; 37788eaa6501SKonrad Dybcio bias-disable; 37798eaa6501SKonrad Dybcio }; 37808eaa6501SKonrad Dybcio 37818eaa6501SKonrad Dybcio cmd { 37828eaa6501SKonrad Dybcio pins = "sdc2_cmd"; 37838eaa6501SKonrad Dybcio drive-strength = <2>; 37848eaa6501SKonrad Dybcio bias-pull-up; 37858eaa6501SKonrad Dybcio }; 37868eaa6501SKonrad Dybcio 37878eaa6501SKonrad Dybcio data { 37888eaa6501SKonrad Dybcio pins = "sdc2_data"; 37898eaa6501SKonrad Dybcio drive-strength = <2>; 37908eaa6501SKonrad Dybcio bias-pull-up; 37918eaa6501SKonrad Dybcio }; 37928eaa6501SKonrad Dybcio }; 379313e948a3SKonrad Dybcio 379413e948a3SKonrad Dybcio pcie0_default_state: pcie0-default { 379513e948a3SKonrad Dybcio perst { 379613e948a3SKonrad Dybcio pins = "gpio79"; 379713e948a3SKonrad Dybcio function = "gpio"; 379813e948a3SKonrad Dybcio drive-strength = <2>; 379913e948a3SKonrad Dybcio bias-pull-down; 380013e948a3SKonrad Dybcio }; 380113e948a3SKonrad Dybcio 380213e948a3SKonrad Dybcio clkreq { 380313e948a3SKonrad Dybcio pins = "gpio80"; 380413e948a3SKonrad Dybcio function = "pci_e0"; 380513e948a3SKonrad Dybcio drive-strength = <2>; 380613e948a3SKonrad Dybcio bias-pull-up; 380713e948a3SKonrad Dybcio }; 380813e948a3SKonrad Dybcio 380913e948a3SKonrad Dybcio wake { 381013e948a3SKonrad Dybcio pins = "gpio81"; 381113e948a3SKonrad Dybcio function = "gpio"; 381213e948a3SKonrad Dybcio drive-strength = <2>; 381313e948a3SKonrad Dybcio bias-pull-up; 381413e948a3SKonrad Dybcio }; 381513e948a3SKonrad Dybcio }; 381613e948a3SKonrad Dybcio 381713e948a3SKonrad Dybcio pcie1_default_state: pcie1-default { 381813e948a3SKonrad Dybcio perst { 381913e948a3SKonrad Dybcio pins = "gpio82"; 382013e948a3SKonrad Dybcio function = "gpio"; 382113e948a3SKonrad Dybcio drive-strength = <2>; 382213e948a3SKonrad Dybcio bias-pull-down; 382313e948a3SKonrad Dybcio }; 382413e948a3SKonrad Dybcio 382513e948a3SKonrad Dybcio clkreq { 382613e948a3SKonrad Dybcio pins = "gpio83"; 382713e948a3SKonrad Dybcio function = "pci_e1"; 382813e948a3SKonrad Dybcio drive-strength = <2>; 382913e948a3SKonrad Dybcio bias-pull-up; 383013e948a3SKonrad Dybcio }; 383113e948a3SKonrad Dybcio 383213e948a3SKonrad Dybcio wake { 383313e948a3SKonrad Dybcio pins = "gpio84"; 383413e948a3SKonrad Dybcio function = "gpio"; 383513e948a3SKonrad Dybcio drive-strength = <2>; 383613e948a3SKonrad Dybcio bias-pull-up; 383713e948a3SKonrad Dybcio }; 383813e948a3SKonrad Dybcio }; 383913e948a3SKonrad Dybcio 384013e948a3SKonrad Dybcio pcie2_default_state: pcie2-default { 384113e948a3SKonrad Dybcio perst { 384213e948a3SKonrad Dybcio pins = "gpio85"; 384313e948a3SKonrad Dybcio function = "gpio"; 384413e948a3SKonrad Dybcio drive-strength = <2>; 384513e948a3SKonrad Dybcio bias-pull-down; 384613e948a3SKonrad Dybcio }; 384713e948a3SKonrad Dybcio 384813e948a3SKonrad Dybcio clkreq { 384913e948a3SKonrad Dybcio pins = "gpio86"; 385013e948a3SKonrad Dybcio function = "pci_e2"; 385113e948a3SKonrad Dybcio drive-strength = <2>; 385213e948a3SKonrad Dybcio bias-pull-up; 385313e948a3SKonrad Dybcio }; 385413e948a3SKonrad Dybcio 385513e948a3SKonrad Dybcio wake { 385613e948a3SKonrad Dybcio pins = "gpio87"; 385713e948a3SKonrad Dybcio function = "gpio"; 385813e948a3SKonrad Dybcio drive-strength = <2>; 385913e948a3SKonrad Dybcio bias-pull-up; 386013e948a3SKonrad Dybcio }; 386113e948a3SKonrad Dybcio }; 386216951b49SBjorn Andersson }; 386316951b49SBjorn Andersson 3864a89441fcSJonathan Marek apps_smmu: iommu@15000000 { 3865a89441fcSJonathan Marek compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 3866a89441fcSJonathan Marek reg = <0 0x15000000 0 0x100000>; 3867a89441fcSJonathan Marek #iommu-cells = <2>; 3868a89441fcSJonathan Marek #global-interrupts = <2>; 3869a89441fcSJonathan Marek interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3870a89441fcSJonathan Marek <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3871a89441fcSJonathan Marek <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3872a89441fcSJonathan Marek <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3873a89441fcSJonathan Marek <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3874a89441fcSJonathan Marek <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3875a89441fcSJonathan Marek <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3876a89441fcSJonathan Marek <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3877a89441fcSJonathan Marek <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3878a89441fcSJonathan Marek <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3879a89441fcSJonathan Marek <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3880a89441fcSJonathan Marek <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3881a89441fcSJonathan Marek <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3882a89441fcSJonathan Marek <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3883a89441fcSJonathan Marek <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3884a89441fcSJonathan Marek <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3885a89441fcSJonathan Marek <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3886a89441fcSJonathan Marek <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3887a89441fcSJonathan Marek <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3888a89441fcSJonathan Marek <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3889a89441fcSJonathan Marek <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3890a89441fcSJonathan Marek <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3891a89441fcSJonathan Marek <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3892a89441fcSJonathan Marek <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3893a89441fcSJonathan Marek <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3894a89441fcSJonathan Marek <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3895a89441fcSJonathan Marek <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3896a89441fcSJonathan Marek <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3897a89441fcSJonathan Marek <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3898a89441fcSJonathan Marek <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3899a89441fcSJonathan Marek <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3900a89441fcSJonathan Marek <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3901a89441fcSJonathan Marek <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3902a89441fcSJonathan Marek <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3903a89441fcSJonathan Marek <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3904a89441fcSJonathan Marek <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3905a89441fcSJonathan Marek <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3906a89441fcSJonathan Marek <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3907a89441fcSJonathan Marek <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3908a89441fcSJonathan Marek <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3909a89441fcSJonathan Marek <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3910a89441fcSJonathan Marek <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3911a89441fcSJonathan Marek <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3912a89441fcSJonathan Marek <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3913a89441fcSJonathan Marek <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3914a89441fcSJonathan Marek <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3915a89441fcSJonathan Marek <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3916a89441fcSJonathan Marek <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3917a89441fcSJonathan Marek <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3918a89441fcSJonathan Marek <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3919a89441fcSJonathan Marek <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3920a89441fcSJonathan Marek <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3921a89441fcSJonathan Marek <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3922a89441fcSJonathan Marek <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3923a89441fcSJonathan Marek <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3924a89441fcSJonathan Marek <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3925a89441fcSJonathan Marek <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3926a89441fcSJonathan Marek <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3927a89441fcSJonathan Marek <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3928a89441fcSJonathan Marek <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3929a89441fcSJonathan Marek <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3930a89441fcSJonathan Marek <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3931a89441fcSJonathan Marek <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3932a89441fcSJonathan Marek <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3933a89441fcSJonathan Marek <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3934a89441fcSJonathan Marek <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3935a89441fcSJonathan Marek <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3936a89441fcSJonathan Marek <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3937a89441fcSJonathan Marek <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3938a89441fcSJonathan Marek <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3939a89441fcSJonathan Marek <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3940a89441fcSJonathan Marek <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3941a89441fcSJonathan Marek <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3942a89441fcSJonathan Marek <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3943a89441fcSJonathan Marek <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3944a89441fcSJonathan Marek <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3945a89441fcSJonathan Marek <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3946a89441fcSJonathan Marek <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3947a89441fcSJonathan Marek <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3948a89441fcSJonathan Marek <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3949a89441fcSJonathan Marek <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3950a89441fcSJonathan Marek <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3951a89441fcSJonathan Marek <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3952a89441fcSJonathan Marek <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3953a89441fcSJonathan Marek <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3954a89441fcSJonathan Marek <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3955a89441fcSJonathan Marek <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3956a89441fcSJonathan Marek <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3957a89441fcSJonathan Marek <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3958a89441fcSJonathan Marek <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3959a89441fcSJonathan Marek <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3960a89441fcSJonathan Marek <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3961a89441fcSJonathan Marek <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3962a89441fcSJonathan Marek <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3963a89441fcSJonathan Marek <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3964a89441fcSJonathan Marek <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3965a89441fcSJonathan Marek <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3966a89441fcSJonathan Marek <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3967a89441fcSJonathan Marek }; 3968a89441fcSJonathan Marek 396923a89037SBjorn Andersson adsp: remoteproc@17300000 { 397023a89037SBjorn Andersson compatible = "qcom,sm8250-adsp-pas"; 397123a89037SBjorn Andersson reg = <0 0x17300000 0 0x100>; 397223a89037SBjorn Andersson 397323a89037SBjorn Andersson interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 397423a89037SBjorn Andersson <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 397523a89037SBjorn Andersson <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 397623a89037SBjorn Andersson <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 397723a89037SBjorn Andersson <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 397823a89037SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 397923a89037SBjorn Andersson "handover", "stop-ack"; 398023a89037SBjorn Andersson 398123a89037SBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>; 398223a89037SBjorn Andersson clock-names = "xo"; 398323a89037SBjorn Andersson 3984b74ee2d7SSibi Sankar power-domains = <&rpmhpd SM8250_LCX>, 398523a89037SBjorn Andersson <&rpmhpd SM8250_LMX>; 3986b74ee2d7SSibi Sankar power-domain-names = "lcx", "lmx"; 398723a89037SBjorn Andersson 398823a89037SBjorn Andersson memory-region = <&adsp_mem>; 398923a89037SBjorn Andersson 3990b74ee2d7SSibi Sankar qcom,qmp = <&aoss_qmp>; 3991b74ee2d7SSibi Sankar 399223a89037SBjorn Andersson qcom,smem-states = <&smp2p_adsp_out 0>; 399323a89037SBjorn Andersson qcom,smem-state-names = "stop"; 399423a89037SBjorn Andersson 399523a89037SBjorn Andersson status = "disabled"; 399623a89037SBjorn Andersson 399723a89037SBjorn Andersson glink-edge { 399823a89037SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 399923a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 400023a89037SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 400123a89037SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_LPASS 400223a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 400323a89037SBjorn Andersson 400423a89037SBjorn Andersson label = "lpass"; 400523a89037SBjorn Andersson qcom,remote-pid = <2>; 400625695808SJonathan Marek 400763e10791SSrinivas Kandagatla apr { 400863e10791SSrinivas Kandagatla compatible = "qcom,apr-v2"; 400963e10791SSrinivas Kandagatla qcom,glink-channels = "apr_audio_svc"; 401063e10791SSrinivas Kandagatla qcom,apr-domain = <APR_DOMAIN_ADSP>; 401163e10791SSrinivas Kandagatla #address-cells = <1>; 401263e10791SSrinivas Kandagatla #size-cells = <0>; 401363e10791SSrinivas Kandagatla 401463e10791SSrinivas Kandagatla apr-service@3 { 401563e10791SSrinivas Kandagatla reg = <APR_SVC_ADSP_CORE>; 401663e10791SSrinivas Kandagatla compatible = "qcom,q6core"; 401763e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 401863e10791SSrinivas Kandagatla }; 401963e10791SSrinivas Kandagatla 402063e10791SSrinivas Kandagatla q6afe: apr-service@4 { 402163e10791SSrinivas Kandagatla compatible = "qcom,q6afe"; 402263e10791SSrinivas Kandagatla reg = <APR_SVC_AFE>; 402363e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 402463e10791SSrinivas Kandagatla q6afedai: dais { 402563e10791SSrinivas Kandagatla compatible = "qcom,q6afe-dais"; 402663e10791SSrinivas Kandagatla #address-cells = <1>; 402763e10791SSrinivas Kandagatla #size-cells = <0>; 402863e10791SSrinivas Kandagatla #sound-dai-cells = <1>; 402963e10791SSrinivas Kandagatla }; 403063e10791SSrinivas Kandagatla 403163e10791SSrinivas Kandagatla q6afecc: cc { 403263e10791SSrinivas Kandagatla compatible = "qcom,q6afe-clocks"; 403363e10791SSrinivas Kandagatla #clock-cells = <2>; 403463e10791SSrinivas Kandagatla }; 403563e10791SSrinivas Kandagatla }; 403663e10791SSrinivas Kandagatla 403763e10791SSrinivas Kandagatla q6asm: apr-service@7 { 403863e10791SSrinivas Kandagatla compatible = "qcom,q6asm"; 403963e10791SSrinivas Kandagatla reg = <APR_SVC_ASM>; 404063e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 404163e10791SSrinivas Kandagatla q6asmdai: dais { 404263e10791SSrinivas Kandagatla compatible = "qcom,q6asm-dais"; 404363e10791SSrinivas Kandagatla #address-cells = <1>; 404463e10791SSrinivas Kandagatla #size-cells = <0>; 404563e10791SSrinivas Kandagatla #sound-dai-cells = <1>; 404663e10791SSrinivas Kandagatla iommus = <&apps_smmu 0x1801 0x0>; 404763e10791SSrinivas Kandagatla }; 404863e10791SSrinivas Kandagatla }; 404963e10791SSrinivas Kandagatla 405063e10791SSrinivas Kandagatla q6adm: apr-service@8 { 405163e10791SSrinivas Kandagatla compatible = "qcom,q6adm"; 405263e10791SSrinivas Kandagatla reg = <APR_SVC_ADM>; 405363e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 405463e10791SSrinivas Kandagatla q6routing: routing { 405563e10791SSrinivas Kandagatla compatible = "qcom,q6adm-routing"; 405663e10791SSrinivas Kandagatla #sound-dai-cells = <0>; 405763e10791SSrinivas Kandagatla }; 405863e10791SSrinivas Kandagatla }; 405963e10791SSrinivas Kandagatla }; 406063e10791SSrinivas Kandagatla 406125695808SJonathan Marek fastrpc { 406225695808SJonathan Marek compatible = "qcom,fastrpc"; 406325695808SJonathan Marek qcom,glink-channels = "fastrpcglink-apps-dsp"; 406425695808SJonathan Marek label = "adsp"; 406525695808SJonathan Marek #address-cells = <1>; 406625695808SJonathan Marek #size-cells = <0>; 406725695808SJonathan Marek 406825695808SJonathan Marek compute-cb@3 { 406925695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 407025695808SJonathan Marek reg = <3>; 407125695808SJonathan Marek iommus = <&apps_smmu 0x1803 0x0>; 407225695808SJonathan Marek }; 407325695808SJonathan Marek 407425695808SJonathan Marek compute-cb@4 { 407525695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 407625695808SJonathan Marek reg = <4>; 407725695808SJonathan Marek iommus = <&apps_smmu 0x1804 0x0>; 407825695808SJonathan Marek }; 407925695808SJonathan Marek 408025695808SJonathan Marek compute-cb@5 { 408125695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 408225695808SJonathan Marek reg = <5>; 408325695808SJonathan Marek iommus = <&apps_smmu 0x1805 0x0>; 408425695808SJonathan Marek }; 408525695808SJonathan Marek }; 408623a89037SBjorn Andersson }; 408723a89037SBjorn Andersson }; 408823a89037SBjorn Andersson 4089b9ec8cbcSJonathan Marek intc: interrupt-controller@17a00000 { 4090b9ec8cbcSJonathan Marek compatible = "arm,gic-v3"; 4091b9ec8cbcSJonathan Marek #interrupt-cells = <3>; 4092b9ec8cbcSJonathan Marek interrupt-controller; 4093b9ec8cbcSJonathan Marek reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4094b9ec8cbcSJonathan Marek <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4095b9ec8cbcSJonathan Marek interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4096b9ec8cbcSJonathan Marek }; 4097b9ec8cbcSJonathan Marek 4098e0d9acceSDmitry Baryshkov watchdog@17c10000 { 4099e0d9acceSDmitry Baryshkov compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 4100e0d9acceSDmitry Baryshkov reg = <0 0x17c10000 0 0x1000>; 4101e0d9acceSDmitry Baryshkov clocks = <&sleep_clk>; 410246a4359fSSai Prakash Ranjan interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4103e0d9acceSDmitry Baryshkov }; 4104e0d9acceSDmitry Baryshkov 4105b9ec8cbcSJonathan Marek timer@17c20000 { 4106b9ec8cbcSJonathan Marek #address-cells = <2>; 4107b9ec8cbcSJonathan Marek #size-cells = <2>; 4108b9ec8cbcSJonathan Marek ranges; 4109b9ec8cbcSJonathan Marek compatible = "arm,armv7-timer-mem"; 4110b9ec8cbcSJonathan Marek reg = <0x0 0x17c20000 0x0 0x1000>; 4111b9ec8cbcSJonathan Marek clock-frequency = <19200000>; 4112b9ec8cbcSJonathan Marek 4113b9ec8cbcSJonathan Marek frame@17c21000 { 4114b9ec8cbcSJonathan Marek frame-number = <0>; 4115b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4116b9ec8cbcSJonathan Marek <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4117b9ec8cbcSJonathan Marek reg = <0x0 0x17c21000 0x0 0x1000>, 4118b9ec8cbcSJonathan Marek <0x0 0x17c22000 0x0 0x1000>; 4119b9ec8cbcSJonathan Marek }; 4120b9ec8cbcSJonathan Marek 4121b9ec8cbcSJonathan Marek frame@17c23000 { 4122b9ec8cbcSJonathan Marek frame-number = <1>; 4123b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4124b9ec8cbcSJonathan Marek reg = <0x0 0x17c23000 0x0 0x1000>; 4125b9ec8cbcSJonathan Marek status = "disabled"; 4126b9ec8cbcSJonathan Marek }; 4127b9ec8cbcSJonathan Marek 4128b9ec8cbcSJonathan Marek frame@17c25000 { 4129b9ec8cbcSJonathan Marek frame-number = <2>; 4130b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4131b9ec8cbcSJonathan Marek reg = <0x0 0x17c25000 0x0 0x1000>; 4132b9ec8cbcSJonathan Marek status = "disabled"; 4133b9ec8cbcSJonathan Marek }; 4134b9ec8cbcSJonathan Marek 4135b9ec8cbcSJonathan Marek frame@17c27000 { 4136b9ec8cbcSJonathan Marek frame-number = <3>; 4137b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4138b9ec8cbcSJonathan Marek reg = <0x0 0x17c27000 0x0 0x1000>; 4139b9ec8cbcSJonathan Marek status = "disabled"; 4140b9ec8cbcSJonathan Marek }; 4141b9ec8cbcSJonathan Marek 4142b9ec8cbcSJonathan Marek frame@17c29000 { 4143b9ec8cbcSJonathan Marek frame-number = <4>; 4144b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4145b9ec8cbcSJonathan Marek reg = <0x0 0x17c29000 0x0 0x1000>; 4146b9ec8cbcSJonathan Marek status = "disabled"; 4147b9ec8cbcSJonathan Marek }; 4148b9ec8cbcSJonathan Marek 4149b9ec8cbcSJonathan Marek frame@17c2b000 { 4150b9ec8cbcSJonathan Marek frame-number = <5>; 4151b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4152b9ec8cbcSJonathan Marek reg = <0x0 0x17c2b000 0x0 0x1000>; 4153b9ec8cbcSJonathan Marek status = "disabled"; 4154b9ec8cbcSJonathan Marek }; 4155b9ec8cbcSJonathan Marek 4156b9ec8cbcSJonathan Marek frame@17c2d000 { 4157b9ec8cbcSJonathan Marek frame-number = <6>; 4158b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4159b9ec8cbcSJonathan Marek reg = <0x0 0x17c2d000 0x0 0x1000>; 4160b9ec8cbcSJonathan Marek status = "disabled"; 4161b9ec8cbcSJonathan Marek }; 4162b9ec8cbcSJonathan Marek }; 4163b9ec8cbcSJonathan Marek 416460378f1aSVenkata Narendra Kumar Gutta apps_rsc: rsc@18200000 { 416560378f1aSVenkata Narendra Kumar Gutta label = "apps_rsc"; 416660378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,rpmh-rsc"; 416760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x18200000 0x0 0x10000>, 416860378f1aSVenkata Narendra Kumar Gutta <0x0 0x18210000 0x0 0x10000>, 416960378f1aSVenkata Narendra Kumar Gutta <0x0 0x18220000 0x0 0x10000>; 417060378f1aSVenkata Narendra Kumar Gutta reg-names = "drv-0", "drv-1", "drv-2"; 417160378f1aSVenkata Narendra Kumar Gutta interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 417260378f1aSVenkata Narendra Kumar Gutta <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 417360378f1aSVenkata Narendra Kumar Gutta <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 417460378f1aSVenkata Narendra Kumar Gutta qcom,tcs-offset = <0xd00>; 417560378f1aSVenkata Narendra Kumar Gutta qcom,drv-id = <2>; 417660378f1aSVenkata Narendra Kumar Gutta qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 417760378f1aSVenkata Narendra Kumar Gutta <WAKE_TCS 3>, <CONTROL_TCS 1>; 417860378f1aSVenkata Narendra Kumar Gutta 417960378f1aSVenkata Narendra Kumar Gutta rpmhcc: clock-controller { 418060378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,sm8250-rpmh-clk"; 418160378f1aSVenkata Narendra Kumar Gutta #clock-cells = <1>; 418260378f1aSVenkata Narendra Kumar Gutta clock-names = "xo"; 418360378f1aSVenkata Narendra Kumar Gutta clocks = <&xo_board>; 418460378f1aSVenkata Narendra Kumar Gutta }; 4185b6f78e27SBjorn Andersson 4186b6f78e27SBjorn Andersson rpmhpd: power-controller { 4187b6f78e27SBjorn Andersson compatible = "qcom,sm8250-rpmhpd"; 4188b6f78e27SBjorn Andersson #power-domain-cells = <1>; 4189b6f78e27SBjorn Andersson operating-points-v2 = <&rpmhpd_opp_table>; 4190b6f78e27SBjorn Andersson 4191b6f78e27SBjorn Andersson rpmhpd_opp_table: opp-table { 4192b6f78e27SBjorn Andersson compatible = "operating-points-v2"; 4193b6f78e27SBjorn Andersson 4194b6f78e27SBjorn Andersson rpmhpd_opp_ret: opp1 { 4195b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4196b6f78e27SBjorn Andersson }; 4197b6f78e27SBjorn Andersson 4198b6f78e27SBjorn Andersson rpmhpd_opp_min_svs: opp2 { 4199b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4200b6f78e27SBjorn Andersson }; 4201b6f78e27SBjorn Andersson 4202b6f78e27SBjorn Andersson rpmhpd_opp_low_svs: opp3 { 4203b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4204b6f78e27SBjorn Andersson }; 4205b6f78e27SBjorn Andersson 4206b6f78e27SBjorn Andersson rpmhpd_opp_svs: opp4 { 4207b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4208b6f78e27SBjorn Andersson }; 4209b6f78e27SBjorn Andersson 4210b6f78e27SBjorn Andersson rpmhpd_opp_svs_l1: opp5 { 4211b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4212b6f78e27SBjorn Andersson }; 4213b6f78e27SBjorn Andersson 4214b6f78e27SBjorn Andersson rpmhpd_opp_nom: opp6 { 4215b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4216b6f78e27SBjorn Andersson }; 4217b6f78e27SBjorn Andersson 4218b6f78e27SBjorn Andersson rpmhpd_opp_nom_l1: opp7 { 4219b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4220b6f78e27SBjorn Andersson }; 4221b6f78e27SBjorn Andersson 4222b6f78e27SBjorn Andersson rpmhpd_opp_nom_l2: opp8 { 4223b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4224b6f78e27SBjorn Andersson }; 4225b6f78e27SBjorn Andersson 4226b6f78e27SBjorn Andersson rpmhpd_opp_turbo: opp9 { 4227b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4228b6f78e27SBjorn Andersson }; 4229b6f78e27SBjorn Andersson 4230b6f78e27SBjorn Andersson rpmhpd_opp_turbo_l1: opp10 { 4231b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4232b6f78e27SBjorn Andersson }; 4233b6f78e27SBjorn Andersson }; 4234b6f78e27SBjorn Andersson }; 4235e7e41a20SJonathan Marek 4236e7e41a20SJonathan Marek apps_bcm_voter: bcm_voter { 4237e7e41a20SJonathan Marek compatible = "qcom,bcm-voter"; 4238e7e41a20SJonathan Marek }; 423960378f1aSVenkata Narendra Kumar Gutta }; 424079a595bbSSibi Sankar 424177b53d65SGeorgi Djakov epss_l3: interconnect@18590000 { 424279a595bbSSibi Sankar compatible = "qcom,sm8250-epss-l3"; 424379a595bbSSibi Sankar reg = <0 0x18590000 0 0x1000>; 424479a595bbSSibi Sankar 424579a595bbSSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 424679a595bbSSibi Sankar clock-names = "xo", "alternate"; 424779a595bbSSibi Sankar 424879a595bbSSibi Sankar #interconnect-cells = <1>; 424979a595bbSSibi Sankar }; 425002ae4a0eSBjorn Andersson 425102ae4a0eSBjorn Andersson cpufreq_hw: cpufreq@18591000 { 425202ae4a0eSBjorn Andersson compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 425302ae4a0eSBjorn Andersson reg = <0 0x18591000 0 0x1000>, 425402ae4a0eSBjorn Andersson <0 0x18592000 0 0x1000>, 425502ae4a0eSBjorn Andersson <0 0x18593000 0 0x1000>; 425602ae4a0eSBjorn Andersson reg-names = "freq-domain0", "freq-domain1", 425702ae4a0eSBjorn Andersson "freq-domain2"; 425802ae4a0eSBjorn Andersson 425902ae4a0eSBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 426002ae4a0eSBjorn Andersson clock-names = "xo", "alternate"; 426102ae4a0eSBjorn Andersson 426202ae4a0eSBjorn Andersson #freq-domain-cells = <1>; 426302ae4a0eSBjorn Andersson }; 426460378f1aSVenkata Narendra Kumar Gutta }; 426560378f1aSVenkata Narendra Kumar Gutta 426660378f1aSVenkata Narendra Kumar Gutta timer { 426760378f1aSVenkata Narendra Kumar Gutta compatible = "arm,armv8-timer"; 426860378f1aSVenkata Narendra Kumar Gutta interrupts = <GIC_PPI 13 426960378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 427060378f1aSVenkata Narendra Kumar Gutta <GIC_PPI 14 427160378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 427260378f1aSVenkata Narendra Kumar Gutta <GIC_PPI 11 427360378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 427429a33495SSai Prakash Ranjan <GIC_PPI 10 427560378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 427660378f1aSVenkata Narendra Kumar Gutta }; 4277bac12f25SAmit Kucheria 4278bac12f25SAmit Kucheria thermal-zones { 4279bac12f25SAmit Kucheria cpu0-thermal { 4280bac12f25SAmit Kucheria polling-delay-passive = <250>; 4281bac12f25SAmit Kucheria polling-delay = <1000>; 4282bac12f25SAmit Kucheria 4283bac12f25SAmit Kucheria thermal-sensors = <&tsens0 1>; 4284bac12f25SAmit Kucheria 4285bac12f25SAmit Kucheria trips { 4286bac12f25SAmit Kucheria cpu0_alert0: trip-point0 { 4287bac12f25SAmit Kucheria temperature = <90000>; 4288bac12f25SAmit Kucheria hysteresis = <2000>; 4289bac12f25SAmit Kucheria type = "passive"; 4290bac12f25SAmit Kucheria }; 4291bac12f25SAmit Kucheria 4292bac12f25SAmit Kucheria cpu0_alert1: trip-point1 { 4293bac12f25SAmit Kucheria temperature = <95000>; 4294bac12f25SAmit Kucheria hysteresis = <2000>; 4295bac12f25SAmit Kucheria type = "passive"; 4296bac12f25SAmit Kucheria }; 4297bac12f25SAmit Kucheria 4298bac12f25SAmit Kucheria cpu0_crit: cpu_crit { 4299bac12f25SAmit Kucheria temperature = <110000>; 4300bac12f25SAmit Kucheria hysteresis = <1000>; 4301bac12f25SAmit Kucheria type = "critical"; 4302bac12f25SAmit Kucheria }; 4303bac12f25SAmit Kucheria }; 4304bac12f25SAmit Kucheria 4305bac12f25SAmit Kucheria cooling-maps { 4306bac12f25SAmit Kucheria map0 { 4307bac12f25SAmit Kucheria trip = <&cpu0_alert0>; 4308bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4309bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4310bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4311bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4312bac12f25SAmit Kucheria }; 4313bac12f25SAmit Kucheria map1 { 4314bac12f25SAmit Kucheria trip = <&cpu0_alert1>; 4315bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4316bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4317bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4318bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4319bac12f25SAmit Kucheria }; 4320bac12f25SAmit Kucheria }; 4321bac12f25SAmit Kucheria }; 4322bac12f25SAmit Kucheria 4323bac12f25SAmit Kucheria cpu1-thermal { 4324bac12f25SAmit Kucheria polling-delay-passive = <250>; 4325bac12f25SAmit Kucheria polling-delay = <1000>; 4326bac12f25SAmit Kucheria 4327bac12f25SAmit Kucheria thermal-sensors = <&tsens0 2>; 4328bac12f25SAmit Kucheria 4329bac12f25SAmit Kucheria trips { 4330bac12f25SAmit Kucheria cpu1_alert0: trip-point0 { 4331bac12f25SAmit Kucheria temperature = <90000>; 4332bac12f25SAmit Kucheria hysteresis = <2000>; 4333bac12f25SAmit Kucheria type = "passive"; 4334bac12f25SAmit Kucheria }; 4335bac12f25SAmit Kucheria 4336bac12f25SAmit Kucheria cpu1_alert1: trip-point1 { 4337bac12f25SAmit Kucheria temperature = <95000>; 4338bac12f25SAmit Kucheria hysteresis = <2000>; 4339bac12f25SAmit Kucheria type = "passive"; 4340bac12f25SAmit Kucheria }; 4341bac12f25SAmit Kucheria 4342bac12f25SAmit Kucheria cpu1_crit: cpu_crit { 4343bac12f25SAmit Kucheria temperature = <110000>; 4344bac12f25SAmit Kucheria hysteresis = <1000>; 4345bac12f25SAmit Kucheria type = "critical"; 4346bac12f25SAmit Kucheria }; 4347bac12f25SAmit Kucheria }; 4348bac12f25SAmit Kucheria 4349bac12f25SAmit Kucheria cooling-maps { 4350bac12f25SAmit Kucheria map0 { 4351bac12f25SAmit Kucheria trip = <&cpu1_alert0>; 4352bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4353bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4354bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4355bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4356bac12f25SAmit Kucheria }; 4357bac12f25SAmit Kucheria map1 { 4358bac12f25SAmit Kucheria trip = <&cpu1_alert1>; 4359bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4360bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4361bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4362bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4363bac12f25SAmit Kucheria }; 4364bac12f25SAmit Kucheria }; 4365bac12f25SAmit Kucheria }; 4366bac12f25SAmit Kucheria 4367bac12f25SAmit Kucheria cpu2-thermal { 4368bac12f25SAmit Kucheria polling-delay-passive = <250>; 4369bac12f25SAmit Kucheria polling-delay = <1000>; 4370bac12f25SAmit Kucheria 4371bac12f25SAmit Kucheria thermal-sensors = <&tsens0 3>; 4372bac12f25SAmit Kucheria 4373bac12f25SAmit Kucheria trips { 4374bac12f25SAmit Kucheria cpu2_alert0: trip-point0 { 4375bac12f25SAmit Kucheria temperature = <90000>; 4376bac12f25SAmit Kucheria hysteresis = <2000>; 4377bac12f25SAmit Kucheria type = "passive"; 4378bac12f25SAmit Kucheria }; 4379bac12f25SAmit Kucheria 4380bac12f25SAmit Kucheria cpu2_alert1: trip-point1 { 4381bac12f25SAmit Kucheria temperature = <95000>; 4382bac12f25SAmit Kucheria hysteresis = <2000>; 4383bac12f25SAmit Kucheria type = "passive"; 4384bac12f25SAmit Kucheria }; 4385bac12f25SAmit Kucheria 4386bac12f25SAmit Kucheria cpu2_crit: cpu_crit { 4387bac12f25SAmit Kucheria temperature = <110000>; 4388bac12f25SAmit Kucheria hysteresis = <1000>; 4389bac12f25SAmit Kucheria type = "critical"; 4390bac12f25SAmit Kucheria }; 4391bac12f25SAmit Kucheria }; 4392bac12f25SAmit Kucheria 4393bac12f25SAmit Kucheria cooling-maps { 4394bac12f25SAmit Kucheria map0 { 4395bac12f25SAmit Kucheria trip = <&cpu2_alert0>; 4396bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4397bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4398bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4399bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4400bac12f25SAmit Kucheria }; 4401bac12f25SAmit Kucheria map1 { 4402bac12f25SAmit Kucheria trip = <&cpu2_alert1>; 4403bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4404bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4405bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4406bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4407bac12f25SAmit Kucheria }; 4408bac12f25SAmit Kucheria }; 4409bac12f25SAmit Kucheria }; 4410bac12f25SAmit Kucheria 4411bac12f25SAmit Kucheria cpu3-thermal { 4412bac12f25SAmit Kucheria polling-delay-passive = <250>; 4413bac12f25SAmit Kucheria polling-delay = <1000>; 4414bac12f25SAmit Kucheria 4415bac12f25SAmit Kucheria thermal-sensors = <&tsens0 4>; 4416bac12f25SAmit Kucheria 4417bac12f25SAmit Kucheria trips { 4418bac12f25SAmit Kucheria cpu3_alert0: trip-point0 { 4419bac12f25SAmit Kucheria temperature = <90000>; 4420bac12f25SAmit Kucheria hysteresis = <2000>; 4421bac12f25SAmit Kucheria type = "passive"; 4422bac12f25SAmit Kucheria }; 4423bac12f25SAmit Kucheria 4424bac12f25SAmit Kucheria cpu3_alert1: trip-point1 { 4425bac12f25SAmit Kucheria temperature = <95000>; 4426bac12f25SAmit Kucheria hysteresis = <2000>; 4427bac12f25SAmit Kucheria type = "passive"; 4428bac12f25SAmit Kucheria }; 4429bac12f25SAmit Kucheria 4430bac12f25SAmit Kucheria cpu3_crit: cpu_crit { 4431bac12f25SAmit Kucheria temperature = <110000>; 4432bac12f25SAmit Kucheria hysteresis = <1000>; 4433bac12f25SAmit Kucheria type = "critical"; 4434bac12f25SAmit Kucheria }; 4435bac12f25SAmit Kucheria }; 4436bac12f25SAmit Kucheria 4437bac12f25SAmit Kucheria cooling-maps { 4438bac12f25SAmit Kucheria map0 { 4439bac12f25SAmit Kucheria trip = <&cpu3_alert0>; 4440bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4441bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4442bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4443bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4444bac12f25SAmit Kucheria }; 4445bac12f25SAmit Kucheria map1 { 4446bac12f25SAmit Kucheria trip = <&cpu3_alert1>; 4447bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4448bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4449bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4450bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4451bac12f25SAmit Kucheria }; 4452bac12f25SAmit Kucheria }; 4453bac12f25SAmit Kucheria }; 4454bac12f25SAmit Kucheria 4455bac12f25SAmit Kucheria cpu4-top-thermal { 4456bac12f25SAmit Kucheria polling-delay-passive = <250>; 4457bac12f25SAmit Kucheria polling-delay = <1000>; 4458bac12f25SAmit Kucheria 4459bac12f25SAmit Kucheria thermal-sensors = <&tsens0 7>; 4460bac12f25SAmit Kucheria 4461bac12f25SAmit Kucheria trips { 4462bac12f25SAmit Kucheria cpu4_top_alert0: trip-point0 { 4463bac12f25SAmit Kucheria temperature = <90000>; 4464bac12f25SAmit Kucheria hysteresis = <2000>; 4465bac12f25SAmit Kucheria type = "passive"; 4466bac12f25SAmit Kucheria }; 4467bac12f25SAmit Kucheria 4468bac12f25SAmit Kucheria cpu4_top_alert1: trip-point1 { 4469bac12f25SAmit Kucheria temperature = <95000>; 4470bac12f25SAmit Kucheria hysteresis = <2000>; 4471bac12f25SAmit Kucheria type = "passive"; 4472bac12f25SAmit Kucheria }; 4473bac12f25SAmit Kucheria 4474bac12f25SAmit Kucheria cpu4_top_crit: cpu_crit { 4475bac12f25SAmit Kucheria temperature = <110000>; 4476bac12f25SAmit Kucheria hysteresis = <1000>; 4477bac12f25SAmit Kucheria type = "critical"; 4478bac12f25SAmit Kucheria }; 4479bac12f25SAmit Kucheria }; 4480bac12f25SAmit Kucheria 4481bac12f25SAmit Kucheria cooling-maps { 4482bac12f25SAmit Kucheria map0 { 4483bac12f25SAmit Kucheria trip = <&cpu4_top_alert0>; 4484bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4485bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4486bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4487bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4488bac12f25SAmit Kucheria }; 4489bac12f25SAmit Kucheria map1 { 4490bac12f25SAmit Kucheria trip = <&cpu4_top_alert1>; 4491bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4492bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4493bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4494bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4495bac12f25SAmit Kucheria }; 4496bac12f25SAmit Kucheria }; 4497bac12f25SAmit Kucheria }; 4498bac12f25SAmit Kucheria 4499bac12f25SAmit Kucheria cpu5-top-thermal { 4500bac12f25SAmit Kucheria polling-delay-passive = <250>; 4501bac12f25SAmit Kucheria polling-delay = <1000>; 4502bac12f25SAmit Kucheria 4503bac12f25SAmit Kucheria thermal-sensors = <&tsens0 8>; 4504bac12f25SAmit Kucheria 4505bac12f25SAmit Kucheria trips { 4506bac12f25SAmit Kucheria cpu5_top_alert0: trip-point0 { 4507bac12f25SAmit Kucheria temperature = <90000>; 4508bac12f25SAmit Kucheria hysteresis = <2000>; 4509bac12f25SAmit Kucheria type = "passive"; 4510bac12f25SAmit Kucheria }; 4511bac12f25SAmit Kucheria 4512bac12f25SAmit Kucheria cpu5_top_alert1: trip-point1 { 4513bac12f25SAmit Kucheria temperature = <95000>; 4514bac12f25SAmit Kucheria hysteresis = <2000>; 4515bac12f25SAmit Kucheria type = "passive"; 4516bac12f25SAmit Kucheria }; 4517bac12f25SAmit Kucheria 4518bac12f25SAmit Kucheria cpu5_top_crit: cpu_crit { 4519bac12f25SAmit Kucheria temperature = <110000>; 4520bac12f25SAmit Kucheria hysteresis = <1000>; 4521bac12f25SAmit Kucheria type = "critical"; 4522bac12f25SAmit Kucheria }; 4523bac12f25SAmit Kucheria }; 4524bac12f25SAmit Kucheria 4525bac12f25SAmit Kucheria cooling-maps { 4526bac12f25SAmit Kucheria map0 { 4527bac12f25SAmit Kucheria trip = <&cpu5_top_alert0>; 4528bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4529bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4530bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4531bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4532bac12f25SAmit Kucheria }; 4533bac12f25SAmit Kucheria map1 { 4534bac12f25SAmit Kucheria trip = <&cpu5_top_alert1>; 4535bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4536bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4537bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4538bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4539bac12f25SAmit Kucheria }; 4540bac12f25SAmit Kucheria }; 4541bac12f25SAmit Kucheria }; 4542bac12f25SAmit Kucheria 4543bac12f25SAmit Kucheria cpu6-top-thermal { 4544bac12f25SAmit Kucheria polling-delay-passive = <250>; 4545bac12f25SAmit Kucheria polling-delay = <1000>; 4546bac12f25SAmit Kucheria 4547bac12f25SAmit Kucheria thermal-sensors = <&tsens0 9>; 4548bac12f25SAmit Kucheria 4549bac12f25SAmit Kucheria trips { 4550bac12f25SAmit Kucheria cpu6_top_alert0: trip-point0 { 4551bac12f25SAmit Kucheria temperature = <90000>; 4552bac12f25SAmit Kucheria hysteresis = <2000>; 4553bac12f25SAmit Kucheria type = "passive"; 4554bac12f25SAmit Kucheria }; 4555bac12f25SAmit Kucheria 4556bac12f25SAmit Kucheria cpu6_top_alert1: trip-point1 { 4557bac12f25SAmit Kucheria temperature = <95000>; 4558bac12f25SAmit Kucheria hysteresis = <2000>; 4559bac12f25SAmit Kucheria type = "passive"; 4560bac12f25SAmit Kucheria }; 4561bac12f25SAmit Kucheria 4562bac12f25SAmit Kucheria cpu6_top_crit: cpu_crit { 4563bac12f25SAmit Kucheria temperature = <110000>; 4564bac12f25SAmit Kucheria hysteresis = <1000>; 4565bac12f25SAmit Kucheria type = "critical"; 4566bac12f25SAmit Kucheria }; 4567bac12f25SAmit Kucheria }; 4568bac12f25SAmit Kucheria 4569bac12f25SAmit Kucheria cooling-maps { 4570bac12f25SAmit Kucheria map0 { 4571bac12f25SAmit Kucheria trip = <&cpu6_top_alert0>; 4572bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4573bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4574bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4575bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4576bac12f25SAmit Kucheria }; 4577bac12f25SAmit Kucheria map1 { 4578bac12f25SAmit Kucheria trip = <&cpu6_top_alert1>; 4579bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4580bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4581bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4582bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4583bac12f25SAmit Kucheria }; 4584bac12f25SAmit Kucheria }; 4585bac12f25SAmit Kucheria }; 4586bac12f25SAmit Kucheria 4587bac12f25SAmit Kucheria cpu7-top-thermal { 4588bac12f25SAmit Kucheria polling-delay-passive = <250>; 4589bac12f25SAmit Kucheria polling-delay = <1000>; 4590bac12f25SAmit Kucheria 4591bac12f25SAmit Kucheria thermal-sensors = <&tsens0 10>; 4592bac12f25SAmit Kucheria 4593bac12f25SAmit Kucheria trips { 4594bac12f25SAmit Kucheria cpu7_top_alert0: trip-point0 { 4595bac12f25SAmit Kucheria temperature = <90000>; 4596bac12f25SAmit Kucheria hysteresis = <2000>; 4597bac12f25SAmit Kucheria type = "passive"; 4598bac12f25SAmit Kucheria }; 4599bac12f25SAmit Kucheria 4600bac12f25SAmit Kucheria cpu7_top_alert1: trip-point1 { 4601bac12f25SAmit Kucheria temperature = <95000>; 4602bac12f25SAmit Kucheria hysteresis = <2000>; 4603bac12f25SAmit Kucheria type = "passive"; 4604bac12f25SAmit Kucheria }; 4605bac12f25SAmit Kucheria 4606bac12f25SAmit Kucheria cpu7_top_crit: cpu_crit { 4607bac12f25SAmit Kucheria temperature = <110000>; 4608bac12f25SAmit Kucheria hysteresis = <1000>; 4609bac12f25SAmit Kucheria type = "critical"; 4610bac12f25SAmit Kucheria }; 4611bac12f25SAmit Kucheria }; 4612bac12f25SAmit Kucheria 4613bac12f25SAmit Kucheria cooling-maps { 4614bac12f25SAmit Kucheria map0 { 4615bac12f25SAmit Kucheria trip = <&cpu7_top_alert0>; 4616bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4617bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4618bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4619bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4620bac12f25SAmit Kucheria }; 4621bac12f25SAmit Kucheria map1 { 4622bac12f25SAmit Kucheria trip = <&cpu7_top_alert1>; 4623bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4624bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4625bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4626bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4627bac12f25SAmit Kucheria }; 4628bac12f25SAmit Kucheria }; 4629bac12f25SAmit Kucheria }; 4630bac12f25SAmit Kucheria 4631bac12f25SAmit Kucheria cpu4-bottom-thermal { 4632bac12f25SAmit Kucheria polling-delay-passive = <250>; 4633bac12f25SAmit Kucheria polling-delay = <1000>; 4634bac12f25SAmit Kucheria 4635bac12f25SAmit Kucheria thermal-sensors = <&tsens0 11>; 4636bac12f25SAmit Kucheria 4637bac12f25SAmit Kucheria trips { 4638bac12f25SAmit Kucheria cpu4_bottom_alert0: trip-point0 { 4639bac12f25SAmit Kucheria temperature = <90000>; 4640bac12f25SAmit Kucheria hysteresis = <2000>; 4641bac12f25SAmit Kucheria type = "passive"; 4642bac12f25SAmit Kucheria }; 4643bac12f25SAmit Kucheria 4644bac12f25SAmit Kucheria cpu4_bottom_alert1: trip-point1 { 4645bac12f25SAmit Kucheria temperature = <95000>; 4646bac12f25SAmit Kucheria hysteresis = <2000>; 4647bac12f25SAmit Kucheria type = "passive"; 4648bac12f25SAmit Kucheria }; 4649bac12f25SAmit Kucheria 4650bac12f25SAmit Kucheria cpu4_bottom_crit: cpu_crit { 4651bac12f25SAmit Kucheria temperature = <110000>; 4652bac12f25SAmit Kucheria hysteresis = <1000>; 4653bac12f25SAmit Kucheria type = "critical"; 4654bac12f25SAmit Kucheria }; 4655bac12f25SAmit Kucheria }; 4656bac12f25SAmit Kucheria 4657bac12f25SAmit Kucheria cooling-maps { 4658bac12f25SAmit Kucheria map0 { 4659bac12f25SAmit Kucheria trip = <&cpu4_bottom_alert0>; 4660bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4661bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4662bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4663bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4664bac12f25SAmit Kucheria }; 4665bac12f25SAmit Kucheria map1 { 4666bac12f25SAmit Kucheria trip = <&cpu4_bottom_alert1>; 4667bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4668bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4669bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4670bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4671bac12f25SAmit Kucheria }; 4672bac12f25SAmit Kucheria }; 4673bac12f25SAmit Kucheria }; 4674bac12f25SAmit Kucheria 4675bac12f25SAmit Kucheria cpu5-bottom-thermal { 4676bac12f25SAmit Kucheria polling-delay-passive = <250>; 4677bac12f25SAmit Kucheria polling-delay = <1000>; 4678bac12f25SAmit Kucheria 4679bac12f25SAmit Kucheria thermal-sensors = <&tsens0 12>; 4680bac12f25SAmit Kucheria 4681bac12f25SAmit Kucheria trips { 4682bac12f25SAmit Kucheria cpu5_bottom_alert0: trip-point0 { 4683bac12f25SAmit Kucheria temperature = <90000>; 4684bac12f25SAmit Kucheria hysteresis = <2000>; 4685bac12f25SAmit Kucheria type = "passive"; 4686bac12f25SAmit Kucheria }; 4687bac12f25SAmit Kucheria 4688bac12f25SAmit Kucheria cpu5_bottom_alert1: trip-point1 { 4689bac12f25SAmit Kucheria temperature = <95000>; 4690bac12f25SAmit Kucheria hysteresis = <2000>; 4691bac12f25SAmit Kucheria type = "passive"; 4692bac12f25SAmit Kucheria }; 4693bac12f25SAmit Kucheria 4694bac12f25SAmit Kucheria cpu5_bottom_crit: cpu_crit { 4695bac12f25SAmit Kucheria temperature = <110000>; 4696bac12f25SAmit Kucheria hysteresis = <1000>; 4697bac12f25SAmit Kucheria type = "critical"; 4698bac12f25SAmit Kucheria }; 4699bac12f25SAmit Kucheria }; 4700bac12f25SAmit Kucheria 4701bac12f25SAmit Kucheria cooling-maps { 4702bac12f25SAmit Kucheria map0 { 4703bac12f25SAmit Kucheria trip = <&cpu5_bottom_alert0>; 4704bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4705bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4706bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4707bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4708bac12f25SAmit Kucheria }; 4709bac12f25SAmit Kucheria map1 { 4710bac12f25SAmit Kucheria trip = <&cpu5_bottom_alert1>; 4711bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4712bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4713bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4714bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4715bac12f25SAmit Kucheria }; 4716bac12f25SAmit Kucheria }; 4717bac12f25SAmit Kucheria }; 4718bac12f25SAmit Kucheria 4719bac12f25SAmit Kucheria cpu6-bottom-thermal { 4720bac12f25SAmit Kucheria polling-delay-passive = <250>; 4721bac12f25SAmit Kucheria polling-delay = <1000>; 4722bac12f25SAmit Kucheria 4723bac12f25SAmit Kucheria thermal-sensors = <&tsens0 13>; 4724bac12f25SAmit Kucheria 4725bac12f25SAmit Kucheria trips { 4726bac12f25SAmit Kucheria cpu6_bottom_alert0: trip-point0 { 4727bac12f25SAmit Kucheria temperature = <90000>; 4728bac12f25SAmit Kucheria hysteresis = <2000>; 4729bac12f25SAmit Kucheria type = "passive"; 4730bac12f25SAmit Kucheria }; 4731bac12f25SAmit Kucheria 4732bac12f25SAmit Kucheria cpu6_bottom_alert1: trip-point1 { 4733bac12f25SAmit Kucheria temperature = <95000>; 4734bac12f25SAmit Kucheria hysteresis = <2000>; 4735bac12f25SAmit Kucheria type = "passive"; 4736bac12f25SAmit Kucheria }; 4737bac12f25SAmit Kucheria 4738bac12f25SAmit Kucheria cpu6_bottom_crit: cpu_crit { 4739bac12f25SAmit Kucheria temperature = <110000>; 4740bac12f25SAmit Kucheria hysteresis = <1000>; 4741bac12f25SAmit Kucheria type = "critical"; 4742bac12f25SAmit Kucheria }; 4743bac12f25SAmit Kucheria }; 4744bac12f25SAmit Kucheria 4745bac12f25SAmit Kucheria cooling-maps { 4746bac12f25SAmit Kucheria map0 { 4747bac12f25SAmit Kucheria trip = <&cpu6_bottom_alert0>; 4748bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4749bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4750bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4751bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4752bac12f25SAmit Kucheria }; 4753bac12f25SAmit Kucheria map1 { 4754bac12f25SAmit Kucheria trip = <&cpu6_bottom_alert1>; 4755bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4756bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4757bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4758bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4759bac12f25SAmit Kucheria }; 4760bac12f25SAmit Kucheria }; 4761bac12f25SAmit Kucheria }; 4762bac12f25SAmit Kucheria 4763bac12f25SAmit Kucheria cpu7-bottom-thermal { 4764bac12f25SAmit Kucheria polling-delay-passive = <250>; 4765bac12f25SAmit Kucheria polling-delay = <1000>; 4766bac12f25SAmit Kucheria 4767bac12f25SAmit Kucheria thermal-sensors = <&tsens0 14>; 4768bac12f25SAmit Kucheria 4769bac12f25SAmit Kucheria trips { 4770bac12f25SAmit Kucheria cpu7_bottom_alert0: trip-point0 { 4771bac12f25SAmit Kucheria temperature = <90000>; 4772bac12f25SAmit Kucheria hysteresis = <2000>; 4773bac12f25SAmit Kucheria type = "passive"; 4774bac12f25SAmit Kucheria }; 4775bac12f25SAmit Kucheria 4776bac12f25SAmit Kucheria cpu7_bottom_alert1: trip-point1 { 4777bac12f25SAmit Kucheria temperature = <95000>; 4778bac12f25SAmit Kucheria hysteresis = <2000>; 4779bac12f25SAmit Kucheria type = "passive"; 4780bac12f25SAmit Kucheria }; 4781bac12f25SAmit Kucheria 4782bac12f25SAmit Kucheria cpu7_bottom_crit: cpu_crit { 4783bac12f25SAmit Kucheria temperature = <110000>; 4784bac12f25SAmit Kucheria hysteresis = <1000>; 4785bac12f25SAmit Kucheria type = "critical"; 4786bac12f25SAmit Kucheria }; 4787bac12f25SAmit Kucheria }; 4788bac12f25SAmit Kucheria 4789bac12f25SAmit Kucheria cooling-maps { 4790bac12f25SAmit Kucheria map0 { 4791bac12f25SAmit Kucheria trip = <&cpu7_bottom_alert0>; 4792bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4793bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4794bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4795bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4796bac12f25SAmit Kucheria }; 4797bac12f25SAmit Kucheria map1 { 4798bac12f25SAmit Kucheria trip = <&cpu7_bottom_alert1>; 4799bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4800bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4801bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4802bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4803bac12f25SAmit Kucheria }; 4804bac12f25SAmit Kucheria }; 4805bac12f25SAmit Kucheria }; 4806bac12f25SAmit Kucheria 4807bac12f25SAmit Kucheria aoss0-thermal { 4808bac12f25SAmit Kucheria polling-delay-passive = <250>; 4809bac12f25SAmit Kucheria polling-delay = <1000>; 4810bac12f25SAmit Kucheria 4811bac12f25SAmit Kucheria thermal-sensors = <&tsens0 0>; 4812bac12f25SAmit Kucheria 4813bac12f25SAmit Kucheria trips { 4814bac12f25SAmit Kucheria aoss0_alert0: trip-point0 { 4815bac12f25SAmit Kucheria temperature = <90000>; 4816bac12f25SAmit Kucheria hysteresis = <2000>; 4817bac12f25SAmit Kucheria type = "hot"; 4818bac12f25SAmit Kucheria }; 4819bac12f25SAmit Kucheria }; 4820bac12f25SAmit Kucheria }; 4821bac12f25SAmit Kucheria 4822bac12f25SAmit Kucheria cluster0-thermal { 4823bac12f25SAmit Kucheria polling-delay-passive = <250>; 4824bac12f25SAmit Kucheria polling-delay = <1000>; 4825bac12f25SAmit Kucheria 4826bac12f25SAmit Kucheria thermal-sensors = <&tsens0 5>; 4827bac12f25SAmit Kucheria 4828bac12f25SAmit Kucheria trips { 4829bac12f25SAmit Kucheria cluster0_alert0: trip-point0 { 4830bac12f25SAmit Kucheria temperature = <90000>; 4831bac12f25SAmit Kucheria hysteresis = <2000>; 4832bac12f25SAmit Kucheria type = "hot"; 4833bac12f25SAmit Kucheria }; 4834bac12f25SAmit Kucheria cluster0_crit: cluster0_crit { 4835bac12f25SAmit Kucheria temperature = <110000>; 4836bac12f25SAmit Kucheria hysteresis = <2000>; 4837bac12f25SAmit Kucheria type = "critical"; 4838bac12f25SAmit Kucheria }; 4839bac12f25SAmit Kucheria }; 4840bac12f25SAmit Kucheria }; 4841bac12f25SAmit Kucheria 4842bac12f25SAmit Kucheria cluster1-thermal { 4843bac12f25SAmit Kucheria polling-delay-passive = <250>; 4844bac12f25SAmit Kucheria polling-delay = <1000>; 4845bac12f25SAmit Kucheria 4846bac12f25SAmit Kucheria thermal-sensors = <&tsens0 6>; 4847bac12f25SAmit Kucheria 4848bac12f25SAmit Kucheria trips { 4849bac12f25SAmit Kucheria cluster1_alert0: trip-point0 { 4850bac12f25SAmit Kucheria temperature = <90000>; 4851bac12f25SAmit Kucheria hysteresis = <2000>; 4852bac12f25SAmit Kucheria type = "hot"; 4853bac12f25SAmit Kucheria }; 4854bac12f25SAmit Kucheria cluster1_crit: cluster1_crit { 4855bac12f25SAmit Kucheria temperature = <110000>; 4856bac12f25SAmit Kucheria hysteresis = <2000>; 4857bac12f25SAmit Kucheria type = "critical"; 4858bac12f25SAmit Kucheria }; 4859bac12f25SAmit Kucheria }; 4860bac12f25SAmit Kucheria }; 4861bac12f25SAmit Kucheria 4862bac12f25SAmit Kucheria gpu-thermal-top { 4863bac12f25SAmit Kucheria polling-delay-passive = <250>; 4864bac12f25SAmit Kucheria polling-delay = <1000>; 4865bac12f25SAmit Kucheria 4866bac12f25SAmit Kucheria thermal-sensors = <&tsens0 15>; 4867bac12f25SAmit Kucheria 4868bac12f25SAmit Kucheria trips { 4869bac12f25SAmit Kucheria gpu1_alert0: trip-point0 { 4870bac12f25SAmit Kucheria temperature = <90000>; 4871bac12f25SAmit Kucheria hysteresis = <2000>; 4872bac12f25SAmit Kucheria type = "hot"; 4873bac12f25SAmit Kucheria }; 4874bac12f25SAmit Kucheria }; 4875bac12f25SAmit Kucheria }; 4876bac12f25SAmit Kucheria 4877bac12f25SAmit Kucheria aoss1-thermal { 4878bac12f25SAmit Kucheria polling-delay-passive = <250>; 4879bac12f25SAmit Kucheria polling-delay = <1000>; 4880bac12f25SAmit Kucheria 4881bac12f25SAmit Kucheria thermal-sensors = <&tsens1 0>; 4882bac12f25SAmit Kucheria 4883bac12f25SAmit Kucheria trips { 4884bac12f25SAmit Kucheria aoss1_alert0: trip-point0 { 4885bac12f25SAmit Kucheria temperature = <90000>; 4886bac12f25SAmit Kucheria hysteresis = <2000>; 4887bac12f25SAmit Kucheria type = "hot"; 4888bac12f25SAmit Kucheria }; 4889bac12f25SAmit Kucheria }; 4890bac12f25SAmit Kucheria }; 4891bac12f25SAmit Kucheria 4892bac12f25SAmit Kucheria wlan-thermal { 4893bac12f25SAmit Kucheria polling-delay-passive = <250>; 4894bac12f25SAmit Kucheria polling-delay = <1000>; 4895bac12f25SAmit Kucheria 4896bac12f25SAmit Kucheria thermal-sensors = <&tsens1 1>; 4897bac12f25SAmit Kucheria 4898bac12f25SAmit Kucheria trips { 4899bac12f25SAmit Kucheria wlan_alert0: trip-point0 { 4900bac12f25SAmit Kucheria temperature = <90000>; 4901bac12f25SAmit Kucheria hysteresis = <2000>; 4902bac12f25SAmit Kucheria type = "hot"; 4903bac12f25SAmit Kucheria }; 4904bac12f25SAmit Kucheria }; 4905bac12f25SAmit Kucheria }; 4906bac12f25SAmit Kucheria 4907bac12f25SAmit Kucheria video-thermal { 4908bac12f25SAmit Kucheria polling-delay-passive = <250>; 4909bac12f25SAmit Kucheria polling-delay = <1000>; 4910bac12f25SAmit Kucheria 4911bac12f25SAmit Kucheria thermal-sensors = <&tsens1 2>; 4912bac12f25SAmit Kucheria 4913bac12f25SAmit Kucheria trips { 4914bac12f25SAmit Kucheria video_alert0: trip-point0 { 4915bac12f25SAmit Kucheria temperature = <90000>; 4916bac12f25SAmit Kucheria hysteresis = <2000>; 4917bac12f25SAmit Kucheria type = "hot"; 4918bac12f25SAmit Kucheria }; 4919bac12f25SAmit Kucheria }; 4920bac12f25SAmit Kucheria }; 4921bac12f25SAmit Kucheria 4922bac12f25SAmit Kucheria mem-thermal { 4923bac12f25SAmit Kucheria polling-delay-passive = <250>; 4924bac12f25SAmit Kucheria polling-delay = <1000>; 4925bac12f25SAmit Kucheria 4926bac12f25SAmit Kucheria thermal-sensors = <&tsens1 3>; 4927bac12f25SAmit Kucheria 4928bac12f25SAmit Kucheria trips { 4929bac12f25SAmit Kucheria mem_alert0: trip-point0 { 4930bac12f25SAmit Kucheria temperature = <90000>; 4931bac12f25SAmit Kucheria hysteresis = <2000>; 4932bac12f25SAmit Kucheria type = "hot"; 4933bac12f25SAmit Kucheria }; 4934bac12f25SAmit Kucheria }; 4935bac12f25SAmit Kucheria }; 4936bac12f25SAmit Kucheria 4937bac12f25SAmit Kucheria q6-hvx-thermal { 4938bac12f25SAmit Kucheria polling-delay-passive = <250>; 4939bac12f25SAmit Kucheria polling-delay = <1000>; 4940bac12f25SAmit Kucheria 4941bac12f25SAmit Kucheria thermal-sensors = <&tsens1 4>; 4942bac12f25SAmit Kucheria 4943bac12f25SAmit Kucheria trips { 4944bac12f25SAmit Kucheria q6_hvx_alert0: trip-point0 { 4945bac12f25SAmit Kucheria temperature = <90000>; 4946bac12f25SAmit Kucheria hysteresis = <2000>; 4947bac12f25SAmit Kucheria type = "hot"; 4948bac12f25SAmit Kucheria }; 4949bac12f25SAmit Kucheria }; 4950bac12f25SAmit Kucheria }; 4951bac12f25SAmit Kucheria 4952bac12f25SAmit Kucheria camera-thermal { 4953bac12f25SAmit Kucheria polling-delay-passive = <250>; 4954bac12f25SAmit Kucheria polling-delay = <1000>; 4955bac12f25SAmit Kucheria 4956bac12f25SAmit Kucheria thermal-sensors = <&tsens1 5>; 4957bac12f25SAmit Kucheria 4958bac12f25SAmit Kucheria trips { 4959bac12f25SAmit Kucheria camera_alert0: trip-point0 { 4960bac12f25SAmit Kucheria temperature = <90000>; 4961bac12f25SAmit Kucheria hysteresis = <2000>; 4962bac12f25SAmit Kucheria type = "hot"; 4963bac12f25SAmit Kucheria }; 4964bac12f25SAmit Kucheria }; 4965bac12f25SAmit Kucheria }; 4966bac12f25SAmit Kucheria 4967bac12f25SAmit Kucheria compute-thermal { 4968bac12f25SAmit Kucheria polling-delay-passive = <250>; 4969bac12f25SAmit Kucheria polling-delay = <1000>; 4970bac12f25SAmit Kucheria 4971bac12f25SAmit Kucheria thermal-sensors = <&tsens1 6>; 4972bac12f25SAmit Kucheria 4973bac12f25SAmit Kucheria trips { 4974bac12f25SAmit Kucheria compute_alert0: trip-point0 { 4975bac12f25SAmit Kucheria temperature = <90000>; 4976bac12f25SAmit Kucheria hysteresis = <2000>; 4977bac12f25SAmit Kucheria type = "hot"; 4978bac12f25SAmit Kucheria }; 4979bac12f25SAmit Kucheria }; 4980bac12f25SAmit Kucheria }; 4981bac12f25SAmit Kucheria 4982bac12f25SAmit Kucheria npu-thermal { 4983bac12f25SAmit Kucheria polling-delay-passive = <250>; 4984bac12f25SAmit Kucheria polling-delay = <1000>; 4985bac12f25SAmit Kucheria 4986bac12f25SAmit Kucheria thermal-sensors = <&tsens1 7>; 4987bac12f25SAmit Kucheria 4988bac12f25SAmit Kucheria trips { 4989bac12f25SAmit Kucheria npu_alert0: trip-point0 { 4990bac12f25SAmit Kucheria temperature = <90000>; 4991bac12f25SAmit Kucheria hysteresis = <2000>; 4992bac12f25SAmit Kucheria type = "hot"; 4993bac12f25SAmit Kucheria }; 4994bac12f25SAmit Kucheria }; 4995bac12f25SAmit Kucheria }; 4996bac12f25SAmit Kucheria 4997bac12f25SAmit Kucheria gpu-thermal-bottom { 4998bac12f25SAmit Kucheria polling-delay-passive = <250>; 4999bac12f25SAmit Kucheria polling-delay = <1000>; 5000bac12f25SAmit Kucheria 5001bac12f25SAmit Kucheria thermal-sensors = <&tsens1 8>; 5002bac12f25SAmit Kucheria 5003bac12f25SAmit Kucheria trips { 5004bac12f25SAmit Kucheria gpu2_alert0: trip-point0 { 5005bac12f25SAmit Kucheria temperature = <90000>; 5006bac12f25SAmit Kucheria hysteresis = <2000>; 5007bac12f25SAmit Kucheria type = "hot"; 5008bac12f25SAmit Kucheria }; 5009bac12f25SAmit Kucheria }; 5010bac12f25SAmit Kucheria }; 5011bac12f25SAmit Kucheria }; 501260378f1aSVenkata Narendra Kumar Gutta}; 5013