160378f1aSVenkata Narendra Kumar Gutta// SPDX-License-Identifier: BSD-3-Clause 260378f1aSVenkata Narendra Kumar Gutta/* 360378f1aSVenkata Narendra Kumar Gutta * Copyright (c) 2020, The Linux Foundation. All rights reserved. 460378f1aSVenkata Narendra Kumar Gutta */ 560378f1aSVenkata Narendra Kumar Gutta 660378f1aSVenkata Narendra Kumar Gutta#include <dt-bindings/interrupt-controller/arm-gic.h> 77c1dffd4SDmitry Baryshkov#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8b7e2fba0SBryan O'Donoghue#include <dt-bindings/clock/qcom,gcc-sm8250.h> 90e6aa9dbSJonathan Marek#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 1060378f1aSVenkata Narendra Kumar Gutta#include <dt-bindings/clock/qcom,rpmh.h> 11*15049bb5SKonrad Dybcio#include <dt-bindings/dma/qcom-gpi.h> 1279a595bbSSibi Sankar#include <dt-bindings/interconnect/qcom,osm-l3.h> 137c1dffd4SDmitry Baryshkov#include <dt-bindings/interconnect/qcom,sm8250.h> 14e5361e75SBjorn Andersson#include <dt-bindings/mailbox/qcom-ipcc.h> 15087d537aSBjorn Andersson#include <dt-bindings/power/qcom-aoss-qmp.h> 16b6f78e27SBjorn Andersson#include <dt-bindings/power/qcom-rpmpd.h> 1763e10791SSrinivas Kandagatla#include <dt-bindings/soc/qcom,apr.h> 1860378f1aSVenkata Narendra Kumar Gutta#include <dt-bindings/soc/qcom,rpmh-rsc.h> 1963e10791SSrinivas Kandagatla#include <dt-bindings/sound/qcom,q6afe.h> 20bac12f25SAmit Kucheria#include <dt-bindings/thermal/thermal.h> 215b9ec225Sjonathan@marek.ca#include <dt-bindings/clock/qcom,videocc-sm8250.h> 2260378f1aSVenkata Narendra Kumar Gutta 2360378f1aSVenkata Narendra Kumar Gutta/ { 2460378f1aSVenkata Narendra Kumar Gutta interrupt-parent = <&intc>; 2560378f1aSVenkata Narendra Kumar Gutta 2660378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 2760378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 2860378f1aSVenkata Narendra Kumar Gutta 29e5813b15SDmitry Baryshkov aliases { 30e5813b15SDmitry Baryshkov i2c0 = &i2c0; 31e5813b15SDmitry Baryshkov i2c1 = &i2c1; 32e5813b15SDmitry Baryshkov i2c2 = &i2c2; 33e5813b15SDmitry Baryshkov i2c3 = &i2c3; 34e5813b15SDmitry Baryshkov i2c4 = &i2c4; 35e5813b15SDmitry Baryshkov i2c5 = &i2c5; 36e5813b15SDmitry Baryshkov i2c6 = &i2c6; 37e5813b15SDmitry Baryshkov i2c7 = &i2c7; 38e5813b15SDmitry Baryshkov i2c8 = &i2c8; 39e5813b15SDmitry Baryshkov i2c9 = &i2c9; 40e5813b15SDmitry Baryshkov i2c10 = &i2c10; 41e5813b15SDmitry Baryshkov i2c11 = &i2c11; 42e5813b15SDmitry Baryshkov i2c12 = &i2c12; 43e5813b15SDmitry Baryshkov i2c13 = &i2c13; 44e5813b15SDmitry Baryshkov i2c14 = &i2c14; 45e5813b15SDmitry Baryshkov i2c15 = &i2c15; 46e5813b15SDmitry Baryshkov i2c16 = &i2c16; 47e5813b15SDmitry Baryshkov i2c17 = &i2c17; 48e5813b15SDmitry Baryshkov i2c18 = &i2c18; 49e5813b15SDmitry Baryshkov i2c19 = &i2c19; 50e5813b15SDmitry Baryshkov spi0 = &spi0; 51e5813b15SDmitry Baryshkov spi1 = &spi1; 52e5813b15SDmitry Baryshkov spi2 = &spi2; 53e5813b15SDmitry Baryshkov spi3 = &spi3; 54e5813b15SDmitry Baryshkov spi4 = &spi4; 55e5813b15SDmitry Baryshkov spi5 = &spi5; 56e5813b15SDmitry Baryshkov spi6 = &spi6; 57e5813b15SDmitry Baryshkov spi7 = &spi7; 58e5813b15SDmitry Baryshkov spi8 = &spi8; 59e5813b15SDmitry Baryshkov spi9 = &spi9; 60e5813b15SDmitry Baryshkov spi10 = &spi10; 61e5813b15SDmitry Baryshkov spi11 = &spi11; 62e5813b15SDmitry Baryshkov spi12 = &spi12; 63e5813b15SDmitry Baryshkov spi13 = &spi13; 64e5813b15SDmitry Baryshkov spi14 = &spi14; 65e5813b15SDmitry Baryshkov spi15 = &spi15; 66e5813b15SDmitry Baryshkov spi16 = &spi16; 67e5813b15SDmitry Baryshkov spi17 = &spi17; 68e5813b15SDmitry Baryshkov spi18 = &spi18; 69e5813b15SDmitry Baryshkov spi19 = &spi19; 70e5813b15SDmitry Baryshkov }; 71e5813b15SDmitry Baryshkov 7260378f1aSVenkata Narendra Kumar Gutta chosen { }; 7360378f1aSVenkata Narendra Kumar Gutta 7460378f1aSVenkata Narendra Kumar Gutta clocks { 7560378f1aSVenkata Narendra Kumar Gutta xo_board: xo-board { 7660378f1aSVenkata Narendra Kumar Gutta compatible = "fixed-clock"; 7760378f1aSVenkata Narendra Kumar Gutta #clock-cells = <0>; 7860378f1aSVenkata Narendra Kumar Gutta clock-frequency = <38400000>; 7960378f1aSVenkata Narendra Kumar Gutta clock-output-names = "xo_board"; 8060378f1aSVenkata Narendra Kumar Gutta }; 8160378f1aSVenkata Narendra Kumar Gutta 8260378f1aSVenkata Narendra Kumar Gutta sleep_clk: sleep-clk { 8360378f1aSVenkata Narendra Kumar Gutta compatible = "fixed-clock"; 849ff8b059SJonathan Marek clock-frequency = <32768>; 8560378f1aSVenkata Narendra Kumar Gutta #clock-cells = <0>; 8660378f1aSVenkata Narendra Kumar Gutta }; 8760378f1aSVenkata Narendra Kumar Gutta }; 8860378f1aSVenkata Narendra Kumar Gutta 8960378f1aSVenkata Narendra Kumar Gutta cpus { 9060378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 9160378f1aSVenkata Narendra Kumar Gutta #size-cells = <0>; 9260378f1aSVenkata Narendra Kumar Gutta 9360378f1aSVenkata Narendra Kumar Gutta CPU0: cpu@0 { 9460378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 9560378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 9660378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x0>; 9760378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 986aabed55SDanny Lin capacity-dmips-mhz = <448>; 996aabed55SDanny Lin dynamic-power-coefficient = <205>; 10060378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_0>; 10102ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 102bac12f25SAmit Kucheria #cooling-cells = <2>; 10360378f1aSVenkata Narendra Kumar Gutta L2_0: l2-cache { 10460378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 10560378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 10660378f1aSVenkata Narendra Kumar Gutta L3_0: l3-cache { 10760378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 10860378f1aSVenkata Narendra Kumar Gutta }; 10960378f1aSVenkata Narendra Kumar Gutta }; 11060378f1aSVenkata Narendra Kumar Gutta }; 11160378f1aSVenkata Narendra Kumar Gutta 11260378f1aSVenkata Narendra Kumar Gutta CPU1: cpu@100 { 11360378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 11460378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 11560378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x100>; 11660378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1176aabed55SDanny Lin capacity-dmips-mhz = <448>; 1186aabed55SDanny Lin dynamic-power-coefficient = <205>; 11960378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_100>; 12002ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 121bac12f25SAmit Kucheria #cooling-cells = <2>; 12260378f1aSVenkata Narendra Kumar Gutta L2_100: l2-cache { 12360378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 12460378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 12560378f1aSVenkata Narendra Kumar Gutta }; 12660378f1aSVenkata Narendra Kumar Gutta }; 12760378f1aSVenkata Narendra Kumar Gutta 12860378f1aSVenkata Narendra Kumar Gutta CPU2: cpu@200 { 12960378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 13060378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 13160378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x200>; 13260378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1336aabed55SDanny Lin capacity-dmips-mhz = <448>; 1346aabed55SDanny Lin dynamic-power-coefficient = <205>; 13560378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_200>; 13602ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 137bac12f25SAmit Kucheria #cooling-cells = <2>; 13860378f1aSVenkata Narendra Kumar Gutta L2_200: l2-cache { 13960378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 14060378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 14160378f1aSVenkata Narendra Kumar Gutta }; 14260378f1aSVenkata Narendra Kumar Gutta }; 14360378f1aSVenkata Narendra Kumar Gutta 14460378f1aSVenkata Narendra Kumar Gutta CPU3: cpu@300 { 14560378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 14660378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 14760378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x300>; 14860378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1496aabed55SDanny Lin capacity-dmips-mhz = <448>; 1506aabed55SDanny Lin dynamic-power-coefficient = <205>; 15160378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_300>; 15202ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 0>; 153bac12f25SAmit Kucheria #cooling-cells = <2>; 15460378f1aSVenkata Narendra Kumar Gutta L2_300: l2-cache { 15560378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 15660378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 15760378f1aSVenkata Narendra Kumar Gutta }; 15860378f1aSVenkata Narendra Kumar Gutta }; 15960378f1aSVenkata Narendra Kumar Gutta 16060378f1aSVenkata Narendra Kumar Gutta CPU4: cpu@400 { 16160378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 16260378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 16360378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x400>; 16460378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1656aabed55SDanny Lin capacity-dmips-mhz = <1024>; 1666aabed55SDanny Lin dynamic-power-coefficient = <379>; 16760378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_400>; 16802ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 1>; 169bac12f25SAmit Kucheria #cooling-cells = <2>; 17060378f1aSVenkata Narendra Kumar Gutta L2_400: l2-cache { 17160378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 17260378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 17360378f1aSVenkata Narendra Kumar Gutta }; 17460378f1aSVenkata Narendra Kumar Gutta }; 17560378f1aSVenkata Narendra Kumar Gutta 17660378f1aSVenkata Narendra Kumar Gutta CPU5: cpu@500 { 17760378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 17860378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 17960378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x500>; 18060378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1816aabed55SDanny Lin capacity-dmips-mhz = <1024>; 1826aabed55SDanny Lin dynamic-power-coefficient = <379>; 18360378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_500>; 18402ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 1>; 185bac12f25SAmit Kucheria #cooling-cells = <2>; 18660378f1aSVenkata Narendra Kumar Gutta L2_500: l2-cache { 18760378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 18860378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 18960378f1aSVenkata Narendra Kumar Gutta }; 19060378f1aSVenkata Narendra Kumar Gutta 19160378f1aSVenkata Narendra Kumar Gutta }; 19260378f1aSVenkata Narendra Kumar Gutta 19360378f1aSVenkata Narendra Kumar Gutta CPU6: cpu@600 { 19460378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 19560378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 19660378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x600>; 19760378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 1986aabed55SDanny Lin capacity-dmips-mhz = <1024>; 1996aabed55SDanny Lin dynamic-power-coefficient = <379>; 20060378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_600>; 20102ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 1>; 202bac12f25SAmit Kucheria #cooling-cells = <2>; 20360378f1aSVenkata Narendra Kumar Gutta L2_600: l2-cache { 20460378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 20560378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 20660378f1aSVenkata Narendra Kumar Gutta }; 20760378f1aSVenkata Narendra Kumar Gutta }; 20860378f1aSVenkata Narendra Kumar Gutta 20960378f1aSVenkata Narendra Kumar Gutta CPU7: cpu@700 { 21060378f1aSVenkata Narendra Kumar Gutta device_type = "cpu"; 21160378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,kryo485"; 21260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x700>; 21360378f1aSVenkata Narendra Kumar Gutta enable-method = "psci"; 2146aabed55SDanny Lin capacity-dmips-mhz = <1024>; 2156aabed55SDanny Lin dynamic-power-coefficient = <444>; 21660378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L2_700>; 21702ae4a0eSBjorn Andersson qcom,freq-domain = <&cpufreq_hw 2>; 218bac12f25SAmit Kucheria #cooling-cells = <2>; 21960378f1aSVenkata Narendra Kumar Gutta L2_700: l2-cache { 22060378f1aSVenkata Narendra Kumar Gutta compatible = "cache"; 22160378f1aSVenkata Narendra Kumar Gutta next-level-cache = <&L3_0>; 22260378f1aSVenkata Narendra Kumar Gutta }; 22360378f1aSVenkata Narendra Kumar Gutta }; 224b4791e69SDanny Lin 225b4791e69SDanny Lin cpu-map { 226b4791e69SDanny Lin cluster0 { 227b4791e69SDanny Lin core0 { 228b4791e69SDanny Lin cpu = <&CPU0>; 229b4791e69SDanny Lin }; 230b4791e69SDanny Lin 231b4791e69SDanny Lin core1 { 232b4791e69SDanny Lin cpu = <&CPU1>; 233b4791e69SDanny Lin }; 234b4791e69SDanny Lin 235b4791e69SDanny Lin core2 { 236b4791e69SDanny Lin cpu = <&CPU2>; 237b4791e69SDanny Lin }; 238b4791e69SDanny Lin 239b4791e69SDanny Lin core3 { 240b4791e69SDanny Lin cpu = <&CPU3>; 241b4791e69SDanny Lin }; 242b4791e69SDanny Lin 243b4791e69SDanny Lin core4 { 244b4791e69SDanny Lin cpu = <&CPU4>; 245b4791e69SDanny Lin }; 246b4791e69SDanny Lin 247b4791e69SDanny Lin core5 { 248b4791e69SDanny Lin cpu = <&CPU5>; 249b4791e69SDanny Lin }; 250b4791e69SDanny Lin 251b4791e69SDanny Lin core6 { 252b4791e69SDanny Lin cpu = <&CPU6>; 253b4791e69SDanny Lin }; 254b4791e69SDanny Lin 255b4791e69SDanny Lin core7 { 256b4791e69SDanny Lin cpu = <&CPU7>; 257b4791e69SDanny Lin }; 258b4791e69SDanny Lin }; 259b4791e69SDanny Lin }; 26060378f1aSVenkata Narendra Kumar Gutta }; 26160378f1aSVenkata Narendra Kumar Gutta 26260378f1aSVenkata Narendra Kumar Gutta firmware { 26360378f1aSVenkata Narendra Kumar Gutta scm: scm { 26460378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,scm"; 26560378f1aSVenkata Narendra Kumar Gutta #reset-cells = <1>; 26660378f1aSVenkata Narendra Kumar Gutta }; 26760378f1aSVenkata Narendra Kumar Gutta }; 26860378f1aSVenkata Narendra Kumar Gutta 26960378f1aSVenkata Narendra Kumar Gutta memory@80000000 { 27060378f1aSVenkata Narendra Kumar Gutta device_type = "memory"; 27160378f1aSVenkata Narendra Kumar Gutta /* We expect the bootloader to fill in the size */ 27260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80000000 0x0 0x0>; 27360378f1aSVenkata Narendra Kumar Gutta }; 27460378f1aSVenkata Narendra Kumar Gutta 2753f2094dfSDmitry Baryshkov mmcx_reg: mmcx-reg { 2763f2094dfSDmitry Baryshkov compatible = "regulator-fixed-domain"; 2773f2094dfSDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 2783f2094dfSDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 2793f2094dfSDmitry Baryshkov regulator-name = "MMCX"; 2803f2094dfSDmitry Baryshkov }; 2813f2094dfSDmitry Baryshkov 28260378f1aSVenkata Narendra Kumar Gutta pmu { 28360378f1aSVenkata Narendra Kumar Gutta compatible = "arm,armv8-pmuv3"; 28493138ef5SSai Prakash Ranjan interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 28560378f1aSVenkata Narendra Kumar Gutta }; 28660378f1aSVenkata Narendra Kumar Gutta 28760378f1aSVenkata Narendra Kumar Gutta psci { 28860378f1aSVenkata Narendra Kumar Gutta compatible = "arm,psci-1.0"; 28960378f1aSVenkata Narendra Kumar Gutta method = "smc"; 29060378f1aSVenkata Narendra Kumar Gutta }; 29160378f1aSVenkata Narendra Kumar Gutta 29260378f1aSVenkata Narendra Kumar Gutta reserved-memory { 29360378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 29460378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 29560378f1aSVenkata Narendra Kumar Gutta ranges; 29660378f1aSVenkata Narendra Kumar Gutta 29760378f1aSVenkata Narendra Kumar Gutta hyp_mem: memory@80000000 { 29860378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80000000 0x0 0x600000>; 29960378f1aSVenkata Narendra Kumar Gutta no-map; 30060378f1aSVenkata Narendra Kumar Gutta }; 30160378f1aSVenkata Narendra Kumar Gutta 30260378f1aSVenkata Narendra Kumar Gutta xbl_aop_mem: memory@80700000 { 30360378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80700000 0x0 0x160000>; 30460378f1aSVenkata Narendra Kumar Gutta no-map; 30560378f1aSVenkata Narendra Kumar Gutta }; 30660378f1aSVenkata Narendra Kumar Gutta 30760378f1aSVenkata Narendra Kumar Gutta cmd_db: memory@80860000 { 30860378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,cmd-db"; 30960378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80860000 0x0 0x20000>; 31060378f1aSVenkata Narendra Kumar Gutta no-map; 31160378f1aSVenkata Narendra Kumar Gutta }; 31260378f1aSVenkata Narendra Kumar Gutta 31360378f1aSVenkata Narendra Kumar Gutta smem_mem: memory@80900000 { 31460378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80900000 0x0 0x200000>; 31560378f1aSVenkata Narendra Kumar Gutta no-map; 31660378f1aSVenkata Narendra Kumar Gutta }; 31760378f1aSVenkata Narendra Kumar Gutta 31860378f1aSVenkata Narendra Kumar Gutta removed_mem: memory@80b00000 { 31960378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x80b00000 0x0 0x5300000>; 32060378f1aSVenkata Narendra Kumar Gutta no-map; 32160378f1aSVenkata Narendra Kumar Gutta }; 32260378f1aSVenkata Narendra Kumar Gutta 32360378f1aSVenkata Narendra Kumar Gutta camera_mem: memory@86200000 { 32460378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86200000 0x0 0x500000>; 32560378f1aSVenkata Narendra Kumar Gutta no-map; 32660378f1aSVenkata Narendra Kumar Gutta }; 32760378f1aSVenkata Narendra Kumar Gutta 32860378f1aSVenkata Narendra Kumar Gutta wlan_mem: memory@86700000 { 32960378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86700000 0x0 0x100000>; 33060378f1aSVenkata Narendra Kumar Gutta no-map; 33160378f1aSVenkata Narendra Kumar Gutta }; 33260378f1aSVenkata Narendra Kumar Gutta 33360378f1aSVenkata Narendra Kumar Gutta ipa_fw_mem: memory@86800000 { 33460378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86800000 0x0 0x10000>; 33560378f1aSVenkata Narendra Kumar Gutta no-map; 33660378f1aSVenkata Narendra Kumar Gutta }; 33760378f1aSVenkata Narendra Kumar Gutta 33860378f1aSVenkata Narendra Kumar Gutta ipa_gsi_mem: memory@86810000 { 33960378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86810000 0x0 0xa000>; 34060378f1aSVenkata Narendra Kumar Gutta no-map; 34160378f1aSVenkata Narendra Kumar Gutta }; 34260378f1aSVenkata Narendra Kumar Gutta 34360378f1aSVenkata Narendra Kumar Gutta gpu_mem: memory@8681a000 { 34460378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8681a000 0x0 0x2000>; 34560378f1aSVenkata Narendra Kumar Gutta no-map; 34660378f1aSVenkata Narendra Kumar Gutta }; 34760378f1aSVenkata Narendra Kumar Gutta 34860378f1aSVenkata Narendra Kumar Gutta npu_mem: memory@86900000 { 34960378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86900000 0x0 0x500000>; 35060378f1aSVenkata Narendra Kumar Gutta no-map; 35160378f1aSVenkata Narendra Kumar Gutta }; 35260378f1aSVenkata Narendra Kumar Gutta 35360378f1aSVenkata Narendra Kumar Gutta video_mem: memory@86e00000 { 35460378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x86e00000 0x0 0x500000>; 35560378f1aSVenkata Narendra Kumar Gutta no-map; 35660378f1aSVenkata Narendra Kumar Gutta }; 35760378f1aSVenkata Narendra Kumar Gutta 35860378f1aSVenkata Narendra Kumar Gutta cvp_mem: memory@87300000 { 35960378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x87300000 0x0 0x500000>; 36060378f1aSVenkata Narendra Kumar Gutta no-map; 36160378f1aSVenkata Narendra Kumar Gutta }; 36260378f1aSVenkata Narendra Kumar Gutta 36360378f1aSVenkata Narendra Kumar Gutta cdsp_mem: memory@87800000 { 36460378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x87800000 0x0 0x1400000>; 36560378f1aSVenkata Narendra Kumar Gutta no-map; 36660378f1aSVenkata Narendra Kumar Gutta }; 36760378f1aSVenkata Narendra Kumar Gutta 36860378f1aSVenkata Narendra Kumar Gutta slpi_mem: memory@88c00000 { 36960378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x88c00000 0x0 0x1500000>; 37060378f1aSVenkata Narendra Kumar Gutta no-map; 37160378f1aSVenkata Narendra Kumar Gutta }; 37260378f1aSVenkata Narendra Kumar Gutta 37360378f1aSVenkata Narendra Kumar Gutta adsp_mem: memory@8a100000 { 37460378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8a100000 0x0 0x1d00000>; 37560378f1aSVenkata Narendra Kumar Gutta no-map; 37660378f1aSVenkata Narendra Kumar Gutta }; 37760378f1aSVenkata Narendra Kumar Gutta 37860378f1aSVenkata Narendra Kumar Gutta spss_mem: memory@8be00000 { 37960378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8be00000 0x0 0x100000>; 38060378f1aSVenkata Narendra Kumar Gutta no-map; 38160378f1aSVenkata Narendra Kumar Gutta }; 38260378f1aSVenkata Narendra Kumar Gutta 38360378f1aSVenkata Narendra Kumar Gutta cdsp_secure_heap: memory@8bf00000 { 38460378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x8bf00000 0x0 0x4600000>; 38560378f1aSVenkata Narendra Kumar Gutta no-map; 38660378f1aSVenkata Narendra Kumar Gutta }; 38760378f1aSVenkata Narendra Kumar Gutta }; 38860378f1aSVenkata Narendra Kumar Gutta 38988b57bc3SDmitry Baryshkov smem { 39060378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,smem"; 39160378f1aSVenkata Narendra Kumar Gutta memory-region = <&smem_mem>; 39260378f1aSVenkata Narendra Kumar Gutta hwlocks = <&tcsr_mutex 3>; 39360378f1aSVenkata Narendra Kumar Gutta }; 39460378f1aSVenkata Narendra Kumar Gutta 3958770a2a8SBjorn Andersson smp2p-adsp { 3968770a2a8SBjorn Andersson compatible = "qcom,smp2p"; 3978770a2a8SBjorn Andersson qcom,smem = <443>, <429>; 3988770a2a8SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3998770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P 4008770a2a8SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 4018770a2a8SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_LPASS 4028770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P>; 4038770a2a8SBjorn Andersson 4048770a2a8SBjorn Andersson qcom,local-pid = <0>; 4058770a2a8SBjorn Andersson qcom,remote-pid = <2>; 4068770a2a8SBjorn Andersson 4078770a2a8SBjorn Andersson smp2p_adsp_out: master-kernel { 4088770a2a8SBjorn Andersson qcom,entry-name = "master-kernel"; 4098770a2a8SBjorn Andersson #qcom,smem-state-cells = <1>; 4108770a2a8SBjorn Andersson }; 4118770a2a8SBjorn Andersson 4128770a2a8SBjorn Andersson smp2p_adsp_in: slave-kernel { 4138770a2a8SBjorn Andersson qcom,entry-name = "slave-kernel"; 4148770a2a8SBjorn Andersson interrupt-controller; 4158770a2a8SBjorn Andersson #interrupt-cells = <2>; 4168770a2a8SBjorn Andersson }; 4178770a2a8SBjorn Andersson }; 4188770a2a8SBjorn Andersson 4198770a2a8SBjorn Andersson smp2p-cdsp { 4208770a2a8SBjorn Andersson compatible = "qcom,smp2p"; 4218770a2a8SBjorn Andersson qcom,smem = <94>, <432>; 4228770a2a8SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4238770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P 4248770a2a8SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 4258770a2a8SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_CDSP 4268770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P>; 4278770a2a8SBjorn Andersson 4288770a2a8SBjorn Andersson qcom,local-pid = <0>; 4298770a2a8SBjorn Andersson qcom,remote-pid = <5>; 4308770a2a8SBjorn Andersson 4318770a2a8SBjorn Andersson smp2p_cdsp_out: master-kernel { 4328770a2a8SBjorn Andersson qcom,entry-name = "master-kernel"; 4338770a2a8SBjorn Andersson #qcom,smem-state-cells = <1>; 4348770a2a8SBjorn Andersson }; 4358770a2a8SBjorn Andersson 4368770a2a8SBjorn Andersson smp2p_cdsp_in: slave-kernel { 4378770a2a8SBjorn Andersson qcom,entry-name = "slave-kernel"; 4388770a2a8SBjorn Andersson interrupt-controller; 4398770a2a8SBjorn Andersson #interrupt-cells = <2>; 4408770a2a8SBjorn Andersson }; 4418770a2a8SBjorn Andersson }; 4428770a2a8SBjorn Andersson 4438770a2a8SBjorn Andersson smp2p-slpi { 4448770a2a8SBjorn Andersson compatible = "qcom,smp2p"; 4458770a2a8SBjorn Andersson qcom,smem = <481>, <430>; 4468770a2a8SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 4478770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P 4488770a2a8SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 4498770a2a8SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_SLPI 4508770a2a8SBjorn Andersson IPCC_MPROC_SIGNAL_SMP2P>; 4518770a2a8SBjorn Andersson 4528770a2a8SBjorn Andersson qcom,local-pid = <0>; 4538770a2a8SBjorn Andersson qcom,remote-pid = <3>; 4548770a2a8SBjorn Andersson 4558770a2a8SBjorn Andersson smp2p_slpi_out: master-kernel { 4568770a2a8SBjorn Andersson qcom,entry-name = "master-kernel"; 4578770a2a8SBjorn Andersson #qcom,smem-state-cells = <1>; 4588770a2a8SBjorn Andersson }; 4598770a2a8SBjorn Andersson 4608770a2a8SBjorn Andersson smp2p_slpi_in: slave-kernel { 4618770a2a8SBjorn Andersson qcom,entry-name = "slave-kernel"; 4628770a2a8SBjorn Andersson interrupt-controller; 4638770a2a8SBjorn Andersson #interrupt-cells = <2>; 4648770a2a8SBjorn Andersson }; 4658770a2a8SBjorn Andersson }; 4668770a2a8SBjorn Andersson 46760378f1aSVenkata Narendra Kumar Gutta soc: soc@0 { 46860378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 46960378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 47060378f1aSVenkata Narendra Kumar Gutta ranges = <0 0 0 0 0x10 0>; 47160378f1aSVenkata Narendra Kumar Gutta dma-ranges = <0 0 0 0 0x10 0>; 47260378f1aSVenkata Narendra Kumar Gutta compatible = "simple-bus"; 47360378f1aSVenkata Narendra Kumar Gutta 47460378f1aSVenkata Narendra Kumar Gutta gcc: clock-controller@100000 { 47560378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,gcc-sm8250"; 47660378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x00100000 0x0 0x1f0000>; 47760378f1aSVenkata Narendra Kumar Gutta #clock-cells = <1>; 47860378f1aSVenkata Narendra Kumar Gutta #reset-cells = <1>; 47960378f1aSVenkata Narendra Kumar Gutta #power-domain-cells = <1>; 48076bd127eSDmitry Baryshkov clock-names = "bi_tcxo", 48176bd127eSDmitry Baryshkov "bi_tcxo_ao", 48276bd127eSDmitry Baryshkov "sleep_clk"; 48376bd127eSDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>, 48476bd127eSDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK_A>, 48576bd127eSDmitry Baryshkov <&sleep_clk>; 48660378f1aSVenkata Narendra Kumar Gutta }; 48760378f1aSVenkata Narendra Kumar Gutta 488e5361e75SBjorn Andersson ipcc: mailbox@408000 { 489e5361e75SBjorn Andersson compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 490e5361e75SBjorn Andersson reg = <0 0x00408000 0 0x1000>; 491e5361e75SBjorn Andersson interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 492e5361e75SBjorn Andersson interrupt-controller; 493e5361e75SBjorn Andersson #interrupt-cells = <3>; 494e5361e75SBjorn Andersson #mbox-cells = <2>; 495e5361e75SBjorn Andersson }; 496e5361e75SBjorn Andersson 49765389ce6SManivannan Sadhasivam rng: rng@793000 { 49865389ce6SManivannan Sadhasivam compatible = "qcom,prng-ee"; 49965389ce6SManivannan Sadhasivam reg = <0 0x00793000 0 0x1000>; 50065389ce6SManivannan Sadhasivam clocks = <&gcc GCC_PRNG_AHB_CLK>; 50165389ce6SManivannan Sadhasivam clock-names = "core"; 50265389ce6SManivannan Sadhasivam }; 50365389ce6SManivannan Sadhasivam 50401e869ccSDmitry Baryshkov qup_opp_table: qup-opp-table { 50501e869ccSDmitry Baryshkov compatible = "operating-points-v2"; 50601e869ccSDmitry Baryshkov 50701e869ccSDmitry Baryshkov opp-50000000 { 50801e869ccSDmitry Baryshkov opp-hz = /bits/ 64 <50000000>; 50901e869ccSDmitry Baryshkov required-opps = <&rpmhpd_opp_min_svs>; 51001e869ccSDmitry Baryshkov }; 51101e869ccSDmitry Baryshkov 51201e869ccSDmitry Baryshkov opp-75000000 { 51301e869ccSDmitry Baryshkov opp-hz = /bits/ 64 <75000000>; 51401e869ccSDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 51501e869ccSDmitry Baryshkov }; 51601e869ccSDmitry Baryshkov 51701e869ccSDmitry Baryshkov opp-120000000 { 51801e869ccSDmitry Baryshkov opp-hz = /bits/ 64 <120000000>; 51901e869ccSDmitry Baryshkov required-opps = <&rpmhpd_opp_svs>; 52001e869ccSDmitry Baryshkov }; 52101e869ccSDmitry Baryshkov }; 52201e869ccSDmitry Baryshkov 523*15049bb5SKonrad Dybcio gpi_dma2: dma-controller@800000 { 524*15049bb5SKonrad Dybcio compatible = "qcom,sm8250-gpi-dma"; 525*15049bb5SKonrad Dybcio reg = <0 0x00800000 0 0x70000>; 526*15049bb5SKonrad Dybcio interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 527*15049bb5SKonrad Dybcio <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 528*15049bb5SKonrad Dybcio <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 529*15049bb5SKonrad Dybcio <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 530*15049bb5SKonrad Dybcio <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 531*15049bb5SKonrad Dybcio <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 532*15049bb5SKonrad Dybcio <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 533*15049bb5SKonrad Dybcio <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 534*15049bb5SKonrad Dybcio <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 535*15049bb5SKonrad Dybcio <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 536*15049bb5SKonrad Dybcio dma-channels = <10>; 537*15049bb5SKonrad Dybcio dma-channel-mask = <0x3f>; 538*15049bb5SKonrad Dybcio iommus = <&apps_smmu 0x76 0x0>; 539*15049bb5SKonrad Dybcio #dma-cells = <3>; 540*15049bb5SKonrad Dybcio status = "disabled"; 541*15049bb5SKonrad Dybcio }; 542*15049bb5SKonrad Dybcio 543e5813b15SDmitry Baryshkov qupv3_id_2: geniqup@8c0000 { 544e5813b15SDmitry Baryshkov compatible = "qcom,geni-se-qup"; 545e5813b15SDmitry Baryshkov reg = <0x0 0x008c0000 0x0 0x6000>; 546e5813b15SDmitry Baryshkov clock-names = "m-ahb", "s-ahb"; 547e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 548e5813b15SDmitry Baryshkov <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 549e5813b15SDmitry Baryshkov #address-cells = <2>; 550e5813b15SDmitry Baryshkov #size-cells = <2>; 55185309393SDmitry Baryshkov iommus = <&apps_smmu 0x63 0x0>; 552e5813b15SDmitry Baryshkov ranges; 553e5813b15SDmitry Baryshkov status = "disabled"; 554e5813b15SDmitry Baryshkov 555e5813b15SDmitry Baryshkov i2c14: i2c@880000 { 556e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 557e5813b15SDmitry Baryshkov reg = <0 0x00880000 0 0x4000>; 558e5813b15SDmitry Baryshkov clock-names = "se"; 559e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 560e5813b15SDmitry Baryshkov pinctrl-names = "default"; 561e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c14_default>; 562e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 563e5813b15SDmitry Baryshkov #address-cells = <1>; 564e5813b15SDmitry Baryshkov #size-cells = <0>; 565e5813b15SDmitry Baryshkov status = "disabled"; 566e5813b15SDmitry Baryshkov }; 567e5813b15SDmitry Baryshkov 568e5813b15SDmitry Baryshkov spi14: spi@880000 { 569e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 570e5813b15SDmitry Baryshkov reg = <0 0x00880000 0 0x4000>; 571e5813b15SDmitry Baryshkov clock-names = "se"; 572e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 573e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 574e5813b15SDmitry Baryshkov #address-cells = <1>; 575e5813b15SDmitry Baryshkov #size-cells = <0>; 57601e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 57701e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 578e5813b15SDmitry Baryshkov status = "disabled"; 579e5813b15SDmitry Baryshkov }; 580e5813b15SDmitry Baryshkov 581e5813b15SDmitry Baryshkov i2c15: i2c@884000 { 582e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 583e5813b15SDmitry Baryshkov reg = <0 0x00884000 0 0x4000>; 584e5813b15SDmitry Baryshkov clock-names = "se"; 585e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 586e5813b15SDmitry Baryshkov pinctrl-names = "default"; 587e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c15_default>; 588e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 589e5813b15SDmitry Baryshkov #address-cells = <1>; 590e5813b15SDmitry Baryshkov #size-cells = <0>; 591e5813b15SDmitry Baryshkov status = "disabled"; 592e5813b15SDmitry Baryshkov }; 593e5813b15SDmitry Baryshkov 594e5813b15SDmitry Baryshkov spi15: spi@884000 { 595e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 596e5813b15SDmitry Baryshkov reg = <0 0x00884000 0 0x4000>; 597e5813b15SDmitry Baryshkov clock-names = "se"; 598e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 599e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 600e5813b15SDmitry Baryshkov #address-cells = <1>; 601e5813b15SDmitry Baryshkov #size-cells = <0>; 60201e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 60301e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 604e5813b15SDmitry Baryshkov status = "disabled"; 605e5813b15SDmitry Baryshkov }; 606e5813b15SDmitry Baryshkov 607e5813b15SDmitry Baryshkov i2c16: i2c@888000 { 608e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 609e5813b15SDmitry Baryshkov reg = <0 0x00888000 0 0x4000>; 610e5813b15SDmitry Baryshkov clock-names = "se"; 611e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 612e5813b15SDmitry Baryshkov pinctrl-names = "default"; 613e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c16_default>; 614e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 615e5813b15SDmitry Baryshkov #address-cells = <1>; 616e5813b15SDmitry Baryshkov #size-cells = <0>; 617e5813b15SDmitry Baryshkov status = "disabled"; 618e5813b15SDmitry Baryshkov }; 619e5813b15SDmitry Baryshkov 620e5813b15SDmitry Baryshkov spi16: spi@888000 { 621e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 622e5813b15SDmitry Baryshkov reg = <0 0x00888000 0 0x4000>; 623e5813b15SDmitry Baryshkov clock-names = "se"; 624e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 625e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 626e5813b15SDmitry Baryshkov #address-cells = <1>; 627e5813b15SDmitry Baryshkov #size-cells = <0>; 62801e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 62901e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 630e5813b15SDmitry Baryshkov status = "disabled"; 631e5813b15SDmitry Baryshkov }; 632e5813b15SDmitry Baryshkov 633e5813b15SDmitry Baryshkov i2c17: i2c@88c000 { 634e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 635e5813b15SDmitry Baryshkov reg = <0 0x0088c000 0 0x4000>; 636e5813b15SDmitry Baryshkov clock-names = "se"; 637e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 638e5813b15SDmitry Baryshkov pinctrl-names = "default"; 639e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c17_default>; 640e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 641e5813b15SDmitry Baryshkov #address-cells = <1>; 642e5813b15SDmitry Baryshkov #size-cells = <0>; 643e5813b15SDmitry Baryshkov status = "disabled"; 644e5813b15SDmitry Baryshkov }; 645e5813b15SDmitry Baryshkov 646e5813b15SDmitry Baryshkov spi17: spi@88c000 { 647e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 648e5813b15SDmitry Baryshkov reg = <0 0x0088c000 0 0x4000>; 649e5813b15SDmitry Baryshkov clock-names = "se"; 650e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 651e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 652e5813b15SDmitry Baryshkov #address-cells = <1>; 653e5813b15SDmitry Baryshkov #size-cells = <0>; 65401e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 65501e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 656e5813b15SDmitry Baryshkov status = "disabled"; 657e5813b15SDmitry Baryshkov }; 658e5813b15SDmitry Baryshkov 65908a9ae2dSDmitry Baryshkov uart17: serial@88c000 { 66008a9ae2dSDmitry Baryshkov compatible = "qcom,geni-uart"; 66108a9ae2dSDmitry Baryshkov reg = <0 0x0088c000 0 0x4000>; 66208a9ae2dSDmitry Baryshkov clock-names = "se"; 66308a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 66408a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 66508a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart17_default>; 66608a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 66701e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 66801e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 66908a9ae2dSDmitry Baryshkov status = "disabled"; 67008a9ae2dSDmitry Baryshkov }; 67108a9ae2dSDmitry Baryshkov 672e5813b15SDmitry Baryshkov i2c18: i2c@890000 { 673e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 674e5813b15SDmitry Baryshkov reg = <0 0x00890000 0 0x4000>; 675e5813b15SDmitry Baryshkov clock-names = "se"; 676e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 677e5813b15SDmitry Baryshkov pinctrl-names = "default"; 678e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c18_default>; 679e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 680e5813b15SDmitry Baryshkov #address-cells = <1>; 681e5813b15SDmitry Baryshkov #size-cells = <0>; 682e5813b15SDmitry Baryshkov status = "disabled"; 683e5813b15SDmitry Baryshkov }; 684e5813b15SDmitry Baryshkov 685e5813b15SDmitry Baryshkov spi18: spi@890000 { 686e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 687e5813b15SDmitry Baryshkov reg = <0 0x00890000 0 0x4000>; 688e5813b15SDmitry Baryshkov clock-names = "se"; 689e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 690e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 691e5813b15SDmitry Baryshkov #address-cells = <1>; 692e5813b15SDmitry Baryshkov #size-cells = <0>; 69301e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 69401e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 695e5813b15SDmitry Baryshkov status = "disabled"; 696e5813b15SDmitry Baryshkov }; 697e5813b15SDmitry Baryshkov 69808a9ae2dSDmitry Baryshkov uart18: serial@890000 { 69908a9ae2dSDmitry Baryshkov compatible = "qcom,geni-uart"; 70008a9ae2dSDmitry Baryshkov reg = <0 0x00890000 0 0x4000>; 70108a9ae2dSDmitry Baryshkov clock-names = "se"; 70208a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 70308a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 70408a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart18_default>; 70508a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 70601e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 70701e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 70808a9ae2dSDmitry Baryshkov status = "disabled"; 70908a9ae2dSDmitry Baryshkov }; 71008a9ae2dSDmitry Baryshkov 711e5813b15SDmitry Baryshkov i2c19: i2c@894000 { 712e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 713e5813b15SDmitry Baryshkov reg = <0 0x00894000 0 0x4000>; 714e5813b15SDmitry Baryshkov clock-names = "se"; 715e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 716e5813b15SDmitry Baryshkov pinctrl-names = "default"; 717e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c19_default>; 718e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 719e5813b15SDmitry Baryshkov #address-cells = <1>; 720e5813b15SDmitry Baryshkov #size-cells = <0>; 721e5813b15SDmitry Baryshkov status = "disabled"; 722e5813b15SDmitry Baryshkov }; 723e5813b15SDmitry Baryshkov 724e5813b15SDmitry Baryshkov spi19: spi@894000 { 725e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 726e5813b15SDmitry Baryshkov reg = <0 0x00894000 0 0x4000>; 727e5813b15SDmitry Baryshkov clock-names = "se"; 728e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 729e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 730e5813b15SDmitry Baryshkov #address-cells = <1>; 731e5813b15SDmitry Baryshkov #size-cells = <0>; 73201e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 73301e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 734e5813b15SDmitry Baryshkov status = "disabled"; 735e5813b15SDmitry Baryshkov }; 736e5813b15SDmitry Baryshkov }; 737e5813b15SDmitry Baryshkov 738*15049bb5SKonrad Dybcio gpi_dma0: dma-controller@900000 { 739*15049bb5SKonrad Dybcio compatible = "qcom,sm8250-gpi-dma"; 740*15049bb5SKonrad Dybcio reg = <0 0x00900000 0 0x70000>; 741*15049bb5SKonrad Dybcio interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 742*15049bb5SKonrad Dybcio <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 743*15049bb5SKonrad Dybcio <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 744*15049bb5SKonrad Dybcio <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 745*15049bb5SKonrad Dybcio <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 746*15049bb5SKonrad Dybcio <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 747*15049bb5SKonrad Dybcio <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 748*15049bb5SKonrad Dybcio <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 749*15049bb5SKonrad Dybcio <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 750*15049bb5SKonrad Dybcio <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 751*15049bb5SKonrad Dybcio <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 752*15049bb5SKonrad Dybcio <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 753*15049bb5SKonrad Dybcio <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 754*15049bb5SKonrad Dybcio dma-channels = <15>; 755*15049bb5SKonrad Dybcio dma-channel-mask = <0x7ff>; 756*15049bb5SKonrad Dybcio iommus = <&apps_smmu 0x5b6 0x0>; 757*15049bb5SKonrad Dybcio #dma-cells = <3>; 758*15049bb5SKonrad Dybcio status = "disabled"; 759*15049bb5SKonrad Dybcio }; 760*15049bb5SKonrad Dybcio 761e5813b15SDmitry Baryshkov qupv3_id_0: geniqup@9c0000 { 762e5813b15SDmitry Baryshkov compatible = "qcom,geni-se-qup"; 763e5813b15SDmitry Baryshkov reg = <0x0 0x009c0000 0x0 0x6000>; 764e5813b15SDmitry Baryshkov clock-names = "m-ahb", "s-ahb"; 765e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 766e5813b15SDmitry Baryshkov <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 767e5813b15SDmitry Baryshkov #address-cells = <2>; 768e5813b15SDmitry Baryshkov #size-cells = <2>; 76985309393SDmitry Baryshkov iommus = <&apps_smmu 0x5a3 0x0>; 770e5813b15SDmitry Baryshkov ranges; 771e5813b15SDmitry Baryshkov status = "disabled"; 772e5813b15SDmitry Baryshkov 773e5813b15SDmitry Baryshkov i2c0: i2c@980000 { 774e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 775e5813b15SDmitry Baryshkov reg = <0 0x00980000 0 0x4000>; 776e5813b15SDmitry Baryshkov clock-names = "se"; 777e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 778e5813b15SDmitry Baryshkov pinctrl-names = "default"; 779e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c0_default>; 780e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 781e5813b15SDmitry Baryshkov #address-cells = <1>; 782e5813b15SDmitry Baryshkov #size-cells = <0>; 783e5813b15SDmitry Baryshkov status = "disabled"; 784e5813b15SDmitry Baryshkov }; 785e5813b15SDmitry Baryshkov 786e5813b15SDmitry Baryshkov spi0: spi@980000 { 787e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 788e5813b15SDmitry Baryshkov reg = <0 0x00980000 0 0x4000>; 789e5813b15SDmitry Baryshkov clock-names = "se"; 790e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 791e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 792e5813b15SDmitry Baryshkov #address-cells = <1>; 793e5813b15SDmitry Baryshkov #size-cells = <0>; 79401e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 79501e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 796e5813b15SDmitry Baryshkov status = "disabled"; 797e5813b15SDmitry Baryshkov }; 798e5813b15SDmitry Baryshkov 799e5813b15SDmitry Baryshkov i2c1: i2c@984000 { 800e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 801e5813b15SDmitry Baryshkov reg = <0 0x00984000 0 0x4000>; 802e5813b15SDmitry Baryshkov clock-names = "se"; 803e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 804e5813b15SDmitry Baryshkov pinctrl-names = "default"; 805e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c1_default>; 806e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 807e5813b15SDmitry Baryshkov #address-cells = <1>; 808e5813b15SDmitry Baryshkov #size-cells = <0>; 809e5813b15SDmitry Baryshkov status = "disabled"; 810e5813b15SDmitry Baryshkov }; 811e5813b15SDmitry Baryshkov 812e5813b15SDmitry Baryshkov spi1: spi@984000 { 813e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 814e5813b15SDmitry Baryshkov reg = <0 0x00984000 0 0x4000>; 815e5813b15SDmitry Baryshkov clock-names = "se"; 816e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 817e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 818e5813b15SDmitry Baryshkov #address-cells = <1>; 819e5813b15SDmitry Baryshkov #size-cells = <0>; 82001e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 82101e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 822e5813b15SDmitry Baryshkov status = "disabled"; 823e5813b15SDmitry Baryshkov }; 824e5813b15SDmitry Baryshkov 825e5813b15SDmitry Baryshkov i2c2: i2c@988000 { 826e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 827e5813b15SDmitry Baryshkov reg = <0 0x00988000 0 0x4000>; 828e5813b15SDmitry Baryshkov clock-names = "se"; 829e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 830e5813b15SDmitry Baryshkov pinctrl-names = "default"; 831e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c2_default>; 832e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 833e5813b15SDmitry Baryshkov #address-cells = <1>; 834e5813b15SDmitry Baryshkov #size-cells = <0>; 835e5813b15SDmitry Baryshkov status = "disabled"; 836e5813b15SDmitry Baryshkov }; 837e5813b15SDmitry Baryshkov 838e5813b15SDmitry Baryshkov spi2: spi@988000 { 839e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 840e5813b15SDmitry Baryshkov reg = <0 0x00988000 0 0x4000>; 841e5813b15SDmitry Baryshkov clock-names = "se"; 842e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 843e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 844e5813b15SDmitry Baryshkov #address-cells = <1>; 845e5813b15SDmitry Baryshkov #size-cells = <0>; 84601e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 84701e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 848e5813b15SDmitry Baryshkov status = "disabled"; 849e5813b15SDmitry Baryshkov }; 850e5813b15SDmitry Baryshkov 85108a9ae2dSDmitry Baryshkov uart2: serial@988000 { 85208a9ae2dSDmitry Baryshkov compatible = "qcom,geni-debug-uart"; 85308a9ae2dSDmitry Baryshkov reg = <0 0x00988000 0 0x4000>; 85408a9ae2dSDmitry Baryshkov clock-names = "se"; 85508a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 85608a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 85708a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart2_default>; 85808a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 85901e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 86001e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 86108a9ae2dSDmitry Baryshkov status = "disabled"; 86208a9ae2dSDmitry Baryshkov }; 86308a9ae2dSDmitry Baryshkov 864e5813b15SDmitry Baryshkov i2c3: i2c@98c000 { 865e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 866e5813b15SDmitry Baryshkov reg = <0 0x0098c000 0 0x4000>; 867e5813b15SDmitry Baryshkov clock-names = "se"; 868e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 869e5813b15SDmitry Baryshkov pinctrl-names = "default"; 870e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c3_default>; 871e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 872e5813b15SDmitry Baryshkov #address-cells = <1>; 873e5813b15SDmitry Baryshkov #size-cells = <0>; 874e5813b15SDmitry Baryshkov status = "disabled"; 875e5813b15SDmitry Baryshkov }; 876e5813b15SDmitry Baryshkov 877e5813b15SDmitry Baryshkov spi3: spi@98c000 { 878e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 879e5813b15SDmitry Baryshkov reg = <0 0x0098c000 0 0x4000>; 880e5813b15SDmitry Baryshkov clock-names = "se"; 881e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 882e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 883e5813b15SDmitry Baryshkov #address-cells = <1>; 884e5813b15SDmitry Baryshkov #size-cells = <0>; 88501e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 88601e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 887e5813b15SDmitry Baryshkov status = "disabled"; 888e5813b15SDmitry Baryshkov }; 889e5813b15SDmitry Baryshkov 890e5813b15SDmitry Baryshkov i2c4: i2c@990000 { 891e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 892e5813b15SDmitry Baryshkov reg = <0 0x00990000 0 0x4000>; 893e5813b15SDmitry Baryshkov clock-names = "se"; 894e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 895e5813b15SDmitry Baryshkov pinctrl-names = "default"; 896e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c4_default>; 897e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 898e5813b15SDmitry Baryshkov #address-cells = <1>; 899e5813b15SDmitry Baryshkov #size-cells = <0>; 900e5813b15SDmitry Baryshkov status = "disabled"; 901e5813b15SDmitry Baryshkov }; 902e5813b15SDmitry Baryshkov 903e5813b15SDmitry Baryshkov spi4: spi@990000 { 904e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 905e5813b15SDmitry Baryshkov reg = <0 0x00990000 0 0x4000>; 906e5813b15SDmitry Baryshkov clock-names = "se"; 907e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 908e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 909e5813b15SDmitry Baryshkov #address-cells = <1>; 910e5813b15SDmitry Baryshkov #size-cells = <0>; 91101e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 91201e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 913e5813b15SDmitry Baryshkov status = "disabled"; 914e5813b15SDmitry Baryshkov }; 915e5813b15SDmitry Baryshkov 916e5813b15SDmitry Baryshkov i2c5: i2c@994000 { 917e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 918e5813b15SDmitry Baryshkov reg = <0 0x00994000 0 0x4000>; 919e5813b15SDmitry Baryshkov clock-names = "se"; 920e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 921e5813b15SDmitry Baryshkov pinctrl-names = "default"; 922e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c5_default>; 923e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 924e5813b15SDmitry Baryshkov #address-cells = <1>; 925e5813b15SDmitry Baryshkov #size-cells = <0>; 926e5813b15SDmitry Baryshkov status = "disabled"; 927e5813b15SDmitry Baryshkov }; 928e5813b15SDmitry Baryshkov 929e5813b15SDmitry Baryshkov spi5: spi@994000 { 930e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 931e5813b15SDmitry Baryshkov reg = <0 0x00994000 0 0x4000>; 932e5813b15SDmitry Baryshkov clock-names = "se"; 933e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 934e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 935e5813b15SDmitry Baryshkov #address-cells = <1>; 936e5813b15SDmitry Baryshkov #size-cells = <0>; 93701e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 93801e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 939e5813b15SDmitry Baryshkov status = "disabled"; 940e5813b15SDmitry Baryshkov }; 941e5813b15SDmitry Baryshkov 942e5813b15SDmitry Baryshkov i2c6: i2c@998000 { 943e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 944e5813b15SDmitry Baryshkov reg = <0 0x00998000 0 0x4000>; 945e5813b15SDmitry Baryshkov clock-names = "se"; 946e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 947e5813b15SDmitry Baryshkov pinctrl-names = "default"; 948e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c6_default>; 949e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 950e5813b15SDmitry Baryshkov #address-cells = <1>; 951e5813b15SDmitry Baryshkov #size-cells = <0>; 952e5813b15SDmitry Baryshkov status = "disabled"; 953e5813b15SDmitry Baryshkov }; 954e5813b15SDmitry Baryshkov 955e5813b15SDmitry Baryshkov spi6: spi@998000 { 956e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 957e5813b15SDmitry Baryshkov reg = <0 0x00998000 0 0x4000>; 958e5813b15SDmitry Baryshkov clock-names = "se"; 959e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 960e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 961e5813b15SDmitry Baryshkov #address-cells = <1>; 962e5813b15SDmitry Baryshkov #size-cells = <0>; 96301e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 96401e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 965e5813b15SDmitry Baryshkov status = "disabled"; 966e5813b15SDmitry Baryshkov }; 967e5813b15SDmitry Baryshkov 96808a9ae2dSDmitry Baryshkov uart6: serial@998000 { 96908a9ae2dSDmitry Baryshkov compatible = "qcom,geni-uart"; 97008a9ae2dSDmitry Baryshkov reg = <0 0x00998000 0 0x4000>; 97108a9ae2dSDmitry Baryshkov clock-names = "se"; 97208a9ae2dSDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 97308a9ae2dSDmitry Baryshkov pinctrl-names = "default"; 97408a9ae2dSDmitry Baryshkov pinctrl-0 = <&qup_uart6_default>; 97508a9ae2dSDmitry Baryshkov interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 97601e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 97701e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 97808a9ae2dSDmitry Baryshkov status = "disabled"; 97908a9ae2dSDmitry Baryshkov }; 98008a9ae2dSDmitry Baryshkov 981e5813b15SDmitry Baryshkov i2c7: i2c@99c000 { 982e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 983e5813b15SDmitry Baryshkov reg = <0 0x0099c000 0 0x4000>; 984e5813b15SDmitry Baryshkov clock-names = "se"; 985e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 986e5813b15SDmitry Baryshkov pinctrl-names = "default"; 987e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c7_default>; 988e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 989e5813b15SDmitry Baryshkov #address-cells = <1>; 990e5813b15SDmitry Baryshkov #size-cells = <0>; 991e5813b15SDmitry Baryshkov status = "disabled"; 992e5813b15SDmitry Baryshkov }; 993e5813b15SDmitry Baryshkov 994e5813b15SDmitry Baryshkov spi7: spi@99c000 { 995e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 996e5813b15SDmitry Baryshkov reg = <0 0x0099c000 0 0x4000>; 997e5813b15SDmitry Baryshkov clock-names = "se"; 998e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 999e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1000e5813b15SDmitry Baryshkov #address-cells = <1>; 1001e5813b15SDmitry Baryshkov #size-cells = <0>; 100201e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 100301e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 1004e5813b15SDmitry Baryshkov status = "disabled"; 1005e5813b15SDmitry Baryshkov }; 1006e5813b15SDmitry Baryshkov }; 1007e5813b15SDmitry Baryshkov 1008*15049bb5SKonrad Dybcio gpi_dma1: dma-controller@a00000 { 1009*15049bb5SKonrad Dybcio compatible = "qcom,sm8250-gpi-dma"; 1010*15049bb5SKonrad Dybcio reg = <0 0x00a00000 0 0x70000>; 1011*15049bb5SKonrad Dybcio interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1012*15049bb5SKonrad Dybcio <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1013*15049bb5SKonrad Dybcio <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1014*15049bb5SKonrad Dybcio <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1015*15049bb5SKonrad Dybcio <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1016*15049bb5SKonrad Dybcio <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1017*15049bb5SKonrad Dybcio <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1018*15049bb5SKonrad Dybcio <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1019*15049bb5SKonrad Dybcio <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1020*15049bb5SKonrad Dybcio <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1021*15049bb5SKonrad Dybcio dma-channels = <10>; 1022*15049bb5SKonrad Dybcio dma-channel-mask = <0x3f>; 1023*15049bb5SKonrad Dybcio iommus = <&apps_smmu 0x56 0x0>; 1024*15049bb5SKonrad Dybcio #dma-cells = <3>; 1025*15049bb5SKonrad Dybcio status = "disabled"; 1026*15049bb5SKonrad Dybcio }; 1027*15049bb5SKonrad Dybcio 102860378f1aSVenkata Narendra Kumar Gutta qupv3_id_1: geniqup@ac0000 { 102960378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,geni-se-qup"; 103060378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x00ac0000 0x0 0x6000>; 103160378f1aSVenkata Narendra Kumar Gutta clock-names = "m-ahb", "s-ahb"; 1032fe3dfc25SJonathan Marek clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1033fe3dfc25SJonathan Marek <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 103460378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 103560378f1aSVenkata Narendra Kumar Gutta #size-cells = <2>; 103685309393SDmitry Baryshkov iommus = <&apps_smmu 0x43 0x0>; 103760378f1aSVenkata Narendra Kumar Gutta ranges; 103860378f1aSVenkata Narendra Kumar Gutta status = "disabled"; 103960378f1aSVenkata Narendra Kumar Gutta 1040e5813b15SDmitry Baryshkov i2c8: i2c@a80000 { 1041e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1042e5813b15SDmitry Baryshkov reg = <0 0x00a80000 0 0x4000>; 1043e5813b15SDmitry Baryshkov clock-names = "se"; 1044e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1045e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1046e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c8_default>; 1047e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1048e5813b15SDmitry Baryshkov #address-cells = <1>; 1049e5813b15SDmitry Baryshkov #size-cells = <0>; 1050e5813b15SDmitry Baryshkov status = "disabled"; 1051e5813b15SDmitry Baryshkov }; 1052e5813b15SDmitry Baryshkov 1053e5813b15SDmitry Baryshkov spi8: spi@a80000 { 1054e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1055e5813b15SDmitry Baryshkov reg = <0 0x00a80000 0 0x4000>; 1056e5813b15SDmitry Baryshkov clock-names = "se"; 1057e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1058e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1059e5813b15SDmitry Baryshkov #address-cells = <1>; 1060e5813b15SDmitry Baryshkov #size-cells = <0>; 106101e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 106201e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 1063e5813b15SDmitry Baryshkov status = "disabled"; 1064e5813b15SDmitry Baryshkov }; 1065e5813b15SDmitry Baryshkov 1066e5813b15SDmitry Baryshkov i2c9: i2c@a84000 { 1067e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1068e5813b15SDmitry Baryshkov reg = <0 0x00a84000 0 0x4000>; 1069e5813b15SDmitry Baryshkov clock-names = "se"; 1070e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1071e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1072e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c9_default>; 1073e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1074e5813b15SDmitry Baryshkov #address-cells = <1>; 1075e5813b15SDmitry Baryshkov #size-cells = <0>; 1076e5813b15SDmitry Baryshkov status = "disabled"; 1077e5813b15SDmitry Baryshkov }; 1078e5813b15SDmitry Baryshkov 1079e5813b15SDmitry Baryshkov spi9: spi@a84000 { 1080e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1081e5813b15SDmitry Baryshkov reg = <0 0x00a84000 0 0x4000>; 1082e5813b15SDmitry Baryshkov clock-names = "se"; 1083e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1084e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1085e5813b15SDmitry Baryshkov #address-cells = <1>; 1086e5813b15SDmitry Baryshkov #size-cells = <0>; 108701e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 108801e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 1089e5813b15SDmitry Baryshkov status = "disabled"; 1090e5813b15SDmitry Baryshkov }; 1091e5813b15SDmitry Baryshkov 1092e5813b15SDmitry Baryshkov i2c10: i2c@a88000 { 1093e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1094e5813b15SDmitry Baryshkov reg = <0 0x00a88000 0 0x4000>; 1095e5813b15SDmitry Baryshkov clock-names = "se"; 1096e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1097e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1098e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c10_default>; 1099e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1100e5813b15SDmitry Baryshkov #address-cells = <1>; 1101e5813b15SDmitry Baryshkov #size-cells = <0>; 1102e5813b15SDmitry Baryshkov status = "disabled"; 1103e5813b15SDmitry Baryshkov }; 1104e5813b15SDmitry Baryshkov 1105e5813b15SDmitry Baryshkov spi10: spi@a88000 { 1106e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1107e5813b15SDmitry Baryshkov reg = <0 0x00a88000 0 0x4000>; 1108e5813b15SDmitry Baryshkov clock-names = "se"; 1109e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1110e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1111e5813b15SDmitry Baryshkov #address-cells = <1>; 1112e5813b15SDmitry Baryshkov #size-cells = <0>; 111301e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 111401e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 1115e5813b15SDmitry Baryshkov status = "disabled"; 1116e5813b15SDmitry Baryshkov }; 1117e5813b15SDmitry Baryshkov 1118e5813b15SDmitry Baryshkov i2c11: i2c@a8c000 { 1119e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1120e5813b15SDmitry Baryshkov reg = <0 0x00a8c000 0 0x4000>; 1121e5813b15SDmitry Baryshkov clock-names = "se"; 1122e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1123e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1124e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c11_default>; 1125e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1126e5813b15SDmitry Baryshkov #address-cells = <1>; 1127e5813b15SDmitry Baryshkov #size-cells = <0>; 1128e5813b15SDmitry Baryshkov status = "disabled"; 1129e5813b15SDmitry Baryshkov }; 1130e5813b15SDmitry Baryshkov 1131e5813b15SDmitry Baryshkov spi11: spi@a8c000 { 1132e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1133e5813b15SDmitry Baryshkov reg = <0 0x00a8c000 0 0x4000>; 1134e5813b15SDmitry Baryshkov clock-names = "se"; 1135e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1136e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1137e5813b15SDmitry Baryshkov #address-cells = <1>; 1138e5813b15SDmitry Baryshkov #size-cells = <0>; 113901e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 114001e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 1141e5813b15SDmitry Baryshkov status = "disabled"; 1142e5813b15SDmitry Baryshkov }; 1143e5813b15SDmitry Baryshkov 1144e5813b15SDmitry Baryshkov i2c12: i2c@a90000 { 1145e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1146e5813b15SDmitry Baryshkov reg = <0 0x00a90000 0 0x4000>; 1147e5813b15SDmitry Baryshkov clock-names = "se"; 1148e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1149e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1150e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c12_default>; 1151e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1152e5813b15SDmitry Baryshkov #address-cells = <1>; 1153e5813b15SDmitry Baryshkov #size-cells = <0>; 1154e5813b15SDmitry Baryshkov status = "disabled"; 1155e5813b15SDmitry Baryshkov }; 1156e5813b15SDmitry Baryshkov 1157e5813b15SDmitry Baryshkov spi12: spi@a90000 { 1158e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1159e5813b15SDmitry Baryshkov reg = <0 0x00a90000 0 0x4000>; 1160e5813b15SDmitry Baryshkov clock-names = "se"; 1161e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1162e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1163e5813b15SDmitry Baryshkov #address-cells = <1>; 1164e5813b15SDmitry Baryshkov #size-cells = <0>; 116501e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 116601e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 1167e5813b15SDmitry Baryshkov status = "disabled"; 1168e5813b15SDmitry Baryshkov }; 1169e5813b15SDmitry Baryshkov 1170bb1dfb4dSManivannan Sadhasivam uart12: serial@a90000 { 117160378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,geni-debug-uart"; 117260378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x00a90000 0x0 0x4000>; 117360378f1aSVenkata Narendra Kumar Gutta clock-names = "se"; 1174fe3dfc25SJonathan Marek clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1175bb1dfb4dSManivannan Sadhasivam pinctrl-names = "default"; 1176bb1dfb4dSManivannan Sadhasivam pinctrl-0 = <&qup_uart12_default>; 117760378f1aSVenkata Narendra Kumar Gutta interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 117801e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 117901e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 118060378f1aSVenkata Narendra Kumar Gutta status = "disabled"; 118160378f1aSVenkata Narendra Kumar Gutta }; 1182e5813b15SDmitry Baryshkov 1183e5813b15SDmitry Baryshkov i2c13: i2c@a94000 { 1184e5813b15SDmitry Baryshkov compatible = "qcom,geni-i2c"; 1185e5813b15SDmitry Baryshkov reg = <0 0x00a94000 0 0x4000>; 1186e5813b15SDmitry Baryshkov clock-names = "se"; 1187e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1188e5813b15SDmitry Baryshkov pinctrl-names = "default"; 1189e5813b15SDmitry Baryshkov pinctrl-0 = <&qup_i2c13_default>; 1190e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1191e5813b15SDmitry Baryshkov #address-cells = <1>; 1192e5813b15SDmitry Baryshkov #size-cells = <0>; 1193e5813b15SDmitry Baryshkov status = "disabled"; 1194e5813b15SDmitry Baryshkov }; 1195e5813b15SDmitry Baryshkov 1196e5813b15SDmitry Baryshkov spi13: spi@a94000 { 1197e5813b15SDmitry Baryshkov compatible = "qcom,geni-spi"; 1198e5813b15SDmitry Baryshkov reg = <0 0x00a94000 0 0x4000>; 1199e5813b15SDmitry Baryshkov clock-names = "se"; 1200e5813b15SDmitry Baryshkov clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1201e5813b15SDmitry Baryshkov interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1202e5813b15SDmitry Baryshkov #address-cells = <1>; 1203e5813b15SDmitry Baryshkov #size-cells = <0>; 120401e869ccSDmitry Baryshkov power-domains = <&rpmhpd SM8250_CX>; 120501e869ccSDmitry Baryshkov operating-points-v2 = <&qup_opp_table>; 1206e5813b15SDmitry Baryshkov status = "disabled"; 1207e5813b15SDmitry Baryshkov }; 120860378f1aSVenkata Narendra Kumar Gutta }; 120960378f1aSVenkata Narendra Kumar Gutta 1210e7e41a20SJonathan Marek config_noc: interconnect@1500000 { 1211e7e41a20SJonathan Marek compatible = "qcom,sm8250-config-noc"; 1212e7e41a20SJonathan Marek reg = <0 0x01500000 0 0xa580>; 1213e7e41a20SJonathan Marek #interconnect-cells = <1>; 1214e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1215e7e41a20SJonathan Marek }; 1216e7e41a20SJonathan Marek 1217e7e41a20SJonathan Marek system_noc: interconnect@1620000 { 1218e7e41a20SJonathan Marek compatible = "qcom,sm8250-system-noc"; 1219e7e41a20SJonathan Marek reg = <0 0x01620000 0 0x1c200>; 1220e7e41a20SJonathan Marek #interconnect-cells = <1>; 1221e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1222e7e41a20SJonathan Marek }; 1223e7e41a20SJonathan Marek 1224e7e41a20SJonathan Marek mc_virt: interconnect@163d000 { 1225e7e41a20SJonathan Marek compatible = "qcom,sm8250-mc-virt"; 1226e7e41a20SJonathan Marek reg = <0 0x0163d000 0 0x1000>; 1227e7e41a20SJonathan Marek #interconnect-cells = <1>; 1228e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1229e7e41a20SJonathan Marek }; 1230e7e41a20SJonathan Marek 1231e7e41a20SJonathan Marek aggre1_noc: interconnect@16e0000 { 1232e7e41a20SJonathan Marek compatible = "qcom,sm8250-aggre1-noc"; 1233e7e41a20SJonathan Marek reg = <0 0x016e0000 0 0x1f180>; 1234e7e41a20SJonathan Marek #interconnect-cells = <1>; 1235e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1236e7e41a20SJonathan Marek }; 1237e7e41a20SJonathan Marek 1238e7e41a20SJonathan Marek aggre2_noc: interconnect@1700000 { 1239e7e41a20SJonathan Marek compatible = "qcom,sm8250-aggre2-noc"; 1240e7e41a20SJonathan Marek reg = <0 0x01700000 0 0x33000>; 1241e7e41a20SJonathan Marek #interconnect-cells = <1>; 1242e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1243e7e41a20SJonathan Marek }; 1244e7e41a20SJonathan Marek 1245e7e41a20SJonathan Marek compute_noc: interconnect@1733000 { 1246e7e41a20SJonathan Marek compatible = "qcom,sm8250-compute-noc"; 1247e7e41a20SJonathan Marek reg = <0 0x01733000 0 0xa180>; 1248e7e41a20SJonathan Marek #interconnect-cells = <1>; 1249e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1250e7e41a20SJonathan Marek }; 1251e7e41a20SJonathan Marek 1252e7e41a20SJonathan Marek mmss_noc: interconnect@1740000 { 1253e7e41a20SJonathan Marek compatible = "qcom,sm8250-mmss-noc"; 1254e7e41a20SJonathan Marek reg = <0 0x01740000 0 0x1f080>; 1255e7e41a20SJonathan Marek #interconnect-cells = <1>; 1256e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1257e7e41a20SJonathan Marek }; 1258e7e41a20SJonathan Marek 1259e53bdfc0SManivannan Sadhasivam pcie0: pci@1c00000 { 1260e53bdfc0SManivannan Sadhasivam compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1261e53bdfc0SManivannan Sadhasivam reg = <0 0x01c00000 0 0x3000>, 1262e53bdfc0SManivannan Sadhasivam <0 0x60000000 0 0xf1d>, 1263e53bdfc0SManivannan Sadhasivam <0 0x60000f20 0 0xa8>, 1264e53bdfc0SManivannan Sadhasivam <0 0x60001000 0 0x1000>, 1265e53bdfc0SManivannan Sadhasivam <0 0x60100000 0 0x100000>; 1266e53bdfc0SManivannan Sadhasivam reg-names = "parf", "dbi", "elbi", "atu", "config"; 1267e53bdfc0SManivannan Sadhasivam device_type = "pci"; 1268e53bdfc0SManivannan Sadhasivam linux,pci-domain = <0>; 1269e53bdfc0SManivannan Sadhasivam bus-range = <0x00 0xff>; 1270e53bdfc0SManivannan Sadhasivam num-lanes = <1>; 1271e53bdfc0SManivannan Sadhasivam 1272e53bdfc0SManivannan Sadhasivam #address-cells = <3>; 1273e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1274e53bdfc0SManivannan Sadhasivam 1275e53bdfc0SManivannan Sadhasivam ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1276e53bdfc0SManivannan Sadhasivam <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1277e53bdfc0SManivannan Sadhasivam 1278e53bdfc0SManivannan Sadhasivam interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1279e53bdfc0SManivannan Sadhasivam interrupt-names = "msi"; 1280e53bdfc0SManivannan Sadhasivam #interrupt-cells = <1>; 1281e53bdfc0SManivannan Sadhasivam interrupt-map-mask = <0 0 0 0x7>; 1282e53bdfc0SManivannan Sadhasivam interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1283e53bdfc0SManivannan Sadhasivam <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1284e53bdfc0SManivannan Sadhasivam <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1285e53bdfc0SManivannan Sadhasivam <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1286e53bdfc0SManivannan Sadhasivam 1287e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1288e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_AUX_CLK>, 1289e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1290e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1291e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1292e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1293e53bdfc0SManivannan Sadhasivam <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1294e53bdfc0SManivannan Sadhasivam <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1295e53bdfc0SManivannan Sadhasivam clock-names = "pipe", 1296e53bdfc0SManivannan Sadhasivam "aux", 1297e53bdfc0SManivannan Sadhasivam "cfg", 1298e53bdfc0SManivannan Sadhasivam "bus_master", 1299e53bdfc0SManivannan Sadhasivam "bus_slave", 1300e53bdfc0SManivannan Sadhasivam "slave_q2a", 1301e53bdfc0SManivannan Sadhasivam "tbu", 1302e53bdfc0SManivannan Sadhasivam "ddrss_sf_tbu"; 1303e53bdfc0SManivannan Sadhasivam 1304e53bdfc0SManivannan Sadhasivam iommus = <&apps_smmu 0x1c00 0x7f>; 1305e53bdfc0SManivannan Sadhasivam iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1306e53bdfc0SManivannan Sadhasivam <0x100 &apps_smmu 0x1c01 0x1>; 1307e53bdfc0SManivannan Sadhasivam 1308e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_0_BCR>; 1309e53bdfc0SManivannan Sadhasivam reset-names = "pci"; 1310e53bdfc0SManivannan Sadhasivam 1311e53bdfc0SManivannan Sadhasivam power-domains = <&gcc PCIE_0_GDSC>; 1312e53bdfc0SManivannan Sadhasivam 1313e53bdfc0SManivannan Sadhasivam phys = <&pcie0_lane>; 1314e53bdfc0SManivannan Sadhasivam phy-names = "pciephy"; 1315e53bdfc0SManivannan Sadhasivam 1316e53bdfc0SManivannan Sadhasivam status = "disabled"; 1317e53bdfc0SManivannan Sadhasivam }; 1318e53bdfc0SManivannan Sadhasivam 1319e53bdfc0SManivannan Sadhasivam pcie0_phy: phy@1c06000 { 1320e53bdfc0SManivannan Sadhasivam compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1321e53bdfc0SManivannan Sadhasivam reg = <0 0x01c06000 0 0x1c0>; 1322e53bdfc0SManivannan Sadhasivam #address-cells = <2>; 1323e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1324e53bdfc0SManivannan Sadhasivam ranges; 1325e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1326e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1327e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1328e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1329e53bdfc0SManivannan Sadhasivam clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1330e53bdfc0SManivannan Sadhasivam 1331e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1332e53bdfc0SManivannan Sadhasivam reset-names = "phy"; 1333e53bdfc0SManivannan Sadhasivam 1334e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1335e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <100000000>; 1336e53bdfc0SManivannan Sadhasivam 1337e53bdfc0SManivannan Sadhasivam status = "disabled"; 1338e53bdfc0SManivannan Sadhasivam 1339e53bdfc0SManivannan Sadhasivam pcie0_lane: lanes@1c06200 { 1340e53bdfc0SManivannan Sadhasivam reg = <0 0x1c06200 0 0x170>, /* tx */ 1341e53bdfc0SManivannan Sadhasivam <0 0x1c06400 0 0x200>, /* rx */ 1342e53bdfc0SManivannan Sadhasivam <0 0x1c06800 0 0x1f0>, /* pcs */ 1343e53bdfc0SManivannan Sadhasivam <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1344e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1345e53bdfc0SManivannan Sadhasivam clock-names = "pipe0"; 1346e53bdfc0SManivannan Sadhasivam 1347e53bdfc0SManivannan Sadhasivam #phy-cells = <0>; 1348e53bdfc0SManivannan Sadhasivam clock-output-names = "pcie_0_pipe_clk"; 1349e53bdfc0SManivannan Sadhasivam }; 1350e53bdfc0SManivannan Sadhasivam }; 1351e53bdfc0SManivannan Sadhasivam 1352e53bdfc0SManivannan Sadhasivam pcie1: pci@1c08000 { 1353e53bdfc0SManivannan Sadhasivam compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1354e53bdfc0SManivannan Sadhasivam reg = <0 0x01c08000 0 0x3000>, 1355e53bdfc0SManivannan Sadhasivam <0 0x40000000 0 0xf1d>, 1356e53bdfc0SManivannan Sadhasivam <0 0x40000f20 0 0xa8>, 1357e53bdfc0SManivannan Sadhasivam <0 0x40001000 0 0x1000>, 1358e53bdfc0SManivannan Sadhasivam <0 0x40100000 0 0x100000>; 1359e53bdfc0SManivannan Sadhasivam reg-names = "parf", "dbi", "elbi", "atu", "config"; 1360e53bdfc0SManivannan Sadhasivam device_type = "pci"; 1361e53bdfc0SManivannan Sadhasivam linux,pci-domain = <1>; 1362e53bdfc0SManivannan Sadhasivam bus-range = <0x00 0xff>; 1363e53bdfc0SManivannan Sadhasivam num-lanes = <2>; 1364e53bdfc0SManivannan Sadhasivam 1365e53bdfc0SManivannan Sadhasivam #address-cells = <3>; 1366e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1367e53bdfc0SManivannan Sadhasivam 1368e53bdfc0SManivannan Sadhasivam ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1369e53bdfc0SManivannan Sadhasivam <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1370e53bdfc0SManivannan Sadhasivam 1371e53bdfc0SManivannan Sadhasivam interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>; 1372e53bdfc0SManivannan Sadhasivam interrupt-names = "msi"; 1373e53bdfc0SManivannan Sadhasivam #interrupt-cells = <1>; 1374e53bdfc0SManivannan Sadhasivam interrupt-map-mask = <0 0 0 0x7>; 1375e53bdfc0SManivannan Sadhasivam interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1376e53bdfc0SManivannan Sadhasivam <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1377e53bdfc0SManivannan Sadhasivam <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1378e53bdfc0SManivannan Sadhasivam <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1379e53bdfc0SManivannan Sadhasivam 1380e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1381e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_AUX_CLK>, 1382e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1383e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1384e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1385e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1386e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1387e53bdfc0SManivannan Sadhasivam <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1388e53bdfc0SManivannan Sadhasivam <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1389e53bdfc0SManivannan Sadhasivam clock-names = "pipe", 1390e53bdfc0SManivannan Sadhasivam "aux", 1391e53bdfc0SManivannan Sadhasivam "cfg", 1392e53bdfc0SManivannan Sadhasivam "bus_master", 1393e53bdfc0SManivannan Sadhasivam "bus_slave", 1394e53bdfc0SManivannan Sadhasivam "slave_q2a", 1395e53bdfc0SManivannan Sadhasivam "ref", 1396e53bdfc0SManivannan Sadhasivam "tbu", 1397e53bdfc0SManivannan Sadhasivam "ddrss_sf_tbu"; 1398e53bdfc0SManivannan Sadhasivam 1399e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1400e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <19200000>; 1401e53bdfc0SManivannan Sadhasivam 1402e53bdfc0SManivannan Sadhasivam iommus = <&apps_smmu 0x1c80 0x7f>; 1403e53bdfc0SManivannan Sadhasivam iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1404e53bdfc0SManivannan Sadhasivam <0x100 &apps_smmu 0x1c81 0x1>; 1405e53bdfc0SManivannan Sadhasivam 1406e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_1_BCR>; 1407e53bdfc0SManivannan Sadhasivam reset-names = "pci"; 1408e53bdfc0SManivannan Sadhasivam 1409e53bdfc0SManivannan Sadhasivam power-domains = <&gcc PCIE_1_GDSC>; 1410e53bdfc0SManivannan Sadhasivam 1411e53bdfc0SManivannan Sadhasivam phys = <&pcie1_lane>; 1412e53bdfc0SManivannan Sadhasivam phy-names = "pciephy"; 1413e53bdfc0SManivannan Sadhasivam 1414e53bdfc0SManivannan Sadhasivam status = "disabled"; 1415e53bdfc0SManivannan Sadhasivam }; 1416e53bdfc0SManivannan Sadhasivam 1417e53bdfc0SManivannan Sadhasivam pcie1_phy: phy@1c0e000 { 1418e53bdfc0SManivannan Sadhasivam compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1419e53bdfc0SManivannan Sadhasivam reg = <0 0x01c0e000 0 0x1c0>; 1420e53bdfc0SManivannan Sadhasivam #address-cells = <2>; 1421e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1422e53bdfc0SManivannan Sadhasivam ranges; 1423e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1424e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1425e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1426e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1427e53bdfc0SManivannan Sadhasivam clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1428e53bdfc0SManivannan Sadhasivam 1429e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1430e53bdfc0SManivannan Sadhasivam reset-names = "phy"; 1431e53bdfc0SManivannan Sadhasivam 1432e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1433e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <100000000>; 1434e53bdfc0SManivannan Sadhasivam 1435e53bdfc0SManivannan Sadhasivam status = "disabled"; 1436e53bdfc0SManivannan Sadhasivam 1437e53bdfc0SManivannan Sadhasivam pcie1_lane: lanes@1c0e200 { 1438e53bdfc0SManivannan Sadhasivam reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1439e53bdfc0SManivannan Sadhasivam <0 0x1c0e400 0 0x200>, /* rx0 */ 1440e53bdfc0SManivannan Sadhasivam <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1441e53bdfc0SManivannan Sadhasivam <0 0x1c0e600 0 0x170>, /* tx1 */ 1442e53bdfc0SManivannan Sadhasivam <0 0x1c0e800 0 0x200>, /* rx1 */ 1443e53bdfc0SManivannan Sadhasivam <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1444e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1445e53bdfc0SManivannan Sadhasivam clock-names = "pipe0"; 1446e53bdfc0SManivannan Sadhasivam 1447e53bdfc0SManivannan Sadhasivam #phy-cells = <0>; 1448e53bdfc0SManivannan Sadhasivam clock-output-names = "pcie_1_pipe_clk"; 1449e53bdfc0SManivannan Sadhasivam }; 1450e53bdfc0SManivannan Sadhasivam }; 1451e53bdfc0SManivannan Sadhasivam 1452e53bdfc0SManivannan Sadhasivam pcie2: pci@1c10000 { 1453e53bdfc0SManivannan Sadhasivam compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1454e53bdfc0SManivannan Sadhasivam reg = <0 0x01c10000 0 0x3000>, 1455e53bdfc0SManivannan Sadhasivam <0 0x64000000 0 0xf1d>, 1456e53bdfc0SManivannan Sadhasivam <0 0x64000f20 0 0xa8>, 1457e53bdfc0SManivannan Sadhasivam <0 0x64001000 0 0x1000>, 1458e53bdfc0SManivannan Sadhasivam <0 0x64100000 0 0x100000>; 1459e53bdfc0SManivannan Sadhasivam reg-names = "parf", "dbi", "elbi", "atu", "config"; 1460e53bdfc0SManivannan Sadhasivam device_type = "pci"; 1461e53bdfc0SManivannan Sadhasivam linux,pci-domain = <2>; 1462e53bdfc0SManivannan Sadhasivam bus-range = <0x00 0xff>; 1463e53bdfc0SManivannan Sadhasivam num-lanes = <2>; 1464e53bdfc0SManivannan Sadhasivam 1465e53bdfc0SManivannan Sadhasivam #address-cells = <3>; 1466e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1467e53bdfc0SManivannan Sadhasivam 1468e53bdfc0SManivannan Sadhasivam ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, 1469e53bdfc0SManivannan Sadhasivam <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 1470e53bdfc0SManivannan Sadhasivam 1471e53bdfc0SManivannan Sadhasivam interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; 1472e53bdfc0SManivannan Sadhasivam interrupt-names = "msi"; 1473e53bdfc0SManivannan Sadhasivam #interrupt-cells = <1>; 1474e53bdfc0SManivannan Sadhasivam interrupt-map-mask = <0 0 0 0x7>; 1475e53bdfc0SManivannan Sadhasivam interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1476e53bdfc0SManivannan Sadhasivam <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1477e53bdfc0SManivannan Sadhasivam <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1478e53bdfc0SManivannan Sadhasivam <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1479e53bdfc0SManivannan Sadhasivam 1480e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1481e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_AUX_CLK>, 1482e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1483e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1484e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 1485e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 1486e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1487e53bdfc0SManivannan Sadhasivam <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1488e53bdfc0SManivannan Sadhasivam <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1489e53bdfc0SManivannan Sadhasivam clock-names = "pipe", 1490e53bdfc0SManivannan Sadhasivam "aux", 1491e53bdfc0SManivannan Sadhasivam "cfg", 1492e53bdfc0SManivannan Sadhasivam "bus_master", 1493e53bdfc0SManivannan Sadhasivam "bus_slave", 1494e53bdfc0SManivannan Sadhasivam "slave_q2a", 1495e53bdfc0SManivannan Sadhasivam "ref", 1496e53bdfc0SManivannan Sadhasivam "tbu", 1497e53bdfc0SManivannan Sadhasivam "ddrss_sf_tbu"; 1498e53bdfc0SManivannan Sadhasivam 1499e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 1500e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <19200000>; 1501e53bdfc0SManivannan Sadhasivam 1502e53bdfc0SManivannan Sadhasivam iommus = <&apps_smmu 0x1d00 0x7f>; 1503e53bdfc0SManivannan Sadhasivam iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 1504e53bdfc0SManivannan Sadhasivam <0x100 &apps_smmu 0x1d01 0x1>; 1505e53bdfc0SManivannan Sadhasivam 1506e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_2_BCR>; 1507e53bdfc0SManivannan Sadhasivam reset-names = "pci"; 1508e53bdfc0SManivannan Sadhasivam 1509e53bdfc0SManivannan Sadhasivam power-domains = <&gcc PCIE_2_GDSC>; 1510e53bdfc0SManivannan Sadhasivam 1511e53bdfc0SManivannan Sadhasivam phys = <&pcie2_lane>; 1512e53bdfc0SManivannan Sadhasivam phy-names = "pciephy"; 1513e53bdfc0SManivannan Sadhasivam 1514e53bdfc0SManivannan Sadhasivam status = "disabled"; 1515e53bdfc0SManivannan Sadhasivam }; 1516e53bdfc0SManivannan Sadhasivam 1517e53bdfc0SManivannan Sadhasivam pcie2_phy: phy@1c16000 { 1518e53bdfc0SManivannan Sadhasivam compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 1519e53bdfc0SManivannan Sadhasivam reg = <0 0x1c16000 0 0x1c0>; 1520e53bdfc0SManivannan Sadhasivam #address-cells = <2>; 1521e53bdfc0SManivannan Sadhasivam #size-cells = <2>; 1522e53bdfc0SManivannan Sadhasivam ranges; 1523e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1524e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1525e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1526e53bdfc0SManivannan Sadhasivam <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1527e53bdfc0SManivannan Sadhasivam clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1528e53bdfc0SManivannan Sadhasivam 1529e53bdfc0SManivannan Sadhasivam resets = <&gcc GCC_PCIE_2_PHY_BCR>; 1530e53bdfc0SManivannan Sadhasivam reset-names = "phy"; 1531e53bdfc0SManivannan Sadhasivam 1532e53bdfc0SManivannan Sadhasivam assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1533e53bdfc0SManivannan Sadhasivam assigned-clock-rates = <100000000>; 1534e53bdfc0SManivannan Sadhasivam 1535e53bdfc0SManivannan Sadhasivam status = "disabled"; 1536e53bdfc0SManivannan Sadhasivam 1537dc2f8636SKonrad Dybcio pcie2_lane: lanes@1c16200 { 1538e53bdfc0SManivannan Sadhasivam reg = <0 0x1c16200 0 0x170>, /* tx0 */ 1539e53bdfc0SManivannan Sadhasivam <0 0x1c16400 0 0x200>, /* rx0 */ 1540e53bdfc0SManivannan Sadhasivam <0 0x1c16a00 0 0x1f0>, /* pcs */ 1541e53bdfc0SManivannan Sadhasivam <0 0x1c16600 0 0x170>, /* tx1 */ 1542e53bdfc0SManivannan Sadhasivam <0 0x1c16800 0 0x200>, /* rx1 */ 1543e53bdfc0SManivannan Sadhasivam <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1544e53bdfc0SManivannan Sadhasivam clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 1545e53bdfc0SManivannan Sadhasivam clock-names = "pipe0"; 1546e53bdfc0SManivannan Sadhasivam 1547e53bdfc0SManivannan Sadhasivam #phy-cells = <0>; 1548e53bdfc0SManivannan Sadhasivam clock-output-names = "pcie_2_pipe_clk"; 1549e53bdfc0SManivannan Sadhasivam }; 1550e53bdfc0SManivannan Sadhasivam }; 1551e53bdfc0SManivannan Sadhasivam 15526b9afd8fSJonathan Marek ufs_mem_hc: ufshc@1d84000 { 1553b7e2fba0SBryan O'Donoghue compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 1554b7e2fba0SBryan O'Donoghue "jedec,ufs-2.0"; 1555b7e2fba0SBryan O'Donoghue reg = <0 0x01d84000 0 0x3000>; 1556b7e2fba0SBryan O'Donoghue interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1557b7e2fba0SBryan O'Donoghue phys = <&ufs_mem_phy_lanes>; 1558b7e2fba0SBryan O'Donoghue phy-names = "ufsphy"; 1559b7e2fba0SBryan O'Donoghue lanes-per-direction = <2>; 1560b7e2fba0SBryan O'Donoghue #reset-cells = <1>; 1561b7e2fba0SBryan O'Donoghue resets = <&gcc GCC_UFS_PHY_BCR>; 1562b7e2fba0SBryan O'Donoghue reset-names = "rst"; 1563b7e2fba0SBryan O'Donoghue 1564b7e2fba0SBryan O'Donoghue power-domains = <&gcc UFS_PHY_GDSC>; 1565b7e2fba0SBryan O'Donoghue 1566a89441fcSJonathan Marek iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 1567a89441fcSJonathan Marek 1568b7e2fba0SBryan O'Donoghue clock-names = 1569b7e2fba0SBryan O'Donoghue "core_clk", 1570b7e2fba0SBryan O'Donoghue "bus_aggr_clk", 1571b7e2fba0SBryan O'Donoghue "iface_clk", 1572b7e2fba0SBryan O'Donoghue "core_clk_unipro", 1573b7e2fba0SBryan O'Donoghue "ref_clk", 1574b7e2fba0SBryan O'Donoghue "tx_lane0_sync_clk", 1575b7e2fba0SBryan O'Donoghue "rx_lane0_sync_clk", 1576b7e2fba0SBryan O'Donoghue "rx_lane1_sync_clk"; 1577b7e2fba0SBryan O'Donoghue clocks = 1578b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_AXI_CLK>, 1579b7e2fba0SBryan O'Donoghue <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1580b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_AHB_CLK>, 1581b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1582b7e2fba0SBryan O'Donoghue <&rpmhcc RPMH_CXO_CLK>, 1583b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1584b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1585b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1586b7e2fba0SBryan O'Donoghue freq-table-hz = 1587b7e2fba0SBryan O'Donoghue <37500000 300000000>, 1588b7e2fba0SBryan O'Donoghue <0 0>, 1589b7e2fba0SBryan O'Donoghue <0 0>, 1590b7e2fba0SBryan O'Donoghue <37500000 300000000>, 1591b7e2fba0SBryan O'Donoghue <0 0>, 1592b7e2fba0SBryan O'Donoghue <0 0>, 1593b7e2fba0SBryan O'Donoghue <0 0>, 1594b7e2fba0SBryan O'Donoghue <0 0>; 1595b7e2fba0SBryan O'Donoghue 1596b7e2fba0SBryan O'Donoghue status = "disabled"; 1597b7e2fba0SBryan O'Donoghue }; 1598b7e2fba0SBryan O'Donoghue 1599b7e2fba0SBryan O'Donoghue ufs_mem_phy: phy@1d87000 { 1600b7e2fba0SBryan O'Donoghue compatible = "qcom,sm8250-qmp-ufs-phy"; 1601b7e2fba0SBryan O'Donoghue reg = <0 0x01d87000 0 0x1c0>; 1602b7e2fba0SBryan O'Donoghue #address-cells = <2>; 1603b7e2fba0SBryan O'Donoghue #size-cells = <2>; 1604b7e2fba0SBryan O'Donoghue ranges; 1605b7e2fba0SBryan O'Donoghue clock-names = "ref", 1606b7e2fba0SBryan O'Donoghue "ref_aux"; 1607b7e2fba0SBryan O'Donoghue clocks = <&rpmhcc RPMH_CXO_CLK>, 1608b7e2fba0SBryan O'Donoghue <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1609b7e2fba0SBryan O'Donoghue 1610b7e2fba0SBryan O'Donoghue resets = <&ufs_mem_hc 0>; 1611b7e2fba0SBryan O'Donoghue reset-names = "ufsphy"; 1612b7e2fba0SBryan O'Donoghue status = "disabled"; 1613b7e2fba0SBryan O'Donoghue 1614b7e2fba0SBryan O'Donoghue ufs_mem_phy_lanes: lanes@1d87400 { 1615b7e2fba0SBryan O'Donoghue reg = <0 0x01d87400 0 0x108>, 1616b7e2fba0SBryan O'Donoghue <0 0x01d87600 0 0x1e0>, 1617b7e2fba0SBryan O'Donoghue <0 0x01d87c00 0 0x1dc>, 1618b7e2fba0SBryan O'Donoghue <0 0x01d87800 0 0x108>, 1619b7e2fba0SBryan O'Donoghue <0 0x01d87a00 0 0x1e0>; 1620b7e2fba0SBryan O'Donoghue #phy-cells = <0>; 1621b7e2fba0SBryan O'Donoghue }; 1622b7e2fba0SBryan O'Donoghue }; 1623b7e2fba0SBryan O'Donoghue 1624e7e41a20SJonathan Marek ipa_virt: interconnect@1e00000 { 1625e7e41a20SJonathan Marek compatible = "qcom,sm8250-ipa-virt"; 1626e7e41a20SJonathan Marek reg = <0 0x01e00000 0 0x1000>; 1627e7e41a20SJonathan Marek #interconnect-cells = <1>; 1628e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 1629e7e41a20SJonathan Marek }; 1630e7e41a20SJonathan Marek 1631dff0f49cSBjorn Andersson tcsr_mutex: hwlock@1f40000 { 1632dff0f49cSBjorn Andersson compatible = "qcom,tcsr-mutex"; 1633b9ec8cbcSJonathan Marek reg = <0x0 0x01f40000 0x0 0x40000>; 1634dff0f49cSBjorn Andersson #hwlock-cells = <1>; 163560378f1aSVenkata Narendra Kumar Gutta }; 163660378f1aSVenkata Narendra Kumar Gutta 1637768270caSSrinivas Kandagatla wsamacro: codec@3240000 { 1638768270caSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-wsa-macro"; 1639768270caSSrinivas Kandagatla reg = <0 0x03240000 0 0x1000>; 1640768270caSSrinivas Kandagatla clocks = <&audiocc 1>, 1641768270caSSrinivas Kandagatla <&audiocc 0>, 1642768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1643768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1644768270caSSrinivas Kandagatla <&aoncc 0>, 1645768270caSSrinivas Kandagatla <&vamacro>; 1646768270caSSrinivas Kandagatla 1647768270caSSrinivas Kandagatla clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 1648768270caSSrinivas Kandagatla 1649768270caSSrinivas Kandagatla #clock-cells = <0>; 1650768270caSSrinivas Kandagatla clock-frequency = <9600000>; 1651768270caSSrinivas Kandagatla clock-output-names = "mclk"; 1652768270caSSrinivas Kandagatla #sound-dai-cells = <1>; 1653768270caSSrinivas Kandagatla 1654768270caSSrinivas Kandagatla pinctrl-names = "default"; 1655768270caSSrinivas Kandagatla pinctrl-0 = <&wsa_swr_active>; 1656768270caSSrinivas Kandagatla }; 1657768270caSSrinivas Kandagatla 1658768270caSSrinivas Kandagatla swr0: soundwire-controller@3250000 { 1659768270caSSrinivas Kandagatla reg = <0 0x03250000 0 0x2000>; 1660768270caSSrinivas Kandagatla compatible = "qcom,soundwire-v1.5.1"; 1661768270caSSrinivas Kandagatla interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1662768270caSSrinivas Kandagatla clocks = <&wsamacro>; 1663768270caSSrinivas Kandagatla clock-names = "iface"; 1664768270caSSrinivas Kandagatla 1665768270caSSrinivas Kandagatla qcom,din-ports = <2>; 1666768270caSSrinivas Kandagatla qcom,dout-ports = <6>; 1667768270caSSrinivas Kandagatla 1668768270caSSrinivas Kandagatla qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 1669768270caSSrinivas Kandagatla qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 1670768270caSSrinivas Kandagatla qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 1671768270caSSrinivas Kandagatla qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 1672768270caSSrinivas Kandagatla 1673768270caSSrinivas Kandagatla #sound-dai-cells = <1>; 1674768270caSSrinivas Kandagatla #address-cells = <2>; 1675768270caSSrinivas Kandagatla #size-cells = <0>; 1676768270caSSrinivas Kandagatla }; 1677768270caSSrinivas Kandagatla 1678793bbd2dSSrinivas Kandagatla audiocc: clock-controller@3300000 { 1679793bbd2dSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-audiocc"; 1680793bbd2dSSrinivas Kandagatla reg = <0 0x03300000 0 0x30000>; 1681793bbd2dSSrinivas Kandagatla #clock-cells = <1>; 1682793bbd2dSSrinivas Kandagatla clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1683793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1684793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1685793bbd2dSSrinivas Kandagatla clock-names = "core", "audio", "bus"; 1686793bbd2dSSrinivas Kandagatla }; 1687793bbd2dSSrinivas Kandagatla 1688768270caSSrinivas Kandagatla vamacro: codec@3370000 { 1689768270caSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-va-macro"; 1690768270caSSrinivas Kandagatla reg = <0 0x03370000 0 0x1000>; 1691768270caSSrinivas Kandagatla clocks = <&aoncc 0>, 1692768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1693768270caSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1694768270caSSrinivas Kandagatla 1695768270caSSrinivas Kandagatla clock-names = "mclk", "macro", "dcodec"; 1696768270caSSrinivas Kandagatla 1697768270caSSrinivas Kandagatla #clock-cells = <0>; 1698768270caSSrinivas Kandagatla clock-frequency = <9600000>; 1699768270caSSrinivas Kandagatla clock-output-names = "fsgen"; 1700768270caSSrinivas Kandagatla #sound-dai-cells = <1>; 1701768270caSSrinivas Kandagatla }; 1702768270caSSrinivas Kandagatla 1703793bbd2dSSrinivas Kandagatla aoncc: clock-controller@3380000 { 1704793bbd2dSSrinivas Kandagatla compatible = "qcom,sm8250-lpass-aoncc"; 1705793bbd2dSSrinivas Kandagatla reg = <0 0x03380000 0 0x40000>; 1706793bbd2dSSrinivas Kandagatla #clock-cells = <1>; 1707793bbd2dSSrinivas Kandagatla clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1708793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1709793bbd2dSSrinivas Kandagatla <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1710793bbd2dSSrinivas Kandagatla clock-names = "core", "audio", "bus"; 1711793bbd2dSSrinivas Kandagatla }; 1712793bbd2dSSrinivas Kandagatla 17133160c1b8SSrinivas Kandagatla lpass_tlmm: pinctrl@33c0000{ 17143160c1b8SSrinivas Kandagatla compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 17153160c1b8SSrinivas Kandagatla reg = <0 0x033c0000 0x0 0x20000>, 17163160c1b8SSrinivas Kandagatla <0 0x03550000 0x0 0x10000>; 17173160c1b8SSrinivas Kandagatla gpio-controller; 17183160c1b8SSrinivas Kandagatla #gpio-cells = <2>; 17193160c1b8SSrinivas Kandagatla gpio-ranges = <&lpass_tlmm 0 0 14>; 17203160c1b8SSrinivas Kandagatla 17213160c1b8SSrinivas Kandagatla clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 17223160c1b8SSrinivas Kandagatla <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 17233160c1b8SSrinivas Kandagatla clock-names = "core", "audio"; 17243160c1b8SSrinivas Kandagatla 17253160c1b8SSrinivas Kandagatla wsa_swr_active: wsa-swr-active-pins { 17263160c1b8SSrinivas Kandagatla clk { 17273160c1b8SSrinivas Kandagatla pins = "gpio10"; 17283160c1b8SSrinivas Kandagatla function = "wsa_swr_clk"; 17293160c1b8SSrinivas Kandagatla drive-strength = <2>; 17303160c1b8SSrinivas Kandagatla slew-rate = <1>; 17313160c1b8SSrinivas Kandagatla bias-disable; 17323160c1b8SSrinivas Kandagatla }; 17333160c1b8SSrinivas Kandagatla 17343160c1b8SSrinivas Kandagatla data { 17353160c1b8SSrinivas Kandagatla pins = "gpio11"; 17363160c1b8SSrinivas Kandagatla function = "wsa_swr_data"; 17373160c1b8SSrinivas Kandagatla drive-strength = <2>; 17383160c1b8SSrinivas Kandagatla slew-rate = <1>; 17393160c1b8SSrinivas Kandagatla bias-bus-hold; 17403160c1b8SSrinivas Kandagatla 17413160c1b8SSrinivas Kandagatla }; 17423160c1b8SSrinivas Kandagatla }; 17433160c1b8SSrinivas Kandagatla 17443160c1b8SSrinivas Kandagatla wsa_swr_sleep: wsa-swr-sleep-pins { 17453160c1b8SSrinivas Kandagatla clk { 17463160c1b8SSrinivas Kandagatla pins = "gpio10"; 17473160c1b8SSrinivas Kandagatla function = "wsa_swr_clk"; 17483160c1b8SSrinivas Kandagatla drive-strength = <2>; 17493160c1b8SSrinivas Kandagatla input-enable; 17503160c1b8SSrinivas Kandagatla bias-pull-down; 17513160c1b8SSrinivas Kandagatla }; 17523160c1b8SSrinivas Kandagatla 17533160c1b8SSrinivas Kandagatla data { 17543160c1b8SSrinivas Kandagatla pins = "gpio11"; 17553160c1b8SSrinivas Kandagatla function = "wsa_swr_data"; 17563160c1b8SSrinivas Kandagatla drive-strength = <2>; 17573160c1b8SSrinivas Kandagatla input-enable; 17583160c1b8SSrinivas Kandagatla bias-pull-down; 17593160c1b8SSrinivas Kandagatla 17603160c1b8SSrinivas Kandagatla }; 17613160c1b8SSrinivas Kandagatla }; 17623160c1b8SSrinivas Kandagatla 17633160c1b8SSrinivas Kandagatla dmic01_active: dmic01-active-pins { 17643160c1b8SSrinivas Kandagatla clk { 17653160c1b8SSrinivas Kandagatla pins = "gpio6"; 17663160c1b8SSrinivas Kandagatla function = "dmic1_clk"; 17673160c1b8SSrinivas Kandagatla drive-strength = <8>; 17683160c1b8SSrinivas Kandagatla output-high; 17693160c1b8SSrinivas Kandagatla }; 17703160c1b8SSrinivas Kandagatla data { 17713160c1b8SSrinivas Kandagatla pins = "gpio7"; 17723160c1b8SSrinivas Kandagatla function = "dmic1_data"; 17733160c1b8SSrinivas Kandagatla drive-strength = <8>; 17743160c1b8SSrinivas Kandagatla input-enable; 17753160c1b8SSrinivas Kandagatla }; 17763160c1b8SSrinivas Kandagatla }; 17773160c1b8SSrinivas Kandagatla 17783160c1b8SSrinivas Kandagatla dmic01_sleep: dmic01-sleep-pins { 17793160c1b8SSrinivas Kandagatla clk { 17803160c1b8SSrinivas Kandagatla pins = "gpio6"; 17813160c1b8SSrinivas Kandagatla function = "dmic1_clk"; 17823160c1b8SSrinivas Kandagatla drive-strength = <2>; 17833160c1b8SSrinivas Kandagatla bias-disable; 17843160c1b8SSrinivas Kandagatla output-low; 17853160c1b8SSrinivas Kandagatla }; 17863160c1b8SSrinivas Kandagatla 17873160c1b8SSrinivas Kandagatla data { 17883160c1b8SSrinivas Kandagatla pins = "gpio7"; 17893160c1b8SSrinivas Kandagatla function = "dmic1_data"; 17903160c1b8SSrinivas Kandagatla drive-strength = <2>; 17913160c1b8SSrinivas Kandagatla pull-down; 17923160c1b8SSrinivas Kandagatla input-enable; 17933160c1b8SSrinivas Kandagatla }; 17943160c1b8SSrinivas Kandagatla }; 17953160c1b8SSrinivas Kandagatla }; 17963160c1b8SSrinivas Kandagatla 179704a3605bSJonathan Marek gpu: gpu@3d00000 { 179804a3605bSJonathan Marek compatible = "qcom,adreno-650.2", 17997c1dffd4SDmitry Baryshkov "qcom,adreno"; 180004a3605bSJonathan Marek #stream-id-cells = <16>; 180104a3605bSJonathan Marek 180204a3605bSJonathan Marek reg = <0 0x03d00000 0 0x40000>; 180304a3605bSJonathan Marek reg-names = "kgsl_3d0_reg_memory"; 180404a3605bSJonathan Marek 180504a3605bSJonathan Marek interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 180604a3605bSJonathan Marek 180704a3605bSJonathan Marek iommus = <&adreno_smmu 0 0x401>; 180804a3605bSJonathan Marek 180904a3605bSJonathan Marek operating-points-v2 = <&gpu_opp_table>; 181004a3605bSJonathan Marek 181104a3605bSJonathan Marek qcom,gmu = <&gmu>; 181204a3605bSJonathan Marek 181304a3605bSJonathan Marek zap-shader { 181404a3605bSJonathan Marek memory-region = <&gpu_mem>; 181504a3605bSJonathan Marek }; 181604a3605bSJonathan Marek 181704a3605bSJonathan Marek /* note: downstream checks gpu binning for 670 Mhz */ 181804a3605bSJonathan Marek gpu_opp_table: opp-table { 181904a3605bSJonathan Marek compatible = "operating-points-v2"; 182004a3605bSJonathan Marek 182104a3605bSJonathan Marek opp-670000000 { 182204a3605bSJonathan Marek opp-hz = /bits/ 64 <670000000>; 182304a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 182404a3605bSJonathan Marek }; 182504a3605bSJonathan Marek 182604a3605bSJonathan Marek opp-587000000 { 182704a3605bSJonathan Marek opp-hz = /bits/ 64 <587000000>; 182804a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 182904a3605bSJonathan Marek }; 183004a3605bSJonathan Marek 183104a3605bSJonathan Marek opp-525000000 { 183204a3605bSJonathan Marek opp-hz = /bits/ 64 <525000000>; 183304a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 183404a3605bSJonathan Marek }; 183504a3605bSJonathan Marek 183604a3605bSJonathan Marek opp-490000000 { 183704a3605bSJonathan Marek opp-hz = /bits/ 64 <490000000>; 183804a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 183904a3605bSJonathan Marek }; 184004a3605bSJonathan Marek 184104a3605bSJonathan Marek opp-441600000 { 184204a3605bSJonathan Marek opp-hz = /bits/ 64 <441600000>; 184304a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 184404a3605bSJonathan Marek }; 184504a3605bSJonathan Marek 184604a3605bSJonathan Marek opp-400000000 { 184704a3605bSJonathan Marek opp-hz = /bits/ 64 <400000000>; 184804a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 184904a3605bSJonathan Marek }; 185004a3605bSJonathan Marek 185104a3605bSJonathan Marek opp-305000000 { 185204a3605bSJonathan Marek opp-hz = /bits/ 64 <305000000>; 185304a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 185404a3605bSJonathan Marek }; 185504a3605bSJonathan Marek }; 185604a3605bSJonathan Marek }; 185704a3605bSJonathan Marek 185804a3605bSJonathan Marek gmu: gmu@3d6a000 { 185904a3605bSJonathan Marek compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 186004a3605bSJonathan Marek 186104a3605bSJonathan Marek reg = <0 0x03d6a000 0 0x30000>, 186204a3605bSJonathan Marek <0 0x3de0000 0 0x10000>, 186304a3605bSJonathan Marek <0 0xb290000 0 0x10000>, 186404a3605bSJonathan Marek <0 0xb490000 0 0x10000>; 186504a3605bSJonathan Marek reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 186604a3605bSJonathan Marek 186704a3605bSJonathan Marek interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 186804a3605bSJonathan Marek <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 186904a3605bSJonathan Marek interrupt-names = "hfi", "gmu"; 187004a3605bSJonathan Marek 18710e6aa9dbSJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 18720e6aa9dbSJonathan Marek <&gpucc GPU_CC_CX_GMU_CLK>, 18730e6aa9dbSJonathan Marek <&gpucc GPU_CC_CXO_CLK>, 187404a3605bSJonathan Marek <&gcc GCC_DDRSS_GPU_AXI_CLK>, 187504a3605bSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 187604a3605bSJonathan Marek clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 187704a3605bSJonathan Marek 18780e6aa9dbSJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>, 18790e6aa9dbSJonathan Marek <&gpucc GPU_GX_GDSC>; 188004a3605bSJonathan Marek power-domain-names = "cx", "gx"; 188104a3605bSJonathan Marek 188204a3605bSJonathan Marek iommus = <&adreno_smmu 5 0x400>; 188304a3605bSJonathan Marek 188404a3605bSJonathan Marek operating-points-v2 = <&gmu_opp_table>; 188504a3605bSJonathan Marek 188604a3605bSJonathan Marek gmu_opp_table: opp-table { 188704a3605bSJonathan Marek compatible = "operating-points-v2"; 188804a3605bSJonathan Marek 188904a3605bSJonathan Marek opp-200000000 { 189004a3605bSJonathan Marek opp-hz = /bits/ 64 <200000000>; 189104a3605bSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 189204a3605bSJonathan Marek }; 189304a3605bSJonathan Marek }; 189404a3605bSJonathan Marek }; 189504a3605bSJonathan Marek 189604a3605bSJonathan Marek gpucc: clock-controller@3d90000 { 189704a3605bSJonathan Marek compatible = "qcom,sm8250-gpucc"; 189804a3605bSJonathan Marek reg = <0 0x03d90000 0 0x9000>; 189904a3605bSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>, 190004a3605bSJonathan Marek <&gcc GCC_GPU_GPLL0_CLK_SRC>, 190104a3605bSJonathan Marek <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 190204a3605bSJonathan Marek clock-names = "bi_tcxo", 190304a3605bSJonathan Marek "gcc_gpu_gpll0_clk_src", 190404a3605bSJonathan Marek "gcc_gpu_gpll0_div_clk_src"; 190504a3605bSJonathan Marek #clock-cells = <1>; 190604a3605bSJonathan Marek #reset-cells = <1>; 190704a3605bSJonathan Marek #power-domain-cells = <1>; 190804a3605bSJonathan Marek }; 190904a3605bSJonathan Marek 191004a3605bSJonathan Marek adreno_smmu: iommu@3da0000 { 191104a3605bSJonathan Marek compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 191204a3605bSJonathan Marek reg = <0 0x03da0000 0 0x10000>; 191304a3605bSJonathan Marek #iommu-cells = <2>; 191404a3605bSJonathan Marek #global-interrupts = <2>; 191504a3605bSJonathan Marek interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 191604a3605bSJonathan Marek <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 191704a3605bSJonathan Marek <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 191804a3605bSJonathan Marek <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 191904a3605bSJonathan Marek <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 192004a3605bSJonathan Marek <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 192104a3605bSJonathan Marek <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 192204a3605bSJonathan Marek <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 192304a3605bSJonathan Marek <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 192404a3605bSJonathan Marek <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 19250e6aa9dbSJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 192604a3605bSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 192704a3605bSJonathan Marek <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 192804a3605bSJonathan Marek clock-names = "ahb", "bus", "iface"; 192904a3605bSJonathan Marek 19300e6aa9dbSJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>; 193104a3605bSJonathan Marek }; 193204a3605bSJonathan Marek 193323a89037SBjorn Andersson slpi: remoteproc@5c00000 { 193423a89037SBjorn Andersson compatible = "qcom,sm8250-slpi-pas"; 193523a89037SBjorn Andersson reg = <0 0x05c00000 0 0x4000>; 193623a89037SBjorn Andersson 193723a89037SBjorn Andersson interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 193823a89037SBjorn Andersson <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 193923a89037SBjorn Andersson <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 194023a89037SBjorn Andersson <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 194123a89037SBjorn Andersson <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 194223a89037SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 194323a89037SBjorn Andersson "handover", "stop-ack"; 194423a89037SBjorn Andersson 194523a89037SBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>; 194623a89037SBjorn Andersson clock-names = "xo"; 194723a89037SBjorn Andersson 194823a89037SBjorn Andersson power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, 194923a89037SBjorn Andersson <&rpmhpd SM8250_LCX>, 195023a89037SBjorn Andersson <&rpmhpd SM8250_LMX>; 195123a89037SBjorn Andersson power-domain-names = "load_state", "lcx", "lmx"; 195223a89037SBjorn Andersson 195323a89037SBjorn Andersson memory-region = <&slpi_mem>; 195423a89037SBjorn Andersson 195523a89037SBjorn Andersson qcom,smem-states = <&smp2p_slpi_out 0>; 195623a89037SBjorn Andersson qcom,smem-state-names = "stop"; 195723a89037SBjorn Andersson 195823a89037SBjorn Andersson status = "disabled"; 195923a89037SBjorn Andersson 196023a89037SBjorn Andersson glink-edge { 196123a89037SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 196223a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 196323a89037SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 196423a89037SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_SLPI 196523a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 196623a89037SBjorn Andersson 196725695808SJonathan Marek label = "slpi"; 196823a89037SBjorn Andersson qcom,remote-pid = <3>; 196925695808SJonathan Marek 197025695808SJonathan Marek fastrpc { 197125695808SJonathan Marek compatible = "qcom,fastrpc"; 197225695808SJonathan Marek qcom,glink-channels = "fastrpcglink-apps-dsp"; 197325695808SJonathan Marek label = "sdsp"; 197425695808SJonathan Marek #address-cells = <1>; 197525695808SJonathan Marek #size-cells = <0>; 197625695808SJonathan Marek 197725695808SJonathan Marek compute-cb@1 { 197825695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 197925695808SJonathan Marek reg = <1>; 198025695808SJonathan Marek iommus = <&apps_smmu 0x0541 0x0>; 198125695808SJonathan Marek }; 198225695808SJonathan Marek 198325695808SJonathan Marek compute-cb@2 { 198425695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 198525695808SJonathan Marek reg = <2>; 198625695808SJonathan Marek iommus = <&apps_smmu 0x0542 0x0>; 198725695808SJonathan Marek }; 198825695808SJonathan Marek 198925695808SJonathan Marek compute-cb@3 { 199025695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 199125695808SJonathan Marek reg = <3>; 199225695808SJonathan Marek iommus = <&apps_smmu 0x0543 0x0>; 199325695808SJonathan Marek /* note: shared-cb = <4> in downstream */ 199425695808SJonathan Marek }; 199525695808SJonathan Marek }; 199623a89037SBjorn Andersson }; 199723a89037SBjorn Andersson }; 199823a89037SBjorn Andersson 199923a89037SBjorn Andersson cdsp: remoteproc@8300000 { 200023a89037SBjorn Andersson compatible = "qcom,sm8250-cdsp-pas"; 200123a89037SBjorn Andersson reg = <0 0x08300000 0 0x10000>; 200223a89037SBjorn Andersson 200323a89037SBjorn Andersson interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 200423a89037SBjorn Andersson <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 200523a89037SBjorn Andersson <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 200623a89037SBjorn Andersson <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 200723a89037SBjorn Andersson <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 200823a89037SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 200923a89037SBjorn Andersson "handover", "stop-ack"; 201023a89037SBjorn Andersson 201123a89037SBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>; 201223a89037SBjorn Andersson clock-names = "xo"; 201323a89037SBjorn Andersson 201423a89037SBjorn Andersson power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, 201523a89037SBjorn Andersson <&rpmhpd SM8250_CX>; 201623a89037SBjorn Andersson power-domain-names = "load_state", "cx"; 201723a89037SBjorn Andersson 201823a89037SBjorn Andersson memory-region = <&cdsp_mem>; 201923a89037SBjorn Andersson 202023a89037SBjorn Andersson qcom,smem-states = <&smp2p_cdsp_out 0>; 202123a89037SBjorn Andersson qcom,smem-state-names = "stop"; 202223a89037SBjorn Andersson 202323a89037SBjorn Andersson status = "disabled"; 202423a89037SBjorn Andersson 202523a89037SBjorn Andersson glink-edge { 202623a89037SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 202723a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 202823a89037SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 202923a89037SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_CDSP 203023a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 203123a89037SBjorn Andersson 203225695808SJonathan Marek label = "cdsp"; 203323a89037SBjorn Andersson qcom,remote-pid = <5>; 203425695808SJonathan Marek 203525695808SJonathan Marek fastrpc { 203625695808SJonathan Marek compatible = "qcom,fastrpc"; 203725695808SJonathan Marek qcom,glink-channels = "fastrpcglink-apps-dsp"; 203825695808SJonathan Marek label = "cdsp"; 203925695808SJonathan Marek #address-cells = <1>; 204025695808SJonathan Marek #size-cells = <0>; 204125695808SJonathan Marek 204225695808SJonathan Marek compute-cb@1 { 204325695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 204425695808SJonathan Marek reg = <1>; 204525695808SJonathan Marek iommus = <&apps_smmu 0x1001 0x0460>; 204625695808SJonathan Marek }; 204725695808SJonathan Marek 204825695808SJonathan Marek compute-cb@2 { 204925695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 205025695808SJonathan Marek reg = <2>; 205125695808SJonathan Marek iommus = <&apps_smmu 0x1002 0x0460>; 205225695808SJonathan Marek }; 205325695808SJonathan Marek 205425695808SJonathan Marek compute-cb@3 { 205525695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 205625695808SJonathan Marek reg = <3>; 205725695808SJonathan Marek iommus = <&apps_smmu 0x1003 0x0460>; 205825695808SJonathan Marek }; 205925695808SJonathan Marek 206025695808SJonathan Marek compute-cb@4 { 206125695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 206225695808SJonathan Marek reg = <4>; 206325695808SJonathan Marek iommus = <&apps_smmu 0x1004 0x0460>; 206425695808SJonathan Marek }; 206525695808SJonathan Marek 206625695808SJonathan Marek compute-cb@5 { 206725695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 206825695808SJonathan Marek reg = <5>; 206925695808SJonathan Marek iommus = <&apps_smmu 0x1005 0x0460>; 207025695808SJonathan Marek }; 207125695808SJonathan Marek 207225695808SJonathan Marek compute-cb@6 { 207325695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 207425695808SJonathan Marek reg = <6>; 207525695808SJonathan Marek iommus = <&apps_smmu 0x1006 0x0460>; 207625695808SJonathan Marek }; 207725695808SJonathan Marek 207825695808SJonathan Marek compute-cb@7 { 207925695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 208025695808SJonathan Marek reg = <7>; 208125695808SJonathan Marek iommus = <&apps_smmu 0x1007 0x0460>; 208225695808SJonathan Marek }; 208325695808SJonathan Marek 208425695808SJonathan Marek compute-cb@8 { 208525695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 208625695808SJonathan Marek reg = <8>; 208725695808SJonathan Marek iommus = <&apps_smmu 0x1008 0x0460>; 208825695808SJonathan Marek }; 208925695808SJonathan Marek 209025695808SJonathan Marek /* note: secure cb9 in downstream */ 209125695808SJonathan Marek }; 209223a89037SBjorn Andersson }; 209323a89037SBjorn Andersson }; 209423a89037SBjorn Andersson 2095590a135eSSrinivas Kandagatla sound: sound { 2096590a135eSSrinivas Kandagatla }; 2097590a135eSSrinivas Kandagatla 209846a6f297SJonathan Marek usb_1_hsphy: phy@88e3000 { 209946a6f297SJonathan Marek compatible = "qcom,sm8250-usb-hs-phy", 210046a6f297SJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 210146a6f297SJonathan Marek reg = <0 0x088e3000 0 0x400>; 210246a6f297SJonathan Marek status = "disabled"; 210346a6f297SJonathan Marek #phy-cells = <0>; 210446a6f297SJonathan Marek 210546a6f297SJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 210646a6f297SJonathan Marek clock-names = "ref"; 210746a6f297SJonathan Marek 210846a6f297SJonathan Marek resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 210946a6f297SJonathan Marek }; 211046a6f297SJonathan Marek 211146a6f297SJonathan Marek usb_2_hsphy: phy@88e4000 { 211246a6f297SJonathan Marek compatible = "qcom,sm8250-usb-hs-phy", 211346a6f297SJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 211446a6f297SJonathan Marek reg = <0 0x088e4000 0 0x400>; 211546a6f297SJonathan Marek status = "disabled"; 211646a6f297SJonathan Marek #phy-cells = <0>; 211746a6f297SJonathan Marek 211846a6f297SJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 211946a6f297SJonathan Marek clock-names = "ref"; 212046a6f297SJonathan Marek 212146a6f297SJonathan Marek resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 212246a6f297SJonathan Marek }; 212346a6f297SJonathan Marek 212446a6f297SJonathan Marek usb_1_qmpphy: phy@88e9000 { 21255aa0d1beSDmitry Baryshkov compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 212646a6f297SJonathan Marek reg = <0 0x088e9000 0 0x200>, 21275aa0d1beSDmitry Baryshkov <0 0x088e8000 0 0x40>, 21285aa0d1beSDmitry Baryshkov <0 0x088ea000 0 0x200>; 212946a6f297SJonathan Marek status = "disabled"; 213046a6f297SJonathan Marek #address-cells = <2>; 213146a6f297SJonathan Marek #size-cells = <2>; 213246a6f297SJonathan Marek ranges; 213346a6f297SJonathan Marek 213446a6f297SJonathan Marek clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 213546a6f297SJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 213646a6f297SJonathan Marek <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 213746a6f297SJonathan Marek clock-names = "aux", "ref_clk_src", "com_aux"; 213846a6f297SJonathan Marek 213946a6f297SJonathan Marek resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 214046a6f297SJonathan Marek <&gcc GCC_USB3_PHY_PRIM_BCR>; 214146a6f297SJonathan Marek reset-names = "phy", "common"; 214246a6f297SJonathan Marek 21435aa0d1beSDmitry Baryshkov usb_1_ssphy: usb3-phy@88e9200 { 214446a6f297SJonathan Marek reg = <0 0x088e9200 0 0x200>, 214546a6f297SJonathan Marek <0 0x088e9400 0 0x200>, 214646a6f297SJonathan Marek <0 0x088e9c00 0 0x400>, 214746a6f297SJonathan Marek <0 0x088e9600 0 0x200>, 214846a6f297SJonathan Marek <0 0x088e9800 0 0x200>, 214946a6f297SJonathan Marek <0 0x088e9a00 0 0x100>; 21507178d4ccSJonathan Marek #clock-cells = <0>; 215146a6f297SJonathan Marek #phy-cells = <0>; 215246a6f297SJonathan Marek clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 215346a6f297SJonathan Marek clock-names = "pipe0"; 215446a6f297SJonathan Marek clock-output-names = "usb3_phy_pipe_clk_src"; 215546a6f297SJonathan Marek }; 21565aa0d1beSDmitry Baryshkov 21575aa0d1beSDmitry Baryshkov dp_phy: dp-phy@88ea200 { 21585aa0d1beSDmitry Baryshkov reg = <0 0x088ea200 0 0x200>, 21595aa0d1beSDmitry Baryshkov <0 0x088ea400 0 0x200>, 21605aa0d1beSDmitry Baryshkov <0 0x088eac00 0 0x400>, 21615aa0d1beSDmitry Baryshkov <0 0x088ea600 0 0x200>, 21625aa0d1beSDmitry Baryshkov <0 0x088ea800 0 0x200>, 21635aa0d1beSDmitry Baryshkov <0 0x088eaa00 0 0x100>; 21645aa0d1beSDmitry Baryshkov #phy-cells = <0>; 21655aa0d1beSDmitry Baryshkov #clock-cells = <1>; 21665aa0d1beSDmitry Baryshkov clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 21675aa0d1beSDmitry Baryshkov clock-names = "pipe0"; 21685aa0d1beSDmitry Baryshkov clock-output-names = "usb3_phy_pipe_clk_src"; 21695aa0d1beSDmitry Baryshkov }; 217046a6f297SJonathan Marek }; 217146a6f297SJonathan Marek 217246a6f297SJonathan Marek usb_2_qmpphy: phy@88eb000 { 217346a6f297SJonathan Marek compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 217446a6f297SJonathan Marek reg = <0 0x088eb000 0 0x200>; 217546a6f297SJonathan Marek status = "disabled"; 217646a6f297SJonathan Marek #address-cells = <2>; 217746a6f297SJonathan Marek #size-cells = <2>; 217846a6f297SJonathan Marek ranges; 217946a6f297SJonathan Marek 218046a6f297SJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 218146a6f297SJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 218246a6f297SJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_EN>, 218346a6f297SJonathan Marek <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 218446a6f297SJonathan Marek clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 218546a6f297SJonathan Marek 218646a6f297SJonathan Marek resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 218746a6f297SJonathan Marek <&gcc GCC_USB3_PHY_SEC_BCR>; 218846a6f297SJonathan Marek reset-names = "phy", "common"; 218946a6f297SJonathan Marek 219046a6f297SJonathan Marek usb_2_ssphy: lane@88eb200 { 219146a6f297SJonathan Marek reg = <0 0x088eb200 0 0x200>, 219246a6f297SJonathan Marek <0 0x088eb400 0 0x200>, 219346a6f297SJonathan Marek <0 0x088eb800 0 0x800>; 21947178d4ccSJonathan Marek #clock-cells = <0>; 219546a6f297SJonathan Marek #phy-cells = <0>; 219646a6f297SJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 219746a6f297SJonathan Marek clock-names = "pipe0"; 219846a6f297SJonathan Marek clock-output-names = "usb3_uni_phy_pipe_clk_src"; 219946a6f297SJonathan Marek }; 220046a6f297SJonathan Marek }; 220146a6f297SJonathan Marek 2202c4cf0300SManivannan Sadhasivam sdhc_2: sdhci@8804000 { 2203c4cf0300SManivannan Sadhasivam compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 2204c4cf0300SManivannan Sadhasivam reg = <0 0x08804000 0 0x1000>; 2205c4cf0300SManivannan Sadhasivam 2206c4cf0300SManivannan Sadhasivam interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2207c4cf0300SManivannan Sadhasivam <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2208c4cf0300SManivannan Sadhasivam interrupt-names = "hc_irq", "pwr_irq"; 2209c4cf0300SManivannan Sadhasivam 2210c4cf0300SManivannan Sadhasivam clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2211c4cf0300SManivannan Sadhasivam <&gcc GCC_SDCC2_APPS_CLK>, 221274097d80SDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK>; 2213c4cf0300SManivannan Sadhasivam clock-names = "iface", "core", "xo"; 2214c4cf0300SManivannan Sadhasivam iommus = <&apps_smmu 0x4a0 0x0>; 2215c4cf0300SManivannan Sadhasivam qcom,dll-config = <0x0007642c>; 2216c4cf0300SManivannan Sadhasivam qcom,ddr-config = <0x80040868>; 2217c4cf0300SManivannan Sadhasivam power-domains = <&rpmhpd SM8250_CX>; 2218c4cf0300SManivannan Sadhasivam operating-points-v2 = <&sdhc2_opp_table>; 2219c4cf0300SManivannan Sadhasivam 2220c4cf0300SManivannan Sadhasivam status = "disabled"; 2221c4cf0300SManivannan Sadhasivam 2222c4cf0300SManivannan Sadhasivam sdhc2_opp_table: sdhc2-opp-table { 2223c4cf0300SManivannan Sadhasivam compatible = "operating-points-v2"; 2224c4cf0300SManivannan Sadhasivam 2225c4cf0300SManivannan Sadhasivam opp-19200000 { 2226c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <19200000>; 2227c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_min_svs>; 2228c4cf0300SManivannan Sadhasivam }; 2229c4cf0300SManivannan Sadhasivam 2230c4cf0300SManivannan Sadhasivam opp-50000000 { 2231c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <50000000>; 2232c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_low_svs>; 2233c4cf0300SManivannan Sadhasivam }; 2234c4cf0300SManivannan Sadhasivam 2235c4cf0300SManivannan Sadhasivam opp-100000000 { 2236c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <100000000>; 2237c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_svs>; 2238c4cf0300SManivannan Sadhasivam }; 2239c4cf0300SManivannan Sadhasivam 2240c4cf0300SManivannan Sadhasivam opp-202000000 { 2241c4cf0300SManivannan Sadhasivam opp-hz = /bits/ 64 <202000000>; 2242c4cf0300SManivannan Sadhasivam required-opps = <&rpmhpd_opp_svs_l1>; 2243c4cf0300SManivannan Sadhasivam }; 2244c4cf0300SManivannan Sadhasivam }; 2245c4cf0300SManivannan Sadhasivam }; 2246c4cf0300SManivannan Sadhasivam 2247e7e41a20SJonathan Marek dc_noc: interconnect@90c0000 { 2248e7e41a20SJonathan Marek compatible = "qcom,sm8250-dc-noc"; 2249e7e41a20SJonathan Marek reg = <0 0x090c0000 0 0x4200>; 2250e7e41a20SJonathan Marek #interconnect-cells = <1>; 2251e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 2252e7e41a20SJonathan Marek }; 2253e7e41a20SJonathan Marek 2254e7e41a20SJonathan Marek gem_noc: interconnect@9100000 { 2255e7e41a20SJonathan Marek compatible = "qcom,sm8250-gem-noc"; 2256e7e41a20SJonathan Marek reg = <0 0x09100000 0 0xb4000>; 2257e7e41a20SJonathan Marek #interconnect-cells = <1>; 2258e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 2259e7e41a20SJonathan Marek }; 2260e7e41a20SJonathan Marek 2261e7e41a20SJonathan Marek npu_noc: interconnect@9990000 { 2262e7e41a20SJonathan Marek compatible = "qcom,sm8250-npu-noc"; 2263e7e41a20SJonathan Marek reg = <0 0x09990000 0 0x1600>; 2264e7e41a20SJonathan Marek #interconnect-cells = <1>; 2265e7e41a20SJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 2266e7e41a20SJonathan Marek }; 2267e7e41a20SJonathan Marek 226846a6f297SJonathan Marek usb_1: usb@a6f8800 { 226946a6f297SJonathan Marek compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 227046a6f297SJonathan Marek reg = <0 0x0a6f8800 0 0x400>; 227146a6f297SJonathan Marek status = "disabled"; 227246a6f297SJonathan Marek #address-cells = <2>; 227346a6f297SJonathan Marek #size-cells = <2>; 227446a6f297SJonathan Marek ranges; 227546a6f297SJonathan Marek dma-ranges; 227646a6f297SJonathan Marek 227746a6f297SJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 227846a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_MASTER_CLK>, 227946a6f297SJonathan Marek <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 228046a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 228146a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 228246a6f297SJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_EN>; 228346a6f297SJonathan Marek clock-names = "cfg_noc", "core", "iface", "mock_utmi", 228446a6f297SJonathan Marek "sleep", "xo"; 228546a6f297SJonathan Marek 228646a6f297SJonathan Marek assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 228746a6f297SJonathan Marek <&gcc GCC_USB30_PRIM_MASTER_CLK>; 228846a6f297SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 228946a6f297SJonathan Marek 229046a6f297SJonathan Marek interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 229146a6f297SJonathan Marek <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 229246a6f297SJonathan Marek <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 229346a6f297SJonathan Marek <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 229446a6f297SJonathan Marek interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 229546a6f297SJonathan Marek "dm_hs_phy_irq", "ss_phy_irq"; 229646a6f297SJonathan Marek 229746a6f297SJonathan Marek power-domains = <&gcc USB30_PRIM_GDSC>; 229846a6f297SJonathan Marek 229946a6f297SJonathan Marek resets = <&gcc GCC_USB30_PRIM_BCR>; 230046a6f297SJonathan Marek 230146a6f297SJonathan Marek usb_1_dwc3: dwc3@a600000 { 230246a6f297SJonathan Marek compatible = "snps,dwc3"; 230346a6f297SJonathan Marek reg = <0 0x0a600000 0 0xcd00>; 230446a6f297SJonathan Marek interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 230546a6f297SJonathan Marek iommus = <&apps_smmu 0x0 0x0>; 230646a6f297SJonathan Marek snps,dis_u2_susphy_quirk; 230746a6f297SJonathan Marek snps,dis_enblslpm_quirk; 230846a6f297SJonathan Marek phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 230946a6f297SJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 231046a6f297SJonathan Marek }; 231146a6f297SJonathan Marek }; 231246a6f297SJonathan Marek 23130085a33aSManivannan Sadhasivam system-cache-controller@9200000 { 23140085a33aSManivannan Sadhasivam compatible = "qcom,sm8250-llcc"; 23150085a33aSManivannan Sadhasivam reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 23160085a33aSManivannan Sadhasivam reg-names = "llcc_base", "llcc_broadcast_base"; 23170085a33aSManivannan Sadhasivam }; 23180085a33aSManivannan Sadhasivam 231946a6f297SJonathan Marek usb_2: usb@a8f8800 { 232046a6f297SJonathan Marek compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 232146a6f297SJonathan Marek reg = <0 0x0a8f8800 0 0x400>; 232246a6f297SJonathan Marek status = "disabled"; 232346a6f297SJonathan Marek #address-cells = <2>; 232446a6f297SJonathan Marek #size-cells = <2>; 232546a6f297SJonathan Marek ranges; 232646a6f297SJonathan Marek dma-ranges; 232746a6f297SJonathan Marek 232846a6f297SJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 232946a6f297SJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>, 233046a6f297SJonathan Marek <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 233146a6f297SJonathan Marek <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 233246a6f297SJonathan Marek <&gcc GCC_USB30_SEC_SLEEP_CLK>, 233346a6f297SJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_EN>; 233446a6f297SJonathan Marek clock-names = "cfg_noc", "core", "iface", "mock_utmi", 233546a6f297SJonathan Marek "sleep", "xo"; 233646a6f297SJonathan Marek 233746a6f297SJonathan Marek assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 233846a6f297SJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>; 233946a6f297SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 234046a6f297SJonathan Marek 234146a6f297SJonathan Marek interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 234246a6f297SJonathan Marek <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 234346a6f297SJonathan Marek <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 234446a6f297SJonathan Marek <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 234546a6f297SJonathan Marek interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 234646a6f297SJonathan Marek "dm_hs_phy_irq", "ss_phy_irq"; 234746a6f297SJonathan Marek 234846a6f297SJonathan Marek power-domains = <&gcc USB30_SEC_GDSC>; 234946a6f297SJonathan Marek 235046a6f297SJonathan Marek resets = <&gcc GCC_USB30_SEC_BCR>; 235146a6f297SJonathan Marek 235246a6f297SJonathan Marek usb_2_dwc3: dwc3@a800000 { 235346a6f297SJonathan Marek compatible = "snps,dwc3"; 235446a6f297SJonathan Marek reg = <0 0x0a800000 0 0xcd00>; 235546a6f297SJonathan Marek interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 235646a6f297SJonathan Marek iommus = <&apps_smmu 0x20 0>; 235746a6f297SJonathan Marek snps,dis_u2_susphy_quirk; 235846a6f297SJonathan Marek snps,dis_enblslpm_quirk; 235946a6f297SJonathan Marek phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 236046a6f297SJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 236146a6f297SJonathan Marek }; 236246a6f297SJonathan Marek }; 236346a6f297SJonathan Marek 2364fa245b3fSBryan O'Donoghue venus: video-codec@aa00000 { 2365fa245b3fSBryan O'Donoghue compatible = "qcom,sm8250-venus"; 2366fa245b3fSBryan O'Donoghue reg = <0 0x0aa00000 0 0x100000>; 2367fa245b3fSBryan O'Donoghue interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2368fa245b3fSBryan O'Donoghue power-domains = <&videocc MVS0C_GDSC>, 2369fa245b3fSBryan O'Donoghue <&videocc MVS0_GDSC>, 2370fa245b3fSBryan O'Donoghue <&rpmhpd SM8250_MX>; 2371fa245b3fSBryan O'Donoghue power-domain-names = "venus", "vcodec0", "mx"; 2372fa245b3fSBryan O'Donoghue operating-points-v2 = <&venus_opp_table>; 2373fa245b3fSBryan O'Donoghue 2374fa245b3fSBryan O'Donoghue clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 2375fa245b3fSBryan O'Donoghue <&videocc VIDEO_CC_MVS0C_CLK>, 2376fa245b3fSBryan O'Donoghue <&videocc VIDEO_CC_MVS0_CLK>; 2377fa245b3fSBryan O'Donoghue clock-names = "iface", "core", "vcodec0_core"; 2378fa245b3fSBryan O'Donoghue 2379fa245b3fSBryan O'Donoghue interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, 2380fa245b3fSBryan O'Donoghue <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; 2381fa245b3fSBryan O'Donoghue interconnect-names = "cpu-cfg", "video-mem"; 2382fa245b3fSBryan O'Donoghue 2383fa245b3fSBryan O'Donoghue iommus = <&apps_smmu 0x2100 0x0400>; 2384fa245b3fSBryan O'Donoghue memory-region = <&video_mem>; 2385fa245b3fSBryan O'Donoghue 2386fa245b3fSBryan O'Donoghue resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 2387fa245b3fSBryan O'Donoghue <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 2388fa245b3fSBryan O'Donoghue reset-names = "bus", "core"; 2389fa245b3fSBryan O'Donoghue 2390fa245b3fSBryan O'Donoghue video-decoder { 2391fa245b3fSBryan O'Donoghue compatible = "venus-decoder"; 2392fa245b3fSBryan O'Donoghue }; 2393fa245b3fSBryan O'Donoghue 2394fa245b3fSBryan O'Donoghue video-encoder { 2395fa245b3fSBryan O'Donoghue compatible = "venus-encoder"; 2396fa245b3fSBryan O'Donoghue }; 2397fa245b3fSBryan O'Donoghue 2398fa245b3fSBryan O'Donoghue venus_opp_table: venus-opp-table { 2399fa245b3fSBryan O'Donoghue compatible = "operating-points-v2"; 2400fa245b3fSBryan O'Donoghue 2401fa245b3fSBryan O'Donoghue opp-720000000 { 2402fa245b3fSBryan O'Donoghue opp-hz = /bits/ 64 <720000000>; 2403fa245b3fSBryan O'Donoghue required-opps = <&rpmhpd_opp_low_svs>; 2404fa245b3fSBryan O'Donoghue }; 2405fa245b3fSBryan O'Donoghue 2406fa245b3fSBryan O'Donoghue opp-1014000000 { 2407fa245b3fSBryan O'Donoghue opp-hz = /bits/ 64 <1014000000>; 2408fa245b3fSBryan O'Donoghue required-opps = <&rpmhpd_opp_svs>; 2409fa245b3fSBryan O'Donoghue }; 2410fa245b3fSBryan O'Donoghue 2411fa245b3fSBryan O'Donoghue opp-1098000000 { 2412fa245b3fSBryan O'Donoghue opp-hz = /bits/ 64 <1098000000>; 2413fa245b3fSBryan O'Donoghue required-opps = <&rpmhpd_opp_svs_l1>; 2414fa245b3fSBryan O'Donoghue }; 2415fa245b3fSBryan O'Donoghue 2416fa245b3fSBryan O'Donoghue opp-1332000000 { 2417fa245b3fSBryan O'Donoghue opp-hz = /bits/ 64 <1332000000>; 2418fa245b3fSBryan O'Donoghue required-opps = <&rpmhpd_opp_nom>; 2419fa245b3fSBryan O'Donoghue }; 2420fa245b3fSBryan O'Donoghue }; 2421fa245b3fSBryan O'Donoghue }; 2422fa245b3fSBryan O'Donoghue 24235b9ec225Sjonathan@marek.ca videocc: clock-controller@abf0000 { 24245b9ec225Sjonathan@marek.ca compatible = "qcom,sm8250-videocc"; 24255b9ec225Sjonathan@marek.ca reg = <0 0x0abf0000 0 0x10000>; 24265b9ec225Sjonathan@marek.ca clocks = <&gcc GCC_VIDEO_AHB_CLK>, 24275b9ec225Sjonathan@marek.ca <&rpmhcc RPMH_CXO_CLK>, 24285b9ec225Sjonathan@marek.ca <&rpmhcc RPMH_CXO_CLK_A>; 24295b9ec225Sjonathan@marek.ca mmcx-supply = <&mmcx_reg>; 24305b9ec225Sjonathan@marek.ca clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 24315b9ec225Sjonathan@marek.ca #clock-cells = <1>; 24325b9ec225Sjonathan@marek.ca #reset-cells = <1>; 24335b9ec225Sjonathan@marek.ca #power-domain-cells = <1>; 24345b9ec225Sjonathan@marek.ca }; 24355b9ec225Sjonathan@marek.ca 24367c1dffd4SDmitry Baryshkov mdss: mdss@ae00000 { 2437dc5d9125SJonathan Marek compatible = "qcom,sm8250-mdss"; 24387c1dffd4SDmitry Baryshkov reg = <0 0x0ae00000 0 0x1000>; 24397c1dffd4SDmitry Baryshkov reg-names = "mdss"; 24407c1dffd4SDmitry Baryshkov 2441888771a9SJonathan Marek interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 24427c1dffd4SDmitry Baryshkov <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 2443888771a9SJonathan Marek interconnect-names = "mdp0-mem", "mdp1-mem"; 24447c1dffd4SDmitry Baryshkov 24457c1dffd4SDmitry Baryshkov power-domains = <&dispcc MDSS_GDSC>; 24467c1dffd4SDmitry Baryshkov 24477c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 24487c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_HF_AXI_CLK>, 24497c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_SF_AXI_CLK>, 24507c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_MDP_CLK>; 24517c1dffd4SDmitry Baryshkov clock-names = "iface", "bus", "nrt_bus", "core"; 24527c1dffd4SDmitry Baryshkov 24537c1dffd4SDmitry Baryshkov assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 24547c1dffd4SDmitry Baryshkov assigned-clock-rates = <460000000>; 24557c1dffd4SDmitry Baryshkov 24567c1dffd4SDmitry Baryshkov interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 24577c1dffd4SDmitry Baryshkov interrupt-controller; 24587c1dffd4SDmitry Baryshkov #interrupt-cells = <1>; 24597c1dffd4SDmitry Baryshkov 24607c1dffd4SDmitry Baryshkov iommus = <&apps_smmu 0x820 0x402>; 24617c1dffd4SDmitry Baryshkov 24627c1dffd4SDmitry Baryshkov status = "disabled"; 24637c1dffd4SDmitry Baryshkov 24647c1dffd4SDmitry Baryshkov #address-cells = <2>; 24657c1dffd4SDmitry Baryshkov #size-cells = <2>; 24667c1dffd4SDmitry Baryshkov ranges; 24677c1dffd4SDmitry Baryshkov 24687c1dffd4SDmitry Baryshkov mdss_mdp: mdp@ae01000 { 2469dc5d9125SJonathan Marek compatible = "qcom,sm8250-dpu"; 24707c1dffd4SDmitry Baryshkov reg = <0 0x0ae01000 0 0x8f000>, 24717c1dffd4SDmitry Baryshkov <0 0x0aeb0000 0 0x2008>; 24727c1dffd4SDmitry Baryshkov reg-names = "mdp", "vbif"; 24737c1dffd4SDmitry Baryshkov 24747c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 24757c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_HF_AXI_CLK>, 24767c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_MDP_CLK>, 24777c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 24787c1dffd4SDmitry Baryshkov clock-names = "iface", "bus", "core", "vsync"; 24797c1dffd4SDmitry Baryshkov 24807c1dffd4SDmitry Baryshkov assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 24817c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 24827c1dffd4SDmitry Baryshkov assigned-clock-rates = <460000000>, 24837c1dffd4SDmitry Baryshkov <19200000>; 24847c1dffd4SDmitry Baryshkov 24857c1dffd4SDmitry Baryshkov operating-points-v2 = <&mdp_opp_table>; 24867c1dffd4SDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 24877c1dffd4SDmitry Baryshkov 24887c1dffd4SDmitry Baryshkov interrupt-parent = <&mdss>; 24897c1dffd4SDmitry Baryshkov interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 24907c1dffd4SDmitry Baryshkov 24917c1dffd4SDmitry Baryshkov ports { 24927c1dffd4SDmitry Baryshkov #address-cells = <1>; 24937c1dffd4SDmitry Baryshkov #size-cells = <0>; 24947c1dffd4SDmitry Baryshkov 24957c1dffd4SDmitry Baryshkov port@0 { 24967c1dffd4SDmitry Baryshkov reg = <0>; 24977c1dffd4SDmitry Baryshkov dpu_intf1_out: endpoint { 24987c1dffd4SDmitry Baryshkov remote-endpoint = <&dsi0_in>; 24997c1dffd4SDmitry Baryshkov }; 25007c1dffd4SDmitry Baryshkov }; 25017c1dffd4SDmitry Baryshkov 25027c1dffd4SDmitry Baryshkov port@1 { 25037c1dffd4SDmitry Baryshkov reg = <1>; 25047c1dffd4SDmitry Baryshkov dpu_intf2_out: endpoint { 25057c1dffd4SDmitry Baryshkov remote-endpoint = <&dsi1_in>; 25067c1dffd4SDmitry Baryshkov }; 25077c1dffd4SDmitry Baryshkov }; 25087c1dffd4SDmitry Baryshkov }; 25097c1dffd4SDmitry Baryshkov 25107c1dffd4SDmitry Baryshkov mdp_opp_table: mdp-opp-table { 25117c1dffd4SDmitry Baryshkov compatible = "operating-points-v2"; 25127c1dffd4SDmitry Baryshkov 25137c1dffd4SDmitry Baryshkov opp-200000000 { 25147c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <200000000>; 25157c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 25167c1dffd4SDmitry Baryshkov }; 25177c1dffd4SDmitry Baryshkov 25187c1dffd4SDmitry Baryshkov opp-300000000 { 25197c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <300000000>; 25207c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs>; 25217c1dffd4SDmitry Baryshkov }; 25227c1dffd4SDmitry Baryshkov 25237c1dffd4SDmitry Baryshkov opp-345000000 { 25247c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <345000000>; 25257c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs_l1>; 25267c1dffd4SDmitry Baryshkov }; 25277c1dffd4SDmitry Baryshkov 25287c1dffd4SDmitry Baryshkov opp-460000000 { 25297c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <460000000>; 25307c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_nom>; 25317c1dffd4SDmitry Baryshkov }; 25327c1dffd4SDmitry Baryshkov }; 25337c1dffd4SDmitry Baryshkov }; 25347c1dffd4SDmitry Baryshkov 25357c1dffd4SDmitry Baryshkov dsi0: dsi@ae94000 { 25367c1dffd4SDmitry Baryshkov compatible = "qcom,mdss-dsi-ctrl"; 25377c1dffd4SDmitry Baryshkov reg = <0 0x0ae94000 0 0x400>; 25387c1dffd4SDmitry Baryshkov reg-names = "dsi_ctrl"; 25397c1dffd4SDmitry Baryshkov 25407c1dffd4SDmitry Baryshkov interrupt-parent = <&mdss>; 25417c1dffd4SDmitry Baryshkov interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 25427c1dffd4SDmitry Baryshkov 25437c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 25447c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 25457c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 25467c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_ESC0_CLK>, 25477c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_AHB_CLK>, 25487c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_HF_AXI_CLK>; 25497c1dffd4SDmitry Baryshkov clock-names = "byte", 25507c1dffd4SDmitry Baryshkov "byte_intf", 25517c1dffd4SDmitry Baryshkov "pixel", 25527c1dffd4SDmitry Baryshkov "core", 25537c1dffd4SDmitry Baryshkov "iface", 25547c1dffd4SDmitry Baryshkov "bus"; 25557c1dffd4SDmitry Baryshkov 25567c1dffd4SDmitry Baryshkov operating-points-v2 = <&dsi_opp_table>; 25577c1dffd4SDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 25587c1dffd4SDmitry Baryshkov 25597c1dffd4SDmitry Baryshkov phys = <&dsi0_phy>; 25607c1dffd4SDmitry Baryshkov phy-names = "dsi"; 25617c1dffd4SDmitry Baryshkov 25627c1dffd4SDmitry Baryshkov status = "disabled"; 25637c1dffd4SDmitry Baryshkov 256440f7d36dSKonrad Dybcio #address-cells = <1>; 256540f7d36dSKonrad Dybcio #size-cells = <0>; 256640f7d36dSKonrad Dybcio 25677c1dffd4SDmitry Baryshkov ports { 25687c1dffd4SDmitry Baryshkov #address-cells = <1>; 25697c1dffd4SDmitry Baryshkov #size-cells = <0>; 25707c1dffd4SDmitry Baryshkov 25717c1dffd4SDmitry Baryshkov port@0 { 25727c1dffd4SDmitry Baryshkov reg = <0>; 25737c1dffd4SDmitry Baryshkov dsi0_in: endpoint { 25747c1dffd4SDmitry Baryshkov remote-endpoint = <&dpu_intf1_out>; 25757c1dffd4SDmitry Baryshkov }; 25767c1dffd4SDmitry Baryshkov }; 25777c1dffd4SDmitry Baryshkov 25787c1dffd4SDmitry Baryshkov port@1 { 25797c1dffd4SDmitry Baryshkov reg = <1>; 25807c1dffd4SDmitry Baryshkov dsi0_out: endpoint { 25817c1dffd4SDmitry Baryshkov }; 25827c1dffd4SDmitry Baryshkov }; 25837c1dffd4SDmitry Baryshkov }; 25847c1dffd4SDmitry Baryshkov }; 25857c1dffd4SDmitry Baryshkov 25867c1dffd4SDmitry Baryshkov dsi0_phy: dsi-phy@ae94400 { 25877c1dffd4SDmitry Baryshkov compatible = "qcom,dsi-phy-7nm"; 25887c1dffd4SDmitry Baryshkov reg = <0 0x0ae94400 0 0x200>, 25897c1dffd4SDmitry Baryshkov <0 0x0ae94600 0 0x280>, 25907c1dffd4SDmitry Baryshkov <0 0x0ae94900 0 0x260>; 25917c1dffd4SDmitry Baryshkov reg-names = "dsi_phy", 25927c1dffd4SDmitry Baryshkov "dsi_phy_lane", 25937c1dffd4SDmitry Baryshkov "dsi_pll"; 25947c1dffd4SDmitry Baryshkov 25957c1dffd4SDmitry Baryshkov #clock-cells = <1>; 25967c1dffd4SDmitry Baryshkov #phy-cells = <0>; 25977c1dffd4SDmitry Baryshkov 25987c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 25997c1dffd4SDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK>; 26007c1dffd4SDmitry Baryshkov clock-names = "iface", "ref"; 26017c1dffd4SDmitry Baryshkov 26027c1dffd4SDmitry Baryshkov status = "disabled"; 26037c1dffd4SDmitry Baryshkov }; 26047c1dffd4SDmitry Baryshkov 26057c1dffd4SDmitry Baryshkov dsi1: dsi@ae96000 { 26067c1dffd4SDmitry Baryshkov compatible = "qcom,mdss-dsi-ctrl"; 26077c1dffd4SDmitry Baryshkov reg = <0 0x0ae96000 0 0x400>; 26087c1dffd4SDmitry Baryshkov reg-names = "dsi_ctrl"; 26097c1dffd4SDmitry Baryshkov 26107c1dffd4SDmitry Baryshkov interrupt-parent = <&mdss>; 26117c1dffd4SDmitry Baryshkov interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 26127c1dffd4SDmitry Baryshkov 26137c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 26147c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 26157c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 26167c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_ESC1_CLK>, 26177c1dffd4SDmitry Baryshkov <&dispcc DISP_CC_MDSS_AHB_CLK>, 26187c1dffd4SDmitry Baryshkov <&gcc GCC_DISP_HF_AXI_CLK>; 26197c1dffd4SDmitry Baryshkov clock-names = "byte", 26207c1dffd4SDmitry Baryshkov "byte_intf", 26217c1dffd4SDmitry Baryshkov "pixel", 26227c1dffd4SDmitry Baryshkov "core", 26237c1dffd4SDmitry Baryshkov "iface", 26247c1dffd4SDmitry Baryshkov "bus"; 26257c1dffd4SDmitry Baryshkov 26267c1dffd4SDmitry Baryshkov operating-points-v2 = <&dsi_opp_table>; 26277c1dffd4SDmitry Baryshkov power-domains = <&rpmhpd SM8250_MMCX>; 26287c1dffd4SDmitry Baryshkov 26297c1dffd4SDmitry Baryshkov phys = <&dsi1_phy>; 26307c1dffd4SDmitry Baryshkov phy-names = "dsi"; 26317c1dffd4SDmitry Baryshkov 26327c1dffd4SDmitry Baryshkov status = "disabled"; 26337c1dffd4SDmitry Baryshkov 263440f7d36dSKonrad Dybcio #address-cells = <1>; 263540f7d36dSKonrad Dybcio #size-cells = <0>; 263640f7d36dSKonrad Dybcio 26377c1dffd4SDmitry Baryshkov ports { 26387c1dffd4SDmitry Baryshkov #address-cells = <1>; 26397c1dffd4SDmitry Baryshkov #size-cells = <0>; 26407c1dffd4SDmitry Baryshkov 26417c1dffd4SDmitry Baryshkov port@0 { 26427c1dffd4SDmitry Baryshkov reg = <0>; 26437c1dffd4SDmitry Baryshkov dsi1_in: endpoint { 26447c1dffd4SDmitry Baryshkov remote-endpoint = <&dpu_intf2_out>; 26457c1dffd4SDmitry Baryshkov }; 26467c1dffd4SDmitry Baryshkov }; 26477c1dffd4SDmitry Baryshkov 26487c1dffd4SDmitry Baryshkov port@1 { 26497c1dffd4SDmitry Baryshkov reg = <1>; 26507c1dffd4SDmitry Baryshkov dsi1_out: endpoint { 26517c1dffd4SDmitry Baryshkov }; 26527c1dffd4SDmitry Baryshkov }; 26537c1dffd4SDmitry Baryshkov }; 26547c1dffd4SDmitry Baryshkov }; 26557c1dffd4SDmitry Baryshkov 26567c1dffd4SDmitry Baryshkov dsi1_phy: dsi-phy@ae96400 { 26577c1dffd4SDmitry Baryshkov compatible = "qcom,dsi-phy-7nm"; 26587c1dffd4SDmitry Baryshkov reg = <0 0x0ae96400 0 0x200>, 26597c1dffd4SDmitry Baryshkov <0 0x0ae96600 0 0x280>, 26607c1dffd4SDmitry Baryshkov <0 0x0ae96900 0 0x260>; 26617c1dffd4SDmitry Baryshkov reg-names = "dsi_phy", 26627c1dffd4SDmitry Baryshkov "dsi_phy_lane", 26637c1dffd4SDmitry Baryshkov "dsi_pll"; 26647c1dffd4SDmitry Baryshkov 26657c1dffd4SDmitry Baryshkov #clock-cells = <1>; 26667c1dffd4SDmitry Baryshkov #phy-cells = <0>; 26677c1dffd4SDmitry Baryshkov 26687c1dffd4SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 26697c1dffd4SDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK>; 26707c1dffd4SDmitry Baryshkov clock-names = "iface", "ref"; 26717c1dffd4SDmitry Baryshkov 26727c1dffd4SDmitry Baryshkov status = "disabled"; 26737c1dffd4SDmitry Baryshkov 26747c1dffd4SDmitry Baryshkov dsi_opp_table: dsi-opp-table { 26757c1dffd4SDmitry Baryshkov compatible = "operating-points-v2"; 26767c1dffd4SDmitry Baryshkov 26777c1dffd4SDmitry Baryshkov opp-187500000 { 26787c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <187500000>; 26797c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 26807c1dffd4SDmitry Baryshkov }; 26817c1dffd4SDmitry Baryshkov 26827c1dffd4SDmitry Baryshkov opp-300000000 { 26837c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <300000000>; 26847c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs>; 26857c1dffd4SDmitry Baryshkov }; 26867c1dffd4SDmitry Baryshkov 26877c1dffd4SDmitry Baryshkov opp-358000000 { 26887c1dffd4SDmitry Baryshkov opp-hz = /bits/ 64 <358000000>; 26897c1dffd4SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs_l1>; 26907c1dffd4SDmitry Baryshkov }; 26917c1dffd4SDmitry Baryshkov }; 26927c1dffd4SDmitry Baryshkov }; 26937c1dffd4SDmitry Baryshkov }; 26947c1dffd4SDmitry Baryshkov 26957c1dffd4SDmitry Baryshkov dispcc: clock-controller@af00000 { 26967c1dffd4SDmitry Baryshkov compatible = "qcom,sm8250-dispcc"; 2697888771a9SJonathan Marek reg = <0 0x0af00000 0 0x10000>; 26983f2094dfSDmitry Baryshkov mmcx-supply = <&mmcx_reg>; 26997c1dffd4SDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>, 27007c1dffd4SDmitry Baryshkov <&dsi0_phy 0>, 27017c1dffd4SDmitry Baryshkov <&dsi0_phy 1>, 27027c1dffd4SDmitry Baryshkov <&dsi1_phy 0>, 27037c1dffd4SDmitry Baryshkov <&dsi1_phy 1>, 27049b315324SDmitry Baryshkov <&dp_phy 0>, 27059b315324SDmitry Baryshkov <&dp_phy 1>; 27067c1dffd4SDmitry Baryshkov clock-names = "bi_tcxo", 27077c1dffd4SDmitry Baryshkov "dsi0_phy_pll_out_byteclk", 27087c1dffd4SDmitry Baryshkov "dsi0_phy_pll_out_dsiclk", 27097c1dffd4SDmitry Baryshkov "dsi1_phy_pll_out_byteclk", 27107c1dffd4SDmitry Baryshkov "dsi1_phy_pll_out_dsiclk", 2711888771a9SJonathan Marek "dp_phy_pll_link_clk", 2712888771a9SJonathan Marek "dp_phy_pll_vco_div_clk"; 27137c1dffd4SDmitry Baryshkov #clock-cells = <1>; 27147c1dffd4SDmitry Baryshkov #reset-cells = <1>; 27157c1dffd4SDmitry Baryshkov #power-domain-cells = <1>; 27167c1dffd4SDmitry Baryshkov }; 27177c1dffd4SDmitry Baryshkov 271860378f1aSVenkata Narendra Kumar Gutta pdc: interrupt-controller@b220000 { 271924003196SBjorn Andersson compatible = "qcom,sm8250-pdc", "qcom,pdc"; 272024003196SBjorn Andersson reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 272160378f1aSVenkata Narendra Kumar Gutta qcom,pdc-ranges = <0 480 94>, <94 609 31>, 272260378f1aSVenkata Narendra Kumar Gutta <125 63 1>, <126 716 12>; 272360378f1aSVenkata Narendra Kumar Gutta #interrupt-cells = <2>; 272460378f1aSVenkata Narendra Kumar Gutta interrupt-parent = <&intc>; 272560378f1aSVenkata Narendra Kumar Gutta interrupt-controller; 272660378f1aSVenkata Narendra Kumar Gutta }; 272760378f1aSVenkata Narendra Kumar Gutta 2728bac12f25SAmit Kucheria tsens0: thermal-sensor@c263000 { 2729bac12f25SAmit Kucheria compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 2730bac12f25SAmit Kucheria reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2731bac12f25SAmit Kucheria <0 0x0c222000 0 0x1ff>; /* SROT */ 2732bac12f25SAmit Kucheria #qcom,sensors = <16>; 2733bac12f25SAmit Kucheria interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2734bac12f25SAmit Kucheria <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2735bac12f25SAmit Kucheria interrupt-names = "uplow", "critical"; 2736bac12f25SAmit Kucheria #thermal-sensor-cells = <1>; 2737bac12f25SAmit Kucheria }; 2738bac12f25SAmit Kucheria 2739bac12f25SAmit Kucheria tsens1: thermal-sensor@c265000 { 2740bac12f25SAmit Kucheria compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 2741bac12f25SAmit Kucheria reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2742bac12f25SAmit Kucheria <0 0x0c223000 0 0x1ff>; /* SROT */ 2743bac12f25SAmit Kucheria #qcom,sensors = <9>; 2744bac12f25SAmit Kucheria interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2745bac12f25SAmit Kucheria <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2746bac12f25SAmit Kucheria interrupt-names = "uplow", "critical"; 2747bac12f25SAmit Kucheria #thermal-sensor-cells = <1>; 2748bac12f25SAmit Kucheria }; 2749bac12f25SAmit Kucheria 275043f14a0bSSai Prakash Ranjan aoss_qmp: power-controller@c300000 { 2751087d537aSBjorn Andersson compatible = "qcom,sm8250-aoss-qmp"; 2752087d537aSBjorn Andersson reg = <0 0x0c300000 0 0x100000>; 2753087d537aSBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2754087d537aSBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 2755087d537aSBjorn Andersson IRQ_TYPE_EDGE_RISING>; 2756087d537aSBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_AOP 2757087d537aSBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 2758087d537aSBjorn Andersson 2759087d537aSBjorn Andersson #clock-cells = <0>; 2760087d537aSBjorn Andersson #power-domain-cells = <1>; 2761087d537aSBjorn Andersson }; 2762087d537aSBjorn Andersson 2763bccc7dd2SJonathan Marek spmi_bus: spmi@c440000 { 276460378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,spmi-pmic-arb"; 276560378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x0c440000 0x0 0x0001100>, 276660378f1aSVenkata Narendra Kumar Gutta <0x0 0x0c600000 0x0 0x2000000>, 276760378f1aSVenkata Narendra Kumar Gutta <0x0 0x0e600000 0x0 0x0100000>, 276860378f1aSVenkata Narendra Kumar Gutta <0x0 0x0e700000 0x0 0x00a0000>, 276960378f1aSVenkata Narendra Kumar Gutta <0x0 0x0c40a000 0x0 0x0026000>; 277060378f1aSVenkata Narendra Kumar Gutta reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 277160378f1aSVenkata Narendra Kumar Gutta interrupt-names = "periph_irq"; 277260378f1aSVenkata Narendra Kumar Gutta interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 277360378f1aSVenkata Narendra Kumar Gutta qcom,ee = <0>; 277460378f1aSVenkata Narendra Kumar Gutta qcom,channel = <0>; 277560378f1aSVenkata Narendra Kumar Gutta #address-cells = <2>; 277660378f1aSVenkata Narendra Kumar Gutta #size-cells = <0>; 277760378f1aSVenkata Narendra Kumar Gutta interrupt-controller; 277860378f1aSVenkata Narendra Kumar Gutta #interrupt-cells = <4>; 277960378f1aSVenkata Narendra Kumar Gutta }; 278060378f1aSVenkata Narendra Kumar Gutta 278116951b49SBjorn Andersson tlmm: pinctrl@f100000 { 278216951b49SBjorn Andersson compatible = "qcom,sm8250-pinctrl"; 278316951b49SBjorn Andersson reg = <0 0x0f100000 0 0x300000>, 278416951b49SBjorn Andersson <0 0x0f500000 0 0x300000>, 278516951b49SBjorn Andersson <0 0x0f900000 0 0x300000>; 278616951b49SBjorn Andersson reg-names = "west", "south", "north"; 278716951b49SBjorn Andersson interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 278816951b49SBjorn Andersson gpio-controller; 278916951b49SBjorn Andersson #gpio-cells = <2>; 279016951b49SBjorn Andersson interrupt-controller; 279116951b49SBjorn Andersson #interrupt-cells = <2>; 2792e526cb03SShawn Guo gpio-ranges = <&tlmm 0 0 181>; 279316951b49SBjorn Andersson wakeup-parent = <&pdc>; 2794e5813b15SDmitry Baryshkov 2795b657d372SSrinivas Kandagatla pri_mi2s_active: pri-mi2s-active { 2796b657d372SSrinivas Kandagatla sclk { 2797b657d372SSrinivas Kandagatla pins = "gpio138"; 2798b657d372SSrinivas Kandagatla function = "mi2s0_sck"; 2799b657d372SSrinivas Kandagatla drive-strength = <8>; 2800b657d372SSrinivas Kandagatla bias-disable; 2801b657d372SSrinivas Kandagatla }; 2802b657d372SSrinivas Kandagatla 2803b657d372SSrinivas Kandagatla ws { 2804b657d372SSrinivas Kandagatla pins = "gpio141"; 2805b657d372SSrinivas Kandagatla function = "mi2s0_ws"; 2806b657d372SSrinivas Kandagatla drive-strength = <8>; 2807b657d372SSrinivas Kandagatla output-high; 2808b657d372SSrinivas Kandagatla }; 2809b657d372SSrinivas Kandagatla 2810b657d372SSrinivas Kandagatla data0 { 2811b657d372SSrinivas Kandagatla pins = "gpio139"; 2812b657d372SSrinivas Kandagatla function = "mi2s0_data0"; 2813b657d372SSrinivas Kandagatla drive-strength = <8>; 2814b657d372SSrinivas Kandagatla bias-disable; 2815b657d372SSrinivas Kandagatla output-high; 2816b657d372SSrinivas Kandagatla }; 2817b657d372SSrinivas Kandagatla 2818b657d372SSrinivas Kandagatla data1 { 2819b657d372SSrinivas Kandagatla pins = "gpio140"; 2820b657d372SSrinivas Kandagatla function = "mi2s0_data1"; 2821b657d372SSrinivas Kandagatla drive-strength = <8>; 2822b657d372SSrinivas Kandagatla output-high; 2823b657d372SSrinivas Kandagatla }; 2824b657d372SSrinivas Kandagatla }; 2825b657d372SSrinivas Kandagatla 2826e5813b15SDmitry Baryshkov qup_i2c0_default: qup-i2c0-default { 2827e5813b15SDmitry Baryshkov mux { 2828e5813b15SDmitry Baryshkov pins = "gpio28", "gpio29"; 2829e5813b15SDmitry Baryshkov function = "qup0"; 2830e5813b15SDmitry Baryshkov }; 2831e5813b15SDmitry Baryshkov 2832e5813b15SDmitry Baryshkov config { 2833e5813b15SDmitry Baryshkov pins = "gpio28", "gpio29"; 2834e5813b15SDmitry Baryshkov drive-strength = <2>; 2835e5813b15SDmitry Baryshkov bias-disable; 2836e5813b15SDmitry Baryshkov }; 2837e5813b15SDmitry Baryshkov }; 2838e5813b15SDmitry Baryshkov 2839e5813b15SDmitry Baryshkov qup_i2c1_default: qup-i2c1-default { 2840e5813b15SDmitry Baryshkov pinmux { 2841e5813b15SDmitry Baryshkov pins = "gpio4", "gpio5"; 2842e5813b15SDmitry Baryshkov function = "qup1"; 2843e5813b15SDmitry Baryshkov }; 2844e5813b15SDmitry Baryshkov 2845e5813b15SDmitry Baryshkov config { 2846e5813b15SDmitry Baryshkov pins = "gpio4", "gpio5"; 2847e5813b15SDmitry Baryshkov drive-strength = <2>; 2848e5813b15SDmitry Baryshkov bias-disable; 2849e5813b15SDmitry Baryshkov }; 2850e5813b15SDmitry Baryshkov }; 2851e5813b15SDmitry Baryshkov 2852e5813b15SDmitry Baryshkov qup_i2c2_default: qup-i2c2-default { 2853e5813b15SDmitry Baryshkov mux { 2854e5813b15SDmitry Baryshkov pins = "gpio115", "gpio116"; 2855e5813b15SDmitry Baryshkov function = "qup2"; 2856e5813b15SDmitry Baryshkov }; 2857e5813b15SDmitry Baryshkov 2858e5813b15SDmitry Baryshkov config { 2859e5813b15SDmitry Baryshkov pins = "gpio115", "gpio116"; 2860e5813b15SDmitry Baryshkov drive-strength = <2>; 2861e5813b15SDmitry Baryshkov bias-disable; 2862e5813b15SDmitry Baryshkov }; 2863e5813b15SDmitry Baryshkov }; 2864e5813b15SDmitry Baryshkov 2865e5813b15SDmitry Baryshkov qup_i2c3_default: qup-i2c3-default { 2866e5813b15SDmitry Baryshkov mux { 2867e5813b15SDmitry Baryshkov pins = "gpio119", "gpio120"; 2868e5813b15SDmitry Baryshkov function = "qup3"; 2869e5813b15SDmitry Baryshkov }; 2870e5813b15SDmitry Baryshkov 2871e5813b15SDmitry Baryshkov config { 2872e5813b15SDmitry Baryshkov pins = "gpio119", "gpio120"; 2873e5813b15SDmitry Baryshkov drive-strength = <2>; 2874e5813b15SDmitry Baryshkov bias-disable; 2875e5813b15SDmitry Baryshkov }; 2876e5813b15SDmitry Baryshkov }; 2877e5813b15SDmitry Baryshkov 2878e5813b15SDmitry Baryshkov qup_i2c4_default: qup-i2c4-default { 2879e5813b15SDmitry Baryshkov mux { 2880e5813b15SDmitry Baryshkov pins = "gpio8", "gpio9"; 2881e5813b15SDmitry Baryshkov function = "qup4"; 2882e5813b15SDmitry Baryshkov }; 2883e5813b15SDmitry Baryshkov 2884e5813b15SDmitry Baryshkov config { 2885e5813b15SDmitry Baryshkov pins = "gpio8", "gpio9"; 2886e5813b15SDmitry Baryshkov drive-strength = <2>; 2887e5813b15SDmitry Baryshkov bias-disable; 2888e5813b15SDmitry Baryshkov }; 2889e5813b15SDmitry Baryshkov }; 2890e5813b15SDmitry Baryshkov 2891e5813b15SDmitry Baryshkov qup_i2c5_default: qup-i2c5-default { 2892e5813b15SDmitry Baryshkov mux { 2893e5813b15SDmitry Baryshkov pins = "gpio12", "gpio13"; 2894e5813b15SDmitry Baryshkov function = "qup5"; 2895e5813b15SDmitry Baryshkov }; 2896e5813b15SDmitry Baryshkov 2897e5813b15SDmitry Baryshkov config { 2898e5813b15SDmitry Baryshkov pins = "gpio12", "gpio13"; 2899e5813b15SDmitry Baryshkov drive-strength = <2>; 2900e5813b15SDmitry Baryshkov bias-disable; 2901e5813b15SDmitry Baryshkov }; 2902e5813b15SDmitry Baryshkov }; 2903e5813b15SDmitry Baryshkov 2904e5813b15SDmitry Baryshkov qup_i2c6_default: qup-i2c6-default { 2905e5813b15SDmitry Baryshkov mux { 2906e5813b15SDmitry Baryshkov pins = "gpio16", "gpio17"; 2907e5813b15SDmitry Baryshkov function = "qup6"; 2908e5813b15SDmitry Baryshkov }; 2909e5813b15SDmitry Baryshkov 2910e5813b15SDmitry Baryshkov config { 2911e5813b15SDmitry Baryshkov pins = "gpio16", "gpio17"; 2912e5813b15SDmitry Baryshkov drive-strength = <2>; 2913e5813b15SDmitry Baryshkov bias-disable; 2914e5813b15SDmitry Baryshkov }; 2915e5813b15SDmitry Baryshkov }; 2916e5813b15SDmitry Baryshkov 2917e5813b15SDmitry Baryshkov qup_i2c7_default: qup-i2c7-default { 2918e5813b15SDmitry Baryshkov mux { 2919e5813b15SDmitry Baryshkov pins = "gpio20", "gpio21"; 2920e5813b15SDmitry Baryshkov function = "qup7"; 2921e5813b15SDmitry Baryshkov }; 2922e5813b15SDmitry Baryshkov 2923e5813b15SDmitry Baryshkov config { 2924e5813b15SDmitry Baryshkov pins = "gpio20", "gpio21"; 2925e5813b15SDmitry Baryshkov drive-strength = <2>; 2926e5813b15SDmitry Baryshkov bias-disable; 2927e5813b15SDmitry Baryshkov }; 2928e5813b15SDmitry Baryshkov }; 2929e5813b15SDmitry Baryshkov 2930e5813b15SDmitry Baryshkov qup_i2c8_default: qup-i2c8-default { 2931e5813b15SDmitry Baryshkov mux { 2932e5813b15SDmitry Baryshkov pins = "gpio24", "gpio25"; 2933e5813b15SDmitry Baryshkov function = "qup8"; 2934e5813b15SDmitry Baryshkov }; 2935e5813b15SDmitry Baryshkov 2936e5813b15SDmitry Baryshkov config { 2937e5813b15SDmitry Baryshkov pins = "gpio24", "gpio25"; 2938e5813b15SDmitry Baryshkov drive-strength = <2>; 2939e5813b15SDmitry Baryshkov bias-disable; 2940e5813b15SDmitry Baryshkov }; 2941e5813b15SDmitry Baryshkov }; 2942e5813b15SDmitry Baryshkov 2943e5813b15SDmitry Baryshkov qup_i2c9_default: qup-i2c9-default { 2944e5813b15SDmitry Baryshkov mux { 2945e5813b15SDmitry Baryshkov pins = "gpio125", "gpio126"; 2946e5813b15SDmitry Baryshkov function = "qup9"; 2947e5813b15SDmitry Baryshkov }; 2948e5813b15SDmitry Baryshkov 2949e5813b15SDmitry Baryshkov config { 2950e5813b15SDmitry Baryshkov pins = "gpio125", "gpio126"; 2951e5813b15SDmitry Baryshkov drive-strength = <2>; 2952e5813b15SDmitry Baryshkov bias-disable; 2953e5813b15SDmitry Baryshkov }; 2954e5813b15SDmitry Baryshkov }; 2955e5813b15SDmitry Baryshkov 2956e5813b15SDmitry Baryshkov qup_i2c10_default: qup-i2c10-default { 2957e5813b15SDmitry Baryshkov mux { 2958e5813b15SDmitry Baryshkov pins = "gpio129", "gpio130"; 2959e5813b15SDmitry Baryshkov function = "qup10"; 2960e5813b15SDmitry Baryshkov }; 2961e5813b15SDmitry Baryshkov 2962e5813b15SDmitry Baryshkov config { 2963e5813b15SDmitry Baryshkov pins = "gpio129", "gpio130"; 2964e5813b15SDmitry Baryshkov drive-strength = <2>; 2965e5813b15SDmitry Baryshkov bias-disable; 2966e5813b15SDmitry Baryshkov }; 2967e5813b15SDmitry Baryshkov }; 2968e5813b15SDmitry Baryshkov 2969e5813b15SDmitry Baryshkov qup_i2c11_default: qup-i2c11-default { 2970e5813b15SDmitry Baryshkov mux { 2971e5813b15SDmitry Baryshkov pins = "gpio60", "gpio61"; 2972e5813b15SDmitry Baryshkov function = "qup11"; 2973e5813b15SDmitry Baryshkov }; 2974e5813b15SDmitry Baryshkov 2975e5813b15SDmitry Baryshkov config { 2976e5813b15SDmitry Baryshkov pins = "gpio60", "gpio61"; 2977e5813b15SDmitry Baryshkov drive-strength = <2>; 2978e5813b15SDmitry Baryshkov bias-disable; 2979e5813b15SDmitry Baryshkov }; 2980e5813b15SDmitry Baryshkov }; 2981e5813b15SDmitry Baryshkov 2982e5813b15SDmitry Baryshkov qup_i2c12_default: qup-i2c12-default { 2983e5813b15SDmitry Baryshkov mux { 2984e5813b15SDmitry Baryshkov pins = "gpio32", "gpio33"; 2985e5813b15SDmitry Baryshkov function = "qup12"; 2986e5813b15SDmitry Baryshkov }; 2987e5813b15SDmitry Baryshkov 2988e5813b15SDmitry Baryshkov config { 2989e5813b15SDmitry Baryshkov pins = "gpio32", "gpio33"; 2990e5813b15SDmitry Baryshkov drive-strength = <2>; 2991e5813b15SDmitry Baryshkov bias-disable; 2992e5813b15SDmitry Baryshkov }; 2993e5813b15SDmitry Baryshkov }; 2994e5813b15SDmitry Baryshkov 2995e5813b15SDmitry Baryshkov qup_i2c13_default: qup-i2c13-default { 2996e5813b15SDmitry Baryshkov mux { 2997e5813b15SDmitry Baryshkov pins = "gpio36", "gpio37"; 2998e5813b15SDmitry Baryshkov function = "qup13"; 2999e5813b15SDmitry Baryshkov }; 3000e5813b15SDmitry Baryshkov 3001e5813b15SDmitry Baryshkov config { 3002e5813b15SDmitry Baryshkov pins = "gpio36", "gpio37"; 3003e5813b15SDmitry Baryshkov drive-strength = <2>; 3004e5813b15SDmitry Baryshkov bias-disable; 3005e5813b15SDmitry Baryshkov }; 3006e5813b15SDmitry Baryshkov }; 3007e5813b15SDmitry Baryshkov 3008e5813b15SDmitry Baryshkov qup_i2c14_default: qup-i2c14-default { 3009e5813b15SDmitry Baryshkov mux { 3010e5813b15SDmitry Baryshkov pins = "gpio40", "gpio41"; 3011e5813b15SDmitry Baryshkov function = "qup14"; 3012e5813b15SDmitry Baryshkov }; 3013e5813b15SDmitry Baryshkov 3014e5813b15SDmitry Baryshkov config { 3015e5813b15SDmitry Baryshkov pins = "gpio40", "gpio41"; 3016e5813b15SDmitry Baryshkov drive-strength = <2>; 3017e5813b15SDmitry Baryshkov bias-disable; 3018e5813b15SDmitry Baryshkov }; 3019e5813b15SDmitry Baryshkov }; 3020e5813b15SDmitry Baryshkov 3021e5813b15SDmitry Baryshkov qup_i2c15_default: qup-i2c15-default { 3022e5813b15SDmitry Baryshkov mux { 3023e5813b15SDmitry Baryshkov pins = "gpio44", "gpio45"; 3024e5813b15SDmitry Baryshkov function = "qup15"; 3025e5813b15SDmitry Baryshkov }; 3026e5813b15SDmitry Baryshkov 3027e5813b15SDmitry Baryshkov config { 3028e5813b15SDmitry Baryshkov pins = "gpio44", "gpio45"; 3029e5813b15SDmitry Baryshkov drive-strength = <2>; 3030e5813b15SDmitry Baryshkov bias-disable; 3031e5813b15SDmitry Baryshkov }; 3032e5813b15SDmitry Baryshkov }; 3033e5813b15SDmitry Baryshkov 3034e5813b15SDmitry Baryshkov qup_i2c16_default: qup-i2c16-default { 3035e5813b15SDmitry Baryshkov mux { 3036e5813b15SDmitry Baryshkov pins = "gpio48", "gpio49"; 3037e5813b15SDmitry Baryshkov function = "qup16"; 3038e5813b15SDmitry Baryshkov }; 3039e5813b15SDmitry Baryshkov 3040e5813b15SDmitry Baryshkov config { 3041e5813b15SDmitry Baryshkov pins = "gpio48", "gpio49"; 3042e5813b15SDmitry Baryshkov drive-strength = <2>; 3043e5813b15SDmitry Baryshkov bias-disable; 3044e5813b15SDmitry Baryshkov }; 3045e5813b15SDmitry Baryshkov }; 3046e5813b15SDmitry Baryshkov 3047e5813b15SDmitry Baryshkov qup_i2c17_default: qup-i2c17-default { 3048e5813b15SDmitry Baryshkov mux { 3049e5813b15SDmitry Baryshkov pins = "gpio52", "gpio53"; 3050e5813b15SDmitry Baryshkov function = "qup17"; 3051e5813b15SDmitry Baryshkov }; 3052e5813b15SDmitry Baryshkov 3053e5813b15SDmitry Baryshkov config { 3054e5813b15SDmitry Baryshkov pins = "gpio52", "gpio53"; 3055e5813b15SDmitry Baryshkov drive-strength = <2>; 3056e5813b15SDmitry Baryshkov bias-disable; 3057e5813b15SDmitry Baryshkov }; 3058e5813b15SDmitry Baryshkov }; 3059e5813b15SDmitry Baryshkov 3060e5813b15SDmitry Baryshkov qup_i2c18_default: qup-i2c18-default { 3061e5813b15SDmitry Baryshkov mux { 3062e5813b15SDmitry Baryshkov pins = "gpio56", "gpio57"; 3063e5813b15SDmitry Baryshkov function = "qup18"; 3064e5813b15SDmitry Baryshkov }; 3065e5813b15SDmitry Baryshkov 3066e5813b15SDmitry Baryshkov config { 3067e5813b15SDmitry Baryshkov pins = "gpio56", "gpio57"; 3068e5813b15SDmitry Baryshkov drive-strength = <2>; 3069e5813b15SDmitry Baryshkov bias-disable; 3070e5813b15SDmitry Baryshkov }; 3071e5813b15SDmitry Baryshkov }; 3072e5813b15SDmitry Baryshkov 3073e5813b15SDmitry Baryshkov qup_i2c19_default: qup-i2c19-default { 3074e5813b15SDmitry Baryshkov mux { 3075e5813b15SDmitry Baryshkov pins = "gpio0", "gpio1"; 3076e5813b15SDmitry Baryshkov function = "qup19"; 3077e5813b15SDmitry Baryshkov }; 3078e5813b15SDmitry Baryshkov 3079e5813b15SDmitry Baryshkov config { 3080e5813b15SDmitry Baryshkov pins = "gpio0", "gpio1"; 3081e5813b15SDmitry Baryshkov drive-strength = <2>; 3082e5813b15SDmitry Baryshkov bias-disable; 3083e5813b15SDmitry Baryshkov }; 3084e5813b15SDmitry Baryshkov }; 3085e5813b15SDmitry Baryshkov 3086c88f9eccSDmitry Baryshkov qup_spi0_cs: qup-spi0-cs { 3087c88f9eccSDmitry Baryshkov pins = "gpio31"; 3088e5813b15SDmitry Baryshkov function = "qup0"; 3089e5813b15SDmitry Baryshkov }; 3090e5813b15SDmitry Baryshkov 3091eb97ccbbSDmitry Baryshkov qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3092eb97ccbbSDmitry Baryshkov pins = "gpio31"; 3093eb97ccbbSDmitry Baryshkov function = "gpio"; 3094eb97ccbbSDmitry Baryshkov }; 3095eb97ccbbSDmitry Baryshkov 3096c88f9eccSDmitry Baryshkov qup_spi0_data_clk: qup-spi0-data-clk { 3097c88f9eccSDmitry Baryshkov pins = "gpio28", "gpio29", 3098c88f9eccSDmitry Baryshkov "gpio30"; 3099c88f9eccSDmitry Baryshkov function = "qup0"; 3100c88f9eccSDmitry Baryshkov }; 3101c88f9eccSDmitry Baryshkov 3102c88f9eccSDmitry Baryshkov qup_spi1_cs: qup-spi1-cs { 3103c88f9eccSDmitry Baryshkov pins = "gpio7"; 3104e5813b15SDmitry Baryshkov function = "qup1"; 3105e5813b15SDmitry Baryshkov }; 3106e5813b15SDmitry Baryshkov 3107eb97ccbbSDmitry Baryshkov qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3108eb97ccbbSDmitry Baryshkov pins = "gpio7"; 3109eb97ccbbSDmitry Baryshkov function = "gpio"; 3110eb97ccbbSDmitry Baryshkov }; 3111eb97ccbbSDmitry Baryshkov 3112c88f9eccSDmitry Baryshkov qup_spi1_data_clk: qup-spi1-data-clk { 3113c88f9eccSDmitry Baryshkov pins = "gpio4", "gpio5", 3114c88f9eccSDmitry Baryshkov "gpio6"; 3115c88f9eccSDmitry Baryshkov function = "qup1"; 3116c88f9eccSDmitry Baryshkov }; 3117c88f9eccSDmitry Baryshkov 3118c88f9eccSDmitry Baryshkov qup_spi2_cs: qup-spi2-cs { 3119c88f9eccSDmitry Baryshkov pins = "gpio118"; 3120e5813b15SDmitry Baryshkov function = "qup2"; 3121e5813b15SDmitry Baryshkov }; 3122e5813b15SDmitry Baryshkov 3123eb97ccbbSDmitry Baryshkov qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3124eb97ccbbSDmitry Baryshkov pins = "gpio118"; 3125eb97ccbbSDmitry Baryshkov function = "gpio"; 3126eb97ccbbSDmitry Baryshkov }; 3127eb97ccbbSDmitry Baryshkov 3128c88f9eccSDmitry Baryshkov qup_spi2_data_clk: qup-spi2-data-clk { 3129c88f9eccSDmitry Baryshkov pins = "gpio115", "gpio116", 3130c88f9eccSDmitry Baryshkov "gpio117"; 3131c88f9eccSDmitry Baryshkov function = "qup2"; 3132c88f9eccSDmitry Baryshkov }; 3133c88f9eccSDmitry Baryshkov 3134c88f9eccSDmitry Baryshkov qup_spi3_cs: qup-spi3-cs { 3135c88f9eccSDmitry Baryshkov pins = "gpio122"; 3136e5813b15SDmitry Baryshkov function = "qup3"; 3137e5813b15SDmitry Baryshkov }; 3138e5813b15SDmitry Baryshkov 3139eb97ccbbSDmitry Baryshkov qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3140eb97ccbbSDmitry Baryshkov pins = "gpio122"; 3141eb97ccbbSDmitry Baryshkov function = "gpio"; 3142eb97ccbbSDmitry Baryshkov }; 3143eb97ccbbSDmitry Baryshkov 3144c88f9eccSDmitry Baryshkov qup_spi3_data_clk: qup-spi3-data-clk { 3145c88f9eccSDmitry Baryshkov pins = "gpio119", "gpio120", 3146c88f9eccSDmitry Baryshkov "gpio121"; 3147c88f9eccSDmitry Baryshkov function = "qup3"; 3148c88f9eccSDmitry Baryshkov }; 3149c88f9eccSDmitry Baryshkov 3150c88f9eccSDmitry Baryshkov qup_spi4_cs: qup-spi4-cs { 3151c88f9eccSDmitry Baryshkov pins = "gpio11"; 3152e5813b15SDmitry Baryshkov function = "qup4"; 3153e5813b15SDmitry Baryshkov }; 3154e5813b15SDmitry Baryshkov 3155eb97ccbbSDmitry Baryshkov qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3156eb97ccbbSDmitry Baryshkov pins = "gpio11"; 3157eb97ccbbSDmitry Baryshkov function = "gpio"; 3158eb97ccbbSDmitry Baryshkov }; 3159eb97ccbbSDmitry Baryshkov 3160c88f9eccSDmitry Baryshkov qup_spi4_data_clk: qup-spi4-data-clk { 3161c88f9eccSDmitry Baryshkov pins = "gpio8", "gpio9", 3162c88f9eccSDmitry Baryshkov "gpio10"; 3163c88f9eccSDmitry Baryshkov function = "qup4"; 3164c88f9eccSDmitry Baryshkov }; 3165c88f9eccSDmitry Baryshkov 3166c88f9eccSDmitry Baryshkov qup_spi5_cs: qup-spi5-cs { 3167c88f9eccSDmitry Baryshkov pins = "gpio15"; 3168e5813b15SDmitry Baryshkov function = "qup5"; 3169e5813b15SDmitry Baryshkov }; 3170e5813b15SDmitry Baryshkov 3171eb97ccbbSDmitry Baryshkov qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3172eb97ccbbSDmitry Baryshkov pins = "gpio15"; 3173eb97ccbbSDmitry Baryshkov function = "gpio"; 3174eb97ccbbSDmitry Baryshkov }; 3175eb97ccbbSDmitry Baryshkov 3176c88f9eccSDmitry Baryshkov qup_spi5_data_clk: qup-spi5-data-clk { 3177c88f9eccSDmitry Baryshkov pins = "gpio12", "gpio13", 3178c88f9eccSDmitry Baryshkov "gpio14"; 3179c88f9eccSDmitry Baryshkov function = "qup5"; 3180c88f9eccSDmitry Baryshkov }; 3181c88f9eccSDmitry Baryshkov 3182c88f9eccSDmitry Baryshkov qup_spi6_cs: qup-spi6-cs { 3183c88f9eccSDmitry Baryshkov pins = "gpio19"; 3184e5813b15SDmitry Baryshkov function = "qup6"; 3185e5813b15SDmitry Baryshkov }; 3186e5813b15SDmitry Baryshkov 3187eb97ccbbSDmitry Baryshkov qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3188eb97ccbbSDmitry Baryshkov pins = "gpio19"; 3189eb97ccbbSDmitry Baryshkov function = "gpio"; 3190eb97ccbbSDmitry Baryshkov }; 3191eb97ccbbSDmitry Baryshkov 3192c88f9eccSDmitry Baryshkov qup_spi6_data_clk: qup-spi6-data-clk { 3193c88f9eccSDmitry Baryshkov pins = "gpio16", "gpio17", 3194c88f9eccSDmitry Baryshkov "gpio18"; 3195c88f9eccSDmitry Baryshkov function = "qup6"; 3196c88f9eccSDmitry Baryshkov }; 3197c88f9eccSDmitry Baryshkov 3198c88f9eccSDmitry Baryshkov qup_spi7_cs: qup-spi7-cs { 3199c88f9eccSDmitry Baryshkov pins = "gpio23"; 3200e5813b15SDmitry Baryshkov function = "qup7"; 3201e5813b15SDmitry Baryshkov }; 3202e5813b15SDmitry Baryshkov 3203eb97ccbbSDmitry Baryshkov qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3204eb97ccbbSDmitry Baryshkov pins = "gpio23"; 3205eb97ccbbSDmitry Baryshkov function = "gpio"; 3206eb97ccbbSDmitry Baryshkov }; 3207eb97ccbbSDmitry Baryshkov 3208c88f9eccSDmitry Baryshkov qup_spi7_data_clk: qup-spi7-data-clk { 3209c88f9eccSDmitry Baryshkov pins = "gpio20", "gpio21", 3210c88f9eccSDmitry Baryshkov "gpio22"; 3211c88f9eccSDmitry Baryshkov function = "qup7"; 3212c88f9eccSDmitry Baryshkov }; 3213c88f9eccSDmitry Baryshkov 3214c88f9eccSDmitry Baryshkov qup_spi8_cs: qup-spi8-cs { 3215c88f9eccSDmitry Baryshkov pins = "gpio27"; 3216e5813b15SDmitry Baryshkov function = "qup8"; 3217e5813b15SDmitry Baryshkov }; 3218e5813b15SDmitry Baryshkov 3219eb97ccbbSDmitry Baryshkov qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3220eb97ccbbSDmitry Baryshkov pins = "gpio27"; 3221eb97ccbbSDmitry Baryshkov function = "gpio"; 3222eb97ccbbSDmitry Baryshkov }; 3223eb97ccbbSDmitry Baryshkov 3224c88f9eccSDmitry Baryshkov qup_spi8_data_clk: qup-spi8-data-clk { 3225c88f9eccSDmitry Baryshkov pins = "gpio24", "gpio25", 3226c88f9eccSDmitry Baryshkov "gpio26"; 3227c88f9eccSDmitry Baryshkov function = "qup8"; 3228c88f9eccSDmitry Baryshkov }; 3229c88f9eccSDmitry Baryshkov 3230c88f9eccSDmitry Baryshkov qup_spi9_cs: qup-spi9-cs { 3231c88f9eccSDmitry Baryshkov pins = "gpio128"; 3232e5813b15SDmitry Baryshkov function = "qup9"; 3233e5813b15SDmitry Baryshkov }; 3234e5813b15SDmitry Baryshkov 3235eb97ccbbSDmitry Baryshkov qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3236eb97ccbbSDmitry Baryshkov pins = "gpio128"; 3237eb97ccbbSDmitry Baryshkov function = "gpio"; 3238eb97ccbbSDmitry Baryshkov }; 3239eb97ccbbSDmitry Baryshkov 3240c88f9eccSDmitry Baryshkov qup_spi9_data_clk: qup-spi9-data-clk { 3241c88f9eccSDmitry Baryshkov pins = "gpio125", "gpio126", 3242c88f9eccSDmitry Baryshkov "gpio127"; 3243c88f9eccSDmitry Baryshkov function = "qup9"; 3244c88f9eccSDmitry Baryshkov }; 3245c88f9eccSDmitry Baryshkov 3246c88f9eccSDmitry Baryshkov qup_spi10_cs: qup-spi10-cs { 3247c88f9eccSDmitry Baryshkov pins = "gpio132"; 3248e5813b15SDmitry Baryshkov function = "qup10"; 3249e5813b15SDmitry Baryshkov }; 3250e5813b15SDmitry Baryshkov 3251eb97ccbbSDmitry Baryshkov qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3252eb97ccbbSDmitry Baryshkov pins = "gpio132"; 3253eb97ccbbSDmitry Baryshkov function = "gpio"; 3254eb97ccbbSDmitry Baryshkov }; 3255eb97ccbbSDmitry Baryshkov 3256c88f9eccSDmitry Baryshkov qup_spi10_data_clk: qup-spi10-data-clk { 3257c88f9eccSDmitry Baryshkov pins = "gpio129", "gpio130", 3258c88f9eccSDmitry Baryshkov "gpio131"; 3259c88f9eccSDmitry Baryshkov function = "qup10"; 3260c88f9eccSDmitry Baryshkov }; 3261c88f9eccSDmitry Baryshkov 3262c88f9eccSDmitry Baryshkov qup_spi11_cs: qup-spi11-cs { 3263c88f9eccSDmitry Baryshkov pins = "gpio63"; 3264e5813b15SDmitry Baryshkov function = "qup11"; 3265e5813b15SDmitry Baryshkov }; 3266e5813b15SDmitry Baryshkov 3267eb97ccbbSDmitry Baryshkov qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3268eb97ccbbSDmitry Baryshkov pins = "gpio63"; 3269eb97ccbbSDmitry Baryshkov function = "gpio"; 3270eb97ccbbSDmitry Baryshkov }; 3271eb97ccbbSDmitry Baryshkov 3272c88f9eccSDmitry Baryshkov qup_spi11_data_clk: qup-spi11-data-clk { 3273c88f9eccSDmitry Baryshkov pins = "gpio60", "gpio61", 3274c88f9eccSDmitry Baryshkov "gpio62"; 3275c88f9eccSDmitry Baryshkov function = "qup11"; 3276c88f9eccSDmitry Baryshkov }; 3277c88f9eccSDmitry Baryshkov 3278c88f9eccSDmitry Baryshkov qup_spi12_cs: qup-spi12-cs { 3279c88f9eccSDmitry Baryshkov pins = "gpio35"; 3280e5813b15SDmitry Baryshkov function = "qup12"; 3281e5813b15SDmitry Baryshkov }; 3282e5813b15SDmitry Baryshkov 3283eb97ccbbSDmitry Baryshkov qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3284eb97ccbbSDmitry Baryshkov pins = "gpio35"; 3285eb97ccbbSDmitry Baryshkov function = "gpio"; 3286eb97ccbbSDmitry Baryshkov }; 3287eb97ccbbSDmitry Baryshkov 3288c88f9eccSDmitry Baryshkov qup_spi12_data_clk: qup-spi12-data-clk { 3289c88f9eccSDmitry Baryshkov pins = "gpio32", "gpio33", 3290c88f9eccSDmitry Baryshkov "gpio34"; 3291c88f9eccSDmitry Baryshkov function = "qup12"; 3292c88f9eccSDmitry Baryshkov }; 3293c88f9eccSDmitry Baryshkov 3294c88f9eccSDmitry Baryshkov qup_spi13_cs: qup-spi13-cs { 3295c88f9eccSDmitry Baryshkov pins = "gpio39"; 3296e5813b15SDmitry Baryshkov function = "qup13"; 3297e5813b15SDmitry Baryshkov }; 3298e5813b15SDmitry Baryshkov 3299eb97ccbbSDmitry Baryshkov qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3300eb97ccbbSDmitry Baryshkov pins = "gpio39"; 3301eb97ccbbSDmitry Baryshkov function = "gpio"; 3302eb97ccbbSDmitry Baryshkov }; 3303eb97ccbbSDmitry Baryshkov 3304c88f9eccSDmitry Baryshkov qup_spi13_data_clk: qup-spi13-data-clk { 3305c88f9eccSDmitry Baryshkov pins = "gpio36", "gpio37", 3306c88f9eccSDmitry Baryshkov "gpio38"; 3307c88f9eccSDmitry Baryshkov function = "qup13"; 3308c88f9eccSDmitry Baryshkov }; 3309c88f9eccSDmitry Baryshkov 3310c88f9eccSDmitry Baryshkov qup_spi14_cs: qup-spi14-cs { 3311c88f9eccSDmitry Baryshkov pins = "gpio43"; 3312e5813b15SDmitry Baryshkov function = "qup14"; 3313e5813b15SDmitry Baryshkov }; 3314e5813b15SDmitry Baryshkov 3315eb97ccbbSDmitry Baryshkov qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3316eb97ccbbSDmitry Baryshkov pins = "gpio43"; 3317eb97ccbbSDmitry Baryshkov function = "gpio"; 3318eb97ccbbSDmitry Baryshkov }; 3319eb97ccbbSDmitry Baryshkov 3320c88f9eccSDmitry Baryshkov qup_spi14_data_clk: qup-spi14-data-clk { 3321c88f9eccSDmitry Baryshkov pins = "gpio40", "gpio41", 3322c88f9eccSDmitry Baryshkov "gpio42"; 3323c88f9eccSDmitry Baryshkov function = "qup14"; 3324c88f9eccSDmitry Baryshkov }; 3325c88f9eccSDmitry Baryshkov 3326c88f9eccSDmitry Baryshkov qup_spi15_cs: qup-spi15-cs { 3327c88f9eccSDmitry Baryshkov pins = "gpio47"; 3328e5813b15SDmitry Baryshkov function = "qup15"; 3329e5813b15SDmitry Baryshkov }; 3330e5813b15SDmitry Baryshkov 3331eb97ccbbSDmitry Baryshkov qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3332eb97ccbbSDmitry Baryshkov pins = "gpio47"; 3333eb97ccbbSDmitry Baryshkov function = "gpio"; 3334eb97ccbbSDmitry Baryshkov }; 3335eb97ccbbSDmitry Baryshkov 3336c88f9eccSDmitry Baryshkov qup_spi15_data_clk: qup-spi15-data-clk { 3337c88f9eccSDmitry Baryshkov pins = "gpio44", "gpio45", 3338c88f9eccSDmitry Baryshkov "gpio46"; 3339c88f9eccSDmitry Baryshkov function = "qup15"; 3340c88f9eccSDmitry Baryshkov }; 3341c88f9eccSDmitry Baryshkov 3342c88f9eccSDmitry Baryshkov qup_spi16_cs: qup-spi16-cs { 3343c88f9eccSDmitry Baryshkov pins = "gpio51"; 3344e5813b15SDmitry Baryshkov function = "qup16"; 3345e5813b15SDmitry Baryshkov }; 3346e5813b15SDmitry Baryshkov 3347eb97ccbbSDmitry Baryshkov qup_spi16_cs_gpio: qup-spi16-cs-gpio { 3348eb97ccbbSDmitry Baryshkov pins = "gpio51"; 3349eb97ccbbSDmitry Baryshkov function = "gpio"; 3350eb97ccbbSDmitry Baryshkov }; 3351eb97ccbbSDmitry Baryshkov 3352c88f9eccSDmitry Baryshkov qup_spi16_data_clk: qup-spi16-data-clk { 3353c88f9eccSDmitry Baryshkov pins = "gpio48", "gpio49", 3354c88f9eccSDmitry Baryshkov "gpio50"; 3355c88f9eccSDmitry Baryshkov function = "qup16"; 3356c88f9eccSDmitry Baryshkov }; 3357c88f9eccSDmitry Baryshkov 3358c88f9eccSDmitry Baryshkov qup_spi17_cs: qup-spi17-cs { 3359c88f9eccSDmitry Baryshkov pins = "gpio55"; 3360e5813b15SDmitry Baryshkov function = "qup17"; 3361e5813b15SDmitry Baryshkov }; 3362e5813b15SDmitry Baryshkov 3363eb97ccbbSDmitry Baryshkov qup_spi17_cs_gpio: qup-spi17-cs-gpio { 3364eb97ccbbSDmitry Baryshkov pins = "gpio55"; 3365eb97ccbbSDmitry Baryshkov function = "gpio"; 3366eb97ccbbSDmitry Baryshkov }; 3367eb97ccbbSDmitry Baryshkov 3368c88f9eccSDmitry Baryshkov qup_spi17_data_clk: qup-spi17-data-clk { 3369c88f9eccSDmitry Baryshkov pins = "gpio52", "gpio53", 3370c88f9eccSDmitry Baryshkov "gpio54"; 3371c88f9eccSDmitry Baryshkov function = "qup17"; 3372c88f9eccSDmitry Baryshkov }; 3373c88f9eccSDmitry Baryshkov 3374c88f9eccSDmitry Baryshkov qup_spi18_cs: qup-spi18-cs { 3375c88f9eccSDmitry Baryshkov pins = "gpio59"; 3376e5813b15SDmitry Baryshkov function = "qup18"; 3377e5813b15SDmitry Baryshkov }; 3378e5813b15SDmitry Baryshkov 3379eb97ccbbSDmitry Baryshkov qup_spi18_cs_gpio: qup-spi18-cs-gpio { 3380eb97ccbbSDmitry Baryshkov pins = "gpio59"; 3381eb97ccbbSDmitry Baryshkov function = "gpio"; 3382eb97ccbbSDmitry Baryshkov }; 3383eb97ccbbSDmitry Baryshkov 3384c88f9eccSDmitry Baryshkov qup_spi18_data_clk: qup-spi18-data-clk { 3385c88f9eccSDmitry Baryshkov pins = "gpio56", "gpio57", 3386c88f9eccSDmitry Baryshkov "gpio58"; 3387c88f9eccSDmitry Baryshkov function = "qup18"; 3388c88f9eccSDmitry Baryshkov }; 3389c88f9eccSDmitry Baryshkov 3390c88f9eccSDmitry Baryshkov qup_spi19_cs: qup-spi19-cs { 3391c88f9eccSDmitry Baryshkov pins = "gpio3"; 3392c88f9eccSDmitry Baryshkov function = "qup19"; 3393c88f9eccSDmitry Baryshkov }; 3394c88f9eccSDmitry Baryshkov 3395eb97ccbbSDmitry Baryshkov qup_spi19_cs_gpio: qup-spi19-cs-gpio { 3396eb97ccbbSDmitry Baryshkov pins = "gpio3"; 3397eb97ccbbSDmitry Baryshkov function = "gpio"; 3398eb97ccbbSDmitry Baryshkov }; 3399eb97ccbbSDmitry Baryshkov 3400c88f9eccSDmitry Baryshkov qup_spi19_data_clk: qup-spi19-data-clk { 3401e5813b15SDmitry Baryshkov pins = "gpio0", "gpio1", 3402c88f9eccSDmitry Baryshkov "gpio2"; 3403e5813b15SDmitry Baryshkov function = "qup19"; 3404e5813b15SDmitry Baryshkov }; 3405e5813b15SDmitry Baryshkov 340608a9ae2dSDmitry Baryshkov qup_uart2_default: qup-uart2-default { 340708a9ae2dSDmitry Baryshkov mux { 340808a9ae2dSDmitry Baryshkov pins = "gpio117", "gpio118"; 340908a9ae2dSDmitry Baryshkov function = "qup2"; 341008a9ae2dSDmitry Baryshkov }; 341108a9ae2dSDmitry Baryshkov }; 341208a9ae2dSDmitry Baryshkov 341308a9ae2dSDmitry Baryshkov qup_uart6_default: qup-uart6-default { 341408a9ae2dSDmitry Baryshkov mux { 341508a9ae2dSDmitry Baryshkov pins = "gpio16", "gpio17", 341608a9ae2dSDmitry Baryshkov "gpio18", "gpio19"; 341708a9ae2dSDmitry Baryshkov function = "qup6"; 341808a9ae2dSDmitry Baryshkov }; 341908a9ae2dSDmitry Baryshkov }; 342008a9ae2dSDmitry Baryshkov 3421bb1dfb4dSManivannan Sadhasivam qup_uart12_default: qup-uart12-default { 3422bb1dfb4dSManivannan Sadhasivam mux { 3423bb1dfb4dSManivannan Sadhasivam pins = "gpio34", "gpio35"; 3424bb1dfb4dSManivannan Sadhasivam function = "qup12"; 3425bb1dfb4dSManivannan Sadhasivam }; 3426bb1dfb4dSManivannan Sadhasivam }; 342708a9ae2dSDmitry Baryshkov 342808a9ae2dSDmitry Baryshkov qup_uart17_default: qup-uart17-default { 342908a9ae2dSDmitry Baryshkov mux { 343008a9ae2dSDmitry Baryshkov pins = "gpio52", "gpio53", 343108a9ae2dSDmitry Baryshkov "gpio54", "gpio55"; 343208a9ae2dSDmitry Baryshkov function = "qup17"; 343308a9ae2dSDmitry Baryshkov }; 343408a9ae2dSDmitry Baryshkov }; 343508a9ae2dSDmitry Baryshkov 343608a9ae2dSDmitry Baryshkov qup_uart18_default: qup-uart18-default { 343708a9ae2dSDmitry Baryshkov mux { 343808a9ae2dSDmitry Baryshkov pins = "gpio58", "gpio59"; 343908a9ae2dSDmitry Baryshkov function = "qup18"; 344008a9ae2dSDmitry Baryshkov }; 344108a9ae2dSDmitry Baryshkov }; 3442b657d372SSrinivas Kandagatla 3443b657d372SSrinivas Kandagatla tert_mi2s_active: tert-mi2s-active { 3444b657d372SSrinivas Kandagatla sck { 3445b657d372SSrinivas Kandagatla pins = "gpio133"; 3446b657d372SSrinivas Kandagatla function = "mi2s2_sck"; 3447b657d372SSrinivas Kandagatla drive-strength = <8>; 3448b657d372SSrinivas Kandagatla bias-disable; 3449b657d372SSrinivas Kandagatla }; 3450b657d372SSrinivas Kandagatla 3451b657d372SSrinivas Kandagatla data0 { 3452b657d372SSrinivas Kandagatla pins = "gpio134"; 3453b657d372SSrinivas Kandagatla function = "mi2s2_data0"; 3454b657d372SSrinivas Kandagatla drive-strength = <8>; 3455b657d372SSrinivas Kandagatla bias-disable; 3456b657d372SSrinivas Kandagatla output-high; 3457b657d372SSrinivas Kandagatla }; 3458b657d372SSrinivas Kandagatla 3459b657d372SSrinivas Kandagatla ws { 3460b657d372SSrinivas Kandagatla pins = "gpio135"; 3461b657d372SSrinivas Kandagatla function = "mi2s2_ws"; 3462b657d372SSrinivas Kandagatla drive-strength = <8>; 3463b657d372SSrinivas Kandagatla output-high; 3464b657d372SSrinivas Kandagatla }; 3465b657d372SSrinivas Kandagatla }; 346616951b49SBjorn Andersson }; 346716951b49SBjorn Andersson 3468a89441fcSJonathan Marek apps_smmu: iommu@15000000 { 3469a89441fcSJonathan Marek compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 3470a89441fcSJonathan Marek reg = <0 0x15000000 0 0x100000>; 3471a89441fcSJonathan Marek #iommu-cells = <2>; 3472a89441fcSJonathan Marek #global-interrupts = <2>; 3473a89441fcSJonathan Marek interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3474a89441fcSJonathan Marek <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3475a89441fcSJonathan Marek <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3476a89441fcSJonathan Marek <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3477a89441fcSJonathan Marek <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3478a89441fcSJonathan Marek <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3479a89441fcSJonathan Marek <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3480a89441fcSJonathan Marek <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3481a89441fcSJonathan Marek <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3482a89441fcSJonathan Marek <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3483a89441fcSJonathan Marek <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3484a89441fcSJonathan Marek <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3485a89441fcSJonathan Marek <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3486a89441fcSJonathan Marek <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3487a89441fcSJonathan Marek <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3488a89441fcSJonathan Marek <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3489a89441fcSJonathan Marek <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3490a89441fcSJonathan Marek <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3491a89441fcSJonathan Marek <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3492a89441fcSJonathan Marek <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3493a89441fcSJonathan Marek <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3494a89441fcSJonathan Marek <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3495a89441fcSJonathan Marek <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3496a89441fcSJonathan Marek <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3497a89441fcSJonathan Marek <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3498a89441fcSJonathan Marek <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3499a89441fcSJonathan Marek <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3500a89441fcSJonathan Marek <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3501a89441fcSJonathan Marek <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3502a89441fcSJonathan Marek <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3503a89441fcSJonathan Marek <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3504a89441fcSJonathan Marek <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3505a89441fcSJonathan Marek <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3506a89441fcSJonathan Marek <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3507a89441fcSJonathan Marek <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3508a89441fcSJonathan Marek <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3509a89441fcSJonathan Marek <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3510a89441fcSJonathan Marek <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3511a89441fcSJonathan Marek <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3512a89441fcSJonathan Marek <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3513a89441fcSJonathan Marek <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3514a89441fcSJonathan Marek <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3515a89441fcSJonathan Marek <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3516a89441fcSJonathan Marek <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3517a89441fcSJonathan Marek <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3518a89441fcSJonathan Marek <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3519a89441fcSJonathan Marek <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3520a89441fcSJonathan Marek <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3521a89441fcSJonathan Marek <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3522a89441fcSJonathan Marek <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3523a89441fcSJonathan Marek <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3524a89441fcSJonathan Marek <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3525a89441fcSJonathan Marek <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3526a89441fcSJonathan Marek <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3527a89441fcSJonathan Marek <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3528a89441fcSJonathan Marek <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3529a89441fcSJonathan Marek <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3530a89441fcSJonathan Marek <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3531a89441fcSJonathan Marek <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3532a89441fcSJonathan Marek <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3533a89441fcSJonathan Marek <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3534a89441fcSJonathan Marek <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3535a89441fcSJonathan Marek <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3536a89441fcSJonathan Marek <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3537a89441fcSJonathan Marek <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3538a89441fcSJonathan Marek <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3539a89441fcSJonathan Marek <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3540a89441fcSJonathan Marek <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3541a89441fcSJonathan Marek <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3542a89441fcSJonathan Marek <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3543a89441fcSJonathan Marek <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3544a89441fcSJonathan Marek <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3545a89441fcSJonathan Marek <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3546a89441fcSJonathan Marek <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3547a89441fcSJonathan Marek <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3548a89441fcSJonathan Marek <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3549a89441fcSJonathan Marek <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3550a89441fcSJonathan Marek <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3551a89441fcSJonathan Marek <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3552a89441fcSJonathan Marek <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3553a89441fcSJonathan Marek <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3554a89441fcSJonathan Marek <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3555a89441fcSJonathan Marek <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3556a89441fcSJonathan Marek <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3557a89441fcSJonathan Marek <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3558a89441fcSJonathan Marek <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3559a89441fcSJonathan Marek <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3560a89441fcSJonathan Marek <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3561a89441fcSJonathan Marek <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3562a89441fcSJonathan Marek <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3563a89441fcSJonathan Marek <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3564a89441fcSJonathan Marek <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3565a89441fcSJonathan Marek <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3566a89441fcSJonathan Marek <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3567a89441fcSJonathan Marek <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3568a89441fcSJonathan Marek <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3569a89441fcSJonathan Marek <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3570a89441fcSJonathan Marek <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3571a89441fcSJonathan Marek }; 3572a89441fcSJonathan Marek 357323a89037SBjorn Andersson adsp: remoteproc@17300000 { 357423a89037SBjorn Andersson compatible = "qcom,sm8250-adsp-pas"; 357523a89037SBjorn Andersson reg = <0 0x17300000 0 0x100>; 357623a89037SBjorn Andersson 357723a89037SBjorn Andersson interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 357823a89037SBjorn Andersson <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 357923a89037SBjorn Andersson <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 358023a89037SBjorn Andersson <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 358123a89037SBjorn Andersson <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 358223a89037SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 358323a89037SBjorn Andersson "handover", "stop-ack"; 358423a89037SBjorn Andersson 358523a89037SBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>; 358623a89037SBjorn Andersson clock-names = "xo"; 358723a89037SBjorn Andersson 358823a89037SBjorn Andersson power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, 358923a89037SBjorn Andersson <&rpmhpd SM8250_LCX>, 359023a89037SBjorn Andersson <&rpmhpd SM8250_LMX>; 359123a89037SBjorn Andersson power-domain-names = "load_state", "lcx", "lmx"; 359223a89037SBjorn Andersson 359323a89037SBjorn Andersson memory-region = <&adsp_mem>; 359423a89037SBjorn Andersson 359523a89037SBjorn Andersson qcom,smem-states = <&smp2p_adsp_out 0>; 359623a89037SBjorn Andersson qcom,smem-state-names = "stop"; 359723a89037SBjorn Andersson 359823a89037SBjorn Andersson status = "disabled"; 359923a89037SBjorn Andersson 360023a89037SBjorn Andersson glink-edge { 360123a89037SBjorn Andersson interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 360223a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP 360323a89037SBjorn Andersson IRQ_TYPE_EDGE_RISING>; 360423a89037SBjorn Andersson mboxes = <&ipcc IPCC_CLIENT_LPASS 360523a89037SBjorn Andersson IPCC_MPROC_SIGNAL_GLINK_QMP>; 360623a89037SBjorn Andersson 360723a89037SBjorn Andersson label = "lpass"; 360823a89037SBjorn Andersson qcom,remote-pid = <2>; 360925695808SJonathan Marek 361063e10791SSrinivas Kandagatla apr { 361163e10791SSrinivas Kandagatla compatible = "qcom,apr-v2"; 361263e10791SSrinivas Kandagatla qcom,glink-channels = "apr_audio_svc"; 361363e10791SSrinivas Kandagatla qcom,apr-domain = <APR_DOMAIN_ADSP>; 361463e10791SSrinivas Kandagatla #address-cells = <1>; 361563e10791SSrinivas Kandagatla #size-cells = <0>; 361663e10791SSrinivas Kandagatla 361763e10791SSrinivas Kandagatla apr-service@3 { 361863e10791SSrinivas Kandagatla reg = <APR_SVC_ADSP_CORE>; 361963e10791SSrinivas Kandagatla compatible = "qcom,q6core"; 362063e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 362163e10791SSrinivas Kandagatla }; 362263e10791SSrinivas Kandagatla 362363e10791SSrinivas Kandagatla q6afe: apr-service@4 { 362463e10791SSrinivas Kandagatla compatible = "qcom,q6afe"; 362563e10791SSrinivas Kandagatla reg = <APR_SVC_AFE>; 362663e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 362763e10791SSrinivas Kandagatla q6afedai: dais { 362863e10791SSrinivas Kandagatla compatible = "qcom,q6afe-dais"; 362963e10791SSrinivas Kandagatla #address-cells = <1>; 363063e10791SSrinivas Kandagatla #size-cells = <0>; 363163e10791SSrinivas Kandagatla #sound-dai-cells = <1>; 363263e10791SSrinivas Kandagatla }; 363363e10791SSrinivas Kandagatla 363463e10791SSrinivas Kandagatla q6afecc: cc { 363563e10791SSrinivas Kandagatla compatible = "qcom,q6afe-clocks"; 363663e10791SSrinivas Kandagatla #clock-cells = <2>; 363763e10791SSrinivas Kandagatla }; 363863e10791SSrinivas Kandagatla }; 363963e10791SSrinivas Kandagatla 364063e10791SSrinivas Kandagatla q6asm: apr-service@7 { 364163e10791SSrinivas Kandagatla compatible = "qcom,q6asm"; 364263e10791SSrinivas Kandagatla reg = <APR_SVC_ASM>; 364363e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 364463e10791SSrinivas Kandagatla q6asmdai: dais { 364563e10791SSrinivas Kandagatla compatible = "qcom,q6asm-dais"; 364663e10791SSrinivas Kandagatla #address-cells = <1>; 364763e10791SSrinivas Kandagatla #size-cells = <0>; 364863e10791SSrinivas Kandagatla #sound-dai-cells = <1>; 364963e10791SSrinivas Kandagatla iommus = <&apps_smmu 0x1801 0x0>; 365063e10791SSrinivas Kandagatla }; 365163e10791SSrinivas Kandagatla }; 365263e10791SSrinivas Kandagatla 365363e10791SSrinivas Kandagatla q6adm: apr-service@8 { 365463e10791SSrinivas Kandagatla compatible = "qcom,q6adm"; 365563e10791SSrinivas Kandagatla reg = <APR_SVC_ADM>; 365663e10791SSrinivas Kandagatla qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 365763e10791SSrinivas Kandagatla q6routing: routing { 365863e10791SSrinivas Kandagatla compatible = "qcom,q6adm-routing"; 365963e10791SSrinivas Kandagatla #sound-dai-cells = <0>; 366063e10791SSrinivas Kandagatla }; 366163e10791SSrinivas Kandagatla }; 366263e10791SSrinivas Kandagatla }; 366363e10791SSrinivas Kandagatla 366425695808SJonathan Marek fastrpc { 366525695808SJonathan Marek compatible = "qcom,fastrpc"; 366625695808SJonathan Marek qcom,glink-channels = "fastrpcglink-apps-dsp"; 366725695808SJonathan Marek label = "adsp"; 366825695808SJonathan Marek #address-cells = <1>; 366925695808SJonathan Marek #size-cells = <0>; 367025695808SJonathan Marek 367125695808SJonathan Marek compute-cb@3 { 367225695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 367325695808SJonathan Marek reg = <3>; 367425695808SJonathan Marek iommus = <&apps_smmu 0x1803 0x0>; 367525695808SJonathan Marek }; 367625695808SJonathan Marek 367725695808SJonathan Marek compute-cb@4 { 367825695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 367925695808SJonathan Marek reg = <4>; 368025695808SJonathan Marek iommus = <&apps_smmu 0x1804 0x0>; 368125695808SJonathan Marek }; 368225695808SJonathan Marek 368325695808SJonathan Marek compute-cb@5 { 368425695808SJonathan Marek compatible = "qcom,fastrpc-compute-cb"; 368525695808SJonathan Marek reg = <5>; 368625695808SJonathan Marek iommus = <&apps_smmu 0x1805 0x0>; 368725695808SJonathan Marek }; 368825695808SJonathan Marek }; 368923a89037SBjorn Andersson }; 369023a89037SBjorn Andersson }; 369123a89037SBjorn Andersson 3692b9ec8cbcSJonathan Marek intc: interrupt-controller@17a00000 { 3693b9ec8cbcSJonathan Marek compatible = "arm,gic-v3"; 3694b9ec8cbcSJonathan Marek #interrupt-cells = <3>; 3695b9ec8cbcSJonathan Marek interrupt-controller; 3696b9ec8cbcSJonathan Marek reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3697b9ec8cbcSJonathan Marek <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3698b9ec8cbcSJonathan Marek interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3699b9ec8cbcSJonathan Marek }; 3700b9ec8cbcSJonathan Marek 3701e0d9acceSDmitry Baryshkov watchdog@17c10000 { 3702e0d9acceSDmitry Baryshkov compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 3703e0d9acceSDmitry Baryshkov reg = <0 0x17c10000 0 0x1000>; 3704e0d9acceSDmitry Baryshkov clocks = <&sleep_clk>; 370546a4359fSSai Prakash Ranjan interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3706e0d9acceSDmitry Baryshkov }; 3707e0d9acceSDmitry Baryshkov 3708b9ec8cbcSJonathan Marek timer@17c20000 { 3709b9ec8cbcSJonathan Marek #address-cells = <2>; 3710b9ec8cbcSJonathan Marek #size-cells = <2>; 3711b9ec8cbcSJonathan Marek ranges; 3712b9ec8cbcSJonathan Marek compatible = "arm,armv7-timer-mem"; 3713b9ec8cbcSJonathan Marek reg = <0x0 0x17c20000 0x0 0x1000>; 3714b9ec8cbcSJonathan Marek clock-frequency = <19200000>; 3715b9ec8cbcSJonathan Marek 3716b9ec8cbcSJonathan Marek frame@17c21000 { 3717b9ec8cbcSJonathan Marek frame-number = <0>; 3718b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3719b9ec8cbcSJonathan Marek <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3720b9ec8cbcSJonathan Marek reg = <0x0 0x17c21000 0x0 0x1000>, 3721b9ec8cbcSJonathan Marek <0x0 0x17c22000 0x0 0x1000>; 3722b9ec8cbcSJonathan Marek }; 3723b9ec8cbcSJonathan Marek 3724b9ec8cbcSJonathan Marek frame@17c23000 { 3725b9ec8cbcSJonathan Marek frame-number = <1>; 3726b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3727b9ec8cbcSJonathan Marek reg = <0x0 0x17c23000 0x0 0x1000>; 3728b9ec8cbcSJonathan Marek status = "disabled"; 3729b9ec8cbcSJonathan Marek }; 3730b9ec8cbcSJonathan Marek 3731b9ec8cbcSJonathan Marek frame@17c25000 { 3732b9ec8cbcSJonathan Marek frame-number = <2>; 3733b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3734b9ec8cbcSJonathan Marek reg = <0x0 0x17c25000 0x0 0x1000>; 3735b9ec8cbcSJonathan Marek status = "disabled"; 3736b9ec8cbcSJonathan Marek }; 3737b9ec8cbcSJonathan Marek 3738b9ec8cbcSJonathan Marek frame@17c27000 { 3739b9ec8cbcSJonathan Marek frame-number = <3>; 3740b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3741b9ec8cbcSJonathan Marek reg = <0x0 0x17c27000 0x0 0x1000>; 3742b9ec8cbcSJonathan Marek status = "disabled"; 3743b9ec8cbcSJonathan Marek }; 3744b9ec8cbcSJonathan Marek 3745b9ec8cbcSJonathan Marek frame@17c29000 { 3746b9ec8cbcSJonathan Marek frame-number = <4>; 3747b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3748b9ec8cbcSJonathan Marek reg = <0x0 0x17c29000 0x0 0x1000>; 3749b9ec8cbcSJonathan Marek status = "disabled"; 3750b9ec8cbcSJonathan Marek }; 3751b9ec8cbcSJonathan Marek 3752b9ec8cbcSJonathan Marek frame@17c2b000 { 3753b9ec8cbcSJonathan Marek frame-number = <5>; 3754b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3755b9ec8cbcSJonathan Marek reg = <0x0 0x17c2b000 0x0 0x1000>; 3756b9ec8cbcSJonathan Marek status = "disabled"; 3757b9ec8cbcSJonathan Marek }; 3758b9ec8cbcSJonathan Marek 3759b9ec8cbcSJonathan Marek frame@17c2d000 { 3760b9ec8cbcSJonathan Marek frame-number = <6>; 3761b9ec8cbcSJonathan Marek interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3762b9ec8cbcSJonathan Marek reg = <0x0 0x17c2d000 0x0 0x1000>; 3763b9ec8cbcSJonathan Marek status = "disabled"; 3764b9ec8cbcSJonathan Marek }; 3765b9ec8cbcSJonathan Marek }; 3766b9ec8cbcSJonathan Marek 376760378f1aSVenkata Narendra Kumar Gutta apps_rsc: rsc@18200000 { 376860378f1aSVenkata Narendra Kumar Gutta label = "apps_rsc"; 376960378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,rpmh-rsc"; 377060378f1aSVenkata Narendra Kumar Gutta reg = <0x0 0x18200000 0x0 0x10000>, 377160378f1aSVenkata Narendra Kumar Gutta <0x0 0x18210000 0x0 0x10000>, 377260378f1aSVenkata Narendra Kumar Gutta <0x0 0x18220000 0x0 0x10000>; 377360378f1aSVenkata Narendra Kumar Gutta reg-names = "drv-0", "drv-1", "drv-2"; 377460378f1aSVenkata Narendra Kumar Gutta interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 377560378f1aSVenkata Narendra Kumar Gutta <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 377660378f1aSVenkata Narendra Kumar Gutta <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 377760378f1aSVenkata Narendra Kumar Gutta qcom,tcs-offset = <0xd00>; 377860378f1aSVenkata Narendra Kumar Gutta qcom,drv-id = <2>; 377960378f1aSVenkata Narendra Kumar Gutta qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 378060378f1aSVenkata Narendra Kumar Gutta <WAKE_TCS 3>, <CONTROL_TCS 1>; 378160378f1aSVenkata Narendra Kumar Gutta 378260378f1aSVenkata Narendra Kumar Gutta rpmhcc: clock-controller { 378360378f1aSVenkata Narendra Kumar Gutta compatible = "qcom,sm8250-rpmh-clk"; 378460378f1aSVenkata Narendra Kumar Gutta #clock-cells = <1>; 378560378f1aSVenkata Narendra Kumar Gutta clock-names = "xo"; 378660378f1aSVenkata Narendra Kumar Gutta clocks = <&xo_board>; 378760378f1aSVenkata Narendra Kumar Gutta }; 3788b6f78e27SBjorn Andersson 3789b6f78e27SBjorn Andersson rpmhpd: power-controller { 3790b6f78e27SBjorn Andersson compatible = "qcom,sm8250-rpmhpd"; 3791b6f78e27SBjorn Andersson #power-domain-cells = <1>; 3792b6f78e27SBjorn Andersson operating-points-v2 = <&rpmhpd_opp_table>; 3793b6f78e27SBjorn Andersson 3794b6f78e27SBjorn Andersson rpmhpd_opp_table: opp-table { 3795b6f78e27SBjorn Andersson compatible = "operating-points-v2"; 3796b6f78e27SBjorn Andersson 3797b6f78e27SBjorn Andersson rpmhpd_opp_ret: opp1 { 3798b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3799b6f78e27SBjorn Andersson }; 3800b6f78e27SBjorn Andersson 3801b6f78e27SBjorn Andersson rpmhpd_opp_min_svs: opp2 { 3802b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3803b6f78e27SBjorn Andersson }; 3804b6f78e27SBjorn Andersson 3805b6f78e27SBjorn Andersson rpmhpd_opp_low_svs: opp3 { 3806b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3807b6f78e27SBjorn Andersson }; 3808b6f78e27SBjorn Andersson 3809b6f78e27SBjorn Andersson rpmhpd_opp_svs: opp4 { 3810b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3811b6f78e27SBjorn Andersson }; 3812b6f78e27SBjorn Andersson 3813b6f78e27SBjorn Andersson rpmhpd_opp_svs_l1: opp5 { 3814b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3815b6f78e27SBjorn Andersson }; 3816b6f78e27SBjorn Andersson 3817b6f78e27SBjorn Andersson rpmhpd_opp_nom: opp6 { 3818b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3819b6f78e27SBjorn Andersson }; 3820b6f78e27SBjorn Andersson 3821b6f78e27SBjorn Andersson rpmhpd_opp_nom_l1: opp7 { 3822b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3823b6f78e27SBjorn Andersson }; 3824b6f78e27SBjorn Andersson 3825b6f78e27SBjorn Andersson rpmhpd_opp_nom_l2: opp8 { 3826b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3827b6f78e27SBjorn Andersson }; 3828b6f78e27SBjorn Andersson 3829b6f78e27SBjorn Andersson rpmhpd_opp_turbo: opp9 { 3830b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3831b6f78e27SBjorn Andersson }; 3832b6f78e27SBjorn Andersson 3833b6f78e27SBjorn Andersson rpmhpd_opp_turbo_l1: opp10 { 3834b6f78e27SBjorn Andersson opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3835b6f78e27SBjorn Andersson }; 3836b6f78e27SBjorn Andersson }; 3837b6f78e27SBjorn Andersson }; 3838e7e41a20SJonathan Marek 3839e7e41a20SJonathan Marek apps_bcm_voter: bcm_voter { 3840e7e41a20SJonathan Marek compatible = "qcom,bcm-voter"; 3841e7e41a20SJonathan Marek }; 384260378f1aSVenkata Narendra Kumar Gutta }; 384379a595bbSSibi Sankar 384479a595bbSSibi Sankar epss_l3: interconnect@18591000 { 384579a595bbSSibi Sankar compatible = "qcom,sm8250-epss-l3"; 384679a595bbSSibi Sankar reg = <0 0x18590000 0 0x1000>; 384779a595bbSSibi Sankar 384879a595bbSSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 384979a595bbSSibi Sankar clock-names = "xo", "alternate"; 385079a595bbSSibi Sankar 385179a595bbSSibi Sankar #interconnect-cells = <1>; 385279a595bbSSibi Sankar }; 385302ae4a0eSBjorn Andersson 385402ae4a0eSBjorn Andersson cpufreq_hw: cpufreq@18591000 { 385502ae4a0eSBjorn Andersson compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 385602ae4a0eSBjorn Andersson reg = <0 0x18591000 0 0x1000>, 385702ae4a0eSBjorn Andersson <0 0x18592000 0 0x1000>, 385802ae4a0eSBjorn Andersson <0 0x18593000 0 0x1000>; 385902ae4a0eSBjorn Andersson reg-names = "freq-domain0", "freq-domain1", 386002ae4a0eSBjorn Andersson "freq-domain2"; 386102ae4a0eSBjorn Andersson 386202ae4a0eSBjorn Andersson clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 386302ae4a0eSBjorn Andersson clock-names = "xo", "alternate"; 386402ae4a0eSBjorn Andersson 386502ae4a0eSBjorn Andersson #freq-domain-cells = <1>; 386602ae4a0eSBjorn Andersson }; 386760378f1aSVenkata Narendra Kumar Gutta }; 386860378f1aSVenkata Narendra Kumar Gutta 386960378f1aSVenkata Narendra Kumar Gutta timer { 387060378f1aSVenkata Narendra Kumar Gutta compatible = "arm,armv8-timer"; 387160378f1aSVenkata Narendra Kumar Gutta interrupts = <GIC_PPI 13 387260378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 387360378f1aSVenkata Narendra Kumar Gutta <GIC_PPI 14 387460378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 387560378f1aSVenkata Narendra Kumar Gutta <GIC_PPI 11 387660378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 387729a33495SSai Prakash Ranjan <GIC_PPI 10 387860378f1aSVenkata Narendra Kumar Gutta (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 387960378f1aSVenkata Narendra Kumar Gutta }; 3880bac12f25SAmit Kucheria 3881bac12f25SAmit Kucheria thermal-zones { 3882bac12f25SAmit Kucheria cpu0-thermal { 3883bac12f25SAmit Kucheria polling-delay-passive = <250>; 3884bac12f25SAmit Kucheria polling-delay = <1000>; 3885bac12f25SAmit Kucheria 3886bac12f25SAmit Kucheria thermal-sensors = <&tsens0 1>; 3887bac12f25SAmit Kucheria 3888bac12f25SAmit Kucheria trips { 3889bac12f25SAmit Kucheria cpu0_alert0: trip-point0 { 3890bac12f25SAmit Kucheria temperature = <90000>; 3891bac12f25SAmit Kucheria hysteresis = <2000>; 3892bac12f25SAmit Kucheria type = "passive"; 3893bac12f25SAmit Kucheria }; 3894bac12f25SAmit Kucheria 3895bac12f25SAmit Kucheria cpu0_alert1: trip-point1 { 3896bac12f25SAmit Kucheria temperature = <95000>; 3897bac12f25SAmit Kucheria hysteresis = <2000>; 3898bac12f25SAmit Kucheria type = "passive"; 3899bac12f25SAmit Kucheria }; 3900bac12f25SAmit Kucheria 3901bac12f25SAmit Kucheria cpu0_crit: cpu_crit { 3902bac12f25SAmit Kucheria temperature = <110000>; 3903bac12f25SAmit Kucheria hysteresis = <1000>; 3904bac12f25SAmit Kucheria type = "critical"; 3905bac12f25SAmit Kucheria }; 3906bac12f25SAmit Kucheria }; 3907bac12f25SAmit Kucheria 3908bac12f25SAmit Kucheria cooling-maps { 3909bac12f25SAmit Kucheria map0 { 3910bac12f25SAmit Kucheria trip = <&cpu0_alert0>; 3911bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3912bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3913bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3914bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3915bac12f25SAmit Kucheria }; 3916bac12f25SAmit Kucheria map1 { 3917bac12f25SAmit Kucheria trip = <&cpu0_alert1>; 3918bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3919bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3920bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3921bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3922bac12f25SAmit Kucheria }; 3923bac12f25SAmit Kucheria }; 3924bac12f25SAmit Kucheria }; 3925bac12f25SAmit Kucheria 3926bac12f25SAmit Kucheria cpu1-thermal { 3927bac12f25SAmit Kucheria polling-delay-passive = <250>; 3928bac12f25SAmit Kucheria polling-delay = <1000>; 3929bac12f25SAmit Kucheria 3930bac12f25SAmit Kucheria thermal-sensors = <&tsens0 2>; 3931bac12f25SAmit Kucheria 3932bac12f25SAmit Kucheria trips { 3933bac12f25SAmit Kucheria cpu1_alert0: trip-point0 { 3934bac12f25SAmit Kucheria temperature = <90000>; 3935bac12f25SAmit Kucheria hysteresis = <2000>; 3936bac12f25SAmit Kucheria type = "passive"; 3937bac12f25SAmit Kucheria }; 3938bac12f25SAmit Kucheria 3939bac12f25SAmit Kucheria cpu1_alert1: trip-point1 { 3940bac12f25SAmit Kucheria temperature = <95000>; 3941bac12f25SAmit Kucheria hysteresis = <2000>; 3942bac12f25SAmit Kucheria type = "passive"; 3943bac12f25SAmit Kucheria }; 3944bac12f25SAmit Kucheria 3945bac12f25SAmit Kucheria cpu1_crit: cpu_crit { 3946bac12f25SAmit Kucheria temperature = <110000>; 3947bac12f25SAmit Kucheria hysteresis = <1000>; 3948bac12f25SAmit Kucheria type = "critical"; 3949bac12f25SAmit Kucheria }; 3950bac12f25SAmit Kucheria }; 3951bac12f25SAmit Kucheria 3952bac12f25SAmit Kucheria cooling-maps { 3953bac12f25SAmit Kucheria map0 { 3954bac12f25SAmit Kucheria trip = <&cpu1_alert0>; 3955bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3956bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3957bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3958bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3959bac12f25SAmit Kucheria }; 3960bac12f25SAmit Kucheria map1 { 3961bac12f25SAmit Kucheria trip = <&cpu1_alert1>; 3962bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3963bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3964bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3965bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3966bac12f25SAmit Kucheria }; 3967bac12f25SAmit Kucheria }; 3968bac12f25SAmit Kucheria }; 3969bac12f25SAmit Kucheria 3970bac12f25SAmit Kucheria cpu2-thermal { 3971bac12f25SAmit Kucheria polling-delay-passive = <250>; 3972bac12f25SAmit Kucheria polling-delay = <1000>; 3973bac12f25SAmit Kucheria 3974bac12f25SAmit Kucheria thermal-sensors = <&tsens0 3>; 3975bac12f25SAmit Kucheria 3976bac12f25SAmit Kucheria trips { 3977bac12f25SAmit Kucheria cpu2_alert0: trip-point0 { 3978bac12f25SAmit Kucheria temperature = <90000>; 3979bac12f25SAmit Kucheria hysteresis = <2000>; 3980bac12f25SAmit Kucheria type = "passive"; 3981bac12f25SAmit Kucheria }; 3982bac12f25SAmit Kucheria 3983bac12f25SAmit Kucheria cpu2_alert1: trip-point1 { 3984bac12f25SAmit Kucheria temperature = <95000>; 3985bac12f25SAmit Kucheria hysteresis = <2000>; 3986bac12f25SAmit Kucheria type = "passive"; 3987bac12f25SAmit Kucheria }; 3988bac12f25SAmit Kucheria 3989bac12f25SAmit Kucheria cpu2_crit: cpu_crit { 3990bac12f25SAmit Kucheria temperature = <110000>; 3991bac12f25SAmit Kucheria hysteresis = <1000>; 3992bac12f25SAmit Kucheria type = "critical"; 3993bac12f25SAmit Kucheria }; 3994bac12f25SAmit Kucheria }; 3995bac12f25SAmit Kucheria 3996bac12f25SAmit Kucheria cooling-maps { 3997bac12f25SAmit Kucheria map0 { 3998bac12f25SAmit Kucheria trip = <&cpu2_alert0>; 3999bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4000bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4001bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4002bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4003bac12f25SAmit Kucheria }; 4004bac12f25SAmit Kucheria map1 { 4005bac12f25SAmit Kucheria trip = <&cpu2_alert1>; 4006bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4007bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4008bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4009bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4010bac12f25SAmit Kucheria }; 4011bac12f25SAmit Kucheria }; 4012bac12f25SAmit Kucheria }; 4013bac12f25SAmit Kucheria 4014bac12f25SAmit Kucheria cpu3-thermal { 4015bac12f25SAmit Kucheria polling-delay-passive = <250>; 4016bac12f25SAmit Kucheria polling-delay = <1000>; 4017bac12f25SAmit Kucheria 4018bac12f25SAmit Kucheria thermal-sensors = <&tsens0 4>; 4019bac12f25SAmit Kucheria 4020bac12f25SAmit Kucheria trips { 4021bac12f25SAmit Kucheria cpu3_alert0: trip-point0 { 4022bac12f25SAmit Kucheria temperature = <90000>; 4023bac12f25SAmit Kucheria hysteresis = <2000>; 4024bac12f25SAmit Kucheria type = "passive"; 4025bac12f25SAmit Kucheria }; 4026bac12f25SAmit Kucheria 4027bac12f25SAmit Kucheria cpu3_alert1: trip-point1 { 4028bac12f25SAmit Kucheria temperature = <95000>; 4029bac12f25SAmit Kucheria hysteresis = <2000>; 4030bac12f25SAmit Kucheria type = "passive"; 4031bac12f25SAmit Kucheria }; 4032bac12f25SAmit Kucheria 4033bac12f25SAmit Kucheria cpu3_crit: cpu_crit { 4034bac12f25SAmit Kucheria temperature = <110000>; 4035bac12f25SAmit Kucheria hysteresis = <1000>; 4036bac12f25SAmit Kucheria type = "critical"; 4037bac12f25SAmit Kucheria }; 4038bac12f25SAmit Kucheria }; 4039bac12f25SAmit Kucheria 4040bac12f25SAmit Kucheria cooling-maps { 4041bac12f25SAmit Kucheria map0 { 4042bac12f25SAmit Kucheria trip = <&cpu3_alert0>; 4043bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4044bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4045bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4046bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4047bac12f25SAmit Kucheria }; 4048bac12f25SAmit Kucheria map1 { 4049bac12f25SAmit Kucheria trip = <&cpu3_alert1>; 4050bac12f25SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4051bac12f25SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4052bac12f25SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4053bac12f25SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4054bac12f25SAmit Kucheria }; 4055bac12f25SAmit Kucheria }; 4056bac12f25SAmit Kucheria }; 4057bac12f25SAmit Kucheria 4058bac12f25SAmit Kucheria cpu4-top-thermal { 4059bac12f25SAmit Kucheria polling-delay-passive = <250>; 4060bac12f25SAmit Kucheria polling-delay = <1000>; 4061bac12f25SAmit Kucheria 4062bac12f25SAmit Kucheria thermal-sensors = <&tsens0 7>; 4063bac12f25SAmit Kucheria 4064bac12f25SAmit Kucheria trips { 4065bac12f25SAmit Kucheria cpu4_top_alert0: trip-point0 { 4066bac12f25SAmit Kucheria temperature = <90000>; 4067bac12f25SAmit Kucheria hysteresis = <2000>; 4068bac12f25SAmit Kucheria type = "passive"; 4069bac12f25SAmit Kucheria }; 4070bac12f25SAmit Kucheria 4071bac12f25SAmit Kucheria cpu4_top_alert1: trip-point1 { 4072bac12f25SAmit Kucheria temperature = <95000>; 4073bac12f25SAmit Kucheria hysteresis = <2000>; 4074bac12f25SAmit Kucheria type = "passive"; 4075bac12f25SAmit Kucheria }; 4076bac12f25SAmit Kucheria 4077bac12f25SAmit Kucheria cpu4_top_crit: cpu_crit { 4078bac12f25SAmit Kucheria temperature = <110000>; 4079bac12f25SAmit Kucheria hysteresis = <1000>; 4080bac12f25SAmit Kucheria type = "critical"; 4081bac12f25SAmit Kucheria }; 4082bac12f25SAmit Kucheria }; 4083bac12f25SAmit Kucheria 4084bac12f25SAmit Kucheria cooling-maps { 4085bac12f25SAmit Kucheria map0 { 4086bac12f25SAmit Kucheria trip = <&cpu4_top_alert0>; 4087bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4088bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4089bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4090bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4091bac12f25SAmit Kucheria }; 4092bac12f25SAmit Kucheria map1 { 4093bac12f25SAmit Kucheria trip = <&cpu4_top_alert1>; 4094bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4095bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4096bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4097bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4098bac12f25SAmit Kucheria }; 4099bac12f25SAmit Kucheria }; 4100bac12f25SAmit Kucheria }; 4101bac12f25SAmit Kucheria 4102bac12f25SAmit Kucheria cpu5-top-thermal { 4103bac12f25SAmit Kucheria polling-delay-passive = <250>; 4104bac12f25SAmit Kucheria polling-delay = <1000>; 4105bac12f25SAmit Kucheria 4106bac12f25SAmit Kucheria thermal-sensors = <&tsens0 8>; 4107bac12f25SAmit Kucheria 4108bac12f25SAmit Kucheria trips { 4109bac12f25SAmit Kucheria cpu5_top_alert0: trip-point0 { 4110bac12f25SAmit Kucheria temperature = <90000>; 4111bac12f25SAmit Kucheria hysteresis = <2000>; 4112bac12f25SAmit Kucheria type = "passive"; 4113bac12f25SAmit Kucheria }; 4114bac12f25SAmit Kucheria 4115bac12f25SAmit Kucheria cpu5_top_alert1: trip-point1 { 4116bac12f25SAmit Kucheria temperature = <95000>; 4117bac12f25SAmit Kucheria hysteresis = <2000>; 4118bac12f25SAmit Kucheria type = "passive"; 4119bac12f25SAmit Kucheria }; 4120bac12f25SAmit Kucheria 4121bac12f25SAmit Kucheria cpu5_top_crit: cpu_crit { 4122bac12f25SAmit Kucheria temperature = <110000>; 4123bac12f25SAmit Kucheria hysteresis = <1000>; 4124bac12f25SAmit Kucheria type = "critical"; 4125bac12f25SAmit Kucheria }; 4126bac12f25SAmit Kucheria }; 4127bac12f25SAmit Kucheria 4128bac12f25SAmit Kucheria cooling-maps { 4129bac12f25SAmit Kucheria map0 { 4130bac12f25SAmit Kucheria trip = <&cpu5_top_alert0>; 4131bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4132bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4133bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4134bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4135bac12f25SAmit Kucheria }; 4136bac12f25SAmit Kucheria map1 { 4137bac12f25SAmit Kucheria trip = <&cpu5_top_alert1>; 4138bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4139bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4140bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4141bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4142bac12f25SAmit Kucheria }; 4143bac12f25SAmit Kucheria }; 4144bac12f25SAmit Kucheria }; 4145bac12f25SAmit Kucheria 4146bac12f25SAmit Kucheria cpu6-top-thermal { 4147bac12f25SAmit Kucheria polling-delay-passive = <250>; 4148bac12f25SAmit Kucheria polling-delay = <1000>; 4149bac12f25SAmit Kucheria 4150bac12f25SAmit Kucheria thermal-sensors = <&tsens0 9>; 4151bac12f25SAmit Kucheria 4152bac12f25SAmit Kucheria trips { 4153bac12f25SAmit Kucheria cpu6_top_alert0: trip-point0 { 4154bac12f25SAmit Kucheria temperature = <90000>; 4155bac12f25SAmit Kucheria hysteresis = <2000>; 4156bac12f25SAmit Kucheria type = "passive"; 4157bac12f25SAmit Kucheria }; 4158bac12f25SAmit Kucheria 4159bac12f25SAmit Kucheria cpu6_top_alert1: trip-point1 { 4160bac12f25SAmit Kucheria temperature = <95000>; 4161bac12f25SAmit Kucheria hysteresis = <2000>; 4162bac12f25SAmit Kucheria type = "passive"; 4163bac12f25SAmit Kucheria }; 4164bac12f25SAmit Kucheria 4165bac12f25SAmit Kucheria cpu6_top_crit: cpu_crit { 4166bac12f25SAmit Kucheria temperature = <110000>; 4167bac12f25SAmit Kucheria hysteresis = <1000>; 4168bac12f25SAmit Kucheria type = "critical"; 4169bac12f25SAmit Kucheria }; 4170bac12f25SAmit Kucheria }; 4171bac12f25SAmit Kucheria 4172bac12f25SAmit Kucheria cooling-maps { 4173bac12f25SAmit Kucheria map0 { 4174bac12f25SAmit Kucheria trip = <&cpu6_top_alert0>; 4175bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4176bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4177bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4178bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4179bac12f25SAmit Kucheria }; 4180bac12f25SAmit Kucheria map1 { 4181bac12f25SAmit Kucheria trip = <&cpu6_top_alert1>; 4182bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4183bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4184bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4185bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4186bac12f25SAmit Kucheria }; 4187bac12f25SAmit Kucheria }; 4188bac12f25SAmit Kucheria }; 4189bac12f25SAmit Kucheria 4190bac12f25SAmit Kucheria cpu7-top-thermal { 4191bac12f25SAmit Kucheria polling-delay-passive = <250>; 4192bac12f25SAmit Kucheria polling-delay = <1000>; 4193bac12f25SAmit Kucheria 4194bac12f25SAmit Kucheria thermal-sensors = <&tsens0 10>; 4195bac12f25SAmit Kucheria 4196bac12f25SAmit Kucheria trips { 4197bac12f25SAmit Kucheria cpu7_top_alert0: trip-point0 { 4198bac12f25SAmit Kucheria temperature = <90000>; 4199bac12f25SAmit Kucheria hysteresis = <2000>; 4200bac12f25SAmit Kucheria type = "passive"; 4201bac12f25SAmit Kucheria }; 4202bac12f25SAmit Kucheria 4203bac12f25SAmit Kucheria cpu7_top_alert1: trip-point1 { 4204bac12f25SAmit Kucheria temperature = <95000>; 4205bac12f25SAmit Kucheria hysteresis = <2000>; 4206bac12f25SAmit Kucheria type = "passive"; 4207bac12f25SAmit Kucheria }; 4208bac12f25SAmit Kucheria 4209bac12f25SAmit Kucheria cpu7_top_crit: cpu_crit { 4210bac12f25SAmit Kucheria temperature = <110000>; 4211bac12f25SAmit Kucheria hysteresis = <1000>; 4212bac12f25SAmit Kucheria type = "critical"; 4213bac12f25SAmit Kucheria }; 4214bac12f25SAmit Kucheria }; 4215bac12f25SAmit Kucheria 4216bac12f25SAmit Kucheria cooling-maps { 4217bac12f25SAmit Kucheria map0 { 4218bac12f25SAmit Kucheria trip = <&cpu7_top_alert0>; 4219bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4220bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4221bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4222bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4223bac12f25SAmit Kucheria }; 4224bac12f25SAmit Kucheria map1 { 4225bac12f25SAmit Kucheria trip = <&cpu7_top_alert1>; 4226bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4227bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4228bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4229bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4230bac12f25SAmit Kucheria }; 4231bac12f25SAmit Kucheria }; 4232bac12f25SAmit Kucheria }; 4233bac12f25SAmit Kucheria 4234bac12f25SAmit Kucheria cpu4-bottom-thermal { 4235bac12f25SAmit Kucheria polling-delay-passive = <250>; 4236bac12f25SAmit Kucheria polling-delay = <1000>; 4237bac12f25SAmit Kucheria 4238bac12f25SAmit Kucheria thermal-sensors = <&tsens0 11>; 4239bac12f25SAmit Kucheria 4240bac12f25SAmit Kucheria trips { 4241bac12f25SAmit Kucheria cpu4_bottom_alert0: trip-point0 { 4242bac12f25SAmit Kucheria temperature = <90000>; 4243bac12f25SAmit Kucheria hysteresis = <2000>; 4244bac12f25SAmit Kucheria type = "passive"; 4245bac12f25SAmit Kucheria }; 4246bac12f25SAmit Kucheria 4247bac12f25SAmit Kucheria cpu4_bottom_alert1: trip-point1 { 4248bac12f25SAmit Kucheria temperature = <95000>; 4249bac12f25SAmit Kucheria hysteresis = <2000>; 4250bac12f25SAmit Kucheria type = "passive"; 4251bac12f25SAmit Kucheria }; 4252bac12f25SAmit Kucheria 4253bac12f25SAmit Kucheria cpu4_bottom_crit: cpu_crit { 4254bac12f25SAmit Kucheria temperature = <110000>; 4255bac12f25SAmit Kucheria hysteresis = <1000>; 4256bac12f25SAmit Kucheria type = "critical"; 4257bac12f25SAmit Kucheria }; 4258bac12f25SAmit Kucheria }; 4259bac12f25SAmit Kucheria 4260bac12f25SAmit Kucheria cooling-maps { 4261bac12f25SAmit Kucheria map0 { 4262bac12f25SAmit Kucheria trip = <&cpu4_bottom_alert0>; 4263bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4264bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4265bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4266bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4267bac12f25SAmit Kucheria }; 4268bac12f25SAmit Kucheria map1 { 4269bac12f25SAmit Kucheria trip = <&cpu4_bottom_alert1>; 4270bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4271bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4272bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4273bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4274bac12f25SAmit Kucheria }; 4275bac12f25SAmit Kucheria }; 4276bac12f25SAmit Kucheria }; 4277bac12f25SAmit Kucheria 4278bac12f25SAmit Kucheria cpu5-bottom-thermal { 4279bac12f25SAmit Kucheria polling-delay-passive = <250>; 4280bac12f25SAmit Kucheria polling-delay = <1000>; 4281bac12f25SAmit Kucheria 4282bac12f25SAmit Kucheria thermal-sensors = <&tsens0 12>; 4283bac12f25SAmit Kucheria 4284bac12f25SAmit Kucheria trips { 4285bac12f25SAmit Kucheria cpu5_bottom_alert0: trip-point0 { 4286bac12f25SAmit Kucheria temperature = <90000>; 4287bac12f25SAmit Kucheria hysteresis = <2000>; 4288bac12f25SAmit Kucheria type = "passive"; 4289bac12f25SAmit Kucheria }; 4290bac12f25SAmit Kucheria 4291bac12f25SAmit Kucheria cpu5_bottom_alert1: trip-point1 { 4292bac12f25SAmit Kucheria temperature = <95000>; 4293bac12f25SAmit Kucheria hysteresis = <2000>; 4294bac12f25SAmit Kucheria type = "passive"; 4295bac12f25SAmit Kucheria }; 4296bac12f25SAmit Kucheria 4297bac12f25SAmit Kucheria cpu5_bottom_crit: cpu_crit { 4298bac12f25SAmit Kucheria temperature = <110000>; 4299bac12f25SAmit Kucheria hysteresis = <1000>; 4300bac12f25SAmit Kucheria type = "critical"; 4301bac12f25SAmit Kucheria }; 4302bac12f25SAmit Kucheria }; 4303bac12f25SAmit Kucheria 4304bac12f25SAmit Kucheria cooling-maps { 4305bac12f25SAmit Kucheria map0 { 4306bac12f25SAmit Kucheria trip = <&cpu5_bottom_alert0>; 4307bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4308bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4309bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4310bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4311bac12f25SAmit Kucheria }; 4312bac12f25SAmit Kucheria map1 { 4313bac12f25SAmit Kucheria trip = <&cpu5_bottom_alert1>; 4314bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4315bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4316bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4317bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4318bac12f25SAmit Kucheria }; 4319bac12f25SAmit Kucheria }; 4320bac12f25SAmit Kucheria }; 4321bac12f25SAmit Kucheria 4322bac12f25SAmit Kucheria cpu6-bottom-thermal { 4323bac12f25SAmit Kucheria polling-delay-passive = <250>; 4324bac12f25SAmit Kucheria polling-delay = <1000>; 4325bac12f25SAmit Kucheria 4326bac12f25SAmit Kucheria thermal-sensors = <&tsens0 13>; 4327bac12f25SAmit Kucheria 4328bac12f25SAmit Kucheria trips { 4329bac12f25SAmit Kucheria cpu6_bottom_alert0: trip-point0 { 4330bac12f25SAmit Kucheria temperature = <90000>; 4331bac12f25SAmit Kucheria hysteresis = <2000>; 4332bac12f25SAmit Kucheria type = "passive"; 4333bac12f25SAmit Kucheria }; 4334bac12f25SAmit Kucheria 4335bac12f25SAmit Kucheria cpu6_bottom_alert1: trip-point1 { 4336bac12f25SAmit Kucheria temperature = <95000>; 4337bac12f25SAmit Kucheria hysteresis = <2000>; 4338bac12f25SAmit Kucheria type = "passive"; 4339bac12f25SAmit Kucheria }; 4340bac12f25SAmit Kucheria 4341bac12f25SAmit Kucheria cpu6_bottom_crit: cpu_crit { 4342bac12f25SAmit Kucheria temperature = <110000>; 4343bac12f25SAmit Kucheria hysteresis = <1000>; 4344bac12f25SAmit Kucheria type = "critical"; 4345bac12f25SAmit Kucheria }; 4346bac12f25SAmit Kucheria }; 4347bac12f25SAmit Kucheria 4348bac12f25SAmit Kucheria cooling-maps { 4349bac12f25SAmit Kucheria map0 { 4350bac12f25SAmit Kucheria trip = <&cpu6_bottom_alert0>; 4351bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4352bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4353bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4354bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4355bac12f25SAmit Kucheria }; 4356bac12f25SAmit Kucheria map1 { 4357bac12f25SAmit Kucheria trip = <&cpu6_bottom_alert1>; 4358bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4359bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4360bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4361bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4362bac12f25SAmit Kucheria }; 4363bac12f25SAmit Kucheria }; 4364bac12f25SAmit Kucheria }; 4365bac12f25SAmit Kucheria 4366bac12f25SAmit Kucheria cpu7-bottom-thermal { 4367bac12f25SAmit Kucheria polling-delay-passive = <250>; 4368bac12f25SAmit Kucheria polling-delay = <1000>; 4369bac12f25SAmit Kucheria 4370bac12f25SAmit Kucheria thermal-sensors = <&tsens0 14>; 4371bac12f25SAmit Kucheria 4372bac12f25SAmit Kucheria trips { 4373bac12f25SAmit Kucheria cpu7_bottom_alert0: trip-point0 { 4374bac12f25SAmit Kucheria temperature = <90000>; 4375bac12f25SAmit Kucheria hysteresis = <2000>; 4376bac12f25SAmit Kucheria type = "passive"; 4377bac12f25SAmit Kucheria }; 4378bac12f25SAmit Kucheria 4379bac12f25SAmit Kucheria cpu7_bottom_alert1: trip-point1 { 4380bac12f25SAmit Kucheria temperature = <95000>; 4381bac12f25SAmit Kucheria hysteresis = <2000>; 4382bac12f25SAmit Kucheria type = "passive"; 4383bac12f25SAmit Kucheria }; 4384bac12f25SAmit Kucheria 4385bac12f25SAmit Kucheria cpu7_bottom_crit: cpu_crit { 4386bac12f25SAmit Kucheria temperature = <110000>; 4387bac12f25SAmit Kucheria hysteresis = <1000>; 4388bac12f25SAmit Kucheria type = "critical"; 4389bac12f25SAmit Kucheria }; 4390bac12f25SAmit Kucheria }; 4391bac12f25SAmit Kucheria 4392bac12f25SAmit Kucheria cooling-maps { 4393bac12f25SAmit Kucheria map0 { 4394bac12f25SAmit Kucheria trip = <&cpu7_bottom_alert0>; 4395bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4396bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4397bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4398bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4399bac12f25SAmit Kucheria }; 4400bac12f25SAmit Kucheria map1 { 4401bac12f25SAmit Kucheria trip = <&cpu7_bottom_alert1>; 4402bac12f25SAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4403bac12f25SAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4404bac12f25SAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4405bac12f25SAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4406bac12f25SAmit Kucheria }; 4407bac12f25SAmit Kucheria }; 4408bac12f25SAmit Kucheria }; 4409bac12f25SAmit Kucheria 4410bac12f25SAmit Kucheria aoss0-thermal { 4411bac12f25SAmit Kucheria polling-delay-passive = <250>; 4412bac12f25SAmit Kucheria polling-delay = <1000>; 4413bac12f25SAmit Kucheria 4414bac12f25SAmit Kucheria thermal-sensors = <&tsens0 0>; 4415bac12f25SAmit Kucheria 4416bac12f25SAmit Kucheria trips { 4417bac12f25SAmit Kucheria aoss0_alert0: trip-point0 { 4418bac12f25SAmit Kucheria temperature = <90000>; 4419bac12f25SAmit Kucheria hysteresis = <2000>; 4420bac12f25SAmit Kucheria type = "hot"; 4421bac12f25SAmit Kucheria }; 4422bac12f25SAmit Kucheria }; 4423bac12f25SAmit Kucheria }; 4424bac12f25SAmit Kucheria 4425bac12f25SAmit Kucheria cluster0-thermal { 4426bac12f25SAmit Kucheria polling-delay-passive = <250>; 4427bac12f25SAmit Kucheria polling-delay = <1000>; 4428bac12f25SAmit Kucheria 4429bac12f25SAmit Kucheria thermal-sensors = <&tsens0 5>; 4430bac12f25SAmit Kucheria 4431bac12f25SAmit Kucheria trips { 4432bac12f25SAmit Kucheria cluster0_alert0: trip-point0 { 4433bac12f25SAmit Kucheria temperature = <90000>; 4434bac12f25SAmit Kucheria hysteresis = <2000>; 4435bac12f25SAmit Kucheria type = "hot"; 4436bac12f25SAmit Kucheria }; 4437bac12f25SAmit Kucheria cluster0_crit: cluster0_crit { 4438bac12f25SAmit Kucheria temperature = <110000>; 4439bac12f25SAmit Kucheria hysteresis = <2000>; 4440bac12f25SAmit Kucheria type = "critical"; 4441bac12f25SAmit Kucheria }; 4442bac12f25SAmit Kucheria }; 4443bac12f25SAmit Kucheria }; 4444bac12f25SAmit Kucheria 4445bac12f25SAmit Kucheria cluster1-thermal { 4446bac12f25SAmit Kucheria polling-delay-passive = <250>; 4447bac12f25SAmit Kucheria polling-delay = <1000>; 4448bac12f25SAmit Kucheria 4449bac12f25SAmit Kucheria thermal-sensors = <&tsens0 6>; 4450bac12f25SAmit Kucheria 4451bac12f25SAmit Kucheria trips { 4452bac12f25SAmit Kucheria cluster1_alert0: trip-point0 { 4453bac12f25SAmit Kucheria temperature = <90000>; 4454bac12f25SAmit Kucheria hysteresis = <2000>; 4455bac12f25SAmit Kucheria type = "hot"; 4456bac12f25SAmit Kucheria }; 4457bac12f25SAmit Kucheria cluster1_crit: cluster1_crit { 4458bac12f25SAmit Kucheria temperature = <110000>; 4459bac12f25SAmit Kucheria hysteresis = <2000>; 4460bac12f25SAmit Kucheria type = "critical"; 4461bac12f25SAmit Kucheria }; 4462bac12f25SAmit Kucheria }; 4463bac12f25SAmit Kucheria }; 4464bac12f25SAmit Kucheria 4465bac12f25SAmit Kucheria gpu-thermal-top { 4466bac12f25SAmit Kucheria polling-delay-passive = <250>; 4467bac12f25SAmit Kucheria polling-delay = <1000>; 4468bac12f25SAmit Kucheria 4469bac12f25SAmit Kucheria thermal-sensors = <&tsens0 15>; 4470bac12f25SAmit Kucheria 4471bac12f25SAmit Kucheria trips { 4472bac12f25SAmit Kucheria gpu1_alert0: trip-point0 { 4473bac12f25SAmit Kucheria temperature = <90000>; 4474bac12f25SAmit Kucheria hysteresis = <2000>; 4475bac12f25SAmit Kucheria type = "hot"; 4476bac12f25SAmit Kucheria }; 4477bac12f25SAmit Kucheria }; 4478bac12f25SAmit Kucheria }; 4479bac12f25SAmit Kucheria 4480bac12f25SAmit Kucheria aoss1-thermal { 4481bac12f25SAmit Kucheria polling-delay-passive = <250>; 4482bac12f25SAmit Kucheria polling-delay = <1000>; 4483bac12f25SAmit Kucheria 4484bac12f25SAmit Kucheria thermal-sensors = <&tsens1 0>; 4485bac12f25SAmit Kucheria 4486bac12f25SAmit Kucheria trips { 4487bac12f25SAmit Kucheria aoss1_alert0: trip-point0 { 4488bac12f25SAmit Kucheria temperature = <90000>; 4489bac12f25SAmit Kucheria hysteresis = <2000>; 4490bac12f25SAmit Kucheria type = "hot"; 4491bac12f25SAmit Kucheria }; 4492bac12f25SAmit Kucheria }; 4493bac12f25SAmit Kucheria }; 4494bac12f25SAmit Kucheria 4495bac12f25SAmit Kucheria wlan-thermal { 4496bac12f25SAmit Kucheria polling-delay-passive = <250>; 4497bac12f25SAmit Kucheria polling-delay = <1000>; 4498bac12f25SAmit Kucheria 4499bac12f25SAmit Kucheria thermal-sensors = <&tsens1 1>; 4500bac12f25SAmit Kucheria 4501bac12f25SAmit Kucheria trips { 4502bac12f25SAmit Kucheria wlan_alert0: trip-point0 { 4503bac12f25SAmit Kucheria temperature = <90000>; 4504bac12f25SAmit Kucheria hysteresis = <2000>; 4505bac12f25SAmit Kucheria type = "hot"; 4506bac12f25SAmit Kucheria }; 4507bac12f25SAmit Kucheria }; 4508bac12f25SAmit Kucheria }; 4509bac12f25SAmit Kucheria 4510bac12f25SAmit Kucheria video-thermal { 4511bac12f25SAmit Kucheria polling-delay-passive = <250>; 4512bac12f25SAmit Kucheria polling-delay = <1000>; 4513bac12f25SAmit Kucheria 4514bac12f25SAmit Kucheria thermal-sensors = <&tsens1 2>; 4515bac12f25SAmit Kucheria 4516bac12f25SAmit Kucheria trips { 4517bac12f25SAmit Kucheria video_alert0: trip-point0 { 4518bac12f25SAmit Kucheria temperature = <90000>; 4519bac12f25SAmit Kucheria hysteresis = <2000>; 4520bac12f25SAmit Kucheria type = "hot"; 4521bac12f25SAmit Kucheria }; 4522bac12f25SAmit Kucheria }; 4523bac12f25SAmit Kucheria }; 4524bac12f25SAmit Kucheria 4525bac12f25SAmit Kucheria mem-thermal { 4526bac12f25SAmit Kucheria polling-delay-passive = <250>; 4527bac12f25SAmit Kucheria polling-delay = <1000>; 4528bac12f25SAmit Kucheria 4529bac12f25SAmit Kucheria thermal-sensors = <&tsens1 3>; 4530bac12f25SAmit Kucheria 4531bac12f25SAmit Kucheria trips { 4532bac12f25SAmit Kucheria mem_alert0: trip-point0 { 4533bac12f25SAmit Kucheria temperature = <90000>; 4534bac12f25SAmit Kucheria hysteresis = <2000>; 4535bac12f25SAmit Kucheria type = "hot"; 4536bac12f25SAmit Kucheria }; 4537bac12f25SAmit Kucheria }; 4538bac12f25SAmit Kucheria }; 4539bac12f25SAmit Kucheria 4540bac12f25SAmit Kucheria q6-hvx-thermal { 4541bac12f25SAmit Kucheria polling-delay-passive = <250>; 4542bac12f25SAmit Kucheria polling-delay = <1000>; 4543bac12f25SAmit Kucheria 4544bac12f25SAmit Kucheria thermal-sensors = <&tsens1 4>; 4545bac12f25SAmit Kucheria 4546bac12f25SAmit Kucheria trips { 4547bac12f25SAmit Kucheria q6_hvx_alert0: trip-point0 { 4548bac12f25SAmit Kucheria temperature = <90000>; 4549bac12f25SAmit Kucheria hysteresis = <2000>; 4550bac12f25SAmit Kucheria type = "hot"; 4551bac12f25SAmit Kucheria }; 4552bac12f25SAmit Kucheria }; 4553bac12f25SAmit Kucheria }; 4554bac12f25SAmit Kucheria 4555bac12f25SAmit Kucheria camera-thermal { 4556bac12f25SAmit Kucheria polling-delay-passive = <250>; 4557bac12f25SAmit Kucheria polling-delay = <1000>; 4558bac12f25SAmit Kucheria 4559bac12f25SAmit Kucheria thermal-sensors = <&tsens1 5>; 4560bac12f25SAmit Kucheria 4561bac12f25SAmit Kucheria trips { 4562bac12f25SAmit Kucheria camera_alert0: trip-point0 { 4563bac12f25SAmit Kucheria temperature = <90000>; 4564bac12f25SAmit Kucheria hysteresis = <2000>; 4565bac12f25SAmit Kucheria type = "hot"; 4566bac12f25SAmit Kucheria }; 4567bac12f25SAmit Kucheria }; 4568bac12f25SAmit Kucheria }; 4569bac12f25SAmit Kucheria 4570bac12f25SAmit Kucheria compute-thermal { 4571bac12f25SAmit Kucheria polling-delay-passive = <250>; 4572bac12f25SAmit Kucheria polling-delay = <1000>; 4573bac12f25SAmit Kucheria 4574bac12f25SAmit Kucheria thermal-sensors = <&tsens1 6>; 4575bac12f25SAmit Kucheria 4576bac12f25SAmit Kucheria trips { 4577bac12f25SAmit Kucheria compute_alert0: trip-point0 { 4578bac12f25SAmit Kucheria temperature = <90000>; 4579bac12f25SAmit Kucheria hysteresis = <2000>; 4580bac12f25SAmit Kucheria type = "hot"; 4581bac12f25SAmit Kucheria }; 4582bac12f25SAmit Kucheria }; 4583bac12f25SAmit Kucheria }; 4584bac12f25SAmit Kucheria 4585bac12f25SAmit Kucheria npu-thermal { 4586bac12f25SAmit Kucheria polling-delay-passive = <250>; 4587bac12f25SAmit Kucheria polling-delay = <1000>; 4588bac12f25SAmit Kucheria 4589bac12f25SAmit Kucheria thermal-sensors = <&tsens1 7>; 4590bac12f25SAmit Kucheria 4591bac12f25SAmit Kucheria trips { 4592bac12f25SAmit Kucheria npu_alert0: trip-point0 { 4593bac12f25SAmit Kucheria temperature = <90000>; 4594bac12f25SAmit Kucheria hysteresis = <2000>; 4595bac12f25SAmit Kucheria type = "hot"; 4596bac12f25SAmit Kucheria }; 4597bac12f25SAmit Kucheria }; 4598bac12f25SAmit Kucheria }; 4599bac12f25SAmit Kucheria 4600bac12f25SAmit Kucheria gpu-thermal-bottom { 4601bac12f25SAmit Kucheria polling-delay-passive = <250>; 4602bac12f25SAmit Kucheria polling-delay = <1000>; 4603bac12f25SAmit Kucheria 4604bac12f25SAmit Kucheria thermal-sensors = <&tsens1 8>; 4605bac12f25SAmit Kucheria 4606bac12f25SAmit Kucheria trips { 4607bac12f25SAmit Kucheria gpu2_alert0: trip-point0 { 4608bac12f25SAmit Kucheria temperature = <90000>; 4609bac12f25SAmit Kucheria hysteresis = <2000>; 4610bac12f25SAmit Kucheria type = "hot"; 4611bac12f25SAmit Kucheria }; 4612bac12f25SAmit Kucheria }; 4613bac12f25SAmit Kucheria }; 4614bac12f25SAmit Kucheria }; 461560378f1aSVenkata Narendra Kumar Gutta}; 4616