1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/dma/qcom-gpi.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,dispcc-sm8150.h> 13#include <dt-bindings/clock/qcom,gcc-sm8150.h> 14#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sm8150.h> 17#include <dt-bindings/thermal/thermal.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 chosen { }; 26 27 clocks { 28 xo_board: xo-board { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <38400000>; 32 clock-output-names = "xo_board"; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32764>; 39 clock-output-names = "sleep_clk"; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 CPU0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "qcom,kryo485"; 50 reg = <0x0 0x0>; 51 clocks = <&cpufreq_hw 0>; 52 enable-method = "psci"; 53 capacity-dmips-mhz = <488>; 54 dynamic-power-coefficient = <232>; 55 next-level-cache = <&L2_0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 operating-points-v2 = <&cpu0_opp_table>; 58 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 59 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 60 power-domains = <&CPU_PD0>; 61 power-domain-names = "psci"; 62 #cooling-cells = <2>; 63 L2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 next-level-cache = <&L3_0>; 67 L3_0: l3-cache { 68 compatible = "cache"; 69 cache-level = <3>; 70 }; 71 }; 72 }; 73 74 CPU1: cpu@100 { 75 device_type = "cpu"; 76 compatible = "qcom,kryo485"; 77 reg = <0x0 0x100>; 78 clocks = <&cpufreq_hw 0>; 79 enable-method = "psci"; 80 capacity-dmips-mhz = <488>; 81 dynamic-power-coefficient = <232>; 82 next-level-cache = <&L2_100>; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 operating-points-v2 = <&cpu0_opp_table>; 85 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 86 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 87 power-domains = <&CPU_PD1>; 88 power-domain-names = "psci"; 89 #cooling-cells = <2>; 90 L2_100: l2-cache { 91 compatible = "cache"; 92 cache-level = <2>; 93 next-level-cache = <&L3_0>; 94 }; 95 }; 96 97 CPU2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "qcom,kryo485"; 100 reg = <0x0 0x200>; 101 clocks = <&cpufreq_hw 0>; 102 enable-method = "psci"; 103 capacity-dmips-mhz = <488>; 104 dynamic-power-coefficient = <232>; 105 next-level-cache = <&L2_200>; 106 qcom,freq-domain = <&cpufreq_hw 0>; 107 operating-points-v2 = <&cpu0_opp_table>; 108 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 109 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 110 power-domains = <&CPU_PD2>; 111 power-domain-names = "psci"; 112 #cooling-cells = <2>; 113 L2_200: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 next-level-cache = <&L3_0>; 117 }; 118 }; 119 120 CPU3: cpu@300 { 121 device_type = "cpu"; 122 compatible = "qcom,kryo485"; 123 reg = <0x0 0x300>; 124 clocks = <&cpufreq_hw 0>; 125 enable-method = "psci"; 126 capacity-dmips-mhz = <488>; 127 dynamic-power-coefficient = <232>; 128 next-level-cache = <&L2_300>; 129 qcom,freq-domain = <&cpufreq_hw 0>; 130 operating-points-v2 = <&cpu0_opp_table>; 131 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 132 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 133 power-domains = <&CPU_PD3>; 134 power-domain-names = "psci"; 135 #cooling-cells = <2>; 136 L2_300: l2-cache { 137 compatible = "cache"; 138 cache-level = <2>; 139 next-level-cache = <&L3_0>; 140 }; 141 }; 142 143 CPU4: cpu@400 { 144 device_type = "cpu"; 145 compatible = "qcom,kryo485"; 146 reg = <0x0 0x400>; 147 clocks = <&cpufreq_hw 1>; 148 enable-method = "psci"; 149 capacity-dmips-mhz = <1024>; 150 dynamic-power-coefficient = <369>; 151 next-level-cache = <&L2_400>; 152 qcom,freq-domain = <&cpufreq_hw 1>; 153 operating-points-v2 = <&cpu4_opp_table>; 154 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 155 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 156 power-domains = <&CPU_PD4>; 157 power-domain-names = "psci"; 158 #cooling-cells = <2>; 159 L2_400: l2-cache { 160 compatible = "cache"; 161 cache-level = <2>; 162 next-level-cache = <&L3_0>; 163 }; 164 }; 165 166 CPU5: cpu@500 { 167 device_type = "cpu"; 168 compatible = "qcom,kryo485"; 169 reg = <0x0 0x500>; 170 clocks = <&cpufreq_hw 1>; 171 enable-method = "psci"; 172 capacity-dmips-mhz = <1024>; 173 dynamic-power-coefficient = <369>; 174 next-level-cache = <&L2_500>; 175 qcom,freq-domain = <&cpufreq_hw 1>; 176 operating-points-v2 = <&cpu4_opp_table>; 177 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 178 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 179 power-domains = <&CPU_PD5>; 180 power-domain-names = "psci"; 181 #cooling-cells = <2>; 182 L2_500: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 next-level-cache = <&L3_0>; 186 }; 187 }; 188 189 CPU6: cpu@600 { 190 device_type = "cpu"; 191 compatible = "qcom,kryo485"; 192 reg = <0x0 0x600>; 193 clocks = <&cpufreq_hw 1>; 194 enable-method = "psci"; 195 capacity-dmips-mhz = <1024>; 196 dynamic-power-coefficient = <369>; 197 next-level-cache = <&L2_600>; 198 qcom,freq-domain = <&cpufreq_hw 1>; 199 operating-points-v2 = <&cpu4_opp_table>; 200 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 201 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 202 power-domains = <&CPU_PD6>; 203 power-domain-names = "psci"; 204 #cooling-cells = <2>; 205 L2_600: l2-cache { 206 compatible = "cache"; 207 cache-level = <2>; 208 next-level-cache = <&L3_0>; 209 }; 210 }; 211 212 CPU7: cpu@700 { 213 device_type = "cpu"; 214 compatible = "qcom,kryo485"; 215 reg = <0x0 0x700>; 216 clocks = <&cpufreq_hw 2>; 217 enable-method = "psci"; 218 capacity-dmips-mhz = <1024>; 219 dynamic-power-coefficient = <421>; 220 next-level-cache = <&L2_700>; 221 qcom,freq-domain = <&cpufreq_hw 2>; 222 operating-points-v2 = <&cpu7_opp_table>; 223 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 224 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 225 power-domains = <&CPU_PD7>; 226 power-domain-names = "psci"; 227 #cooling-cells = <2>; 228 L2_700: l2-cache { 229 compatible = "cache"; 230 cache-level = <2>; 231 next-level-cache = <&L3_0>; 232 }; 233 }; 234 235 cpu-map { 236 cluster0 { 237 core0 { 238 cpu = <&CPU0>; 239 }; 240 241 core1 { 242 cpu = <&CPU1>; 243 }; 244 245 core2 { 246 cpu = <&CPU2>; 247 }; 248 249 core3 { 250 cpu = <&CPU3>; 251 }; 252 253 core4 { 254 cpu = <&CPU4>; 255 }; 256 257 core5 { 258 cpu = <&CPU5>; 259 }; 260 261 core6 { 262 cpu = <&CPU6>; 263 }; 264 265 core7 { 266 cpu = <&CPU7>; 267 }; 268 }; 269 }; 270 271 idle-states { 272 entry-method = "psci"; 273 274 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 275 compatible = "arm,idle-state"; 276 idle-state-name = "little-rail-power-collapse"; 277 arm,psci-suspend-param = <0x40000004>; 278 entry-latency-us = <355>; 279 exit-latency-us = <909>; 280 min-residency-us = <3934>; 281 local-timer-stop; 282 }; 283 284 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 285 compatible = "arm,idle-state"; 286 idle-state-name = "big-rail-power-collapse"; 287 arm,psci-suspend-param = <0x40000004>; 288 entry-latency-us = <241>; 289 exit-latency-us = <1461>; 290 min-residency-us = <4488>; 291 local-timer-stop; 292 }; 293 }; 294 295 domain-idle-states { 296 CLUSTER_SLEEP_0: cluster-sleep-0 { 297 compatible = "domain-idle-state"; 298 arm,psci-suspend-param = <0x4100c244>; 299 entry-latency-us = <3263>; 300 exit-latency-us = <6562>; 301 min-residency-us = <9987>; 302 }; 303 }; 304 }; 305 306 cpu0_opp_table: opp-table-cpu0 { 307 compatible = "operating-points-v2"; 308 opp-shared; 309 310 cpu0_opp1: opp-300000000 { 311 opp-hz = /bits/ 64 <300000000>; 312 opp-peak-kBps = <800000 9600000>; 313 }; 314 315 cpu0_opp2: opp-403200000 { 316 opp-hz = /bits/ 64 <403200000>; 317 opp-peak-kBps = <800000 9600000>; 318 }; 319 320 cpu0_opp3: opp-499200000 { 321 opp-hz = /bits/ 64 <499200000>; 322 opp-peak-kBps = <800000 12902400>; 323 }; 324 325 cpu0_opp4: opp-576000000 { 326 opp-hz = /bits/ 64 <576000000>; 327 opp-peak-kBps = <800000 12902400>; 328 }; 329 330 cpu0_opp5: opp-672000000 { 331 opp-hz = /bits/ 64 <672000000>; 332 opp-peak-kBps = <800000 15974400>; 333 }; 334 335 cpu0_opp6: opp-768000000 { 336 opp-hz = /bits/ 64 <768000000>; 337 opp-peak-kBps = <1804000 19660800>; 338 }; 339 340 cpu0_opp7: opp-844800000 { 341 opp-hz = /bits/ 64 <844800000>; 342 opp-peak-kBps = <1804000 19660800>; 343 }; 344 345 cpu0_opp8: opp-940800000 { 346 opp-hz = /bits/ 64 <940800000>; 347 opp-peak-kBps = <1804000 22732800>; 348 }; 349 350 cpu0_opp9: opp-1036800000 { 351 opp-hz = /bits/ 64 <1036800000>; 352 opp-peak-kBps = <1804000 22732800>; 353 }; 354 355 cpu0_opp10: opp-1113600000 { 356 opp-hz = /bits/ 64 <1113600000>; 357 opp-peak-kBps = <2188000 25804800>; 358 }; 359 360 cpu0_opp11: opp-1209600000 { 361 opp-hz = /bits/ 64 <1209600000>; 362 opp-peak-kBps = <2188000 31948800>; 363 }; 364 365 cpu0_opp12: opp-1305600000 { 366 opp-hz = /bits/ 64 <1305600000>; 367 opp-peak-kBps = <3072000 31948800>; 368 }; 369 370 cpu0_opp13: opp-1382400000 { 371 opp-hz = /bits/ 64 <1382400000>; 372 opp-peak-kBps = <3072000 31948800>; 373 }; 374 375 cpu0_opp14: opp-1478400000 { 376 opp-hz = /bits/ 64 <1478400000>; 377 opp-peak-kBps = <3072000 31948800>; 378 }; 379 380 cpu0_opp15: opp-1555200000 { 381 opp-hz = /bits/ 64 <1555200000>; 382 opp-peak-kBps = <3072000 40550400>; 383 }; 384 385 cpu0_opp16: opp-1632000000 { 386 opp-hz = /bits/ 64 <1632000000>; 387 opp-peak-kBps = <3072000 40550400>; 388 }; 389 390 cpu0_opp17: opp-1708800000 { 391 opp-hz = /bits/ 64 <1708800000>; 392 opp-peak-kBps = <3072000 43008000>; 393 }; 394 395 cpu0_opp18: opp-1785600000 { 396 opp-hz = /bits/ 64 <1785600000>; 397 opp-peak-kBps = <3072000 43008000>; 398 }; 399 }; 400 401 cpu4_opp_table: opp-table-cpu4 { 402 compatible = "operating-points-v2"; 403 opp-shared; 404 405 cpu4_opp1: opp-710400000 { 406 opp-hz = /bits/ 64 <710400000>; 407 opp-peak-kBps = <1804000 15974400>; 408 }; 409 410 cpu4_opp2: opp-825600000 { 411 opp-hz = /bits/ 64 <825600000>; 412 opp-peak-kBps = <2188000 19660800>; 413 }; 414 415 cpu4_opp3: opp-940800000 { 416 opp-hz = /bits/ 64 <940800000>; 417 opp-peak-kBps = <2188000 22732800>; 418 }; 419 420 cpu4_opp4: opp-1056000000 { 421 opp-hz = /bits/ 64 <1056000000>; 422 opp-peak-kBps = <3072000 25804800>; 423 }; 424 425 cpu4_opp5: opp-1171200000 { 426 opp-hz = /bits/ 64 <1171200000>; 427 opp-peak-kBps = <3072000 31948800>; 428 }; 429 430 cpu4_opp6: opp-1286400000 { 431 opp-hz = /bits/ 64 <1286400000>; 432 opp-peak-kBps = <4068000 31948800>; 433 }; 434 435 cpu4_opp7: opp-1401600000 { 436 opp-hz = /bits/ 64 <1401600000>; 437 opp-peak-kBps = <4068000 31948800>; 438 }; 439 440 cpu4_opp8: opp-1497600000 { 441 opp-hz = /bits/ 64 <1497600000>; 442 opp-peak-kBps = <4068000 40550400>; 443 }; 444 445 cpu4_opp9: opp-1612800000 { 446 opp-hz = /bits/ 64 <1612800000>; 447 opp-peak-kBps = <4068000 40550400>; 448 }; 449 450 cpu4_opp10: opp-1708800000 { 451 opp-hz = /bits/ 64 <1708800000>; 452 opp-peak-kBps = <4068000 43008000>; 453 }; 454 455 cpu4_opp11: opp-1804800000 { 456 opp-hz = /bits/ 64 <1804800000>; 457 opp-peak-kBps = <6220000 43008000>; 458 }; 459 460 cpu4_opp12: opp-1920000000 { 461 opp-hz = /bits/ 64 <1920000000>; 462 opp-peak-kBps = <6220000 49152000>; 463 }; 464 465 cpu4_opp13: opp-2016000000 { 466 opp-hz = /bits/ 64 <2016000000>; 467 opp-peak-kBps = <7216000 49152000>; 468 }; 469 470 cpu4_opp14: opp-2131200000 { 471 opp-hz = /bits/ 64 <2131200000>; 472 opp-peak-kBps = <8368000 49152000>; 473 }; 474 475 cpu4_opp15: opp-2227200000 { 476 opp-hz = /bits/ 64 <2227200000>; 477 opp-peak-kBps = <8368000 51609600>; 478 }; 479 480 cpu4_opp16: opp-2323200000 { 481 opp-hz = /bits/ 64 <2323200000>; 482 opp-peak-kBps = <8368000 51609600>; 483 }; 484 485 cpu4_opp17: opp-2419200000 { 486 opp-hz = /bits/ 64 <2419200000>; 487 opp-peak-kBps = <8368000 51609600>; 488 }; 489 }; 490 491 cpu7_opp_table: opp-table-cpu7 { 492 compatible = "operating-points-v2"; 493 opp-shared; 494 495 cpu7_opp1: opp-825600000 { 496 opp-hz = /bits/ 64 <825600000>; 497 opp-peak-kBps = <2188000 19660800>; 498 }; 499 500 cpu7_opp2: opp-940800000 { 501 opp-hz = /bits/ 64 <940800000>; 502 opp-peak-kBps = <2188000 22732800>; 503 }; 504 505 cpu7_opp3: opp-1056000000 { 506 opp-hz = /bits/ 64 <1056000000>; 507 opp-peak-kBps = <3072000 25804800>; 508 }; 509 510 cpu7_opp4: opp-1171200000 { 511 opp-hz = /bits/ 64 <1171200000>; 512 opp-peak-kBps = <3072000 31948800>; 513 }; 514 515 cpu7_opp5: opp-1286400000 { 516 opp-hz = /bits/ 64 <1286400000>; 517 opp-peak-kBps = <4068000 31948800>; 518 }; 519 520 cpu7_opp6: opp-1401600000 { 521 opp-hz = /bits/ 64 <1401600000>; 522 opp-peak-kBps = <4068000 31948800>; 523 }; 524 525 cpu7_opp7: opp-1497600000 { 526 opp-hz = /bits/ 64 <1497600000>; 527 opp-peak-kBps = <4068000 40550400>; 528 }; 529 530 cpu7_opp8: opp-1612800000 { 531 opp-hz = /bits/ 64 <1612800000>; 532 opp-peak-kBps = <4068000 40550400>; 533 }; 534 535 cpu7_opp9: opp-1708800000 { 536 opp-hz = /bits/ 64 <1708800000>; 537 opp-peak-kBps = <4068000 43008000>; 538 }; 539 540 cpu7_opp10: opp-1804800000 { 541 opp-hz = /bits/ 64 <1804800000>; 542 opp-peak-kBps = <6220000 43008000>; 543 }; 544 545 cpu7_opp11: opp-1920000000 { 546 opp-hz = /bits/ 64 <1920000000>; 547 opp-peak-kBps = <6220000 49152000>; 548 }; 549 550 cpu7_opp12: opp-2016000000 { 551 opp-hz = /bits/ 64 <2016000000>; 552 opp-peak-kBps = <7216000 49152000>; 553 }; 554 555 cpu7_opp13: opp-2131200000 { 556 opp-hz = /bits/ 64 <2131200000>; 557 opp-peak-kBps = <8368000 49152000>; 558 }; 559 560 cpu7_opp14: opp-2227200000 { 561 opp-hz = /bits/ 64 <2227200000>; 562 opp-peak-kBps = <8368000 51609600>; 563 }; 564 565 cpu7_opp15: opp-2323200000 { 566 opp-hz = /bits/ 64 <2323200000>; 567 opp-peak-kBps = <8368000 51609600>; 568 }; 569 570 cpu7_opp16: opp-2419200000 { 571 opp-hz = /bits/ 64 <2419200000>; 572 opp-peak-kBps = <8368000 51609600>; 573 }; 574 575 cpu7_opp17: opp-2534400000 { 576 opp-hz = /bits/ 64 <2534400000>; 577 opp-peak-kBps = <8368000 51609600>; 578 }; 579 580 cpu7_opp18: opp-2649600000 { 581 opp-hz = /bits/ 64 <2649600000>; 582 opp-peak-kBps = <8368000 51609600>; 583 }; 584 585 cpu7_opp19: opp-2745600000 { 586 opp-hz = /bits/ 64 <2745600000>; 587 opp-peak-kBps = <8368000 51609600>; 588 }; 589 590 cpu7_opp20: opp-2841600000 { 591 opp-hz = /bits/ 64 <2841600000>; 592 opp-peak-kBps = <8368000 51609600>; 593 }; 594 }; 595 596 firmware { 597 scm: scm { 598 compatible = "qcom,scm-sm8150", "qcom,scm"; 599 #reset-cells = <1>; 600 }; 601 }; 602 603 memory@80000000 { 604 device_type = "memory"; 605 /* We expect the bootloader to fill in the size */ 606 reg = <0x0 0x80000000 0x0 0x0>; 607 }; 608 609 pmu { 610 compatible = "arm,armv8-pmuv3"; 611 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 612 }; 613 614 psci { 615 compatible = "arm,psci-1.0"; 616 method = "smc"; 617 618 CPU_PD0: power-domain-cpu0 { 619 #power-domain-cells = <0>; 620 power-domains = <&CLUSTER_PD>; 621 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 622 }; 623 624 CPU_PD1: power-domain-cpu1 { 625 #power-domain-cells = <0>; 626 power-domains = <&CLUSTER_PD>; 627 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 628 }; 629 630 CPU_PD2: power-domain-cpu2 { 631 #power-domain-cells = <0>; 632 power-domains = <&CLUSTER_PD>; 633 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 634 }; 635 636 CPU_PD3: power-domain-cpu3 { 637 #power-domain-cells = <0>; 638 power-domains = <&CLUSTER_PD>; 639 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 640 }; 641 642 CPU_PD4: power-domain-cpu4 { 643 #power-domain-cells = <0>; 644 power-domains = <&CLUSTER_PD>; 645 domain-idle-states = <&BIG_CPU_SLEEP_0>; 646 }; 647 648 CPU_PD5: power-domain-cpu5 { 649 #power-domain-cells = <0>; 650 power-domains = <&CLUSTER_PD>; 651 domain-idle-states = <&BIG_CPU_SLEEP_0>; 652 }; 653 654 CPU_PD6: power-domain-cpu6 { 655 #power-domain-cells = <0>; 656 power-domains = <&CLUSTER_PD>; 657 domain-idle-states = <&BIG_CPU_SLEEP_0>; 658 }; 659 660 CPU_PD7: power-domain-cpu7 { 661 #power-domain-cells = <0>; 662 power-domains = <&CLUSTER_PD>; 663 domain-idle-states = <&BIG_CPU_SLEEP_0>; 664 }; 665 666 CLUSTER_PD: power-domain-cpu-cluster0 { 667 #power-domain-cells = <0>; 668 domain-idle-states = <&CLUSTER_SLEEP_0>; 669 }; 670 }; 671 672 reserved-memory { 673 #address-cells = <2>; 674 #size-cells = <2>; 675 ranges; 676 677 hyp_mem: memory@85700000 { 678 reg = <0x0 0x85700000 0x0 0x600000>; 679 no-map; 680 }; 681 682 xbl_mem: memory@85d00000 { 683 reg = <0x0 0x85d00000 0x0 0x140000>; 684 no-map; 685 }; 686 687 aop_mem: memory@85f00000 { 688 reg = <0x0 0x85f00000 0x0 0x20000>; 689 no-map; 690 }; 691 692 aop_cmd_db: memory@85f20000 { 693 compatible = "qcom,cmd-db"; 694 reg = <0x0 0x85f20000 0x0 0x20000>; 695 no-map; 696 }; 697 698 smem_mem: memory@86000000 { 699 reg = <0x0 0x86000000 0x0 0x200000>; 700 no-map; 701 }; 702 703 tz_mem: memory@86200000 { 704 reg = <0x0 0x86200000 0x0 0x3900000>; 705 no-map; 706 }; 707 708 rmtfs_mem: memory@89b00000 { 709 compatible = "qcom,rmtfs-mem"; 710 reg = <0x0 0x89b00000 0x0 0x200000>; 711 no-map; 712 713 qcom,client-id = <1>; 714 qcom,vmid = <15>; 715 }; 716 717 camera_mem: memory@8b700000 { 718 reg = <0x0 0x8b700000 0x0 0x500000>; 719 no-map; 720 }; 721 722 wlan_mem: memory@8bc00000 { 723 reg = <0x0 0x8bc00000 0x0 0x180000>; 724 no-map; 725 }; 726 727 npu_mem: memory@8bd80000 { 728 reg = <0x0 0x8bd80000 0x0 0x80000>; 729 no-map; 730 }; 731 732 adsp_mem: memory@8be00000 { 733 reg = <0x0 0x8be00000 0x0 0x1a00000>; 734 no-map; 735 }; 736 737 mpss_mem: memory@8d800000 { 738 reg = <0x0 0x8d800000 0x0 0x9600000>; 739 no-map; 740 }; 741 742 venus_mem: memory@96e00000 { 743 reg = <0x0 0x96e00000 0x0 0x500000>; 744 no-map; 745 }; 746 747 slpi_mem: memory@97300000 { 748 reg = <0x0 0x97300000 0x0 0x1400000>; 749 no-map; 750 }; 751 752 ipa_fw_mem: memory@98700000 { 753 reg = <0x0 0x98700000 0x0 0x10000>; 754 no-map; 755 }; 756 757 ipa_gsi_mem: memory@98710000 { 758 reg = <0x0 0x98710000 0x0 0x5000>; 759 no-map; 760 }; 761 762 gpu_mem: memory@98715000 { 763 reg = <0x0 0x98715000 0x0 0x2000>; 764 no-map; 765 }; 766 767 spss_mem: memory@98800000 { 768 reg = <0x0 0x98800000 0x0 0x100000>; 769 no-map; 770 }; 771 772 cdsp_mem: memory@98900000 { 773 reg = <0x0 0x98900000 0x0 0x1400000>; 774 no-map; 775 }; 776 777 qseecom_mem: memory@9e400000 { 778 reg = <0x0 0x9e400000 0x0 0x1400000>; 779 no-map; 780 }; 781 }; 782 783 smem { 784 compatible = "qcom,smem"; 785 memory-region = <&smem_mem>; 786 hwlocks = <&tcsr_mutex 3>; 787 }; 788 789 smp2p-cdsp { 790 compatible = "qcom,smp2p"; 791 qcom,smem = <94>, <432>; 792 793 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 794 795 mboxes = <&apss_shared 6>; 796 797 qcom,local-pid = <0>; 798 qcom,remote-pid = <5>; 799 800 cdsp_smp2p_out: master-kernel { 801 qcom,entry-name = "master-kernel"; 802 #qcom,smem-state-cells = <1>; 803 }; 804 805 cdsp_smp2p_in: slave-kernel { 806 qcom,entry-name = "slave-kernel"; 807 808 interrupt-controller; 809 #interrupt-cells = <2>; 810 }; 811 }; 812 813 smp2p-lpass { 814 compatible = "qcom,smp2p"; 815 qcom,smem = <443>, <429>; 816 817 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 818 819 mboxes = <&apss_shared 10>; 820 821 qcom,local-pid = <0>; 822 qcom,remote-pid = <2>; 823 824 adsp_smp2p_out: master-kernel { 825 qcom,entry-name = "master-kernel"; 826 #qcom,smem-state-cells = <1>; 827 }; 828 829 adsp_smp2p_in: slave-kernel { 830 qcom,entry-name = "slave-kernel"; 831 832 interrupt-controller; 833 #interrupt-cells = <2>; 834 }; 835 }; 836 837 smp2p-mpss { 838 compatible = "qcom,smp2p"; 839 qcom,smem = <435>, <428>; 840 841 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 842 843 mboxes = <&apss_shared 14>; 844 845 qcom,local-pid = <0>; 846 qcom,remote-pid = <1>; 847 848 modem_smp2p_out: master-kernel { 849 qcom,entry-name = "master-kernel"; 850 #qcom,smem-state-cells = <1>; 851 }; 852 853 modem_smp2p_in: slave-kernel { 854 qcom,entry-name = "slave-kernel"; 855 856 interrupt-controller; 857 #interrupt-cells = <2>; 858 }; 859 }; 860 861 smp2p-slpi { 862 compatible = "qcom,smp2p"; 863 qcom,smem = <481>, <430>; 864 865 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 866 867 mboxes = <&apss_shared 26>; 868 869 qcom,local-pid = <0>; 870 qcom,remote-pid = <3>; 871 872 slpi_smp2p_out: master-kernel { 873 qcom,entry-name = "master-kernel"; 874 #qcom,smem-state-cells = <1>; 875 }; 876 877 slpi_smp2p_in: slave-kernel { 878 qcom,entry-name = "slave-kernel"; 879 880 interrupt-controller; 881 #interrupt-cells = <2>; 882 }; 883 }; 884 885 soc: soc@0 { 886 #address-cells = <2>; 887 #size-cells = <2>; 888 ranges = <0 0 0 0 0x10 0>; 889 dma-ranges = <0 0 0 0 0x10 0>; 890 compatible = "simple-bus"; 891 892 gcc: clock-controller@100000 { 893 compatible = "qcom,gcc-sm8150"; 894 reg = <0x0 0x00100000 0x0 0x1f0000>; 895 #clock-cells = <1>; 896 #reset-cells = <1>; 897 #power-domain-cells = <1>; 898 clock-names = "bi_tcxo", 899 "sleep_clk"; 900 clocks = <&rpmhcc RPMH_CXO_CLK>, 901 <&sleep_clk>; 902 }; 903 904 gpi_dma0: dma-controller@800000 { 905 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 906 reg = <0 0x00800000 0 0x60000>; 907 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 920 dma-channels = <13>; 921 dma-channel-mask = <0xfa>; 922 iommus = <&apps_smmu 0x00d6 0x0>; 923 #dma-cells = <3>; 924 status = "disabled"; 925 }; 926 927 ethernet: ethernet@20000 { 928 compatible = "qcom,sm8150-ethqos"; 929 reg = <0x0 0x00020000 0x0 0x10000>, 930 <0x0 0x00036000 0x0 0x100>; 931 reg-names = "stmmaceth", "rgmii"; 932 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 933 clocks = <&gcc GCC_EMAC_AXI_CLK>, 934 <&gcc GCC_EMAC_SLV_AHB_CLK>, 935 <&gcc GCC_EMAC_PTP_CLK>, 936 <&gcc GCC_EMAC_RGMII_CLK>; 937 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 939 interrupt-names = "macirq", "eth_lpi"; 940 941 power-domains = <&gcc EMAC_GDSC>; 942 resets = <&gcc GCC_EMAC_BCR>; 943 944 iommus = <&apps_smmu 0x3c0 0x0>; 945 946 snps,tso; 947 rx-fifo-depth = <4096>; 948 tx-fifo-depth = <4096>; 949 950 status = "disabled"; 951 }; 952 953 qfprom: efuse@784000 { 954 compatible = "qcom,sm8150-qfprom", "qcom,qfprom"; 955 reg = <0 0x00784000 0 0x8ff>; 956 #address-cells = <1>; 957 #size-cells = <1>; 958 959 gpu_speed_bin: gpu_speed_bin@133 { 960 reg = <0x133 0x1>; 961 bits = <5 3>; 962 }; 963 }; 964 965 qupv3_id_0: geniqup@8c0000 { 966 compatible = "qcom,geni-se-qup"; 967 reg = <0x0 0x008c0000 0x0 0x6000>; 968 clock-names = "m-ahb", "s-ahb"; 969 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 970 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 971 iommus = <&apps_smmu 0xc3 0x0>; 972 #address-cells = <2>; 973 #size-cells = <2>; 974 ranges; 975 status = "disabled"; 976 977 i2c0: i2c@880000 { 978 compatible = "qcom,geni-i2c"; 979 reg = <0 0x00880000 0 0x4000>; 980 clock-names = "se"; 981 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 982 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 983 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 984 dma-names = "tx", "rx"; 985 pinctrl-names = "default"; 986 pinctrl-0 = <&qup_i2c0_default>; 987 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 988 #address-cells = <1>; 989 #size-cells = <0>; 990 status = "disabled"; 991 }; 992 993 spi0: spi@880000 { 994 compatible = "qcom,geni-spi"; 995 reg = <0 0x00880000 0 0x4000>; 996 reg-names = "se"; 997 clock-names = "se"; 998 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 999 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1000 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1001 dma-names = "tx", "rx"; 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&qup_spi0_default>; 1004 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1005 spi-max-frequency = <50000000>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 status = "disabled"; 1009 }; 1010 1011 i2c1: i2c@884000 { 1012 compatible = "qcom,geni-i2c"; 1013 reg = <0 0x00884000 0 0x4000>; 1014 clock-names = "se"; 1015 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1016 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1017 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1018 dma-names = "tx", "rx"; 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&qup_i2c1_default>; 1021 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 status = "disabled"; 1025 }; 1026 1027 spi1: spi@884000 { 1028 compatible = "qcom,geni-spi"; 1029 reg = <0 0x00884000 0 0x4000>; 1030 reg-names = "se"; 1031 clock-names = "se"; 1032 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1033 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1034 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1035 dma-names = "tx", "rx"; 1036 pinctrl-names = "default"; 1037 pinctrl-0 = <&qup_spi1_default>; 1038 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1039 spi-max-frequency = <50000000>; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 status = "disabled"; 1043 }; 1044 1045 i2c2: i2c@888000 { 1046 compatible = "qcom,geni-i2c"; 1047 reg = <0 0x00888000 0 0x4000>; 1048 clock-names = "se"; 1049 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1050 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1051 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1052 dma-names = "tx", "rx"; 1053 pinctrl-names = "default"; 1054 pinctrl-0 = <&qup_i2c2_default>; 1055 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1056 #address-cells = <1>; 1057 #size-cells = <0>; 1058 status = "disabled"; 1059 }; 1060 1061 spi2: spi@888000 { 1062 compatible = "qcom,geni-spi"; 1063 reg = <0 0x00888000 0 0x4000>; 1064 reg-names = "se"; 1065 clock-names = "se"; 1066 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1067 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1068 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1069 dma-names = "tx", "rx"; 1070 pinctrl-names = "default"; 1071 pinctrl-0 = <&qup_spi2_default>; 1072 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1073 spi-max-frequency = <50000000>; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 status = "disabled"; 1077 }; 1078 1079 i2c3: i2c@88c000 { 1080 compatible = "qcom,geni-i2c"; 1081 reg = <0 0x0088c000 0 0x4000>; 1082 clock-names = "se"; 1083 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1084 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1085 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1086 dma-names = "tx", "rx"; 1087 pinctrl-names = "default"; 1088 pinctrl-0 = <&qup_i2c3_default>; 1089 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 status = "disabled"; 1093 }; 1094 1095 spi3: spi@88c000 { 1096 compatible = "qcom,geni-spi"; 1097 reg = <0 0x0088c000 0 0x4000>; 1098 reg-names = "se"; 1099 clock-names = "se"; 1100 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1101 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1102 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1103 dma-names = "tx", "rx"; 1104 pinctrl-names = "default"; 1105 pinctrl-0 = <&qup_spi3_default>; 1106 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1107 spi-max-frequency = <50000000>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 status = "disabled"; 1111 }; 1112 1113 i2c4: i2c@890000 { 1114 compatible = "qcom,geni-i2c"; 1115 reg = <0 0x00890000 0 0x4000>; 1116 clock-names = "se"; 1117 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1118 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1119 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1120 dma-names = "tx", "rx"; 1121 pinctrl-names = "default"; 1122 pinctrl-0 = <&qup_i2c4_default>; 1123 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 status = "disabled"; 1127 }; 1128 1129 spi4: spi@890000 { 1130 compatible = "qcom,geni-spi"; 1131 reg = <0 0x00890000 0 0x4000>; 1132 reg-names = "se"; 1133 clock-names = "se"; 1134 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1135 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1136 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1137 dma-names = "tx", "rx"; 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&qup_spi4_default>; 1140 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1141 spi-max-frequency = <50000000>; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 status = "disabled"; 1145 }; 1146 1147 i2c5: i2c@894000 { 1148 compatible = "qcom,geni-i2c"; 1149 reg = <0 0x00894000 0 0x4000>; 1150 clock-names = "se"; 1151 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1152 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1153 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1154 dma-names = "tx", "rx"; 1155 pinctrl-names = "default"; 1156 pinctrl-0 = <&qup_i2c5_default>; 1157 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 status = "disabled"; 1161 }; 1162 1163 spi5: spi@894000 { 1164 compatible = "qcom,geni-spi"; 1165 reg = <0 0x00894000 0 0x4000>; 1166 reg-names = "se"; 1167 clock-names = "se"; 1168 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1169 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1170 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1171 dma-names = "tx", "rx"; 1172 pinctrl-names = "default"; 1173 pinctrl-0 = <&qup_spi5_default>; 1174 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1175 spi-max-frequency = <50000000>; 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 status = "disabled"; 1179 }; 1180 1181 i2c6: i2c@898000 { 1182 compatible = "qcom,geni-i2c"; 1183 reg = <0 0x00898000 0 0x4000>; 1184 clock-names = "se"; 1185 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1186 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1187 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1188 dma-names = "tx", "rx"; 1189 pinctrl-names = "default"; 1190 pinctrl-0 = <&qup_i2c6_default>; 1191 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 status = "disabled"; 1195 }; 1196 1197 spi6: spi@898000 { 1198 compatible = "qcom,geni-spi"; 1199 reg = <0 0x00898000 0 0x4000>; 1200 reg-names = "se"; 1201 clock-names = "se"; 1202 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1203 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1204 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1205 dma-names = "tx", "rx"; 1206 pinctrl-names = "default"; 1207 pinctrl-0 = <&qup_spi6_default>; 1208 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1209 spi-max-frequency = <50000000>; 1210 #address-cells = <1>; 1211 #size-cells = <0>; 1212 status = "disabled"; 1213 }; 1214 1215 i2c7: i2c@89c000 { 1216 compatible = "qcom,geni-i2c"; 1217 reg = <0 0x0089c000 0 0x4000>; 1218 clock-names = "se"; 1219 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1220 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1221 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1222 dma-names = "tx", "rx"; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&qup_i2c7_default>; 1225 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 status = "disabled"; 1229 }; 1230 1231 spi7: spi@89c000 { 1232 compatible = "qcom,geni-spi"; 1233 reg = <0 0x0089c000 0 0x4000>; 1234 reg-names = "se"; 1235 clock-names = "se"; 1236 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1237 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1238 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1239 dma-names = "tx", "rx"; 1240 pinctrl-names = "default"; 1241 pinctrl-0 = <&qup_spi7_default>; 1242 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1243 spi-max-frequency = <50000000>; 1244 #address-cells = <1>; 1245 #size-cells = <0>; 1246 status = "disabled"; 1247 }; 1248 }; 1249 1250 gpi_dma1: dma-controller@a00000 { 1251 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1252 reg = <0 0x00a00000 0 0x60000>; 1253 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1259 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1261 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1262 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1266 dma-channels = <13>; 1267 dma-channel-mask = <0xfa>; 1268 iommus = <&apps_smmu 0x0616 0x0>; 1269 #dma-cells = <3>; 1270 status = "disabled"; 1271 }; 1272 1273 qupv3_id_1: geniqup@ac0000 { 1274 compatible = "qcom,geni-se-qup"; 1275 reg = <0x0 0x00ac0000 0x0 0x6000>; 1276 clock-names = "m-ahb", "s-ahb"; 1277 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1278 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1279 iommus = <&apps_smmu 0x603 0x0>; 1280 #address-cells = <2>; 1281 #size-cells = <2>; 1282 ranges; 1283 status = "disabled"; 1284 1285 i2c8: i2c@a80000 { 1286 compatible = "qcom,geni-i2c"; 1287 reg = <0 0x00a80000 0 0x4000>; 1288 clock-names = "se"; 1289 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1290 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1291 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1292 dma-names = "tx", "rx"; 1293 pinctrl-names = "default"; 1294 pinctrl-0 = <&qup_i2c8_default>; 1295 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 status = "disabled"; 1299 }; 1300 1301 spi8: spi@a80000 { 1302 compatible = "qcom,geni-spi"; 1303 reg = <0 0x00a80000 0 0x4000>; 1304 reg-names = "se"; 1305 clock-names = "se"; 1306 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1307 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1308 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1309 dma-names = "tx", "rx"; 1310 pinctrl-names = "default"; 1311 pinctrl-0 = <&qup_spi8_default>; 1312 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1313 spi-max-frequency = <50000000>; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 status = "disabled"; 1317 }; 1318 1319 i2c9: i2c@a84000 { 1320 compatible = "qcom,geni-i2c"; 1321 reg = <0 0x00a84000 0 0x4000>; 1322 clock-names = "se"; 1323 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1324 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1325 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1326 dma-names = "tx", "rx"; 1327 pinctrl-names = "default"; 1328 pinctrl-0 = <&qup_i2c9_default>; 1329 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 status = "disabled"; 1333 }; 1334 1335 spi9: spi@a84000 { 1336 compatible = "qcom,geni-spi"; 1337 reg = <0 0x00a84000 0 0x4000>; 1338 reg-names = "se"; 1339 clock-names = "se"; 1340 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1341 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1342 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1343 dma-names = "tx", "rx"; 1344 pinctrl-names = "default"; 1345 pinctrl-0 = <&qup_spi9_default>; 1346 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1347 spi-max-frequency = <50000000>; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 status = "disabled"; 1351 }; 1352 1353 uart9: serial@a84000 { 1354 compatible = "qcom,geni-uart"; 1355 reg = <0x0 0x00a84000 0x0 0x4000>; 1356 reg-names = "se"; 1357 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1358 clock-names = "se"; 1359 pinctrl-0 = <&qup_uart9_default>; 1360 pinctrl-names = "default"; 1361 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 status = "disabled"; 1365 }; 1366 1367 i2c10: i2c@a88000 { 1368 compatible = "qcom,geni-i2c"; 1369 reg = <0 0x00a88000 0 0x4000>; 1370 clock-names = "se"; 1371 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1372 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1373 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1374 dma-names = "tx", "rx"; 1375 pinctrl-names = "default"; 1376 pinctrl-0 = <&qup_i2c10_default>; 1377 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 status = "disabled"; 1381 }; 1382 1383 spi10: spi@a88000 { 1384 compatible = "qcom,geni-spi"; 1385 reg = <0 0x00a88000 0 0x4000>; 1386 reg-names = "se"; 1387 clock-names = "se"; 1388 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1389 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1390 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1391 dma-names = "tx", "rx"; 1392 pinctrl-names = "default"; 1393 pinctrl-0 = <&qup_spi10_default>; 1394 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1395 spi-max-frequency = <50000000>; 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 status = "disabled"; 1399 }; 1400 1401 i2c11: i2c@a8c000 { 1402 compatible = "qcom,geni-i2c"; 1403 reg = <0 0x00a8c000 0 0x4000>; 1404 clock-names = "se"; 1405 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1406 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1407 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1408 dma-names = "tx", "rx"; 1409 pinctrl-names = "default"; 1410 pinctrl-0 = <&qup_i2c11_default>; 1411 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1412 #address-cells = <1>; 1413 #size-cells = <0>; 1414 status = "disabled"; 1415 }; 1416 1417 spi11: spi@a8c000 { 1418 compatible = "qcom,geni-spi"; 1419 reg = <0 0x00a8c000 0 0x4000>; 1420 reg-names = "se"; 1421 clock-names = "se"; 1422 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1423 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1424 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1425 dma-names = "tx", "rx"; 1426 pinctrl-names = "default"; 1427 pinctrl-0 = <&qup_spi11_default>; 1428 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1429 spi-max-frequency = <50000000>; 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 status = "disabled"; 1433 }; 1434 1435 uart2: serial@a90000 { 1436 compatible = "qcom,geni-debug-uart"; 1437 reg = <0x0 0x00a90000 0x0 0x4000>; 1438 clock-names = "se"; 1439 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1440 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1441 status = "disabled"; 1442 }; 1443 1444 i2c12: i2c@a90000 { 1445 compatible = "qcom,geni-i2c"; 1446 reg = <0 0x00a90000 0 0x4000>; 1447 clock-names = "se"; 1448 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1449 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1450 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1451 dma-names = "tx", "rx"; 1452 pinctrl-names = "default"; 1453 pinctrl-0 = <&qup_i2c12_default>; 1454 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1455 #address-cells = <1>; 1456 #size-cells = <0>; 1457 status = "disabled"; 1458 }; 1459 1460 spi12: spi@a90000 { 1461 compatible = "qcom,geni-spi"; 1462 reg = <0 0x00a90000 0 0x4000>; 1463 reg-names = "se"; 1464 clock-names = "se"; 1465 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1466 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1467 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1468 dma-names = "tx", "rx"; 1469 pinctrl-names = "default"; 1470 pinctrl-0 = <&qup_spi12_default>; 1471 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1472 spi-max-frequency = <50000000>; 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 status = "disabled"; 1476 }; 1477 1478 i2c16: i2c@94000 { 1479 compatible = "qcom,geni-i2c"; 1480 reg = <0 0x00094000 0 0x4000>; 1481 clock-names = "se"; 1482 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1483 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1484 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1485 dma-names = "tx", "rx"; 1486 pinctrl-names = "default"; 1487 pinctrl-0 = <&qup_i2c16_default>; 1488 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1489 #address-cells = <1>; 1490 #size-cells = <0>; 1491 status = "disabled"; 1492 }; 1493 1494 spi16: spi@a94000 { 1495 compatible = "qcom,geni-spi"; 1496 reg = <0 0x00a94000 0 0x4000>; 1497 reg-names = "se"; 1498 clock-names = "se"; 1499 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1500 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1501 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1502 dma-names = "tx", "rx"; 1503 pinctrl-names = "default"; 1504 pinctrl-0 = <&qup_spi16_default>; 1505 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1506 spi-max-frequency = <50000000>; 1507 #address-cells = <1>; 1508 #size-cells = <0>; 1509 status = "disabled"; 1510 }; 1511 }; 1512 1513 gpi_dma2: dma-controller@c00000 { 1514 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1515 reg = <0 0x00c00000 0 0x60000>; 1516 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 1529 dma-channels = <13>; 1530 dma-channel-mask = <0xfa>; 1531 iommus = <&apps_smmu 0x07b6 0x0>; 1532 #dma-cells = <3>; 1533 status = "disabled"; 1534 }; 1535 1536 qupv3_id_2: geniqup@cc0000 { 1537 compatible = "qcom,geni-se-qup"; 1538 reg = <0x0 0x00cc0000 0x0 0x6000>; 1539 1540 clock-names = "m-ahb", "s-ahb"; 1541 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1542 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1543 iommus = <&apps_smmu 0x7a3 0x0>; 1544 #address-cells = <2>; 1545 #size-cells = <2>; 1546 ranges; 1547 status = "disabled"; 1548 1549 i2c17: i2c@c80000 { 1550 compatible = "qcom,geni-i2c"; 1551 reg = <0 0x00c80000 0 0x4000>; 1552 clock-names = "se"; 1553 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1554 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1555 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1556 dma-names = "tx", "rx"; 1557 pinctrl-names = "default"; 1558 pinctrl-0 = <&qup_i2c17_default>; 1559 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1560 #address-cells = <1>; 1561 #size-cells = <0>; 1562 status = "disabled"; 1563 }; 1564 1565 spi17: spi@c80000 { 1566 compatible = "qcom,geni-spi"; 1567 reg = <0 0x00c80000 0 0x4000>; 1568 reg-names = "se"; 1569 clock-names = "se"; 1570 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1571 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1572 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1573 dma-names = "tx", "rx"; 1574 pinctrl-names = "default"; 1575 pinctrl-0 = <&qup_spi17_default>; 1576 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1577 spi-max-frequency = <50000000>; 1578 #address-cells = <1>; 1579 #size-cells = <0>; 1580 status = "disabled"; 1581 }; 1582 1583 i2c18: i2c@c84000 { 1584 compatible = "qcom,geni-i2c"; 1585 reg = <0 0x00c84000 0 0x4000>; 1586 clock-names = "se"; 1587 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1588 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1589 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1590 dma-names = "tx", "rx"; 1591 pinctrl-names = "default"; 1592 pinctrl-0 = <&qup_i2c18_default>; 1593 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1594 #address-cells = <1>; 1595 #size-cells = <0>; 1596 status = "disabled"; 1597 }; 1598 1599 spi18: spi@c84000 { 1600 compatible = "qcom,geni-spi"; 1601 reg = <0 0x00c84000 0 0x4000>; 1602 reg-names = "se"; 1603 clock-names = "se"; 1604 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1605 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1606 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1607 dma-names = "tx", "rx"; 1608 pinctrl-names = "default"; 1609 pinctrl-0 = <&qup_spi18_default>; 1610 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1611 spi-max-frequency = <50000000>; 1612 #address-cells = <1>; 1613 #size-cells = <0>; 1614 status = "disabled"; 1615 }; 1616 1617 i2c19: i2c@c88000 { 1618 compatible = "qcom,geni-i2c"; 1619 reg = <0 0x00c88000 0 0x4000>; 1620 clock-names = "se"; 1621 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1622 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1623 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1624 dma-names = "tx", "rx"; 1625 pinctrl-names = "default"; 1626 pinctrl-0 = <&qup_i2c19_default>; 1627 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1628 #address-cells = <1>; 1629 #size-cells = <0>; 1630 status = "disabled"; 1631 }; 1632 1633 spi19: spi@c88000 { 1634 compatible = "qcom,geni-spi"; 1635 reg = <0 0x00c88000 0 0x4000>; 1636 reg-names = "se"; 1637 clock-names = "se"; 1638 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1639 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1640 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1641 dma-names = "tx", "rx"; 1642 pinctrl-names = "default"; 1643 pinctrl-0 = <&qup_spi19_default>; 1644 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1645 spi-max-frequency = <50000000>; 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 status = "disabled"; 1649 }; 1650 1651 i2c13: i2c@c8c000 { 1652 compatible = "qcom,geni-i2c"; 1653 reg = <0 0x00c8c000 0 0x4000>; 1654 clock-names = "se"; 1655 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1656 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1657 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1658 dma-names = "tx", "rx"; 1659 pinctrl-names = "default"; 1660 pinctrl-0 = <&qup_i2c13_default>; 1661 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1662 #address-cells = <1>; 1663 #size-cells = <0>; 1664 status = "disabled"; 1665 }; 1666 1667 spi13: spi@c8c000 { 1668 compatible = "qcom,geni-spi"; 1669 reg = <0 0x00c8c000 0 0x4000>; 1670 reg-names = "se"; 1671 clock-names = "se"; 1672 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1673 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1674 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1675 dma-names = "tx", "rx"; 1676 pinctrl-names = "default"; 1677 pinctrl-0 = <&qup_spi13_default>; 1678 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1679 spi-max-frequency = <50000000>; 1680 #address-cells = <1>; 1681 #size-cells = <0>; 1682 status = "disabled"; 1683 }; 1684 1685 i2c14: i2c@c90000 { 1686 compatible = "qcom,geni-i2c"; 1687 reg = <0 0x00c90000 0 0x4000>; 1688 clock-names = "se"; 1689 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1690 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1691 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1692 dma-names = "tx", "rx"; 1693 pinctrl-names = "default"; 1694 pinctrl-0 = <&qup_i2c14_default>; 1695 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1696 #address-cells = <1>; 1697 #size-cells = <0>; 1698 status = "disabled"; 1699 }; 1700 1701 spi14: spi@c90000 { 1702 compatible = "qcom,geni-spi"; 1703 reg = <0 0x00c90000 0 0x4000>; 1704 reg-names = "se"; 1705 clock-names = "se"; 1706 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1707 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1708 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1709 dma-names = "tx", "rx"; 1710 pinctrl-names = "default"; 1711 pinctrl-0 = <&qup_spi14_default>; 1712 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1713 spi-max-frequency = <50000000>; 1714 #address-cells = <1>; 1715 #size-cells = <0>; 1716 status = "disabled"; 1717 }; 1718 1719 i2c15: i2c@c94000 { 1720 compatible = "qcom,geni-i2c"; 1721 reg = <0 0x00c94000 0 0x4000>; 1722 clock-names = "se"; 1723 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1724 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1725 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1726 dma-names = "tx", "rx"; 1727 pinctrl-names = "default"; 1728 pinctrl-0 = <&qup_i2c15_default>; 1729 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1730 #address-cells = <1>; 1731 #size-cells = <0>; 1732 status = "disabled"; 1733 }; 1734 1735 spi15: spi@c94000 { 1736 compatible = "qcom,geni-spi"; 1737 reg = <0 0x00c94000 0 0x4000>; 1738 reg-names = "se"; 1739 clock-names = "se"; 1740 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1741 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1742 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1743 dma-names = "tx", "rx"; 1744 pinctrl-names = "default"; 1745 pinctrl-0 = <&qup_spi15_default>; 1746 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1747 spi-max-frequency = <50000000>; 1748 #address-cells = <1>; 1749 #size-cells = <0>; 1750 status = "disabled"; 1751 }; 1752 }; 1753 1754 config_noc: interconnect@1500000 { 1755 compatible = "qcom,sm8150-config-noc"; 1756 reg = <0 0x01500000 0 0x7400>; 1757 #interconnect-cells = <1>; 1758 qcom,bcm-voters = <&apps_bcm_voter>; 1759 }; 1760 1761 system_noc: interconnect@1620000 { 1762 compatible = "qcom,sm8150-system-noc"; 1763 reg = <0 0x01620000 0 0x19400>; 1764 #interconnect-cells = <1>; 1765 qcom,bcm-voters = <&apps_bcm_voter>; 1766 }; 1767 1768 mc_virt: interconnect@163a000 { 1769 compatible = "qcom,sm8150-mc-virt"; 1770 reg = <0 0x0163a000 0 0x1000>; 1771 #interconnect-cells = <1>; 1772 qcom,bcm-voters = <&apps_bcm_voter>; 1773 }; 1774 1775 aggre1_noc: interconnect@16e0000 { 1776 compatible = "qcom,sm8150-aggre1-noc"; 1777 reg = <0 0x016e0000 0 0xd080>; 1778 #interconnect-cells = <1>; 1779 qcom,bcm-voters = <&apps_bcm_voter>; 1780 }; 1781 1782 aggre2_noc: interconnect@1700000 { 1783 compatible = "qcom,sm8150-aggre2-noc"; 1784 reg = <0 0x01700000 0 0x20000>; 1785 #interconnect-cells = <1>; 1786 qcom,bcm-voters = <&apps_bcm_voter>; 1787 }; 1788 1789 compute_noc: interconnect@1720000 { 1790 compatible = "qcom,sm8150-compute-noc"; 1791 reg = <0 0x01720000 0 0x7000>; 1792 #interconnect-cells = <1>; 1793 qcom,bcm-voters = <&apps_bcm_voter>; 1794 }; 1795 1796 mmss_noc: interconnect@1740000 { 1797 compatible = "qcom,sm8150-mmss-noc"; 1798 reg = <0 0x01740000 0 0x1c100>; 1799 #interconnect-cells = <1>; 1800 qcom,bcm-voters = <&apps_bcm_voter>; 1801 }; 1802 1803 system-cache-controller@9200000 { 1804 compatible = "qcom,sm8150-llcc"; 1805 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 1806 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 1807 <0 0x09600000 0 0x50000>; 1808 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 1809 "llcc3_base", "llcc_broadcast_base"; 1810 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1811 }; 1812 1813 dma@10a2000 { 1814 compatible = "qcom,sm8150-dcc", "qcom,dcc"; 1815 reg = <0x0 0x010a2000 0x0 0x1000>, 1816 <0x0 0x010ad000 0x0 0x3000>; 1817 }; 1818 1819 pcie0: pci@1c00000 { 1820 compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1821 reg = <0 0x01c00000 0 0x3000>, 1822 <0 0x60000000 0 0xf1d>, 1823 <0 0x60000f20 0 0xa8>, 1824 <0 0x60001000 0 0x1000>, 1825 <0 0x60100000 0 0x100000>; 1826 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1827 device_type = "pci"; 1828 linux,pci-domain = <0>; 1829 bus-range = <0x00 0xff>; 1830 num-lanes = <1>; 1831 1832 #address-cells = <3>; 1833 #size-cells = <2>; 1834 1835 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1836 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1837 1838 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1839 interrupt-names = "msi"; 1840 #interrupt-cells = <1>; 1841 interrupt-map-mask = <0 0 0 0x7>; 1842 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1843 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1844 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1845 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1846 1847 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1848 <&gcc GCC_PCIE_0_AUX_CLK>, 1849 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1850 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1851 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1852 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1853 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1854 clock-names = "pipe", 1855 "aux", 1856 "cfg", 1857 "bus_master", 1858 "bus_slave", 1859 "slave_q2a", 1860 "tbu"; 1861 1862 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1863 <0x100 &apps_smmu 0x1d81 0x1>; 1864 1865 resets = <&gcc GCC_PCIE_0_BCR>; 1866 reset-names = "pci"; 1867 1868 power-domains = <&gcc PCIE_0_GDSC>; 1869 1870 phys = <&pcie0_lane>; 1871 phy-names = "pciephy"; 1872 1873 perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1874 enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1875 1876 pinctrl-names = "default"; 1877 pinctrl-0 = <&pcie0_default_state>; 1878 1879 status = "disabled"; 1880 }; 1881 1882 pcie0_phy: phy@1c06000 { 1883 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1884 reg = <0 0x01c06000 0 0x1c0>; 1885 #address-cells = <2>; 1886 #size-cells = <2>; 1887 ranges; 1888 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1889 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1890 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1891 clock-names = "aux", "cfg_ahb", "refgen"; 1892 1893 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1894 reset-names = "phy"; 1895 1896 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1897 assigned-clock-rates = <100000000>; 1898 1899 status = "disabled"; 1900 1901 pcie0_lane: phy@1c06200 { 1902 reg = <0 0x01c06200 0 0x170>, /* tx */ 1903 <0 0x01c06400 0 0x200>, /* rx */ 1904 <0 0x01c06800 0 0x1f0>, /* pcs */ 1905 <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1906 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1907 clock-names = "pipe0"; 1908 1909 #phy-cells = <0>; 1910 clock-output-names = "pcie_0_pipe_clk"; 1911 }; 1912 }; 1913 1914 pcie1: pci@1c08000 { 1915 compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1916 reg = <0 0x01c08000 0 0x3000>, 1917 <0 0x40000000 0 0xf1d>, 1918 <0 0x40000f20 0 0xa8>, 1919 <0 0x40001000 0 0x1000>, 1920 <0 0x40100000 0 0x100000>; 1921 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1922 device_type = "pci"; 1923 linux,pci-domain = <1>; 1924 bus-range = <0x00 0xff>; 1925 num-lanes = <2>; 1926 1927 #address-cells = <3>; 1928 #size-cells = <2>; 1929 1930 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1931 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1932 1933 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1934 interrupt-names = "msi"; 1935 #interrupt-cells = <1>; 1936 interrupt-map-mask = <0 0 0 0x7>; 1937 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1938 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1939 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1940 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1941 1942 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1943 <&gcc GCC_PCIE_1_AUX_CLK>, 1944 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1945 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1946 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1947 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1948 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1949 clock-names = "pipe", 1950 "aux", 1951 "cfg", 1952 "bus_master", 1953 "bus_slave", 1954 "slave_q2a", 1955 "tbu"; 1956 1957 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1958 assigned-clock-rates = <19200000>; 1959 1960 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1961 <0x100 &apps_smmu 0x1e01 0x1>; 1962 1963 resets = <&gcc GCC_PCIE_1_BCR>; 1964 reset-names = "pci"; 1965 1966 power-domains = <&gcc PCIE_1_GDSC>; 1967 1968 phys = <&pcie1_lane>; 1969 phy-names = "pciephy"; 1970 1971 perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; 1972 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 1973 1974 pinctrl-names = "default"; 1975 pinctrl-0 = <&pcie1_default_state>; 1976 1977 status = "disabled"; 1978 }; 1979 1980 pcie1_phy: phy@1c0e000 { 1981 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 1982 reg = <0 0x01c0e000 0 0x1c0>; 1983 #address-cells = <2>; 1984 #size-cells = <2>; 1985 ranges; 1986 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1987 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1988 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1989 clock-names = "aux", "cfg_ahb", "refgen"; 1990 1991 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1992 reset-names = "phy"; 1993 1994 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1995 assigned-clock-rates = <100000000>; 1996 1997 status = "disabled"; 1998 1999 pcie1_lane: phy@1c0e200 { 2000 reg = <0 0x01c0e200 0 0x170>, /* tx0 */ 2001 <0 0x01c0e400 0 0x200>, /* rx0 */ 2002 <0 0x01c0ea00 0 0x1f0>, /* pcs */ 2003 <0 0x01c0e600 0 0x170>, /* tx1 */ 2004 <0 0x01c0e800 0 0x200>, /* rx1 */ 2005 <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2006 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2007 clock-names = "pipe0"; 2008 2009 #phy-cells = <0>; 2010 clock-output-names = "pcie_1_pipe_clk"; 2011 }; 2012 }; 2013 2014 ufs_mem_hc: ufshc@1d84000 { 2015 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 2016 "jedec,ufs-2.0"; 2017 reg = <0 0x01d84000 0 0x2500>, 2018 <0 0x01d90000 0 0x8000>; 2019 reg-names = "std", "ice"; 2020 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2021 phys = <&ufs_mem_phy_lanes>; 2022 phy-names = "ufsphy"; 2023 lanes-per-direction = <2>; 2024 #reset-cells = <1>; 2025 resets = <&gcc GCC_UFS_PHY_BCR>; 2026 reset-names = "rst"; 2027 2028 iommus = <&apps_smmu 0x300 0>; 2029 2030 clock-names = 2031 "core_clk", 2032 "bus_aggr_clk", 2033 "iface_clk", 2034 "core_clk_unipro", 2035 "ref_clk", 2036 "tx_lane0_sync_clk", 2037 "rx_lane0_sync_clk", 2038 "rx_lane1_sync_clk", 2039 "ice_core_clk"; 2040 clocks = 2041 <&gcc GCC_UFS_PHY_AXI_CLK>, 2042 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2043 <&gcc GCC_UFS_PHY_AHB_CLK>, 2044 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2045 <&rpmhcc RPMH_CXO_CLK>, 2046 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2047 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2048 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2049 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2050 freq-table-hz = 2051 <37500000 300000000>, 2052 <0 0>, 2053 <0 0>, 2054 <37500000 300000000>, 2055 <0 0>, 2056 <0 0>, 2057 <0 0>, 2058 <0 0>, 2059 <0 300000000>; 2060 2061 status = "disabled"; 2062 }; 2063 2064 ufs_mem_phy: phy@1d87000 { 2065 compatible = "qcom,sm8150-qmp-ufs-phy"; 2066 reg = <0 0x01d87000 0 0x1c0>; 2067 #address-cells = <2>; 2068 #size-cells = <2>; 2069 ranges; 2070 clock-names = "ref", 2071 "ref_aux"; 2072 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2073 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2074 2075 power-domains = <&gcc UFS_PHY_GDSC>; 2076 2077 resets = <&ufs_mem_hc 0>; 2078 reset-names = "ufsphy"; 2079 status = "disabled"; 2080 2081 ufs_mem_phy_lanes: phy@1d87400 { 2082 reg = <0 0x01d87400 0 0x16c>, 2083 <0 0x01d87600 0 0x200>, 2084 <0 0x01d87c00 0 0x200>, 2085 <0 0x01d87800 0 0x16c>, 2086 <0 0x01d87a00 0 0x200>; 2087 #phy-cells = <0>; 2088 }; 2089 }; 2090 2091 tcsr_mutex: hwlock@1f40000 { 2092 compatible = "qcom,tcsr-mutex"; 2093 reg = <0x0 0x01f40000 0x0 0x20000>; 2094 #hwlock-cells = <1>; 2095 }; 2096 2097 tcsr_regs_1: syscon@1f60000 { 2098 compatible = "qcom,sm8150-tcsr", "syscon"; 2099 reg = <0x0 0x01f60000 0x0 0x20000>; 2100 }; 2101 2102 remoteproc_slpi: remoteproc@2400000 { 2103 compatible = "qcom,sm8150-slpi-pas"; 2104 reg = <0x0 0x02400000 0x0 0x4040>; 2105 2106 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 2107 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2108 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2109 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2110 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2111 interrupt-names = "wdog", "fatal", "ready", 2112 "handover", "stop-ack"; 2113 2114 clocks = <&rpmhcc RPMH_CXO_CLK>; 2115 clock-names = "xo"; 2116 2117 power-domains = <&rpmhpd SM8150_LCX>, 2118 <&rpmhpd SM8150_LMX>; 2119 power-domain-names = "lcx", "lmx"; 2120 2121 memory-region = <&slpi_mem>; 2122 2123 qcom,qmp = <&aoss_qmp>; 2124 2125 qcom,smem-states = <&slpi_smp2p_out 0>; 2126 qcom,smem-state-names = "stop"; 2127 2128 status = "disabled"; 2129 2130 glink-edge { 2131 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 2132 label = "dsps"; 2133 qcom,remote-pid = <3>; 2134 mboxes = <&apss_shared 24>; 2135 2136 fastrpc { 2137 compatible = "qcom,fastrpc"; 2138 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2139 label = "sdsp"; 2140 qcom,non-secure-domain; 2141 #address-cells = <1>; 2142 #size-cells = <0>; 2143 2144 compute-cb@1 { 2145 compatible = "qcom,fastrpc-compute-cb"; 2146 reg = <1>; 2147 iommus = <&apps_smmu 0x05a1 0x0>; 2148 }; 2149 2150 compute-cb@2 { 2151 compatible = "qcom,fastrpc-compute-cb"; 2152 reg = <2>; 2153 iommus = <&apps_smmu 0x05a2 0x0>; 2154 }; 2155 2156 compute-cb@3 { 2157 compatible = "qcom,fastrpc-compute-cb"; 2158 reg = <3>; 2159 iommus = <&apps_smmu 0x05a3 0x0>; 2160 /* note: shared-cb = <4> in downstream */ 2161 }; 2162 }; 2163 }; 2164 }; 2165 2166 gpu: gpu@2c00000 { 2167 compatible = "qcom,adreno-640.1", "qcom,adreno"; 2168 reg = <0 0x02c00000 0 0x40000>; 2169 reg-names = "kgsl_3d0_reg_memory"; 2170 2171 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2172 2173 iommus = <&adreno_smmu 0 0x401>; 2174 2175 operating-points-v2 = <&gpu_opp_table>; 2176 2177 qcom,gmu = <&gmu>; 2178 2179 nvmem-cells = <&gpu_speed_bin>; 2180 nvmem-cell-names = "speed_bin"; 2181 2182 status = "disabled"; 2183 2184 zap-shader { 2185 memory-region = <&gpu_mem>; 2186 }; 2187 2188 gpu_opp_table: opp-table { 2189 compatible = "operating-points-v2"; 2190 2191 opp-675000000 { 2192 opp-hz = /bits/ 64 <675000000>; 2193 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2194 opp-supported-hw = <0x2>; 2195 }; 2196 2197 opp-585000000 { 2198 opp-hz = /bits/ 64 <585000000>; 2199 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2200 opp-supported-hw = <0x3>; 2201 }; 2202 2203 opp-499200000 { 2204 opp-hz = /bits/ 64 <499200000>; 2205 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2206 opp-supported-hw = <0x3>; 2207 }; 2208 2209 opp-427000000 { 2210 opp-hz = /bits/ 64 <427000000>; 2211 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2212 opp-supported-hw = <0x3>; 2213 }; 2214 2215 opp-345000000 { 2216 opp-hz = /bits/ 64 <345000000>; 2217 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2218 opp-supported-hw = <0x3>; 2219 }; 2220 2221 opp-257000000 { 2222 opp-hz = /bits/ 64 <257000000>; 2223 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2224 opp-supported-hw = <0x3>; 2225 }; 2226 }; 2227 }; 2228 2229 gmu: gmu@2c6a000 { 2230 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2231 2232 reg = <0 0x02c6a000 0 0x30000>, 2233 <0 0x0b290000 0 0x10000>, 2234 <0 0x0b490000 0 0x10000>; 2235 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2236 2237 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2238 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2239 interrupt-names = "hfi", "gmu"; 2240 2241 clocks = <&gpucc GPU_CC_AHB_CLK>, 2242 <&gpucc GPU_CC_CX_GMU_CLK>, 2243 <&gpucc GPU_CC_CXO_CLK>, 2244 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2245 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2246 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2247 2248 power-domains = <&gpucc GPU_CX_GDSC>, 2249 <&gpucc GPU_GX_GDSC>; 2250 power-domain-names = "cx", "gx"; 2251 2252 iommus = <&adreno_smmu 5 0x400>; 2253 2254 operating-points-v2 = <&gmu_opp_table>; 2255 2256 status = "disabled"; 2257 2258 gmu_opp_table: opp-table { 2259 compatible = "operating-points-v2"; 2260 2261 opp-200000000 { 2262 opp-hz = /bits/ 64 <200000000>; 2263 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2264 }; 2265 }; 2266 }; 2267 2268 gpucc: clock-controller@2c90000 { 2269 compatible = "qcom,sm8150-gpucc"; 2270 reg = <0 0x02c90000 0 0x9000>; 2271 clocks = <&rpmhcc RPMH_CXO_CLK>, 2272 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2273 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2274 clock-names = "bi_tcxo", 2275 "gcc_gpu_gpll0_clk_src", 2276 "gcc_gpu_gpll0_div_clk_src"; 2277 #clock-cells = <1>; 2278 #reset-cells = <1>; 2279 #power-domain-cells = <1>; 2280 }; 2281 2282 adreno_smmu: iommu@2ca0000 { 2283 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", 2284 "qcom,smmu-500", "arm,mmu-500"; 2285 reg = <0 0x02ca0000 0 0x10000>; 2286 #iommu-cells = <2>; 2287 #global-interrupts = <1>; 2288 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2289 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2290 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2291 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2292 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2293 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2294 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2295 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2296 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2297 clocks = <&gpucc GPU_CC_AHB_CLK>, 2298 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2299 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2300 clock-names = "ahb", "bus", "iface"; 2301 2302 power-domains = <&gpucc GPU_CX_GDSC>; 2303 }; 2304 2305 tlmm: pinctrl@3100000 { 2306 compatible = "qcom,sm8150-pinctrl"; 2307 reg = <0x0 0x03100000 0x0 0x300000>, 2308 <0x0 0x03500000 0x0 0x300000>, 2309 <0x0 0x03900000 0x0 0x300000>, 2310 <0x0 0x03D00000 0x0 0x300000>; 2311 reg-names = "west", "east", "north", "south"; 2312 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2313 gpio-ranges = <&tlmm 0 0 176>; 2314 gpio-controller; 2315 #gpio-cells = <2>; 2316 interrupt-controller; 2317 #interrupt-cells = <2>; 2318 wakeup-parent = <&pdc>; 2319 2320 qup_i2c0_default: qup-i2c0-default-state { 2321 pins = "gpio0", "gpio1"; 2322 function = "qup0"; 2323 drive-strength = <0x02>; 2324 bias-disable; 2325 }; 2326 2327 qup_spi0_default: qup-spi0-default-state { 2328 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2329 function = "qup0"; 2330 drive-strength = <6>; 2331 bias-disable; 2332 }; 2333 2334 qup_i2c1_default: qup-i2c1-default-state { 2335 pins = "gpio114", "gpio115"; 2336 function = "qup1"; 2337 drive-strength = <2>; 2338 bias-disable; 2339 }; 2340 2341 qup_spi1_default: qup-spi1-default-state { 2342 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2343 function = "qup1"; 2344 drive-strength = <6>; 2345 bias-disable; 2346 }; 2347 2348 qup_i2c2_default: qup-i2c2-default-state { 2349 pins = "gpio126", "gpio127"; 2350 function = "qup2"; 2351 drive-strength = <2>; 2352 bias-disable; 2353 }; 2354 2355 qup_spi2_default: qup-spi2-default-state { 2356 pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2357 function = "qup2"; 2358 drive-strength = <6>; 2359 bias-disable; 2360 }; 2361 2362 qup_i2c3_default: qup-i2c3-default-state { 2363 pins = "gpio144", "gpio145"; 2364 function = "qup3"; 2365 drive-strength = <2>; 2366 bias-disable; 2367 }; 2368 2369 qup_spi3_default: qup-spi3-default-state { 2370 pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2371 function = "qup3"; 2372 drive-strength = <6>; 2373 bias-disable; 2374 }; 2375 2376 qup_i2c4_default: qup-i2c4-default-state { 2377 pins = "gpio51", "gpio52"; 2378 function = "qup4"; 2379 drive-strength = <2>; 2380 bias-disable; 2381 }; 2382 2383 qup_spi4_default: qup-spi4-default-state { 2384 pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2385 function = "qup4"; 2386 drive-strength = <6>; 2387 bias-disable; 2388 }; 2389 2390 qup_i2c5_default: qup-i2c5-default-state { 2391 pins = "gpio121", "gpio122"; 2392 function = "qup5"; 2393 drive-strength = <2>; 2394 bias-disable; 2395 }; 2396 2397 qup_spi5_default: qup-spi5-default-state { 2398 pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2399 function = "qup5"; 2400 drive-strength = <6>; 2401 bias-disable; 2402 }; 2403 2404 qup_i2c6_default: qup-i2c6-default-state { 2405 pins = "gpio6", "gpio7"; 2406 function = "qup6"; 2407 drive-strength = <2>; 2408 bias-disable; 2409 }; 2410 2411 qup_spi6_default: qup-spi6_default-state { 2412 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2413 function = "qup6"; 2414 drive-strength = <6>; 2415 bias-disable; 2416 }; 2417 2418 qup_i2c7_default: qup-i2c7-default-state { 2419 pins = "gpio98", "gpio99"; 2420 function = "qup7"; 2421 drive-strength = <2>; 2422 bias-disable; 2423 }; 2424 2425 qup_spi7_default: qup-spi7_default-state { 2426 pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2427 function = "qup7"; 2428 drive-strength = <6>; 2429 bias-disable; 2430 }; 2431 2432 qup_i2c8_default: qup-i2c8-default-state { 2433 pins = "gpio88", "gpio89"; 2434 function = "qup8"; 2435 drive-strength = <2>; 2436 bias-disable; 2437 }; 2438 2439 qup_spi8_default: qup-spi8-default-state { 2440 pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2441 function = "qup8"; 2442 drive-strength = <6>; 2443 bias-disable; 2444 }; 2445 2446 qup_i2c9_default: qup-i2c9-default-state { 2447 pins = "gpio39", "gpio40"; 2448 function = "qup9"; 2449 drive-strength = <2>; 2450 bias-disable; 2451 }; 2452 2453 qup_spi9_default: qup-spi9-default-state { 2454 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2455 function = "qup9"; 2456 drive-strength = <6>; 2457 bias-disable; 2458 }; 2459 2460 qup_uart9_default: qup-uart9-default-state { 2461 pins = "gpio41", "gpio42"; 2462 function = "qup9"; 2463 drive-strength = <2>; 2464 bias-disable; 2465 }; 2466 2467 qup_i2c10_default: qup-i2c10-default-state { 2468 pins = "gpio9", "gpio10"; 2469 function = "qup10"; 2470 drive-strength = <2>; 2471 bias-disable; 2472 }; 2473 2474 qup_spi10_default: qup-spi10-default-state { 2475 pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2476 function = "qup10"; 2477 drive-strength = <6>; 2478 bias-disable; 2479 }; 2480 2481 qup_i2c11_default: qup-i2c11-default-state { 2482 pins = "gpio94", "gpio95"; 2483 function = "qup11"; 2484 drive-strength = <2>; 2485 bias-disable; 2486 }; 2487 2488 qup_spi11_default: qup-spi11-default-state { 2489 pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2490 function = "qup11"; 2491 drive-strength = <6>; 2492 bias-disable; 2493 }; 2494 2495 qup_i2c12_default: qup-i2c12-default-state { 2496 pins = "gpio83", "gpio84"; 2497 function = "qup12"; 2498 drive-strength = <2>; 2499 bias-disable; 2500 }; 2501 2502 qup_spi12_default: qup-spi12-default-state { 2503 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2504 function = "qup12"; 2505 drive-strength = <6>; 2506 bias-disable; 2507 }; 2508 2509 qup_i2c13_default: qup-i2c13-default-state { 2510 pins = "gpio43", "gpio44"; 2511 function = "qup13"; 2512 drive-strength = <2>; 2513 bias-disable; 2514 }; 2515 2516 qup_spi13_default: qup-spi13-default-state { 2517 pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2518 function = "qup13"; 2519 drive-strength = <6>; 2520 bias-disable; 2521 }; 2522 2523 qup_i2c14_default: qup-i2c14-default-state { 2524 pins = "gpio47", "gpio48"; 2525 function = "qup14"; 2526 drive-strength = <2>; 2527 bias-disable; 2528 }; 2529 2530 qup_spi14_default: qup-spi14-default-state { 2531 pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2532 function = "qup14"; 2533 drive-strength = <6>; 2534 bias-disable; 2535 }; 2536 2537 qup_i2c15_default: qup-i2c15-default-state { 2538 pins = "gpio27", "gpio28"; 2539 function = "qup15"; 2540 drive-strength = <2>; 2541 bias-disable; 2542 }; 2543 2544 qup_spi15_default: qup-spi15-default-state { 2545 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2546 function = "qup15"; 2547 drive-strength = <6>; 2548 bias-disable; 2549 }; 2550 2551 qup_i2c16_default: qup-i2c16-default-state { 2552 pins = "gpio86", "gpio85"; 2553 function = "qup16"; 2554 drive-strength = <2>; 2555 bias-disable; 2556 }; 2557 2558 qup_spi16_default: qup-spi16-default-state { 2559 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2560 function = "qup16"; 2561 drive-strength = <6>; 2562 bias-disable; 2563 }; 2564 2565 qup_i2c17_default: qup-i2c17-default-state { 2566 pins = "gpio55", "gpio56"; 2567 function = "qup17"; 2568 drive-strength = <2>; 2569 bias-disable; 2570 }; 2571 2572 qup_spi17_default: qup-spi17-default-state { 2573 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2574 function = "qup17"; 2575 drive-strength = <6>; 2576 bias-disable; 2577 }; 2578 2579 qup_i2c18_default: qup-i2c18-default-state { 2580 pins = "gpio23", "gpio24"; 2581 function = "qup18"; 2582 drive-strength = <2>; 2583 bias-disable; 2584 }; 2585 2586 qup_spi18_default: qup-spi18-default-state { 2587 pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2588 function = "qup18"; 2589 drive-strength = <6>; 2590 bias-disable; 2591 }; 2592 2593 qup_i2c19_default: qup-i2c19-default-state { 2594 pins = "gpio57", "gpio58"; 2595 function = "qup19"; 2596 drive-strength = <2>; 2597 bias-disable; 2598 }; 2599 2600 qup_spi19_default: qup-spi19-default-state { 2601 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2602 function = "qup19"; 2603 drive-strength = <6>; 2604 bias-disable; 2605 }; 2606 2607 pcie0_default_state: pcie0-default-state { 2608 perst-pins { 2609 pins = "gpio35"; 2610 function = "gpio"; 2611 drive-strength = <2>; 2612 bias-pull-down; 2613 }; 2614 2615 clkreq-pins { 2616 pins = "gpio36"; 2617 function = "pci_e0"; 2618 drive-strength = <2>; 2619 bias-pull-up; 2620 }; 2621 2622 wake-pins { 2623 pins = "gpio37"; 2624 function = "gpio"; 2625 drive-strength = <2>; 2626 bias-pull-up; 2627 }; 2628 }; 2629 2630 pcie1_default_state: pcie1-default-state { 2631 perst-pins { 2632 pins = "gpio102"; 2633 function = "gpio"; 2634 drive-strength = <2>; 2635 bias-pull-down; 2636 }; 2637 2638 clkreq-pins { 2639 pins = "gpio103"; 2640 function = "pci_e1"; 2641 drive-strength = <2>; 2642 bias-pull-up; 2643 }; 2644 2645 wake-pins { 2646 pins = "gpio104"; 2647 function = "gpio"; 2648 drive-strength = <2>; 2649 bias-pull-up; 2650 }; 2651 }; 2652 }; 2653 2654 remoteproc_mpss: remoteproc@4080000 { 2655 compatible = "qcom,sm8150-mpss-pas"; 2656 reg = <0x0 0x04080000 0x0 0x4040>; 2657 2658 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2659 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2660 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2661 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2662 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2663 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2664 interrupt-names = "wdog", "fatal", "ready", "handover", 2665 "stop-ack", "shutdown-ack"; 2666 2667 clocks = <&rpmhcc RPMH_CXO_CLK>; 2668 clock-names = "xo"; 2669 2670 power-domains = <&rpmhpd SM8150_CX>, 2671 <&rpmhpd SM8150_MSS>; 2672 power-domain-names = "cx", "mss"; 2673 2674 memory-region = <&mpss_mem>; 2675 2676 qcom,qmp = <&aoss_qmp>; 2677 2678 qcom,smem-states = <&modem_smp2p_out 0>; 2679 qcom,smem-state-names = "stop"; 2680 2681 status = "disabled"; 2682 2683 glink-edge { 2684 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2685 label = "modem"; 2686 qcom,remote-pid = <1>; 2687 mboxes = <&apss_shared 12>; 2688 }; 2689 }; 2690 2691 stm@6002000 { 2692 compatible = "arm,coresight-stm", "arm,primecell"; 2693 reg = <0 0x06002000 0 0x1000>, 2694 <0 0x16280000 0 0x180000>; 2695 reg-names = "stm-base", "stm-stimulus-base"; 2696 2697 clocks = <&aoss_qmp>; 2698 clock-names = "apb_pclk"; 2699 2700 out-ports { 2701 port { 2702 stm_out: endpoint { 2703 remote-endpoint = <&funnel0_in7>; 2704 }; 2705 }; 2706 }; 2707 }; 2708 2709 funnel@6041000 { 2710 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2711 reg = <0 0x06041000 0 0x1000>; 2712 2713 clocks = <&aoss_qmp>; 2714 clock-names = "apb_pclk"; 2715 2716 out-ports { 2717 port { 2718 funnel0_out: endpoint { 2719 remote-endpoint = <&merge_funnel_in0>; 2720 }; 2721 }; 2722 }; 2723 2724 in-ports { 2725 #address-cells = <1>; 2726 #size-cells = <0>; 2727 2728 port@7 { 2729 reg = <7>; 2730 funnel0_in7: endpoint { 2731 remote-endpoint = <&stm_out>; 2732 }; 2733 }; 2734 }; 2735 }; 2736 2737 funnel@6042000 { 2738 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2739 reg = <0 0x06042000 0 0x1000>; 2740 2741 clocks = <&aoss_qmp>; 2742 clock-names = "apb_pclk"; 2743 2744 out-ports { 2745 port { 2746 funnel1_out: endpoint { 2747 remote-endpoint = <&merge_funnel_in1>; 2748 }; 2749 }; 2750 }; 2751 2752 in-ports { 2753 #address-cells = <1>; 2754 #size-cells = <0>; 2755 2756 port@4 { 2757 reg = <4>; 2758 funnel1_in4: endpoint { 2759 remote-endpoint = <&swao_replicator_out>; 2760 }; 2761 }; 2762 }; 2763 }; 2764 2765 funnel@6043000 { 2766 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2767 reg = <0 0x06043000 0 0x1000>; 2768 2769 clocks = <&aoss_qmp>; 2770 clock-names = "apb_pclk"; 2771 2772 out-ports { 2773 port { 2774 funnel2_out: endpoint { 2775 remote-endpoint = <&merge_funnel_in2>; 2776 }; 2777 }; 2778 }; 2779 2780 in-ports { 2781 #address-cells = <1>; 2782 #size-cells = <0>; 2783 2784 port@2 { 2785 reg = <2>; 2786 funnel2_in2: endpoint { 2787 remote-endpoint = <&apss_merge_funnel_out>; 2788 }; 2789 }; 2790 }; 2791 }; 2792 2793 funnel@6045000 { 2794 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2795 reg = <0 0x06045000 0 0x1000>; 2796 2797 clocks = <&aoss_qmp>; 2798 clock-names = "apb_pclk"; 2799 2800 out-ports { 2801 port { 2802 merge_funnel_out: endpoint { 2803 remote-endpoint = <&etf_in>; 2804 }; 2805 }; 2806 }; 2807 2808 in-ports { 2809 #address-cells = <1>; 2810 #size-cells = <0>; 2811 2812 port@0 { 2813 reg = <0>; 2814 merge_funnel_in0: endpoint { 2815 remote-endpoint = <&funnel0_out>; 2816 }; 2817 }; 2818 2819 port@1 { 2820 reg = <1>; 2821 merge_funnel_in1: endpoint { 2822 remote-endpoint = <&funnel1_out>; 2823 }; 2824 }; 2825 2826 port@2 { 2827 reg = <2>; 2828 merge_funnel_in2: endpoint { 2829 remote-endpoint = <&funnel2_out>; 2830 }; 2831 }; 2832 }; 2833 }; 2834 2835 replicator@6046000 { 2836 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2837 reg = <0 0x06046000 0 0x1000>; 2838 2839 clocks = <&aoss_qmp>; 2840 clock-names = "apb_pclk"; 2841 2842 out-ports { 2843 #address-cells = <1>; 2844 #size-cells = <0>; 2845 2846 port@0 { 2847 reg = <0>; 2848 replicator_out0: endpoint { 2849 remote-endpoint = <&etr_in>; 2850 }; 2851 }; 2852 2853 port@1 { 2854 reg = <1>; 2855 replicator_out1: endpoint { 2856 remote-endpoint = <&replicator1_in>; 2857 }; 2858 }; 2859 }; 2860 2861 in-ports { 2862 port { 2863 replicator_in0: endpoint { 2864 remote-endpoint = <&etf_out>; 2865 }; 2866 }; 2867 }; 2868 }; 2869 2870 etf@6047000 { 2871 compatible = "arm,coresight-tmc", "arm,primecell"; 2872 reg = <0 0x06047000 0 0x1000>; 2873 2874 clocks = <&aoss_qmp>; 2875 clock-names = "apb_pclk"; 2876 2877 out-ports { 2878 port { 2879 etf_out: endpoint { 2880 remote-endpoint = <&replicator_in0>; 2881 }; 2882 }; 2883 }; 2884 2885 in-ports { 2886 port { 2887 etf_in: endpoint { 2888 remote-endpoint = <&merge_funnel_out>; 2889 }; 2890 }; 2891 }; 2892 }; 2893 2894 etr@6048000 { 2895 compatible = "arm,coresight-tmc", "arm,primecell"; 2896 reg = <0 0x06048000 0 0x1000>; 2897 iommus = <&apps_smmu 0x05e0 0x0>; 2898 2899 clocks = <&aoss_qmp>; 2900 clock-names = "apb_pclk"; 2901 arm,scatter-gather; 2902 2903 in-ports { 2904 port { 2905 etr_in: endpoint { 2906 remote-endpoint = <&replicator_out0>; 2907 }; 2908 }; 2909 }; 2910 }; 2911 2912 replicator@604a000 { 2913 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2914 reg = <0 0x0604a000 0 0x1000>; 2915 2916 clocks = <&aoss_qmp>; 2917 clock-names = "apb_pclk"; 2918 2919 out-ports { 2920 #address-cells = <1>; 2921 #size-cells = <0>; 2922 2923 port@1 { 2924 reg = <1>; 2925 replicator1_out: endpoint { 2926 remote-endpoint = <&swao_funnel_in>; 2927 }; 2928 }; 2929 }; 2930 2931 in-ports { 2932 #address-cells = <1>; 2933 #size-cells = <0>; 2934 2935 port@1 { 2936 reg = <1>; 2937 replicator1_in: endpoint { 2938 remote-endpoint = <&replicator_out1>; 2939 }; 2940 }; 2941 }; 2942 }; 2943 2944 funnel@6b08000 { 2945 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2946 reg = <0 0x06b08000 0 0x1000>; 2947 2948 clocks = <&aoss_qmp>; 2949 clock-names = "apb_pclk"; 2950 2951 out-ports { 2952 port { 2953 swao_funnel_out: endpoint { 2954 remote-endpoint = <&swao_etf_in>; 2955 }; 2956 }; 2957 }; 2958 2959 in-ports { 2960 #address-cells = <1>; 2961 #size-cells = <0>; 2962 2963 port@6 { 2964 reg = <6>; 2965 swao_funnel_in: endpoint { 2966 remote-endpoint = <&replicator1_out>; 2967 }; 2968 }; 2969 }; 2970 }; 2971 2972 etf@6b09000 { 2973 compatible = "arm,coresight-tmc", "arm,primecell"; 2974 reg = <0 0x06b09000 0 0x1000>; 2975 2976 clocks = <&aoss_qmp>; 2977 clock-names = "apb_pclk"; 2978 2979 out-ports { 2980 port { 2981 swao_etf_out: endpoint { 2982 remote-endpoint = <&swao_replicator_in>; 2983 }; 2984 }; 2985 }; 2986 2987 in-ports { 2988 port { 2989 swao_etf_in: endpoint { 2990 remote-endpoint = <&swao_funnel_out>; 2991 }; 2992 }; 2993 }; 2994 }; 2995 2996 replicator@6b0a000 { 2997 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2998 reg = <0 0x06b0a000 0 0x1000>; 2999 3000 clocks = <&aoss_qmp>; 3001 clock-names = "apb_pclk"; 3002 qcom,replicator-loses-context; 3003 3004 out-ports { 3005 port { 3006 swao_replicator_out: endpoint { 3007 remote-endpoint = <&funnel1_in4>; 3008 }; 3009 }; 3010 }; 3011 3012 in-ports { 3013 port { 3014 swao_replicator_in: endpoint { 3015 remote-endpoint = <&swao_etf_out>; 3016 }; 3017 }; 3018 }; 3019 }; 3020 3021 etm@7040000 { 3022 compatible = "arm,coresight-etm4x", "arm,primecell"; 3023 reg = <0 0x07040000 0 0x1000>; 3024 3025 cpu = <&CPU0>; 3026 3027 clocks = <&aoss_qmp>; 3028 clock-names = "apb_pclk"; 3029 arm,coresight-loses-context-with-cpu; 3030 qcom,skip-power-up; 3031 3032 out-ports { 3033 port { 3034 etm0_out: endpoint { 3035 remote-endpoint = <&apss_funnel_in0>; 3036 }; 3037 }; 3038 }; 3039 }; 3040 3041 etm@7140000 { 3042 compatible = "arm,coresight-etm4x", "arm,primecell"; 3043 reg = <0 0x07140000 0 0x1000>; 3044 3045 cpu = <&CPU1>; 3046 3047 clocks = <&aoss_qmp>; 3048 clock-names = "apb_pclk"; 3049 arm,coresight-loses-context-with-cpu; 3050 qcom,skip-power-up; 3051 3052 out-ports { 3053 port { 3054 etm1_out: endpoint { 3055 remote-endpoint = <&apss_funnel_in1>; 3056 }; 3057 }; 3058 }; 3059 }; 3060 3061 etm@7240000 { 3062 compatible = "arm,coresight-etm4x", "arm,primecell"; 3063 reg = <0 0x07240000 0 0x1000>; 3064 3065 cpu = <&CPU2>; 3066 3067 clocks = <&aoss_qmp>; 3068 clock-names = "apb_pclk"; 3069 arm,coresight-loses-context-with-cpu; 3070 qcom,skip-power-up; 3071 3072 out-ports { 3073 port { 3074 etm2_out: endpoint { 3075 remote-endpoint = <&apss_funnel_in2>; 3076 }; 3077 }; 3078 }; 3079 }; 3080 3081 etm@7340000 { 3082 compatible = "arm,coresight-etm4x", "arm,primecell"; 3083 reg = <0 0x07340000 0 0x1000>; 3084 3085 cpu = <&CPU3>; 3086 3087 clocks = <&aoss_qmp>; 3088 clock-names = "apb_pclk"; 3089 arm,coresight-loses-context-with-cpu; 3090 qcom,skip-power-up; 3091 3092 out-ports { 3093 port { 3094 etm3_out: endpoint { 3095 remote-endpoint = <&apss_funnel_in3>; 3096 }; 3097 }; 3098 }; 3099 }; 3100 3101 etm@7440000 { 3102 compatible = "arm,coresight-etm4x", "arm,primecell"; 3103 reg = <0 0x07440000 0 0x1000>; 3104 3105 cpu = <&CPU4>; 3106 3107 clocks = <&aoss_qmp>; 3108 clock-names = "apb_pclk"; 3109 arm,coresight-loses-context-with-cpu; 3110 qcom,skip-power-up; 3111 3112 out-ports { 3113 port { 3114 etm4_out: endpoint { 3115 remote-endpoint = <&apss_funnel_in4>; 3116 }; 3117 }; 3118 }; 3119 }; 3120 3121 etm@7540000 { 3122 compatible = "arm,coresight-etm4x", "arm,primecell"; 3123 reg = <0 0x07540000 0 0x1000>; 3124 3125 cpu = <&CPU5>; 3126 3127 clocks = <&aoss_qmp>; 3128 clock-names = "apb_pclk"; 3129 arm,coresight-loses-context-with-cpu; 3130 qcom,skip-power-up; 3131 3132 out-ports { 3133 port { 3134 etm5_out: endpoint { 3135 remote-endpoint = <&apss_funnel_in5>; 3136 }; 3137 }; 3138 }; 3139 }; 3140 3141 etm@7640000 { 3142 compatible = "arm,coresight-etm4x", "arm,primecell"; 3143 reg = <0 0x07640000 0 0x1000>; 3144 3145 cpu = <&CPU6>; 3146 3147 clocks = <&aoss_qmp>; 3148 clock-names = "apb_pclk"; 3149 arm,coresight-loses-context-with-cpu; 3150 qcom,skip-power-up; 3151 3152 out-ports { 3153 port { 3154 etm6_out: endpoint { 3155 remote-endpoint = <&apss_funnel_in6>; 3156 }; 3157 }; 3158 }; 3159 }; 3160 3161 etm@7740000 { 3162 compatible = "arm,coresight-etm4x", "arm,primecell"; 3163 reg = <0 0x07740000 0 0x1000>; 3164 3165 cpu = <&CPU7>; 3166 3167 clocks = <&aoss_qmp>; 3168 clock-names = "apb_pclk"; 3169 arm,coresight-loses-context-with-cpu; 3170 qcom,skip-power-up; 3171 3172 out-ports { 3173 port { 3174 etm7_out: endpoint { 3175 remote-endpoint = <&apss_funnel_in7>; 3176 }; 3177 }; 3178 }; 3179 }; 3180 3181 funnel@7800000 { /* APSS Funnel */ 3182 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3183 reg = <0 0x07800000 0 0x1000>; 3184 3185 clocks = <&aoss_qmp>; 3186 clock-names = "apb_pclk"; 3187 3188 out-ports { 3189 port { 3190 apss_funnel_out: endpoint { 3191 remote-endpoint = <&apss_merge_funnel_in>; 3192 }; 3193 }; 3194 }; 3195 3196 in-ports { 3197 #address-cells = <1>; 3198 #size-cells = <0>; 3199 3200 port@0 { 3201 reg = <0>; 3202 apss_funnel_in0: endpoint { 3203 remote-endpoint = <&etm0_out>; 3204 }; 3205 }; 3206 3207 port@1 { 3208 reg = <1>; 3209 apss_funnel_in1: endpoint { 3210 remote-endpoint = <&etm1_out>; 3211 }; 3212 }; 3213 3214 port@2 { 3215 reg = <2>; 3216 apss_funnel_in2: endpoint { 3217 remote-endpoint = <&etm2_out>; 3218 }; 3219 }; 3220 3221 port@3 { 3222 reg = <3>; 3223 apss_funnel_in3: endpoint { 3224 remote-endpoint = <&etm3_out>; 3225 }; 3226 }; 3227 3228 port@4 { 3229 reg = <4>; 3230 apss_funnel_in4: endpoint { 3231 remote-endpoint = <&etm4_out>; 3232 }; 3233 }; 3234 3235 port@5 { 3236 reg = <5>; 3237 apss_funnel_in5: endpoint { 3238 remote-endpoint = <&etm5_out>; 3239 }; 3240 }; 3241 3242 port@6 { 3243 reg = <6>; 3244 apss_funnel_in6: endpoint { 3245 remote-endpoint = <&etm6_out>; 3246 }; 3247 }; 3248 3249 port@7 { 3250 reg = <7>; 3251 apss_funnel_in7: endpoint { 3252 remote-endpoint = <&etm7_out>; 3253 }; 3254 }; 3255 }; 3256 }; 3257 3258 funnel@7810000 { 3259 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3260 reg = <0 0x07810000 0 0x1000>; 3261 3262 clocks = <&aoss_qmp>; 3263 clock-names = "apb_pclk"; 3264 3265 out-ports { 3266 port { 3267 apss_merge_funnel_out: endpoint { 3268 remote-endpoint = <&funnel2_in2>; 3269 }; 3270 }; 3271 }; 3272 3273 in-ports { 3274 port { 3275 apss_merge_funnel_in: endpoint { 3276 remote-endpoint = <&apss_funnel_out>; 3277 }; 3278 }; 3279 }; 3280 }; 3281 3282 remoteproc_cdsp: remoteproc@8300000 { 3283 compatible = "qcom,sm8150-cdsp-pas"; 3284 reg = <0x0 0x08300000 0x0 0x4040>; 3285 3286 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3287 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3288 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3289 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3290 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3291 interrupt-names = "wdog", "fatal", "ready", 3292 "handover", "stop-ack"; 3293 3294 clocks = <&rpmhcc RPMH_CXO_CLK>; 3295 clock-names = "xo"; 3296 3297 power-domains = <&rpmhpd SM8150_CX>; 3298 3299 memory-region = <&cdsp_mem>; 3300 3301 qcom,qmp = <&aoss_qmp>; 3302 3303 qcom,smem-states = <&cdsp_smp2p_out 0>; 3304 qcom,smem-state-names = "stop"; 3305 3306 status = "disabled"; 3307 3308 glink-edge { 3309 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 3310 label = "cdsp"; 3311 qcom,remote-pid = <5>; 3312 mboxes = <&apss_shared 4>; 3313 3314 fastrpc { 3315 compatible = "qcom,fastrpc"; 3316 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3317 label = "cdsp"; 3318 qcom,non-secure-domain; 3319 #address-cells = <1>; 3320 #size-cells = <0>; 3321 3322 compute-cb@1 { 3323 compatible = "qcom,fastrpc-compute-cb"; 3324 reg = <1>; 3325 iommus = <&apps_smmu 0x1001 0x0460>; 3326 }; 3327 3328 compute-cb@2 { 3329 compatible = "qcom,fastrpc-compute-cb"; 3330 reg = <2>; 3331 iommus = <&apps_smmu 0x1002 0x0460>; 3332 }; 3333 3334 compute-cb@3 { 3335 compatible = "qcom,fastrpc-compute-cb"; 3336 reg = <3>; 3337 iommus = <&apps_smmu 0x1003 0x0460>; 3338 }; 3339 3340 compute-cb@4 { 3341 compatible = "qcom,fastrpc-compute-cb"; 3342 reg = <4>; 3343 iommus = <&apps_smmu 0x1004 0x0460>; 3344 }; 3345 3346 compute-cb@5 { 3347 compatible = "qcom,fastrpc-compute-cb"; 3348 reg = <5>; 3349 iommus = <&apps_smmu 0x1005 0x0460>; 3350 }; 3351 3352 compute-cb@6 { 3353 compatible = "qcom,fastrpc-compute-cb"; 3354 reg = <6>; 3355 iommus = <&apps_smmu 0x1006 0x0460>; 3356 }; 3357 3358 compute-cb@7 { 3359 compatible = "qcom,fastrpc-compute-cb"; 3360 reg = <7>; 3361 iommus = <&apps_smmu 0x1007 0x0460>; 3362 }; 3363 3364 compute-cb@8 { 3365 compatible = "qcom,fastrpc-compute-cb"; 3366 reg = <8>; 3367 iommus = <&apps_smmu 0x1008 0x0460>; 3368 }; 3369 3370 /* note: secure cb9 in downstream */ 3371 }; 3372 }; 3373 }; 3374 3375 usb_1_hsphy: phy@88e2000 { 3376 compatible = "qcom,sm8150-usb-hs-phy", 3377 "qcom,usb-snps-hs-7nm-phy"; 3378 reg = <0 0x088e2000 0 0x400>; 3379 status = "disabled"; 3380 #phy-cells = <0>; 3381 3382 clocks = <&rpmhcc RPMH_CXO_CLK>; 3383 clock-names = "ref"; 3384 3385 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3386 }; 3387 3388 usb_2_hsphy: phy@88e3000 { 3389 compatible = "qcom,sm8150-usb-hs-phy", 3390 "qcom,usb-snps-hs-7nm-phy"; 3391 reg = <0 0x088e3000 0 0x400>; 3392 status = "disabled"; 3393 #phy-cells = <0>; 3394 3395 clocks = <&rpmhcc RPMH_CXO_CLK>; 3396 clock-names = "ref"; 3397 3398 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3399 }; 3400 3401 usb_1_qmpphy: phy@88e9000 { 3402 compatible = "qcom,sm8150-qmp-usb3-phy"; 3403 reg = <0 0x088e9000 0 0x18c>, 3404 <0 0x088e8000 0 0x10>; 3405 status = "disabled"; 3406 #address-cells = <2>; 3407 #size-cells = <2>; 3408 ranges; 3409 3410 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3411 <&rpmhcc RPMH_CXO_CLK>, 3412 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3413 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3414 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3415 3416 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3417 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3418 reset-names = "phy", "common"; 3419 3420 usb_1_ssphy: phy@88e9200 { 3421 reg = <0 0x088e9200 0 0x200>, 3422 <0 0x088e9400 0 0x200>, 3423 <0 0x088e9c00 0 0x218>, 3424 <0 0x088e9600 0 0x200>, 3425 <0 0x088e9800 0 0x200>, 3426 <0 0x088e9a00 0 0x100>; 3427 #clock-cells = <0>; 3428 #phy-cells = <0>; 3429 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3430 clock-names = "pipe0"; 3431 clock-output-names = "usb3_phy_pipe_clk_src"; 3432 }; 3433 }; 3434 3435 usb_2_qmpphy: phy@88eb000 { 3436 compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 3437 reg = <0 0x088eb000 0 0x200>; 3438 status = "disabled"; 3439 #address-cells = <2>; 3440 #size-cells = <2>; 3441 ranges; 3442 3443 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3444 <&rpmhcc RPMH_CXO_CLK>, 3445 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3446 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3447 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3448 3449 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3450 <&gcc GCC_USB3_PHY_SEC_BCR>; 3451 reset-names = "phy", "common"; 3452 3453 usb_2_ssphy: phy@88eb200 { 3454 reg = <0 0x088eb200 0 0x200>, 3455 <0 0x088eb400 0 0x200>, 3456 <0 0x088eb800 0 0x800>, 3457 <0 0x088eb600 0 0x200>; 3458 #clock-cells = <0>; 3459 #phy-cells = <0>; 3460 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3461 clock-names = "pipe0"; 3462 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3463 }; 3464 }; 3465 3466 sdhc_2: mmc@8804000 { 3467 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3468 reg = <0 0x08804000 0 0x1000>; 3469 3470 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3471 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3472 interrupt-names = "hc_irq", "pwr_irq"; 3473 3474 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3475 <&gcc GCC_SDCC2_APPS_CLK>, 3476 <&rpmhcc RPMH_CXO_CLK>; 3477 clock-names = "iface", "core", "xo"; 3478 iommus = <&apps_smmu 0x6a0 0x0>; 3479 qcom,dll-config = <0x0007642c>; 3480 qcom,ddr-config = <0x80040868>; 3481 power-domains = <&rpmhpd 0>; 3482 operating-points-v2 = <&sdhc2_opp_table>; 3483 3484 status = "disabled"; 3485 3486 sdhc2_opp_table: opp-table { 3487 compatible = "operating-points-v2"; 3488 3489 opp-19200000 { 3490 opp-hz = /bits/ 64 <19200000>; 3491 required-opps = <&rpmhpd_opp_min_svs>; 3492 }; 3493 3494 opp-50000000 { 3495 opp-hz = /bits/ 64 <50000000>; 3496 required-opps = <&rpmhpd_opp_low_svs>; 3497 }; 3498 3499 opp-100000000 { 3500 opp-hz = /bits/ 64 <100000000>; 3501 required-opps = <&rpmhpd_opp_svs>; 3502 }; 3503 3504 opp-202000000 { 3505 opp-hz = /bits/ 64 <202000000>; 3506 required-opps = <&rpmhpd_opp_svs_l1>; 3507 }; 3508 }; 3509 }; 3510 3511 dc_noc: interconnect@9160000 { 3512 compatible = "qcom,sm8150-dc-noc"; 3513 reg = <0 0x09160000 0 0x3200>; 3514 #interconnect-cells = <1>; 3515 qcom,bcm-voters = <&apps_bcm_voter>; 3516 }; 3517 3518 gem_noc: interconnect@9680000 { 3519 compatible = "qcom,sm8150-gem-noc"; 3520 reg = <0 0x09680000 0 0x3e200>; 3521 #interconnect-cells = <1>; 3522 qcom,bcm-voters = <&apps_bcm_voter>; 3523 }; 3524 3525 usb_1: usb@a6f8800 { 3526 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3527 reg = <0 0x0a6f8800 0 0x400>; 3528 status = "disabled"; 3529 #address-cells = <2>; 3530 #size-cells = <2>; 3531 ranges; 3532 dma-ranges; 3533 3534 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3535 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3536 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3537 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3538 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3539 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3540 clock-names = "cfg_noc", 3541 "core", 3542 "iface", 3543 "sleep", 3544 "mock_utmi", 3545 "xo"; 3546 3547 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3548 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3549 assigned-clock-rates = <19200000>, <200000000>; 3550 3551 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3552 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3553 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3554 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3555 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3556 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3557 3558 power-domains = <&gcc USB30_PRIM_GDSC>; 3559 3560 resets = <&gcc GCC_USB30_PRIM_BCR>; 3561 3562 usb_1_dwc3: usb@a600000 { 3563 compatible = "snps,dwc3"; 3564 reg = <0 0x0a600000 0 0xcd00>; 3565 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3566 iommus = <&apps_smmu 0x140 0>; 3567 snps,dis_u2_susphy_quirk; 3568 snps,dis_enblslpm_quirk; 3569 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3570 phy-names = "usb2-phy", "usb3-phy"; 3571 }; 3572 }; 3573 3574 usb_2: usb@a8f8800 { 3575 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3576 reg = <0 0x0a8f8800 0 0x400>; 3577 status = "disabled"; 3578 #address-cells = <2>; 3579 #size-cells = <2>; 3580 ranges; 3581 dma-ranges; 3582 3583 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3584 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3585 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3586 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3587 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3588 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3589 clock-names = "cfg_noc", 3590 "core", 3591 "iface", 3592 "sleep", 3593 "mock_utmi", 3594 "xo"; 3595 3596 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3597 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3598 assigned-clock-rates = <19200000>, <200000000>; 3599 3600 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3601 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 3602 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3603 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 3604 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3605 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3606 3607 power-domains = <&gcc USB30_SEC_GDSC>; 3608 3609 resets = <&gcc GCC_USB30_SEC_BCR>; 3610 3611 usb_2_dwc3: usb@a800000 { 3612 compatible = "snps,dwc3"; 3613 reg = <0 0x0a800000 0 0xcd00>; 3614 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3615 iommus = <&apps_smmu 0x160 0>; 3616 snps,dis_u2_susphy_quirk; 3617 snps,dis_enblslpm_quirk; 3618 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3619 phy-names = "usb2-phy", "usb3-phy"; 3620 }; 3621 }; 3622 3623 camnoc_virt: interconnect@ac00000 { 3624 compatible = "qcom,sm8150-camnoc-virt"; 3625 reg = <0 0x0ac00000 0 0x1000>; 3626 #interconnect-cells = <1>; 3627 qcom,bcm-voters = <&apps_bcm_voter>; 3628 }; 3629 3630 mdss: display-subsystem@ae00000 { 3631 compatible = "qcom,sm8150-mdss"; 3632 reg = <0 0x0ae00000 0 0x1000>; 3633 reg-names = "mdss"; 3634 3635 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 3636 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 3637 interconnect-names = "mdp0-mem", "mdp1-mem"; 3638 3639 power-domains = <&dispcc MDSS_GDSC>; 3640 3641 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3642 <&gcc GCC_DISP_HF_AXI_CLK>, 3643 <&gcc GCC_DISP_SF_AXI_CLK>, 3644 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3645 clock-names = "iface", "bus", "nrt_bus", "core"; 3646 3647 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3648 interrupt-controller; 3649 #interrupt-cells = <1>; 3650 3651 iommus = <&apps_smmu 0x800 0x420>; 3652 3653 status = "disabled"; 3654 3655 #address-cells = <2>; 3656 #size-cells = <2>; 3657 ranges; 3658 3659 mdss_mdp: display-controller@ae01000 { 3660 compatible = "qcom,sm8150-dpu"; 3661 reg = <0 0x0ae01000 0 0x8f000>, 3662 <0 0x0aeb0000 0 0x2008>; 3663 reg-names = "mdp", "vbif"; 3664 3665 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3666 <&gcc GCC_DISP_HF_AXI_CLK>, 3667 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3668 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3669 clock-names = "iface", "bus", "core", "vsync"; 3670 3671 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3672 assigned-clock-rates = <19200000>; 3673 3674 operating-points-v2 = <&mdp_opp_table>; 3675 power-domains = <&rpmhpd SM8150_MMCX>; 3676 3677 interrupt-parent = <&mdss>; 3678 interrupts = <0>; 3679 3680 ports { 3681 #address-cells = <1>; 3682 #size-cells = <0>; 3683 3684 port@0 { 3685 reg = <0>; 3686 dpu_intf1_out: endpoint { 3687 remote-endpoint = <&mdss_dsi0_in>; 3688 }; 3689 }; 3690 3691 port@1 { 3692 reg = <1>; 3693 dpu_intf2_out: endpoint { 3694 remote-endpoint = <&mdss_dsi1_in>; 3695 }; 3696 }; 3697 }; 3698 3699 mdp_opp_table: opp-table { 3700 compatible = "operating-points-v2"; 3701 3702 opp-171428571 { 3703 opp-hz = /bits/ 64 <171428571>; 3704 required-opps = <&rpmhpd_opp_low_svs>; 3705 }; 3706 3707 opp-300000000 { 3708 opp-hz = /bits/ 64 <300000000>; 3709 required-opps = <&rpmhpd_opp_svs>; 3710 }; 3711 3712 opp-345000000 { 3713 opp-hz = /bits/ 64 <345000000>; 3714 required-opps = <&rpmhpd_opp_svs_l1>; 3715 }; 3716 3717 opp-460000000 { 3718 opp-hz = /bits/ 64 <460000000>; 3719 required-opps = <&rpmhpd_opp_nom>; 3720 }; 3721 }; 3722 }; 3723 3724 mdss_dsi0: dsi@ae94000 { 3725 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3726 reg = <0 0x0ae94000 0 0x400>; 3727 reg-names = "dsi_ctrl"; 3728 3729 interrupt-parent = <&mdss>; 3730 interrupts = <4>; 3731 3732 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3733 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3734 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3735 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3736 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3737 <&gcc GCC_DISP_HF_AXI_CLK>; 3738 clock-names = "byte", 3739 "byte_intf", 3740 "pixel", 3741 "core", 3742 "iface", 3743 "bus"; 3744 3745 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3746 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3747 assigned-clock-parents = <&mdss_dsi0_phy 0>, 3748 <&mdss_dsi0_phy 1>; 3749 3750 operating-points-v2 = <&dsi_opp_table>; 3751 power-domains = <&rpmhpd SM8150_MMCX>; 3752 3753 phys = <&mdss_dsi0_phy>; 3754 3755 status = "disabled"; 3756 3757 #address-cells = <1>; 3758 #size-cells = <0>; 3759 3760 ports { 3761 #address-cells = <1>; 3762 #size-cells = <0>; 3763 3764 port@0 { 3765 reg = <0>; 3766 mdss_dsi0_in: endpoint { 3767 remote-endpoint = <&dpu_intf1_out>; 3768 }; 3769 }; 3770 3771 port@1 { 3772 reg = <1>; 3773 mdss_dsi0_out: endpoint { 3774 }; 3775 }; 3776 }; 3777 3778 dsi_opp_table: opp-table { 3779 compatible = "operating-points-v2"; 3780 3781 opp-187500000 { 3782 opp-hz = /bits/ 64 <187500000>; 3783 required-opps = <&rpmhpd_opp_low_svs>; 3784 }; 3785 3786 opp-300000000 { 3787 opp-hz = /bits/ 64 <300000000>; 3788 required-opps = <&rpmhpd_opp_svs>; 3789 }; 3790 3791 opp-358000000 { 3792 opp-hz = /bits/ 64 <358000000>; 3793 required-opps = <&rpmhpd_opp_svs_l1>; 3794 }; 3795 }; 3796 }; 3797 3798 mdss_dsi0_phy: phy@ae94400 { 3799 compatible = "qcom,dsi-phy-7nm"; 3800 reg = <0 0x0ae94400 0 0x200>, 3801 <0 0x0ae94600 0 0x280>, 3802 <0 0x0ae94900 0 0x260>; 3803 reg-names = "dsi_phy", 3804 "dsi_phy_lane", 3805 "dsi_pll"; 3806 3807 #clock-cells = <1>; 3808 #phy-cells = <0>; 3809 3810 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3811 <&rpmhcc RPMH_CXO_CLK>; 3812 clock-names = "iface", "ref"; 3813 3814 status = "disabled"; 3815 }; 3816 3817 mdss_dsi1: dsi@ae96000 { 3818 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3819 reg = <0 0x0ae96000 0 0x400>; 3820 reg-names = "dsi_ctrl"; 3821 3822 interrupt-parent = <&mdss>; 3823 interrupts = <5>; 3824 3825 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3826 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3827 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3828 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3829 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3830 <&gcc GCC_DISP_HF_AXI_CLK>; 3831 clock-names = "byte", 3832 "byte_intf", 3833 "pixel", 3834 "core", 3835 "iface", 3836 "bus"; 3837 3838 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3839 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3840 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3841 <&mdss_dsi1_phy 1>; 3842 3843 operating-points-v2 = <&dsi_opp_table>; 3844 power-domains = <&rpmhpd SM8150_MMCX>; 3845 3846 phys = <&mdss_dsi1_phy>; 3847 3848 status = "disabled"; 3849 3850 #address-cells = <1>; 3851 #size-cells = <0>; 3852 3853 ports { 3854 #address-cells = <1>; 3855 #size-cells = <0>; 3856 3857 port@0 { 3858 reg = <0>; 3859 mdss_dsi1_in: endpoint { 3860 remote-endpoint = <&dpu_intf2_out>; 3861 }; 3862 }; 3863 3864 port@1 { 3865 reg = <1>; 3866 mdss_dsi1_out: endpoint { 3867 }; 3868 }; 3869 }; 3870 }; 3871 3872 mdss_dsi1_phy: phy@ae96400 { 3873 compatible = "qcom,dsi-phy-7nm"; 3874 reg = <0 0x0ae96400 0 0x200>, 3875 <0 0x0ae96600 0 0x280>, 3876 <0 0x0ae96900 0 0x260>; 3877 reg-names = "dsi_phy", 3878 "dsi_phy_lane", 3879 "dsi_pll"; 3880 3881 #clock-cells = <1>; 3882 #phy-cells = <0>; 3883 3884 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3885 <&rpmhcc RPMH_CXO_CLK>; 3886 clock-names = "iface", "ref"; 3887 3888 status = "disabled"; 3889 }; 3890 }; 3891 3892 dispcc: clock-controller@af00000 { 3893 compatible = "qcom,sm8150-dispcc"; 3894 reg = <0 0x0af00000 0 0x10000>; 3895 clocks = <&rpmhcc RPMH_CXO_CLK>, 3896 <&mdss_dsi0_phy 0>, 3897 <&mdss_dsi0_phy 1>, 3898 <&mdss_dsi1_phy 0>, 3899 <&mdss_dsi1_phy 1>, 3900 <0>, 3901 <0>; 3902 clock-names = "bi_tcxo", 3903 "dsi0_phy_pll_out_byteclk", 3904 "dsi0_phy_pll_out_dsiclk", 3905 "dsi1_phy_pll_out_byteclk", 3906 "dsi1_phy_pll_out_dsiclk", 3907 "dp_phy_pll_link_clk", 3908 "dp_phy_pll_vco_div_clk"; 3909 power-domains = <&rpmhpd SM8150_MMCX>; 3910 #clock-cells = <1>; 3911 #reset-cells = <1>; 3912 #power-domain-cells = <1>; 3913 }; 3914 3915 pdc: interrupt-controller@b220000 { 3916 compatible = "qcom,sm8150-pdc", "qcom,pdc"; 3917 reg = <0 0x0b220000 0 0x400>; 3918 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3919 <125 63 1>; 3920 #interrupt-cells = <2>; 3921 interrupt-parent = <&intc>; 3922 interrupt-controller; 3923 }; 3924 3925 aoss_qmp: power-management@c300000 { 3926 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 3927 reg = <0x0 0x0c300000 0x0 0x400>; 3928 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3929 mboxes = <&apss_shared 0>; 3930 3931 #clock-cells = <0>; 3932 }; 3933 3934 sram@c3f0000 { 3935 compatible = "qcom,rpmh-stats"; 3936 reg = <0 0x0c3f0000 0 0x400>; 3937 }; 3938 3939 tsens0: thermal-sensor@c263000 { 3940 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3941 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3942 <0 0x0c222000 0 0x1ff>; /* SROT */ 3943 #qcom,sensors = <16>; 3944 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3945 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3946 interrupt-names = "uplow", "critical"; 3947 #thermal-sensor-cells = <1>; 3948 }; 3949 3950 tsens1: thermal-sensor@c265000 { 3951 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3952 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3953 <0 0x0c223000 0 0x1ff>; /* SROT */ 3954 #qcom,sensors = <8>; 3955 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3956 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3957 interrupt-names = "uplow", "critical"; 3958 #thermal-sensor-cells = <1>; 3959 }; 3960 3961 spmi_bus: spmi@c440000 { 3962 compatible = "qcom,spmi-pmic-arb"; 3963 reg = <0x0 0x0c440000 0x0 0x0001100>, 3964 <0x0 0x0c600000 0x0 0x2000000>, 3965 <0x0 0x0e600000 0x0 0x0100000>, 3966 <0x0 0x0e700000 0x0 0x00a0000>, 3967 <0x0 0x0c40a000 0x0 0x0026000>; 3968 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3969 interrupt-names = "periph_irq"; 3970 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3971 qcom,ee = <0>; 3972 qcom,channel = <0>; 3973 #address-cells = <2>; 3974 #size-cells = <0>; 3975 interrupt-controller; 3976 #interrupt-cells = <4>; 3977 }; 3978 3979 apps_smmu: iommu@15000000 { 3980 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 3981 reg = <0 0x15000000 0 0x100000>; 3982 #iommu-cells = <2>; 3983 #global-interrupts = <1>; 3984 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3985 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3986 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3987 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3988 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3989 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3990 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3991 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3992 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3993 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3994 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3995 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3996 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3997 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3998 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3999 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4000 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4001 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4002 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4003 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4004 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4005 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4006 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4007 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4008 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4009 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4010 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4011 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4012 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4013 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4014 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4015 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4016 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4017 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4018 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4019 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4020 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4021 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4022 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4023 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4024 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4025 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4026 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4027 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4028 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4029 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4030 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4031 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4032 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4033 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4034 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4035 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4036 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4037 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4038 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4039 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4040 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4041 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4042 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4043 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4044 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4045 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4046 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4047 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4048 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4049 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4050 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4051 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4052 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4053 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4054 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4055 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4056 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4057 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4058 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4059 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4060 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4061 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4062 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4063 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4064 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 4065 }; 4066 4067 remoteproc_adsp: remoteproc@17300000 { 4068 compatible = "qcom,sm8150-adsp-pas"; 4069 reg = <0x0 0x17300000 0x0 0x4040>; 4070 4071 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 4072 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4073 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4074 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4075 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 4076 interrupt-names = "wdog", "fatal", "ready", 4077 "handover", "stop-ack"; 4078 4079 clocks = <&rpmhcc RPMH_CXO_CLK>; 4080 clock-names = "xo"; 4081 4082 power-domains = <&rpmhpd SM8150_CX>; 4083 4084 memory-region = <&adsp_mem>; 4085 4086 qcom,qmp = <&aoss_qmp>; 4087 4088 qcom,smem-states = <&adsp_smp2p_out 0>; 4089 qcom,smem-state-names = "stop"; 4090 4091 status = "disabled"; 4092 4093 glink-edge { 4094 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 4095 label = "lpass"; 4096 qcom,remote-pid = <2>; 4097 mboxes = <&apss_shared 8>; 4098 4099 fastrpc { 4100 compatible = "qcom,fastrpc"; 4101 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4102 label = "adsp"; 4103 qcom,non-secure-domain; 4104 #address-cells = <1>; 4105 #size-cells = <0>; 4106 4107 compute-cb@3 { 4108 compatible = "qcom,fastrpc-compute-cb"; 4109 reg = <3>; 4110 iommus = <&apps_smmu 0x1b23 0x0>; 4111 }; 4112 4113 compute-cb@4 { 4114 compatible = "qcom,fastrpc-compute-cb"; 4115 reg = <4>; 4116 iommus = <&apps_smmu 0x1b24 0x0>; 4117 }; 4118 4119 compute-cb@5 { 4120 compatible = "qcom,fastrpc-compute-cb"; 4121 reg = <5>; 4122 iommus = <&apps_smmu 0x1b25 0x0>; 4123 }; 4124 }; 4125 }; 4126 }; 4127 4128 intc: interrupt-controller@17a00000 { 4129 compatible = "arm,gic-v3"; 4130 interrupt-controller; 4131 #interrupt-cells = <3>; 4132 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4133 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4134 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4135 }; 4136 4137 apss_shared: mailbox@17c00000 { 4138 compatible = "qcom,sm8150-apss-shared", 4139 "qcom,sdm845-apss-shared"; 4140 reg = <0x0 0x17c00000 0x0 0x1000>; 4141 #mbox-cells = <1>; 4142 }; 4143 4144 watchdog@17c10000 { 4145 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 4146 reg = <0 0x17c10000 0 0x1000>; 4147 clocks = <&sleep_clk>; 4148 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4149 }; 4150 4151 timer@17c20000 { 4152 #address-cells = <1>; 4153 #size-cells = <1>; 4154 ranges = <0 0 0 0x20000000>; 4155 compatible = "arm,armv7-timer-mem"; 4156 reg = <0x0 0x17c20000 0x0 0x1000>; 4157 clock-frequency = <19200000>; 4158 4159 frame@17c21000 { 4160 frame-number = <0>; 4161 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4162 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4163 reg = <0x17c21000 0x1000>, 4164 <0x17c22000 0x1000>; 4165 }; 4166 4167 frame@17c23000 { 4168 frame-number = <1>; 4169 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4170 reg = <0x17c23000 0x1000>; 4171 status = "disabled"; 4172 }; 4173 4174 frame@17c25000 { 4175 frame-number = <2>; 4176 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4177 reg = <0x17c25000 0x1000>; 4178 status = "disabled"; 4179 }; 4180 4181 frame@17c27000 { 4182 frame-number = <3>; 4183 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4184 reg = <0x17c26000 0x1000>; 4185 status = "disabled"; 4186 }; 4187 4188 frame@17c29000 { 4189 frame-number = <4>; 4190 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4191 reg = <0x17c29000 0x1000>; 4192 status = "disabled"; 4193 }; 4194 4195 frame@17c2b000 { 4196 frame-number = <5>; 4197 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4198 reg = <0x17c2b000 0x1000>; 4199 status = "disabled"; 4200 }; 4201 4202 frame@17c2d000 { 4203 frame-number = <6>; 4204 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4205 reg = <0x17c2d000 0x1000>; 4206 status = "disabled"; 4207 }; 4208 }; 4209 4210 apps_rsc: rsc@18200000 { 4211 label = "apps_rsc"; 4212 compatible = "qcom,rpmh-rsc"; 4213 reg = <0x0 0x18200000 0x0 0x10000>, 4214 <0x0 0x18210000 0x0 0x10000>, 4215 <0x0 0x18220000 0x0 0x10000>; 4216 reg-names = "drv-0", "drv-1", "drv-2"; 4217 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4218 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4219 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4220 qcom,tcs-offset = <0xd00>; 4221 qcom,drv-id = <2>; 4222 qcom,tcs-config = <ACTIVE_TCS 2>, 4223 <SLEEP_TCS 3>, 4224 <WAKE_TCS 3>, 4225 <CONTROL_TCS 1>; 4226 power-domains = <&CLUSTER_PD>; 4227 4228 rpmhcc: clock-controller { 4229 compatible = "qcom,sm8150-rpmh-clk"; 4230 #clock-cells = <1>; 4231 clock-names = "xo"; 4232 clocks = <&xo_board>; 4233 }; 4234 4235 rpmhpd: power-controller { 4236 compatible = "qcom,sm8150-rpmhpd"; 4237 #power-domain-cells = <1>; 4238 operating-points-v2 = <&rpmhpd_opp_table>; 4239 4240 rpmhpd_opp_table: opp-table { 4241 compatible = "operating-points-v2"; 4242 4243 rpmhpd_opp_ret: opp1 { 4244 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4245 }; 4246 4247 rpmhpd_opp_min_svs: opp2 { 4248 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4249 }; 4250 4251 rpmhpd_opp_low_svs: opp3 { 4252 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4253 }; 4254 4255 rpmhpd_opp_svs: opp4 { 4256 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4257 }; 4258 4259 rpmhpd_opp_svs_l1: opp5 { 4260 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4261 }; 4262 4263 rpmhpd_opp_svs_l2: opp6 { 4264 opp-level = <224>; 4265 }; 4266 4267 rpmhpd_opp_nom: opp7 { 4268 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4269 }; 4270 4271 rpmhpd_opp_nom_l1: opp8 { 4272 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4273 }; 4274 4275 rpmhpd_opp_nom_l2: opp9 { 4276 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4277 }; 4278 4279 rpmhpd_opp_turbo: opp10 { 4280 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4281 }; 4282 4283 rpmhpd_opp_turbo_l1: opp11 { 4284 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4285 }; 4286 }; 4287 }; 4288 4289 apps_bcm_voter: bcm-voter { 4290 compatible = "qcom,bcm-voter"; 4291 }; 4292 }; 4293 4294 osm_l3: interconnect@18321000 { 4295 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4296 reg = <0 0x18321000 0 0x1400>; 4297 4298 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4299 clock-names = "xo", "alternate"; 4300 4301 #interconnect-cells = <1>; 4302 }; 4303 4304 cpufreq_hw: cpufreq@18323000 { 4305 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw"; 4306 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 4307 <0 0x18327800 0 0x1400>; 4308 reg-names = "freq-domain0", "freq-domain1", 4309 "freq-domain2"; 4310 4311 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4312 clock-names = "xo", "alternate"; 4313 4314 #freq-domain-cells = <1>; 4315 #clock-cells = <1>; 4316 }; 4317 4318 lmh_cluster1: lmh@18350800 { 4319 compatible = "qcom,sm8150-lmh"; 4320 reg = <0 0x18350800 0 0x400>; 4321 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 4322 cpus = <&CPU4>; 4323 qcom,lmh-temp-arm-millicelsius = <60000>; 4324 qcom,lmh-temp-low-millicelsius = <84500>; 4325 qcom,lmh-temp-high-millicelsius = <85000>; 4326 interrupt-controller; 4327 #interrupt-cells = <1>; 4328 }; 4329 4330 lmh_cluster0: lmh@18358800 { 4331 compatible = "qcom,sm8150-lmh"; 4332 reg = <0 0x18358800 0 0x400>; 4333 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4334 cpus = <&CPU0>; 4335 qcom,lmh-temp-arm-millicelsius = <60000>; 4336 qcom,lmh-temp-low-millicelsius = <84500>; 4337 qcom,lmh-temp-high-millicelsius = <85000>; 4338 interrupt-controller; 4339 #interrupt-cells = <1>; 4340 }; 4341 4342 wifi: wifi@18800000 { 4343 compatible = "qcom,wcn3990-wifi"; 4344 reg = <0 0x18800000 0 0x800000>; 4345 reg-names = "membase"; 4346 memory-region = <&wlan_mem>; 4347 clock-names = "cxo_ref_clk_pin", "qdss"; 4348 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 4349 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4350 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4351 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4352 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4353 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4354 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4355 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4356 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4357 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4358 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4359 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4360 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4361 iommus = <&apps_smmu 0x0640 0x1>; 4362 status = "disabled"; 4363 }; 4364 }; 4365 4366 timer { 4367 compatible = "arm,armv8-timer"; 4368 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4369 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4370 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4371 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4372 }; 4373 4374 thermal-zones { 4375 cpu0-thermal { 4376 polling-delay-passive = <250>; 4377 polling-delay = <1000>; 4378 4379 thermal-sensors = <&tsens0 1>; 4380 4381 trips { 4382 cpu0_alert0: trip-point0 { 4383 temperature = <90000>; 4384 hysteresis = <2000>; 4385 type = "passive"; 4386 }; 4387 4388 cpu0_alert1: trip-point1 { 4389 temperature = <95000>; 4390 hysteresis = <2000>; 4391 type = "passive"; 4392 }; 4393 4394 cpu0_crit: cpu-crit { 4395 temperature = <110000>; 4396 hysteresis = <1000>; 4397 type = "critical"; 4398 }; 4399 }; 4400 4401 cooling-maps { 4402 map0 { 4403 trip = <&cpu0_alert0>; 4404 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4405 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4406 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4407 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4408 }; 4409 map1 { 4410 trip = <&cpu0_alert1>; 4411 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4412 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4413 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4414 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4415 }; 4416 }; 4417 }; 4418 4419 cpu1-thermal { 4420 polling-delay-passive = <250>; 4421 polling-delay = <1000>; 4422 4423 thermal-sensors = <&tsens0 2>; 4424 4425 trips { 4426 cpu1_alert0: trip-point0 { 4427 temperature = <90000>; 4428 hysteresis = <2000>; 4429 type = "passive"; 4430 }; 4431 4432 cpu1_alert1: trip-point1 { 4433 temperature = <95000>; 4434 hysteresis = <2000>; 4435 type = "passive"; 4436 }; 4437 4438 cpu1_crit: cpu-crit { 4439 temperature = <110000>; 4440 hysteresis = <1000>; 4441 type = "critical"; 4442 }; 4443 }; 4444 4445 cooling-maps { 4446 map0 { 4447 trip = <&cpu1_alert0>; 4448 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4449 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4450 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4451 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4452 }; 4453 map1 { 4454 trip = <&cpu1_alert1>; 4455 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4456 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4457 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4458 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4459 }; 4460 }; 4461 }; 4462 4463 cpu2-thermal { 4464 polling-delay-passive = <250>; 4465 polling-delay = <1000>; 4466 4467 thermal-sensors = <&tsens0 3>; 4468 4469 trips { 4470 cpu2_alert0: trip-point0 { 4471 temperature = <90000>; 4472 hysteresis = <2000>; 4473 type = "passive"; 4474 }; 4475 4476 cpu2_alert1: trip-point1 { 4477 temperature = <95000>; 4478 hysteresis = <2000>; 4479 type = "passive"; 4480 }; 4481 4482 cpu2_crit: cpu-crit { 4483 temperature = <110000>; 4484 hysteresis = <1000>; 4485 type = "critical"; 4486 }; 4487 }; 4488 4489 cooling-maps { 4490 map0 { 4491 trip = <&cpu2_alert0>; 4492 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4493 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4494 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4495 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4496 }; 4497 map1 { 4498 trip = <&cpu2_alert1>; 4499 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4500 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4501 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4502 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4503 }; 4504 }; 4505 }; 4506 4507 cpu3-thermal { 4508 polling-delay-passive = <250>; 4509 polling-delay = <1000>; 4510 4511 thermal-sensors = <&tsens0 4>; 4512 4513 trips { 4514 cpu3_alert0: trip-point0 { 4515 temperature = <90000>; 4516 hysteresis = <2000>; 4517 type = "passive"; 4518 }; 4519 4520 cpu3_alert1: trip-point1 { 4521 temperature = <95000>; 4522 hysteresis = <2000>; 4523 type = "passive"; 4524 }; 4525 4526 cpu3_crit: cpu-crit { 4527 temperature = <110000>; 4528 hysteresis = <1000>; 4529 type = "critical"; 4530 }; 4531 }; 4532 4533 cooling-maps { 4534 map0 { 4535 trip = <&cpu3_alert0>; 4536 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4537 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4538 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4539 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4540 }; 4541 map1 { 4542 trip = <&cpu3_alert1>; 4543 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4544 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4545 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4546 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4547 }; 4548 }; 4549 }; 4550 4551 cpu4-top-thermal { 4552 polling-delay-passive = <250>; 4553 polling-delay = <1000>; 4554 4555 thermal-sensors = <&tsens0 7>; 4556 4557 trips { 4558 cpu4_top_alert0: trip-point0 { 4559 temperature = <90000>; 4560 hysteresis = <2000>; 4561 type = "passive"; 4562 }; 4563 4564 cpu4_top_alert1: trip-point1 { 4565 temperature = <95000>; 4566 hysteresis = <2000>; 4567 type = "passive"; 4568 }; 4569 4570 cpu4_top_crit: cpu-crit { 4571 temperature = <110000>; 4572 hysteresis = <1000>; 4573 type = "critical"; 4574 }; 4575 }; 4576 4577 cooling-maps { 4578 map0 { 4579 trip = <&cpu4_top_alert0>; 4580 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4581 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4582 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4583 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4584 }; 4585 map1 { 4586 trip = <&cpu4_top_alert1>; 4587 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4588 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4589 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4590 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4591 }; 4592 }; 4593 }; 4594 4595 cpu5-top-thermal { 4596 polling-delay-passive = <250>; 4597 polling-delay = <1000>; 4598 4599 thermal-sensors = <&tsens0 8>; 4600 4601 trips { 4602 cpu5_top_alert0: trip-point0 { 4603 temperature = <90000>; 4604 hysteresis = <2000>; 4605 type = "passive"; 4606 }; 4607 4608 cpu5_top_alert1: trip-point1 { 4609 temperature = <95000>; 4610 hysteresis = <2000>; 4611 type = "passive"; 4612 }; 4613 4614 cpu5_top_crit: cpu-crit { 4615 temperature = <110000>; 4616 hysteresis = <1000>; 4617 type = "critical"; 4618 }; 4619 }; 4620 4621 cooling-maps { 4622 map0 { 4623 trip = <&cpu5_top_alert0>; 4624 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4625 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4626 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4627 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4628 }; 4629 map1 { 4630 trip = <&cpu5_top_alert1>; 4631 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4632 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4633 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4634 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4635 }; 4636 }; 4637 }; 4638 4639 cpu6-top-thermal { 4640 polling-delay-passive = <250>; 4641 polling-delay = <1000>; 4642 4643 thermal-sensors = <&tsens0 9>; 4644 4645 trips { 4646 cpu6_top_alert0: trip-point0 { 4647 temperature = <90000>; 4648 hysteresis = <2000>; 4649 type = "passive"; 4650 }; 4651 4652 cpu6_top_alert1: trip-point1 { 4653 temperature = <95000>; 4654 hysteresis = <2000>; 4655 type = "passive"; 4656 }; 4657 4658 cpu6_top_crit: cpu-crit { 4659 temperature = <110000>; 4660 hysteresis = <1000>; 4661 type = "critical"; 4662 }; 4663 }; 4664 4665 cooling-maps { 4666 map0 { 4667 trip = <&cpu6_top_alert0>; 4668 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4669 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4670 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4671 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4672 }; 4673 map1 { 4674 trip = <&cpu6_top_alert1>; 4675 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4676 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4677 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4678 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4679 }; 4680 }; 4681 }; 4682 4683 cpu7-top-thermal { 4684 polling-delay-passive = <250>; 4685 polling-delay = <1000>; 4686 4687 thermal-sensors = <&tsens0 10>; 4688 4689 trips { 4690 cpu7_top_alert0: trip-point0 { 4691 temperature = <90000>; 4692 hysteresis = <2000>; 4693 type = "passive"; 4694 }; 4695 4696 cpu7_top_alert1: trip-point1 { 4697 temperature = <95000>; 4698 hysteresis = <2000>; 4699 type = "passive"; 4700 }; 4701 4702 cpu7_top_crit: cpu-crit { 4703 temperature = <110000>; 4704 hysteresis = <1000>; 4705 type = "critical"; 4706 }; 4707 }; 4708 4709 cooling-maps { 4710 map0 { 4711 trip = <&cpu7_top_alert0>; 4712 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4713 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4714 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4715 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4716 }; 4717 map1 { 4718 trip = <&cpu7_top_alert1>; 4719 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4720 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4721 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4722 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4723 }; 4724 }; 4725 }; 4726 4727 cpu4-bottom-thermal { 4728 polling-delay-passive = <250>; 4729 polling-delay = <1000>; 4730 4731 thermal-sensors = <&tsens0 11>; 4732 4733 trips { 4734 cpu4_bottom_alert0: trip-point0 { 4735 temperature = <90000>; 4736 hysteresis = <2000>; 4737 type = "passive"; 4738 }; 4739 4740 cpu4_bottom_alert1: trip-point1 { 4741 temperature = <95000>; 4742 hysteresis = <2000>; 4743 type = "passive"; 4744 }; 4745 4746 cpu4_bottom_crit: cpu-crit { 4747 temperature = <110000>; 4748 hysteresis = <1000>; 4749 type = "critical"; 4750 }; 4751 }; 4752 4753 cooling-maps { 4754 map0 { 4755 trip = <&cpu4_bottom_alert0>; 4756 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4757 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4758 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4759 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4760 }; 4761 map1 { 4762 trip = <&cpu4_bottom_alert1>; 4763 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4764 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4765 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4766 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4767 }; 4768 }; 4769 }; 4770 4771 cpu5-bottom-thermal { 4772 polling-delay-passive = <250>; 4773 polling-delay = <1000>; 4774 4775 thermal-sensors = <&tsens0 12>; 4776 4777 trips { 4778 cpu5_bottom_alert0: trip-point0 { 4779 temperature = <90000>; 4780 hysteresis = <2000>; 4781 type = "passive"; 4782 }; 4783 4784 cpu5_bottom_alert1: trip-point1 { 4785 temperature = <95000>; 4786 hysteresis = <2000>; 4787 type = "passive"; 4788 }; 4789 4790 cpu5_bottom_crit: cpu-crit { 4791 temperature = <110000>; 4792 hysteresis = <1000>; 4793 type = "critical"; 4794 }; 4795 }; 4796 4797 cooling-maps { 4798 map0 { 4799 trip = <&cpu5_bottom_alert0>; 4800 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4801 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4802 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4803 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4804 }; 4805 map1 { 4806 trip = <&cpu5_bottom_alert1>; 4807 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4808 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4809 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4810 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4811 }; 4812 }; 4813 }; 4814 4815 cpu6-bottom-thermal { 4816 polling-delay-passive = <250>; 4817 polling-delay = <1000>; 4818 4819 thermal-sensors = <&tsens0 13>; 4820 4821 trips { 4822 cpu6_bottom_alert0: trip-point0 { 4823 temperature = <90000>; 4824 hysteresis = <2000>; 4825 type = "passive"; 4826 }; 4827 4828 cpu6_bottom_alert1: trip-point1 { 4829 temperature = <95000>; 4830 hysteresis = <2000>; 4831 type = "passive"; 4832 }; 4833 4834 cpu6_bottom_crit: cpu-crit { 4835 temperature = <110000>; 4836 hysteresis = <1000>; 4837 type = "critical"; 4838 }; 4839 }; 4840 4841 cooling-maps { 4842 map0 { 4843 trip = <&cpu6_bottom_alert0>; 4844 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4845 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4846 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4847 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4848 }; 4849 map1 { 4850 trip = <&cpu6_bottom_alert1>; 4851 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4852 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4853 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4854 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4855 }; 4856 }; 4857 }; 4858 4859 cpu7-bottom-thermal { 4860 polling-delay-passive = <250>; 4861 polling-delay = <1000>; 4862 4863 thermal-sensors = <&tsens0 14>; 4864 4865 trips { 4866 cpu7_bottom_alert0: trip-point0 { 4867 temperature = <90000>; 4868 hysteresis = <2000>; 4869 type = "passive"; 4870 }; 4871 4872 cpu7_bottom_alert1: trip-point1 { 4873 temperature = <95000>; 4874 hysteresis = <2000>; 4875 type = "passive"; 4876 }; 4877 4878 cpu7_bottom_crit: cpu-crit { 4879 temperature = <110000>; 4880 hysteresis = <1000>; 4881 type = "critical"; 4882 }; 4883 }; 4884 4885 cooling-maps { 4886 map0 { 4887 trip = <&cpu7_bottom_alert0>; 4888 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4889 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4890 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4891 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4892 }; 4893 map1 { 4894 trip = <&cpu7_bottom_alert1>; 4895 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4896 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4897 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4898 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4899 }; 4900 }; 4901 }; 4902 4903 aoss0-thermal { 4904 polling-delay-passive = <250>; 4905 polling-delay = <1000>; 4906 4907 thermal-sensors = <&tsens0 0>; 4908 4909 trips { 4910 aoss0_alert0: trip-point0 { 4911 temperature = <90000>; 4912 hysteresis = <2000>; 4913 type = "hot"; 4914 }; 4915 }; 4916 }; 4917 4918 cluster0-thermal { 4919 polling-delay-passive = <250>; 4920 polling-delay = <1000>; 4921 4922 thermal-sensors = <&tsens0 5>; 4923 4924 trips { 4925 cluster0_alert0: trip-point0 { 4926 temperature = <90000>; 4927 hysteresis = <2000>; 4928 type = "hot"; 4929 }; 4930 cluster0_crit: cluster0_crit { 4931 temperature = <110000>; 4932 hysteresis = <2000>; 4933 type = "critical"; 4934 }; 4935 }; 4936 }; 4937 4938 cluster1-thermal { 4939 polling-delay-passive = <250>; 4940 polling-delay = <1000>; 4941 4942 thermal-sensors = <&tsens0 6>; 4943 4944 trips { 4945 cluster1_alert0: trip-point0 { 4946 temperature = <90000>; 4947 hysteresis = <2000>; 4948 type = "hot"; 4949 }; 4950 cluster1_crit: cluster1_crit { 4951 temperature = <110000>; 4952 hysteresis = <2000>; 4953 type = "critical"; 4954 }; 4955 }; 4956 }; 4957 4958 gpu-top-thermal { 4959 polling-delay-passive = <250>; 4960 polling-delay = <1000>; 4961 4962 thermal-sensors = <&tsens0 15>; 4963 4964 trips { 4965 gpu1_alert0: trip-point0 { 4966 temperature = <90000>; 4967 hysteresis = <2000>; 4968 type = "hot"; 4969 }; 4970 }; 4971 }; 4972 4973 aoss1-thermal { 4974 polling-delay-passive = <250>; 4975 polling-delay = <1000>; 4976 4977 thermal-sensors = <&tsens1 0>; 4978 4979 trips { 4980 aoss1_alert0: trip-point0 { 4981 temperature = <90000>; 4982 hysteresis = <2000>; 4983 type = "hot"; 4984 }; 4985 }; 4986 }; 4987 4988 wlan-thermal { 4989 polling-delay-passive = <250>; 4990 polling-delay = <1000>; 4991 4992 thermal-sensors = <&tsens1 1>; 4993 4994 trips { 4995 wlan_alert0: trip-point0 { 4996 temperature = <90000>; 4997 hysteresis = <2000>; 4998 type = "hot"; 4999 }; 5000 }; 5001 }; 5002 5003 video-thermal { 5004 polling-delay-passive = <250>; 5005 polling-delay = <1000>; 5006 5007 thermal-sensors = <&tsens1 2>; 5008 5009 trips { 5010 video_alert0: trip-point0 { 5011 temperature = <90000>; 5012 hysteresis = <2000>; 5013 type = "hot"; 5014 }; 5015 }; 5016 }; 5017 5018 mem-thermal { 5019 polling-delay-passive = <250>; 5020 polling-delay = <1000>; 5021 5022 thermal-sensors = <&tsens1 3>; 5023 5024 trips { 5025 mem_alert0: trip-point0 { 5026 temperature = <90000>; 5027 hysteresis = <2000>; 5028 type = "hot"; 5029 }; 5030 }; 5031 }; 5032 5033 q6-hvx-thermal { 5034 polling-delay-passive = <250>; 5035 polling-delay = <1000>; 5036 5037 thermal-sensors = <&tsens1 4>; 5038 5039 trips { 5040 q6_hvx_alert0: trip-point0 { 5041 temperature = <90000>; 5042 hysteresis = <2000>; 5043 type = "hot"; 5044 }; 5045 }; 5046 }; 5047 5048 camera-thermal { 5049 polling-delay-passive = <250>; 5050 polling-delay = <1000>; 5051 5052 thermal-sensors = <&tsens1 5>; 5053 5054 trips { 5055 camera_alert0: trip-point0 { 5056 temperature = <90000>; 5057 hysteresis = <2000>; 5058 type = "hot"; 5059 }; 5060 }; 5061 }; 5062 5063 compute-thermal { 5064 polling-delay-passive = <250>; 5065 polling-delay = <1000>; 5066 5067 thermal-sensors = <&tsens1 6>; 5068 5069 trips { 5070 compute_alert0: trip-point0 { 5071 temperature = <90000>; 5072 hysteresis = <2000>; 5073 type = "hot"; 5074 }; 5075 }; 5076 }; 5077 5078 modem-thermal { 5079 polling-delay-passive = <250>; 5080 polling-delay = <1000>; 5081 5082 thermal-sensors = <&tsens1 7>; 5083 5084 trips { 5085 modem_alert0: trip-point0 { 5086 temperature = <90000>; 5087 hysteresis = <2000>; 5088 type = "hot"; 5089 }; 5090 }; 5091 }; 5092 5093 npu-thermal { 5094 polling-delay-passive = <250>; 5095 polling-delay = <1000>; 5096 5097 thermal-sensors = <&tsens1 8>; 5098 5099 trips { 5100 npu_alert0: trip-point0 { 5101 temperature = <90000>; 5102 hysteresis = <2000>; 5103 type = "hot"; 5104 }; 5105 }; 5106 }; 5107 5108 modem-vec-thermal { 5109 polling-delay-passive = <250>; 5110 polling-delay = <1000>; 5111 5112 thermal-sensors = <&tsens1 9>; 5113 5114 trips { 5115 modem_vec_alert0: trip-point0 { 5116 temperature = <90000>; 5117 hysteresis = <2000>; 5118 type = "hot"; 5119 }; 5120 }; 5121 }; 5122 5123 modem-scl-thermal { 5124 polling-delay-passive = <250>; 5125 polling-delay = <1000>; 5126 5127 thermal-sensors = <&tsens1 10>; 5128 5129 trips { 5130 modem_scl_alert0: trip-point0 { 5131 temperature = <90000>; 5132 hysteresis = <2000>; 5133 type = "hot"; 5134 }; 5135 }; 5136 }; 5137 5138 gpu-bottom-thermal { 5139 polling-delay-passive = <250>; 5140 polling-delay = <1000>; 5141 5142 thermal-sensors = <&tsens1 11>; 5143 5144 trips { 5145 gpu2_alert0: trip-point0 { 5146 temperature = <90000>; 5147 hysteresis = <2000>; 5148 type = "hot"; 5149 }; 5150 }; 5151 }; 5152 }; 5153}; 5154