xref: /openbmc/linux/arch/arm64/boot/dts/qcom/sm8150.dtsi (revision f4c3b83b)
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, Linaro Limited
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/power/qcom-aoss-qmp.h>
9#include <dt-bindings/power/qcom-rpmpd.h>
10#include <dt-bindings/soc/qcom,rpmh-rsc.h>
11#include <dt-bindings/clock/qcom,rpmh.h>
12#include <dt-bindings/clock/qcom,gcc-sm8150.h>
13#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
14#include <dt-bindings/interconnect/qcom,osm-l3.h>
15#include <dt-bindings/thermal/thermal.h>
16
17/ {
18	interrupt-parent = <&intc>;
19
20	#address-cells = <2>;
21	#size-cells = <2>;
22
23	chosen { };
24
25	clocks {
26		xo_board: xo-board {
27			compatible = "fixed-clock";
28			#clock-cells = <0>;
29			clock-frequency = <38400000>;
30			clock-output-names = "xo_board";
31		};
32
33		sleep_clk: sleep-clk {
34			compatible = "fixed-clock";
35			#clock-cells = <0>;
36			clock-frequency = <32764>;
37			clock-output-names = "sleep_clk";
38		};
39	};
40
41	cpus {
42		#address-cells = <2>;
43		#size-cells = <0>;
44
45		CPU0: cpu@0 {
46			device_type = "cpu";
47			compatible = "qcom,kryo485";
48			reg = <0x0 0x0>;
49			enable-method = "psci";
50			next-level-cache = <&L2_0>;
51			qcom,freq-domain = <&cpufreq_hw 0>;
52			#cooling-cells = <2>;
53			L2_0: l2-cache {
54				compatible = "cache";
55				next-level-cache = <&L3_0>;
56				L3_0: l3-cache {
57				      compatible = "cache";
58				};
59			};
60		};
61
62		CPU1: cpu@100 {
63			device_type = "cpu";
64			compatible = "qcom,kryo485";
65			reg = <0x0 0x100>;
66			enable-method = "psci";
67			next-level-cache = <&L2_100>;
68			qcom,freq-domain = <&cpufreq_hw 0>;
69			#cooling-cells = <2>;
70			L2_100: l2-cache {
71				compatible = "cache";
72				next-level-cache = <&L3_0>;
73			};
74
75		};
76
77		CPU2: cpu@200 {
78			device_type = "cpu";
79			compatible = "qcom,kryo485";
80			reg = <0x0 0x200>;
81			enable-method = "psci";
82			next-level-cache = <&L2_200>;
83			qcom,freq-domain = <&cpufreq_hw 0>;
84			#cooling-cells = <2>;
85			L2_200: l2-cache {
86				compatible = "cache";
87				next-level-cache = <&L3_0>;
88			};
89		};
90
91		CPU3: cpu@300 {
92			device_type = "cpu";
93			compatible = "qcom,kryo485";
94			reg = <0x0 0x300>;
95			enable-method = "psci";
96			next-level-cache = <&L2_300>;
97			qcom,freq-domain = <&cpufreq_hw 0>;
98			#cooling-cells = <2>;
99			L2_300: l2-cache {
100				compatible = "cache";
101				next-level-cache = <&L3_0>;
102			};
103		};
104
105		CPU4: cpu@400 {
106			device_type = "cpu";
107			compatible = "qcom,kryo485";
108			reg = <0x0 0x400>;
109			enable-method = "psci";
110			next-level-cache = <&L2_400>;
111			qcom,freq-domain = <&cpufreq_hw 1>;
112			#cooling-cells = <2>;
113			L2_400: l2-cache {
114				compatible = "cache";
115				next-level-cache = <&L3_0>;
116			};
117		};
118
119		CPU5: cpu@500 {
120			device_type = "cpu";
121			compatible = "qcom,kryo485";
122			reg = <0x0 0x500>;
123			enable-method = "psci";
124			next-level-cache = <&L2_500>;
125			qcom,freq-domain = <&cpufreq_hw 1>;
126			#cooling-cells = <2>;
127			L2_500: l2-cache {
128				compatible = "cache";
129				next-level-cache = <&L3_0>;
130			};
131		};
132
133		CPU6: cpu@600 {
134			device_type = "cpu";
135			compatible = "qcom,kryo485";
136			reg = <0x0 0x600>;
137			enable-method = "psci";
138			next-level-cache = <&L2_600>;
139			qcom,freq-domain = <&cpufreq_hw 1>;
140			#cooling-cells = <2>;
141			L2_600: l2-cache {
142				compatible = "cache";
143				next-level-cache = <&L3_0>;
144			};
145		};
146
147		CPU7: cpu@700 {
148			device_type = "cpu";
149			compatible = "qcom,kryo485";
150			reg = <0x0 0x700>;
151			enable-method = "psci";
152			next-level-cache = <&L2_700>;
153			qcom,freq-domain = <&cpufreq_hw 2>;
154			#cooling-cells = <2>;
155			L2_700: l2-cache {
156				compatible = "cache";
157				next-level-cache = <&L3_0>;
158			};
159		};
160	};
161
162	firmware {
163		scm: scm {
164			compatible = "qcom,scm-sm8150", "qcom,scm";
165			#reset-cells = <1>;
166		};
167	};
168
169	tcsr_mutex: hwlock {
170		compatible = "qcom,tcsr-mutex";
171		syscon = <&tcsr_mutex_regs 0 0x1000>;
172		#hwlock-cells = <1>;
173	};
174
175	memory@80000000 {
176		device_type = "memory";
177		/* We expect the bootloader to fill in the size */
178		reg = <0x0 0x80000000 0x0 0x0>;
179	};
180
181	pmu {
182		compatible = "arm,armv8-pmuv3";
183		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
184	};
185
186	psci {
187		compatible = "arm,psci-1.0";
188		method = "smc";
189	};
190
191	reserved-memory {
192		#address-cells = <2>;
193		#size-cells = <2>;
194		ranges;
195
196		hyp_mem: memory@85700000 {
197			reg = <0x0 0x85700000 0x0 0x600000>;
198			no-map;
199		};
200
201		xbl_mem: memory@85d00000 {
202			reg = <0x0 0x85d00000 0x0 0x140000>;
203			no-map;
204		};
205
206		aop_mem: memory@85f00000 {
207			reg = <0x0 0x85f00000 0x0 0x20000>;
208			no-map;
209		};
210
211		aop_cmd_db: memory@85f20000 {
212			compatible = "qcom,cmd-db";
213			reg = <0x0 0x85f20000 0x0 0x20000>;
214			no-map;
215		};
216
217		smem_mem: memory@86000000 {
218			reg = <0x0 0x86000000 0x0 0x200000>;
219			no-map;
220		};
221
222		tz_mem: memory@86200000 {
223			reg = <0x0 0x86200000 0x0 0x3900000>;
224			no-map;
225		};
226
227		rmtfs_mem: memory@89b00000 {
228			compatible = "qcom,rmtfs-mem";
229			reg = <0x0 0x89b00000 0x0 0x200000>;
230			no-map;
231
232			qcom,client-id = <1>;
233			qcom,vmid = <15>;
234		};
235
236		camera_mem: memory@8b700000 {
237			reg = <0x0 0x8b700000 0x0 0x500000>;
238			no-map;
239		};
240
241		wlan_mem: memory@8bc00000 {
242			reg = <0x0 0x8bc00000 0x0 0x180000>;
243			no-map;
244		};
245
246		npu_mem: memory@8bd80000 {
247			reg = <0x0 0x8bd80000 0x0 0x80000>;
248			no-map;
249		};
250
251		adsp_mem: memory@8be00000 {
252			reg = <0x0 0x8be00000 0x0 0x1a00000>;
253			no-map;
254		};
255
256		mpss_mem: memory@8d800000 {
257			reg = <0x0 0x8d800000 0x0 0x9600000>;
258			no-map;
259		};
260
261		venus_mem: memory@96e00000 {
262			reg = <0x0 0x96e00000 0x0 0x500000>;
263			no-map;
264		};
265
266		slpi_mem: memory@97300000 {
267			reg = <0x0 0x97300000 0x0 0x1400000>;
268			no-map;
269		};
270
271		ipa_fw_mem: memory@98700000 {
272			reg = <0x0 0x98700000 0x0 0x10000>;
273			no-map;
274		};
275
276		ipa_gsi_mem: memory@98710000 {
277			reg = <0x0 0x98710000 0x0 0x5000>;
278			no-map;
279		};
280
281		gpu_mem: memory@98715000 {
282			reg = <0x0 0x98715000 0x0 0x2000>;
283			no-map;
284		};
285
286		spss_mem: memory@98800000 {
287			reg = <0x0 0x98800000 0x0 0x100000>;
288			no-map;
289		};
290
291		cdsp_mem: memory@98900000 {
292			reg = <0x0 0x98900000 0x0 0x1400000>;
293			no-map;
294		};
295
296		qseecom_mem: memory@9e400000 {
297			reg = <0x0 0x9e400000 0x0 0x1400000>;
298			no-map;
299		};
300	};
301
302	smem {
303		compatible = "qcom,smem";
304		memory-region = <&smem_mem>;
305		hwlocks = <&tcsr_mutex 3>;
306	};
307
308	smp2p-cdsp {
309		compatible = "qcom,smp2p";
310		qcom,smem = <94>, <432>;
311
312		interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
313
314		mboxes = <&apss_shared 6>;
315
316		qcom,local-pid = <0>;
317		qcom,remote-pid = <5>;
318
319		cdsp_smp2p_out: master-kernel {
320			qcom,entry-name = "master-kernel";
321			#qcom,smem-state-cells = <1>;
322		};
323
324		cdsp_smp2p_in: slave-kernel {
325			qcom,entry-name = "slave-kernel";
326
327			interrupt-controller;
328			#interrupt-cells = <2>;
329		};
330	};
331
332	smp2p-lpass {
333		compatible = "qcom,smp2p";
334		qcom,smem = <443>, <429>;
335
336		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
337
338		mboxes = <&apss_shared 10>;
339
340		qcom,local-pid = <0>;
341		qcom,remote-pid = <2>;
342
343		adsp_smp2p_out: master-kernel {
344			qcom,entry-name = "master-kernel";
345			#qcom,smem-state-cells = <1>;
346		};
347
348		adsp_smp2p_in: slave-kernel {
349			qcom,entry-name = "slave-kernel";
350
351			interrupt-controller;
352			#interrupt-cells = <2>;
353		};
354	};
355
356	smp2p-mpss {
357		compatible = "qcom,smp2p";
358		qcom,smem = <435>, <428>;
359
360		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
361
362		mboxes = <&apss_shared 14>;
363
364		qcom,local-pid = <0>;
365		qcom,remote-pid = <1>;
366
367		modem_smp2p_out: master-kernel {
368			qcom,entry-name = "master-kernel";
369			#qcom,smem-state-cells = <1>;
370		};
371
372		modem_smp2p_in: slave-kernel {
373			qcom,entry-name = "slave-kernel";
374
375			interrupt-controller;
376			#interrupt-cells = <2>;
377		};
378	};
379
380	smp2p-slpi {
381		compatible = "qcom,smp2p";
382		qcom,smem = <481>, <430>;
383
384		interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
385
386		mboxes = <&apss_shared 26>;
387
388		qcom,local-pid = <0>;
389		qcom,remote-pid = <3>;
390
391		slpi_smp2p_out: master-kernel {
392			qcom,entry-name = "master-kernel";
393			#qcom,smem-state-cells = <1>;
394		};
395
396		slpi_smp2p_in: slave-kernel {
397			qcom,entry-name = "slave-kernel";
398
399			interrupt-controller;
400			#interrupt-cells = <2>;
401		};
402	};
403
404	soc: soc@0 {
405		#address-cells = <2>;
406		#size-cells = <2>;
407		ranges = <0 0 0 0 0x10 0>;
408		dma-ranges = <0 0 0 0 0x10 0>;
409		compatible = "simple-bus";
410
411		gcc: clock-controller@100000 {
412			compatible = "qcom,gcc-sm8150";
413			reg = <0x0 0x00100000 0x0 0x1f0000>;
414			#clock-cells = <1>;
415			#reset-cells = <1>;
416			#power-domain-cells = <1>;
417			clock-names = "bi_tcxo",
418				      "sleep_clk";
419			clocks = <&rpmhcc RPMH_CXO_CLK>,
420				 <&sleep_clk>;
421		};
422
423		qupv3_id_1: geniqup@ac0000 {
424			compatible = "qcom,geni-se-qup";
425			reg = <0x0 0x00ac0000 0x0 0x6000>;
426			clock-names = "m-ahb", "s-ahb";
427			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
428				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
429			#address-cells = <2>;
430			#size-cells = <2>;
431			ranges;
432			status = "disabled";
433
434			uart2: serial@a90000 {
435				compatible = "qcom,geni-debug-uart";
436				reg = <0x0 0x00a90000 0x0 0x4000>;
437				clock-names = "se";
438				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
439				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
440				status = "disabled";
441			};
442		};
443
444		config_noc: interconnect@1500000 {
445			compatible = "qcom,sm8150-config-noc";
446			reg = <0 0x01500000 0 0x7400>;
447			#interconnect-cells = <1>;
448			qcom,bcm-voters = <&apps_bcm_voter>;
449		};
450
451		system_noc: interconnect@1620000 {
452			compatible = "qcom,sm8150-system-noc";
453			reg = <0 0x01620000 0 0x19400>;
454			#interconnect-cells = <1>;
455			qcom,bcm-voters = <&apps_bcm_voter>;
456		};
457
458		mc_virt: interconnect@163a000 {
459			compatible = "qcom,sm8150-mc-virt";
460			reg = <0 0x0163a000 0 0x1000>;
461			#interconnect-cells = <1>;
462			qcom,bcm-voters = <&apps_bcm_voter>;
463		};
464
465		aggre1_noc: interconnect@16e0000 {
466			compatible = "qcom,sm8150-aggre1-noc";
467			reg = <0 0x016e0000 0 0xd080>;
468			#interconnect-cells = <1>;
469			qcom,bcm-voters = <&apps_bcm_voter>;
470		};
471
472		aggre2_noc: interconnect@1700000 {
473			compatible = "qcom,sm8150-aggre2-noc";
474			reg = <0 0x01700000 0 0x20000>;
475			#interconnect-cells = <1>;
476			qcom,bcm-voters = <&apps_bcm_voter>;
477		};
478
479		compute_noc: interconnect@1720000 {
480			compatible = "qcom,sm8150-compute-noc";
481			reg = <0 0x01720000 0 0x7000>;
482			#interconnect-cells = <1>;
483			qcom,bcm-voters = <&apps_bcm_voter>;
484		};
485
486		mmss_noc: interconnect@1740000 {
487			compatible = "qcom,sm8150-mmss-noc";
488			reg = <0 0x01740000 0 0x1c100>;
489			#interconnect-cells = <1>;
490			qcom,bcm-voters = <&apps_bcm_voter>;
491		};
492
493		system-cache-controller@9200000 {
494			compatible = "qcom,sm8150-llcc";
495			reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
496			reg-names = "llcc_base", "llcc_broadcast_base";
497			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
498		};
499
500		ufs_mem_hc: ufshc@1d84000 {
501			compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
502				     "jedec,ufs-2.0";
503			reg = <0 0x01d84000 0 0x2500>;
504			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
505			phys = <&ufs_mem_phy_lanes>;
506			phy-names = "ufsphy";
507			lanes-per-direction = <2>;
508			#reset-cells = <1>;
509			resets = <&gcc GCC_UFS_PHY_BCR>;
510			reset-names = "rst";
511
512			iommus = <&apps_smmu 0x300 0>;
513
514			clock-names =
515				"core_clk",
516				"bus_aggr_clk",
517				"iface_clk",
518				"core_clk_unipro",
519				"ref_clk",
520				"tx_lane0_sync_clk",
521				"rx_lane0_sync_clk",
522				"rx_lane1_sync_clk";
523			clocks =
524				<&gcc GCC_UFS_PHY_AXI_CLK>,
525				<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
526				<&gcc GCC_UFS_PHY_AHB_CLK>,
527				<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
528				<&rpmhcc RPMH_CXO_CLK>,
529				<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
530				<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
531				<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
532			freq-table-hz =
533				<37500000 300000000>,
534				<0 0>,
535				<0 0>,
536				<37500000 300000000>,
537				<0 0>,
538				<0 0>,
539				<0 0>,
540				<0 0>;
541
542			status = "disabled";
543		};
544
545		ufs_mem_phy: phy@1d87000 {
546			compatible = "qcom,sm8150-qmp-ufs-phy";
547			reg = <0 0x01d87000 0 0x1c0>;
548			#address-cells = <2>;
549			#size-cells = <2>;
550			ranges;
551			clock-names = "ref",
552				      "ref_aux";
553			clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
554				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
555
556			resets = <&ufs_mem_hc 0>;
557			reset-names = "ufsphy";
558			status = "disabled";
559
560			ufs_mem_phy_lanes: lanes@1d87400 {
561				reg = <0 0x01d87400 0 0x108>,
562				      <0 0x01d87600 0 0x1e0>,
563				      <0 0x01d87c00 0 0x1dc>,
564				      <0 0x01d87800 0 0x108>,
565				      <0 0x01d87a00 0 0x1e0>;
566				#phy-cells = <0>;
567			};
568		};
569
570		ipa_virt: interconnect@1e00000 {
571			compatible = "qcom,sm8150-ipa-virt";
572			reg = <0 0x01e00000 0 0x1000>;
573			#interconnect-cells = <1>;
574			qcom,bcm-voters = <&apps_bcm_voter>;
575		};
576
577		tcsr_mutex_regs: syscon@1f40000 {
578			compatible = "syscon";
579			reg = <0x0 0x01f40000 0x0 0x40000>;
580		};
581
582		remoteproc_slpi: remoteproc@2400000 {
583			compatible = "qcom,sm8150-slpi-pas";
584			reg = <0x0 0x02400000 0x0 0x4040>;
585
586			interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
587					      <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
588					      <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
589					      <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
590					      <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
591			interrupt-names = "wdog", "fatal", "ready",
592					  "handover", "stop-ack";
593
594			clocks = <&rpmhcc RPMH_CXO_CLK>;
595			clock-names = "xo";
596
597			power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
598					<&rpmhpd 3>,
599					<&rpmhpd 2>;
600			power-domain-names = "load_state", "lcx", "lmx";
601
602			memory-region = <&slpi_mem>;
603
604			qcom,smem-states = <&slpi_smp2p_out 0>;
605			qcom,smem-state-names = "stop";
606
607			status = "disabled";
608
609			glink-edge {
610				interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
611				label = "dsps";
612				qcom,remote-pid = <3>;
613				mboxes = <&apss_shared 24>;
614			};
615		};
616
617		gpu: gpu@2c00000 {
618			/*
619			 * note: the amd,imageon compatible makes it possible
620			 * to use the drm/msm driver without the display node,
621			 * make sure to remove it when display node is added
622			 */
623			compatible = "qcom,adreno-640.1",
624				     "qcom,adreno",
625				     "amd,imageon";
626			#stream-id-cells = <16>;
627
628			reg = <0 0x02c00000 0 0x40000>;
629			reg-names = "kgsl_3d0_reg_memory";
630
631			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
632
633			iommus = <&adreno_smmu 0 0x401>;
634
635			operating-points-v2 = <&gpu_opp_table>;
636
637			qcom,gmu = <&gmu>;
638
639			zap-shader {
640				memory-region = <&gpu_mem>;
641			};
642
643			/* note: downstream checks gpu binning for 675 Mhz */
644			gpu_opp_table: opp-table {
645				compatible = "operating-points-v2";
646
647				opp-675000000 {
648					opp-hz = /bits/ 64 <675000000>;
649					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
650				};
651
652				opp-585000000 {
653					opp-hz = /bits/ 64 <585000000>;
654					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
655				};
656
657				opp-499200000 {
658					opp-hz = /bits/ 64 <499200000>;
659					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
660				};
661
662				opp-427000000 {
663					opp-hz = /bits/ 64 <427000000>;
664					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
665				};
666
667				opp-345000000 {
668					opp-hz = /bits/ 64 <345000000>;
669					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
670				};
671
672				opp-257000000 {
673					opp-hz = /bits/ 64 <257000000>;
674					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
675				};
676			};
677		};
678
679		gmu: gmu@2c6a000 {
680			compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
681
682			reg = <0 0x02c6a000 0 0x30000>,
683			      <0 0x0b290000 0 0x10000>,
684			      <0 0x0b490000 0 0x10000>;
685			reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
686
687			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
688				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
689			interrupt-names = "hfi", "gmu";
690
691			clocks = <&gpucc GPU_CC_AHB_CLK>,
692				 <&gpucc GPU_CC_CX_GMU_CLK>,
693				 <&gpucc GPU_CC_CXO_CLK>,
694				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
695				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
696			clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
697
698			power-domains = <&gpucc GPU_CX_GDSC>,
699					<&gpucc GPU_GX_GDSC>;
700			power-domain-names = "cx", "gx";
701
702			iommus = <&adreno_smmu 5 0x400>;
703
704			operating-points-v2 = <&gmu_opp_table>;
705
706			gmu_opp_table: opp-table {
707				compatible = "operating-points-v2";
708
709				opp-200000000 {
710					opp-hz = /bits/ 64 <200000000>;
711					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
712				};
713			};
714		};
715
716		gpucc: clock-controller@2c90000 {
717			compatible = "qcom,sm8150-gpucc";
718			reg = <0 0x02c90000 0 0x9000>;
719			clocks = <&rpmhcc RPMH_CXO_CLK>,
720				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
721				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
722			clock-names = "bi_tcxo",
723				      "gcc_gpu_gpll0_clk_src",
724				      "gcc_gpu_gpll0_div_clk_src";
725			#clock-cells = <1>;
726			#reset-cells = <1>;
727			#power-domain-cells = <1>;
728		};
729
730		adreno_smmu: iommu@2ca0000 {
731			compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
732			reg = <0 0x02ca0000 0 0x10000>;
733			#iommu-cells = <2>;
734			#global-interrupts = <1>;
735			interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
736				<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
737				<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
738				<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
739				<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
740				<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
741				<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
742				<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
743				<GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
744			clocks = <&gpucc GPU_CC_AHB_CLK>,
745				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
746				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
747			clock-names = "ahb", "bus", "iface";
748
749			power-domains = <&gpucc GPU_CX_GDSC>;
750		};
751
752		tlmm: pinctrl@3100000 {
753			compatible = "qcom,sm8150-pinctrl";
754			reg = <0x0 0x03100000 0x0 0x300000>,
755			      <0x0 0x03500000 0x0 0x300000>,
756			      <0x0 0x03900000 0x0 0x300000>,
757			      <0x0 0x03D00000 0x0 0x300000>;
758			reg-names = "west", "east", "north", "south";
759			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
760			gpio-ranges = <&tlmm 0 0 175>;
761			gpio-controller;
762			#gpio-cells = <2>;
763			interrupt-controller;
764			#interrupt-cells = <2>;
765		};
766
767		remoteproc_mpss: remoteproc@4080000 {
768			compatible = "qcom,sm8150-mpss-pas";
769			reg = <0x0 0x04080000 0x0 0x4040>;
770
771			interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
772					      <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
773					      <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
774					      <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
775					      <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
776					      <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
777			interrupt-names = "wdog", "fatal", "ready", "handover",
778					  "stop-ack", "shutdown-ack";
779
780			clocks = <&rpmhcc RPMH_CXO_CLK>;
781			clock-names = "xo";
782
783			power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
784					<&rpmhpd 7>,
785					<&rpmhpd 0>;
786			power-domain-names = "load_state", "cx", "mss";
787
788			memory-region = <&mpss_mem>;
789
790			qcom,smem-states = <&modem_smp2p_out 0>;
791			qcom,smem-state-names = "stop";
792
793			glink-edge {
794				interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
795				label = "modem";
796				qcom,remote-pid = <1>;
797				mboxes = <&apss_shared 12>;
798			};
799		};
800
801		stm@6002000 {
802			compatible = "arm,coresight-stm", "arm,primecell";
803			reg = <0 0x06002000 0 0x1000>,
804			      <0 0x16280000 0 0x180000>;
805			reg-names = "stm-base", "stm-stimulus-base";
806
807			clocks = <&aoss_qmp>;
808			clock-names = "apb_pclk";
809
810			out-ports {
811				port {
812					stm_out: endpoint {
813						remote-endpoint = <&funnel0_in7>;
814					};
815				};
816			};
817		};
818
819		funnel@6041000 {
820			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
821			reg = <0 0x06041000 0 0x1000>;
822
823			clocks = <&aoss_qmp>;
824			clock-names = "apb_pclk";
825
826			out-ports {
827				port {
828					funnel0_out: endpoint {
829						remote-endpoint = <&merge_funnel_in0>;
830					};
831				};
832			};
833
834			in-ports {
835				#address-cells = <1>;
836				#size-cells = <0>;
837
838				port@7 {
839					reg = <7>;
840					funnel0_in7: endpoint {
841						remote-endpoint = <&stm_out>;
842					};
843				};
844			};
845		};
846
847		funnel@6042000 {
848			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
849			reg = <0 0x06042000 0 0x1000>;
850
851			clocks = <&aoss_qmp>;
852			clock-names = "apb_pclk";
853
854			out-ports {
855				port {
856					funnel1_out: endpoint {
857						remote-endpoint = <&merge_funnel_in1>;
858					};
859				};
860			};
861
862			in-ports {
863				#address-cells = <1>;
864				#size-cells = <0>;
865
866				port@4 {
867					reg = <4>;
868					funnel1_in4: endpoint {
869						remote-endpoint = <&swao_replicator_out>;
870					};
871				};
872			};
873		};
874
875		funnel@6043000 {
876			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
877			reg = <0 0x06043000 0 0x1000>;
878
879			clocks = <&aoss_qmp>;
880			clock-names = "apb_pclk";
881
882			out-ports {
883				port {
884					funnel2_out: endpoint {
885						remote-endpoint = <&merge_funnel_in2>;
886					};
887				};
888			};
889
890			in-ports {
891				#address-cells = <1>;
892				#size-cells = <0>;
893
894				port@2 {
895					reg = <2>;
896					funnel2_in2: endpoint {
897						remote-endpoint = <&apss_merge_funnel_out>;
898					};
899				};
900			};
901		};
902
903		funnel@6045000 {
904			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
905			reg = <0 0x06045000 0 0x1000>;
906
907			clocks = <&aoss_qmp>;
908			clock-names = "apb_pclk";
909
910			out-ports {
911				port {
912					merge_funnel_out: endpoint {
913						remote-endpoint = <&etf_in>;
914					};
915				};
916			};
917
918			in-ports {
919				#address-cells = <1>;
920				#size-cells = <0>;
921
922				port@0 {
923					reg = <0>;
924					merge_funnel_in0: endpoint {
925						remote-endpoint = <&funnel0_out>;
926					};
927				};
928
929				port@1 {
930					reg = <1>;
931					merge_funnel_in1: endpoint {
932						remote-endpoint = <&funnel1_out>;
933					};
934				};
935
936				port@2 {
937					reg = <2>;
938					merge_funnel_in2: endpoint {
939						remote-endpoint = <&funnel2_out>;
940					};
941				};
942			};
943		};
944
945		replicator@6046000 {
946			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
947			reg = <0 0x06046000 0 0x1000>;
948
949			clocks = <&aoss_qmp>;
950			clock-names = "apb_pclk";
951
952			out-ports {
953				#address-cells = <1>;
954				#size-cells = <0>;
955
956				port@0 {
957					reg = <0>;
958					replicator_out0: endpoint {
959						remote-endpoint = <&etr_in>;
960					};
961				};
962
963				port@1 {
964					reg = <1>;
965					replicator_out1: endpoint {
966						remote-endpoint = <&replicator1_in>;
967					};
968				};
969			};
970
971			in-ports {
972				port {
973					replicator_in0: endpoint {
974						remote-endpoint = <&etf_out>;
975					};
976				};
977			};
978		};
979
980		etf@6047000 {
981			compatible = "arm,coresight-tmc", "arm,primecell";
982			reg = <0 0x06047000 0 0x1000>;
983
984			clocks = <&aoss_qmp>;
985			clock-names = "apb_pclk";
986
987			out-ports {
988				port {
989					etf_out: endpoint {
990						remote-endpoint = <&replicator_in0>;
991					};
992				};
993			};
994
995			in-ports {
996				port {
997					etf_in: endpoint {
998						remote-endpoint = <&merge_funnel_out>;
999					};
1000				};
1001			};
1002		};
1003
1004		etr@6048000 {
1005			compatible = "arm,coresight-tmc", "arm,primecell";
1006			reg = <0 0x06048000 0 0x1000>;
1007			iommus = <&apps_smmu 0x05e0 0x0>;
1008
1009			clocks = <&aoss_qmp>;
1010			clock-names = "apb_pclk";
1011			arm,scatter-gather;
1012
1013			in-ports {
1014				port {
1015					etr_in: endpoint {
1016						remote-endpoint = <&replicator_out0>;
1017					};
1018				};
1019			};
1020		};
1021
1022		replicator@604a000 {
1023			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1024			reg = <0 0x0604a000 0 0x1000>;
1025
1026			clocks = <&aoss_qmp>;
1027			clock-names = "apb_pclk";
1028
1029			out-ports {
1030				#address-cells = <1>;
1031				#size-cells = <0>;
1032
1033				port@1 {
1034					reg = <1>;
1035					replicator1_out: endpoint {
1036						remote-endpoint = <&swao_funnel_in>;
1037					};
1038				};
1039			};
1040
1041			in-ports {
1042				#address-cells = <1>;
1043				#size-cells = <0>;
1044
1045				port@1 {
1046					reg = <1>;
1047					replicator1_in: endpoint {
1048						remote-endpoint = <&replicator_out1>;
1049					};
1050				};
1051			};
1052		};
1053
1054		funnel@6b08000 {
1055			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1056			reg = <0 0x06b08000 0 0x1000>;
1057
1058			clocks = <&aoss_qmp>;
1059			clock-names = "apb_pclk";
1060
1061			out-ports {
1062				port {
1063					swao_funnel_out: endpoint {
1064						remote-endpoint = <&swao_etf_in>;
1065					};
1066				};
1067			};
1068
1069			in-ports {
1070				#address-cells = <1>;
1071				#size-cells = <0>;
1072
1073				port@6 {
1074					reg = <6>;
1075					swao_funnel_in: endpoint {
1076						remote-endpoint = <&replicator1_out>;
1077					};
1078				};
1079			};
1080		};
1081
1082		etf@6b09000 {
1083			compatible = "arm,coresight-tmc", "arm,primecell";
1084			reg = <0 0x06b09000 0 0x1000>;
1085
1086			clocks = <&aoss_qmp>;
1087			clock-names = "apb_pclk";
1088
1089			out-ports {
1090				port {
1091					swao_etf_out: endpoint {
1092						remote-endpoint = <&swao_replicator_in>;
1093					};
1094				};
1095			};
1096
1097			in-ports {
1098				port {
1099					swao_etf_in: endpoint {
1100						remote-endpoint = <&swao_funnel_out>;
1101					};
1102				};
1103			};
1104		};
1105
1106		replicator@6b0a000 {
1107			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1108			reg = <0 0x06b0a000 0 0x1000>;
1109
1110			clocks = <&aoss_qmp>;
1111			clock-names = "apb_pclk";
1112			qcom,replicator-loses-context;
1113
1114			out-ports {
1115				port {
1116					swao_replicator_out: endpoint {
1117						remote-endpoint = <&funnel1_in4>;
1118					};
1119				};
1120			};
1121
1122			in-ports {
1123				port {
1124					swao_replicator_in: endpoint {
1125						remote-endpoint = <&swao_etf_out>;
1126					};
1127				};
1128			};
1129		};
1130
1131		etm@7040000 {
1132			compatible = "arm,coresight-etm4x", "arm,primecell";
1133			reg = <0 0x07040000 0 0x1000>;
1134
1135			cpu = <&CPU0>;
1136
1137			clocks = <&aoss_qmp>;
1138			clock-names = "apb_pclk";
1139			arm,coresight-loses-context-with-cpu;
1140			qcom,skip-power-up;
1141
1142			out-ports {
1143				port {
1144					etm0_out: endpoint {
1145						remote-endpoint = <&apss_funnel_in0>;
1146					};
1147				};
1148			};
1149		};
1150
1151		etm@7140000 {
1152			compatible = "arm,coresight-etm4x", "arm,primecell";
1153			reg = <0 0x07140000 0 0x1000>;
1154
1155			cpu = <&CPU1>;
1156
1157			clocks = <&aoss_qmp>;
1158			clock-names = "apb_pclk";
1159			arm,coresight-loses-context-with-cpu;
1160			qcom,skip-power-up;
1161
1162			out-ports {
1163				port {
1164					etm1_out: endpoint {
1165						remote-endpoint = <&apss_funnel_in1>;
1166					};
1167				};
1168			};
1169		};
1170
1171		etm@7240000 {
1172			compatible = "arm,coresight-etm4x", "arm,primecell";
1173			reg = <0 0x07240000 0 0x1000>;
1174
1175			cpu = <&CPU2>;
1176
1177			clocks = <&aoss_qmp>;
1178			clock-names = "apb_pclk";
1179			arm,coresight-loses-context-with-cpu;
1180			qcom,skip-power-up;
1181
1182			out-ports {
1183				port {
1184					etm2_out: endpoint {
1185						remote-endpoint = <&apss_funnel_in2>;
1186					};
1187				};
1188			};
1189		};
1190
1191		etm@7340000 {
1192			compatible = "arm,coresight-etm4x", "arm,primecell";
1193			reg = <0 0x07340000 0 0x1000>;
1194
1195			cpu = <&CPU3>;
1196
1197			clocks = <&aoss_qmp>;
1198			clock-names = "apb_pclk";
1199			arm,coresight-loses-context-with-cpu;
1200			qcom,skip-power-up;
1201
1202			out-ports {
1203				port {
1204					etm3_out: endpoint {
1205						remote-endpoint = <&apss_funnel_in3>;
1206					};
1207				};
1208			};
1209		};
1210
1211		etm@7440000 {
1212			compatible = "arm,coresight-etm4x", "arm,primecell";
1213			reg = <0 0x07440000 0 0x1000>;
1214
1215			cpu = <&CPU4>;
1216
1217			clocks = <&aoss_qmp>;
1218			clock-names = "apb_pclk";
1219			arm,coresight-loses-context-with-cpu;
1220			qcom,skip-power-up;
1221
1222			out-ports {
1223				port {
1224					etm4_out: endpoint {
1225						remote-endpoint = <&apss_funnel_in4>;
1226					};
1227				};
1228			};
1229		};
1230
1231		etm@7540000 {
1232			compatible = "arm,coresight-etm4x", "arm,primecell";
1233			reg = <0 0x07540000 0 0x1000>;
1234
1235			cpu = <&CPU5>;
1236
1237			clocks = <&aoss_qmp>;
1238			clock-names = "apb_pclk";
1239			arm,coresight-loses-context-with-cpu;
1240			qcom,skip-power-up;
1241
1242			out-ports {
1243				port {
1244					etm5_out: endpoint {
1245						remote-endpoint = <&apss_funnel_in5>;
1246					};
1247				};
1248			};
1249		};
1250
1251		etm@7640000 {
1252			compatible = "arm,coresight-etm4x", "arm,primecell";
1253			reg = <0 0x07640000 0 0x1000>;
1254
1255			cpu = <&CPU6>;
1256
1257			clocks = <&aoss_qmp>;
1258			clock-names = "apb_pclk";
1259			arm,coresight-loses-context-with-cpu;
1260			qcom,skip-power-up;
1261
1262			out-ports {
1263				port {
1264					etm6_out: endpoint {
1265						remote-endpoint = <&apss_funnel_in6>;
1266					};
1267				};
1268			};
1269		};
1270
1271		etm@7740000 {
1272			compatible = "arm,coresight-etm4x", "arm,primecell";
1273			reg = <0 0x07740000 0 0x1000>;
1274
1275			cpu = <&CPU7>;
1276
1277			clocks = <&aoss_qmp>;
1278			clock-names = "apb_pclk";
1279			arm,coresight-loses-context-with-cpu;
1280			qcom,skip-power-up;
1281
1282			out-ports {
1283				port {
1284					etm7_out: endpoint {
1285						remote-endpoint = <&apss_funnel_in7>;
1286					};
1287				};
1288			};
1289		};
1290
1291		funnel@7800000 { /* APSS Funnel */
1292			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1293			reg = <0 0x07800000 0 0x1000>;
1294
1295			clocks = <&aoss_qmp>;
1296			clock-names = "apb_pclk";
1297
1298			out-ports {
1299				port {
1300					apss_funnel_out: endpoint {
1301						remote-endpoint = <&apss_merge_funnel_in>;
1302					};
1303				};
1304			};
1305
1306			in-ports {
1307				#address-cells = <1>;
1308				#size-cells = <0>;
1309
1310				port@0 {
1311					reg = <0>;
1312					apss_funnel_in0: endpoint {
1313						remote-endpoint = <&etm0_out>;
1314					};
1315				};
1316
1317				port@1 {
1318					reg = <1>;
1319					apss_funnel_in1: endpoint {
1320						remote-endpoint = <&etm1_out>;
1321					};
1322				};
1323
1324				port@2 {
1325					reg = <2>;
1326					apss_funnel_in2: endpoint {
1327						remote-endpoint = <&etm2_out>;
1328					};
1329				};
1330
1331				port@3 {
1332					reg = <3>;
1333					apss_funnel_in3: endpoint {
1334						remote-endpoint = <&etm3_out>;
1335					};
1336				};
1337
1338				port@4 {
1339					reg = <4>;
1340					apss_funnel_in4: endpoint {
1341						remote-endpoint = <&etm4_out>;
1342					};
1343				};
1344
1345				port@5 {
1346					reg = <5>;
1347					apss_funnel_in5: endpoint {
1348						remote-endpoint = <&etm5_out>;
1349					};
1350				};
1351
1352				port@6 {
1353					reg = <6>;
1354					apss_funnel_in6: endpoint {
1355						remote-endpoint = <&etm6_out>;
1356					};
1357				};
1358
1359				port@7 {
1360					reg = <7>;
1361					apss_funnel_in7: endpoint {
1362						remote-endpoint = <&etm7_out>;
1363					};
1364				};
1365			};
1366		};
1367
1368		funnel@7810000 {
1369			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1370			reg = <0 0x07810000 0 0x1000>;
1371
1372			clocks = <&aoss_qmp>;
1373			clock-names = "apb_pclk";
1374
1375			out-ports {
1376				port {
1377					apss_merge_funnel_out: endpoint {
1378						remote-endpoint = <&funnel2_in2>;
1379					};
1380				};
1381			};
1382
1383			in-ports {
1384				port {
1385					apss_merge_funnel_in: endpoint {
1386						remote-endpoint = <&apss_funnel_out>;
1387					};
1388				};
1389			};
1390		};
1391
1392		remoteproc_cdsp: remoteproc@8300000 {
1393			compatible = "qcom,sm8150-cdsp-pas";
1394			reg = <0x0 0x08300000 0x0 0x4040>;
1395
1396			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1397					      <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1398					      <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1399					      <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1400					      <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1401			interrupt-names = "wdog", "fatal", "ready",
1402					  "handover", "stop-ack";
1403
1404			clocks = <&rpmhcc RPMH_CXO_CLK>;
1405			clock-names = "xo";
1406
1407			power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
1408					<&rpmhpd 7>;
1409			power-domain-names = "load_state", "cx";
1410
1411			memory-region = <&cdsp_mem>;
1412
1413			qcom,smem-states = <&cdsp_smp2p_out 0>;
1414			qcom,smem-state-names = "stop";
1415
1416			status = "disabled";
1417
1418			glink-edge {
1419				interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1420				label = "cdsp";
1421				qcom,remote-pid = <5>;
1422				mboxes = <&apss_shared 4>;
1423			};
1424		};
1425
1426		usb_1_hsphy: phy@88e2000 {
1427			compatible = "qcom,sm8150-usb-hs-phy",
1428				     "qcom,usb-snps-hs-7nm-phy";
1429			reg = <0 0x088e2000 0 0x400>;
1430			status = "disabled";
1431			#phy-cells = <0>;
1432
1433			clocks = <&rpmhcc RPMH_CXO_CLK>;
1434			clock-names = "ref";
1435
1436			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1437		};
1438
1439		usb_2_hsphy: phy@88e3000 {
1440			compatible = "qcom,sm8150-usb-hs-phy",
1441				     "qcom,usb-snps-hs-7nm-phy";
1442			reg = <0 0x088e3000 0 0x400>;
1443			status = "disabled";
1444			#phy-cells = <0>;
1445
1446			clocks = <&rpmhcc RPMH_CXO_CLK>;
1447			clock-names = "ref";
1448
1449			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1450		};
1451
1452		usb_1_qmpphy: phy@88e9000 {
1453			compatible = "qcom,sm8150-qmp-usb3-phy";
1454			reg = <0 0x088e9000 0 0x18c>,
1455			      <0 0x088e8000 0 0x10>;
1456			reg-names = "reg-base", "dp_com";
1457			status = "disabled";
1458			#clock-cells = <1>;
1459			#address-cells = <2>;
1460			#size-cells = <2>;
1461			ranges;
1462
1463			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1464				 <&rpmhcc RPMH_CXO_CLK>,
1465				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
1466				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1467			clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1468
1469			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
1470				 <&gcc GCC_USB3_PHY_PRIM_BCR>;
1471			reset-names = "phy", "common";
1472
1473			usb_1_ssphy: lanes@88e9200 {
1474				reg = <0 0x088e9200 0 0x200>,
1475				      <0 0x088e9400 0 0x200>,
1476				      <0 0x088e9c00 0 0x218>,
1477				      <0 0x088e9600 0 0x200>,
1478				      <0 0x088e9800 0 0x200>,
1479				      <0 0x088e9a00 0 0x100>;
1480				#phy-cells = <0>;
1481				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1482				clock-names = "pipe0";
1483				clock-output-names = "usb3_phy_pipe_clk_src";
1484			};
1485		};
1486
1487		dc_noc: interconnect@9160000 {
1488			compatible = "qcom,sm8150-dc-noc";
1489			reg = <0 0x09160000 0 0x3200>;
1490			#interconnect-cells = <1>;
1491			qcom,bcm-voters = <&apps_bcm_voter>;
1492		};
1493
1494		gem_noc: interconnect@9680000 {
1495			compatible = "qcom,sm8150-gem-noc";
1496			reg = <0 0x09680000 0 0x3e200>;
1497			#interconnect-cells = <1>;
1498			qcom,bcm-voters = <&apps_bcm_voter>;
1499		};
1500
1501		usb_2_qmpphy: phy@88eb000 {
1502			compatible = "qcom,sm8150-qmp-usb3-uni-phy";
1503			reg = <0 0x088eb000 0 0x200>;
1504			status = "disabled";
1505			#clock-cells = <1>;
1506			#address-cells = <2>;
1507			#size-cells = <2>;
1508			ranges;
1509
1510			clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1511				 <&rpmhcc RPMH_CXO_CLK>,
1512				 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
1513				 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
1514			clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1515
1516			resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
1517				 <&gcc GCC_USB3_PHY_SEC_BCR>;
1518			reset-names = "phy", "common";
1519
1520			usb_2_ssphy: lane@88eb200 {
1521				reg = <0 0x088eb200 0 0x200>,
1522				      <0 0x088eb400 0 0x200>,
1523				      <0 0x088eb800 0 0x800>,
1524				      <0 0x088eb600 0 0x200>;
1525				#phy-cells = <0>;
1526				clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1527				clock-names = "pipe0";
1528				clock-output-names = "usb3_uni_phy_pipe_clk_src";
1529			};
1530		};
1531
1532		usb_1: usb@a6f8800 {
1533			compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
1534			reg = <0 0x0a6f8800 0 0x400>;
1535			status = "disabled";
1536			#address-cells = <2>;
1537			#size-cells = <2>;
1538			ranges;
1539			dma-ranges;
1540
1541			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1542				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1543				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1544				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1545				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1546				 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
1547			clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1548				      "sleep", "xo";
1549
1550			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1551					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1552			assigned-clock-rates = <19200000>, <200000000>;
1553
1554			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1555				     <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
1556				     <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
1557				     <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
1558			interrupt-names = "hs_phy_irq", "ss_phy_irq",
1559					  "dm_hs_phy_irq", "dp_hs_phy_irq";
1560
1561			power-domains = <&gcc USB30_PRIM_GDSC>;
1562
1563			resets = <&gcc GCC_USB30_PRIM_BCR>;
1564
1565			usb_1_dwc3: dwc3@a600000 {
1566				compatible = "snps,dwc3";
1567				reg = <0 0x0a600000 0 0xcd00>;
1568				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1569				iommus = <&apps_smmu 0x140 0>;
1570				snps,dis_u2_susphy_quirk;
1571				snps,dis_enblslpm_quirk;
1572				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1573				phy-names = "usb2-phy", "usb3-phy";
1574			};
1575		};
1576
1577		usb_2: usb@a8f8800 {
1578			compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
1579			reg = <0 0x0a8f8800 0 0x400>;
1580			status = "disabled";
1581			#address-cells = <2>;
1582			#size-cells = <2>;
1583			ranges;
1584			dma-ranges;
1585
1586			clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1587				 <&gcc GCC_USB30_SEC_MASTER_CLK>,
1588				 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1589				 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1590				 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1591				 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
1592			clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1593				      "sleep", "xo";
1594
1595			assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1596					  <&gcc GCC_USB30_SEC_MASTER_CLK>;
1597			assigned-clock-rates = <19200000>, <200000000>;
1598
1599			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1600				     <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
1601				     <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
1602				     <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
1603			interrupt-names = "hs_phy_irq", "ss_phy_irq",
1604					  "dm_hs_phy_irq", "dp_hs_phy_irq";
1605
1606			power-domains = <&gcc USB30_SEC_GDSC>;
1607
1608			resets = <&gcc GCC_USB30_SEC_BCR>;
1609
1610			usb_2_dwc3: dwc3@a800000 {
1611				compatible = "snps,dwc3";
1612				reg = <0 0x0a800000 0 0xcd00>;
1613				interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1614				iommus = <&apps_smmu 0x160 0>;
1615				snps,dis_u2_susphy_quirk;
1616				snps,dis_enblslpm_quirk;
1617				phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
1618				phy-names = "usb2-phy", "usb3-phy";
1619			};
1620		};
1621
1622		camnoc_virt: interconnect@ac00000 {
1623			compatible = "qcom,sm8150-camnoc-virt";
1624			reg = <0 0x0ac00000 0 0x1000>;
1625			#interconnect-cells = <1>;
1626			qcom,bcm-voters = <&apps_bcm_voter>;
1627		};
1628
1629		aoss_qmp: power-controller@c300000 {
1630			compatible = "qcom,sm8150-aoss-qmp";
1631			reg = <0x0 0x0c300000 0x0 0x100000>;
1632			interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
1633			mboxes = <&apss_shared 0>;
1634
1635			#clock-cells = <0>;
1636			#power-domain-cells = <1>;
1637		};
1638
1639		tsens0: thermal-sensor@c263000 {
1640			compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
1641			reg = <0 0x0c263000 0 0x1ff>, /* TM */
1642			      <0 0x0c222000 0 0x1ff>; /* SROT */
1643			#qcom,sensors = <16>;
1644			interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
1645				     <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
1646			interrupt-names = "uplow", "critical";
1647			#thermal-sensor-cells = <1>;
1648		};
1649
1650		tsens1: thermal-sensor@c265000 {
1651			compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
1652			reg = <0 0x0c265000 0 0x1ff>, /* TM */
1653			      <0 0x0c223000 0 0x1ff>; /* SROT */
1654			#qcom,sensors = <8>;
1655			interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
1656				     <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
1657			interrupt-names = "uplow", "critical";
1658			#thermal-sensor-cells = <1>;
1659		};
1660
1661		spmi_bus: spmi@c440000 {
1662			compatible = "qcom,spmi-pmic-arb";
1663			reg = <0x0 0x0c440000 0x0 0x0001100>,
1664			      <0x0 0x0c600000 0x0 0x2000000>,
1665			      <0x0 0x0e600000 0x0 0x0100000>,
1666			      <0x0 0x0e700000 0x0 0x00a0000>,
1667			      <0x0 0x0c40a000 0x0 0x0026000>;
1668			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1669			interrupt-names = "periph_irq";
1670			interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
1671			qcom,ee = <0>;
1672			qcom,channel = <0>;
1673			#address-cells = <2>;
1674			#size-cells = <0>;
1675			interrupt-controller;
1676			#interrupt-cells = <4>;
1677			cell-index = <0>;
1678		};
1679
1680		apps_smmu: iommu@15000000 {
1681			compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
1682			reg = <0 0x15000000 0 0x100000>;
1683			#iommu-cells = <2>;
1684			#global-interrupts = <1>;
1685			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1686				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1687				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1688				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1689				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1690				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1691				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1692				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1693				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1694				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1695				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1696				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1697				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1698				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1699				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1700				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1701				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1702				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1703				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1704				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1705				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1706				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1707				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1708				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1709				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1710				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1711				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1712				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1713				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1714				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1715				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1716				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1717				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1718				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1719				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1720				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1721				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1722				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1723				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1724				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1725				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1726				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1727				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1728				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1729				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1730				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1731				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1732				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1733				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1734				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1735				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1736				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1737				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1738				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1739				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1740				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1741				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1742				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1743				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1744				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1745				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1746				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1747				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1748				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1749				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1750				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1751				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1752				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1753				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1754				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1755				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1756				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1757				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1758				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1759				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1760				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1761				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1762				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1763				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1764				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
1765				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
1766		};
1767
1768		remoteproc_adsp: remoteproc@17300000 {
1769			compatible = "qcom,sm8150-adsp-pas";
1770			reg = <0x0 0x17300000 0x0 0x4040>;
1771
1772			interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
1773					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1774					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1775					      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1776					      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1777			interrupt-names = "wdog", "fatal", "ready",
1778					  "handover", "stop-ack";
1779
1780			clocks = <&rpmhcc RPMH_CXO_CLK>;
1781			clock-names = "xo";
1782
1783			power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
1784					<&rpmhpd 7>;
1785			power-domain-names = "load_state", "cx";
1786
1787			memory-region = <&adsp_mem>;
1788
1789			qcom,smem-states = <&adsp_smp2p_out 0>;
1790			qcom,smem-state-names = "stop";
1791
1792			status = "disabled";
1793
1794			glink-edge {
1795				interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1796				label = "lpass";
1797				qcom,remote-pid = <2>;
1798				mboxes = <&apss_shared 8>;
1799			};
1800		};
1801
1802		intc: interrupt-controller@17a00000 {
1803			compatible = "arm,gic-v3";
1804			interrupt-controller;
1805			#interrupt-cells = <3>;
1806			reg = <0x0 0x17a00000 0x0 0x10000>,	/* GICD */
1807			      <0x0 0x17a60000 0x0 0x100000>;	/* GICR * 8 */
1808			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1809		};
1810
1811		apss_shared: mailbox@17c00000 {
1812			compatible = "qcom,sm8150-apss-shared";
1813			reg = <0x0 0x17c00000 0x0 0x1000>;
1814			#mbox-cells = <1>;
1815		};
1816
1817		watchdog@17c10000 {
1818			compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
1819			reg = <0 0x17c10000 0 0x1000>;
1820			clocks = <&sleep_clk>;
1821		};
1822
1823		timer@17c20000 {
1824			#address-cells = <2>;
1825			#size-cells = <2>;
1826			ranges;
1827			compatible = "arm,armv7-timer-mem";
1828			reg = <0x0 0x17c20000 0x0 0x1000>;
1829			clock-frequency = <19200000>;
1830
1831			frame@17c21000{
1832				frame-number = <0>;
1833				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1834					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1835				reg = <0x0 0x17c21000 0x0 0x1000>,
1836				      <0x0 0x17c22000 0x0 0x1000>;
1837			};
1838
1839			frame@17c23000 {
1840				frame-number = <1>;
1841				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1842				reg = <0x0 0x17c23000 0x0 0x1000>;
1843				status = "disabled";
1844			};
1845
1846			frame@17c25000 {
1847				frame-number = <2>;
1848				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1849				reg = <0x0 0x17c25000 0x0 0x1000>;
1850				status = "disabled";
1851			};
1852
1853			frame@17c27000 {
1854				frame-number = <3>;
1855				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1856				reg = <0x0 0x17c26000 0x0 0x1000>;
1857				status = "disabled";
1858			};
1859
1860			frame@17c29000 {
1861				frame-number = <4>;
1862				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1863				reg = <0x0 0x17c29000 0x0 0x1000>;
1864				status = "disabled";
1865			};
1866
1867			frame@17c2b000 {
1868				frame-number = <5>;
1869				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1870				reg = <0x0 0x17c2b000 0x0 0x1000>;
1871				status = "disabled";
1872			};
1873
1874			frame@17c2d000 {
1875				frame-number = <6>;
1876				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1877				reg = <0x0 0x17c2d000 0x0 0x1000>;
1878				status = "disabled";
1879			};
1880		};
1881
1882		apps_rsc: rsc@18200000 {
1883			label = "apps_rsc";
1884			compatible = "qcom,rpmh-rsc";
1885			reg = <0x0 0x18200000 0x0 0x10000>,
1886			      <0x0 0x18210000 0x0 0x10000>,
1887			      <0x0 0x18220000 0x0 0x10000>;
1888			reg-names = "drv-0", "drv-1", "drv-2";
1889			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1890				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1891				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1892			qcom,tcs-offset = <0xd00>;
1893			qcom,drv-id = <2>;
1894			qcom,tcs-config = <ACTIVE_TCS  2>,
1895					  <SLEEP_TCS   1>,
1896					  <WAKE_TCS    1>,
1897					  <CONTROL_TCS 0>;
1898
1899			rpmhcc: clock-controller {
1900				compatible = "qcom,sm8150-rpmh-clk";
1901				#clock-cells = <1>;
1902				clock-names = "xo";
1903				clocks = <&xo_board>;
1904			};
1905
1906			rpmhpd: power-controller {
1907				compatible = "qcom,sm8150-rpmhpd";
1908				#power-domain-cells = <1>;
1909				operating-points-v2 = <&rpmhpd_opp_table>;
1910
1911				rpmhpd_opp_table: opp-table {
1912					compatible = "operating-points-v2";
1913
1914					rpmhpd_opp_ret: opp1 {
1915						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1916					};
1917
1918					rpmhpd_opp_min_svs: opp2 {
1919						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1920					};
1921
1922					rpmhpd_opp_low_svs: opp3 {
1923						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1924					};
1925
1926					rpmhpd_opp_svs: opp4 {
1927						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1928					};
1929
1930					rpmhpd_opp_svs_l1: opp5 {
1931						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1932					};
1933
1934					rpmhpd_opp_svs_l2: opp6 {
1935						opp-level = <224>;
1936					};
1937
1938					rpmhpd_opp_nom: opp7 {
1939						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1940					};
1941
1942					rpmhpd_opp_nom_l1: opp8 {
1943						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1944					};
1945
1946					rpmhpd_opp_nom_l2: opp9 {
1947						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1948					};
1949
1950					rpmhpd_opp_turbo: opp10 {
1951						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1952					};
1953
1954					rpmhpd_opp_turbo_l1: opp11 {
1955						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1956					};
1957				};
1958			};
1959
1960			apps_bcm_voter: bcm_voter {
1961				compatible = "qcom,bcm-voter";
1962			};
1963		};
1964
1965		osm_l3: interconnect@18321000 {
1966			compatible = "qcom,sm8150-osm-l3";
1967			reg = <0 0x18321000 0 0x1400>;
1968
1969			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
1970			clock-names = "xo", "alternate";
1971
1972			#interconnect-cells = <1>;
1973		};
1974
1975		cpufreq_hw: cpufreq@18323000 {
1976			compatible = "qcom,cpufreq-hw";
1977			reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
1978			      <0 0x18327800 0 0x1400>;
1979			reg-names = "freq-domain0", "freq-domain1",
1980				    "freq-domain2";
1981
1982			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
1983			clock-names = "xo", "alternate";
1984
1985			#freq-domain-cells = <1>;
1986		};
1987
1988		wifi: wifi@18800000 {
1989			compatible = "qcom,wcn3990-wifi";
1990			reg = <0 0x18800000 0 0x800000>;
1991			reg-names = "membase";
1992			memory-region = <&wlan_mem>;
1993			clock-names = "cxo_ref_clk_pin", "qdss";
1994			clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
1995			interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
1996				     <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
1997				     <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1998				     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1999				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2000				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2001				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2002				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2003				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2004				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2005				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2006				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
2007			iommus = <&apps_smmu 0x0640 0x1>;
2008			status = "disabled";
2009		};
2010	};
2011
2012	timer {
2013		compatible = "arm,armv8-timer";
2014		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
2015			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
2016			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
2017			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
2018	};
2019
2020	thermal-zones {
2021		cpu0-thermal {
2022			polling-delay-passive = <250>;
2023			polling-delay = <1000>;
2024
2025			thermal-sensors = <&tsens0 1>;
2026
2027			trips {
2028				cpu0_alert0: trip-point0 {
2029					temperature = <90000>;
2030					hysteresis = <2000>;
2031					type = "passive";
2032				};
2033
2034				cpu0_alert1: trip-point1 {
2035					temperature = <95000>;
2036					hysteresis = <2000>;
2037					type = "passive";
2038				};
2039
2040				cpu0_crit: cpu_crit {
2041					temperature = <110000>;
2042					hysteresis = <1000>;
2043					type = "critical";
2044				};
2045			};
2046
2047			cooling-maps {
2048				map0 {
2049					trip = <&cpu0_alert0>;
2050					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2051							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2052							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2053							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2054				};
2055				map1 {
2056					trip = <&cpu0_alert1>;
2057					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2058							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2059							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2060							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2061				};
2062			};
2063		};
2064
2065		cpu1-thermal {
2066			polling-delay-passive = <250>;
2067			polling-delay = <1000>;
2068
2069			thermal-sensors = <&tsens0 2>;
2070
2071			trips {
2072				cpu1_alert0: trip-point0 {
2073					temperature = <90000>;
2074					hysteresis = <2000>;
2075					type = "passive";
2076				};
2077
2078				cpu1_alert1: trip-point1 {
2079					temperature = <95000>;
2080					hysteresis = <2000>;
2081					type = "passive";
2082				};
2083
2084				cpu1_crit: cpu_crit {
2085					temperature = <110000>;
2086					hysteresis = <1000>;
2087					type = "critical";
2088				};
2089			};
2090
2091			cooling-maps {
2092				map0 {
2093					trip = <&cpu1_alert0>;
2094					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2095							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2096							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2097							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2098				};
2099				map1 {
2100					trip = <&cpu1_alert1>;
2101					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2102							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2103							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2104							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2105				};
2106			};
2107		};
2108
2109		cpu2-thermal {
2110			polling-delay-passive = <250>;
2111			polling-delay = <1000>;
2112
2113			thermal-sensors = <&tsens0 3>;
2114
2115			trips {
2116				cpu2_alert0: trip-point0 {
2117					temperature = <90000>;
2118					hysteresis = <2000>;
2119					type = "passive";
2120				};
2121
2122				cpu2_alert1: trip-point1 {
2123					temperature = <95000>;
2124					hysteresis = <2000>;
2125					type = "passive";
2126				};
2127
2128				cpu2_crit: cpu_crit {
2129					temperature = <110000>;
2130					hysteresis = <1000>;
2131					type = "critical";
2132				};
2133			};
2134
2135			cooling-maps {
2136				map0 {
2137					trip = <&cpu2_alert0>;
2138					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2139							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2140							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2141							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2142				};
2143				map1 {
2144					trip = <&cpu2_alert1>;
2145					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2146							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2147							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2148							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2149				};
2150			};
2151		};
2152
2153		cpu3-thermal {
2154			polling-delay-passive = <250>;
2155			polling-delay = <1000>;
2156
2157			thermal-sensors = <&tsens0 4>;
2158
2159			trips {
2160				cpu3_alert0: trip-point0 {
2161					temperature = <90000>;
2162					hysteresis = <2000>;
2163					type = "passive";
2164				};
2165
2166				cpu3_alert1: trip-point1 {
2167					temperature = <95000>;
2168					hysteresis = <2000>;
2169					type = "passive";
2170				};
2171
2172				cpu3_crit: cpu_crit {
2173					temperature = <110000>;
2174					hysteresis = <1000>;
2175					type = "critical";
2176				};
2177			};
2178
2179			cooling-maps {
2180				map0 {
2181					trip = <&cpu3_alert0>;
2182					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2183							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2184							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2185							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2186				};
2187				map1 {
2188					trip = <&cpu3_alert1>;
2189					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2190							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2191							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2192							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2193				};
2194			};
2195		};
2196
2197		cpu4-top-thermal {
2198			polling-delay-passive = <250>;
2199			polling-delay = <1000>;
2200
2201			thermal-sensors = <&tsens0 7>;
2202
2203			trips {
2204				cpu4_top_alert0: trip-point0 {
2205					temperature = <90000>;
2206					hysteresis = <2000>;
2207					type = "passive";
2208				};
2209
2210				cpu4_top_alert1: trip-point1 {
2211					temperature = <95000>;
2212					hysteresis = <2000>;
2213					type = "passive";
2214				};
2215
2216				cpu4_top_crit: cpu_crit {
2217					temperature = <110000>;
2218					hysteresis = <1000>;
2219					type = "critical";
2220				};
2221			};
2222
2223			cooling-maps {
2224				map0 {
2225					trip = <&cpu4_top_alert0>;
2226					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2227							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2228							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2229							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2230				};
2231				map1 {
2232					trip = <&cpu4_top_alert1>;
2233					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2234							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2235							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2236							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2237				};
2238			};
2239		};
2240
2241		cpu5-top-thermal {
2242			polling-delay-passive = <250>;
2243			polling-delay = <1000>;
2244
2245			thermal-sensors = <&tsens0 8>;
2246
2247			trips {
2248				cpu5_top_alert0: trip-point0 {
2249					temperature = <90000>;
2250					hysteresis = <2000>;
2251					type = "passive";
2252				};
2253
2254				cpu5_top_alert1: trip-point1 {
2255					temperature = <95000>;
2256					hysteresis = <2000>;
2257					type = "passive";
2258				};
2259
2260				cpu5_top_crit: cpu_crit {
2261					temperature = <110000>;
2262					hysteresis = <1000>;
2263					type = "critical";
2264				};
2265			};
2266
2267			cooling-maps {
2268				map0 {
2269					trip = <&cpu5_top_alert0>;
2270					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2271							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2272							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2273							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2274				};
2275				map1 {
2276					trip = <&cpu5_top_alert1>;
2277					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2278							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2279							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2280							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2281				};
2282			};
2283		};
2284
2285		cpu6-top-thermal {
2286			polling-delay-passive = <250>;
2287			polling-delay = <1000>;
2288
2289			thermal-sensors = <&tsens0 9>;
2290
2291			trips {
2292				cpu6_top_alert0: trip-point0 {
2293					temperature = <90000>;
2294					hysteresis = <2000>;
2295					type = "passive";
2296				};
2297
2298				cpu6_top_alert1: trip-point1 {
2299					temperature = <95000>;
2300					hysteresis = <2000>;
2301					type = "passive";
2302				};
2303
2304				cpu6_top_crit: cpu_crit {
2305					temperature = <110000>;
2306					hysteresis = <1000>;
2307					type = "critical";
2308				};
2309			};
2310
2311			cooling-maps {
2312				map0 {
2313					trip = <&cpu6_top_alert0>;
2314					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2315							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2316							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2317							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2318				};
2319				map1 {
2320					trip = <&cpu6_top_alert1>;
2321					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2322							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2323							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2324							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2325				};
2326			};
2327		};
2328
2329		cpu7-top-thermal {
2330			polling-delay-passive = <250>;
2331			polling-delay = <1000>;
2332
2333			thermal-sensors = <&tsens0 10>;
2334
2335			trips {
2336				cpu7_top_alert0: trip-point0 {
2337					temperature = <90000>;
2338					hysteresis = <2000>;
2339					type = "passive";
2340				};
2341
2342				cpu7_top_alert1: trip-point1 {
2343					temperature = <95000>;
2344					hysteresis = <2000>;
2345					type = "passive";
2346				};
2347
2348				cpu7_top_crit: cpu_crit {
2349					temperature = <110000>;
2350					hysteresis = <1000>;
2351					type = "critical";
2352				};
2353			};
2354
2355			cooling-maps {
2356				map0 {
2357					trip = <&cpu7_top_alert0>;
2358					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2359							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2360							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2361							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2362				};
2363				map1 {
2364					trip = <&cpu7_top_alert1>;
2365					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2366							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2367							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2368							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2369				};
2370			};
2371		};
2372
2373		cpu4-bottom-thermal {
2374			polling-delay-passive = <250>;
2375			polling-delay = <1000>;
2376
2377			thermal-sensors = <&tsens0 11>;
2378
2379			trips {
2380				cpu4_bottom_alert0: trip-point0 {
2381					temperature = <90000>;
2382					hysteresis = <2000>;
2383					type = "passive";
2384				};
2385
2386				cpu4_bottom_alert1: trip-point1 {
2387					temperature = <95000>;
2388					hysteresis = <2000>;
2389					type = "passive";
2390				};
2391
2392				cpu4_bottom_crit: cpu_crit {
2393					temperature = <110000>;
2394					hysteresis = <1000>;
2395					type = "critical";
2396				};
2397			};
2398
2399			cooling-maps {
2400				map0 {
2401					trip = <&cpu4_bottom_alert0>;
2402					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2403							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2404							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2405							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2406				};
2407				map1 {
2408					trip = <&cpu4_bottom_alert1>;
2409					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2410							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2411							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2412							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2413				};
2414			};
2415		};
2416
2417		cpu5-bottom-thermal {
2418			polling-delay-passive = <250>;
2419			polling-delay = <1000>;
2420
2421			thermal-sensors = <&tsens0 12>;
2422
2423			trips {
2424				cpu5_bottom_alert0: trip-point0 {
2425					temperature = <90000>;
2426					hysteresis = <2000>;
2427					type = "passive";
2428				};
2429
2430				cpu5_bottom_alert1: trip-point1 {
2431					temperature = <95000>;
2432					hysteresis = <2000>;
2433					type = "passive";
2434				};
2435
2436				cpu5_bottom_crit: cpu_crit {
2437					temperature = <110000>;
2438					hysteresis = <1000>;
2439					type = "critical";
2440				};
2441			};
2442
2443			cooling-maps {
2444				map0 {
2445					trip = <&cpu5_bottom_alert0>;
2446					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2447							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2448							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2449							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2450				};
2451				map1 {
2452					trip = <&cpu5_bottom_alert1>;
2453					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2454							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2455							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2456							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2457				};
2458			};
2459		};
2460
2461		cpu6-bottom-thermal {
2462			polling-delay-passive = <250>;
2463			polling-delay = <1000>;
2464
2465			thermal-sensors = <&tsens0 13>;
2466
2467			trips {
2468				cpu6_bottom_alert0: trip-point0 {
2469					temperature = <90000>;
2470					hysteresis = <2000>;
2471					type = "passive";
2472				};
2473
2474				cpu6_bottom_alert1: trip-point1 {
2475					temperature = <95000>;
2476					hysteresis = <2000>;
2477					type = "passive";
2478				};
2479
2480				cpu6_bottom_crit: cpu_crit {
2481					temperature = <110000>;
2482					hysteresis = <1000>;
2483					type = "critical";
2484				};
2485			};
2486
2487			cooling-maps {
2488				map0 {
2489					trip = <&cpu6_bottom_alert0>;
2490					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2491							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2492							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2493							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2494				};
2495				map1 {
2496					trip = <&cpu6_bottom_alert1>;
2497					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2498							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2499							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2500							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2501				};
2502			};
2503		};
2504
2505		cpu7-bottom-thermal {
2506			polling-delay-passive = <250>;
2507			polling-delay = <1000>;
2508
2509			thermal-sensors = <&tsens0 14>;
2510
2511			trips {
2512				cpu7_bottom_alert0: trip-point0 {
2513					temperature = <90000>;
2514					hysteresis = <2000>;
2515					type = "passive";
2516				};
2517
2518				cpu7_bottom_alert1: trip-point1 {
2519					temperature = <95000>;
2520					hysteresis = <2000>;
2521					type = "passive";
2522				};
2523
2524				cpu7_bottom_crit: cpu_crit {
2525					temperature = <110000>;
2526					hysteresis = <1000>;
2527					type = "critical";
2528				};
2529			};
2530
2531			cooling-maps {
2532				map0 {
2533					trip = <&cpu7_bottom_alert0>;
2534					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2535							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2536							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2537							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2538				};
2539				map1 {
2540					trip = <&cpu7_bottom_alert1>;
2541					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2542							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2543							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2544							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2545				};
2546			};
2547		};
2548
2549		aoss0-thermal {
2550			polling-delay-passive = <250>;
2551			polling-delay = <1000>;
2552
2553			thermal-sensors = <&tsens0 0>;
2554
2555			trips {
2556				aoss0_alert0: trip-point0 {
2557					temperature = <90000>;
2558					hysteresis = <2000>;
2559					type = "hot";
2560				};
2561			};
2562		};
2563
2564		cluster0-thermal {
2565			polling-delay-passive = <250>;
2566			polling-delay = <1000>;
2567
2568			thermal-sensors = <&tsens0 5>;
2569
2570			trips {
2571				cluster0_alert0: trip-point0 {
2572					temperature = <90000>;
2573					hysteresis = <2000>;
2574					type = "hot";
2575				};
2576				cluster0_crit: cluster0_crit {
2577					temperature = <110000>;
2578					hysteresis = <2000>;
2579					type = "critical";
2580				};
2581			};
2582		};
2583
2584		cluster1-thermal {
2585			polling-delay-passive = <250>;
2586			polling-delay = <1000>;
2587
2588			thermal-sensors = <&tsens0 6>;
2589
2590			trips {
2591				cluster1_alert0: trip-point0 {
2592					temperature = <90000>;
2593					hysteresis = <2000>;
2594					type = "hot";
2595				};
2596				cluster1_crit: cluster1_crit {
2597					temperature = <110000>;
2598					hysteresis = <2000>;
2599					type = "critical";
2600				};
2601			};
2602		};
2603
2604		gpu-thermal-top {
2605			polling-delay-passive = <250>;
2606			polling-delay = <1000>;
2607
2608			thermal-sensors = <&tsens0 15>;
2609
2610			trips {
2611				gpu1_alert0: trip-point0 {
2612					temperature = <90000>;
2613					hysteresis = <2000>;
2614					type = "hot";
2615				};
2616			};
2617		};
2618
2619		aoss1-thermal {
2620			polling-delay-passive = <250>;
2621			polling-delay = <1000>;
2622
2623			thermal-sensors = <&tsens1 0>;
2624
2625			trips {
2626				aoss1_alert0: trip-point0 {
2627					temperature = <90000>;
2628					hysteresis = <2000>;
2629					type = "hot";
2630				};
2631			};
2632		};
2633
2634		wlan-thermal {
2635			polling-delay-passive = <250>;
2636			polling-delay = <1000>;
2637
2638			thermal-sensors = <&tsens1 1>;
2639
2640			trips {
2641				wlan_alert0: trip-point0 {
2642					temperature = <90000>;
2643					hysteresis = <2000>;
2644					type = "hot";
2645				};
2646			};
2647		};
2648
2649		video-thermal {
2650			polling-delay-passive = <250>;
2651			polling-delay = <1000>;
2652
2653			thermal-sensors = <&tsens1 2>;
2654
2655			trips {
2656				video_alert0: trip-point0 {
2657					temperature = <90000>;
2658					hysteresis = <2000>;
2659					type = "hot";
2660				};
2661			};
2662		};
2663
2664		mem-thermal {
2665			polling-delay-passive = <250>;
2666			polling-delay = <1000>;
2667
2668			thermal-sensors = <&tsens1 3>;
2669
2670			trips {
2671				mem_alert0: trip-point0 {
2672					temperature = <90000>;
2673					hysteresis = <2000>;
2674					type = "hot";
2675				};
2676			};
2677		};
2678
2679		q6-hvx-thermal {
2680			polling-delay-passive = <250>;
2681			polling-delay = <1000>;
2682
2683			thermal-sensors = <&tsens1 4>;
2684
2685			trips {
2686				q6_hvx_alert0: trip-point0 {
2687					temperature = <90000>;
2688					hysteresis = <2000>;
2689					type = "hot";
2690				};
2691			};
2692		};
2693
2694		camera-thermal {
2695			polling-delay-passive = <250>;
2696			polling-delay = <1000>;
2697
2698			thermal-sensors = <&tsens1 5>;
2699
2700			trips {
2701				camera_alert0: trip-point0 {
2702					temperature = <90000>;
2703					hysteresis = <2000>;
2704					type = "hot";
2705				};
2706			};
2707		};
2708
2709		compute-thermal {
2710			polling-delay-passive = <250>;
2711			polling-delay = <1000>;
2712
2713			thermal-sensors = <&tsens1 6>;
2714
2715			trips {
2716				compute_alert0: trip-point0 {
2717					temperature = <90000>;
2718					hysteresis = <2000>;
2719					type = "hot";
2720				};
2721			};
2722		};
2723
2724		modem-thermal {
2725			polling-delay-passive = <250>;
2726			polling-delay = <1000>;
2727
2728			thermal-sensors = <&tsens1 7>;
2729
2730			trips {
2731				modem_alert0: trip-point0 {
2732					temperature = <90000>;
2733					hysteresis = <2000>;
2734					type = "hot";
2735				};
2736			};
2737		};
2738
2739		npu-thermal {
2740			polling-delay-passive = <250>;
2741			polling-delay = <1000>;
2742
2743			thermal-sensors = <&tsens1 8>;
2744
2745			trips {
2746				npu_alert0: trip-point0 {
2747					temperature = <90000>;
2748					hysteresis = <2000>;
2749					type = "hot";
2750				};
2751			};
2752		};
2753
2754		modem-vec-thermal {
2755			polling-delay-passive = <250>;
2756			polling-delay = <1000>;
2757
2758			thermal-sensors = <&tsens1 9>;
2759
2760			trips {
2761				modem_vec_alert0: trip-point0 {
2762					temperature = <90000>;
2763					hysteresis = <2000>;
2764					type = "hot";
2765				};
2766			};
2767		};
2768
2769		modem-scl-thermal {
2770			polling-delay-passive = <250>;
2771			polling-delay = <1000>;
2772
2773			thermal-sensors = <&tsens1 10>;
2774
2775			trips {
2776				modem_scl_alert0: trip-point0 {
2777					temperature = <90000>;
2778					hysteresis = <2000>;
2779					type = "hot";
2780				};
2781			};
2782		};
2783
2784		gpu-thermal-bottom {
2785			polling-delay-passive = <250>;
2786			polling-delay = <1000>;
2787
2788			thermal-sensors = <&tsens1 11>;
2789
2790			trips {
2791				gpu2_alert0: trip-point0 {
2792					temperature = <90000>;
2793					hysteresis = <2000>;
2794					type = "hot";
2795				};
2796			};
2797		};
2798	};
2799};
2800