1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/dma/qcom-gpi.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/power/qcom-aoss-qmp.h> 10#include <dt-bindings/power/qcom-rpmpd.h> 11#include <dt-bindings/soc/qcom,rpmh-rsc.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,gcc-sm8150.h> 14#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/thermal/thermal.h> 17 18/ { 19 interrupt-parent = <&intc>; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 chosen { }; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <38400000>; 31 clock-output-names = "xo_board"; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32764>; 38 clock-output-names = "sleep_clk"; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "qcom,kryo485"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 capacity-dmips-mhz = <488>; 52 dynamic-power-coefficient = <232>; 53 next-level-cache = <&L2_0>; 54 qcom,freq-domain = <&cpufreq_hw 0>; 55 power-domains = <&CPU_PD0>; 56 power-domain-names = "psci"; 57 #cooling-cells = <2>; 58 L2_0: l2-cache { 59 compatible = "cache"; 60 next-level-cache = <&L3_0>; 61 L3_0: l3-cache { 62 compatible = "cache"; 63 }; 64 }; 65 }; 66 67 CPU1: cpu@100 { 68 device_type = "cpu"; 69 compatible = "qcom,kryo485"; 70 reg = <0x0 0x100>; 71 enable-method = "psci"; 72 capacity-dmips-mhz = <488>; 73 dynamic-power-coefficient = <232>; 74 next-level-cache = <&L2_100>; 75 qcom,freq-domain = <&cpufreq_hw 0>; 76 power-domains = <&CPU_PD1>; 77 power-domain-names = "psci"; 78 #cooling-cells = <2>; 79 L2_100: l2-cache { 80 compatible = "cache"; 81 next-level-cache = <&L3_0>; 82 }; 83 84 }; 85 86 CPU2: cpu@200 { 87 device_type = "cpu"; 88 compatible = "qcom,kryo485"; 89 reg = <0x0 0x200>; 90 enable-method = "psci"; 91 capacity-dmips-mhz = <488>; 92 dynamic-power-coefficient = <232>; 93 next-level-cache = <&L2_200>; 94 qcom,freq-domain = <&cpufreq_hw 0>; 95 power-domains = <&CPU_PD2>; 96 power-domain-names = "psci"; 97 #cooling-cells = <2>; 98 L2_200: l2-cache { 99 compatible = "cache"; 100 next-level-cache = <&L3_0>; 101 }; 102 }; 103 104 CPU3: cpu@300 { 105 device_type = "cpu"; 106 compatible = "qcom,kryo485"; 107 reg = <0x0 0x300>; 108 enable-method = "psci"; 109 capacity-dmips-mhz = <488>; 110 dynamic-power-coefficient = <232>; 111 next-level-cache = <&L2_300>; 112 qcom,freq-domain = <&cpufreq_hw 0>; 113 power-domains = <&CPU_PD3>; 114 power-domain-names = "psci"; 115 #cooling-cells = <2>; 116 L2_300: l2-cache { 117 compatible = "cache"; 118 next-level-cache = <&L3_0>; 119 }; 120 }; 121 122 CPU4: cpu@400 { 123 device_type = "cpu"; 124 compatible = "qcom,kryo485"; 125 reg = <0x0 0x400>; 126 enable-method = "psci"; 127 capacity-dmips-mhz = <1024>; 128 dynamic-power-coefficient = <369>; 129 next-level-cache = <&L2_400>; 130 qcom,freq-domain = <&cpufreq_hw 1>; 131 power-domains = <&CPU_PD4>; 132 power-domain-names = "psci"; 133 #cooling-cells = <2>; 134 L2_400: l2-cache { 135 compatible = "cache"; 136 next-level-cache = <&L3_0>; 137 }; 138 }; 139 140 CPU5: cpu@500 { 141 device_type = "cpu"; 142 compatible = "qcom,kryo485"; 143 reg = <0x0 0x500>; 144 enable-method = "psci"; 145 capacity-dmips-mhz = <1024>; 146 dynamic-power-coefficient = <369>; 147 next-level-cache = <&L2_500>; 148 qcom,freq-domain = <&cpufreq_hw 1>; 149 power-domains = <&CPU_PD5>; 150 power-domain-names = "psci"; 151 #cooling-cells = <2>; 152 L2_500: l2-cache { 153 compatible = "cache"; 154 next-level-cache = <&L3_0>; 155 }; 156 }; 157 158 CPU6: cpu@600 { 159 device_type = "cpu"; 160 compatible = "qcom,kryo485"; 161 reg = <0x0 0x600>; 162 enable-method = "psci"; 163 capacity-dmips-mhz = <1024>; 164 dynamic-power-coefficient = <369>; 165 next-level-cache = <&L2_600>; 166 qcom,freq-domain = <&cpufreq_hw 1>; 167 power-domains = <&CPU_PD6>; 168 power-domain-names = "psci"; 169 #cooling-cells = <2>; 170 L2_600: l2-cache { 171 compatible = "cache"; 172 next-level-cache = <&L3_0>; 173 }; 174 }; 175 176 CPU7: cpu@700 { 177 device_type = "cpu"; 178 compatible = "qcom,kryo485"; 179 reg = <0x0 0x700>; 180 enable-method = "psci"; 181 capacity-dmips-mhz = <1024>; 182 dynamic-power-coefficient = <421>; 183 next-level-cache = <&L2_700>; 184 qcom,freq-domain = <&cpufreq_hw 2>; 185 power-domains = <&CPU_PD7>; 186 power-domain-names = "psci"; 187 #cooling-cells = <2>; 188 L2_700: l2-cache { 189 compatible = "cache"; 190 next-level-cache = <&L3_0>; 191 }; 192 }; 193 194 cpu-map { 195 cluster0 { 196 core0 { 197 cpu = <&CPU0>; 198 }; 199 200 core1 { 201 cpu = <&CPU1>; 202 }; 203 204 core2 { 205 cpu = <&CPU2>; 206 }; 207 208 core3 { 209 cpu = <&CPU3>; 210 }; 211 212 core4 { 213 cpu = <&CPU4>; 214 }; 215 216 core5 { 217 cpu = <&CPU5>; 218 }; 219 220 core6 { 221 cpu = <&CPU6>; 222 }; 223 224 core7 { 225 cpu = <&CPU7>; 226 }; 227 }; 228 }; 229 230 idle-states { 231 entry-method = "psci"; 232 233 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 234 compatible = "arm,idle-state"; 235 idle-state-name = "little-rail-power-collapse"; 236 arm,psci-suspend-param = <0x40000004>; 237 entry-latency-us = <355>; 238 exit-latency-us = <909>; 239 min-residency-us = <3934>; 240 local-timer-stop; 241 }; 242 243 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 244 compatible = "arm,idle-state"; 245 idle-state-name = "big-rail-power-collapse"; 246 arm,psci-suspend-param = <0x40000004>; 247 entry-latency-us = <241>; 248 exit-latency-us = <1461>; 249 min-residency-us = <4488>; 250 local-timer-stop; 251 }; 252 }; 253 254 domain-idle-states { 255 CLUSTER_SLEEP_0: cluster-sleep-0 { 256 compatible = "domain-idle-state"; 257 idle-state-name = "cluster-power-collapse"; 258 arm,psci-suspend-param = <0x4100c244>; 259 entry-latency-us = <3263>; 260 exit-latency-us = <6562>; 261 min-residency-us = <9987>; 262 local-timer-stop; 263 }; 264 }; 265 }; 266 267 firmware { 268 scm: scm { 269 compatible = "qcom,scm-sm8150", "qcom,scm"; 270 #reset-cells = <1>; 271 }; 272 }; 273 274 tcsr_mutex: hwlock { 275 compatible = "qcom,tcsr-mutex"; 276 syscon = <&tcsr_mutex_regs 0 0x1000>; 277 #hwlock-cells = <1>; 278 }; 279 280 memory@80000000 { 281 device_type = "memory"; 282 /* We expect the bootloader to fill in the size */ 283 reg = <0x0 0x80000000 0x0 0x0>; 284 }; 285 286 pmu { 287 compatible = "arm,armv8-pmuv3"; 288 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 289 }; 290 291 psci { 292 compatible = "arm,psci-1.0"; 293 method = "smc"; 294 295 CPU_PD0: cpu0 { 296 #power-domain-cells = <0>; 297 power-domains = <&CLUSTER_PD>; 298 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 299 }; 300 301 CPU_PD1: cpu1 { 302 #power-domain-cells = <0>; 303 power-domains = <&CLUSTER_PD>; 304 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 305 }; 306 307 CPU_PD2: cpu2 { 308 #power-domain-cells = <0>; 309 power-domains = <&CLUSTER_PD>; 310 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 311 }; 312 313 CPU_PD3: cpu3 { 314 #power-domain-cells = <0>; 315 power-domains = <&CLUSTER_PD>; 316 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 317 }; 318 319 CPU_PD4: cpu4 { 320 #power-domain-cells = <0>; 321 power-domains = <&CLUSTER_PD>; 322 domain-idle-states = <&BIG_CPU_SLEEP_0>; 323 }; 324 325 CPU_PD5: cpu5 { 326 #power-domain-cells = <0>; 327 power-domains = <&CLUSTER_PD>; 328 domain-idle-states = <&BIG_CPU_SLEEP_0>; 329 }; 330 331 CPU_PD6: cpu6 { 332 #power-domain-cells = <0>; 333 power-domains = <&CLUSTER_PD>; 334 domain-idle-states = <&BIG_CPU_SLEEP_0>; 335 }; 336 337 CPU_PD7: cpu7 { 338 #power-domain-cells = <0>; 339 power-domains = <&CLUSTER_PD>; 340 domain-idle-states = <&BIG_CPU_SLEEP_0>; 341 }; 342 343 CLUSTER_PD: cpu-cluster0 { 344 #power-domain-cells = <0>; 345 domain-idle-states = <&CLUSTER_SLEEP_0>; 346 }; 347 }; 348 349 reserved-memory { 350 #address-cells = <2>; 351 #size-cells = <2>; 352 ranges; 353 354 hyp_mem: memory@85700000 { 355 reg = <0x0 0x85700000 0x0 0x600000>; 356 no-map; 357 }; 358 359 xbl_mem: memory@85d00000 { 360 reg = <0x0 0x85d00000 0x0 0x140000>; 361 no-map; 362 }; 363 364 aop_mem: memory@85f00000 { 365 reg = <0x0 0x85f00000 0x0 0x20000>; 366 no-map; 367 }; 368 369 aop_cmd_db: memory@85f20000 { 370 compatible = "qcom,cmd-db"; 371 reg = <0x0 0x85f20000 0x0 0x20000>; 372 no-map; 373 }; 374 375 smem_mem: memory@86000000 { 376 reg = <0x0 0x86000000 0x0 0x200000>; 377 no-map; 378 }; 379 380 tz_mem: memory@86200000 { 381 reg = <0x0 0x86200000 0x0 0x3900000>; 382 no-map; 383 }; 384 385 rmtfs_mem: memory@89b00000 { 386 compatible = "qcom,rmtfs-mem"; 387 reg = <0x0 0x89b00000 0x0 0x200000>; 388 no-map; 389 390 qcom,client-id = <1>; 391 qcom,vmid = <15>; 392 }; 393 394 camera_mem: memory@8b700000 { 395 reg = <0x0 0x8b700000 0x0 0x500000>; 396 no-map; 397 }; 398 399 wlan_mem: memory@8bc00000 { 400 reg = <0x0 0x8bc00000 0x0 0x180000>; 401 no-map; 402 }; 403 404 npu_mem: memory@8bd80000 { 405 reg = <0x0 0x8bd80000 0x0 0x80000>; 406 no-map; 407 }; 408 409 adsp_mem: memory@8be00000 { 410 reg = <0x0 0x8be00000 0x0 0x1a00000>; 411 no-map; 412 }; 413 414 mpss_mem: memory@8d800000 { 415 reg = <0x0 0x8d800000 0x0 0x9600000>; 416 no-map; 417 }; 418 419 venus_mem: memory@96e00000 { 420 reg = <0x0 0x96e00000 0x0 0x500000>; 421 no-map; 422 }; 423 424 slpi_mem: memory@97300000 { 425 reg = <0x0 0x97300000 0x0 0x1400000>; 426 no-map; 427 }; 428 429 ipa_fw_mem: memory@98700000 { 430 reg = <0x0 0x98700000 0x0 0x10000>; 431 no-map; 432 }; 433 434 ipa_gsi_mem: memory@98710000 { 435 reg = <0x0 0x98710000 0x0 0x5000>; 436 no-map; 437 }; 438 439 gpu_mem: memory@98715000 { 440 reg = <0x0 0x98715000 0x0 0x2000>; 441 no-map; 442 }; 443 444 spss_mem: memory@98800000 { 445 reg = <0x0 0x98800000 0x0 0x100000>; 446 no-map; 447 }; 448 449 cdsp_mem: memory@98900000 { 450 reg = <0x0 0x98900000 0x0 0x1400000>; 451 no-map; 452 }; 453 454 qseecom_mem: memory@9e400000 { 455 reg = <0x0 0x9e400000 0x0 0x1400000>; 456 no-map; 457 }; 458 }; 459 460 smem { 461 compatible = "qcom,smem"; 462 memory-region = <&smem_mem>; 463 hwlocks = <&tcsr_mutex 3>; 464 }; 465 466 smp2p-cdsp { 467 compatible = "qcom,smp2p"; 468 qcom,smem = <94>, <432>; 469 470 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 471 472 mboxes = <&apss_shared 6>; 473 474 qcom,local-pid = <0>; 475 qcom,remote-pid = <5>; 476 477 cdsp_smp2p_out: master-kernel { 478 qcom,entry-name = "master-kernel"; 479 #qcom,smem-state-cells = <1>; 480 }; 481 482 cdsp_smp2p_in: slave-kernel { 483 qcom,entry-name = "slave-kernel"; 484 485 interrupt-controller; 486 #interrupt-cells = <2>; 487 }; 488 }; 489 490 smp2p-lpass { 491 compatible = "qcom,smp2p"; 492 qcom,smem = <443>, <429>; 493 494 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 495 496 mboxes = <&apss_shared 10>; 497 498 qcom,local-pid = <0>; 499 qcom,remote-pid = <2>; 500 501 adsp_smp2p_out: master-kernel { 502 qcom,entry-name = "master-kernel"; 503 #qcom,smem-state-cells = <1>; 504 }; 505 506 adsp_smp2p_in: slave-kernel { 507 qcom,entry-name = "slave-kernel"; 508 509 interrupt-controller; 510 #interrupt-cells = <2>; 511 }; 512 }; 513 514 smp2p-mpss { 515 compatible = "qcom,smp2p"; 516 qcom,smem = <435>, <428>; 517 518 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 519 520 mboxes = <&apss_shared 14>; 521 522 qcom,local-pid = <0>; 523 qcom,remote-pid = <1>; 524 525 modem_smp2p_out: master-kernel { 526 qcom,entry-name = "master-kernel"; 527 #qcom,smem-state-cells = <1>; 528 }; 529 530 modem_smp2p_in: slave-kernel { 531 qcom,entry-name = "slave-kernel"; 532 533 interrupt-controller; 534 #interrupt-cells = <2>; 535 }; 536 }; 537 538 smp2p-slpi { 539 compatible = "qcom,smp2p"; 540 qcom,smem = <481>, <430>; 541 542 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 543 544 mboxes = <&apss_shared 26>; 545 546 qcom,local-pid = <0>; 547 qcom,remote-pid = <3>; 548 549 slpi_smp2p_out: master-kernel { 550 qcom,entry-name = "master-kernel"; 551 #qcom,smem-state-cells = <1>; 552 }; 553 554 slpi_smp2p_in: slave-kernel { 555 qcom,entry-name = "slave-kernel"; 556 557 interrupt-controller; 558 #interrupt-cells = <2>; 559 }; 560 }; 561 562 soc: soc@0 { 563 #address-cells = <2>; 564 #size-cells = <2>; 565 ranges = <0 0 0 0 0x10 0>; 566 dma-ranges = <0 0 0 0 0x10 0>; 567 compatible = "simple-bus"; 568 569 gcc: clock-controller@100000 { 570 compatible = "qcom,gcc-sm8150"; 571 reg = <0x0 0x00100000 0x0 0x1f0000>; 572 #clock-cells = <1>; 573 #reset-cells = <1>; 574 #power-domain-cells = <1>; 575 clock-names = "bi_tcxo", 576 "sleep_clk"; 577 clocks = <&rpmhcc RPMH_CXO_CLK>, 578 <&sleep_clk>; 579 }; 580 581 gpi_dma0: dma-controller@800000 { 582 compatible = "qcom,sm8150-gpi-dma"; 583 reg = <0 0x800000 0 0x60000>; 584 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 597 dma-channels = <13>; 598 dma-channel-mask = <0xfa>; 599 iommus = <&apps_smmu 0x00d6 0x0>; 600 #dma-cells = <3>; 601 status = "disabled"; 602 }; 603 604 qupv3_id_0: geniqup@8c0000 { 605 compatible = "qcom,geni-se-qup"; 606 reg = <0x0 0x008c0000 0x0 0x6000>; 607 clock-names = "m-ahb", "s-ahb"; 608 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 609 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 610 iommus = <&apps_smmu 0xc3 0x0>; 611 #address-cells = <2>; 612 #size-cells = <2>; 613 ranges; 614 status = "disabled"; 615 616 i2c0: i2c@880000 { 617 compatible = "qcom,geni-i2c"; 618 reg = <0 0x00880000 0 0x4000>; 619 clock-names = "se"; 620 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 621 pinctrl-names = "default"; 622 pinctrl-0 = <&qup_i2c0_default>; 623 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 624 #address-cells = <1>; 625 #size-cells = <0>; 626 status = "disabled"; 627 }; 628 629 i2c1: i2c@884000 { 630 compatible = "qcom,geni-i2c"; 631 reg = <0 0x00884000 0 0x4000>; 632 clock-names = "se"; 633 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 634 pinctrl-names = "default"; 635 pinctrl-0 = <&qup_i2c1_default>; 636 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 637 #address-cells = <1>; 638 #size-cells = <0>; 639 status = "disabled"; 640 }; 641 642 i2c2: i2c@888000 { 643 compatible = "qcom,geni-i2c"; 644 reg = <0 0x00888000 0 0x4000>; 645 clock-names = "se"; 646 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 647 pinctrl-names = "default"; 648 pinctrl-0 = <&qup_i2c2_default>; 649 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 status = "disabled"; 653 }; 654 655 i2c3: i2c@88c000 { 656 compatible = "qcom,geni-i2c"; 657 reg = <0 0x0088c000 0 0x4000>; 658 clock-names = "se"; 659 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 660 pinctrl-names = "default"; 661 pinctrl-0 = <&qup_i2c3_default>; 662 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 status = "disabled"; 666 }; 667 668 i2c4: i2c@890000 { 669 compatible = "qcom,geni-i2c"; 670 reg = <0 0x00890000 0 0x4000>; 671 clock-names = "se"; 672 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 673 pinctrl-names = "default"; 674 pinctrl-0 = <&qup_i2c4_default>; 675 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 676 #address-cells = <1>; 677 #size-cells = <0>; 678 status = "disabled"; 679 }; 680 681 i2c5: i2c@894000 { 682 compatible = "qcom,geni-i2c"; 683 reg = <0 0x00894000 0 0x4000>; 684 clock-names = "se"; 685 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 686 pinctrl-names = "default"; 687 pinctrl-0 = <&qup_i2c5_default>; 688 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 status = "disabled"; 692 }; 693 694 i2c6: i2c@898000 { 695 compatible = "qcom,geni-i2c"; 696 reg = <0 0x00898000 0 0x4000>; 697 clock-names = "se"; 698 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 699 pinctrl-names = "default"; 700 pinctrl-0 = <&qup_i2c6_default>; 701 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 status = "disabled"; 705 }; 706 707 i2c7: i2c@89c000 { 708 compatible = "qcom,geni-i2c"; 709 reg = <0 0x0089c000 0 0x4000>; 710 clock-names = "se"; 711 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 712 pinctrl-names = "default"; 713 pinctrl-0 = <&qup_i2c7_default>; 714 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 715 #address-cells = <1>; 716 #size-cells = <0>; 717 status = "disabled"; 718 }; 719 720 }; 721 722 gpi_dma1: dma-controller@a00000 { 723 compatible = "qcom,sm8150-gpi-dma"; 724 reg = <0 0xa00000 0 0x60000>; 725 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 738 dma-channels = <13>; 739 dma-channel-mask = <0xfa>; 740 iommus = <&apps_smmu 0x0616 0x0>; 741 #dma-cells = <3>; 742 status = "disabled"; 743 }; 744 745 qupv3_id_1: geniqup@ac0000 { 746 compatible = "qcom,geni-se-qup"; 747 reg = <0x0 0x00ac0000 0x0 0x6000>; 748 clock-names = "m-ahb", "s-ahb"; 749 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 750 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 751 iommus = <&apps_smmu 0x603 0x0>; 752 #address-cells = <2>; 753 #size-cells = <2>; 754 ranges; 755 status = "disabled"; 756 757 i2c8: i2c@a80000 { 758 compatible = "qcom,geni-i2c"; 759 reg = <0 0x00a80000 0 0x4000>; 760 clock-names = "se"; 761 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 762 pinctrl-names = "default"; 763 pinctrl-0 = <&qup_i2c8_default>; 764 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 765 #address-cells = <1>; 766 #size-cells = <0>; 767 status = "disabled"; 768 }; 769 770 i2c9: i2c@a84000 { 771 compatible = "qcom,geni-i2c"; 772 reg = <0 0x00a84000 0 0x4000>; 773 clock-names = "se"; 774 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 775 pinctrl-names = "default"; 776 pinctrl-0 = <&qup_i2c9_default>; 777 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 status = "disabled"; 781 }; 782 783 i2c10: i2c@a88000 { 784 compatible = "qcom,geni-i2c"; 785 reg = <0 0x00a88000 0 0x4000>; 786 clock-names = "se"; 787 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 788 pinctrl-names = "default"; 789 pinctrl-0 = <&qup_i2c10_default>; 790 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 791 #address-cells = <1>; 792 #size-cells = <0>; 793 status = "disabled"; 794 }; 795 796 i2c11: i2c@a8c000 { 797 compatible = "qcom,geni-i2c"; 798 reg = <0 0x00a8c000 0 0x4000>; 799 clock-names = "se"; 800 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 801 pinctrl-names = "default"; 802 pinctrl-0 = <&qup_i2c11_default>; 803 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 804 #address-cells = <1>; 805 #size-cells = <0>; 806 status = "disabled"; 807 }; 808 809 uart2: serial@a90000 { 810 compatible = "qcom,geni-debug-uart"; 811 reg = <0x0 0x00a90000 0x0 0x4000>; 812 clock-names = "se"; 813 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 814 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 815 status = "disabled"; 816 }; 817 818 i2c12: i2c@a90000 { 819 compatible = "qcom,geni-i2c"; 820 reg = <0 0x00a90000 0 0x4000>; 821 clock-names = "se"; 822 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 823 pinctrl-names = "default"; 824 pinctrl-0 = <&qup_i2c12_default>; 825 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 826 #address-cells = <1>; 827 #size-cells = <0>; 828 status = "disabled"; 829 }; 830 831 i2c16: i2c@94000 { 832 compatible = "qcom,geni-i2c"; 833 reg = <0 0x0094000 0 0x4000>; 834 clock-names = "se"; 835 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 836 pinctrl-names = "default"; 837 pinctrl-0 = <&qup_i2c16_default>; 838 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 status = "disabled"; 842 }; 843 }; 844 845 gpi_dma2: dma-controller@c00000 { 846 compatible = "qcom,sm8150-gpi-dma"; 847 reg = <0 0xc00000 0 0x60000>; 848 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 861 dma-channels = <13>; 862 dma-channel-mask = <0xfa>; 863 iommus = <&apps_smmu 0x07b6 0x0>; 864 #dma-cells = <3>; 865 status = "disabled"; 866 }; 867 868 qupv3_id_2: geniqup@cc0000 { 869 compatible = "qcom,geni-se-qup"; 870 reg = <0x0 0x00cc0000 0x0 0x6000>; 871 872 clock-names = "m-ahb", "s-ahb"; 873 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 874 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 875 iommus = <&apps_smmu 0x7a3 0x0>; 876 #address-cells = <2>; 877 #size-cells = <2>; 878 ranges; 879 status = "disabled"; 880 881 i2c17: i2c@c80000 { 882 compatible = "qcom,geni-i2c"; 883 reg = <0 0x00c80000 0 0x4000>; 884 clock-names = "se"; 885 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 886 pinctrl-names = "default"; 887 pinctrl-0 = <&qup_i2c17_default>; 888 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 889 #address-cells = <1>; 890 #size-cells = <0>; 891 status = "disabled"; 892 }; 893 894 i2c18: i2c@c84000 { 895 compatible = "qcom,geni-i2c"; 896 reg = <0 0x00c84000 0 0x4000>; 897 clock-names = "se"; 898 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 899 pinctrl-names = "default"; 900 pinctrl-0 = <&qup_i2c18_default>; 901 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 902 #address-cells = <1>; 903 #size-cells = <0>; 904 status = "disabled"; 905 }; 906 907 i2c19: i2c@c88000 { 908 compatible = "qcom,geni-i2c"; 909 reg = <0 0x00c88000 0 0x4000>; 910 clock-names = "se"; 911 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&qup_i2c19_default>; 914 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 status = "disabled"; 918 }; 919 920 i2c13: i2c@c8c000 { 921 compatible = "qcom,geni-i2c"; 922 reg = <0 0x00c8c000 0 0x4000>; 923 clock-names = "se"; 924 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 925 pinctrl-names = "default"; 926 pinctrl-0 = <&qup_i2c13_default>; 927 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 928 #address-cells = <1>; 929 #size-cells = <0>; 930 status = "disabled"; 931 }; 932 933 i2c14: i2c@c90000 { 934 compatible = "qcom,geni-i2c"; 935 reg = <0 0x00c90000 0 0x4000>; 936 clock-names = "se"; 937 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 938 pinctrl-names = "default"; 939 pinctrl-0 = <&qup_i2c14_default>; 940 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 status = "disabled"; 944 }; 945 946 i2c15: i2c@c94000 { 947 compatible = "qcom,geni-i2c"; 948 reg = <0 0x00c94000 0 0x4000>; 949 clock-names = "se"; 950 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 951 pinctrl-names = "default"; 952 pinctrl-0 = <&qup_i2c15_default>; 953 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 status = "disabled"; 957 }; 958 }; 959 960 config_noc: interconnect@1500000 { 961 compatible = "qcom,sm8150-config-noc"; 962 reg = <0 0x01500000 0 0x7400>; 963 #interconnect-cells = <1>; 964 qcom,bcm-voters = <&apps_bcm_voter>; 965 }; 966 967 system_noc: interconnect@1620000 { 968 compatible = "qcom,sm8150-system-noc"; 969 reg = <0 0x01620000 0 0x19400>; 970 #interconnect-cells = <1>; 971 qcom,bcm-voters = <&apps_bcm_voter>; 972 }; 973 974 mc_virt: interconnect@163a000 { 975 compatible = "qcom,sm8150-mc-virt"; 976 reg = <0 0x0163a000 0 0x1000>; 977 #interconnect-cells = <1>; 978 qcom,bcm-voters = <&apps_bcm_voter>; 979 }; 980 981 aggre1_noc: interconnect@16e0000 { 982 compatible = "qcom,sm8150-aggre1-noc"; 983 reg = <0 0x016e0000 0 0xd080>; 984 #interconnect-cells = <1>; 985 qcom,bcm-voters = <&apps_bcm_voter>; 986 }; 987 988 aggre2_noc: interconnect@1700000 { 989 compatible = "qcom,sm8150-aggre2-noc"; 990 reg = <0 0x01700000 0 0x20000>; 991 #interconnect-cells = <1>; 992 qcom,bcm-voters = <&apps_bcm_voter>; 993 }; 994 995 compute_noc: interconnect@1720000 { 996 compatible = "qcom,sm8150-compute-noc"; 997 reg = <0 0x01720000 0 0x7000>; 998 #interconnect-cells = <1>; 999 qcom,bcm-voters = <&apps_bcm_voter>; 1000 }; 1001 1002 mmss_noc: interconnect@1740000 { 1003 compatible = "qcom,sm8150-mmss-noc"; 1004 reg = <0 0x01740000 0 0x1c100>; 1005 #interconnect-cells = <1>; 1006 qcom,bcm-voters = <&apps_bcm_voter>; 1007 }; 1008 1009 system-cache-controller@9200000 { 1010 compatible = "qcom,sm8150-llcc"; 1011 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 1012 reg-names = "llcc_base", "llcc_broadcast_base"; 1013 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1014 }; 1015 1016 ufs_mem_hc: ufshc@1d84000 { 1017 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 1018 "jedec,ufs-2.0"; 1019 reg = <0 0x01d84000 0 0x2500>; 1020 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1021 phys = <&ufs_mem_phy_lanes>; 1022 phy-names = "ufsphy"; 1023 lanes-per-direction = <2>; 1024 #reset-cells = <1>; 1025 resets = <&gcc GCC_UFS_PHY_BCR>; 1026 reset-names = "rst"; 1027 1028 iommus = <&apps_smmu 0x300 0>; 1029 1030 clock-names = 1031 "core_clk", 1032 "bus_aggr_clk", 1033 "iface_clk", 1034 "core_clk_unipro", 1035 "ref_clk", 1036 "tx_lane0_sync_clk", 1037 "rx_lane0_sync_clk", 1038 "rx_lane1_sync_clk"; 1039 clocks = 1040 <&gcc GCC_UFS_PHY_AXI_CLK>, 1041 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1042 <&gcc GCC_UFS_PHY_AHB_CLK>, 1043 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1044 <&rpmhcc RPMH_CXO_CLK>, 1045 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1046 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1047 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1048 freq-table-hz = 1049 <37500000 300000000>, 1050 <0 0>, 1051 <0 0>, 1052 <37500000 300000000>, 1053 <0 0>, 1054 <0 0>, 1055 <0 0>, 1056 <0 0>; 1057 1058 status = "disabled"; 1059 }; 1060 1061 ufs_mem_phy: phy@1d87000 { 1062 compatible = "qcom,sm8150-qmp-ufs-phy"; 1063 reg = <0 0x01d87000 0 0x1c0>; 1064 #address-cells = <2>; 1065 #size-cells = <2>; 1066 ranges; 1067 clock-names = "ref", 1068 "ref_aux"; 1069 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 1070 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1071 1072 resets = <&ufs_mem_hc 0>; 1073 reset-names = "ufsphy"; 1074 status = "disabled"; 1075 1076 ufs_mem_phy_lanes: lanes@1d87400 { 1077 reg = <0 0x01d87400 0 0x108>, 1078 <0 0x01d87600 0 0x1e0>, 1079 <0 0x01d87c00 0 0x1dc>, 1080 <0 0x01d87800 0 0x108>, 1081 <0 0x01d87a00 0 0x1e0>; 1082 #phy-cells = <0>; 1083 }; 1084 }; 1085 1086 ipa_virt: interconnect@1e00000 { 1087 compatible = "qcom,sm8150-ipa-virt"; 1088 reg = <0 0x01e00000 0 0x1000>; 1089 #interconnect-cells = <1>; 1090 qcom,bcm-voters = <&apps_bcm_voter>; 1091 }; 1092 1093 tcsr_mutex_regs: syscon@1f40000 { 1094 compatible = "syscon"; 1095 reg = <0x0 0x01f40000 0x0 0x40000>; 1096 }; 1097 1098 remoteproc_slpi: remoteproc@2400000 { 1099 compatible = "qcom,sm8150-slpi-pas"; 1100 reg = <0x0 0x02400000 0x0 0x4040>; 1101 1102 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 1103 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1104 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1105 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1106 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1107 interrupt-names = "wdog", "fatal", "ready", 1108 "handover", "stop-ack"; 1109 1110 clocks = <&rpmhcc RPMH_CXO_CLK>; 1111 clock-names = "xo"; 1112 1113 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, 1114 <&rpmhpd 3>, 1115 <&rpmhpd 2>; 1116 power-domain-names = "load_state", "lcx", "lmx"; 1117 1118 memory-region = <&slpi_mem>; 1119 1120 qcom,smem-states = <&slpi_smp2p_out 0>; 1121 qcom,smem-state-names = "stop"; 1122 1123 status = "disabled"; 1124 1125 glink-edge { 1126 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 1127 label = "dsps"; 1128 qcom,remote-pid = <3>; 1129 mboxes = <&apss_shared 24>; 1130 }; 1131 }; 1132 1133 gpu: gpu@2c00000 { 1134 /* 1135 * note: the amd,imageon compatible makes it possible 1136 * to use the drm/msm driver without the display node, 1137 * make sure to remove it when display node is added 1138 */ 1139 compatible = "qcom,adreno-640.1", 1140 "qcom,adreno", 1141 "amd,imageon"; 1142 #stream-id-cells = <16>; 1143 1144 reg = <0 0x02c00000 0 0x40000>; 1145 reg-names = "kgsl_3d0_reg_memory"; 1146 1147 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1148 1149 iommus = <&adreno_smmu 0 0x401>; 1150 1151 operating-points-v2 = <&gpu_opp_table>; 1152 1153 qcom,gmu = <&gmu>; 1154 1155 status = "disabled"; 1156 1157 zap-shader { 1158 memory-region = <&gpu_mem>; 1159 }; 1160 1161 /* note: downstream checks gpu binning for 675 Mhz */ 1162 gpu_opp_table: opp-table { 1163 compatible = "operating-points-v2"; 1164 1165 opp-675000000 { 1166 opp-hz = /bits/ 64 <675000000>; 1167 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1168 }; 1169 1170 opp-585000000 { 1171 opp-hz = /bits/ 64 <585000000>; 1172 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1173 }; 1174 1175 opp-499200000 { 1176 opp-hz = /bits/ 64 <499200000>; 1177 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1178 }; 1179 1180 opp-427000000 { 1181 opp-hz = /bits/ 64 <427000000>; 1182 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1183 }; 1184 1185 opp-345000000 { 1186 opp-hz = /bits/ 64 <345000000>; 1187 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1188 }; 1189 1190 opp-257000000 { 1191 opp-hz = /bits/ 64 <257000000>; 1192 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1193 }; 1194 }; 1195 }; 1196 1197 gmu: gmu@2c6a000 { 1198 compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 1199 1200 reg = <0 0x02c6a000 0 0x30000>, 1201 <0 0x0b290000 0 0x10000>, 1202 <0 0x0b490000 0 0x10000>; 1203 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 1204 1205 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1207 interrupt-names = "hfi", "gmu"; 1208 1209 clocks = <&gpucc GPU_CC_AHB_CLK>, 1210 <&gpucc GPU_CC_CX_GMU_CLK>, 1211 <&gpucc GPU_CC_CXO_CLK>, 1212 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1213 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1214 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 1215 1216 power-domains = <&gpucc GPU_CX_GDSC>, 1217 <&gpucc GPU_GX_GDSC>; 1218 power-domain-names = "cx", "gx"; 1219 1220 iommus = <&adreno_smmu 5 0x400>; 1221 1222 operating-points-v2 = <&gmu_opp_table>; 1223 1224 status = "disabled"; 1225 1226 gmu_opp_table: opp-table { 1227 compatible = "operating-points-v2"; 1228 1229 opp-200000000 { 1230 opp-hz = /bits/ 64 <200000000>; 1231 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1232 }; 1233 }; 1234 }; 1235 1236 gpucc: clock-controller@2c90000 { 1237 compatible = "qcom,sm8150-gpucc"; 1238 reg = <0 0x02c90000 0 0x9000>; 1239 clocks = <&rpmhcc RPMH_CXO_CLK>, 1240 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1241 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1242 clock-names = "bi_tcxo", 1243 "gcc_gpu_gpll0_clk_src", 1244 "gcc_gpu_gpll0_div_clk_src"; 1245 #clock-cells = <1>; 1246 #reset-cells = <1>; 1247 #power-domain-cells = <1>; 1248 }; 1249 1250 adreno_smmu: iommu@2ca0000 { 1251 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 1252 reg = <0 0x02ca0000 0 0x10000>; 1253 #iommu-cells = <2>; 1254 #global-interrupts = <1>; 1255 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1259 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1261 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1262 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 1264 clocks = <&gpucc GPU_CC_AHB_CLK>, 1265 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1266 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1267 clock-names = "ahb", "bus", "iface"; 1268 1269 power-domains = <&gpucc GPU_CX_GDSC>; 1270 }; 1271 1272 tlmm: pinctrl@3100000 { 1273 compatible = "qcom,sm8150-pinctrl"; 1274 reg = <0x0 0x03100000 0x0 0x300000>, 1275 <0x0 0x03500000 0x0 0x300000>, 1276 <0x0 0x03900000 0x0 0x300000>, 1277 <0x0 0x03D00000 0x0 0x300000>; 1278 reg-names = "west", "east", "north", "south"; 1279 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1280 gpio-ranges = <&tlmm 0 0 176>; 1281 gpio-controller; 1282 #gpio-cells = <2>; 1283 interrupt-controller; 1284 #interrupt-cells = <2>; 1285 1286 qup_i2c0_default: qup-i2c0-default { 1287 mux { 1288 pins = "gpio0", "gpio1"; 1289 function = "qup0"; 1290 }; 1291 1292 config { 1293 pins = "gpio0", "gpio1"; 1294 drive-strength = <0x02>; 1295 bias-disable; 1296 }; 1297 }; 1298 1299 qup_i2c1_default: qup-i2c1-default { 1300 mux { 1301 pins = "gpio114", "gpio115"; 1302 function = "qup1"; 1303 }; 1304 1305 config { 1306 pins = "gpio114", "gpio115"; 1307 drive-strength = <0x02>; 1308 bias-disable; 1309 }; 1310 }; 1311 1312 qup_i2c2_default: qup-i2c2-default { 1313 mux { 1314 pins = "gpio126", "gpio127"; 1315 function = "qup2"; 1316 }; 1317 1318 config { 1319 pins = "gpio126", "gpio127"; 1320 drive-strength = <0x02>; 1321 bias-disable; 1322 }; 1323 }; 1324 1325 qup_i2c3_default: qup-i2c3-default { 1326 mux { 1327 pins = "gpio144", "gpio145"; 1328 function = "qup3"; 1329 }; 1330 1331 config { 1332 pins = "gpio144", "gpio145"; 1333 drive-strength = <0x02>; 1334 bias-disable; 1335 }; 1336 }; 1337 1338 qup_i2c4_default: qup-i2c4-default { 1339 mux { 1340 pins = "gpio51", "gpio52"; 1341 function = "qup4"; 1342 }; 1343 1344 config { 1345 pins = "gpio51", "gpio52"; 1346 drive-strength = <0x02>; 1347 bias-disable; 1348 }; 1349 }; 1350 1351 qup_i2c5_default: qup-i2c5-default { 1352 mux { 1353 pins = "gpio121", "gpio122"; 1354 function = "qup5"; 1355 }; 1356 1357 config { 1358 pins = "gpio121", "gpio122"; 1359 drive-strength = <0x02>; 1360 bias-disable; 1361 }; 1362 }; 1363 1364 qup_i2c6_default: qup-i2c6-default { 1365 mux { 1366 pins = "gpio6", "gpio7"; 1367 function = "qup6"; 1368 }; 1369 1370 config { 1371 pins = "gpio6", "gpio7"; 1372 drive-strength = <0x02>; 1373 bias-disable; 1374 }; 1375 }; 1376 1377 qup_i2c7_default: qup-i2c7-default { 1378 mux { 1379 pins = "gpio98", "gpio99"; 1380 function = "qup7"; 1381 }; 1382 1383 config { 1384 pins = "gpio98", "gpio99"; 1385 drive-strength = <0x02>; 1386 bias-disable; 1387 }; 1388 }; 1389 1390 qup_i2c8_default: qup-i2c8-default { 1391 mux { 1392 pins = "gpio88", "gpio89"; 1393 function = "qup8"; 1394 }; 1395 1396 config { 1397 pins = "gpio88", "gpio89"; 1398 drive-strength = <0x02>; 1399 bias-disable; 1400 }; 1401 }; 1402 1403 qup_i2c9_default: qup-i2c9-default { 1404 mux { 1405 pins = "gpio39", "gpio40"; 1406 function = "qup9"; 1407 }; 1408 1409 config { 1410 pins = "gpio39", "gpio40"; 1411 drive-strength = <0x02>; 1412 bias-disable; 1413 }; 1414 }; 1415 1416 qup_i2c10_default: qup-i2c10-default { 1417 mux { 1418 pins = "gpio9", "gpio10"; 1419 function = "qup10"; 1420 }; 1421 1422 config { 1423 pins = "gpio9", "gpio10"; 1424 drive-strength = <0x02>; 1425 bias-disable; 1426 }; 1427 }; 1428 1429 qup_i2c11_default: qup-i2c11-default { 1430 mux { 1431 pins = "gpio94", "gpio95"; 1432 function = "qup11"; 1433 }; 1434 1435 config { 1436 pins = "gpio94", "gpio95"; 1437 drive-strength = <0x02>; 1438 bias-disable; 1439 }; 1440 }; 1441 1442 qup_i2c12_default: qup-i2c12-default { 1443 mux { 1444 pins = "gpio83", "gpio84"; 1445 function = "qup12"; 1446 }; 1447 1448 config { 1449 pins = "gpio83", "gpio84"; 1450 drive-strength = <0x02>; 1451 bias-disable; 1452 }; 1453 }; 1454 1455 qup_i2c13_default: qup-i2c13-default { 1456 mux { 1457 pins = "gpio43", "gpio44"; 1458 function = "qup13"; 1459 }; 1460 1461 config { 1462 pins = "gpio43", "gpio44"; 1463 drive-strength = <0x02>; 1464 bias-disable; 1465 }; 1466 }; 1467 1468 qup_i2c14_default: qup-i2c14-default { 1469 mux { 1470 pins = "gpio47", "gpio48"; 1471 function = "qup14"; 1472 }; 1473 1474 config { 1475 pins = "gpio47", "gpio48"; 1476 drive-strength = <0x02>; 1477 bias-disable; 1478 }; 1479 }; 1480 1481 qup_i2c15_default: qup-i2c15-default { 1482 mux { 1483 pins = "gpio27", "gpio28"; 1484 function = "qup15"; 1485 }; 1486 1487 config { 1488 pins = "gpio27", "gpio28"; 1489 drive-strength = <0x02>; 1490 bias-disable; 1491 }; 1492 }; 1493 1494 qup_i2c16_default: qup-i2c16-default { 1495 mux { 1496 pins = "gpio86", "gpio85"; 1497 function = "qup16"; 1498 }; 1499 1500 config { 1501 pins = "gpio86", "gpio85"; 1502 drive-strength = <0x02>; 1503 bias-disable; 1504 }; 1505 }; 1506 1507 qup_i2c17_default: qup-i2c17-default { 1508 mux { 1509 pins = "gpio55", "gpio56"; 1510 function = "qup17"; 1511 }; 1512 1513 config { 1514 pins = "gpio55", "gpio56"; 1515 drive-strength = <0x02>; 1516 bias-disable; 1517 }; 1518 }; 1519 1520 qup_i2c18_default: qup-i2c18-default { 1521 mux { 1522 pins = "gpio23", "gpio24"; 1523 function = "qup18"; 1524 }; 1525 1526 config { 1527 pins = "gpio23", "gpio24"; 1528 drive-strength = <0x02>; 1529 bias-disable; 1530 }; 1531 }; 1532 1533 qup_i2c19_default: qup-i2c19-default { 1534 mux { 1535 pins = "gpio57", "gpio58"; 1536 function = "qup19"; 1537 }; 1538 1539 config { 1540 pins = "gpio57", "gpio58"; 1541 drive-strength = <0x02>; 1542 bias-disable; 1543 }; 1544 }; 1545 }; 1546 1547 remoteproc_mpss: remoteproc@4080000 { 1548 compatible = "qcom,sm8150-mpss-pas"; 1549 reg = <0x0 0x04080000 0x0 0x4040>; 1550 1551 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 1552 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1553 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1554 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1555 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1556 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1557 interrupt-names = "wdog", "fatal", "ready", "handover", 1558 "stop-ack", "shutdown-ack"; 1559 1560 clocks = <&rpmhcc RPMH_CXO_CLK>; 1561 clock-names = "xo"; 1562 1563 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, 1564 <&rpmhpd 7>, 1565 <&rpmhpd 0>; 1566 power-domain-names = "load_state", "cx", "mss"; 1567 1568 memory-region = <&mpss_mem>; 1569 1570 qcom,smem-states = <&modem_smp2p_out 0>; 1571 qcom,smem-state-names = "stop"; 1572 1573 status = "disabled"; 1574 1575 glink-edge { 1576 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 1577 label = "modem"; 1578 qcom,remote-pid = <1>; 1579 mboxes = <&apss_shared 12>; 1580 }; 1581 }; 1582 1583 stm@6002000 { 1584 compatible = "arm,coresight-stm", "arm,primecell"; 1585 reg = <0 0x06002000 0 0x1000>, 1586 <0 0x16280000 0 0x180000>; 1587 reg-names = "stm-base", "stm-stimulus-base"; 1588 1589 clocks = <&aoss_qmp>; 1590 clock-names = "apb_pclk"; 1591 1592 out-ports { 1593 port { 1594 stm_out: endpoint { 1595 remote-endpoint = <&funnel0_in7>; 1596 }; 1597 }; 1598 }; 1599 }; 1600 1601 funnel@6041000 { 1602 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1603 reg = <0 0x06041000 0 0x1000>; 1604 1605 clocks = <&aoss_qmp>; 1606 clock-names = "apb_pclk"; 1607 1608 out-ports { 1609 port { 1610 funnel0_out: endpoint { 1611 remote-endpoint = <&merge_funnel_in0>; 1612 }; 1613 }; 1614 }; 1615 1616 in-ports { 1617 #address-cells = <1>; 1618 #size-cells = <0>; 1619 1620 port@7 { 1621 reg = <7>; 1622 funnel0_in7: endpoint { 1623 remote-endpoint = <&stm_out>; 1624 }; 1625 }; 1626 }; 1627 }; 1628 1629 funnel@6042000 { 1630 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1631 reg = <0 0x06042000 0 0x1000>; 1632 1633 clocks = <&aoss_qmp>; 1634 clock-names = "apb_pclk"; 1635 1636 out-ports { 1637 port { 1638 funnel1_out: endpoint { 1639 remote-endpoint = <&merge_funnel_in1>; 1640 }; 1641 }; 1642 }; 1643 1644 in-ports { 1645 #address-cells = <1>; 1646 #size-cells = <0>; 1647 1648 port@4 { 1649 reg = <4>; 1650 funnel1_in4: endpoint { 1651 remote-endpoint = <&swao_replicator_out>; 1652 }; 1653 }; 1654 }; 1655 }; 1656 1657 funnel@6043000 { 1658 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1659 reg = <0 0x06043000 0 0x1000>; 1660 1661 clocks = <&aoss_qmp>; 1662 clock-names = "apb_pclk"; 1663 1664 out-ports { 1665 port { 1666 funnel2_out: endpoint { 1667 remote-endpoint = <&merge_funnel_in2>; 1668 }; 1669 }; 1670 }; 1671 1672 in-ports { 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 1676 port@2 { 1677 reg = <2>; 1678 funnel2_in2: endpoint { 1679 remote-endpoint = <&apss_merge_funnel_out>; 1680 }; 1681 }; 1682 }; 1683 }; 1684 1685 funnel@6045000 { 1686 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1687 reg = <0 0x06045000 0 0x1000>; 1688 1689 clocks = <&aoss_qmp>; 1690 clock-names = "apb_pclk"; 1691 1692 out-ports { 1693 port { 1694 merge_funnel_out: endpoint { 1695 remote-endpoint = <&etf_in>; 1696 }; 1697 }; 1698 }; 1699 1700 in-ports { 1701 #address-cells = <1>; 1702 #size-cells = <0>; 1703 1704 port@0 { 1705 reg = <0>; 1706 merge_funnel_in0: endpoint { 1707 remote-endpoint = <&funnel0_out>; 1708 }; 1709 }; 1710 1711 port@1 { 1712 reg = <1>; 1713 merge_funnel_in1: endpoint { 1714 remote-endpoint = <&funnel1_out>; 1715 }; 1716 }; 1717 1718 port@2 { 1719 reg = <2>; 1720 merge_funnel_in2: endpoint { 1721 remote-endpoint = <&funnel2_out>; 1722 }; 1723 }; 1724 }; 1725 }; 1726 1727 replicator@6046000 { 1728 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1729 reg = <0 0x06046000 0 0x1000>; 1730 1731 clocks = <&aoss_qmp>; 1732 clock-names = "apb_pclk"; 1733 1734 out-ports { 1735 #address-cells = <1>; 1736 #size-cells = <0>; 1737 1738 port@0 { 1739 reg = <0>; 1740 replicator_out0: endpoint { 1741 remote-endpoint = <&etr_in>; 1742 }; 1743 }; 1744 1745 port@1 { 1746 reg = <1>; 1747 replicator_out1: endpoint { 1748 remote-endpoint = <&replicator1_in>; 1749 }; 1750 }; 1751 }; 1752 1753 in-ports { 1754 port { 1755 replicator_in0: endpoint { 1756 remote-endpoint = <&etf_out>; 1757 }; 1758 }; 1759 }; 1760 }; 1761 1762 etf@6047000 { 1763 compatible = "arm,coresight-tmc", "arm,primecell"; 1764 reg = <0 0x06047000 0 0x1000>; 1765 1766 clocks = <&aoss_qmp>; 1767 clock-names = "apb_pclk"; 1768 1769 out-ports { 1770 port { 1771 etf_out: endpoint { 1772 remote-endpoint = <&replicator_in0>; 1773 }; 1774 }; 1775 }; 1776 1777 in-ports { 1778 port { 1779 etf_in: endpoint { 1780 remote-endpoint = <&merge_funnel_out>; 1781 }; 1782 }; 1783 }; 1784 }; 1785 1786 etr@6048000 { 1787 compatible = "arm,coresight-tmc", "arm,primecell"; 1788 reg = <0 0x06048000 0 0x1000>; 1789 iommus = <&apps_smmu 0x05e0 0x0>; 1790 1791 clocks = <&aoss_qmp>; 1792 clock-names = "apb_pclk"; 1793 arm,scatter-gather; 1794 1795 in-ports { 1796 port { 1797 etr_in: endpoint { 1798 remote-endpoint = <&replicator_out0>; 1799 }; 1800 }; 1801 }; 1802 }; 1803 1804 replicator@604a000 { 1805 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1806 reg = <0 0x0604a000 0 0x1000>; 1807 1808 clocks = <&aoss_qmp>; 1809 clock-names = "apb_pclk"; 1810 1811 out-ports { 1812 #address-cells = <1>; 1813 #size-cells = <0>; 1814 1815 port@1 { 1816 reg = <1>; 1817 replicator1_out: endpoint { 1818 remote-endpoint = <&swao_funnel_in>; 1819 }; 1820 }; 1821 }; 1822 1823 in-ports { 1824 #address-cells = <1>; 1825 #size-cells = <0>; 1826 1827 port@1 { 1828 reg = <1>; 1829 replicator1_in: endpoint { 1830 remote-endpoint = <&replicator_out1>; 1831 }; 1832 }; 1833 }; 1834 }; 1835 1836 funnel@6b08000 { 1837 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1838 reg = <0 0x06b08000 0 0x1000>; 1839 1840 clocks = <&aoss_qmp>; 1841 clock-names = "apb_pclk"; 1842 1843 out-ports { 1844 port { 1845 swao_funnel_out: endpoint { 1846 remote-endpoint = <&swao_etf_in>; 1847 }; 1848 }; 1849 }; 1850 1851 in-ports { 1852 #address-cells = <1>; 1853 #size-cells = <0>; 1854 1855 port@6 { 1856 reg = <6>; 1857 swao_funnel_in: endpoint { 1858 remote-endpoint = <&replicator1_out>; 1859 }; 1860 }; 1861 }; 1862 }; 1863 1864 etf@6b09000 { 1865 compatible = "arm,coresight-tmc", "arm,primecell"; 1866 reg = <0 0x06b09000 0 0x1000>; 1867 1868 clocks = <&aoss_qmp>; 1869 clock-names = "apb_pclk"; 1870 1871 out-ports { 1872 port { 1873 swao_etf_out: endpoint { 1874 remote-endpoint = <&swao_replicator_in>; 1875 }; 1876 }; 1877 }; 1878 1879 in-ports { 1880 port { 1881 swao_etf_in: endpoint { 1882 remote-endpoint = <&swao_funnel_out>; 1883 }; 1884 }; 1885 }; 1886 }; 1887 1888 replicator@6b0a000 { 1889 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1890 reg = <0 0x06b0a000 0 0x1000>; 1891 1892 clocks = <&aoss_qmp>; 1893 clock-names = "apb_pclk"; 1894 qcom,replicator-loses-context; 1895 1896 out-ports { 1897 port { 1898 swao_replicator_out: endpoint { 1899 remote-endpoint = <&funnel1_in4>; 1900 }; 1901 }; 1902 }; 1903 1904 in-ports { 1905 port { 1906 swao_replicator_in: endpoint { 1907 remote-endpoint = <&swao_etf_out>; 1908 }; 1909 }; 1910 }; 1911 }; 1912 1913 etm@7040000 { 1914 compatible = "arm,coresight-etm4x", "arm,primecell"; 1915 reg = <0 0x07040000 0 0x1000>; 1916 1917 cpu = <&CPU0>; 1918 1919 clocks = <&aoss_qmp>; 1920 clock-names = "apb_pclk"; 1921 arm,coresight-loses-context-with-cpu; 1922 qcom,skip-power-up; 1923 1924 out-ports { 1925 port { 1926 etm0_out: endpoint { 1927 remote-endpoint = <&apss_funnel_in0>; 1928 }; 1929 }; 1930 }; 1931 }; 1932 1933 etm@7140000 { 1934 compatible = "arm,coresight-etm4x", "arm,primecell"; 1935 reg = <0 0x07140000 0 0x1000>; 1936 1937 cpu = <&CPU1>; 1938 1939 clocks = <&aoss_qmp>; 1940 clock-names = "apb_pclk"; 1941 arm,coresight-loses-context-with-cpu; 1942 qcom,skip-power-up; 1943 1944 out-ports { 1945 port { 1946 etm1_out: endpoint { 1947 remote-endpoint = <&apss_funnel_in1>; 1948 }; 1949 }; 1950 }; 1951 }; 1952 1953 etm@7240000 { 1954 compatible = "arm,coresight-etm4x", "arm,primecell"; 1955 reg = <0 0x07240000 0 0x1000>; 1956 1957 cpu = <&CPU2>; 1958 1959 clocks = <&aoss_qmp>; 1960 clock-names = "apb_pclk"; 1961 arm,coresight-loses-context-with-cpu; 1962 qcom,skip-power-up; 1963 1964 out-ports { 1965 port { 1966 etm2_out: endpoint { 1967 remote-endpoint = <&apss_funnel_in2>; 1968 }; 1969 }; 1970 }; 1971 }; 1972 1973 etm@7340000 { 1974 compatible = "arm,coresight-etm4x", "arm,primecell"; 1975 reg = <0 0x07340000 0 0x1000>; 1976 1977 cpu = <&CPU3>; 1978 1979 clocks = <&aoss_qmp>; 1980 clock-names = "apb_pclk"; 1981 arm,coresight-loses-context-with-cpu; 1982 qcom,skip-power-up; 1983 1984 out-ports { 1985 port { 1986 etm3_out: endpoint { 1987 remote-endpoint = <&apss_funnel_in3>; 1988 }; 1989 }; 1990 }; 1991 }; 1992 1993 etm@7440000 { 1994 compatible = "arm,coresight-etm4x", "arm,primecell"; 1995 reg = <0 0x07440000 0 0x1000>; 1996 1997 cpu = <&CPU4>; 1998 1999 clocks = <&aoss_qmp>; 2000 clock-names = "apb_pclk"; 2001 arm,coresight-loses-context-with-cpu; 2002 qcom,skip-power-up; 2003 2004 out-ports { 2005 port { 2006 etm4_out: endpoint { 2007 remote-endpoint = <&apss_funnel_in4>; 2008 }; 2009 }; 2010 }; 2011 }; 2012 2013 etm@7540000 { 2014 compatible = "arm,coresight-etm4x", "arm,primecell"; 2015 reg = <0 0x07540000 0 0x1000>; 2016 2017 cpu = <&CPU5>; 2018 2019 clocks = <&aoss_qmp>; 2020 clock-names = "apb_pclk"; 2021 arm,coresight-loses-context-with-cpu; 2022 qcom,skip-power-up; 2023 2024 out-ports { 2025 port { 2026 etm5_out: endpoint { 2027 remote-endpoint = <&apss_funnel_in5>; 2028 }; 2029 }; 2030 }; 2031 }; 2032 2033 etm@7640000 { 2034 compatible = "arm,coresight-etm4x", "arm,primecell"; 2035 reg = <0 0x07640000 0 0x1000>; 2036 2037 cpu = <&CPU6>; 2038 2039 clocks = <&aoss_qmp>; 2040 clock-names = "apb_pclk"; 2041 arm,coresight-loses-context-with-cpu; 2042 qcom,skip-power-up; 2043 2044 out-ports { 2045 port { 2046 etm6_out: endpoint { 2047 remote-endpoint = <&apss_funnel_in6>; 2048 }; 2049 }; 2050 }; 2051 }; 2052 2053 etm@7740000 { 2054 compatible = "arm,coresight-etm4x", "arm,primecell"; 2055 reg = <0 0x07740000 0 0x1000>; 2056 2057 cpu = <&CPU7>; 2058 2059 clocks = <&aoss_qmp>; 2060 clock-names = "apb_pclk"; 2061 arm,coresight-loses-context-with-cpu; 2062 qcom,skip-power-up; 2063 2064 out-ports { 2065 port { 2066 etm7_out: endpoint { 2067 remote-endpoint = <&apss_funnel_in7>; 2068 }; 2069 }; 2070 }; 2071 }; 2072 2073 funnel@7800000 { /* APSS Funnel */ 2074 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2075 reg = <0 0x07800000 0 0x1000>; 2076 2077 clocks = <&aoss_qmp>; 2078 clock-names = "apb_pclk"; 2079 2080 out-ports { 2081 port { 2082 apss_funnel_out: endpoint { 2083 remote-endpoint = <&apss_merge_funnel_in>; 2084 }; 2085 }; 2086 }; 2087 2088 in-ports { 2089 #address-cells = <1>; 2090 #size-cells = <0>; 2091 2092 port@0 { 2093 reg = <0>; 2094 apss_funnel_in0: endpoint { 2095 remote-endpoint = <&etm0_out>; 2096 }; 2097 }; 2098 2099 port@1 { 2100 reg = <1>; 2101 apss_funnel_in1: endpoint { 2102 remote-endpoint = <&etm1_out>; 2103 }; 2104 }; 2105 2106 port@2 { 2107 reg = <2>; 2108 apss_funnel_in2: endpoint { 2109 remote-endpoint = <&etm2_out>; 2110 }; 2111 }; 2112 2113 port@3 { 2114 reg = <3>; 2115 apss_funnel_in3: endpoint { 2116 remote-endpoint = <&etm3_out>; 2117 }; 2118 }; 2119 2120 port@4 { 2121 reg = <4>; 2122 apss_funnel_in4: endpoint { 2123 remote-endpoint = <&etm4_out>; 2124 }; 2125 }; 2126 2127 port@5 { 2128 reg = <5>; 2129 apss_funnel_in5: endpoint { 2130 remote-endpoint = <&etm5_out>; 2131 }; 2132 }; 2133 2134 port@6 { 2135 reg = <6>; 2136 apss_funnel_in6: endpoint { 2137 remote-endpoint = <&etm6_out>; 2138 }; 2139 }; 2140 2141 port@7 { 2142 reg = <7>; 2143 apss_funnel_in7: endpoint { 2144 remote-endpoint = <&etm7_out>; 2145 }; 2146 }; 2147 }; 2148 }; 2149 2150 funnel@7810000 { 2151 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2152 reg = <0 0x07810000 0 0x1000>; 2153 2154 clocks = <&aoss_qmp>; 2155 clock-names = "apb_pclk"; 2156 2157 out-ports { 2158 port { 2159 apss_merge_funnel_out: endpoint { 2160 remote-endpoint = <&funnel2_in2>; 2161 }; 2162 }; 2163 }; 2164 2165 in-ports { 2166 port { 2167 apss_merge_funnel_in: endpoint { 2168 remote-endpoint = <&apss_funnel_out>; 2169 }; 2170 }; 2171 }; 2172 }; 2173 2174 remoteproc_cdsp: remoteproc@8300000 { 2175 compatible = "qcom,sm8150-cdsp-pas"; 2176 reg = <0x0 0x08300000 0x0 0x4040>; 2177 2178 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2179 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2180 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2181 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2182 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2183 interrupt-names = "wdog", "fatal", "ready", 2184 "handover", "stop-ack"; 2185 2186 clocks = <&rpmhcc RPMH_CXO_CLK>; 2187 clock-names = "xo"; 2188 2189 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, 2190 <&rpmhpd 7>; 2191 power-domain-names = "load_state", "cx"; 2192 2193 memory-region = <&cdsp_mem>; 2194 2195 qcom,smem-states = <&cdsp_smp2p_out 0>; 2196 qcom,smem-state-names = "stop"; 2197 2198 status = "disabled"; 2199 2200 glink-edge { 2201 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 2202 label = "cdsp"; 2203 qcom,remote-pid = <5>; 2204 mboxes = <&apss_shared 4>; 2205 }; 2206 }; 2207 2208 usb_1_hsphy: phy@88e2000 { 2209 compatible = "qcom,sm8150-usb-hs-phy", 2210 "qcom,usb-snps-hs-7nm-phy"; 2211 reg = <0 0x088e2000 0 0x400>; 2212 status = "disabled"; 2213 #phy-cells = <0>; 2214 2215 clocks = <&rpmhcc RPMH_CXO_CLK>; 2216 clock-names = "ref"; 2217 2218 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2219 }; 2220 2221 usb_2_hsphy: phy@88e3000 { 2222 compatible = "qcom,sm8150-usb-hs-phy", 2223 "qcom,usb-snps-hs-7nm-phy"; 2224 reg = <0 0x088e3000 0 0x400>; 2225 status = "disabled"; 2226 #phy-cells = <0>; 2227 2228 clocks = <&rpmhcc RPMH_CXO_CLK>; 2229 clock-names = "ref"; 2230 2231 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2232 }; 2233 2234 usb_1_qmpphy: phy@88e9000 { 2235 compatible = "qcom,sm8150-qmp-usb3-phy"; 2236 reg = <0 0x088e9000 0 0x18c>, 2237 <0 0x088e8000 0 0x10>; 2238 reg-names = "reg-base", "dp_com"; 2239 status = "disabled"; 2240 #address-cells = <2>; 2241 #size-cells = <2>; 2242 ranges; 2243 2244 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2245 <&rpmhcc RPMH_CXO_CLK>, 2246 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2247 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2248 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2249 2250 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2251 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2252 reset-names = "phy", "common"; 2253 2254 usb_1_ssphy: lanes@88e9200 { 2255 reg = <0 0x088e9200 0 0x200>, 2256 <0 0x088e9400 0 0x200>, 2257 <0 0x088e9c00 0 0x218>, 2258 <0 0x088e9600 0 0x200>, 2259 <0 0x088e9800 0 0x200>, 2260 <0 0x088e9a00 0 0x100>; 2261 #clock-cells = <0>; 2262 #phy-cells = <0>; 2263 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2264 clock-names = "pipe0"; 2265 clock-output-names = "usb3_phy_pipe_clk_src"; 2266 }; 2267 }; 2268 2269 dc_noc: interconnect@9160000 { 2270 compatible = "qcom,sm8150-dc-noc"; 2271 reg = <0 0x09160000 0 0x3200>; 2272 #interconnect-cells = <1>; 2273 qcom,bcm-voters = <&apps_bcm_voter>; 2274 }; 2275 2276 gem_noc: interconnect@9680000 { 2277 compatible = "qcom,sm8150-gem-noc"; 2278 reg = <0 0x09680000 0 0x3e200>; 2279 #interconnect-cells = <1>; 2280 qcom,bcm-voters = <&apps_bcm_voter>; 2281 }; 2282 2283 usb_2_qmpphy: phy@88eb000 { 2284 compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 2285 reg = <0 0x088eb000 0 0x200>; 2286 status = "disabled"; 2287 #address-cells = <2>; 2288 #size-cells = <2>; 2289 ranges; 2290 2291 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2292 <&rpmhcc RPMH_CXO_CLK>, 2293 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 2294 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2295 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2296 2297 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2298 <&gcc GCC_USB3_PHY_SEC_BCR>; 2299 reset-names = "phy", "common"; 2300 2301 usb_2_ssphy: lane@88eb200 { 2302 reg = <0 0x088eb200 0 0x200>, 2303 <0 0x088eb400 0 0x200>, 2304 <0 0x088eb800 0 0x800>, 2305 <0 0x088eb600 0 0x200>; 2306 #clock-cells = <0>; 2307 #phy-cells = <0>; 2308 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2309 clock-names = "pipe0"; 2310 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2311 }; 2312 }; 2313 2314 usb_1: usb@a6f8800 { 2315 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 2316 reg = <0 0x0a6f8800 0 0x400>; 2317 status = "disabled"; 2318 #address-cells = <2>; 2319 #size-cells = <2>; 2320 ranges; 2321 dma-ranges; 2322 2323 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2324 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2325 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2326 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2327 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2328 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2329 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2330 "sleep", "xo"; 2331 2332 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2333 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2334 assigned-clock-rates = <19200000>, <200000000>; 2335 2336 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2337 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 2338 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 2339 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 2340 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2341 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2342 2343 power-domains = <&gcc USB30_PRIM_GDSC>; 2344 2345 resets = <&gcc GCC_USB30_PRIM_BCR>; 2346 2347 usb_1_dwc3: dwc3@a600000 { 2348 compatible = "snps,dwc3"; 2349 reg = <0 0x0a600000 0 0xcd00>; 2350 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2351 iommus = <&apps_smmu 0x140 0>; 2352 snps,dis_u2_susphy_quirk; 2353 snps,dis_enblslpm_quirk; 2354 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2355 phy-names = "usb2-phy", "usb3-phy"; 2356 }; 2357 }; 2358 2359 usb_2: usb@a8f8800 { 2360 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 2361 reg = <0 0x0a8f8800 0 0x400>; 2362 status = "disabled"; 2363 #address-cells = <2>; 2364 #size-cells = <2>; 2365 ranges; 2366 dma-ranges; 2367 2368 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2369 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2370 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2371 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2372 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2373 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2374 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2375 "sleep", "xo"; 2376 2377 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2378 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2379 assigned-clock-rates = <19200000>, <200000000>; 2380 2381 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2382 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 2383 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 2384 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 2385 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2386 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2387 2388 power-domains = <&gcc USB30_SEC_GDSC>; 2389 2390 resets = <&gcc GCC_USB30_SEC_BCR>; 2391 2392 usb_2_dwc3: dwc3@a800000 { 2393 compatible = "snps,dwc3"; 2394 reg = <0 0x0a800000 0 0xcd00>; 2395 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2396 iommus = <&apps_smmu 0x160 0>; 2397 snps,dis_u2_susphy_quirk; 2398 snps,dis_enblslpm_quirk; 2399 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2400 phy-names = "usb2-phy", "usb3-phy"; 2401 }; 2402 }; 2403 2404 camnoc_virt: interconnect@ac00000 { 2405 compatible = "qcom,sm8150-camnoc-virt"; 2406 reg = <0 0x0ac00000 0 0x1000>; 2407 #interconnect-cells = <1>; 2408 qcom,bcm-voters = <&apps_bcm_voter>; 2409 }; 2410 2411 aoss_qmp: power-controller@c300000 { 2412 compatible = "qcom,sm8150-aoss-qmp"; 2413 reg = <0x0 0x0c300000 0x0 0x100000>; 2414 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 2415 mboxes = <&apss_shared 0>; 2416 2417 #clock-cells = <0>; 2418 #power-domain-cells = <1>; 2419 }; 2420 2421 tsens0: thermal-sensor@c263000 { 2422 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 2423 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2424 <0 0x0c222000 0 0x1ff>; /* SROT */ 2425 #qcom,sensors = <16>; 2426 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2427 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2428 interrupt-names = "uplow", "critical"; 2429 #thermal-sensor-cells = <1>; 2430 }; 2431 2432 tsens1: thermal-sensor@c265000 { 2433 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 2434 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2435 <0 0x0c223000 0 0x1ff>; /* SROT */ 2436 #qcom,sensors = <8>; 2437 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2438 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2439 interrupt-names = "uplow", "critical"; 2440 #thermal-sensor-cells = <1>; 2441 }; 2442 2443 spmi_bus: spmi@c440000 { 2444 compatible = "qcom,spmi-pmic-arb"; 2445 reg = <0x0 0x0c440000 0x0 0x0001100>, 2446 <0x0 0x0c600000 0x0 0x2000000>, 2447 <0x0 0x0e600000 0x0 0x0100000>, 2448 <0x0 0x0e700000 0x0 0x00a0000>, 2449 <0x0 0x0c40a000 0x0 0x0026000>; 2450 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2451 interrupt-names = "periph_irq"; 2452 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 2453 qcom,ee = <0>; 2454 qcom,channel = <0>; 2455 #address-cells = <2>; 2456 #size-cells = <0>; 2457 interrupt-controller; 2458 #interrupt-cells = <4>; 2459 cell-index = <0>; 2460 }; 2461 2462 apps_smmu: iommu@15000000 { 2463 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 2464 reg = <0 0x15000000 0 0x100000>; 2465 #iommu-cells = <2>; 2466 #global-interrupts = <1>; 2467 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2468 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2469 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2470 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2471 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2472 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2473 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2474 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2475 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2478 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2479 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2480 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2481 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2482 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2483 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2484 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2485 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2486 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2487 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2488 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2489 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2490 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2491 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2492 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2493 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2494 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2495 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2496 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2497 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2498 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2499 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2500 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2501 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2502 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2503 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2504 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2505 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2506 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2507 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2508 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2509 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2510 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2511 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2512 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2513 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2514 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2515 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2516 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2517 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2518 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2519 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2520 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2521 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2522 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2523 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2524 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2525 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2526 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2527 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2528 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2529 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2530 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2531 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2532 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2533 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2534 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2535 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2536 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2537 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2538 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2539 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2540 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2541 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2542 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2543 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2544 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2545 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2546 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2547 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 2548 }; 2549 2550 remoteproc_adsp: remoteproc@17300000 { 2551 compatible = "qcom,sm8150-adsp-pas"; 2552 reg = <0x0 0x17300000 0x0 0x4040>; 2553 2554 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2555 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2556 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2557 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2558 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2559 interrupt-names = "wdog", "fatal", "ready", 2560 "handover", "stop-ack"; 2561 2562 clocks = <&rpmhcc RPMH_CXO_CLK>; 2563 clock-names = "xo"; 2564 2565 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, 2566 <&rpmhpd 7>; 2567 power-domain-names = "load_state", "cx"; 2568 2569 memory-region = <&adsp_mem>; 2570 2571 qcom,smem-states = <&adsp_smp2p_out 0>; 2572 qcom,smem-state-names = "stop"; 2573 2574 status = "disabled"; 2575 2576 glink-edge { 2577 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 2578 label = "lpass"; 2579 qcom,remote-pid = <2>; 2580 mboxes = <&apss_shared 8>; 2581 }; 2582 }; 2583 2584 intc: interrupt-controller@17a00000 { 2585 compatible = "arm,gic-v3"; 2586 interrupt-controller; 2587 #interrupt-cells = <3>; 2588 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 2589 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 2590 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2591 }; 2592 2593 apss_shared: mailbox@17c00000 { 2594 compatible = "qcom,sm8150-apss-shared"; 2595 reg = <0x0 0x17c00000 0x0 0x1000>; 2596 #mbox-cells = <1>; 2597 }; 2598 2599 watchdog@17c10000 { 2600 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 2601 reg = <0 0x17c10000 0 0x1000>; 2602 clocks = <&sleep_clk>; 2603 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 2604 }; 2605 2606 timer@17c20000 { 2607 #address-cells = <2>; 2608 #size-cells = <2>; 2609 ranges; 2610 compatible = "arm,armv7-timer-mem"; 2611 reg = <0x0 0x17c20000 0x0 0x1000>; 2612 clock-frequency = <19200000>; 2613 2614 frame@17c21000{ 2615 frame-number = <0>; 2616 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2617 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2618 reg = <0x0 0x17c21000 0x0 0x1000>, 2619 <0x0 0x17c22000 0x0 0x1000>; 2620 }; 2621 2622 frame@17c23000 { 2623 frame-number = <1>; 2624 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2625 reg = <0x0 0x17c23000 0x0 0x1000>; 2626 status = "disabled"; 2627 }; 2628 2629 frame@17c25000 { 2630 frame-number = <2>; 2631 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2632 reg = <0x0 0x17c25000 0x0 0x1000>; 2633 status = "disabled"; 2634 }; 2635 2636 frame@17c27000 { 2637 frame-number = <3>; 2638 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2639 reg = <0x0 0x17c26000 0x0 0x1000>; 2640 status = "disabled"; 2641 }; 2642 2643 frame@17c29000 { 2644 frame-number = <4>; 2645 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2646 reg = <0x0 0x17c29000 0x0 0x1000>; 2647 status = "disabled"; 2648 }; 2649 2650 frame@17c2b000 { 2651 frame-number = <5>; 2652 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2653 reg = <0x0 0x17c2b000 0x0 0x1000>; 2654 status = "disabled"; 2655 }; 2656 2657 frame@17c2d000 { 2658 frame-number = <6>; 2659 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2660 reg = <0x0 0x17c2d000 0x0 0x1000>; 2661 status = "disabled"; 2662 }; 2663 }; 2664 2665 apps_rsc: rsc@18200000 { 2666 label = "apps_rsc"; 2667 compatible = "qcom,rpmh-rsc"; 2668 reg = <0x0 0x18200000 0x0 0x10000>, 2669 <0x0 0x18210000 0x0 0x10000>, 2670 <0x0 0x18220000 0x0 0x10000>; 2671 reg-names = "drv-0", "drv-1", "drv-2"; 2672 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2673 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2674 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2675 qcom,tcs-offset = <0xd00>; 2676 qcom,drv-id = <2>; 2677 qcom,tcs-config = <ACTIVE_TCS 2>, 2678 <SLEEP_TCS 1>, 2679 <WAKE_TCS 1>, 2680 <CONTROL_TCS 0>; 2681 2682 rpmhcc: clock-controller { 2683 compatible = "qcom,sm8150-rpmh-clk"; 2684 #clock-cells = <1>; 2685 clock-names = "xo"; 2686 clocks = <&xo_board>; 2687 }; 2688 2689 rpmhpd: power-controller { 2690 compatible = "qcom,sm8150-rpmhpd"; 2691 #power-domain-cells = <1>; 2692 operating-points-v2 = <&rpmhpd_opp_table>; 2693 2694 rpmhpd_opp_table: opp-table { 2695 compatible = "operating-points-v2"; 2696 2697 rpmhpd_opp_ret: opp1 { 2698 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2699 }; 2700 2701 rpmhpd_opp_min_svs: opp2 { 2702 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2703 }; 2704 2705 rpmhpd_opp_low_svs: opp3 { 2706 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2707 }; 2708 2709 rpmhpd_opp_svs: opp4 { 2710 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2711 }; 2712 2713 rpmhpd_opp_svs_l1: opp5 { 2714 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2715 }; 2716 2717 rpmhpd_opp_svs_l2: opp6 { 2718 opp-level = <224>; 2719 }; 2720 2721 rpmhpd_opp_nom: opp7 { 2722 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2723 }; 2724 2725 rpmhpd_opp_nom_l1: opp8 { 2726 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2727 }; 2728 2729 rpmhpd_opp_nom_l2: opp9 { 2730 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2731 }; 2732 2733 rpmhpd_opp_turbo: opp10 { 2734 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2735 }; 2736 2737 rpmhpd_opp_turbo_l1: opp11 { 2738 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2739 }; 2740 }; 2741 }; 2742 2743 apps_bcm_voter: bcm_voter { 2744 compatible = "qcom,bcm-voter"; 2745 }; 2746 }; 2747 2748 osm_l3: interconnect@18321000 { 2749 compatible = "qcom,sm8150-osm-l3"; 2750 reg = <0 0x18321000 0 0x1400>; 2751 2752 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2753 clock-names = "xo", "alternate"; 2754 2755 #interconnect-cells = <1>; 2756 }; 2757 2758 cpufreq_hw: cpufreq@18323000 { 2759 compatible = "qcom,cpufreq-hw"; 2760 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 2761 <0 0x18327800 0 0x1400>; 2762 reg-names = "freq-domain0", "freq-domain1", 2763 "freq-domain2"; 2764 2765 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2766 clock-names = "xo", "alternate"; 2767 2768 #freq-domain-cells = <1>; 2769 }; 2770 2771 wifi: wifi@18800000 { 2772 compatible = "qcom,wcn3990-wifi"; 2773 reg = <0 0x18800000 0 0x800000>; 2774 reg-names = "membase"; 2775 memory-region = <&wlan_mem>; 2776 clock-names = "cxo_ref_clk_pin", "qdss"; 2777 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 2778 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2779 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2780 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2781 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2782 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2783 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2784 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2785 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2786 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2787 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2788 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2789 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2790 iommus = <&apps_smmu 0x0640 0x1>; 2791 status = "disabled"; 2792 }; 2793 }; 2794 2795 timer { 2796 compatible = "arm,armv8-timer"; 2797 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 2798 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 2799 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 2800 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 2801 }; 2802 2803 thermal-zones { 2804 cpu0-thermal { 2805 polling-delay-passive = <250>; 2806 polling-delay = <1000>; 2807 2808 thermal-sensors = <&tsens0 1>; 2809 2810 trips { 2811 cpu0_alert0: trip-point0 { 2812 temperature = <90000>; 2813 hysteresis = <2000>; 2814 type = "passive"; 2815 }; 2816 2817 cpu0_alert1: trip-point1 { 2818 temperature = <95000>; 2819 hysteresis = <2000>; 2820 type = "passive"; 2821 }; 2822 2823 cpu0_crit: cpu_crit { 2824 temperature = <110000>; 2825 hysteresis = <1000>; 2826 type = "critical"; 2827 }; 2828 }; 2829 2830 cooling-maps { 2831 map0 { 2832 trip = <&cpu0_alert0>; 2833 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2834 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2835 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2836 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2837 }; 2838 map1 { 2839 trip = <&cpu0_alert1>; 2840 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2841 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2842 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2843 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2844 }; 2845 }; 2846 }; 2847 2848 cpu1-thermal { 2849 polling-delay-passive = <250>; 2850 polling-delay = <1000>; 2851 2852 thermal-sensors = <&tsens0 2>; 2853 2854 trips { 2855 cpu1_alert0: trip-point0 { 2856 temperature = <90000>; 2857 hysteresis = <2000>; 2858 type = "passive"; 2859 }; 2860 2861 cpu1_alert1: trip-point1 { 2862 temperature = <95000>; 2863 hysteresis = <2000>; 2864 type = "passive"; 2865 }; 2866 2867 cpu1_crit: cpu_crit { 2868 temperature = <110000>; 2869 hysteresis = <1000>; 2870 type = "critical"; 2871 }; 2872 }; 2873 2874 cooling-maps { 2875 map0 { 2876 trip = <&cpu1_alert0>; 2877 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2878 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2879 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2880 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2881 }; 2882 map1 { 2883 trip = <&cpu1_alert1>; 2884 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2885 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2886 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2887 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2888 }; 2889 }; 2890 }; 2891 2892 cpu2-thermal { 2893 polling-delay-passive = <250>; 2894 polling-delay = <1000>; 2895 2896 thermal-sensors = <&tsens0 3>; 2897 2898 trips { 2899 cpu2_alert0: trip-point0 { 2900 temperature = <90000>; 2901 hysteresis = <2000>; 2902 type = "passive"; 2903 }; 2904 2905 cpu2_alert1: trip-point1 { 2906 temperature = <95000>; 2907 hysteresis = <2000>; 2908 type = "passive"; 2909 }; 2910 2911 cpu2_crit: cpu_crit { 2912 temperature = <110000>; 2913 hysteresis = <1000>; 2914 type = "critical"; 2915 }; 2916 }; 2917 2918 cooling-maps { 2919 map0 { 2920 trip = <&cpu2_alert0>; 2921 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2922 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2923 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2924 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2925 }; 2926 map1 { 2927 trip = <&cpu2_alert1>; 2928 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2929 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2930 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2931 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2932 }; 2933 }; 2934 }; 2935 2936 cpu3-thermal { 2937 polling-delay-passive = <250>; 2938 polling-delay = <1000>; 2939 2940 thermal-sensors = <&tsens0 4>; 2941 2942 trips { 2943 cpu3_alert0: trip-point0 { 2944 temperature = <90000>; 2945 hysteresis = <2000>; 2946 type = "passive"; 2947 }; 2948 2949 cpu3_alert1: trip-point1 { 2950 temperature = <95000>; 2951 hysteresis = <2000>; 2952 type = "passive"; 2953 }; 2954 2955 cpu3_crit: cpu_crit { 2956 temperature = <110000>; 2957 hysteresis = <1000>; 2958 type = "critical"; 2959 }; 2960 }; 2961 2962 cooling-maps { 2963 map0 { 2964 trip = <&cpu3_alert0>; 2965 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2966 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2967 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2968 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2969 }; 2970 map1 { 2971 trip = <&cpu3_alert1>; 2972 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2973 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2974 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2975 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2976 }; 2977 }; 2978 }; 2979 2980 cpu4-top-thermal { 2981 polling-delay-passive = <250>; 2982 polling-delay = <1000>; 2983 2984 thermal-sensors = <&tsens0 7>; 2985 2986 trips { 2987 cpu4_top_alert0: trip-point0 { 2988 temperature = <90000>; 2989 hysteresis = <2000>; 2990 type = "passive"; 2991 }; 2992 2993 cpu4_top_alert1: trip-point1 { 2994 temperature = <95000>; 2995 hysteresis = <2000>; 2996 type = "passive"; 2997 }; 2998 2999 cpu4_top_crit: cpu_crit { 3000 temperature = <110000>; 3001 hysteresis = <1000>; 3002 type = "critical"; 3003 }; 3004 }; 3005 3006 cooling-maps { 3007 map0 { 3008 trip = <&cpu4_top_alert0>; 3009 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3010 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3011 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3012 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3013 }; 3014 map1 { 3015 trip = <&cpu4_top_alert1>; 3016 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3017 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3018 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3019 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3020 }; 3021 }; 3022 }; 3023 3024 cpu5-top-thermal { 3025 polling-delay-passive = <250>; 3026 polling-delay = <1000>; 3027 3028 thermal-sensors = <&tsens0 8>; 3029 3030 trips { 3031 cpu5_top_alert0: trip-point0 { 3032 temperature = <90000>; 3033 hysteresis = <2000>; 3034 type = "passive"; 3035 }; 3036 3037 cpu5_top_alert1: trip-point1 { 3038 temperature = <95000>; 3039 hysteresis = <2000>; 3040 type = "passive"; 3041 }; 3042 3043 cpu5_top_crit: cpu_crit { 3044 temperature = <110000>; 3045 hysteresis = <1000>; 3046 type = "critical"; 3047 }; 3048 }; 3049 3050 cooling-maps { 3051 map0 { 3052 trip = <&cpu5_top_alert0>; 3053 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3054 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3055 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3056 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3057 }; 3058 map1 { 3059 trip = <&cpu5_top_alert1>; 3060 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3061 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3062 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3063 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3064 }; 3065 }; 3066 }; 3067 3068 cpu6-top-thermal { 3069 polling-delay-passive = <250>; 3070 polling-delay = <1000>; 3071 3072 thermal-sensors = <&tsens0 9>; 3073 3074 trips { 3075 cpu6_top_alert0: trip-point0 { 3076 temperature = <90000>; 3077 hysteresis = <2000>; 3078 type = "passive"; 3079 }; 3080 3081 cpu6_top_alert1: trip-point1 { 3082 temperature = <95000>; 3083 hysteresis = <2000>; 3084 type = "passive"; 3085 }; 3086 3087 cpu6_top_crit: cpu_crit { 3088 temperature = <110000>; 3089 hysteresis = <1000>; 3090 type = "critical"; 3091 }; 3092 }; 3093 3094 cooling-maps { 3095 map0 { 3096 trip = <&cpu6_top_alert0>; 3097 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3098 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3099 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3100 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3101 }; 3102 map1 { 3103 trip = <&cpu6_top_alert1>; 3104 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3105 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3106 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3107 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3108 }; 3109 }; 3110 }; 3111 3112 cpu7-top-thermal { 3113 polling-delay-passive = <250>; 3114 polling-delay = <1000>; 3115 3116 thermal-sensors = <&tsens0 10>; 3117 3118 trips { 3119 cpu7_top_alert0: trip-point0 { 3120 temperature = <90000>; 3121 hysteresis = <2000>; 3122 type = "passive"; 3123 }; 3124 3125 cpu7_top_alert1: trip-point1 { 3126 temperature = <95000>; 3127 hysteresis = <2000>; 3128 type = "passive"; 3129 }; 3130 3131 cpu7_top_crit: cpu_crit { 3132 temperature = <110000>; 3133 hysteresis = <1000>; 3134 type = "critical"; 3135 }; 3136 }; 3137 3138 cooling-maps { 3139 map0 { 3140 trip = <&cpu7_top_alert0>; 3141 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3142 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3143 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3144 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3145 }; 3146 map1 { 3147 trip = <&cpu7_top_alert1>; 3148 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3149 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3150 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3151 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3152 }; 3153 }; 3154 }; 3155 3156 cpu4-bottom-thermal { 3157 polling-delay-passive = <250>; 3158 polling-delay = <1000>; 3159 3160 thermal-sensors = <&tsens0 11>; 3161 3162 trips { 3163 cpu4_bottom_alert0: trip-point0 { 3164 temperature = <90000>; 3165 hysteresis = <2000>; 3166 type = "passive"; 3167 }; 3168 3169 cpu4_bottom_alert1: trip-point1 { 3170 temperature = <95000>; 3171 hysteresis = <2000>; 3172 type = "passive"; 3173 }; 3174 3175 cpu4_bottom_crit: cpu_crit { 3176 temperature = <110000>; 3177 hysteresis = <1000>; 3178 type = "critical"; 3179 }; 3180 }; 3181 3182 cooling-maps { 3183 map0 { 3184 trip = <&cpu4_bottom_alert0>; 3185 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3186 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3187 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3188 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3189 }; 3190 map1 { 3191 trip = <&cpu4_bottom_alert1>; 3192 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3193 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3194 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3195 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3196 }; 3197 }; 3198 }; 3199 3200 cpu5-bottom-thermal { 3201 polling-delay-passive = <250>; 3202 polling-delay = <1000>; 3203 3204 thermal-sensors = <&tsens0 12>; 3205 3206 trips { 3207 cpu5_bottom_alert0: trip-point0 { 3208 temperature = <90000>; 3209 hysteresis = <2000>; 3210 type = "passive"; 3211 }; 3212 3213 cpu5_bottom_alert1: trip-point1 { 3214 temperature = <95000>; 3215 hysteresis = <2000>; 3216 type = "passive"; 3217 }; 3218 3219 cpu5_bottom_crit: cpu_crit { 3220 temperature = <110000>; 3221 hysteresis = <1000>; 3222 type = "critical"; 3223 }; 3224 }; 3225 3226 cooling-maps { 3227 map0 { 3228 trip = <&cpu5_bottom_alert0>; 3229 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3230 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3231 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3232 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3233 }; 3234 map1 { 3235 trip = <&cpu5_bottom_alert1>; 3236 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3237 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3238 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3239 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3240 }; 3241 }; 3242 }; 3243 3244 cpu6-bottom-thermal { 3245 polling-delay-passive = <250>; 3246 polling-delay = <1000>; 3247 3248 thermal-sensors = <&tsens0 13>; 3249 3250 trips { 3251 cpu6_bottom_alert0: trip-point0 { 3252 temperature = <90000>; 3253 hysteresis = <2000>; 3254 type = "passive"; 3255 }; 3256 3257 cpu6_bottom_alert1: trip-point1 { 3258 temperature = <95000>; 3259 hysteresis = <2000>; 3260 type = "passive"; 3261 }; 3262 3263 cpu6_bottom_crit: cpu_crit { 3264 temperature = <110000>; 3265 hysteresis = <1000>; 3266 type = "critical"; 3267 }; 3268 }; 3269 3270 cooling-maps { 3271 map0 { 3272 trip = <&cpu6_bottom_alert0>; 3273 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3274 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3275 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3276 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3277 }; 3278 map1 { 3279 trip = <&cpu6_bottom_alert1>; 3280 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3281 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3282 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3283 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3284 }; 3285 }; 3286 }; 3287 3288 cpu7-bottom-thermal { 3289 polling-delay-passive = <250>; 3290 polling-delay = <1000>; 3291 3292 thermal-sensors = <&tsens0 14>; 3293 3294 trips { 3295 cpu7_bottom_alert0: trip-point0 { 3296 temperature = <90000>; 3297 hysteresis = <2000>; 3298 type = "passive"; 3299 }; 3300 3301 cpu7_bottom_alert1: trip-point1 { 3302 temperature = <95000>; 3303 hysteresis = <2000>; 3304 type = "passive"; 3305 }; 3306 3307 cpu7_bottom_crit: cpu_crit { 3308 temperature = <110000>; 3309 hysteresis = <1000>; 3310 type = "critical"; 3311 }; 3312 }; 3313 3314 cooling-maps { 3315 map0 { 3316 trip = <&cpu7_bottom_alert0>; 3317 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3318 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3319 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3320 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3321 }; 3322 map1 { 3323 trip = <&cpu7_bottom_alert1>; 3324 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3325 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3326 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3327 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3328 }; 3329 }; 3330 }; 3331 3332 aoss0-thermal { 3333 polling-delay-passive = <250>; 3334 polling-delay = <1000>; 3335 3336 thermal-sensors = <&tsens0 0>; 3337 3338 trips { 3339 aoss0_alert0: trip-point0 { 3340 temperature = <90000>; 3341 hysteresis = <2000>; 3342 type = "hot"; 3343 }; 3344 }; 3345 }; 3346 3347 cluster0-thermal { 3348 polling-delay-passive = <250>; 3349 polling-delay = <1000>; 3350 3351 thermal-sensors = <&tsens0 5>; 3352 3353 trips { 3354 cluster0_alert0: trip-point0 { 3355 temperature = <90000>; 3356 hysteresis = <2000>; 3357 type = "hot"; 3358 }; 3359 cluster0_crit: cluster0_crit { 3360 temperature = <110000>; 3361 hysteresis = <2000>; 3362 type = "critical"; 3363 }; 3364 }; 3365 }; 3366 3367 cluster1-thermal { 3368 polling-delay-passive = <250>; 3369 polling-delay = <1000>; 3370 3371 thermal-sensors = <&tsens0 6>; 3372 3373 trips { 3374 cluster1_alert0: trip-point0 { 3375 temperature = <90000>; 3376 hysteresis = <2000>; 3377 type = "hot"; 3378 }; 3379 cluster1_crit: cluster1_crit { 3380 temperature = <110000>; 3381 hysteresis = <2000>; 3382 type = "critical"; 3383 }; 3384 }; 3385 }; 3386 3387 gpu-thermal-top { 3388 polling-delay-passive = <250>; 3389 polling-delay = <1000>; 3390 3391 thermal-sensors = <&tsens0 15>; 3392 3393 trips { 3394 gpu1_alert0: trip-point0 { 3395 temperature = <90000>; 3396 hysteresis = <2000>; 3397 type = "hot"; 3398 }; 3399 }; 3400 }; 3401 3402 aoss1-thermal { 3403 polling-delay-passive = <250>; 3404 polling-delay = <1000>; 3405 3406 thermal-sensors = <&tsens1 0>; 3407 3408 trips { 3409 aoss1_alert0: trip-point0 { 3410 temperature = <90000>; 3411 hysteresis = <2000>; 3412 type = "hot"; 3413 }; 3414 }; 3415 }; 3416 3417 wlan-thermal { 3418 polling-delay-passive = <250>; 3419 polling-delay = <1000>; 3420 3421 thermal-sensors = <&tsens1 1>; 3422 3423 trips { 3424 wlan_alert0: trip-point0 { 3425 temperature = <90000>; 3426 hysteresis = <2000>; 3427 type = "hot"; 3428 }; 3429 }; 3430 }; 3431 3432 video-thermal { 3433 polling-delay-passive = <250>; 3434 polling-delay = <1000>; 3435 3436 thermal-sensors = <&tsens1 2>; 3437 3438 trips { 3439 video_alert0: trip-point0 { 3440 temperature = <90000>; 3441 hysteresis = <2000>; 3442 type = "hot"; 3443 }; 3444 }; 3445 }; 3446 3447 mem-thermal { 3448 polling-delay-passive = <250>; 3449 polling-delay = <1000>; 3450 3451 thermal-sensors = <&tsens1 3>; 3452 3453 trips { 3454 mem_alert0: trip-point0 { 3455 temperature = <90000>; 3456 hysteresis = <2000>; 3457 type = "hot"; 3458 }; 3459 }; 3460 }; 3461 3462 q6-hvx-thermal { 3463 polling-delay-passive = <250>; 3464 polling-delay = <1000>; 3465 3466 thermal-sensors = <&tsens1 4>; 3467 3468 trips { 3469 q6_hvx_alert0: trip-point0 { 3470 temperature = <90000>; 3471 hysteresis = <2000>; 3472 type = "hot"; 3473 }; 3474 }; 3475 }; 3476 3477 camera-thermal { 3478 polling-delay-passive = <250>; 3479 polling-delay = <1000>; 3480 3481 thermal-sensors = <&tsens1 5>; 3482 3483 trips { 3484 camera_alert0: trip-point0 { 3485 temperature = <90000>; 3486 hysteresis = <2000>; 3487 type = "hot"; 3488 }; 3489 }; 3490 }; 3491 3492 compute-thermal { 3493 polling-delay-passive = <250>; 3494 polling-delay = <1000>; 3495 3496 thermal-sensors = <&tsens1 6>; 3497 3498 trips { 3499 compute_alert0: trip-point0 { 3500 temperature = <90000>; 3501 hysteresis = <2000>; 3502 type = "hot"; 3503 }; 3504 }; 3505 }; 3506 3507 modem-thermal { 3508 polling-delay-passive = <250>; 3509 polling-delay = <1000>; 3510 3511 thermal-sensors = <&tsens1 7>; 3512 3513 trips { 3514 modem_alert0: trip-point0 { 3515 temperature = <90000>; 3516 hysteresis = <2000>; 3517 type = "hot"; 3518 }; 3519 }; 3520 }; 3521 3522 npu-thermal { 3523 polling-delay-passive = <250>; 3524 polling-delay = <1000>; 3525 3526 thermal-sensors = <&tsens1 8>; 3527 3528 trips { 3529 npu_alert0: trip-point0 { 3530 temperature = <90000>; 3531 hysteresis = <2000>; 3532 type = "hot"; 3533 }; 3534 }; 3535 }; 3536 3537 modem-vec-thermal { 3538 polling-delay-passive = <250>; 3539 polling-delay = <1000>; 3540 3541 thermal-sensors = <&tsens1 9>; 3542 3543 trips { 3544 modem_vec_alert0: trip-point0 { 3545 temperature = <90000>; 3546 hysteresis = <2000>; 3547 type = "hot"; 3548 }; 3549 }; 3550 }; 3551 3552 modem-scl-thermal { 3553 polling-delay-passive = <250>; 3554 polling-delay = <1000>; 3555 3556 thermal-sensors = <&tsens1 10>; 3557 3558 trips { 3559 modem_scl_alert0: trip-point0 { 3560 temperature = <90000>; 3561 hysteresis = <2000>; 3562 type = "hot"; 3563 }; 3564 }; 3565 }; 3566 3567 gpu-thermal-bottom { 3568 polling-delay-passive = <250>; 3569 polling-delay = <1000>; 3570 3571 thermal-sensors = <&tsens1 11>; 3572 3573 trips { 3574 gpu2_alert0: trip-point0 { 3575 temperature = <90000>; 3576 hysteresis = <2000>; 3577 type = "hot"; 3578 }; 3579 }; 3580 }; 3581 }; 3582}; 3583