1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/dma/qcom-gpi.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/power/qcom-aoss-qmp.h> 10#include <dt-bindings/power/qcom-rpmpd.h> 11#include <dt-bindings/soc/qcom,rpmh-rsc.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,gcc-sm8150.h> 14#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sm8150.h> 17#include <dt-bindings/thermal/thermal.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 chosen { }; 26 27 clocks { 28 xo_board: xo-board { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <38400000>; 32 clock-output-names = "xo_board"; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32764>; 39 clock-output-names = "sleep_clk"; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 CPU0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "qcom,kryo485"; 50 reg = <0x0 0x0>; 51 enable-method = "psci"; 52 capacity-dmips-mhz = <488>; 53 dynamic-power-coefficient = <232>; 54 next-level-cache = <&L2_0>; 55 qcom,freq-domain = <&cpufreq_hw 0>; 56 operating-points-v2 = <&cpu0_opp_table>; 57 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 58 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 59 power-domains = <&CPU_PD0>; 60 power-domain-names = "psci"; 61 #cooling-cells = <2>; 62 L2_0: l2-cache { 63 compatible = "cache"; 64 next-level-cache = <&L3_0>; 65 L3_0: l3-cache { 66 compatible = "cache"; 67 }; 68 }; 69 }; 70 71 CPU1: cpu@100 { 72 device_type = "cpu"; 73 compatible = "qcom,kryo485"; 74 reg = <0x0 0x100>; 75 enable-method = "psci"; 76 capacity-dmips-mhz = <488>; 77 dynamic-power-coefficient = <232>; 78 next-level-cache = <&L2_100>; 79 qcom,freq-domain = <&cpufreq_hw 0>; 80 operating-points-v2 = <&cpu0_opp_table>; 81 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 82 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 83 power-domains = <&CPU_PD1>; 84 power-domain-names = "psci"; 85 #cooling-cells = <2>; 86 L2_100: l2-cache { 87 compatible = "cache"; 88 next-level-cache = <&L3_0>; 89 }; 90 91 }; 92 93 CPU2: cpu@200 { 94 device_type = "cpu"; 95 compatible = "qcom,kryo485"; 96 reg = <0x0 0x200>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <488>; 99 dynamic-power-coefficient = <232>; 100 next-level-cache = <&L2_200>; 101 qcom,freq-domain = <&cpufreq_hw 0>; 102 operating-points-v2 = <&cpu0_opp_table>; 103 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 104 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 105 power-domains = <&CPU_PD2>; 106 power-domain-names = "psci"; 107 #cooling-cells = <2>; 108 L2_200: l2-cache { 109 compatible = "cache"; 110 next-level-cache = <&L3_0>; 111 }; 112 }; 113 114 CPU3: cpu@300 { 115 device_type = "cpu"; 116 compatible = "qcom,kryo485"; 117 reg = <0x0 0x300>; 118 enable-method = "psci"; 119 capacity-dmips-mhz = <488>; 120 dynamic-power-coefficient = <232>; 121 next-level-cache = <&L2_300>; 122 qcom,freq-domain = <&cpufreq_hw 0>; 123 operating-points-v2 = <&cpu0_opp_table>; 124 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 125 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 126 power-domains = <&CPU_PD3>; 127 power-domain-names = "psci"; 128 #cooling-cells = <2>; 129 L2_300: l2-cache { 130 compatible = "cache"; 131 next-level-cache = <&L3_0>; 132 }; 133 }; 134 135 CPU4: cpu@400 { 136 device_type = "cpu"; 137 compatible = "qcom,kryo485"; 138 reg = <0x0 0x400>; 139 enable-method = "psci"; 140 capacity-dmips-mhz = <1024>; 141 dynamic-power-coefficient = <369>; 142 next-level-cache = <&L2_400>; 143 qcom,freq-domain = <&cpufreq_hw 1>; 144 operating-points-v2 = <&cpu4_opp_table>; 145 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 146 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 147 power-domains = <&CPU_PD4>; 148 power-domain-names = "psci"; 149 #cooling-cells = <2>; 150 L2_400: l2-cache { 151 compatible = "cache"; 152 next-level-cache = <&L3_0>; 153 }; 154 }; 155 156 CPU5: cpu@500 { 157 device_type = "cpu"; 158 compatible = "qcom,kryo485"; 159 reg = <0x0 0x500>; 160 enable-method = "psci"; 161 capacity-dmips-mhz = <1024>; 162 dynamic-power-coefficient = <369>; 163 next-level-cache = <&L2_500>; 164 qcom,freq-domain = <&cpufreq_hw 1>; 165 operating-points-v2 = <&cpu4_opp_table>; 166 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 167 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 168 power-domains = <&CPU_PD5>; 169 power-domain-names = "psci"; 170 #cooling-cells = <2>; 171 L2_500: l2-cache { 172 compatible = "cache"; 173 next-level-cache = <&L3_0>; 174 }; 175 }; 176 177 CPU6: cpu@600 { 178 device_type = "cpu"; 179 compatible = "qcom,kryo485"; 180 reg = <0x0 0x600>; 181 enable-method = "psci"; 182 capacity-dmips-mhz = <1024>; 183 dynamic-power-coefficient = <369>; 184 next-level-cache = <&L2_600>; 185 qcom,freq-domain = <&cpufreq_hw 1>; 186 operating-points-v2 = <&cpu4_opp_table>; 187 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 188 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 189 power-domains = <&CPU_PD6>; 190 power-domain-names = "psci"; 191 #cooling-cells = <2>; 192 L2_600: l2-cache { 193 compatible = "cache"; 194 next-level-cache = <&L3_0>; 195 }; 196 }; 197 198 CPU7: cpu@700 { 199 device_type = "cpu"; 200 compatible = "qcom,kryo485"; 201 reg = <0x0 0x700>; 202 enable-method = "psci"; 203 capacity-dmips-mhz = <1024>; 204 dynamic-power-coefficient = <421>; 205 next-level-cache = <&L2_700>; 206 qcom,freq-domain = <&cpufreq_hw 2>; 207 operating-points-v2 = <&cpu7_opp_table>; 208 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 209 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 210 power-domains = <&CPU_PD7>; 211 power-domain-names = "psci"; 212 #cooling-cells = <2>; 213 L2_700: l2-cache { 214 compatible = "cache"; 215 next-level-cache = <&L3_0>; 216 }; 217 }; 218 219 cpu-map { 220 cluster0 { 221 core0 { 222 cpu = <&CPU0>; 223 }; 224 225 core1 { 226 cpu = <&CPU1>; 227 }; 228 229 core2 { 230 cpu = <&CPU2>; 231 }; 232 233 core3 { 234 cpu = <&CPU3>; 235 }; 236 237 core4 { 238 cpu = <&CPU4>; 239 }; 240 241 core5 { 242 cpu = <&CPU5>; 243 }; 244 245 core6 { 246 cpu = <&CPU6>; 247 }; 248 249 core7 { 250 cpu = <&CPU7>; 251 }; 252 }; 253 }; 254 255 idle-states { 256 entry-method = "psci"; 257 258 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 259 compatible = "arm,idle-state"; 260 idle-state-name = "little-rail-power-collapse"; 261 arm,psci-suspend-param = <0x40000004>; 262 entry-latency-us = <355>; 263 exit-latency-us = <909>; 264 min-residency-us = <3934>; 265 local-timer-stop; 266 }; 267 268 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 269 compatible = "arm,idle-state"; 270 idle-state-name = "big-rail-power-collapse"; 271 arm,psci-suspend-param = <0x40000004>; 272 entry-latency-us = <241>; 273 exit-latency-us = <1461>; 274 min-residency-us = <4488>; 275 local-timer-stop; 276 }; 277 }; 278 279 domain-idle-states { 280 CLUSTER_SLEEP_0: cluster-sleep-0 { 281 compatible = "domain-idle-state"; 282 idle-state-name = "cluster-power-collapse"; 283 arm,psci-suspend-param = <0x4100c244>; 284 entry-latency-us = <3263>; 285 exit-latency-us = <6562>; 286 min-residency-us = <9987>; 287 local-timer-stop; 288 }; 289 }; 290 }; 291 292 cpu0_opp_table: cpu0_opp_table { 293 compatible = "operating-points-v2"; 294 opp-shared; 295 296 cpu0_opp1: opp-300000000 { 297 opp-hz = /bits/ 64 <300000000>; 298 opp-peak-kBps = <800000 9600000>; 299 }; 300 301 cpu0_opp2: opp-403200000 { 302 opp-hz = /bits/ 64 <403200000>; 303 opp-peak-kBps = <800000 9600000>; 304 }; 305 306 cpu0_opp3: opp-499200000 { 307 opp-hz = /bits/ 64 <499200000>; 308 opp-peak-kBps = <800000 12902400>; 309 }; 310 311 cpu0_opp4: opp-576000000 { 312 opp-hz = /bits/ 64 <576000000>; 313 opp-peak-kBps = <800000 12902400>; 314 }; 315 316 cpu0_opp5: opp-672000000 { 317 opp-hz = /bits/ 64 <672000000>; 318 opp-peak-kBps = <800000 15974400>; 319 }; 320 321 cpu0_opp6: opp-768000000 { 322 opp-hz = /bits/ 64 <768000000>; 323 opp-peak-kBps = <1804000 19660800>; 324 }; 325 326 cpu0_opp7: opp-844800000 { 327 opp-hz = /bits/ 64 <844800000>; 328 opp-peak-kBps = <1804000 19660800>; 329 }; 330 331 cpu0_opp8: opp-940800000 { 332 opp-hz = /bits/ 64 <940800000>; 333 opp-peak-kBps = <1804000 22732800>; 334 }; 335 336 cpu0_opp9: opp-1036800000 { 337 opp-hz = /bits/ 64 <1036800000>; 338 opp-peak-kBps = <1804000 22732800>; 339 }; 340 341 cpu0_opp10: opp-1113600000 { 342 opp-hz = /bits/ 64 <1113600000>; 343 opp-peak-kBps = <2188000 25804800>; 344 }; 345 346 cpu0_opp11: opp-1209600000 { 347 opp-hz = /bits/ 64 <1209600000>; 348 opp-peak-kBps = <2188000 31948800>; 349 }; 350 351 cpu0_opp12: opp-1305600000 { 352 opp-hz = /bits/ 64 <1305600000>; 353 opp-peak-kBps = <3072000 31948800>; 354 }; 355 356 cpu0_opp13: opp-1382400000 { 357 opp-hz = /bits/ 64 <1382400000>; 358 opp-peak-kBps = <3072000 31948800>; 359 }; 360 361 cpu0_opp14: opp-1478400000 { 362 opp-hz = /bits/ 64 <1478400000>; 363 opp-peak-kBps = <3072000 31948800>; 364 }; 365 366 cpu0_opp15: opp-1555200000 { 367 opp-hz = /bits/ 64 <1555200000>; 368 opp-peak-kBps = <3072000 40550400>; 369 }; 370 371 cpu0_opp16: opp-1632000000 { 372 opp-hz = /bits/ 64 <1632000000>; 373 opp-peak-kBps = <3072000 40550400>; 374 }; 375 376 cpu0_opp17: opp-1708800000 { 377 opp-hz = /bits/ 64 <1708800000>; 378 opp-peak-kBps = <3072000 43008000>; 379 }; 380 381 cpu0_opp18: opp-1785600000 { 382 opp-hz = /bits/ 64 <1785600000>; 383 opp-peak-kBps = <3072000 43008000>; 384 }; 385 }; 386 387 cpu4_opp_table: cpu4_opp_table { 388 compatible = "operating-points-v2"; 389 opp-shared; 390 391 cpu4_opp1: opp-710400000 { 392 opp-hz = /bits/ 64 <710400000>; 393 opp-peak-kBps = <1804000 15974400>; 394 }; 395 396 cpu4_opp2: opp-825600000 { 397 opp-hz = /bits/ 64 <825600000>; 398 opp-peak-kBps = <2188000 19660800>; 399 }; 400 401 cpu4_opp3: opp-940800000 { 402 opp-hz = /bits/ 64 <940800000>; 403 opp-peak-kBps = <2188000 22732800>; 404 }; 405 406 cpu4_opp4: opp-1056000000 { 407 opp-hz = /bits/ 64 <1056000000>; 408 opp-peak-kBps = <3072000 25804800>; 409 }; 410 411 cpu4_opp5: opp-1171200000 { 412 opp-hz = /bits/ 64 <1171200000>; 413 opp-peak-kBps = <3072000 31948800>; 414 }; 415 416 cpu4_opp6: opp-1286400000 { 417 opp-hz = /bits/ 64 <1286400000>; 418 opp-peak-kBps = <4068000 31948800>; 419 }; 420 421 cpu4_opp7: opp-1401600000 { 422 opp-hz = /bits/ 64 <1401600000>; 423 opp-peak-kBps = <4068000 31948800>; 424 }; 425 426 cpu4_opp8: opp-1497600000 { 427 opp-hz = /bits/ 64 <1497600000>; 428 opp-peak-kBps = <4068000 40550400>; 429 }; 430 431 cpu4_opp9: opp-1612800000 { 432 opp-hz = /bits/ 64 <1612800000>; 433 opp-peak-kBps = <4068000 40550400>; 434 }; 435 436 cpu4_opp10: opp-1708800000 { 437 opp-hz = /bits/ 64 <1708800000>; 438 opp-peak-kBps = <4068000 43008000>; 439 }; 440 441 cpu4_opp11: opp-1804800000 { 442 opp-hz = /bits/ 64 <1804800000>; 443 opp-peak-kBps = <6220000 43008000>; 444 }; 445 446 cpu4_opp12: opp-1920000000 { 447 opp-hz = /bits/ 64 <1920000000>; 448 opp-peak-kBps = <6220000 49152000>; 449 }; 450 451 cpu4_opp13: opp-2016000000 { 452 opp-hz = /bits/ 64 <2016000000>; 453 opp-peak-kBps = <7216000 49152000>; 454 }; 455 456 cpu4_opp14: opp-2131200000 { 457 opp-hz = /bits/ 64 <2131200000>; 458 opp-peak-kBps = <8368000 49152000>; 459 }; 460 461 cpu4_opp15: opp-2227200000 { 462 opp-hz = /bits/ 64 <2227200000>; 463 opp-peak-kBps = <8368000 51609600>; 464 }; 465 466 cpu4_opp16: opp-2323200000 { 467 opp-hz = /bits/ 64 <2323200000>; 468 opp-peak-kBps = <8368000 51609600>; 469 }; 470 471 cpu4_opp17: opp-2419200000 { 472 opp-hz = /bits/ 64 <2419200000>; 473 opp-peak-kBps = <8368000 51609600>; 474 }; 475 }; 476 477 cpu7_opp_table: cpu7_opp_table { 478 compatible = "operating-points-v2"; 479 opp-shared; 480 481 cpu7_opp1: opp-825600000 { 482 opp-hz = /bits/ 64 <825600000>; 483 opp-peak-kBps = <2188000 19660800>; 484 }; 485 486 cpu7_opp2: opp-940800000 { 487 opp-hz = /bits/ 64 <940800000>; 488 opp-peak-kBps = <2188000 22732800>; 489 }; 490 491 cpu7_opp3: opp-1056000000 { 492 opp-hz = /bits/ 64 <1056000000>; 493 opp-peak-kBps = <3072000 25804800>; 494 }; 495 496 cpu7_opp4: opp-1171200000 { 497 opp-hz = /bits/ 64 <1171200000>; 498 opp-peak-kBps = <3072000 31948800>; 499 }; 500 501 cpu7_opp5: opp-1286400000 { 502 opp-hz = /bits/ 64 <1286400000>; 503 opp-peak-kBps = <4068000 31948800>; 504 }; 505 506 cpu7_opp6: opp-1401600000 { 507 opp-hz = /bits/ 64 <1401600000>; 508 opp-peak-kBps = <4068000 31948800>; 509 }; 510 511 cpu7_opp7: opp-1497600000 { 512 opp-hz = /bits/ 64 <1497600000>; 513 opp-peak-kBps = <4068000 40550400>; 514 }; 515 516 cpu7_opp8: opp-1612800000 { 517 opp-hz = /bits/ 64 <1612800000>; 518 opp-peak-kBps = <4068000 40550400>; 519 }; 520 521 cpu7_opp9: opp-1708800000 { 522 opp-hz = /bits/ 64 <1708800000>; 523 opp-peak-kBps = <4068000 43008000>; 524 }; 525 526 cpu7_opp10: opp-1804800000 { 527 opp-hz = /bits/ 64 <1804800000>; 528 opp-peak-kBps = <6220000 43008000>; 529 }; 530 531 cpu7_opp11: opp-1920000000 { 532 opp-hz = /bits/ 64 <1920000000>; 533 opp-peak-kBps = <6220000 49152000>; 534 }; 535 536 cpu7_opp12: opp-2016000000 { 537 opp-hz = /bits/ 64 <2016000000>; 538 opp-peak-kBps = <7216000 49152000>; 539 }; 540 541 cpu7_opp13: opp-2131200000 { 542 opp-hz = /bits/ 64 <2131200000>; 543 opp-peak-kBps = <8368000 49152000>; 544 }; 545 546 cpu7_opp14: opp-2227200000 { 547 opp-hz = /bits/ 64 <2227200000>; 548 opp-peak-kBps = <8368000 51609600>; 549 }; 550 551 cpu7_opp15: opp-2323200000 { 552 opp-hz = /bits/ 64 <2323200000>; 553 opp-peak-kBps = <8368000 51609600>; 554 }; 555 556 cpu7_opp16: opp-2419200000 { 557 opp-hz = /bits/ 64 <2419200000>; 558 opp-peak-kBps = <8368000 51609600>; 559 }; 560 561 cpu7_opp17: opp-2534400000 { 562 opp-hz = /bits/ 64 <2534400000>; 563 opp-peak-kBps = <8368000 51609600>; 564 }; 565 566 cpu7_opp18: opp-2649600000 { 567 opp-hz = /bits/ 64 <2649600000>; 568 opp-peak-kBps = <8368000 51609600>; 569 }; 570 571 cpu7_opp19: opp-2745600000 { 572 opp-hz = /bits/ 64 <2745600000>; 573 opp-peak-kBps = <8368000 51609600>; 574 }; 575 576 cpu7_opp20: opp-2841600000 { 577 opp-hz = /bits/ 64 <2841600000>; 578 opp-peak-kBps = <8368000 51609600>; 579 }; 580 }; 581 582 firmware { 583 scm: scm { 584 compatible = "qcom,scm-sm8150", "qcom,scm"; 585 #reset-cells = <1>; 586 }; 587 }; 588 589 tcsr_mutex: hwlock { 590 compatible = "qcom,tcsr-mutex"; 591 syscon = <&tcsr_mutex_regs 0 0x1000>; 592 #hwlock-cells = <1>; 593 }; 594 595 memory@80000000 { 596 device_type = "memory"; 597 /* We expect the bootloader to fill in the size */ 598 reg = <0x0 0x80000000 0x0 0x0>; 599 }; 600 601 pmu { 602 compatible = "arm,armv8-pmuv3"; 603 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 604 }; 605 606 psci { 607 compatible = "arm,psci-1.0"; 608 method = "smc"; 609 610 CPU_PD0: cpu0 { 611 #power-domain-cells = <0>; 612 power-domains = <&CLUSTER_PD>; 613 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 614 }; 615 616 CPU_PD1: cpu1 { 617 #power-domain-cells = <0>; 618 power-domains = <&CLUSTER_PD>; 619 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 620 }; 621 622 CPU_PD2: cpu2 { 623 #power-domain-cells = <0>; 624 power-domains = <&CLUSTER_PD>; 625 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 626 }; 627 628 CPU_PD3: cpu3 { 629 #power-domain-cells = <0>; 630 power-domains = <&CLUSTER_PD>; 631 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 632 }; 633 634 CPU_PD4: cpu4 { 635 #power-domain-cells = <0>; 636 power-domains = <&CLUSTER_PD>; 637 domain-idle-states = <&BIG_CPU_SLEEP_0>; 638 }; 639 640 CPU_PD5: cpu5 { 641 #power-domain-cells = <0>; 642 power-domains = <&CLUSTER_PD>; 643 domain-idle-states = <&BIG_CPU_SLEEP_0>; 644 }; 645 646 CPU_PD6: cpu6 { 647 #power-domain-cells = <0>; 648 power-domains = <&CLUSTER_PD>; 649 domain-idle-states = <&BIG_CPU_SLEEP_0>; 650 }; 651 652 CPU_PD7: cpu7 { 653 #power-domain-cells = <0>; 654 power-domains = <&CLUSTER_PD>; 655 domain-idle-states = <&BIG_CPU_SLEEP_0>; 656 }; 657 658 CLUSTER_PD: cpu-cluster0 { 659 #power-domain-cells = <0>; 660 domain-idle-states = <&CLUSTER_SLEEP_0>; 661 }; 662 }; 663 664 reserved-memory { 665 #address-cells = <2>; 666 #size-cells = <2>; 667 ranges; 668 669 hyp_mem: memory@85700000 { 670 reg = <0x0 0x85700000 0x0 0x600000>; 671 no-map; 672 }; 673 674 xbl_mem: memory@85d00000 { 675 reg = <0x0 0x85d00000 0x0 0x140000>; 676 no-map; 677 }; 678 679 aop_mem: memory@85f00000 { 680 reg = <0x0 0x85f00000 0x0 0x20000>; 681 no-map; 682 }; 683 684 aop_cmd_db: memory@85f20000 { 685 compatible = "qcom,cmd-db"; 686 reg = <0x0 0x85f20000 0x0 0x20000>; 687 no-map; 688 }; 689 690 smem_mem: memory@86000000 { 691 reg = <0x0 0x86000000 0x0 0x200000>; 692 no-map; 693 }; 694 695 tz_mem: memory@86200000 { 696 reg = <0x0 0x86200000 0x0 0x3900000>; 697 no-map; 698 }; 699 700 rmtfs_mem: memory@89b00000 { 701 compatible = "qcom,rmtfs-mem"; 702 reg = <0x0 0x89b00000 0x0 0x200000>; 703 no-map; 704 705 qcom,client-id = <1>; 706 qcom,vmid = <15>; 707 }; 708 709 camera_mem: memory@8b700000 { 710 reg = <0x0 0x8b700000 0x0 0x500000>; 711 no-map; 712 }; 713 714 wlan_mem: memory@8bc00000 { 715 reg = <0x0 0x8bc00000 0x0 0x180000>; 716 no-map; 717 }; 718 719 npu_mem: memory@8bd80000 { 720 reg = <0x0 0x8bd80000 0x0 0x80000>; 721 no-map; 722 }; 723 724 adsp_mem: memory@8be00000 { 725 reg = <0x0 0x8be00000 0x0 0x1a00000>; 726 no-map; 727 }; 728 729 mpss_mem: memory@8d800000 { 730 reg = <0x0 0x8d800000 0x0 0x9600000>; 731 no-map; 732 }; 733 734 venus_mem: memory@96e00000 { 735 reg = <0x0 0x96e00000 0x0 0x500000>; 736 no-map; 737 }; 738 739 slpi_mem: memory@97300000 { 740 reg = <0x0 0x97300000 0x0 0x1400000>; 741 no-map; 742 }; 743 744 ipa_fw_mem: memory@98700000 { 745 reg = <0x0 0x98700000 0x0 0x10000>; 746 no-map; 747 }; 748 749 ipa_gsi_mem: memory@98710000 { 750 reg = <0x0 0x98710000 0x0 0x5000>; 751 no-map; 752 }; 753 754 gpu_mem: memory@98715000 { 755 reg = <0x0 0x98715000 0x0 0x2000>; 756 no-map; 757 }; 758 759 spss_mem: memory@98800000 { 760 reg = <0x0 0x98800000 0x0 0x100000>; 761 no-map; 762 }; 763 764 cdsp_mem: memory@98900000 { 765 reg = <0x0 0x98900000 0x0 0x1400000>; 766 no-map; 767 }; 768 769 qseecom_mem: memory@9e400000 { 770 reg = <0x0 0x9e400000 0x0 0x1400000>; 771 no-map; 772 }; 773 }; 774 775 smem { 776 compatible = "qcom,smem"; 777 memory-region = <&smem_mem>; 778 hwlocks = <&tcsr_mutex 3>; 779 }; 780 781 smp2p-cdsp { 782 compatible = "qcom,smp2p"; 783 qcom,smem = <94>, <432>; 784 785 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 786 787 mboxes = <&apss_shared 6>; 788 789 qcom,local-pid = <0>; 790 qcom,remote-pid = <5>; 791 792 cdsp_smp2p_out: master-kernel { 793 qcom,entry-name = "master-kernel"; 794 #qcom,smem-state-cells = <1>; 795 }; 796 797 cdsp_smp2p_in: slave-kernel { 798 qcom,entry-name = "slave-kernel"; 799 800 interrupt-controller; 801 #interrupt-cells = <2>; 802 }; 803 }; 804 805 smp2p-lpass { 806 compatible = "qcom,smp2p"; 807 qcom,smem = <443>, <429>; 808 809 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 810 811 mboxes = <&apss_shared 10>; 812 813 qcom,local-pid = <0>; 814 qcom,remote-pid = <2>; 815 816 adsp_smp2p_out: master-kernel { 817 qcom,entry-name = "master-kernel"; 818 #qcom,smem-state-cells = <1>; 819 }; 820 821 adsp_smp2p_in: slave-kernel { 822 qcom,entry-name = "slave-kernel"; 823 824 interrupt-controller; 825 #interrupt-cells = <2>; 826 }; 827 }; 828 829 smp2p-mpss { 830 compatible = "qcom,smp2p"; 831 qcom,smem = <435>, <428>; 832 833 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 834 835 mboxes = <&apss_shared 14>; 836 837 qcom,local-pid = <0>; 838 qcom,remote-pid = <1>; 839 840 modem_smp2p_out: master-kernel { 841 qcom,entry-name = "master-kernel"; 842 #qcom,smem-state-cells = <1>; 843 }; 844 845 modem_smp2p_in: slave-kernel { 846 qcom,entry-name = "slave-kernel"; 847 848 interrupt-controller; 849 #interrupt-cells = <2>; 850 }; 851 }; 852 853 smp2p-slpi { 854 compatible = "qcom,smp2p"; 855 qcom,smem = <481>, <430>; 856 857 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 858 859 mboxes = <&apss_shared 26>; 860 861 qcom,local-pid = <0>; 862 qcom,remote-pid = <3>; 863 864 slpi_smp2p_out: master-kernel { 865 qcom,entry-name = "master-kernel"; 866 #qcom,smem-state-cells = <1>; 867 }; 868 869 slpi_smp2p_in: slave-kernel { 870 qcom,entry-name = "slave-kernel"; 871 872 interrupt-controller; 873 #interrupt-cells = <2>; 874 }; 875 }; 876 877 soc: soc@0 { 878 #address-cells = <2>; 879 #size-cells = <2>; 880 ranges = <0 0 0 0 0x10 0>; 881 dma-ranges = <0 0 0 0 0x10 0>; 882 compatible = "simple-bus"; 883 884 gcc: clock-controller@100000 { 885 compatible = "qcom,gcc-sm8150"; 886 reg = <0x0 0x00100000 0x0 0x1f0000>; 887 #clock-cells = <1>; 888 #reset-cells = <1>; 889 #power-domain-cells = <1>; 890 clock-names = "bi_tcxo", 891 "sleep_clk"; 892 clocks = <&rpmhcc RPMH_CXO_CLK>, 893 <&sleep_clk>; 894 }; 895 896 gpi_dma0: dma-controller@800000 { 897 compatible = "qcom,sm8150-gpi-dma"; 898 reg = <0 0x800000 0 0x60000>; 899 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 912 dma-channels = <13>; 913 dma-channel-mask = <0xfa>; 914 iommus = <&apps_smmu 0x00d6 0x0>; 915 #dma-cells = <3>; 916 status = "disabled"; 917 }; 918 919 qupv3_id_0: geniqup@8c0000 { 920 compatible = "qcom,geni-se-qup"; 921 reg = <0x0 0x008c0000 0x0 0x6000>; 922 clock-names = "m-ahb", "s-ahb"; 923 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 924 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 925 iommus = <&apps_smmu 0xc3 0x0>; 926 #address-cells = <2>; 927 #size-cells = <2>; 928 ranges; 929 status = "disabled"; 930 931 i2c0: i2c@880000 { 932 compatible = "qcom,geni-i2c"; 933 reg = <0 0x00880000 0 0x4000>; 934 clock-names = "se"; 935 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&qup_i2c0_default>; 938 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 939 #address-cells = <1>; 940 #size-cells = <0>; 941 status = "disabled"; 942 }; 943 944 spi0: spi@880000 { 945 compatible = "qcom,geni-spi"; 946 reg = <0 0x880000 0 0x4000>; 947 reg-names = "se"; 948 clock-names = "se"; 949 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 950 pinctrl-names = "default"; 951 pinctrl-0 = <&qup_spi0_default>; 952 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 953 spi-max-frequency = <50000000>; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 status = "disabled"; 957 }; 958 959 i2c1: i2c@884000 { 960 compatible = "qcom,geni-i2c"; 961 reg = <0 0x00884000 0 0x4000>; 962 clock-names = "se"; 963 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 964 pinctrl-names = "default"; 965 pinctrl-0 = <&qup_i2c1_default>; 966 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 status = "disabled"; 970 }; 971 972 spi1: spi@884000 { 973 compatible = "qcom,geni-spi"; 974 reg = <0 0x884000 0 0x4000>; 975 reg-names = "se"; 976 clock-names = "se"; 977 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 978 pinctrl-names = "default"; 979 pinctrl-0 = <&qup_spi1_default>; 980 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 981 spi-max-frequency = <50000000>; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 status = "disabled"; 985 }; 986 987 i2c2: i2c@888000 { 988 compatible = "qcom,geni-i2c"; 989 reg = <0 0x00888000 0 0x4000>; 990 clock-names = "se"; 991 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&qup_i2c2_default>; 994 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 status = "disabled"; 998 }; 999 1000 spi2: spi@888000 { 1001 compatible = "qcom,geni-spi"; 1002 reg = <0 0x888000 0 0x4000>; 1003 reg-names = "se"; 1004 clock-names = "se"; 1005 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1006 pinctrl-names = "default"; 1007 pinctrl-0 = <&qup_spi2_default>; 1008 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1009 spi-max-frequency = <50000000>; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 status = "disabled"; 1013 }; 1014 1015 i2c3: i2c@88c000 { 1016 compatible = "qcom,geni-i2c"; 1017 reg = <0 0x0088c000 0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&qup_i2c3_default>; 1022 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 status = "disabled"; 1026 }; 1027 1028 spi3: spi@88c000 { 1029 compatible = "qcom,geni-spi"; 1030 reg = <0 0x88c000 0 0x4000>; 1031 reg-names = "se"; 1032 clock-names = "se"; 1033 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1034 pinctrl-names = "default"; 1035 pinctrl-0 = <&qup_spi3_default>; 1036 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1037 spi-max-frequency = <50000000>; 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 status = "disabled"; 1041 }; 1042 1043 i2c4: i2c@890000 { 1044 compatible = "qcom,geni-i2c"; 1045 reg = <0 0x00890000 0 0x4000>; 1046 clock-names = "se"; 1047 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1048 pinctrl-names = "default"; 1049 pinctrl-0 = <&qup_i2c4_default>; 1050 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 status = "disabled"; 1054 }; 1055 1056 spi4: spi@890000 { 1057 compatible = "qcom,geni-spi"; 1058 reg = <0 0x890000 0 0x4000>; 1059 reg-names = "se"; 1060 clock-names = "se"; 1061 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1062 pinctrl-names = "default"; 1063 pinctrl-0 = <&qup_spi4_default>; 1064 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1065 spi-max-frequency = <50000000>; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 status = "disabled"; 1069 }; 1070 1071 i2c5: i2c@894000 { 1072 compatible = "qcom,geni-i2c"; 1073 reg = <0 0x00894000 0 0x4000>; 1074 clock-names = "se"; 1075 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1076 pinctrl-names = "default"; 1077 pinctrl-0 = <&qup_i2c5_default>; 1078 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 status = "disabled"; 1082 }; 1083 1084 spi5: spi@894000 { 1085 compatible = "qcom,geni-spi"; 1086 reg = <0 0x894000 0 0x4000>; 1087 reg-names = "se"; 1088 clock-names = "se"; 1089 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1090 pinctrl-names = "default"; 1091 pinctrl-0 = <&qup_spi5_default>; 1092 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1093 spi-max-frequency = <50000000>; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 status = "disabled"; 1097 }; 1098 1099 i2c6: i2c@898000 { 1100 compatible = "qcom,geni-i2c"; 1101 reg = <0 0x00898000 0 0x4000>; 1102 clock-names = "se"; 1103 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1104 pinctrl-names = "default"; 1105 pinctrl-0 = <&qup_i2c6_default>; 1106 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 status = "disabled"; 1110 }; 1111 1112 spi6: spi@898000 { 1113 compatible = "qcom,geni-spi"; 1114 reg = <0 0x898000 0 0x4000>; 1115 reg-names = "se"; 1116 clock-names = "se"; 1117 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_spi6_default>; 1120 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1121 spi-max-frequency = <50000000>; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 status = "disabled"; 1125 }; 1126 1127 i2c7: i2c@89c000 { 1128 compatible = "qcom,geni-i2c"; 1129 reg = <0 0x0089c000 0 0x4000>; 1130 clock-names = "se"; 1131 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1132 pinctrl-names = "default"; 1133 pinctrl-0 = <&qup_i2c7_default>; 1134 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 status = "disabled"; 1138 }; 1139 1140 spi7: spi@89c000 { 1141 compatible = "qcom,geni-spi"; 1142 reg = <0 0x89c000 0 0x4000>; 1143 reg-names = "se"; 1144 clock-names = "se"; 1145 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1146 pinctrl-names = "default"; 1147 pinctrl-0 = <&qup_spi7_default>; 1148 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1149 spi-max-frequency = <50000000>; 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 status = "disabled"; 1153 }; 1154 }; 1155 1156 gpi_dma1: dma-controller@a00000 { 1157 compatible = "qcom,sm8150-gpi-dma"; 1158 reg = <0 0xa00000 0 0x60000>; 1159 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1172 dma-channels = <13>; 1173 dma-channel-mask = <0xfa>; 1174 iommus = <&apps_smmu 0x0616 0x0>; 1175 #dma-cells = <3>; 1176 status = "disabled"; 1177 }; 1178 1179 qupv3_id_1: geniqup@ac0000 { 1180 compatible = "qcom,geni-se-qup"; 1181 reg = <0x0 0x00ac0000 0x0 0x6000>; 1182 clock-names = "m-ahb", "s-ahb"; 1183 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1184 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1185 iommus = <&apps_smmu 0x603 0x0>; 1186 #address-cells = <2>; 1187 #size-cells = <2>; 1188 ranges; 1189 status = "disabled"; 1190 1191 i2c8: i2c@a80000 { 1192 compatible = "qcom,geni-i2c"; 1193 reg = <0 0x00a80000 0 0x4000>; 1194 clock-names = "se"; 1195 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1196 pinctrl-names = "default"; 1197 pinctrl-0 = <&qup_i2c8_default>; 1198 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 status = "disabled"; 1202 }; 1203 1204 spi8: spi@a80000 { 1205 compatible = "qcom,geni-spi"; 1206 reg = <0 0xa80000 0 0x4000>; 1207 reg-names = "se"; 1208 clock-names = "se"; 1209 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1210 pinctrl-names = "default"; 1211 pinctrl-0 = <&qup_spi8_default>; 1212 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1213 spi-max-frequency = <50000000>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 status = "disabled"; 1217 }; 1218 1219 i2c9: i2c@a84000 { 1220 compatible = "qcom,geni-i2c"; 1221 reg = <0 0x00a84000 0 0x4000>; 1222 clock-names = "se"; 1223 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1224 pinctrl-names = "default"; 1225 pinctrl-0 = <&qup_i2c9_default>; 1226 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 status = "disabled"; 1230 }; 1231 1232 spi9: spi@a84000 { 1233 compatible = "qcom,geni-spi"; 1234 reg = <0 0xa84000 0 0x4000>; 1235 reg-names = "se"; 1236 clock-names = "se"; 1237 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1238 pinctrl-names = "default"; 1239 pinctrl-0 = <&qup_spi9_default>; 1240 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1241 spi-max-frequency = <50000000>; 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 status = "disabled"; 1245 }; 1246 1247 i2c10: i2c@a88000 { 1248 compatible = "qcom,geni-i2c"; 1249 reg = <0 0x00a88000 0 0x4000>; 1250 clock-names = "se"; 1251 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1252 pinctrl-names = "default"; 1253 pinctrl-0 = <&qup_i2c10_default>; 1254 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1255 #address-cells = <1>; 1256 #size-cells = <0>; 1257 status = "disabled"; 1258 }; 1259 1260 spi10: spi@a88000 { 1261 compatible = "qcom,geni-spi"; 1262 reg = <0 0xa88000 0 0x4000>; 1263 reg-names = "se"; 1264 clock-names = "se"; 1265 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&qup_spi10_default>; 1268 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1269 spi-max-frequency = <50000000>; 1270 #address-cells = <1>; 1271 #size-cells = <0>; 1272 status = "disabled"; 1273 }; 1274 1275 i2c11: i2c@a8c000 { 1276 compatible = "qcom,geni-i2c"; 1277 reg = <0 0x00a8c000 0 0x4000>; 1278 clock-names = "se"; 1279 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1280 pinctrl-names = "default"; 1281 pinctrl-0 = <&qup_i2c11_default>; 1282 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1283 #address-cells = <1>; 1284 #size-cells = <0>; 1285 status = "disabled"; 1286 }; 1287 1288 spi11: spi@a8c000 { 1289 compatible = "qcom,geni-spi"; 1290 reg = <0 0xa8c000 0 0x4000>; 1291 reg-names = "se"; 1292 clock-names = "se"; 1293 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1294 pinctrl-names = "default"; 1295 pinctrl-0 = <&qup_spi11_default>; 1296 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1297 spi-max-frequency = <50000000>; 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 status = "disabled"; 1301 }; 1302 1303 uart2: serial@a90000 { 1304 compatible = "qcom,geni-debug-uart"; 1305 reg = <0x0 0x00a90000 0x0 0x4000>; 1306 clock-names = "se"; 1307 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1308 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1309 status = "disabled"; 1310 }; 1311 1312 i2c12: i2c@a90000 { 1313 compatible = "qcom,geni-i2c"; 1314 reg = <0 0x00a90000 0 0x4000>; 1315 clock-names = "se"; 1316 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1317 pinctrl-names = "default"; 1318 pinctrl-0 = <&qup_i2c12_default>; 1319 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 status = "disabled"; 1323 }; 1324 1325 spi12: spi@a90000 { 1326 compatible = "qcom,geni-spi"; 1327 reg = <0 0xa90000 0 0x4000>; 1328 reg-names = "se"; 1329 clock-names = "se"; 1330 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1331 pinctrl-names = "default"; 1332 pinctrl-0 = <&qup_spi12_default>; 1333 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1334 spi-max-frequency = <50000000>; 1335 #address-cells = <1>; 1336 #size-cells = <0>; 1337 status = "disabled"; 1338 }; 1339 1340 i2c16: i2c@94000 { 1341 compatible = "qcom,geni-i2c"; 1342 reg = <0 0x0094000 0 0x4000>; 1343 clock-names = "se"; 1344 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1345 pinctrl-names = "default"; 1346 pinctrl-0 = <&qup_i2c16_default>; 1347 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 status = "disabled"; 1351 }; 1352 1353 spi16: spi@a94000 { 1354 compatible = "qcom,geni-spi"; 1355 reg = <0 0xa94000 0 0x4000>; 1356 reg-names = "se"; 1357 clock-names = "se"; 1358 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1359 pinctrl-names = "default"; 1360 pinctrl-0 = <&qup_spi16_default>; 1361 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1362 spi-max-frequency = <50000000>; 1363 #address-cells = <1>; 1364 #size-cells = <0>; 1365 status = "disabled"; 1366 }; 1367 }; 1368 1369 gpi_dma2: dma-controller@c00000 { 1370 compatible = "qcom,sm8150-gpi-dma"; 1371 reg = <0 0xc00000 0 0x60000>; 1372 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 1385 dma-channels = <13>; 1386 dma-channel-mask = <0xfa>; 1387 iommus = <&apps_smmu 0x07b6 0x0>; 1388 #dma-cells = <3>; 1389 status = "disabled"; 1390 }; 1391 1392 qupv3_id_2: geniqup@cc0000 { 1393 compatible = "qcom,geni-se-qup"; 1394 reg = <0x0 0x00cc0000 0x0 0x6000>; 1395 1396 clock-names = "m-ahb", "s-ahb"; 1397 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1398 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1399 iommus = <&apps_smmu 0x7a3 0x0>; 1400 #address-cells = <2>; 1401 #size-cells = <2>; 1402 ranges; 1403 status = "disabled"; 1404 1405 i2c17: i2c@c80000 { 1406 compatible = "qcom,geni-i2c"; 1407 reg = <0 0x00c80000 0 0x4000>; 1408 clock-names = "se"; 1409 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1410 pinctrl-names = "default"; 1411 pinctrl-0 = <&qup_i2c17_default>; 1412 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1413 #address-cells = <1>; 1414 #size-cells = <0>; 1415 status = "disabled"; 1416 }; 1417 1418 spi17: spi@c80000 { 1419 compatible = "qcom,geni-spi"; 1420 reg = <0 0xc80000 0 0x4000>; 1421 reg-names = "se"; 1422 clock-names = "se"; 1423 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1424 pinctrl-names = "default"; 1425 pinctrl-0 = <&qup_spi17_default>; 1426 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1427 spi-max-frequency = <50000000>; 1428 #address-cells = <1>; 1429 #size-cells = <0>; 1430 status = "disabled"; 1431 }; 1432 1433 i2c18: i2c@c84000 { 1434 compatible = "qcom,geni-i2c"; 1435 reg = <0 0x00c84000 0 0x4000>; 1436 clock-names = "se"; 1437 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1438 pinctrl-names = "default"; 1439 pinctrl-0 = <&qup_i2c18_default>; 1440 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 status = "disabled"; 1444 }; 1445 1446 spi18: spi@c84000 { 1447 compatible = "qcom,geni-spi"; 1448 reg = <0 0xc84000 0 0x4000>; 1449 reg-names = "se"; 1450 clock-names = "se"; 1451 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1452 pinctrl-names = "default"; 1453 pinctrl-0 = <&qup_spi18_default>; 1454 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1455 spi-max-frequency = <50000000>; 1456 #address-cells = <1>; 1457 #size-cells = <0>; 1458 status = "disabled"; 1459 }; 1460 1461 i2c19: i2c@c88000 { 1462 compatible = "qcom,geni-i2c"; 1463 reg = <0 0x00c88000 0 0x4000>; 1464 clock-names = "se"; 1465 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1466 pinctrl-names = "default"; 1467 pinctrl-0 = <&qup_i2c19_default>; 1468 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 status = "disabled"; 1472 }; 1473 1474 spi19: spi@c88000 { 1475 compatible = "qcom,geni-spi"; 1476 reg = <0 0xc88000 0 0x4000>; 1477 reg-names = "se"; 1478 clock-names = "se"; 1479 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1480 pinctrl-names = "default"; 1481 pinctrl-0 = <&qup_spi19_default>; 1482 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1483 spi-max-frequency = <50000000>; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 status = "disabled"; 1487 }; 1488 1489 i2c13: i2c@c8c000 { 1490 compatible = "qcom,geni-i2c"; 1491 reg = <0 0x00c8c000 0 0x4000>; 1492 clock-names = "se"; 1493 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1494 pinctrl-names = "default"; 1495 pinctrl-0 = <&qup_i2c13_default>; 1496 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1497 #address-cells = <1>; 1498 #size-cells = <0>; 1499 status = "disabled"; 1500 }; 1501 1502 spi13: spi@c8c000 { 1503 compatible = "qcom,geni-spi"; 1504 reg = <0 0xc8c000 0 0x4000>; 1505 reg-names = "se"; 1506 clock-names = "se"; 1507 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1508 pinctrl-names = "default"; 1509 pinctrl-0 = <&qup_spi13_default>; 1510 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1511 spi-max-frequency = <50000000>; 1512 #address-cells = <1>; 1513 #size-cells = <0>; 1514 status = "disabled"; 1515 }; 1516 1517 i2c14: i2c@c90000 { 1518 compatible = "qcom,geni-i2c"; 1519 reg = <0 0x00c90000 0 0x4000>; 1520 clock-names = "se"; 1521 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1522 pinctrl-names = "default"; 1523 pinctrl-0 = <&qup_i2c14_default>; 1524 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1525 #address-cells = <1>; 1526 #size-cells = <0>; 1527 status = "disabled"; 1528 }; 1529 1530 spi14: spi@c90000 { 1531 compatible = "qcom,geni-spi"; 1532 reg = <0 0xc90000 0 0x4000>; 1533 reg-names = "se"; 1534 clock-names = "se"; 1535 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1536 pinctrl-names = "default"; 1537 pinctrl-0 = <&qup_spi14_default>; 1538 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1539 spi-max-frequency = <50000000>; 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 status = "disabled"; 1543 }; 1544 1545 i2c15: i2c@c94000 { 1546 compatible = "qcom,geni-i2c"; 1547 reg = <0 0x00c94000 0 0x4000>; 1548 clock-names = "se"; 1549 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1550 pinctrl-names = "default"; 1551 pinctrl-0 = <&qup_i2c15_default>; 1552 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1553 #address-cells = <1>; 1554 #size-cells = <0>; 1555 status = "disabled"; 1556 }; 1557 1558 spi15: spi@c94000 { 1559 compatible = "qcom,geni-spi"; 1560 reg = <0 0xc94000 0 0x4000>; 1561 reg-names = "se"; 1562 clock-names = "se"; 1563 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1564 pinctrl-names = "default"; 1565 pinctrl-0 = <&qup_spi15_default>; 1566 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1567 spi-max-frequency = <50000000>; 1568 #address-cells = <1>; 1569 #size-cells = <0>; 1570 status = "disabled"; 1571 }; 1572 }; 1573 1574 config_noc: interconnect@1500000 { 1575 compatible = "qcom,sm8150-config-noc"; 1576 reg = <0 0x01500000 0 0x7400>; 1577 #interconnect-cells = <1>; 1578 qcom,bcm-voters = <&apps_bcm_voter>; 1579 }; 1580 1581 system_noc: interconnect@1620000 { 1582 compatible = "qcom,sm8150-system-noc"; 1583 reg = <0 0x01620000 0 0x19400>; 1584 #interconnect-cells = <1>; 1585 qcom,bcm-voters = <&apps_bcm_voter>; 1586 }; 1587 1588 mc_virt: interconnect@163a000 { 1589 compatible = "qcom,sm8150-mc-virt"; 1590 reg = <0 0x0163a000 0 0x1000>; 1591 #interconnect-cells = <1>; 1592 qcom,bcm-voters = <&apps_bcm_voter>; 1593 }; 1594 1595 aggre1_noc: interconnect@16e0000 { 1596 compatible = "qcom,sm8150-aggre1-noc"; 1597 reg = <0 0x016e0000 0 0xd080>; 1598 #interconnect-cells = <1>; 1599 qcom,bcm-voters = <&apps_bcm_voter>; 1600 }; 1601 1602 aggre2_noc: interconnect@1700000 { 1603 compatible = "qcom,sm8150-aggre2-noc"; 1604 reg = <0 0x01700000 0 0x20000>; 1605 #interconnect-cells = <1>; 1606 qcom,bcm-voters = <&apps_bcm_voter>; 1607 }; 1608 1609 compute_noc: interconnect@1720000 { 1610 compatible = "qcom,sm8150-compute-noc"; 1611 reg = <0 0x01720000 0 0x7000>; 1612 #interconnect-cells = <1>; 1613 qcom,bcm-voters = <&apps_bcm_voter>; 1614 }; 1615 1616 mmss_noc: interconnect@1740000 { 1617 compatible = "qcom,sm8150-mmss-noc"; 1618 reg = <0 0x01740000 0 0x1c100>; 1619 #interconnect-cells = <1>; 1620 qcom,bcm-voters = <&apps_bcm_voter>; 1621 }; 1622 1623 system-cache-controller@9200000 { 1624 compatible = "qcom,sm8150-llcc"; 1625 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 1626 reg-names = "llcc_base", "llcc_broadcast_base"; 1627 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1628 }; 1629 1630 ufs_mem_hc: ufshc@1d84000 { 1631 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 1632 "jedec,ufs-2.0"; 1633 reg = <0 0x01d84000 0 0x2500>, 1634 <0 0x01d90000 0 0x8000>; 1635 reg-names = "std", "ice"; 1636 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1637 phys = <&ufs_mem_phy_lanes>; 1638 phy-names = "ufsphy"; 1639 lanes-per-direction = <2>; 1640 #reset-cells = <1>; 1641 resets = <&gcc GCC_UFS_PHY_BCR>; 1642 reset-names = "rst"; 1643 1644 iommus = <&apps_smmu 0x300 0>; 1645 1646 clock-names = 1647 "core_clk", 1648 "bus_aggr_clk", 1649 "iface_clk", 1650 "core_clk_unipro", 1651 "ref_clk", 1652 "tx_lane0_sync_clk", 1653 "rx_lane0_sync_clk", 1654 "rx_lane1_sync_clk", 1655 "ice_core_clk"; 1656 clocks = 1657 <&gcc GCC_UFS_PHY_AXI_CLK>, 1658 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1659 <&gcc GCC_UFS_PHY_AHB_CLK>, 1660 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1661 <&rpmhcc RPMH_CXO_CLK>, 1662 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1663 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1664 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 1665 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1666 freq-table-hz = 1667 <37500000 300000000>, 1668 <0 0>, 1669 <0 0>, 1670 <37500000 300000000>, 1671 <0 0>, 1672 <0 0>, 1673 <0 0>, 1674 <0 0>, 1675 <0 300000000>; 1676 1677 status = "disabled"; 1678 }; 1679 1680 ufs_mem_phy: phy@1d87000 { 1681 compatible = "qcom,sm8150-qmp-ufs-phy"; 1682 reg = <0 0x01d87000 0 0x1c0>; 1683 #address-cells = <2>; 1684 #size-cells = <2>; 1685 ranges; 1686 clock-names = "ref", 1687 "ref_aux"; 1688 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 1689 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1690 1691 resets = <&ufs_mem_hc 0>; 1692 reset-names = "ufsphy"; 1693 status = "disabled"; 1694 1695 ufs_mem_phy_lanes: lanes@1d87400 { 1696 reg = <0 0x01d87400 0 0x108>, 1697 <0 0x01d87600 0 0x1e0>, 1698 <0 0x01d87c00 0 0x1dc>, 1699 <0 0x01d87800 0 0x108>, 1700 <0 0x01d87a00 0 0x1e0>; 1701 #phy-cells = <0>; 1702 }; 1703 }; 1704 1705 ipa_virt: interconnect@1e00000 { 1706 compatible = "qcom,sm8150-ipa-virt"; 1707 reg = <0 0x01e00000 0 0x1000>; 1708 #interconnect-cells = <1>; 1709 qcom,bcm-voters = <&apps_bcm_voter>; 1710 }; 1711 1712 tcsr_mutex_regs: syscon@1f40000 { 1713 compatible = "syscon"; 1714 reg = <0x0 0x01f40000 0x0 0x40000>; 1715 }; 1716 1717 remoteproc_slpi: remoteproc@2400000 { 1718 compatible = "qcom,sm8150-slpi-pas"; 1719 reg = <0x0 0x02400000 0x0 0x4040>; 1720 1721 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 1722 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1723 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1724 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1725 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1726 interrupt-names = "wdog", "fatal", "ready", 1727 "handover", "stop-ack"; 1728 1729 clocks = <&rpmhcc RPMH_CXO_CLK>; 1730 clock-names = "xo"; 1731 1732 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, 1733 <&rpmhpd 3>, 1734 <&rpmhpd 2>; 1735 power-domain-names = "load_state", "lcx", "lmx"; 1736 1737 memory-region = <&slpi_mem>; 1738 1739 qcom,smem-states = <&slpi_smp2p_out 0>; 1740 qcom,smem-state-names = "stop"; 1741 1742 status = "disabled"; 1743 1744 glink-edge { 1745 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 1746 label = "dsps"; 1747 qcom,remote-pid = <3>; 1748 mboxes = <&apss_shared 24>; 1749 }; 1750 }; 1751 1752 gpu: gpu@2c00000 { 1753 /* 1754 * note: the amd,imageon compatible makes it possible 1755 * to use the drm/msm driver without the display node, 1756 * make sure to remove it when display node is added 1757 */ 1758 compatible = "qcom,adreno-640.1", 1759 "qcom,adreno", 1760 "amd,imageon"; 1761 #stream-id-cells = <16>; 1762 1763 reg = <0 0x02c00000 0 0x40000>; 1764 reg-names = "kgsl_3d0_reg_memory"; 1765 1766 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1767 1768 iommus = <&adreno_smmu 0 0x401>; 1769 1770 operating-points-v2 = <&gpu_opp_table>; 1771 1772 qcom,gmu = <&gmu>; 1773 1774 status = "disabled"; 1775 1776 zap-shader { 1777 memory-region = <&gpu_mem>; 1778 }; 1779 1780 /* note: downstream checks gpu binning for 675 Mhz */ 1781 gpu_opp_table: opp-table { 1782 compatible = "operating-points-v2"; 1783 1784 opp-675000000 { 1785 opp-hz = /bits/ 64 <675000000>; 1786 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1787 }; 1788 1789 opp-585000000 { 1790 opp-hz = /bits/ 64 <585000000>; 1791 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1792 }; 1793 1794 opp-499200000 { 1795 opp-hz = /bits/ 64 <499200000>; 1796 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1797 }; 1798 1799 opp-427000000 { 1800 opp-hz = /bits/ 64 <427000000>; 1801 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1802 }; 1803 1804 opp-345000000 { 1805 opp-hz = /bits/ 64 <345000000>; 1806 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1807 }; 1808 1809 opp-257000000 { 1810 opp-hz = /bits/ 64 <257000000>; 1811 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1812 }; 1813 }; 1814 }; 1815 1816 gmu: gmu@2c6a000 { 1817 compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 1818 1819 reg = <0 0x02c6a000 0 0x30000>, 1820 <0 0x0b290000 0 0x10000>, 1821 <0 0x0b490000 0 0x10000>; 1822 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 1823 1824 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1826 interrupt-names = "hfi", "gmu"; 1827 1828 clocks = <&gpucc GPU_CC_AHB_CLK>, 1829 <&gpucc GPU_CC_CX_GMU_CLK>, 1830 <&gpucc GPU_CC_CXO_CLK>, 1831 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1832 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1833 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 1834 1835 power-domains = <&gpucc GPU_CX_GDSC>, 1836 <&gpucc GPU_GX_GDSC>; 1837 power-domain-names = "cx", "gx"; 1838 1839 iommus = <&adreno_smmu 5 0x400>; 1840 1841 operating-points-v2 = <&gmu_opp_table>; 1842 1843 status = "disabled"; 1844 1845 gmu_opp_table: opp-table { 1846 compatible = "operating-points-v2"; 1847 1848 opp-200000000 { 1849 opp-hz = /bits/ 64 <200000000>; 1850 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1851 }; 1852 }; 1853 }; 1854 1855 gpucc: clock-controller@2c90000 { 1856 compatible = "qcom,sm8150-gpucc"; 1857 reg = <0 0x02c90000 0 0x9000>; 1858 clocks = <&rpmhcc RPMH_CXO_CLK>, 1859 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1860 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1861 clock-names = "bi_tcxo", 1862 "gcc_gpu_gpll0_clk_src", 1863 "gcc_gpu_gpll0_div_clk_src"; 1864 #clock-cells = <1>; 1865 #reset-cells = <1>; 1866 #power-domain-cells = <1>; 1867 }; 1868 1869 adreno_smmu: iommu@2ca0000 { 1870 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 1871 reg = <0 0x02ca0000 0 0x10000>; 1872 #iommu-cells = <2>; 1873 #global-interrupts = <1>; 1874 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 1883 clocks = <&gpucc GPU_CC_AHB_CLK>, 1884 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1885 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1886 clock-names = "ahb", "bus", "iface"; 1887 1888 power-domains = <&gpucc GPU_CX_GDSC>; 1889 }; 1890 1891 tlmm: pinctrl@3100000 { 1892 compatible = "qcom,sm8150-pinctrl"; 1893 reg = <0x0 0x03100000 0x0 0x300000>, 1894 <0x0 0x03500000 0x0 0x300000>, 1895 <0x0 0x03900000 0x0 0x300000>, 1896 <0x0 0x03D00000 0x0 0x300000>; 1897 reg-names = "west", "east", "north", "south"; 1898 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1899 gpio-ranges = <&tlmm 0 0 176>; 1900 gpio-controller; 1901 #gpio-cells = <2>; 1902 interrupt-controller; 1903 #interrupt-cells = <2>; 1904 1905 qup_i2c0_default: qup-i2c0-default { 1906 mux { 1907 pins = "gpio0", "gpio1"; 1908 function = "qup0"; 1909 }; 1910 1911 config { 1912 pins = "gpio0", "gpio1"; 1913 drive-strength = <0x02>; 1914 bias-disable; 1915 }; 1916 }; 1917 1918 qup_spi0_default: qup-spi0-default { 1919 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1920 function = "qup0"; 1921 drive-strength = <6>; 1922 bias-disable; 1923 }; 1924 1925 qup_i2c1_default: qup-i2c1-default { 1926 mux { 1927 pins = "gpio114", "gpio115"; 1928 function = "qup1"; 1929 }; 1930 1931 config { 1932 pins = "gpio114", "gpio115"; 1933 drive-strength = <0x02>; 1934 bias-disable; 1935 }; 1936 }; 1937 1938 qup_spi1_default: qup-spi1-default { 1939 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 1940 function = "qup1"; 1941 drive-strength = <6>; 1942 bias-disable; 1943 }; 1944 1945 qup_i2c2_default: qup-i2c2-default { 1946 mux { 1947 pins = "gpio126", "gpio127"; 1948 function = "qup2"; 1949 }; 1950 1951 config { 1952 pins = "gpio126", "gpio127"; 1953 drive-strength = <0x02>; 1954 bias-disable; 1955 }; 1956 }; 1957 1958 qup_spi2_default: qup-spi2-default { 1959 pins = "gpio126", "gpio127", "gpio128", "gpio129"; 1960 function = "qup2"; 1961 drive-strength = <6>; 1962 bias-disable; 1963 }; 1964 1965 qup_i2c3_default: qup-i2c3-default { 1966 mux { 1967 pins = "gpio144", "gpio145"; 1968 function = "qup3"; 1969 }; 1970 1971 config { 1972 pins = "gpio144", "gpio145"; 1973 drive-strength = <0x02>; 1974 bias-disable; 1975 }; 1976 }; 1977 1978 qup_spi3_default: qup-spi3-default { 1979 pins = "gpio144", "gpio145", "gpio146", "gpio147"; 1980 function = "qup3"; 1981 drive-strength = <6>; 1982 bias-disable; 1983 }; 1984 1985 qup_i2c4_default: qup-i2c4-default { 1986 mux { 1987 pins = "gpio51", "gpio52"; 1988 function = "qup4"; 1989 }; 1990 1991 config { 1992 pins = "gpio51", "gpio52"; 1993 drive-strength = <0x02>; 1994 bias-disable; 1995 }; 1996 }; 1997 1998 qup_spi4_default: qup-spi4-default { 1999 pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2000 function = "qup4"; 2001 drive-strength = <6>; 2002 bias-disable; 2003 }; 2004 2005 qup_i2c5_default: qup-i2c5-default { 2006 mux { 2007 pins = "gpio121", "gpio122"; 2008 function = "qup5"; 2009 }; 2010 2011 config { 2012 pins = "gpio121", "gpio122"; 2013 drive-strength = <0x02>; 2014 bias-disable; 2015 }; 2016 }; 2017 2018 qup_spi5_default: qup-spi5-default { 2019 pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2020 function = "qup5"; 2021 drive-strength = <6>; 2022 bias-disable; 2023 }; 2024 2025 qup_i2c6_default: qup-i2c6-default { 2026 mux { 2027 pins = "gpio6", "gpio7"; 2028 function = "qup6"; 2029 }; 2030 2031 config { 2032 pins = "gpio6", "gpio7"; 2033 drive-strength = <0x02>; 2034 bias-disable; 2035 }; 2036 }; 2037 2038 qup_spi6_default: qup-spi6_default { 2039 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2040 function = "qup6"; 2041 drive-strength = <6>; 2042 bias-disable; 2043 }; 2044 2045 qup_i2c7_default: qup-i2c7-default { 2046 mux { 2047 pins = "gpio98", "gpio99"; 2048 function = "qup7"; 2049 }; 2050 2051 config { 2052 pins = "gpio98", "gpio99"; 2053 drive-strength = <0x02>; 2054 bias-disable; 2055 }; 2056 }; 2057 2058 qup_spi7_default: qup-spi7_default { 2059 pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2060 function = "qup7"; 2061 drive-strength = <6>; 2062 bias-disable; 2063 }; 2064 2065 qup_i2c8_default: qup-i2c8-default { 2066 mux { 2067 pins = "gpio88", "gpio89"; 2068 function = "qup8"; 2069 }; 2070 2071 config { 2072 pins = "gpio88", "gpio89"; 2073 drive-strength = <0x02>; 2074 bias-disable; 2075 }; 2076 }; 2077 2078 qup_spi8_default: qup-spi8-default { 2079 pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2080 function = "qup8"; 2081 drive-strength = <6>; 2082 bias-disable; 2083 }; 2084 2085 qup_i2c9_default: qup-i2c9-default { 2086 mux { 2087 pins = "gpio39", "gpio40"; 2088 function = "qup9"; 2089 }; 2090 2091 config { 2092 pins = "gpio39", "gpio40"; 2093 drive-strength = <0x02>; 2094 bias-disable; 2095 }; 2096 }; 2097 2098 qup_spi9_default: qup-spi9-default { 2099 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2100 function = "qup9"; 2101 drive-strength = <6>; 2102 bias-disable; 2103 }; 2104 2105 qup_i2c10_default: qup-i2c10-default { 2106 mux { 2107 pins = "gpio9", "gpio10"; 2108 function = "qup10"; 2109 }; 2110 2111 config { 2112 pins = "gpio9", "gpio10"; 2113 drive-strength = <0x02>; 2114 bias-disable; 2115 }; 2116 }; 2117 2118 qup_spi10_default: qup-spi10-default { 2119 pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2120 function = "qup10"; 2121 drive-strength = <6>; 2122 bias-disable; 2123 }; 2124 2125 qup_i2c11_default: qup-i2c11-default { 2126 mux { 2127 pins = "gpio94", "gpio95"; 2128 function = "qup11"; 2129 }; 2130 2131 config { 2132 pins = "gpio94", "gpio95"; 2133 drive-strength = <0x02>; 2134 bias-disable; 2135 }; 2136 }; 2137 2138 qup_spi11_default: qup-spi11-default { 2139 pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2140 function = "qup11"; 2141 drive-strength = <6>; 2142 bias-disable; 2143 }; 2144 2145 qup_i2c12_default: qup-i2c12-default { 2146 mux { 2147 pins = "gpio83", "gpio84"; 2148 function = "qup12"; 2149 }; 2150 2151 config { 2152 pins = "gpio83", "gpio84"; 2153 drive-strength = <0x02>; 2154 bias-disable; 2155 }; 2156 }; 2157 2158 qup_spi12_default: qup-spi12-default { 2159 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2160 function = "qup12"; 2161 drive-strength = <6>; 2162 bias-disable; 2163 }; 2164 2165 qup_i2c13_default: qup-i2c13-default { 2166 mux { 2167 pins = "gpio43", "gpio44"; 2168 function = "qup13"; 2169 }; 2170 2171 config { 2172 pins = "gpio43", "gpio44"; 2173 drive-strength = <0x02>; 2174 bias-disable; 2175 }; 2176 }; 2177 2178 qup_spi13_default: qup-spi13-default { 2179 pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2180 function = "qup13"; 2181 drive-strength = <6>; 2182 bias-disable; 2183 }; 2184 2185 qup_i2c14_default: qup-i2c14-default { 2186 mux { 2187 pins = "gpio47", "gpio48"; 2188 function = "qup14"; 2189 }; 2190 2191 config { 2192 pins = "gpio47", "gpio48"; 2193 drive-strength = <0x02>; 2194 bias-disable; 2195 }; 2196 }; 2197 2198 qup_spi14_default: qup-spi14-default { 2199 pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2200 function = "qup14"; 2201 drive-strength = <6>; 2202 bias-disable; 2203 }; 2204 2205 qup_i2c15_default: qup-i2c15-default { 2206 mux { 2207 pins = "gpio27", "gpio28"; 2208 function = "qup15"; 2209 }; 2210 2211 config { 2212 pins = "gpio27", "gpio28"; 2213 drive-strength = <0x02>; 2214 bias-disable; 2215 }; 2216 }; 2217 2218 qup_spi15_default: qup-spi15-default { 2219 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2220 function = "qup15"; 2221 drive-strength = <6>; 2222 bias-disable; 2223 }; 2224 2225 qup_i2c16_default: qup-i2c16-default { 2226 mux { 2227 pins = "gpio86", "gpio85"; 2228 function = "qup16"; 2229 }; 2230 2231 config { 2232 pins = "gpio86", "gpio85"; 2233 drive-strength = <0x02>; 2234 bias-disable; 2235 }; 2236 }; 2237 2238 qup_spi16_default: qup-spi16-default { 2239 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2240 function = "qup16"; 2241 drive-strength = <6>; 2242 bias-disable; 2243 }; 2244 2245 qup_i2c17_default: qup-i2c17-default { 2246 mux { 2247 pins = "gpio55", "gpio56"; 2248 function = "qup17"; 2249 }; 2250 2251 config { 2252 pins = "gpio55", "gpio56"; 2253 drive-strength = <0x02>; 2254 bias-disable; 2255 }; 2256 }; 2257 2258 qup_spi17_default: qup-spi17-default { 2259 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2260 function = "qup17"; 2261 drive-strength = <6>; 2262 bias-disable; 2263 }; 2264 2265 qup_i2c18_default: qup-i2c18-default { 2266 mux { 2267 pins = "gpio23", "gpio24"; 2268 function = "qup18"; 2269 }; 2270 2271 config { 2272 pins = "gpio23", "gpio24"; 2273 drive-strength = <0x02>; 2274 bias-disable; 2275 }; 2276 }; 2277 2278 qup_spi18_default: qup-spi18-default { 2279 pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2280 function = "qup18"; 2281 drive-strength = <6>; 2282 bias-disable; 2283 }; 2284 2285 qup_i2c19_default: qup-i2c19-default { 2286 mux { 2287 pins = "gpio57", "gpio58"; 2288 function = "qup19"; 2289 }; 2290 2291 config { 2292 pins = "gpio57", "gpio58"; 2293 drive-strength = <0x02>; 2294 bias-disable; 2295 }; 2296 }; 2297 2298 qup_spi19_default: qup-spi19-default { 2299 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2300 function = "qup19"; 2301 drive-strength = <6>; 2302 bias-disable; 2303 }; 2304 }; 2305 2306 remoteproc_mpss: remoteproc@4080000 { 2307 compatible = "qcom,sm8150-mpss-pas"; 2308 reg = <0x0 0x04080000 0x0 0x4040>; 2309 2310 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2311 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2312 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2313 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2314 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2315 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2316 interrupt-names = "wdog", "fatal", "ready", "handover", 2317 "stop-ack", "shutdown-ack"; 2318 2319 clocks = <&rpmhcc RPMH_CXO_CLK>; 2320 clock-names = "xo"; 2321 2322 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, 2323 <&rpmhpd 7>, 2324 <&rpmhpd 0>; 2325 power-domain-names = "load_state", "cx", "mss"; 2326 2327 memory-region = <&mpss_mem>; 2328 2329 qcom,smem-states = <&modem_smp2p_out 0>; 2330 qcom,smem-state-names = "stop"; 2331 2332 status = "disabled"; 2333 2334 glink-edge { 2335 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2336 label = "modem"; 2337 qcom,remote-pid = <1>; 2338 mboxes = <&apss_shared 12>; 2339 }; 2340 }; 2341 2342 stm@6002000 { 2343 compatible = "arm,coresight-stm", "arm,primecell"; 2344 reg = <0 0x06002000 0 0x1000>, 2345 <0 0x16280000 0 0x180000>; 2346 reg-names = "stm-base", "stm-stimulus-base"; 2347 2348 clocks = <&aoss_qmp>; 2349 clock-names = "apb_pclk"; 2350 2351 out-ports { 2352 port { 2353 stm_out: endpoint { 2354 remote-endpoint = <&funnel0_in7>; 2355 }; 2356 }; 2357 }; 2358 }; 2359 2360 funnel@6041000 { 2361 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2362 reg = <0 0x06041000 0 0x1000>; 2363 2364 clocks = <&aoss_qmp>; 2365 clock-names = "apb_pclk"; 2366 2367 out-ports { 2368 port { 2369 funnel0_out: endpoint { 2370 remote-endpoint = <&merge_funnel_in0>; 2371 }; 2372 }; 2373 }; 2374 2375 in-ports { 2376 #address-cells = <1>; 2377 #size-cells = <0>; 2378 2379 port@7 { 2380 reg = <7>; 2381 funnel0_in7: endpoint { 2382 remote-endpoint = <&stm_out>; 2383 }; 2384 }; 2385 }; 2386 }; 2387 2388 funnel@6042000 { 2389 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2390 reg = <0 0x06042000 0 0x1000>; 2391 2392 clocks = <&aoss_qmp>; 2393 clock-names = "apb_pclk"; 2394 2395 out-ports { 2396 port { 2397 funnel1_out: endpoint { 2398 remote-endpoint = <&merge_funnel_in1>; 2399 }; 2400 }; 2401 }; 2402 2403 in-ports { 2404 #address-cells = <1>; 2405 #size-cells = <0>; 2406 2407 port@4 { 2408 reg = <4>; 2409 funnel1_in4: endpoint { 2410 remote-endpoint = <&swao_replicator_out>; 2411 }; 2412 }; 2413 }; 2414 }; 2415 2416 funnel@6043000 { 2417 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2418 reg = <0 0x06043000 0 0x1000>; 2419 2420 clocks = <&aoss_qmp>; 2421 clock-names = "apb_pclk"; 2422 2423 out-ports { 2424 port { 2425 funnel2_out: endpoint { 2426 remote-endpoint = <&merge_funnel_in2>; 2427 }; 2428 }; 2429 }; 2430 2431 in-ports { 2432 #address-cells = <1>; 2433 #size-cells = <0>; 2434 2435 port@2 { 2436 reg = <2>; 2437 funnel2_in2: endpoint { 2438 remote-endpoint = <&apss_merge_funnel_out>; 2439 }; 2440 }; 2441 }; 2442 }; 2443 2444 funnel@6045000 { 2445 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2446 reg = <0 0x06045000 0 0x1000>; 2447 2448 clocks = <&aoss_qmp>; 2449 clock-names = "apb_pclk"; 2450 2451 out-ports { 2452 port { 2453 merge_funnel_out: endpoint { 2454 remote-endpoint = <&etf_in>; 2455 }; 2456 }; 2457 }; 2458 2459 in-ports { 2460 #address-cells = <1>; 2461 #size-cells = <0>; 2462 2463 port@0 { 2464 reg = <0>; 2465 merge_funnel_in0: endpoint { 2466 remote-endpoint = <&funnel0_out>; 2467 }; 2468 }; 2469 2470 port@1 { 2471 reg = <1>; 2472 merge_funnel_in1: endpoint { 2473 remote-endpoint = <&funnel1_out>; 2474 }; 2475 }; 2476 2477 port@2 { 2478 reg = <2>; 2479 merge_funnel_in2: endpoint { 2480 remote-endpoint = <&funnel2_out>; 2481 }; 2482 }; 2483 }; 2484 }; 2485 2486 replicator@6046000 { 2487 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2488 reg = <0 0x06046000 0 0x1000>; 2489 2490 clocks = <&aoss_qmp>; 2491 clock-names = "apb_pclk"; 2492 2493 out-ports { 2494 #address-cells = <1>; 2495 #size-cells = <0>; 2496 2497 port@0 { 2498 reg = <0>; 2499 replicator_out0: endpoint { 2500 remote-endpoint = <&etr_in>; 2501 }; 2502 }; 2503 2504 port@1 { 2505 reg = <1>; 2506 replicator_out1: endpoint { 2507 remote-endpoint = <&replicator1_in>; 2508 }; 2509 }; 2510 }; 2511 2512 in-ports { 2513 port { 2514 replicator_in0: endpoint { 2515 remote-endpoint = <&etf_out>; 2516 }; 2517 }; 2518 }; 2519 }; 2520 2521 etf@6047000 { 2522 compatible = "arm,coresight-tmc", "arm,primecell"; 2523 reg = <0 0x06047000 0 0x1000>; 2524 2525 clocks = <&aoss_qmp>; 2526 clock-names = "apb_pclk"; 2527 2528 out-ports { 2529 port { 2530 etf_out: endpoint { 2531 remote-endpoint = <&replicator_in0>; 2532 }; 2533 }; 2534 }; 2535 2536 in-ports { 2537 port { 2538 etf_in: endpoint { 2539 remote-endpoint = <&merge_funnel_out>; 2540 }; 2541 }; 2542 }; 2543 }; 2544 2545 etr@6048000 { 2546 compatible = "arm,coresight-tmc", "arm,primecell"; 2547 reg = <0 0x06048000 0 0x1000>; 2548 iommus = <&apps_smmu 0x05e0 0x0>; 2549 2550 clocks = <&aoss_qmp>; 2551 clock-names = "apb_pclk"; 2552 arm,scatter-gather; 2553 2554 in-ports { 2555 port { 2556 etr_in: endpoint { 2557 remote-endpoint = <&replicator_out0>; 2558 }; 2559 }; 2560 }; 2561 }; 2562 2563 replicator@604a000 { 2564 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2565 reg = <0 0x0604a000 0 0x1000>; 2566 2567 clocks = <&aoss_qmp>; 2568 clock-names = "apb_pclk"; 2569 2570 out-ports { 2571 #address-cells = <1>; 2572 #size-cells = <0>; 2573 2574 port@1 { 2575 reg = <1>; 2576 replicator1_out: endpoint { 2577 remote-endpoint = <&swao_funnel_in>; 2578 }; 2579 }; 2580 }; 2581 2582 in-ports { 2583 #address-cells = <1>; 2584 #size-cells = <0>; 2585 2586 port@1 { 2587 reg = <1>; 2588 replicator1_in: endpoint { 2589 remote-endpoint = <&replicator_out1>; 2590 }; 2591 }; 2592 }; 2593 }; 2594 2595 funnel@6b08000 { 2596 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2597 reg = <0 0x06b08000 0 0x1000>; 2598 2599 clocks = <&aoss_qmp>; 2600 clock-names = "apb_pclk"; 2601 2602 out-ports { 2603 port { 2604 swao_funnel_out: endpoint { 2605 remote-endpoint = <&swao_etf_in>; 2606 }; 2607 }; 2608 }; 2609 2610 in-ports { 2611 #address-cells = <1>; 2612 #size-cells = <0>; 2613 2614 port@6 { 2615 reg = <6>; 2616 swao_funnel_in: endpoint { 2617 remote-endpoint = <&replicator1_out>; 2618 }; 2619 }; 2620 }; 2621 }; 2622 2623 etf@6b09000 { 2624 compatible = "arm,coresight-tmc", "arm,primecell"; 2625 reg = <0 0x06b09000 0 0x1000>; 2626 2627 clocks = <&aoss_qmp>; 2628 clock-names = "apb_pclk"; 2629 2630 out-ports { 2631 port { 2632 swao_etf_out: endpoint { 2633 remote-endpoint = <&swao_replicator_in>; 2634 }; 2635 }; 2636 }; 2637 2638 in-ports { 2639 port { 2640 swao_etf_in: endpoint { 2641 remote-endpoint = <&swao_funnel_out>; 2642 }; 2643 }; 2644 }; 2645 }; 2646 2647 replicator@6b0a000 { 2648 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2649 reg = <0 0x06b0a000 0 0x1000>; 2650 2651 clocks = <&aoss_qmp>; 2652 clock-names = "apb_pclk"; 2653 qcom,replicator-loses-context; 2654 2655 out-ports { 2656 port { 2657 swao_replicator_out: endpoint { 2658 remote-endpoint = <&funnel1_in4>; 2659 }; 2660 }; 2661 }; 2662 2663 in-ports { 2664 port { 2665 swao_replicator_in: endpoint { 2666 remote-endpoint = <&swao_etf_out>; 2667 }; 2668 }; 2669 }; 2670 }; 2671 2672 etm@7040000 { 2673 compatible = "arm,coresight-etm4x", "arm,primecell"; 2674 reg = <0 0x07040000 0 0x1000>; 2675 2676 cpu = <&CPU0>; 2677 2678 clocks = <&aoss_qmp>; 2679 clock-names = "apb_pclk"; 2680 arm,coresight-loses-context-with-cpu; 2681 qcom,skip-power-up; 2682 2683 out-ports { 2684 port { 2685 etm0_out: endpoint { 2686 remote-endpoint = <&apss_funnel_in0>; 2687 }; 2688 }; 2689 }; 2690 }; 2691 2692 etm@7140000 { 2693 compatible = "arm,coresight-etm4x", "arm,primecell"; 2694 reg = <0 0x07140000 0 0x1000>; 2695 2696 cpu = <&CPU1>; 2697 2698 clocks = <&aoss_qmp>; 2699 clock-names = "apb_pclk"; 2700 arm,coresight-loses-context-with-cpu; 2701 qcom,skip-power-up; 2702 2703 out-ports { 2704 port { 2705 etm1_out: endpoint { 2706 remote-endpoint = <&apss_funnel_in1>; 2707 }; 2708 }; 2709 }; 2710 }; 2711 2712 etm@7240000 { 2713 compatible = "arm,coresight-etm4x", "arm,primecell"; 2714 reg = <0 0x07240000 0 0x1000>; 2715 2716 cpu = <&CPU2>; 2717 2718 clocks = <&aoss_qmp>; 2719 clock-names = "apb_pclk"; 2720 arm,coresight-loses-context-with-cpu; 2721 qcom,skip-power-up; 2722 2723 out-ports { 2724 port { 2725 etm2_out: endpoint { 2726 remote-endpoint = <&apss_funnel_in2>; 2727 }; 2728 }; 2729 }; 2730 }; 2731 2732 etm@7340000 { 2733 compatible = "arm,coresight-etm4x", "arm,primecell"; 2734 reg = <0 0x07340000 0 0x1000>; 2735 2736 cpu = <&CPU3>; 2737 2738 clocks = <&aoss_qmp>; 2739 clock-names = "apb_pclk"; 2740 arm,coresight-loses-context-with-cpu; 2741 qcom,skip-power-up; 2742 2743 out-ports { 2744 port { 2745 etm3_out: endpoint { 2746 remote-endpoint = <&apss_funnel_in3>; 2747 }; 2748 }; 2749 }; 2750 }; 2751 2752 etm@7440000 { 2753 compatible = "arm,coresight-etm4x", "arm,primecell"; 2754 reg = <0 0x07440000 0 0x1000>; 2755 2756 cpu = <&CPU4>; 2757 2758 clocks = <&aoss_qmp>; 2759 clock-names = "apb_pclk"; 2760 arm,coresight-loses-context-with-cpu; 2761 qcom,skip-power-up; 2762 2763 out-ports { 2764 port { 2765 etm4_out: endpoint { 2766 remote-endpoint = <&apss_funnel_in4>; 2767 }; 2768 }; 2769 }; 2770 }; 2771 2772 etm@7540000 { 2773 compatible = "arm,coresight-etm4x", "arm,primecell"; 2774 reg = <0 0x07540000 0 0x1000>; 2775 2776 cpu = <&CPU5>; 2777 2778 clocks = <&aoss_qmp>; 2779 clock-names = "apb_pclk"; 2780 arm,coresight-loses-context-with-cpu; 2781 qcom,skip-power-up; 2782 2783 out-ports { 2784 port { 2785 etm5_out: endpoint { 2786 remote-endpoint = <&apss_funnel_in5>; 2787 }; 2788 }; 2789 }; 2790 }; 2791 2792 etm@7640000 { 2793 compatible = "arm,coresight-etm4x", "arm,primecell"; 2794 reg = <0 0x07640000 0 0x1000>; 2795 2796 cpu = <&CPU6>; 2797 2798 clocks = <&aoss_qmp>; 2799 clock-names = "apb_pclk"; 2800 arm,coresight-loses-context-with-cpu; 2801 qcom,skip-power-up; 2802 2803 out-ports { 2804 port { 2805 etm6_out: endpoint { 2806 remote-endpoint = <&apss_funnel_in6>; 2807 }; 2808 }; 2809 }; 2810 }; 2811 2812 etm@7740000 { 2813 compatible = "arm,coresight-etm4x", "arm,primecell"; 2814 reg = <0 0x07740000 0 0x1000>; 2815 2816 cpu = <&CPU7>; 2817 2818 clocks = <&aoss_qmp>; 2819 clock-names = "apb_pclk"; 2820 arm,coresight-loses-context-with-cpu; 2821 qcom,skip-power-up; 2822 2823 out-ports { 2824 port { 2825 etm7_out: endpoint { 2826 remote-endpoint = <&apss_funnel_in7>; 2827 }; 2828 }; 2829 }; 2830 }; 2831 2832 funnel@7800000 { /* APSS Funnel */ 2833 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2834 reg = <0 0x07800000 0 0x1000>; 2835 2836 clocks = <&aoss_qmp>; 2837 clock-names = "apb_pclk"; 2838 2839 out-ports { 2840 port { 2841 apss_funnel_out: endpoint { 2842 remote-endpoint = <&apss_merge_funnel_in>; 2843 }; 2844 }; 2845 }; 2846 2847 in-ports { 2848 #address-cells = <1>; 2849 #size-cells = <0>; 2850 2851 port@0 { 2852 reg = <0>; 2853 apss_funnel_in0: endpoint { 2854 remote-endpoint = <&etm0_out>; 2855 }; 2856 }; 2857 2858 port@1 { 2859 reg = <1>; 2860 apss_funnel_in1: endpoint { 2861 remote-endpoint = <&etm1_out>; 2862 }; 2863 }; 2864 2865 port@2 { 2866 reg = <2>; 2867 apss_funnel_in2: endpoint { 2868 remote-endpoint = <&etm2_out>; 2869 }; 2870 }; 2871 2872 port@3 { 2873 reg = <3>; 2874 apss_funnel_in3: endpoint { 2875 remote-endpoint = <&etm3_out>; 2876 }; 2877 }; 2878 2879 port@4 { 2880 reg = <4>; 2881 apss_funnel_in4: endpoint { 2882 remote-endpoint = <&etm4_out>; 2883 }; 2884 }; 2885 2886 port@5 { 2887 reg = <5>; 2888 apss_funnel_in5: endpoint { 2889 remote-endpoint = <&etm5_out>; 2890 }; 2891 }; 2892 2893 port@6 { 2894 reg = <6>; 2895 apss_funnel_in6: endpoint { 2896 remote-endpoint = <&etm6_out>; 2897 }; 2898 }; 2899 2900 port@7 { 2901 reg = <7>; 2902 apss_funnel_in7: endpoint { 2903 remote-endpoint = <&etm7_out>; 2904 }; 2905 }; 2906 }; 2907 }; 2908 2909 funnel@7810000 { 2910 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2911 reg = <0 0x07810000 0 0x1000>; 2912 2913 clocks = <&aoss_qmp>; 2914 clock-names = "apb_pclk"; 2915 2916 out-ports { 2917 port { 2918 apss_merge_funnel_out: endpoint { 2919 remote-endpoint = <&funnel2_in2>; 2920 }; 2921 }; 2922 }; 2923 2924 in-ports { 2925 port { 2926 apss_merge_funnel_in: endpoint { 2927 remote-endpoint = <&apss_funnel_out>; 2928 }; 2929 }; 2930 }; 2931 }; 2932 2933 remoteproc_cdsp: remoteproc@8300000 { 2934 compatible = "qcom,sm8150-cdsp-pas"; 2935 reg = <0x0 0x08300000 0x0 0x4040>; 2936 2937 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2938 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2939 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2940 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2941 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2942 interrupt-names = "wdog", "fatal", "ready", 2943 "handover", "stop-ack"; 2944 2945 clocks = <&rpmhcc RPMH_CXO_CLK>; 2946 clock-names = "xo"; 2947 2948 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, 2949 <&rpmhpd 7>; 2950 power-domain-names = "load_state", "cx"; 2951 2952 memory-region = <&cdsp_mem>; 2953 2954 qcom,smem-states = <&cdsp_smp2p_out 0>; 2955 qcom,smem-state-names = "stop"; 2956 2957 status = "disabled"; 2958 2959 glink-edge { 2960 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 2961 label = "cdsp"; 2962 qcom,remote-pid = <5>; 2963 mboxes = <&apss_shared 4>; 2964 }; 2965 }; 2966 2967 usb_1_hsphy: phy@88e2000 { 2968 compatible = "qcom,sm8150-usb-hs-phy", 2969 "qcom,usb-snps-hs-7nm-phy"; 2970 reg = <0 0x088e2000 0 0x400>; 2971 status = "disabled"; 2972 #phy-cells = <0>; 2973 2974 clocks = <&rpmhcc RPMH_CXO_CLK>; 2975 clock-names = "ref"; 2976 2977 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2978 }; 2979 2980 usb_2_hsphy: phy@88e3000 { 2981 compatible = "qcom,sm8150-usb-hs-phy", 2982 "qcom,usb-snps-hs-7nm-phy"; 2983 reg = <0 0x088e3000 0 0x400>; 2984 status = "disabled"; 2985 #phy-cells = <0>; 2986 2987 clocks = <&rpmhcc RPMH_CXO_CLK>; 2988 clock-names = "ref"; 2989 2990 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2991 }; 2992 2993 usb_1_qmpphy: phy@88e9000 { 2994 compatible = "qcom,sm8150-qmp-usb3-phy"; 2995 reg = <0 0x088e9000 0 0x18c>, 2996 <0 0x088e8000 0 0x10>; 2997 reg-names = "reg-base", "dp_com"; 2998 status = "disabled"; 2999 #address-cells = <2>; 3000 #size-cells = <2>; 3001 ranges; 3002 3003 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3004 <&rpmhcc RPMH_CXO_CLK>, 3005 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3006 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3007 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3008 3009 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3010 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3011 reset-names = "phy", "common"; 3012 3013 usb_1_ssphy: lanes@88e9200 { 3014 reg = <0 0x088e9200 0 0x200>, 3015 <0 0x088e9400 0 0x200>, 3016 <0 0x088e9c00 0 0x218>, 3017 <0 0x088e9600 0 0x200>, 3018 <0 0x088e9800 0 0x200>, 3019 <0 0x088e9a00 0 0x100>; 3020 #clock-cells = <0>; 3021 #phy-cells = <0>; 3022 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3023 clock-names = "pipe0"; 3024 clock-output-names = "usb3_phy_pipe_clk_src"; 3025 }; 3026 }; 3027 3028 usb_2_qmpphy: phy@88eb000 { 3029 compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 3030 reg = <0 0x088eb000 0 0x200>; 3031 status = "disabled"; 3032 #address-cells = <2>; 3033 #size-cells = <2>; 3034 ranges; 3035 3036 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3037 <&rpmhcc RPMH_CXO_CLK>, 3038 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3039 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3040 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3041 3042 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3043 <&gcc GCC_USB3_PHY_SEC_BCR>; 3044 reset-names = "phy", "common"; 3045 3046 usb_2_ssphy: lane@88eb200 { 3047 reg = <0 0x088eb200 0 0x200>, 3048 <0 0x088eb400 0 0x200>, 3049 <0 0x088eb800 0 0x800>, 3050 <0 0x088eb600 0 0x200>; 3051 #clock-cells = <0>; 3052 #phy-cells = <0>; 3053 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3054 clock-names = "pipe0"; 3055 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3056 }; 3057 }; 3058 3059 dc_noc: interconnect@9160000 { 3060 compatible = "qcom,sm8150-dc-noc"; 3061 reg = <0 0x09160000 0 0x3200>; 3062 #interconnect-cells = <1>; 3063 qcom,bcm-voters = <&apps_bcm_voter>; 3064 }; 3065 3066 gem_noc: interconnect@9680000 { 3067 compatible = "qcom,sm8150-gem-noc"; 3068 reg = <0 0x09680000 0 0x3e200>; 3069 #interconnect-cells = <1>; 3070 qcom,bcm-voters = <&apps_bcm_voter>; 3071 }; 3072 3073 usb_1: usb@a6f8800 { 3074 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3075 reg = <0 0x0a6f8800 0 0x400>; 3076 status = "disabled"; 3077 #address-cells = <2>; 3078 #size-cells = <2>; 3079 ranges; 3080 dma-ranges; 3081 3082 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3083 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3084 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3085 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3086 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3087 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3088 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3089 "sleep", "xo"; 3090 3091 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3092 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3093 assigned-clock-rates = <19200000>, <200000000>; 3094 3095 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3096 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3097 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3098 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3099 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3100 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3101 3102 power-domains = <&gcc USB30_PRIM_GDSC>; 3103 3104 resets = <&gcc GCC_USB30_PRIM_BCR>; 3105 3106 usb_1_dwc3: dwc3@a600000 { 3107 compatible = "snps,dwc3"; 3108 reg = <0 0x0a600000 0 0xcd00>; 3109 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3110 iommus = <&apps_smmu 0x140 0>; 3111 snps,dis_u2_susphy_quirk; 3112 snps,dis_enblslpm_quirk; 3113 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3114 phy-names = "usb2-phy", "usb3-phy"; 3115 }; 3116 }; 3117 3118 usb_2: usb@a8f8800 { 3119 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3120 reg = <0 0x0a8f8800 0 0x400>; 3121 status = "disabled"; 3122 #address-cells = <2>; 3123 #size-cells = <2>; 3124 ranges; 3125 dma-ranges; 3126 3127 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3128 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3129 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3130 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3131 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3132 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3133 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3134 "sleep", "xo"; 3135 3136 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3137 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3138 assigned-clock-rates = <19200000>, <200000000>; 3139 3140 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3141 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3143 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 3144 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3145 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3146 3147 power-domains = <&gcc USB30_SEC_GDSC>; 3148 3149 resets = <&gcc GCC_USB30_SEC_BCR>; 3150 3151 usb_2_dwc3: usb@a800000 { 3152 compatible = "snps,dwc3"; 3153 reg = <0 0x0a800000 0 0xcd00>; 3154 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3155 iommus = <&apps_smmu 0x160 0>; 3156 snps,dis_u2_susphy_quirk; 3157 snps,dis_enblslpm_quirk; 3158 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3159 phy-names = "usb2-phy", "usb3-phy"; 3160 }; 3161 }; 3162 3163 camnoc_virt: interconnect@ac00000 { 3164 compatible = "qcom,sm8150-camnoc-virt"; 3165 reg = <0 0x0ac00000 0 0x1000>; 3166 #interconnect-cells = <1>; 3167 qcom,bcm-voters = <&apps_bcm_voter>; 3168 }; 3169 3170 aoss_qmp: power-controller@c300000 { 3171 compatible = "qcom,sm8150-aoss-qmp"; 3172 reg = <0x0 0x0c300000 0x0 0x100000>; 3173 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3174 mboxes = <&apss_shared 0>; 3175 3176 #clock-cells = <0>; 3177 #power-domain-cells = <1>; 3178 }; 3179 3180 tsens0: thermal-sensor@c263000 { 3181 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3182 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3183 <0 0x0c222000 0 0x1ff>; /* SROT */ 3184 #qcom,sensors = <16>; 3185 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3186 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3187 interrupt-names = "uplow", "critical"; 3188 #thermal-sensor-cells = <1>; 3189 }; 3190 3191 tsens1: thermal-sensor@c265000 { 3192 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3193 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3194 <0 0x0c223000 0 0x1ff>; /* SROT */ 3195 #qcom,sensors = <8>; 3196 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3197 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3198 interrupt-names = "uplow", "critical"; 3199 #thermal-sensor-cells = <1>; 3200 }; 3201 3202 spmi_bus: spmi@c440000 { 3203 compatible = "qcom,spmi-pmic-arb"; 3204 reg = <0x0 0x0c440000 0x0 0x0001100>, 3205 <0x0 0x0c600000 0x0 0x2000000>, 3206 <0x0 0x0e600000 0x0 0x0100000>, 3207 <0x0 0x0e700000 0x0 0x00a0000>, 3208 <0x0 0x0c40a000 0x0 0x0026000>; 3209 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3210 interrupt-names = "periph_irq"; 3211 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3212 qcom,ee = <0>; 3213 qcom,channel = <0>; 3214 #address-cells = <2>; 3215 #size-cells = <0>; 3216 interrupt-controller; 3217 #interrupt-cells = <4>; 3218 cell-index = <0>; 3219 }; 3220 3221 apps_smmu: iommu@15000000 { 3222 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 3223 reg = <0 0x15000000 0 0x100000>; 3224 #iommu-cells = <2>; 3225 #global-interrupts = <1>; 3226 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3227 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3228 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3229 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3230 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3231 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3232 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3233 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3234 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3235 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3236 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3237 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3238 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3239 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3240 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3241 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3242 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3243 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3244 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3245 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3246 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3247 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3248 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3249 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3250 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3251 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3252 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3253 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3254 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3255 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3256 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3257 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3258 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3259 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3260 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3261 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3262 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3263 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3264 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3265 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3266 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3267 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3268 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3269 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3270 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3271 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3272 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3273 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3274 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3275 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3276 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3277 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3278 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3279 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3280 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3281 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3282 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3283 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3284 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3285 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3286 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3287 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3288 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3289 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3290 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3291 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3292 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3293 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3294 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3295 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3296 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3297 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3298 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3299 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3300 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3301 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3302 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3303 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3304 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3305 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3306 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 3307 }; 3308 3309 remoteproc_adsp: remoteproc@17300000 { 3310 compatible = "qcom,sm8150-adsp-pas"; 3311 reg = <0x0 0x17300000 0x0 0x4040>; 3312 3313 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3314 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3315 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3316 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3317 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3318 interrupt-names = "wdog", "fatal", "ready", 3319 "handover", "stop-ack"; 3320 3321 clocks = <&rpmhcc RPMH_CXO_CLK>; 3322 clock-names = "xo"; 3323 3324 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, 3325 <&rpmhpd 7>; 3326 power-domain-names = "load_state", "cx"; 3327 3328 memory-region = <&adsp_mem>; 3329 3330 qcom,smem-states = <&adsp_smp2p_out 0>; 3331 qcom,smem-state-names = "stop"; 3332 3333 status = "disabled"; 3334 3335 glink-edge { 3336 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3337 label = "lpass"; 3338 qcom,remote-pid = <2>; 3339 mboxes = <&apss_shared 8>; 3340 }; 3341 }; 3342 3343 intc: interrupt-controller@17a00000 { 3344 compatible = "arm,gic-v3"; 3345 interrupt-controller; 3346 #interrupt-cells = <3>; 3347 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3348 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3349 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3350 }; 3351 3352 apss_shared: mailbox@17c00000 { 3353 compatible = "qcom,sm8150-apss-shared"; 3354 reg = <0x0 0x17c00000 0x0 0x1000>; 3355 #mbox-cells = <1>; 3356 }; 3357 3358 watchdog@17c10000 { 3359 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 3360 reg = <0 0x17c10000 0 0x1000>; 3361 clocks = <&sleep_clk>; 3362 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3363 }; 3364 3365 timer@17c20000 { 3366 #address-cells = <2>; 3367 #size-cells = <2>; 3368 ranges; 3369 compatible = "arm,armv7-timer-mem"; 3370 reg = <0x0 0x17c20000 0x0 0x1000>; 3371 clock-frequency = <19200000>; 3372 3373 frame@17c21000{ 3374 frame-number = <0>; 3375 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3377 reg = <0x0 0x17c21000 0x0 0x1000>, 3378 <0x0 0x17c22000 0x0 0x1000>; 3379 }; 3380 3381 frame@17c23000 { 3382 frame-number = <1>; 3383 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3384 reg = <0x0 0x17c23000 0x0 0x1000>; 3385 status = "disabled"; 3386 }; 3387 3388 frame@17c25000 { 3389 frame-number = <2>; 3390 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3391 reg = <0x0 0x17c25000 0x0 0x1000>; 3392 status = "disabled"; 3393 }; 3394 3395 frame@17c27000 { 3396 frame-number = <3>; 3397 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3398 reg = <0x0 0x17c26000 0x0 0x1000>; 3399 status = "disabled"; 3400 }; 3401 3402 frame@17c29000 { 3403 frame-number = <4>; 3404 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3405 reg = <0x0 0x17c29000 0x0 0x1000>; 3406 status = "disabled"; 3407 }; 3408 3409 frame@17c2b000 { 3410 frame-number = <5>; 3411 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3412 reg = <0x0 0x17c2b000 0x0 0x1000>; 3413 status = "disabled"; 3414 }; 3415 3416 frame@17c2d000 { 3417 frame-number = <6>; 3418 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3419 reg = <0x0 0x17c2d000 0x0 0x1000>; 3420 status = "disabled"; 3421 }; 3422 }; 3423 3424 apps_rsc: rsc@18200000 { 3425 label = "apps_rsc"; 3426 compatible = "qcom,rpmh-rsc"; 3427 reg = <0x0 0x18200000 0x0 0x10000>, 3428 <0x0 0x18210000 0x0 0x10000>, 3429 <0x0 0x18220000 0x0 0x10000>; 3430 reg-names = "drv-0", "drv-1", "drv-2"; 3431 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3432 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3433 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3434 qcom,tcs-offset = <0xd00>; 3435 qcom,drv-id = <2>; 3436 qcom,tcs-config = <ACTIVE_TCS 2>, 3437 <SLEEP_TCS 1>, 3438 <WAKE_TCS 1>, 3439 <CONTROL_TCS 0>; 3440 3441 rpmhcc: clock-controller { 3442 compatible = "qcom,sm8150-rpmh-clk"; 3443 #clock-cells = <1>; 3444 clock-names = "xo"; 3445 clocks = <&xo_board>; 3446 }; 3447 3448 rpmhpd: power-controller { 3449 compatible = "qcom,sm8150-rpmhpd"; 3450 #power-domain-cells = <1>; 3451 operating-points-v2 = <&rpmhpd_opp_table>; 3452 3453 rpmhpd_opp_table: opp-table { 3454 compatible = "operating-points-v2"; 3455 3456 rpmhpd_opp_ret: opp1 { 3457 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3458 }; 3459 3460 rpmhpd_opp_min_svs: opp2 { 3461 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3462 }; 3463 3464 rpmhpd_opp_low_svs: opp3 { 3465 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3466 }; 3467 3468 rpmhpd_opp_svs: opp4 { 3469 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3470 }; 3471 3472 rpmhpd_opp_svs_l1: opp5 { 3473 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3474 }; 3475 3476 rpmhpd_opp_svs_l2: opp6 { 3477 opp-level = <224>; 3478 }; 3479 3480 rpmhpd_opp_nom: opp7 { 3481 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3482 }; 3483 3484 rpmhpd_opp_nom_l1: opp8 { 3485 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3486 }; 3487 3488 rpmhpd_opp_nom_l2: opp9 { 3489 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3490 }; 3491 3492 rpmhpd_opp_turbo: opp10 { 3493 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3494 }; 3495 3496 rpmhpd_opp_turbo_l1: opp11 { 3497 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3498 }; 3499 }; 3500 }; 3501 3502 apps_bcm_voter: bcm_voter { 3503 compatible = "qcom,bcm-voter"; 3504 }; 3505 }; 3506 3507 osm_l3: interconnect@18321000 { 3508 compatible = "qcom,sm8150-osm-l3"; 3509 reg = <0 0x18321000 0 0x1400>; 3510 3511 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3512 clock-names = "xo", "alternate"; 3513 3514 #interconnect-cells = <1>; 3515 }; 3516 3517 cpufreq_hw: cpufreq@18323000 { 3518 compatible = "qcom,cpufreq-hw"; 3519 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 3520 <0 0x18327800 0 0x1400>; 3521 reg-names = "freq-domain0", "freq-domain1", 3522 "freq-domain2"; 3523 3524 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3525 clock-names = "xo", "alternate"; 3526 3527 #freq-domain-cells = <1>; 3528 }; 3529 3530 wifi: wifi@18800000 { 3531 compatible = "qcom,wcn3990-wifi"; 3532 reg = <0 0x18800000 0 0x800000>; 3533 reg-names = "membase"; 3534 memory-region = <&wlan_mem>; 3535 clock-names = "cxo_ref_clk_pin", "qdss"; 3536 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 3537 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3538 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3539 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3540 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3541 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3542 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3543 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3544 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3545 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3546 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3547 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3548 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3549 iommus = <&apps_smmu 0x0640 0x1>; 3550 status = "disabled"; 3551 }; 3552 }; 3553 3554 timer { 3555 compatible = "arm,armv8-timer"; 3556 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 3557 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 3558 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 3559 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 3560 }; 3561 3562 thermal-zones { 3563 cpu0-thermal { 3564 polling-delay-passive = <250>; 3565 polling-delay = <1000>; 3566 3567 thermal-sensors = <&tsens0 1>; 3568 3569 trips { 3570 cpu0_alert0: trip-point0 { 3571 temperature = <90000>; 3572 hysteresis = <2000>; 3573 type = "passive"; 3574 }; 3575 3576 cpu0_alert1: trip-point1 { 3577 temperature = <95000>; 3578 hysteresis = <2000>; 3579 type = "passive"; 3580 }; 3581 3582 cpu0_crit: cpu_crit { 3583 temperature = <110000>; 3584 hysteresis = <1000>; 3585 type = "critical"; 3586 }; 3587 }; 3588 3589 cooling-maps { 3590 map0 { 3591 trip = <&cpu0_alert0>; 3592 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3593 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3594 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3595 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3596 }; 3597 map1 { 3598 trip = <&cpu0_alert1>; 3599 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3600 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3601 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3602 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3603 }; 3604 }; 3605 }; 3606 3607 cpu1-thermal { 3608 polling-delay-passive = <250>; 3609 polling-delay = <1000>; 3610 3611 thermal-sensors = <&tsens0 2>; 3612 3613 trips { 3614 cpu1_alert0: trip-point0 { 3615 temperature = <90000>; 3616 hysteresis = <2000>; 3617 type = "passive"; 3618 }; 3619 3620 cpu1_alert1: trip-point1 { 3621 temperature = <95000>; 3622 hysteresis = <2000>; 3623 type = "passive"; 3624 }; 3625 3626 cpu1_crit: cpu_crit { 3627 temperature = <110000>; 3628 hysteresis = <1000>; 3629 type = "critical"; 3630 }; 3631 }; 3632 3633 cooling-maps { 3634 map0 { 3635 trip = <&cpu1_alert0>; 3636 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3637 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3638 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3639 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3640 }; 3641 map1 { 3642 trip = <&cpu1_alert1>; 3643 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3644 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3645 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3646 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3647 }; 3648 }; 3649 }; 3650 3651 cpu2-thermal { 3652 polling-delay-passive = <250>; 3653 polling-delay = <1000>; 3654 3655 thermal-sensors = <&tsens0 3>; 3656 3657 trips { 3658 cpu2_alert0: trip-point0 { 3659 temperature = <90000>; 3660 hysteresis = <2000>; 3661 type = "passive"; 3662 }; 3663 3664 cpu2_alert1: trip-point1 { 3665 temperature = <95000>; 3666 hysteresis = <2000>; 3667 type = "passive"; 3668 }; 3669 3670 cpu2_crit: cpu_crit { 3671 temperature = <110000>; 3672 hysteresis = <1000>; 3673 type = "critical"; 3674 }; 3675 }; 3676 3677 cooling-maps { 3678 map0 { 3679 trip = <&cpu2_alert0>; 3680 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3681 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3682 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3683 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3684 }; 3685 map1 { 3686 trip = <&cpu2_alert1>; 3687 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3688 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3689 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3690 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3691 }; 3692 }; 3693 }; 3694 3695 cpu3-thermal { 3696 polling-delay-passive = <250>; 3697 polling-delay = <1000>; 3698 3699 thermal-sensors = <&tsens0 4>; 3700 3701 trips { 3702 cpu3_alert0: trip-point0 { 3703 temperature = <90000>; 3704 hysteresis = <2000>; 3705 type = "passive"; 3706 }; 3707 3708 cpu3_alert1: trip-point1 { 3709 temperature = <95000>; 3710 hysteresis = <2000>; 3711 type = "passive"; 3712 }; 3713 3714 cpu3_crit: cpu_crit { 3715 temperature = <110000>; 3716 hysteresis = <1000>; 3717 type = "critical"; 3718 }; 3719 }; 3720 3721 cooling-maps { 3722 map0 { 3723 trip = <&cpu3_alert0>; 3724 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3725 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3726 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3727 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3728 }; 3729 map1 { 3730 trip = <&cpu3_alert1>; 3731 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3732 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3733 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3734 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3735 }; 3736 }; 3737 }; 3738 3739 cpu4-top-thermal { 3740 polling-delay-passive = <250>; 3741 polling-delay = <1000>; 3742 3743 thermal-sensors = <&tsens0 7>; 3744 3745 trips { 3746 cpu4_top_alert0: trip-point0 { 3747 temperature = <90000>; 3748 hysteresis = <2000>; 3749 type = "passive"; 3750 }; 3751 3752 cpu4_top_alert1: trip-point1 { 3753 temperature = <95000>; 3754 hysteresis = <2000>; 3755 type = "passive"; 3756 }; 3757 3758 cpu4_top_crit: cpu_crit { 3759 temperature = <110000>; 3760 hysteresis = <1000>; 3761 type = "critical"; 3762 }; 3763 }; 3764 3765 cooling-maps { 3766 map0 { 3767 trip = <&cpu4_top_alert0>; 3768 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3769 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3770 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3771 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3772 }; 3773 map1 { 3774 trip = <&cpu4_top_alert1>; 3775 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3776 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3777 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3778 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3779 }; 3780 }; 3781 }; 3782 3783 cpu5-top-thermal { 3784 polling-delay-passive = <250>; 3785 polling-delay = <1000>; 3786 3787 thermal-sensors = <&tsens0 8>; 3788 3789 trips { 3790 cpu5_top_alert0: trip-point0 { 3791 temperature = <90000>; 3792 hysteresis = <2000>; 3793 type = "passive"; 3794 }; 3795 3796 cpu5_top_alert1: trip-point1 { 3797 temperature = <95000>; 3798 hysteresis = <2000>; 3799 type = "passive"; 3800 }; 3801 3802 cpu5_top_crit: cpu_crit { 3803 temperature = <110000>; 3804 hysteresis = <1000>; 3805 type = "critical"; 3806 }; 3807 }; 3808 3809 cooling-maps { 3810 map0 { 3811 trip = <&cpu5_top_alert0>; 3812 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3813 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3814 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3815 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3816 }; 3817 map1 { 3818 trip = <&cpu5_top_alert1>; 3819 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3820 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3821 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3822 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3823 }; 3824 }; 3825 }; 3826 3827 cpu6-top-thermal { 3828 polling-delay-passive = <250>; 3829 polling-delay = <1000>; 3830 3831 thermal-sensors = <&tsens0 9>; 3832 3833 trips { 3834 cpu6_top_alert0: trip-point0 { 3835 temperature = <90000>; 3836 hysteresis = <2000>; 3837 type = "passive"; 3838 }; 3839 3840 cpu6_top_alert1: trip-point1 { 3841 temperature = <95000>; 3842 hysteresis = <2000>; 3843 type = "passive"; 3844 }; 3845 3846 cpu6_top_crit: cpu_crit { 3847 temperature = <110000>; 3848 hysteresis = <1000>; 3849 type = "critical"; 3850 }; 3851 }; 3852 3853 cooling-maps { 3854 map0 { 3855 trip = <&cpu6_top_alert0>; 3856 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3857 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3858 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3859 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3860 }; 3861 map1 { 3862 trip = <&cpu6_top_alert1>; 3863 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3864 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3865 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3866 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3867 }; 3868 }; 3869 }; 3870 3871 cpu7-top-thermal { 3872 polling-delay-passive = <250>; 3873 polling-delay = <1000>; 3874 3875 thermal-sensors = <&tsens0 10>; 3876 3877 trips { 3878 cpu7_top_alert0: trip-point0 { 3879 temperature = <90000>; 3880 hysteresis = <2000>; 3881 type = "passive"; 3882 }; 3883 3884 cpu7_top_alert1: trip-point1 { 3885 temperature = <95000>; 3886 hysteresis = <2000>; 3887 type = "passive"; 3888 }; 3889 3890 cpu7_top_crit: cpu_crit { 3891 temperature = <110000>; 3892 hysteresis = <1000>; 3893 type = "critical"; 3894 }; 3895 }; 3896 3897 cooling-maps { 3898 map0 { 3899 trip = <&cpu7_top_alert0>; 3900 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3901 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3902 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3903 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3904 }; 3905 map1 { 3906 trip = <&cpu7_top_alert1>; 3907 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3908 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3909 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3910 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3911 }; 3912 }; 3913 }; 3914 3915 cpu4-bottom-thermal { 3916 polling-delay-passive = <250>; 3917 polling-delay = <1000>; 3918 3919 thermal-sensors = <&tsens0 11>; 3920 3921 trips { 3922 cpu4_bottom_alert0: trip-point0 { 3923 temperature = <90000>; 3924 hysteresis = <2000>; 3925 type = "passive"; 3926 }; 3927 3928 cpu4_bottom_alert1: trip-point1 { 3929 temperature = <95000>; 3930 hysteresis = <2000>; 3931 type = "passive"; 3932 }; 3933 3934 cpu4_bottom_crit: cpu_crit { 3935 temperature = <110000>; 3936 hysteresis = <1000>; 3937 type = "critical"; 3938 }; 3939 }; 3940 3941 cooling-maps { 3942 map0 { 3943 trip = <&cpu4_bottom_alert0>; 3944 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3945 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3946 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3947 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3948 }; 3949 map1 { 3950 trip = <&cpu4_bottom_alert1>; 3951 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3952 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3953 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3954 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3955 }; 3956 }; 3957 }; 3958 3959 cpu5-bottom-thermal { 3960 polling-delay-passive = <250>; 3961 polling-delay = <1000>; 3962 3963 thermal-sensors = <&tsens0 12>; 3964 3965 trips { 3966 cpu5_bottom_alert0: trip-point0 { 3967 temperature = <90000>; 3968 hysteresis = <2000>; 3969 type = "passive"; 3970 }; 3971 3972 cpu5_bottom_alert1: trip-point1 { 3973 temperature = <95000>; 3974 hysteresis = <2000>; 3975 type = "passive"; 3976 }; 3977 3978 cpu5_bottom_crit: cpu_crit { 3979 temperature = <110000>; 3980 hysteresis = <1000>; 3981 type = "critical"; 3982 }; 3983 }; 3984 3985 cooling-maps { 3986 map0 { 3987 trip = <&cpu5_bottom_alert0>; 3988 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3989 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3990 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3991 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3992 }; 3993 map1 { 3994 trip = <&cpu5_bottom_alert1>; 3995 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3996 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3997 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3998 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3999 }; 4000 }; 4001 }; 4002 4003 cpu6-bottom-thermal { 4004 polling-delay-passive = <250>; 4005 polling-delay = <1000>; 4006 4007 thermal-sensors = <&tsens0 13>; 4008 4009 trips { 4010 cpu6_bottom_alert0: trip-point0 { 4011 temperature = <90000>; 4012 hysteresis = <2000>; 4013 type = "passive"; 4014 }; 4015 4016 cpu6_bottom_alert1: trip-point1 { 4017 temperature = <95000>; 4018 hysteresis = <2000>; 4019 type = "passive"; 4020 }; 4021 4022 cpu6_bottom_crit: cpu_crit { 4023 temperature = <110000>; 4024 hysteresis = <1000>; 4025 type = "critical"; 4026 }; 4027 }; 4028 4029 cooling-maps { 4030 map0 { 4031 trip = <&cpu6_bottom_alert0>; 4032 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4033 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4034 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4035 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4036 }; 4037 map1 { 4038 trip = <&cpu6_bottom_alert1>; 4039 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4040 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4041 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4042 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4043 }; 4044 }; 4045 }; 4046 4047 cpu7-bottom-thermal { 4048 polling-delay-passive = <250>; 4049 polling-delay = <1000>; 4050 4051 thermal-sensors = <&tsens0 14>; 4052 4053 trips { 4054 cpu7_bottom_alert0: trip-point0 { 4055 temperature = <90000>; 4056 hysteresis = <2000>; 4057 type = "passive"; 4058 }; 4059 4060 cpu7_bottom_alert1: trip-point1 { 4061 temperature = <95000>; 4062 hysteresis = <2000>; 4063 type = "passive"; 4064 }; 4065 4066 cpu7_bottom_crit: cpu_crit { 4067 temperature = <110000>; 4068 hysteresis = <1000>; 4069 type = "critical"; 4070 }; 4071 }; 4072 4073 cooling-maps { 4074 map0 { 4075 trip = <&cpu7_bottom_alert0>; 4076 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4077 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4078 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4079 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4080 }; 4081 map1 { 4082 trip = <&cpu7_bottom_alert1>; 4083 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4084 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4085 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4086 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4087 }; 4088 }; 4089 }; 4090 4091 aoss0-thermal { 4092 polling-delay-passive = <250>; 4093 polling-delay = <1000>; 4094 4095 thermal-sensors = <&tsens0 0>; 4096 4097 trips { 4098 aoss0_alert0: trip-point0 { 4099 temperature = <90000>; 4100 hysteresis = <2000>; 4101 type = "hot"; 4102 }; 4103 }; 4104 }; 4105 4106 cluster0-thermal { 4107 polling-delay-passive = <250>; 4108 polling-delay = <1000>; 4109 4110 thermal-sensors = <&tsens0 5>; 4111 4112 trips { 4113 cluster0_alert0: trip-point0 { 4114 temperature = <90000>; 4115 hysteresis = <2000>; 4116 type = "hot"; 4117 }; 4118 cluster0_crit: cluster0_crit { 4119 temperature = <110000>; 4120 hysteresis = <2000>; 4121 type = "critical"; 4122 }; 4123 }; 4124 }; 4125 4126 cluster1-thermal { 4127 polling-delay-passive = <250>; 4128 polling-delay = <1000>; 4129 4130 thermal-sensors = <&tsens0 6>; 4131 4132 trips { 4133 cluster1_alert0: trip-point0 { 4134 temperature = <90000>; 4135 hysteresis = <2000>; 4136 type = "hot"; 4137 }; 4138 cluster1_crit: cluster1_crit { 4139 temperature = <110000>; 4140 hysteresis = <2000>; 4141 type = "critical"; 4142 }; 4143 }; 4144 }; 4145 4146 gpu-thermal-top { 4147 polling-delay-passive = <250>; 4148 polling-delay = <1000>; 4149 4150 thermal-sensors = <&tsens0 15>; 4151 4152 trips { 4153 gpu1_alert0: trip-point0 { 4154 temperature = <90000>; 4155 hysteresis = <2000>; 4156 type = "hot"; 4157 }; 4158 }; 4159 }; 4160 4161 aoss1-thermal { 4162 polling-delay-passive = <250>; 4163 polling-delay = <1000>; 4164 4165 thermal-sensors = <&tsens1 0>; 4166 4167 trips { 4168 aoss1_alert0: trip-point0 { 4169 temperature = <90000>; 4170 hysteresis = <2000>; 4171 type = "hot"; 4172 }; 4173 }; 4174 }; 4175 4176 wlan-thermal { 4177 polling-delay-passive = <250>; 4178 polling-delay = <1000>; 4179 4180 thermal-sensors = <&tsens1 1>; 4181 4182 trips { 4183 wlan_alert0: trip-point0 { 4184 temperature = <90000>; 4185 hysteresis = <2000>; 4186 type = "hot"; 4187 }; 4188 }; 4189 }; 4190 4191 video-thermal { 4192 polling-delay-passive = <250>; 4193 polling-delay = <1000>; 4194 4195 thermal-sensors = <&tsens1 2>; 4196 4197 trips { 4198 video_alert0: trip-point0 { 4199 temperature = <90000>; 4200 hysteresis = <2000>; 4201 type = "hot"; 4202 }; 4203 }; 4204 }; 4205 4206 mem-thermal { 4207 polling-delay-passive = <250>; 4208 polling-delay = <1000>; 4209 4210 thermal-sensors = <&tsens1 3>; 4211 4212 trips { 4213 mem_alert0: trip-point0 { 4214 temperature = <90000>; 4215 hysteresis = <2000>; 4216 type = "hot"; 4217 }; 4218 }; 4219 }; 4220 4221 q6-hvx-thermal { 4222 polling-delay-passive = <250>; 4223 polling-delay = <1000>; 4224 4225 thermal-sensors = <&tsens1 4>; 4226 4227 trips { 4228 q6_hvx_alert0: trip-point0 { 4229 temperature = <90000>; 4230 hysteresis = <2000>; 4231 type = "hot"; 4232 }; 4233 }; 4234 }; 4235 4236 camera-thermal { 4237 polling-delay-passive = <250>; 4238 polling-delay = <1000>; 4239 4240 thermal-sensors = <&tsens1 5>; 4241 4242 trips { 4243 camera_alert0: trip-point0 { 4244 temperature = <90000>; 4245 hysteresis = <2000>; 4246 type = "hot"; 4247 }; 4248 }; 4249 }; 4250 4251 compute-thermal { 4252 polling-delay-passive = <250>; 4253 polling-delay = <1000>; 4254 4255 thermal-sensors = <&tsens1 6>; 4256 4257 trips { 4258 compute_alert0: trip-point0 { 4259 temperature = <90000>; 4260 hysteresis = <2000>; 4261 type = "hot"; 4262 }; 4263 }; 4264 }; 4265 4266 modem-thermal { 4267 polling-delay-passive = <250>; 4268 polling-delay = <1000>; 4269 4270 thermal-sensors = <&tsens1 7>; 4271 4272 trips { 4273 modem_alert0: trip-point0 { 4274 temperature = <90000>; 4275 hysteresis = <2000>; 4276 type = "hot"; 4277 }; 4278 }; 4279 }; 4280 4281 npu-thermal { 4282 polling-delay-passive = <250>; 4283 polling-delay = <1000>; 4284 4285 thermal-sensors = <&tsens1 8>; 4286 4287 trips { 4288 npu_alert0: trip-point0 { 4289 temperature = <90000>; 4290 hysteresis = <2000>; 4291 type = "hot"; 4292 }; 4293 }; 4294 }; 4295 4296 modem-vec-thermal { 4297 polling-delay-passive = <250>; 4298 polling-delay = <1000>; 4299 4300 thermal-sensors = <&tsens1 9>; 4301 4302 trips { 4303 modem_vec_alert0: trip-point0 { 4304 temperature = <90000>; 4305 hysteresis = <2000>; 4306 type = "hot"; 4307 }; 4308 }; 4309 }; 4310 4311 modem-scl-thermal { 4312 polling-delay-passive = <250>; 4313 polling-delay = <1000>; 4314 4315 thermal-sensors = <&tsens1 10>; 4316 4317 trips { 4318 modem_scl_alert0: trip-point0 { 4319 temperature = <90000>; 4320 hysteresis = <2000>; 4321 type = "hot"; 4322 }; 4323 }; 4324 }; 4325 4326 gpu-thermal-bottom { 4327 polling-delay-passive = <250>; 4328 polling-delay = <1000>; 4329 4330 thermal-sensors = <&tsens1 11>; 4331 4332 trips { 4333 gpu2_alert0: trip-point0 { 4334 temperature = <90000>; 4335 hysteresis = <2000>; 4336 type = "hot"; 4337 }; 4338 }; 4339 }; 4340 }; 4341}; 4342