1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/dma/qcom-gpi.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,gcc-sm8150.h> 13#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sm8150.h> 16#include <dt-bindings/thermal/thermal.h> 17 18/ { 19 interrupt-parent = <&intc>; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 chosen { }; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <38400000>; 31 clock-output-names = "xo_board"; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32764>; 38 clock-output-names = "sleep_clk"; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "qcom,kryo485"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 capacity-dmips-mhz = <488>; 52 dynamic-power-coefficient = <232>; 53 next-level-cache = <&L2_0>; 54 qcom,freq-domain = <&cpufreq_hw 0>; 55 operating-points-v2 = <&cpu0_opp_table>; 56 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 57 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 58 power-domains = <&CPU_PD0>; 59 power-domain-names = "psci"; 60 #cooling-cells = <2>; 61 L2_0: l2-cache { 62 compatible = "cache"; 63 next-level-cache = <&L3_0>; 64 L3_0: l3-cache { 65 compatible = "cache"; 66 }; 67 }; 68 }; 69 70 CPU1: cpu@100 { 71 device_type = "cpu"; 72 compatible = "qcom,kryo485"; 73 reg = <0x0 0x100>; 74 enable-method = "psci"; 75 capacity-dmips-mhz = <488>; 76 dynamic-power-coefficient = <232>; 77 next-level-cache = <&L2_100>; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 operating-points-v2 = <&cpu0_opp_table>; 80 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 81 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 82 power-domains = <&CPU_PD1>; 83 power-domain-names = "psci"; 84 #cooling-cells = <2>; 85 L2_100: l2-cache { 86 compatible = "cache"; 87 next-level-cache = <&L3_0>; 88 }; 89 90 }; 91 92 CPU2: cpu@200 { 93 device_type = "cpu"; 94 compatible = "qcom,kryo485"; 95 reg = <0x0 0x200>; 96 enable-method = "psci"; 97 capacity-dmips-mhz = <488>; 98 dynamic-power-coefficient = <232>; 99 next-level-cache = <&L2_200>; 100 qcom,freq-domain = <&cpufreq_hw 0>; 101 operating-points-v2 = <&cpu0_opp_table>; 102 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 103 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 104 power-domains = <&CPU_PD2>; 105 power-domain-names = "psci"; 106 #cooling-cells = <2>; 107 L2_200: l2-cache { 108 compatible = "cache"; 109 next-level-cache = <&L3_0>; 110 }; 111 }; 112 113 CPU3: cpu@300 { 114 device_type = "cpu"; 115 compatible = "qcom,kryo485"; 116 reg = <0x0 0x300>; 117 enable-method = "psci"; 118 capacity-dmips-mhz = <488>; 119 dynamic-power-coefficient = <232>; 120 next-level-cache = <&L2_300>; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 operating-points-v2 = <&cpu0_opp_table>; 123 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 124 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 125 power-domains = <&CPU_PD3>; 126 power-domain-names = "psci"; 127 #cooling-cells = <2>; 128 L2_300: l2-cache { 129 compatible = "cache"; 130 next-level-cache = <&L3_0>; 131 }; 132 }; 133 134 CPU4: cpu@400 { 135 device_type = "cpu"; 136 compatible = "qcom,kryo485"; 137 reg = <0x0 0x400>; 138 enable-method = "psci"; 139 capacity-dmips-mhz = <1024>; 140 dynamic-power-coefficient = <369>; 141 next-level-cache = <&L2_400>; 142 qcom,freq-domain = <&cpufreq_hw 1>; 143 operating-points-v2 = <&cpu4_opp_table>; 144 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 145 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 146 power-domains = <&CPU_PD4>; 147 power-domain-names = "psci"; 148 #cooling-cells = <2>; 149 L2_400: l2-cache { 150 compatible = "cache"; 151 next-level-cache = <&L3_0>; 152 }; 153 }; 154 155 CPU5: cpu@500 { 156 device_type = "cpu"; 157 compatible = "qcom,kryo485"; 158 reg = <0x0 0x500>; 159 enable-method = "psci"; 160 capacity-dmips-mhz = <1024>; 161 dynamic-power-coefficient = <369>; 162 next-level-cache = <&L2_500>; 163 qcom,freq-domain = <&cpufreq_hw 1>; 164 operating-points-v2 = <&cpu4_opp_table>; 165 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 166 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 167 power-domains = <&CPU_PD5>; 168 power-domain-names = "psci"; 169 #cooling-cells = <2>; 170 L2_500: l2-cache { 171 compatible = "cache"; 172 next-level-cache = <&L3_0>; 173 }; 174 }; 175 176 CPU6: cpu@600 { 177 device_type = "cpu"; 178 compatible = "qcom,kryo485"; 179 reg = <0x0 0x600>; 180 enable-method = "psci"; 181 capacity-dmips-mhz = <1024>; 182 dynamic-power-coefficient = <369>; 183 next-level-cache = <&L2_600>; 184 qcom,freq-domain = <&cpufreq_hw 1>; 185 operating-points-v2 = <&cpu4_opp_table>; 186 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 187 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 188 power-domains = <&CPU_PD6>; 189 power-domain-names = "psci"; 190 #cooling-cells = <2>; 191 L2_600: l2-cache { 192 compatible = "cache"; 193 next-level-cache = <&L3_0>; 194 }; 195 }; 196 197 CPU7: cpu@700 { 198 device_type = "cpu"; 199 compatible = "qcom,kryo485"; 200 reg = <0x0 0x700>; 201 enable-method = "psci"; 202 capacity-dmips-mhz = <1024>; 203 dynamic-power-coefficient = <421>; 204 next-level-cache = <&L2_700>; 205 qcom,freq-domain = <&cpufreq_hw 2>; 206 operating-points-v2 = <&cpu7_opp_table>; 207 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 208 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 209 power-domains = <&CPU_PD7>; 210 power-domain-names = "psci"; 211 #cooling-cells = <2>; 212 L2_700: l2-cache { 213 compatible = "cache"; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 cpu-map { 219 cluster0 { 220 core0 { 221 cpu = <&CPU0>; 222 }; 223 224 core1 { 225 cpu = <&CPU1>; 226 }; 227 228 core2 { 229 cpu = <&CPU2>; 230 }; 231 232 core3 { 233 cpu = <&CPU3>; 234 }; 235 236 core4 { 237 cpu = <&CPU4>; 238 }; 239 240 core5 { 241 cpu = <&CPU5>; 242 }; 243 244 core6 { 245 cpu = <&CPU6>; 246 }; 247 248 core7 { 249 cpu = <&CPU7>; 250 }; 251 }; 252 }; 253 254 idle-states { 255 entry-method = "psci"; 256 257 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 258 compatible = "arm,idle-state"; 259 idle-state-name = "little-rail-power-collapse"; 260 arm,psci-suspend-param = <0x40000004>; 261 entry-latency-us = <355>; 262 exit-latency-us = <909>; 263 min-residency-us = <3934>; 264 local-timer-stop; 265 }; 266 267 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "big-rail-power-collapse"; 270 arm,psci-suspend-param = <0x40000004>; 271 entry-latency-us = <241>; 272 exit-latency-us = <1461>; 273 min-residency-us = <4488>; 274 local-timer-stop; 275 }; 276 }; 277 278 domain-idle-states { 279 CLUSTER_SLEEP_0: cluster-sleep-0 { 280 compatible = "domain-idle-state"; 281 idle-state-name = "cluster-power-collapse"; 282 arm,psci-suspend-param = <0x4100c244>; 283 entry-latency-us = <3263>; 284 exit-latency-us = <6562>; 285 min-residency-us = <9987>; 286 local-timer-stop; 287 }; 288 }; 289 }; 290 291 cpu0_opp_table: opp-table-cpu0 { 292 compatible = "operating-points-v2"; 293 opp-shared; 294 295 cpu0_opp1: opp-300000000 { 296 opp-hz = /bits/ 64 <300000000>; 297 opp-peak-kBps = <800000 9600000>; 298 }; 299 300 cpu0_opp2: opp-403200000 { 301 opp-hz = /bits/ 64 <403200000>; 302 opp-peak-kBps = <800000 9600000>; 303 }; 304 305 cpu0_opp3: opp-499200000 { 306 opp-hz = /bits/ 64 <499200000>; 307 opp-peak-kBps = <800000 12902400>; 308 }; 309 310 cpu0_opp4: opp-576000000 { 311 opp-hz = /bits/ 64 <576000000>; 312 opp-peak-kBps = <800000 12902400>; 313 }; 314 315 cpu0_opp5: opp-672000000 { 316 opp-hz = /bits/ 64 <672000000>; 317 opp-peak-kBps = <800000 15974400>; 318 }; 319 320 cpu0_opp6: opp-768000000 { 321 opp-hz = /bits/ 64 <768000000>; 322 opp-peak-kBps = <1804000 19660800>; 323 }; 324 325 cpu0_opp7: opp-844800000 { 326 opp-hz = /bits/ 64 <844800000>; 327 opp-peak-kBps = <1804000 19660800>; 328 }; 329 330 cpu0_opp8: opp-940800000 { 331 opp-hz = /bits/ 64 <940800000>; 332 opp-peak-kBps = <1804000 22732800>; 333 }; 334 335 cpu0_opp9: opp-1036800000 { 336 opp-hz = /bits/ 64 <1036800000>; 337 opp-peak-kBps = <1804000 22732800>; 338 }; 339 340 cpu0_opp10: opp-1113600000 { 341 opp-hz = /bits/ 64 <1113600000>; 342 opp-peak-kBps = <2188000 25804800>; 343 }; 344 345 cpu0_opp11: opp-1209600000 { 346 opp-hz = /bits/ 64 <1209600000>; 347 opp-peak-kBps = <2188000 31948800>; 348 }; 349 350 cpu0_opp12: opp-1305600000 { 351 opp-hz = /bits/ 64 <1305600000>; 352 opp-peak-kBps = <3072000 31948800>; 353 }; 354 355 cpu0_opp13: opp-1382400000 { 356 opp-hz = /bits/ 64 <1382400000>; 357 opp-peak-kBps = <3072000 31948800>; 358 }; 359 360 cpu0_opp14: opp-1478400000 { 361 opp-hz = /bits/ 64 <1478400000>; 362 opp-peak-kBps = <3072000 31948800>; 363 }; 364 365 cpu0_opp15: opp-1555200000 { 366 opp-hz = /bits/ 64 <1555200000>; 367 opp-peak-kBps = <3072000 40550400>; 368 }; 369 370 cpu0_opp16: opp-1632000000 { 371 opp-hz = /bits/ 64 <1632000000>; 372 opp-peak-kBps = <3072000 40550400>; 373 }; 374 375 cpu0_opp17: opp-1708800000 { 376 opp-hz = /bits/ 64 <1708800000>; 377 opp-peak-kBps = <3072000 43008000>; 378 }; 379 380 cpu0_opp18: opp-1785600000 { 381 opp-hz = /bits/ 64 <1785600000>; 382 opp-peak-kBps = <3072000 43008000>; 383 }; 384 }; 385 386 cpu4_opp_table: opp-table-cpu4 { 387 compatible = "operating-points-v2"; 388 opp-shared; 389 390 cpu4_opp1: opp-710400000 { 391 opp-hz = /bits/ 64 <710400000>; 392 opp-peak-kBps = <1804000 15974400>; 393 }; 394 395 cpu4_opp2: opp-825600000 { 396 opp-hz = /bits/ 64 <825600000>; 397 opp-peak-kBps = <2188000 19660800>; 398 }; 399 400 cpu4_opp3: opp-940800000 { 401 opp-hz = /bits/ 64 <940800000>; 402 opp-peak-kBps = <2188000 22732800>; 403 }; 404 405 cpu4_opp4: opp-1056000000 { 406 opp-hz = /bits/ 64 <1056000000>; 407 opp-peak-kBps = <3072000 25804800>; 408 }; 409 410 cpu4_opp5: opp-1171200000 { 411 opp-hz = /bits/ 64 <1171200000>; 412 opp-peak-kBps = <3072000 31948800>; 413 }; 414 415 cpu4_opp6: opp-1286400000 { 416 opp-hz = /bits/ 64 <1286400000>; 417 opp-peak-kBps = <4068000 31948800>; 418 }; 419 420 cpu4_opp7: opp-1401600000 { 421 opp-hz = /bits/ 64 <1401600000>; 422 opp-peak-kBps = <4068000 31948800>; 423 }; 424 425 cpu4_opp8: opp-1497600000 { 426 opp-hz = /bits/ 64 <1497600000>; 427 opp-peak-kBps = <4068000 40550400>; 428 }; 429 430 cpu4_opp9: opp-1612800000 { 431 opp-hz = /bits/ 64 <1612800000>; 432 opp-peak-kBps = <4068000 40550400>; 433 }; 434 435 cpu4_opp10: opp-1708800000 { 436 opp-hz = /bits/ 64 <1708800000>; 437 opp-peak-kBps = <4068000 43008000>; 438 }; 439 440 cpu4_opp11: opp-1804800000 { 441 opp-hz = /bits/ 64 <1804800000>; 442 opp-peak-kBps = <6220000 43008000>; 443 }; 444 445 cpu4_opp12: opp-1920000000 { 446 opp-hz = /bits/ 64 <1920000000>; 447 opp-peak-kBps = <6220000 49152000>; 448 }; 449 450 cpu4_opp13: opp-2016000000 { 451 opp-hz = /bits/ 64 <2016000000>; 452 opp-peak-kBps = <7216000 49152000>; 453 }; 454 455 cpu4_opp14: opp-2131200000 { 456 opp-hz = /bits/ 64 <2131200000>; 457 opp-peak-kBps = <8368000 49152000>; 458 }; 459 460 cpu4_opp15: opp-2227200000 { 461 opp-hz = /bits/ 64 <2227200000>; 462 opp-peak-kBps = <8368000 51609600>; 463 }; 464 465 cpu4_opp16: opp-2323200000 { 466 opp-hz = /bits/ 64 <2323200000>; 467 opp-peak-kBps = <8368000 51609600>; 468 }; 469 470 cpu4_opp17: opp-2419200000 { 471 opp-hz = /bits/ 64 <2419200000>; 472 opp-peak-kBps = <8368000 51609600>; 473 }; 474 }; 475 476 cpu7_opp_table: opp-table-cpu7 { 477 compatible = "operating-points-v2"; 478 opp-shared; 479 480 cpu7_opp1: opp-825600000 { 481 opp-hz = /bits/ 64 <825600000>; 482 opp-peak-kBps = <2188000 19660800>; 483 }; 484 485 cpu7_opp2: opp-940800000 { 486 opp-hz = /bits/ 64 <940800000>; 487 opp-peak-kBps = <2188000 22732800>; 488 }; 489 490 cpu7_opp3: opp-1056000000 { 491 opp-hz = /bits/ 64 <1056000000>; 492 opp-peak-kBps = <3072000 25804800>; 493 }; 494 495 cpu7_opp4: opp-1171200000 { 496 opp-hz = /bits/ 64 <1171200000>; 497 opp-peak-kBps = <3072000 31948800>; 498 }; 499 500 cpu7_opp5: opp-1286400000 { 501 opp-hz = /bits/ 64 <1286400000>; 502 opp-peak-kBps = <4068000 31948800>; 503 }; 504 505 cpu7_opp6: opp-1401600000 { 506 opp-hz = /bits/ 64 <1401600000>; 507 opp-peak-kBps = <4068000 31948800>; 508 }; 509 510 cpu7_opp7: opp-1497600000 { 511 opp-hz = /bits/ 64 <1497600000>; 512 opp-peak-kBps = <4068000 40550400>; 513 }; 514 515 cpu7_opp8: opp-1612800000 { 516 opp-hz = /bits/ 64 <1612800000>; 517 opp-peak-kBps = <4068000 40550400>; 518 }; 519 520 cpu7_opp9: opp-1708800000 { 521 opp-hz = /bits/ 64 <1708800000>; 522 opp-peak-kBps = <4068000 43008000>; 523 }; 524 525 cpu7_opp10: opp-1804800000 { 526 opp-hz = /bits/ 64 <1804800000>; 527 opp-peak-kBps = <6220000 43008000>; 528 }; 529 530 cpu7_opp11: opp-1920000000 { 531 opp-hz = /bits/ 64 <1920000000>; 532 opp-peak-kBps = <6220000 49152000>; 533 }; 534 535 cpu7_opp12: opp-2016000000 { 536 opp-hz = /bits/ 64 <2016000000>; 537 opp-peak-kBps = <7216000 49152000>; 538 }; 539 540 cpu7_opp13: opp-2131200000 { 541 opp-hz = /bits/ 64 <2131200000>; 542 opp-peak-kBps = <8368000 49152000>; 543 }; 544 545 cpu7_opp14: opp-2227200000 { 546 opp-hz = /bits/ 64 <2227200000>; 547 opp-peak-kBps = <8368000 51609600>; 548 }; 549 550 cpu7_opp15: opp-2323200000 { 551 opp-hz = /bits/ 64 <2323200000>; 552 opp-peak-kBps = <8368000 51609600>; 553 }; 554 555 cpu7_opp16: opp-2419200000 { 556 opp-hz = /bits/ 64 <2419200000>; 557 opp-peak-kBps = <8368000 51609600>; 558 }; 559 560 cpu7_opp17: opp-2534400000 { 561 opp-hz = /bits/ 64 <2534400000>; 562 opp-peak-kBps = <8368000 51609600>; 563 }; 564 565 cpu7_opp18: opp-2649600000 { 566 opp-hz = /bits/ 64 <2649600000>; 567 opp-peak-kBps = <8368000 51609600>; 568 }; 569 570 cpu7_opp19: opp-2745600000 { 571 opp-hz = /bits/ 64 <2745600000>; 572 opp-peak-kBps = <8368000 51609600>; 573 }; 574 575 cpu7_opp20: opp-2841600000 { 576 opp-hz = /bits/ 64 <2841600000>; 577 opp-peak-kBps = <8368000 51609600>; 578 }; 579 }; 580 581 firmware { 582 scm: scm { 583 compatible = "qcom,scm-sm8150", "qcom,scm"; 584 #reset-cells = <1>; 585 }; 586 }; 587 588 memory@80000000 { 589 device_type = "memory"; 590 /* We expect the bootloader to fill in the size */ 591 reg = <0x0 0x80000000 0x0 0x0>; 592 }; 593 594 pmu { 595 compatible = "arm,armv8-pmuv3"; 596 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 597 }; 598 599 psci { 600 compatible = "arm,psci-1.0"; 601 method = "smc"; 602 603 CPU_PD0: cpu0 { 604 #power-domain-cells = <0>; 605 power-domains = <&CLUSTER_PD>; 606 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 607 }; 608 609 CPU_PD1: cpu1 { 610 #power-domain-cells = <0>; 611 power-domains = <&CLUSTER_PD>; 612 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 613 }; 614 615 CPU_PD2: cpu2 { 616 #power-domain-cells = <0>; 617 power-domains = <&CLUSTER_PD>; 618 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 619 }; 620 621 CPU_PD3: cpu3 { 622 #power-domain-cells = <0>; 623 power-domains = <&CLUSTER_PD>; 624 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 625 }; 626 627 CPU_PD4: cpu4 { 628 #power-domain-cells = <0>; 629 power-domains = <&CLUSTER_PD>; 630 domain-idle-states = <&BIG_CPU_SLEEP_0>; 631 }; 632 633 CPU_PD5: cpu5 { 634 #power-domain-cells = <0>; 635 power-domains = <&CLUSTER_PD>; 636 domain-idle-states = <&BIG_CPU_SLEEP_0>; 637 }; 638 639 CPU_PD6: cpu6 { 640 #power-domain-cells = <0>; 641 power-domains = <&CLUSTER_PD>; 642 domain-idle-states = <&BIG_CPU_SLEEP_0>; 643 }; 644 645 CPU_PD7: cpu7 { 646 #power-domain-cells = <0>; 647 power-domains = <&CLUSTER_PD>; 648 domain-idle-states = <&BIG_CPU_SLEEP_0>; 649 }; 650 651 CLUSTER_PD: cpu-cluster0 { 652 #power-domain-cells = <0>; 653 domain-idle-states = <&CLUSTER_SLEEP_0>; 654 }; 655 }; 656 657 reserved-memory { 658 #address-cells = <2>; 659 #size-cells = <2>; 660 ranges; 661 662 hyp_mem: memory@85700000 { 663 reg = <0x0 0x85700000 0x0 0x600000>; 664 no-map; 665 }; 666 667 xbl_mem: memory@85d00000 { 668 reg = <0x0 0x85d00000 0x0 0x140000>; 669 no-map; 670 }; 671 672 aop_mem: memory@85f00000 { 673 reg = <0x0 0x85f00000 0x0 0x20000>; 674 no-map; 675 }; 676 677 aop_cmd_db: memory@85f20000 { 678 compatible = "qcom,cmd-db"; 679 reg = <0x0 0x85f20000 0x0 0x20000>; 680 no-map; 681 }; 682 683 smem_mem: memory@86000000 { 684 reg = <0x0 0x86000000 0x0 0x200000>; 685 no-map; 686 }; 687 688 tz_mem: memory@86200000 { 689 reg = <0x0 0x86200000 0x0 0x3900000>; 690 no-map; 691 }; 692 693 rmtfs_mem: memory@89b00000 { 694 compatible = "qcom,rmtfs-mem"; 695 reg = <0x0 0x89b00000 0x0 0x200000>; 696 no-map; 697 698 qcom,client-id = <1>; 699 qcom,vmid = <15>; 700 }; 701 702 camera_mem: memory@8b700000 { 703 reg = <0x0 0x8b700000 0x0 0x500000>; 704 no-map; 705 }; 706 707 wlan_mem: memory@8bc00000 { 708 reg = <0x0 0x8bc00000 0x0 0x180000>; 709 no-map; 710 }; 711 712 npu_mem: memory@8bd80000 { 713 reg = <0x0 0x8bd80000 0x0 0x80000>; 714 no-map; 715 }; 716 717 adsp_mem: memory@8be00000 { 718 reg = <0x0 0x8be00000 0x0 0x1a00000>; 719 no-map; 720 }; 721 722 mpss_mem: memory@8d800000 { 723 reg = <0x0 0x8d800000 0x0 0x9600000>; 724 no-map; 725 }; 726 727 venus_mem: memory@96e00000 { 728 reg = <0x0 0x96e00000 0x0 0x500000>; 729 no-map; 730 }; 731 732 slpi_mem: memory@97300000 { 733 reg = <0x0 0x97300000 0x0 0x1400000>; 734 no-map; 735 }; 736 737 ipa_fw_mem: memory@98700000 { 738 reg = <0x0 0x98700000 0x0 0x10000>; 739 no-map; 740 }; 741 742 ipa_gsi_mem: memory@98710000 { 743 reg = <0x0 0x98710000 0x0 0x5000>; 744 no-map; 745 }; 746 747 gpu_mem: memory@98715000 { 748 reg = <0x0 0x98715000 0x0 0x2000>; 749 no-map; 750 }; 751 752 spss_mem: memory@98800000 { 753 reg = <0x0 0x98800000 0x0 0x100000>; 754 no-map; 755 }; 756 757 cdsp_mem: memory@98900000 { 758 reg = <0x0 0x98900000 0x0 0x1400000>; 759 no-map; 760 }; 761 762 qseecom_mem: memory@9e400000 { 763 reg = <0x0 0x9e400000 0x0 0x1400000>; 764 no-map; 765 }; 766 }; 767 768 smem { 769 compatible = "qcom,smem"; 770 memory-region = <&smem_mem>; 771 hwlocks = <&tcsr_mutex 3>; 772 }; 773 774 smp2p-cdsp { 775 compatible = "qcom,smp2p"; 776 qcom,smem = <94>, <432>; 777 778 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 779 780 mboxes = <&apss_shared 6>; 781 782 qcom,local-pid = <0>; 783 qcom,remote-pid = <5>; 784 785 cdsp_smp2p_out: master-kernel { 786 qcom,entry-name = "master-kernel"; 787 #qcom,smem-state-cells = <1>; 788 }; 789 790 cdsp_smp2p_in: slave-kernel { 791 qcom,entry-name = "slave-kernel"; 792 793 interrupt-controller; 794 #interrupt-cells = <2>; 795 }; 796 }; 797 798 smp2p-lpass { 799 compatible = "qcom,smp2p"; 800 qcom,smem = <443>, <429>; 801 802 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 803 804 mboxes = <&apss_shared 10>; 805 806 qcom,local-pid = <0>; 807 qcom,remote-pid = <2>; 808 809 adsp_smp2p_out: master-kernel { 810 qcom,entry-name = "master-kernel"; 811 #qcom,smem-state-cells = <1>; 812 }; 813 814 adsp_smp2p_in: slave-kernel { 815 qcom,entry-name = "slave-kernel"; 816 817 interrupt-controller; 818 #interrupt-cells = <2>; 819 }; 820 }; 821 822 smp2p-mpss { 823 compatible = "qcom,smp2p"; 824 qcom,smem = <435>, <428>; 825 826 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 827 828 mboxes = <&apss_shared 14>; 829 830 qcom,local-pid = <0>; 831 qcom,remote-pid = <1>; 832 833 modem_smp2p_out: master-kernel { 834 qcom,entry-name = "master-kernel"; 835 #qcom,smem-state-cells = <1>; 836 }; 837 838 modem_smp2p_in: slave-kernel { 839 qcom,entry-name = "slave-kernel"; 840 841 interrupt-controller; 842 #interrupt-cells = <2>; 843 }; 844 }; 845 846 smp2p-slpi { 847 compatible = "qcom,smp2p"; 848 qcom,smem = <481>, <430>; 849 850 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 851 852 mboxes = <&apss_shared 26>; 853 854 qcom,local-pid = <0>; 855 qcom,remote-pid = <3>; 856 857 slpi_smp2p_out: master-kernel { 858 qcom,entry-name = "master-kernel"; 859 #qcom,smem-state-cells = <1>; 860 }; 861 862 slpi_smp2p_in: slave-kernel { 863 qcom,entry-name = "slave-kernel"; 864 865 interrupt-controller; 866 #interrupt-cells = <2>; 867 }; 868 }; 869 870 soc: soc@0 { 871 #address-cells = <2>; 872 #size-cells = <2>; 873 ranges = <0 0 0 0 0x10 0>; 874 dma-ranges = <0 0 0 0 0x10 0>; 875 compatible = "simple-bus"; 876 877 gcc: clock-controller@100000 { 878 compatible = "qcom,gcc-sm8150"; 879 reg = <0x0 0x00100000 0x0 0x1f0000>; 880 #clock-cells = <1>; 881 #reset-cells = <1>; 882 #power-domain-cells = <1>; 883 clock-names = "bi_tcxo", 884 "sleep_clk"; 885 clocks = <&rpmhcc RPMH_CXO_CLK>, 886 <&sleep_clk>; 887 }; 888 889 gpi_dma0: dma-controller@800000 { 890 compatible = "qcom,sm8150-gpi-dma"; 891 reg = <0 0x800000 0 0x60000>; 892 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 905 dma-channels = <13>; 906 dma-channel-mask = <0xfa>; 907 iommus = <&apps_smmu 0x00d6 0x0>; 908 #dma-cells = <3>; 909 status = "disabled"; 910 }; 911 912 ethernet: ethernet@20000 { 913 compatible = "qcom,sm8150-ethqos"; 914 reg = <0x0 0x00020000 0x0 0x10000>, 915 <0x0 0x00036000 0x0 0x100>; 916 reg-names = "stmmaceth", "rgmii"; 917 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 918 clocks = <&gcc GCC_EMAC_AXI_CLK>, 919 <&gcc GCC_EMAC_SLV_AHB_CLK>, 920 <&gcc GCC_EMAC_PTP_CLK>, 921 <&gcc GCC_EMAC_RGMII_CLK>; 922 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 924 interrupt-names = "macirq", "eth_lpi"; 925 926 power-domains = <&gcc EMAC_GDSC>; 927 resets = <&gcc GCC_EMAC_BCR>; 928 929 iommus = <&apps_smmu 0x3C0 0x0>; 930 931 snps,tso; 932 rx-fifo-depth = <4096>; 933 tx-fifo-depth = <4096>; 934 935 status = "disabled"; 936 }; 937 938 939 qupv3_id_0: geniqup@8c0000 { 940 compatible = "qcom,geni-se-qup"; 941 reg = <0x0 0x008c0000 0x0 0x6000>; 942 clock-names = "m-ahb", "s-ahb"; 943 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 944 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 945 iommus = <&apps_smmu 0xc3 0x0>; 946 #address-cells = <2>; 947 #size-cells = <2>; 948 ranges; 949 status = "disabled"; 950 951 i2c0: i2c@880000 { 952 compatible = "qcom,geni-i2c"; 953 reg = <0 0x00880000 0 0x4000>; 954 clock-names = "se"; 955 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 956 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 957 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 958 dma-names = "tx", "rx"; 959 pinctrl-names = "default"; 960 pinctrl-0 = <&qup_i2c0_default>; 961 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 status = "disabled"; 965 }; 966 967 spi0: spi@880000 { 968 compatible = "qcom,geni-spi"; 969 reg = <0 0x880000 0 0x4000>; 970 reg-names = "se"; 971 clock-names = "se"; 972 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 973 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 974 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 975 dma-names = "tx", "rx"; 976 pinctrl-names = "default"; 977 pinctrl-0 = <&qup_spi0_default>; 978 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 979 spi-max-frequency = <50000000>; 980 #address-cells = <1>; 981 #size-cells = <0>; 982 status = "disabled"; 983 }; 984 985 i2c1: i2c@884000 { 986 compatible = "qcom,geni-i2c"; 987 reg = <0 0x00884000 0 0x4000>; 988 clock-names = "se"; 989 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 990 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 991 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 992 dma-names = "tx", "rx"; 993 pinctrl-names = "default"; 994 pinctrl-0 = <&qup_i2c1_default>; 995 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 996 #address-cells = <1>; 997 #size-cells = <0>; 998 status = "disabled"; 999 }; 1000 1001 spi1: spi@884000 { 1002 compatible = "qcom,geni-spi"; 1003 reg = <0 0x884000 0 0x4000>; 1004 reg-names = "se"; 1005 clock-names = "se"; 1006 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1007 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1008 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1009 dma-names = "tx", "rx"; 1010 pinctrl-names = "default"; 1011 pinctrl-0 = <&qup_spi1_default>; 1012 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1013 spi-max-frequency = <50000000>; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 status = "disabled"; 1017 }; 1018 1019 i2c2: i2c@888000 { 1020 compatible = "qcom,geni-i2c"; 1021 reg = <0 0x00888000 0 0x4000>; 1022 clock-names = "se"; 1023 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1024 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1025 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1026 dma-names = "tx", "rx"; 1027 pinctrl-names = "default"; 1028 pinctrl-0 = <&qup_i2c2_default>; 1029 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 status = "disabled"; 1033 }; 1034 1035 spi2: spi@888000 { 1036 compatible = "qcom,geni-spi"; 1037 reg = <0 0x888000 0 0x4000>; 1038 reg-names = "se"; 1039 clock-names = "se"; 1040 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1041 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1042 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1043 dma-names = "tx", "rx"; 1044 pinctrl-names = "default"; 1045 pinctrl-0 = <&qup_spi2_default>; 1046 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1047 spi-max-frequency = <50000000>; 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 status = "disabled"; 1051 }; 1052 1053 i2c3: i2c@88c000 { 1054 compatible = "qcom,geni-i2c"; 1055 reg = <0 0x0088c000 0 0x4000>; 1056 clock-names = "se"; 1057 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1058 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1059 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1060 dma-names = "tx", "rx"; 1061 pinctrl-names = "default"; 1062 pinctrl-0 = <&qup_i2c3_default>; 1063 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 status = "disabled"; 1067 }; 1068 1069 spi3: spi@88c000 { 1070 compatible = "qcom,geni-spi"; 1071 reg = <0 0x88c000 0 0x4000>; 1072 reg-names = "se"; 1073 clock-names = "se"; 1074 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1075 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1076 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1077 dma-names = "tx", "rx"; 1078 pinctrl-names = "default"; 1079 pinctrl-0 = <&qup_spi3_default>; 1080 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1081 spi-max-frequency = <50000000>; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 status = "disabled"; 1085 }; 1086 1087 i2c4: i2c@890000 { 1088 compatible = "qcom,geni-i2c"; 1089 reg = <0 0x00890000 0 0x4000>; 1090 clock-names = "se"; 1091 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1092 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1093 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1094 dma-names = "tx", "rx"; 1095 pinctrl-names = "default"; 1096 pinctrl-0 = <&qup_i2c4_default>; 1097 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 status = "disabled"; 1101 }; 1102 1103 spi4: spi@890000 { 1104 compatible = "qcom,geni-spi"; 1105 reg = <0 0x890000 0 0x4000>; 1106 reg-names = "se"; 1107 clock-names = "se"; 1108 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1109 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1110 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1111 dma-names = "tx", "rx"; 1112 pinctrl-names = "default"; 1113 pinctrl-0 = <&qup_spi4_default>; 1114 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1115 spi-max-frequency = <50000000>; 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 status = "disabled"; 1119 }; 1120 1121 i2c5: i2c@894000 { 1122 compatible = "qcom,geni-i2c"; 1123 reg = <0 0x00894000 0 0x4000>; 1124 clock-names = "se"; 1125 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1126 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1127 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1128 dma-names = "tx", "rx"; 1129 pinctrl-names = "default"; 1130 pinctrl-0 = <&qup_i2c5_default>; 1131 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 status = "disabled"; 1135 }; 1136 1137 spi5: spi@894000 { 1138 compatible = "qcom,geni-spi"; 1139 reg = <0 0x894000 0 0x4000>; 1140 reg-names = "se"; 1141 clock-names = "se"; 1142 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1143 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1144 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1145 dma-names = "tx", "rx"; 1146 pinctrl-names = "default"; 1147 pinctrl-0 = <&qup_spi5_default>; 1148 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1149 spi-max-frequency = <50000000>; 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 status = "disabled"; 1153 }; 1154 1155 i2c6: i2c@898000 { 1156 compatible = "qcom,geni-i2c"; 1157 reg = <0 0x00898000 0 0x4000>; 1158 clock-names = "se"; 1159 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1160 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1161 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1162 dma-names = "tx", "rx"; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&qup_i2c6_default>; 1165 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 status = "disabled"; 1169 }; 1170 1171 spi6: spi@898000 { 1172 compatible = "qcom,geni-spi"; 1173 reg = <0 0x898000 0 0x4000>; 1174 reg-names = "se"; 1175 clock-names = "se"; 1176 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1177 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1178 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1179 dma-names = "tx", "rx"; 1180 pinctrl-names = "default"; 1181 pinctrl-0 = <&qup_spi6_default>; 1182 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1183 spi-max-frequency = <50000000>; 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 status = "disabled"; 1187 }; 1188 1189 i2c7: i2c@89c000 { 1190 compatible = "qcom,geni-i2c"; 1191 reg = <0 0x0089c000 0 0x4000>; 1192 clock-names = "se"; 1193 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1194 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1195 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1196 dma-names = "tx", "rx"; 1197 pinctrl-names = "default"; 1198 pinctrl-0 = <&qup_i2c7_default>; 1199 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 status = "disabled"; 1203 }; 1204 1205 spi7: spi@89c000 { 1206 compatible = "qcom,geni-spi"; 1207 reg = <0 0x89c000 0 0x4000>; 1208 reg-names = "se"; 1209 clock-names = "se"; 1210 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1211 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1212 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1213 dma-names = "tx", "rx"; 1214 pinctrl-names = "default"; 1215 pinctrl-0 = <&qup_spi7_default>; 1216 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1217 spi-max-frequency = <50000000>; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 status = "disabled"; 1221 }; 1222 }; 1223 1224 gpi_dma1: dma-controller@a00000 { 1225 compatible = "qcom,sm8150-gpi-dma"; 1226 reg = <0 0xa00000 0 0x60000>; 1227 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1240 dma-channels = <13>; 1241 dma-channel-mask = <0xfa>; 1242 iommus = <&apps_smmu 0x0616 0x0>; 1243 #dma-cells = <3>; 1244 status = "disabled"; 1245 }; 1246 1247 qupv3_id_1: geniqup@ac0000 { 1248 compatible = "qcom,geni-se-qup"; 1249 reg = <0x0 0x00ac0000 0x0 0x6000>; 1250 clock-names = "m-ahb", "s-ahb"; 1251 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1252 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1253 iommus = <&apps_smmu 0x603 0x0>; 1254 #address-cells = <2>; 1255 #size-cells = <2>; 1256 ranges; 1257 status = "disabled"; 1258 1259 i2c8: i2c@a80000 { 1260 compatible = "qcom,geni-i2c"; 1261 reg = <0 0x00a80000 0 0x4000>; 1262 clock-names = "se"; 1263 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1264 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1265 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1266 dma-names = "tx", "rx"; 1267 pinctrl-names = "default"; 1268 pinctrl-0 = <&qup_i2c8_default>; 1269 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1270 #address-cells = <1>; 1271 #size-cells = <0>; 1272 status = "disabled"; 1273 }; 1274 1275 spi8: spi@a80000 { 1276 compatible = "qcom,geni-spi"; 1277 reg = <0 0xa80000 0 0x4000>; 1278 reg-names = "se"; 1279 clock-names = "se"; 1280 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1281 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1282 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1283 dma-names = "tx", "rx"; 1284 pinctrl-names = "default"; 1285 pinctrl-0 = <&qup_spi8_default>; 1286 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1287 spi-max-frequency = <50000000>; 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 status = "disabled"; 1291 }; 1292 1293 i2c9: i2c@a84000 { 1294 compatible = "qcom,geni-i2c"; 1295 reg = <0 0x00a84000 0 0x4000>; 1296 clock-names = "se"; 1297 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1298 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1299 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1300 dma-names = "tx", "rx"; 1301 pinctrl-names = "default"; 1302 pinctrl-0 = <&qup_i2c9_default>; 1303 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 status = "disabled"; 1307 }; 1308 1309 spi9: spi@a84000 { 1310 compatible = "qcom,geni-spi"; 1311 reg = <0 0xa84000 0 0x4000>; 1312 reg-names = "se"; 1313 clock-names = "se"; 1314 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1315 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1316 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1317 dma-names = "tx", "rx"; 1318 pinctrl-names = "default"; 1319 pinctrl-0 = <&qup_spi9_default>; 1320 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1321 spi-max-frequency = <50000000>; 1322 #address-cells = <1>; 1323 #size-cells = <0>; 1324 status = "disabled"; 1325 }; 1326 1327 i2c10: i2c@a88000 { 1328 compatible = "qcom,geni-i2c"; 1329 reg = <0 0x00a88000 0 0x4000>; 1330 clock-names = "se"; 1331 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1332 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1333 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1334 dma-names = "tx", "rx"; 1335 pinctrl-names = "default"; 1336 pinctrl-0 = <&qup_i2c10_default>; 1337 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1338 #address-cells = <1>; 1339 #size-cells = <0>; 1340 status = "disabled"; 1341 }; 1342 1343 spi10: spi@a88000 { 1344 compatible = "qcom,geni-spi"; 1345 reg = <0 0xa88000 0 0x4000>; 1346 reg-names = "se"; 1347 clock-names = "se"; 1348 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1349 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1350 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1351 dma-names = "tx", "rx"; 1352 pinctrl-names = "default"; 1353 pinctrl-0 = <&qup_spi10_default>; 1354 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1355 spi-max-frequency = <50000000>; 1356 #address-cells = <1>; 1357 #size-cells = <0>; 1358 status = "disabled"; 1359 }; 1360 1361 i2c11: i2c@a8c000 { 1362 compatible = "qcom,geni-i2c"; 1363 reg = <0 0x00a8c000 0 0x4000>; 1364 clock-names = "se"; 1365 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1366 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1367 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1368 dma-names = "tx", "rx"; 1369 pinctrl-names = "default"; 1370 pinctrl-0 = <&qup_i2c11_default>; 1371 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 status = "disabled"; 1375 }; 1376 1377 spi11: spi@a8c000 { 1378 compatible = "qcom,geni-spi"; 1379 reg = <0 0xa8c000 0 0x4000>; 1380 reg-names = "se"; 1381 clock-names = "se"; 1382 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1383 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1384 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1385 dma-names = "tx", "rx"; 1386 pinctrl-names = "default"; 1387 pinctrl-0 = <&qup_spi11_default>; 1388 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1389 spi-max-frequency = <50000000>; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 status = "disabled"; 1393 }; 1394 1395 uart2: serial@a90000 { 1396 compatible = "qcom,geni-debug-uart"; 1397 reg = <0x0 0x00a90000 0x0 0x4000>; 1398 clock-names = "se"; 1399 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1400 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1401 status = "disabled"; 1402 }; 1403 1404 i2c12: i2c@a90000 { 1405 compatible = "qcom,geni-i2c"; 1406 reg = <0 0x00a90000 0 0x4000>; 1407 clock-names = "se"; 1408 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1409 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1410 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1411 dma-names = "tx", "rx"; 1412 pinctrl-names = "default"; 1413 pinctrl-0 = <&qup_i2c12_default>; 1414 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1415 #address-cells = <1>; 1416 #size-cells = <0>; 1417 status = "disabled"; 1418 }; 1419 1420 spi12: spi@a90000 { 1421 compatible = "qcom,geni-spi"; 1422 reg = <0 0xa90000 0 0x4000>; 1423 reg-names = "se"; 1424 clock-names = "se"; 1425 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1426 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1427 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1428 dma-names = "tx", "rx"; 1429 pinctrl-names = "default"; 1430 pinctrl-0 = <&qup_spi12_default>; 1431 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1432 spi-max-frequency = <50000000>; 1433 #address-cells = <1>; 1434 #size-cells = <0>; 1435 status = "disabled"; 1436 }; 1437 1438 i2c16: i2c@94000 { 1439 compatible = "qcom,geni-i2c"; 1440 reg = <0 0x0094000 0 0x4000>; 1441 clock-names = "se"; 1442 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1443 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1444 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1445 dma-names = "tx", "rx"; 1446 pinctrl-names = "default"; 1447 pinctrl-0 = <&qup_i2c16_default>; 1448 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 status = "disabled"; 1452 }; 1453 1454 spi16: spi@a94000 { 1455 compatible = "qcom,geni-spi"; 1456 reg = <0 0xa94000 0 0x4000>; 1457 reg-names = "se"; 1458 clock-names = "se"; 1459 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1460 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1461 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1462 dma-names = "tx", "rx"; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&qup_spi16_default>; 1465 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1466 spi-max-frequency = <50000000>; 1467 #address-cells = <1>; 1468 #size-cells = <0>; 1469 status = "disabled"; 1470 }; 1471 }; 1472 1473 gpi_dma2: dma-controller@c00000 { 1474 compatible = "qcom,sm8150-gpi-dma"; 1475 reg = <0 0xc00000 0 0x60000>; 1476 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 1489 dma-channels = <13>; 1490 dma-channel-mask = <0xfa>; 1491 iommus = <&apps_smmu 0x07b6 0x0>; 1492 #dma-cells = <3>; 1493 status = "disabled"; 1494 }; 1495 1496 qupv3_id_2: geniqup@cc0000 { 1497 compatible = "qcom,geni-se-qup"; 1498 reg = <0x0 0x00cc0000 0x0 0x6000>; 1499 1500 clock-names = "m-ahb", "s-ahb"; 1501 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1502 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1503 iommus = <&apps_smmu 0x7a3 0x0>; 1504 #address-cells = <2>; 1505 #size-cells = <2>; 1506 ranges; 1507 status = "disabled"; 1508 1509 i2c17: i2c@c80000 { 1510 compatible = "qcom,geni-i2c"; 1511 reg = <0 0x00c80000 0 0x4000>; 1512 clock-names = "se"; 1513 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1514 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1515 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1516 dma-names = "tx", "rx"; 1517 pinctrl-names = "default"; 1518 pinctrl-0 = <&qup_i2c17_default>; 1519 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1520 #address-cells = <1>; 1521 #size-cells = <0>; 1522 status = "disabled"; 1523 }; 1524 1525 spi17: spi@c80000 { 1526 compatible = "qcom,geni-spi"; 1527 reg = <0 0xc80000 0 0x4000>; 1528 reg-names = "se"; 1529 clock-names = "se"; 1530 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1531 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1532 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1533 dma-names = "tx", "rx"; 1534 pinctrl-names = "default"; 1535 pinctrl-0 = <&qup_spi17_default>; 1536 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1537 spi-max-frequency = <50000000>; 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 status = "disabled"; 1541 }; 1542 1543 i2c18: i2c@c84000 { 1544 compatible = "qcom,geni-i2c"; 1545 reg = <0 0x00c84000 0 0x4000>; 1546 clock-names = "se"; 1547 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1548 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1549 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1550 dma-names = "tx", "rx"; 1551 pinctrl-names = "default"; 1552 pinctrl-0 = <&qup_i2c18_default>; 1553 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1554 #address-cells = <1>; 1555 #size-cells = <0>; 1556 status = "disabled"; 1557 }; 1558 1559 spi18: spi@c84000 { 1560 compatible = "qcom,geni-spi"; 1561 reg = <0 0xc84000 0 0x4000>; 1562 reg-names = "se"; 1563 clock-names = "se"; 1564 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1565 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1566 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1567 dma-names = "tx", "rx"; 1568 pinctrl-names = "default"; 1569 pinctrl-0 = <&qup_spi18_default>; 1570 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1571 spi-max-frequency = <50000000>; 1572 #address-cells = <1>; 1573 #size-cells = <0>; 1574 status = "disabled"; 1575 }; 1576 1577 i2c19: i2c@c88000 { 1578 compatible = "qcom,geni-i2c"; 1579 reg = <0 0x00c88000 0 0x4000>; 1580 clock-names = "se"; 1581 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1582 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1583 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1584 dma-names = "tx", "rx"; 1585 pinctrl-names = "default"; 1586 pinctrl-0 = <&qup_i2c19_default>; 1587 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1588 #address-cells = <1>; 1589 #size-cells = <0>; 1590 status = "disabled"; 1591 }; 1592 1593 spi19: spi@c88000 { 1594 compatible = "qcom,geni-spi"; 1595 reg = <0 0xc88000 0 0x4000>; 1596 reg-names = "se"; 1597 clock-names = "se"; 1598 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1599 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1600 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1601 dma-names = "tx", "rx"; 1602 pinctrl-names = "default"; 1603 pinctrl-0 = <&qup_spi19_default>; 1604 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1605 spi-max-frequency = <50000000>; 1606 #address-cells = <1>; 1607 #size-cells = <0>; 1608 status = "disabled"; 1609 }; 1610 1611 i2c13: i2c@c8c000 { 1612 compatible = "qcom,geni-i2c"; 1613 reg = <0 0x00c8c000 0 0x4000>; 1614 clock-names = "se"; 1615 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1616 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1617 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1618 dma-names = "tx", "rx"; 1619 pinctrl-names = "default"; 1620 pinctrl-0 = <&qup_i2c13_default>; 1621 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1622 #address-cells = <1>; 1623 #size-cells = <0>; 1624 status = "disabled"; 1625 }; 1626 1627 spi13: spi@c8c000 { 1628 compatible = "qcom,geni-spi"; 1629 reg = <0 0xc8c000 0 0x4000>; 1630 reg-names = "se"; 1631 clock-names = "se"; 1632 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1633 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1634 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1635 dma-names = "tx", "rx"; 1636 pinctrl-names = "default"; 1637 pinctrl-0 = <&qup_spi13_default>; 1638 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1639 spi-max-frequency = <50000000>; 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 status = "disabled"; 1643 }; 1644 1645 i2c14: i2c@c90000 { 1646 compatible = "qcom,geni-i2c"; 1647 reg = <0 0x00c90000 0 0x4000>; 1648 clock-names = "se"; 1649 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1650 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1651 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1652 dma-names = "tx", "rx"; 1653 pinctrl-names = "default"; 1654 pinctrl-0 = <&qup_i2c14_default>; 1655 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1656 #address-cells = <1>; 1657 #size-cells = <0>; 1658 status = "disabled"; 1659 }; 1660 1661 spi14: spi@c90000 { 1662 compatible = "qcom,geni-spi"; 1663 reg = <0 0xc90000 0 0x4000>; 1664 reg-names = "se"; 1665 clock-names = "se"; 1666 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1667 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1668 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1669 dma-names = "tx", "rx"; 1670 pinctrl-names = "default"; 1671 pinctrl-0 = <&qup_spi14_default>; 1672 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1673 spi-max-frequency = <50000000>; 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 status = "disabled"; 1677 }; 1678 1679 i2c15: i2c@c94000 { 1680 compatible = "qcom,geni-i2c"; 1681 reg = <0 0x00c94000 0 0x4000>; 1682 clock-names = "se"; 1683 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1684 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1685 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1686 dma-names = "tx", "rx"; 1687 pinctrl-names = "default"; 1688 pinctrl-0 = <&qup_i2c15_default>; 1689 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 status = "disabled"; 1693 }; 1694 1695 spi15: spi@c94000 { 1696 compatible = "qcom,geni-spi"; 1697 reg = <0 0xc94000 0 0x4000>; 1698 reg-names = "se"; 1699 clock-names = "se"; 1700 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1701 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1702 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1703 dma-names = "tx", "rx"; 1704 pinctrl-names = "default"; 1705 pinctrl-0 = <&qup_spi15_default>; 1706 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1707 spi-max-frequency = <50000000>; 1708 #address-cells = <1>; 1709 #size-cells = <0>; 1710 status = "disabled"; 1711 }; 1712 }; 1713 1714 config_noc: interconnect@1500000 { 1715 compatible = "qcom,sm8150-config-noc"; 1716 reg = <0 0x01500000 0 0x7400>; 1717 #interconnect-cells = <1>; 1718 qcom,bcm-voters = <&apps_bcm_voter>; 1719 }; 1720 1721 system_noc: interconnect@1620000 { 1722 compatible = "qcom,sm8150-system-noc"; 1723 reg = <0 0x01620000 0 0x19400>; 1724 #interconnect-cells = <1>; 1725 qcom,bcm-voters = <&apps_bcm_voter>; 1726 }; 1727 1728 mc_virt: interconnect@163a000 { 1729 compatible = "qcom,sm8150-mc-virt"; 1730 reg = <0 0x0163a000 0 0x1000>; 1731 #interconnect-cells = <1>; 1732 qcom,bcm-voters = <&apps_bcm_voter>; 1733 }; 1734 1735 aggre1_noc: interconnect@16e0000 { 1736 compatible = "qcom,sm8150-aggre1-noc"; 1737 reg = <0 0x016e0000 0 0xd080>; 1738 #interconnect-cells = <1>; 1739 qcom,bcm-voters = <&apps_bcm_voter>; 1740 }; 1741 1742 aggre2_noc: interconnect@1700000 { 1743 compatible = "qcom,sm8150-aggre2-noc"; 1744 reg = <0 0x01700000 0 0x20000>; 1745 #interconnect-cells = <1>; 1746 qcom,bcm-voters = <&apps_bcm_voter>; 1747 }; 1748 1749 compute_noc: interconnect@1720000 { 1750 compatible = "qcom,sm8150-compute-noc"; 1751 reg = <0 0x01720000 0 0x7000>; 1752 #interconnect-cells = <1>; 1753 qcom,bcm-voters = <&apps_bcm_voter>; 1754 }; 1755 1756 mmss_noc: interconnect@1740000 { 1757 compatible = "qcom,sm8150-mmss-noc"; 1758 reg = <0 0x01740000 0 0x1c100>; 1759 #interconnect-cells = <1>; 1760 qcom,bcm-voters = <&apps_bcm_voter>; 1761 }; 1762 1763 system-cache-controller@9200000 { 1764 compatible = "qcom,sm8150-llcc"; 1765 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 1766 reg-names = "llcc_base", "llcc_broadcast_base"; 1767 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1768 }; 1769 1770 pcie0: pci@1c00000 { 1771 compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1772 reg = <0 0x01c00000 0 0x3000>, 1773 <0 0x60000000 0 0xf1d>, 1774 <0 0x60000f20 0 0xa8>, 1775 <0 0x60001000 0 0x1000>, 1776 <0 0x60100000 0 0x100000>; 1777 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1778 device_type = "pci"; 1779 linux,pci-domain = <0>; 1780 bus-range = <0x00 0xff>; 1781 num-lanes = <1>; 1782 1783 #address-cells = <3>; 1784 #size-cells = <2>; 1785 1786 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1787 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1788 1789 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1790 interrupt-names = "msi"; 1791 #interrupt-cells = <1>; 1792 interrupt-map-mask = <0 0 0 0x7>; 1793 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1794 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1795 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1796 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1797 1798 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1799 <&gcc GCC_PCIE_0_AUX_CLK>, 1800 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1801 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1802 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1803 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1804 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1805 clock-names = "pipe", 1806 "aux", 1807 "cfg", 1808 "bus_master", 1809 "bus_slave", 1810 "slave_q2a", 1811 "tbu"; 1812 1813 iommus = <&apps_smmu 0x1d80 0x7f>; 1814 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1815 <0x100 &apps_smmu 0x1d81 0x1>; 1816 1817 resets = <&gcc GCC_PCIE_0_BCR>; 1818 reset-names = "pci"; 1819 1820 power-domains = <&gcc PCIE_0_GDSC>; 1821 1822 phys = <&pcie0_lane>; 1823 phy-names = "pciephy"; 1824 1825 perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1826 enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1827 1828 pinctrl-names = "default"; 1829 pinctrl-0 = <&pcie0_default_state>; 1830 1831 status = "disabled"; 1832 }; 1833 1834 pcie0_phy: phy@1c06000 { 1835 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1836 reg = <0 0x01c06000 0 0x1c0>; 1837 #address-cells = <2>; 1838 #size-cells = <2>; 1839 ranges; 1840 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1841 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1842 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1843 clock-names = "aux", "cfg_ahb", "refgen"; 1844 1845 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1846 reset-names = "phy"; 1847 1848 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1849 assigned-clock-rates = <100000000>; 1850 1851 status = "disabled"; 1852 1853 pcie0_lane: phy@1c06200 { 1854 reg = <0 0x1c06200 0 0x170>, /* tx */ 1855 <0 0x1c06400 0 0x200>, /* rx */ 1856 <0 0x1c06800 0 0x1f0>, /* pcs */ 1857 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1858 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1859 clock-names = "pipe0"; 1860 1861 #phy-cells = <0>; 1862 clock-output-names = "pcie_0_pipe_clk"; 1863 }; 1864 }; 1865 1866 pcie1: pci@1c08000 { 1867 compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1868 reg = <0 0x01c08000 0 0x3000>, 1869 <0 0x40000000 0 0xf1d>, 1870 <0 0x40000f20 0 0xa8>, 1871 <0 0x40001000 0 0x1000>, 1872 <0 0x40100000 0 0x100000>; 1873 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1874 device_type = "pci"; 1875 linux,pci-domain = <1>; 1876 bus-range = <0x00 0xff>; 1877 num-lanes = <2>; 1878 1879 #address-cells = <3>; 1880 #size-cells = <2>; 1881 1882 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1883 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1884 1885 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1886 interrupt-names = "msi"; 1887 #interrupt-cells = <1>; 1888 interrupt-map-mask = <0 0 0 0x7>; 1889 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1890 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1891 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1892 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1893 1894 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1895 <&gcc GCC_PCIE_1_AUX_CLK>, 1896 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1897 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1898 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1899 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1900 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1901 clock-names = "pipe", 1902 "aux", 1903 "cfg", 1904 "bus_master", 1905 "bus_slave", 1906 "slave_q2a", 1907 "tbu"; 1908 1909 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1910 assigned-clock-rates = <19200000>; 1911 1912 iommus = <&apps_smmu 0x1e00 0x7f>; 1913 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1914 <0x100 &apps_smmu 0x1e01 0x1>; 1915 1916 resets = <&gcc GCC_PCIE_1_BCR>; 1917 reset-names = "pci"; 1918 1919 power-domains = <&gcc PCIE_1_GDSC>; 1920 1921 phys = <&pcie1_lane>; 1922 phy-names = "pciephy"; 1923 1924 perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; 1925 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 1926 1927 pinctrl-names = "default"; 1928 pinctrl-0 = <&pcie1_default_state>; 1929 1930 status = "disabled"; 1931 }; 1932 1933 pcie1_phy: phy@1c0e000 { 1934 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 1935 reg = <0 0x01c0e000 0 0x1c0>; 1936 #address-cells = <2>; 1937 #size-cells = <2>; 1938 ranges; 1939 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1940 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1941 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1942 clock-names = "aux", "cfg_ahb", "refgen"; 1943 1944 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1945 reset-names = "phy"; 1946 1947 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1948 assigned-clock-rates = <100000000>; 1949 1950 status = "disabled"; 1951 1952 pcie1_lane: phy@1c0e200 { 1953 reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1954 <0 0x1c0e400 0 0x200>, /* rx0 */ 1955 <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1956 <0 0x1c0e600 0 0x170>, /* tx1 */ 1957 <0 0x1c0e800 0 0x200>, /* rx1 */ 1958 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1959 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1960 clock-names = "pipe0"; 1961 1962 #phy-cells = <0>; 1963 clock-output-names = "pcie_1_pipe_clk"; 1964 }; 1965 }; 1966 1967 ufs_mem_hc: ufshc@1d84000 { 1968 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 1969 "jedec,ufs-2.0"; 1970 reg = <0 0x01d84000 0 0x2500>, 1971 <0 0x01d90000 0 0x8000>; 1972 reg-names = "std", "ice"; 1973 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1974 phys = <&ufs_mem_phy_lanes>; 1975 phy-names = "ufsphy"; 1976 lanes-per-direction = <2>; 1977 #reset-cells = <1>; 1978 resets = <&gcc GCC_UFS_PHY_BCR>; 1979 reset-names = "rst"; 1980 1981 iommus = <&apps_smmu 0x300 0>; 1982 1983 clock-names = 1984 "core_clk", 1985 "bus_aggr_clk", 1986 "iface_clk", 1987 "core_clk_unipro", 1988 "ref_clk", 1989 "tx_lane0_sync_clk", 1990 "rx_lane0_sync_clk", 1991 "rx_lane1_sync_clk", 1992 "ice_core_clk"; 1993 clocks = 1994 <&gcc GCC_UFS_PHY_AXI_CLK>, 1995 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1996 <&gcc GCC_UFS_PHY_AHB_CLK>, 1997 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1998 <&rpmhcc RPMH_CXO_CLK>, 1999 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2000 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2001 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2002 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2003 freq-table-hz = 2004 <37500000 300000000>, 2005 <0 0>, 2006 <0 0>, 2007 <37500000 300000000>, 2008 <0 0>, 2009 <0 0>, 2010 <0 0>, 2011 <0 0>, 2012 <0 300000000>; 2013 2014 status = "disabled"; 2015 }; 2016 2017 ufs_mem_phy: phy@1d87000 { 2018 compatible = "qcom,sm8150-qmp-ufs-phy"; 2019 reg = <0 0x01d87000 0 0x1c0>; 2020 #address-cells = <2>; 2021 #size-cells = <2>; 2022 ranges; 2023 clock-names = "ref", 2024 "ref_aux"; 2025 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2026 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2027 2028 power-domains = <&gcc UFS_PHY_GDSC>; 2029 2030 resets = <&ufs_mem_hc 0>; 2031 reset-names = "ufsphy"; 2032 status = "disabled"; 2033 2034 ufs_mem_phy_lanes: phy@1d87400 { 2035 reg = <0 0x01d87400 0 0x108>, 2036 <0 0x01d87600 0 0x1e0>, 2037 <0 0x01d87c00 0 0x1dc>, 2038 <0 0x01d87800 0 0x108>, 2039 <0 0x01d87a00 0 0x1e0>; 2040 #phy-cells = <0>; 2041 }; 2042 }; 2043 2044 ipa_virt: interconnect@1e00000 { 2045 compatible = "qcom,sm8150-ipa-virt"; 2046 reg = <0 0x01e00000 0 0x1000>; 2047 #interconnect-cells = <1>; 2048 qcom,bcm-voters = <&apps_bcm_voter>; 2049 }; 2050 2051 tcsr_mutex: hwlock@1f40000 { 2052 compatible = "qcom,tcsr-mutex"; 2053 reg = <0x0 0x01f40000 0x0 0x20000>; 2054 #hwlock-cells = <1>; 2055 }; 2056 2057 tcsr_regs_1: syscon@1f60000 { 2058 compatible = "qcom,sm8150-tcsr", "syscon"; 2059 reg = <0x0 0x01f60000 0x0 0x20000>; 2060 }; 2061 2062 remoteproc_slpi: remoteproc@2400000 { 2063 compatible = "qcom,sm8150-slpi-pas"; 2064 reg = <0x0 0x02400000 0x0 0x4040>; 2065 2066 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 2067 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2068 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2069 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2070 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2071 interrupt-names = "wdog", "fatal", "ready", 2072 "handover", "stop-ack"; 2073 2074 clocks = <&rpmhcc RPMH_CXO_CLK>; 2075 clock-names = "xo"; 2076 2077 power-domains = <&rpmhpd 3>, 2078 <&rpmhpd 2>; 2079 power-domain-names = "lcx", "lmx"; 2080 2081 memory-region = <&slpi_mem>; 2082 2083 qcom,qmp = <&aoss_qmp>; 2084 2085 qcom,smem-states = <&slpi_smp2p_out 0>; 2086 qcom,smem-state-names = "stop"; 2087 2088 status = "disabled"; 2089 2090 glink-edge { 2091 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 2092 label = "dsps"; 2093 qcom,remote-pid = <3>; 2094 mboxes = <&apss_shared 24>; 2095 2096 fastrpc { 2097 compatible = "qcom,fastrpc"; 2098 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2099 label = "sdsp"; 2100 qcom,non-secure-domain; 2101 #address-cells = <1>; 2102 #size-cells = <0>; 2103 2104 compute-cb@1 { 2105 compatible = "qcom,fastrpc-compute-cb"; 2106 reg = <1>; 2107 iommus = <&apps_smmu 0x05a1 0x0>; 2108 }; 2109 2110 compute-cb@2 { 2111 compatible = "qcom,fastrpc-compute-cb"; 2112 reg = <2>; 2113 iommus = <&apps_smmu 0x05a2 0x0>; 2114 }; 2115 2116 compute-cb@3 { 2117 compatible = "qcom,fastrpc-compute-cb"; 2118 reg = <3>; 2119 iommus = <&apps_smmu 0x05a3 0x0>; 2120 /* note: shared-cb = <4> in downstream */ 2121 }; 2122 }; 2123 }; 2124 }; 2125 2126 gpu: gpu@2c00000 { 2127 /* 2128 * note: the amd,imageon compatible makes it possible 2129 * to use the drm/msm driver without the display node, 2130 * make sure to remove it when display node is added 2131 */ 2132 compatible = "qcom,adreno-640.1", 2133 "qcom,adreno", 2134 "amd,imageon"; 2135 2136 reg = <0 0x02c00000 0 0x40000>; 2137 reg-names = "kgsl_3d0_reg_memory"; 2138 2139 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2140 2141 iommus = <&adreno_smmu 0 0x401>; 2142 2143 operating-points-v2 = <&gpu_opp_table>; 2144 2145 qcom,gmu = <&gmu>; 2146 2147 status = "disabled"; 2148 2149 zap-shader { 2150 memory-region = <&gpu_mem>; 2151 }; 2152 2153 /* note: downstream checks gpu binning for 675 Mhz */ 2154 gpu_opp_table: opp-table { 2155 compatible = "operating-points-v2"; 2156 2157 opp-675000000 { 2158 opp-hz = /bits/ 64 <675000000>; 2159 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2160 }; 2161 2162 opp-585000000 { 2163 opp-hz = /bits/ 64 <585000000>; 2164 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2165 }; 2166 2167 opp-499200000 { 2168 opp-hz = /bits/ 64 <499200000>; 2169 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2170 }; 2171 2172 opp-427000000 { 2173 opp-hz = /bits/ 64 <427000000>; 2174 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2175 }; 2176 2177 opp-345000000 { 2178 opp-hz = /bits/ 64 <345000000>; 2179 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2180 }; 2181 2182 opp-257000000 { 2183 opp-hz = /bits/ 64 <257000000>; 2184 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2185 }; 2186 }; 2187 }; 2188 2189 gmu: gmu@2c6a000 { 2190 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2191 2192 reg = <0 0x02c6a000 0 0x30000>, 2193 <0 0x0b290000 0 0x10000>, 2194 <0 0x0b490000 0 0x10000>; 2195 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2196 2197 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2198 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2199 interrupt-names = "hfi", "gmu"; 2200 2201 clocks = <&gpucc GPU_CC_AHB_CLK>, 2202 <&gpucc GPU_CC_CX_GMU_CLK>, 2203 <&gpucc GPU_CC_CXO_CLK>, 2204 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2205 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2206 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2207 2208 power-domains = <&gpucc GPU_CX_GDSC>, 2209 <&gpucc GPU_GX_GDSC>; 2210 power-domain-names = "cx", "gx"; 2211 2212 iommus = <&adreno_smmu 5 0x400>; 2213 2214 operating-points-v2 = <&gmu_opp_table>; 2215 2216 status = "disabled"; 2217 2218 gmu_opp_table: opp-table { 2219 compatible = "operating-points-v2"; 2220 2221 opp-200000000 { 2222 opp-hz = /bits/ 64 <200000000>; 2223 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2224 }; 2225 }; 2226 }; 2227 2228 gpucc: clock-controller@2c90000 { 2229 compatible = "qcom,sm8150-gpucc"; 2230 reg = <0 0x02c90000 0 0x9000>; 2231 clocks = <&rpmhcc RPMH_CXO_CLK>, 2232 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2233 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2234 clock-names = "bi_tcxo", 2235 "gcc_gpu_gpll0_clk_src", 2236 "gcc_gpu_gpll0_div_clk_src"; 2237 #clock-cells = <1>; 2238 #reset-cells = <1>; 2239 #power-domain-cells = <1>; 2240 }; 2241 2242 adreno_smmu: iommu@2ca0000 { 2243 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 2244 reg = <0 0x02ca0000 0 0x10000>; 2245 #iommu-cells = <2>; 2246 #global-interrupts = <1>; 2247 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2248 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2249 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2250 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2251 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2252 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2253 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2254 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2255 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2256 clocks = <&gpucc GPU_CC_AHB_CLK>, 2257 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2258 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2259 clock-names = "ahb", "bus", "iface"; 2260 2261 power-domains = <&gpucc GPU_CX_GDSC>; 2262 }; 2263 2264 tlmm: pinctrl@3100000 { 2265 compatible = "qcom,sm8150-pinctrl"; 2266 reg = <0x0 0x03100000 0x0 0x300000>, 2267 <0x0 0x03500000 0x0 0x300000>, 2268 <0x0 0x03900000 0x0 0x300000>, 2269 <0x0 0x03D00000 0x0 0x300000>; 2270 reg-names = "west", "east", "north", "south"; 2271 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2272 gpio-ranges = <&tlmm 0 0 176>; 2273 gpio-controller; 2274 #gpio-cells = <2>; 2275 interrupt-controller; 2276 #interrupt-cells = <2>; 2277 wakeup-parent = <&pdc>; 2278 2279 qup_i2c0_default: qup-i2c0-default { 2280 mux { 2281 pins = "gpio0", "gpio1"; 2282 function = "qup0"; 2283 }; 2284 2285 config { 2286 pins = "gpio0", "gpio1"; 2287 drive-strength = <0x02>; 2288 bias-disable; 2289 }; 2290 }; 2291 2292 qup_spi0_default: qup-spi0-default { 2293 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2294 function = "qup0"; 2295 drive-strength = <6>; 2296 bias-disable; 2297 }; 2298 2299 qup_i2c1_default: qup-i2c1-default { 2300 mux { 2301 pins = "gpio114", "gpio115"; 2302 function = "qup1"; 2303 }; 2304 2305 config { 2306 pins = "gpio114", "gpio115"; 2307 drive-strength = <0x02>; 2308 bias-disable; 2309 }; 2310 }; 2311 2312 qup_spi1_default: qup-spi1-default { 2313 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2314 function = "qup1"; 2315 drive-strength = <6>; 2316 bias-disable; 2317 }; 2318 2319 qup_i2c2_default: qup-i2c2-default { 2320 mux { 2321 pins = "gpio126", "gpio127"; 2322 function = "qup2"; 2323 }; 2324 2325 config { 2326 pins = "gpio126", "gpio127"; 2327 drive-strength = <0x02>; 2328 bias-disable; 2329 }; 2330 }; 2331 2332 qup_spi2_default: qup-spi2-default { 2333 pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2334 function = "qup2"; 2335 drive-strength = <6>; 2336 bias-disable; 2337 }; 2338 2339 qup_i2c3_default: qup-i2c3-default { 2340 mux { 2341 pins = "gpio144", "gpio145"; 2342 function = "qup3"; 2343 }; 2344 2345 config { 2346 pins = "gpio144", "gpio145"; 2347 drive-strength = <0x02>; 2348 bias-disable; 2349 }; 2350 }; 2351 2352 qup_spi3_default: qup-spi3-default { 2353 pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2354 function = "qup3"; 2355 drive-strength = <6>; 2356 bias-disable; 2357 }; 2358 2359 qup_i2c4_default: qup-i2c4-default { 2360 mux { 2361 pins = "gpio51", "gpio52"; 2362 function = "qup4"; 2363 }; 2364 2365 config { 2366 pins = "gpio51", "gpio52"; 2367 drive-strength = <0x02>; 2368 bias-disable; 2369 }; 2370 }; 2371 2372 qup_spi4_default: qup-spi4-default { 2373 pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2374 function = "qup4"; 2375 drive-strength = <6>; 2376 bias-disable; 2377 }; 2378 2379 qup_i2c5_default: qup-i2c5-default { 2380 mux { 2381 pins = "gpio121", "gpio122"; 2382 function = "qup5"; 2383 }; 2384 2385 config { 2386 pins = "gpio121", "gpio122"; 2387 drive-strength = <0x02>; 2388 bias-disable; 2389 }; 2390 }; 2391 2392 qup_spi5_default: qup-spi5-default { 2393 pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2394 function = "qup5"; 2395 drive-strength = <6>; 2396 bias-disable; 2397 }; 2398 2399 qup_i2c6_default: qup-i2c6-default { 2400 mux { 2401 pins = "gpio6", "gpio7"; 2402 function = "qup6"; 2403 }; 2404 2405 config { 2406 pins = "gpio6", "gpio7"; 2407 drive-strength = <0x02>; 2408 bias-disable; 2409 }; 2410 }; 2411 2412 qup_spi6_default: qup-spi6_default { 2413 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2414 function = "qup6"; 2415 drive-strength = <6>; 2416 bias-disable; 2417 }; 2418 2419 qup_i2c7_default: qup-i2c7-default { 2420 mux { 2421 pins = "gpio98", "gpio99"; 2422 function = "qup7"; 2423 }; 2424 2425 config { 2426 pins = "gpio98", "gpio99"; 2427 drive-strength = <0x02>; 2428 bias-disable; 2429 }; 2430 }; 2431 2432 qup_spi7_default: qup-spi7_default { 2433 pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2434 function = "qup7"; 2435 drive-strength = <6>; 2436 bias-disable; 2437 }; 2438 2439 qup_i2c8_default: qup-i2c8-default { 2440 mux { 2441 pins = "gpio88", "gpio89"; 2442 function = "qup8"; 2443 }; 2444 2445 config { 2446 pins = "gpio88", "gpio89"; 2447 drive-strength = <0x02>; 2448 bias-disable; 2449 }; 2450 }; 2451 2452 qup_spi8_default: qup-spi8-default { 2453 pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2454 function = "qup8"; 2455 drive-strength = <6>; 2456 bias-disable; 2457 }; 2458 2459 qup_i2c9_default: qup-i2c9-default { 2460 mux { 2461 pins = "gpio39", "gpio40"; 2462 function = "qup9"; 2463 }; 2464 2465 config { 2466 pins = "gpio39", "gpio40"; 2467 drive-strength = <0x02>; 2468 bias-disable; 2469 }; 2470 }; 2471 2472 qup_spi9_default: qup-spi9-default { 2473 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2474 function = "qup9"; 2475 drive-strength = <6>; 2476 bias-disable; 2477 }; 2478 2479 qup_i2c10_default: qup-i2c10-default { 2480 mux { 2481 pins = "gpio9", "gpio10"; 2482 function = "qup10"; 2483 }; 2484 2485 config { 2486 pins = "gpio9", "gpio10"; 2487 drive-strength = <0x02>; 2488 bias-disable; 2489 }; 2490 }; 2491 2492 qup_spi10_default: qup-spi10-default { 2493 pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2494 function = "qup10"; 2495 drive-strength = <6>; 2496 bias-disable; 2497 }; 2498 2499 qup_i2c11_default: qup-i2c11-default { 2500 mux { 2501 pins = "gpio94", "gpio95"; 2502 function = "qup11"; 2503 }; 2504 2505 config { 2506 pins = "gpio94", "gpio95"; 2507 drive-strength = <0x02>; 2508 bias-disable; 2509 }; 2510 }; 2511 2512 qup_spi11_default: qup-spi11-default { 2513 pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2514 function = "qup11"; 2515 drive-strength = <6>; 2516 bias-disable; 2517 }; 2518 2519 qup_i2c12_default: qup-i2c12-default { 2520 mux { 2521 pins = "gpio83", "gpio84"; 2522 function = "qup12"; 2523 }; 2524 2525 config { 2526 pins = "gpio83", "gpio84"; 2527 drive-strength = <0x02>; 2528 bias-disable; 2529 }; 2530 }; 2531 2532 qup_spi12_default: qup-spi12-default { 2533 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2534 function = "qup12"; 2535 drive-strength = <6>; 2536 bias-disable; 2537 }; 2538 2539 qup_i2c13_default: qup-i2c13-default { 2540 mux { 2541 pins = "gpio43", "gpio44"; 2542 function = "qup13"; 2543 }; 2544 2545 config { 2546 pins = "gpio43", "gpio44"; 2547 drive-strength = <0x02>; 2548 bias-disable; 2549 }; 2550 }; 2551 2552 qup_spi13_default: qup-spi13-default { 2553 pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2554 function = "qup13"; 2555 drive-strength = <6>; 2556 bias-disable; 2557 }; 2558 2559 qup_i2c14_default: qup-i2c14-default { 2560 mux { 2561 pins = "gpio47", "gpio48"; 2562 function = "qup14"; 2563 }; 2564 2565 config { 2566 pins = "gpio47", "gpio48"; 2567 drive-strength = <0x02>; 2568 bias-disable; 2569 }; 2570 }; 2571 2572 qup_spi14_default: qup-spi14-default { 2573 pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2574 function = "qup14"; 2575 drive-strength = <6>; 2576 bias-disable; 2577 }; 2578 2579 qup_i2c15_default: qup-i2c15-default { 2580 mux { 2581 pins = "gpio27", "gpio28"; 2582 function = "qup15"; 2583 }; 2584 2585 config { 2586 pins = "gpio27", "gpio28"; 2587 drive-strength = <0x02>; 2588 bias-disable; 2589 }; 2590 }; 2591 2592 qup_spi15_default: qup-spi15-default { 2593 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2594 function = "qup15"; 2595 drive-strength = <6>; 2596 bias-disable; 2597 }; 2598 2599 qup_i2c16_default: qup-i2c16-default { 2600 mux { 2601 pins = "gpio86", "gpio85"; 2602 function = "qup16"; 2603 }; 2604 2605 config { 2606 pins = "gpio86", "gpio85"; 2607 drive-strength = <0x02>; 2608 bias-disable; 2609 }; 2610 }; 2611 2612 qup_spi16_default: qup-spi16-default { 2613 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2614 function = "qup16"; 2615 drive-strength = <6>; 2616 bias-disable; 2617 }; 2618 2619 qup_i2c17_default: qup-i2c17-default { 2620 mux { 2621 pins = "gpio55", "gpio56"; 2622 function = "qup17"; 2623 }; 2624 2625 config { 2626 pins = "gpio55", "gpio56"; 2627 drive-strength = <0x02>; 2628 bias-disable; 2629 }; 2630 }; 2631 2632 qup_spi17_default: qup-spi17-default { 2633 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2634 function = "qup17"; 2635 drive-strength = <6>; 2636 bias-disable; 2637 }; 2638 2639 qup_i2c18_default: qup-i2c18-default { 2640 mux { 2641 pins = "gpio23", "gpio24"; 2642 function = "qup18"; 2643 }; 2644 2645 config { 2646 pins = "gpio23", "gpio24"; 2647 drive-strength = <0x02>; 2648 bias-disable; 2649 }; 2650 }; 2651 2652 qup_spi18_default: qup-spi18-default { 2653 pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2654 function = "qup18"; 2655 drive-strength = <6>; 2656 bias-disable; 2657 }; 2658 2659 qup_i2c19_default: qup-i2c19-default { 2660 mux { 2661 pins = "gpio57", "gpio58"; 2662 function = "qup19"; 2663 }; 2664 2665 config { 2666 pins = "gpio57", "gpio58"; 2667 drive-strength = <0x02>; 2668 bias-disable; 2669 }; 2670 }; 2671 2672 qup_spi19_default: qup-spi19-default { 2673 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2674 function = "qup19"; 2675 drive-strength = <6>; 2676 bias-disable; 2677 }; 2678 2679 pcie0_default_state: pcie0-default { 2680 perst { 2681 pins = "gpio35"; 2682 function = "gpio"; 2683 drive-strength = <2>; 2684 bias-pull-down; 2685 }; 2686 2687 clkreq { 2688 pins = "gpio36"; 2689 function = "pci_e0"; 2690 drive-strength = <2>; 2691 bias-pull-up; 2692 }; 2693 2694 wake { 2695 pins = "gpio37"; 2696 function = "gpio"; 2697 drive-strength = <2>; 2698 bias-pull-up; 2699 }; 2700 }; 2701 2702 pcie1_default_state: pcie1-default { 2703 perst { 2704 pins = "gpio102"; 2705 function = "gpio"; 2706 drive-strength = <2>; 2707 bias-pull-down; 2708 }; 2709 2710 clkreq { 2711 pins = "gpio103"; 2712 function = "pci_e1"; 2713 drive-strength = <2>; 2714 bias-pull-up; 2715 }; 2716 2717 wake { 2718 pins = "gpio104"; 2719 function = "gpio"; 2720 drive-strength = <2>; 2721 bias-pull-up; 2722 }; 2723 }; 2724 }; 2725 2726 remoteproc_mpss: remoteproc@4080000 { 2727 compatible = "qcom,sm8150-mpss-pas"; 2728 reg = <0x0 0x04080000 0x0 0x4040>; 2729 2730 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2731 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2732 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2733 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2734 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2735 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2736 interrupt-names = "wdog", "fatal", "ready", "handover", 2737 "stop-ack", "shutdown-ack"; 2738 2739 clocks = <&rpmhcc RPMH_CXO_CLK>; 2740 clock-names = "xo"; 2741 2742 power-domains = <&rpmhpd 7>, 2743 <&rpmhpd 0>; 2744 power-domain-names = "cx", "mss"; 2745 2746 memory-region = <&mpss_mem>; 2747 2748 qcom,qmp = <&aoss_qmp>; 2749 2750 qcom,smem-states = <&modem_smp2p_out 0>; 2751 qcom,smem-state-names = "stop"; 2752 2753 status = "disabled"; 2754 2755 glink-edge { 2756 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2757 label = "modem"; 2758 qcom,remote-pid = <1>; 2759 mboxes = <&apss_shared 12>; 2760 }; 2761 }; 2762 2763 stm@6002000 { 2764 compatible = "arm,coresight-stm", "arm,primecell"; 2765 reg = <0 0x06002000 0 0x1000>, 2766 <0 0x16280000 0 0x180000>; 2767 reg-names = "stm-base", "stm-stimulus-base"; 2768 2769 clocks = <&aoss_qmp>; 2770 clock-names = "apb_pclk"; 2771 2772 out-ports { 2773 port { 2774 stm_out: endpoint { 2775 remote-endpoint = <&funnel0_in7>; 2776 }; 2777 }; 2778 }; 2779 }; 2780 2781 funnel@6041000 { 2782 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2783 reg = <0 0x06041000 0 0x1000>; 2784 2785 clocks = <&aoss_qmp>; 2786 clock-names = "apb_pclk"; 2787 2788 out-ports { 2789 port { 2790 funnel0_out: endpoint { 2791 remote-endpoint = <&merge_funnel_in0>; 2792 }; 2793 }; 2794 }; 2795 2796 in-ports { 2797 #address-cells = <1>; 2798 #size-cells = <0>; 2799 2800 port@7 { 2801 reg = <7>; 2802 funnel0_in7: endpoint { 2803 remote-endpoint = <&stm_out>; 2804 }; 2805 }; 2806 }; 2807 }; 2808 2809 funnel@6042000 { 2810 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2811 reg = <0 0x06042000 0 0x1000>; 2812 2813 clocks = <&aoss_qmp>; 2814 clock-names = "apb_pclk"; 2815 2816 out-ports { 2817 port { 2818 funnel1_out: endpoint { 2819 remote-endpoint = <&merge_funnel_in1>; 2820 }; 2821 }; 2822 }; 2823 2824 in-ports { 2825 #address-cells = <1>; 2826 #size-cells = <0>; 2827 2828 port@4 { 2829 reg = <4>; 2830 funnel1_in4: endpoint { 2831 remote-endpoint = <&swao_replicator_out>; 2832 }; 2833 }; 2834 }; 2835 }; 2836 2837 funnel@6043000 { 2838 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2839 reg = <0 0x06043000 0 0x1000>; 2840 2841 clocks = <&aoss_qmp>; 2842 clock-names = "apb_pclk"; 2843 2844 out-ports { 2845 port { 2846 funnel2_out: endpoint { 2847 remote-endpoint = <&merge_funnel_in2>; 2848 }; 2849 }; 2850 }; 2851 2852 in-ports { 2853 #address-cells = <1>; 2854 #size-cells = <0>; 2855 2856 port@2 { 2857 reg = <2>; 2858 funnel2_in2: endpoint { 2859 remote-endpoint = <&apss_merge_funnel_out>; 2860 }; 2861 }; 2862 }; 2863 }; 2864 2865 funnel@6045000 { 2866 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2867 reg = <0 0x06045000 0 0x1000>; 2868 2869 clocks = <&aoss_qmp>; 2870 clock-names = "apb_pclk"; 2871 2872 out-ports { 2873 port { 2874 merge_funnel_out: endpoint { 2875 remote-endpoint = <&etf_in>; 2876 }; 2877 }; 2878 }; 2879 2880 in-ports { 2881 #address-cells = <1>; 2882 #size-cells = <0>; 2883 2884 port@0 { 2885 reg = <0>; 2886 merge_funnel_in0: endpoint { 2887 remote-endpoint = <&funnel0_out>; 2888 }; 2889 }; 2890 2891 port@1 { 2892 reg = <1>; 2893 merge_funnel_in1: endpoint { 2894 remote-endpoint = <&funnel1_out>; 2895 }; 2896 }; 2897 2898 port@2 { 2899 reg = <2>; 2900 merge_funnel_in2: endpoint { 2901 remote-endpoint = <&funnel2_out>; 2902 }; 2903 }; 2904 }; 2905 }; 2906 2907 replicator@6046000 { 2908 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2909 reg = <0 0x06046000 0 0x1000>; 2910 2911 clocks = <&aoss_qmp>; 2912 clock-names = "apb_pclk"; 2913 2914 out-ports { 2915 #address-cells = <1>; 2916 #size-cells = <0>; 2917 2918 port@0 { 2919 reg = <0>; 2920 replicator_out0: endpoint { 2921 remote-endpoint = <&etr_in>; 2922 }; 2923 }; 2924 2925 port@1 { 2926 reg = <1>; 2927 replicator_out1: endpoint { 2928 remote-endpoint = <&replicator1_in>; 2929 }; 2930 }; 2931 }; 2932 2933 in-ports { 2934 port { 2935 replicator_in0: endpoint { 2936 remote-endpoint = <&etf_out>; 2937 }; 2938 }; 2939 }; 2940 }; 2941 2942 etf@6047000 { 2943 compatible = "arm,coresight-tmc", "arm,primecell"; 2944 reg = <0 0x06047000 0 0x1000>; 2945 2946 clocks = <&aoss_qmp>; 2947 clock-names = "apb_pclk"; 2948 2949 out-ports { 2950 port { 2951 etf_out: endpoint { 2952 remote-endpoint = <&replicator_in0>; 2953 }; 2954 }; 2955 }; 2956 2957 in-ports { 2958 port { 2959 etf_in: endpoint { 2960 remote-endpoint = <&merge_funnel_out>; 2961 }; 2962 }; 2963 }; 2964 }; 2965 2966 etr@6048000 { 2967 compatible = "arm,coresight-tmc", "arm,primecell"; 2968 reg = <0 0x06048000 0 0x1000>; 2969 iommus = <&apps_smmu 0x05e0 0x0>; 2970 2971 clocks = <&aoss_qmp>; 2972 clock-names = "apb_pclk"; 2973 arm,scatter-gather; 2974 2975 in-ports { 2976 port { 2977 etr_in: endpoint { 2978 remote-endpoint = <&replicator_out0>; 2979 }; 2980 }; 2981 }; 2982 }; 2983 2984 replicator@604a000 { 2985 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2986 reg = <0 0x0604a000 0 0x1000>; 2987 2988 clocks = <&aoss_qmp>; 2989 clock-names = "apb_pclk"; 2990 2991 out-ports { 2992 #address-cells = <1>; 2993 #size-cells = <0>; 2994 2995 port@1 { 2996 reg = <1>; 2997 replicator1_out: endpoint { 2998 remote-endpoint = <&swao_funnel_in>; 2999 }; 3000 }; 3001 }; 3002 3003 in-ports { 3004 #address-cells = <1>; 3005 #size-cells = <0>; 3006 3007 port@1 { 3008 reg = <1>; 3009 replicator1_in: endpoint { 3010 remote-endpoint = <&replicator_out1>; 3011 }; 3012 }; 3013 }; 3014 }; 3015 3016 funnel@6b08000 { 3017 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3018 reg = <0 0x06b08000 0 0x1000>; 3019 3020 clocks = <&aoss_qmp>; 3021 clock-names = "apb_pclk"; 3022 3023 out-ports { 3024 port { 3025 swao_funnel_out: endpoint { 3026 remote-endpoint = <&swao_etf_in>; 3027 }; 3028 }; 3029 }; 3030 3031 in-ports { 3032 #address-cells = <1>; 3033 #size-cells = <0>; 3034 3035 port@6 { 3036 reg = <6>; 3037 swao_funnel_in: endpoint { 3038 remote-endpoint = <&replicator1_out>; 3039 }; 3040 }; 3041 }; 3042 }; 3043 3044 etf@6b09000 { 3045 compatible = "arm,coresight-tmc", "arm,primecell"; 3046 reg = <0 0x06b09000 0 0x1000>; 3047 3048 clocks = <&aoss_qmp>; 3049 clock-names = "apb_pclk"; 3050 3051 out-ports { 3052 port { 3053 swao_etf_out: endpoint { 3054 remote-endpoint = <&swao_replicator_in>; 3055 }; 3056 }; 3057 }; 3058 3059 in-ports { 3060 port { 3061 swao_etf_in: endpoint { 3062 remote-endpoint = <&swao_funnel_out>; 3063 }; 3064 }; 3065 }; 3066 }; 3067 3068 replicator@6b0a000 { 3069 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3070 reg = <0 0x06b0a000 0 0x1000>; 3071 3072 clocks = <&aoss_qmp>; 3073 clock-names = "apb_pclk"; 3074 qcom,replicator-loses-context; 3075 3076 out-ports { 3077 port { 3078 swao_replicator_out: endpoint { 3079 remote-endpoint = <&funnel1_in4>; 3080 }; 3081 }; 3082 }; 3083 3084 in-ports { 3085 port { 3086 swao_replicator_in: endpoint { 3087 remote-endpoint = <&swao_etf_out>; 3088 }; 3089 }; 3090 }; 3091 }; 3092 3093 etm@7040000 { 3094 compatible = "arm,coresight-etm4x", "arm,primecell"; 3095 reg = <0 0x07040000 0 0x1000>; 3096 3097 cpu = <&CPU0>; 3098 3099 clocks = <&aoss_qmp>; 3100 clock-names = "apb_pclk"; 3101 arm,coresight-loses-context-with-cpu; 3102 qcom,skip-power-up; 3103 3104 out-ports { 3105 port { 3106 etm0_out: endpoint { 3107 remote-endpoint = <&apss_funnel_in0>; 3108 }; 3109 }; 3110 }; 3111 }; 3112 3113 etm@7140000 { 3114 compatible = "arm,coresight-etm4x", "arm,primecell"; 3115 reg = <0 0x07140000 0 0x1000>; 3116 3117 cpu = <&CPU1>; 3118 3119 clocks = <&aoss_qmp>; 3120 clock-names = "apb_pclk"; 3121 arm,coresight-loses-context-with-cpu; 3122 qcom,skip-power-up; 3123 3124 out-ports { 3125 port { 3126 etm1_out: endpoint { 3127 remote-endpoint = <&apss_funnel_in1>; 3128 }; 3129 }; 3130 }; 3131 }; 3132 3133 etm@7240000 { 3134 compatible = "arm,coresight-etm4x", "arm,primecell"; 3135 reg = <0 0x07240000 0 0x1000>; 3136 3137 cpu = <&CPU2>; 3138 3139 clocks = <&aoss_qmp>; 3140 clock-names = "apb_pclk"; 3141 arm,coresight-loses-context-with-cpu; 3142 qcom,skip-power-up; 3143 3144 out-ports { 3145 port { 3146 etm2_out: endpoint { 3147 remote-endpoint = <&apss_funnel_in2>; 3148 }; 3149 }; 3150 }; 3151 }; 3152 3153 etm@7340000 { 3154 compatible = "arm,coresight-etm4x", "arm,primecell"; 3155 reg = <0 0x07340000 0 0x1000>; 3156 3157 cpu = <&CPU3>; 3158 3159 clocks = <&aoss_qmp>; 3160 clock-names = "apb_pclk"; 3161 arm,coresight-loses-context-with-cpu; 3162 qcom,skip-power-up; 3163 3164 out-ports { 3165 port { 3166 etm3_out: endpoint { 3167 remote-endpoint = <&apss_funnel_in3>; 3168 }; 3169 }; 3170 }; 3171 }; 3172 3173 etm@7440000 { 3174 compatible = "arm,coresight-etm4x", "arm,primecell"; 3175 reg = <0 0x07440000 0 0x1000>; 3176 3177 cpu = <&CPU4>; 3178 3179 clocks = <&aoss_qmp>; 3180 clock-names = "apb_pclk"; 3181 arm,coresight-loses-context-with-cpu; 3182 qcom,skip-power-up; 3183 3184 out-ports { 3185 port { 3186 etm4_out: endpoint { 3187 remote-endpoint = <&apss_funnel_in4>; 3188 }; 3189 }; 3190 }; 3191 }; 3192 3193 etm@7540000 { 3194 compatible = "arm,coresight-etm4x", "arm,primecell"; 3195 reg = <0 0x07540000 0 0x1000>; 3196 3197 cpu = <&CPU5>; 3198 3199 clocks = <&aoss_qmp>; 3200 clock-names = "apb_pclk"; 3201 arm,coresight-loses-context-with-cpu; 3202 qcom,skip-power-up; 3203 3204 out-ports { 3205 port { 3206 etm5_out: endpoint { 3207 remote-endpoint = <&apss_funnel_in5>; 3208 }; 3209 }; 3210 }; 3211 }; 3212 3213 etm@7640000 { 3214 compatible = "arm,coresight-etm4x", "arm,primecell"; 3215 reg = <0 0x07640000 0 0x1000>; 3216 3217 cpu = <&CPU6>; 3218 3219 clocks = <&aoss_qmp>; 3220 clock-names = "apb_pclk"; 3221 arm,coresight-loses-context-with-cpu; 3222 qcom,skip-power-up; 3223 3224 out-ports { 3225 port { 3226 etm6_out: endpoint { 3227 remote-endpoint = <&apss_funnel_in6>; 3228 }; 3229 }; 3230 }; 3231 }; 3232 3233 etm@7740000 { 3234 compatible = "arm,coresight-etm4x", "arm,primecell"; 3235 reg = <0 0x07740000 0 0x1000>; 3236 3237 cpu = <&CPU7>; 3238 3239 clocks = <&aoss_qmp>; 3240 clock-names = "apb_pclk"; 3241 arm,coresight-loses-context-with-cpu; 3242 qcom,skip-power-up; 3243 3244 out-ports { 3245 port { 3246 etm7_out: endpoint { 3247 remote-endpoint = <&apss_funnel_in7>; 3248 }; 3249 }; 3250 }; 3251 }; 3252 3253 funnel@7800000 { /* APSS Funnel */ 3254 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3255 reg = <0 0x07800000 0 0x1000>; 3256 3257 clocks = <&aoss_qmp>; 3258 clock-names = "apb_pclk"; 3259 3260 out-ports { 3261 port { 3262 apss_funnel_out: endpoint { 3263 remote-endpoint = <&apss_merge_funnel_in>; 3264 }; 3265 }; 3266 }; 3267 3268 in-ports { 3269 #address-cells = <1>; 3270 #size-cells = <0>; 3271 3272 port@0 { 3273 reg = <0>; 3274 apss_funnel_in0: endpoint { 3275 remote-endpoint = <&etm0_out>; 3276 }; 3277 }; 3278 3279 port@1 { 3280 reg = <1>; 3281 apss_funnel_in1: endpoint { 3282 remote-endpoint = <&etm1_out>; 3283 }; 3284 }; 3285 3286 port@2 { 3287 reg = <2>; 3288 apss_funnel_in2: endpoint { 3289 remote-endpoint = <&etm2_out>; 3290 }; 3291 }; 3292 3293 port@3 { 3294 reg = <3>; 3295 apss_funnel_in3: endpoint { 3296 remote-endpoint = <&etm3_out>; 3297 }; 3298 }; 3299 3300 port@4 { 3301 reg = <4>; 3302 apss_funnel_in4: endpoint { 3303 remote-endpoint = <&etm4_out>; 3304 }; 3305 }; 3306 3307 port@5 { 3308 reg = <5>; 3309 apss_funnel_in5: endpoint { 3310 remote-endpoint = <&etm5_out>; 3311 }; 3312 }; 3313 3314 port@6 { 3315 reg = <6>; 3316 apss_funnel_in6: endpoint { 3317 remote-endpoint = <&etm6_out>; 3318 }; 3319 }; 3320 3321 port@7 { 3322 reg = <7>; 3323 apss_funnel_in7: endpoint { 3324 remote-endpoint = <&etm7_out>; 3325 }; 3326 }; 3327 }; 3328 }; 3329 3330 funnel@7810000 { 3331 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3332 reg = <0 0x07810000 0 0x1000>; 3333 3334 clocks = <&aoss_qmp>; 3335 clock-names = "apb_pclk"; 3336 3337 out-ports { 3338 port { 3339 apss_merge_funnel_out: endpoint { 3340 remote-endpoint = <&funnel2_in2>; 3341 }; 3342 }; 3343 }; 3344 3345 in-ports { 3346 port { 3347 apss_merge_funnel_in: endpoint { 3348 remote-endpoint = <&apss_funnel_out>; 3349 }; 3350 }; 3351 }; 3352 }; 3353 3354 remoteproc_cdsp: remoteproc@8300000 { 3355 compatible = "qcom,sm8150-cdsp-pas"; 3356 reg = <0x0 0x08300000 0x0 0x4040>; 3357 3358 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3359 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3360 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3361 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3362 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3363 interrupt-names = "wdog", "fatal", "ready", 3364 "handover", "stop-ack"; 3365 3366 clocks = <&rpmhcc RPMH_CXO_CLK>; 3367 clock-names = "xo"; 3368 3369 power-domains = <&rpmhpd 7>; 3370 3371 memory-region = <&cdsp_mem>; 3372 3373 qcom,qmp = <&aoss_qmp>; 3374 3375 qcom,smem-states = <&cdsp_smp2p_out 0>; 3376 qcom,smem-state-names = "stop"; 3377 3378 status = "disabled"; 3379 3380 glink-edge { 3381 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 3382 label = "cdsp"; 3383 qcom,remote-pid = <5>; 3384 mboxes = <&apss_shared 4>; 3385 3386 fastrpc { 3387 compatible = "qcom,fastrpc"; 3388 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3389 label = "cdsp"; 3390 qcom,non-secure-domain; 3391 #address-cells = <1>; 3392 #size-cells = <0>; 3393 3394 compute-cb@1 { 3395 compatible = "qcom,fastrpc-compute-cb"; 3396 reg = <1>; 3397 iommus = <&apps_smmu 0x1001 0x0460>; 3398 }; 3399 3400 compute-cb@2 { 3401 compatible = "qcom,fastrpc-compute-cb"; 3402 reg = <2>; 3403 iommus = <&apps_smmu 0x1002 0x0460>; 3404 }; 3405 3406 compute-cb@3 { 3407 compatible = "qcom,fastrpc-compute-cb"; 3408 reg = <3>; 3409 iommus = <&apps_smmu 0x1003 0x0460>; 3410 }; 3411 3412 compute-cb@4 { 3413 compatible = "qcom,fastrpc-compute-cb"; 3414 reg = <4>; 3415 iommus = <&apps_smmu 0x1004 0x0460>; 3416 }; 3417 3418 compute-cb@5 { 3419 compatible = "qcom,fastrpc-compute-cb"; 3420 reg = <5>; 3421 iommus = <&apps_smmu 0x1005 0x0460>; 3422 }; 3423 3424 compute-cb@6 { 3425 compatible = "qcom,fastrpc-compute-cb"; 3426 reg = <6>; 3427 iommus = <&apps_smmu 0x1006 0x0460>; 3428 }; 3429 3430 compute-cb@7 { 3431 compatible = "qcom,fastrpc-compute-cb"; 3432 reg = <7>; 3433 iommus = <&apps_smmu 0x1007 0x0460>; 3434 }; 3435 3436 compute-cb@8 { 3437 compatible = "qcom,fastrpc-compute-cb"; 3438 reg = <8>; 3439 iommus = <&apps_smmu 0x1008 0x0460>; 3440 }; 3441 3442 /* note: secure cb9 in downstream */ 3443 }; 3444 }; 3445 }; 3446 3447 usb_1_hsphy: phy@88e2000 { 3448 compatible = "qcom,sm8150-usb-hs-phy", 3449 "qcom,usb-snps-hs-7nm-phy"; 3450 reg = <0 0x088e2000 0 0x400>; 3451 status = "disabled"; 3452 #phy-cells = <0>; 3453 3454 clocks = <&rpmhcc RPMH_CXO_CLK>; 3455 clock-names = "ref"; 3456 3457 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3458 }; 3459 3460 usb_2_hsphy: phy@88e3000 { 3461 compatible = "qcom,sm8150-usb-hs-phy", 3462 "qcom,usb-snps-hs-7nm-phy"; 3463 reg = <0 0x088e3000 0 0x400>; 3464 status = "disabled"; 3465 #phy-cells = <0>; 3466 3467 clocks = <&rpmhcc RPMH_CXO_CLK>; 3468 clock-names = "ref"; 3469 3470 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3471 }; 3472 3473 usb_1_qmpphy: phy@88e9000 { 3474 compatible = "qcom,sm8150-qmp-usb3-phy"; 3475 reg = <0 0x088e9000 0 0x18c>, 3476 <0 0x088e8000 0 0x10>; 3477 status = "disabled"; 3478 #address-cells = <2>; 3479 #size-cells = <2>; 3480 ranges; 3481 3482 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3483 <&rpmhcc RPMH_CXO_CLK>, 3484 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3485 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3486 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3487 3488 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3489 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3490 reset-names = "phy", "common"; 3491 3492 usb_1_ssphy: phy@88e9200 { 3493 reg = <0 0x088e9200 0 0x200>, 3494 <0 0x088e9400 0 0x200>, 3495 <0 0x088e9c00 0 0x218>, 3496 <0 0x088e9600 0 0x200>, 3497 <0 0x088e9800 0 0x200>, 3498 <0 0x088e9a00 0 0x100>; 3499 #clock-cells = <0>; 3500 #phy-cells = <0>; 3501 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3502 clock-names = "pipe0"; 3503 clock-output-names = "usb3_phy_pipe_clk_src"; 3504 }; 3505 }; 3506 3507 usb_2_qmpphy: phy@88eb000 { 3508 compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 3509 reg = <0 0x088eb000 0 0x200>; 3510 status = "disabled"; 3511 #address-cells = <2>; 3512 #size-cells = <2>; 3513 ranges; 3514 3515 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3516 <&rpmhcc RPMH_CXO_CLK>, 3517 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3518 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3519 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3520 3521 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3522 <&gcc GCC_USB3_PHY_SEC_BCR>; 3523 reset-names = "phy", "common"; 3524 3525 usb_2_ssphy: phy@88eb200 { 3526 reg = <0 0x088eb200 0 0x200>, 3527 <0 0x088eb400 0 0x200>, 3528 <0 0x088eb800 0 0x800>, 3529 <0 0x088eb600 0 0x200>; 3530 #clock-cells = <0>; 3531 #phy-cells = <0>; 3532 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3533 clock-names = "pipe0"; 3534 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3535 }; 3536 }; 3537 3538 sdhc_2: mmc@8804000 { 3539 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3540 reg = <0 0x08804000 0 0x1000>; 3541 3542 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3543 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3544 interrupt-names = "hc_irq", "pwr_irq"; 3545 3546 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3547 <&gcc GCC_SDCC2_APPS_CLK>, 3548 <&rpmhcc RPMH_CXO_CLK>; 3549 clock-names = "iface", "core", "xo"; 3550 iommus = <&apps_smmu 0x6a0 0x0>; 3551 qcom,dll-config = <0x0007642c>; 3552 qcom,ddr-config = <0x80040868>; 3553 power-domains = <&rpmhpd 0>; 3554 operating-points-v2 = <&sdhc2_opp_table>; 3555 3556 status = "disabled"; 3557 3558 sdhc2_opp_table: opp-table { 3559 compatible = "operating-points-v2"; 3560 3561 opp-19200000 { 3562 opp-hz = /bits/ 64 <19200000>; 3563 required-opps = <&rpmhpd_opp_min_svs>; 3564 }; 3565 3566 opp-50000000 { 3567 opp-hz = /bits/ 64 <50000000>; 3568 required-opps = <&rpmhpd_opp_low_svs>; 3569 }; 3570 3571 opp-100000000 { 3572 opp-hz = /bits/ 64 <100000000>; 3573 required-opps = <&rpmhpd_opp_svs>; 3574 }; 3575 3576 opp-202000000 { 3577 opp-hz = /bits/ 64 <202000000>; 3578 required-opps = <&rpmhpd_opp_svs_l1>; 3579 }; 3580 }; 3581 }; 3582 3583 dc_noc: interconnect@9160000 { 3584 compatible = "qcom,sm8150-dc-noc"; 3585 reg = <0 0x09160000 0 0x3200>; 3586 #interconnect-cells = <1>; 3587 qcom,bcm-voters = <&apps_bcm_voter>; 3588 }; 3589 3590 gem_noc: interconnect@9680000 { 3591 compatible = "qcom,sm8150-gem-noc"; 3592 reg = <0 0x09680000 0 0x3e200>; 3593 #interconnect-cells = <1>; 3594 qcom,bcm-voters = <&apps_bcm_voter>; 3595 }; 3596 3597 usb_1: usb@a6f8800 { 3598 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3599 reg = <0 0x0a6f8800 0 0x400>; 3600 status = "disabled"; 3601 #address-cells = <2>; 3602 #size-cells = <2>; 3603 ranges; 3604 dma-ranges; 3605 3606 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3607 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3608 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3609 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3610 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3611 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3612 clock-names = "cfg_noc", 3613 "core", 3614 "iface", 3615 "sleep", 3616 "mock_utmi", 3617 "xo"; 3618 3619 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3620 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3621 assigned-clock-rates = <19200000>, <200000000>; 3622 3623 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3625 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3626 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3627 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3628 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3629 3630 power-domains = <&gcc USB30_PRIM_GDSC>; 3631 3632 resets = <&gcc GCC_USB30_PRIM_BCR>; 3633 3634 usb_1_dwc3: usb@a600000 { 3635 compatible = "snps,dwc3"; 3636 reg = <0 0x0a600000 0 0xcd00>; 3637 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3638 iommus = <&apps_smmu 0x140 0>; 3639 snps,dis_u2_susphy_quirk; 3640 snps,dis_enblslpm_quirk; 3641 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3642 phy-names = "usb2-phy", "usb3-phy"; 3643 }; 3644 }; 3645 3646 usb_2: usb@a8f8800 { 3647 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3648 reg = <0 0x0a8f8800 0 0x400>; 3649 status = "disabled"; 3650 #address-cells = <2>; 3651 #size-cells = <2>; 3652 ranges; 3653 dma-ranges; 3654 3655 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3656 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3657 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3658 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3659 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3660 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3661 clock-names = "cfg_noc", 3662 "core", 3663 "iface", 3664 "sleep", 3665 "mock_utmi", 3666 "xo"; 3667 3668 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3669 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3670 assigned-clock-rates = <19200000>, <200000000>; 3671 3672 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3673 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 3674 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3675 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 3676 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3677 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3678 3679 power-domains = <&gcc USB30_SEC_GDSC>; 3680 3681 resets = <&gcc GCC_USB30_SEC_BCR>; 3682 3683 usb_2_dwc3: usb@a800000 { 3684 compatible = "snps,dwc3"; 3685 reg = <0 0x0a800000 0 0xcd00>; 3686 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3687 iommus = <&apps_smmu 0x160 0>; 3688 snps,dis_u2_susphy_quirk; 3689 snps,dis_enblslpm_quirk; 3690 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3691 phy-names = "usb2-phy", "usb3-phy"; 3692 }; 3693 }; 3694 3695 camnoc_virt: interconnect@ac00000 { 3696 compatible = "qcom,sm8150-camnoc-virt"; 3697 reg = <0 0x0ac00000 0 0x1000>; 3698 #interconnect-cells = <1>; 3699 qcom,bcm-voters = <&apps_bcm_voter>; 3700 }; 3701 3702 pdc: interrupt-controller@b220000 { 3703 compatible = "qcom,sm8150-pdc", "qcom,pdc"; 3704 reg = <0 0x0b220000 0 0x400>; 3705 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3706 <125 63 1>; 3707 #interrupt-cells = <2>; 3708 interrupt-parent = <&intc>; 3709 interrupt-controller; 3710 }; 3711 3712 aoss_qmp: power-controller@c300000 { 3713 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 3714 reg = <0x0 0x0c300000 0x0 0x400>; 3715 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3716 mboxes = <&apss_shared 0>; 3717 3718 #clock-cells = <0>; 3719 }; 3720 3721 sram@c3f0000 { 3722 compatible = "qcom,rpmh-stats"; 3723 reg = <0 0x0c3f0000 0 0x400>; 3724 }; 3725 3726 tsens0: thermal-sensor@c263000 { 3727 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3728 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3729 <0 0x0c222000 0 0x1ff>; /* SROT */ 3730 #qcom,sensors = <16>; 3731 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3732 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3733 interrupt-names = "uplow", "critical"; 3734 #thermal-sensor-cells = <1>; 3735 }; 3736 3737 tsens1: thermal-sensor@c265000 { 3738 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3739 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3740 <0 0x0c223000 0 0x1ff>; /* SROT */ 3741 #qcom,sensors = <8>; 3742 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3743 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3744 interrupt-names = "uplow", "critical"; 3745 #thermal-sensor-cells = <1>; 3746 }; 3747 3748 spmi_bus: spmi@c440000 { 3749 compatible = "qcom,spmi-pmic-arb"; 3750 reg = <0x0 0x0c440000 0x0 0x0001100>, 3751 <0x0 0x0c600000 0x0 0x2000000>, 3752 <0x0 0x0e600000 0x0 0x0100000>, 3753 <0x0 0x0e700000 0x0 0x00a0000>, 3754 <0x0 0x0c40a000 0x0 0x0026000>; 3755 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3756 interrupt-names = "periph_irq"; 3757 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3758 qcom,ee = <0>; 3759 qcom,channel = <0>; 3760 #address-cells = <2>; 3761 #size-cells = <0>; 3762 interrupt-controller; 3763 #interrupt-cells = <4>; 3764 cell-index = <0>; 3765 }; 3766 3767 apps_smmu: iommu@15000000 { 3768 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 3769 reg = <0 0x15000000 0 0x100000>; 3770 #iommu-cells = <2>; 3771 #global-interrupts = <1>; 3772 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3773 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3782 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3783 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3784 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3785 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3786 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3787 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3788 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3789 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3790 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3792 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3793 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3794 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3795 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3796 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3798 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3799 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3800 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3801 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3802 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3803 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3804 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3805 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3806 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3807 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3808 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3809 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3810 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3811 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3812 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3813 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3814 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3815 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3816 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3817 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3818 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3819 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3820 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3821 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3822 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3823 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3824 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3825 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3826 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3827 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3828 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3829 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3830 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3831 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3832 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3833 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3834 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3835 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3836 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3837 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3838 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3839 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3840 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3841 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3842 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3843 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3844 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3845 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3846 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3847 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3848 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3849 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3850 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3851 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3852 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 3853 }; 3854 3855 remoteproc_adsp: remoteproc@17300000 { 3856 compatible = "qcom,sm8150-adsp-pas"; 3857 reg = <0x0 0x17300000 0x0 0x4040>; 3858 3859 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3860 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3861 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3862 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3863 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3864 interrupt-names = "wdog", "fatal", "ready", 3865 "handover", "stop-ack"; 3866 3867 clocks = <&rpmhcc RPMH_CXO_CLK>; 3868 clock-names = "xo"; 3869 3870 power-domains = <&rpmhpd 7>; 3871 3872 memory-region = <&adsp_mem>; 3873 3874 qcom,qmp = <&aoss_qmp>; 3875 3876 qcom,smem-states = <&adsp_smp2p_out 0>; 3877 qcom,smem-state-names = "stop"; 3878 3879 status = "disabled"; 3880 3881 glink-edge { 3882 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3883 label = "lpass"; 3884 qcom,remote-pid = <2>; 3885 mboxes = <&apss_shared 8>; 3886 3887 fastrpc { 3888 compatible = "qcom,fastrpc"; 3889 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3890 label = "adsp"; 3891 qcom,non-secure-domain; 3892 #address-cells = <1>; 3893 #size-cells = <0>; 3894 3895 compute-cb@3 { 3896 compatible = "qcom,fastrpc-compute-cb"; 3897 reg = <3>; 3898 iommus = <&apps_smmu 0x1b23 0x0>; 3899 }; 3900 3901 compute-cb@4 { 3902 compatible = "qcom,fastrpc-compute-cb"; 3903 reg = <4>; 3904 iommus = <&apps_smmu 0x1b24 0x0>; 3905 }; 3906 3907 compute-cb@5 { 3908 compatible = "qcom,fastrpc-compute-cb"; 3909 reg = <5>; 3910 iommus = <&apps_smmu 0x1b25 0x0>; 3911 }; 3912 }; 3913 }; 3914 }; 3915 3916 intc: interrupt-controller@17a00000 { 3917 compatible = "arm,gic-v3"; 3918 interrupt-controller; 3919 #interrupt-cells = <3>; 3920 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3921 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3922 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3923 }; 3924 3925 apss_shared: mailbox@17c00000 { 3926 compatible = "qcom,sm8150-apss-shared"; 3927 reg = <0x0 0x17c00000 0x0 0x1000>; 3928 #mbox-cells = <1>; 3929 }; 3930 3931 watchdog@17c10000 { 3932 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 3933 reg = <0 0x17c10000 0 0x1000>; 3934 clocks = <&sleep_clk>; 3935 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3936 }; 3937 3938 timer@17c20000 { 3939 #address-cells = <1>; 3940 #size-cells = <1>; 3941 ranges = <0 0 0 0x20000000>; 3942 compatible = "arm,armv7-timer-mem"; 3943 reg = <0x0 0x17c20000 0x0 0x1000>; 3944 clock-frequency = <19200000>; 3945 3946 frame@17c21000{ 3947 frame-number = <0>; 3948 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3949 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3950 reg = <0x17c21000 0x1000>, 3951 <0x17c22000 0x1000>; 3952 }; 3953 3954 frame@17c23000 { 3955 frame-number = <1>; 3956 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3957 reg = <0x17c23000 0x1000>; 3958 status = "disabled"; 3959 }; 3960 3961 frame@17c25000 { 3962 frame-number = <2>; 3963 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3964 reg = <0x17c25000 0x1000>; 3965 status = "disabled"; 3966 }; 3967 3968 frame@17c27000 { 3969 frame-number = <3>; 3970 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3971 reg = <0x17c26000 0x1000>; 3972 status = "disabled"; 3973 }; 3974 3975 frame@17c29000 { 3976 frame-number = <4>; 3977 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3978 reg = <0x17c29000 0x1000>; 3979 status = "disabled"; 3980 }; 3981 3982 frame@17c2b000 { 3983 frame-number = <5>; 3984 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3985 reg = <0x17c2b000 0x1000>; 3986 status = "disabled"; 3987 }; 3988 3989 frame@17c2d000 { 3990 frame-number = <6>; 3991 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3992 reg = <0x17c2d000 0x1000>; 3993 status = "disabled"; 3994 }; 3995 }; 3996 3997 apps_rsc: rsc@18200000 { 3998 label = "apps_rsc"; 3999 compatible = "qcom,rpmh-rsc"; 4000 reg = <0x0 0x18200000 0x0 0x10000>, 4001 <0x0 0x18210000 0x0 0x10000>, 4002 <0x0 0x18220000 0x0 0x10000>; 4003 reg-names = "drv-0", "drv-1", "drv-2"; 4004 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4005 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4006 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4007 qcom,tcs-offset = <0xd00>; 4008 qcom,drv-id = <2>; 4009 qcom,tcs-config = <ACTIVE_TCS 2>, 4010 <SLEEP_TCS 3>, 4011 <WAKE_TCS 3>, 4012 <CONTROL_TCS 1>; 4013 4014 rpmhcc: clock-controller { 4015 compatible = "qcom,sm8150-rpmh-clk"; 4016 #clock-cells = <1>; 4017 clock-names = "xo"; 4018 clocks = <&xo_board>; 4019 }; 4020 4021 rpmhpd: power-controller { 4022 compatible = "qcom,sm8150-rpmhpd"; 4023 #power-domain-cells = <1>; 4024 operating-points-v2 = <&rpmhpd_opp_table>; 4025 4026 rpmhpd_opp_table: opp-table { 4027 compatible = "operating-points-v2"; 4028 4029 rpmhpd_opp_ret: opp1 { 4030 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4031 }; 4032 4033 rpmhpd_opp_min_svs: opp2 { 4034 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4035 }; 4036 4037 rpmhpd_opp_low_svs: opp3 { 4038 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4039 }; 4040 4041 rpmhpd_opp_svs: opp4 { 4042 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4043 }; 4044 4045 rpmhpd_opp_svs_l1: opp5 { 4046 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4047 }; 4048 4049 rpmhpd_opp_svs_l2: opp6 { 4050 opp-level = <224>; 4051 }; 4052 4053 rpmhpd_opp_nom: opp7 { 4054 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4055 }; 4056 4057 rpmhpd_opp_nom_l1: opp8 { 4058 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4059 }; 4060 4061 rpmhpd_opp_nom_l2: opp9 { 4062 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4063 }; 4064 4065 rpmhpd_opp_turbo: opp10 { 4066 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4067 }; 4068 4069 rpmhpd_opp_turbo_l1: opp11 { 4070 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4071 }; 4072 }; 4073 }; 4074 4075 apps_bcm_voter: bcm-voter { 4076 compatible = "qcom,bcm-voter"; 4077 }; 4078 }; 4079 4080 osm_l3: interconnect@18321000 { 4081 compatible = "qcom,sm8150-osm-l3"; 4082 reg = <0 0x18321000 0 0x1400>; 4083 4084 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4085 clock-names = "xo", "alternate"; 4086 4087 #interconnect-cells = <1>; 4088 }; 4089 4090 cpufreq_hw: cpufreq@18323000 { 4091 compatible = "qcom,cpufreq-hw"; 4092 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 4093 <0 0x18327800 0 0x1400>; 4094 reg-names = "freq-domain0", "freq-domain1", 4095 "freq-domain2"; 4096 4097 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4098 clock-names = "xo", "alternate"; 4099 4100 #freq-domain-cells = <1>; 4101 }; 4102 4103 lmh_cluster1: lmh@18350800 { 4104 compatible = "qcom,sm8150-lmh"; 4105 reg = <0 0x18350800 0 0x400>; 4106 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 4107 cpus = <&CPU4>; 4108 qcom,lmh-temp-arm-millicelsius = <60000>; 4109 qcom,lmh-temp-low-millicelsius = <84500>; 4110 qcom,lmh-temp-high-millicelsius = <85000>; 4111 interrupt-controller; 4112 #interrupt-cells = <1>; 4113 }; 4114 4115 lmh_cluster0: lmh@18358800 { 4116 compatible = "qcom,sm8150-lmh"; 4117 reg = <0 0x18358800 0 0x400>; 4118 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4119 cpus = <&CPU0>; 4120 qcom,lmh-temp-arm-millicelsius = <60000>; 4121 qcom,lmh-temp-low-millicelsius = <84500>; 4122 qcom,lmh-temp-high-millicelsius = <85000>; 4123 interrupt-controller; 4124 #interrupt-cells = <1>; 4125 }; 4126 4127 wifi: wifi@18800000 { 4128 compatible = "qcom,wcn3990-wifi"; 4129 reg = <0 0x18800000 0 0x800000>; 4130 reg-names = "membase"; 4131 memory-region = <&wlan_mem>; 4132 clock-names = "cxo_ref_clk_pin", "qdss"; 4133 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 4134 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4135 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4136 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4137 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4138 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4139 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4140 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4141 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4142 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4143 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4144 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4145 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4146 iommus = <&apps_smmu 0x0640 0x1>; 4147 status = "disabled"; 4148 }; 4149 }; 4150 4151 timer { 4152 compatible = "arm,armv8-timer"; 4153 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4154 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4155 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4156 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4157 }; 4158 4159 thermal-zones { 4160 cpu0-thermal { 4161 polling-delay-passive = <250>; 4162 polling-delay = <1000>; 4163 4164 thermal-sensors = <&tsens0 1>; 4165 4166 trips { 4167 cpu0_alert0: trip-point0 { 4168 temperature = <90000>; 4169 hysteresis = <2000>; 4170 type = "passive"; 4171 }; 4172 4173 cpu0_alert1: trip-point1 { 4174 temperature = <95000>; 4175 hysteresis = <2000>; 4176 type = "passive"; 4177 }; 4178 4179 cpu0_crit: cpu_crit { 4180 temperature = <110000>; 4181 hysteresis = <1000>; 4182 type = "critical"; 4183 }; 4184 }; 4185 4186 cooling-maps { 4187 map0 { 4188 trip = <&cpu0_alert0>; 4189 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4190 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4191 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4192 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4193 }; 4194 map1 { 4195 trip = <&cpu0_alert1>; 4196 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4197 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4198 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4199 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4200 }; 4201 }; 4202 }; 4203 4204 cpu1-thermal { 4205 polling-delay-passive = <250>; 4206 polling-delay = <1000>; 4207 4208 thermal-sensors = <&tsens0 2>; 4209 4210 trips { 4211 cpu1_alert0: trip-point0 { 4212 temperature = <90000>; 4213 hysteresis = <2000>; 4214 type = "passive"; 4215 }; 4216 4217 cpu1_alert1: trip-point1 { 4218 temperature = <95000>; 4219 hysteresis = <2000>; 4220 type = "passive"; 4221 }; 4222 4223 cpu1_crit: cpu_crit { 4224 temperature = <110000>; 4225 hysteresis = <1000>; 4226 type = "critical"; 4227 }; 4228 }; 4229 4230 cooling-maps { 4231 map0 { 4232 trip = <&cpu1_alert0>; 4233 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4234 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4235 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4236 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4237 }; 4238 map1 { 4239 trip = <&cpu1_alert1>; 4240 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4241 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4242 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4243 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4244 }; 4245 }; 4246 }; 4247 4248 cpu2-thermal { 4249 polling-delay-passive = <250>; 4250 polling-delay = <1000>; 4251 4252 thermal-sensors = <&tsens0 3>; 4253 4254 trips { 4255 cpu2_alert0: trip-point0 { 4256 temperature = <90000>; 4257 hysteresis = <2000>; 4258 type = "passive"; 4259 }; 4260 4261 cpu2_alert1: trip-point1 { 4262 temperature = <95000>; 4263 hysteresis = <2000>; 4264 type = "passive"; 4265 }; 4266 4267 cpu2_crit: cpu_crit { 4268 temperature = <110000>; 4269 hysteresis = <1000>; 4270 type = "critical"; 4271 }; 4272 }; 4273 4274 cooling-maps { 4275 map0 { 4276 trip = <&cpu2_alert0>; 4277 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4278 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4279 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4280 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4281 }; 4282 map1 { 4283 trip = <&cpu2_alert1>; 4284 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4285 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4286 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4287 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4288 }; 4289 }; 4290 }; 4291 4292 cpu3-thermal { 4293 polling-delay-passive = <250>; 4294 polling-delay = <1000>; 4295 4296 thermal-sensors = <&tsens0 4>; 4297 4298 trips { 4299 cpu3_alert0: trip-point0 { 4300 temperature = <90000>; 4301 hysteresis = <2000>; 4302 type = "passive"; 4303 }; 4304 4305 cpu3_alert1: trip-point1 { 4306 temperature = <95000>; 4307 hysteresis = <2000>; 4308 type = "passive"; 4309 }; 4310 4311 cpu3_crit: cpu_crit { 4312 temperature = <110000>; 4313 hysteresis = <1000>; 4314 type = "critical"; 4315 }; 4316 }; 4317 4318 cooling-maps { 4319 map0 { 4320 trip = <&cpu3_alert0>; 4321 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4322 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4323 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4324 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4325 }; 4326 map1 { 4327 trip = <&cpu3_alert1>; 4328 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4329 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4330 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4331 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4332 }; 4333 }; 4334 }; 4335 4336 cpu4-top-thermal { 4337 polling-delay-passive = <250>; 4338 polling-delay = <1000>; 4339 4340 thermal-sensors = <&tsens0 7>; 4341 4342 trips { 4343 cpu4_top_alert0: trip-point0 { 4344 temperature = <90000>; 4345 hysteresis = <2000>; 4346 type = "passive"; 4347 }; 4348 4349 cpu4_top_alert1: trip-point1 { 4350 temperature = <95000>; 4351 hysteresis = <2000>; 4352 type = "passive"; 4353 }; 4354 4355 cpu4_top_crit: cpu_crit { 4356 temperature = <110000>; 4357 hysteresis = <1000>; 4358 type = "critical"; 4359 }; 4360 }; 4361 4362 cooling-maps { 4363 map0 { 4364 trip = <&cpu4_top_alert0>; 4365 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4366 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4367 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4368 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4369 }; 4370 map1 { 4371 trip = <&cpu4_top_alert1>; 4372 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4373 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4374 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4375 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4376 }; 4377 }; 4378 }; 4379 4380 cpu5-top-thermal { 4381 polling-delay-passive = <250>; 4382 polling-delay = <1000>; 4383 4384 thermal-sensors = <&tsens0 8>; 4385 4386 trips { 4387 cpu5_top_alert0: trip-point0 { 4388 temperature = <90000>; 4389 hysteresis = <2000>; 4390 type = "passive"; 4391 }; 4392 4393 cpu5_top_alert1: trip-point1 { 4394 temperature = <95000>; 4395 hysteresis = <2000>; 4396 type = "passive"; 4397 }; 4398 4399 cpu5_top_crit: cpu_crit { 4400 temperature = <110000>; 4401 hysteresis = <1000>; 4402 type = "critical"; 4403 }; 4404 }; 4405 4406 cooling-maps { 4407 map0 { 4408 trip = <&cpu5_top_alert0>; 4409 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4410 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4411 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4412 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4413 }; 4414 map1 { 4415 trip = <&cpu5_top_alert1>; 4416 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4417 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4418 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4419 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4420 }; 4421 }; 4422 }; 4423 4424 cpu6-top-thermal { 4425 polling-delay-passive = <250>; 4426 polling-delay = <1000>; 4427 4428 thermal-sensors = <&tsens0 9>; 4429 4430 trips { 4431 cpu6_top_alert0: trip-point0 { 4432 temperature = <90000>; 4433 hysteresis = <2000>; 4434 type = "passive"; 4435 }; 4436 4437 cpu6_top_alert1: trip-point1 { 4438 temperature = <95000>; 4439 hysteresis = <2000>; 4440 type = "passive"; 4441 }; 4442 4443 cpu6_top_crit: cpu_crit { 4444 temperature = <110000>; 4445 hysteresis = <1000>; 4446 type = "critical"; 4447 }; 4448 }; 4449 4450 cooling-maps { 4451 map0 { 4452 trip = <&cpu6_top_alert0>; 4453 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4454 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4455 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4456 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4457 }; 4458 map1 { 4459 trip = <&cpu6_top_alert1>; 4460 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4461 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4462 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4463 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4464 }; 4465 }; 4466 }; 4467 4468 cpu7-top-thermal { 4469 polling-delay-passive = <250>; 4470 polling-delay = <1000>; 4471 4472 thermal-sensors = <&tsens0 10>; 4473 4474 trips { 4475 cpu7_top_alert0: trip-point0 { 4476 temperature = <90000>; 4477 hysteresis = <2000>; 4478 type = "passive"; 4479 }; 4480 4481 cpu7_top_alert1: trip-point1 { 4482 temperature = <95000>; 4483 hysteresis = <2000>; 4484 type = "passive"; 4485 }; 4486 4487 cpu7_top_crit: cpu_crit { 4488 temperature = <110000>; 4489 hysteresis = <1000>; 4490 type = "critical"; 4491 }; 4492 }; 4493 4494 cooling-maps { 4495 map0 { 4496 trip = <&cpu7_top_alert0>; 4497 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4498 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4499 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4500 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4501 }; 4502 map1 { 4503 trip = <&cpu7_top_alert1>; 4504 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4505 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4506 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4507 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4508 }; 4509 }; 4510 }; 4511 4512 cpu4-bottom-thermal { 4513 polling-delay-passive = <250>; 4514 polling-delay = <1000>; 4515 4516 thermal-sensors = <&tsens0 11>; 4517 4518 trips { 4519 cpu4_bottom_alert0: trip-point0 { 4520 temperature = <90000>; 4521 hysteresis = <2000>; 4522 type = "passive"; 4523 }; 4524 4525 cpu4_bottom_alert1: trip-point1 { 4526 temperature = <95000>; 4527 hysteresis = <2000>; 4528 type = "passive"; 4529 }; 4530 4531 cpu4_bottom_crit: cpu_crit { 4532 temperature = <110000>; 4533 hysteresis = <1000>; 4534 type = "critical"; 4535 }; 4536 }; 4537 4538 cooling-maps { 4539 map0 { 4540 trip = <&cpu4_bottom_alert0>; 4541 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4542 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4543 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4544 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4545 }; 4546 map1 { 4547 trip = <&cpu4_bottom_alert1>; 4548 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4549 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4550 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4551 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4552 }; 4553 }; 4554 }; 4555 4556 cpu5-bottom-thermal { 4557 polling-delay-passive = <250>; 4558 polling-delay = <1000>; 4559 4560 thermal-sensors = <&tsens0 12>; 4561 4562 trips { 4563 cpu5_bottom_alert0: trip-point0 { 4564 temperature = <90000>; 4565 hysteresis = <2000>; 4566 type = "passive"; 4567 }; 4568 4569 cpu5_bottom_alert1: trip-point1 { 4570 temperature = <95000>; 4571 hysteresis = <2000>; 4572 type = "passive"; 4573 }; 4574 4575 cpu5_bottom_crit: cpu_crit { 4576 temperature = <110000>; 4577 hysteresis = <1000>; 4578 type = "critical"; 4579 }; 4580 }; 4581 4582 cooling-maps { 4583 map0 { 4584 trip = <&cpu5_bottom_alert0>; 4585 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4586 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4587 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4588 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4589 }; 4590 map1 { 4591 trip = <&cpu5_bottom_alert1>; 4592 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4593 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4594 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4595 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4596 }; 4597 }; 4598 }; 4599 4600 cpu6-bottom-thermal { 4601 polling-delay-passive = <250>; 4602 polling-delay = <1000>; 4603 4604 thermal-sensors = <&tsens0 13>; 4605 4606 trips { 4607 cpu6_bottom_alert0: trip-point0 { 4608 temperature = <90000>; 4609 hysteresis = <2000>; 4610 type = "passive"; 4611 }; 4612 4613 cpu6_bottom_alert1: trip-point1 { 4614 temperature = <95000>; 4615 hysteresis = <2000>; 4616 type = "passive"; 4617 }; 4618 4619 cpu6_bottom_crit: cpu_crit { 4620 temperature = <110000>; 4621 hysteresis = <1000>; 4622 type = "critical"; 4623 }; 4624 }; 4625 4626 cooling-maps { 4627 map0 { 4628 trip = <&cpu6_bottom_alert0>; 4629 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4630 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4631 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4632 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4633 }; 4634 map1 { 4635 trip = <&cpu6_bottom_alert1>; 4636 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4637 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4638 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4639 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4640 }; 4641 }; 4642 }; 4643 4644 cpu7-bottom-thermal { 4645 polling-delay-passive = <250>; 4646 polling-delay = <1000>; 4647 4648 thermal-sensors = <&tsens0 14>; 4649 4650 trips { 4651 cpu7_bottom_alert0: trip-point0 { 4652 temperature = <90000>; 4653 hysteresis = <2000>; 4654 type = "passive"; 4655 }; 4656 4657 cpu7_bottom_alert1: trip-point1 { 4658 temperature = <95000>; 4659 hysteresis = <2000>; 4660 type = "passive"; 4661 }; 4662 4663 cpu7_bottom_crit: cpu_crit { 4664 temperature = <110000>; 4665 hysteresis = <1000>; 4666 type = "critical"; 4667 }; 4668 }; 4669 4670 cooling-maps { 4671 map0 { 4672 trip = <&cpu7_bottom_alert0>; 4673 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4674 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4675 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4676 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4677 }; 4678 map1 { 4679 trip = <&cpu7_bottom_alert1>; 4680 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4681 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4682 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4683 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4684 }; 4685 }; 4686 }; 4687 4688 aoss0-thermal { 4689 polling-delay-passive = <250>; 4690 polling-delay = <1000>; 4691 4692 thermal-sensors = <&tsens0 0>; 4693 4694 trips { 4695 aoss0_alert0: trip-point0 { 4696 temperature = <90000>; 4697 hysteresis = <2000>; 4698 type = "hot"; 4699 }; 4700 }; 4701 }; 4702 4703 cluster0-thermal { 4704 polling-delay-passive = <250>; 4705 polling-delay = <1000>; 4706 4707 thermal-sensors = <&tsens0 5>; 4708 4709 trips { 4710 cluster0_alert0: trip-point0 { 4711 temperature = <90000>; 4712 hysteresis = <2000>; 4713 type = "hot"; 4714 }; 4715 cluster0_crit: cluster0_crit { 4716 temperature = <110000>; 4717 hysteresis = <2000>; 4718 type = "critical"; 4719 }; 4720 }; 4721 }; 4722 4723 cluster1-thermal { 4724 polling-delay-passive = <250>; 4725 polling-delay = <1000>; 4726 4727 thermal-sensors = <&tsens0 6>; 4728 4729 trips { 4730 cluster1_alert0: trip-point0 { 4731 temperature = <90000>; 4732 hysteresis = <2000>; 4733 type = "hot"; 4734 }; 4735 cluster1_crit: cluster1_crit { 4736 temperature = <110000>; 4737 hysteresis = <2000>; 4738 type = "critical"; 4739 }; 4740 }; 4741 }; 4742 4743 gpu-top-thermal { 4744 polling-delay-passive = <250>; 4745 polling-delay = <1000>; 4746 4747 thermal-sensors = <&tsens0 15>; 4748 4749 trips { 4750 gpu1_alert0: trip-point0 { 4751 temperature = <90000>; 4752 hysteresis = <2000>; 4753 type = "hot"; 4754 }; 4755 }; 4756 }; 4757 4758 aoss1-thermal { 4759 polling-delay-passive = <250>; 4760 polling-delay = <1000>; 4761 4762 thermal-sensors = <&tsens1 0>; 4763 4764 trips { 4765 aoss1_alert0: trip-point0 { 4766 temperature = <90000>; 4767 hysteresis = <2000>; 4768 type = "hot"; 4769 }; 4770 }; 4771 }; 4772 4773 wlan-thermal { 4774 polling-delay-passive = <250>; 4775 polling-delay = <1000>; 4776 4777 thermal-sensors = <&tsens1 1>; 4778 4779 trips { 4780 wlan_alert0: trip-point0 { 4781 temperature = <90000>; 4782 hysteresis = <2000>; 4783 type = "hot"; 4784 }; 4785 }; 4786 }; 4787 4788 video-thermal { 4789 polling-delay-passive = <250>; 4790 polling-delay = <1000>; 4791 4792 thermal-sensors = <&tsens1 2>; 4793 4794 trips { 4795 video_alert0: trip-point0 { 4796 temperature = <90000>; 4797 hysteresis = <2000>; 4798 type = "hot"; 4799 }; 4800 }; 4801 }; 4802 4803 mem-thermal { 4804 polling-delay-passive = <250>; 4805 polling-delay = <1000>; 4806 4807 thermal-sensors = <&tsens1 3>; 4808 4809 trips { 4810 mem_alert0: trip-point0 { 4811 temperature = <90000>; 4812 hysteresis = <2000>; 4813 type = "hot"; 4814 }; 4815 }; 4816 }; 4817 4818 q6-hvx-thermal { 4819 polling-delay-passive = <250>; 4820 polling-delay = <1000>; 4821 4822 thermal-sensors = <&tsens1 4>; 4823 4824 trips { 4825 q6_hvx_alert0: trip-point0 { 4826 temperature = <90000>; 4827 hysteresis = <2000>; 4828 type = "hot"; 4829 }; 4830 }; 4831 }; 4832 4833 camera-thermal { 4834 polling-delay-passive = <250>; 4835 polling-delay = <1000>; 4836 4837 thermal-sensors = <&tsens1 5>; 4838 4839 trips { 4840 camera_alert0: trip-point0 { 4841 temperature = <90000>; 4842 hysteresis = <2000>; 4843 type = "hot"; 4844 }; 4845 }; 4846 }; 4847 4848 compute-thermal { 4849 polling-delay-passive = <250>; 4850 polling-delay = <1000>; 4851 4852 thermal-sensors = <&tsens1 6>; 4853 4854 trips { 4855 compute_alert0: trip-point0 { 4856 temperature = <90000>; 4857 hysteresis = <2000>; 4858 type = "hot"; 4859 }; 4860 }; 4861 }; 4862 4863 modem-thermal { 4864 polling-delay-passive = <250>; 4865 polling-delay = <1000>; 4866 4867 thermal-sensors = <&tsens1 7>; 4868 4869 trips { 4870 modem_alert0: trip-point0 { 4871 temperature = <90000>; 4872 hysteresis = <2000>; 4873 type = "hot"; 4874 }; 4875 }; 4876 }; 4877 4878 npu-thermal { 4879 polling-delay-passive = <250>; 4880 polling-delay = <1000>; 4881 4882 thermal-sensors = <&tsens1 8>; 4883 4884 trips { 4885 npu_alert0: trip-point0 { 4886 temperature = <90000>; 4887 hysteresis = <2000>; 4888 type = "hot"; 4889 }; 4890 }; 4891 }; 4892 4893 modem-vec-thermal { 4894 polling-delay-passive = <250>; 4895 polling-delay = <1000>; 4896 4897 thermal-sensors = <&tsens1 9>; 4898 4899 trips { 4900 modem_vec_alert0: trip-point0 { 4901 temperature = <90000>; 4902 hysteresis = <2000>; 4903 type = "hot"; 4904 }; 4905 }; 4906 }; 4907 4908 modem-scl-thermal { 4909 polling-delay-passive = <250>; 4910 polling-delay = <1000>; 4911 4912 thermal-sensors = <&tsens1 10>; 4913 4914 trips { 4915 modem_scl_alert0: trip-point0 { 4916 temperature = <90000>; 4917 hysteresis = <2000>; 4918 type = "hot"; 4919 }; 4920 }; 4921 }; 4922 4923 gpu-bottom-thermal { 4924 polling-delay-passive = <250>; 4925 polling-delay = <1000>; 4926 4927 thermal-sensors = <&tsens1 11>; 4928 4929 trips { 4930 gpu2_alert0: trip-point0 { 4931 temperature = <90000>; 4932 hysteresis = <2000>; 4933 type = "hot"; 4934 }; 4935 }; 4936 }; 4937 }; 4938}; 4939