1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/power/qcom-aoss-qmp.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,gcc-sm8150.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 clocks { 24 xo_board: xo-board { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <38400000>; 28 clock-output-names = "xo_board"; 29 }; 30 31 sleep_clk: sleep-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <32764>; 35 clock-output-names = "sleep_clk"; 36 }; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 CPU0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "qcom,kryo485"; 46 reg = <0x0 0x0>; 47 enable-method = "psci"; 48 next-level-cache = <&L2_0>; 49 qcom,freq-domain = <&cpufreq_hw 0>; 50 #cooling-cells = <2>; 51 L2_0: l2-cache { 52 compatible = "cache"; 53 next-level-cache = <&L3_0>; 54 L3_0: l3-cache { 55 compatible = "cache"; 56 }; 57 }; 58 }; 59 60 CPU1: cpu@100 { 61 device_type = "cpu"; 62 compatible = "qcom,kryo485"; 63 reg = <0x0 0x100>; 64 enable-method = "psci"; 65 next-level-cache = <&L2_100>; 66 qcom,freq-domain = <&cpufreq_hw 0>; 67 #cooling-cells = <2>; 68 L2_100: l2-cache { 69 compatible = "cache"; 70 next-level-cache = <&L3_0>; 71 }; 72 73 }; 74 75 CPU2: cpu@200 { 76 device_type = "cpu"; 77 compatible = "qcom,kryo485"; 78 reg = <0x0 0x200>; 79 enable-method = "psci"; 80 next-level-cache = <&L2_200>; 81 qcom,freq-domain = <&cpufreq_hw 0>; 82 #cooling-cells = <2>; 83 L2_200: l2-cache { 84 compatible = "cache"; 85 next-level-cache = <&L3_0>; 86 }; 87 }; 88 89 CPU3: cpu@300 { 90 device_type = "cpu"; 91 compatible = "qcom,kryo485"; 92 reg = <0x0 0x300>; 93 enable-method = "psci"; 94 next-level-cache = <&L2_300>; 95 qcom,freq-domain = <&cpufreq_hw 0>; 96 #cooling-cells = <2>; 97 L2_300: l2-cache { 98 compatible = "cache"; 99 next-level-cache = <&L3_0>; 100 }; 101 }; 102 103 CPU4: cpu@400 { 104 device_type = "cpu"; 105 compatible = "qcom,kryo485"; 106 reg = <0x0 0x400>; 107 enable-method = "psci"; 108 next-level-cache = <&L2_400>; 109 qcom,freq-domain = <&cpufreq_hw 1>; 110 #cooling-cells = <2>; 111 L2_400: l2-cache { 112 compatible = "cache"; 113 next-level-cache = <&L3_0>; 114 }; 115 }; 116 117 CPU5: cpu@500 { 118 device_type = "cpu"; 119 compatible = "qcom,kryo485"; 120 reg = <0x0 0x500>; 121 enable-method = "psci"; 122 next-level-cache = <&L2_500>; 123 qcom,freq-domain = <&cpufreq_hw 1>; 124 #cooling-cells = <2>; 125 L2_500: l2-cache { 126 compatible = "cache"; 127 next-level-cache = <&L3_0>; 128 }; 129 }; 130 131 CPU6: cpu@600 { 132 device_type = "cpu"; 133 compatible = "qcom,kryo485"; 134 reg = <0x0 0x600>; 135 enable-method = "psci"; 136 next-level-cache = <&L2_600>; 137 qcom,freq-domain = <&cpufreq_hw 1>; 138 #cooling-cells = <2>; 139 L2_600: l2-cache { 140 compatible = "cache"; 141 next-level-cache = <&L3_0>; 142 }; 143 }; 144 145 CPU7: cpu@700 { 146 device_type = "cpu"; 147 compatible = "qcom,kryo485"; 148 reg = <0x0 0x700>; 149 enable-method = "psci"; 150 next-level-cache = <&L2_700>; 151 qcom,freq-domain = <&cpufreq_hw 2>; 152 #cooling-cells = <2>; 153 L2_700: l2-cache { 154 compatible = "cache"; 155 next-level-cache = <&L3_0>; 156 }; 157 }; 158 }; 159 160 firmware { 161 scm: scm { 162 compatible = "qcom,scm-sm8150", "qcom,scm"; 163 #reset-cells = <1>; 164 }; 165 }; 166 167 tcsr_mutex: hwlock { 168 compatible = "qcom,tcsr-mutex"; 169 syscon = <&tcsr_mutex_regs 0 0x1000>; 170 #hwlock-cells = <1>; 171 }; 172 173 memory@80000000 { 174 device_type = "memory"; 175 /* We expect the bootloader to fill in the size */ 176 reg = <0x0 0x80000000 0x0 0x0>; 177 }; 178 179 pmu { 180 compatible = "arm,armv8-pmuv3"; 181 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 182 }; 183 184 psci { 185 compatible = "arm,psci-1.0"; 186 method = "smc"; 187 }; 188 189 reserved-memory { 190 #address-cells = <2>; 191 #size-cells = <2>; 192 ranges; 193 194 hyp_mem: memory@85700000 { 195 reg = <0x0 0x85700000 0x0 0x600000>; 196 no-map; 197 }; 198 199 xbl_mem: memory@85d00000 { 200 reg = <0x0 0x85d00000 0x0 0x140000>; 201 no-map; 202 }; 203 204 aop_mem: memory@85f00000 { 205 reg = <0x0 0x85f00000 0x0 0x20000>; 206 no-map; 207 }; 208 209 aop_cmd_db: memory@85f20000 { 210 compatible = "qcom,cmd-db"; 211 reg = <0x0 0x85f20000 0x0 0x20000>; 212 no-map; 213 }; 214 215 smem_mem: memory@86000000 { 216 reg = <0x0 0x86000000 0x0 0x200000>; 217 no-map; 218 }; 219 220 tz_mem: memory@86200000 { 221 reg = <0x0 0x86200000 0x0 0x3900000>; 222 no-map; 223 }; 224 225 rmtfs_mem: memory@89b00000 { 226 compatible = "qcom,rmtfs-mem"; 227 reg = <0x0 0x89b00000 0x0 0x200000>; 228 no-map; 229 230 qcom,client-id = <1>; 231 qcom,vmid = <15>; 232 }; 233 234 camera_mem: memory@8b700000 { 235 reg = <0x0 0x8b700000 0x0 0x500000>; 236 no-map; 237 }; 238 239 wlan_mem: memory@8bc00000 { 240 reg = <0x0 0x8bc00000 0x0 0x180000>; 241 no-map; 242 }; 243 244 npu_mem: memory@8bd80000 { 245 reg = <0x0 0x8bd80000 0x0 0x80000>; 246 no-map; 247 }; 248 249 adsp_mem: memory@8be00000 { 250 reg = <0x0 0x8be00000 0x0 0x1a00000>; 251 no-map; 252 }; 253 254 mpss_mem: memory@8d800000 { 255 reg = <0x0 0x8d800000 0x0 0x9600000>; 256 no-map; 257 }; 258 259 venus_mem: memory@96e00000 { 260 reg = <0x0 0x96e00000 0x0 0x500000>; 261 no-map; 262 }; 263 264 slpi_mem: memory@97300000 { 265 reg = <0x0 0x97300000 0x0 0x1400000>; 266 no-map; 267 }; 268 269 ipa_fw_mem: memory@98700000 { 270 reg = <0x0 0x98700000 0x0 0x10000>; 271 no-map; 272 }; 273 274 ipa_gsi_mem: memory@98710000 { 275 reg = <0x0 0x98710000 0x0 0x5000>; 276 no-map; 277 }; 278 279 gpu_mem: memory@98715000 { 280 reg = <0x0 0x98715000 0x0 0x2000>; 281 no-map; 282 }; 283 284 spss_mem: memory@98800000 { 285 reg = <0x0 0x98800000 0x0 0x100000>; 286 no-map; 287 }; 288 289 cdsp_mem: memory@98900000 { 290 reg = <0x0 0x98900000 0x0 0x1400000>; 291 no-map; 292 }; 293 294 qseecom_mem: memory@9e400000 { 295 reg = <0x0 0x9e400000 0x0 0x1400000>; 296 no-map; 297 }; 298 }; 299 300 smem { 301 compatible = "qcom,smem"; 302 memory-region = <&smem_mem>; 303 hwlocks = <&tcsr_mutex 3>; 304 }; 305 306 smp2p-cdsp { 307 compatible = "qcom,smp2p"; 308 qcom,smem = <94>, <432>; 309 310 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 311 312 mboxes = <&apss_shared 6>; 313 314 qcom,local-pid = <0>; 315 qcom,remote-pid = <5>; 316 317 cdsp_smp2p_out: master-kernel { 318 qcom,entry-name = "master-kernel"; 319 #qcom,smem-state-cells = <1>; 320 }; 321 322 cdsp_smp2p_in: slave-kernel { 323 qcom,entry-name = "slave-kernel"; 324 325 interrupt-controller; 326 #interrupt-cells = <2>; 327 }; 328 }; 329 330 smp2p-lpass { 331 compatible = "qcom,smp2p"; 332 qcom,smem = <443>, <429>; 333 334 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 335 336 mboxes = <&apss_shared 10>; 337 338 qcom,local-pid = <0>; 339 qcom,remote-pid = <2>; 340 341 adsp_smp2p_out: master-kernel { 342 qcom,entry-name = "master-kernel"; 343 #qcom,smem-state-cells = <1>; 344 }; 345 346 adsp_smp2p_in: slave-kernel { 347 qcom,entry-name = "slave-kernel"; 348 349 interrupt-controller; 350 #interrupt-cells = <2>; 351 }; 352 }; 353 354 smp2p-mpss { 355 compatible = "qcom,smp2p"; 356 qcom,smem = <435>, <428>; 357 358 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 359 360 mboxes = <&apss_shared 14>; 361 362 qcom,local-pid = <0>; 363 qcom,remote-pid = <1>; 364 365 modem_smp2p_out: master-kernel { 366 qcom,entry-name = "master-kernel"; 367 #qcom,smem-state-cells = <1>; 368 }; 369 370 modem_smp2p_in: slave-kernel { 371 qcom,entry-name = "slave-kernel"; 372 373 interrupt-controller; 374 #interrupt-cells = <2>; 375 }; 376 }; 377 378 smp2p-slpi { 379 compatible = "qcom,smp2p"; 380 qcom,smem = <481>, <430>; 381 382 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 383 384 mboxes = <&apss_shared 26>; 385 386 qcom,local-pid = <0>; 387 qcom,remote-pid = <3>; 388 389 slpi_smp2p_out: master-kernel { 390 qcom,entry-name = "master-kernel"; 391 #qcom,smem-state-cells = <1>; 392 }; 393 394 slpi_smp2p_in: slave-kernel { 395 qcom,entry-name = "slave-kernel"; 396 397 interrupt-controller; 398 #interrupt-cells = <2>; 399 }; 400 }; 401 402 soc: soc@0 { 403 #address-cells = <2>; 404 #size-cells = <2>; 405 ranges = <0 0 0 0 0x10 0>; 406 dma-ranges = <0 0 0 0 0x10 0>; 407 compatible = "simple-bus"; 408 409 gcc: clock-controller@100000 { 410 compatible = "qcom,gcc-sm8150"; 411 reg = <0x0 0x00100000 0x0 0x1f0000>; 412 #clock-cells = <1>; 413 #reset-cells = <1>; 414 #power-domain-cells = <1>; 415 clock-names = "bi_tcxo", 416 "sleep_clk"; 417 clocks = <&rpmhcc RPMH_CXO_CLK>, 418 <&sleep_clk>; 419 }; 420 421 qupv3_id_1: geniqup@ac0000 { 422 compatible = "qcom,geni-se-qup"; 423 reg = <0x0 0x00ac0000 0x0 0x6000>; 424 clock-names = "m-ahb", "s-ahb"; 425 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 426 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 427 #address-cells = <2>; 428 #size-cells = <2>; 429 ranges; 430 status = "disabled"; 431 432 uart2: serial@a90000 { 433 compatible = "qcom,geni-debug-uart"; 434 reg = <0x0 0x00a90000 0x0 0x4000>; 435 clock-names = "se"; 436 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 437 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 438 status = "disabled"; 439 }; 440 }; 441 442 ufs_mem_hc: ufshc@1d84000 { 443 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 444 "jedec,ufs-2.0"; 445 reg = <0 0x01d84000 0 0x2500>; 446 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 447 phys = <&ufs_mem_phy_lanes>; 448 phy-names = "ufsphy"; 449 lanes-per-direction = <2>; 450 #reset-cells = <1>; 451 resets = <&gcc GCC_UFS_PHY_BCR>; 452 reset-names = "rst"; 453 454 clock-names = 455 "core_clk", 456 "bus_aggr_clk", 457 "iface_clk", 458 "core_clk_unipro", 459 "ref_clk", 460 "tx_lane0_sync_clk", 461 "rx_lane0_sync_clk", 462 "rx_lane1_sync_clk"; 463 clocks = 464 <&gcc GCC_UFS_PHY_AXI_CLK>, 465 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 466 <&gcc GCC_UFS_PHY_AHB_CLK>, 467 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 468 <&rpmhcc RPMH_CXO_CLK>, 469 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 470 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 471 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 472 freq-table-hz = 473 <37500000 300000000>, 474 <0 0>, 475 <0 0>, 476 <37500000 300000000>, 477 <0 0>, 478 <0 0>, 479 <0 0>, 480 <0 0>; 481 482 status = "disabled"; 483 }; 484 485 ufs_mem_phy: phy@1d87000 { 486 compatible = "qcom,sm8150-qmp-ufs-phy"; 487 reg = <0 0x01d87000 0 0x1c0>; 488 #address-cells = <2>; 489 #size-cells = <2>; 490 ranges; 491 clock-names = "ref", 492 "ref_aux"; 493 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 494 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 495 496 resets = <&ufs_mem_hc 0>; 497 reset-names = "ufsphy"; 498 status = "disabled"; 499 500 ufs_mem_phy_lanes: lanes@1d87400 { 501 reg = <0 0x01d87400 0 0x108>, 502 <0 0x01d87600 0 0x1e0>, 503 <0 0x01d87c00 0 0x1dc>, 504 <0 0x01d87800 0 0x108>, 505 <0 0x01d87a00 0 0x1e0>; 506 #phy-cells = <0>; 507 }; 508 }; 509 510 tcsr_mutex_regs: syscon@1f40000 { 511 compatible = "syscon"; 512 reg = <0x0 0x01f40000 0x0 0x40000>; 513 }; 514 515 remoteproc_slpi: remoteproc@2400000 { 516 compatible = "qcom,sm8150-slpi-pas"; 517 reg = <0x0 0x02400000 0x0 0x4040>; 518 519 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 520 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 521 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 522 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 523 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 524 interrupt-names = "wdog", "fatal", "ready", 525 "handover", "stop-ack"; 526 527 clocks = <&rpmhcc RPMH_CXO_CLK>; 528 clock-names = "xo"; 529 530 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, 531 <&rpmhpd 3>, 532 <&rpmhpd 2>; 533 power-domain-names = "load_state", "lcx", "lmx"; 534 535 memory-region = <&slpi_mem>; 536 537 qcom,smem-states = <&slpi_smp2p_out 0>; 538 qcom,smem-state-names = "stop"; 539 540 status = "disabled"; 541 542 glink-edge { 543 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 544 label = "dsps"; 545 qcom,remote-pid = <3>; 546 mboxes = <&apss_shared 24>; 547 }; 548 }; 549 550 gpu: gpu@2c00000 { 551 /* 552 * note: the amd,imageon compatible makes it possible 553 * to use the drm/msm driver without the display node, 554 * make sure to remove it when display node is added 555 */ 556 compatible = "qcom,adreno-640.1", 557 "qcom,adreno", 558 "amd,imageon"; 559 #stream-id-cells = <16>; 560 561 reg = <0 0x02c00000 0 0x40000>; 562 reg-names = "kgsl_3d0_reg_memory"; 563 564 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 565 566 iommus = <&adreno_smmu 0 0x401>; 567 568 operating-points-v2 = <&gpu_opp_table>; 569 570 qcom,gmu = <&gmu>; 571 572 zap-shader { 573 memory-region = <&gpu_mem>; 574 }; 575 576 /* note: downstream checks gpu binning for 675 Mhz */ 577 gpu_opp_table: opp-table { 578 compatible = "operating-points-v2"; 579 580 opp-675000000 { 581 opp-hz = /bits/ 64 <675000000>; 582 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 583 }; 584 585 opp-585000000 { 586 opp-hz = /bits/ 64 <585000000>; 587 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 588 }; 589 590 opp-499200000 { 591 opp-hz = /bits/ 64 <499200000>; 592 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 593 }; 594 595 opp-427000000 { 596 opp-hz = /bits/ 64 <427000000>; 597 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 598 }; 599 600 opp-345000000 { 601 opp-hz = /bits/ 64 <345000000>; 602 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 603 }; 604 605 opp-257000000 { 606 opp-hz = /bits/ 64 <257000000>; 607 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 608 }; 609 }; 610 }; 611 612 gmu: gmu@2c6a000 { 613 compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 614 615 reg = <0 0x02c6a000 0 0x30000>, 616 <0 0x0b290000 0 0x10000>, 617 <0 0x0b490000 0 0x10000>; 618 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 619 620 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 622 interrupt-names = "hfi", "gmu"; 623 624 clocks = <&gpucc 0>, 625 <&gpucc 3>, 626 <&gpucc 6>, 627 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 628 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 629 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 630 631 power-domains = <&gpucc 0>, 632 <&gpucc 1>; 633 power-domain-names = "cx", "gx"; 634 635 iommus = <&adreno_smmu 5 0x400>; 636 637 operating-points-v2 = <&gmu_opp_table>; 638 639 gmu_opp_table: opp-table { 640 compatible = "operating-points-v2"; 641 642 opp-200000000 { 643 opp-hz = /bits/ 64 <200000000>; 644 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 645 }; 646 }; 647 }; 648 649 gpucc: clock-controller@2c90000 { 650 compatible = "qcom,sm8150-gpucc"; 651 reg = <0 0x02c90000 0 0x9000>; 652 clocks = <&rpmhcc RPMH_CXO_CLK>, 653 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 654 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 655 clock-names = "bi_tcxo", 656 "gcc_gpu_gpll0_clk_src", 657 "gcc_gpu_gpll0_div_clk_src"; 658 #clock-cells = <1>; 659 #reset-cells = <1>; 660 #power-domain-cells = <1>; 661 }; 662 663 adreno_smmu: iommu@2ca0000 { 664 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 665 reg = <0 0x02ca0000 0 0x10000>; 666 #iommu-cells = <2>; 667 #global-interrupts = <1>; 668 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&gpucc 0>, 678 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 679 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 680 clock-names = "ahb", "bus", "iface"; 681 682 power-domains = <&gpucc 0>; 683 }; 684 685 tlmm: pinctrl@3100000 { 686 compatible = "qcom,sm8150-pinctrl"; 687 reg = <0x0 0x03100000 0x0 0x300000>, 688 <0x0 0x03500000 0x0 0x300000>, 689 <0x0 0x03900000 0x0 0x300000>, 690 <0x0 0x03D00000 0x0 0x300000>; 691 reg-names = "west", "east", "north", "south"; 692 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 693 gpio-ranges = <&tlmm 0 0 175>; 694 gpio-controller; 695 #gpio-cells = <2>; 696 interrupt-controller; 697 #interrupt-cells = <2>; 698 }; 699 700 remoteproc_mpss: remoteproc@4080000 { 701 compatible = "qcom,sm8150-mpss-pas"; 702 reg = <0x0 0x04080000 0x0 0x4040>; 703 704 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 705 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 706 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 707 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 708 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 709 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 710 interrupt-names = "wdog", "fatal", "ready", "handover", 711 "stop-ack", "shutdown-ack"; 712 713 clocks = <&rpmhcc RPMH_CXO_CLK>; 714 clock-names = "xo"; 715 716 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, 717 <&rpmhpd 7>, 718 <&rpmhpd 0>; 719 power-domain-names = "load_state", "cx", "mss"; 720 721 memory-region = <&mpss_mem>; 722 723 qcom,smem-states = <&modem_smp2p_out 0>; 724 qcom,smem-state-names = "stop"; 725 726 glink-edge { 727 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 728 label = "modem"; 729 qcom,remote-pid = <1>; 730 mboxes = <&apss_shared 12>; 731 }; 732 }; 733 734 remoteproc_cdsp: remoteproc@8300000 { 735 compatible = "qcom,sm8150-cdsp-pas"; 736 reg = <0x0 0x08300000 0x0 0x4040>; 737 738 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 739 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 740 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 741 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 742 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 743 interrupt-names = "wdog", "fatal", "ready", 744 "handover", "stop-ack"; 745 746 clocks = <&rpmhcc RPMH_CXO_CLK>; 747 clock-names = "xo"; 748 749 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, 750 <&rpmhpd 7>; 751 power-domain-names = "load_state", "cx"; 752 753 memory-region = <&cdsp_mem>; 754 755 qcom,smem-states = <&cdsp_smp2p_out 0>; 756 qcom,smem-state-names = "stop"; 757 758 status = "disabled"; 759 760 glink-edge { 761 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 762 label = "cdsp"; 763 qcom,remote-pid = <5>; 764 mboxes = <&apss_shared 4>; 765 }; 766 }; 767 768 usb_1_hsphy: phy@88e2000 { 769 compatible = "qcom,sm8150-usb-hs-phy", 770 "qcom,usb-snps-hs-7nm-phy"; 771 reg = <0 0x088e2000 0 0x400>; 772 status = "disabled"; 773 #phy-cells = <0>; 774 775 clocks = <&rpmhcc RPMH_CXO_CLK>; 776 clock-names = "ref"; 777 778 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 779 }; 780 781 usb_1_qmpphy: phy@88e9000 { 782 compatible = "qcom,sm8150-qmp-usb3-phy"; 783 reg = <0 0x088e9000 0 0x18c>, 784 <0 0x088e8000 0 0x10>; 785 reg-names = "reg-base", "dp_com"; 786 status = "disabled"; 787 #clock-cells = <1>; 788 #address-cells = <2>; 789 #size-cells = <2>; 790 ranges; 791 792 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 793 <&rpmhcc RPMH_CXO_CLK>, 794 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 795 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 796 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 797 798 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 799 <&gcc GCC_USB3_PHY_PRIM_BCR>; 800 reset-names = "phy", "common"; 801 802 usb_1_ssphy: lanes@88e9200 { 803 reg = <0 0x088e9200 0 0x200>, 804 <0 0x088e9400 0 0x200>, 805 <0 0x088e9c00 0 0x218>, 806 <0 0x088e9600 0 0x200>, 807 <0 0x088e9800 0 0x200>, 808 <0 0x088e9a00 0 0x100>; 809 #phy-cells = <0>; 810 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 811 clock-names = "pipe0"; 812 clock-output-names = "usb3_phy_pipe_clk_src"; 813 }; 814 }; 815 816 usb_1: usb@a6f8800 { 817 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 818 reg = <0 0x0a6f8800 0 0x400>; 819 status = "disabled"; 820 #address-cells = <2>; 821 #size-cells = <2>; 822 ranges; 823 dma-ranges; 824 825 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 826 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 827 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 828 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 829 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 830 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 831 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 832 "sleep", "xo"; 833 834 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 835 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 836 assigned-clock-rates = <19200000>, <150000000>; 837 838 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 842 interrupt-names = "hs_phy_irq", "ss_phy_irq", 843 "dm_hs_phy_irq", "dp_hs_phy_irq"; 844 845 power-domains = <&gcc USB30_PRIM_GDSC>; 846 847 resets = <&gcc GCC_USB30_PRIM_BCR>; 848 849 usb_1_dwc3: dwc3@a600000 { 850 compatible = "snps,dwc3"; 851 reg = <0 0x0a600000 0 0xcd00>; 852 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 853 snps,dis_u2_susphy_quirk; 854 snps,dis_enblslpm_quirk; 855 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 856 phy-names = "usb2-phy", "usb3-phy"; 857 }; 858 }; 859 860 aoss_qmp: power-controller@c300000 { 861 compatible = "qcom,sm8150-aoss-qmp"; 862 reg = <0x0 0x0c300000 0x0 0x100000>; 863 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 864 mboxes = <&apss_shared 0>; 865 866 #clock-cells = <0>; 867 #power-domain-cells = <1>; 868 }; 869 870 tsens0: thermal-sensor@c263000 { 871 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 872 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 873 <0 0x0c222000 0 0x1ff>; /* SROT */ 874 #qcom,sensors = <16>; 875 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 877 interrupt-names = "uplow", "critical"; 878 #thermal-sensor-cells = <1>; 879 }; 880 881 tsens1: thermal-sensor@c265000 { 882 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 883 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 884 <0 0x0c223000 0 0x1ff>; /* SROT */ 885 #qcom,sensors = <8>; 886 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 888 interrupt-names = "uplow", "critical"; 889 #thermal-sensor-cells = <1>; 890 }; 891 892 spmi_bus: spmi@c440000 { 893 compatible = "qcom,spmi-pmic-arb"; 894 reg = <0x0 0x0c440000 0x0 0x0001100>, 895 <0x0 0x0c600000 0x0 0x2000000>, 896 <0x0 0x0e600000 0x0 0x0100000>, 897 <0x0 0x0e700000 0x0 0x00a0000>, 898 <0x0 0x0c40a000 0x0 0x0026000>; 899 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 900 interrupt-names = "periph_irq"; 901 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 902 qcom,ee = <0>; 903 qcom,channel = <0>; 904 #address-cells = <2>; 905 #size-cells = <0>; 906 interrupt-controller; 907 #interrupt-cells = <4>; 908 cell-index = <0>; 909 }; 910 911 remoteproc_adsp: remoteproc@17300000 { 912 compatible = "qcom,sm8150-adsp-pas"; 913 reg = <0x0 0x17300000 0x0 0x4040>; 914 915 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 916 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 917 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 918 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 919 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 920 interrupt-names = "wdog", "fatal", "ready", 921 "handover", "stop-ack"; 922 923 clocks = <&rpmhcc RPMH_CXO_CLK>; 924 clock-names = "xo"; 925 926 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, 927 <&rpmhpd 7>; 928 power-domain-names = "load_state", "cx"; 929 930 memory-region = <&adsp_mem>; 931 932 qcom,smem-states = <&adsp_smp2p_out 0>; 933 qcom,smem-state-names = "stop"; 934 935 status = "disabled"; 936 937 glink-edge { 938 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 939 label = "lpass"; 940 qcom,remote-pid = <2>; 941 mboxes = <&apss_shared 8>; 942 }; 943 }; 944 945 intc: interrupt-controller@17a00000 { 946 compatible = "arm,gic-v3"; 947 interrupt-controller; 948 #interrupt-cells = <3>; 949 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 950 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 951 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 952 }; 953 954 apss_shared: mailbox@17c00000 { 955 compatible = "qcom,sm8150-apss-shared"; 956 reg = <0x0 0x17c00000 0x0 0x1000>; 957 #mbox-cells = <1>; 958 }; 959 960 watchdog@17c10000 { 961 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 962 reg = <0 0x17c10000 0 0x1000>; 963 clocks = <&sleep_clk>; 964 }; 965 966 timer@17c20000 { 967 #address-cells = <2>; 968 #size-cells = <2>; 969 ranges; 970 compatible = "arm,armv7-timer-mem"; 971 reg = <0x0 0x17c20000 0x0 0x1000>; 972 clock-frequency = <19200000>; 973 974 frame@17c21000{ 975 frame-number = <0>; 976 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 978 reg = <0x0 0x17c21000 0x0 0x1000>, 979 <0x0 0x17c22000 0x0 0x1000>; 980 }; 981 982 frame@17c23000 { 983 frame-number = <1>; 984 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 985 reg = <0x0 0x17c23000 0x0 0x1000>; 986 status = "disabled"; 987 }; 988 989 frame@17c25000 { 990 frame-number = <2>; 991 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 992 reg = <0x0 0x17c25000 0x0 0x1000>; 993 status = "disabled"; 994 }; 995 996 frame@17c27000 { 997 frame-number = <3>; 998 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 999 reg = <0x0 0x17c26000 0x0 0x1000>; 1000 status = "disabled"; 1001 }; 1002 1003 frame@17c29000 { 1004 frame-number = <4>; 1005 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1006 reg = <0x0 0x17c29000 0x0 0x1000>; 1007 status = "disabled"; 1008 }; 1009 1010 frame@17c2b000 { 1011 frame-number = <5>; 1012 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1013 reg = <0x0 0x17c2b000 0x0 0x1000>; 1014 status = "disabled"; 1015 }; 1016 1017 frame@17c2d000 { 1018 frame-number = <6>; 1019 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1020 reg = <0x0 0x17c2d000 0x0 0x1000>; 1021 status = "disabled"; 1022 }; 1023 }; 1024 1025 apps_rsc: rsc@18200000 { 1026 label = "apps_rsc"; 1027 compatible = "qcom,rpmh-rsc"; 1028 reg = <0x0 0x18200000 0x0 0x10000>, 1029 <0x0 0x18210000 0x0 0x10000>, 1030 <0x0 0x18220000 0x0 0x10000>; 1031 reg-names = "drv-0", "drv-1", "drv-2"; 1032 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1035 qcom,tcs-offset = <0xd00>; 1036 qcom,drv-id = <2>; 1037 qcom,tcs-config = <ACTIVE_TCS 2>, 1038 <SLEEP_TCS 1>, 1039 <WAKE_TCS 1>, 1040 <CONTROL_TCS 0>; 1041 1042 rpmhcc: clock-controller { 1043 compatible = "qcom,sm8150-rpmh-clk"; 1044 #clock-cells = <1>; 1045 clock-names = "xo"; 1046 clocks = <&xo_board>; 1047 }; 1048 1049 rpmhpd: power-controller { 1050 compatible = "qcom,sm8150-rpmhpd"; 1051 #power-domain-cells = <1>; 1052 operating-points-v2 = <&rpmhpd_opp_table>; 1053 1054 rpmhpd_opp_table: opp-table { 1055 compatible = "operating-points-v2"; 1056 1057 rpmhpd_opp_ret: opp1 { 1058 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1059 }; 1060 1061 rpmhpd_opp_min_svs: opp2 { 1062 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1063 }; 1064 1065 rpmhpd_opp_low_svs: opp3 { 1066 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1067 }; 1068 1069 rpmhpd_opp_svs: opp4 { 1070 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1071 }; 1072 1073 rpmhpd_opp_svs_l1: opp5 { 1074 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1075 }; 1076 1077 rpmhpd_opp_svs_l2: opp6 { 1078 opp-level = <224>; 1079 }; 1080 1081 rpmhpd_opp_nom: opp7 { 1082 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1083 }; 1084 1085 rpmhpd_opp_nom_l1: opp8 { 1086 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1087 }; 1088 1089 rpmhpd_opp_nom_l2: opp9 { 1090 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1091 }; 1092 1093 rpmhpd_opp_turbo: opp10 { 1094 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1095 }; 1096 1097 rpmhpd_opp_turbo_l1: opp11 { 1098 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1099 }; 1100 }; 1101 }; 1102 }; 1103 1104 cpufreq_hw: cpufreq@18323000 { 1105 compatible = "qcom,cpufreq-hw"; 1106 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 1107 <0 0x18327800 0 0x1400>; 1108 reg-names = "freq-domain0", "freq-domain1", 1109 "freq-domain2"; 1110 1111 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 1112 clock-names = "xo", "alternate"; 1113 1114 #freq-domain-cells = <1>; 1115 }; 1116 }; 1117 1118 timer { 1119 compatible = "arm,armv8-timer"; 1120 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 1121 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 1122 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 1123 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 1124 }; 1125 1126 thermal-zones { 1127 cpu0-thermal { 1128 polling-delay-passive = <250>; 1129 polling-delay = <1000>; 1130 1131 thermal-sensors = <&tsens0 1>; 1132 1133 trips { 1134 cpu0_alert0: trip-point0 { 1135 temperature = <90000>; 1136 hysteresis = <2000>; 1137 type = "passive"; 1138 }; 1139 1140 cpu0_alert1: trip-point1 { 1141 temperature = <95000>; 1142 hysteresis = <2000>; 1143 type = "passive"; 1144 }; 1145 1146 cpu0_crit: cpu_crit { 1147 temperature = <110000>; 1148 hysteresis = <1000>; 1149 type = "critical"; 1150 }; 1151 }; 1152 1153 cooling-maps { 1154 map0 { 1155 trip = <&cpu0_alert0>; 1156 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1157 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1158 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1159 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1160 }; 1161 map1 { 1162 trip = <&cpu0_alert1>; 1163 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1164 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1165 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1166 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1167 }; 1168 }; 1169 }; 1170 1171 cpu1-thermal { 1172 polling-delay-passive = <250>; 1173 polling-delay = <1000>; 1174 1175 thermal-sensors = <&tsens0 2>; 1176 1177 trips { 1178 cpu1_alert0: trip-point0 { 1179 temperature = <90000>; 1180 hysteresis = <2000>; 1181 type = "passive"; 1182 }; 1183 1184 cpu1_alert1: trip-point1 { 1185 temperature = <95000>; 1186 hysteresis = <2000>; 1187 type = "passive"; 1188 }; 1189 1190 cpu1_crit: cpu_crit { 1191 temperature = <110000>; 1192 hysteresis = <1000>; 1193 type = "critical"; 1194 }; 1195 }; 1196 1197 cooling-maps { 1198 map0 { 1199 trip = <&cpu1_alert0>; 1200 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1201 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1202 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1203 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1204 }; 1205 map1 { 1206 trip = <&cpu1_alert1>; 1207 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1208 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1209 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1210 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1211 }; 1212 }; 1213 }; 1214 1215 cpu2-thermal { 1216 polling-delay-passive = <250>; 1217 polling-delay = <1000>; 1218 1219 thermal-sensors = <&tsens0 3>; 1220 1221 trips { 1222 cpu2_alert0: trip-point0 { 1223 temperature = <90000>; 1224 hysteresis = <2000>; 1225 type = "passive"; 1226 }; 1227 1228 cpu2_alert1: trip-point1 { 1229 temperature = <95000>; 1230 hysteresis = <2000>; 1231 type = "passive"; 1232 }; 1233 1234 cpu2_crit: cpu_crit { 1235 temperature = <110000>; 1236 hysteresis = <1000>; 1237 type = "critical"; 1238 }; 1239 }; 1240 1241 cooling-maps { 1242 map0 { 1243 trip = <&cpu2_alert0>; 1244 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1245 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1246 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1247 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1248 }; 1249 map1 { 1250 trip = <&cpu2_alert1>; 1251 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1252 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1253 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1254 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1255 }; 1256 }; 1257 }; 1258 1259 cpu3-thermal { 1260 polling-delay-passive = <250>; 1261 polling-delay = <1000>; 1262 1263 thermal-sensors = <&tsens0 4>; 1264 1265 trips { 1266 cpu3_alert0: trip-point0 { 1267 temperature = <90000>; 1268 hysteresis = <2000>; 1269 type = "passive"; 1270 }; 1271 1272 cpu3_alert1: trip-point1 { 1273 temperature = <95000>; 1274 hysteresis = <2000>; 1275 type = "passive"; 1276 }; 1277 1278 cpu3_crit: cpu_crit { 1279 temperature = <110000>; 1280 hysteresis = <1000>; 1281 type = "critical"; 1282 }; 1283 }; 1284 1285 cooling-maps { 1286 map0 { 1287 trip = <&cpu3_alert0>; 1288 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1289 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1290 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1291 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1292 }; 1293 map1 { 1294 trip = <&cpu3_alert1>; 1295 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1296 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1297 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1298 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1299 }; 1300 }; 1301 }; 1302 1303 cpu4-top-thermal { 1304 polling-delay-passive = <250>; 1305 polling-delay = <1000>; 1306 1307 thermal-sensors = <&tsens0 7>; 1308 1309 trips { 1310 cpu4_top_alert0: trip-point0 { 1311 temperature = <90000>; 1312 hysteresis = <2000>; 1313 type = "passive"; 1314 }; 1315 1316 cpu4_top_alert1: trip-point1 { 1317 temperature = <95000>; 1318 hysteresis = <2000>; 1319 type = "passive"; 1320 }; 1321 1322 cpu4_top_crit: cpu_crit { 1323 temperature = <110000>; 1324 hysteresis = <1000>; 1325 type = "critical"; 1326 }; 1327 }; 1328 1329 cooling-maps { 1330 map0 { 1331 trip = <&cpu4_top_alert0>; 1332 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1333 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1334 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1335 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1336 }; 1337 map1 { 1338 trip = <&cpu4_top_alert1>; 1339 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1340 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1341 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1342 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1343 }; 1344 }; 1345 }; 1346 1347 cpu5-top-thermal { 1348 polling-delay-passive = <250>; 1349 polling-delay = <1000>; 1350 1351 thermal-sensors = <&tsens0 8>; 1352 1353 trips { 1354 cpu5_top_alert0: trip-point0 { 1355 temperature = <90000>; 1356 hysteresis = <2000>; 1357 type = "passive"; 1358 }; 1359 1360 cpu5_top_alert1: trip-point1 { 1361 temperature = <95000>; 1362 hysteresis = <2000>; 1363 type = "passive"; 1364 }; 1365 1366 cpu5_top_crit: cpu_crit { 1367 temperature = <110000>; 1368 hysteresis = <1000>; 1369 type = "critical"; 1370 }; 1371 }; 1372 1373 cooling-maps { 1374 map0 { 1375 trip = <&cpu5_top_alert0>; 1376 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1377 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1378 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1379 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1380 }; 1381 map1 { 1382 trip = <&cpu5_top_alert1>; 1383 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1384 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1385 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1386 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1387 }; 1388 }; 1389 }; 1390 1391 cpu6-top-thermal { 1392 polling-delay-passive = <250>; 1393 polling-delay = <1000>; 1394 1395 thermal-sensors = <&tsens0 9>; 1396 1397 trips { 1398 cpu6_top_alert0: trip-point0 { 1399 temperature = <90000>; 1400 hysteresis = <2000>; 1401 type = "passive"; 1402 }; 1403 1404 cpu6_top_alert1: trip-point1 { 1405 temperature = <95000>; 1406 hysteresis = <2000>; 1407 type = "passive"; 1408 }; 1409 1410 cpu6_top_crit: cpu_crit { 1411 temperature = <110000>; 1412 hysteresis = <1000>; 1413 type = "critical"; 1414 }; 1415 }; 1416 1417 cooling-maps { 1418 map0 { 1419 trip = <&cpu6_top_alert0>; 1420 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1421 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1422 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1423 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1424 }; 1425 map1 { 1426 trip = <&cpu6_top_alert1>; 1427 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1428 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1429 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1430 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1431 }; 1432 }; 1433 }; 1434 1435 cpu7-top-thermal { 1436 polling-delay-passive = <250>; 1437 polling-delay = <1000>; 1438 1439 thermal-sensors = <&tsens0 10>; 1440 1441 trips { 1442 cpu7_top_alert0: trip-point0 { 1443 temperature = <90000>; 1444 hysteresis = <2000>; 1445 type = "passive"; 1446 }; 1447 1448 cpu7_top_alert1: trip-point1 { 1449 temperature = <95000>; 1450 hysteresis = <2000>; 1451 type = "passive"; 1452 }; 1453 1454 cpu7_top_crit: cpu_crit { 1455 temperature = <110000>; 1456 hysteresis = <1000>; 1457 type = "critical"; 1458 }; 1459 }; 1460 1461 cooling-maps { 1462 map0 { 1463 trip = <&cpu7_top_alert0>; 1464 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1465 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1466 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1467 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1468 }; 1469 map1 { 1470 trip = <&cpu7_top_alert1>; 1471 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1472 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1473 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1474 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1475 }; 1476 }; 1477 }; 1478 1479 cpu4-bottom-thermal { 1480 polling-delay-passive = <250>; 1481 polling-delay = <1000>; 1482 1483 thermal-sensors = <&tsens0 11>; 1484 1485 trips { 1486 cpu4_bottom_alert0: trip-point0 { 1487 temperature = <90000>; 1488 hysteresis = <2000>; 1489 type = "passive"; 1490 }; 1491 1492 cpu4_bottom_alert1: trip-point1 { 1493 temperature = <95000>; 1494 hysteresis = <2000>; 1495 type = "passive"; 1496 }; 1497 1498 cpu4_bottom_crit: cpu_crit { 1499 temperature = <110000>; 1500 hysteresis = <1000>; 1501 type = "critical"; 1502 }; 1503 }; 1504 1505 cooling-maps { 1506 map0 { 1507 trip = <&cpu4_bottom_alert0>; 1508 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1509 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1510 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1511 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1512 }; 1513 map1 { 1514 trip = <&cpu4_bottom_alert1>; 1515 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1516 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1517 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1518 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1519 }; 1520 }; 1521 }; 1522 1523 cpu5-bottom-thermal { 1524 polling-delay-passive = <250>; 1525 polling-delay = <1000>; 1526 1527 thermal-sensors = <&tsens0 12>; 1528 1529 trips { 1530 cpu5_bottom_alert0: trip-point0 { 1531 temperature = <90000>; 1532 hysteresis = <2000>; 1533 type = "passive"; 1534 }; 1535 1536 cpu5_bottom_alert1: trip-point1 { 1537 temperature = <95000>; 1538 hysteresis = <2000>; 1539 type = "passive"; 1540 }; 1541 1542 cpu5_bottom_crit: cpu_crit { 1543 temperature = <110000>; 1544 hysteresis = <1000>; 1545 type = "critical"; 1546 }; 1547 }; 1548 1549 cooling-maps { 1550 map0 { 1551 trip = <&cpu5_bottom_alert0>; 1552 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1553 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1554 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1555 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1556 }; 1557 map1 { 1558 trip = <&cpu5_bottom_alert1>; 1559 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1560 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1561 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1562 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1563 }; 1564 }; 1565 }; 1566 1567 cpu6-bottom-thermal { 1568 polling-delay-passive = <250>; 1569 polling-delay = <1000>; 1570 1571 thermal-sensors = <&tsens0 13>; 1572 1573 trips { 1574 cpu6_bottom_alert0: trip-point0 { 1575 temperature = <90000>; 1576 hysteresis = <2000>; 1577 type = "passive"; 1578 }; 1579 1580 cpu6_bottom_alert1: trip-point1 { 1581 temperature = <95000>; 1582 hysteresis = <2000>; 1583 type = "passive"; 1584 }; 1585 1586 cpu6_bottom_crit: cpu_crit { 1587 temperature = <110000>; 1588 hysteresis = <1000>; 1589 type = "critical"; 1590 }; 1591 }; 1592 1593 cooling-maps { 1594 map0 { 1595 trip = <&cpu6_bottom_alert0>; 1596 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1597 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1598 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1599 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1600 }; 1601 map1 { 1602 trip = <&cpu6_bottom_alert1>; 1603 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1604 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1605 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1606 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1607 }; 1608 }; 1609 }; 1610 1611 cpu7-bottom-thermal { 1612 polling-delay-passive = <250>; 1613 polling-delay = <1000>; 1614 1615 thermal-sensors = <&tsens0 14>; 1616 1617 trips { 1618 cpu7_bottom_alert0: trip-point0 { 1619 temperature = <90000>; 1620 hysteresis = <2000>; 1621 type = "passive"; 1622 }; 1623 1624 cpu7_bottom_alert1: trip-point1 { 1625 temperature = <95000>; 1626 hysteresis = <2000>; 1627 type = "passive"; 1628 }; 1629 1630 cpu7_bottom_crit: cpu_crit { 1631 temperature = <110000>; 1632 hysteresis = <1000>; 1633 type = "critical"; 1634 }; 1635 }; 1636 1637 cooling-maps { 1638 map0 { 1639 trip = <&cpu7_bottom_alert0>; 1640 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1641 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1642 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1643 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1644 }; 1645 map1 { 1646 trip = <&cpu7_bottom_alert1>; 1647 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1648 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1649 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1650 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1651 }; 1652 }; 1653 }; 1654 1655 aoss0-thermal { 1656 polling-delay-passive = <250>; 1657 polling-delay = <1000>; 1658 1659 thermal-sensors = <&tsens0 0>; 1660 1661 trips { 1662 aoss0_alert0: trip-point0 { 1663 temperature = <90000>; 1664 hysteresis = <2000>; 1665 type = "hot"; 1666 }; 1667 }; 1668 }; 1669 1670 cluster0-thermal { 1671 polling-delay-passive = <250>; 1672 polling-delay = <1000>; 1673 1674 thermal-sensors = <&tsens0 5>; 1675 1676 trips { 1677 cluster0_alert0: trip-point0 { 1678 temperature = <90000>; 1679 hysteresis = <2000>; 1680 type = "hot"; 1681 }; 1682 cluster0_crit: cluster0_crit { 1683 temperature = <110000>; 1684 hysteresis = <2000>; 1685 type = "critical"; 1686 }; 1687 }; 1688 }; 1689 1690 cluster1-thermal { 1691 polling-delay-passive = <250>; 1692 polling-delay = <1000>; 1693 1694 thermal-sensors = <&tsens0 6>; 1695 1696 trips { 1697 cluster1_alert0: trip-point0 { 1698 temperature = <90000>; 1699 hysteresis = <2000>; 1700 type = "hot"; 1701 }; 1702 cluster1_crit: cluster1_crit { 1703 temperature = <110000>; 1704 hysteresis = <2000>; 1705 type = "critical"; 1706 }; 1707 }; 1708 }; 1709 1710 gpu-thermal-top { 1711 polling-delay-passive = <250>; 1712 polling-delay = <1000>; 1713 1714 thermal-sensors = <&tsens0 15>; 1715 1716 trips { 1717 gpu1_alert0: trip-point0 { 1718 temperature = <90000>; 1719 hysteresis = <2000>; 1720 type = "hot"; 1721 }; 1722 }; 1723 }; 1724 1725 aoss1-thermal { 1726 polling-delay-passive = <250>; 1727 polling-delay = <1000>; 1728 1729 thermal-sensors = <&tsens1 0>; 1730 1731 trips { 1732 aoss1_alert0: trip-point0 { 1733 temperature = <90000>; 1734 hysteresis = <2000>; 1735 type = "hot"; 1736 }; 1737 }; 1738 }; 1739 1740 wlan-thermal { 1741 polling-delay-passive = <250>; 1742 polling-delay = <1000>; 1743 1744 thermal-sensors = <&tsens1 1>; 1745 1746 trips { 1747 wlan_alert0: trip-point0 { 1748 temperature = <90000>; 1749 hysteresis = <2000>; 1750 type = "hot"; 1751 }; 1752 }; 1753 }; 1754 1755 video-thermal { 1756 polling-delay-passive = <250>; 1757 polling-delay = <1000>; 1758 1759 thermal-sensors = <&tsens1 2>; 1760 1761 trips { 1762 video_alert0: trip-point0 { 1763 temperature = <90000>; 1764 hysteresis = <2000>; 1765 type = "hot"; 1766 }; 1767 }; 1768 }; 1769 1770 mem-thermal { 1771 polling-delay-passive = <250>; 1772 polling-delay = <1000>; 1773 1774 thermal-sensors = <&tsens1 3>; 1775 1776 trips { 1777 mem_alert0: trip-point0 { 1778 temperature = <90000>; 1779 hysteresis = <2000>; 1780 type = "hot"; 1781 }; 1782 }; 1783 }; 1784 1785 q6-hvx-thermal { 1786 polling-delay-passive = <250>; 1787 polling-delay = <1000>; 1788 1789 thermal-sensors = <&tsens1 4>; 1790 1791 trips { 1792 q6_hvx_alert0: trip-point0 { 1793 temperature = <90000>; 1794 hysteresis = <2000>; 1795 type = "hot"; 1796 }; 1797 }; 1798 }; 1799 1800 camera-thermal { 1801 polling-delay-passive = <250>; 1802 polling-delay = <1000>; 1803 1804 thermal-sensors = <&tsens1 5>; 1805 1806 trips { 1807 camera_alert0: trip-point0 { 1808 temperature = <90000>; 1809 hysteresis = <2000>; 1810 type = "hot"; 1811 }; 1812 }; 1813 }; 1814 1815 compute-thermal { 1816 polling-delay-passive = <250>; 1817 polling-delay = <1000>; 1818 1819 thermal-sensors = <&tsens1 6>; 1820 1821 trips { 1822 compute_alert0: trip-point0 { 1823 temperature = <90000>; 1824 hysteresis = <2000>; 1825 type = "hot"; 1826 }; 1827 }; 1828 }; 1829 1830 modem-thermal { 1831 polling-delay-passive = <250>; 1832 polling-delay = <1000>; 1833 1834 thermal-sensors = <&tsens1 7>; 1835 1836 trips { 1837 modem_alert0: trip-point0 { 1838 temperature = <90000>; 1839 hysteresis = <2000>; 1840 type = "hot"; 1841 }; 1842 }; 1843 }; 1844 1845 npu-thermal { 1846 polling-delay-passive = <250>; 1847 polling-delay = <1000>; 1848 1849 thermal-sensors = <&tsens1 8>; 1850 1851 trips { 1852 npu_alert0: trip-point0 { 1853 temperature = <90000>; 1854 hysteresis = <2000>; 1855 type = "hot"; 1856 }; 1857 }; 1858 }; 1859 1860 modem-vec-thermal { 1861 polling-delay-passive = <250>; 1862 polling-delay = <1000>; 1863 1864 thermal-sensors = <&tsens1 9>; 1865 1866 trips { 1867 modem_vec_alert0: trip-point0 { 1868 temperature = <90000>; 1869 hysteresis = <2000>; 1870 type = "hot"; 1871 }; 1872 }; 1873 }; 1874 1875 modem-scl-thermal { 1876 polling-delay-passive = <250>; 1877 polling-delay = <1000>; 1878 1879 thermal-sensors = <&tsens1 10>; 1880 1881 trips { 1882 modem_scl_alert0: trip-point0 { 1883 temperature = <90000>; 1884 hysteresis = <2000>; 1885 type = "hot"; 1886 }; 1887 }; 1888 }; 1889 1890 gpu-thermal-bottom { 1891 polling-delay-passive = <250>; 1892 polling-delay = <1000>; 1893 1894 thermal-sensors = <&tsens1 11>; 1895 1896 trips { 1897 gpu2_alert0: trip-point0 { 1898 temperature = <90000>; 1899 hysteresis = <2000>; 1900 type = "hot"; 1901 }; 1902 }; 1903 }; 1904 }; 1905}; 1906