1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/dma/qcom-gpi.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,gcc-sm8150.h> 13#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sm8150.h> 16#include <dt-bindings/thermal/thermal.h> 17 18/ { 19 interrupt-parent = <&intc>; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 chosen { }; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <38400000>; 31 clock-output-names = "xo_board"; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32764>; 38 clock-output-names = "sleep_clk"; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "qcom,kryo485"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 capacity-dmips-mhz = <488>; 52 dynamic-power-coefficient = <232>; 53 next-level-cache = <&L2_0>; 54 qcom,freq-domain = <&cpufreq_hw 0>; 55 operating-points-v2 = <&cpu0_opp_table>; 56 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 57 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 58 power-domains = <&CPU_PD0>; 59 power-domain-names = "psci"; 60 #cooling-cells = <2>; 61 L2_0: l2-cache { 62 compatible = "cache"; 63 next-level-cache = <&L3_0>; 64 L3_0: l3-cache { 65 compatible = "cache"; 66 }; 67 }; 68 }; 69 70 CPU1: cpu@100 { 71 device_type = "cpu"; 72 compatible = "qcom,kryo485"; 73 reg = <0x0 0x100>; 74 enable-method = "psci"; 75 capacity-dmips-mhz = <488>; 76 dynamic-power-coefficient = <232>; 77 next-level-cache = <&L2_100>; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 operating-points-v2 = <&cpu0_opp_table>; 80 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 81 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 82 power-domains = <&CPU_PD1>; 83 power-domain-names = "psci"; 84 #cooling-cells = <2>; 85 L2_100: l2-cache { 86 compatible = "cache"; 87 next-level-cache = <&L3_0>; 88 }; 89 90 }; 91 92 CPU2: cpu@200 { 93 device_type = "cpu"; 94 compatible = "qcom,kryo485"; 95 reg = <0x0 0x200>; 96 enable-method = "psci"; 97 capacity-dmips-mhz = <488>; 98 dynamic-power-coefficient = <232>; 99 next-level-cache = <&L2_200>; 100 qcom,freq-domain = <&cpufreq_hw 0>; 101 operating-points-v2 = <&cpu0_opp_table>; 102 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 103 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 104 power-domains = <&CPU_PD2>; 105 power-domain-names = "psci"; 106 #cooling-cells = <2>; 107 L2_200: l2-cache { 108 compatible = "cache"; 109 next-level-cache = <&L3_0>; 110 }; 111 }; 112 113 CPU3: cpu@300 { 114 device_type = "cpu"; 115 compatible = "qcom,kryo485"; 116 reg = <0x0 0x300>; 117 enable-method = "psci"; 118 capacity-dmips-mhz = <488>; 119 dynamic-power-coefficient = <232>; 120 next-level-cache = <&L2_300>; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 operating-points-v2 = <&cpu0_opp_table>; 123 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 124 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 125 power-domains = <&CPU_PD3>; 126 power-domain-names = "psci"; 127 #cooling-cells = <2>; 128 L2_300: l2-cache { 129 compatible = "cache"; 130 next-level-cache = <&L3_0>; 131 }; 132 }; 133 134 CPU4: cpu@400 { 135 device_type = "cpu"; 136 compatible = "qcom,kryo485"; 137 reg = <0x0 0x400>; 138 enable-method = "psci"; 139 capacity-dmips-mhz = <1024>; 140 dynamic-power-coefficient = <369>; 141 next-level-cache = <&L2_400>; 142 qcom,freq-domain = <&cpufreq_hw 1>; 143 operating-points-v2 = <&cpu4_opp_table>; 144 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 145 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 146 power-domains = <&CPU_PD4>; 147 power-domain-names = "psci"; 148 #cooling-cells = <2>; 149 L2_400: l2-cache { 150 compatible = "cache"; 151 next-level-cache = <&L3_0>; 152 }; 153 }; 154 155 CPU5: cpu@500 { 156 device_type = "cpu"; 157 compatible = "qcom,kryo485"; 158 reg = <0x0 0x500>; 159 enable-method = "psci"; 160 capacity-dmips-mhz = <1024>; 161 dynamic-power-coefficient = <369>; 162 next-level-cache = <&L2_500>; 163 qcom,freq-domain = <&cpufreq_hw 1>; 164 operating-points-v2 = <&cpu4_opp_table>; 165 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 166 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 167 power-domains = <&CPU_PD5>; 168 power-domain-names = "psci"; 169 #cooling-cells = <2>; 170 L2_500: l2-cache { 171 compatible = "cache"; 172 next-level-cache = <&L3_0>; 173 }; 174 }; 175 176 CPU6: cpu@600 { 177 device_type = "cpu"; 178 compatible = "qcom,kryo485"; 179 reg = <0x0 0x600>; 180 enable-method = "psci"; 181 capacity-dmips-mhz = <1024>; 182 dynamic-power-coefficient = <369>; 183 next-level-cache = <&L2_600>; 184 qcom,freq-domain = <&cpufreq_hw 1>; 185 operating-points-v2 = <&cpu4_opp_table>; 186 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 187 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 188 power-domains = <&CPU_PD6>; 189 power-domain-names = "psci"; 190 #cooling-cells = <2>; 191 L2_600: l2-cache { 192 compatible = "cache"; 193 next-level-cache = <&L3_0>; 194 }; 195 }; 196 197 CPU7: cpu@700 { 198 device_type = "cpu"; 199 compatible = "qcom,kryo485"; 200 reg = <0x0 0x700>; 201 enable-method = "psci"; 202 capacity-dmips-mhz = <1024>; 203 dynamic-power-coefficient = <421>; 204 next-level-cache = <&L2_700>; 205 qcom,freq-domain = <&cpufreq_hw 2>; 206 operating-points-v2 = <&cpu7_opp_table>; 207 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 208 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 209 power-domains = <&CPU_PD7>; 210 power-domain-names = "psci"; 211 #cooling-cells = <2>; 212 L2_700: l2-cache { 213 compatible = "cache"; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 cpu-map { 219 cluster0 { 220 core0 { 221 cpu = <&CPU0>; 222 }; 223 224 core1 { 225 cpu = <&CPU1>; 226 }; 227 228 core2 { 229 cpu = <&CPU2>; 230 }; 231 232 core3 { 233 cpu = <&CPU3>; 234 }; 235 236 core4 { 237 cpu = <&CPU4>; 238 }; 239 240 core5 { 241 cpu = <&CPU5>; 242 }; 243 244 core6 { 245 cpu = <&CPU6>; 246 }; 247 248 core7 { 249 cpu = <&CPU7>; 250 }; 251 }; 252 }; 253 254 idle-states { 255 entry-method = "psci"; 256 257 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 258 compatible = "arm,idle-state"; 259 idle-state-name = "little-rail-power-collapse"; 260 arm,psci-suspend-param = <0x40000004>; 261 entry-latency-us = <355>; 262 exit-latency-us = <909>; 263 min-residency-us = <3934>; 264 local-timer-stop; 265 }; 266 267 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "big-rail-power-collapse"; 270 arm,psci-suspend-param = <0x40000004>; 271 entry-latency-us = <241>; 272 exit-latency-us = <1461>; 273 min-residency-us = <4488>; 274 local-timer-stop; 275 }; 276 }; 277 278 domain-idle-states { 279 CLUSTER_SLEEP_0: cluster-sleep-0 { 280 compatible = "domain-idle-state"; 281 idle-state-name = "cluster-power-collapse"; 282 arm,psci-suspend-param = <0x4100c244>; 283 entry-latency-us = <3263>; 284 exit-latency-us = <6562>; 285 min-residency-us = <9987>; 286 local-timer-stop; 287 }; 288 }; 289 }; 290 291 cpu0_opp_table: opp-table-cpu0 { 292 compatible = "operating-points-v2"; 293 opp-shared; 294 295 cpu0_opp1: opp-300000000 { 296 opp-hz = /bits/ 64 <300000000>; 297 opp-peak-kBps = <800000 9600000>; 298 }; 299 300 cpu0_opp2: opp-403200000 { 301 opp-hz = /bits/ 64 <403200000>; 302 opp-peak-kBps = <800000 9600000>; 303 }; 304 305 cpu0_opp3: opp-499200000 { 306 opp-hz = /bits/ 64 <499200000>; 307 opp-peak-kBps = <800000 12902400>; 308 }; 309 310 cpu0_opp4: opp-576000000 { 311 opp-hz = /bits/ 64 <576000000>; 312 opp-peak-kBps = <800000 12902400>; 313 }; 314 315 cpu0_opp5: opp-672000000 { 316 opp-hz = /bits/ 64 <672000000>; 317 opp-peak-kBps = <800000 15974400>; 318 }; 319 320 cpu0_opp6: opp-768000000 { 321 opp-hz = /bits/ 64 <768000000>; 322 opp-peak-kBps = <1804000 19660800>; 323 }; 324 325 cpu0_opp7: opp-844800000 { 326 opp-hz = /bits/ 64 <844800000>; 327 opp-peak-kBps = <1804000 19660800>; 328 }; 329 330 cpu0_opp8: opp-940800000 { 331 opp-hz = /bits/ 64 <940800000>; 332 opp-peak-kBps = <1804000 22732800>; 333 }; 334 335 cpu0_opp9: opp-1036800000 { 336 opp-hz = /bits/ 64 <1036800000>; 337 opp-peak-kBps = <1804000 22732800>; 338 }; 339 340 cpu0_opp10: opp-1113600000 { 341 opp-hz = /bits/ 64 <1113600000>; 342 opp-peak-kBps = <2188000 25804800>; 343 }; 344 345 cpu0_opp11: opp-1209600000 { 346 opp-hz = /bits/ 64 <1209600000>; 347 opp-peak-kBps = <2188000 31948800>; 348 }; 349 350 cpu0_opp12: opp-1305600000 { 351 opp-hz = /bits/ 64 <1305600000>; 352 opp-peak-kBps = <3072000 31948800>; 353 }; 354 355 cpu0_opp13: opp-1382400000 { 356 opp-hz = /bits/ 64 <1382400000>; 357 opp-peak-kBps = <3072000 31948800>; 358 }; 359 360 cpu0_opp14: opp-1478400000 { 361 opp-hz = /bits/ 64 <1478400000>; 362 opp-peak-kBps = <3072000 31948800>; 363 }; 364 365 cpu0_opp15: opp-1555200000 { 366 opp-hz = /bits/ 64 <1555200000>; 367 opp-peak-kBps = <3072000 40550400>; 368 }; 369 370 cpu0_opp16: opp-1632000000 { 371 opp-hz = /bits/ 64 <1632000000>; 372 opp-peak-kBps = <3072000 40550400>; 373 }; 374 375 cpu0_opp17: opp-1708800000 { 376 opp-hz = /bits/ 64 <1708800000>; 377 opp-peak-kBps = <3072000 43008000>; 378 }; 379 380 cpu0_opp18: opp-1785600000 { 381 opp-hz = /bits/ 64 <1785600000>; 382 opp-peak-kBps = <3072000 43008000>; 383 }; 384 }; 385 386 cpu4_opp_table: opp-table-cpu4 { 387 compatible = "operating-points-v2"; 388 opp-shared; 389 390 cpu4_opp1: opp-710400000 { 391 opp-hz = /bits/ 64 <710400000>; 392 opp-peak-kBps = <1804000 15974400>; 393 }; 394 395 cpu4_opp2: opp-825600000 { 396 opp-hz = /bits/ 64 <825600000>; 397 opp-peak-kBps = <2188000 19660800>; 398 }; 399 400 cpu4_opp3: opp-940800000 { 401 opp-hz = /bits/ 64 <940800000>; 402 opp-peak-kBps = <2188000 22732800>; 403 }; 404 405 cpu4_opp4: opp-1056000000 { 406 opp-hz = /bits/ 64 <1056000000>; 407 opp-peak-kBps = <3072000 25804800>; 408 }; 409 410 cpu4_opp5: opp-1171200000 { 411 opp-hz = /bits/ 64 <1171200000>; 412 opp-peak-kBps = <3072000 31948800>; 413 }; 414 415 cpu4_opp6: opp-1286400000 { 416 opp-hz = /bits/ 64 <1286400000>; 417 opp-peak-kBps = <4068000 31948800>; 418 }; 419 420 cpu4_opp7: opp-1401600000 { 421 opp-hz = /bits/ 64 <1401600000>; 422 opp-peak-kBps = <4068000 31948800>; 423 }; 424 425 cpu4_opp8: opp-1497600000 { 426 opp-hz = /bits/ 64 <1497600000>; 427 opp-peak-kBps = <4068000 40550400>; 428 }; 429 430 cpu4_opp9: opp-1612800000 { 431 opp-hz = /bits/ 64 <1612800000>; 432 opp-peak-kBps = <4068000 40550400>; 433 }; 434 435 cpu4_opp10: opp-1708800000 { 436 opp-hz = /bits/ 64 <1708800000>; 437 opp-peak-kBps = <4068000 43008000>; 438 }; 439 440 cpu4_opp11: opp-1804800000 { 441 opp-hz = /bits/ 64 <1804800000>; 442 opp-peak-kBps = <6220000 43008000>; 443 }; 444 445 cpu4_opp12: opp-1920000000 { 446 opp-hz = /bits/ 64 <1920000000>; 447 opp-peak-kBps = <6220000 49152000>; 448 }; 449 450 cpu4_opp13: opp-2016000000 { 451 opp-hz = /bits/ 64 <2016000000>; 452 opp-peak-kBps = <7216000 49152000>; 453 }; 454 455 cpu4_opp14: opp-2131200000 { 456 opp-hz = /bits/ 64 <2131200000>; 457 opp-peak-kBps = <8368000 49152000>; 458 }; 459 460 cpu4_opp15: opp-2227200000 { 461 opp-hz = /bits/ 64 <2227200000>; 462 opp-peak-kBps = <8368000 51609600>; 463 }; 464 465 cpu4_opp16: opp-2323200000 { 466 opp-hz = /bits/ 64 <2323200000>; 467 opp-peak-kBps = <8368000 51609600>; 468 }; 469 470 cpu4_opp17: opp-2419200000 { 471 opp-hz = /bits/ 64 <2419200000>; 472 opp-peak-kBps = <8368000 51609600>; 473 }; 474 }; 475 476 cpu7_opp_table: opp-table-cpu7 { 477 compatible = "operating-points-v2"; 478 opp-shared; 479 480 cpu7_opp1: opp-825600000 { 481 opp-hz = /bits/ 64 <825600000>; 482 opp-peak-kBps = <2188000 19660800>; 483 }; 484 485 cpu7_opp2: opp-940800000 { 486 opp-hz = /bits/ 64 <940800000>; 487 opp-peak-kBps = <2188000 22732800>; 488 }; 489 490 cpu7_opp3: opp-1056000000 { 491 opp-hz = /bits/ 64 <1056000000>; 492 opp-peak-kBps = <3072000 25804800>; 493 }; 494 495 cpu7_opp4: opp-1171200000 { 496 opp-hz = /bits/ 64 <1171200000>; 497 opp-peak-kBps = <3072000 31948800>; 498 }; 499 500 cpu7_opp5: opp-1286400000 { 501 opp-hz = /bits/ 64 <1286400000>; 502 opp-peak-kBps = <4068000 31948800>; 503 }; 504 505 cpu7_opp6: opp-1401600000 { 506 opp-hz = /bits/ 64 <1401600000>; 507 opp-peak-kBps = <4068000 31948800>; 508 }; 509 510 cpu7_opp7: opp-1497600000 { 511 opp-hz = /bits/ 64 <1497600000>; 512 opp-peak-kBps = <4068000 40550400>; 513 }; 514 515 cpu7_opp8: opp-1612800000 { 516 opp-hz = /bits/ 64 <1612800000>; 517 opp-peak-kBps = <4068000 40550400>; 518 }; 519 520 cpu7_opp9: opp-1708800000 { 521 opp-hz = /bits/ 64 <1708800000>; 522 opp-peak-kBps = <4068000 43008000>; 523 }; 524 525 cpu7_opp10: opp-1804800000 { 526 opp-hz = /bits/ 64 <1804800000>; 527 opp-peak-kBps = <6220000 43008000>; 528 }; 529 530 cpu7_opp11: opp-1920000000 { 531 opp-hz = /bits/ 64 <1920000000>; 532 opp-peak-kBps = <6220000 49152000>; 533 }; 534 535 cpu7_opp12: opp-2016000000 { 536 opp-hz = /bits/ 64 <2016000000>; 537 opp-peak-kBps = <7216000 49152000>; 538 }; 539 540 cpu7_opp13: opp-2131200000 { 541 opp-hz = /bits/ 64 <2131200000>; 542 opp-peak-kBps = <8368000 49152000>; 543 }; 544 545 cpu7_opp14: opp-2227200000 { 546 opp-hz = /bits/ 64 <2227200000>; 547 opp-peak-kBps = <8368000 51609600>; 548 }; 549 550 cpu7_opp15: opp-2323200000 { 551 opp-hz = /bits/ 64 <2323200000>; 552 opp-peak-kBps = <8368000 51609600>; 553 }; 554 555 cpu7_opp16: opp-2419200000 { 556 opp-hz = /bits/ 64 <2419200000>; 557 opp-peak-kBps = <8368000 51609600>; 558 }; 559 560 cpu7_opp17: opp-2534400000 { 561 opp-hz = /bits/ 64 <2534400000>; 562 opp-peak-kBps = <8368000 51609600>; 563 }; 564 565 cpu7_opp18: opp-2649600000 { 566 opp-hz = /bits/ 64 <2649600000>; 567 opp-peak-kBps = <8368000 51609600>; 568 }; 569 570 cpu7_opp19: opp-2745600000 { 571 opp-hz = /bits/ 64 <2745600000>; 572 opp-peak-kBps = <8368000 51609600>; 573 }; 574 575 cpu7_opp20: opp-2841600000 { 576 opp-hz = /bits/ 64 <2841600000>; 577 opp-peak-kBps = <8368000 51609600>; 578 }; 579 }; 580 581 firmware { 582 scm: scm { 583 compatible = "qcom,scm-sm8150", "qcom,scm"; 584 #reset-cells = <1>; 585 }; 586 }; 587 588 memory@80000000 { 589 device_type = "memory"; 590 /* We expect the bootloader to fill in the size */ 591 reg = <0x0 0x80000000 0x0 0x0>; 592 }; 593 594 pmu { 595 compatible = "arm,armv8-pmuv3"; 596 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 597 }; 598 599 psci { 600 compatible = "arm,psci-1.0"; 601 method = "smc"; 602 603 CPU_PD0: cpu0 { 604 #power-domain-cells = <0>; 605 power-domains = <&CLUSTER_PD>; 606 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 607 }; 608 609 CPU_PD1: cpu1 { 610 #power-domain-cells = <0>; 611 power-domains = <&CLUSTER_PD>; 612 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 613 }; 614 615 CPU_PD2: cpu2 { 616 #power-domain-cells = <0>; 617 power-domains = <&CLUSTER_PD>; 618 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 619 }; 620 621 CPU_PD3: cpu3 { 622 #power-domain-cells = <0>; 623 power-domains = <&CLUSTER_PD>; 624 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 625 }; 626 627 CPU_PD4: cpu4 { 628 #power-domain-cells = <0>; 629 power-domains = <&CLUSTER_PD>; 630 domain-idle-states = <&BIG_CPU_SLEEP_0>; 631 }; 632 633 CPU_PD5: cpu5 { 634 #power-domain-cells = <0>; 635 power-domains = <&CLUSTER_PD>; 636 domain-idle-states = <&BIG_CPU_SLEEP_0>; 637 }; 638 639 CPU_PD6: cpu6 { 640 #power-domain-cells = <0>; 641 power-domains = <&CLUSTER_PD>; 642 domain-idle-states = <&BIG_CPU_SLEEP_0>; 643 }; 644 645 CPU_PD7: cpu7 { 646 #power-domain-cells = <0>; 647 power-domains = <&CLUSTER_PD>; 648 domain-idle-states = <&BIG_CPU_SLEEP_0>; 649 }; 650 651 CLUSTER_PD: cpu-cluster0 { 652 #power-domain-cells = <0>; 653 domain-idle-states = <&CLUSTER_SLEEP_0>; 654 }; 655 }; 656 657 reserved-memory { 658 #address-cells = <2>; 659 #size-cells = <2>; 660 ranges; 661 662 hyp_mem: memory@85700000 { 663 reg = <0x0 0x85700000 0x0 0x600000>; 664 no-map; 665 }; 666 667 xbl_mem: memory@85d00000 { 668 reg = <0x0 0x85d00000 0x0 0x140000>; 669 no-map; 670 }; 671 672 aop_mem: memory@85f00000 { 673 reg = <0x0 0x85f00000 0x0 0x20000>; 674 no-map; 675 }; 676 677 aop_cmd_db: memory@85f20000 { 678 compatible = "qcom,cmd-db"; 679 reg = <0x0 0x85f20000 0x0 0x20000>; 680 no-map; 681 }; 682 683 smem_mem: memory@86000000 { 684 reg = <0x0 0x86000000 0x0 0x200000>; 685 no-map; 686 }; 687 688 tz_mem: memory@86200000 { 689 reg = <0x0 0x86200000 0x0 0x3900000>; 690 no-map; 691 }; 692 693 rmtfs_mem: memory@89b00000 { 694 compatible = "qcom,rmtfs-mem"; 695 reg = <0x0 0x89b00000 0x0 0x200000>; 696 no-map; 697 698 qcom,client-id = <1>; 699 qcom,vmid = <15>; 700 }; 701 702 camera_mem: memory@8b700000 { 703 reg = <0x0 0x8b700000 0x0 0x500000>; 704 no-map; 705 }; 706 707 wlan_mem: memory@8bc00000 { 708 reg = <0x0 0x8bc00000 0x0 0x180000>; 709 no-map; 710 }; 711 712 npu_mem: memory@8bd80000 { 713 reg = <0x0 0x8bd80000 0x0 0x80000>; 714 no-map; 715 }; 716 717 adsp_mem: memory@8be00000 { 718 reg = <0x0 0x8be00000 0x0 0x1a00000>; 719 no-map; 720 }; 721 722 mpss_mem: memory@8d800000 { 723 reg = <0x0 0x8d800000 0x0 0x9600000>; 724 no-map; 725 }; 726 727 venus_mem: memory@96e00000 { 728 reg = <0x0 0x96e00000 0x0 0x500000>; 729 no-map; 730 }; 731 732 slpi_mem: memory@97300000 { 733 reg = <0x0 0x97300000 0x0 0x1400000>; 734 no-map; 735 }; 736 737 ipa_fw_mem: memory@98700000 { 738 reg = <0x0 0x98700000 0x0 0x10000>; 739 no-map; 740 }; 741 742 ipa_gsi_mem: memory@98710000 { 743 reg = <0x0 0x98710000 0x0 0x5000>; 744 no-map; 745 }; 746 747 gpu_mem: memory@98715000 { 748 reg = <0x0 0x98715000 0x0 0x2000>; 749 no-map; 750 }; 751 752 spss_mem: memory@98800000 { 753 reg = <0x0 0x98800000 0x0 0x100000>; 754 no-map; 755 }; 756 757 cdsp_mem: memory@98900000 { 758 reg = <0x0 0x98900000 0x0 0x1400000>; 759 no-map; 760 }; 761 762 qseecom_mem: memory@9e400000 { 763 reg = <0x0 0x9e400000 0x0 0x1400000>; 764 no-map; 765 }; 766 }; 767 768 smem { 769 compatible = "qcom,smem"; 770 memory-region = <&smem_mem>; 771 hwlocks = <&tcsr_mutex 3>; 772 }; 773 774 smp2p-cdsp { 775 compatible = "qcom,smp2p"; 776 qcom,smem = <94>, <432>; 777 778 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 779 780 mboxes = <&apss_shared 6>; 781 782 qcom,local-pid = <0>; 783 qcom,remote-pid = <5>; 784 785 cdsp_smp2p_out: master-kernel { 786 qcom,entry-name = "master-kernel"; 787 #qcom,smem-state-cells = <1>; 788 }; 789 790 cdsp_smp2p_in: slave-kernel { 791 qcom,entry-name = "slave-kernel"; 792 793 interrupt-controller; 794 #interrupt-cells = <2>; 795 }; 796 }; 797 798 smp2p-lpass { 799 compatible = "qcom,smp2p"; 800 qcom,smem = <443>, <429>; 801 802 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 803 804 mboxes = <&apss_shared 10>; 805 806 qcom,local-pid = <0>; 807 qcom,remote-pid = <2>; 808 809 adsp_smp2p_out: master-kernel { 810 qcom,entry-name = "master-kernel"; 811 #qcom,smem-state-cells = <1>; 812 }; 813 814 adsp_smp2p_in: slave-kernel { 815 qcom,entry-name = "slave-kernel"; 816 817 interrupt-controller; 818 #interrupt-cells = <2>; 819 }; 820 }; 821 822 smp2p-mpss { 823 compatible = "qcom,smp2p"; 824 qcom,smem = <435>, <428>; 825 826 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 827 828 mboxes = <&apss_shared 14>; 829 830 qcom,local-pid = <0>; 831 qcom,remote-pid = <1>; 832 833 modem_smp2p_out: master-kernel { 834 qcom,entry-name = "master-kernel"; 835 #qcom,smem-state-cells = <1>; 836 }; 837 838 modem_smp2p_in: slave-kernel { 839 qcom,entry-name = "slave-kernel"; 840 841 interrupt-controller; 842 #interrupt-cells = <2>; 843 }; 844 }; 845 846 smp2p-slpi { 847 compatible = "qcom,smp2p"; 848 qcom,smem = <481>, <430>; 849 850 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 851 852 mboxes = <&apss_shared 26>; 853 854 qcom,local-pid = <0>; 855 qcom,remote-pid = <3>; 856 857 slpi_smp2p_out: master-kernel { 858 qcom,entry-name = "master-kernel"; 859 #qcom,smem-state-cells = <1>; 860 }; 861 862 slpi_smp2p_in: slave-kernel { 863 qcom,entry-name = "slave-kernel"; 864 865 interrupt-controller; 866 #interrupt-cells = <2>; 867 }; 868 }; 869 870 soc: soc@0 { 871 #address-cells = <2>; 872 #size-cells = <2>; 873 ranges = <0 0 0 0 0x10 0>; 874 dma-ranges = <0 0 0 0 0x10 0>; 875 compatible = "simple-bus"; 876 877 gcc: clock-controller@100000 { 878 compatible = "qcom,gcc-sm8150"; 879 reg = <0x0 0x00100000 0x0 0x1f0000>; 880 #clock-cells = <1>; 881 #reset-cells = <1>; 882 #power-domain-cells = <1>; 883 clock-names = "bi_tcxo", 884 "sleep_clk"; 885 clocks = <&rpmhcc RPMH_CXO_CLK>, 886 <&sleep_clk>; 887 }; 888 889 gpi_dma0: dma-controller@800000 { 890 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 891 reg = <0 0x800000 0 0x60000>; 892 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 905 dma-channels = <13>; 906 dma-channel-mask = <0xfa>; 907 iommus = <&apps_smmu 0x00d6 0x0>; 908 #dma-cells = <3>; 909 status = "disabled"; 910 }; 911 912 ethernet: ethernet@20000 { 913 compatible = "qcom,sm8150-ethqos"; 914 reg = <0x0 0x00020000 0x0 0x10000>, 915 <0x0 0x00036000 0x0 0x100>; 916 reg-names = "stmmaceth", "rgmii"; 917 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 918 clocks = <&gcc GCC_EMAC_AXI_CLK>, 919 <&gcc GCC_EMAC_SLV_AHB_CLK>, 920 <&gcc GCC_EMAC_PTP_CLK>, 921 <&gcc GCC_EMAC_RGMII_CLK>; 922 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 924 interrupt-names = "macirq", "eth_lpi"; 925 926 power-domains = <&gcc EMAC_GDSC>; 927 resets = <&gcc GCC_EMAC_BCR>; 928 929 iommus = <&apps_smmu 0x3C0 0x0>; 930 931 snps,tso; 932 rx-fifo-depth = <4096>; 933 tx-fifo-depth = <4096>; 934 935 status = "disabled"; 936 }; 937 938 939 qupv3_id_0: geniqup@8c0000 { 940 compatible = "qcom,geni-se-qup"; 941 reg = <0x0 0x008c0000 0x0 0x6000>; 942 clock-names = "m-ahb", "s-ahb"; 943 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 944 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 945 iommus = <&apps_smmu 0xc3 0x0>; 946 #address-cells = <2>; 947 #size-cells = <2>; 948 ranges; 949 status = "disabled"; 950 951 i2c0: i2c@880000 { 952 compatible = "qcom,geni-i2c"; 953 reg = <0 0x00880000 0 0x4000>; 954 clock-names = "se"; 955 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 956 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 957 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 958 dma-names = "tx", "rx"; 959 pinctrl-names = "default"; 960 pinctrl-0 = <&qup_i2c0_default>; 961 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 status = "disabled"; 965 }; 966 967 spi0: spi@880000 { 968 compatible = "qcom,geni-spi"; 969 reg = <0 0x880000 0 0x4000>; 970 reg-names = "se"; 971 clock-names = "se"; 972 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 973 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 974 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 975 dma-names = "tx", "rx"; 976 pinctrl-names = "default"; 977 pinctrl-0 = <&qup_spi0_default>; 978 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 979 spi-max-frequency = <50000000>; 980 #address-cells = <1>; 981 #size-cells = <0>; 982 status = "disabled"; 983 }; 984 985 i2c1: i2c@884000 { 986 compatible = "qcom,geni-i2c"; 987 reg = <0 0x00884000 0 0x4000>; 988 clock-names = "se"; 989 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 990 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 991 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 992 dma-names = "tx", "rx"; 993 pinctrl-names = "default"; 994 pinctrl-0 = <&qup_i2c1_default>; 995 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 996 #address-cells = <1>; 997 #size-cells = <0>; 998 status = "disabled"; 999 }; 1000 1001 spi1: spi@884000 { 1002 compatible = "qcom,geni-spi"; 1003 reg = <0 0x884000 0 0x4000>; 1004 reg-names = "se"; 1005 clock-names = "se"; 1006 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1007 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1008 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1009 dma-names = "tx", "rx"; 1010 pinctrl-names = "default"; 1011 pinctrl-0 = <&qup_spi1_default>; 1012 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1013 spi-max-frequency = <50000000>; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 status = "disabled"; 1017 }; 1018 1019 i2c2: i2c@888000 { 1020 compatible = "qcom,geni-i2c"; 1021 reg = <0 0x00888000 0 0x4000>; 1022 clock-names = "se"; 1023 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1024 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1025 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1026 dma-names = "tx", "rx"; 1027 pinctrl-names = "default"; 1028 pinctrl-0 = <&qup_i2c2_default>; 1029 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 status = "disabled"; 1033 }; 1034 1035 spi2: spi@888000 { 1036 compatible = "qcom,geni-spi"; 1037 reg = <0 0x888000 0 0x4000>; 1038 reg-names = "se"; 1039 clock-names = "se"; 1040 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1041 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1042 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1043 dma-names = "tx", "rx"; 1044 pinctrl-names = "default"; 1045 pinctrl-0 = <&qup_spi2_default>; 1046 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1047 spi-max-frequency = <50000000>; 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 status = "disabled"; 1051 }; 1052 1053 i2c3: i2c@88c000 { 1054 compatible = "qcom,geni-i2c"; 1055 reg = <0 0x0088c000 0 0x4000>; 1056 clock-names = "se"; 1057 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1058 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1059 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1060 dma-names = "tx", "rx"; 1061 pinctrl-names = "default"; 1062 pinctrl-0 = <&qup_i2c3_default>; 1063 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 status = "disabled"; 1067 }; 1068 1069 spi3: spi@88c000 { 1070 compatible = "qcom,geni-spi"; 1071 reg = <0 0x88c000 0 0x4000>; 1072 reg-names = "se"; 1073 clock-names = "se"; 1074 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1075 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1076 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1077 dma-names = "tx", "rx"; 1078 pinctrl-names = "default"; 1079 pinctrl-0 = <&qup_spi3_default>; 1080 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1081 spi-max-frequency = <50000000>; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 status = "disabled"; 1085 }; 1086 1087 i2c4: i2c@890000 { 1088 compatible = "qcom,geni-i2c"; 1089 reg = <0 0x00890000 0 0x4000>; 1090 clock-names = "se"; 1091 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1092 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1093 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1094 dma-names = "tx", "rx"; 1095 pinctrl-names = "default"; 1096 pinctrl-0 = <&qup_i2c4_default>; 1097 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 status = "disabled"; 1101 }; 1102 1103 spi4: spi@890000 { 1104 compatible = "qcom,geni-spi"; 1105 reg = <0 0x890000 0 0x4000>; 1106 reg-names = "se"; 1107 clock-names = "se"; 1108 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1109 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1110 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1111 dma-names = "tx", "rx"; 1112 pinctrl-names = "default"; 1113 pinctrl-0 = <&qup_spi4_default>; 1114 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1115 spi-max-frequency = <50000000>; 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 status = "disabled"; 1119 }; 1120 1121 i2c5: i2c@894000 { 1122 compatible = "qcom,geni-i2c"; 1123 reg = <0 0x00894000 0 0x4000>; 1124 clock-names = "se"; 1125 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1126 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1127 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1128 dma-names = "tx", "rx"; 1129 pinctrl-names = "default"; 1130 pinctrl-0 = <&qup_i2c5_default>; 1131 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 status = "disabled"; 1135 }; 1136 1137 spi5: spi@894000 { 1138 compatible = "qcom,geni-spi"; 1139 reg = <0 0x894000 0 0x4000>; 1140 reg-names = "se"; 1141 clock-names = "se"; 1142 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1143 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1144 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1145 dma-names = "tx", "rx"; 1146 pinctrl-names = "default"; 1147 pinctrl-0 = <&qup_spi5_default>; 1148 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1149 spi-max-frequency = <50000000>; 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 status = "disabled"; 1153 }; 1154 1155 i2c6: i2c@898000 { 1156 compatible = "qcom,geni-i2c"; 1157 reg = <0 0x00898000 0 0x4000>; 1158 clock-names = "se"; 1159 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1160 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1161 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1162 dma-names = "tx", "rx"; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&qup_i2c6_default>; 1165 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 status = "disabled"; 1169 }; 1170 1171 spi6: spi@898000 { 1172 compatible = "qcom,geni-spi"; 1173 reg = <0 0x898000 0 0x4000>; 1174 reg-names = "se"; 1175 clock-names = "se"; 1176 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1177 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1178 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1179 dma-names = "tx", "rx"; 1180 pinctrl-names = "default"; 1181 pinctrl-0 = <&qup_spi6_default>; 1182 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1183 spi-max-frequency = <50000000>; 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 status = "disabled"; 1187 }; 1188 1189 i2c7: i2c@89c000 { 1190 compatible = "qcom,geni-i2c"; 1191 reg = <0 0x0089c000 0 0x4000>; 1192 clock-names = "se"; 1193 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1194 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1195 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1196 dma-names = "tx", "rx"; 1197 pinctrl-names = "default"; 1198 pinctrl-0 = <&qup_i2c7_default>; 1199 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 status = "disabled"; 1203 }; 1204 1205 spi7: spi@89c000 { 1206 compatible = "qcom,geni-spi"; 1207 reg = <0 0x89c000 0 0x4000>; 1208 reg-names = "se"; 1209 clock-names = "se"; 1210 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1211 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1212 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1213 dma-names = "tx", "rx"; 1214 pinctrl-names = "default"; 1215 pinctrl-0 = <&qup_spi7_default>; 1216 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1217 spi-max-frequency = <50000000>; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 status = "disabled"; 1221 }; 1222 }; 1223 1224 gpi_dma1: dma-controller@a00000 { 1225 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1226 reg = <0 0xa00000 0 0x60000>; 1227 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1240 dma-channels = <13>; 1241 dma-channel-mask = <0xfa>; 1242 iommus = <&apps_smmu 0x0616 0x0>; 1243 #dma-cells = <3>; 1244 status = "disabled"; 1245 }; 1246 1247 qupv3_id_1: geniqup@ac0000 { 1248 compatible = "qcom,geni-se-qup"; 1249 reg = <0x0 0x00ac0000 0x0 0x6000>; 1250 clock-names = "m-ahb", "s-ahb"; 1251 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1252 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1253 iommus = <&apps_smmu 0x603 0x0>; 1254 #address-cells = <2>; 1255 #size-cells = <2>; 1256 ranges; 1257 status = "disabled"; 1258 1259 i2c8: i2c@a80000 { 1260 compatible = "qcom,geni-i2c"; 1261 reg = <0 0x00a80000 0 0x4000>; 1262 clock-names = "se"; 1263 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1264 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1265 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1266 dma-names = "tx", "rx"; 1267 pinctrl-names = "default"; 1268 pinctrl-0 = <&qup_i2c8_default>; 1269 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1270 #address-cells = <1>; 1271 #size-cells = <0>; 1272 status = "disabled"; 1273 }; 1274 1275 spi8: spi@a80000 { 1276 compatible = "qcom,geni-spi"; 1277 reg = <0 0xa80000 0 0x4000>; 1278 reg-names = "se"; 1279 clock-names = "se"; 1280 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1281 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1282 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1283 dma-names = "tx", "rx"; 1284 pinctrl-names = "default"; 1285 pinctrl-0 = <&qup_spi8_default>; 1286 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1287 spi-max-frequency = <50000000>; 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 status = "disabled"; 1291 }; 1292 1293 i2c9: i2c@a84000 { 1294 compatible = "qcom,geni-i2c"; 1295 reg = <0 0x00a84000 0 0x4000>; 1296 clock-names = "se"; 1297 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1298 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1299 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1300 dma-names = "tx", "rx"; 1301 pinctrl-names = "default"; 1302 pinctrl-0 = <&qup_i2c9_default>; 1303 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 status = "disabled"; 1307 }; 1308 1309 spi9: spi@a84000 { 1310 compatible = "qcom,geni-spi"; 1311 reg = <0 0xa84000 0 0x4000>; 1312 reg-names = "se"; 1313 clock-names = "se"; 1314 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1315 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1316 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1317 dma-names = "tx", "rx"; 1318 pinctrl-names = "default"; 1319 pinctrl-0 = <&qup_spi9_default>; 1320 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1321 spi-max-frequency = <50000000>; 1322 #address-cells = <1>; 1323 #size-cells = <0>; 1324 status = "disabled"; 1325 }; 1326 1327 i2c10: i2c@a88000 { 1328 compatible = "qcom,geni-i2c"; 1329 reg = <0 0x00a88000 0 0x4000>; 1330 clock-names = "se"; 1331 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1332 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1333 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1334 dma-names = "tx", "rx"; 1335 pinctrl-names = "default"; 1336 pinctrl-0 = <&qup_i2c10_default>; 1337 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1338 #address-cells = <1>; 1339 #size-cells = <0>; 1340 status = "disabled"; 1341 }; 1342 1343 spi10: spi@a88000 { 1344 compatible = "qcom,geni-spi"; 1345 reg = <0 0xa88000 0 0x4000>; 1346 reg-names = "se"; 1347 clock-names = "se"; 1348 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1349 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1350 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1351 dma-names = "tx", "rx"; 1352 pinctrl-names = "default"; 1353 pinctrl-0 = <&qup_spi10_default>; 1354 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1355 spi-max-frequency = <50000000>; 1356 #address-cells = <1>; 1357 #size-cells = <0>; 1358 status = "disabled"; 1359 }; 1360 1361 i2c11: i2c@a8c000 { 1362 compatible = "qcom,geni-i2c"; 1363 reg = <0 0x00a8c000 0 0x4000>; 1364 clock-names = "se"; 1365 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1366 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1367 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1368 dma-names = "tx", "rx"; 1369 pinctrl-names = "default"; 1370 pinctrl-0 = <&qup_i2c11_default>; 1371 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 status = "disabled"; 1375 }; 1376 1377 spi11: spi@a8c000 { 1378 compatible = "qcom,geni-spi"; 1379 reg = <0 0xa8c000 0 0x4000>; 1380 reg-names = "se"; 1381 clock-names = "se"; 1382 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1383 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1384 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1385 dma-names = "tx", "rx"; 1386 pinctrl-names = "default"; 1387 pinctrl-0 = <&qup_spi11_default>; 1388 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1389 spi-max-frequency = <50000000>; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 status = "disabled"; 1393 }; 1394 1395 uart2: serial@a90000 { 1396 compatible = "qcom,geni-debug-uart"; 1397 reg = <0x0 0x00a90000 0x0 0x4000>; 1398 clock-names = "se"; 1399 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1400 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1401 status = "disabled"; 1402 }; 1403 1404 i2c12: i2c@a90000 { 1405 compatible = "qcom,geni-i2c"; 1406 reg = <0 0x00a90000 0 0x4000>; 1407 clock-names = "se"; 1408 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1409 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1410 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1411 dma-names = "tx", "rx"; 1412 pinctrl-names = "default"; 1413 pinctrl-0 = <&qup_i2c12_default>; 1414 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1415 #address-cells = <1>; 1416 #size-cells = <0>; 1417 status = "disabled"; 1418 }; 1419 1420 spi12: spi@a90000 { 1421 compatible = "qcom,geni-spi"; 1422 reg = <0 0xa90000 0 0x4000>; 1423 reg-names = "se"; 1424 clock-names = "se"; 1425 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1426 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1427 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1428 dma-names = "tx", "rx"; 1429 pinctrl-names = "default"; 1430 pinctrl-0 = <&qup_spi12_default>; 1431 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1432 spi-max-frequency = <50000000>; 1433 #address-cells = <1>; 1434 #size-cells = <0>; 1435 status = "disabled"; 1436 }; 1437 1438 i2c16: i2c@94000 { 1439 compatible = "qcom,geni-i2c"; 1440 reg = <0 0x0094000 0 0x4000>; 1441 clock-names = "se"; 1442 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1443 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1444 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1445 dma-names = "tx", "rx"; 1446 pinctrl-names = "default"; 1447 pinctrl-0 = <&qup_i2c16_default>; 1448 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 status = "disabled"; 1452 }; 1453 1454 spi16: spi@a94000 { 1455 compatible = "qcom,geni-spi"; 1456 reg = <0 0xa94000 0 0x4000>; 1457 reg-names = "se"; 1458 clock-names = "se"; 1459 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1460 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1461 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1462 dma-names = "tx", "rx"; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&qup_spi16_default>; 1465 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1466 spi-max-frequency = <50000000>; 1467 #address-cells = <1>; 1468 #size-cells = <0>; 1469 status = "disabled"; 1470 }; 1471 }; 1472 1473 gpi_dma2: dma-controller@c00000 { 1474 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1475 reg = <0 0xc00000 0 0x60000>; 1476 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 1489 dma-channels = <13>; 1490 dma-channel-mask = <0xfa>; 1491 iommus = <&apps_smmu 0x07b6 0x0>; 1492 #dma-cells = <3>; 1493 status = "disabled"; 1494 }; 1495 1496 qupv3_id_2: geniqup@cc0000 { 1497 compatible = "qcom,geni-se-qup"; 1498 reg = <0x0 0x00cc0000 0x0 0x6000>; 1499 1500 clock-names = "m-ahb", "s-ahb"; 1501 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1502 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1503 iommus = <&apps_smmu 0x7a3 0x0>; 1504 #address-cells = <2>; 1505 #size-cells = <2>; 1506 ranges; 1507 status = "disabled"; 1508 1509 i2c17: i2c@c80000 { 1510 compatible = "qcom,geni-i2c"; 1511 reg = <0 0x00c80000 0 0x4000>; 1512 clock-names = "se"; 1513 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1514 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1515 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1516 dma-names = "tx", "rx"; 1517 pinctrl-names = "default"; 1518 pinctrl-0 = <&qup_i2c17_default>; 1519 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1520 #address-cells = <1>; 1521 #size-cells = <0>; 1522 status = "disabled"; 1523 }; 1524 1525 spi17: spi@c80000 { 1526 compatible = "qcom,geni-spi"; 1527 reg = <0 0xc80000 0 0x4000>; 1528 reg-names = "se"; 1529 clock-names = "se"; 1530 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1531 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1532 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1533 dma-names = "tx", "rx"; 1534 pinctrl-names = "default"; 1535 pinctrl-0 = <&qup_spi17_default>; 1536 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1537 spi-max-frequency = <50000000>; 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 status = "disabled"; 1541 }; 1542 1543 i2c18: i2c@c84000 { 1544 compatible = "qcom,geni-i2c"; 1545 reg = <0 0x00c84000 0 0x4000>; 1546 clock-names = "se"; 1547 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1548 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1549 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1550 dma-names = "tx", "rx"; 1551 pinctrl-names = "default"; 1552 pinctrl-0 = <&qup_i2c18_default>; 1553 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1554 #address-cells = <1>; 1555 #size-cells = <0>; 1556 status = "disabled"; 1557 }; 1558 1559 spi18: spi@c84000 { 1560 compatible = "qcom,geni-spi"; 1561 reg = <0 0xc84000 0 0x4000>; 1562 reg-names = "se"; 1563 clock-names = "se"; 1564 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1565 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1566 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1567 dma-names = "tx", "rx"; 1568 pinctrl-names = "default"; 1569 pinctrl-0 = <&qup_spi18_default>; 1570 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1571 spi-max-frequency = <50000000>; 1572 #address-cells = <1>; 1573 #size-cells = <0>; 1574 status = "disabled"; 1575 }; 1576 1577 i2c19: i2c@c88000 { 1578 compatible = "qcom,geni-i2c"; 1579 reg = <0 0x00c88000 0 0x4000>; 1580 clock-names = "se"; 1581 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1582 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1583 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1584 dma-names = "tx", "rx"; 1585 pinctrl-names = "default"; 1586 pinctrl-0 = <&qup_i2c19_default>; 1587 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1588 #address-cells = <1>; 1589 #size-cells = <0>; 1590 status = "disabled"; 1591 }; 1592 1593 spi19: spi@c88000 { 1594 compatible = "qcom,geni-spi"; 1595 reg = <0 0xc88000 0 0x4000>; 1596 reg-names = "se"; 1597 clock-names = "se"; 1598 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1599 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1600 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1601 dma-names = "tx", "rx"; 1602 pinctrl-names = "default"; 1603 pinctrl-0 = <&qup_spi19_default>; 1604 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1605 spi-max-frequency = <50000000>; 1606 #address-cells = <1>; 1607 #size-cells = <0>; 1608 status = "disabled"; 1609 }; 1610 1611 i2c13: i2c@c8c000 { 1612 compatible = "qcom,geni-i2c"; 1613 reg = <0 0x00c8c000 0 0x4000>; 1614 clock-names = "se"; 1615 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1616 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1617 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1618 dma-names = "tx", "rx"; 1619 pinctrl-names = "default"; 1620 pinctrl-0 = <&qup_i2c13_default>; 1621 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1622 #address-cells = <1>; 1623 #size-cells = <0>; 1624 status = "disabled"; 1625 }; 1626 1627 spi13: spi@c8c000 { 1628 compatible = "qcom,geni-spi"; 1629 reg = <0 0xc8c000 0 0x4000>; 1630 reg-names = "se"; 1631 clock-names = "se"; 1632 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1633 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1634 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1635 dma-names = "tx", "rx"; 1636 pinctrl-names = "default"; 1637 pinctrl-0 = <&qup_spi13_default>; 1638 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1639 spi-max-frequency = <50000000>; 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 status = "disabled"; 1643 }; 1644 1645 i2c14: i2c@c90000 { 1646 compatible = "qcom,geni-i2c"; 1647 reg = <0 0x00c90000 0 0x4000>; 1648 clock-names = "se"; 1649 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1650 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1651 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1652 dma-names = "tx", "rx"; 1653 pinctrl-names = "default"; 1654 pinctrl-0 = <&qup_i2c14_default>; 1655 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1656 #address-cells = <1>; 1657 #size-cells = <0>; 1658 status = "disabled"; 1659 }; 1660 1661 spi14: spi@c90000 { 1662 compatible = "qcom,geni-spi"; 1663 reg = <0 0xc90000 0 0x4000>; 1664 reg-names = "se"; 1665 clock-names = "se"; 1666 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1667 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1668 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1669 dma-names = "tx", "rx"; 1670 pinctrl-names = "default"; 1671 pinctrl-0 = <&qup_spi14_default>; 1672 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1673 spi-max-frequency = <50000000>; 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 status = "disabled"; 1677 }; 1678 1679 i2c15: i2c@c94000 { 1680 compatible = "qcom,geni-i2c"; 1681 reg = <0 0x00c94000 0 0x4000>; 1682 clock-names = "se"; 1683 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1684 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1685 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1686 dma-names = "tx", "rx"; 1687 pinctrl-names = "default"; 1688 pinctrl-0 = <&qup_i2c15_default>; 1689 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 status = "disabled"; 1693 }; 1694 1695 spi15: spi@c94000 { 1696 compatible = "qcom,geni-spi"; 1697 reg = <0 0xc94000 0 0x4000>; 1698 reg-names = "se"; 1699 clock-names = "se"; 1700 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1701 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1702 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1703 dma-names = "tx", "rx"; 1704 pinctrl-names = "default"; 1705 pinctrl-0 = <&qup_spi15_default>; 1706 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1707 spi-max-frequency = <50000000>; 1708 #address-cells = <1>; 1709 #size-cells = <0>; 1710 status = "disabled"; 1711 }; 1712 }; 1713 1714 config_noc: interconnect@1500000 { 1715 compatible = "qcom,sm8150-config-noc"; 1716 reg = <0 0x01500000 0 0x7400>; 1717 #interconnect-cells = <1>; 1718 qcom,bcm-voters = <&apps_bcm_voter>; 1719 }; 1720 1721 system_noc: interconnect@1620000 { 1722 compatible = "qcom,sm8150-system-noc"; 1723 reg = <0 0x01620000 0 0x19400>; 1724 #interconnect-cells = <1>; 1725 qcom,bcm-voters = <&apps_bcm_voter>; 1726 }; 1727 1728 mc_virt: interconnect@163a000 { 1729 compatible = "qcom,sm8150-mc-virt"; 1730 reg = <0 0x0163a000 0 0x1000>; 1731 #interconnect-cells = <1>; 1732 qcom,bcm-voters = <&apps_bcm_voter>; 1733 }; 1734 1735 aggre1_noc: interconnect@16e0000 { 1736 compatible = "qcom,sm8150-aggre1-noc"; 1737 reg = <0 0x016e0000 0 0xd080>; 1738 #interconnect-cells = <1>; 1739 qcom,bcm-voters = <&apps_bcm_voter>; 1740 }; 1741 1742 aggre2_noc: interconnect@1700000 { 1743 compatible = "qcom,sm8150-aggre2-noc"; 1744 reg = <0 0x01700000 0 0x20000>; 1745 #interconnect-cells = <1>; 1746 qcom,bcm-voters = <&apps_bcm_voter>; 1747 }; 1748 1749 compute_noc: interconnect@1720000 { 1750 compatible = "qcom,sm8150-compute-noc"; 1751 reg = <0 0x01720000 0 0x7000>; 1752 #interconnect-cells = <1>; 1753 qcom,bcm-voters = <&apps_bcm_voter>; 1754 }; 1755 1756 mmss_noc: interconnect@1740000 { 1757 compatible = "qcom,sm8150-mmss-noc"; 1758 reg = <0 0x01740000 0 0x1c100>; 1759 #interconnect-cells = <1>; 1760 qcom,bcm-voters = <&apps_bcm_voter>; 1761 }; 1762 1763 system-cache-controller@9200000 { 1764 compatible = "qcom,sm8150-llcc"; 1765 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 1766 reg-names = "llcc_base", "llcc_broadcast_base"; 1767 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1768 }; 1769 1770 pcie0: pci@1c00000 { 1771 compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1772 reg = <0 0x01c00000 0 0x3000>, 1773 <0 0x60000000 0 0xf1d>, 1774 <0 0x60000f20 0 0xa8>, 1775 <0 0x60001000 0 0x1000>, 1776 <0 0x60100000 0 0x100000>; 1777 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1778 device_type = "pci"; 1779 linux,pci-domain = <0>; 1780 bus-range = <0x00 0xff>; 1781 num-lanes = <1>; 1782 1783 #address-cells = <3>; 1784 #size-cells = <2>; 1785 1786 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1787 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1788 1789 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1790 interrupt-names = "msi"; 1791 #interrupt-cells = <1>; 1792 interrupt-map-mask = <0 0 0 0x7>; 1793 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1794 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1795 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1796 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1797 1798 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1799 <&gcc GCC_PCIE_0_AUX_CLK>, 1800 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1801 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1802 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1803 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1804 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1805 clock-names = "pipe", 1806 "aux", 1807 "cfg", 1808 "bus_master", 1809 "bus_slave", 1810 "slave_q2a", 1811 "tbu"; 1812 1813 iommus = <&apps_smmu 0x1d80 0x7f>; 1814 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1815 <0x100 &apps_smmu 0x1d81 0x1>; 1816 1817 resets = <&gcc GCC_PCIE_0_BCR>; 1818 reset-names = "pci"; 1819 1820 power-domains = <&gcc PCIE_0_GDSC>; 1821 1822 phys = <&pcie0_lane>; 1823 phy-names = "pciephy"; 1824 1825 perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1826 enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1827 1828 pinctrl-names = "default"; 1829 pinctrl-0 = <&pcie0_default_state>; 1830 1831 status = "disabled"; 1832 }; 1833 1834 pcie0_phy: phy@1c06000 { 1835 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1836 reg = <0 0x01c06000 0 0x1c0>; 1837 #address-cells = <2>; 1838 #size-cells = <2>; 1839 ranges; 1840 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1841 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1842 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1843 clock-names = "aux", "cfg_ahb", "refgen"; 1844 1845 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1846 reset-names = "phy"; 1847 1848 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1849 assigned-clock-rates = <100000000>; 1850 1851 status = "disabled"; 1852 1853 pcie0_lane: phy@1c06200 { 1854 reg = <0 0x1c06200 0 0x170>, /* tx */ 1855 <0 0x1c06400 0 0x200>, /* rx */ 1856 <0 0x1c06800 0 0x1f0>, /* pcs */ 1857 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1858 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1859 clock-names = "pipe0"; 1860 1861 #phy-cells = <0>; 1862 clock-output-names = "pcie_0_pipe_clk"; 1863 }; 1864 }; 1865 1866 pcie1: pci@1c08000 { 1867 compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1868 reg = <0 0x01c08000 0 0x3000>, 1869 <0 0x40000000 0 0xf1d>, 1870 <0 0x40000f20 0 0xa8>, 1871 <0 0x40001000 0 0x1000>, 1872 <0 0x40100000 0 0x100000>; 1873 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1874 device_type = "pci"; 1875 linux,pci-domain = <1>; 1876 bus-range = <0x00 0xff>; 1877 num-lanes = <2>; 1878 1879 #address-cells = <3>; 1880 #size-cells = <2>; 1881 1882 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1883 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1884 1885 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1886 interrupt-names = "msi"; 1887 #interrupt-cells = <1>; 1888 interrupt-map-mask = <0 0 0 0x7>; 1889 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1890 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1891 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1892 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1893 1894 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1895 <&gcc GCC_PCIE_1_AUX_CLK>, 1896 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1897 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1898 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1899 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1900 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1901 clock-names = "pipe", 1902 "aux", 1903 "cfg", 1904 "bus_master", 1905 "bus_slave", 1906 "slave_q2a", 1907 "tbu"; 1908 1909 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1910 assigned-clock-rates = <19200000>; 1911 1912 iommus = <&apps_smmu 0x1e00 0x7f>; 1913 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1914 <0x100 &apps_smmu 0x1e01 0x1>; 1915 1916 resets = <&gcc GCC_PCIE_1_BCR>; 1917 reset-names = "pci"; 1918 1919 power-domains = <&gcc PCIE_1_GDSC>; 1920 1921 phys = <&pcie1_lane>; 1922 phy-names = "pciephy"; 1923 1924 perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; 1925 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 1926 1927 pinctrl-names = "default"; 1928 pinctrl-0 = <&pcie1_default_state>; 1929 1930 status = "disabled"; 1931 }; 1932 1933 pcie1_phy: phy@1c0e000 { 1934 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 1935 reg = <0 0x01c0e000 0 0x1c0>; 1936 #address-cells = <2>; 1937 #size-cells = <2>; 1938 ranges; 1939 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1940 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1941 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1942 clock-names = "aux", "cfg_ahb", "refgen"; 1943 1944 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1945 reset-names = "phy"; 1946 1947 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1948 assigned-clock-rates = <100000000>; 1949 1950 status = "disabled"; 1951 1952 pcie1_lane: phy@1c0e200 { 1953 reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1954 <0 0x1c0e400 0 0x200>, /* rx0 */ 1955 <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1956 <0 0x1c0e600 0 0x170>, /* tx1 */ 1957 <0 0x1c0e800 0 0x200>, /* rx1 */ 1958 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1959 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1960 clock-names = "pipe0"; 1961 1962 #phy-cells = <0>; 1963 clock-output-names = "pcie_1_pipe_clk"; 1964 }; 1965 }; 1966 1967 ufs_mem_hc: ufshc@1d84000 { 1968 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 1969 "jedec,ufs-2.0"; 1970 reg = <0 0x01d84000 0 0x2500>, 1971 <0 0x01d90000 0 0x8000>; 1972 reg-names = "std", "ice"; 1973 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1974 phys = <&ufs_mem_phy_lanes>; 1975 phy-names = "ufsphy"; 1976 lanes-per-direction = <2>; 1977 #reset-cells = <1>; 1978 resets = <&gcc GCC_UFS_PHY_BCR>; 1979 reset-names = "rst"; 1980 1981 iommus = <&apps_smmu 0x300 0>; 1982 1983 clock-names = 1984 "core_clk", 1985 "bus_aggr_clk", 1986 "iface_clk", 1987 "core_clk_unipro", 1988 "ref_clk", 1989 "tx_lane0_sync_clk", 1990 "rx_lane0_sync_clk", 1991 "rx_lane1_sync_clk", 1992 "ice_core_clk"; 1993 clocks = 1994 <&gcc GCC_UFS_PHY_AXI_CLK>, 1995 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1996 <&gcc GCC_UFS_PHY_AHB_CLK>, 1997 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1998 <&rpmhcc RPMH_CXO_CLK>, 1999 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2000 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2001 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2002 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2003 freq-table-hz = 2004 <37500000 300000000>, 2005 <0 0>, 2006 <0 0>, 2007 <37500000 300000000>, 2008 <0 0>, 2009 <0 0>, 2010 <0 0>, 2011 <0 0>, 2012 <0 300000000>; 2013 2014 status = "disabled"; 2015 }; 2016 2017 ufs_mem_phy: phy@1d87000 { 2018 compatible = "qcom,sm8150-qmp-ufs-phy"; 2019 reg = <0 0x01d87000 0 0x1c0>; 2020 #address-cells = <2>; 2021 #size-cells = <2>; 2022 ranges; 2023 clock-names = "ref", 2024 "ref_aux"; 2025 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2026 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2027 2028 power-domains = <&gcc UFS_PHY_GDSC>; 2029 2030 resets = <&ufs_mem_hc 0>; 2031 reset-names = "ufsphy"; 2032 status = "disabled"; 2033 2034 ufs_mem_phy_lanes: phy@1d87400 { 2035 reg = <0 0x01d87400 0 0x16c>, 2036 <0 0x01d87600 0 0x200>, 2037 <0 0x01d87c00 0 0x200>, 2038 <0 0x01d87800 0 0x16c>, 2039 <0 0x01d87a00 0 0x200>; 2040 #phy-cells = <0>; 2041 }; 2042 }; 2043 2044 ipa_virt: interconnect@1e00000 { 2045 compatible = "qcom,sm8150-ipa-virt"; 2046 reg = <0 0x01e00000 0 0x1000>; 2047 #interconnect-cells = <1>; 2048 qcom,bcm-voters = <&apps_bcm_voter>; 2049 }; 2050 2051 tcsr_mutex: hwlock@1f40000 { 2052 compatible = "qcom,tcsr-mutex"; 2053 reg = <0x0 0x01f40000 0x0 0x20000>; 2054 #hwlock-cells = <1>; 2055 }; 2056 2057 tcsr_regs_1: syscon@1f60000 { 2058 compatible = "qcom,sm8150-tcsr", "syscon"; 2059 reg = <0x0 0x01f60000 0x0 0x20000>; 2060 }; 2061 2062 remoteproc_slpi: remoteproc@2400000 { 2063 compatible = "qcom,sm8150-slpi-pas"; 2064 reg = <0x0 0x02400000 0x0 0x4040>; 2065 2066 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 2067 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2068 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2069 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2070 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2071 interrupt-names = "wdog", "fatal", "ready", 2072 "handover", "stop-ack"; 2073 2074 clocks = <&rpmhcc RPMH_CXO_CLK>; 2075 clock-names = "xo"; 2076 2077 power-domains = <&rpmhpd SM8150_LCX>, 2078 <&rpmhpd SM8150_LMX>; 2079 power-domain-names = "lcx", "lmx"; 2080 2081 memory-region = <&slpi_mem>; 2082 2083 qcom,qmp = <&aoss_qmp>; 2084 2085 qcom,smem-states = <&slpi_smp2p_out 0>; 2086 qcom,smem-state-names = "stop"; 2087 2088 status = "disabled"; 2089 2090 glink-edge { 2091 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 2092 label = "dsps"; 2093 qcom,remote-pid = <3>; 2094 mboxes = <&apss_shared 24>; 2095 2096 fastrpc { 2097 compatible = "qcom,fastrpc"; 2098 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2099 label = "sdsp"; 2100 qcom,non-secure-domain; 2101 #address-cells = <1>; 2102 #size-cells = <0>; 2103 2104 compute-cb@1 { 2105 compatible = "qcom,fastrpc-compute-cb"; 2106 reg = <1>; 2107 iommus = <&apps_smmu 0x05a1 0x0>; 2108 }; 2109 2110 compute-cb@2 { 2111 compatible = "qcom,fastrpc-compute-cb"; 2112 reg = <2>; 2113 iommus = <&apps_smmu 0x05a2 0x0>; 2114 }; 2115 2116 compute-cb@3 { 2117 compatible = "qcom,fastrpc-compute-cb"; 2118 reg = <3>; 2119 iommus = <&apps_smmu 0x05a3 0x0>; 2120 /* note: shared-cb = <4> in downstream */ 2121 }; 2122 }; 2123 }; 2124 }; 2125 2126 gpu: gpu@2c00000 { 2127 /* 2128 * note: the amd,imageon compatible makes it possible 2129 * to use the drm/msm driver without the display node, 2130 * make sure to remove it when display node is added 2131 */ 2132 compatible = "qcom,adreno-640.1", 2133 "qcom,adreno", 2134 "amd,imageon"; 2135 2136 reg = <0 0x02c00000 0 0x40000>; 2137 reg-names = "kgsl_3d0_reg_memory"; 2138 2139 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2140 2141 iommus = <&adreno_smmu 0 0x401>; 2142 2143 operating-points-v2 = <&gpu_opp_table>; 2144 2145 qcom,gmu = <&gmu>; 2146 2147 status = "disabled"; 2148 2149 zap-shader { 2150 memory-region = <&gpu_mem>; 2151 }; 2152 2153 /* note: downstream checks gpu binning for 675 Mhz */ 2154 gpu_opp_table: opp-table { 2155 compatible = "operating-points-v2"; 2156 2157 opp-675000000 { 2158 opp-hz = /bits/ 64 <675000000>; 2159 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2160 }; 2161 2162 opp-585000000 { 2163 opp-hz = /bits/ 64 <585000000>; 2164 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2165 }; 2166 2167 opp-499200000 { 2168 opp-hz = /bits/ 64 <499200000>; 2169 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2170 }; 2171 2172 opp-427000000 { 2173 opp-hz = /bits/ 64 <427000000>; 2174 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2175 }; 2176 2177 opp-345000000 { 2178 opp-hz = /bits/ 64 <345000000>; 2179 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2180 }; 2181 2182 opp-257000000 { 2183 opp-hz = /bits/ 64 <257000000>; 2184 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2185 }; 2186 }; 2187 }; 2188 2189 gmu: gmu@2c6a000 { 2190 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2191 2192 reg = <0 0x02c6a000 0 0x30000>, 2193 <0 0x0b290000 0 0x10000>, 2194 <0 0x0b490000 0 0x10000>; 2195 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2196 2197 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2198 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2199 interrupt-names = "hfi", "gmu"; 2200 2201 clocks = <&gpucc GPU_CC_AHB_CLK>, 2202 <&gpucc GPU_CC_CX_GMU_CLK>, 2203 <&gpucc GPU_CC_CXO_CLK>, 2204 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2205 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2206 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2207 2208 power-domains = <&gpucc GPU_CX_GDSC>, 2209 <&gpucc GPU_GX_GDSC>; 2210 power-domain-names = "cx", "gx"; 2211 2212 iommus = <&adreno_smmu 5 0x400>; 2213 2214 operating-points-v2 = <&gmu_opp_table>; 2215 2216 status = "disabled"; 2217 2218 gmu_opp_table: opp-table { 2219 compatible = "operating-points-v2"; 2220 2221 opp-200000000 { 2222 opp-hz = /bits/ 64 <200000000>; 2223 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2224 }; 2225 }; 2226 }; 2227 2228 gpucc: clock-controller@2c90000 { 2229 compatible = "qcom,sm8150-gpucc"; 2230 reg = <0 0x02c90000 0 0x9000>; 2231 clocks = <&rpmhcc RPMH_CXO_CLK>, 2232 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2233 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2234 clock-names = "bi_tcxo", 2235 "gcc_gpu_gpll0_clk_src", 2236 "gcc_gpu_gpll0_div_clk_src"; 2237 #clock-cells = <1>; 2238 #reset-cells = <1>; 2239 #power-domain-cells = <1>; 2240 }; 2241 2242 adreno_smmu: iommu@2ca0000 { 2243 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 2244 reg = <0 0x02ca0000 0 0x10000>; 2245 #iommu-cells = <2>; 2246 #global-interrupts = <1>; 2247 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2248 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2249 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2250 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2251 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2252 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2253 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2254 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2255 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2256 clocks = <&gpucc GPU_CC_AHB_CLK>, 2257 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2258 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2259 clock-names = "ahb", "bus", "iface"; 2260 2261 power-domains = <&gpucc GPU_CX_GDSC>; 2262 }; 2263 2264 tlmm: pinctrl@3100000 { 2265 compatible = "qcom,sm8150-pinctrl"; 2266 reg = <0x0 0x03100000 0x0 0x300000>, 2267 <0x0 0x03500000 0x0 0x300000>, 2268 <0x0 0x03900000 0x0 0x300000>, 2269 <0x0 0x03D00000 0x0 0x300000>; 2270 reg-names = "west", "east", "north", "south"; 2271 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2272 gpio-ranges = <&tlmm 0 0 176>; 2273 gpio-controller; 2274 #gpio-cells = <2>; 2275 interrupt-controller; 2276 #interrupt-cells = <2>; 2277 wakeup-parent = <&pdc>; 2278 2279 qup_i2c0_default: qup-i2c0-default-state { 2280 pins = "gpio0", "gpio1"; 2281 function = "qup0"; 2282 drive-strength = <0x02>; 2283 bias-disable; 2284 }; 2285 2286 qup_spi0_default: qup-spi0-default-state { 2287 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2288 function = "qup0"; 2289 drive-strength = <6>; 2290 bias-disable; 2291 }; 2292 2293 qup_i2c1_default: qup-i2c1-default-state { 2294 pins = "gpio114", "gpio115"; 2295 function = "qup1"; 2296 drive-strength = <2>; 2297 bias-disable; 2298 }; 2299 2300 qup_spi1_default: qup-spi1-default-state { 2301 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2302 function = "qup1"; 2303 drive-strength = <6>; 2304 bias-disable; 2305 }; 2306 2307 qup_i2c2_default: qup-i2c2-default-state { 2308 pins = "gpio126", "gpio127"; 2309 function = "qup2"; 2310 drive-strength = <2>; 2311 bias-disable; 2312 }; 2313 2314 qup_spi2_default: qup-spi2-default-state { 2315 pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2316 function = "qup2"; 2317 drive-strength = <6>; 2318 bias-disable; 2319 }; 2320 2321 qup_i2c3_default: qup-i2c3-default-state { 2322 pins = "gpio144", "gpio145"; 2323 function = "qup3"; 2324 drive-strength = <2>; 2325 bias-disable; 2326 }; 2327 2328 qup_spi3_default: qup-spi3-default-state { 2329 pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2330 function = "qup3"; 2331 drive-strength = <6>; 2332 bias-disable; 2333 }; 2334 2335 qup_i2c4_default: qup-i2c4-default-state { 2336 pins = "gpio51", "gpio52"; 2337 function = "qup4"; 2338 drive-strength = <2>; 2339 bias-disable; 2340 }; 2341 2342 qup_spi4_default: qup-spi4-default-state { 2343 pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2344 function = "qup4"; 2345 drive-strength = <6>; 2346 bias-disable; 2347 }; 2348 2349 qup_i2c5_default: qup-i2c5-default-state { 2350 pins = "gpio121", "gpio122"; 2351 function = "qup5"; 2352 drive-strength = <2>; 2353 bias-disable; 2354 }; 2355 2356 qup_spi5_default: qup-spi5-default-state { 2357 pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2358 function = "qup5"; 2359 drive-strength = <6>; 2360 bias-disable; 2361 }; 2362 2363 qup_i2c6_default: qup-i2c6-default-state { 2364 pins = "gpio6", "gpio7"; 2365 function = "qup6"; 2366 drive-strength = <2>; 2367 bias-disable; 2368 }; 2369 2370 qup_spi6_default: qup-spi6_default-state { 2371 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2372 function = "qup6"; 2373 drive-strength = <6>; 2374 bias-disable; 2375 }; 2376 2377 qup_i2c7_default: qup-i2c7-default-state { 2378 pins = "gpio98", "gpio99"; 2379 function = "qup7"; 2380 drive-strength = <2>; 2381 bias-disable; 2382 }; 2383 2384 qup_spi7_default: qup-spi7_default-state { 2385 pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2386 function = "qup7"; 2387 drive-strength = <6>; 2388 bias-disable; 2389 }; 2390 2391 qup_i2c8_default: qup-i2c8-default-state { 2392 pins = "gpio88", "gpio89"; 2393 function = "qup8"; 2394 drive-strength = <2>; 2395 bias-disable; 2396 }; 2397 2398 qup_spi8_default: qup-spi8-default-state { 2399 pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2400 function = "qup8"; 2401 drive-strength = <6>; 2402 bias-disable; 2403 }; 2404 2405 qup_i2c9_default: qup-i2c9-default-state { 2406 pins = "gpio39", "gpio40"; 2407 function = "qup9"; 2408 drive-strength = <2>; 2409 bias-disable; 2410 }; 2411 2412 qup_spi9_default: qup-spi9-default-state { 2413 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2414 function = "qup9"; 2415 drive-strength = <6>; 2416 bias-disable; 2417 }; 2418 2419 qup_i2c10_default: qup-i2c10-default-state { 2420 pins = "gpio9", "gpio10"; 2421 function = "qup10"; 2422 drive-strength = <2>; 2423 bias-disable; 2424 }; 2425 2426 qup_spi10_default: qup-spi10-default-state { 2427 pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2428 function = "qup10"; 2429 drive-strength = <6>; 2430 bias-disable; 2431 }; 2432 2433 qup_i2c11_default: qup-i2c11-default-state { 2434 pins = "gpio94", "gpio95"; 2435 function = "qup11"; 2436 drive-strength = <2>; 2437 bias-disable; 2438 }; 2439 2440 qup_spi11_default: qup-spi11-default-state { 2441 pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2442 function = "qup11"; 2443 drive-strength = <6>; 2444 bias-disable; 2445 }; 2446 2447 qup_i2c12_default: qup-i2c12-default-state { 2448 pins = "gpio83", "gpio84"; 2449 function = "qup12"; 2450 drive-strength = <2>; 2451 bias-disable; 2452 }; 2453 2454 qup_spi12_default: qup-spi12-default-state { 2455 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2456 function = "qup12"; 2457 drive-strength = <6>; 2458 bias-disable; 2459 }; 2460 2461 qup_i2c13_default: qup-i2c13-default-state { 2462 pins = "gpio43", "gpio44"; 2463 function = "qup13"; 2464 drive-strength = <2>; 2465 bias-disable; 2466 }; 2467 2468 qup_spi13_default: qup-spi13-default-state { 2469 pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2470 function = "qup13"; 2471 drive-strength = <6>; 2472 bias-disable; 2473 }; 2474 2475 qup_i2c14_default: qup-i2c14-default-state { 2476 pins = "gpio47", "gpio48"; 2477 function = "qup14"; 2478 drive-strength = <2>; 2479 bias-disable; 2480 }; 2481 2482 qup_spi14_default: qup-spi14-default-state { 2483 pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2484 function = "qup14"; 2485 drive-strength = <6>; 2486 bias-disable; 2487 }; 2488 2489 qup_i2c15_default: qup-i2c15-default-state { 2490 pins = "gpio27", "gpio28"; 2491 function = "qup15"; 2492 drive-strength = <2>; 2493 bias-disable; 2494 }; 2495 2496 qup_spi15_default: qup-spi15-default-state { 2497 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2498 function = "qup15"; 2499 drive-strength = <6>; 2500 bias-disable; 2501 }; 2502 2503 qup_i2c16_default: qup-i2c16-default-state { 2504 pins = "gpio86", "gpio85"; 2505 function = "qup16"; 2506 drive-strength = <2>; 2507 bias-disable; 2508 }; 2509 2510 qup_spi16_default: qup-spi16-default-state { 2511 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2512 function = "qup16"; 2513 drive-strength = <6>; 2514 bias-disable; 2515 }; 2516 2517 qup_i2c17_default: qup-i2c17-default-state { 2518 pins = "gpio55", "gpio56"; 2519 function = "qup17"; 2520 drive-strength = <2>; 2521 bias-disable; 2522 }; 2523 2524 qup_spi17_default: qup-spi17-default-state { 2525 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2526 function = "qup17"; 2527 drive-strength = <6>; 2528 bias-disable; 2529 }; 2530 2531 qup_i2c18_default: qup-i2c18-default-state { 2532 pins = "gpio23", "gpio24"; 2533 function = "qup18"; 2534 drive-strength = <2>; 2535 bias-disable; 2536 }; 2537 2538 qup_spi18_default: qup-spi18-default-state { 2539 pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2540 function = "qup18"; 2541 drive-strength = <6>; 2542 bias-disable; 2543 }; 2544 2545 qup_i2c19_default: qup-i2c19-default-state { 2546 pins = "gpio57", "gpio58"; 2547 function = "qup19"; 2548 drive-strength = <2>; 2549 bias-disable; 2550 }; 2551 2552 qup_spi19_default: qup-spi19-default-state { 2553 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2554 function = "qup19"; 2555 drive-strength = <6>; 2556 bias-disable; 2557 }; 2558 2559 pcie0_default_state: pcie0-default-state { 2560 perst-pins { 2561 pins = "gpio35"; 2562 function = "gpio"; 2563 drive-strength = <2>; 2564 bias-pull-down; 2565 }; 2566 2567 clkreq-pins { 2568 pins = "gpio36"; 2569 function = "pci_e0"; 2570 drive-strength = <2>; 2571 bias-pull-up; 2572 }; 2573 2574 wake-pins { 2575 pins = "gpio37"; 2576 function = "gpio"; 2577 drive-strength = <2>; 2578 bias-pull-up; 2579 }; 2580 }; 2581 2582 pcie1_default_state: pcie1-default-state { 2583 perst-pins { 2584 pins = "gpio102"; 2585 function = "gpio"; 2586 drive-strength = <2>; 2587 bias-pull-down; 2588 }; 2589 2590 clkreq-pins { 2591 pins = "gpio103"; 2592 function = "pci_e1"; 2593 drive-strength = <2>; 2594 bias-pull-up; 2595 }; 2596 2597 wake-pins { 2598 pins = "gpio104"; 2599 function = "gpio"; 2600 drive-strength = <2>; 2601 bias-pull-up; 2602 }; 2603 }; 2604 }; 2605 2606 remoteproc_mpss: remoteproc@4080000 { 2607 compatible = "qcom,sm8150-mpss-pas"; 2608 reg = <0x0 0x04080000 0x0 0x4040>; 2609 2610 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2611 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2612 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2613 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2614 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2615 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2616 interrupt-names = "wdog", "fatal", "ready", "handover", 2617 "stop-ack", "shutdown-ack"; 2618 2619 clocks = <&rpmhcc RPMH_CXO_CLK>; 2620 clock-names = "xo"; 2621 2622 power-domains = <&rpmhpd SM8150_CX>, 2623 <&rpmhpd SM8150_MSS>; 2624 power-domain-names = "cx", "mss"; 2625 2626 memory-region = <&mpss_mem>; 2627 2628 qcom,qmp = <&aoss_qmp>; 2629 2630 qcom,smem-states = <&modem_smp2p_out 0>; 2631 qcom,smem-state-names = "stop"; 2632 2633 status = "disabled"; 2634 2635 glink-edge { 2636 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2637 label = "modem"; 2638 qcom,remote-pid = <1>; 2639 mboxes = <&apss_shared 12>; 2640 }; 2641 }; 2642 2643 stm@6002000 { 2644 compatible = "arm,coresight-stm", "arm,primecell"; 2645 reg = <0 0x06002000 0 0x1000>, 2646 <0 0x16280000 0 0x180000>; 2647 reg-names = "stm-base", "stm-stimulus-base"; 2648 2649 clocks = <&aoss_qmp>; 2650 clock-names = "apb_pclk"; 2651 2652 out-ports { 2653 port { 2654 stm_out: endpoint { 2655 remote-endpoint = <&funnel0_in7>; 2656 }; 2657 }; 2658 }; 2659 }; 2660 2661 funnel@6041000 { 2662 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2663 reg = <0 0x06041000 0 0x1000>; 2664 2665 clocks = <&aoss_qmp>; 2666 clock-names = "apb_pclk"; 2667 2668 out-ports { 2669 port { 2670 funnel0_out: endpoint { 2671 remote-endpoint = <&merge_funnel_in0>; 2672 }; 2673 }; 2674 }; 2675 2676 in-ports { 2677 #address-cells = <1>; 2678 #size-cells = <0>; 2679 2680 port@7 { 2681 reg = <7>; 2682 funnel0_in7: endpoint { 2683 remote-endpoint = <&stm_out>; 2684 }; 2685 }; 2686 }; 2687 }; 2688 2689 funnel@6042000 { 2690 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2691 reg = <0 0x06042000 0 0x1000>; 2692 2693 clocks = <&aoss_qmp>; 2694 clock-names = "apb_pclk"; 2695 2696 out-ports { 2697 port { 2698 funnel1_out: endpoint { 2699 remote-endpoint = <&merge_funnel_in1>; 2700 }; 2701 }; 2702 }; 2703 2704 in-ports { 2705 #address-cells = <1>; 2706 #size-cells = <0>; 2707 2708 port@4 { 2709 reg = <4>; 2710 funnel1_in4: endpoint { 2711 remote-endpoint = <&swao_replicator_out>; 2712 }; 2713 }; 2714 }; 2715 }; 2716 2717 funnel@6043000 { 2718 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2719 reg = <0 0x06043000 0 0x1000>; 2720 2721 clocks = <&aoss_qmp>; 2722 clock-names = "apb_pclk"; 2723 2724 out-ports { 2725 port { 2726 funnel2_out: endpoint { 2727 remote-endpoint = <&merge_funnel_in2>; 2728 }; 2729 }; 2730 }; 2731 2732 in-ports { 2733 #address-cells = <1>; 2734 #size-cells = <0>; 2735 2736 port@2 { 2737 reg = <2>; 2738 funnel2_in2: endpoint { 2739 remote-endpoint = <&apss_merge_funnel_out>; 2740 }; 2741 }; 2742 }; 2743 }; 2744 2745 funnel@6045000 { 2746 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2747 reg = <0 0x06045000 0 0x1000>; 2748 2749 clocks = <&aoss_qmp>; 2750 clock-names = "apb_pclk"; 2751 2752 out-ports { 2753 port { 2754 merge_funnel_out: endpoint { 2755 remote-endpoint = <&etf_in>; 2756 }; 2757 }; 2758 }; 2759 2760 in-ports { 2761 #address-cells = <1>; 2762 #size-cells = <0>; 2763 2764 port@0 { 2765 reg = <0>; 2766 merge_funnel_in0: endpoint { 2767 remote-endpoint = <&funnel0_out>; 2768 }; 2769 }; 2770 2771 port@1 { 2772 reg = <1>; 2773 merge_funnel_in1: endpoint { 2774 remote-endpoint = <&funnel1_out>; 2775 }; 2776 }; 2777 2778 port@2 { 2779 reg = <2>; 2780 merge_funnel_in2: endpoint { 2781 remote-endpoint = <&funnel2_out>; 2782 }; 2783 }; 2784 }; 2785 }; 2786 2787 replicator@6046000 { 2788 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2789 reg = <0 0x06046000 0 0x1000>; 2790 2791 clocks = <&aoss_qmp>; 2792 clock-names = "apb_pclk"; 2793 2794 out-ports { 2795 #address-cells = <1>; 2796 #size-cells = <0>; 2797 2798 port@0 { 2799 reg = <0>; 2800 replicator_out0: endpoint { 2801 remote-endpoint = <&etr_in>; 2802 }; 2803 }; 2804 2805 port@1 { 2806 reg = <1>; 2807 replicator_out1: endpoint { 2808 remote-endpoint = <&replicator1_in>; 2809 }; 2810 }; 2811 }; 2812 2813 in-ports { 2814 port { 2815 replicator_in0: endpoint { 2816 remote-endpoint = <&etf_out>; 2817 }; 2818 }; 2819 }; 2820 }; 2821 2822 etf@6047000 { 2823 compatible = "arm,coresight-tmc", "arm,primecell"; 2824 reg = <0 0x06047000 0 0x1000>; 2825 2826 clocks = <&aoss_qmp>; 2827 clock-names = "apb_pclk"; 2828 2829 out-ports { 2830 port { 2831 etf_out: endpoint { 2832 remote-endpoint = <&replicator_in0>; 2833 }; 2834 }; 2835 }; 2836 2837 in-ports { 2838 port { 2839 etf_in: endpoint { 2840 remote-endpoint = <&merge_funnel_out>; 2841 }; 2842 }; 2843 }; 2844 }; 2845 2846 etr@6048000 { 2847 compatible = "arm,coresight-tmc", "arm,primecell"; 2848 reg = <0 0x06048000 0 0x1000>; 2849 iommus = <&apps_smmu 0x05e0 0x0>; 2850 2851 clocks = <&aoss_qmp>; 2852 clock-names = "apb_pclk"; 2853 arm,scatter-gather; 2854 2855 in-ports { 2856 port { 2857 etr_in: endpoint { 2858 remote-endpoint = <&replicator_out0>; 2859 }; 2860 }; 2861 }; 2862 }; 2863 2864 replicator@604a000 { 2865 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2866 reg = <0 0x0604a000 0 0x1000>; 2867 2868 clocks = <&aoss_qmp>; 2869 clock-names = "apb_pclk"; 2870 2871 out-ports { 2872 #address-cells = <1>; 2873 #size-cells = <0>; 2874 2875 port@1 { 2876 reg = <1>; 2877 replicator1_out: endpoint { 2878 remote-endpoint = <&swao_funnel_in>; 2879 }; 2880 }; 2881 }; 2882 2883 in-ports { 2884 #address-cells = <1>; 2885 #size-cells = <0>; 2886 2887 port@1 { 2888 reg = <1>; 2889 replicator1_in: endpoint { 2890 remote-endpoint = <&replicator_out1>; 2891 }; 2892 }; 2893 }; 2894 }; 2895 2896 funnel@6b08000 { 2897 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2898 reg = <0 0x06b08000 0 0x1000>; 2899 2900 clocks = <&aoss_qmp>; 2901 clock-names = "apb_pclk"; 2902 2903 out-ports { 2904 port { 2905 swao_funnel_out: endpoint { 2906 remote-endpoint = <&swao_etf_in>; 2907 }; 2908 }; 2909 }; 2910 2911 in-ports { 2912 #address-cells = <1>; 2913 #size-cells = <0>; 2914 2915 port@6 { 2916 reg = <6>; 2917 swao_funnel_in: endpoint { 2918 remote-endpoint = <&replicator1_out>; 2919 }; 2920 }; 2921 }; 2922 }; 2923 2924 etf@6b09000 { 2925 compatible = "arm,coresight-tmc", "arm,primecell"; 2926 reg = <0 0x06b09000 0 0x1000>; 2927 2928 clocks = <&aoss_qmp>; 2929 clock-names = "apb_pclk"; 2930 2931 out-ports { 2932 port { 2933 swao_etf_out: endpoint { 2934 remote-endpoint = <&swao_replicator_in>; 2935 }; 2936 }; 2937 }; 2938 2939 in-ports { 2940 port { 2941 swao_etf_in: endpoint { 2942 remote-endpoint = <&swao_funnel_out>; 2943 }; 2944 }; 2945 }; 2946 }; 2947 2948 replicator@6b0a000 { 2949 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2950 reg = <0 0x06b0a000 0 0x1000>; 2951 2952 clocks = <&aoss_qmp>; 2953 clock-names = "apb_pclk"; 2954 qcom,replicator-loses-context; 2955 2956 out-ports { 2957 port { 2958 swao_replicator_out: endpoint { 2959 remote-endpoint = <&funnel1_in4>; 2960 }; 2961 }; 2962 }; 2963 2964 in-ports { 2965 port { 2966 swao_replicator_in: endpoint { 2967 remote-endpoint = <&swao_etf_out>; 2968 }; 2969 }; 2970 }; 2971 }; 2972 2973 etm@7040000 { 2974 compatible = "arm,coresight-etm4x", "arm,primecell"; 2975 reg = <0 0x07040000 0 0x1000>; 2976 2977 cpu = <&CPU0>; 2978 2979 clocks = <&aoss_qmp>; 2980 clock-names = "apb_pclk"; 2981 arm,coresight-loses-context-with-cpu; 2982 qcom,skip-power-up; 2983 2984 out-ports { 2985 port { 2986 etm0_out: endpoint { 2987 remote-endpoint = <&apss_funnel_in0>; 2988 }; 2989 }; 2990 }; 2991 }; 2992 2993 etm@7140000 { 2994 compatible = "arm,coresight-etm4x", "arm,primecell"; 2995 reg = <0 0x07140000 0 0x1000>; 2996 2997 cpu = <&CPU1>; 2998 2999 clocks = <&aoss_qmp>; 3000 clock-names = "apb_pclk"; 3001 arm,coresight-loses-context-with-cpu; 3002 qcom,skip-power-up; 3003 3004 out-ports { 3005 port { 3006 etm1_out: endpoint { 3007 remote-endpoint = <&apss_funnel_in1>; 3008 }; 3009 }; 3010 }; 3011 }; 3012 3013 etm@7240000 { 3014 compatible = "arm,coresight-etm4x", "arm,primecell"; 3015 reg = <0 0x07240000 0 0x1000>; 3016 3017 cpu = <&CPU2>; 3018 3019 clocks = <&aoss_qmp>; 3020 clock-names = "apb_pclk"; 3021 arm,coresight-loses-context-with-cpu; 3022 qcom,skip-power-up; 3023 3024 out-ports { 3025 port { 3026 etm2_out: endpoint { 3027 remote-endpoint = <&apss_funnel_in2>; 3028 }; 3029 }; 3030 }; 3031 }; 3032 3033 etm@7340000 { 3034 compatible = "arm,coresight-etm4x", "arm,primecell"; 3035 reg = <0 0x07340000 0 0x1000>; 3036 3037 cpu = <&CPU3>; 3038 3039 clocks = <&aoss_qmp>; 3040 clock-names = "apb_pclk"; 3041 arm,coresight-loses-context-with-cpu; 3042 qcom,skip-power-up; 3043 3044 out-ports { 3045 port { 3046 etm3_out: endpoint { 3047 remote-endpoint = <&apss_funnel_in3>; 3048 }; 3049 }; 3050 }; 3051 }; 3052 3053 etm@7440000 { 3054 compatible = "arm,coresight-etm4x", "arm,primecell"; 3055 reg = <0 0x07440000 0 0x1000>; 3056 3057 cpu = <&CPU4>; 3058 3059 clocks = <&aoss_qmp>; 3060 clock-names = "apb_pclk"; 3061 arm,coresight-loses-context-with-cpu; 3062 qcom,skip-power-up; 3063 3064 out-ports { 3065 port { 3066 etm4_out: endpoint { 3067 remote-endpoint = <&apss_funnel_in4>; 3068 }; 3069 }; 3070 }; 3071 }; 3072 3073 etm@7540000 { 3074 compatible = "arm,coresight-etm4x", "arm,primecell"; 3075 reg = <0 0x07540000 0 0x1000>; 3076 3077 cpu = <&CPU5>; 3078 3079 clocks = <&aoss_qmp>; 3080 clock-names = "apb_pclk"; 3081 arm,coresight-loses-context-with-cpu; 3082 qcom,skip-power-up; 3083 3084 out-ports { 3085 port { 3086 etm5_out: endpoint { 3087 remote-endpoint = <&apss_funnel_in5>; 3088 }; 3089 }; 3090 }; 3091 }; 3092 3093 etm@7640000 { 3094 compatible = "arm,coresight-etm4x", "arm,primecell"; 3095 reg = <0 0x07640000 0 0x1000>; 3096 3097 cpu = <&CPU6>; 3098 3099 clocks = <&aoss_qmp>; 3100 clock-names = "apb_pclk"; 3101 arm,coresight-loses-context-with-cpu; 3102 qcom,skip-power-up; 3103 3104 out-ports { 3105 port { 3106 etm6_out: endpoint { 3107 remote-endpoint = <&apss_funnel_in6>; 3108 }; 3109 }; 3110 }; 3111 }; 3112 3113 etm@7740000 { 3114 compatible = "arm,coresight-etm4x", "arm,primecell"; 3115 reg = <0 0x07740000 0 0x1000>; 3116 3117 cpu = <&CPU7>; 3118 3119 clocks = <&aoss_qmp>; 3120 clock-names = "apb_pclk"; 3121 arm,coresight-loses-context-with-cpu; 3122 qcom,skip-power-up; 3123 3124 out-ports { 3125 port { 3126 etm7_out: endpoint { 3127 remote-endpoint = <&apss_funnel_in7>; 3128 }; 3129 }; 3130 }; 3131 }; 3132 3133 funnel@7800000 { /* APSS Funnel */ 3134 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3135 reg = <0 0x07800000 0 0x1000>; 3136 3137 clocks = <&aoss_qmp>; 3138 clock-names = "apb_pclk"; 3139 3140 out-ports { 3141 port { 3142 apss_funnel_out: endpoint { 3143 remote-endpoint = <&apss_merge_funnel_in>; 3144 }; 3145 }; 3146 }; 3147 3148 in-ports { 3149 #address-cells = <1>; 3150 #size-cells = <0>; 3151 3152 port@0 { 3153 reg = <0>; 3154 apss_funnel_in0: endpoint { 3155 remote-endpoint = <&etm0_out>; 3156 }; 3157 }; 3158 3159 port@1 { 3160 reg = <1>; 3161 apss_funnel_in1: endpoint { 3162 remote-endpoint = <&etm1_out>; 3163 }; 3164 }; 3165 3166 port@2 { 3167 reg = <2>; 3168 apss_funnel_in2: endpoint { 3169 remote-endpoint = <&etm2_out>; 3170 }; 3171 }; 3172 3173 port@3 { 3174 reg = <3>; 3175 apss_funnel_in3: endpoint { 3176 remote-endpoint = <&etm3_out>; 3177 }; 3178 }; 3179 3180 port@4 { 3181 reg = <4>; 3182 apss_funnel_in4: endpoint { 3183 remote-endpoint = <&etm4_out>; 3184 }; 3185 }; 3186 3187 port@5 { 3188 reg = <5>; 3189 apss_funnel_in5: endpoint { 3190 remote-endpoint = <&etm5_out>; 3191 }; 3192 }; 3193 3194 port@6 { 3195 reg = <6>; 3196 apss_funnel_in6: endpoint { 3197 remote-endpoint = <&etm6_out>; 3198 }; 3199 }; 3200 3201 port@7 { 3202 reg = <7>; 3203 apss_funnel_in7: endpoint { 3204 remote-endpoint = <&etm7_out>; 3205 }; 3206 }; 3207 }; 3208 }; 3209 3210 funnel@7810000 { 3211 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3212 reg = <0 0x07810000 0 0x1000>; 3213 3214 clocks = <&aoss_qmp>; 3215 clock-names = "apb_pclk"; 3216 3217 out-ports { 3218 port { 3219 apss_merge_funnel_out: endpoint { 3220 remote-endpoint = <&funnel2_in2>; 3221 }; 3222 }; 3223 }; 3224 3225 in-ports { 3226 port { 3227 apss_merge_funnel_in: endpoint { 3228 remote-endpoint = <&apss_funnel_out>; 3229 }; 3230 }; 3231 }; 3232 }; 3233 3234 remoteproc_cdsp: remoteproc@8300000 { 3235 compatible = "qcom,sm8150-cdsp-pas"; 3236 reg = <0x0 0x08300000 0x0 0x4040>; 3237 3238 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3239 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3240 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3241 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3242 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3243 interrupt-names = "wdog", "fatal", "ready", 3244 "handover", "stop-ack"; 3245 3246 clocks = <&rpmhcc RPMH_CXO_CLK>; 3247 clock-names = "xo"; 3248 3249 power-domains = <&rpmhpd SM8150_CX>; 3250 3251 memory-region = <&cdsp_mem>; 3252 3253 qcom,qmp = <&aoss_qmp>; 3254 3255 qcom,smem-states = <&cdsp_smp2p_out 0>; 3256 qcom,smem-state-names = "stop"; 3257 3258 status = "disabled"; 3259 3260 glink-edge { 3261 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 3262 label = "cdsp"; 3263 qcom,remote-pid = <5>; 3264 mboxes = <&apss_shared 4>; 3265 3266 fastrpc { 3267 compatible = "qcom,fastrpc"; 3268 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3269 label = "cdsp"; 3270 qcom,non-secure-domain; 3271 #address-cells = <1>; 3272 #size-cells = <0>; 3273 3274 compute-cb@1 { 3275 compatible = "qcom,fastrpc-compute-cb"; 3276 reg = <1>; 3277 iommus = <&apps_smmu 0x1001 0x0460>; 3278 }; 3279 3280 compute-cb@2 { 3281 compatible = "qcom,fastrpc-compute-cb"; 3282 reg = <2>; 3283 iommus = <&apps_smmu 0x1002 0x0460>; 3284 }; 3285 3286 compute-cb@3 { 3287 compatible = "qcom,fastrpc-compute-cb"; 3288 reg = <3>; 3289 iommus = <&apps_smmu 0x1003 0x0460>; 3290 }; 3291 3292 compute-cb@4 { 3293 compatible = "qcom,fastrpc-compute-cb"; 3294 reg = <4>; 3295 iommus = <&apps_smmu 0x1004 0x0460>; 3296 }; 3297 3298 compute-cb@5 { 3299 compatible = "qcom,fastrpc-compute-cb"; 3300 reg = <5>; 3301 iommus = <&apps_smmu 0x1005 0x0460>; 3302 }; 3303 3304 compute-cb@6 { 3305 compatible = "qcom,fastrpc-compute-cb"; 3306 reg = <6>; 3307 iommus = <&apps_smmu 0x1006 0x0460>; 3308 }; 3309 3310 compute-cb@7 { 3311 compatible = "qcom,fastrpc-compute-cb"; 3312 reg = <7>; 3313 iommus = <&apps_smmu 0x1007 0x0460>; 3314 }; 3315 3316 compute-cb@8 { 3317 compatible = "qcom,fastrpc-compute-cb"; 3318 reg = <8>; 3319 iommus = <&apps_smmu 0x1008 0x0460>; 3320 }; 3321 3322 /* note: secure cb9 in downstream */ 3323 }; 3324 }; 3325 }; 3326 3327 usb_1_hsphy: phy@88e2000 { 3328 compatible = "qcom,sm8150-usb-hs-phy", 3329 "qcom,usb-snps-hs-7nm-phy"; 3330 reg = <0 0x088e2000 0 0x400>; 3331 status = "disabled"; 3332 #phy-cells = <0>; 3333 3334 clocks = <&rpmhcc RPMH_CXO_CLK>; 3335 clock-names = "ref"; 3336 3337 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3338 }; 3339 3340 usb_2_hsphy: phy@88e3000 { 3341 compatible = "qcom,sm8150-usb-hs-phy", 3342 "qcom,usb-snps-hs-7nm-phy"; 3343 reg = <0 0x088e3000 0 0x400>; 3344 status = "disabled"; 3345 #phy-cells = <0>; 3346 3347 clocks = <&rpmhcc RPMH_CXO_CLK>; 3348 clock-names = "ref"; 3349 3350 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3351 }; 3352 3353 usb_1_qmpphy: phy@88e9000 { 3354 compatible = "qcom,sm8150-qmp-usb3-phy"; 3355 reg = <0 0x088e9000 0 0x18c>, 3356 <0 0x088e8000 0 0x10>; 3357 status = "disabled"; 3358 #address-cells = <2>; 3359 #size-cells = <2>; 3360 ranges; 3361 3362 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3363 <&rpmhcc RPMH_CXO_CLK>, 3364 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3365 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3366 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3367 3368 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3369 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3370 reset-names = "phy", "common"; 3371 3372 usb_1_ssphy: phy@88e9200 { 3373 reg = <0 0x088e9200 0 0x200>, 3374 <0 0x088e9400 0 0x200>, 3375 <0 0x088e9c00 0 0x218>, 3376 <0 0x088e9600 0 0x200>, 3377 <0 0x088e9800 0 0x200>, 3378 <0 0x088e9a00 0 0x100>; 3379 #clock-cells = <0>; 3380 #phy-cells = <0>; 3381 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3382 clock-names = "pipe0"; 3383 clock-output-names = "usb3_phy_pipe_clk_src"; 3384 }; 3385 }; 3386 3387 usb_2_qmpphy: phy@88eb000 { 3388 compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 3389 reg = <0 0x088eb000 0 0x200>; 3390 status = "disabled"; 3391 #address-cells = <2>; 3392 #size-cells = <2>; 3393 ranges; 3394 3395 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3396 <&rpmhcc RPMH_CXO_CLK>, 3397 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3398 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3399 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3400 3401 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3402 <&gcc GCC_USB3_PHY_SEC_BCR>; 3403 reset-names = "phy", "common"; 3404 3405 usb_2_ssphy: phy@88eb200 { 3406 reg = <0 0x088eb200 0 0x200>, 3407 <0 0x088eb400 0 0x200>, 3408 <0 0x088eb800 0 0x800>, 3409 <0 0x088eb600 0 0x200>; 3410 #clock-cells = <0>; 3411 #phy-cells = <0>; 3412 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3413 clock-names = "pipe0"; 3414 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3415 }; 3416 }; 3417 3418 sdhc_2: mmc@8804000 { 3419 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3420 reg = <0 0x08804000 0 0x1000>; 3421 3422 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3423 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3424 interrupt-names = "hc_irq", "pwr_irq"; 3425 3426 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3427 <&gcc GCC_SDCC2_APPS_CLK>, 3428 <&rpmhcc RPMH_CXO_CLK>; 3429 clock-names = "iface", "core", "xo"; 3430 iommus = <&apps_smmu 0x6a0 0x0>; 3431 qcom,dll-config = <0x0007642c>; 3432 qcom,ddr-config = <0x80040868>; 3433 power-domains = <&rpmhpd 0>; 3434 operating-points-v2 = <&sdhc2_opp_table>; 3435 3436 status = "disabled"; 3437 3438 sdhc2_opp_table: opp-table { 3439 compatible = "operating-points-v2"; 3440 3441 opp-19200000 { 3442 opp-hz = /bits/ 64 <19200000>; 3443 required-opps = <&rpmhpd_opp_min_svs>; 3444 }; 3445 3446 opp-50000000 { 3447 opp-hz = /bits/ 64 <50000000>; 3448 required-opps = <&rpmhpd_opp_low_svs>; 3449 }; 3450 3451 opp-100000000 { 3452 opp-hz = /bits/ 64 <100000000>; 3453 required-opps = <&rpmhpd_opp_svs>; 3454 }; 3455 3456 opp-202000000 { 3457 opp-hz = /bits/ 64 <202000000>; 3458 required-opps = <&rpmhpd_opp_svs_l1>; 3459 }; 3460 }; 3461 }; 3462 3463 dc_noc: interconnect@9160000 { 3464 compatible = "qcom,sm8150-dc-noc"; 3465 reg = <0 0x09160000 0 0x3200>; 3466 #interconnect-cells = <1>; 3467 qcom,bcm-voters = <&apps_bcm_voter>; 3468 }; 3469 3470 gem_noc: interconnect@9680000 { 3471 compatible = "qcom,sm8150-gem-noc"; 3472 reg = <0 0x09680000 0 0x3e200>; 3473 #interconnect-cells = <1>; 3474 qcom,bcm-voters = <&apps_bcm_voter>; 3475 }; 3476 3477 usb_1: usb@a6f8800 { 3478 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3479 reg = <0 0x0a6f8800 0 0x400>; 3480 status = "disabled"; 3481 #address-cells = <2>; 3482 #size-cells = <2>; 3483 ranges; 3484 dma-ranges; 3485 3486 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3487 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3488 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3489 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3490 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3491 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3492 clock-names = "cfg_noc", 3493 "core", 3494 "iface", 3495 "sleep", 3496 "mock_utmi", 3497 "xo"; 3498 3499 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3500 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3501 assigned-clock-rates = <19200000>, <200000000>; 3502 3503 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3504 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3505 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3506 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3507 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3508 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3509 3510 power-domains = <&gcc USB30_PRIM_GDSC>; 3511 3512 resets = <&gcc GCC_USB30_PRIM_BCR>; 3513 3514 usb_1_dwc3: usb@a600000 { 3515 compatible = "snps,dwc3"; 3516 reg = <0 0x0a600000 0 0xcd00>; 3517 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3518 iommus = <&apps_smmu 0x140 0>; 3519 snps,dis_u2_susphy_quirk; 3520 snps,dis_enblslpm_quirk; 3521 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3522 phy-names = "usb2-phy", "usb3-phy"; 3523 }; 3524 }; 3525 3526 usb_2: usb@a8f8800 { 3527 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3528 reg = <0 0x0a8f8800 0 0x400>; 3529 status = "disabled"; 3530 #address-cells = <2>; 3531 #size-cells = <2>; 3532 ranges; 3533 dma-ranges; 3534 3535 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3536 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3537 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3538 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3539 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3540 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3541 clock-names = "cfg_noc", 3542 "core", 3543 "iface", 3544 "sleep", 3545 "mock_utmi", 3546 "xo"; 3547 3548 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3549 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3550 assigned-clock-rates = <19200000>, <200000000>; 3551 3552 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3553 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 3554 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3555 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 3556 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3557 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3558 3559 power-domains = <&gcc USB30_SEC_GDSC>; 3560 3561 resets = <&gcc GCC_USB30_SEC_BCR>; 3562 3563 usb_2_dwc3: usb@a800000 { 3564 compatible = "snps,dwc3"; 3565 reg = <0 0x0a800000 0 0xcd00>; 3566 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3567 iommus = <&apps_smmu 0x160 0>; 3568 snps,dis_u2_susphy_quirk; 3569 snps,dis_enblslpm_quirk; 3570 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3571 phy-names = "usb2-phy", "usb3-phy"; 3572 }; 3573 }; 3574 3575 camnoc_virt: interconnect@ac00000 { 3576 compatible = "qcom,sm8150-camnoc-virt"; 3577 reg = <0 0x0ac00000 0 0x1000>; 3578 #interconnect-cells = <1>; 3579 qcom,bcm-voters = <&apps_bcm_voter>; 3580 }; 3581 3582 pdc: interrupt-controller@b220000 { 3583 compatible = "qcom,sm8150-pdc", "qcom,pdc"; 3584 reg = <0 0x0b220000 0 0x400>; 3585 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3586 <125 63 1>; 3587 #interrupt-cells = <2>; 3588 interrupt-parent = <&intc>; 3589 interrupt-controller; 3590 }; 3591 3592 aoss_qmp: power-controller@c300000 { 3593 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 3594 reg = <0x0 0x0c300000 0x0 0x400>; 3595 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3596 mboxes = <&apss_shared 0>; 3597 3598 #clock-cells = <0>; 3599 }; 3600 3601 sram@c3f0000 { 3602 compatible = "qcom,rpmh-stats"; 3603 reg = <0 0x0c3f0000 0 0x400>; 3604 }; 3605 3606 tsens0: thermal-sensor@c263000 { 3607 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3608 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3609 <0 0x0c222000 0 0x1ff>; /* SROT */ 3610 #qcom,sensors = <16>; 3611 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3613 interrupt-names = "uplow", "critical"; 3614 #thermal-sensor-cells = <1>; 3615 }; 3616 3617 tsens1: thermal-sensor@c265000 { 3618 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3619 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3620 <0 0x0c223000 0 0x1ff>; /* SROT */ 3621 #qcom,sensors = <8>; 3622 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3623 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3624 interrupt-names = "uplow", "critical"; 3625 #thermal-sensor-cells = <1>; 3626 }; 3627 3628 spmi_bus: spmi@c440000 { 3629 compatible = "qcom,spmi-pmic-arb"; 3630 reg = <0x0 0x0c440000 0x0 0x0001100>, 3631 <0x0 0x0c600000 0x0 0x2000000>, 3632 <0x0 0x0e600000 0x0 0x0100000>, 3633 <0x0 0x0e700000 0x0 0x00a0000>, 3634 <0x0 0x0c40a000 0x0 0x0026000>; 3635 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3636 interrupt-names = "periph_irq"; 3637 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3638 qcom,ee = <0>; 3639 qcom,channel = <0>; 3640 #address-cells = <2>; 3641 #size-cells = <0>; 3642 interrupt-controller; 3643 #interrupt-cells = <4>; 3644 cell-index = <0>; 3645 }; 3646 3647 apps_smmu: iommu@15000000 { 3648 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 3649 reg = <0 0x15000000 0 0x100000>; 3650 #iommu-cells = <2>; 3651 #global-interrupts = <1>; 3652 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3653 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3654 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3655 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3656 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3657 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3658 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3659 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3660 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3661 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3662 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3663 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3664 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3665 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3666 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3667 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3668 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3669 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3670 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3671 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3672 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3673 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3674 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3675 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3676 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3677 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3678 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3679 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3680 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3681 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3682 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3683 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3684 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3685 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3686 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3687 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3688 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3689 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3690 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3691 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3692 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3693 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3694 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3695 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3696 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3697 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3698 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3699 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3700 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3701 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3702 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3703 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3704 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3705 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3706 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3707 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3708 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3709 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3710 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3711 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3712 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3713 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3714 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3715 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3716 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3717 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3718 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3719 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3720 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3721 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3722 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3723 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3724 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3725 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3726 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3727 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3728 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3729 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3730 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3731 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3732 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 3733 }; 3734 3735 remoteproc_adsp: remoteproc@17300000 { 3736 compatible = "qcom,sm8150-adsp-pas"; 3737 reg = <0x0 0x17300000 0x0 0x4040>; 3738 3739 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3740 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3741 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3742 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3743 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3744 interrupt-names = "wdog", "fatal", "ready", 3745 "handover", "stop-ack"; 3746 3747 clocks = <&rpmhcc RPMH_CXO_CLK>; 3748 clock-names = "xo"; 3749 3750 power-domains = <&rpmhpd SM8150_CX>; 3751 3752 memory-region = <&adsp_mem>; 3753 3754 qcom,qmp = <&aoss_qmp>; 3755 3756 qcom,smem-states = <&adsp_smp2p_out 0>; 3757 qcom,smem-state-names = "stop"; 3758 3759 status = "disabled"; 3760 3761 glink-edge { 3762 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3763 label = "lpass"; 3764 qcom,remote-pid = <2>; 3765 mboxes = <&apss_shared 8>; 3766 3767 fastrpc { 3768 compatible = "qcom,fastrpc"; 3769 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3770 label = "adsp"; 3771 qcom,non-secure-domain; 3772 #address-cells = <1>; 3773 #size-cells = <0>; 3774 3775 compute-cb@3 { 3776 compatible = "qcom,fastrpc-compute-cb"; 3777 reg = <3>; 3778 iommus = <&apps_smmu 0x1b23 0x0>; 3779 }; 3780 3781 compute-cb@4 { 3782 compatible = "qcom,fastrpc-compute-cb"; 3783 reg = <4>; 3784 iommus = <&apps_smmu 0x1b24 0x0>; 3785 }; 3786 3787 compute-cb@5 { 3788 compatible = "qcom,fastrpc-compute-cb"; 3789 reg = <5>; 3790 iommus = <&apps_smmu 0x1b25 0x0>; 3791 }; 3792 }; 3793 }; 3794 }; 3795 3796 intc: interrupt-controller@17a00000 { 3797 compatible = "arm,gic-v3"; 3798 interrupt-controller; 3799 #interrupt-cells = <3>; 3800 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3801 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3802 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3803 }; 3804 3805 apss_shared: mailbox@17c00000 { 3806 compatible = "qcom,sm8150-apss-shared"; 3807 reg = <0x0 0x17c00000 0x0 0x1000>; 3808 #mbox-cells = <1>; 3809 }; 3810 3811 watchdog@17c10000 { 3812 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 3813 reg = <0 0x17c10000 0 0x1000>; 3814 clocks = <&sleep_clk>; 3815 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3816 }; 3817 3818 timer@17c20000 { 3819 #address-cells = <1>; 3820 #size-cells = <1>; 3821 ranges = <0 0 0 0x20000000>; 3822 compatible = "arm,armv7-timer-mem"; 3823 reg = <0x0 0x17c20000 0x0 0x1000>; 3824 clock-frequency = <19200000>; 3825 3826 frame@17c21000{ 3827 frame-number = <0>; 3828 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3829 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3830 reg = <0x17c21000 0x1000>, 3831 <0x17c22000 0x1000>; 3832 }; 3833 3834 frame@17c23000 { 3835 frame-number = <1>; 3836 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3837 reg = <0x17c23000 0x1000>; 3838 status = "disabled"; 3839 }; 3840 3841 frame@17c25000 { 3842 frame-number = <2>; 3843 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3844 reg = <0x17c25000 0x1000>; 3845 status = "disabled"; 3846 }; 3847 3848 frame@17c27000 { 3849 frame-number = <3>; 3850 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3851 reg = <0x17c26000 0x1000>; 3852 status = "disabled"; 3853 }; 3854 3855 frame@17c29000 { 3856 frame-number = <4>; 3857 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3858 reg = <0x17c29000 0x1000>; 3859 status = "disabled"; 3860 }; 3861 3862 frame@17c2b000 { 3863 frame-number = <5>; 3864 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3865 reg = <0x17c2b000 0x1000>; 3866 status = "disabled"; 3867 }; 3868 3869 frame@17c2d000 { 3870 frame-number = <6>; 3871 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3872 reg = <0x17c2d000 0x1000>; 3873 status = "disabled"; 3874 }; 3875 }; 3876 3877 apps_rsc: rsc@18200000 { 3878 label = "apps_rsc"; 3879 compatible = "qcom,rpmh-rsc"; 3880 reg = <0x0 0x18200000 0x0 0x10000>, 3881 <0x0 0x18210000 0x0 0x10000>, 3882 <0x0 0x18220000 0x0 0x10000>; 3883 reg-names = "drv-0", "drv-1", "drv-2"; 3884 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3885 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3886 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3887 qcom,tcs-offset = <0xd00>; 3888 qcom,drv-id = <2>; 3889 qcom,tcs-config = <ACTIVE_TCS 2>, 3890 <SLEEP_TCS 3>, 3891 <WAKE_TCS 3>, 3892 <CONTROL_TCS 1>; 3893 power-domains = <&CLUSTER_PD>; 3894 3895 rpmhcc: clock-controller { 3896 compatible = "qcom,sm8150-rpmh-clk"; 3897 #clock-cells = <1>; 3898 clock-names = "xo"; 3899 clocks = <&xo_board>; 3900 }; 3901 3902 rpmhpd: power-controller { 3903 compatible = "qcom,sm8150-rpmhpd"; 3904 #power-domain-cells = <1>; 3905 operating-points-v2 = <&rpmhpd_opp_table>; 3906 3907 rpmhpd_opp_table: opp-table { 3908 compatible = "operating-points-v2"; 3909 3910 rpmhpd_opp_ret: opp1 { 3911 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3912 }; 3913 3914 rpmhpd_opp_min_svs: opp2 { 3915 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3916 }; 3917 3918 rpmhpd_opp_low_svs: opp3 { 3919 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3920 }; 3921 3922 rpmhpd_opp_svs: opp4 { 3923 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3924 }; 3925 3926 rpmhpd_opp_svs_l1: opp5 { 3927 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3928 }; 3929 3930 rpmhpd_opp_svs_l2: opp6 { 3931 opp-level = <224>; 3932 }; 3933 3934 rpmhpd_opp_nom: opp7 { 3935 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3936 }; 3937 3938 rpmhpd_opp_nom_l1: opp8 { 3939 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3940 }; 3941 3942 rpmhpd_opp_nom_l2: opp9 { 3943 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3944 }; 3945 3946 rpmhpd_opp_turbo: opp10 { 3947 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3948 }; 3949 3950 rpmhpd_opp_turbo_l1: opp11 { 3951 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3952 }; 3953 }; 3954 }; 3955 3956 apps_bcm_voter: bcm-voter { 3957 compatible = "qcom,bcm-voter"; 3958 }; 3959 }; 3960 3961 osm_l3: interconnect@18321000 { 3962 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3"; 3963 reg = <0 0x18321000 0 0x1400>; 3964 3965 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3966 clock-names = "xo", "alternate"; 3967 3968 #interconnect-cells = <1>; 3969 }; 3970 3971 cpufreq_hw: cpufreq@18323000 { 3972 compatible = "qcom,cpufreq-hw"; 3973 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 3974 <0 0x18327800 0 0x1400>; 3975 reg-names = "freq-domain0", "freq-domain1", 3976 "freq-domain2"; 3977 3978 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3979 clock-names = "xo", "alternate"; 3980 3981 #freq-domain-cells = <1>; 3982 }; 3983 3984 lmh_cluster1: lmh@18350800 { 3985 compatible = "qcom,sm8150-lmh"; 3986 reg = <0 0x18350800 0 0x400>; 3987 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3988 cpus = <&CPU4>; 3989 qcom,lmh-temp-arm-millicelsius = <60000>; 3990 qcom,lmh-temp-low-millicelsius = <84500>; 3991 qcom,lmh-temp-high-millicelsius = <85000>; 3992 interrupt-controller; 3993 #interrupt-cells = <1>; 3994 }; 3995 3996 lmh_cluster0: lmh@18358800 { 3997 compatible = "qcom,sm8150-lmh"; 3998 reg = <0 0x18358800 0 0x400>; 3999 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4000 cpus = <&CPU0>; 4001 qcom,lmh-temp-arm-millicelsius = <60000>; 4002 qcom,lmh-temp-low-millicelsius = <84500>; 4003 qcom,lmh-temp-high-millicelsius = <85000>; 4004 interrupt-controller; 4005 #interrupt-cells = <1>; 4006 }; 4007 4008 wifi: wifi@18800000 { 4009 compatible = "qcom,wcn3990-wifi"; 4010 reg = <0 0x18800000 0 0x800000>; 4011 reg-names = "membase"; 4012 memory-region = <&wlan_mem>; 4013 clock-names = "cxo_ref_clk_pin", "qdss"; 4014 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 4015 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4016 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4017 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4018 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4019 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4020 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4021 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4022 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4023 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4024 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4025 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4026 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4027 iommus = <&apps_smmu 0x0640 0x1>; 4028 status = "disabled"; 4029 }; 4030 }; 4031 4032 timer { 4033 compatible = "arm,armv8-timer"; 4034 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4035 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4036 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4037 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4038 }; 4039 4040 thermal-zones { 4041 cpu0-thermal { 4042 polling-delay-passive = <250>; 4043 polling-delay = <1000>; 4044 4045 thermal-sensors = <&tsens0 1>; 4046 4047 trips { 4048 cpu0_alert0: trip-point0 { 4049 temperature = <90000>; 4050 hysteresis = <2000>; 4051 type = "passive"; 4052 }; 4053 4054 cpu0_alert1: trip-point1 { 4055 temperature = <95000>; 4056 hysteresis = <2000>; 4057 type = "passive"; 4058 }; 4059 4060 cpu0_crit: cpu_crit { 4061 temperature = <110000>; 4062 hysteresis = <1000>; 4063 type = "critical"; 4064 }; 4065 }; 4066 4067 cooling-maps { 4068 map0 { 4069 trip = <&cpu0_alert0>; 4070 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4071 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4072 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4073 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4074 }; 4075 map1 { 4076 trip = <&cpu0_alert1>; 4077 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4078 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4079 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4080 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4081 }; 4082 }; 4083 }; 4084 4085 cpu1-thermal { 4086 polling-delay-passive = <250>; 4087 polling-delay = <1000>; 4088 4089 thermal-sensors = <&tsens0 2>; 4090 4091 trips { 4092 cpu1_alert0: trip-point0 { 4093 temperature = <90000>; 4094 hysteresis = <2000>; 4095 type = "passive"; 4096 }; 4097 4098 cpu1_alert1: trip-point1 { 4099 temperature = <95000>; 4100 hysteresis = <2000>; 4101 type = "passive"; 4102 }; 4103 4104 cpu1_crit: cpu_crit { 4105 temperature = <110000>; 4106 hysteresis = <1000>; 4107 type = "critical"; 4108 }; 4109 }; 4110 4111 cooling-maps { 4112 map0 { 4113 trip = <&cpu1_alert0>; 4114 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4115 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4116 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4117 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4118 }; 4119 map1 { 4120 trip = <&cpu1_alert1>; 4121 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4122 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4123 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4124 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4125 }; 4126 }; 4127 }; 4128 4129 cpu2-thermal { 4130 polling-delay-passive = <250>; 4131 polling-delay = <1000>; 4132 4133 thermal-sensors = <&tsens0 3>; 4134 4135 trips { 4136 cpu2_alert0: trip-point0 { 4137 temperature = <90000>; 4138 hysteresis = <2000>; 4139 type = "passive"; 4140 }; 4141 4142 cpu2_alert1: trip-point1 { 4143 temperature = <95000>; 4144 hysteresis = <2000>; 4145 type = "passive"; 4146 }; 4147 4148 cpu2_crit: cpu_crit { 4149 temperature = <110000>; 4150 hysteresis = <1000>; 4151 type = "critical"; 4152 }; 4153 }; 4154 4155 cooling-maps { 4156 map0 { 4157 trip = <&cpu2_alert0>; 4158 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4159 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4160 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4161 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4162 }; 4163 map1 { 4164 trip = <&cpu2_alert1>; 4165 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4166 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4167 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4168 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4169 }; 4170 }; 4171 }; 4172 4173 cpu3-thermal { 4174 polling-delay-passive = <250>; 4175 polling-delay = <1000>; 4176 4177 thermal-sensors = <&tsens0 4>; 4178 4179 trips { 4180 cpu3_alert0: trip-point0 { 4181 temperature = <90000>; 4182 hysteresis = <2000>; 4183 type = "passive"; 4184 }; 4185 4186 cpu3_alert1: trip-point1 { 4187 temperature = <95000>; 4188 hysteresis = <2000>; 4189 type = "passive"; 4190 }; 4191 4192 cpu3_crit: cpu_crit { 4193 temperature = <110000>; 4194 hysteresis = <1000>; 4195 type = "critical"; 4196 }; 4197 }; 4198 4199 cooling-maps { 4200 map0 { 4201 trip = <&cpu3_alert0>; 4202 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4203 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4204 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4205 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4206 }; 4207 map1 { 4208 trip = <&cpu3_alert1>; 4209 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4210 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4211 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4212 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4213 }; 4214 }; 4215 }; 4216 4217 cpu4-top-thermal { 4218 polling-delay-passive = <250>; 4219 polling-delay = <1000>; 4220 4221 thermal-sensors = <&tsens0 7>; 4222 4223 trips { 4224 cpu4_top_alert0: trip-point0 { 4225 temperature = <90000>; 4226 hysteresis = <2000>; 4227 type = "passive"; 4228 }; 4229 4230 cpu4_top_alert1: trip-point1 { 4231 temperature = <95000>; 4232 hysteresis = <2000>; 4233 type = "passive"; 4234 }; 4235 4236 cpu4_top_crit: cpu_crit { 4237 temperature = <110000>; 4238 hysteresis = <1000>; 4239 type = "critical"; 4240 }; 4241 }; 4242 4243 cooling-maps { 4244 map0 { 4245 trip = <&cpu4_top_alert0>; 4246 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4247 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4248 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4249 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4250 }; 4251 map1 { 4252 trip = <&cpu4_top_alert1>; 4253 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4254 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4255 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4256 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4257 }; 4258 }; 4259 }; 4260 4261 cpu5-top-thermal { 4262 polling-delay-passive = <250>; 4263 polling-delay = <1000>; 4264 4265 thermal-sensors = <&tsens0 8>; 4266 4267 trips { 4268 cpu5_top_alert0: trip-point0 { 4269 temperature = <90000>; 4270 hysteresis = <2000>; 4271 type = "passive"; 4272 }; 4273 4274 cpu5_top_alert1: trip-point1 { 4275 temperature = <95000>; 4276 hysteresis = <2000>; 4277 type = "passive"; 4278 }; 4279 4280 cpu5_top_crit: cpu_crit { 4281 temperature = <110000>; 4282 hysteresis = <1000>; 4283 type = "critical"; 4284 }; 4285 }; 4286 4287 cooling-maps { 4288 map0 { 4289 trip = <&cpu5_top_alert0>; 4290 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4291 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4292 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4293 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4294 }; 4295 map1 { 4296 trip = <&cpu5_top_alert1>; 4297 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4298 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4299 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4300 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4301 }; 4302 }; 4303 }; 4304 4305 cpu6-top-thermal { 4306 polling-delay-passive = <250>; 4307 polling-delay = <1000>; 4308 4309 thermal-sensors = <&tsens0 9>; 4310 4311 trips { 4312 cpu6_top_alert0: trip-point0 { 4313 temperature = <90000>; 4314 hysteresis = <2000>; 4315 type = "passive"; 4316 }; 4317 4318 cpu6_top_alert1: trip-point1 { 4319 temperature = <95000>; 4320 hysteresis = <2000>; 4321 type = "passive"; 4322 }; 4323 4324 cpu6_top_crit: cpu_crit { 4325 temperature = <110000>; 4326 hysteresis = <1000>; 4327 type = "critical"; 4328 }; 4329 }; 4330 4331 cooling-maps { 4332 map0 { 4333 trip = <&cpu6_top_alert0>; 4334 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4335 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4336 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4337 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4338 }; 4339 map1 { 4340 trip = <&cpu6_top_alert1>; 4341 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4342 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4343 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4344 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4345 }; 4346 }; 4347 }; 4348 4349 cpu7-top-thermal { 4350 polling-delay-passive = <250>; 4351 polling-delay = <1000>; 4352 4353 thermal-sensors = <&tsens0 10>; 4354 4355 trips { 4356 cpu7_top_alert0: trip-point0 { 4357 temperature = <90000>; 4358 hysteresis = <2000>; 4359 type = "passive"; 4360 }; 4361 4362 cpu7_top_alert1: trip-point1 { 4363 temperature = <95000>; 4364 hysteresis = <2000>; 4365 type = "passive"; 4366 }; 4367 4368 cpu7_top_crit: cpu_crit { 4369 temperature = <110000>; 4370 hysteresis = <1000>; 4371 type = "critical"; 4372 }; 4373 }; 4374 4375 cooling-maps { 4376 map0 { 4377 trip = <&cpu7_top_alert0>; 4378 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4379 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4380 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4381 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4382 }; 4383 map1 { 4384 trip = <&cpu7_top_alert1>; 4385 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4386 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4387 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4388 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4389 }; 4390 }; 4391 }; 4392 4393 cpu4-bottom-thermal { 4394 polling-delay-passive = <250>; 4395 polling-delay = <1000>; 4396 4397 thermal-sensors = <&tsens0 11>; 4398 4399 trips { 4400 cpu4_bottom_alert0: trip-point0 { 4401 temperature = <90000>; 4402 hysteresis = <2000>; 4403 type = "passive"; 4404 }; 4405 4406 cpu4_bottom_alert1: trip-point1 { 4407 temperature = <95000>; 4408 hysteresis = <2000>; 4409 type = "passive"; 4410 }; 4411 4412 cpu4_bottom_crit: cpu_crit { 4413 temperature = <110000>; 4414 hysteresis = <1000>; 4415 type = "critical"; 4416 }; 4417 }; 4418 4419 cooling-maps { 4420 map0 { 4421 trip = <&cpu4_bottom_alert0>; 4422 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4423 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4424 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4425 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4426 }; 4427 map1 { 4428 trip = <&cpu4_bottom_alert1>; 4429 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4430 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4431 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4432 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4433 }; 4434 }; 4435 }; 4436 4437 cpu5-bottom-thermal { 4438 polling-delay-passive = <250>; 4439 polling-delay = <1000>; 4440 4441 thermal-sensors = <&tsens0 12>; 4442 4443 trips { 4444 cpu5_bottom_alert0: trip-point0 { 4445 temperature = <90000>; 4446 hysteresis = <2000>; 4447 type = "passive"; 4448 }; 4449 4450 cpu5_bottom_alert1: trip-point1 { 4451 temperature = <95000>; 4452 hysteresis = <2000>; 4453 type = "passive"; 4454 }; 4455 4456 cpu5_bottom_crit: cpu_crit { 4457 temperature = <110000>; 4458 hysteresis = <1000>; 4459 type = "critical"; 4460 }; 4461 }; 4462 4463 cooling-maps { 4464 map0 { 4465 trip = <&cpu5_bottom_alert0>; 4466 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4467 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4468 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4469 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4470 }; 4471 map1 { 4472 trip = <&cpu5_bottom_alert1>; 4473 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4474 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4475 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4476 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4477 }; 4478 }; 4479 }; 4480 4481 cpu6-bottom-thermal { 4482 polling-delay-passive = <250>; 4483 polling-delay = <1000>; 4484 4485 thermal-sensors = <&tsens0 13>; 4486 4487 trips { 4488 cpu6_bottom_alert0: trip-point0 { 4489 temperature = <90000>; 4490 hysteresis = <2000>; 4491 type = "passive"; 4492 }; 4493 4494 cpu6_bottom_alert1: trip-point1 { 4495 temperature = <95000>; 4496 hysteresis = <2000>; 4497 type = "passive"; 4498 }; 4499 4500 cpu6_bottom_crit: cpu_crit { 4501 temperature = <110000>; 4502 hysteresis = <1000>; 4503 type = "critical"; 4504 }; 4505 }; 4506 4507 cooling-maps { 4508 map0 { 4509 trip = <&cpu6_bottom_alert0>; 4510 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4511 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4512 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4513 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4514 }; 4515 map1 { 4516 trip = <&cpu6_bottom_alert1>; 4517 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4518 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4519 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4520 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4521 }; 4522 }; 4523 }; 4524 4525 cpu7-bottom-thermal { 4526 polling-delay-passive = <250>; 4527 polling-delay = <1000>; 4528 4529 thermal-sensors = <&tsens0 14>; 4530 4531 trips { 4532 cpu7_bottom_alert0: trip-point0 { 4533 temperature = <90000>; 4534 hysteresis = <2000>; 4535 type = "passive"; 4536 }; 4537 4538 cpu7_bottom_alert1: trip-point1 { 4539 temperature = <95000>; 4540 hysteresis = <2000>; 4541 type = "passive"; 4542 }; 4543 4544 cpu7_bottom_crit: cpu_crit { 4545 temperature = <110000>; 4546 hysteresis = <1000>; 4547 type = "critical"; 4548 }; 4549 }; 4550 4551 cooling-maps { 4552 map0 { 4553 trip = <&cpu7_bottom_alert0>; 4554 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4555 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4556 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4557 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4558 }; 4559 map1 { 4560 trip = <&cpu7_bottom_alert1>; 4561 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4562 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4563 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4564 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4565 }; 4566 }; 4567 }; 4568 4569 aoss0-thermal { 4570 polling-delay-passive = <250>; 4571 polling-delay = <1000>; 4572 4573 thermal-sensors = <&tsens0 0>; 4574 4575 trips { 4576 aoss0_alert0: trip-point0 { 4577 temperature = <90000>; 4578 hysteresis = <2000>; 4579 type = "hot"; 4580 }; 4581 }; 4582 }; 4583 4584 cluster0-thermal { 4585 polling-delay-passive = <250>; 4586 polling-delay = <1000>; 4587 4588 thermal-sensors = <&tsens0 5>; 4589 4590 trips { 4591 cluster0_alert0: trip-point0 { 4592 temperature = <90000>; 4593 hysteresis = <2000>; 4594 type = "hot"; 4595 }; 4596 cluster0_crit: cluster0_crit { 4597 temperature = <110000>; 4598 hysteresis = <2000>; 4599 type = "critical"; 4600 }; 4601 }; 4602 }; 4603 4604 cluster1-thermal { 4605 polling-delay-passive = <250>; 4606 polling-delay = <1000>; 4607 4608 thermal-sensors = <&tsens0 6>; 4609 4610 trips { 4611 cluster1_alert0: trip-point0 { 4612 temperature = <90000>; 4613 hysteresis = <2000>; 4614 type = "hot"; 4615 }; 4616 cluster1_crit: cluster1_crit { 4617 temperature = <110000>; 4618 hysteresis = <2000>; 4619 type = "critical"; 4620 }; 4621 }; 4622 }; 4623 4624 gpu-top-thermal { 4625 polling-delay-passive = <250>; 4626 polling-delay = <1000>; 4627 4628 thermal-sensors = <&tsens0 15>; 4629 4630 trips { 4631 gpu1_alert0: trip-point0 { 4632 temperature = <90000>; 4633 hysteresis = <2000>; 4634 type = "hot"; 4635 }; 4636 }; 4637 }; 4638 4639 aoss1-thermal { 4640 polling-delay-passive = <250>; 4641 polling-delay = <1000>; 4642 4643 thermal-sensors = <&tsens1 0>; 4644 4645 trips { 4646 aoss1_alert0: trip-point0 { 4647 temperature = <90000>; 4648 hysteresis = <2000>; 4649 type = "hot"; 4650 }; 4651 }; 4652 }; 4653 4654 wlan-thermal { 4655 polling-delay-passive = <250>; 4656 polling-delay = <1000>; 4657 4658 thermal-sensors = <&tsens1 1>; 4659 4660 trips { 4661 wlan_alert0: trip-point0 { 4662 temperature = <90000>; 4663 hysteresis = <2000>; 4664 type = "hot"; 4665 }; 4666 }; 4667 }; 4668 4669 video-thermal { 4670 polling-delay-passive = <250>; 4671 polling-delay = <1000>; 4672 4673 thermal-sensors = <&tsens1 2>; 4674 4675 trips { 4676 video_alert0: trip-point0 { 4677 temperature = <90000>; 4678 hysteresis = <2000>; 4679 type = "hot"; 4680 }; 4681 }; 4682 }; 4683 4684 mem-thermal { 4685 polling-delay-passive = <250>; 4686 polling-delay = <1000>; 4687 4688 thermal-sensors = <&tsens1 3>; 4689 4690 trips { 4691 mem_alert0: trip-point0 { 4692 temperature = <90000>; 4693 hysteresis = <2000>; 4694 type = "hot"; 4695 }; 4696 }; 4697 }; 4698 4699 q6-hvx-thermal { 4700 polling-delay-passive = <250>; 4701 polling-delay = <1000>; 4702 4703 thermal-sensors = <&tsens1 4>; 4704 4705 trips { 4706 q6_hvx_alert0: trip-point0 { 4707 temperature = <90000>; 4708 hysteresis = <2000>; 4709 type = "hot"; 4710 }; 4711 }; 4712 }; 4713 4714 camera-thermal { 4715 polling-delay-passive = <250>; 4716 polling-delay = <1000>; 4717 4718 thermal-sensors = <&tsens1 5>; 4719 4720 trips { 4721 camera_alert0: trip-point0 { 4722 temperature = <90000>; 4723 hysteresis = <2000>; 4724 type = "hot"; 4725 }; 4726 }; 4727 }; 4728 4729 compute-thermal { 4730 polling-delay-passive = <250>; 4731 polling-delay = <1000>; 4732 4733 thermal-sensors = <&tsens1 6>; 4734 4735 trips { 4736 compute_alert0: trip-point0 { 4737 temperature = <90000>; 4738 hysteresis = <2000>; 4739 type = "hot"; 4740 }; 4741 }; 4742 }; 4743 4744 modem-thermal { 4745 polling-delay-passive = <250>; 4746 polling-delay = <1000>; 4747 4748 thermal-sensors = <&tsens1 7>; 4749 4750 trips { 4751 modem_alert0: trip-point0 { 4752 temperature = <90000>; 4753 hysteresis = <2000>; 4754 type = "hot"; 4755 }; 4756 }; 4757 }; 4758 4759 npu-thermal { 4760 polling-delay-passive = <250>; 4761 polling-delay = <1000>; 4762 4763 thermal-sensors = <&tsens1 8>; 4764 4765 trips { 4766 npu_alert0: trip-point0 { 4767 temperature = <90000>; 4768 hysteresis = <2000>; 4769 type = "hot"; 4770 }; 4771 }; 4772 }; 4773 4774 modem-vec-thermal { 4775 polling-delay-passive = <250>; 4776 polling-delay = <1000>; 4777 4778 thermal-sensors = <&tsens1 9>; 4779 4780 trips { 4781 modem_vec_alert0: trip-point0 { 4782 temperature = <90000>; 4783 hysteresis = <2000>; 4784 type = "hot"; 4785 }; 4786 }; 4787 }; 4788 4789 modem-scl-thermal { 4790 polling-delay-passive = <250>; 4791 polling-delay = <1000>; 4792 4793 thermal-sensors = <&tsens1 10>; 4794 4795 trips { 4796 modem_scl_alert0: trip-point0 { 4797 temperature = <90000>; 4798 hysteresis = <2000>; 4799 type = "hot"; 4800 }; 4801 }; 4802 }; 4803 4804 gpu-bottom-thermal { 4805 polling-delay-passive = <250>; 4806 polling-delay = <1000>; 4807 4808 thermal-sensors = <&tsens1 11>; 4809 4810 trips { 4811 gpu2_alert0: trip-point0 { 4812 temperature = <90000>; 4813 hysteresis = <2000>; 4814 type = "hot"; 4815 }; 4816 }; 4817 }; 4818 }; 4819}; 4820