1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/dma/qcom-gpi.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,gcc-sm8150.h> 13#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sm8150.h> 16#include <dt-bindings/thermal/thermal.h> 17 18/ { 19 interrupt-parent = <&intc>; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 chosen { }; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <38400000>; 31 clock-output-names = "xo_board"; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32764>; 38 clock-output-names = "sleep_clk"; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "qcom,kryo485"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 capacity-dmips-mhz = <488>; 52 dynamic-power-coefficient = <232>; 53 next-level-cache = <&L2_0>; 54 qcom,freq-domain = <&cpufreq_hw 0>; 55 operating-points-v2 = <&cpu0_opp_table>; 56 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 57 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 58 power-domains = <&CPU_PD0>; 59 power-domain-names = "psci"; 60 #cooling-cells = <2>; 61 L2_0: l2-cache { 62 compatible = "cache"; 63 next-level-cache = <&L3_0>; 64 L3_0: l3-cache { 65 compatible = "cache"; 66 }; 67 }; 68 }; 69 70 CPU1: cpu@100 { 71 device_type = "cpu"; 72 compatible = "qcom,kryo485"; 73 reg = <0x0 0x100>; 74 enable-method = "psci"; 75 capacity-dmips-mhz = <488>; 76 dynamic-power-coefficient = <232>; 77 next-level-cache = <&L2_100>; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 operating-points-v2 = <&cpu0_opp_table>; 80 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 81 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 82 power-domains = <&CPU_PD1>; 83 power-domain-names = "psci"; 84 #cooling-cells = <2>; 85 L2_100: l2-cache { 86 compatible = "cache"; 87 next-level-cache = <&L3_0>; 88 }; 89 90 }; 91 92 CPU2: cpu@200 { 93 device_type = "cpu"; 94 compatible = "qcom,kryo485"; 95 reg = <0x0 0x200>; 96 enable-method = "psci"; 97 capacity-dmips-mhz = <488>; 98 dynamic-power-coefficient = <232>; 99 next-level-cache = <&L2_200>; 100 qcom,freq-domain = <&cpufreq_hw 0>; 101 operating-points-v2 = <&cpu0_opp_table>; 102 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 103 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 104 power-domains = <&CPU_PD2>; 105 power-domain-names = "psci"; 106 #cooling-cells = <2>; 107 L2_200: l2-cache { 108 compatible = "cache"; 109 next-level-cache = <&L3_0>; 110 }; 111 }; 112 113 CPU3: cpu@300 { 114 device_type = "cpu"; 115 compatible = "qcom,kryo485"; 116 reg = <0x0 0x300>; 117 enable-method = "psci"; 118 capacity-dmips-mhz = <488>; 119 dynamic-power-coefficient = <232>; 120 next-level-cache = <&L2_300>; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 operating-points-v2 = <&cpu0_opp_table>; 123 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 124 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 125 power-domains = <&CPU_PD3>; 126 power-domain-names = "psci"; 127 #cooling-cells = <2>; 128 L2_300: l2-cache { 129 compatible = "cache"; 130 next-level-cache = <&L3_0>; 131 }; 132 }; 133 134 CPU4: cpu@400 { 135 device_type = "cpu"; 136 compatible = "qcom,kryo485"; 137 reg = <0x0 0x400>; 138 enable-method = "psci"; 139 capacity-dmips-mhz = <1024>; 140 dynamic-power-coefficient = <369>; 141 next-level-cache = <&L2_400>; 142 qcom,freq-domain = <&cpufreq_hw 1>; 143 operating-points-v2 = <&cpu4_opp_table>; 144 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 145 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 146 power-domains = <&CPU_PD4>; 147 power-domain-names = "psci"; 148 #cooling-cells = <2>; 149 L2_400: l2-cache { 150 compatible = "cache"; 151 next-level-cache = <&L3_0>; 152 }; 153 }; 154 155 CPU5: cpu@500 { 156 device_type = "cpu"; 157 compatible = "qcom,kryo485"; 158 reg = <0x0 0x500>; 159 enable-method = "psci"; 160 capacity-dmips-mhz = <1024>; 161 dynamic-power-coefficient = <369>; 162 next-level-cache = <&L2_500>; 163 qcom,freq-domain = <&cpufreq_hw 1>; 164 operating-points-v2 = <&cpu4_opp_table>; 165 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 166 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 167 power-domains = <&CPU_PD5>; 168 power-domain-names = "psci"; 169 #cooling-cells = <2>; 170 L2_500: l2-cache { 171 compatible = "cache"; 172 next-level-cache = <&L3_0>; 173 }; 174 }; 175 176 CPU6: cpu@600 { 177 device_type = "cpu"; 178 compatible = "qcom,kryo485"; 179 reg = <0x0 0x600>; 180 enable-method = "psci"; 181 capacity-dmips-mhz = <1024>; 182 dynamic-power-coefficient = <369>; 183 next-level-cache = <&L2_600>; 184 qcom,freq-domain = <&cpufreq_hw 1>; 185 operating-points-v2 = <&cpu4_opp_table>; 186 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 187 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 188 power-domains = <&CPU_PD6>; 189 power-domain-names = "psci"; 190 #cooling-cells = <2>; 191 L2_600: l2-cache { 192 compatible = "cache"; 193 next-level-cache = <&L3_0>; 194 }; 195 }; 196 197 CPU7: cpu@700 { 198 device_type = "cpu"; 199 compatible = "qcom,kryo485"; 200 reg = <0x0 0x700>; 201 enable-method = "psci"; 202 capacity-dmips-mhz = <1024>; 203 dynamic-power-coefficient = <421>; 204 next-level-cache = <&L2_700>; 205 qcom,freq-domain = <&cpufreq_hw 2>; 206 operating-points-v2 = <&cpu7_opp_table>; 207 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 208 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 209 power-domains = <&CPU_PD7>; 210 power-domain-names = "psci"; 211 #cooling-cells = <2>; 212 L2_700: l2-cache { 213 compatible = "cache"; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 cpu-map { 219 cluster0 { 220 core0 { 221 cpu = <&CPU0>; 222 }; 223 224 core1 { 225 cpu = <&CPU1>; 226 }; 227 228 core2 { 229 cpu = <&CPU2>; 230 }; 231 232 core3 { 233 cpu = <&CPU3>; 234 }; 235 236 core4 { 237 cpu = <&CPU4>; 238 }; 239 240 core5 { 241 cpu = <&CPU5>; 242 }; 243 244 core6 { 245 cpu = <&CPU6>; 246 }; 247 248 core7 { 249 cpu = <&CPU7>; 250 }; 251 }; 252 }; 253 254 idle-states { 255 entry-method = "psci"; 256 257 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 258 compatible = "arm,idle-state"; 259 idle-state-name = "little-rail-power-collapse"; 260 arm,psci-suspend-param = <0x40000004>; 261 entry-latency-us = <355>; 262 exit-latency-us = <909>; 263 min-residency-us = <3934>; 264 local-timer-stop; 265 }; 266 267 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "big-rail-power-collapse"; 270 arm,psci-suspend-param = <0x40000004>; 271 entry-latency-us = <241>; 272 exit-latency-us = <1461>; 273 min-residency-us = <4488>; 274 local-timer-stop; 275 }; 276 }; 277 278 domain-idle-states { 279 CLUSTER_SLEEP_0: cluster-sleep-0 { 280 compatible = "domain-idle-state"; 281 idle-state-name = "cluster-power-collapse"; 282 arm,psci-suspend-param = <0x4100c244>; 283 entry-latency-us = <3263>; 284 exit-latency-us = <6562>; 285 min-residency-us = <9987>; 286 local-timer-stop; 287 }; 288 }; 289 }; 290 291 cpu0_opp_table: cpu0_opp_table { 292 compatible = "operating-points-v2"; 293 opp-shared; 294 295 cpu0_opp1: opp-300000000 { 296 opp-hz = /bits/ 64 <300000000>; 297 opp-peak-kBps = <800000 9600000>; 298 }; 299 300 cpu0_opp2: opp-403200000 { 301 opp-hz = /bits/ 64 <403200000>; 302 opp-peak-kBps = <800000 9600000>; 303 }; 304 305 cpu0_opp3: opp-499200000 { 306 opp-hz = /bits/ 64 <499200000>; 307 opp-peak-kBps = <800000 12902400>; 308 }; 309 310 cpu0_opp4: opp-576000000 { 311 opp-hz = /bits/ 64 <576000000>; 312 opp-peak-kBps = <800000 12902400>; 313 }; 314 315 cpu0_opp5: opp-672000000 { 316 opp-hz = /bits/ 64 <672000000>; 317 opp-peak-kBps = <800000 15974400>; 318 }; 319 320 cpu0_opp6: opp-768000000 { 321 opp-hz = /bits/ 64 <768000000>; 322 opp-peak-kBps = <1804000 19660800>; 323 }; 324 325 cpu0_opp7: opp-844800000 { 326 opp-hz = /bits/ 64 <844800000>; 327 opp-peak-kBps = <1804000 19660800>; 328 }; 329 330 cpu0_opp8: opp-940800000 { 331 opp-hz = /bits/ 64 <940800000>; 332 opp-peak-kBps = <1804000 22732800>; 333 }; 334 335 cpu0_opp9: opp-1036800000 { 336 opp-hz = /bits/ 64 <1036800000>; 337 opp-peak-kBps = <1804000 22732800>; 338 }; 339 340 cpu0_opp10: opp-1113600000 { 341 opp-hz = /bits/ 64 <1113600000>; 342 opp-peak-kBps = <2188000 25804800>; 343 }; 344 345 cpu0_opp11: opp-1209600000 { 346 opp-hz = /bits/ 64 <1209600000>; 347 opp-peak-kBps = <2188000 31948800>; 348 }; 349 350 cpu0_opp12: opp-1305600000 { 351 opp-hz = /bits/ 64 <1305600000>; 352 opp-peak-kBps = <3072000 31948800>; 353 }; 354 355 cpu0_opp13: opp-1382400000 { 356 opp-hz = /bits/ 64 <1382400000>; 357 opp-peak-kBps = <3072000 31948800>; 358 }; 359 360 cpu0_opp14: opp-1478400000 { 361 opp-hz = /bits/ 64 <1478400000>; 362 opp-peak-kBps = <3072000 31948800>; 363 }; 364 365 cpu0_opp15: opp-1555200000 { 366 opp-hz = /bits/ 64 <1555200000>; 367 opp-peak-kBps = <3072000 40550400>; 368 }; 369 370 cpu0_opp16: opp-1632000000 { 371 opp-hz = /bits/ 64 <1632000000>; 372 opp-peak-kBps = <3072000 40550400>; 373 }; 374 375 cpu0_opp17: opp-1708800000 { 376 opp-hz = /bits/ 64 <1708800000>; 377 opp-peak-kBps = <3072000 43008000>; 378 }; 379 380 cpu0_opp18: opp-1785600000 { 381 opp-hz = /bits/ 64 <1785600000>; 382 opp-peak-kBps = <3072000 43008000>; 383 }; 384 }; 385 386 cpu4_opp_table: cpu4_opp_table { 387 compatible = "operating-points-v2"; 388 opp-shared; 389 390 cpu4_opp1: opp-710400000 { 391 opp-hz = /bits/ 64 <710400000>; 392 opp-peak-kBps = <1804000 15974400>; 393 }; 394 395 cpu4_opp2: opp-825600000 { 396 opp-hz = /bits/ 64 <825600000>; 397 opp-peak-kBps = <2188000 19660800>; 398 }; 399 400 cpu4_opp3: opp-940800000 { 401 opp-hz = /bits/ 64 <940800000>; 402 opp-peak-kBps = <2188000 22732800>; 403 }; 404 405 cpu4_opp4: opp-1056000000 { 406 opp-hz = /bits/ 64 <1056000000>; 407 opp-peak-kBps = <3072000 25804800>; 408 }; 409 410 cpu4_opp5: opp-1171200000 { 411 opp-hz = /bits/ 64 <1171200000>; 412 opp-peak-kBps = <3072000 31948800>; 413 }; 414 415 cpu4_opp6: opp-1286400000 { 416 opp-hz = /bits/ 64 <1286400000>; 417 opp-peak-kBps = <4068000 31948800>; 418 }; 419 420 cpu4_opp7: opp-1401600000 { 421 opp-hz = /bits/ 64 <1401600000>; 422 opp-peak-kBps = <4068000 31948800>; 423 }; 424 425 cpu4_opp8: opp-1497600000 { 426 opp-hz = /bits/ 64 <1497600000>; 427 opp-peak-kBps = <4068000 40550400>; 428 }; 429 430 cpu4_opp9: opp-1612800000 { 431 opp-hz = /bits/ 64 <1612800000>; 432 opp-peak-kBps = <4068000 40550400>; 433 }; 434 435 cpu4_opp10: opp-1708800000 { 436 opp-hz = /bits/ 64 <1708800000>; 437 opp-peak-kBps = <4068000 43008000>; 438 }; 439 440 cpu4_opp11: opp-1804800000 { 441 opp-hz = /bits/ 64 <1804800000>; 442 opp-peak-kBps = <6220000 43008000>; 443 }; 444 445 cpu4_opp12: opp-1920000000 { 446 opp-hz = /bits/ 64 <1920000000>; 447 opp-peak-kBps = <6220000 49152000>; 448 }; 449 450 cpu4_opp13: opp-2016000000 { 451 opp-hz = /bits/ 64 <2016000000>; 452 opp-peak-kBps = <7216000 49152000>; 453 }; 454 455 cpu4_opp14: opp-2131200000 { 456 opp-hz = /bits/ 64 <2131200000>; 457 opp-peak-kBps = <8368000 49152000>; 458 }; 459 460 cpu4_opp15: opp-2227200000 { 461 opp-hz = /bits/ 64 <2227200000>; 462 opp-peak-kBps = <8368000 51609600>; 463 }; 464 465 cpu4_opp16: opp-2323200000 { 466 opp-hz = /bits/ 64 <2323200000>; 467 opp-peak-kBps = <8368000 51609600>; 468 }; 469 470 cpu4_opp17: opp-2419200000 { 471 opp-hz = /bits/ 64 <2419200000>; 472 opp-peak-kBps = <8368000 51609600>; 473 }; 474 }; 475 476 cpu7_opp_table: cpu7_opp_table { 477 compatible = "operating-points-v2"; 478 opp-shared; 479 480 cpu7_opp1: opp-825600000 { 481 opp-hz = /bits/ 64 <825600000>; 482 opp-peak-kBps = <2188000 19660800>; 483 }; 484 485 cpu7_opp2: opp-940800000 { 486 opp-hz = /bits/ 64 <940800000>; 487 opp-peak-kBps = <2188000 22732800>; 488 }; 489 490 cpu7_opp3: opp-1056000000 { 491 opp-hz = /bits/ 64 <1056000000>; 492 opp-peak-kBps = <3072000 25804800>; 493 }; 494 495 cpu7_opp4: opp-1171200000 { 496 opp-hz = /bits/ 64 <1171200000>; 497 opp-peak-kBps = <3072000 31948800>; 498 }; 499 500 cpu7_opp5: opp-1286400000 { 501 opp-hz = /bits/ 64 <1286400000>; 502 opp-peak-kBps = <4068000 31948800>; 503 }; 504 505 cpu7_opp6: opp-1401600000 { 506 opp-hz = /bits/ 64 <1401600000>; 507 opp-peak-kBps = <4068000 31948800>; 508 }; 509 510 cpu7_opp7: opp-1497600000 { 511 opp-hz = /bits/ 64 <1497600000>; 512 opp-peak-kBps = <4068000 40550400>; 513 }; 514 515 cpu7_opp8: opp-1612800000 { 516 opp-hz = /bits/ 64 <1612800000>; 517 opp-peak-kBps = <4068000 40550400>; 518 }; 519 520 cpu7_opp9: opp-1708800000 { 521 opp-hz = /bits/ 64 <1708800000>; 522 opp-peak-kBps = <4068000 43008000>; 523 }; 524 525 cpu7_opp10: opp-1804800000 { 526 opp-hz = /bits/ 64 <1804800000>; 527 opp-peak-kBps = <6220000 43008000>; 528 }; 529 530 cpu7_opp11: opp-1920000000 { 531 opp-hz = /bits/ 64 <1920000000>; 532 opp-peak-kBps = <6220000 49152000>; 533 }; 534 535 cpu7_opp12: opp-2016000000 { 536 opp-hz = /bits/ 64 <2016000000>; 537 opp-peak-kBps = <7216000 49152000>; 538 }; 539 540 cpu7_opp13: opp-2131200000 { 541 opp-hz = /bits/ 64 <2131200000>; 542 opp-peak-kBps = <8368000 49152000>; 543 }; 544 545 cpu7_opp14: opp-2227200000 { 546 opp-hz = /bits/ 64 <2227200000>; 547 opp-peak-kBps = <8368000 51609600>; 548 }; 549 550 cpu7_opp15: opp-2323200000 { 551 opp-hz = /bits/ 64 <2323200000>; 552 opp-peak-kBps = <8368000 51609600>; 553 }; 554 555 cpu7_opp16: opp-2419200000 { 556 opp-hz = /bits/ 64 <2419200000>; 557 opp-peak-kBps = <8368000 51609600>; 558 }; 559 560 cpu7_opp17: opp-2534400000 { 561 opp-hz = /bits/ 64 <2534400000>; 562 opp-peak-kBps = <8368000 51609600>; 563 }; 564 565 cpu7_opp18: opp-2649600000 { 566 opp-hz = /bits/ 64 <2649600000>; 567 opp-peak-kBps = <8368000 51609600>; 568 }; 569 570 cpu7_opp19: opp-2745600000 { 571 opp-hz = /bits/ 64 <2745600000>; 572 opp-peak-kBps = <8368000 51609600>; 573 }; 574 575 cpu7_opp20: opp-2841600000 { 576 opp-hz = /bits/ 64 <2841600000>; 577 opp-peak-kBps = <8368000 51609600>; 578 }; 579 }; 580 581 firmware { 582 scm: scm { 583 compatible = "qcom,scm-sm8150", "qcom,scm"; 584 #reset-cells = <1>; 585 }; 586 }; 587 588 tcsr_mutex: hwlock { 589 compatible = "qcom,tcsr-mutex"; 590 syscon = <&tcsr_mutex_regs 0 0x1000>; 591 #hwlock-cells = <1>; 592 }; 593 594 memory@80000000 { 595 device_type = "memory"; 596 /* We expect the bootloader to fill in the size */ 597 reg = <0x0 0x80000000 0x0 0x0>; 598 }; 599 600 pmu { 601 compatible = "arm,armv8-pmuv3"; 602 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 603 }; 604 605 psci { 606 compatible = "arm,psci-1.0"; 607 method = "smc"; 608 609 CPU_PD0: cpu0 { 610 #power-domain-cells = <0>; 611 power-domains = <&CLUSTER_PD>; 612 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 613 }; 614 615 CPU_PD1: cpu1 { 616 #power-domain-cells = <0>; 617 power-domains = <&CLUSTER_PD>; 618 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 619 }; 620 621 CPU_PD2: cpu2 { 622 #power-domain-cells = <0>; 623 power-domains = <&CLUSTER_PD>; 624 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 625 }; 626 627 CPU_PD3: cpu3 { 628 #power-domain-cells = <0>; 629 power-domains = <&CLUSTER_PD>; 630 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 631 }; 632 633 CPU_PD4: cpu4 { 634 #power-domain-cells = <0>; 635 power-domains = <&CLUSTER_PD>; 636 domain-idle-states = <&BIG_CPU_SLEEP_0>; 637 }; 638 639 CPU_PD5: cpu5 { 640 #power-domain-cells = <0>; 641 power-domains = <&CLUSTER_PD>; 642 domain-idle-states = <&BIG_CPU_SLEEP_0>; 643 }; 644 645 CPU_PD6: cpu6 { 646 #power-domain-cells = <0>; 647 power-domains = <&CLUSTER_PD>; 648 domain-idle-states = <&BIG_CPU_SLEEP_0>; 649 }; 650 651 CPU_PD7: cpu7 { 652 #power-domain-cells = <0>; 653 power-domains = <&CLUSTER_PD>; 654 domain-idle-states = <&BIG_CPU_SLEEP_0>; 655 }; 656 657 CLUSTER_PD: cpu-cluster0 { 658 #power-domain-cells = <0>; 659 domain-idle-states = <&CLUSTER_SLEEP_0>; 660 }; 661 }; 662 663 reserved-memory { 664 #address-cells = <2>; 665 #size-cells = <2>; 666 ranges; 667 668 hyp_mem: memory@85700000 { 669 reg = <0x0 0x85700000 0x0 0x600000>; 670 no-map; 671 }; 672 673 xbl_mem: memory@85d00000 { 674 reg = <0x0 0x85d00000 0x0 0x140000>; 675 no-map; 676 }; 677 678 aop_mem: memory@85f00000 { 679 reg = <0x0 0x85f00000 0x0 0x20000>; 680 no-map; 681 }; 682 683 aop_cmd_db: memory@85f20000 { 684 compatible = "qcom,cmd-db"; 685 reg = <0x0 0x85f20000 0x0 0x20000>; 686 no-map; 687 }; 688 689 smem_mem: memory@86000000 { 690 reg = <0x0 0x86000000 0x0 0x200000>; 691 no-map; 692 }; 693 694 tz_mem: memory@86200000 { 695 reg = <0x0 0x86200000 0x0 0x3900000>; 696 no-map; 697 }; 698 699 rmtfs_mem: memory@89b00000 { 700 compatible = "qcom,rmtfs-mem"; 701 reg = <0x0 0x89b00000 0x0 0x200000>; 702 no-map; 703 704 qcom,client-id = <1>; 705 qcom,vmid = <15>; 706 }; 707 708 camera_mem: memory@8b700000 { 709 reg = <0x0 0x8b700000 0x0 0x500000>; 710 no-map; 711 }; 712 713 wlan_mem: memory@8bc00000 { 714 reg = <0x0 0x8bc00000 0x0 0x180000>; 715 no-map; 716 }; 717 718 npu_mem: memory@8bd80000 { 719 reg = <0x0 0x8bd80000 0x0 0x80000>; 720 no-map; 721 }; 722 723 adsp_mem: memory@8be00000 { 724 reg = <0x0 0x8be00000 0x0 0x1a00000>; 725 no-map; 726 }; 727 728 mpss_mem: memory@8d800000 { 729 reg = <0x0 0x8d800000 0x0 0x9600000>; 730 no-map; 731 }; 732 733 venus_mem: memory@96e00000 { 734 reg = <0x0 0x96e00000 0x0 0x500000>; 735 no-map; 736 }; 737 738 slpi_mem: memory@97300000 { 739 reg = <0x0 0x97300000 0x0 0x1400000>; 740 no-map; 741 }; 742 743 ipa_fw_mem: memory@98700000 { 744 reg = <0x0 0x98700000 0x0 0x10000>; 745 no-map; 746 }; 747 748 ipa_gsi_mem: memory@98710000 { 749 reg = <0x0 0x98710000 0x0 0x5000>; 750 no-map; 751 }; 752 753 gpu_mem: memory@98715000 { 754 reg = <0x0 0x98715000 0x0 0x2000>; 755 no-map; 756 }; 757 758 spss_mem: memory@98800000 { 759 reg = <0x0 0x98800000 0x0 0x100000>; 760 no-map; 761 }; 762 763 cdsp_mem: memory@98900000 { 764 reg = <0x0 0x98900000 0x0 0x1400000>; 765 no-map; 766 }; 767 768 qseecom_mem: memory@9e400000 { 769 reg = <0x0 0x9e400000 0x0 0x1400000>; 770 no-map; 771 }; 772 }; 773 774 smem { 775 compatible = "qcom,smem"; 776 memory-region = <&smem_mem>; 777 hwlocks = <&tcsr_mutex 3>; 778 }; 779 780 smp2p-cdsp { 781 compatible = "qcom,smp2p"; 782 qcom,smem = <94>, <432>; 783 784 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 785 786 mboxes = <&apss_shared 6>; 787 788 qcom,local-pid = <0>; 789 qcom,remote-pid = <5>; 790 791 cdsp_smp2p_out: master-kernel { 792 qcom,entry-name = "master-kernel"; 793 #qcom,smem-state-cells = <1>; 794 }; 795 796 cdsp_smp2p_in: slave-kernel { 797 qcom,entry-name = "slave-kernel"; 798 799 interrupt-controller; 800 #interrupt-cells = <2>; 801 }; 802 }; 803 804 smp2p-lpass { 805 compatible = "qcom,smp2p"; 806 qcom,smem = <443>, <429>; 807 808 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 809 810 mboxes = <&apss_shared 10>; 811 812 qcom,local-pid = <0>; 813 qcom,remote-pid = <2>; 814 815 adsp_smp2p_out: master-kernel { 816 qcom,entry-name = "master-kernel"; 817 #qcom,smem-state-cells = <1>; 818 }; 819 820 adsp_smp2p_in: slave-kernel { 821 qcom,entry-name = "slave-kernel"; 822 823 interrupt-controller; 824 #interrupt-cells = <2>; 825 }; 826 }; 827 828 smp2p-mpss { 829 compatible = "qcom,smp2p"; 830 qcom,smem = <435>, <428>; 831 832 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 833 834 mboxes = <&apss_shared 14>; 835 836 qcom,local-pid = <0>; 837 qcom,remote-pid = <1>; 838 839 modem_smp2p_out: master-kernel { 840 qcom,entry-name = "master-kernel"; 841 #qcom,smem-state-cells = <1>; 842 }; 843 844 modem_smp2p_in: slave-kernel { 845 qcom,entry-name = "slave-kernel"; 846 847 interrupt-controller; 848 #interrupt-cells = <2>; 849 }; 850 }; 851 852 smp2p-slpi { 853 compatible = "qcom,smp2p"; 854 qcom,smem = <481>, <430>; 855 856 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 857 858 mboxes = <&apss_shared 26>; 859 860 qcom,local-pid = <0>; 861 qcom,remote-pid = <3>; 862 863 slpi_smp2p_out: master-kernel { 864 qcom,entry-name = "master-kernel"; 865 #qcom,smem-state-cells = <1>; 866 }; 867 868 slpi_smp2p_in: slave-kernel { 869 qcom,entry-name = "slave-kernel"; 870 871 interrupt-controller; 872 #interrupt-cells = <2>; 873 }; 874 }; 875 876 soc: soc@0 { 877 #address-cells = <2>; 878 #size-cells = <2>; 879 ranges = <0 0 0 0 0x10 0>; 880 dma-ranges = <0 0 0 0 0x10 0>; 881 compatible = "simple-bus"; 882 883 gcc: clock-controller@100000 { 884 compatible = "qcom,gcc-sm8150"; 885 reg = <0x0 0x00100000 0x0 0x1f0000>; 886 #clock-cells = <1>; 887 #reset-cells = <1>; 888 #power-domain-cells = <1>; 889 clock-names = "bi_tcxo", 890 "sleep_clk"; 891 clocks = <&rpmhcc RPMH_CXO_CLK>, 892 <&sleep_clk>; 893 }; 894 895 gpi_dma0: dma-controller@800000 { 896 compatible = "qcom,sm8150-gpi-dma"; 897 reg = <0 0x800000 0 0x60000>; 898 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 911 dma-channels = <13>; 912 dma-channel-mask = <0xfa>; 913 iommus = <&apps_smmu 0x00d6 0x0>; 914 #dma-cells = <3>; 915 status = "disabled"; 916 }; 917 918 qupv3_id_0: geniqup@8c0000 { 919 compatible = "qcom,geni-se-qup"; 920 reg = <0x0 0x008c0000 0x0 0x6000>; 921 clock-names = "m-ahb", "s-ahb"; 922 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 923 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 924 iommus = <&apps_smmu 0xc3 0x0>; 925 #address-cells = <2>; 926 #size-cells = <2>; 927 ranges; 928 status = "disabled"; 929 930 i2c0: i2c@880000 { 931 compatible = "qcom,geni-i2c"; 932 reg = <0 0x00880000 0 0x4000>; 933 clock-names = "se"; 934 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 935 pinctrl-names = "default"; 936 pinctrl-0 = <&qup_i2c0_default>; 937 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 938 #address-cells = <1>; 939 #size-cells = <0>; 940 status = "disabled"; 941 }; 942 943 spi0: spi@880000 { 944 compatible = "qcom,geni-spi"; 945 reg = <0 0x880000 0 0x4000>; 946 reg-names = "se"; 947 clock-names = "se"; 948 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 949 pinctrl-names = "default"; 950 pinctrl-0 = <&qup_spi0_default>; 951 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 952 spi-max-frequency = <50000000>; 953 #address-cells = <1>; 954 #size-cells = <0>; 955 status = "disabled"; 956 }; 957 958 i2c1: i2c@884000 { 959 compatible = "qcom,geni-i2c"; 960 reg = <0 0x00884000 0 0x4000>; 961 clock-names = "se"; 962 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 963 pinctrl-names = "default"; 964 pinctrl-0 = <&qup_i2c1_default>; 965 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 status = "disabled"; 969 }; 970 971 spi1: spi@884000 { 972 compatible = "qcom,geni-spi"; 973 reg = <0 0x884000 0 0x4000>; 974 reg-names = "se"; 975 clock-names = "se"; 976 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 977 pinctrl-names = "default"; 978 pinctrl-0 = <&qup_spi1_default>; 979 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 980 spi-max-frequency = <50000000>; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 status = "disabled"; 984 }; 985 986 i2c2: i2c@888000 { 987 compatible = "qcom,geni-i2c"; 988 reg = <0 0x00888000 0 0x4000>; 989 clock-names = "se"; 990 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 991 pinctrl-names = "default"; 992 pinctrl-0 = <&qup_i2c2_default>; 993 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 status = "disabled"; 997 }; 998 999 spi2: spi@888000 { 1000 compatible = "qcom,geni-spi"; 1001 reg = <0 0x888000 0 0x4000>; 1002 reg-names = "se"; 1003 clock-names = "se"; 1004 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_spi2_default>; 1007 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1008 spi-max-frequency = <50000000>; 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 status = "disabled"; 1012 }; 1013 1014 i2c3: i2c@88c000 { 1015 compatible = "qcom,geni-i2c"; 1016 reg = <0 0x0088c000 0 0x4000>; 1017 clock-names = "se"; 1018 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&qup_i2c3_default>; 1021 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 status = "disabled"; 1025 }; 1026 1027 spi3: spi@88c000 { 1028 compatible = "qcom,geni-spi"; 1029 reg = <0 0x88c000 0 0x4000>; 1030 reg-names = "se"; 1031 clock-names = "se"; 1032 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1033 pinctrl-names = "default"; 1034 pinctrl-0 = <&qup_spi3_default>; 1035 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1036 spi-max-frequency = <50000000>; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 status = "disabled"; 1040 }; 1041 1042 i2c4: i2c@890000 { 1043 compatible = "qcom,geni-i2c"; 1044 reg = <0 0x00890000 0 0x4000>; 1045 clock-names = "se"; 1046 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1047 pinctrl-names = "default"; 1048 pinctrl-0 = <&qup_i2c4_default>; 1049 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 status = "disabled"; 1053 }; 1054 1055 spi4: spi@890000 { 1056 compatible = "qcom,geni-spi"; 1057 reg = <0 0x890000 0 0x4000>; 1058 reg-names = "se"; 1059 clock-names = "se"; 1060 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1061 pinctrl-names = "default"; 1062 pinctrl-0 = <&qup_spi4_default>; 1063 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1064 spi-max-frequency = <50000000>; 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 status = "disabled"; 1068 }; 1069 1070 i2c5: i2c@894000 { 1071 compatible = "qcom,geni-i2c"; 1072 reg = <0 0x00894000 0 0x4000>; 1073 clock-names = "se"; 1074 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1075 pinctrl-names = "default"; 1076 pinctrl-0 = <&qup_i2c5_default>; 1077 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 status = "disabled"; 1081 }; 1082 1083 spi5: spi@894000 { 1084 compatible = "qcom,geni-spi"; 1085 reg = <0 0x894000 0 0x4000>; 1086 reg-names = "se"; 1087 clock-names = "se"; 1088 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1089 pinctrl-names = "default"; 1090 pinctrl-0 = <&qup_spi5_default>; 1091 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1092 spi-max-frequency = <50000000>; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 status = "disabled"; 1096 }; 1097 1098 i2c6: i2c@898000 { 1099 compatible = "qcom,geni-i2c"; 1100 reg = <0 0x00898000 0 0x4000>; 1101 clock-names = "se"; 1102 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1103 pinctrl-names = "default"; 1104 pinctrl-0 = <&qup_i2c6_default>; 1105 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 status = "disabled"; 1109 }; 1110 1111 spi6: spi@898000 { 1112 compatible = "qcom,geni-spi"; 1113 reg = <0 0x898000 0 0x4000>; 1114 reg-names = "se"; 1115 clock-names = "se"; 1116 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&qup_spi6_default>; 1119 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1120 spi-max-frequency = <50000000>; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 status = "disabled"; 1124 }; 1125 1126 i2c7: i2c@89c000 { 1127 compatible = "qcom,geni-i2c"; 1128 reg = <0 0x0089c000 0 0x4000>; 1129 clock-names = "se"; 1130 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1131 pinctrl-names = "default"; 1132 pinctrl-0 = <&qup_i2c7_default>; 1133 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 status = "disabled"; 1137 }; 1138 1139 spi7: spi@89c000 { 1140 compatible = "qcom,geni-spi"; 1141 reg = <0 0x89c000 0 0x4000>; 1142 reg-names = "se"; 1143 clock-names = "se"; 1144 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1145 pinctrl-names = "default"; 1146 pinctrl-0 = <&qup_spi7_default>; 1147 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1148 spi-max-frequency = <50000000>; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 status = "disabled"; 1152 }; 1153 }; 1154 1155 gpi_dma1: dma-controller@a00000 { 1156 compatible = "qcom,sm8150-gpi-dma"; 1157 reg = <0 0xa00000 0 0x60000>; 1158 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1171 dma-channels = <13>; 1172 dma-channel-mask = <0xfa>; 1173 iommus = <&apps_smmu 0x0616 0x0>; 1174 #dma-cells = <3>; 1175 status = "disabled"; 1176 }; 1177 1178 qupv3_id_1: geniqup@ac0000 { 1179 compatible = "qcom,geni-se-qup"; 1180 reg = <0x0 0x00ac0000 0x0 0x6000>; 1181 clock-names = "m-ahb", "s-ahb"; 1182 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1183 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1184 iommus = <&apps_smmu 0x603 0x0>; 1185 #address-cells = <2>; 1186 #size-cells = <2>; 1187 ranges; 1188 status = "disabled"; 1189 1190 i2c8: i2c@a80000 { 1191 compatible = "qcom,geni-i2c"; 1192 reg = <0 0x00a80000 0 0x4000>; 1193 clock-names = "se"; 1194 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&qup_i2c8_default>; 1197 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 status = "disabled"; 1201 }; 1202 1203 spi8: spi@a80000 { 1204 compatible = "qcom,geni-spi"; 1205 reg = <0 0xa80000 0 0x4000>; 1206 reg-names = "se"; 1207 clock-names = "se"; 1208 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1209 pinctrl-names = "default"; 1210 pinctrl-0 = <&qup_spi8_default>; 1211 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1212 spi-max-frequency = <50000000>; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 status = "disabled"; 1216 }; 1217 1218 i2c9: i2c@a84000 { 1219 compatible = "qcom,geni-i2c"; 1220 reg = <0 0x00a84000 0 0x4000>; 1221 clock-names = "se"; 1222 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&qup_i2c9_default>; 1225 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 status = "disabled"; 1229 }; 1230 1231 spi9: spi@a84000 { 1232 compatible = "qcom,geni-spi"; 1233 reg = <0 0xa84000 0 0x4000>; 1234 reg-names = "se"; 1235 clock-names = "se"; 1236 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1237 pinctrl-names = "default"; 1238 pinctrl-0 = <&qup_spi9_default>; 1239 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1240 spi-max-frequency = <50000000>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 status = "disabled"; 1244 }; 1245 1246 i2c10: i2c@a88000 { 1247 compatible = "qcom,geni-i2c"; 1248 reg = <0 0x00a88000 0 0x4000>; 1249 clock-names = "se"; 1250 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&qup_i2c10_default>; 1253 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 status = "disabled"; 1257 }; 1258 1259 spi10: spi@a88000 { 1260 compatible = "qcom,geni-spi"; 1261 reg = <0 0xa88000 0 0x4000>; 1262 reg-names = "se"; 1263 clock-names = "se"; 1264 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1265 pinctrl-names = "default"; 1266 pinctrl-0 = <&qup_spi10_default>; 1267 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1268 spi-max-frequency = <50000000>; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 status = "disabled"; 1272 }; 1273 1274 i2c11: i2c@a8c000 { 1275 compatible = "qcom,geni-i2c"; 1276 reg = <0 0x00a8c000 0 0x4000>; 1277 clock-names = "se"; 1278 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&qup_i2c11_default>; 1281 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 status = "disabled"; 1285 }; 1286 1287 spi11: spi@a8c000 { 1288 compatible = "qcom,geni-spi"; 1289 reg = <0 0xa8c000 0 0x4000>; 1290 reg-names = "se"; 1291 clock-names = "se"; 1292 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1293 pinctrl-names = "default"; 1294 pinctrl-0 = <&qup_spi11_default>; 1295 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1296 spi-max-frequency = <50000000>; 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 status = "disabled"; 1300 }; 1301 1302 uart2: serial@a90000 { 1303 compatible = "qcom,geni-debug-uart"; 1304 reg = <0x0 0x00a90000 0x0 0x4000>; 1305 clock-names = "se"; 1306 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1307 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1308 status = "disabled"; 1309 }; 1310 1311 i2c12: i2c@a90000 { 1312 compatible = "qcom,geni-i2c"; 1313 reg = <0 0x00a90000 0 0x4000>; 1314 clock-names = "se"; 1315 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1316 pinctrl-names = "default"; 1317 pinctrl-0 = <&qup_i2c12_default>; 1318 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1319 #address-cells = <1>; 1320 #size-cells = <0>; 1321 status = "disabled"; 1322 }; 1323 1324 spi12: spi@a90000 { 1325 compatible = "qcom,geni-spi"; 1326 reg = <0 0xa90000 0 0x4000>; 1327 reg-names = "se"; 1328 clock-names = "se"; 1329 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1330 pinctrl-names = "default"; 1331 pinctrl-0 = <&qup_spi12_default>; 1332 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1333 spi-max-frequency = <50000000>; 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 status = "disabled"; 1337 }; 1338 1339 i2c16: i2c@94000 { 1340 compatible = "qcom,geni-i2c"; 1341 reg = <0 0x0094000 0 0x4000>; 1342 clock-names = "se"; 1343 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1344 pinctrl-names = "default"; 1345 pinctrl-0 = <&qup_i2c16_default>; 1346 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1347 #address-cells = <1>; 1348 #size-cells = <0>; 1349 status = "disabled"; 1350 }; 1351 1352 spi16: spi@a94000 { 1353 compatible = "qcom,geni-spi"; 1354 reg = <0 0xa94000 0 0x4000>; 1355 reg-names = "se"; 1356 clock-names = "se"; 1357 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&qup_spi16_default>; 1360 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1361 spi-max-frequency = <50000000>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 status = "disabled"; 1365 }; 1366 }; 1367 1368 gpi_dma2: dma-controller@c00000 { 1369 compatible = "qcom,sm8150-gpi-dma"; 1370 reg = <0 0xc00000 0 0x60000>; 1371 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 1384 dma-channels = <13>; 1385 dma-channel-mask = <0xfa>; 1386 iommus = <&apps_smmu 0x07b6 0x0>; 1387 #dma-cells = <3>; 1388 status = "disabled"; 1389 }; 1390 1391 qupv3_id_2: geniqup@cc0000 { 1392 compatible = "qcom,geni-se-qup"; 1393 reg = <0x0 0x00cc0000 0x0 0x6000>; 1394 1395 clock-names = "m-ahb", "s-ahb"; 1396 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1397 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1398 iommus = <&apps_smmu 0x7a3 0x0>; 1399 #address-cells = <2>; 1400 #size-cells = <2>; 1401 ranges; 1402 status = "disabled"; 1403 1404 i2c17: i2c@c80000 { 1405 compatible = "qcom,geni-i2c"; 1406 reg = <0 0x00c80000 0 0x4000>; 1407 clock-names = "se"; 1408 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1409 pinctrl-names = "default"; 1410 pinctrl-0 = <&qup_i2c17_default>; 1411 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1412 #address-cells = <1>; 1413 #size-cells = <0>; 1414 status = "disabled"; 1415 }; 1416 1417 spi17: spi@c80000 { 1418 compatible = "qcom,geni-spi"; 1419 reg = <0 0xc80000 0 0x4000>; 1420 reg-names = "se"; 1421 clock-names = "se"; 1422 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1423 pinctrl-names = "default"; 1424 pinctrl-0 = <&qup_spi17_default>; 1425 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1426 spi-max-frequency = <50000000>; 1427 #address-cells = <1>; 1428 #size-cells = <0>; 1429 status = "disabled"; 1430 }; 1431 1432 i2c18: i2c@c84000 { 1433 compatible = "qcom,geni-i2c"; 1434 reg = <0 0x00c84000 0 0x4000>; 1435 clock-names = "se"; 1436 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1437 pinctrl-names = "default"; 1438 pinctrl-0 = <&qup_i2c18_default>; 1439 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1440 #address-cells = <1>; 1441 #size-cells = <0>; 1442 status = "disabled"; 1443 }; 1444 1445 spi18: spi@c84000 { 1446 compatible = "qcom,geni-spi"; 1447 reg = <0 0xc84000 0 0x4000>; 1448 reg-names = "se"; 1449 clock-names = "se"; 1450 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1451 pinctrl-names = "default"; 1452 pinctrl-0 = <&qup_spi18_default>; 1453 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1454 spi-max-frequency = <50000000>; 1455 #address-cells = <1>; 1456 #size-cells = <0>; 1457 status = "disabled"; 1458 }; 1459 1460 i2c19: i2c@c88000 { 1461 compatible = "qcom,geni-i2c"; 1462 reg = <0 0x00c88000 0 0x4000>; 1463 clock-names = "se"; 1464 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1465 pinctrl-names = "default"; 1466 pinctrl-0 = <&qup_i2c19_default>; 1467 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1468 #address-cells = <1>; 1469 #size-cells = <0>; 1470 status = "disabled"; 1471 }; 1472 1473 spi19: spi@c88000 { 1474 compatible = "qcom,geni-spi"; 1475 reg = <0 0xc88000 0 0x4000>; 1476 reg-names = "se"; 1477 clock-names = "se"; 1478 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1479 pinctrl-names = "default"; 1480 pinctrl-0 = <&qup_spi19_default>; 1481 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1482 spi-max-frequency = <50000000>; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 status = "disabled"; 1486 }; 1487 1488 i2c13: i2c@c8c000 { 1489 compatible = "qcom,geni-i2c"; 1490 reg = <0 0x00c8c000 0 0x4000>; 1491 clock-names = "se"; 1492 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1493 pinctrl-names = "default"; 1494 pinctrl-0 = <&qup_i2c13_default>; 1495 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1496 #address-cells = <1>; 1497 #size-cells = <0>; 1498 status = "disabled"; 1499 }; 1500 1501 spi13: spi@c8c000 { 1502 compatible = "qcom,geni-spi"; 1503 reg = <0 0xc8c000 0 0x4000>; 1504 reg-names = "se"; 1505 clock-names = "se"; 1506 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1507 pinctrl-names = "default"; 1508 pinctrl-0 = <&qup_spi13_default>; 1509 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1510 spi-max-frequency = <50000000>; 1511 #address-cells = <1>; 1512 #size-cells = <0>; 1513 status = "disabled"; 1514 }; 1515 1516 i2c14: i2c@c90000 { 1517 compatible = "qcom,geni-i2c"; 1518 reg = <0 0x00c90000 0 0x4000>; 1519 clock-names = "se"; 1520 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1521 pinctrl-names = "default"; 1522 pinctrl-0 = <&qup_i2c14_default>; 1523 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1524 #address-cells = <1>; 1525 #size-cells = <0>; 1526 status = "disabled"; 1527 }; 1528 1529 spi14: spi@c90000 { 1530 compatible = "qcom,geni-spi"; 1531 reg = <0 0xc90000 0 0x4000>; 1532 reg-names = "se"; 1533 clock-names = "se"; 1534 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1535 pinctrl-names = "default"; 1536 pinctrl-0 = <&qup_spi14_default>; 1537 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1538 spi-max-frequency = <50000000>; 1539 #address-cells = <1>; 1540 #size-cells = <0>; 1541 status = "disabled"; 1542 }; 1543 1544 i2c15: i2c@c94000 { 1545 compatible = "qcom,geni-i2c"; 1546 reg = <0 0x00c94000 0 0x4000>; 1547 clock-names = "se"; 1548 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1549 pinctrl-names = "default"; 1550 pinctrl-0 = <&qup_i2c15_default>; 1551 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1552 #address-cells = <1>; 1553 #size-cells = <0>; 1554 status = "disabled"; 1555 }; 1556 1557 spi15: spi@c94000 { 1558 compatible = "qcom,geni-spi"; 1559 reg = <0 0xc94000 0 0x4000>; 1560 reg-names = "se"; 1561 clock-names = "se"; 1562 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1563 pinctrl-names = "default"; 1564 pinctrl-0 = <&qup_spi15_default>; 1565 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1566 spi-max-frequency = <50000000>; 1567 #address-cells = <1>; 1568 #size-cells = <0>; 1569 status = "disabled"; 1570 }; 1571 }; 1572 1573 config_noc: interconnect@1500000 { 1574 compatible = "qcom,sm8150-config-noc"; 1575 reg = <0 0x01500000 0 0x7400>; 1576 #interconnect-cells = <1>; 1577 qcom,bcm-voters = <&apps_bcm_voter>; 1578 }; 1579 1580 system_noc: interconnect@1620000 { 1581 compatible = "qcom,sm8150-system-noc"; 1582 reg = <0 0x01620000 0 0x19400>; 1583 #interconnect-cells = <1>; 1584 qcom,bcm-voters = <&apps_bcm_voter>; 1585 }; 1586 1587 mc_virt: interconnect@163a000 { 1588 compatible = "qcom,sm8150-mc-virt"; 1589 reg = <0 0x0163a000 0 0x1000>; 1590 #interconnect-cells = <1>; 1591 qcom,bcm-voters = <&apps_bcm_voter>; 1592 }; 1593 1594 aggre1_noc: interconnect@16e0000 { 1595 compatible = "qcom,sm8150-aggre1-noc"; 1596 reg = <0 0x016e0000 0 0xd080>; 1597 #interconnect-cells = <1>; 1598 qcom,bcm-voters = <&apps_bcm_voter>; 1599 }; 1600 1601 aggre2_noc: interconnect@1700000 { 1602 compatible = "qcom,sm8150-aggre2-noc"; 1603 reg = <0 0x01700000 0 0x20000>; 1604 #interconnect-cells = <1>; 1605 qcom,bcm-voters = <&apps_bcm_voter>; 1606 }; 1607 1608 compute_noc: interconnect@1720000 { 1609 compatible = "qcom,sm8150-compute-noc"; 1610 reg = <0 0x01720000 0 0x7000>; 1611 #interconnect-cells = <1>; 1612 qcom,bcm-voters = <&apps_bcm_voter>; 1613 }; 1614 1615 mmss_noc: interconnect@1740000 { 1616 compatible = "qcom,sm8150-mmss-noc"; 1617 reg = <0 0x01740000 0 0x1c100>; 1618 #interconnect-cells = <1>; 1619 qcom,bcm-voters = <&apps_bcm_voter>; 1620 }; 1621 1622 system-cache-controller@9200000 { 1623 compatible = "qcom,sm8150-llcc"; 1624 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 1625 reg-names = "llcc_base", "llcc_broadcast_base"; 1626 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1627 }; 1628 1629 ufs_mem_hc: ufshc@1d84000 { 1630 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 1631 "jedec,ufs-2.0"; 1632 reg = <0 0x01d84000 0 0x2500>, 1633 <0 0x01d90000 0 0x8000>; 1634 reg-names = "std", "ice"; 1635 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1636 phys = <&ufs_mem_phy_lanes>; 1637 phy-names = "ufsphy"; 1638 lanes-per-direction = <2>; 1639 #reset-cells = <1>; 1640 resets = <&gcc GCC_UFS_PHY_BCR>; 1641 reset-names = "rst"; 1642 1643 iommus = <&apps_smmu 0x300 0>; 1644 1645 clock-names = 1646 "core_clk", 1647 "bus_aggr_clk", 1648 "iface_clk", 1649 "core_clk_unipro", 1650 "ref_clk", 1651 "tx_lane0_sync_clk", 1652 "rx_lane0_sync_clk", 1653 "rx_lane1_sync_clk", 1654 "ice_core_clk"; 1655 clocks = 1656 <&gcc GCC_UFS_PHY_AXI_CLK>, 1657 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1658 <&gcc GCC_UFS_PHY_AHB_CLK>, 1659 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1660 <&rpmhcc RPMH_CXO_CLK>, 1661 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1662 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1663 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 1664 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1665 freq-table-hz = 1666 <37500000 300000000>, 1667 <0 0>, 1668 <0 0>, 1669 <37500000 300000000>, 1670 <0 0>, 1671 <0 0>, 1672 <0 0>, 1673 <0 0>, 1674 <0 300000000>; 1675 1676 status = "disabled"; 1677 }; 1678 1679 ufs_mem_phy: phy@1d87000 { 1680 compatible = "qcom,sm8150-qmp-ufs-phy"; 1681 reg = <0 0x01d87000 0 0x1c0>; 1682 #address-cells = <2>; 1683 #size-cells = <2>; 1684 ranges; 1685 clock-names = "ref", 1686 "ref_aux"; 1687 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 1688 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1689 1690 resets = <&ufs_mem_hc 0>; 1691 reset-names = "ufsphy"; 1692 status = "disabled"; 1693 1694 ufs_mem_phy_lanes: lanes@1d87400 { 1695 reg = <0 0x01d87400 0 0x108>, 1696 <0 0x01d87600 0 0x1e0>, 1697 <0 0x01d87c00 0 0x1dc>, 1698 <0 0x01d87800 0 0x108>, 1699 <0 0x01d87a00 0 0x1e0>; 1700 #phy-cells = <0>; 1701 }; 1702 }; 1703 1704 ipa_virt: interconnect@1e00000 { 1705 compatible = "qcom,sm8150-ipa-virt"; 1706 reg = <0 0x01e00000 0 0x1000>; 1707 #interconnect-cells = <1>; 1708 qcom,bcm-voters = <&apps_bcm_voter>; 1709 }; 1710 1711 tcsr_mutex_regs: syscon@1f40000 { 1712 compatible = "syscon"; 1713 reg = <0x0 0x01f40000 0x0 0x40000>; 1714 }; 1715 1716 remoteproc_slpi: remoteproc@2400000 { 1717 compatible = "qcom,sm8150-slpi-pas"; 1718 reg = <0x0 0x02400000 0x0 0x4040>; 1719 1720 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 1721 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1722 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1723 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1724 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1725 interrupt-names = "wdog", "fatal", "ready", 1726 "handover", "stop-ack"; 1727 1728 clocks = <&rpmhcc RPMH_CXO_CLK>; 1729 clock-names = "xo"; 1730 1731 power-domains = <&rpmhpd 3>, 1732 <&rpmhpd 2>; 1733 power-domain-names = "lcx", "lmx"; 1734 1735 memory-region = <&slpi_mem>; 1736 1737 qcom,qmp = <&aoss_qmp>; 1738 1739 qcom,smem-states = <&slpi_smp2p_out 0>; 1740 qcom,smem-state-names = "stop"; 1741 1742 status = "disabled"; 1743 1744 glink-edge { 1745 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 1746 label = "dsps"; 1747 qcom,remote-pid = <3>; 1748 mboxes = <&apss_shared 24>; 1749 1750 fastrpc { 1751 compatible = "qcom,fastrpc"; 1752 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1753 label = "sdsp"; 1754 #address-cells = <1>; 1755 #size-cells = <0>; 1756 1757 compute-cb@1 { 1758 compatible = "qcom,fastrpc-compute-cb"; 1759 reg = <1>; 1760 iommus = <&apps_smmu 0x05a1 0x0>; 1761 }; 1762 1763 compute-cb@2 { 1764 compatible = "qcom,fastrpc-compute-cb"; 1765 reg = <2>; 1766 iommus = <&apps_smmu 0x05a2 0x0>; 1767 }; 1768 1769 compute-cb@3 { 1770 compatible = "qcom,fastrpc-compute-cb"; 1771 reg = <3>; 1772 iommus = <&apps_smmu 0x05a3 0x0>; 1773 /* note: shared-cb = <4> in downstream */ 1774 }; 1775 }; 1776 }; 1777 }; 1778 1779 gpu: gpu@2c00000 { 1780 /* 1781 * note: the amd,imageon compatible makes it possible 1782 * to use the drm/msm driver without the display node, 1783 * make sure to remove it when display node is added 1784 */ 1785 compatible = "qcom,adreno-640.1", 1786 "qcom,adreno", 1787 "amd,imageon"; 1788 #stream-id-cells = <16>; 1789 1790 reg = <0 0x02c00000 0 0x40000>; 1791 reg-names = "kgsl_3d0_reg_memory"; 1792 1793 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1794 1795 iommus = <&adreno_smmu 0 0x401>; 1796 1797 operating-points-v2 = <&gpu_opp_table>; 1798 1799 qcom,gmu = <&gmu>; 1800 1801 status = "disabled"; 1802 1803 zap-shader { 1804 memory-region = <&gpu_mem>; 1805 }; 1806 1807 /* note: downstream checks gpu binning for 675 Mhz */ 1808 gpu_opp_table: opp-table { 1809 compatible = "operating-points-v2"; 1810 1811 opp-675000000 { 1812 opp-hz = /bits/ 64 <675000000>; 1813 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1814 }; 1815 1816 opp-585000000 { 1817 opp-hz = /bits/ 64 <585000000>; 1818 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1819 }; 1820 1821 opp-499200000 { 1822 opp-hz = /bits/ 64 <499200000>; 1823 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1824 }; 1825 1826 opp-427000000 { 1827 opp-hz = /bits/ 64 <427000000>; 1828 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1829 }; 1830 1831 opp-345000000 { 1832 opp-hz = /bits/ 64 <345000000>; 1833 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1834 }; 1835 1836 opp-257000000 { 1837 opp-hz = /bits/ 64 <257000000>; 1838 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1839 }; 1840 }; 1841 }; 1842 1843 gmu: gmu@2c6a000 { 1844 compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 1845 1846 reg = <0 0x02c6a000 0 0x30000>, 1847 <0 0x0b290000 0 0x10000>, 1848 <0 0x0b490000 0 0x10000>; 1849 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 1850 1851 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1853 interrupt-names = "hfi", "gmu"; 1854 1855 clocks = <&gpucc GPU_CC_AHB_CLK>, 1856 <&gpucc GPU_CC_CX_GMU_CLK>, 1857 <&gpucc GPU_CC_CXO_CLK>, 1858 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1859 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1860 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 1861 1862 power-domains = <&gpucc GPU_CX_GDSC>, 1863 <&gpucc GPU_GX_GDSC>; 1864 power-domain-names = "cx", "gx"; 1865 1866 iommus = <&adreno_smmu 5 0x400>; 1867 1868 operating-points-v2 = <&gmu_opp_table>; 1869 1870 status = "disabled"; 1871 1872 gmu_opp_table: opp-table { 1873 compatible = "operating-points-v2"; 1874 1875 opp-200000000 { 1876 opp-hz = /bits/ 64 <200000000>; 1877 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1878 }; 1879 }; 1880 }; 1881 1882 gpucc: clock-controller@2c90000 { 1883 compatible = "qcom,sm8150-gpucc"; 1884 reg = <0 0x02c90000 0 0x9000>; 1885 clocks = <&rpmhcc RPMH_CXO_CLK>, 1886 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1887 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1888 clock-names = "bi_tcxo", 1889 "gcc_gpu_gpll0_clk_src", 1890 "gcc_gpu_gpll0_div_clk_src"; 1891 #clock-cells = <1>; 1892 #reset-cells = <1>; 1893 #power-domain-cells = <1>; 1894 }; 1895 1896 adreno_smmu: iommu@2ca0000 { 1897 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 1898 reg = <0 0x02ca0000 0 0x10000>; 1899 #iommu-cells = <2>; 1900 #global-interrupts = <1>; 1901 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 1909 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 1910 clocks = <&gpucc GPU_CC_AHB_CLK>, 1911 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1912 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1913 clock-names = "ahb", "bus", "iface"; 1914 1915 power-domains = <&gpucc GPU_CX_GDSC>; 1916 }; 1917 1918 tlmm: pinctrl@3100000 { 1919 compatible = "qcom,sm8150-pinctrl"; 1920 reg = <0x0 0x03100000 0x0 0x300000>, 1921 <0x0 0x03500000 0x0 0x300000>, 1922 <0x0 0x03900000 0x0 0x300000>, 1923 <0x0 0x03D00000 0x0 0x300000>; 1924 reg-names = "west", "east", "north", "south"; 1925 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1926 gpio-ranges = <&tlmm 0 0 176>; 1927 gpio-controller; 1928 #gpio-cells = <2>; 1929 interrupt-controller; 1930 #interrupt-cells = <2>; 1931 1932 qup_i2c0_default: qup-i2c0-default { 1933 mux { 1934 pins = "gpio0", "gpio1"; 1935 function = "qup0"; 1936 }; 1937 1938 config { 1939 pins = "gpio0", "gpio1"; 1940 drive-strength = <0x02>; 1941 bias-disable; 1942 }; 1943 }; 1944 1945 qup_spi0_default: qup-spi0-default { 1946 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1947 function = "qup0"; 1948 drive-strength = <6>; 1949 bias-disable; 1950 }; 1951 1952 qup_i2c1_default: qup-i2c1-default { 1953 mux { 1954 pins = "gpio114", "gpio115"; 1955 function = "qup1"; 1956 }; 1957 1958 config { 1959 pins = "gpio114", "gpio115"; 1960 drive-strength = <0x02>; 1961 bias-disable; 1962 }; 1963 }; 1964 1965 qup_spi1_default: qup-spi1-default { 1966 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 1967 function = "qup1"; 1968 drive-strength = <6>; 1969 bias-disable; 1970 }; 1971 1972 qup_i2c2_default: qup-i2c2-default { 1973 mux { 1974 pins = "gpio126", "gpio127"; 1975 function = "qup2"; 1976 }; 1977 1978 config { 1979 pins = "gpio126", "gpio127"; 1980 drive-strength = <0x02>; 1981 bias-disable; 1982 }; 1983 }; 1984 1985 qup_spi2_default: qup-spi2-default { 1986 pins = "gpio126", "gpio127", "gpio128", "gpio129"; 1987 function = "qup2"; 1988 drive-strength = <6>; 1989 bias-disable; 1990 }; 1991 1992 qup_i2c3_default: qup-i2c3-default { 1993 mux { 1994 pins = "gpio144", "gpio145"; 1995 function = "qup3"; 1996 }; 1997 1998 config { 1999 pins = "gpio144", "gpio145"; 2000 drive-strength = <0x02>; 2001 bias-disable; 2002 }; 2003 }; 2004 2005 qup_spi3_default: qup-spi3-default { 2006 pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2007 function = "qup3"; 2008 drive-strength = <6>; 2009 bias-disable; 2010 }; 2011 2012 qup_i2c4_default: qup-i2c4-default { 2013 mux { 2014 pins = "gpio51", "gpio52"; 2015 function = "qup4"; 2016 }; 2017 2018 config { 2019 pins = "gpio51", "gpio52"; 2020 drive-strength = <0x02>; 2021 bias-disable; 2022 }; 2023 }; 2024 2025 qup_spi4_default: qup-spi4-default { 2026 pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2027 function = "qup4"; 2028 drive-strength = <6>; 2029 bias-disable; 2030 }; 2031 2032 qup_i2c5_default: qup-i2c5-default { 2033 mux { 2034 pins = "gpio121", "gpio122"; 2035 function = "qup5"; 2036 }; 2037 2038 config { 2039 pins = "gpio121", "gpio122"; 2040 drive-strength = <0x02>; 2041 bias-disable; 2042 }; 2043 }; 2044 2045 qup_spi5_default: qup-spi5-default { 2046 pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2047 function = "qup5"; 2048 drive-strength = <6>; 2049 bias-disable; 2050 }; 2051 2052 qup_i2c6_default: qup-i2c6-default { 2053 mux { 2054 pins = "gpio6", "gpio7"; 2055 function = "qup6"; 2056 }; 2057 2058 config { 2059 pins = "gpio6", "gpio7"; 2060 drive-strength = <0x02>; 2061 bias-disable; 2062 }; 2063 }; 2064 2065 qup_spi6_default: qup-spi6_default { 2066 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2067 function = "qup6"; 2068 drive-strength = <6>; 2069 bias-disable; 2070 }; 2071 2072 qup_i2c7_default: qup-i2c7-default { 2073 mux { 2074 pins = "gpio98", "gpio99"; 2075 function = "qup7"; 2076 }; 2077 2078 config { 2079 pins = "gpio98", "gpio99"; 2080 drive-strength = <0x02>; 2081 bias-disable; 2082 }; 2083 }; 2084 2085 qup_spi7_default: qup-spi7_default { 2086 pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2087 function = "qup7"; 2088 drive-strength = <6>; 2089 bias-disable; 2090 }; 2091 2092 qup_i2c8_default: qup-i2c8-default { 2093 mux { 2094 pins = "gpio88", "gpio89"; 2095 function = "qup8"; 2096 }; 2097 2098 config { 2099 pins = "gpio88", "gpio89"; 2100 drive-strength = <0x02>; 2101 bias-disable; 2102 }; 2103 }; 2104 2105 qup_spi8_default: qup-spi8-default { 2106 pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2107 function = "qup8"; 2108 drive-strength = <6>; 2109 bias-disable; 2110 }; 2111 2112 qup_i2c9_default: qup-i2c9-default { 2113 mux { 2114 pins = "gpio39", "gpio40"; 2115 function = "qup9"; 2116 }; 2117 2118 config { 2119 pins = "gpio39", "gpio40"; 2120 drive-strength = <0x02>; 2121 bias-disable; 2122 }; 2123 }; 2124 2125 qup_spi9_default: qup-spi9-default { 2126 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2127 function = "qup9"; 2128 drive-strength = <6>; 2129 bias-disable; 2130 }; 2131 2132 qup_i2c10_default: qup-i2c10-default { 2133 mux { 2134 pins = "gpio9", "gpio10"; 2135 function = "qup10"; 2136 }; 2137 2138 config { 2139 pins = "gpio9", "gpio10"; 2140 drive-strength = <0x02>; 2141 bias-disable; 2142 }; 2143 }; 2144 2145 qup_spi10_default: qup-spi10-default { 2146 pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2147 function = "qup10"; 2148 drive-strength = <6>; 2149 bias-disable; 2150 }; 2151 2152 qup_i2c11_default: qup-i2c11-default { 2153 mux { 2154 pins = "gpio94", "gpio95"; 2155 function = "qup11"; 2156 }; 2157 2158 config { 2159 pins = "gpio94", "gpio95"; 2160 drive-strength = <0x02>; 2161 bias-disable; 2162 }; 2163 }; 2164 2165 qup_spi11_default: qup-spi11-default { 2166 pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2167 function = "qup11"; 2168 drive-strength = <6>; 2169 bias-disable; 2170 }; 2171 2172 qup_i2c12_default: qup-i2c12-default { 2173 mux { 2174 pins = "gpio83", "gpio84"; 2175 function = "qup12"; 2176 }; 2177 2178 config { 2179 pins = "gpio83", "gpio84"; 2180 drive-strength = <0x02>; 2181 bias-disable; 2182 }; 2183 }; 2184 2185 qup_spi12_default: qup-spi12-default { 2186 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2187 function = "qup12"; 2188 drive-strength = <6>; 2189 bias-disable; 2190 }; 2191 2192 qup_i2c13_default: qup-i2c13-default { 2193 mux { 2194 pins = "gpio43", "gpio44"; 2195 function = "qup13"; 2196 }; 2197 2198 config { 2199 pins = "gpio43", "gpio44"; 2200 drive-strength = <0x02>; 2201 bias-disable; 2202 }; 2203 }; 2204 2205 qup_spi13_default: qup-spi13-default { 2206 pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2207 function = "qup13"; 2208 drive-strength = <6>; 2209 bias-disable; 2210 }; 2211 2212 qup_i2c14_default: qup-i2c14-default { 2213 mux { 2214 pins = "gpio47", "gpio48"; 2215 function = "qup14"; 2216 }; 2217 2218 config { 2219 pins = "gpio47", "gpio48"; 2220 drive-strength = <0x02>; 2221 bias-disable; 2222 }; 2223 }; 2224 2225 qup_spi14_default: qup-spi14-default { 2226 pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2227 function = "qup14"; 2228 drive-strength = <6>; 2229 bias-disable; 2230 }; 2231 2232 qup_i2c15_default: qup-i2c15-default { 2233 mux { 2234 pins = "gpio27", "gpio28"; 2235 function = "qup15"; 2236 }; 2237 2238 config { 2239 pins = "gpio27", "gpio28"; 2240 drive-strength = <0x02>; 2241 bias-disable; 2242 }; 2243 }; 2244 2245 qup_spi15_default: qup-spi15-default { 2246 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2247 function = "qup15"; 2248 drive-strength = <6>; 2249 bias-disable; 2250 }; 2251 2252 qup_i2c16_default: qup-i2c16-default { 2253 mux { 2254 pins = "gpio86", "gpio85"; 2255 function = "qup16"; 2256 }; 2257 2258 config { 2259 pins = "gpio86", "gpio85"; 2260 drive-strength = <0x02>; 2261 bias-disable; 2262 }; 2263 }; 2264 2265 qup_spi16_default: qup-spi16-default { 2266 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2267 function = "qup16"; 2268 drive-strength = <6>; 2269 bias-disable; 2270 }; 2271 2272 qup_i2c17_default: qup-i2c17-default { 2273 mux { 2274 pins = "gpio55", "gpio56"; 2275 function = "qup17"; 2276 }; 2277 2278 config { 2279 pins = "gpio55", "gpio56"; 2280 drive-strength = <0x02>; 2281 bias-disable; 2282 }; 2283 }; 2284 2285 qup_spi17_default: qup-spi17-default { 2286 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2287 function = "qup17"; 2288 drive-strength = <6>; 2289 bias-disable; 2290 }; 2291 2292 qup_i2c18_default: qup-i2c18-default { 2293 mux { 2294 pins = "gpio23", "gpio24"; 2295 function = "qup18"; 2296 }; 2297 2298 config { 2299 pins = "gpio23", "gpio24"; 2300 drive-strength = <0x02>; 2301 bias-disable; 2302 }; 2303 }; 2304 2305 qup_spi18_default: qup-spi18-default { 2306 pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2307 function = "qup18"; 2308 drive-strength = <6>; 2309 bias-disable; 2310 }; 2311 2312 qup_i2c19_default: qup-i2c19-default { 2313 mux { 2314 pins = "gpio57", "gpio58"; 2315 function = "qup19"; 2316 }; 2317 2318 config { 2319 pins = "gpio57", "gpio58"; 2320 drive-strength = <0x02>; 2321 bias-disable; 2322 }; 2323 }; 2324 2325 qup_spi19_default: qup-spi19-default { 2326 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2327 function = "qup19"; 2328 drive-strength = <6>; 2329 bias-disable; 2330 }; 2331 }; 2332 2333 remoteproc_mpss: remoteproc@4080000 { 2334 compatible = "qcom,sm8150-mpss-pas"; 2335 reg = <0x0 0x04080000 0x0 0x4040>; 2336 2337 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2338 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2339 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2340 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2341 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2342 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2343 interrupt-names = "wdog", "fatal", "ready", "handover", 2344 "stop-ack", "shutdown-ack"; 2345 2346 clocks = <&rpmhcc RPMH_CXO_CLK>; 2347 clock-names = "xo"; 2348 2349 power-domains = <&rpmhpd 7>, 2350 <&rpmhpd 0>; 2351 power-domain-names = "cx", "mss"; 2352 2353 memory-region = <&mpss_mem>; 2354 2355 qcom,qmp = <&aoss_qmp>; 2356 2357 qcom,smem-states = <&modem_smp2p_out 0>; 2358 qcom,smem-state-names = "stop"; 2359 2360 status = "disabled"; 2361 2362 glink-edge { 2363 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2364 label = "modem"; 2365 qcom,remote-pid = <1>; 2366 mboxes = <&apss_shared 12>; 2367 }; 2368 }; 2369 2370 stm@6002000 { 2371 compatible = "arm,coresight-stm", "arm,primecell"; 2372 reg = <0 0x06002000 0 0x1000>, 2373 <0 0x16280000 0 0x180000>; 2374 reg-names = "stm-base", "stm-stimulus-base"; 2375 2376 clocks = <&aoss_qmp>; 2377 clock-names = "apb_pclk"; 2378 2379 out-ports { 2380 port { 2381 stm_out: endpoint { 2382 remote-endpoint = <&funnel0_in7>; 2383 }; 2384 }; 2385 }; 2386 }; 2387 2388 funnel@6041000 { 2389 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2390 reg = <0 0x06041000 0 0x1000>; 2391 2392 clocks = <&aoss_qmp>; 2393 clock-names = "apb_pclk"; 2394 2395 out-ports { 2396 port { 2397 funnel0_out: endpoint { 2398 remote-endpoint = <&merge_funnel_in0>; 2399 }; 2400 }; 2401 }; 2402 2403 in-ports { 2404 #address-cells = <1>; 2405 #size-cells = <0>; 2406 2407 port@7 { 2408 reg = <7>; 2409 funnel0_in7: endpoint { 2410 remote-endpoint = <&stm_out>; 2411 }; 2412 }; 2413 }; 2414 }; 2415 2416 funnel@6042000 { 2417 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2418 reg = <0 0x06042000 0 0x1000>; 2419 2420 clocks = <&aoss_qmp>; 2421 clock-names = "apb_pclk"; 2422 2423 out-ports { 2424 port { 2425 funnel1_out: endpoint { 2426 remote-endpoint = <&merge_funnel_in1>; 2427 }; 2428 }; 2429 }; 2430 2431 in-ports { 2432 #address-cells = <1>; 2433 #size-cells = <0>; 2434 2435 port@4 { 2436 reg = <4>; 2437 funnel1_in4: endpoint { 2438 remote-endpoint = <&swao_replicator_out>; 2439 }; 2440 }; 2441 }; 2442 }; 2443 2444 funnel@6043000 { 2445 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2446 reg = <0 0x06043000 0 0x1000>; 2447 2448 clocks = <&aoss_qmp>; 2449 clock-names = "apb_pclk"; 2450 2451 out-ports { 2452 port { 2453 funnel2_out: endpoint { 2454 remote-endpoint = <&merge_funnel_in2>; 2455 }; 2456 }; 2457 }; 2458 2459 in-ports { 2460 #address-cells = <1>; 2461 #size-cells = <0>; 2462 2463 port@2 { 2464 reg = <2>; 2465 funnel2_in2: endpoint { 2466 remote-endpoint = <&apss_merge_funnel_out>; 2467 }; 2468 }; 2469 }; 2470 }; 2471 2472 funnel@6045000 { 2473 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2474 reg = <0 0x06045000 0 0x1000>; 2475 2476 clocks = <&aoss_qmp>; 2477 clock-names = "apb_pclk"; 2478 2479 out-ports { 2480 port { 2481 merge_funnel_out: endpoint { 2482 remote-endpoint = <&etf_in>; 2483 }; 2484 }; 2485 }; 2486 2487 in-ports { 2488 #address-cells = <1>; 2489 #size-cells = <0>; 2490 2491 port@0 { 2492 reg = <0>; 2493 merge_funnel_in0: endpoint { 2494 remote-endpoint = <&funnel0_out>; 2495 }; 2496 }; 2497 2498 port@1 { 2499 reg = <1>; 2500 merge_funnel_in1: endpoint { 2501 remote-endpoint = <&funnel1_out>; 2502 }; 2503 }; 2504 2505 port@2 { 2506 reg = <2>; 2507 merge_funnel_in2: endpoint { 2508 remote-endpoint = <&funnel2_out>; 2509 }; 2510 }; 2511 }; 2512 }; 2513 2514 replicator@6046000 { 2515 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2516 reg = <0 0x06046000 0 0x1000>; 2517 2518 clocks = <&aoss_qmp>; 2519 clock-names = "apb_pclk"; 2520 2521 out-ports { 2522 #address-cells = <1>; 2523 #size-cells = <0>; 2524 2525 port@0 { 2526 reg = <0>; 2527 replicator_out0: endpoint { 2528 remote-endpoint = <&etr_in>; 2529 }; 2530 }; 2531 2532 port@1 { 2533 reg = <1>; 2534 replicator_out1: endpoint { 2535 remote-endpoint = <&replicator1_in>; 2536 }; 2537 }; 2538 }; 2539 2540 in-ports { 2541 port { 2542 replicator_in0: endpoint { 2543 remote-endpoint = <&etf_out>; 2544 }; 2545 }; 2546 }; 2547 }; 2548 2549 etf@6047000 { 2550 compatible = "arm,coresight-tmc", "arm,primecell"; 2551 reg = <0 0x06047000 0 0x1000>; 2552 2553 clocks = <&aoss_qmp>; 2554 clock-names = "apb_pclk"; 2555 2556 out-ports { 2557 port { 2558 etf_out: endpoint { 2559 remote-endpoint = <&replicator_in0>; 2560 }; 2561 }; 2562 }; 2563 2564 in-ports { 2565 port { 2566 etf_in: endpoint { 2567 remote-endpoint = <&merge_funnel_out>; 2568 }; 2569 }; 2570 }; 2571 }; 2572 2573 etr@6048000 { 2574 compatible = "arm,coresight-tmc", "arm,primecell"; 2575 reg = <0 0x06048000 0 0x1000>; 2576 iommus = <&apps_smmu 0x05e0 0x0>; 2577 2578 clocks = <&aoss_qmp>; 2579 clock-names = "apb_pclk"; 2580 arm,scatter-gather; 2581 2582 in-ports { 2583 port { 2584 etr_in: endpoint { 2585 remote-endpoint = <&replicator_out0>; 2586 }; 2587 }; 2588 }; 2589 }; 2590 2591 replicator@604a000 { 2592 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2593 reg = <0 0x0604a000 0 0x1000>; 2594 2595 clocks = <&aoss_qmp>; 2596 clock-names = "apb_pclk"; 2597 2598 out-ports { 2599 #address-cells = <1>; 2600 #size-cells = <0>; 2601 2602 port@1 { 2603 reg = <1>; 2604 replicator1_out: endpoint { 2605 remote-endpoint = <&swao_funnel_in>; 2606 }; 2607 }; 2608 }; 2609 2610 in-ports { 2611 #address-cells = <1>; 2612 #size-cells = <0>; 2613 2614 port@1 { 2615 reg = <1>; 2616 replicator1_in: endpoint { 2617 remote-endpoint = <&replicator_out1>; 2618 }; 2619 }; 2620 }; 2621 }; 2622 2623 funnel@6b08000 { 2624 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2625 reg = <0 0x06b08000 0 0x1000>; 2626 2627 clocks = <&aoss_qmp>; 2628 clock-names = "apb_pclk"; 2629 2630 out-ports { 2631 port { 2632 swao_funnel_out: endpoint { 2633 remote-endpoint = <&swao_etf_in>; 2634 }; 2635 }; 2636 }; 2637 2638 in-ports { 2639 #address-cells = <1>; 2640 #size-cells = <0>; 2641 2642 port@6 { 2643 reg = <6>; 2644 swao_funnel_in: endpoint { 2645 remote-endpoint = <&replicator1_out>; 2646 }; 2647 }; 2648 }; 2649 }; 2650 2651 etf@6b09000 { 2652 compatible = "arm,coresight-tmc", "arm,primecell"; 2653 reg = <0 0x06b09000 0 0x1000>; 2654 2655 clocks = <&aoss_qmp>; 2656 clock-names = "apb_pclk"; 2657 2658 out-ports { 2659 port { 2660 swao_etf_out: endpoint { 2661 remote-endpoint = <&swao_replicator_in>; 2662 }; 2663 }; 2664 }; 2665 2666 in-ports { 2667 port { 2668 swao_etf_in: endpoint { 2669 remote-endpoint = <&swao_funnel_out>; 2670 }; 2671 }; 2672 }; 2673 }; 2674 2675 replicator@6b0a000 { 2676 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2677 reg = <0 0x06b0a000 0 0x1000>; 2678 2679 clocks = <&aoss_qmp>; 2680 clock-names = "apb_pclk"; 2681 qcom,replicator-loses-context; 2682 2683 out-ports { 2684 port { 2685 swao_replicator_out: endpoint { 2686 remote-endpoint = <&funnel1_in4>; 2687 }; 2688 }; 2689 }; 2690 2691 in-ports { 2692 port { 2693 swao_replicator_in: endpoint { 2694 remote-endpoint = <&swao_etf_out>; 2695 }; 2696 }; 2697 }; 2698 }; 2699 2700 etm@7040000 { 2701 compatible = "arm,coresight-etm4x", "arm,primecell"; 2702 reg = <0 0x07040000 0 0x1000>; 2703 2704 cpu = <&CPU0>; 2705 2706 clocks = <&aoss_qmp>; 2707 clock-names = "apb_pclk"; 2708 arm,coresight-loses-context-with-cpu; 2709 qcom,skip-power-up; 2710 2711 out-ports { 2712 port { 2713 etm0_out: endpoint { 2714 remote-endpoint = <&apss_funnel_in0>; 2715 }; 2716 }; 2717 }; 2718 }; 2719 2720 etm@7140000 { 2721 compatible = "arm,coresight-etm4x", "arm,primecell"; 2722 reg = <0 0x07140000 0 0x1000>; 2723 2724 cpu = <&CPU1>; 2725 2726 clocks = <&aoss_qmp>; 2727 clock-names = "apb_pclk"; 2728 arm,coresight-loses-context-with-cpu; 2729 qcom,skip-power-up; 2730 2731 out-ports { 2732 port { 2733 etm1_out: endpoint { 2734 remote-endpoint = <&apss_funnel_in1>; 2735 }; 2736 }; 2737 }; 2738 }; 2739 2740 etm@7240000 { 2741 compatible = "arm,coresight-etm4x", "arm,primecell"; 2742 reg = <0 0x07240000 0 0x1000>; 2743 2744 cpu = <&CPU2>; 2745 2746 clocks = <&aoss_qmp>; 2747 clock-names = "apb_pclk"; 2748 arm,coresight-loses-context-with-cpu; 2749 qcom,skip-power-up; 2750 2751 out-ports { 2752 port { 2753 etm2_out: endpoint { 2754 remote-endpoint = <&apss_funnel_in2>; 2755 }; 2756 }; 2757 }; 2758 }; 2759 2760 etm@7340000 { 2761 compatible = "arm,coresight-etm4x", "arm,primecell"; 2762 reg = <0 0x07340000 0 0x1000>; 2763 2764 cpu = <&CPU3>; 2765 2766 clocks = <&aoss_qmp>; 2767 clock-names = "apb_pclk"; 2768 arm,coresight-loses-context-with-cpu; 2769 qcom,skip-power-up; 2770 2771 out-ports { 2772 port { 2773 etm3_out: endpoint { 2774 remote-endpoint = <&apss_funnel_in3>; 2775 }; 2776 }; 2777 }; 2778 }; 2779 2780 etm@7440000 { 2781 compatible = "arm,coresight-etm4x", "arm,primecell"; 2782 reg = <0 0x07440000 0 0x1000>; 2783 2784 cpu = <&CPU4>; 2785 2786 clocks = <&aoss_qmp>; 2787 clock-names = "apb_pclk"; 2788 arm,coresight-loses-context-with-cpu; 2789 qcom,skip-power-up; 2790 2791 out-ports { 2792 port { 2793 etm4_out: endpoint { 2794 remote-endpoint = <&apss_funnel_in4>; 2795 }; 2796 }; 2797 }; 2798 }; 2799 2800 etm@7540000 { 2801 compatible = "arm,coresight-etm4x", "arm,primecell"; 2802 reg = <0 0x07540000 0 0x1000>; 2803 2804 cpu = <&CPU5>; 2805 2806 clocks = <&aoss_qmp>; 2807 clock-names = "apb_pclk"; 2808 arm,coresight-loses-context-with-cpu; 2809 qcom,skip-power-up; 2810 2811 out-ports { 2812 port { 2813 etm5_out: endpoint { 2814 remote-endpoint = <&apss_funnel_in5>; 2815 }; 2816 }; 2817 }; 2818 }; 2819 2820 etm@7640000 { 2821 compatible = "arm,coresight-etm4x", "arm,primecell"; 2822 reg = <0 0x07640000 0 0x1000>; 2823 2824 cpu = <&CPU6>; 2825 2826 clocks = <&aoss_qmp>; 2827 clock-names = "apb_pclk"; 2828 arm,coresight-loses-context-with-cpu; 2829 qcom,skip-power-up; 2830 2831 out-ports { 2832 port { 2833 etm6_out: endpoint { 2834 remote-endpoint = <&apss_funnel_in6>; 2835 }; 2836 }; 2837 }; 2838 }; 2839 2840 etm@7740000 { 2841 compatible = "arm,coresight-etm4x", "arm,primecell"; 2842 reg = <0 0x07740000 0 0x1000>; 2843 2844 cpu = <&CPU7>; 2845 2846 clocks = <&aoss_qmp>; 2847 clock-names = "apb_pclk"; 2848 arm,coresight-loses-context-with-cpu; 2849 qcom,skip-power-up; 2850 2851 out-ports { 2852 port { 2853 etm7_out: endpoint { 2854 remote-endpoint = <&apss_funnel_in7>; 2855 }; 2856 }; 2857 }; 2858 }; 2859 2860 funnel@7800000 { /* APSS Funnel */ 2861 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2862 reg = <0 0x07800000 0 0x1000>; 2863 2864 clocks = <&aoss_qmp>; 2865 clock-names = "apb_pclk"; 2866 2867 out-ports { 2868 port { 2869 apss_funnel_out: endpoint { 2870 remote-endpoint = <&apss_merge_funnel_in>; 2871 }; 2872 }; 2873 }; 2874 2875 in-ports { 2876 #address-cells = <1>; 2877 #size-cells = <0>; 2878 2879 port@0 { 2880 reg = <0>; 2881 apss_funnel_in0: endpoint { 2882 remote-endpoint = <&etm0_out>; 2883 }; 2884 }; 2885 2886 port@1 { 2887 reg = <1>; 2888 apss_funnel_in1: endpoint { 2889 remote-endpoint = <&etm1_out>; 2890 }; 2891 }; 2892 2893 port@2 { 2894 reg = <2>; 2895 apss_funnel_in2: endpoint { 2896 remote-endpoint = <&etm2_out>; 2897 }; 2898 }; 2899 2900 port@3 { 2901 reg = <3>; 2902 apss_funnel_in3: endpoint { 2903 remote-endpoint = <&etm3_out>; 2904 }; 2905 }; 2906 2907 port@4 { 2908 reg = <4>; 2909 apss_funnel_in4: endpoint { 2910 remote-endpoint = <&etm4_out>; 2911 }; 2912 }; 2913 2914 port@5 { 2915 reg = <5>; 2916 apss_funnel_in5: endpoint { 2917 remote-endpoint = <&etm5_out>; 2918 }; 2919 }; 2920 2921 port@6 { 2922 reg = <6>; 2923 apss_funnel_in6: endpoint { 2924 remote-endpoint = <&etm6_out>; 2925 }; 2926 }; 2927 2928 port@7 { 2929 reg = <7>; 2930 apss_funnel_in7: endpoint { 2931 remote-endpoint = <&etm7_out>; 2932 }; 2933 }; 2934 }; 2935 }; 2936 2937 funnel@7810000 { 2938 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2939 reg = <0 0x07810000 0 0x1000>; 2940 2941 clocks = <&aoss_qmp>; 2942 clock-names = "apb_pclk"; 2943 2944 out-ports { 2945 port { 2946 apss_merge_funnel_out: endpoint { 2947 remote-endpoint = <&funnel2_in2>; 2948 }; 2949 }; 2950 }; 2951 2952 in-ports { 2953 port { 2954 apss_merge_funnel_in: endpoint { 2955 remote-endpoint = <&apss_funnel_out>; 2956 }; 2957 }; 2958 }; 2959 }; 2960 2961 remoteproc_cdsp: remoteproc@8300000 { 2962 compatible = "qcom,sm8150-cdsp-pas"; 2963 reg = <0x0 0x08300000 0x0 0x4040>; 2964 2965 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2966 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2967 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2968 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2969 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2970 interrupt-names = "wdog", "fatal", "ready", 2971 "handover", "stop-ack"; 2972 2973 clocks = <&rpmhcc RPMH_CXO_CLK>; 2974 clock-names = "xo"; 2975 2976 power-domains = <&rpmhpd 7>; 2977 2978 memory-region = <&cdsp_mem>; 2979 2980 qcom,qmp = <&aoss_qmp>; 2981 2982 qcom,smem-states = <&cdsp_smp2p_out 0>; 2983 qcom,smem-state-names = "stop"; 2984 2985 status = "disabled"; 2986 2987 glink-edge { 2988 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 2989 label = "cdsp"; 2990 qcom,remote-pid = <5>; 2991 mboxes = <&apss_shared 4>; 2992 2993 fastrpc { 2994 compatible = "qcom,fastrpc"; 2995 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2996 label = "cdsp"; 2997 #address-cells = <1>; 2998 #size-cells = <0>; 2999 3000 compute-cb@1 { 3001 compatible = "qcom,fastrpc-compute-cb"; 3002 reg = <1>; 3003 iommus = <&apps_smmu 0x1401 0x2040>, 3004 <&apps_smmu 0x1421 0x0>, 3005 <&apps_smmu 0x2001 0x420>, 3006 <&apps_smmu 0x2041 0x0>; 3007 }; 3008 3009 compute-cb@2 { 3010 compatible = "qcom,fastrpc-compute-cb"; 3011 reg = <2>; 3012 iommus = <&apps_smmu 0x2 0x3440>, 3013 <&apps_smmu 0x22 0x3400>; 3014 }; 3015 3016 compute-cb@3 { 3017 compatible = "qcom,fastrpc-compute-cb"; 3018 reg = <3>; 3019 iommus = <&apps_smmu 0x3 0x3440>, 3020 <&apps_smmu 0x1423 0x0>, 3021 <&apps_smmu 0x2023 0x0>; 3022 }; 3023 3024 compute-cb@4 { 3025 compatible = "qcom,fastrpc-compute-cb"; 3026 reg = <4>; 3027 iommus = <&apps_smmu 0x4 0x3440>, 3028 <&apps_smmu 0x24 0x3400>; 3029 }; 3030 3031 compute-cb@5 { 3032 compatible = "qcom,fastrpc-compute-cb"; 3033 reg = <5>; 3034 iommus = <&apps_smmu 0x5 0x3440>, 3035 <&apps_smmu 0x25 0x3400>; 3036 }; 3037 3038 compute-cb@6 { 3039 compatible = "qcom,fastrpc-compute-cb"; 3040 reg = <6>; 3041 iommus = <&apps_smmu 0x6 0x3460>; 3042 }; 3043 3044 compute-cb@7 { 3045 compatible = "qcom,fastrpc-compute-cb"; 3046 reg = <7>; 3047 iommus = <&apps_smmu 0x7 0x3460>; 3048 }; 3049 3050 compute-cb@8 { 3051 compatible = "qcom,fastrpc-compute-cb"; 3052 reg = <8>; 3053 iommus = <&apps_smmu 0x8 0x3460>; 3054 }; 3055 3056 /* note: secure cb9 in downstream */ 3057 }; 3058 }; 3059 }; 3060 3061 usb_1_hsphy: phy@88e2000 { 3062 compatible = "qcom,sm8150-usb-hs-phy", 3063 "qcom,usb-snps-hs-7nm-phy"; 3064 reg = <0 0x088e2000 0 0x400>; 3065 status = "disabled"; 3066 #phy-cells = <0>; 3067 3068 clocks = <&rpmhcc RPMH_CXO_CLK>; 3069 clock-names = "ref"; 3070 3071 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3072 }; 3073 3074 usb_2_hsphy: phy@88e3000 { 3075 compatible = "qcom,sm8150-usb-hs-phy", 3076 "qcom,usb-snps-hs-7nm-phy"; 3077 reg = <0 0x088e3000 0 0x400>; 3078 status = "disabled"; 3079 #phy-cells = <0>; 3080 3081 clocks = <&rpmhcc RPMH_CXO_CLK>; 3082 clock-names = "ref"; 3083 3084 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3085 }; 3086 3087 usb_1_qmpphy: phy@88e9000 { 3088 compatible = "qcom,sm8150-qmp-usb3-phy"; 3089 reg = <0 0x088e9000 0 0x18c>, 3090 <0 0x088e8000 0 0x10>; 3091 reg-names = "reg-base", "dp_com"; 3092 status = "disabled"; 3093 #address-cells = <2>; 3094 #size-cells = <2>; 3095 ranges; 3096 3097 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3098 <&rpmhcc RPMH_CXO_CLK>, 3099 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3100 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3101 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3102 3103 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3104 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3105 reset-names = "phy", "common"; 3106 3107 usb_1_ssphy: lanes@88e9200 { 3108 reg = <0 0x088e9200 0 0x200>, 3109 <0 0x088e9400 0 0x200>, 3110 <0 0x088e9c00 0 0x218>, 3111 <0 0x088e9600 0 0x200>, 3112 <0 0x088e9800 0 0x200>, 3113 <0 0x088e9a00 0 0x100>; 3114 #clock-cells = <0>; 3115 #phy-cells = <0>; 3116 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3117 clock-names = "pipe0"; 3118 clock-output-names = "usb3_phy_pipe_clk_src"; 3119 }; 3120 }; 3121 3122 usb_2_qmpphy: phy@88eb000 { 3123 compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 3124 reg = <0 0x088eb000 0 0x200>; 3125 status = "disabled"; 3126 #address-cells = <2>; 3127 #size-cells = <2>; 3128 ranges; 3129 3130 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3131 <&rpmhcc RPMH_CXO_CLK>, 3132 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3133 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3134 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3135 3136 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3137 <&gcc GCC_USB3_PHY_SEC_BCR>; 3138 reset-names = "phy", "common"; 3139 3140 usb_2_ssphy: lane@88eb200 { 3141 reg = <0 0x088eb200 0 0x200>, 3142 <0 0x088eb400 0 0x200>, 3143 <0 0x088eb800 0 0x800>, 3144 <0 0x088eb600 0 0x200>; 3145 #clock-cells = <0>; 3146 #phy-cells = <0>; 3147 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3148 clock-names = "pipe0"; 3149 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3150 }; 3151 }; 3152 3153 dc_noc: interconnect@9160000 { 3154 compatible = "qcom,sm8150-dc-noc"; 3155 reg = <0 0x09160000 0 0x3200>; 3156 #interconnect-cells = <1>; 3157 qcom,bcm-voters = <&apps_bcm_voter>; 3158 }; 3159 3160 gem_noc: interconnect@9680000 { 3161 compatible = "qcom,sm8150-gem-noc"; 3162 reg = <0 0x09680000 0 0x3e200>; 3163 #interconnect-cells = <1>; 3164 qcom,bcm-voters = <&apps_bcm_voter>; 3165 }; 3166 3167 usb_1: usb@a6f8800 { 3168 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3169 reg = <0 0x0a6f8800 0 0x400>; 3170 status = "disabled"; 3171 #address-cells = <2>; 3172 #size-cells = <2>; 3173 ranges; 3174 dma-ranges; 3175 3176 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3177 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3178 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3179 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3180 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3181 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3182 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3183 "sleep", "xo"; 3184 3185 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3186 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3187 assigned-clock-rates = <19200000>, <200000000>; 3188 3189 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3190 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3191 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3192 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3193 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3194 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3195 3196 power-domains = <&gcc USB30_PRIM_GDSC>; 3197 3198 resets = <&gcc GCC_USB30_PRIM_BCR>; 3199 3200 usb_1_dwc3: dwc3@a600000 { 3201 compatible = "snps,dwc3"; 3202 reg = <0 0x0a600000 0 0xcd00>; 3203 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3204 iommus = <&apps_smmu 0x140 0>; 3205 snps,dis_u2_susphy_quirk; 3206 snps,dis_enblslpm_quirk; 3207 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3208 phy-names = "usb2-phy", "usb3-phy"; 3209 }; 3210 }; 3211 3212 usb_2: usb@a8f8800 { 3213 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3214 reg = <0 0x0a8f8800 0 0x400>; 3215 status = "disabled"; 3216 #address-cells = <2>; 3217 #size-cells = <2>; 3218 ranges; 3219 dma-ranges; 3220 3221 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3222 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3223 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3224 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3225 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3226 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3227 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3228 "sleep", "xo"; 3229 3230 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3231 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3232 assigned-clock-rates = <19200000>, <200000000>; 3233 3234 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3235 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 3236 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3237 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 3238 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3239 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3240 3241 power-domains = <&gcc USB30_SEC_GDSC>; 3242 3243 resets = <&gcc GCC_USB30_SEC_BCR>; 3244 3245 usb_2_dwc3: usb@a800000 { 3246 compatible = "snps,dwc3"; 3247 reg = <0 0x0a800000 0 0xcd00>; 3248 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3249 iommus = <&apps_smmu 0x160 0>; 3250 snps,dis_u2_susphy_quirk; 3251 snps,dis_enblslpm_quirk; 3252 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3253 phy-names = "usb2-phy", "usb3-phy"; 3254 }; 3255 }; 3256 3257 camnoc_virt: interconnect@ac00000 { 3258 compatible = "qcom,sm8150-camnoc-virt"; 3259 reg = <0 0x0ac00000 0 0x1000>; 3260 #interconnect-cells = <1>; 3261 qcom,bcm-voters = <&apps_bcm_voter>; 3262 }; 3263 3264 aoss_qmp: power-controller@c300000 { 3265 compatible = "qcom,sm8150-aoss-qmp"; 3266 reg = <0x0 0x0c300000 0x0 0x400>; 3267 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3268 mboxes = <&apss_shared 0>; 3269 3270 #clock-cells = <0>; 3271 }; 3272 3273 sram@c3f0000 { 3274 compatible = "qcom,rpmh-stats"; 3275 reg = <0 0x0c3f0000 0 0x400>; 3276 }; 3277 3278 tsens0: thermal-sensor@c263000 { 3279 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3280 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3281 <0 0x0c222000 0 0x1ff>; /* SROT */ 3282 #qcom,sensors = <16>; 3283 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3284 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3285 interrupt-names = "uplow", "critical"; 3286 #thermal-sensor-cells = <1>; 3287 }; 3288 3289 tsens1: thermal-sensor@c265000 { 3290 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3291 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3292 <0 0x0c223000 0 0x1ff>; /* SROT */ 3293 #qcom,sensors = <8>; 3294 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3295 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3296 interrupt-names = "uplow", "critical"; 3297 #thermal-sensor-cells = <1>; 3298 }; 3299 3300 spmi_bus: spmi@c440000 { 3301 compatible = "qcom,spmi-pmic-arb"; 3302 reg = <0x0 0x0c440000 0x0 0x0001100>, 3303 <0x0 0x0c600000 0x0 0x2000000>, 3304 <0x0 0x0e600000 0x0 0x0100000>, 3305 <0x0 0x0e700000 0x0 0x00a0000>, 3306 <0x0 0x0c40a000 0x0 0x0026000>; 3307 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3308 interrupt-names = "periph_irq"; 3309 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3310 qcom,ee = <0>; 3311 qcom,channel = <0>; 3312 #address-cells = <2>; 3313 #size-cells = <0>; 3314 interrupt-controller; 3315 #interrupt-cells = <4>; 3316 cell-index = <0>; 3317 }; 3318 3319 apps_smmu: iommu@15000000 { 3320 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 3321 reg = <0 0x15000000 0 0x100000>; 3322 #iommu-cells = <2>; 3323 #global-interrupts = <1>; 3324 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3331 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3332 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3333 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3334 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3336 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3337 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3338 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3340 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3341 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3342 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3343 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3344 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3345 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3347 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3349 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3350 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3351 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3352 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3353 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3354 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3360 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3362 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3387 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3388 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3389 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3390 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3391 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3393 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3394 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3395 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3396 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3397 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3398 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3399 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3400 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3401 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3402 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3403 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3404 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 3405 }; 3406 3407 remoteproc_adsp: remoteproc@17300000 { 3408 compatible = "qcom,sm8150-adsp-pas"; 3409 reg = <0x0 0x17300000 0x0 0x4040>; 3410 3411 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3412 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3413 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3414 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3415 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3416 interrupt-names = "wdog", "fatal", "ready", 3417 "handover", "stop-ack"; 3418 3419 clocks = <&rpmhcc RPMH_CXO_CLK>; 3420 clock-names = "xo"; 3421 3422 power-domains = <&rpmhpd 7>; 3423 3424 memory-region = <&adsp_mem>; 3425 3426 qcom,qmp = <&aoss_qmp>; 3427 3428 qcom,smem-states = <&adsp_smp2p_out 0>; 3429 qcom,smem-state-names = "stop"; 3430 3431 status = "disabled"; 3432 3433 glink-edge { 3434 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3435 label = "lpass"; 3436 qcom,remote-pid = <2>; 3437 mboxes = <&apss_shared 8>; 3438 3439 fastrpc { 3440 compatible = "qcom,fastrpc"; 3441 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3442 label = "adsp"; 3443 #address-cells = <1>; 3444 #size-cells = <0>; 3445 3446 compute-cb@3 { 3447 compatible = "qcom,fastrpc-compute-cb"; 3448 reg = <3>; 3449 iommus = <&apps_smmu 0x1b23 0x0>; 3450 }; 3451 3452 compute-cb@4 { 3453 compatible = "qcom,fastrpc-compute-cb"; 3454 reg = <4>; 3455 iommus = <&apps_smmu 0x1b24 0x0>; 3456 }; 3457 3458 compute-cb@5 { 3459 compatible = "qcom,fastrpc-compute-cb"; 3460 reg = <5>; 3461 iommus = <&apps_smmu 0x1b25 0x0>; 3462 }; 3463 }; 3464 }; 3465 }; 3466 3467 intc: interrupt-controller@17a00000 { 3468 compatible = "arm,gic-v3"; 3469 interrupt-controller; 3470 #interrupt-cells = <3>; 3471 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3472 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3473 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3474 }; 3475 3476 apss_shared: mailbox@17c00000 { 3477 compatible = "qcom,sm8150-apss-shared"; 3478 reg = <0x0 0x17c00000 0x0 0x1000>; 3479 #mbox-cells = <1>; 3480 }; 3481 3482 watchdog@17c10000 { 3483 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 3484 reg = <0 0x17c10000 0 0x1000>; 3485 clocks = <&sleep_clk>; 3486 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3487 }; 3488 3489 timer@17c20000 { 3490 #address-cells = <2>; 3491 #size-cells = <2>; 3492 ranges; 3493 compatible = "arm,armv7-timer-mem"; 3494 reg = <0x0 0x17c20000 0x0 0x1000>; 3495 clock-frequency = <19200000>; 3496 3497 frame@17c21000{ 3498 frame-number = <0>; 3499 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3500 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3501 reg = <0x0 0x17c21000 0x0 0x1000>, 3502 <0x0 0x17c22000 0x0 0x1000>; 3503 }; 3504 3505 frame@17c23000 { 3506 frame-number = <1>; 3507 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3508 reg = <0x0 0x17c23000 0x0 0x1000>; 3509 status = "disabled"; 3510 }; 3511 3512 frame@17c25000 { 3513 frame-number = <2>; 3514 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3515 reg = <0x0 0x17c25000 0x0 0x1000>; 3516 status = "disabled"; 3517 }; 3518 3519 frame@17c27000 { 3520 frame-number = <3>; 3521 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3522 reg = <0x0 0x17c26000 0x0 0x1000>; 3523 status = "disabled"; 3524 }; 3525 3526 frame@17c29000 { 3527 frame-number = <4>; 3528 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3529 reg = <0x0 0x17c29000 0x0 0x1000>; 3530 status = "disabled"; 3531 }; 3532 3533 frame@17c2b000 { 3534 frame-number = <5>; 3535 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3536 reg = <0x0 0x17c2b000 0x0 0x1000>; 3537 status = "disabled"; 3538 }; 3539 3540 frame@17c2d000 { 3541 frame-number = <6>; 3542 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3543 reg = <0x0 0x17c2d000 0x0 0x1000>; 3544 status = "disabled"; 3545 }; 3546 }; 3547 3548 apps_rsc: rsc@18200000 { 3549 label = "apps_rsc"; 3550 compatible = "qcom,rpmh-rsc"; 3551 reg = <0x0 0x18200000 0x0 0x10000>, 3552 <0x0 0x18210000 0x0 0x10000>, 3553 <0x0 0x18220000 0x0 0x10000>; 3554 reg-names = "drv-0", "drv-1", "drv-2"; 3555 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3556 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3557 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3558 qcom,tcs-offset = <0xd00>; 3559 qcom,drv-id = <2>; 3560 qcom,tcs-config = <ACTIVE_TCS 2>, 3561 <SLEEP_TCS 1>, 3562 <WAKE_TCS 1>, 3563 <CONTROL_TCS 0>; 3564 3565 rpmhcc: clock-controller { 3566 compatible = "qcom,sm8150-rpmh-clk"; 3567 #clock-cells = <1>; 3568 clock-names = "xo"; 3569 clocks = <&xo_board>; 3570 }; 3571 3572 rpmhpd: power-controller { 3573 compatible = "qcom,sm8150-rpmhpd"; 3574 #power-domain-cells = <1>; 3575 operating-points-v2 = <&rpmhpd_opp_table>; 3576 3577 rpmhpd_opp_table: opp-table { 3578 compatible = "operating-points-v2"; 3579 3580 rpmhpd_opp_ret: opp1 { 3581 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3582 }; 3583 3584 rpmhpd_opp_min_svs: opp2 { 3585 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3586 }; 3587 3588 rpmhpd_opp_low_svs: opp3 { 3589 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3590 }; 3591 3592 rpmhpd_opp_svs: opp4 { 3593 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3594 }; 3595 3596 rpmhpd_opp_svs_l1: opp5 { 3597 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3598 }; 3599 3600 rpmhpd_opp_svs_l2: opp6 { 3601 opp-level = <224>; 3602 }; 3603 3604 rpmhpd_opp_nom: opp7 { 3605 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3606 }; 3607 3608 rpmhpd_opp_nom_l1: opp8 { 3609 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3610 }; 3611 3612 rpmhpd_opp_nom_l2: opp9 { 3613 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3614 }; 3615 3616 rpmhpd_opp_turbo: opp10 { 3617 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3618 }; 3619 3620 rpmhpd_opp_turbo_l1: opp11 { 3621 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3622 }; 3623 }; 3624 }; 3625 3626 apps_bcm_voter: bcm_voter { 3627 compatible = "qcom,bcm-voter"; 3628 }; 3629 }; 3630 3631 osm_l3: interconnect@18321000 { 3632 compatible = "qcom,sm8150-osm-l3"; 3633 reg = <0 0x18321000 0 0x1400>; 3634 3635 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3636 clock-names = "xo", "alternate"; 3637 3638 #interconnect-cells = <1>; 3639 }; 3640 3641 cpufreq_hw: cpufreq@18323000 { 3642 compatible = "qcom,cpufreq-hw"; 3643 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 3644 <0 0x18327800 0 0x1400>; 3645 reg-names = "freq-domain0", "freq-domain1", 3646 "freq-domain2"; 3647 3648 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3649 clock-names = "xo", "alternate"; 3650 3651 #freq-domain-cells = <1>; 3652 }; 3653 3654 wifi: wifi@18800000 { 3655 compatible = "qcom,wcn3990-wifi"; 3656 reg = <0 0x18800000 0 0x800000>; 3657 reg-names = "membase"; 3658 memory-region = <&wlan_mem>; 3659 clock-names = "cxo_ref_clk_pin", "qdss"; 3660 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 3661 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3662 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3663 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3664 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3665 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3666 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3667 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3668 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3669 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3670 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3671 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3672 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3673 iommus = <&apps_smmu 0x0640 0x1>; 3674 status = "disabled"; 3675 }; 3676 }; 3677 3678 timer { 3679 compatible = "arm,armv8-timer"; 3680 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 3681 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 3682 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 3683 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 3684 }; 3685 3686 thermal-zones { 3687 cpu0-thermal { 3688 polling-delay-passive = <250>; 3689 polling-delay = <1000>; 3690 3691 thermal-sensors = <&tsens0 1>; 3692 3693 trips { 3694 cpu0_alert0: trip-point0 { 3695 temperature = <90000>; 3696 hysteresis = <2000>; 3697 type = "passive"; 3698 }; 3699 3700 cpu0_alert1: trip-point1 { 3701 temperature = <95000>; 3702 hysteresis = <2000>; 3703 type = "passive"; 3704 }; 3705 3706 cpu0_crit: cpu_crit { 3707 temperature = <110000>; 3708 hysteresis = <1000>; 3709 type = "critical"; 3710 }; 3711 }; 3712 3713 cooling-maps { 3714 map0 { 3715 trip = <&cpu0_alert0>; 3716 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3717 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3718 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3719 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3720 }; 3721 map1 { 3722 trip = <&cpu0_alert1>; 3723 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3724 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3725 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3726 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3727 }; 3728 }; 3729 }; 3730 3731 cpu1-thermal { 3732 polling-delay-passive = <250>; 3733 polling-delay = <1000>; 3734 3735 thermal-sensors = <&tsens0 2>; 3736 3737 trips { 3738 cpu1_alert0: trip-point0 { 3739 temperature = <90000>; 3740 hysteresis = <2000>; 3741 type = "passive"; 3742 }; 3743 3744 cpu1_alert1: trip-point1 { 3745 temperature = <95000>; 3746 hysteresis = <2000>; 3747 type = "passive"; 3748 }; 3749 3750 cpu1_crit: cpu_crit { 3751 temperature = <110000>; 3752 hysteresis = <1000>; 3753 type = "critical"; 3754 }; 3755 }; 3756 3757 cooling-maps { 3758 map0 { 3759 trip = <&cpu1_alert0>; 3760 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3761 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3762 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3763 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3764 }; 3765 map1 { 3766 trip = <&cpu1_alert1>; 3767 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3768 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3769 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3770 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3771 }; 3772 }; 3773 }; 3774 3775 cpu2-thermal { 3776 polling-delay-passive = <250>; 3777 polling-delay = <1000>; 3778 3779 thermal-sensors = <&tsens0 3>; 3780 3781 trips { 3782 cpu2_alert0: trip-point0 { 3783 temperature = <90000>; 3784 hysteresis = <2000>; 3785 type = "passive"; 3786 }; 3787 3788 cpu2_alert1: trip-point1 { 3789 temperature = <95000>; 3790 hysteresis = <2000>; 3791 type = "passive"; 3792 }; 3793 3794 cpu2_crit: cpu_crit { 3795 temperature = <110000>; 3796 hysteresis = <1000>; 3797 type = "critical"; 3798 }; 3799 }; 3800 3801 cooling-maps { 3802 map0 { 3803 trip = <&cpu2_alert0>; 3804 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3805 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3806 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3807 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3808 }; 3809 map1 { 3810 trip = <&cpu2_alert1>; 3811 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3812 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3813 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3814 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3815 }; 3816 }; 3817 }; 3818 3819 cpu3-thermal { 3820 polling-delay-passive = <250>; 3821 polling-delay = <1000>; 3822 3823 thermal-sensors = <&tsens0 4>; 3824 3825 trips { 3826 cpu3_alert0: trip-point0 { 3827 temperature = <90000>; 3828 hysteresis = <2000>; 3829 type = "passive"; 3830 }; 3831 3832 cpu3_alert1: trip-point1 { 3833 temperature = <95000>; 3834 hysteresis = <2000>; 3835 type = "passive"; 3836 }; 3837 3838 cpu3_crit: cpu_crit { 3839 temperature = <110000>; 3840 hysteresis = <1000>; 3841 type = "critical"; 3842 }; 3843 }; 3844 3845 cooling-maps { 3846 map0 { 3847 trip = <&cpu3_alert0>; 3848 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3849 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3850 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3851 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3852 }; 3853 map1 { 3854 trip = <&cpu3_alert1>; 3855 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3856 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3857 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3858 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3859 }; 3860 }; 3861 }; 3862 3863 cpu4-top-thermal { 3864 polling-delay-passive = <250>; 3865 polling-delay = <1000>; 3866 3867 thermal-sensors = <&tsens0 7>; 3868 3869 trips { 3870 cpu4_top_alert0: trip-point0 { 3871 temperature = <90000>; 3872 hysteresis = <2000>; 3873 type = "passive"; 3874 }; 3875 3876 cpu4_top_alert1: trip-point1 { 3877 temperature = <95000>; 3878 hysteresis = <2000>; 3879 type = "passive"; 3880 }; 3881 3882 cpu4_top_crit: cpu_crit { 3883 temperature = <110000>; 3884 hysteresis = <1000>; 3885 type = "critical"; 3886 }; 3887 }; 3888 3889 cooling-maps { 3890 map0 { 3891 trip = <&cpu4_top_alert0>; 3892 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3893 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3894 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3895 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3896 }; 3897 map1 { 3898 trip = <&cpu4_top_alert1>; 3899 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3900 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3901 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3902 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3903 }; 3904 }; 3905 }; 3906 3907 cpu5-top-thermal { 3908 polling-delay-passive = <250>; 3909 polling-delay = <1000>; 3910 3911 thermal-sensors = <&tsens0 8>; 3912 3913 trips { 3914 cpu5_top_alert0: trip-point0 { 3915 temperature = <90000>; 3916 hysteresis = <2000>; 3917 type = "passive"; 3918 }; 3919 3920 cpu5_top_alert1: trip-point1 { 3921 temperature = <95000>; 3922 hysteresis = <2000>; 3923 type = "passive"; 3924 }; 3925 3926 cpu5_top_crit: cpu_crit { 3927 temperature = <110000>; 3928 hysteresis = <1000>; 3929 type = "critical"; 3930 }; 3931 }; 3932 3933 cooling-maps { 3934 map0 { 3935 trip = <&cpu5_top_alert0>; 3936 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3937 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3938 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3939 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3940 }; 3941 map1 { 3942 trip = <&cpu5_top_alert1>; 3943 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3944 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3945 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3946 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3947 }; 3948 }; 3949 }; 3950 3951 cpu6-top-thermal { 3952 polling-delay-passive = <250>; 3953 polling-delay = <1000>; 3954 3955 thermal-sensors = <&tsens0 9>; 3956 3957 trips { 3958 cpu6_top_alert0: trip-point0 { 3959 temperature = <90000>; 3960 hysteresis = <2000>; 3961 type = "passive"; 3962 }; 3963 3964 cpu6_top_alert1: trip-point1 { 3965 temperature = <95000>; 3966 hysteresis = <2000>; 3967 type = "passive"; 3968 }; 3969 3970 cpu6_top_crit: cpu_crit { 3971 temperature = <110000>; 3972 hysteresis = <1000>; 3973 type = "critical"; 3974 }; 3975 }; 3976 3977 cooling-maps { 3978 map0 { 3979 trip = <&cpu6_top_alert0>; 3980 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3981 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3982 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3983 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3984 }; 3985 map1 { 3986 trip = <&cpu6_top_alert1>; 3987 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3988 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3989 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3990 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3991 }; 3992 }; 3993 }; 3994 3995 cpu7-top-thermal { 3996 polling-delay-passive = <250>; 3997 polling-delay = <1000>; 3998 3999 thermal-sensors = <&tsens0 10>; 4000 4001 trips { 4002 cpu7_top_alert0: trip-point0 { 4003 temperature = <90000>; 4004 hysteresis = <2000>; 4005 type = "passive"; 4006 }; 4007 4008 cpu7_top_alert1: trip-point1 { 4009 temperature = <95000>; 4010 hysteresis = <2000>; 4011 type = "passive"; 4012 }; 4013 4014 cpu7_top_crit: cpu_crit { 4015 temperature = <110000>; 4016 hysteresis = <1000>; 4017 type = "critical"; 4018 }; 4019 }; 4020 4021 cooling-maps { 4022 map0 { 4023 trip = <&cpu7_top_alert0>; 4024 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4025 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4026 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4027 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4028 }; 4029 map1 { 4030 trip = <&cpu7_top_alert1>; 4031 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4032 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4033 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4034 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4035 }; 4036 }; 4037 }; 4038 4039 cpu4-bottom-thermal { 4040 polling-delay-passive = <250>; 4041 polling-delay = <1000>; 4042 4043 thermal-sensors = <&tsens0 11>; 4044 4045 trips { 4046 cpu4_bottom_alert0: trip-point0 { 4047 temperature = <90000>; 4048 hysteresis = <2000>; 4049 type = "passive"; 4050 }; 4051 4052 cpu4_bottom_alert1: trip-point1 { 4053 temperature = <95000>; 4054 hysteresis = <2000>; 4055 type = "passive"; 4056 }; 4057 4058 cpu4_bottom_crit: cpu_crit { 4059 temperature = <110000>; 4060 hysteresis = <1000>; 4061 type = "critical"; 4062 }; 4063 }; 4064 4065 cooling-maps { 4066 map0 { 4067 trip = <&cpu4_bottom_alert0>; 4068 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4069 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4070 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4071 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4072 }; 4073 map1 { 4074 trip = <&cpu4_bottom_alert1>; 4075 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4076 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4077 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4078 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4079 }; 4080 }; 4081 }; 4082 4083 cpu5-bottom-thermal { 4084 polling-delay-passive = <250>; 4085 polling-delay = <1000>; 4086 4087 thermal-sensors = <&tsens0 12>; 4088 4089 trips { 4090 cpu5_bottom_alert0: trip-point0 { 4091 temperature = <90000>; 4092 hysteresis = <2000>; 4093 type = "passive"; 4094 }; 4095 4096 cpu5_bottom_alert1: trip-point1 { 4097 temperature = <95000>; 4098 hysteresis = <2000>; 4099 type = "passive"; 4100 }; 4101 4102 cpu5_bottom_crit: cpu_crit { 4103 temperature = <110000>; 4104 hysteresis = <1000>; 4105 type = "critical"; 4106 }; 4107 }; 4108 4109 cooling-maps { 4110 map0 { 4111 trip = <&cpu5_bottom_alert0>; 4112 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4113 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4114 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4115 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4116 }; 4117 map1 { 4118 trip = <&cpu5_bottom_alert1>; 4119 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4120 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4121 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4122 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4123 }; 4124 }; 4125 }; 4126 4127 cpu6-bottom-thermal { 4128 polling-delay-passive = <250>; 4129 polling-delay = <1000>; 4130 4131 thermal-sensors = <&tsens0 13>; 4132 4133 trips { 4134 cpu6_bottom_alert0: trip-point0 { 4135 temperature = <90000>; 4136 hysteresis = <2000>; 4137 type = "passive"; 4138 }; 4139 4140 cpu6_bottom_alert1: trip-point1 { 4141 temperature = <95000>; 4142 hysteresis = <2000>; 4143 type = "passive"; 4144 }; 4145 4146 cpu6_bottom_crit: cpu_crit { 4147 temperature = <110000>; 4148 hysteresis = <1000>; 4149 type = "critical"; 4150 }; 4151 }; 4152 4153 cooling-maps { 4154 map0 { 4155 trip = <&cpu6_bottom_alert0>; 4156 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4157 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4158 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4159 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4160 }; 4161 map1 { 4162 trip = <&cpu6_bottom_alert1>; 4163 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4164 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4165 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4166 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4167 }; 4168 }; 4169 }; 4170 4171 cpu7-bottom-thermal { 4172 polling-delay-passive = <250>; 4173 polling-delay = <1000>; 4174 4175 thermal-sensors = <&tsens0 14>; 4176 4177 trips { 4178 cpu7_bottom_alert0: trip-point0 { 4179 temperature = <90000>; 4180 hysteresis = <2000>; 4181 type = "passive"; 4182 }; 4183 4184 cpu7_bottom_alert1: trip-point1 { 4185 temperature = <95000>; 4186 hysteresis = <2000>; 4187 type = "passive"; 4188 }; 4189 4190 cpu7_bottom_crit: cpu_crit { 4191 temperature = <110000>; 4192 hysteresis = <1000>; 4193 type = "critical"; 4194 }; 4195 }; 4196 4197 cooling-maps { 4198 map0 { 4199 trip = <&cpu7_bottom_alert0>; 4200 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4201 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4202 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4203 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4204 }; 4205 map1 { 4206 trip = <&cpu7_bottom_alert1>; 4207 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4208 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4209 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4210 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4211 }; 4212 }; 4213 }; 4214 4215 aoss0-thermal { 4216 polling-delay-passive = <250>; 4217 polling-delay = <1000>; 4218 4219 thermal-sensors = <&tsens0 0>; 4220 4221 trips { 4222 aoss0_alert0: trip-point0 { 4223 temperature = <90000>; 4224 hysteresis = <2000>; 4225 type = "hot"; 4226 }; 4227 }; 4228 }; 4229 4230 cluster0-thermal { 4231 polling-delay-passive = <250>; 4232 polling-delay = <1000>; 4233 4234 thermal-sensors = <&tsens0 5>; 4235 4236 trips { 4237 cluster0_alert0: trip-point0 { 4238 temperature = <90000>; 4239 hysteresis = <2000>; 4240 type = "hot"; 4241 }; 4242 cluster0_crit: cluster0_crit { 4243 temperature = <110000>; 4244 hysteresis = <2000>; 4245 type = "critical"; 4246 }; 4247 }; 4248 }; 4249 4250 cluster1-thermal { 4251 polling-delay-passive = <250>; 4252 polling-delay = <1000>; 4253 4254 thermal-sensors = <&tsens0 6>; 4255 4256 trips { 4257 cluster1_alert0: trip-point0 { 4258 temperature = <90000>; 4259 hysteresis = <2000>; 4260 type = "hot"; 4261 }; 4262 cluster1_crit: cluster1_crit { 4263 temperature = <110000>; 4264 hysteresis = <2000>; 4265 type = "critical"; 4266 }; 4267 }; 4268 }; 4269 4270 gpu-thermal-top { 4271 polling-delay-passive = <250>; 4272 polling-delay = <1000>; 4273 4274 thermal-sensors = <&tsens0 15>; 4275 4276 trips { 4277 gpu1_alert0: trip-point0 { 4278 temperature = <90000>; 4279 hysteresis = <2000>; 4280 type = "hot"; 4281 }; 4282 }; 4283 }; 4284 4285 aoss1-thermal { 4286 polling-delay-passive = <250>; 4287 polling-delay = <1000>; 4288 4289 thermal-sensors = <&tsens1 0>; 4290 4291 trips { 4292 aoss1_alert0: trip-point0 { 4293 temperature = <90000>; 4294 hysteresis = <2000>; 4295 type = "hot"; 4296 }; 4297 }; 4298 }; 4299 4300 wlan-thermal { 4301 polling-delay-passive = <250>; 4302 polling-delay = <1000>; 4303 4304 thermal-sensors = <&tsens1 1>; 4305 4306 trips { 4307 wlan_alert0: trip-point0 { 4308 temperature = <90000>; 4309 hysteresis = <2000>; 4310 type = "hot"; 4311 }; 4312 }; 4313 }; 4314 4315 video-thermal { 4316 polling-delay-passive = <250>; 4317 polling-delay = <1000>; 4318 4319 thermal-sensors = <&tsens1 2>; 4320 4321 trips { 4322 video_alert0: trip-point0 { 4323 temperature = <90000>; 4324 hysteresis = <2000>; 4325 type = "hot"; 4326 }; 4327 }; 4328 }; 4329 4330 mem-thermal { 4331 polling-delay-passive = <250>; 4332 polling-delay = <1000>; 4333 4334 thermal-sensors = <&tsens1 3>; 4335 4336 trips { 4337 mem_alert0: trip-point0 { 4338 temperature = <90000>; 4339 hysteresis = <2000>; 4340 type = "hot"; 4341 }; 4342 }; 4343 }; 4344 4345 q6-hvx-thermal { 4346 polling-delay-passive = <250>; 4347 polling-delay = <1000>; 4348 4349 thermal-sensors = <&tsens1 4>; 4350 4351 trips { 4352 q6_hvx_alert0: trip-point0 { 4353 temperature = <90000>; 4354 hysteresis = <2000>; 4355 type = "hot"; 4356 }; 4357 }; 4358 }; 4359 4360 camera-thermal { 4361 polling-delay-passive = <250>; 4362 polling-delay = <1000>; 4363 4364 thermal-sensors = <&tsens1 5>; 4365 4366 trips { 4367 camera_alert0: trip-point0 { 4368 temperature = <90000>; 4369 hysteresis = <2000>; 4370 type = "hot"; 4371 }; 4372 }; 4373 }; 4374 4375 compute-thermal { 4376 polling-delay-passive = <250>; 4377 polling-delay = <1000>; 4378 4379 thermal-sensors = <&tsens1 6>; 4380 4381 trips { 4382 compute_alert0: trip-point0 { 4383 temperature = <90000>; 4384 hysteresis = <2000>; 4385 type = "hot"; 4386 }; 4387 }; 4388 }; 4389 4390 modem-thermal { 4391 polling-delay-passive = <250>; 4392 polling-delay = <1000>; 4393 4394 thermal-sensors = <&tsens1 7>; 4395 4396 trips { 4397 modem_alert0: trip-point0 { 4398 temperature = <90000>; 4399 hysteresis = <2000>; 4400 type = "hot"; 4401 }; 4402 }; 4403 }; 4404 4405 npu-thermal { 4406 polling-delay-passive = <250>; 4407 polling-delay = <1000>; 4408 4409 thermal-sensors = <&tsens1 8>; 4410 4411 trips { 4412 npu_alert0: trip-point0 { 4413 temperature = <90000>; 4414 hysteresis = <2000>; 4415 type = "hot"; 4416 }; 4417 }; 4418 }; 4419 4420 modem-vec-thermal { 4421 polling-delay-passive = <250>; 4422 polling-delay = <1000>; 4423 4424 thermal-sensors = <&tsens1 9>; 4425 4426 trips { 4427 modem_vec_alert0: trip-point0 { 4428 temperature = <90000>; 4429 hysteresis = <2000>; 4430 type = "hot"; 4431 }; 4432 }; 4433 }; 4434 4435 modem-scl-thermal { 4436 polling-delay-passive = <250>; 4437 polling-delay = <1000>; 4438 4439 thermal-sensors = <&tsens1 10>; 4440 4441 trips { 4442 modem_scl_alert0: trip-point0 { 4443 temperature = <90000>; 4444 hysteresis = <2000>; 4445 type = "hot"; 4446 }; 4447 }; 4448 }; 4449 4450 gpu-thermal-bottom { 4451 polling-delay-passive = <250>; 4452 polling-delay = <1000>; 4453 4454 thermal-sensors = <&tsens1 11>; 4455 4456 trips { 4457 gpu2_alert0: trip-point0 { 4458 temperature = <90000>; 4459 hysteresis = <2000>; 4460 type = "hot"; 4461 }; 4462 }; 4463 }; 4464 }; 4465}; 4466