1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/dma/qcom-gpi.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,dispcc-sm8150.h> 13#include <dt-bindings/clock/qcom,gcc-sm8150.h> 14#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sm8150.h> 17#include <dt-bindings/thermal/thermal.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 chosen { }; 26 27 clocks { 28 xo_board: xo-board { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <38400000>; 32 clock-output-names = "xo_board"; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32764>; 39 clock-output-names = "sleep_clk"; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 CPU0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "qcom,kryo485"; 50 reg = <0x0 0x0>; 51 enable-method = "psci"; 52 capacity-dmips-mhz = <488>; 53 dynamic-power-coefficient = <232>; 54 next-level-cache = <&L2_0>; 55 qcom,freq-domain = <&cpufreq_hw 0>; 56 operating-points-v2 = <&cpu0_opp_table>; 57 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 58 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 59 power-domains = <&CPU_PD0>; 60 power-domain-names = "psci"; 61 #cooling-cells = <2>; 62 L2_0: l2-cache { 63 compatible = "cache"; 64 cache-level = <2>; 65 next-level-cache = <&L3_0>; 66 L3_0: l3-cache { 67 compatible = "cache"; 68 cache-level = <3>; 69 }; 70 }; 71 }; 72 73 CPU1: cpu@100 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo485"; 76 reg = <0x0 0x100>; 77 enable-method = "psci"; 78 capacity-dmips-mhz = <488>; 79 dynamic-power-coefficient = <232>; 80 next-level-cache = <&L2_100>; 81 qcom,freq-domain = <&cpufreq_hw 0>; 82 operating-points-v2 = <&cpu0_opp_table>; 83 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 84 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 85 power-domains = <&CPU_PD1>; 86 power-domain-names = "psci"; 87 #cooling-cells = <2>; 88 L2_100: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 next-level-cache = <&L3_0>; 92 }; 93 94 }; 95 96 CPU2: cpu@200 { 97 device_type = "cpu"; 98 compatible = "qcom,kryo485"; 99 reg = <0x0 0x200>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <488>; 102 dynamic-power-coefficient = <232>; 103 next-level-cache = <&L2_200>; 104 qcom,freq-domain = <&cpufreq_hw 0>; 105 operating-points-v2 = <&cpu0_opp_table>; 106 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 107 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 108 power-domains = <&CPU_PD2>; 109 power-domain-names = "psci"; 110 #cooling-cells = <2>; 111 L2_200: l2-cache { 112 compatible = "cache"; 113 cache-level = <2>; 114 next-level-cache = <&L3_0>; 115 }; 116 }; 117 118 CPU3: cpu@300 { 119 device_type = "cpu"; 120 compatible = "qcom,kryo485"; 121 reg = <0x0 0x300>; 122 enable-method = "psci"; 123 capacity-dmips-mhz = <488>; 124 dynamic-power-coefficient = <232>; 125 next-level-cache = <&L2_300>; 126 qcom,freq-domain = <&cpufreq_hw 0>; 127 operating-points-v2 = <&cpu0_opp_table>; 128 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 129 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 130 power-domains = <&CPU_PD3>; 131 power-domain-names = "psci"; 132 #cooling-cells = <2>; 133 L2_300: l2-cache { 134 compatible = "cache"; 135 cache-level = <2>; 136 next-level-cache = <&L3_0>; 137 }; 138 }; 139 140 CPU4: cpu@400 { 141 device_type = "cpu"; 142 compatible = "qcom,kryo485"; 143 reg = <0x0 0x400>; 144 enable-method = "psci"; 145 capacity-dmips-mhz = <1024>; 146 dynamic-power-coefficient = <369>; 147 next-level-cache = <&L2_400>; 148 qcom,freq-domain = <&cpufreq_hw 1>; 149 operating-points-v2 = <&cpu4_opp_table>; 150 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 151 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 152 power-domains = <&CPU_PD4>; 153 power-domain-names = "psci"; 154 #cooling-cells = <2>; 155 L2_400: l2-cache { 156 compatible = "cache"; 157 cache-level = <2>; 158 next-level-cache = <&L3_0>; 159 }; 160 }; 161 162 CPU5: cpu@500 { 163 device_type = "cpu"; 164 compatible = "qcom,kryo485"; 165 reg = <0x0 0x500>; 166 enable-method = "psci"; 167 capacity-dmips-mhz = <1024>; 168 dynamic-power-coefficient = <369>; 169 next-level-cache = <&L2_500>; 170 qcom,freq-domain = <&cpufreq_hw 1>; 171 operating-points-v2 = <&cpu4_opp_table>; 172 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 173 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 174 power-domains = <&CPU_PD5>; 175 power-domain-names = "psci"; 176 #cooling-cells = <2>; 177 L2_500: l2-cache { 178 compatible = "cache"; 179 cache-level = <2>; 180 next-level-cache = <&L3_0>; 181 }; 182 }; 183 184 CPU6: cpu@600 { 185 device_type = "cpu"; 186 compatible = "qcom,kryo485"; 187 reg = <0x0 0x600>; 188 enable-method = "psci"; 189 capacity-dmips-mhz = <1024>; 190 dynamic-power-coefficient = <369>; 191 next-level-cache = <&L2_600>; 192 qcom,freq-domain = <&cpufreq_hw 1>; 193 operating-points-v2 = <&cpu4_opp_table>; 194 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 195 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 196 power-domains = <&CPU_PD6>; 197 power-domain-names = "psci"; 198 #cooling-cells = <2>; 199 L2_600: l2-cache { 200 compatible = "cache"; 201 cache-level = <2>; 202 next-level-cache = <&L3_0>; 203 }; 204 }; 205 206 CPU7: cpu@700 { 207 device_type = "cpu"; 208 compatible = "qcom,kryo485"; 209 reg = <0x0 0x700>; 210 enable-method = "psci"; 211 capacity-dmips-mhz = <1024>; 212 dynamic-power-coefficient = <421>; 213 next-level-cache = <&L2_700>; 214 qcom,freq-domain = <&cpufreq_hw 2>; 215 operating-points-v2 = <&cpu7_opp_table>; 216 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 217 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 218 power-domains = <&CPU_PD7>; 219 power-domain-names = "psci"; 220 #cooling-cells = <2>; 221 L2_700: l2-cache { 222 compatible = "cache"; 223 cache-level = <2>; 224 next-level-cache = <&L3_0>; 225 }; 226 }; 227 228 cpu-map { 229 cluster0 { 230 core0 { 231 cpu = <&CPU0>; 232 }; 233 234 core1 { 235 cpu = <&CPU1>; 236 }; 237 238 core2 { 239 cpu = <&CPU2>; 240 }; 241 242 core3 { 243 cpu = <&CPU3>; 244 }; 245 246 core4 { 247 cpu = <&CPU4>; 248 }; 249 250 core5 { 251 cpu = <&CPU5>; 252 }; 253 254 core6 { 255 cpu = <&CPU6>; 256 }; 257 258 core7 { 259 cpu = <&CPU7>; 260 }; 261 }; 262 }; 263 264 idle-states { 265 entry-method = "psci"; 266 267 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "little-rail-power-collapse"; 270 arm,psci-suspend-param = <0x40000004>; 271 entry-latency-us = <355>; 272 exit-latency-us = <909>; 273 min-residency-us = <3934>; 274 local-timer-stop; 275 }; 276 277 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 278 compatible = "arm,idle-state"; 279 idle-state-name = "big-rail-power-collapse"; 280 arm,psci-suspend-param = <0x40000004>; 281 entry-latency-us = <241>; 282 exit-latency-us = <1461>; 283 min-residency-us = <4488>; 284 local-timer-stop; 285 }; 286 }; 287 288 domain-idle-states { 289 CLUSTER_SLEEP_0: cluster-sleep-0 { 290 compatible = "domain-idle-state"; 291 idle-state-name = "cluster-power-collapse"; 292 arm,psci-suspend-param = <0x4100c244>; 293 entry-latency-us = <3263>; 294 exit-latency-us = <6562>; 295 min-residency-us = <9987>; 296 local-timer-stop; 297 }; 298 }; 299 }; 300 301 cpu0_opp_table: opp-table-cpu0 { 302 compatible = "operating-points-v2"; 303 opp-shared; 304 305 cpu0_opp1: opp-300000000 { 306 opp-hz = /bits/ 64 <300000000>; 307 opp-peak-kBps = <800000 9600000>; 308 }; 309 310 cpu0_opp2: opp-403200000 { 311 opp-hz = /bits/ 64 <403200000>; 312 opp-peak-kBps = <800000 9600000>; 313 }; 314 315 cpu0_opp3: opp-499200000 { 316 opp-hz = /bits/ 64 <499200000>; 317 opp-peak-kBps = <800000 12902400>; 318 }; 319 320 cpu0_opp4: opp-576000000 { 321 opp-hz = /bits/ 64 <576000000>; 322 opp-peak-kBps = <800000 12902400>; 323 }; 324 325 cpu0_opp5: opp-672000000 { 326 opp-hz = /bits/ 64 <672000000>; 327 opp-peak-kBps = <800000 15974400>; 328 }; 329 330 cpu0_opp6: opp-768000000 { 331 opp-hz = /bits/ 64 <768000000>; 332 opp-peak-kBps = <1804000 19660800>; 333 }; 334 335 cpu0_opp7: opp-844800000 { 336 opp-hz = /bits/ 64 <844800000>; 337 opp-peak-kBps = <1804000 19660800>; 338 }; 339 340 cpu0_opp8: opp-940800000 { 341 opp-hz = /bits/ 64 <940800000>; 342 opp-peak-kBps = <1804000 22732800>; 343 }; 344 345 cpu0_opp9: opp-1036800000 { 346 opp-hz = /bits/ 64 <1036800000>; 347 opp-peak-kBps = <1804000 22732800>; 348 }; 349 350 cpu0_opp10: opp-1113600000 { 351 opp-hz = /bits/ 64 <1113600000>; 352 opp-peak-kBps = <2188000 25804800>; 353 }; 354 355 cpu0_opp11: opp-1209600000 { 356 opp-hz = /bits/ 64 <1209600000>; 357 opp-peak-kBps = <2188000 31948800>; 358 }; 359 360 cpu0_opp12: opp-1305600000 { 361 opp-hz = /bits/ 64 <1305600000>; 362 opp-peak-kBps = <3072000 31948800>; 363 }; 364 365 cpu0_opp13: opp-1382400000 { 366 opp-hz = /bits/ 64 <1382400000>; 367 opp-peak-kBps = <3072000 31948800>; 368 }; 369 370 cpu0_opp14: opp-1478400000 { 371 opp-hz = /bits/ 64 <1478400000>; 372 opp-peak-kBps = <3072000 31948800>; 373 }; 374 375 cpu0_opp15: opp-1555200000 { 376 opp-hz = /bits/ 64 <1555200000>; 377 opp-peak-kBps = <3072000 40550400>; 378 }; 379 380 cpu0_opp16: opp-1632000000 { 381 opp-hz = /bits/ 64 <1632000000>; 382 opp-peak-kBps = <3072000 40550400>; 383 }; 384 385 cpu0_opp17: opp-1708800000 { 386 opp-hz = /bits/ 64 <1708800000>; 387 opp-peak-kBps = <3072000 43008000>; 388 }; 389 390 cpu0_opp18: opp-1785600000 { 391 opp-hz = /bits/ 64 <1785600000>; 392 opp-peak-kBps = <3072000 43008000>; 393 }; 394 }; 395 396 cpu4_opp_table: opp-table-cpu4 { 397 compatible = "operating-points-v2"; 398 opp-shared; 399 400 cpu4_opp1: opp-710400000 { 401 opp-hz = /bits/ 64 <710400000>; 402 opp-peak-kBps = <1804000 15974400>; 403 }; 404 405 cpu4_opp2: opp-825600000 { 406 opp-hz = /bits/ 64 <825600000>; 407 opp-peak-kBps = <2188000 19660800>; 408 }; 409 410 cpu4_opp3: opp-940800000 { 411 opp-hz = /bits/ 64 <940800000>; 412 opp-peak-kBps = <2188000 22732800>; 413 }; 414 415 cpu4_opp4: opp-1056000000 { 416 opp-hz = /bits/ 64 <1056000000>; 417 opp-peak-kBps = <3072000 25804800>; 418 }; 419 420 cpu4_opp5: opp-1171200000 { 421 opp-hz = /bits/ 64 <1171200000>; 422 opp-peak-kBps = <3072000 31948800>; 423 }; 424 425 cpu4_opp6: opp-1286400000 { 426 opp-hz = /bits/ 64 <1286400000>; 427 opp-peak-kBps = <4068000 31948800>; 428 }; 429 430 cpu4_opp7: opp-1401600000 { 431 opp-hz = /bits/ 64 <1401600000>; 432 opp-peak-kBps = <4068000 31948800>; 433 }; 434 435 cpu4_opp8: opp-1497600000 { 436 opp-hz = /bits/ 64 <1497600000>; 437 opp-peak-kBps = <4068000 40550400>; 438 }; 439 440 cpu4_opp9: opp-1612800000 { 441 opp-hz = /bits/ 64 <1612800000>; 442 opp-peak-kBps = <4068000 40550400>; 443 }; 444 445 cpu4_opp10: opp-1708800000 { 446 opp-hz = /bits/ 64 <1708800000>; 447 opp-peak-kBps = <4068000 43008000>; 448 }; 449 450 cpu4_opp11: opp-1804800000 { 451 opp-hz = /bits/ 64 <1804800000>; 452 opp-peak-kBps = <6220000 43008000>; 453 }; 454 455 cpu4_opp12: opp-1920000000 { 456 opp-hz = /bits/ 64 <1920000000>; 457 opp-peak-kBps = <6220000 49152000>; 458 }; 459 460 cpu4_opp13: opp-2016000000 { 461 opp-hz = /bits/ 64 <2016000000>; 462 opp-peak-kBps = <7216000 49152000>; 463 }; 464 465 cpu4_opp14: opp-2131200000 { 466 opp-hz = /bits/ 64 <2131200000>; 467 opp-peak-kBps = <8368000 49152000>; 468 }; 469 470 cpu4_opp15: opp-2227200000 { 471 opp-hz = /bits/ 64 <2227200000>; 472 opp-peak-kBps = <8368000 51609600>; 473 }; 474 475 cpu4_opp16: opp-2323200000 { 476 opp-hz = /bits/ 64 <2323200000>; 477 opp-peak-kBps = <8368000 51609600>; 478 }; 479 480 cpu4_opp17: opp-2419200000 { 481 opp-hz = /bits/ 64 <2419200000>; 482 opp-peak-kBps = <8368000 51609600>; 483 }; 484 }; 485 486 cpu7_opp_table: opp-table-cpu7 { 487 compatible = "operating-points-v2"; 488 opp-shared; 489 490 cpu7_opp1: opp-825600000 { 491 opp-hz = /bits/ 64 <825600000>; 492 opp-peak-kBps = <2188000 19660800>; 493 }; 494 495 cpu7_opp2: opp-940800000 { 496 opp-hz = /bits/ 64 <940800000>; 497 opp-peak-kBps = <2188000 22732800>; 498 }; 499 500 cpu7_opp3: opp-1056000000 { 501 opp-hz = /bits/ 64 <1056000000>; 502 opp-peak-kBps = <3072000 25804800>; 503 }; 504 505 cpu7_opp4: opp-1171200000 { 506 opp-hz = /bits/ 64 <1171200000>; 507 opp-peak-kBps = <3072000 31948800>; 508 }; 509 510 cpu7_opp5: opp-1286400000 { 511 opp-hz = /bits/ 64 <1286400000>; 512 opp-peak-kBps = <4068000 31948800>; 513 }; 514 515 cpu7_opp6: opp-1401600000 { 516 opp-hz = /bits/ 64 <1401600000>; 517 opp-peak-kBps = <4068000 31948800>; 518 }; 519 520 cpu7_opp7: opp-1497600000 { 521 opp-hz = /bits/ 64 <1497600000>; 522 opp-peak-kBps = <4068000 40550400>; 523 }; 524 525 cpu7_opp8: opp-1612800000 { 526 opp-hz = /bits/ 64 <1612800000>; 527 opp-peak-kBps = <4068000 40550400>; 528 }; 529 530 cpu7_opp9: opp-1708800000 { 531 opp-hz = /bits/ 64 <1708800000>; 532 opp-peak-kBps = <4068000 43008000>; 533 }; 534 535 cpu7_opp10: opp-1804800000 { 536 opp-hz = /bits/ 64 <1804800000>; 537 opp-peak-kBps = <6220000 43008000>; 538 }; 539 540 cpu7_opp11: opp-1920000000 { 541 opp-hz = /bits/ 64 <1920000000>; 542 opp-peak-kBps = <6220000 49152000>; 543 }; 544 545 cpu7_opp12: opp-2016000000 { 546 opp-hz = /bits/ 64 <2016000000>; 547 opp-peak-kBps = <7216000 49152000>; 548 }; 549 550 cpu7_opp13: opp-2131200000 { 551 opp-hz = /bits/ 64 <2131200000>; 552 opp-peak-kBps = <8368000 49152000>; 553 }; 554 555 cpu7_opp14: opp-2227200000 { 556 opp-hz = /bits/ 64 <2227200000>; 557 opp-peak-kBps = <8368000 51609600>; 558 }; 559 560 cpu7_opp15: opp-2323200000 { 561 opp-hz = /bits/ 64 <2323200000>; 562 opp-peak-kBps = <8368000 51609600>; 563 }; 564 565 cpu7_opp16: opp-2419200000 { 566 opp-hz = /bits/ 64 <2419200000>; 567 opp-peak-kBps = <8368000 51609600>; 568 }; 569 570 cpu7_opp17: opp-2534400000 { 571 opp-hz = /bits/ 64 <2534400000>; 572 opp-peak-kBps = <8368000 51609600>; 573 }; 574 575 cpu7_opp18: opp-2649600000 { 576 opp-hz = /bits/ 64 <2649600000>; 577 opp-peak-kBps = <8368000 51609600>; 578 }; 579 580 cpu7_opp19: opp-2745600000 { 581 opp-hz = /bits/ 64 <2745600000>; 582 opp-peak-kBps = <8368000 51609600>; 583 }; 584 585 cpu7_opp20: opp-2841600000 { 586 opp-hz = /bits/ 64 <2841600000>; 587 opp-peak-kBps = <8368000 51609600>; 588 }; 589 }; 590 591 firmware { 592 scm: scm { 593 compatible = "qcom,scm-sm8150", "qcom,scm"; 594 #reset-cells = <1>; 595 }; 596 }; 597 598 memory@80000000 { 599 device_type = "memory"; 600 /* We expect the bootloader to fill in the size */ 601 reg = <0x0 0x80000000 0x0 0x0>; 602 }; 603 604 pmu { 605 compatible = "arm,armv8-pmuv3"; 606 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 607 }; 608 609 psci { 610 compatible = "arm,psci-1.0"; 611 method = "smc"; 612 613 CPU_PD0: power-domain-cpu0 { 614 #power-domain-cells = <0>; 615 power-domains = <&CLUSTER_PD>; 616 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 617 }; 618 619 CPU_PD1: power-domain-cpu1 { 620 #power-domain-cells = <0>; 621 power-domains = <&CLUSTER_PD>; 622 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 623 }; 624 625 CPU_PD2: power-domain-cpu2 { 626 #power-domain-cells = <0>; 627 power-domains = <&CLUSTER_PD>; 628 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 629 }; 630 631 CPU_PD3: power-domain-cpu3 { 632 #power-domain-cells = <0>; 633 power-domains = <&CLUSTER_PD>; 634 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 635 }; 636 637 CPU_PD4: power-domain-cpu4 { 638 #power-domain-cells = <0>; 639 power-domains = <&CLUSTER_PD>; 640 domain-idle-states = <&BIG_CPU_SLEEP_0>; 641 }; 642 643 CPU_PD5: power-domain-cpu5 { 644 #power-domain-cells = <0>; 645 power-domains = <&CLUSTER_PD>; 646 domain-idle-states = <&BIG_CPU_SLEEP_0>; 647 }; 648 649 CPU_PD6: power-domain-cpu6 { 650 #power-domain-cells = <0>; 651 power-domains = <&CLUSTER_PD>; 652 domain-idle-states = <&BIG_CPU_SLEEP_0>; 653 }; 654 655 CPU_PD7: power-domain-cpu7 { 656 #power-domain-cells = <0>; 657 power-domains = <&CLUSTER_PD>; 658 domain-idle-states = <&BIG_CPU_SLEEP_0>; 659 }; 660 661 CLUSTER_PD: power-domain-cpu-cluster0 { 662 #power-domain-cells = <0>; 663 domain-idle-states = <&CLUSTER_SLEEP_0>; 664 }; 665 }; 666 667 reserved-memory { 668 #address-cells = <2>; 669 #size-cells = <2>; 670 ranges; 671 672 hyp_mem: memory@85700000 { 673 reg = <0x0 0x85700000 0x0 0x600000>; 674 no-map; 675 }; 676 677 xbl_mem: memory@85d00000 { 678 reg = <0x0 0x85d00000 0x0 0x140000>; 679 no-map; 680 }; 681 682 aop_mem: memory@85f00000 { 683 reg = <0x0 0x85f00000 0x0 0x20000>; 684 no-map; 685 }; 686 687 aop_cmd_db: memory@85f20000 { 688 compatible = "qcom,cmd-db"; 689 reg = <0x0 0x85f20000 0x0 0x20000>; 690 no-map; 691 }; 692 693 smem_mem: memory@86000000 { 694 reg = <0x0 0x86000000 0x0 0x200000>; 695 no-map; 696 }; 697 698 tz_mem: memory@86200000 { 699 reg = <0x0 0x86200000 0x0 0x3900000>; 700 no-map; 701 }; 702 703 rmtfs_mem: memory@89b00000 { 704 compatible = "qcom,rmtfs-mem"; 705 reg = <0x0 0x89b00000 0x0 0x200000>; 706 no-map; 707 708 qcom,client-id = <1>; 709 qcom,vmid = <15>; 710 }; 711 712 camera_mem: memory@8b700000 { 713 reg = <0x0 0x8b700000 0x0 0x500000>; 714 no-map; 715 }; 716 717 wlan_mem: memory@8bc00000 { 718 reg = <0x0 0x8bc00000 0x0 0x180000>; 719 no-map; 720 }; 721 722 npu_mem: memory@8bd80000 { 723 reg = <0x0 0x8bd80000 0x0 0x80000>; 724 no-map; 725 }; 726 727 adsp_mem: memory@8be00000 { 728 reg = <0x0 0x8be00000 0x0 0x1a00000>; 729 no-map; 730 }; 731 732 mpss_mem: memory@8d800000 { 733 reg = <0x0 0x8d800000 0x0 0x9600000>; 734 no-map; 735 }; 736 737 venus_mem: memory@96e00000 { 738 reg = <0x0 0x96e00000 0x0 0x500000>; 739 no-map; 740 }; 741 742 slpi_mem: memory@97300000 { 743 reg = <0x0 0x97300000 0x0 0x1400000>; 744 no-map; 745 }; 746 747 ipa_fw_mem: memory@98700000 { 748 reg = <0x0 0x98700000 0x0 0x10000>; 749 no-map; 750 }; 751 752 ipa_gsi_mem: memory@98710000 { 753 reg = <0x0 0x98710000 0x0 0x5000>; 754 no-map; 755 }; 756 757 gpu_mem: memory@98715000 { 758 reg = <0x0 0x98715000 0x0 0x2000>; 759 no-map; 760 }; 761 762 spss_mem: memory@98800000 { 763 reg = <0x0 0x98800000 0x0 0x100000>; 764 no-map; 765 }; 766 767 cdsp_mem: memory@98900000 { 768 reg = <0x0 0x98900000 0x0 0x1400000>; 769 no-map; 770 }; 771 772 qseecom_mem: memory@9e400000 { 773 reg = <0x0 0x9e400000 0x0 0x1400000>; 774 no-map; 775 }; 776 }; 777 778 smem { 779 compatible = "qcom,smem"; 780 memory-region = <&smem_mem>; 781 hwlocks = <&tcsr_mutex 3>; 782 }; 783 784 smp2p-cdsp { 785 compatible = "qcom,smp2p"; 786 qcom,smem = <94>, <432>; 787 788 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 789 790 mboxes = <&apss_shared 6>; 791 792 qcom,local-pid = <0>; 793 qcom,remote-pid = <5>; 794 795 cdsp_smp2p_out: master-kernel { 796 qcom,entry-name = "master-kernel"; 797 #qcom,smem-state-cells = <1>; 798 }; 799 800 cdsp_smp2p_in: slave-kernel { 801 qcom,entry-name = "slave-kernel"; 802 803 interrupt-controller; 804 #interrupt-cells = <2>; 805 }; 806 }; 807 808 smp2p-lpass { 809 compatible = "qcom,smp2p"; 810 qcom,smem = <443>, <429>; 811 812 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 813 814 mboxes = <&apss_shared 10>; 815 816 qcom,local-pid = <0>; 817 qcom,remote-pid = <2>; 818 819 adsp_smp2p_out: master-kernel { 820 qcom,entry-name = "master-kernel"; 821 #qcom,smem-state-cells = <1>; 822 }; 823 824 adsp_smp2p_in: slave-kernel { 825 qcom,entry-name = "slave-kernel"; 826 827 interrupt-controller; 828 #interrupt-cells = <2>; 829 }; 830 }; 831 832 smp2p-mpss { 833 compatible = "qcom,smp2p"; 834 qcom,smem = <435>, <428>; 835 836 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 837 838 mboxes = <&apss_shared 14>; 839 840 qcom,local-pid = <0>; 841 qcom,remote-pid = <1>; 842 843 modem_smp2p_out: master-kernel { 844 qcom,entry-name = "master-kernel"; 845 #qcom,smem-state-cells = <1>; 846 }; 847 848 modem_smp2p_in: slave-kernel { 849 qcom,entry-name = "slave-kernel"; 850 851 interrupt-controller; 852 #interrupt-cells = <2>; 853 }; 854 }; 855 856 smp2p-slpi { 857 compatible = "qcom,smp2p"; 858 qcom,smem = <481>, <430>; 859 860 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 861 862 mboxes = <&apss_shared 26>; 863 864 qcom,local-pid = <0>; 865 qcom,remote-pid = <3>; 866 867 slpi_smp2p_out: master-kernel { 868 qcom,entry-name = "master-kernel"; 869 #qcom,smem-state-cells = <1>; 870 }; 871 872 slpi_smp2p_in: slave-kernel { 873 qcom,entry-name = "slave-kernel"; 874 875 interrupt-controller; 876 #interrupt-cells = <2>; 877 }; 878 }; 879 880 soc: soc@0 { 881 #address-cells = <2>; 882 #size-cells = <2>; 883 ranges = <0 0 0 0 0x10 0>; 884 dma-ranges = <0 0 0 0 0x10 0>; 885 compatible = "simple-bus"; 886 887 gcc: clock-controller@100000 { 888 compatible = "qcom,gcc-sm8150"; 889 reg = <0x0 0x00100000 0x0 0x1f0000>; 890 #clock-cells = <1>; 891 #reset-cells = <1>; 892 #power-domain-cells = <1>; 893 clock-names = "bi_tcxo", 894 "sleep_clk"; 895 clocks = <&rpmhcc RPMH_CXO_CLK>, 896 <&sleep_clk>; 897 }; 898 899 gpi_dma0: dma-controller@800000 { 900 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 901 reg = <0 0x00800000 0 0x60000>; 902 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 915 dma-channels = <13>; 916 dma-channel-mask = <0xfa>; 917 iommus = <&apps_smmu 0x00d6 0x0>; 918 #dma-cells = <3>; 919 status = "disabled"; 920 }; 921 922 ethernet: ethernet@20000 { 923 compatible = "qcom,sm8150-ethqos"; 924 reg = <0x0 0x00020000 0x0 0x10000>, 925 <0x0 0x00036000 0x0 0x100>; 926 reg-names = "stmmaceth", "rgmii"; 927 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 928 clocks = <&gcc GCC_EMAC_AXI_CLK>, 929 <&gcc GCC_EMAC_SLV_AHB_CLK>, 930 <&gcc GCC_EMAC_PTP_CLK>, 931 <&gcc GCC_EMAC_RGMII_CLK>; 932 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 934 interrupt-names = "macirq", "eth_lpi"; 935 936 power-domains = <&gcc EMAC_GDSC>; 937 resets = <&gcc GCC_EMAC_BCR>; 938 939 iommus = <&apps_smmu 0x3c0 0x0>; 940 941 snps,tso; 942 rx-fifo-depth = <4096>; 943 tx-fifo-depth = <4096>; 944 945 status = "disabled"; 946 }; 947 948 949 qupv3_id_0: geniqup@8c0000 { 950 compatible = "qcom,geni-se-qup"; 951 reg = <0x0 0x008c0000 0x0 0x6000>; 952 clock-names = "m-ahb", "s-ahb"; 953 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 954 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 955 iommus = <&apps_smmu 0xc3 0x0>; 956 #address-cells = <2>; 957 #size-cells = <2>; 958 ranges; 959 status = "disabled"; 960 961 i2c0: i2c@880000 { 962 compatible = "qcom,geni-i2c"; 963 reg = <0 0x00880000 0 0x4000>; 964 clock-names = "se"; 965 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 966 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 967 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 968 dma-names = "tx", "rx"; 969 pinctrl-names = "default"; 970 pinctrl-0 = <&qup_i2c0_default>; 971 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 status = "disabled"; 975 }; 976 977 spi0: spi@880000 { 978 compatible = "qcom,geni-spi"; 979 reg = <0 0x00880000 0 0x4000>; 980 reg-names = "se"; 981 clock-names = "se"; 982 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 983 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 984 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 985 dma-names = "tx", "rx"; 986 pinctrl-names = "default"; 987 pinctrl-0 = <&qup_spi0_default>; 988 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 989 spi-max-frequency = <50000000>; 990 #address-cells = <1>; 991 #size-cells = <0>; 992 status = "disabled"; 993 }; 994 995 i2c1: i2c@884000 { 996 compatible = "qcom,geni-i2c"; 997 reg = <0 0x00884000 0 0x4000>; 998 clock-names = "se"; 999 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1000 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1001 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1002 dma-names = "tx", "rx"; 1003 pinctrl-names = "default"; 1004 pinctrl-0 = <&qup_i2c1_default>; 1005 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 status = "disabled"; 1009 }; 1010 1011 spi1: spi@884000 { 1012 compatible = "qcom,geni-spi"; 1013 reg = <0 0x00884000 0 0x4000>; 1014 reg-names = "se"; 1015 clock-names = "se"; 1016 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1017 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1018 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1019 dma-names = "tx", "rx"; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&qup_spi1_default>; 1022 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1023 spi-max-frequency = <50000000>; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 status = "disabled"; 1027 }; 1028 1029 i2c2: i2c@888000 { 1030 compatible = "qcom,geni-i2c"; 1031 reg = <0 0x00888000 0 0x4000>; 1032 clock-names = "se"; 1033 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1034 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1035 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1036 dma-names = "tx", "rx"; 1037 pinctrl-names = "default"; 1038 pinctrl-0 = <&qup_i2c2_default>; 1039 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 status = "disabled"; 1043 }; 1044 1045 spi2: spi@888000 { 1046 compatible = "qcom,geni-spi"; 1047 reg = <0 0x00888000 0 0x4000>; 1048 reg-names = "se"; 1049 clock-names = "se"; 1050 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1051 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1052 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1053 dma-names = "tx", "rx"; 1054 pinctrl-names = "default"; 1055 pinctrl-0 = <&qup_spi2_default>; 1056 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1057 spi-max-frequency = <50000000>; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 status = "disabled"; 1061 }; 1062 1063 i2c3: i2c@88c000 { 1064 compatible = "qcom,geni-i2c"; 1065 reg = <0 0x0088c000 0 0x4000>; 1066 clock-names = "se"; 1067 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1068 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1069 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1070 dma-names = "tx", "rx"; 1071 pinctrl-names = "default"; 1072 pinctrl-0 = <&qup_i2c3_default>; 1073 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 status = "disabled"; 1077 }; 1078 1079 spi3: spi@88c000 { 1080 compatible = "qcom,geni-spi"; 1081 reg = <0 0x0088c000 0 0x4000>; 1082 reg-names = "se"; 1083 clock-names = "se"; 1084 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1085 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1086 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1087 dma-names = "tx", "rx"; 1088 pinctrl-names = "default"; 1089 pinctrl-0 = <&qup_spi3_default>; 1090 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1091 spi-max-frequency = <50000000>; 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 status = "disabled"; 1095 }; 1096 1097 i2c4: i2c@890000 { 1098 compatible = "qcom,geni-i2c"; 1099 reg = <0 0x00890000 0 0x4000>; 1100 clock-names = "se"; 1101 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1102 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1103 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1104 dma-names = "tx", "rx"; 1105 pinctrl-names = "default"; 1106 pinctrl-0 = <&qup_i2c4_default>; 1107 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 status = "disabled"; 1111 }; 1112 1113 spi4: spi@890000 { 1114 compatible = "qcom,geni-spi"; 1115 reg = <0 0x00890000 0 0x4000>; 1116 reg-names = "se"; 1117 clock-names = "se"; 1118 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1119 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1120 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1121 dma-names = "tx", "rx"; 1122 pinctrl-names = "default"; 1123 pinctrl-0 = <&qup_spi4_default>; 1124 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1125 spi-max-frequency = <50000000>; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 status = "disabled"; 1129 }; 1130 1131 i2c5: i2c@894000 { 1132 compatible = "qcom,geni-i2c"; 1133 reg = <0 0x00894000 0 0x4000>; 1134 clock-names = "se"; 1135 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1136 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1137 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1138 dma-names = "tx", "rx"; 1139 pinctrl-names = "default"; 1140 pinctrl-0 = <&qup_i2c5_default>; 1141 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 status = "disabled"; 1145 }; 1146 1147 spi5: spi@894000 { 1148 compatible = "qcom,geni-spi"; 1149 reg = <0 0x00894000 0 0x4000>; 1150 reg-names = "se"; 1151 clock-names = "se"; 1152 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1153 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1154 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1155 dma-names = "tx", "rx"; 1156 pinctrl-names = "default"; 1157 pinctrl-0 = <&qup_spi5_default>; 1158 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1159 spi-max-frequency = <50000000>; 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 status = "disabled"; 1163 }; 1164 1165 i2c6: i2c@898000 { 1166 compatible = "qcom,geni-i2c"; 1167 reg = <0 0x00898000 0 0x4000>; 1168 clock-names = "se"; 1169 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1170 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1171 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1172 dma-names = "tx", "rx"; 1173 pinctrl-names = "default"; 1174 pinctrl-0 = <&qup_i2c6_default>; 1175 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 status = "disabled"; 1179 }; 1180 1181 spi6: spi@898000 { 1182 compatible = "qcom,geni-spi"; 1183 reg = <0 0x00898000 0 0x4000>; 1184 reg-names = "se"; 1185 clock-names = "se"; 1186 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1187 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1188 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1189 dma-names = "tx", "rx"; 1190 pinctrl-names = "default"; 1191 pinctrl-0 = <&qup_spi6_default>; 1192 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1193 spi-max-frequency = <50000000>; 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 status = "disabled"; 1197 }; 1198 1199 i2c7: i2c@89c000 { 1200 compatible = "qcom,geni-i2c"; 1201 reg = <0 0x0089c000 0 0x4000>; 1202 clock-names = "se"; 1203 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1204 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1205 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1206 dma-names = "tx", "rx"; 1207 pinctrl-names = "default"; 1208 pinctrl-0 = <&qup_i2c7_default>; 1209 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1210 #address-cells = <1>; 1211 #size-cells = <0>; 1212 status = "disabled"; 1213 }; 1214 1215 spi7: spi@89c000 { 1216 compatible = "qcom,geni-spi"; 1217 reg = <0 0x0089c000 0 0x4000>; 1218 reg-names = "se"; 1219 clock-names = "se"; 1220 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1221 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1222 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1223 dma-names = "tx", "rx"; 1224 pinctrl-names = "default"; 1225 pinctrl-0 = <&qup_spi7_default>; 1226 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1227 spi-max-frequency = <50000000>; 1228 #address-cells = <1>; 1229 #size-cells = <0>; 1230 status = "disabled"; 1231 }; 1232 }; 1233 1234 gpi_dma1: dma-controller@a00000 { 1235 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1236 reg = <0 0x00a00000 0 0x60000>; 1237 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1250 dma-channels = <13>; 1251 dma-channel-mask = <0xfa>; 1252 iommus = <&apps_smmu 0x0616 0x0>; 1253 #dma-cells = <3>; 1254 status = "disabled"; 1255 }; 1256 1257 qupv3_id_1: geniqup@ac0000 { 1258 compatible = "qcom,geni-se-qup"; 1259 reg = <0x0 0x00ac0000 0x0 0x6000>; 1260 clock-names = "m-ahb", "s-ahb"; 1261 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1262 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1263 iommus = <&apps_smmu 0x603 0x0>; 1264 #address-cells = <2>; 1265 #size-cells = <2>; 1266 ranges; 1267 status = "disabled"; 1268 1269 i2c8: i2c@a80000 { 1270 compatible = "qcom,geni-i2c"; 1271 reg = <0 0x00a80000 0 0x4000>; 1272 clock-names = "se"; 1273 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1274 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1275 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1276 dma-names = "tx", "rx"; 1277 pinctrl-names = "default"; 1278 pinctrl-0 = <&qup_i2c8_default>; 1279 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 status = "disabled"; 1283 }; 1284 1285 spi8: spi@a80000 { 1286 compatible = "qcom,geni-spi"; 1287 reg = <0 0x00a80000 0 0x4000>; 1288 reg-names = "se"; 1289 clock-names = "se"; 1290 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1291 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1292 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1293 dma-names = "tx", "rx"; 1294 pinctrl-names = "default"; 1295 pinctrl-0 = <&qup_spi8_default>; 1296 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1297 spi-max-frequency = <50000000>; 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 status = "disabled"; 1301 }; 1302 1303 i2c9: i2c@a84000 { 1304 compatible = "qcom,geni-i2c"; 1305 reg = <0 0x00a84000 0 0x4000>; 1306 clock-names = "se"; 1307 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1308 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1309 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1310 dma-names = "tx", "rx"; 1311 pinctrl-names = "default"; 1312 pinctrl-0 = <&qup_i2c9_default>; 1313 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 status = "disabled"; 1317 }; 1318 1319 spi9: spi@a84000 { 1320 compatible = "qcom,geni-spi"; 1321 reg = <0 0x00a84000 0 0x4000>; 1322 reg-names = "se"; 1323 clock-names = "se"; 1324 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1325 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1326 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1327 dma-names = "tx", "rx"; 1328 pinctrl-names = "default"; 1329 pinctrl-0 = <&qup_spi9_default>; 1330 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1331 spi-max-frequency = <50000000>; 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 status = "disabled"; 1335 }; 1336 1337 i2c10: i2c@a88000 { 1338 compatible = "qcom,geni-i2c"; 1339 reg = <0 0x00a88000 0 0x4000>; 1340 clock-names = "se"; 1341 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1342 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1343 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1344 dma-names = "tx", "rx"; 1345 pinctrl-names = "default"; 1346 pinctrl-0 = <&qup_i2c10_default>; 1347 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 status = "disabled"; 1351 }; 1352 1353 spi10: spi@a88000 { 1354 compatible = "qcom,geni-spi"; 1355 reg = <0 0x00a88000 0 0x4000>; 1356 reg-names = "se"; 1357 clock-names = "se"; 1358 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1359 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1360 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1361 dma-names = "tx", "rx"; 1362 pinctrl-names = "default"; 1363 pinctrl-0 = <&qup_spi10_default>; 1364 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1365 spi-max-frequency = <50000000>; 1366 #address-cells = <1>; 1367 #size-cells = <0>; 1368 status = "disabled"; 1369 }; 1370 1371 i2c11: i2c@a8c000 { 1372 compatible = "qcom,geni-i2c"; 1373 reg = <0 0x00a8c000 0 0x4000>; 1374 clock-names = "se"; 1375 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1376 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1377 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1378 dma-names = "tx", "rx"; 1379 pinctrl-names = "default"; 1380 pinctrl-0 = <&qup_i2c11_default>; 1381 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 status = "disabled"; 1385 }; 1386 1387 spi11: spi@a8c000 { 1388 compatible = "qcom,geni-spi"; 1389 reg = <0 0x00a8c000 0 0x4000>; 1390 reg-names = "se"; 1391 clock-names = "se"; 1392 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1393 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1394 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1395 dma-names = "tx", "rx"; 1396 pinctrl-names = "default"; 1397 pinctrl-0 = <&qup_spi11_default>; 1398 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1399 spi-max-frequency = <50000000>; 1400 #address-cells = <1>; 1401 #size-cells = <0>; 1402 status = "disabled"; 1403 }; 1404 1405 uart2: serial@a90000 { 1406 compatible = "qcom,geni-debug-uart"; 1407 reg = <0x0 0x00a90000 0x0 0x4000>; 1408 clock-names = "se"; 1409 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1410 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1411 status = "disabled"; 1412 }; 1413 1414 i2c12: i2c@a90000 { 1415 compatible = "qcom,geni-i2c"; 1416 reg = <0 0x00a90000 0 0x4000>; 1417 clock-names = "se"; 1418 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1419 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1420 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1421 dma-names = "tx", "rx"; 1422 pinctrl-names = "default"; 1423 pinctrl-0 = <&qup_i2c12_default>; 1424 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1425 #address-cells = <1>; 1426 #size-cells = <0>; 1427 status = "disabled"; 1428 }; 1429 1430 spi12: spi@a90000 { 1431 compatible = "qcom,geni-spi"; 1432 reg = <0 0x00a90000 0 0x4000>; 1433 reg-names = "se"; 1434 clock-names = "se"; 1435 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1436 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1437 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1438 dma-names = "tx", "rx"; 1439 pinctrl-names = "default"; 1440 pinctrl-0 = <&qup_spi12_default>; 1441 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1442 spi-max-frequency = <50000000>; 1443 #address-cells = <1>; 1444 #size-cells = <0>; 1445 status = "disabled"; 1446 }; 1447 1448 i2c16: i2c@94000 { 1449 compatible = "qcom,geni-i2c"; 1450 reg = <0 0x00094000 0 0x4000>; 1451 clock-names = "se"; 1452 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1453 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1454 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1455 dma-names = "tx", "rx"; 1456 pinctrl-names = "default"; 1457 pinctrl-0 = <&qup_i2c16_default>; 1458 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1459 #address-cells = <1>; 1460 #size-cells = <0>; 1461 status = "disabled"; 1462 }; 1463 1464 spi16: spi@a94000 { 1465 compatible = "qcom,geni-spi"; 1466 reg = <0 0x00a94000 0 0x4000>; 1467 reg-names = "se"; 1468 clock-names = "se"; 1469 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1470 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1471 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1472 dma-names = "tx", "rx"; 1473 pinctrl-names = "default"; 1474 pinctrl-0 = <&qup_spi16_default>; 1475 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1476 spi-max-frequency = <50000000>; 1477 #address-cells = <1>; 1478 #size-cells = <0>; 1479 status = "disabled"; 1480 }; 1481 }; 1482 1483 gpi_dma2: dma-controller@c00000 { 1484 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1485 reg = <0 0x00c00000 0 0x60000>; 1486 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 1499 dma-channels = <13>; 1500 dma-channel-mask = <0xfa>; 1501 iommus = <&apps_smmu 0x07b6 0x0>; 1502 #dma-cells = <3>; 1503 status = "disabled"; 1504 }; 1505 1506 qupv3_id_2: geniqup@cc0000 { 1507 compatible = "qcom,geni-se-qup"; 1508 reg = <0x0 0x00cc0000 0x0 0x6000>; 1509 1510 clock-names = "m-ahb", "s-ahb"; 1511 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1512 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1513 iommus = <&apps_smmu 0x7a3 0x0>; 1514 #address-cells = <2>; 1515 #size-cells = <2>; 1516 ranges; 1517 status = "disabled"; 1518 1519 i2c17: i2c@c80000 { 1520 compatible = "qcom,geni-i2c"; 1521 reg = <0 0x00c80000 0 0x4000>; 1522 clock-names = "se"; 1523 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1524 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1525 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1526 dma-names = "tx", "rx"; 1527 pinctrl-names = "default"; 1528 pinctrl-0 = <&qup_i2c17_default>; 1529 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1530 #address-cells = <1>; 1531 #size-cells = <0>; 1532 status = "disabled"; 1533 }; 1534 1535 spi17: spi@c80000 { 1536 compatible = "qcom,geni-spi"; 1537 reg = <0 0x00c80000 0 0x4000>; 1538 reg-names = "se"; 1539 clock-names = "se"; 1540 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1541 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1542 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1543 dma-names = "tx", "rx"; 1544 pinctrl-names = "default"; 1545 pinctrl-0 = <&qup_spi17_default>; 1546 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1547 spi-max-frequency = <50000000>; 1548 #address-cells = <1>; 1549 #size-cells = <0>; 1550 status = "disabled"; 1551 }; 1552 1553 i2c18: i2c@c84000 { 1554 compatible = "qcom,geni-i2c"; 1555 reg = <0 0x00c84000 0 0x4000>; 1556 clock-names = "se"; 1557 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1558 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1559 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1560 dma-names = "tx", "rx"; 1561 pinctrl-names = "default"; 1562 pinctrl-0 = <&qup_i2c18_default>; 1563 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1564 #address-cells = <1>; 1565 #size-cells = <0>; 1566 status = "disabled"; 1567 }; 1568 1569 spi18: spi@c84000 { 1570 compatible = "qcom,geni-spi"; 1571 reg = <0 0x00c84000 0 0x4000>; 1572 reg-names = "se"; 1573 clock-names = "se"; 1574 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1575 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1576 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1577 dma-names = "tx", "rx"; 1578 pinctrl-names = "default"; 1579 pinctrl-0 = <&qup_spi18_default>; 1580 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1581 spi-max-frequency = <50000000>; 1582 #address-cells = <1>; 1583 #size-cells = <0>; 1584 status = "disabled"; 1585 }; 1586 1587 i2c19: i2c@c88000 { 1588 compatible = "qcom,geni-i2c"; 1589 reg = <0 0x00c88000 0 0x4000>; 1590 clock-names = "se"; 1591 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1592 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1593 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1594 dma-names = "tx", "rx"; 1595 pinctrl-names = "default"; 1596 pinctrl-0 = <&qup_i2c19_default>; 1597 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 status = "disabled"; 1601 }; 1602 1603 spi19: spi@c88000 { 1604 compatible = "qcom,geni-spi"; 1605 reg = <0 0x00c88000 0 0x4000>; 1606 reg-names = "se"; 1607 clock-names = "se"; 1608 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1609 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1610 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1611 dma-names = "tx", "rx"; 1612 pinctrl-names = "default"; 1613 pinctrl-0 = <&qup_spi19_default>; 1614 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1615 spi-max-frequency = <50000000>; 1616 #address-cells = <1>; 1617 #size-cells = <0>; 1618 status = "disabled"; 1619 }; 1620 1621 i2c13: i2c@c8c000 { 1622 compatible = "qcom,geni-i2c"; 1623 reg = <0 0x00c8c000 0 0x4000>; 1624 clock-names = "se"; 1625 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1626 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1627 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1628 dma-names = "tx", "rx"; 1629 pinctrl-names = "default"; 1630 pinctrl-0 = <&qup_i2c13_default>; 1631 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1632 #address-cells = <1>; 1633 #size-cells = <0>; 1634 status = "disabled"; 1635 }; 1636 1637 spi13: spi@c8c000 { 1638 compatible = "qcom,geni-spi"; 1639 reg = <0 0x00c8c000 0 0x4000>; 1640 reg-names = "se"; 1641 clock-names = "se"; 1642 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1643 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1644 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1645 dma-names = "tx", "rx"; 1646 pinctrl-names = "default"; 1647 pinctrl-0 = <&qup_spi13_default>; 1648 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1649 spi-max-frequency = <50000000>; 1650 #address-cells = <1>; 1651 #size-cells = <0>; 1652 status = "disabled"; 1653 }; 1654 1655 i2c14: i2c@c90000 { 1656 compatible = "qcom,geni-i2c"; 1657 reg = <0 0x00c90000 0 0x4000>; 1658 clock-names = "se"; 1659 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1660 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1661 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1662 dma-names = "tx", "rx"; 1663 pinctrl-names = "default"; 1664 pinctrl-0 = <&qup_i2c14_default>; 1665 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1666 #address-cells = <1>; 1667 #size-cells = <0>; 1668 status = "disabled"; 1669 }; 1670 1671 spi14: spi@c90000 { 1672 compatible = "qcom,geni-spi"; 1673 reg = <0 0x00c90000 0 0x4000>; 1674 reg-names = "se"; 1675 clock-names = "se"; 1676 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1677 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1678 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1679 dma-names = "tx", "rx"; 1680 pinctrl-names = "default"; 1681 pinctrl-0 = <&qup_spi14_default>; 1682 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1683 spi-max-frequency = <50000000>; 1684 #address-cells = <1>; 1685 #size-cells = <0>; 1686 status = "disabled"; 1687 }; 1688 1689 i2c15: i2c@c94000 { 1690 compatible = "qcom,geni-i2c"; 1691 reg = <0 0x00c94000 0 0x4000>; 1692 clock-names = "se"; 1693 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1694 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1695 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1696 dma-names = "tx", "rx"; 1697 pinctrl-names = "default"; 1698 pinctrl-0 = <&qup_i2c15_default>; 1699 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1700 #address-cells = <1>; 1701 #size-cells = <0>; 1702 status = "disabled"; 1703 }; 1704 1705 spi15: spi@c94000 { 1706 compatible = "qcom,geni-spi"; 1707 reg = <0 0x00c94000 0 0x4000>; 1708 reg-names = "se"; 1709 clock-names = "se"; 1710 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1711 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1712 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1713 dma-names = "tx", "rx"; 1714 pinctrl-names = "default"; 1715 pinctrl-0 = <&qup_spi15_default>; 1716 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1717 spi-max-frequency = <50000000>; 1718 #address-cells = <1>; 1719 #size-cells = <0>; 1720 status = "disabled"; 1721 }; 1722 }; 1723 1724 config_noc: interconnect@1500000 { 1725 compatible = "qcom,sm8150-config-noc"; 1726 reg = <0 0x01500000 0 0x7400>; 1727 #interconnect-cells = <1>; 1728 qcom,bcm-voters = <&apps_bcm_voter>; 1729 }; 1730 1731 system_noc: interconnect@1620000 { 1732 compatible = "qcom,sm8150-system-noc"; 1733 reg = <0 0x01620000 0 0x19400>; 1734 #interconnect-cells = <1>; 1735 qcom,bcm-voters = <&apps_bcm_voter>; 1736 }; 1737 1738 mc_virt: interconnect@163a000 { 1739 compatible = "qcom,sm8150-mc-virt"; 1740 reg = <0 0x0163a000 0 0x1000>; 1741 #interconnect-cells = <1>; 1742 qcom,bcm-voters = <&apps_bcm_voter>; 1743 }; 1744 1745 aggre1_noc: interconnect@16e0000 { 1746 compatible = "qcom,sm8150-aggre1-noc"; 1747 reg = <0 0x016e0000 0 0xd080>; 1748 #interconnect-cells = <1>; 1749 qcom,bcm-voters = <&apps_bcm_voter>; 1750 }; 1751 1752 aggre2_noc: interconnect@1700000 { 1753 compatible = "qcom,sm8150-aggre2-noc"; 1754 reg = <0 0x01700000 0 0x20000>; 1755 #interconnect-cells = <1>; 1756 qcom,bcm-voters = <&apps_bcm_voter>; 1757 }; 1758 1759 compute_noc: interconnect@1720000 { 1760 compatible = "qcom,sm8150-compute-noc"; 1761 reg = <0 0x01720000 0 0x7000>; 1762 #interconnect-cells = <1>; 1763 qcom,bcm-voters = <&apps_bcm_voter>; 1764 }; 1765 1766 mmss_noc: interconnect@1740000 { 1767 compatible = "qcom,sm8150-mmss-noc"; 1768 reg = <0 0x01740000 0 0x1c100>; 1769 #interconnect-cells = <1>; 1770 qcom,bcm-voters = <&apps_bcm_voter>; 1771 }; 1772 1773 system-cache-controller@9200000 { 1774 compatible = "qcom,sm8150-llcc"; 1775 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 1776 reg-names = "llcc_base", "llcc_broadcast_base"; 1777 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1778 }; 1779 1780 dma@10a2000 { 1781 compatible = "qcom,sm8150-dcc", "qcom,dcc"; 1782 reg = <0x0 0x010a2000 0x0 0x1000>, 1783 <0x0 0x010ad000 0x0 0x3000>; 1784 }; 1785 1786 pcie0: pci@1c00000 { 1787 compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1788 reg = <0 0x01c00000 0 0x3000>, 1789 <0 0x60000000 0 0xf1d>, 1790 <0 0x60000f20 0 0xa8>, 1791 <0 0x60001000 0 0x1000>, 1792 <0 0x60100000 0 0x100000>; 1793 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1794 device_type = "pci"; 1795 linux,pci-domain = <0>; 1796 bus-range = <0x00 0xff>; 1797 num-lanes = <1>; 1798 1799 #address-cells = <3>; 1800 #size-cells = <2>; 1801 1802 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1803 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1804 1805 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1806 interrupt-names = "msi"; 1807 #interrupt-cells = <1>; 1808 interrupt-map-mask = <0 0 0 0x7>; 1809 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1810 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1811 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1812 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1813 1814 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1815 <&gcc GCC_PCIE_0_AUX_CLK>, 1816 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1817 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1818 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1819 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1820 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1821 clock-names = "pipe", 1822 "aux", 1823 "cfg", 1824 "bus_master", 1825 "bus_slave", 1826 "slave_q2a", 1827 "tbu"; 1828 1829 iommus = <&apps_smmu 0x1d80 0x7f>; 1830 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1831 <0x100 &apps_smmu 0x1d81 0x1>; 1832 1833 resets = <&gcc GCC_PCIE_0_BCR>; 1834 reset-names = "pci"; 1835 1836 power-domains = <&gcc PCIE_0_GDSC>; 1837 1838 phys = <&pcie0_lane>; 1839 phy-names = "pciephy"; 1840 1841 perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1842 enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1843 1844 pinctrl-names = "default"; 1845 pinctrl-0 = <&pcie0_default_state>; 1846 1847 status = "disabled"; 1848 }; 1849 1850 pcie0_phy: phy@1c06000 { 1851 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1852 reg = <0 0x01c06000 0 0x1c0>; 1853 #address-cells = <2>; 1854 #size-cells = <2>; 1855 ranges; 1856 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1857 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1858 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1859 clock-names = "aux", "cfg_ahb", "refgen"; 1860 1861 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1862 reset-names = "phy"; 1863 1864 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1865 assigned-clock-rates = <100000000>; 1866 1867 status = "disabled"; 1868 1869 pcie0_lane: phy@1c06200 { 1870 reg = <0 0x01c06200 0 0x170>, /* tx */ 1871 <0 0x01c06400 0 0x200>, /* rx */ 1872 <0 0x01c06800 0 0x1f0>, /* pcs */ 1873 <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1874 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1875 clock-names = "pipe0"; 1876 1877 #phy-cells = <0>; 1878 clock-output-names = "pcie_0_pipe_clk"; 1879 }; 1880 }; 1881 1882 pcie1: pci@1c08000 { 1883 compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1884 reg = <0 0x01c08000 0 0x3000>, 1885 <0 0x40000000 0 0xf1d>, 1886 <0 0x40000f20 0 0xa8>, 1887 <0 0x40001000 0 0x1000>, 1888 <0 0x40100000 0 0x100000>; 1889 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1890 device_type = "pci"; 1891 linux,pci-domain = <1>; 1892 bus-range = <0x00 0xff>; 1893 num-lanes = <2>; 1894 1895 #address-cells = <3>; 1896 #size-cells = <2>; 1897 1898 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1899 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1900 1901 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1902 interrupt-names = "msi"; 1903 #interrupt-cells = <1>; 1904 interrupt-map-mask = <0 0 0 0x7>; 1905 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1906 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1907 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1908 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1909 1910 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1911 <&gcc GCC_PCIE_1_AUX_CLK>, 1912 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1913 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1914 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1915 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1916 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1917 clock-names = "pipe", 1918 "aux", 1919 "cfg", 1920 "bus_master", 1921 "bus_slave", 1922 "slave_q2a", 1923 "tbu"; 1924 1925 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1926 assigned-clock-rates = <19200000>; 1927 1928 iommus = <&apps_smmu 0x1e00 0x7f>; 1929 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1930 <0x100 &apps_smmu 0x1e01 0x1>; 1931 1932 resets = <&gcc GCC_PCIE_1_BCR>; 1933 reset-names = "pci"; 1934 1935 power-domains = <&gcc PCIE_1_GDSC>; 1936 1937 phys = <&pcie1_lane>; 1938 phy-names = "pciephy"; 1939 1940 perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; 1941 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 1942 1943 pinctrl-names = "default"; 1944 pinctrl-0 = <&pcie1_default_state>; 1945 1946 status = "disabled"; 1947 }; 1948 1949 pcie1_phy: phy@1c0e000 { 1950 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 1951 reg = <0 0x01c0e000 0 0x1c0>; 1952 #address-cells = <2>; 1953 #size-cells = <2>; 1954 ranges; 1955 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1956 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1957 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1958 clock-names = "aux", "cfg_ahb", "refgen"; 1959 1960 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1961 reset-names = "phy"; 1962 1963 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1964 assigned-clock-rates = <100000000>; 1965 1966 status = "disabled"; 1967 1968 pcie1_lane: phy@1c0e200 { 1969 reg = <0 0x01c0e200 0 0x170>, /* tx0 */ 1970 <0 0x01c0e400 0 0x200>, /* rx0 */ 1971 <0 0x01c0ea00 0 0x1f0>, /* pcs */ 1972 <0 0x01c0e600 0 0x170>, /* tx1 */ 1973 <0 0x01c0e800 0 0x200>, /* rx1 */ 1974 <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1975 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1976 clock-names = "pipe0"; 1977 1978 #phy-cells = <0>; 1979 clock-output-names = "pcie_1_pipe_clk"; 1980 }; 1981 }; 1982 1983 ufs_mem_hc: ufshc@1d84000 { 1984 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 1985 "jedec,ufs-2.0"; 1986 reg = <0 0x01d84000 0 0x2500>, 1987 <0 0x01d90000 0 0x8000>; 1988 reg-names = "std", "ice"; 1989 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1990 phys = <&ufs_mem_phy_lanes>; 1991 phy-names = "ufsphy"; 1992 lanes-per-direction = <2>; 1993 #reset-cells = <1>; 1994 resets = <&gcc GCC_UFS_PHY_BCR>; 1995 reset-names = "rst"; 1996 1997 iommus = <&apps_smmu 0x300 0>; 1998 1999 clock-names = 2000 "core_clk", 2001 "bus_aggr_clk", 2002 "iface_clk", 2003 "core_clk_unipro", 2004 "ref_clk", 2005 "tx_lane0_sync_clk", 2006 "rx_lane0_sync_clk", 2007 "rx_lane1_sync_clk", 2008 "ice_core_clk"; 2009 clocks = 2010 <&gcc GCC_UFS_PHY_AXI_CLK>, 2011 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2012 <&gcc GCC_UFS_PHY_AHB_CLK>, 2013 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2014 <&rpmhcc RPMH_CXO_CLK>, 2015 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2016 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2017 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2018 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2019 freq-table-hz = 2020 <37500000 300000000>, 2021 <0 0>, 2022 <0 0>, 2023 <37500000 300000000>, 2024 <0 0>, 2025 <0 0>, 2026 <0 0>, 2027 <0 0>, 2028 <0 300000000>; 2029 2030 status = "disabled"; 2031 }; 2032 2033 ufs_mem_phy: phy@1d87000 { 2034 compatible = "qcom,sm8150-qmp-ufs-phy"; 2035 reg = <0 0x01d87000 0 0x1c0>; 2036 #address-cells = <2>; 2037 #size-cells = <2>; 2038 ranges; 2039 clock-names = "ref", 2040 "ref_aux"; 2041 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2042 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2043 2044 power-domains = <&gcc UFS_PHY_GDSC>; 2045 2046 resets = <&ufs_mem_hc 0>; 2047 reset-names = "ufsphy"; 2048 status = "disabled"; 2049 2050 ufs_mem_phy_lanes: phy@1d87400 { 2051 reg = <0 0x01d87400 0 0x16c>, 2052 <0 0x01d87600 0 0x200>, 2053 <0 0x01d87c00 0 0x200>, 2054 <0 0x01d87800 0 0x16c>, 2055 <0 0x01d87a00 0 0x200>; 2056 #phy-cells = <0>; 2057 }; 2058 }; 2059 2060 tcsr_mutex: hwlock@1f40000 { 2061 compatible = "qcom,tcsr-mutex"; 2062 reg = <0x0 0x01f40000 0x0 0x20000>; 2063 #hwlock-cells = <1>; 2064 }; 2065 2066 tcsr_regs_1: syscon@1f60000 { 2067 compatible = "qcom,sm8150-tcsr", "syscon"; 2068 reg = <0x0 0x01f60000 0x0 0x20000>; 2069 }; 2070 2071 remoteproc_slpi: remoteproc@2400000 { 2072 compatible = "qcom,sm8150-slpi-pas"; 2073 reg = <0x0 0x02400000 0x0 0x4040>; 2074 2075 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 2076 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2077 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2078 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2079 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2080 interrupt-names = "wdog", "fatal", "ready", 2081 "handover", "stop-ack"; 2082 2083 clocks = <&rpmhcc RPMH_CXO_CLK>; 2084 clock-names = "xo"; 2085 2086 power-domains = <&rpmhpd SM8150_LCX>, 2087 <&rpmhpd SM8150_LMX>; 2088 power-domain-names = "lcx", "lmx"; 2089 2090 memory-region = <&slpi_mem>; 2091 2092 qcom,qmp = <&aoss_qmp>; 2093 2094 qcom,smem-states = <&slpi_smp2p_out 0>; 2095 qcom,smem-state-names = "stop"; 2096 2097 status = "disabled"; 2098 2099 glink-edge { 2100 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 2101 label = "dsps"; 2102 qcom,remote-pid = <3>; 2103 mboxes = <&apss_shared 24>; 2104 2105 fastrpc { 2106 compatible = "qcom,fastrpc"; 2107 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2108 label = "sdsp"; 2109 qcom,non-secure-domain; 2110 #address-cells = <1>; 2111 #size-cells = <0>; 2112 2113 compute-cb@1 { 2114 compatible = "qcom,fastrpc-compute-cb"; 2115 reg = <1>; 2116 iommus = <&apps_smmu 0x05a1 0x0>; 2117 }; 2118 2119 compute-cb@2 { 2120 compatible = "qcom,fastrpc-compute-cb"; 2121 reg = <2>; 2122 iommus = <&apps_smmu 0x05a2 0x0>; 2123 }; 2124 2125 compute-cb@3 { 2126 compatible = "qcom,fastrpc-compute-cb"; 2127 reg = <3>; 2128 iommus = <&apps_smmu 0x05a3 0x0>; 2129 /* note: shared-cb = <4> in downstream */ 2130 }; 2131 }; 2132 }; 2133 }; 2134 2135 gpu: gpu@2c00000 { 2136 /* 2137 * note: the amd,imageon compatible makes it possible 2138 * to use the drm/msm driver without the display node, 2139 * make sure to remove it when display node is added 2140 */ 2141 compatible = "qcom,adreno-640.1", 2142 "qcom,adreno", 2143 "amd,imageon"; 2144 2145 reg = <0 0x02c00000 0 0x40000>; 2146 reg-names = "kgsl_3d0_reg_memory"; 2147 2148 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2149 2150 iommus = <&adreno_smmu 0 0x401>; 2151 2152 operating-points-v2 = <&gpu_opp_table>; 2153 2154 qcom,gmu = <&gmu>; 2155 2156 status = "disabled"; 2157 2158 zap-shader { 2159 memory-region = <&gpu_mem>; 2160 }; 2161 2162 /* note: downstream checks gpu binning for 675 Mhz */ 2163 gpu_opp_table: opp-table { 2164 compatible = "operating-points-v2"; 2165 2166 opp-675000000 { 2167 opp-hz = /bits/ 64 <675000000>; 2168 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2169 }; 2170 2171 opp-585000000 { 2172 opp-hz = /bits/ 64 <585000000>; 2173 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2174 }; 2175 2176 opp-499200000 { 2177 opp-hz = /bits/ 64 <499200000>; 2178 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2179 }; 2180 2181 opp-427000000 { 2182 opp-hz = /bits/ 64 <427000000>; 2183 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2184 }; 2185 2186 opp-345000000 { 2187 opp-hz = /bits/ 64 <345000000>; 2188 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2189 }; 2190 2191 opp-257000000 { 2192 opp-hz = /bits/ 64 <257000000>; 2193 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2194 }; 2195 }; 2196 }; 2197 2198 gmu: gmu@2c6a000 { 2199 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2200 2201 reg = <0 0x02c6a000 0 0x30000>, 2202 <0 0x0b290000 0 0x10000>, 2203 <0 0x0b490000 0 0x10000>; 2204 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2205 2206 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2207 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2208 interrupt-names = "hfi", "gmu"; 2209 2210 clocks = <&gpucc GPU_CC_AHB_CLK>, 2211 <&gpucc GPU_CC_CX_GMU_CLK>, 2212 <&gpucc GPU_CC_CXO_CLK>, 2213 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2214 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2215 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2216 2217 power-domains = <&gpucc GPU_CX_GDSC>, 2218 <&gpucc GPU_GX_GDSC>; 2219 power-domain-names = "cx", "gx"; 2220 2221 iommus = <&adreno_smmu 5 0x400>; 2222 2223 operating-points-v2 = <&gmu_opp_table>; 2224 2225 status = "disabled"; 2226 2227 gmu_opp_table: opp-table { 2228 compatible = "operating-points-v2"; 2229 2230 opp-200000000 { 2231 opp-hz = /bits/ 64 <200000000>; 2232 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2233 }; 2234 }; 2235 }; 2236 2237 gpucc: clock-controller@2c90000 { 2238 compatible = "qcom,sm8150-gpucc"; 2239 reg = <0 0x02c90000 0 0x9000>; 2240 clocks = <&rpmhcc RPMH_CXO_CLK>, 2241 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2242 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2243 clock-names = "bi_tcxo", 2244 "gcc_gpu_gpll0_clk_src", 2245 "gcc_gpu_gpll0_div_clk_src"; 2246 #clock-cells = <1>; 2247 #reset-cells = <1>; 2248 #power-domain-cells = <1>; 2249 }; 2250 2251 adreno_smmu: iommu@2ca0000 { 2252 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2253 reg = <0 0x02ca0000 0 0x10000>; 2254 #iommu-cells = <2>; 2255 #global-interrupts = <1>; 2256 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2257 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2258 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2259 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2260 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2261 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2262 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2263 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2264 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2265 clocks = <&gpucc GPU_CC_AHB_CLK>, 2266 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2267 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2268 clock-names = "ahb", "bus", "iface"; 2269 2270 power-domains = <&gpucc GPU_CX_GDSC>; 2271 }; 2272 2273 tlmm: pinctrl@3100000 { 2274 compatible = "qcom,sm8150-pinctrl"; 2275 reg = <0x0 0x03100000 0x0 0x300000>, 2276 <0x0 0x03500000 0x0 0x300000>, 2277 <0x0 0x03900000 0x0 0x300000>, 2278 <0x0 0x03D00000 0x0 0x300000>; 2279 reg-names = "west", "east", "north", "south"; 2280 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2281 gpio-ranges = <&tlmm 0 0 176>; 2282 gpio-controller; 2283 #gpio-cells = <2>; 2284 interrupt-controller; 2285 #interrupt-cells = <2>; 2286 wakeup-parent = <&pdc>; 2287 2288 qup_i2c0_default: qup-i2c0-default-state { 2289 pins = "gpio0", "gpio1"; 2290 function = "qup0"; 2291 drive-strength = <0x02>; 2292 bias-disable; 2293 }; 2294 2295 qup_spi0_default: qup-spi0-default-state { 2296 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2297 function = "qup0"; 2298 drive-strength = <6>; 2299 bias-disable; 2300 }; 2301 2302 qup_i2c1_default: qup-i2c1-default-state { 2303 pins = "gpio114", "gpio115"; 2304 function = "qup1"; 2305 drive-strength = <2>; 2306 bias-disable; 2307 }; 2308 2309 qup_spi1_default: qup-spi1-default-state { 2310 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2311 function = "qup1"; 2312 drive-strength = <6>; 2313 bias-disable; 2314 }; 2315 2316 qup_i2c2_default: qup-i2c2-default-state { 2317 pins = "gpio126", "gpio127"; 2318 function = "qup2"; 2319 drive-strength = <2>; 2320 bias-disable; 2321 }; 2322 2323 qup_spi2_default: qup-spi2-default-state { 2324 pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2325 function = "qup2"; 2326 drive-strength = <6>; 2327 bias-disable; 2328 }; 2329 2330 qup_i2c3_default: qup-i2c3-default-state { 2331 pins = "gpio144", "gpio145"; 2332 function = "qup3"; 2333 drive-strength = <2>; 2334 bias-disable; 2335 }; 2336 2337 qup_spi3_default: qup-spi3-default-state { 2338 pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2339 function = "qup3"; 2340 drive-strength = <6>; 2341 bias-disable; 2342 }; 2343 2344 qup_i2c4_default: qup-i2c4-default-state { 2345 pins = "gpio51", "gpio52"; 2346 function = "qup4"; 2347 drive-strength = <2>; 2348 bias-disable; 2349 }; 2350 2351 qup_spi4_default: qup-spi4-default-state { 2352 pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2353 function = "qup4"; 2354 drive-strength = <6>; 2355 bias-disable; 2356 }; 2357 2358 qup_i2c5_default: qup-i2c5-default-state { 2359 pins = "gpio121", "gpio122"; 2360 function = "qup5"; 2361 drive-strength = <2>; 2362 bias-disable; 2363 }; 2364 2365 qup_spi5_default: qup-spi5-default-state { 2366 pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2367 function = "qup5"; 2368 drive-strength = <6>; 2369 bias-disable; 2370 }; 2371 2372 qup_i2c6_default: qup-i2c6-default-state { 2373 pins = "gpio6", "gpio7"; 2374 function = "qup6"; 2375 drive-strength = <2>; 2376 bias-disable; 2377 }; 2378 2379 qup_spi6_default: qup-spi6_default-state { 2380 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2381 function = "qup6"; 2382 drive-strength = <6>; 2383 bias-disable; 2384 }; 2385 2386 qup_i2c7_default: qup-i2c7-default-state { 2387 pins = "gpio98", "gpio99"; 2388 function = "qup7"; 2389 drive-strength = <2>; 2390 bias-disable; 2391 }; 2392 2393 qup_spi7_default: qup-spi7_default-state { 2394 pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2395 function = "qup7"; 2396 drive-strength = <6>; 2397 bias-disable; 2398 }; 2399 2400 qup_i2c8_default: qup-i2c8-default-state { 2401 pins = "gpio88", "gpio89"; 2402 function = "qup8"; 2403 drive-strength = <2>; 2404 bias-disable; 2405 }; 2406 2407 qup_spi8_default: qup-spi8-default-state { 2408 pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2409 function = "qup8"; 2410 drive-strength = <6>; 2411 bias-disable; 2412 }; 2413 2414 qup_i2c9_default: qup-i2c9-default-state { 2415 pins = "gpio39", "gpio40"; 2416 function = "qup9"; 2417 drive-strength = <2>; 2418 bias-disable; 2419 }; 2420 2421 qup_spi9_default: qup-spi9-default-state { 2422 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2423 function = "qup9"; 2424 drive-strength = <6>; 2425 bias-disable; 2426 }; 2427 2428 qup_i2c10_default: qup-i2c10-default-state { 2429 pins = "gpio9", "gpio10"; 2430 function = "qup10"; 2431 drive-strength = <2>; 2432 bias-disable; 2433 }; 2434 2435 qup_spi10_default: qup-spi10-default-state { 2436 pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2437 function = "qup10"; 2438 drive-strength = <6>; 2439 bias-disable; 2440 }; 2441 2442 qup_i2c11_default: qup-i2c11-default-state { 2443 pins = "gpio94", "gpio95"; 2444 function = "qup11"; 2445 drive-strength = <2>; 2446 bias-disable; 2447 }; 2448 2449 qup_spi11_default: qup-spi11-default-state { 2450 pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2451 function = "qup11"; 2452 drive-strength = <6>; 2453 bias-disable; 2454 }; 2455 2456 qup_i2c12_default: qup-i2c12-default-state { 2457 pins = "gpio83", "gpio84"; 2458 function = "qup12"; 2459 drive-strength = <2>; 2460 bias-disable; 2461 }; 2462 2463 qup_spi12_default: qup-spi12-default-state { 2464 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2465 function = "qup12"; 2466 drive-strength = <6>; 2467 bias-disable; 2468 }; 2469 2470 qup_i2c13_default: qup-i2c13-default-state { 2471 pins = "gpio43", "gpio44"; 2472 function = "qup13"; 2473 drive-strength = <2>; 2474 bias-disable; 2475 }; 2476 2477 qup_spi13_default: qup-spi13-default-state { 2478 pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2479 function = "qup13"; 2480 drive-strength = <6>; 2481 bias-disable; 2482 }; 2483 2484 qup_i2c14_default: qup-i2c14-default-state { 2485 pins = "gpio47", "gpio48"; 2486 function = "qup14"; 2487 drive-strength = <2>; 2488 bias-disable; 2489 }; 2490 2491 qup_spi14_default: qup-spi14-default-state { 2492 pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2493 function = "qup14"; 2494 drive-strength = <6>; 2495 bias-disable; 2496 }; 2497 2498 qup_i2c15_default: qup-i2c15-default-state { 2499 pins = "gpio27", "gpio28"; 2500 function = "qup15"; 2501 drive-strength = <2>; 2502 bias-disable; 2503 }; 2504 2505 qup_spi15_default: qup-spi15-default-state { 2506 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2507 function = "qup15"; 2508 drive-strength = <6>; 2509 bias-disable; 2510 }; 2511 2512 qup_i2c16_default: qup-i2c16-default-state { 2513 pins = "gpio86", "gpio85"; 2514 function = "qup16"; 2515 drive-strength = <2>; 2516 bias-disable; 2517 }; 2518 2519 qup_spi16_default: qup-spi16-default-state { 2520 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2521 function = "qup16"; 2522 drive-strength = <6>; 2523 bias-disable; 2524 }; 2525 2526 qup_i2c17_default: qup-i2c17-default-state { 2527 pins = "gpio55", "gpio56"; 2528 function = "qup17"; 2529 drive-strength = <2>; 2530 bias-disable; 2531 }; 2532 2533 qup_spi17_default: qup-spi17-default-state { 2534 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2535 function = "qup17"; 2536 drive-strength = <6>; 2537 bias-disable; 2538 }; 2539 2540 qup_i2c18_default: qup-i2c18-default-state { 2541 pins = "gpio23", "gpio24"; 2542 function = "qup18"; 2543 drive-strength = <2>; 2544 bias-disable; 2545 }; 2546 2547 qup_spi18_default: qup-spi18-default-state { 2548 pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2549 function = "qup18"; 2550 drive-strength = <6>; 2551 bias-disable; 2552 }; 2553 2554 qup_i2c19_default: qup-i2c19-default-state { 2555 pins = "gpio57", "gpio58"; 2556 function = "qup19"; 2557 drive-strength = <2>; 2558 bias-disable; 2559 }; 2560 2561 qup_spi19_default: qup-spi19-default-state { 2562 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2563 function = "qup19"; 2564 drive-strength = <6>; 2565 bias-disable; 2566 }; 2567 2568 pcie0_default_state: pcie0-default-state { 2569 perst-pins { 2570 pins = "gpio35"; 2571 function = "gpio"; 2572 drive-strength = <2>; 2573 bias-pull-down; 2574 }; 2575 2576 clkreq-pins { 2577 pins = "gpio36"; 2578 function = "pci_e0"; 2579 drive-strength = <2>; 2580 bias-pull-up; 2581 }; 2582 2583 wake-pins { 2584 pins = "gpio37"; 2585 function = "gpio"; 2586 drive-strength = <2>; 2587 bias-pull-up; 2588 }; 2589 }; 2590 2591 pcie1_default_state: pcie1-default-state { 2592 perst-pins { 2593 pins = "gpio102"; 2594 function = "gpio"; 2595 drive-strength = <2>; 2596 bias-pull-down; 2597 }; 2598 2599 clkreq-pins { 2600 pins = "gpio103"; 2601 function = "pci_e1"; 2602 drive-strength = <2>; 2603 bias-pull-up; 2604 }; 2605 2606 wake-pins { 2607 pins = "gpio104"; 2608 function = "gpio"; 2609 drive-strength = <2>; 2610 bias-pull-up; 2611 }; 2612 }; 2613 }; 2614 2615 remoteproc_mpss: remoteproc@4080000 { 2616 compatible = "qcom,sm8150-mpss-pas"; 2617 reg = <0x0 0x04080000 0x0 0x4040>; 2618 2619 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2620 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2621 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2622 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2623 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2624 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2625 interrupt-names = "wdog", "fatal", "ready", "handover", 2626 "stop-ack", "shutdown-ack"; 2627 2628 clocks = <&rpmhcc RPMH_CXO_CLK>; 2629 clock-names = "xo"; 2630 2631 power-domains = <&rpmhpd SM8150_CX>, 2632 <&rpmhpd SM8150_MSS>; 2633 power-domain-names = "cx", "mss"; 2634 2635 memory-region = <&mpss_mem>; 2636 2637 qcom,qmp = <&aoss_qmp>; 2638 2639 qcom,smem-states = <&modem_smp2p_out 0>; 2640 qcom,smem-state-names = "stop"; 2641 2642 status = "disabled"; 2643 2644 glink-edge { 2645 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2646 label = "modem"; 2647 qcom,remote-pid = <1>; 2648 mboxes = <&apss_shared 12>; 2649 }; 2650 }; 2651 2652 stm@6002000 { 2653 compatible = "arm,coresight-stm", "arm,primecell"; 2654 reg = <0 0x06002000 0 0x1000>, 2655 <0 0x16280000 0 0x180000>; 2656 reg-names = "stm-base", "stm-stimulus-base"; 2657 2658 clocks = <&aoss_qmp>; 2659 clock-names = "apb_pclk"; 2660 2661 out-ports { 2662 port { 2663 stm_out: endpoint { 2664 remote-endpoint = <&funnel0_in7>; 2665 }; 2666 }; 2667 }; 2668 }; 2669 2670 funnel@6041000 { 2671 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2672 reg = <0 0x06041000 0 0x1000>; 2673 2674 clocks = <&aoss_qmp>; 2675 clock-names = "apb_pclk"; 2676 2677 out-ports { 2678 port { 2679 funnel0_out: endpoint { 2680 remote-endpoint = <&merge_funnel_in0>; 2681 }; 2682 }; 2683 }; 2684 2685 in-ports { 2686 #address-cells = <1>; 2687 #size-cells = <0>; 2688 2689 port@7 { 2690 reg = <7>; 2691 funnel0_in7: endpoint { 2692 remote-endpoint = <&stm_out>; 2693 }; 2694 }; 2695 }; 2696 }; 2697 2698 funnel@6042000 { 2699 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2700 reg = <0 0x06042000 0 0x1000>; 2701 2702 clocks = <&aoss_qmp>; 2703 clock-names = "apb_pclk"; 2704 2705 out-ports { 2706 port { 2707 funnel1_out: endpoint { 2708 remote-endpoint = <&merge_funnel_in1>; 2709 }; 2710 }; 2711 }; 2712 2713 in-ports { 2714 #address-cells = <1>; 2715 #size-cells = <0>; 2716 2717 port@4 { 2718 reg = <4>; 2719 funnel1_in4: endpoint { 2720 remote-endpoint = <&swao_replicator_out>; 2721 }; 2722 }; 2723 }; 2724 }; 2725 2726 funnel@6043000 { 2727 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2728 reg = <0 0x06043000 0 0x1000>; 2729 2730 clocks = <&aoss_qmp>; 2731 clock-names = "apb_pclk"; 2732 2733 out-ports { 2734 port { 2735 funnel2_out: endpoint { 2736 remote-endpoint = <&merge_funnel_in2>; 2737 }; 2738 }; 2739 }; 2740 2741 in-ports { 2742 #address-cells = <1>; 2743 #size-cells = <0>; 2744 2745 port@2 { 2746 reg = <2>; 2747 funnel2_in2: endpoint { 2748 remote-endpoint = <&apss_merge_funnel_out>; 2749 }; 2750 }; 2751 }; 2752 }; 2753 2754 funnel@6045000 { 2755 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2756 reg = <0 0x06045000 0 0x1000>; 2757 2758 clocks = <&aoss_qmp>; 2759 clock-names = "apb_pclk"; 2760 2761 out-ports { 2762 port { 2763 merge_funnel_out: endpoint { 2764 remote-endpoint = <&etf_in>; 2765 }; 2766 }; 2767 }; 2768 2769 in-ports { 2770 #address-cells = <1>; 2771 #size-cells = <0>; 2772 2773 port@0 { 2774 reg = <0>; 2775 merge_funnel_in0: endpoint { 2776 remote-endpoint = <&funnel0_out>; 2777 }; 2778 }; 2779 2780 port@1 { 2781 reg = <1>; 2782 merge_funnel_in1: endpoint { 2783 remote-endpoint = <&funnel1_out>; 2784 }; 2785 }; 2786 2787 port@2 { 2788 reg = <2>; 2789 merge_funnel_in2: endpoint { 2790 remote-endpoint = <&funnel2_out>; 2791 }; 2792 }; 2793 }; 2794 }; 2795 2796 replicator@6046000 { 2797 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2798 reg = <0 0x06046000 0 0x1000>; 2799 2800 clocks = <&aoss_qmp>; 2801 clock-names = "apb_pclk"; 2802 2803 out-ports { 2804 #address-cells = <1>; 2805 #size-cells = <0>; 2806 2807 port@0 { 2808 reg = <0>; 2809 replicator_out0: endpoint { 2810 remote-endpoint = <&etr_in>; 2811 }; 2812 }; 2813 2814 port@1 { 2815 reg = <1>; 2816 replicator_out1: endpoint { 2817 remote-endpoint = <&replicator1_in>; 2818 }; 2819 }; 2820 }; 2821 2822 in-ports { 2823 port { 2824 replicator_in0: endpoint { 2825 remote-endpoint = <&etf_out>; 2826 }; 2827 }; 2828 }; 2829 }; 2830 2831 etf@6047000 { 2832 compatible = "arm,coresight-tmc", "arm,primecell"; 2833 reg = <0 0x06047000 0 0x1000>; 2834 2835 clocks = <&aoss_qmp>; 2836 clock-names = "apb_pclk"; 2837 2838 out-ports { 2839 port { 2840 etf_out: endpoint { 2841 remote-endpoint = <&replicator_in0>; 2842 }; 2843 }; 2844 }; 2845 2846 in-ports { 2847 port { 2848 etf_in: endpoint { 2849 remote-endpoint = <&merge_funnel_out>; 2850 }; 2851 }; 2852 }; 2853 }; 2854 2855 etr@6048000 { 2856 compatible = "arm,coresight-tmc", "arm,primecell"; 2857 reg = <0 0x06048000 0 0x1000>; 2858 iommus = <&apps_smmu 0x05e0 0x0>; 2859 2860 clocks = <&aoss_qmp>; 2861 clock-names = "apb_pclk"; 2862 arm,scatter-gather; 2863 2864 in-ports { 2865 port { 2866 etr_in: endpoint { 2867 remote-endpoint = <&replicator_out0>; 2868 }; 2869 }; 2870 }; 2871 }; 2872 2873 replicator@604a000 { 2874 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2875 reg = <0 0x0604a000 0 0x1000>; 2876 2877 clocks = <&aoss_qmp>; 2878 clock-names = "apb_pclk"; 2879 2880 out-ports { 2881 #address-cells = <1>; 2882 #size-cells = <0>; 2883 2884 port@1 { 2885 reg = <1>; 2886 replicator1_out: endpoint { 2887 remote-endpoint = <&swao_funnel_in>; 2888 }; 2889 }; 2890 }; 2891 2892 in-ports { 2893 #address-cells = <1>; 2894 #size-cells = <0>; 2895 2896 port@1 { 2897 reg = <1>; 2898 replicator1_in: endpoint { 2899 remote-endpoint = <&replicator_out1>; 2900 }; 2901 }; 2902 }; 2903 }; 2904 2905 funnel@6b08000 { 2906 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2907 reg = <0 0x06b08000 0 0x1000>; 2908 2909 clocks = <&aoss_qmp>; 2910 clock-names = "apb_pclk"; 2911 2912 out-ports { 2913 port { 2914 swao_funnel_out: endpoint { 2915 remote-endpoint = <&swao_etf_in>; 2916 }; 2917 }; 2918 }; 2919 2920 in-ports { 2921 #address-cells = <1>; 2922 #size-cells = <0>; 2923 2924 port@6 { 2925 reg = <6>; 2926 swao_funnel_in: endpoint { 2927 remote-endpoint = <&replicator1_out>; 2928 }; 2929 }; 2930 }; 2931 }; 2932 2933 etf@6b09000 { 2934 compatible = "arm,coresight-tmc", "arm,primecell"; 2935 reg = <0 0x06b09000 0 0x1000>; 2936 2937 clocks = <&aoss_qmp>; 2938 clock-names = "apb_pclk"; 2939 2940 out-ports { 2941 port { 2942 swao_etf_out: endpoint { 2943 remote-endpoint = <&swao_replicator_in>; 2944 }; 2945 }; 2946 }; 2947 2948 in-ports { 2949 port { 2950 swao_etf_in: endpoint { 2951 remote-endpoint = <&swao_funnel_out>; 2952 }; 2953 }; 2954 }; 2955 }; 2956 2957 replicator@6b0a000 { 2958 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2959 reg = <0 0x06b0a000 0 0x1000>; 2960 2961 clocks = <&aoss_qmp>; 2962 clock-names = "apb_pclk"; 2963 qcom,replicator-loses-context; 2964 2965 out-ports { 2966 port { 2967 swao_replicator_out: endpoint { 2968 remote-endpoint = <&funnel1_in4>; 2969 }; 2970 }; 2971 }; 2972 2973 in-ports { 2974 port { 2975 swao_replicator_in: endpoint { 2976 remote-endpoint = <&swao_etf_out>; 2977 }; 2978 }; 2979 }; 2980 }; 2981 2982 etm@7040000 { 2983 compatible = "arm,coresight-etm4x", "arm,primecell"; 2984 reg = <0 0x07040000 0 0x1000>; 2985 2986 cpu = <&CPU0>; 2987 2988 clocks = <&aoss_qmp>; 2989 clock-names = "apb_pclk"; 2990 arm,coresight-loses-context-with-cpu; 2991 qcom,skip-power-up; 2992 2993 out-ports { 2994 port { 2995 etm0_out: endpoint { 2996 remote-endpoint = <&apss_funnel_in0>; 2997 }; 2998 }; 2999 }; 3000 }; 3001 3002 etm@7140000 { 3003 compatible = "arm,coresight-etm4x", "arm,primecell"; 3004 reg = <0 0x07140000 0 0x1000>; 3005 3006 cpu = <&CPU1>; 3007 3008 clocks = <&aoss_qmp>; 3009 clock-names = "apb_pclk"; 3010 arm,coresight-loses-context-with-cpu; 3011 qcom,skip-power-up; 3012 3013 out-ports { 3014 port { 3015 etm1_out: endpoint { 3016 remote-endpoint = <&apss_funnel_in1>; 3017 }; 3018 }; 3019 }; 3020 }; 3021 3022 etm@7240000 { 3023 compatible = "arm,coresight-etm4x", "arm,primecell"; 3024 reg = <0 0x07240000 0 0x1000>; 3025 3026 cpu = <&CPU2>; 3027 3028 clocks = <&aoss_qmp>; 3029 clock-names = "apb_pclk"; 3030 arm,coresight-loses-context-with-cpu; 3031 qcom,skip-power-up; 3032 3033 out-ports { 3034 port { 3035 etm2_out: endpoint { 3036 remote-endpoint = <&apss_funnel_in2>; 3037 }; 3038 }; 3039 }; 3040 }; 3041 3042 etm@7340000 { 3043 compatible = "arm,coresight-etm4x", "arm,primecell"; 3044 reg = <0 0x07340000 0 0x1000>; 3045 3046 cpu = <&CPU3>; 3047 3048 clocks = <&aoss_qmp>; 3049 clock-names = "apb_pclk"; 3050 arm,coresight-loses-context-with-cpu; 3051 qcom,skip-power-up; 3052 3053 out-ports { 3054 port { 3055 etm3_out: endpoint { 3056 remote-endpoint = <&apss_funnel_in3>; 3057 }; 3058 }; 3059 }; 3060 }; 3061 3062 etm@7440000 { 3063 compatible = "arm,coresight-etm4x", "arm,primecell"; 3064 reg = <0 0x07440000 0 0x1000>; 3065 3066 cpu = <&CPU4>; 3067 3068 clocks = <&aoss_qmp>; 3069 clock-names = "apb_pclk"; 3070 arm,coresight-loses-context-with-cpu; 3071 qcom,skip-power-up; 3072 3073 out-ports { 3074 port { 3075 etm4_out: endpoint { 3076 remote-endpoint = <&apss_funnel_in4>; 3077 }; 3078 }; 3079 }; 3080 }; 3081 3082 etm@7540000 { 3083 compatible = "arm,coresight-etm4x", "arm,primecell"; 3084 reg = <0 0x07540000 0 0x1000>; 3085 3086 cpu = <&CPU5>; 3087 3088 clocks = <&aoss_qmp>; 3089 clock-names = "apb_pclk"; 3090 arm,coresight-loses-context-with-cpu; 3091 qcom,skip-power-up; 3092 3093 out-ports { 3094 port { 3095 etm5_out: endpoint { 3096 remote-endpoint = <&apss_funnel_in5>; 3097 }; 3098 }; 3099 }; 3100 }; 3101 3102 etm@7640000 { 3103 compatible = "arm,coresight-etm4x", "arm,primecell"; 3104 reg = <0 0x07640000 0 0x1000>; 3105 3106 cpu = <&CPU6>; 3107 3108 clocks = <&aoss_qmp>; 3109 clock-names = "apb_pclk"; 3110 arm,coresight-loses-context-with-cpu; 3111 qcom,skip-power-up; 3112 3113 out-ports { 3114 port { 3115 etm6_out: endpoint { 3116 remote-endpoint = <&apss_funnel_in6>; 3117 }; 3118 }; 3119 }; 3120 }; 3121 3122 etm@7740000 { 3123 compatible = "arm,coresight-etm4x", "arm,primecell"; 3124 reg = <0 0x07740000 0 0x1000>; 3125 3126 cpu = <&CPU7>; 3127 3128 clocks = <&aoss_qmp>; 3129 clock-names = "apb_pclk"; 3130 arm,coresight-loses-context-with-cpu; 3131 qcom,skip-power-up; 3132 3133 out-ports { 3134 port { 3135 etm7_out: endpoint { 3136 remote-endpoint = <&apss_funnel_in7>; 3137 }; 3138 }; 3139 }; 3140 }; 3141 3142 funnel@7800000 { /* APSS Funnel */ 3143 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3144 reg = <0 0x07800000 0 0x1000>; 3145 3146 clocks = <&aoss_qmp>; 3147 clock-names = "apb_pclk"; 3148 3149 out-ports { 3150 port { 3151 apss_funnel_out: endpoint { 3152 remote-endpoint = <&apss_merge_funnel_in>; 3153 }; 3154 }; 3155 }; 3156 3157 in-ports { 3158 #address-cells = <1>; 3159 #size-cells = <0>; 3160 3161 port@0 { 3162 reg = <0>; 3163 apss_funnel_in0: endpoint { 3164 remote-endpoint = <&etm0_out>; 3165 }; 3166 }; 3167 3168 port@1 { 3169 reg = <1>; 3170 apss_funnel_in1: endpoint { 3171 remote-endpoint = <&etm1_out>; 3172 }; 3173 }; 3174 3175 port@2 { 3176 reg = <2>; 3177 apss_funnel_in2: endpoint { 3178 remote-endpoint = <&etm2_out>; 3179 }; 3180 }; 3181 3182 port@3 { 3183 reg = <3>; 3184 apss_funnel_in3: endpoint { 3185 remote-endpoint = <&etm3_out>; 3186 }; 3187 }; 3188 3189 port@4 { 3190 reg = <4>; 3191 apss_funnel_in4: endpoint { 3192 remote-endpoint = <&etm4_out>; 3193 }; 3194 }; 3195 3196 port@5 { 3197 reg = <5>; 3198 apss_funnel_in5: endpoint { 3199 remote-endpoint = <&etm5_out>; 3200 }; 3201 }; 3202 3203 port@6 { 3204 reg = <6>; 3205 apss_funnel_in6: endpoint { 3206 remote-endpoint = <&etm6_out>; 3207 }; 3208 }; 3209 3210 port@7 { 3211 reg = <7>; 3212 apss_funnel_in7: endpoint { 3213 remote-endpoint = <&etm7_out>; 3214 }; 3215 }; 3216 }; 3217 }; 3218 3219 funnel@7810000 { 3220 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3221 reg = <0 0x07810000 0 0x1000>; 3222 3223 clocks = <&aoss_qmp>; 3224 clock-names = "apb_pclk"; 3225 3226 out-ports { 3227 port { 3228 apss_merge_funnel_out: endpoint { 3229 remote-endpoint = <&funnel2_in2>; 3230 }; 3231 }; 3232 }; 3233 3234 in-ports { 3235 port { 3236 apss_merge_funnel_in: endpoint { 3237 remote-endpoint = <&apss_funnel_out>; 3238 }; 3239 }; 3240 }; 3241 }; 3242 3243 remoteproc_cdsp: remoteproc@8300000 { 3244 compatible = "qcom,sm8150-cdsp-pas"; 3245 reg = <0x0 0x08300000 0x0 0x4040>; 3246 3247 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3248 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3249 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3250 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3251 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3252 interrupt-names = "wdog", "fatal", "ready", 3253 "handover", "stop-ack"; 3254 3255 clocks = <&rpmhcc RPMH_CXO_CLK>; 3256 clock-names = "xo"; 3257 3258 power-domains = <&rpmhpd SM8150_CX>; 3259 3260 memory-region = <&cdsp_mem>; 3261 3262 qcom,qmp = <&aoss_qmp>; 3263 3264 qcom,smem-states = <&cdsp_smp2p_out 0>; 3265 qcom,smem-state-names = "stop"; 3266 3267 status = "disabled"; 3268 3269 glink-edge { 3270 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 3271 label = "cdsp"; 3272 qcom,remote-pid = <5>; 3273 mboxes = <&apss_shared 4>; 3274 3275 fastrpc { 3276 compatible = "qcom,fastrpc"; 3277 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3278 label = "cdsp"; 3279 qcom,non-secure-domain; 3280 #address-cells = <1>; 3281 #size-cells = <0>; 3282 3283 compute-cb@1 { 3284 compatible = "qcom,fastrpc-compute-cb"; 3285 reg = <1>; 3286 iommus = <&apps_smmu 0x1001 0x0460>; 3287 }; 3288 3289 compute-cb@2 { 3290 compatible = "qcom,fastrpc-compute-cb"; 3291 reg = <2>; 3292 iommus = <&apps_smmu 0x1002 0x0460>; 3293 }; 3294 3295 compute-cb@3 { 3296 compatible = "qcom,fastrpc-compute-cb"; 3297 reg = <3>; 3298 iommus = <&apps_smmu 0x1003 0x0460>; 3299 }; 3300 3301 compute-cb@4 { 3302 compatible = "qcom,fastrpc-compute-cb"; 3303 reg = <4>; 3304 iommus = <&apps_smmu 0x1004 0x0460>; 3305 }; 3306 3307 compute-cb@5 { 3308 compatible = "qcom,fastrpc-compute-cb"; 3309 reg = <5>; 3310 iommus = <&apps_smmu 0x1005 0x0460>; 3311 }; 3312 3313 compute-cb@6 { 3314 compatible = "qcom,fastrpc-compute-cb"; 3315 reg = <6>; 3316 iommus = <&apps_smmu 0x1006 0x0460>; 3317 }; 3318 3319 compute-cb@7 { 3320 compatible = "qcom,fastrpc-compute-cb"; 3321 reg = <7>; 3322 iommus = <&apps_smmu 0x1007 0x0460>; 3323 }; 3324 3325 compute-cb@8 { 3326 compatible = "qcom,fastrpc-compute-cb"; 3327 reg = <8>; 3328 iommus = <&apps_smmu 0x1008 0x0460>; 3329 }; 3330 3331 /* note: secure cb9 in downstream */ 3332 }; 3333 }; 3334 }; 3335 3336 usb_1_hsphy: phy@88e2000 { 3337 compatible = "qcom,sm8150-usb-hs-phy", 3338 "qcom,usb-snps-hs-7nm-phy"; 3339 reg = <0 0x088e2000 0 0x400>; 3340 status = "disabled"; 3341 #phy-cells = <0>; 3342 3343 clocks = <&rpmhcc RPMH_CXO_CLK>; 3344 clock-names = "ref"; 3345 3346 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3347 }; 3348 3349 usb_2_hsphy: phy@88e3000 { 3350 compatible = "qcom,sm8150-usb-hs-phy", 3351 "qcom,usb-snps-hs-7nm-phy"; 3352 reg = <0 0x088e3000 0 0x400>; 3353 status = "disabled"; 3354 #phy-cells = <0>; 3355 3356 clocks = <&rpmhcc RPMH_CXO_CLK>; 3357 clock-names = "ref"; 3358 3359 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3360 }; 3361 3362 usb_1_qmpphy: phy@88e9000 { 3363 compatible = "qcom,sm8150-qmp-usb3-phy"; 3364 reg = <0 0x088e9000 0 0x18c>, 3365 <0 0x088e8000 0 0x10>; 3366 status = "disabled"; 3367 #address-cells = <2>; 3368 #size-cells = <2>; 3369 ranges; 3370 3371 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3372 <&rpmhcc RPMH_CXO_CLK>, 3373 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3374 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3375 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3376 3377 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3378 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3379 reset-names = "phy", "common"; 3380 3381 usb_1_ssphy: phy@88e9200 { 3382 reg = <0 0x088e9200 0 0x200>, 3383 <0 0x088e9400 0 0x200>, 3384 <0 0x088e9c00 0 0x218>, 3385 <0 0x088e9600 0 0x200>, 3386 <0 0x088e9800 0 0x200>, 3387 <0 0x088e9a00 0 0x100>; 3388 #clock-cells = <0>; 3389 #phy-cells = <0>; 3390 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3391 clock-names = "pipe0"; 3392 clock-output-names = "usb3_phy_pipe_clk_src"; 3393 }; 3394 }; 3395 3396 usb_2_qmpphy: phy@88eb000 { 3397 compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 3398 reg = <0 0x088eb000 0 0x200>; 3399 status = "disabled"; 3400 #address-cells = <2>; 3401 #size-cells = <2>; 3402 ranges; 3403 3404 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3405 <&rpmhcc RPMH_CXO_CLK>, 3406 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3407 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3408 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3409 3410 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3411 <&gcc GCC_USB3_PHY_SEC_BCR>; 3412 reset-names = "phy", "common"; 3413 3414 usb_2_ssphy: phy@88eb200 { 3415 reg = <0 0x088eb200 0 0x200>, 3416 <0 0x088eb400 0 0x200>, 3417 <0 0x088eb800 0 0x800>, 3418 <0 0x088eb600 0 0x200>; 3419 #clock-cells = <0>; 3420 #phy-cells = <0>; 3421 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3422 clock-names = "pipe0"; 3423 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3424 }; 3425 }; 3426 3427 sdhc_2: mmc@8804000 { 3428 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3429 reg = <0 0x08804000 0 0x1000>; 3430 3431 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3432 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3433 interrupt-names = "hc_irq", "pwr_irq"; 3434 3435 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3436 <&gcc GCC_SDCC2_APPS_CLK>, 3437 <&rpmhcc RPMH_CXO_CLK>; 3438 clock-names = "iface", "core", "xo"; 3439 iommus = <&apps_smmu 0x6a0 0x0>; 3440 qcom,dll-config = <0x0007642c>; 3441 qcom,ddr-config = <0x80040868>; 3442 power-domains = <&rpmhpd 0>; 3443 operating-points-v2 = <&sdhc2_opp_table>; 3444 3445 status = "disabled"; 3446 3447 sdhc2_opp_table: opp-table { 3448 compatible = "operating-points-v2"; 3449 3450 opp-19200000 { 3451 opp-hz = /bits/ 64 <19200000>; 3452 required-opps = <&rpmhpd_opp_min_svs>; 3453 }; 3454 3455 opp-50000000 { 3456 opp-hz = /bits/ 64 <50000000>; 3457 required-opps = <&rpmhpd_opp_low_svs>; 3458 }; 3459 3460 opp-100000000 { 3461 opp-hz = /bits/ 64 <100000000>; 3462 required-opps = <&rpmhpd_opp_svs>; 3463 }; 3464 3465 opp-202000000 { 3466 opp-hz = /bits/ 64 <202000000>; 3467 required-opps = <&rpmhpd_opp_svs_l1>; 3468 }; 3469 }; 3470 }; 3471 3472 dc_noc: interconnect@9160000 { 3473 compatible = "qcom,sm8150-dc-noc"; 3474 reg = <0 0x09160000 0 0x3200>; 3475 #interconnect-cells = <1>; 3476 qcom,bcm-voters = <&apps_bcm_voter>; 3477 }; 3478 3479 gem_noc: interconnect@9680000 { 3480 compatible = "qcom,sm8150-gem-noc"; 3481 reg = <0 0x09680000 0 0x3e200>; 3482 #interconnect-cells = <1>; 3483 qcom,bcm-voters = <&apps_bcm_voter>; 3484 }; 3485 3486 usb_1: usb@a6f8800 { 3487 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3488 reg = <0 0x0a6f8800 0 0x400>; 3489 status = "disabled"; 3490 #address-cells = <2>; 3491 #size-cells = <2>; 3492 ranges; 3493 dma-ranges; 3494 3495 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3496 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3497 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3498 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3499 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3500 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3501 clock-names = "cfg_noc", 3502 "core", 3503 "iface", 3504 "sleep", 3505 "mock_utmi", 3506 "xo"; 3507 3508 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3509 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3510 assigned-clock-rates = <19200000>, <200000000>; 3511 3512 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3513 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3514 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3515 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3516 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3517 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3518 3519 power-domains = <&gcc USB30_PRIM_GDSC>; 3520 3521 resets = <&gcc GCC_USB30_PRIM_BCR>; 3522 3523 usb_1_dwc3: usb@a600000 { 3524 compatible = "snps,dwc3"; 3525 reg = <0 0x0a600000 0 0xcd00>; 3526 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3527 iommus = <&apps_smmu 0x140 0>; 3528 snps,dis_u2_susphy_quirk; 3529 snps,dis_enblslpm_quirk; 3530 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3531 phy-names = "usb2-phy", "usb3-phy"; 3532 }; 3533 }; 3534 3535 usb_2: usb@a8f8800 { 3536 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3537 reg = <0 0x0a8f8800 0 0x400>; 3538 status = "disabled"; 3539 #address-cells = <2>; 3540 #size-cells = <2>; 3541 ranges; 3542 dma-ranges; 3543 3544 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3545 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3546 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3547 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3548 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3549 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3550 clock-names = "cfg_noc", 3551 "core", 3552 "iface", 3553 "sleep", 3554 "mock_utmi", 3555 "xo"; 3556 3557 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3558 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3559 assigned-clock-rates = <19200000>, <200000000>; 3560 3561 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3562 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 3563 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3564 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 3565 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3566 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3567 3568 power-domains = <&gcc USB30_SEC_GDSC>; 3569 3570 resets = <&gcc GCC_USB30_SEC_BCR>; 3571 3572 usb_2_dwc3: usb@a800000 { 3573 compatible = "snps,dwc3"; 3574 reg = <0 0x0a800000 0 0xcd00>; 3575 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3576 iommus = <&apps_smmu 0x160 0>; 3577 snps,dis_u2_susphy_quirk; 3578 snps,dis_enblslpm_quirk; 3579 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3580 phy-names = "usb2-phy", "usb3-phy"; 3581 }; 3582 }; 3583 3584 camnoc_virt: interconnect@ac00000 { 3585 compatible = "qcom,sm8150-camnoc-virt"; 3586 reg = <0 0x0ac00000 0 0x1000>; 3587 #interconnect-cells = <1>; 3588 qcom,bcm-voters = <&apps_bcm_voter>; 3589 }; 3590 3591 mdss: display-subsystem@ae00000 { 3592 compatible = "qcom,sm8150-mdss"; 3593 reg = <0 0x0ae00000 0 0x1000>; 3594 reg-names = "mdss"; 3595 3596 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 3597 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 3598 interconnect-names = "mdp0-mem", "mdp1-mem"; 3599 3600 power-domains = <&dispcc MDSS_GDSC>; 3601 3602 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3603 <&gcc GCC_DISP_HF_AXI_CLK>, 3604 <&gcc GCC_DISP_SF_AXI_CLK>, 3605 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3606 clock-names = "iface", "bus", "nrt_bus", "core"; 3607 3608 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3609 interrupt-controller; 3610 #interrupt-cells = <1>; 3611 3612 iommus = <&apps_smmu 0x800 0x420>; 3613 3614 status = "disabled"; 3615 3616 #address-cells = <2>; 3617 #size-cells = <2>; 3618 ranges; 3619 3620 mdss_mdp: display-controller@ae01000 { 3621 compatible = "qcom,sm8150-dpu"; 3622 reg = <0 0x0ae01000 0 0x8f000>, 3623 <0 0x0aeb0000 0 0x2008>; 3624 reg-names = "mdp", "vbif"; 3625 3626 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3627 <&gcc GCC_DISP_HF_AXI_CLK>, 3628 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3629 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3630 clock-names = "iface", "bus", "core", "vsync"; 3631 3632 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3633 assigned-clock-rates = <19200000>; 3634 3635 operating-points-v2 = <&mdp_opp_table>; 3636 power-domains = <&rpmhpd SM8150_MMCX>; 3637 3638 interrupt-parent = <&mdss>; 3639 interrupts = <0>; 3640 3641 ports { 3642 #address-cells = <1>; 3643 #size-cells = <0>; 3644 3645 port@0 { 3646 reg = <0>; 3647 dpu_intf1_out: endpoint { 3648 remote-endpoint = <&mdss_dsi0_in>; 3649 }; 3650 }; 3651 3652 port@1 { 3653 reg = <1>; 3654 dpu_intf2_out: endpoint { 3655 remote-endpoint = <&mdss_dsi1_in>; 3656 }; 3657 }; 3658 }; 3659 3660 mdp_opp_table: opp-table { 3661 compatible = "operating-points-v2"; 3662 3663 opp-171428571 { 3664 opp-hz = /bits/ 64 <171428571>; 3665 required-opps = <&rpmhpd_opp_low_svs>; 3666 }; 3667 3668 opp-300000000 { 3669 opp-hz = /bits/ 64 <300000000>; 3670 required-opps = <&rpmhpd_opp_svs>; 3671 }; 3672 3673 opp-345000000 { 3674 opp-hz = /bits/ 64 <345000000>; 3675 required-opps = <&rpmhpd_opp_svs_l1>; 3676 }; 3677 3678 opp-460000000 { 3679 opp-hz = /bits/ 64 <460000000>; 3680 required-opps = <&rpmhpd_opp_nom>; 3681 }; 3682 }; 3683 }; 3684 3685 mdss_dsi0: dsi@ae94000 { 3686 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3687 reg = <0 0x0ae94000 0 0x400>; 3688 reg-names = "dsi_ctrl"; 3689 3690 interrupt-parent = <&mdss>; 3691 interrupts = <4>; 3692 3693 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3694 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3695 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3696 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3697 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3698 <&gcc GCC_DISP_HF_AXI_CLK>; 3699 clock-names = "byte", 3700 "byte_intf", 3701 "pixel", 3702 "core", 3703 "iface", 3704 "bus"; 3705 3706 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3707 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3708 assigned-clock-parents = <&mdss_dsi0_phy 0>, 3709 <&mdss_dsi0_phy 1>; 3710 3711 operating-points-v2 = <&dsi_opp_table>; 3712 power-domains = <&rpmhpd SM8150_MMCX>; 3713 3714 phys = <&mdss_dsi0_phy>; 3715 3716 status = "disabled"; 3717 3718 #address-cells = <1>; 3719 #size-cells = <0>; 3720 3721 ports { 3722 #address-cells = <1>; 3723 #size-cells = <0>; 3724 3725 port@0 { 3726 reg = <0>; 3727 mdss_dsi0_in: endpoint { 3728 remote-endpoint = <&dpu_intf1_out>; 3729 }; 3730 }; 3731 3732 port@1 { 3733 reg = <1>; 3734 mdss_dsi0_out: endpoint { 3735 }; 3736 }; 3737 }; 3738 3739 dsi_opp_table: opp-table { 3740 compatible = "operating-points-v2"; 3741 3742 opp-187500000 { 3743 opp-hz = /bits/ 64 <187500000>; 3744 required-opps = <&rpmhpd_opp_low_svs>; 3745 }; 3746 3747 opp-300000000 { 3748 opp-hz = /bits/ 64 <300000000>; 3749 required-opps = <&rpmhpd_opp_svs>; 3750 }; 3751 3752 opp-358000000 { 3753 opp-hz = /bits/ 64 <358000000>; 3754 required-opps = <&rpmhpd_opp_svs_l1>; 3755 }; 3756 }; 3757 }; 3758 3759 mdss_dsi0_phy: phy@ae94400 { 3760 compatible = "qcom,dsi-phy-7nm"; 3761 reg = <0 0x0ae94400 0 0x200>, 3762 <0 0x0ae94600 0 0x280>, 3763 <0 0x0ae94900 0 0x260>; 3764 reg-names = "dsi_phy", 3765 "dsi_phy_lane", 3766 "dsi_pll"; 3767 3768 #clock-cells = <1>; 3769 #phy-cells = <0>; 3770 3771 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3772 <&rpmhcc RPMH_CXO_CLK>; 3773 clock-names = "iface", "ref"; 3774 3775 status = "disabled"; 3776 }; 3777 3778 mdss_dsi1: dsi@ae96000 { 3779 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3780 reg = <0 0x0ae96000 0 0x400>; 3781 reg-names = "dsi_ctrl"; 3782 3783 interrupt-parent = <&mdss>; 3784 interrupts = <5>; 3785 3786 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3787 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3788 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3789 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3790 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3791 <&gcc GCC_DISP_HF_AXI_CLK>; 3792 clock-names = "byte", 3793 "byte_intf", 3794 "pixel", 3795 "core", 3796 "iface", 3797 "bus"; 3798 3799 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3800 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3801 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3802 <&mdss_dsi1_phy 1>; 3803 3804 operating-points-v2 = <&dsi_opp_table>; 3805 power-domains = <&rpmhpd SM8150_MMCX>; 3806 3807 phys = <&mdss_dsi1_phy>; 3808 3809 status = "disabled"; 3810 3811 #address-cells = <1>; 3812 #size-cells = <0>; 3813 3814 ports { 3815 #address-cells = <1>; 3816 #size-cells = <0>; 3817 3818 port@0 { 3819 reg = <0>; 3820 mdss_dsi1_in: endpoint { 3821 remote-endpoint = <&dpu_intf2_out>; 3822 }; 3823 }; 3824 3825 port@1 { 3826 reg = <1>; 3827 mdss_dsi1_out: endpoint { 3828 }; 3829 }; 3830 }; 3831 }; 3832 3833 mdss_dsi1_phy: phy@ae96400 { 3834 compatible = "qcom,dsi-phy-7nm"; 3835 reg = <0 0x0ae96400 0 0x200>, 3836 <0 0x0ae96600 0 0x280>, 3837 <0 0x0ae96900 0 0x260>; 3838 reg-names = "dsi_phy", 3839 "dsi_phy_lane", 3840 "dsi_pll"; 3841 3842 #clock-cells = <1>; 3843 #phy-cells = <0>; 3844 3845 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3846 <&rpmhcc RPMH_CXO_CLK>; 3847 clock-names = "iface", "ref"; 3848 3849 status = "disabled"; 3850 }; 3851 }; 3852 3853 dispcc: clock-controller@af00000 { 3854 compatible = "qcom,sm8150-dispcc"; 3855 reg = <0 0x0af00000 0 0x10000>; 3856 clocks = <&rpmhcc RPMH_CXO_CLK>, 3857 <&mdss_dsi0_phy 0>, 3858 <&mdss_dsi0_phy 1>, 3859 <&mdss_dsi1_phy 0>, 3860 <&mdss_dsi1_phy 1>, 3861 <0>, 3862 <0>; 3863 clock-names = "bi_tcxo", 3864 "dsi0_phy_pll_out_byteclk", 3865 "dsi0_phy_pll_out_dsiclk", 3866 "dsi1_phy_pll_out_byteclk", 3867 "dsi1_phy_pll_out_dsiclk", 3868 "dp_phy_pll_link_clk", 3869 "dp_phy_pll_vco_div_clk"; 3870 power-domains = <&rpmhpd SM8150_MMCX>; 3871 #clock-cells = <1>; 3872 #reset-cells = <1>; 3873 #power-domain-cells = <1>; 3874 }; 3875 3876 pdc: interrupt-controller@b220000 { 3877 compatible = "qcom,sm8150-pdc", "qcom,pdc"; 3878 reg = <0 0x0b220000 0 0x400>; 3879 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3880 <125 63 1>; 3881 #interrupt-cells = <2>; 3882 interrupt-parent = <&intc>; 3883 interrupt-controller; 3884 }; 3885 3886 aoss_qmp: power-management@c300000 { 3887 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 3888 reg = <0x0 0x0c300000 0x0 0x400>; 3889 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3890 mboxes = <&apss_shared 0>; 3891 3892 #clock-cells = <0>; 3893 }; 3894 3895 sram@c3f0000 { 3896 compatible = "qcom,rpmh-stats"; 3897 reg = <0 0x0c3f0000 0 0x400>; 3898 }; 3899 3900 tsens0: thermal-sensor@c263000 { 3901 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3902 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3903 <0 0x0c222000 0 0x1ff>; /* SROT */ 3904 #qcom,sensors = <16>; 3905 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3906 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3907 interrupt-names = "uplow", "critical"; 3908 #thermal-sensor-cells = <1>; 3909 }; 3910 3911 tsens1: thermal-sensor@c265000 { 3912 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3913 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3914 <0 0x0c223000 0 0x1ff>; /* SROT */ 3915 #qcom,sensors = <8>; 3916 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3917 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3918 interrupt-names = "uplow", "critical"; 3919 #thermal-sensor-cells = <1>; 3920 }; 3921 3922 spmi_bus: spmi@c440000 { 3923 compatible = "qcom,spmi-pmic-arb"; 3924 reg = <0x0 0x0c440000 0x0 0x0001100>, 3925 <0x0 0x0c600000 0x0 0x2000000>, 3926 <0x0 0x0e600000 0x0 0x0100000>, 3927 <0x0 0x0e700000 0x0 0x00a0000>, 3928 <0x0 0x0c40a000 0x0 0x0026000>; 3929 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3930 interrupt-names = "periph_irq"; 3931 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3932 qcom,ee = <0>; 3933 qcom,channel = <0>; 3934 #address-cells = <2>; 3935 #size-cells = <0>; 3936 interrupt-controller; 3937 #interrupt-cells = <4>; 3938 cell-index = <0>; 3939 }; 3940 3941 apps_smmu: iommu@15000000 { 3942 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 3943 reg = <0 0x15000000 0 0x100000>; 3944 #iommu-cells = <2>; 3945 #global-interrupts = <1>; 3946 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3947 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3948 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3949 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3950 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3951 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3952 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3953 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3954 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3955 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3956 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3957 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3958 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3959 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3960 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3961 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3962 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3963 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3964 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3965 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3966 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3967 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3968 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3969 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3970 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3971 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3972 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3973 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3974 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3975 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3976 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3977 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3978 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3979 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3980 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3981 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3982 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3983 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3984 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3985 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3986 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3987 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3988 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3989 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3990 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3991 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3992 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3993 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3994 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3995 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3996 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3997 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3998 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3999 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4000 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4001 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4002 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4003 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4004 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4005 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4006 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4007 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4008 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4009 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4010 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4011 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4012 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4013 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4014 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4015 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4016 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4017 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4018 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4019 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4020 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4021 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4022 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4023 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4024 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4025 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4026 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 4027 }; 4028 4029 remoteproc_adsp: remoteproc@17300000 { 4030 compatible = "qcom,sm8150-adsp-pas"; 4031 reg = <0x0 0x17300000 0x0 0x4040>; 4032 4033 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 4034 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4035 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4036 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4037 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 4038 interrupt-names = "wdog", "fatal", "ready", 4039 "handover", "stop-ack"; 4040 4041 clocks = <&rpmhcc RPMH_CXO_CLK>; 4042 clock-names = "xo"; 4043 4044 power-domains = <&rpmhpd SM8150_CX>; 4045 4046 memory-region = <&adsp_mem>; 4047 4048 qcom,qmp = <&aoss_qmp>; 4049 4050 qcom,smem-states = <&adsp_smp2p_out 0>; 4051 qcom,smem-state-names = "stop"; 4052 4053 status = "disabled"; 4054 4055 glink-edge { 4056 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 4057 label = "lpass"; 4058 qcom,remote-pid = <2>; 4059 mboxes = <&apss_shared 8>; 4060 4061 fastrpc { 4062 compatible = "qcom,fastrpc"; 4063 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4064 label = "adsp"; 4065 qcom,non-secure-domain; 4066 #address-cells = <1>; 4067 #size-cells = <0>; 4068 4069 compute-cb@3 { 4070 compatible = "qcom,fastrpc-compute-cb"; 4071 reg = <3>; 4072 iommus = <&apps_smmu 0x1b23 0x0>; 4073 }; 4074 4075 compute-cb@4 { 4076 compatible = "qcom,fastrpc-compute-cb"; 4077 reg = <4>; 4078 iommus = <&apps_smmu 0x1b24 0x0>; 4079 }; 4080 4081 compute-cb@5 { 4082 compatible = "qcom,fastrpc-compute-cb"; 4083 reg = <5>; 4084 iommus = <&apps_smmu 0x1b25 0x0>; 4085 }; 4086 }; 4087 }; 4088 }; 4089 4090 intc: interrupt-controller@17a00000 { 4091 compatible = "arm,gic-v3"; 4092 interrupt-controller; 4093 #interrupt-cells = <3>; 4094 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4095 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4096 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4097 }; 4098 4099 apss_shared: mailbox@17c00000 { 4100 compatible = "qcom,sm8150-apss-shared"; 4101 reg = <0x0 0x17c00000 0x0 0x1000>; 4102 #mbox-cells = <1>; 4103 }; 4104 4105 watchdog@17c10000 { 4106 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 4107 reg = <0 0x17c10000 0 0x1000>; 4108 clocks = <&sleep_clk>; 4109 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4110 }; 4111 4112 timer@17c20000 { 4113 #address-cells = <1>; 4114 #size-cells = <1>; 4115 ranges = <0 0 0 0x20000000>; 4116 compatible = "arm,armv7-timer-mem"; 4117 reg = <0x0 0x17c20000 0x0 0x1000>; 4118 clock-frequency = <19200000>; 4119 4120 frame@17c21000 { 4121 frame-number = <0>; 4122 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4124 reg = <0x17c21000 0x1000>, 4125 <0x17c22000 0x1000>; 4126 }; 4127 4128 frame@17c23000 { 4129 frame-number = <1>; 4130 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4131 reg = <0x17c23000 0x1000>; 4132 status = "disabled"; 4133 }; 4134 4135 frame@17c25000 { 4136 frame-number = <2>; 4137 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4138 reg = <0x17c25000 0x1000>; 4139 status = "disabled"; 4140 }; 4141 4142 frame@17c27000 { 4143 frame-number = <3>; 4144 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4145 reg = <0x17c26000 0x1000>; 4146 status = "disabled"; 4147 }; 4148 4149 frame@17c29000 { 4150 frame-number = <4>; 4151 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4152 reg = <0x17c29000 0x1000>; 4153 status = "disabled"; 4154 }; 4155 4156 frame@17c2b000 { 4157 frame-number = <5>; 4158 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4159 reg = <0x17c2b000 0x1000>; 4160 status = "disabled"; 4161 }; 4162 4163 frame@17c2d000 { 4164 frame-number = <6>; 4165 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4166 reg = <0x17c2d000 0x1000>; 4167 status = "disabled"; 4168 }; 4169 }; 4170 4171 apps_rsc: rsc@18200000 { 4172 label = "apps_rsc"; 4173 compatible = "qcom,rpmh-rsc"; 4174 reg = <0x0 0x18200000 0x0 0x10000>, 4175 <0x0 0x18210000 0x0 0x10000>, 4176 <0x0 0x18220000 0x0 0x10000>; 4177 reg-names = "drv-0", "drv-1", "drv-2"; 4178 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4179 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4180 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4181 qcom,tcs-offset = <0xd00>; 4182 qcom,drv-id = <2>; 4183 qcom,tcs-config = <ACTIVE_TCS 2>, 4184 <SLEEP_TCS 3>, 4185 <WAKE_TCS 3>, 4186 <CONTROL_TCS 1>; 4187 power-domains = <&CLUSTER_PD>; 4188 4189 rpmhcc: clock-controller { 4190 compatible = "qcom,sm8150-rpmh-clk"; 4191 #clock-cells = <1>; 4192 clock-names = "xo"; 4193 clocks = <&xo_board>; 4194 }; 4195 4196 rpmhpd: power-controller { 4197 compatible = "qcom,sm8150-rpmhpd"; 4198 #power-domain-cells = <1>; 4199 operating-points-v2 = <&rpmhpd_opp_table>; 4200 4201 rpmhpd_opp_table: opp-table { 4202 compatible = "operating-points-v2"; 4203 4204 rpmhpd_opp_ret: opp1 { 4205 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4206 }; 4207 4208 rpmhpd_opp_min_svs: opp2 { 4209 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4210 }; 4211 4212 rpmhpd_opp_low_svs: opp3 { 4213 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4214 }; 4215 4216 rpmhpd_opp_svs: opp4 { 4217 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4218 }; 4219 4220 rpmhpd_opp_svs_l1: opp5 { 4221 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4222 }; 4223 4224 rpmhpd_opp_svs_l2: opp6 { 4225 opp-level = <224>; 4226 }; 4227 4228 rpmhpd_opp_nom: opp7 { 4229 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4230 }; 4231 4232 rpmhpd_opp_nom_l1: opp8 { 4233 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4234 }; 4235 4236 rpmhpd_opp_nom_l2: opp9 { 4237 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4238 }; 4239 4240 rpmhpd_opp_turbo: opp10 { 4241 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4242 }; 4243 4244 rpmhpd_opp_turbo_l1: opp11 { 4245 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4246 }; 4247 }; 4248 }; 4249 4250 apps_bcm_voter: bcm-voter { 4251 compatible = "qcom,bcm-voter"; 4252 }; 4253 }; 4254 4255 osm_l3: interconnect@18321000 { 4256 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4257 reg = <0 0x18321000 0 0x1400>; 4258 4259 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4260 clock-names = "xo", "alternate"; 4261 4262 #interconnect-cells = <1>; 4263 }; 4264 4265 cpufreq_hw: cpufreq@18323000 { 4266 compatible = "qcom,cpufreq-hw"; 4267 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 4268 <0 0x18327800 0 0x1400>; 4269 reg-names = "freq-domain0", "freq-domain1", 4270 "freq-domain2"; 4271 4272 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4273 clock-names = "xo", "alternate"; 4274 4275 #freq-domain-cells = <1>; 4276 }; 4277 4278 lmh_cluster1: lmh@18350800 { 4279 compatible = "qcom,sm8150-lmh"; 4280 reg = <0 0x18350800 0 0x400>; 4281 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 4282 cpus = <&CPU4>; 4283 qcom,lmh-temp-arm-millicelsius = <60000>; 4284 qcom,lmh-temp-low-millicelsius = <84500>; 4285 qcom,lmh-temp-high-millicelsius = <85000>; 4286 interrupt-controller; 4287 #interrupt-cells = <1>; 4288 }; 4289 4290 lmh_cluster0: lmh@18358800 { 4291 compatible = "qcom,sm8150-lmh"; 4292 reg = <0 0x18358800 0 0x400>; 4293 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4294 cpus = <&CPU0>; 4295 qcom,lmh-temp-arm-millicelsius = <60000>; 4296 qcom,lmh-temp-low-millicelsius = <84500>; 4297 qcom,lmh-temp-high-millicelsius = <85000>; 4298 interrupt-controller; 4299 #interrupt-cells = <1>; 4300 }; 4301 4302 wifi: wifi@18800000 { 4303 compatible = "qcom,wcn3990-wifi"; 4304 reg = <0 0x18800000 0 0x800000>; 4305 reg-names = "membase"; 4306 memory-region = <&wlan_mem>; 4307 clock-names = "cxo_ref_clk_pin", "qdss"; 4308 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 4309 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4310 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4311 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4312 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4313 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4314 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4315 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4316 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4317 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4318 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4319 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4320 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4321 iommus = <&apps_smmu 0x0640 0x1>; 4322 status = "disabled"; 4323 }; 4324 }; 4325 4326 timer { 4327 compatible = "arm,armv8-timer"; 4328 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4329 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4330 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4331 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4332 }; 4333 4334 thermal-zones { 4335 cpu0-thermal { 4336 polling-delay-passive = <250>; 4337 polling-delay = <1000>; 4338 4339 thermal-sensors = <&tsens0 1>; 4340 4341 trips { 4342 cpu0_alert0: trip-point0 { 4343 temperature = <90000>; 4344 hysteresis = <2000>; 4345 type = "passive"; 4346 }; 4347 4348 cpu0_alert1: trip-point1 { 4349 temperature = <95000>; 4350 hysteresis = <2000>; 4351 type = "passive"; 4352 }; 4353 4354 cpu0_crit: cpu-crit { 4355 temperature = <110000>; 4356 hysteresis = <1000>; 4357 type = "critical"; 4358 }; 4359 }; 4360 4361 cooling-maps { 4362 map0 { 4363 trip = <&cpu0_alert0>; 4364 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4365 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4366 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4367 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4368 }; 4369 map1 { 4370 trip = <&cpu0_alert1>; 4371 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4372 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4373 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4374 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4375 }; 4376 }; 4377 }; 4378 4379 cpu1-thermal { 4380 polling-delay-passive = <250>; 4381 polling-delay = <1000>; 4382 4383 thermal-sensors = <&tsens0 2>; 4384 4385 trips { 4386 cpu1_alert0: trip-point0 { 4387 temperature = <90000>; 4388 hysteresis = <2000>; 4389 type = "passive"; 4390 }; 4391 4392 cpu1_alert1: trip-point1 { 4393 temperature = <95000>; 4394 hysteresis = <2000>; 4395 type = "passive"; 4396 }; 4397 4398 cpu1_crit: cpu-crit { 4399 temperature = <110000>; 4400 hysteresis = <1000>; 4401 type = "critical"; 4402 }; 4403 }; 4404 4405 cooling-maps { 4406 map0 { 4407 trip = <&cpu1_alert0>; 4408 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4409 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4410 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4411 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4412 }; 4413 map1 { 4414 trip = <&cpu1_alert1>; 4415 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4416 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4417 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4418 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4419 }; 4420 }; 4421 }; 4422 4423 cpu2-thermal { 4424 polling-delay-passive = <250>; 4425 polling-delay = <1000>; 4426 4427 thermal-sensors = <&tsens0 3>; 4428 4429 trips { 4430 cpu2_alert0: trip-point0 { 4431 temperature = <90000>; 4432 hysteresis = <2000>; 4433 type = "passive"; 4434 }; 4435 4436 cpu2_alert1: trip-point1 { 4437 temperature = <95000>; 4438 hysteresis = <2000>; 4439 type = "passive"; 4440 }; 4441 4442 cpu2_crit: cpu-crit { 4443 temperature = <110000>; 4444 hysteresis = <1000>; 4445 type = "critical"; 4446 }; 4447 }; 4448 4449 cooling-maps { 4450 map0 { 4451 trip = <&cpu2_alert0>; 4452 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4453 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4454 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4455 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4456 }; 4457 map1 { 4458 trip = <&cpu2_alert1>; 4459 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4460 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4461 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4462 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4463 }; 4464 }; 4465 }; 4466 4467 cpu3-thermal { 4468 polling-delay-passive = <250>; 4469 polling-delay = <1000>; 4470 4471 thermal-sensors = <&tsens0 4>; 4472 4473 trips { 4474 cpu3_alert0: trip-point0 { 4475 temperature = <90000>; 4476 hysteresis = <2000>; 4477 type = "passive"; 4478 }; 4479 4480 cpu3_alert1: trip-point1 { 4481 temperature = <95000>; 4482 hysteresis = <2000>; 4483 type = "passive"; 4484 }; 4485 4486 cpu3_crit: cpu-crit { 4487 temperature = <110000>; 4488 hysteresis = <1000>; 4489 type = "critical"; 4490 }; 4491 }; 4492 4493 cooling-maps { 4494 map0 { 4495 trip = <&cpu3_alert0>; 4496 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4497 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4498 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4499 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4500 }; 4501 map1 { 4502 trip = <&cpu3_alert1>; 4503 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4504 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4505 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4506 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4507 }; 4508 }; 4509 }; 4510 4511 cpu4-top-thermal { 4512 polling-delay-passive = <250>; 4513 polling-delay = <1000>; 4514 4515 thermal-sensors = <&tsens0 7>; 4516 4517 trips { 4518 cpu4_top_alert0: trip-point0 { 4519 temperature = <90000>; 4520 hysteresis = <2000>; 4521 type = "passive"; 4522 }; 4523 4524 cpu4_top_alert1: trip-point1 { 4525 temperature = <95000>; 4526 hysteresis = <2000>; 4527 type = "passive"; 4528 }; 4529 4530 cpu4_top_crit: cpu-crit { 4531 temperature = <110000>; 4532 hysteresis = <1000>; 4533 type = "critical"; 4534 }; 4535 }; 4536 4537 cooling-maps { 4538 map0 { 4539 trip = <&cpu4_top_alert0>; 4540 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4541 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4542 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4543 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4544 }; 4545 map1 { 4546 trip = <&cpu4_top_alert1>; 4547 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4548 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4549 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4550 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4551 }; 4552 }; 4553 }; 4554 4555 cpu5-top-thermal { 4556 polling-delay-passive = <250>; 4557 polling-delay = <1000>; 4558 4559 thermal-sensors = <&tsens0 8>; 4560 4561 trips { 4562 cpu5_top_alert0: trip-point0 { 4563 temperature = <90000>; 4564 hysteresis = <2000>; 4565 type = "passive"; 4566 }; 4567 4568 cpu5_top_alert1: trip-point1 { 4569 temperature = <95000>; 4570 hysteresis = <2000>; 4571 type = "passive"; 4572 }; 4573 4574 cpu5_top_crit: cpu-crit { 4575 temperature = <110000>; 4576 hysteresis = <1000>; 4577 type = "critical"; 4578 }; 4579 }; 4580 4581 cooling-maps { 4582 map0 { 4583 trip = <&cpu5_top_alert0>; 4584 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4585 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4586 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4587 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4588 }; 4589 map1 { 4590 trip = <&cpu5_top_alert1>; 4591 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4592 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4593 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4594 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4595 }; 4596 }; 4597 }; 4598 4599 cpu6-top-thermal { 4600 polling-delay-passive = <250>; 4601 polling-delay = <1000>; 4602 4603 thermal-sensors = <&tsens0 9>; 4604 4605 trips { 4606 cpu6_top_alert0: trip-point0 { 4607 temperature = <90000>; 4608 hysteresis = <2000>; 4609 type = "passive"; 4610 }; 4611 4612 cpu6_top_alert1: trip-point1 { 4613 temperature = <95000>; 4614 hysteresis = <2000>; 4615 type = "passive"; 4616 }; 4617 4618 cpu6_top_crit: cpu-crit { 4619 temperature = <110000>; 4620 hysteresis = <1000>; 4621 type = "critical"; 4622 }; 4623 }; 4624 4625 cooling-maps { 4626 map0 { 4627 trip = <&cpu6_top_alert0>; 4628 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4629 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4630 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4631 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4632 }; 4633 map1 { 4634 trip = <&cpu6_top_alert1>; 4635 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4636 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4637 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4638 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4639 }; 4640 }; 4641 }; 4642 4643 cpu7-top-thermal { 4644 polling-delay-passive = <250>; 4645 polling-delay = <1000>; 4646 4647 thermal-sensors = <&tsens0 10>; 4648 4649 trips { 4650 cpu7_top_alert0: trip-point0 { 4651 temperature = <90000>; 4652 hysteresis = <2000>; 4653 type = "passive"; 4654 }; 4655 4656 cpu7_top_alert1: trip-point1 { 4657 temperature = <95000>; 4658 hysteresis = <2000>; 4659 type = "passive"; 4660 }; 4661 4662 cpu7_top_crit: cpu-crit { 4663 temperature = <110000>; 4664 hysteresis = <1000>; 4665 type = "critical"; 4666 }; 4667 }; 4668 4669 cooling-maps { 4670 map0 { 4671 trip = <&cpu7_top_alert0>; 4672 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4673 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4674 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4675 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4676 }; 4677 map1 { 4678 trip = <&cpu7_top_alert1>; 4679 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4680 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4681 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4682 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4683 }; 4684 }; 4685 }; 4686 4687 cpu4-bottom-thermal { 4688 polling-delay-passive = <250>; 4689 polling-delay = <1000>; 4690 4691 thermal-sensors = <&tsens0 11>; 4692 4693 trips { 4694 cpu4_bottom_alert0: trip-point0 { 4695 temperature = <90000>; 4696 hysteresis = <2000>; 4697 type = "passive"; 4698 }; 4699 4700 cpu4_bottom_alert1: trip-point1 { 4701 temperature = <95000>; 4702 hysteresis = <2000>; 4703 type = "passive"; 4704 }; 4705 4706 cpu4_bottom_crit: cpu-crit { 4707 temperature = <110000>; 4708 hysteresis = <1000>; 4709 type = "critical"; 4710 }; 4711 }; 4712 4713 cooling-maps { 4714 map0 { 4715 trip = <&cpu4_bottom_alert0>; 4716 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4717 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4718 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4719 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4720 }; 4721 map1 { 4722 trip = <&cpu4_bottom_alert1>; 4723 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4724 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4725 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4726 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4727 }; 4728 }; 4729 }; 4730 4731 cpu5-bottom-thermal { 4732 polling-delay-passive = <250>; 4733 polling-delay = <1000>; 4734 4735 thermal-sensors = <&tsens0 12>; 4736 4737 trips { 4738 cpu5_bottom_alert0: trip-point0 { 4739 temperature = <90000>; 4740 hysteresis = <2000>; 4741 type = "passive"; 4742 }; 4743 4744 cpu5_bottom_alert1: trip-point1 { 4745 temperature = <95000>; 4746 hysteresis = <2000>; 4747 type = "passive"; 4748 }; 4749 4750 cpu5_bottom_crit: cpu-crit { 4751 temperature = <110000>; 4752 hysteresis = <1000>; 4753 type = "critical"; 4754 }; 4755 }; 4756 4757 cooling-maps { 4758 map0 { 4759 trip = <&cpu5_bottom_alert0>; 4760 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4761 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4762 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4763 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4764 }; 4765 map1 { 4766 trip = <&cpu5_bottom_alert1>; 4767 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4768 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4769 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4770 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4771 }; 4772 }; 4773 }; 4774 4775 cpu6-bottom-thermal { 4776 polling-delay-passive = <250>; 4777 polling-delay = <1000>; 4778 4779 thermal-sensors = <&tsens0 13>; 4780 4781 trips { 4782 cpu6_bottom_alert0: trip-point0 { 4783 temperature = <90000>; 4784 hysteresis = <2000>; 4785 type = "passive"; 4786 }; 4787 4788 cpu6_bottom_alert1: trip-point1 { 4789 temperature = <95000>; 4790 hysteresis = <2000>; 4791 type = "passive"; 4792 }; 4793 4794 cpu6_bottom_crit: cpu-crit { 4795 temperature = <110000>; 4796 hysteresis = <1000>; 4797 type = "critical"; 4798 }; 4799 }; 4800 4801 cooling-maps { 4802 map0 { 4803 trip = <&cpu6_bottom_alert0>; 4804 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4805 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4806 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4807 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4808 }; 4809 map1 { 4810 trip = <&cpu6_bottom_alert1>; 4811 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4812 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4813 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4814 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4815 }; 4816 }; 4817 }; 4818 4819 cpu7-bottom-thermal { 4820 polling-delay-passive = <250>; 4821 polling-delay = <1000>; 4822 4823 thermal-sensors = <&tsens0 14>; 4824 4825 trips { 4826 cpu7_bottom_alert0: trip-point0 { 4827 temperature = <90000>; 4828 hysteresis = <2000>; 4829 type = "passive"; 4830 }; 4831 4832 cpu7_bottom_alert1: trip-point1 { 4833 temperature = <95000>; 4834 hysteresis = <2000>; 4835 type = "passive"; 4836 }; 4837 4838 cpu7_bottom_crit: cpu-crit { 4839 temperature = <110000>; 4840 hysteresis = <1000>; 4841 type = "critical"; 4842 }; 4843 }; 4844 4845 cooling-maps { 4846 map0 { 4847 trip = <&cpu7_bottom_alert0>; 4848 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4849 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4850 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4851 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4852 }; 4853 map1 { 4854 trip = <&cpu7_bottom_alert1>; 4855 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4856 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4857 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4858 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4859 }; 4860 }; 4861 }; 4862 4863 aoss0-thermal { 4864 polling-delay-passive = <250>; 4865 polling-delay = <1000>; 4866 4867 thermal-sensors = <&tsens0 0>; 4868 4869 trips { 4870 aoss0_alert0: trip-point0 { 4871 temperature = <90000>; 4872 hysteresis = <2000>; 4873 type = "hot"; 4874 }; 4875 }; 4876 }; 4877 4878 cluster0-thermal { 4879 polling-delay-passive = <250>; 4880 polling-delay = <1000>; 4881 4882 thermal-sensors = <&tsens0 5>; 4883 4884 trips { 4885 cluster0_alert0: trip-point0 { 4886 temperature = <90000>; 4887 hysteresis = <2000>; 4888 type = "hot"; 4889 }; 4890 cluster0_crit: cluster0_crit { 4891 temperature = <110000>; 4892 hysteresis = <2000>; 4893 type = "critical"; 4894 }; 4895 }; 4896 }; 4897 4898 cluster1-thermal { 4899 polling-delay-passive = <250>; 4900 polling-delay = <1000>; 4901 4902 thermal-sensors = <&tsens0 6>; 4903 4904 trips { 4905 cluster1_alert0: trip-point0 { 4906 temperature = <90000>; 4907 hysteresis = <2000>; 4908 type = "hot"; 4909 }; 4910 cluster1_crit: cluster1_crit { 4911 temperature = <110000>; 4912 hysteresis = <2000>; 4913 type = "critical"; 4914 }; 4915 }; 4916 }; 4917 4918 gpu-top-thermal { 4919 polling-delay-passive = <250>; 4920 polling-delay = <1000>; 4921 4922 thermal-sensors = <&tsens0 15>; 4923 4924 trips { 4925 gpu1_alert0: trip-point0 { 4926 temperature = <90000>; 4927 hysteresis = <2000>; 4928 type = "hot"; 4929 }; 4930 }; 4931 }; 4932 4933 aoss1-thermal { 4934 polling-delay-passive = <250>; 4935 polling-delay = <1000>; 4936 4937 thermal-sensors = <&tsens1 0>; 4938 4939 trips { 4940 aoss1_alert0: trip-point0 { 4941 temperature = <90000>; 4942 hysteresis = <2000>; 4943 type = "hot"; 4944 }; 4945 }; 4946 }; 4947 4948 wlan-thermal { 4949 polling-delay-passive = <250>; 4950 polling-delay = <1000>; 4951 4952 thermal-sensors = <&tsens1 1>; 4953 4954 trips { 4955 wlan_alert0: trip-point0 { 4956 temperature = <90000>; 4957 hysteresis = <2000>; 4958 type = "hot"; 4959 }; 4960 }; 4961 }; 4962 4963 video-thermal { 4964 polling-delay-passive = <250>; 4965 polling-delay = <1000>; 4966 4967 thermal-sensors = <&tsens1 2>; 4968 4969 trips { 4970 video_alert0: trip-point0 { 4971 temperature = <90000>; 4972 hysteresis = <2000>; 4973 type = "hot"; 4974 }; 4975 }; 4976 }; 4977 4978 mem-thermal { 4979 polling-delay-passive = <250>; 4980 polling-delay = <1000>; 4981 4982 thermal-sensors = <&tsens1 3>; 4983 4984 trips { 4985 mem_alert0: trip-point0 { 4986 temperature = <90000>; 4987 hysteresis = <2000>; 4988 type = "hot"; 4989 }; 4990 }; 4991 }; 4992 4993 q6-hvx-thermal { 4994 polling-delay-passive = <250>; 4995 polling-delay = <1000>; 4996 4997 thermal-sensors = <&tsens1 4>; 4998 4999 trips { 5000 q6_hvx_alert0: trip-point0 { 5001 temperature = <90000>; 5002 hysteresis = <2000>; 5003 type = "hot"; 5004 }; 5005 }; 5006 }; 5007 5008 camera-thermal { 5009 polling-delay-passive = <250>; 5010 polling-delay = <1000>; 5011 5012 thermal-sensors = <&tsens1 5>; 5013 5014 trips { 5015 camera_alert0: trip-point0 { 5016 temperature = <90000>; 5017 hysteresis = <2000>; 5018 type = "hot"; 5019 }; 5020 }; 5021 }; 5022 5023 compute-thermal { 5024 polling-delay-passive = <250>; 5025 polling-delay = <1000>; 5026 5027 thermal-sensors = <&tsens1 6>; 5028 5029 trips { 5030 compute_alert0: trip-point0 { 5031 temperature = <90000>; 5032 hysteresis = <2000>; 5033 type = "hot"; 5034 }; 5035 }; 5036 }; 5037 5038 modem-thermal { 5039 polling-delay-passive = <250>; 5040 polling-delay = <1000>; 5041 5042 thermal-sensors = <&tsens1 7>; 5043 5044 trips { 5045 modem_alert0: trip-point0 { 5046 temperature = <90000>; 5047 hysteresis = <2000>; 5048 type = "hot"; 5049 }; 5050 }; 5051 }; 5052 5053 npu-thermal { 5054 polling-delay-passive = <250>; 5055 polling-delay = <1000>; 5056 5057 thermal-sensors = <&tsens1 8>; 5058 5059 trips { 5060 npu_alert0: trip-point0 { 5061 temperature = <90000>; 5062 hysteresis = <2000>; 5063 type = "hot"; 5064 }; 5065 }; 5066 }; 5067 5068 modem-vec-thermal { 5069 polling-delay-passive = <250>; 5070 polling-delay = <1000>; 5071 5072 thermal-sensors = <&tsens1 9>; 5073 5074 trips { 5075 modem_vec_alert0: trip-point0 { 5076 temperature = <90000>; 5077 hysteresis = <2000>; 5078 type = "hot"; 5079 }; 5080 }; 5081 }; 5082 5083 modem-scl-thermal { 5084 polling-delay-passive = <250>; 5085 polling-delay = <1000>; 5086 5087 thermal-sensors = <&tsens1 10>; 5088 5089 trips { 5090 modem_scl_alert0: trip-point0 { 5091 temperature = <90000>; 5092 hysteresis = <2000>; 5093 type = "hot"; 5094 }; 5095 }; 5096 }; 5097 5098 gpu-bottom-thermal { 5099 polling-delay-passive = <250>; 5100 polling-delay = <1000>; 5101 5102 thermal-sensors = <&tsens1 11>; 5103 5104 trips { 5105 gpu2_alert0: trip-point0 { 5106 temperature = <90000>; 5107 hysteresis = <2000>; 5108 type = "hot"; 5109 }; 5110 }; 5111 }; 5112 }; 5113}; 5114