1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/power/qcom-aoss-qmp.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,gcc-sm8150.h> 13#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 chosen { }; 24 25 clocks { 26 xo_board: xo-board { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <38400000>; 30 clock-output-names = "xo_board"; 31 }; 32 33 sleep_clk: sleep-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <32764>; 37 clock-output-names = "sleep_clk"; 38 }; 39 }; 40 41 cpus { 42 #address-cells = <2>; 43 #size-cells = <0>; 44 45 CPU0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "qcom,kryo485"; 48 reg = <0x0 0x0>; 49 enable-method = "psci"; 50 capacity-dmips-mhz = <488>; 51 dynamic-power-coefficient = <232>; 52 next-level-cache = <&L2_0>; 53 qcom,freq-domain = <&cpufreq_hw 0>; 54 power-domains = <&CPU_PD0>; 55 power-domain-names = "psci"; 56 #cooling-cells = <2>; 57 L2_0: l2-cache { 58 compatible = "cache"; 59 next-level-cache = <&L3_0>; 60 L3_0: l3-cache { 61 compatible = "cache"; 62 }; 63 }; 64 }; 65 66 CPU1: cpu@100 { 67 device_type = "cpu"; 68 compatible = "qcom,kryo485"; 69 reg = <0x0 0x100>; 70 enable-method = "psci"; 71 capacity-dmips-mhz = <488>; 72 dynamic-power-coefficient = <232>; 73 next-level-cache = <&L2_100>; 74 qcom,freq-domain = <&cpufreq_hw 0>; 75 power-domains = <&CPU_PD1>; 76 power-domain-names = "psci"; 77 #cooling-cells = <2>; 78 L2_100: l2-cache { 79 compatible = "cache"; 80 next-level-cache = <&L3_0>; 81 }; 82 83 }; 84 85 CPU2: cpu@200 { 86 device_type = "cpu"; 87 compatible = "qcom,kryo485"; 88 reg = <0x0 0x200>; 89 enable-method = "psci"; 90 capacity-dmips-mhz = <488>; 91 dynamic-power-coefficient = <232>; 92 next-level-cache = <&L2_200>; 93 qcom,freq-domain = <&cpufreq_hw 0>; 94 power-domains = <&CPU_PD2>; 95 power-domain-names = "psci"; 96 #cooling-cells = <2>; 97 L2_200: l2-cache { 98 compatible = "cache"; 99 next-level-cache = <&L3_0>; 100 }; 101 }; 102 103 CPU3: cpu@300 { 104 device_type = "cpu"; 105 compatible = "qcom,kryo485"; 106 reg = <0x0 0x300>; 107 enable-method = "psci"; 108 capacity-dmips-mhz = <488>; 109 dynamic-power-coefficient = <232>; 110 next-level-cache = <&L2_300>; 111 qcom,freq-domain = <&cpufreq_hw 0>; 112 power-domains = <&CPU_PD3>; 113 power-domain-names = "psci"; 114 #cooling-cells = <2>; 115 L2_300: l2-cache { 116 compatible = "cache"; 117 next-level-cache = <&L3_0>; 118 }; 119 }; 120 121 CPU4: cpu@400 { 122 device_type = "cpu"; 123 compatible = "qcom,kryo485"; 124 reg = <0x0 0x400>; 125 enable-method = "psci"; 126 capacity-dmips-mhz = <1024>; 127 dynamic-power-coefficient = <369>; 128 next-level-cache = <&L2_400>; 129 qcom,freq-domain = <&cpufreq_hw 1>; 130 power-domains = <&CPU_PD4>; 131 power-domain-names = "psci"; 132 #cooling-cells = <2>; 133 L2_400: l2-cache { 134 compatible = "cache"; 135 next-level-cache = <&L3_0>; 136 }; 137 }; 138 139 CPU5: cpu@500 { 140 device_type = "cpu"; 141 compatible = "qcom,kryo485"; 142 reg = <0x0 0x500>; 143 enable-method = "psci"; 144 capacity-dmips-mhz = <1024>; 145 dynamic-power-coefficient = <369>; 146 next-level-cache = <&L2_500>; 147 qcom,freq-domain = <&cpufreq_hw 1>; 148 power-domains = <&CPU_PD5>; 149 power-domain-names = "psci"; 150 #cooling-cells = <2>; 151 L2_500: l2-cache { 152 compatible = "cache"; 153 next-level-cache = <&L3_0>; 154 }; 155 }; 156 157 CPU6: cpu@600 { 158 device_type = "cpu"; 159 compatible = "qcom,kryo485"; 160 reg = <0x0 0x600>; 161 enable-method = "psci"; 162 capacity-dmips-mhz = <1024>; 163 dynamic-power-coefficient = <369>; 164 next-level-cache = <&L2_600>; 165 qcom,freq-domain = <&cpufreq_hw 1>; 166 power-domains = <&CPU_PD6>; 167 power-domain-names = "psci"; 168 #cooling-cells = <2>; 169 L2_600: l2-cache { 170 compatible = "cache"; 171 next-level-cache = <&L3_0>; 172 }; 173 }; 174 175 CPU7: cpu@700 { 176 device_type = "cpu"; 177 compatible = "qcom,kryo485"; 178 reg = <0x0 0x700>; 179 enable-method = "psci"; 180 capacity-dmips-mhz = <1024>; 181 dynamic-power-coefficient = <421>; 182 next-level-cache = <&L2_700>; 183 qcom,freq-domain = <&cpufreq_hw 2>; 184 power-domains = <&CPU_PD7>; 185 power-domain-names = "psci"; 186 #cooling-cells = <2>; 187 L2_700: l2-cache { 188 compatible = "cache"; 189 next-level-cache = <&L3_0>; 190 }; 191 }; 192 193 cpu-map { 194 cluster0 { 195 core0 { 196 cpu = <&CPU0>; 197 }; 198 199 core1 { 200 cpu = <&CPU1>; 201 }; 202 203 core2 { 204 cpu = <&CPU2>; 205 }; 206 207 core3 { 208 cpu = <&CPU3>; 209 }; 210 211 core4 { 212 cpu = <&CPU4>; 213 }; 214 215 core5 { 216 cpu = <&CPU5>; 217 }; 218 219 core6 { 220 cpu = <&CPU6>; 221 }; 222 223 core7 { 224 cpu = <&CPU7>; 225 }; 226 }; 227 }; 228 229 idle-states { 230 entry-method = "psci"; 231 232 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 233 compatible = "arm,idle-state"; 234 idle-state-name = "little-rail-power-collapse"; 235 arm,psci-suspend-param = <0x40000004>; 236 entry-latency-us = <355>; 237 exit-latency-us = <909>; 238 min-residency-us = <3934>; 239 local-timer-stop; 240 }; 241 242 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 243 compatible = "arm,idle-state"; 244 idle-state-name = "big-rail-power-collapse"; 245 arm,psci-suspend-param = <0x40000004>; 246 entry-latency-us = <241>; 247 exit-latency-us = <1461>; 248 min-residency-us = <4488>; 249 local-timer-stop; 250 }; 251 }; 252 253 domain-idle-states { 254 CLUSTER_SLEEP_0: cluster-sleep-0 { 255 compatible = "domain-idle-state"; 256 idle-state-name = "cluster-power-collapse"; 257 arm,psci-suspend-param = <0x4100c244>; 258 entry-latency-us = <3263>; 259 exit-latency-us = <6562>; 260 min-residency-us = <9987>; 261 local-timer-stop; 262 }; 263 }; 264 }; 265 266 firmware { 267 scm: scm { 268 compatible = "qcom,scm-sm8150", "qcom,scm"; 269 #reset-cells = <1>; 270 }; 271 }; 272 273 tcsr_mutex: hwlock { 274 compatible = "qcom,tcsr-mutex"; 275 syscon = <&tcsr_mutex_regs 0 0x1000>; 276 #hwlock-cells = <1>; 277 }; 278 279 memory@80000000 { 280 device_type = "memory"; 281 /* We expect the bootloader to fill in the size */ 282 reg = <0x0 0x80000000 0x0 0x0>; 283 }; 284 285 pmu { 286 compatible = "arm,armv8-pmuv3"; 287 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 288 }; 289 290 psci { 291 compatible = "arm,psci-1.0"; 292 method = "smc"; 293 294 CPU_PD0: cpu0 { 295 #power-domain-cells = <0>; 296 power-domains = <&CLUSTER_PD>; 297 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 298 }; 299 300 CPU_PD1: cpu1 { 301 #power-domain-cells = <0>; 302 power-domains = <&CLUSTER_PD>; 303 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 304 }; 305 306 CPU_PD2: cpu2 { 307 #power-domain-cells = <0>; 308 power-domains = <&CLUSTER_PD>; 309 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 310 }; 311 312 CPU_PD3: cpu3 { 313 #power-domain-cells = <0>; 314 power-domains = <&CLUSTER_PD>; 315 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 316 }; 317 318 CPU_PD4: cpu4 { 319 #power-domain-cells = <0>; 320 power-domains = <&CLUSTER_PD>; 321 domain-idle-states = <&BIG_CPU_SLEEP_0>; 322 }; 323 324 CPU_PD5: cpu5 { 325 #power-domain-cells = <0>; 326 power-domains = <&CLUSTER_PD>; 327 domain-idle-states = <&BIG_CPU_SLEEP_0>; 328 }; 329 330 CPU_PD6: cpu6 { 331 #power-domain-cells = <0>; 332 power-domains = <&CLUSTER_PD>; 333 domain-idle-states = <&BIG_CPU_SLEEP_0>; 334 }; 335 336 CPU_PD7: cpu7 { 337 #power-domain-cells = <0>; 338 power-domains = <&CLUSTER_PD>; 339 domain-idle-states = <&BIG_CPU_SLEEP_0>; 340 }; 341 342 CLUSTER_PD: cpu-cluster0 { 343 #power-domain-cells = <0>; 344 domain-idle-states = <&CLUSTER_SLEEP_0>; 345 }; 346 }; 347 348 reserved-memory { 349 #address-cells = <2>; 350 #size-cells = <2>; 351 ranges; 352 353 hyp_mem: memory@85700000 { 354 reg = <0x0 0x85700000 0x0 0x600000>; 355 no-map; 356 }; 357 358 xbl_mem: memory@85d00000 { 359 reg = <0x0 0x85d00000 0x0 0x140000>; 360 no-map; 361 }; 362 363 aop_mem: memory@85f00000 { 364 reg = <0x0 0x85f00000 0x0 0x20000>; 365 no-map; 366 }; 367 368 aop_cmd_db: memory@85f20000 { 369 compatible = "qcom,cmd-db"; 370 reg = <0x0 0x85f20000 0x0 0x20000>; 371 no-map; 372 }; 373 374 smem_mem: memory@86000000 { 375 reg = <0x0 0x86000000 0x0 0x200000>; 376 no-map; 377 }; 378 379 tz_mem: memory@86200000 { 380 reg = <0x0 0x86200000 0x0 0x3900000>; 381 no-map; 382 }; 383 384 rmtfs_mem: memory@89b00000 { 385 compatible = "qcom,rmtfs-mem"; 386 reg = <0x0 0x89b00000 0x0 0x200000>; 387 no-map; 388 389 qcom,client-id = <1>; 390 qcom,vmid = <15>; 391 }; 392 393 camera_mem: memory@8b700000 { 394 reg = <0x0 0x8b700000 0x0 0x500000>; 395 no-map; 396 }; 397 398 wlan_mem: memory@8bc00000 { 399 reg = <0x0 0x8bc00000 0x0 0x180000>; 400 no-map; 401 }; 402 403 npu_mem: memory@8bd80000 { 404 reg = <0x0 0x8bd80000 0x0 0x80000>; 405 no-map; 406 }; 407 408 adsp_mem: memory@8be00000 { 409 reg = <0x0 0x8be00000 0x0 0x1a00000>; 410 no-map; 411 }; 412 413 mpss_mem: memory@8d800000 { 414 reg = <0x0 0x8d800000 0x0 0x9600000>; 415 no-map; 416 }; 417 418 venus_mem: memory@96e00000 { 419 reg = <0x0 0x96e00000 0x0 0x500000>; 420 no-map; 421 }; 422 423 slpi_mem: memory@97300000 { 424 reg = <0x0 0x97300000 0x0 0x1400000>; 425 no-map; 426 }; 427 428 ipa_fw_mem: memory@98700000 { 429 reg = <0x0 0x98700000 0x0 0x10000>; 430 no-map; 431 }; 432 433 ipa_gsi_mem: memory@98710000 { 434 reg = <0x0 0x98710000 0x0 0x5000>; 435 no-map; 436 }; 437 438 gpu_mem: memory@98715000 { 439 reg = <0x0 0x98715000 0x0 0x2000>; 440 no-map; 441 }; 442 443 spss_mem: memory@98800000 { 444 reg = <0x0 0x98800000 0x0 0x100000>; 445 no-map; 446 }; 447 448 cdsp_mem: memory@98900000 { 449 reg = <0x0 0x98900000 0x0 0x1400000>; 450 no-map; 451 }; 452 453 qseecom_mem: memory@9e400000 { 454 reg = <0x0 0x9e400000 0x0 0x1400000>; 455 no-map; 456 }; 457 }; 458 459 smem { 460 compatible = "qcom,smem"; 461 memory-region = <&smem_mem>; 462 hwlocks = <&tcsr_mutex 3>; 463 }; 464 465 smp2p-cdsp { 466 compatible = "qcom,smp2p"; 467 qcom,smem = <94>, <432>; 468 469 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 470 471 mboxes = <&apss_shared 6>; 472 473 qcom,local-pid = <0>; 474 qcom,remote-pid = <5>; 475 476 cdsp_smp2p_out: master-kernel { 477 qcom,entry-name = "master-kernel"; 478 #qcom,smem-state-cells = <1>; 479 }; 480 481 cdsp_smp2p_in: slave-kernel { 482 qcom,entry-name = "slave-kernel"; 483 484 interrupt-controller; 485 #interrupt-cells = <2>; 486 }; 487 }; 488 489 smp2p-lpass { 490 compatible = "qcom,smp2p"; 491 qcom,smem = <443>, <429>; 492 493 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 494 495 mboxes = <&apss_shared 10>; 496 497 qcom,local-pid = <0>; 498 qcom,remote-pid = <2>; 499 500 adsp_smp2p_out: master-kernel { 501 qcom,entry-name = "master-kernel"; 502 #qcom,smem-state-cells = <1>; 503 }; 504 505 adsp_smp2p_in: slave-kernel { 506 qcom,entry-name = "slave-kernel"; 507 508 interrupt-controller; 509 #interrupt-cells = <2>; 510 }; 511 }; 512 513 smp2p-mpss { 514 compatible = "qcom,smp2p"; 515 qcom,smem = <435>, <428>; 516 517 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 518 519 mboxes = <&apss_shared 14>; 520 521 qcom,local-pid = <0>; 522 qcom,remote-pid = <1>; 523 524 modem_smp2p_out: master-kernel { 525 qcom,entry-name = "master-kernel"; 526 #qcom,smem-state-cells = <1>; 527 }; 528 529 modem_smp2p_in: slave-kernel { 530 qcom,entry-name = "slave-kernel"; 531 532 interrupt-controller; 533 #interrupt-cells = <2>; 534 }; 535 }; 536 537 smp2p-slpi { 538 compatible = "qcom,smp2p"; 539 qcom,smem = <481>, <430>; 540 541 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 542 543 mboxes = <&apss_shared 26>; 544 545 qcom,local-pid = <0>; 546 qcom,remote-pid = <3>; 547 548 slpi_smp2p_out: master-kernel { 549 qcom,entry-name = "master-kernel"; 550 #qcom,smem-state-cells = <1>; 551 }; 552 553 slpi_smp2p_in: slave-kernel { 554 qcom,entry-name = "slave-kernel"; 555 556 interrupt-controller; 557 #interrupt-cells = <2>; 558 }; 559 }; 560 561 soc: soc@0 { 562 #address-cells = <2>; 563 #size-cells = <2>; 564 ranges = <0 0 0 0 0x10 0>; 565 dma-ranges = <0 0 0 0 0x10 0>; 566 compatible = "simple-bus"; 567 568 gcc: clock-controller@100000 { 569 compatible = "qcom,gcc-sm8150"; 570 reg = <0x0 0x00100000 0x0 0x1f0000>; 571 #clock-cells = <1>; 572 #reset-cells = <1>; 573 #power-domain-cells = <1>; 574 clock-names = "bi_tcxo", 575 "sleep_clk"; 576 clocks = <&rpmhcc RPMH_CXO_CLK>, 577 <&sleep_clk>; 578 }; 579 580 qupv3_id_1: geniqup@ac0000 { 581 compatible = "qcom,geni-se-qup"; 582 reg = <0x0 0x00ac0000 0x0 0x6000>; 583 clock-names = "m-ahb", "s-ahb"; 584 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 585 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 586 #address-cells = <2>; 587 #size-cells = <2>; 588 ranges; 589 status = "disabled"; 590 591 uart2: serial@a90000 { 592 compatible = "qcom,geni-debug-uart"; 593 reg = <0x0 0x00a90000 0x0 0x4000>; 594 clock-names = "se"; 595 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 596 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 597 status = "disabled"; 598 }; 599 }; 600 601 config_noc: interconnect@1500000 { 602 compatible = "qcom,sm8150-config-noc"; 603 reg = <0 0x01500000 0 0x7400>; 604 #interconnect-cells = <1>; 605 qcom,bcm-voters = <&apps_bcm_voter>; 606 }; 607 608 system_noc: interconnect@1620000 { 609 compatible = "qcom,sm8150-system-noc"; 610 reg = <0 0x01620000 0 0x19400>; 611 #interconnect-cells = <1>; 612 qcom,bcm-voters = <&apps_bcm_voter>; 613 }; 614 615 mc_virt: interconnect@163a000 { 616 compatible = "qcom,sm8150-mc-virt"; 617 reg = <0 0x0163a000 0 0x1000>; 618 #interconnect-cells = <1>; 619 qcom,bcm-voters = <&apps_bcm_voter>; 620 }; 621 622 aggre1_noc: interconnect@16e0000 { 623 compatible = "qcom,sm8150-aggre1-noc"; 624 reg = <0 0x016e0000 0 0xd080>; 625 #interconnect-cells = <1>; 626 qcom,bcm-voters = <&apps_bcm_voter>; 627 }; 628 629 aggre2_noc: interconnect@1700000 { 630 compatible = "qcom,sm8150-aggre2-noc"; 631 reg = <0 0x01700000 0 0x20000>; 632 #interconnect-cells = <1>; 633 qcom,bcm-voters = <&apps_bcm_voter>; 634 }; 635 636 compute_noc: interconnect@1720000 { 637 compatible = "qcom,sm8150-compute-noc"; 638 reg = <0 0x01720000 0 0x7000>; 639 #interconnect-cells = <1>; 640 qcom,bcm-voters = <&apps_bcm_voter>; 641 }; 642 643 mmss_noc: interconnect@1740000 { 644 compatible = "qcom,sm8150-mmss-noc"; 645 reg = <0 0x01740000 0 0x1c100>; 646 #interconnect-cells = <1>; 647 qcom,bcm-voters = <&apps_bcm_voter>; 648 }; 649 650 system-cache-controller@9200000 { 651 compatible = "qcom,sm8150-llcc"; 652 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 653 reg-names = "llcc_base", "llcc_broadcast_base"; 654 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 655 }; 656 657 ufs_mem_hc: ufshc@1d84000 { 658 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 659 "jedec,ufs-2.0"; 660 reg = <0 0x01d84000 0 0x2500>; 661 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 662 phys = <&ufs_mem_phy_lanes>; 663 phy-names = "ufsphy"; 664 lanes-per-direction = <2>; 665 #reset-cells = <1>; 666 resets = <&gcc GCC_UFS_PHY_BCR>; 667 reset-names = "rst"; 668 669 iommus = <&apps_smmu 0x300 0>; 670 671 clock-names = 672 "core_clk", 673 "bus_aggr_clk", 674 "iface_clk", 675 "core_clk_unipro", 676 "ref_clk", 677 "tx_lane0_sync_clk", 678 "rx_lane0_sync_clk", 679 "rx_lane1_sync_clk"; 680 clocks = 681 <&gcc GCC_UFS_PHY_AXI_CLK>, 682 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 683 <&gcc GCC_UFS_PHY_AHB_CLK>, 684 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 685 <&rpmhcc RPMH_CXO_CLK>, 686 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 687 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 688 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 689 freq-table-hz = 690 <37500000 300000000>, 691 <0 0>, 692 <0 0>, 693 <37500000 300000000>, 694 <0 0>, 695 <0 0>, 696 <0 0>, 697 <0 0>; 698 699 status = "disabled"; 700 }; 701 702 ufs_mem_phy: phy@1d87000 { 703 compatible = "qcom,sm8150-qmp-ufs-phy"; 704 reg = <0 0x01d87000 0 0x1c0>; 705 #address-cells = <2>; 706 #size-cells = <2>; 707 ranges; 708 clock-names = "ref", 709 "ref_aux"; 710 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 711 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 712 713 resets = <&ufs_mem_hc 0>; 714 reset-names = "ufsphy"; 715 status = "disabled"; 716 717 ufs_mem_phy_lanes: lanes@1d87400 { 718 reg = <0 0x01d87400 0 0x108>, 719 <0 0x01d87600 0 0x1e0>, 720 <0 0x01d87c00 0 0x1dc>, 721 <0 0x01d87800 0 0x108>, 722 <0 0x01d87a00 0 0x1e0>; 723 #phy-cells = <0>; 724 }; 725 }; 726 727 ipa_virt: interconnect@1e00000 { 728 compatible = "qcom,sm8150-ipa-virt"; 729 reg = <0 0x01e00000 0 0x1000>; 730 #interconnect-cells = <1>; 731 qcom,bcm-voters = <&apps_bcm_voter>; 732 }; 733 734 tcsr_mutex_regs: syscon@1f40000 { 735 compatible = "syscon"; 736 reg = <0x0 0x01f40000 0x0 0x40000>; 737 }; 738 739 remoteproc_slpi: remoteproc@2400000 { 740 compatible = "qcom,sm8150-slpi-pas"; 741 reg = <0x0 0x02400000 0x0 0x4040>; 742 743 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 744 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 745 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 746 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 747 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 748 interrupt-names = "wdog", "fatal", "ready", 749 "handover", "stop-ack"; 750 751 clocks = <&rpmhcc RPMH_CXO_CLK>; 752 clock-names = "xo"; 753 754 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, 755 <&rpmhpd 3>, 756 <&rpmhpd 2>; 757 power-domain-names = "load_state", "lcx", "lmx"; 758 759 memory-region = <&slpi_mem>; 760 761 qcom,smem-states = <&slpi_smp2p_out 0>; 762 qcom,smem-state-names = "stop"; 763 764 status = "disabled"; 765 766 glink-edge { 767 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 768 label = "dsps"; 769 qcom,remote-pid = <3>; 770 mboxes = <&apss_shared 24>; 771 }; 772 }; 773 774 gpu: gpu@2c00000 { 775 /* 776 * note: the amd,imageon compatible makes it possible 777 * to use the drm/msm driver without the display node, 778 * make sure to remove it when display node is added 779 */ 780 compatible = "qcom,adreno-640.1", 781 "qcom,adreno", 782 "amd,imageon"; 783 #stream-id-cells = <16>; 784 785 reg = <0 0x02c00000 0 0x40000>; 786 reg-names = "kgsl_3d0_reg_memory"; 787 788 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 789 790 iommus = <&adreno_smmu 0 0x401>; 791 792 operating-points-v2 = <&gpu_opp_table>; 793 794 qcom,gmu = <&gmu>; 795 796 zap-shader { 797 memory-region = <&gpu_mem>; 798 }; 799 800 /* note: downstream checks gpu binning for 675 Mhz */ 801 gpu_opp_table: opp-table { 802 compatible = "operating-points-v2"; 803 804 opp-675000000 { 805 opp-hz = /bits/ 64 <675000000>; 806 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 807 }; 808 809 opp-585000000 { 810 opp-hz = /bits/ 64 <585000000>; 811 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 812 }; 813 814 opp-499200000 { 815 opp-hz = /bits/ 64 <499200000>; 816 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 817 }; 818 819 opp-427000000 { 820 opp-hz = /bits/ 64 <427000000>; 821 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 822 }; 823 824 opp-345000000 { 825 opp-hz = /bits/ 64 <345000000>; 826 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 827 }; 828 829 opp-257000000 { 830 opp-hz = /bits/ 64 <257000000>; 831 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 832 }; 833 }; 834 }; 835 836 gmu: gmu@2c6a000 { 837 compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 838 839 reg = <0 0x02c6a000 0 0x30000>, 840 <0 0x0b290000 0 0x10000>, 841 <0 0x0b490000 0 0x10000>; 842 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 843 844 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 846 interrupt-names = "hfi", "gmu"; 847 848 clocks = <&gpucc GPU_CC_AHB_CLK>, 849 <&gpucc GPU_CC_CX_GMU_CLK>, 850 <&gpucc GPU_CC_CXO_CLK>, 851 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 852 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 853 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 854 855 power-domains = <&gpucc GPU_CX_GDSC>, 856 <&gpucc GPU_GX_GDSC>; 857 power-domain-names = "cx", "gx"; 858 859 iommus = <&adreno_smmu 5 0x400>; 860 861 operating-points-v2 = <&gmu_opp_table>; 862 863 gmu_opp_table: opp-table { 864 compatible = "operating-points-v2"; 865 866 opp-200000000 { 867 opp-hz = /bits/ 64 <200000000>; 868 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 869 }; 870 }; 871 }; 872 873 gpucc: clock-controller@2c90000 { 874 compatible = "qcom,sm8150-gpucc"; 875 reg = <0 0x02c90000 0 0x9000>; 876 clocks = <&rpmhcc RPMH_CXO_CLK>, 877 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 878 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 879 clock-names = "bi_tcxo", 880 "gcc_gpu_gpll0_clk_src", 881 "gcc_gpu_gpll0_div_clk_src"; 882 #clock-cells = <1>; 883 #reset-cells = <1>; 884 #power-domain-cells = <1>; 885 }; 886 887 adreno_smmu: iommu@2ca0000 { 888 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 889 reg = <0 0x02ca0000 0 0x10000>; 890 #iommu-cells = <2>; 891 #global-interrupts = <1>; 892 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&gpucc GPU_CC_AHB_CLK>, 902 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 903 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 904 clock-names = "ahb", "bus", "iface"; 905 906 power-domains = <&gpucc GPU_CX_GDSC>; 907 }; 908 909 tlmm: pinctrl@3100000 { 910 compatible = "qcom,sm8150-pinctrl"; 911 reg = <0x0 0x03100000 0x0 0x300000>, 912 <0x0 0x03500000 0x0 0x300000>, 913 <0x0 0x03900000 0x0 0x300000>, 914 <0x0 0x03D00000 0x0 0x300000>; 915 reg-names = "west", "east", "north", "south"; 916 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 917 gpio-ranges = <&tlmm 0 0 175>; 918 gpio-controller; 919 #gpio-cells = <2>; 920 interrupt-controller; 921 #interrupt-cells = <2>; 922 }; 923 924 remoteproc_mpss: remoteproc@4080000 { 925 compatible = "qcom,sm8150-mpss-pas"; 926 reg = <0x0 0x04080000 0x0 0x4040>; 927 928 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 929 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 930 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 931 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 932 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 933 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 934 interrupt-names = "wdog", "fatal", "ready", "handover", 935 "stop-ack", "shutdown-ack"; 936 937 clocks = <&rpmhcc RPMH_CXO_CLK>; 938 clock-names = "xo"; 939 940 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, 941 <&rpmhpd 7>, 942 <&rpmhpd 0>; 943 power-domain-names = "load_state", "cx", "mss"; 944 945 memory-region = <&mpss_mem>; 946 947 qcom,smem-states = <&modem_smp2p_out 0>; 948 qcom,smem-state-names = "stop"; 949 950 glink-edge { 951 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 952 label = "modem"; 953 qcom,remote-pid = <1>; 954 mboxes = <&apss_shared 12>; 955 }; 956 }; 957 958 stm@6002000 { 959 compatible = "arm,coresight-stm", "arm,primecell"; 960 reg = <0 0x06002000 0 0x1000>, 961 <0 0x16280000 0 0x180000>; 962 reg-names = "stm-base", "stm-stimulus-base"; 963 964 clocks = <&aoss_qmp>; 965 clock-names = "apb_pclk"; 966 967 out-ports { 968 port { 969 stm_out: endpoint { 970 remote-endpoint = <&funnel0_in7>; 971 }; 972 }; 973 }; 974 }; 975 976 funnel@6041000 { 977 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 978 reg = <0 0x06041000 0 0x1000>; 979 980 clocks = <&aoss_qmp>; 981 clock-names = "apb_pclk"; 982 983 out-ports { 984 port { 985 funnel0_out: endpoint { 986 remote-endpoint = <&merge_funnel_in0>; 987 }; 988 }; 989 }; 990 991 in-ports { 992 #address-cells = <1>; 993 #size-cells = <0>; 994 995 port@7 { 996 reg = <7>; 997 funnel0_in7: endpoint { 998 remote-endpoint = <&stm_out>; 999 }; 1000 }; 1001 }; 1002 }; 1003 1004 funnel@6042000 { 1005 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1006 reg = <0 0x06042000 0 0x1000>; 1007 1008 clocks = <&aoss_qmp>; 1009 clock-names = "apb_pclk"; 1010 1011 out-ports { 1012 port { 1013 funnel1_out: endpoint { 1014 remote-endpoint = <&merge_funnel_in1>; 1015 }; 1016 }; 1017 }; 1018 1019 in-ports { 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 1023 port@4 { 1024 reg = <4>; 1025 funnel1_in4: endpoint { 1026 remote-endpoint = <&swao_replicator_out>; 1027 }; 1028 }; 1029 }; 1030 }; 1031 1032 funnel@6043000 { 1033 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1034 reg = <0 0x06043000 0 0x1000>; 1035 1036 clocks = <&aoss_qmp>; 1037 clock-names = "apb_pclk"; 1038 1039 out-ports { 1040 port { 1041 funnel2_out: endpoint { 1042 remote-endpoint = <&merge_funnel_in2>; 1043 }; 1044 }; 1045 }; 1046 1047 in-ports { 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 1051 port@2 { 1052 reg = <2>; 1053 funnel2_in2: endpoint { 1054 remote-endpoint = <&apss_merge_funnel_out>; 1055 }; 1056 }; 1057 }; 1058 }; 1059 1060 funnel@6045000 { 1061 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1062 reg = <0 0x06045000 0 0x1000>; 1063 1064 clocks = <&aoss_qmp>; 1065 clock-names = "apb_pclk"; 1066 1067 out-ports { 1068 port { 1069 merge_funnel_out: endpoint { 1070 remote-endpoint = <&etf_in>; 1071 }; 1072 }; 1073 }; 1074 1075 in-ports { 1076 #address-cells = <1>; 1077 #size-cells = <0>; 1078 1079 port@0 { 1080 reg = <0>; 1081 merge_funnel_in0: endpoint { 1082 remote-endpoint = <&funnel0_out>; 1083 }; 1084 }; 1085 1086 port@1 { 1087 reg = <1>; 1088 merge_funnel_in1: endpoint { 1089 remote-endpoint = <&funnel1_out>; 1090 }; 1091 }; 1092 1093 port@2 { 1094 reg = <2>; 1095 merge_funnel_in2: endpoint { 1096 remote-endpoint = <&funnel2_out>; 1097 }; 1098 }; 1099 }; 1100 }; 1101 1102 replicator@6046000 { 1103 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1104 reg = <0 0x06046000 0 0x1000>; 1105 1106 clocks = <&aoss_qmp>; 1107 clock-names = "apb_pclk"; 1108 1109 out-ports { 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 1113 port@0 { 1114 reg = <0>; 1115 replicator_out0: endpoint { 1116 remote-endpoint = <&etr_in>; 1117 }; 1118 }; 1119 1120 port@1 { 1121 reg = <1>; 1122 replicator_out1: endpoint { 1123 remote-endpoint = <&replicator1_in>; 1124 }; 1125 }; 1126 }; 1127 1128 in-ports { 1129 port { 1130 replicator_in0: endpoint { 1131 remote-endpoint = <&etf_out>; 1132 }; 1133 }; 1134 }; 1135 }; 1136 1137 etf@6047000 { 1138 compatible = "arm,coresight-tmc", "arm,primecell"; 1139 reg = <0 0x06047000 0 0x1000>; 1140 1141 clocks = <&aoss_qmp>; 1142 clock-names = "apb_pclk"; 1143 1144 out-ports { 1145 port { 1146 etf_out: endpoint { 1147 remote-endpoint = <&replicator_in0>; 1148 }; 1149 }; 1150 }; 1151 1152 in-ports { 1153 port { 1154 etf_in: endpoint { 1155 remote-endpoint = <&merge_funnel_out>; 1156 }; 1157 }; 1158 }; 1159 }; 1160 1161 etr@6048000 { 1162 compatible = "arm,coresight-tmc", "arm,primecell"; 1163 reg = <0 0x06048000 0 0x1000>; 1164 iommus = <&apps_smmu 0x05e0 0x0>; 1165 1166 clocks = <&aoss_qmp>; 1167 clock-names = "apb_pclk"; 1168 arm,scatter-gather; 1169 1170 in-ports { 1171 port { 1172 etr_in: endpoint { 1173 remote-endpoint = <&replicator_out0>; 1174 }; 1175 }; 1176 }; 1177 }; 1178 1179 replicator@604a000 { 1180 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1181 reg = <0 0x0604a000 0 0x1000>; 1182 1183 clocks = <&aoss_qmp>; 1184 clock-names = "apb_pclk"; 1185 1186 out-ports { 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 1190 port@1 { 1191 reg = <1>; 1192 replicator1_out: endpoint { 1193 remote-endpoint = <&swao_funnel_in>; 1194 }; 1195 }; 1196 }; 1197 1198 in-ports { 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 1202 port@1 { 1203 reg = <1>; 1204 replicator1_in: endpoint { 1205 remote-endpoint = <&replicator_out1>; 1206 }; 1207 }; 1208 }; 1209 }; 1210 1211 funnel@6b08000 { 1212 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1213 reg = <0 0x06b08000 0 0x1000>; 1214 1215 clocks = <&aoss_qmp>; 1216 clock-names = "apb_pclk"; 1217 1218 out-ports { 1219 port { 1220 swao_funnel_out: endpoint { 1221 remote-endpoint = <&swao_etf_in>; 1222 }; 1223 }; 1224 }; 1225 1226 in-ports { 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 1230 port@6 { 1231 reg = <6>; 1232 swao_funnel_in: endpoint { 1233 remote-endpoint = <&replicator1_out>; 1234 }; 1235 }; 1236 }; 1237 }; 1238 1239 etf@6b09000 { 1240 compatible = "arm,coresight-tmc", "arm,primecell"; 1241 reg = <0 0x06b09000 0 0x1000>; 1242 1243 clocks = <&aoss_qmp>; 1244 clock-names = "apb_pclk"; 1245 1246 out-ports { 1247 port { 1248 swao_etf_out: endpoint { 1249 remote-endpoint = <&swao_replicator_in>; 1250 }; 1251 }; 1252 }; 1253 1254 in-ports { 1255 port { 1256 swao_etf_in: endpoint { 1257 remote-endpoint = <&swao_funnel_out>; 1258 }; 1259 }; 1260 }; 1261 }; 1262 1263 replicator@6b0a000 { 1264 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1265 reg = <0 0x06b0a000 0 0x1000>; 1266 1267 clocks = <&aoss_qmp>; 1268 clock-names = "apb_pclk"; 1269 qcom,replicator-loses-context; 1270 1271 out-ports { 1272 port { 1273 swao_replicator_out: endpoint { 1274 remote-endpoint = <&funnel1_in4>; 1275 }; 1276 }; 1277 }; 1278 1279 in-ports { 1280 port { 1281 swao_replicator_in: endpoint { 1282 remote-endpoint = <&swao_etf_out>; 1283 }; 1284 }; 1285 }; 1286 }; 1287 1288 etm@7040000 { 1289 compatible = "arm,coresight-etm4x", "arm,primecell"; 1290 reg = <0 0x07040000 0 0x1000>; 1291 1292 cpu = <&CPU0>; 1293 1294 clocks = <&aoss_qmp>; 1295 clock-names = "apb_pclk"; 1296 arm,coresight-loses-context-with-cpu; 1297 qcom,skip-power-up; 1298 1299 out-ports { 1300 port { 1301 etm0_out: endpoint { 1302 remote-endpoint = <&apss_funnel_in0>; 1303 }; 1304 }; 1305 }; 1306 }; 1307 1308 etm@7140000 { 1309 compatible = "arm,coresight-etm4x", "arm,primecell"; 1310 reg = <0 0x07140000 0 0x1000>; 1311 1312 cpu = <&CPU1>; 1313 1314 clocks = <&aoss_qmp>; 1315 clock-names = "apb_pclk"; 1316 arm,coresight-loses-context-with-cpu; 1317 qcom,skip-power-up; 1318 1319 out-ports { 1320 port { 1321 etm1_out: endpoint { 1322 remote-endpoint = <&apss_funnel_in1>; 1323 }; 1324 }; 1325 }; 1326 }; 1327 1328 etm@7240000 { 1329 compatible = "arm,coresight-etm4x", "arm,primecell"; 1330 reg = <0 0x07240000 0 0x1000>; 1331 1332 cpu = <&CPU2>; 1333 1334 clocks = <&aoss_qmp>; 1335 clock-names = "apb_pclk"; 1336 arm,coresight-loses-context-with-cpu; 1337 qcom,skip-power-up; 1338 1339 out-ports { 1340 port { 1341 etm2_out: endpoint { 1342 remote-endpoint = <&apss_funnel_in2>; 1343 }; 1344 }; 1345 }; 1346 }; 1347 1348 etm@7340000 { 1349 compatible = "arm,coresight-etm4x", "arm,primecell"; 1350 reg = <0 0x07340000 0 0x1000>; 1351 1352 cpu = <&CPU3>; 1353 1354 clocks = <&aoss_qmp>; 1355 clock-names = "apb_pclk"; 1356 arm,coresight-loses-context-with-cpu; 1357 qcom,skip-power-up; 1358 1359 out-ports { 1360 port { 1361 etm3_out: endpoint { 1362 remote-endpoint = <&apss_funnel_in3>; 1363 }; 1364 }; 1365 }; 1366 }; 1367 1368 etm@7440000 { 1369 compatible = "arm,coresight-etm4x", "arm,primecell"; 1370 reg = <0 0x07440000 0 0x1000>; 1371 1372 cpu = <&CPU4>; 1373 1374 clocks = <&aoss_qmp>; 1375 clock-names = "apb_pclk"; 1376 arm,coresight-loses-context-with-cpu; 1377 qcom,skip-power-up; 1378 1379 out-ports { 1380 port { 1381 etm4_out: endpoint { 1382 remote-endpoint = <&apss_funnel_in4>; 1383 }; 1384 }; 1385 }; 1386 }; 1387 1388 etm@7540000 { 1389 compatible = "arm,coresight-etm4x", "arm,primecell"; 1390 reg = <0 0x07540000 0 0x1000>; 1391 1392 cpu = <&CPU5>; 1393 1394 clocks = <&aoss_qmp>; 1395 clock-names = "apb_pclk"; 1396 arm,coresight-loses-context-with-cpu; 1397 qcom,skip-power-up; 1398 1399 out-ports { 1400 port { 1401 etm5_out: endpoint { 1402 remote-endpoint = <&apss_funnel_in5>; 1403 }; 1404 }; 1405 }; 1406 }; 1407 1408 etm@7640000 { 1409 compatible = "arm,coresight-etm4x", "arm,primecell"; 1410 reg = <0 0x07640000 0 0x1000>; 1411 1412 cpu = <&CPU6>; 1413 1414 clocks = <&aoss_qmp>; 1415 clock-names = "apb_pclk"; 1416 arm,coresight-loses-context-with-cpu; 1417 qcom,skip-power-up; 1418 1419 out-ports { 1420 port { 1421 etm6_out: endpoint { 1422 remote-endpoint = <&apss_funnel_in6>; 1423 }; 1424 }; 1425 }; 1426 }; 1427 1428 etm@7740000 { 1429 compatible = "arm,coresight-etm4x", "arm,primecell"; 1430 reg = <0 0x07740000 0 0x1000>; 1431 1432 cpu = <&CPU7>; 1433 1434 clocks = <&aoss_qmp>; 1435 clock-names = "apb_pclk"; 1436 arm,coresight-loses-context-with-cpu; 1437 qcom,skip-power-up; 1438 1439 out-ports { 1440 port { 1441 etm7_out: endpoint { 1442 remote-endpoint = <&apss_funnel_in7>; 1443 }; 1444 }; 1445 }; 1446 }; 1447 1448 funnel@7800000 { /* APSS Funnel */ 1449 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1450 reg = <0 0x07800000 0 0x1000>; 1451 1452 clocks = <&aoss_qmp>; 1453 clock-names = "apb_pclk"; 1454 1455 out-ports { 1456 port { 1457 apss_funnel_out: endpoint { 1458 remote-endpoint = <&apss_merge_funnel_in>; 1459 }; 1460 }; 1461 }; 1462 1463 in-ports { 1464 #address-cells = <1>; 1465 #size-cells = <0>; 1466 1467 port@0 { 1468 reg = <0>; 1469 apss_funnel_in0: endpoint { 1470 remote-endpoint = <&etm0_out>; 1471 }; 1472 }; 1473 1474 port@1 { 1475 reg = <1>; 1476 apss_funnel_in1: endpoint { 1477 remote-endpoint = <&etm1_out>; 1478 }; 1479 }; 1480 1481 port@2 { 1482 reg = <2>; 1483 apss_funnel_in2: endpoint { 1484 remote-endpoint = <&etm2_out>; 1485 }; 1486 }; 1487 1488 port@3 { 1489 reg = <3>; 1490 apss_funnel_in3: endpoint { 1491 remote-endpoint = <&etm3_out>; 1492 }; 1493 }; 1494 1495 port@4 { 1496 reg = <4>; 1497 apss_funnel_in4: endpoint { 1498 remote-endpoint = <&etm4_out>; 1499 }; 1500 }; 1501 1502 port@5 { 1503 reg = <5>; 1504 apss_funnel_in5: endpoint { 1505 remote-endpoint = <&etm5_out>; 1506 }; 1507 }; 1508 1509 port@6 { 1510 reg = <6>; 1511 apss_funnel_in6: endpoint { 1512 remote-endpoint = <&etm6_out>; 1513 }; 1514 }; 1515 1516 port@7 { 1517 reg = <7>; 1518 apss_funnel_in7: endpoint { 1519 remote-endpoint = <&etm7_out>; 1520 }; 1521 }; 1522 }; 1523 }; 1524 1525 funnel@7810000 { 1526 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1527 reg = <0 0x07810000 0 0x1000>; 1528 1529 clocks = <&aoss_qmp>; 1530 clock-names = "apb_pclk"; 1531 1532 out-ports { 1533 port { 1534 apss_merge_funnel_out: endpoint { 1535 remote-endpoint = <&funnel2_in2>; 1536 }; 1537 }; 1538 }; 1539 1540 in-ports { 1541 port { 1542 apss_merge_funnel_in: endpoint { 1543 remote-endpoint = <&apss_funnel_out>; 1544 }; 1545 }; 1546 }; 1547 }; 1548 1549 remoteproc_cdsp: remoteproc@8300000 { 1550 compatible = "qcom,sm8150-cdsp-pas"; 1551 reg = <0x0 0x08300000 0x0 0x4040>; 1552 1553 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 1554 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1555 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1556 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1557 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1558 interrupt-names = "wdog", "fatal", "ready", 1559 "handover", "stop-ack"; 1560 1561 clocks = <&rpmhcc RPMH_CXO_CLK>; 1562 clock-names = "xo"; 1563 1564 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, 1565 <&rpmhpd 7>; 1566 power-domain-names = "load_state", "cx"; 1567 1568 memory-region = <&cdsp_mem>; 1569 1570 qcom,smem-states = <&cdsp_smp2p_out 0>; 1571 qcom,smem-state-names = "stop"; 1572 1573 status = "disabled"; 1574 1575 glink-edge { 1576 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 1577 label = "cdsp"; 1578 qcom,remote-pid = <5>; 1579 mboxes = <&apss_shared 4>; 1580 }; 1581 }; 1582 1583 usb_1_hsphy: phy@88e2000 { 1584 compatible = "qcom,sm8150-usb-hs-phy", 1585 "qcom,usb-snps-hs-7nm-phy"; 1586 reg = <0 0x088e2000 0 0x400>; 1587 status = "disabled"; 1588 #phy-cells = <0>; 1589 1590 clocks = <&rpmhcc RPMH_CXO_CLK>; 1591 clock-names = "ref"; 1592 1593 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1594 }; 1595 1596 usb_2_hsphy: phy@88e3000 { 1597 compatible = "qcom,sm8150-usb-hs-phy", 1598 "qcom,usb-snps-hs-7nm-phy"; 1599 reg = <0 0x088e3000 0 0x400>; 1600 status = "disabled"; 1601 #phy-cells = <0>; 1602 1603 clocks = <&rpmhcc RPMH_CXO_CLK>; 1604 clock-names = "ref"; 1605 1606 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1607 }; 1608 1609 usb_1_qmpphy: phy@88e9000 { 1610 compatible = "qcom,sm8150-qmp-usb3-phy"; 1611 reg = <0 0x088e9000 0 0x18c>, 1612 <0 0x088e8000 0 0x10>; 1613 reg-names = "reg-base", "dp_com"; 1614 status = "disabled"; 1615 #clock-cells = <1>; 1616 #address-cells = <2>; 1617 #size-cells = <2>; 1618 ranges; 1619 1620 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1621 <&rpmhcc RPMH_CXO_CLK>, 1622 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1623 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1624 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 1625 1626 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1627 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1628 reset-names = "phy", "common"; 1629 1630 usb_1_ssphy: lanes@88e9200 { 1631 reg = <0 0x088e9200 0 0x200>, 1632 <0 0x088e9400 0 0x200>, 1633 <0 0x088e9c00 0 0x218>, 1634 <0 0x088e9600 0 0x200>, 1635 <0 0x088e9800 0 0x200>, 1636 <0 0x088e9a00 0 0x100>; 1637 #phy-cells = <0>; 1638 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1639 clock-names = "pipe0"; 1640 clock-output-names = "usb3_phy_pipe_clk_src"; 1641 }; 1642 }; 1643 1644 dc_noc: interconnect@9160000 { 1645 compatible = "qcom,sm8150-dc-noc"; 1646 reg = <0 0x09160000 0 0x3200>; 1647 #interconnect-cells = <1>; 1648 qcom,bcm-voters = <&apps_bcm_voter>; 1649 }; 1650 1651 gem_noc: interconnect@9680000 { 1652 compatible = "qcom,sm8150-gem-noc"; 1653 reg = <0 0x09680000 0 0x3e200>; 1654 #interconnect-cells = <1>; 1655 qcom,bcm-voters = <&apps_bcm_voter>; 1656 }; 1657 1658 usb_2_qmpphy: phy@88eb000 { 1659 compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 1660 reg = <0 0x088eb000 0 0x200>; 1661 status = "disabled"; 1662 #clock-cells = <1>; 1663 #address-cells = <2>; 1664 #size-cells = <2>; 1665 ranges; 1666 1667 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 1668 <&rpmhcc RPMH_CXO_CLK>, 1669 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 1670 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 1671 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 1672 1673 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 1674 <&gcc GCC_USB3_PHY_SEC_BCR>; 1675 reset-names = "phy", "common"; 1676 1677 usb_2_ssphy: lane@88eb200 { 1678 reg = <0 0x088eb200 0 0x200>, 1679 <0 0x088eb400 0 0x200>, 1680 <0 0x088eb800 0 0x800>, 1681 <0 0x088eb600 0 0x200>; 1682 #phy-cells = <0>; 1683 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 1684 clock-names = "pipe0"; 1685 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 1686 }; 1687 }; 1688 1689 usb_1: usb@a6f8800 { 1690 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 1691 reg = <0 0x0a6f8800 0 0x400>; 1692 status = "disabled"; 1693 #address-cells = <2>; 1694 #size-cells = <2>; 1695 ranges; 1696 dma-ranges; 1697 1698 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1699 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1700 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1701 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1702 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1703 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 1704 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1705 "sleep", "xo"; 1706 1707 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1708 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1709 assigned-clock-rates = <19200000>, <200000000>; 1710 1711 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 1713 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 1714 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 1715 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1716 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1717 1718 power-domains = <&gcc USB30_PRIM_GDSC>; 1719 1720 resets = <&gcc GCC_USB30_PRIM_BCR>; 1721 1722 usb_1_dwc3: dwc3@a600000 { 1723 compatible = "snps,dwc3"; 1724 reg = <0 0x0a600000 0 0xcd00>; 1725 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1726 iommus = <&apps_smmu 0x140 0>; 1727 snps,dis_u2_susphy_quirk; 1728 snps,dis_enblslpm_quirk; 1729 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1730 phy-names = "usb2-phy", "usb3-phy"; 1731 }; 1732 }; 1733 1734 usb_2: usb@a8f8800 { 1735 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 1736 reg = <0 0x0a8f8800 0 0x400>; 1737 status = "disabled"; 1738 #address-cells = <2>; 1739 #size-cells = <2>; 1740 ranges; 1741 dma-ranges; 1742 1743 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1744 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1745 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1746 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1747 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 1748 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 1749 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1750 "sleep", "xo"; 1751 1752 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1753 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1754 assigned-clock-rates = <19200000>, <200000000>; 1755 1756 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 1760 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1761 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1762 1763 power-domains = <&gcc USB30_SEC_GDSC>; 1764 1765 resets = <&gcc GCC_USB30_SEC_BCR>; 1766 1767 usb_2_dwc3: dwc3@a800000 { 1768 compatible = "snps,dwc3"; 1769 reg = <0 0x0a800000 0 0xcd00>; 1770 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1771 iommus = <&apps_smmu 0x160 0>; 1772 snps,dis_u2_susphy_quirk; 1773 snps,dis_enblslpm_quirk; 1774 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 1775 phy-names = "usb2-phy", "usb3-phy"; 1776 }; 1777 }; 1778 1779 camnoc_virt: interconnect@ac00000 { 1780 compatible = "qcom,sm8150-camnoc-virt"; 1781 reg = <0 0x0ac00000 0 0x1000>; 1782 #interconnect-cells = <1>; 1783 qcom,bcm-voters = <&apps_bcm_voter>; 1784 }; 1785 1786 aoss_qmp: power-controller@c300000 { 1787 compatible = "qcom,sm8150-aoss-qmp"; 1788 reg = <0x0 0x0c300000 0x0 0x100000>; 1789 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 1790 mboxes = <&apss_shared 0>; 1791 1792 #clock-cells = <0>; 1793 #power-domain-cells = <1>; 1794 }; 1795 1796 tsens0: thermal-sensor@c263000 { 1797 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 1798 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1799 <0 0x0c222000 0 0x1ff>; /* SROT */ 1800 #qcom,sensors = <16>; 1801 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1803 interrupt-names = "uplow", "critical"; 1804 #thermal-sensor-cells = <1>; 1805 }; 1806 1807 tsens1: thermal-sensor@c265000 { 1808 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 1809 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1810 <0 0x0c223000 0 0x1ff>; /* SROT */ 1811 #qcom,sensors = <8>; 1812 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1814 interrupt-names = "uplow", "critical"; 1815 #thermal-sensor-cells = <1>; 1816 }; 1817 1818 spmi_bus: spmi@c440000 { 1819 compatible = "qcom,spmi-pmic-arb"; 1820 reg = <0x0 0x0c440000 0x0 0x0001100>, 1821 <0x0 0x0c600000 0x0 0x2000000>, 1822 <0x0 0x0e600000 0x0 0x0100000>, 1823 <0x0 0x0e700000 0x0 0x00a0000>, 1824 <0x0 0x0c40a000 0x0 0x0026000>; 1825 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1826 interrupt-names = "periph_irq"; 1827 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 1828 qcom,ee = <0>; 1829 qcom,channel = <0>; 1830 #address-cells = <2>; 1831 #size-cells = <0>; 1832 interrupt-controller; 1833 #interrupt-cells = <4>; 1834 cell-index = <0>; 1835 }; 1836 1837 apps_smmu: iommu@15000000 { 1838 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 1839 reg = <0 0x15000000 0 0x100000>; 1840 #iommu-cells = <2>; 1841 #global-interrupts = <1>; 1842 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1909 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1910 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1911 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1912 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1913 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1914 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1915 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1917 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1920 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 1923 }; 1924 1925 remoteproc_adsp: remoteproc@17300000 { 1926 compatible = "qcom,sm8150-adsp-pas"; 1927 reg = <0x0 0x17300000 0x0 0x4040>; 1928 1929 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 1930 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1931 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1932 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1933 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1934 interrupt-names = "wdog", "fatal", "ready", 1935 "handover", "stop-ack"; 1936 1937 clocks = <&rpmhcc RPMH_CXO_CLK>; 1938 clock-names = "xo"; 1939 1940 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, 1941 <&rpmhpd 7>; 1942 power-domain-names = "load_state", "cx"; 1943 1944 memory-region = <&adsp_mem>; 1945 1946 qcom,smem-states = <&adsp_smp2p_out 0>; 1947 qcom,smem-state-names = "stop"; 1948 1949 status = "disabled"; 1950 1951 glink-edge { 1952 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 1953 label = "lpass"; 1954 qcom,remote-pid = <2>; 1955 mboxes = <&apss_shared 8>; 1956 }; 1957 }; 1958 1959 intc: interrupt-controller@17a00000 { 1960 compatible = "arm,gic-v3"; 1961 interrupt-controller; 1962 #interrupt-cells = <3>; 1963 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 1964 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 1965 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1966 }; 1967 1968 apss_shared: mailbox@17c00000 { 1969 compatible = "qcom,sm8150-apss-shared"; 1970 reg = <0x0 0x17c00000 0x0 0x1000>; 1971 #mbox-cells = <1>; 1972 }; 1973 1974 watchdog@17c10000 { 1975 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 1976 reg = <0 0x17c10000 0 0x1000>; 1977 clocks = <&sleep_clk>; 1978 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1979 }; 1980 1981 timer@17c20000 { 1982 #address-cells = <2>; 1983 #size-cells = <2>; 1984 ranges; 1985 compatible = "arm,armv7-timer-mem"; 1986 reg = <0x0 0x17c20000 0x0 0x1000>; 1987 clock-frequency = <19200000>; 1988 1989 frame@17c21000{ 1990 frame-number = <0>; 1991 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1993 reg = <0x0 0x17c21000 0x0 0x1000>, 1994 <0x0 0x17c22000 0x0 0x1000>; 1995 }; 1996 1997 frame@17c23000 { 1998 frame-number = <1>; 1999 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2000 reg = <0x0 0x17c23000 0x0 0x1000>; 2001 status = "disabled"; 2002 }; 2003 2004 frame@17c25000 { 2005 frame-number = <2>; 2006 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2007 reg = <0x0 0x17c25000 0x0 0x1000>; 2008 status = "disabled"; 2009 }; 2010 2011 frame@17c27000 { 2012 frame-number = <3>; 2013 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2014 reg = <0x0 0x17c26000 0x0 0x1000>; 2015 status = "disabled"; 2016 }; 2017 2018 frame@17c29000 { 2019 frame-number = <4>; 2020 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2021 reg = <0x0 0x17c29000 0x0 0x1000>; 2022 status = "disabled"; 2023 }; 2024 2025 frame@17c2b000 { 2026 frame-number = <5>; 2027 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2028 reg = <0x0 0x17c2b000 0x0 0x1000>; 2029 status = "disabled"; 2030 }; 2031 2032 frame@17c2d000 { 2033 frame-number = <6>; 2034 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2035 reg = <0x0 0x17c2d000 0x0 0x1000>; 2036 status = "disabled"; 2037 }; 2038 }; 2039 2040 apps_rsc: rsc@18200000 { 2041 label = "apps_rsc"; 2042 compatible = "qcom,rpmh-rsc"; 2043 reg = <0x0 0x18200000 0x0 0x10000>, 2044 <0x0 0x18210000 0x0 0x10000>, 2045 <0x0 0x18220000 0x0 0x10000>; 2046 reg-names = "drv-0", "drv-1", "drv-2"; 2047 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2048 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2050 qcom,tcs-offset = <0xd00>; 2051 qcom,drv-id = <2>; 2052 qcom,tcs-config = <ACTIVE_TCS 2>, 2053 <SLEEP_TCS 1>, 2054 <WAKE_TCS 1>, 2055 <CONTROL_TCS 0>; 2056 2057 rpmhcc: clock-controller { 2058 compatible = "qcom,sm8150-rpmh-clk"; 2059 #clock-cells = <1>; 2060 clock-names = "xo"; 2061 clocks = <&xo_board>; 2062 }; 2063 2064 rpmhpd: power-controller { 2065 compatible = "qcom,sm8150-rpmhpd"; 2066 #power-domain-cells = <1>; 2067 operating-points-v2 = <&rpmhpd_opp_table>; 2068 2069 rpmhpd_opp_table: opp-table { 2070 compatible = "operating-points-v2"; 2071 2072 rpmhpd_opp_ret: opp1 { 2073 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2074 }; 2075 2076 rpmhpd_opp_min_svs: opp2 { 2077 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2078 }; 2079 2080 rpmhpd_opp_low_svs: opp3 { 2081 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2082 }; 2083 2084 rpmhpd_opp_svs: opp4 { 2085 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2086 }; 2087 2088 rpmhpd_opp_svs_l1: opp5 { 2089 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2090 }; 2091 2092 rpmhpd_opp_svs_l2: opp6 { 2093 opp-level = <224>; 2094 }; 2095 2096 rpmhpd_opp_nom: opp7 { 2097 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2098 }; 2099 2100 rpmhpd_opp_nom_l1: opp8 { 2101 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2102 }; 2103 2104 rpmhpd_opp_nom_l2: opp9 { 2105 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2106 }; 2107 2108 rpmhpd_opp_turbo: opp10 { 2109 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2110 }; 2111 2112 rpmhpd_opp_turbo_l1: opp11 { 2113 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2114 }; 2115 }; 2116 }; 2117 2118 apps_bcm_voter: bcm_voter { 2119 compatible = "qcom,bcm-voter"; 2120 }; 2121 }; 2122 2123 osm_l3: interconnect@18321000 { 2124 compatible = "qcom,sm8150-osm-l3"; 2125 reg = <0 0x18321000 0 0x1400>; 2126 2127 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2128 clock-names = "xo", "alternate"; 2129 2130 #interconnect-cells = <1>; 2131 }; 2132 2133 cpufreq_hw: cpufreq@18323000 { 2134 compatible = "qcom,cpufreq-hw"; 2135 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 2136 <0 0x18327800 0 0x1400>; 2137 reg-names = "freq-domain0", "freq-domain1", 2138 "freq-domain2"; 2139 2140 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2141 clock-names = "xo", "alternate"; 2142 2143 #freq-domain-cells = <1>; 2144 }; 2145 2146 wifi: wifi@18800000 { 2147 compatible = "qcom,wcn3990-wifi"; 2148 reg = <0 0x18800000 0 0x800000>; 2149 reg-names = "membase"; 2150 memory-region = <&wlan_mem>; 2151 clock-names = "cxo_ref_clk_pin", "qdss"; 2152 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 2153 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2155 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2157 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2158 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2159 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2160 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2161 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2162 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2163 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2164 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2165 iommus = <&apps_smmu 0x0640 0x1>; 2166 status = "disabled"; 2167 }; 2168 }; 2169 2170 timer { 2171 compatible = "arm,armv8-timer"; 2172 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 2173 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 2174 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 2175 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 2176 }; 2177 2178 thermal-zones { 2179 cpu0-thermal { 2180 polling-delay-passive = <250>; 2181 polling-delay = <1000>; 2182 2183 thermal-sensors = <&tsens0 1>; 2184 2185 trips { 2186 cpu0_alert0: trip-point0 { 2187 temperature = <90000>; 2188 hysteresis = <2000>; 2189 type = "passive"; 2190 }; 2191 2192 cpu0_alert1: trip-point1 { 2193 temperature = <95000>; 2194 hysteresis = <2000>; 2195 type = "passive"; 2196 }; 2197 2198 cpu0_crit: cpu_crit { 2199 temperature = <110000>; 2200 hysteresis = <1000>; 2201 type = "critical"; 2202 }; 2203 }; 2204 2205 cooling-maps { 2206 map0 { 2207 trip = <&cpu0_alert0>; 2208 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2209 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2210 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2211 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2212 }; 2213 map1 { 2214 trip = <&cpu0_alert1>; 2215 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2216 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2217 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2218 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2219 }; 2220 }; 2221 }; 2222 2223 cpu1-thermal { 2224 polling-delay-passive = <250>; 2225 polling-delay = <1000>; 2226 2227 thermal-sensors = <&tsens0 2>; 2228 2229 trips { 2230 cpu1_alert0: trip-point0 { 2231 temperature = <90000>; 2232 hysteresis = <2000>; 2233 type = "passive"; 2234 }; 2235 2236 cpu1_alert1: trip-point1 { 2237 temperature = <95000>; 2238 hysteresis = <2000>; 2239 type = "passive"; 2240 }; 2241 2242 cpu1_crit: cpu_crit { 2243 temperature = <110000>; 2244 hysteresis = <1000>; 2245 type = "critical"; 2246 }; 2247 }; 2248 2249 cooling-maps { 2250 map0 { 2251 trip = <&cpu1_alert0>; 2252 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2253 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2254 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2255 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2256 }; 2257 map1 { 2258 trip = <&cpu1_alert1>; 2259 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2260 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2261 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2262 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2263 }; 2264 }; 2265 }; 2266 2267 cpu2-thermal { 2268 polling-delay-passive = <250>; 2269 polling-delay = <1000>; 2270 2271 thermal-sensors = <&tsens0 3>; 2272 2273 trips { 2274 cpu2_alert0: trip-point0 { 2275 temperature = <90000>; 2276 hysteresis = <2000>; 2277 type = "passive"; 2278 }; 2279 2280 cpu2_alert1: trip-point1 { 2281 temperature = <95000>; 2282 hysteresis = <2000>; 2283 type = "passive"; 2284 }; 2285 2286 cpu2_crit: cpu_crit { 2287 temperature = <110000>; 2288 hysteresis = <1000>; 2289 type = "critical"; 2290 }; 2291 }; 2292 2293 cooling-maps { 2294 map0 { 2295 trip = <&cpu2_alert0>; 2296 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2297 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2298 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2299 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2300 }; 2301 map1 { 2302 trip = <&cpu2_alert1>; 2303 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2304 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2305 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2306 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2307 }; 2308 }; 2309 }; 2310 2311 cpu3-thermal { 2312 polling-delay-passive = <250>; 2313 polling-delay = <1000>; 2314 2315 thermal-sensors = <&tsens0 4>; 2316 2317 trips { 2318 cpu3_alert0: trip-point0 { 2319 temperature = <90000>; 2320 hysteresis = <2000>; 2321 type = "passive"; 2322 }; 2323 2324 cpu3_alert1: trip-point1 { 2325 temperature = <95000>; 2326 hysteresis = <2000>; 2327 type = "passive"; 2328 }; 2329 2330 cpu3_crit: cpu_crit { 2331 temperature = <110000>; 2332 hysteresis = <1000>; 2333 type = "critical"; 2334 }; 2335 }; 2336 2337 cooling-maps { 2338 map0 { 2339 trip = <&cpu3_alert0>; 2340 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2341 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2342 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2343 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2344 }; 2345 map1 { 2346 trip = <&cpu3_alert1>; 2347 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2348 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2349 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2350 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2351 }; 2352 }; 2353 }; 2354 2355 cpu4-top-thermal { 2356 polling-delay-passive = <250>; 2357 polling-delay = <1000>; 2358 2359 thermal-sensors = <&tsens0 7>; 2360 2361 trips { 2362 cpu4_top_alert0: trip-point0 { 2363 temperature = <90000>; 2364 hysteresis = <2000>; 2365 type = "passive"; 2366 }; 2367 2368 cpu4_top_alert1: trip-point1 { 2369 temperature = <95000>; 2370 hysteresis = <2000>; 2371 type = "passive"; 2372 }; 2373 2374 cpu4_top_crit: cpu_crit { 2375 temperature = <110000>; 2376 hysteresis = <1000>; 2377 type = "critical"; 2378 }; 2379 }; 2380 2381 cooling-maps { 2382 map0 { 2383 trip = <&cpu4_top_alert0>; 2384 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2385 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2386 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2387 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2388 }; 2389 map1 { 2390 trip = <&cpu4_top_alert1>; 2391 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2392 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2393 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2394 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2395 }; 2396 }; 2397 }; 2398 2399 cpu5-top-thermal { 2400 polling-delay-passive = <250>; 2401 polling-delay = <1000>; 2402 2403 thermal-sensors = <&tsens0 8>; 2404 2405 trips { 2406 cpu5_top_alert0: trip-point0 { 2407 temperature = <90000>; 2408 hysteresis = <2000>; 2409 type = "passive"; 2410 }; 2411 2412 cpu5_top_alert1: trip-point1 { 2413 temperature = <95000>; 2414 hysteresis = <2000>; 2415 type = "passive"; 2416 }; 2417 2418 cpu5_top_crit: cpu_crit { 2419 temperature = <110000>; 2420 hysteresis = <1000>; 2421 type = "critical"; 2422 }; 2423 }; 2424 2425 cooling-maps { 2426 map0 { 2427 trip = <&cpu5_top_alert0>; 2428 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2429 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2430 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2431 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2432 }; 2433 map1 { 2434 trip = <&cpu5_top_alert1>; 2435 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2436 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2437 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2438 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2439 }; 2440 }; 2441 }; 2442 2443 cpu6-top-thermal { 2444 polling-delay-passive = <250>; 2445 polling-delay = <1000>; 2446 2447 thermal-sensors = <&tsens0 9>; 2448 2449 trips { 2450 cpu6_top_alert0: trip-point0 { 2451 temperature = <90000>; 2452 hysteresis = <2000>; 2453 type = "passive"; 2454 }; 2455 2456 cpu6_top_alert1: trip-point1 { 2457 temperature = <95000>; 2458 hysteresis = <2000>; 2459 type = "passive"; 2460 }; 2461 2462 cpu6_top_crit: cpu_crit { 2463 temperature = <110000>; 2464 hysteresis = <1000>; 2465 type = "critical"; 2466 }; 2467 }; 2468 2469 cooling-maps { 2470 map0 { 2471 trip = <&cpu6_top_alert0>; 2472 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2473 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2474 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2475 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2476 }; 2477 map1 { 2478 trip = <&cpu6_top_alert1>; 2479 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2480 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2481 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2482 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2483 }; 2484 }; 2485 }; 2486 2487 cpu7-top-thermal { 2488 polling-delay-passive = <250>; 2489 polling-delay = <1000>; 2490 2491 thermal-sensors = <&tsens0 10>; 2492 2493 trips { 2494 cpu7_top_alert0: trip-point0 { 2495 temperature = <90000>; 2496 hysteresis = <2000>; 2497 type = "passive"; 2498 }; 2499 2500 cpu7_top_alert1: trip-point1 { 2501 temperature = <95000>; 2502 hysteresis = <2000>; 2503 type = "passive"; 2504 }; 2505 2506 cpu7_top_crit: cpu_crit { 2507 temperature = <110000>; 2508 hysteresis = <1000>; 2509 type = "critical"; 2510 }; 2511 }; 2512 2513 cooling-maps { 2514 map0 { 2515 trip = <&cpu7_top_alert0>; 2516 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2517 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2518 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2519 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2520 }; 2521 map1 { 2522 trip = <&cpu7_top_alert1>; 2523 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2524 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2525 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2526 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2527 }; 2528 }; 2529 }; 2530 2531 cpu4-bottom-thermal { 2532 polling-delay-passive = <250>; 2533 polling-delay = <1000>; 2534 2535 thermal-sensors = <&tsens0 11>; 2536 2537 trips { 2538 cpu4_bottom_alert0: trip-point0 { 2539 temperature = <90000>; 2540 hysteresis = <2000>; 2541 type = "passive"; 2542 }; 2543 2544 cpu4_bottom_alert1: trip-point1 { 2545 temperature = <95000>; 2546 hysteresis = <2000>; 2547 type = "passive"; 2548 }; 2549 2550 cpu4_bottom_crit: cpu_crit { 2551 temperature = <110000>; 2552 hysteresis = <1000>; 2553 type = "critical"; 2554 }; 2555 }; 2556 2557 cooling-maps { 2558 map0 { 2559 trip = <&cpu4_bottom_alert0>; 2560 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2561 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2562 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2563 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2564 }; 2565 map1 { 2566 trip = <&cpu4_bottom_alert1>; 2567 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2568 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2569 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2570 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2571 }; 2572 }; 2573 }; 2574 2575 cpu5-bottom-thermal { 2576 polling-delay-passive = <250>; 2577 polling-delay = <1000>; 2578 2579 thermal-sensors = <&tsens0 12>; 2580 2581 trips { 2582 cpu5_bottom_alert0: trip-point0 { 2583 temperature = <90000>; 2584 hysteresis = <2000>; 2585 type = "passive"; 2586 }; 2587 2588 cpu5_bottom_alert1: trip-point1 { 2589 temperature = <95000>; 2590 hysteresis = <2000>; 2591 type = "passive"; 2592 }; 2593 2594 cpu5_bottom_crit: cpu_crit { 2595 temperature = <110000>; 2596 hysteresis = <1000>; 2597 type = "critical"; 2598 }; 2599 }; 2600 2601 cooling-maps { 2602 map0 { 2603 trip = <&cpu5_bottom_alert0>; 2604 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2605 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2606 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2607 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2608 }; 2609 map1 { 2610 trip = <&cpu5_bottom_alert1>; 2611 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2612 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2613 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2614 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2615 }; 2616 }; 2617 }; 2618 2619 cpu6-bottom-thermal { 2620 polling-delay-passive = <250>; 2621 polling-delay = <1000>; 2622 2623 thermal-sensors = <&tsens0 13>; 2624 2625 trips { 2626 cpu6_bottom_alert0: trip-point0 { 2627 temperature = <90000>; 2628 hysteresis = <2000>; 2629 type = "passive"; 2630 }; 2631 2632 cpu6_bottom_alert1: trip-point1 { 2633 temperature = <95000>; 2634 hysteresis = <2000>; 2635 type = "passive"; 2636 }; 2637 2638 cpu6_bottom_crit: cpu_crit { 2639 temperature = <110000>; 2640 hysteresis = <1000>; 2641 type = "critical"; 2642 }; 2643 }; 2644 2645 cooling-maps { 2646 map0 { 2647 trip = <&cpu6_bottom_alert0>; 2648 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2649 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2650 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2651 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2652 }; 2653 map1 { 2654 trip = <&cpu6_bottom_alert1>; 2655 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2656 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2657 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2658 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2659 }; 2660 }; 2661 }; 2662 2663 cpu7-bottom-thermal { 2664 polling-delay-passive = <250>; 2665 polling-delay = <1000>; 2666 2667 thermal-sensors = <&tsens0 14>; 2668 2669 trips { 2670 cpu7_bottom_alert0: trip-point0 { 2671 temperature = <90000>; 2672 hysteresis = <2000>; 2673 type = "passive"; 2674 }; 2675 2676 cpu7_bottom_alert1: trip-point1 { 2677 temperature = <95000>; 2678 hysteresis = <2000>; 2679 type = "passive"; 2680 }; 2681 2682 cpu7_bottom_crit: cpu_crit { 2683 temperature = <110000>; 2684 hysteresis = <1000>; 2685 type = "critical"; 2686 }; 2687 }; 2688 2689 cooling-maps { 2690 map0 { 2691 trip = <&cpu7_bottom_alert0>; 2692 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2693 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2694 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2695 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2696 }; 2697 map1 { 2698 trip = <&cpu7_bottom_alert1>; 2699 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2700 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2701 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2702 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2703 }; 2704 }; 2705 }; 2706 2707 aoss0-thermal { 2708 polling-delay-passive = <250>; 2709 polling-delay = <1000>; 2710 2711 thermal-sensors = <&tsens0 0>; 2712 2713 trips { 2714 aoss0_alert0: trip-point0 { 2715 temperature = <90000>; 2716 hysteresis = <2000>; 2717 type = "hot"; 2718 }; 2719 }; 2720 }; 2721 2722 cluster0-thermal { 2723 polling-delay-passive = <250>; 2724 polling-delay = <1000>; 2725 2726 thermal-sensors = <&tsens0 5>; 2727 2728 trips { 2729 cluster0_alert0: trip-point0 { 2730 temperature = <90000>; 2731 hysteresis = <2000>; 2732 type = "hot"; 2733 }; 2734 cluster0_crit: cluster0_crit { 2735 temperature = <110000>; 2736 hysteresis = <2000>; 2737 type = "critical"; 2738 }; 2739 }; 2740 }; 2741 2742 cluster1-thermal { 2743 polling-delay-passive = <250>; 2744 polling-delay = <1000>; 2745 2746 thermal-sensors = <&tsens0 6>; 2747 2748 trips { 2749 cluster1_alert0: trip-point0 { 2750 temperature = <90000>; 2751 hysteresis = <2000>; 2752 type = "hot"; 2753 }; 2754 cluster1_crit: cluster1_crit { 2755 temperature = <110000>; 2756 hysteresis = <2000>; 2757 type = "critical"; 2758 }; 2759 }; 2760 }; 2761 2762 gpu-thermal-top { 2763 polling-delay-passive = <250>; 2764 polling-delay = <1000>; 2765 2766 thermal-sensors = <&tsens0 15>; 2767 2768 trips { 2769 gpu1_alert0: trip-point0 { 2770 temperature = <90000>; 2771 hysteresis = <2000>; 2772 type = "hot"; 2773 }; 2774 }; 2775 }; 2776 2777 aoss1-thermal { 2778 polling-delay-passive = <250>; 2779 polling-delay = <1000>; 2780 2781 thermal-sensors = <&tsens1 0>; 2782 2783 trips { 2784 aoss1_alert0: trip-point0 { 2785 temperature = <90000>; 2786 hysteresis = <2000>; 2787 type = "hot"; 2788 }; 2789 }; 2790 }; 2791 2792 wlan-thermal { 2793 polling-delay-passive = <250>; 2794 polling-delay = <1000>; 2795 2796 thermal-sensors = <&tsens1 1>; 2797 2798 trips { 2799 wlan_alert0: trip-point0 { 2800 temperature = <90000>; 2801 hysteresis = <2000>; 2802 type = "hot"; 2803 }; 2804 }; 2805 }; 2806 2807 video-thermal { 2808 polling-delay-passive = <250>; 2809 polling-delay = <1000>; 2810 2811 thermal-sensors = <&tsens1 2>; 2812 2813 trips { 2814 video_alert0: trip-point0 { 2815 temperature = <90000>; 2816 hysteresis = <2000>; 2817 type = "hot"; 2818 }; 2819 }; 2820 }; 2821 2822 mem-thermal { 2823 polling-delay-passive = <250>; 2824 polling-delay = <1000>; 2825 2826 thermal-sensors = <&tsens1 3>; 2827 2828 trips { 2829 mem_alert0: trip-point0 { 2830 temperature = <90000>; 2831 hysteresis = <2000>; 2832 type = "hot"; 2833 }; 2834 }; 2835 }; 2836 2837 q6-hvx-thermal { 2838 polling-delay-passive = <250>; 2839 polling-delay = <1000>; 2840 2841 thermal-sensors = <&tsens1 4>; 2842 2843 trips { 2844 q6_hvx_alert0: trip-point0 { 2845 temperature = <90000>; 2846 hysteresis = <2000>; 2847 type = "hot"; 2848 }; 2849 }; 2850 }; 2851 2852 camera-thermal { 2853 polling-delay-passive = <250>; 2854 polling-delay = <1000>; 2855 2856 thermal-sensors = <&tsens1 5>; 2857 2858 trips { 2859 camera_alert0: trip-point0 { 2860 temperature = <90000>; 2861 hysteresis = <2000>; 2862 type = "hot"; 2863 }; 2864 }; 2865 }; 2866 2867 compute-thermal { 2868 polling-delay-passive = <250>; 2869 polling-delay = <1000>; 2870 2871 thermal-sensors = <&tsens1 6>; 2872 2873 trips { 2874 compute_alert0: trip-point0 { 2875 temperature = <90000>; 2876 hysteresis = <2000>; 2877 type = "hot"; 2878 }; 2879 }; 2880 }; 2881 2882 modem-thermal { 2883 polling-delay-passive = <250>; 2884 polling-delay = <1000>; 2885 2886 thermal-sensors = <&tsens1 7>; 2887 2888 trips { 2889 modem_alert0: trip-point0 { 2890 temperature = <90000>; 2891 hysteresis = <2000>; 2892 type = "hot"; 2893 }; 2894 }; 2895 }; 2896 2897 npu-thermal { 2898 polling-delay-passive = <250>; 2899 polling-delay = <1000>; 2900 2901 thermal-sensors = <&tsens1 8>; 2902 2903 trips { 2904 npu_alert0: trip-point0 { 2905 temperature = <90000>; 2906 hysteresis = <2000>; 2907 type = "hot"; 2908 }; 2909 }; 2910 }; 2911 2912 modem-vec-thermal { 2913 polling-delay-passive = <250>; 2914 polling-delay = <1000>; 2915 2916 thermal-sensors = <&tsens1 9>; 2917 2918 trips { 2919 modem_vec_alert0: trip-point0 { 2920 temperature = <90000>; 2921 hysteresis = <2000>; 2922 type = "hot"; 2923 }; 2924 }; 2925 }; 2926 2927 modem-scl-thermal { 2928 polling-delay-passive = <250>; 2929 polling-delay = <1000>; 2930 2931 thermal-sensors = <&tsens1 10>; 2932 2933 trips { 2934 modem_scl_alert0: trip-point0 { 2935 temperature = <90000>; 2936 hysteresis = <2000>; 2937 type = "hot"; 2938 }; 2939 }; 2940 }; 2941 2942 gpu-thermal-bottom { 2943 polling-delay-passive = <250>; 2944 polling-delay = <1000>; 2945 2946 thermal-sensors = <&tsens1 11>; 2947 2948 trips { 2949 gpu2_alert0: trip-point0 { 2950 temperature = <90000>; 2951 hysteresis = <2000>; 2952 type = "hot"; 2953 }; 2954 }; 2955 }; 2956 }; 2957}; 2958