1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/dma/qcom-gpi.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,gcc-sm8150.h> 13#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sm8150.h> 16#include <dt-bindings/thermal/thermal.h> 17 18/ { 19 interrupt-parent = <&intc>; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 chosen { }; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <38400000>; 31 clock-output-names = "xo_board"; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32764>; 38 clock-output-names = "sleep_clk"; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "qcom,kryo485"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 capacity-dmips-mhz = <488>; 52 dynamic-power-coefficient = <232>; 53 next-level-cache = <&L2_0>; 54 qcom,freq-domain = <&cpufreq_hw 0>; 55 operating-points-v2 = <&cpu0_opp_table>; 56 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 57 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 58 power-domains = <&CPU_PD0>; 59 power-domain-names = "psci"; 60 #cooling-cells = <2>; 61 L2_0: l2-cache { 62 compatible = "cache"; 63 next-level-cache = <&L3_0>; 64 L3_0: l3-cache { 65 compatible = "cache"; 66 }; 67 }; 68 }; 69 70 CPU1: cpu@100 { 71 device_type = "cpu"; 72 compatible = "qcom,kryo485"; 73 reg = <0x0 0x100>; 74 enable-method = "psci"; 75 capacity-dmips-mhz = <488>; 76 dynamic-power-coefficient = <232>; 77 next-level-cache = <&L2_100>; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 operating-points-v2 = <&cpu0_opp_table>; 80 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 81 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 82 power-domains = <&CPU_PD1>; 83 power-domain-names = "psci"; 84 #cooling-cells = <2>; 85 L2_100: l2-cache { 86 compatible = "cache"; 87 next-level-cache = <&L3_0>; 88 }; 89 90 }; 91 92 CPU2: cpu@200 { 93 device_type = "cpu"; 94 compatible = "qcom,kryo485"; 95 reg = <0x0 0x200>; 96 enable-method = "psci"; 97 capacity-dmips-mhz = <488>; 98 dynamic-power-coefficient = <232>; 99 next-level-cache = <&L2_200>; 100 qcom,freq-domain = <&cpufreq_hw 0>; 101 operating-points-v2 = <&cpu0_opp_table>; 102 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 103 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 104 power-domains = <&CPU_PD2>; 105 power-domain-names = "psci"; 106 #cooling-cells = <2>; 107 L2_200: l2-cache { 108 compatible = "cache"; 109 next-level-cache = <&L3_0>; 110 }; 111 }; 112 113 CPU3: cpu@300 { 114 device_type = "cpu"; 115 compatible = "qcom,kryo485"; 116 reg = <0x0 0x300>; 117 enable-method = "psci"; 118 capacity-dmips-mhz = <488>; 119 dynamic-power-coefficient = <232>; 120 next-level-cache = <&L2_300>; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 operating-points-v2 = <&cpu0_opp_table>; 123 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 124 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 125 power-domains = <&CPU_PD3>; 126 power-domain-names = "psci"; 127 #cooling-cells = <2>; 128 L2_300: l2-cache { 129 compatible = "cache"; 130 next-level-cache = <&L3_0>; 131 }; 132 }; 133 134 CPU4: cpu@400 { 135 device_type = "cpu"; 136 compatible = "qcom,kryo485"; 137 reg = <0x0 0x400>; 138 enable-method = "psci"; 139 capacity-dmips-mhz = <1024>; 140 dynamic-power-coefficient = <369>; 141 next-level-cache = <&L2_400>; 142 qcom,freq-domain = <&cpufreq_hw 1>; 143 operating-points-v2 = <&cpu4_opp_table>; 144 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 145 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 146 power-domains = <&CPU_PD4>; 147 power-domain-names = "psci"; 148 #cooling-cells = <2>; 149 L2_400: l2-cache { 150 compatible = "cache"; 151 next-level-cache = <&L3_0>; 152 }; 153 }; 154 155 CPU5: cpu@500 { 156 device_type = "cpu"; 157 compatible = "qcom,kryo485"; 158 reg = <0x0 0x500>; 159 enable-method = "psci"; 160 capacity-dmips-mhz = <1024>; 161 dynamic-power-coefficient = <369>; 162 next-level-cache = <&L2_500>; 163 qcom,freq-domain = <&cpufreq_hw 1>; 164 operating-points-v2 = <&cpu4_opp_table>; 165 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 166 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 167 power-domains = <&CPU_PD5>; 168 power-domain-names = "psci"; 169 #cooling-cells = <2>; 170 L2_500: l2-cache { 171 compatible = "cache"; 172 next-level-cache = <&L3_0>; 173 }; 174 }; 175 176 CPU6: cpu@600 { 177 device_type = "cpu"; 178 compatible = "qcom,kryo485"; 179 reg = <0x0 0x600>; 180 enable-method = "psci"; 181 capacity-dmips-mhz = <1024>; 182 dynamic-power-coefficient = <369>; 183 next-level-cache = <&L2_600>; 184 qcom,freq-domain = <&cpufreq_hw 1>; 185 operating-points-v2 = <&cpu4_opp_table>; 186 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 187 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 188 power-domains = <&CPU_PD6>; 189 power-domain-names = "psci"; 190 #cooling-cells = <2>; 191 L2_600: l2-cache { 192 compatible = "cache"; 193 next-level-cache = <&L3_0>; 194 }; 195 }; 196 197 CPU7: cpu@700 { 198 device_type = "cpu"; 199 compatible = "qcom,kryo485"; 200 reg = <0x0 0x700>; 201 enable-method = "psci"; 202 capacity-dmips-mhz = <1024>; 203 dynamic-power-coefficient = <421>; 204 next-level-cache = <&L2_700>; 205 qcom,freq-domain = <&cpufreq_hw 2>; 206 operating-points-v2 = <&cpu7_opp_table>; 207 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 208 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 209 power-domains = <&CPU_PD7>; 210 power-domain-names = "psci"; 211 #cooling-cells = <2>; 212 L2_700: l2-cache { 213 compatible = "cache"; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 cpu-map { 219 cluster0 { 220 core0 { 221 cpu = <&CPU0>; 222 }; 223 224 core1 { 225 cpu = <&CPU1>; 226 }; 227 228 core2 { 229 cpu = <&CPU2>; 230 }; 231 232 core3 { 233 cpu = <&CPU3>; 234 }; 235 236 core4 { 237 cpu = <&CPU4>; 238 }; 239 240 core5 { 241 cpu = <&CPU5>; 242 }; 243 244 core6 { 245 cpu = <&CPU6>; 246 }; 247 248 core7 { 249 cpu = <&CPU7>; 250 }; 251 }; 252 }; 253 254 idle-states { 255 entry-method = "psci"; 256 257 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 258 compatible = "arm,idle-state"; 259 idle-state-name = "little-rail-power-collapse"; 260 arm,psci-suspend-param = <0x40000004>; 261 entry-latency-us = <355>; 262 exit-latency-us = <909>; 263 min-residency-us = <3934>; 264 local-timer-stop; 265 }; 266 267 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "big-rail-power-collapse"; 270 arm,psci-suspend-param = <0x40000004>; 271 entry-latency-us = <241>; 272 exit-latency-us = <1461>; 273 min-residency-us = <4488>; 274 local-timer-stop; 275 }; 276 }; 277 278 domain-idle-states { 279 CLUSTER_SLEEP_0: cluster-sleep-0 { 280 compatible = "domain-idle-state"; 281 idle-state-name = "cluster-power-collapse"; 282 arm,psci-suspend-param = <0x4100c244>; 283 entry-latency-us = <3263>; 284 exit-latency-us = <6562>; 285 min-residency-us = <9987>; 286 local-timer-stop; 287 }; 288 }; 289 }; 290 291 cpu0_opp_table: cpu0_opp_table { 292 compatible = "operating-points-v2"; 293 opp-shared; 294 295 cpu0_opp1: opp-300000000 { 296 opp-hz = /bits/ 64 <300000000>; 297 opp-peak-kBps = <800000 9600000>; 298 }; 299 300 cpu0_opp2: opp-403200000 { 301 opp-hz = /bits/ 64 <403200000>; 302 opp-peak-kBps = <800000 9600000>; 303 }; 304 305 cpu0_opp3: opp-499200000 { 306 opp-hz = /bits/ 64 <499200000>; 307 opp-peak-kBps = <800000 12902400>; 308 }; 309 310 cpu0_opp4: opp-576000000 { 311 opp-hz = /bits/ 64 <576000000>; 312 opp-peak-kBps = <800000 12902400>; 313 }; 314 315 cpu0_opp5: opp-672000000 { 316 opp-hz = /bits/ 64 <672000000>; 317 opp-peak-kBps = <800000 15974400>; 318 }; 319 320 cpu0_opp6: opp-768000000 { 321 opp-hz = /bits/ 64 <768000000>; 322 opp-peak-kBps = <1804000 19660800>; 323 }; 324 325 cpu0_opp7: opp-844800000 { 326 opp-hz = /bits/ 64 <844800000>; 327 opp-peak-kBps = <1804000 19660800>; 328 }; 329 330 cpu0_opp8: opp-940800000 { 331 opp-hz = /bits/ 64 <940800000>; 332 opp-peak-kBps = <1804000 22732800>; 333 }; 334 335 cpu0_opp9: opp-1036800000 { 336 opp-hz = /bits/ 64 <1036800000>; 337 opp-peak-kBps = <1804000 22732800>; 338 }; 339 340 cpu0_opp10: opp-1113600000 { 341 opp-hz = /bits/ 64 <1113600000>; 342 opp-peak-kBps = <2188000 25804800>; 343 }; 344 345 cpu0_opp11: opp-1209600000 { 346 opp-hz = /bits/ 64 <1209600000>; 347 opp-peak-kBps = <2188000 31948800>; 348 }; 349 350 cpu0_opp12: opp-1305600000 { 351 opp-hz = /bits/ 64 <1305600000>; 352 opp-peak-kBps = <3072000 31948800>; 353 }; 354 355 cpu0_opp13: opp-1382400000 { 356 opp-hz = /bits/ 64 <1382400000>; 357 opp-peak-kBps = <3072000 31948800>; 358 }; 359 360 cpu0_opp14: opp-1478400000 { 361 opp-hz = /bits/ 64 <1478400000>; 362 opp-peak-kBps = <3072000 31948800>; 363 }; 364 365 cpu0_opp15: opp-1555200000 { 366 opp-hz = /bits/ 64 <1555200000>; 367 opp-peak-kBps = <3072000 40550400>; 368 }; 369 370 cpu0_opp16: opp-1632000000 { 371 opp-hz = /bits/ 64 <1632000000>; 372 opp-peak-kBps = <3072000 40550400>; 373 }; 374 375 cpu0_opp17: opp-1708800000 { 376 opp-hz = /bits/ 64 <1708800000>; 377 opp-peak-kBps = <3072000 43008000>; 378 }; 379 380 cpu0_opp18: opp-1785600000 { 381 opp-hz = /bits/ 64 <1785600000>; 382 opp-peak-kBps = <3072000 43008000>; 383 }; 384 }; 385 386 cpu4_opp_table: cpu4_opp_table { 387 compatible = "operating-points-v2"; 388 opp-shared; 389 390 cpu4_opp1: opp-710400000 { 391 opp-hz = /bits/ 64 <710400000>; 392 opp-peak-kBps = <1804000 15974400>; 393 }; 394 395 cpu4_opp2: opp-825600000 { 396 opp-hz = /bits/ 64 <825600000>; 397 opp-peak-kBps = <2188000 19660800>; 398 }; 399 400 cpu4_opp3: opp-940800000 { 401 opp-hz = /bits/ 64 <940800000>; 402 opp-peak-kBps = <2188000 22732800>; 403 }; 404 405 cpu4_opp4: opp-1056000000 { 406 opp-hz = /bits/ 64 <1056000000>; 407 opp-peak-kBps = <3072000 25804800>; 408 }; 409 410 cpu4_opp5: opp-1171200000 { 411 opp-hz = /bits/ 64 <1171200000>; 412 opp-peak-kBps = <3072000 31948800>; 413 }; 414 415 cpu4_opp6: opp-1286400000 { 416 opp-hz = /bits/ 64 <1286400000>; 417 opp-peak-kBps = <4068000 31948800>; 418 }; 419 420 cpu4_opp7: opp-1401600000 { 421 opp-hz = /bits/ 64 <1401600000>; 422 opp-peak-kBps = <4068000 31948800>; 423 }; 424 425 cpu4_opp8: opp-1497600000 { 426 opp-hz = /bits/ 64 <1497600000>; 427 opp-peak-kBps = <4068000 40550400>; 428 }; 429 430 cpu4_opp9: opp-1612800000 { 431 opp-hz = /bits/ 64 <1612800000>; 432 opp-peak-kBps = <4068000 40550400>; 433 }; 434 435 cpu4_opp10: opp-1708800000 { 436 opp-hz = /bits/ 64 <1708800000>; 437 opp-peak-kBps = <4068000 43008000>; 438 }; 439 440 cpu4_opp11: opp-1804800000 { 441 opp-hz = /bits/ 64 <1804800000>; 442 opp-peak-kBps = <6220000 43008000>; 443 }; 444 445 cpu4_opp12: opp-1920000000 { 446 opp-hz = /bits/ 64 <1920000000>; 447 opp-peak-kBps = <6220000 49152000>; 448 }; 449 450 cpu4_opp13: opp-2016000000 { 451 opp-hz = /bits/ 64 <2016000000>; 452 opp-peak-kBps = <7216000 49152000>; 453 }; 454 455 cpu4_opp14: opp-2131200000 { 456 opp-hz = /bits/ 64 <2131200000>; 457 opp-peak-kBps = <8368000 49152000>; 458 }; 459 460 cpu4_opp15: opp-2227200000 { 461 opp-hz = /bits/ 64 <2227200000>; 462 opp-peak-kBps = <8368000 51609600>; 463 }; 464 465 cpu4_opp16: opp-2323200000 { 466 opp-hz = /bits/ 64 <2323200000>; 467 opp-peak-kBps = <8368000 51609600>; 468 }; 469 470 cpu4_opp17: opp-2419200000 { 471 opp-hz = /bits/ 64 <2419200000>; 472 opp-peak-kBps = <8368000 51609600>; 473 }; 474 }; 475 476 cpu7_opp_table: cpu7_opp_table { 477 compatible = "operating-points-v2"; 478 opp-shared; 479 480 cpu7_opp1: opp-825600000 { 481 opp-hz = /bits/ 64 <825600000>; 482 opp-peak-kBps = <2188000 19660800>; 483 }; 484 485 cpu7_opp2: opp-940800000 { 486 opp-hz = /bits/ 64 <940800000>; 487 opp-peak-kBps = <2188000 22732800>; 488 }; 489 490 cpu7_opp3: opp-1056000000 { 491 opp-hz = /bits/ 64 <1056000000>; 492 opp-peak-kBps = <3072000 25804800>; 493 }; 494 495 cpu7_opp4: opp-1171200000 { 496 opp-hz = /bits/ 64 <1171200000>; 497 opp-peak-kBps = <3072000 31948800>; 498 }; 499 500 cpu7_opp5: opp-1286400000 { 501 opp-hz = /bits/ 64 <1286400000>; 502 opp-peak-kBps = <4068000 31948800>; 503 }; 504 505 cpu7_opp6: opp-1401600000 { 506 opp-hz = /bits/ 64 <1401600000>; 507 opp-peak-kBps = <4068000 31948800>; 508 }; 509 510 cpu7_opp7: opp-1497600000 { 511 opp-hz = /bits/ 64 <1497600000>; 512 opp-peak-kBps = <4068000 40550400>; 513 }; 514 515 cpu7_opp8: opp-1612800000 { 516 opp-hz = /bits/ 64 <1612800000>; 517 opp-peak-kBps = <4068000 40550400>; 518 }; 519 520 cpu7_opp9: opp-1708800000 { 521 opp-hz = /bits/ 64 <1708800000>; 522 opp-peak-kBps = <4068000 43008000>; 523 }; 524 525 cpu7_opp10: opp-1804800000 { 526 opp-hz = /bits/ 64 <1804800000>; 527 opp-peak-kBps = <6220000 43008000>; 528 }; 529 530 cpu7_opp11: opp-1920000000 { 531 opp-hz = /bits/ 64 <1920000000>; 532 opp-peak-kBps = <6220000 49152000>; 533 }; 534 535 cpu7_opp12: opp-2016000000 { 536 opp-hz = /bits/ 64 <2016000000>; 537 opp-peak-kBps = <7216000 49152000>; 538 }; 539 540 cpu7_opp13: opp-2131200000 { 541 opp-hz = /bits/ 64 <2131200000>; 542 opp-peak-kBps = <8368000 49152000>; 543 }; 544 545 cpu7_opp14: opp-2227200000 { 546 opp-hz = /bits/ 64 <2227200000>; 547 opp-peak-kBps = <8368000 51609600>; 548 }; 549 550 cpu7_opp15: opp-2323200000 { 551 opp-hz = /bits/ 64 <2323200000>; 552 opp-peak-kBps = <8368000 51609600>; 553 }; 554 555 cpu7_opp16: opp-2419200000 { 556 opp-hz = /bits/ 64 <2419200000>; 557 opp-peak-kBps = <8368000 51609600>; 558 }; 559 560 cpu7_opp17: opp-2534400000 { 561 opp-hz = /bits/ 64 <2534400000>; 562 opp-peak-kBps = <8368000 51609600>; 563 }; 564 565 cpu7_opp18: opp-2649600000 { 566 opp-hz = /bits/ 64 <2649600000>; 567 opp-peak-kBps = <8368000 51609600>; 568 }; 569 570 cpu7_opp19: opp-2745600000 { 571 opp-hz = /bits/ 64 <2745600000>; 572 opp-peak-kBps = <8368000 51609600>; 573 }; 574 575 cpu7_opp20: opp-2841600000 { 576 opp-hz = /bits/ 64 <2841600000>; 577 opp-peak-kBps = <8368000 51609600>; 578 }; 579 }; 580 581 firmware { 582 scm: scm { 583 compatible = "qcom,scm-sm8150", "qcom,scm"; 584 #reset-cells = <1>; 585 }; 586 }; 587 588 tcsr_mutex: hwlock { 589 compatible = "qcom,tcsr-mutex"; 590 syscon = <&tcsr_mutex_regs 0 0x1000>; 591 #hwlock-cells = <1>; 592 }; 593 594 memory@80000000 { 595 device_type = "memory"; 596 /* We expect the bootloader to fill in the size */ 597 reg = <0x0 0x80000000 0x0 0x0>; 598 }; 599 600 pmu { 601 compatible = "arm,armv8-pmuv3"; 602 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 603 }; 604 605 psci { 606 compatible = "arm,psci-1.0"; 607 method = "smc"; 608 609 CPU_PD0: cpu0 { 610 #power-domain-cells = <0>; 611 power-domains = <&CLUSTER_PD>; 612 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 613 }; 614 615 CPU_PD1: cpu1 { 616 #power-domain-cells = <0>; 617 power-domains = <&CLUSTER_PD>; 618 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 619 }; 620 621 CPU_PD2: cpu2 { 622 #power-domain-cells = <0>; 623 power-domains = <&CLUSTER_PD>; 624 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 625 }; 626 627 CPU_PD3: cpu3 { 628 #power-domain-cells = <0>; 629 power-domains = <&CLUSTER_PD>; 630 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 631 }; 632 633 CPU_PD4: cpu4 { 634 #power-domain-cells = <0>; 635 power-domains = <&CLUSTER_PD>; 636 domain-idle-states = <&BIG_CPU_SLEEP_0>; 637 }; 638 639 CPU_PD5: cpu5 { 640 #power-domain-cells = <0>; 641 power-domains = <&CLUSTER_PD>; 642 domain-idle-states = <&BIG_CPU_SLEEP_0>; 643 }; 644 645 CPU_PD6: cpu6 { 646 #power-domain-cells = <0>; 647 power-domains = <&CLUSTER_PD>; 648 domain-idle-states = <&BIG_CPU_SLEEP_0>; 649 }; 650 651 CPU_PD7: cpu7 { 652 #power-domain-cells = <0>; 653 power-domains = <&CLUSTER_PD>; 654 domain-idle-states = <&BIG_CPU_SLEEP_0>; 655 }; 656 657 CLUSTER_PD: cpu-cluster0 { 658 #power-domain-cells = <0>; 659 domain-idle-states = <&CLUSTER_SLEEP_0>; 660 }; 661 }; 662 663 reserved-memory { 664 #address-cells = <2>; 665 #size-cells = <2>; 666 ranges; 667 668 hyp_mem: memory@85700000 { 669 reg = <0x0 0x85700000 0x0 0x600000>; 670 no-map; 671 }; 672 673 xbl_mem: memory@85d00000 { 674 reg = <0x0 0x85d00000 0x0 0x140000>; 675 no-map; 676 }; 677 678 aop_mem: memory@85f00000 { 679 reg = <0x0 0x85f00000 0x0 0x20000>; 680 no-map; 681 }; 682 683 aop_cmd_db: memory@85f20000 { 684 compatible = "qcom,cmd-db"; 685 reg = <0x0 0x85f20000 0x0 0x20000>; 686 no-map; 687 }; 688 689 smem_mem: memory@86000000 { 690 reg = <0x0 0x86000000 0x0 0x200000>; 691 no-map; 692 }; 693 694 tz_mem: memory@86200000 { 695 reg = <0x0 0x86200000 0x0 0x3900000>; 696 no-map; 697 }; 698 699 rmtfs_mem: memory@89b00000 { 700 compatible = "qcom,rmtfs-mem"; 701 reg = <0x0 0x89b00000 0x0 0x200000>; 702 no-map; 703 704 qcom,client-id = <1>; 705 qcom,vmid = <15>; 706 }; 707 708 camera_mem: memory@8b700000 { 709 reg = <0x0 0x8b700000 0x0 0x500000>; 710 no-map; 711 }; 712 713 wlan_mem: memory@8bc00000 { 714 reg = <0x0 0x8bc00000 0x0 0x180000>; 715 no-map; 716 }; 717 718 npu_mem: memory@8bd80000 { 719 reg = <0x0 0x8bd80000 0x0 0x80000>; 720 no-map; 721 }; 722 723 adsp_mem: memory@8be00000 { 724 reg = <0x0 0x8be00000 0x0 0x1a00000>; 725 no-map; 726 }; 727 728 mpss_mem: memory@8d800000 { 729 reg = <0x0 0x8d800000 0x0 0x9600000>; 730 no-map; 731 }; 732 733 venus_mem: memory@96e00000 { 734 reg = <0x0 0x96e00000 0x0 0x500000>; 735 no-map; 736 }; 737 738 slpi_mem: memory@97300000 { 739 reg = <0x0 0x97300000 0x0 0x1400000>; 740 no-map; 741 }; 742 743 ipa_fw_mem: memory@98700000 { 744 reg = <0x0 0x98700000 0x0 0x10000>; 745 no-map; 746 }; 747 748 ipa_gsi_mem: memory@98710000 { 749 reg = <0x0 0x98710000 0x0 0x5000>; 750 no-map; 751 }; 752 753 gpu_mem: memory@98715000 { 754 reg = <0x0 0x98715000 0x0 0x2000>; 755 no-map; 756 }; 757 758 spss_mem: memory@98800000 { 759 reg = <0x0 0x98800000 0x0 0x100000>; 760 no-map; 761 }; 762 763 cdsp_mem: memory@98900000 { 764 reg = <0x0 0x98900000 0x0 0x1400000>; 765 no-map; 766 }; 767 768 qseecom_mem: memory@9e400000 { 769 reg = <0x0 0x9e400000 0x0 0x1400000>; 770 no-map; 771 }; 772 }; 773 774 smem { 775 compatible = "qcom,smem"; 776 memory-region = <&smem_mem>; 777 hwlocks = <&tcsr_mutex 3>; 778 }; 779 780 smp2p-cdsp { 781 compatible = "qcom,smp2p"; 782 qcom,smem = <94>, <432>; 783 784 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 785 786 mboxes = <&apss_shared 6>; 787 788 qcom,local-pid = <0>; 789 qcom,remote-pid = <5>; 790 791 cdsp_smp2p_out: master-kernel { 792 qcom,entry-name = "master-kernel"; 793 #qcom,smem-state-cells = <1>; 794 }; 795 796 cdsp_smp2p_in: slave-kernel { 797 qcom,entry-name = "slave-kernel"; 798 799 interrupt-controller; 800 #interrupt-cells = <2>; 801 }; 802 }; 803 804 smp2p-lpass { 805 compatible = "qcom,smp2p"; 806 qcom,smem = <443>, <429>; 807 808 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 809 810 mboxes = <&apss_shared 10>; 811 812 qcom,local-pid = <0>; 813 qcom,remote-pid = <2>; 814 815 adsp_smp2p_out: master-kernel { 816 qcom,entry-name = "master-kernel"; 817 #qcom,smem-state-cells = <1>; 818 }; 819 820 adsp_smp2p_in: slave-kernel { 821 qcom,entry-name = "slave-kernel"; 822 823 interrupt-controller; 824 #interrupt-cells = <2>; 825 }; 826 }; 827 828 smp2p-mpss { 829 compatible = "qcom,smp2p"; 830 qcom,smem = <435>, <428>; 831 832 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 833 834 mboxes = <&apss_shared 14>; 835 836 qcom,local-pid = <0>; 837 qcom,remote-pid = <1>; 838 839 modem_smp2p_out: master-kernel { 840 qcom,entry-name = "master-kernel"; 841 #qcom,smem-state-cells = <1>; 842 }; 843 844 modem_smp2p_in: slave-kernel { 845 qcom,entry-name = "slave-kernel"; 846 847 interrupt-controller; 848 #interrupt-cells = <2>; 849 }; 850 }; 851 852 smp2p-slpi { 853 compatible = "qcom,smp2p"; 854 qcom,smem = <481>, <430>; 855 856 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 857 858 mboxes = <&apss_shared 26>; 859 860 qcom,local-pid = <0>; 861 qcom,remote-pid = <3>; 862 863 slpi_smp2p_out: master-kernel { 864 qcom,entry-name = "master-kernel"; 865 #qcom,smem-state-cells = <1>; 866 }; 867 868 slpi_smp2p_in: slave-kernel { 869 qcom,entry-name = "slave-kernel"; 870 871 interrupt-controller; 872 #interrupt-cells = <2>; 873 }; 874 }; 875 876 soc: soc@0 { 877 #address-cells = <2>; 878 #size-cells = <2>; 879 ranges = <0 0 0 0 0x10 0>; 880 dma-ranges = <0 0 0 0 0x10 0>; 881 compatible = "simple-bus"; 882 883 gcc: clock-controller@100000 { 884 compatible = "qcom,gcc-sm8150"; 885 reg = <0x0 0x00100000 0x0 0x1f0000>; 886 #clock-cells = <1>; 887 #reset-cells = <1>; 888 #power-domain-cells = <1>; 889 clock-names = "bi_tcxo", 890 "sleep_clk"; 891 clocks = <&rpmhcc RPMH_CXO_CLK>, 892 <&sleep_clk>; 893 }; 894 895 gpi_dma0: dma-controller@800000 { 896 compatible = "qcom,sm8150-gpi-dma"; 897 reg = <0 0x800000 0 0x60000>; 898 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 911 dma-channels = <13>; 912 dma-channel-mask = <0xfa>; 913 iommus = <&apps_smmu 0x00d6 0x0>; 914 #dma-cells = <3>; 915 status = "disabled"; 916 }; 917 918 qupv3_id_0: geniqup@8c0000 { 919 compatible = "qcom,geni-se-qup"; 920 reg = <0x0 0x008c0000 0x0 0x6000>; 921 clock-names = "m-ahb", "s-ahb"; 922 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 923 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 924 iommus = <&apps_smmu 0xc3 0x0>; 925 #address-cells = <2>; 926 #size-cells = <2>; 927 ranges; 928 status = "disabled"; 929 930 i2c0: i2c@880000 { 931 compatible = "qcom,geni-i2c"; 932 reg = <0 0x00880000 0 0x4000>; 933 clock-names = "se"; 934 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 935 pinctrl-names = "default"; 936 pinctrl-0 = <&qup_i2c0_default>; 937 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 938 #address-cells = <1>; 939 #size-cells = <0>; 940 status = "disabled"; 941 }; 942 943 spi0: spi@880000 { 944 compatible = "qcom,geni-spi"; 945 reg = <0 0x880000 0 0x4000>; 946 reg-names = "se"; 947 clock-names = "se"; 948 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 949 pinctrl-names = "default"; 950 pinctrl-0 = <&qup_spi0_default>; 951 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 952 spi-max-frequency = <50000000>; 953 #address-cells = <1>; 954 #size-cells = <0>; 955 status = "disabled"; 956 }; 957 958 i2c1: i2c@884000 { 959 compatible = "qcom,geni-i2c"; 960 reg = <0 0x00884000 0 0x4000>; 961 clock-names = "se"; 962 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 963 pinctrl-names = "default"; 964 pinctrl-0 = <&qup_i2c1_default>; 965 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 status = "disabled"; 969 }; 970 971 spi1: spi@884000 { 972 compatible = "qcom,geni-spi"; 973 reg = <0 0x884000 0 0x4000>; 974 reg-names = "se"; 975 clock-names = "se"; 976 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 977 pinctrl-names = "default"; 978 pinctrl-0 = <&qup_spi1_default>; 979 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 980 spi-max-frequency = <50000000>; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 status = "disabled"; 984 }; 985 986 i2c2: i2c@888000 { 987 compatible = "qcom,geni-i2c"; 988 reg = <0 0x00888000 0 0x4000>; 989 clock-names = "se"; 990 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 991 pinctrl-names = "default"; 992 pinctrl-0 = <&qup_i2c2_default>; 993 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 status = "disabled"; 997 }; 998 999 spi2: spi@888000 { 1000 compatible = "qcom,geni-spi"; 1001 reg = <0 0x888000 0 0x4000>; 1002 reg-names = "se"; 1003 clock-names = "se"; 1004 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_spi2_default>; 1007 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1008 spi-max-frequency = <50000000>; 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 status = "disabled"; 1012 }; 1013 1014 i2c3: i2c@88c000 { 1015 compatible = "qcom,geni-i2c"; 1016 reg = <0 0x0088c000 0 0x4000>; 1017 clock-names = "se"; 1018 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&qup_i2c3_default>; 1021 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 status = "disabled"; 1025 }; 1026 1027 spi3: spi@88c000 { 1028 compatible = "qcom,geni-spi"; 1029 reg = <0 0x88c000 0 0x4000>; 1030 reg-names = "se"; 1031 clock-names = "se"; 1032 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1033 pinctrl-names = "default"; 1034 pinctrl-0 = <&qup_spi3_default>; 1035 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1036 spi-max-frequency = <50000000>; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 status = "disabled"; 1040 }; 1041 1042 i2c4: i2c@890000 { 1043 compatible = "qcom,geni-i2c"; 1044 reg = <0 0x00890000 0 0x4000>; 1045 clock-names = "se"; 1046 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1047 pinctrl-names = "default"; 1048 pinctrl-0 = <&qup_i2c4_default>; 1049 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 status = "disabled"; 1053 }; 1054 1055 spi4: spi@890000 { 1056 compatible = "qcom,geni-spi"; 1057 reg = <0 0x890000 0 0x4000>; 1058 reg-names = "se"; 1059 clock-names = "se"; 1060 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1061 pinctrl-names = "default"; 1062 pinctrl-0 = <&qup_spi4_default>; 1063 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1064 spi-max-frequency = <50000000>; 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 status = "disabled"; 1068 }; 1069 1070 i2c5: i2c@894000 { 1071 compatible = "qcom,geni-i2c"; 1072 reg = <0 0x00894000 0 0x4000>; 1073 clock-names = "se"; 1074 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1075 pinctrl-names = "default"; 1076 pinctrl-0 = <&qup_i2c5_default>; 1077 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 status = "disabled"; 1081 }; 1082 1083 spi5: spi@894000 { 1084 compatible = "qcom,geni-spi"; 1085 reg = <0 0x894000 0 0x4000>; 1086 reg-names = "se"; 1087 clock-names = "se"; 1088 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1089 pinctrl-names = "default"; 1090 pinctrl-0 = <&qup_spi5_default>; 1091 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1092 spi-max-frequency = <50000000>; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 status = "disabled"; 1096 }; 1097 1098 i2c6: i2c@898000 { 1099 compatible = "qcom,geni-i2c"; 1100 reg = <0 0x00898000 0 0x4000>; 1101 clock-names = "se"; 1102 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1103 pinctrl-names = "default"; 1104 pinctrl-0 = <&qup_i2c6_default>; 1105 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 status = "disabled"; 1109 }; 1110 1111 spi6: spi@898000 { 1112 compatible = "qcom,geni-spi"; 1113 reg = <0 0x898000 0 0x4000>; 1114 reg-names = "se"; 1115 clock-names = "se"; 1116 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&qup_spi6_default>; 1119 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1120 spi-max-frequency = <50000000>; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 status = "disabled"; 1124 }; 1125 1126 i2c7: i2c@89c000 { 1127 compatible = "qcom,geni-i2c"; 1128 reg = <0 0x0089c000 0 0x4000>; 1129 clock-names = "se"; 1130 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1131 pinctrl-names = "default"; 1132 pinctrl-0 = <&qup_i2c7_default>; 1133 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 status = "disabled"; 1137 }; 1138 1139 spi7: spi@89c000 { 1140 compatible = "qcom,geni-spi"; 1141 reg = <0 0x89c000 0 0x4000>; 1142 reg-names = "se"; 1143 clock-names = "se"; 1144 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1145 pinctrl-names = "default"; 1146 pinctrl-0 = <&qup_spi7_default>; 1147 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1148 spi-max-frequency = <50000000>; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 status = "disabled"; 1152 }; 1153 }; 1154 1155 gpi_dma1: dma-controller@a00000 { 1156 compatible = "qcom,sm8150-gpi-dma"; 1157 reg = <0 0xa00000 0 0x60000>; 1158 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1171 dma-channels = <13>; 1172 dma-channel-mask = <0xfa>; 1173 iommus = <&apps_smmu 0x0616 0x0>; 1174 #dma-cells = <3>; 1175 status = "disabled"; 1176 }; 1177 1178 qupv3_id_1: geniqup@ac0000 { 1179 compatible = "qcom,geni-se-qup"; 1180 reg = <0x0 0x00ac0000 0x0 0x6000>; 1181 clock-names = "m-ahb", "s-ahb"; 1182 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1183 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1184 iommus = <&apps_smmu 0x603 0x0>; 1185 #address-cells = <2>; 1186 #size-cells = <2>; 1187 ranges; 1188 status = "disabled"; 1189 1190 i2c8: i2c@a80000 { 1191 compatible = "qcom,geni-i2c"; 1192 reg = <0 0x00a80000 0 0x4000>; 1193 clock-names = "se"; 1194 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&qup_i2c8_default>; 1197 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 status = "disabled"; 1201 }; 1202 1203 spi8: spi@a80000 { 1204 compatible = "qcom,geni-spi"; 1205 reg = <0 0xa80000 0 0x4000>; 1206 reg-names = "se"; 1207 clock-names = "se"; 1208 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1209 pinctrl-names = "default"; 1210 pinctrl-0 = <&qup_spi8_default>; 1211 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1212 spi-max-frequency = <50000000>; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 status = "disabled"; 1216 }; 1217 1218 i2c9: i2c@a84000 { 1219 compatible = "qcom,geni-i2c"; 1220 reg = <0 0x00a84000 0 0x4000>; 1221 clock-names = "se"; 1222 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&qup_i2c9_default>; 1225 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 status = "disabled"; 1229 }; 1230 1231 spi9: spi@a84000 { 1232 compatible = "qcom,geni-spi"; 1233 reg = <0 0xa84000 0 0x4000>; 1234 reg-names = "se"; 1235 clock-names = "se"; 1236 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1237 pinctrl-names = "default"; 1238 pinctrl-0 = <&qup_spi9_default>; 1239 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1240 spi-max-frequency = <50000000>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 status = "disabled"; 1244 }; 1245 1246 i2c10: i2c@a88000 { 1247 compatible = "qcom,geni-i2c"; 1248 reg = <0 0x00a88000 0 0x4000>; 1249 clock-names = "se"; 1250 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&qup_i2c10_default>; 1253 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 status = "disabled"; 1257 }; 1258 1259 spi10: spi@a88000 { 1260 compatible = "qcom,geni-spi"; 1261 reg = <0 0xa88000 0 0x4000>; 1262 reg-names = "se"; 1263 clock-names = "se"; 1264 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1265 pinctrl-names = "default"; 1266 pinctrl-0 = <&qup_spi10_default>; 1267 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1268 spi-max-frequency = <50000000>; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 status = "disabled"; 1272 }; 1273 1274 i2c11: i2c@a8c000 { 1275 compatible = "qcom,geni-i2c"; 1276 reg = <0 0x00a8c000 0 0x4000>; 1277 clock-names = "se"; 1278 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&qup_i2c11_default>; 1281 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 status = "disabled"; 1285 }; 1286 1287 spi11: spi@a8c000 { 1288 compatible = "qcom,geni-spi"; 1289 reg = <0 0xa8c000 0 0x4000>; 1290 reg-names = "se"; 1291 clock-names = "se"; 1292 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1293 pinctrl-names = "default"; 1294 pinctrl-0 = <&qup_spi11_default>; 1295 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1296 spi-max-frequency = <50000000>; 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 status = "disabled"; 1300 }; 1301 1302 uart2: serial@a90000 { 1303 compatible = "qcom,geni-debug-uart"; 1304 reg = <0x0 0x00a90000 0x0 0x4000>; 1305 clock-names = "se"; 1306 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1307 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1308 status = "disabled"; 1309 }; 1310 1311 i2c12: i2c@a90000 { 1312 compatible = "qcom,geni-i2c"; 1313 reg = <0 0x00a90000 0 0x4000>; 1314 clock-names = "se"; 1315 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1316 pinctrl-names = "default"; 1317 pinctrl-0 = <&qup_i2c12_default>; 1318 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1319 #address-cells = <1>; 1320 #size-cells = <0>; 1321 status = "disabled"; 1322 }; 1323 1324 spi12: spi@a90000 { 1325 compatible = "qcom,geni-spi"; 1326 reg = <0 0xa90000 0 0x4000>; 1327 reg-names = "se"; 1328 clock-names = "se"; 1329 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1330 pinctrl-names = "default"; 1331 pinctrl-0 = <&qup_spi12_default>; 1332 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1333 spi-max-frequency = <50000000>; 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 status = "disabled"; 1337 }; 1338 1339 i2c16: i2c@94000 { 1340 compatible = "qcom,geni-i2c"; 1341 reg = <0 0x0094000 0 0x4000>; 1342 clock-names = "se"; 1343 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1344 pinctrl-names = "default"; 1345 pinctrl-0 = <&qup_i2c16_default>; 1346 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1347 #address-cells = <1>; 1348 #size-cells = <0>; 1349 status = "disabled"; 1350 }; 1351 1352 spi16: spi@a94000 { 1353 compatible = "qcom,geni-spi"; 1354 reg = <0 0xa94000 0 0x4000>; 1355 reg-names = "se"; 1356 clock-names = "se"; 1357 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&qup_spi16_default>; 1360 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1361 spi-max-frequency = <50000000>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 status = "disabled"; 1365 }; 1366 }; 1367 1368 gpi_dma2: dma-controller@c00000 { 1369 compatible = "qcom,sm8150-gpi-dma"; 1370 reg = <0 0xc00000 0 0x60000>; 1371 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 1384 dma-channels = <13>; 1385 dma-channel-mask = <0xfa>; 1386 iommus = <&apps_smmu 0x07b6 0x0>; 1387 #dma-cells = <3>; 1388 status = "disabled"; 1389 }; 1390 1391 qupv3_id_2: geniqup@cc0000 { 1392 compatible = "qcom,geni-se-qup"; 1393 reg = <0x0 0x00cc0000 0x0 0x6000>; 1394 1395 clock-names = "m-ahb", "s-ahb"; 1396 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1397 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1398 iommus = <&apps_smmu 0x7a3 0x0>; 1399 #address-cells = <2>; 1400 #size-cells = <2>; 1401 ranges; 1402 status = "disabled"; 1403 1404 i2c17: i2c@c80000 { 1405 compatible = "qcom,geni-i2c"; 1406 reg = <0 0x00c80000 0 0x4000>; 1407 clock-names = "se"; 1408 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1409 pinctrl-names = "default"; 1410 pinctrl-0 = <&qup_i2c17_default>; 1411 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1412 #address-cells = <1>; 1413 #size-cells = <0>; 1414 status = "disabled"; 1415 }; 1416 1417 spi17: spi@c80000 { 1418 compatible = "qcom,geni-spi"; 1419 reg = <0 0xc80000 0 0x4000>; 1420 reg-names = "se"; 1421 clock-names = "se"; 1422 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1423 pinctrl-names = "default"; 1424 pinctrl-0 = <&qup_spi17_default>; 1425 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1426 spi-max-frequency = <50000000>; 1427 #address-cells = <1>; 1428 #size-cells = <0>; 1429 status = "disabled"; 1430 }; 1431 1432 i2c18: i2c@c84000 { 1433 compatible = "qcom,geni-i2c"; 1434 reg = <0 0x00c84000 0 0x4000>; 1435 clock-names = "se"; 1436 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1437 pinctrl-names = "default"; 1438 pinctrl-0 = <&qup_i2c18_default>; 1439 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1440 #address-cells = <1>; 1441 #size-cells = <0>; 1442 status = "disabled"; 1443 }; 1444 1445 spi18: spi@c84000 { 1446 compatible = "qcom,geni-spi"; 1447 reg = <0 0xc84000 0 0x4000>; 1448 reg-names = "se"; 1449 clock-names = "se"; 1450 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1451 pinctrl-names = "default"; 1452 pinctrl-0 = <&qup_spi18_default>; 1453 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1454 spi-max-frequency = <50000000>; 1455 #address-cells = <1>; 1456 #size-cells = <0>; 1457 status = "disabled"; 1458 }; 1459 1460 i2c19: i2c@c88000 { 1461 compatible = "qcom,geni-i2c"; 1462 reg = <0 0x00c88000 0 0x4000>; 1463 clock-names = "se"; 1464 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1465 pinctrl-names = "default"; 1466 pinctrl-0 = <&qup_i2c19_default>; 1467 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1468 #address-cells = <1>; 1469 #size-cells = <0>; 1470 status = "disabled"; 1471 }; 1472 1473 spi19: spi@c88000 { 1474 compatible = "qcom,geni-spi"; 1475 reg = <0 0xc88000 0 0x4000>; 1476 reg-names = "se"; 1477 clock-names = "se"; 1478 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1479 pinctrl-names = "default"; 1480 pinctrl-0 = <&qup_spi19_default>; 1481 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1482 spi-max-frequency = <50000000>; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 status = "disabled"; 1486 }; 1487 1488 i2c13: i2c@c8c000 { 1489 compatible = "qcom,geni-i2c"; 1490 reg = <0 0x00c8c000 0 0x4000>; 1491 clock-names = "se"; 1492 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1493 pinctrl-names = "default"; 1494 pinctrl-0 = <&qup_i2c13_default>; 1495 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1496 #address-cells = <1>; 1497 #size-cells = <0>; 1498 status = "disabled"; 1499 }; 1500 1501 spi13: spi@c8c000 { 1502 compatible = "qcom,geni-spi"; 1503 reg = <0 0xc8c000 0 0x4000>; 1504 reg-names = "se"; 1505 clock-names = "se"; 1506 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1507 pinctrl-names = "default"; 1508 pinctrl-0 = <&qup_spi13_default>; 1509 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1510 spi-max-frequency = <50000000>; 1511 #address-cells = <1>; 1512 #size-cells = <0>; 1513 status = "disabled"; 1514 }; 1515 1516 i2c14: i2c@c90000 { 1517 compatible = "qcom,geni-i2c"; 1518 reg = <0 0x00c90000 0 0x4000>; 1519 clock-names = "se"; 1520 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1521 pinctrl-names = "default"; 1522 pinctrl-0 = <&qup_i2c14_default>; 1523 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1524 #address-cells = <1>; 1525 #size-cells = <0>; 1526 status = "disabled"; 1527 }; 1528 1529 spi14: spi@c90000 { 1530 compatible = "qcom,geni-spi"; 1531 reg = <0 0xc90000 0 0x4000>; 1532 reg-names = "se"; 1533 clock-names = "se"; 1534 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1535 pinctrl-names = "default"; 1536 pinctrl-0 = <&qup_spi14_default>; 1537 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1538 spi-max-frequency = <50000000>; 1539 #address-cells = <1>; 1540 #size-cells = <0>; 1541 status = "disabled"; 1542 }; 1543 1544 i2c15: i2c@c94000 { 1545 compatible = "qcom,geni-i2c"; 1546 reg = <0 0x00c94000 0 0x4000>; 1547 clock-names = "se"; 1548 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1549 pinctrl-names = "default"; 1550 pinctrl-0 = <&qup_i2c15_default>; 1551 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1552 #address-cells = <1>; 1553 #size-cells = <0>; 1554 status = "disabled"; 1555 }; 1556 1557 spi15: spi@c94000 { 1558 compatible = "qcom,geni-spi"; 1559 reg = <0 0xc94000 0 0x4000>; 1560 reg-names = "se"; 1561 clock-names = "se"; 1562 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1563 pinctrl-names = "default"; 1564 pinctrl-0 = <&qup_spi15_default>; 1565 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1566 spi-max-frequency = <50000000>; 1567 #address-cells = <1>; 1568 #size-cells = <0>; 1569 status = "disabled"; 1570 }; 1571 }; 1572 1573 config_noc: interconnect@1500000 { 1574 compatible = "qcom,sm8150-config-noc"; 1575 reg = <0 0x01500000 0 0x7400>; 1576 #interconnect-cells = <1>; 1577 qcom,bcm-voters = <&apps_bcm_voter>; 1578 }; 1579 1580 system_noc: interconnect@1620000 { 1581 compatible = "qcom,sm8150-system-noc"; 1582 reg = <0 0x01620000 0 0x19400>; 1583 #interconnect-cells = <1>; 1584 qcom,bcm-voters = <&apps_bcm_voter>; 1585 }; 1586 1587 mc_virt: interconnect@163a000 { 1588 compatible = "qcom,sm8150-mc-virt"; 1589 reg = <0 0x0163a000 0 0x1000>; 1590 #interconnect-cells = <1>; 1591 qcom,bcm-voters = <&apps_bcm_voter>; 1592 }; 1593 1594 aggre1_noc: interconnect@16e0000 { 1595 compatible = "qcom,sm8150-aggre1-noc"; 1596 reg = <0 0x016e0000 0 0xd080>; 1597 #interconnect-cells = <1>; 1598 qcom,bcm-voters = <&apps_bcm_voter>; 1599 }; 1600 1601 aggre2_noc: interconnect@1700000 { 1602 compatible = "qcom,sm8150-aggre2-noc"; 1603 reg = <0 0x01700000 0 0x20000>; 1604 #interconnect-cells = <1>; 1605 qcom,bcm-voters = <&apps_bcm_voter>; 1606 }; 1607 1608 compute_noc: interconnect@1720000 { 1609 compatible = "qcom,sm8150-compute-noc"; 1610 reg = <0 0x01720000 0 0x7000>; 1611 #interconnect-cells = <1>; 1612 qcom,bcm-voters = <&apps_bcm_voter>; 1613 }; 1614 1615 mmss_noc: interconnect@1740000 { 1616 compatible = "qcom,sm8150-mmss-noc"; 1617 reg = <0 0x01740000 0 0x1c100>; 1618 #interconnect-cells = <1>; 1619 qcom,bcm-voters = <&apps_bcm_voter>; 1620 }; 1621 1622 system-cache-controller@9200000 { 1623 compatible = "qcom,sm8150-llcc"; 1624 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 1625 reg-names = "llcc_base", "llcc_broadcast_base"; 1626 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1627 }; 1628 1629 ufs_mem_hc: ufshc@1d84000 { 1630 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 1631 "jedec,ufs-2.0"; 1632 reg = <0 0x01d84000 0 0x2500>, 1633 <0 0x01d90000 0 0x8000>; 1634 reg-names = "std", "ice"; 1635 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1636 phys = <&ufs_mem_phy_lanes>; 1637 phy-names = "ufsphy"; 1638 lanes-per-direction = <2>; 1639 #reset-cells = <1>; 1640 resets = <&gcc GCC_UFS_PHY_BCR>; 1641 reset-names = "rst"; 1642 1643 iommus = <&apps_smmu 0x300 0>; 1644 1645 clock-names = 1646 "core_clk", 1647 "bus_aggr_clk", 1648 "iface_clk", 1649 "core_clk_unipro", 1650 "ref_clk", 1651 "tx_lane0_sync_clk", 1652 "rx_lane0_sync_clk", 1653 "rx_lane1_sync_clk", 1654 "ice_core_clk"; 1655 clocks = 1656 <&gcc GCC_UFS_PHY_AXI_CLK>, 1657 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1658 <&gcc GCC_UFS_PHY_AHB_CLK>, 1659 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1660 <&rpmhcc RPMH_CXO_CLK>, 1661 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1662 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1663 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 1664 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1665 freq-table-hz = 1666 <37500000 300000000>, 1667 <0 0>, 1668 <0 0>, 1669 <37500000 300000000>, 1670 <0 0>, 1671 <0 0>, 1672 <0 0>, 1673 <0 0>, 1674 <0 300000000>; 1675 1676 status = "disabled"; 1677 }; 1678 1679 ufs_mem_phy: phy@1d87000 { 1680 compatible = "qcom,sm8150-qmp-ufs-phy"; 1681 reg = <0 0x01d87000 0 0x1c0>; 1682 #address-cells = <2>; 1683 #size-cells = <2>; 1684 ranges; 1685 clock-names = "ref", 1686 "ref_aux"; 1687 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 1688 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1689 1690 resets = <&ufs_mem_hc 0>; 1691 reset-names = "ufsphy"; 1692 status = "disabled"; 1693 1694 ufs_mem_phy_lanes: phy@1d87400 { 1695 reg = <0 0x01d87400 0 0x108>, 1696 <0 0x01d87600 0 0x1e0>, 1697 <0 0x01d87c00 0 0x1dc>, 1698 <0 0x01d87800 0 0x108>, 1699 <0 0x01d87a00 0 0x1e0>; 1700 #phy-cells = <0>; 1701 }; 1702 }; 1703 1704 ipa_virt: interconnect@1e00000 { 1705 compatible = "qcom,sm8150-ipa-virt"; 1706 reg = <0 0x01e00000 0 0x1000>; 1707 #interconnect-cells = <1>; 1708 qcom,bcm-voters = <&apps_bcm_voter>; 1709 }; 1710 1711 tcsr_mutex_regs: syscon@1f40000 { 1712 compatible = "syscon"; 1713 reg = <0x0 0x01f40000 0x0 0x40000>; 1714 }; 1715 1716 remoteproc_slpi: remoteproc@2400000 { 1717 compatible = "qcom,sm8150-slpi-pas"; 1718 reg = <0x0 0x02400000 0x0 0x4040>; 1719 1720 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 1721 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1722 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1723 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1724 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1725 interrupt-names = "wdog", "fatal", "ready", 1726 "handover", "stop-ack"; 1727 1728 clocks = <&rpmhcc RPMH_CXO_CLK>; 1729 clock-names = "xo"; 1730 1731 power-domains = <&rpmhpd 3>, 1732 <&rpmhpd 2>; 1733 power-domain-names = "lcx", "lmx"; 1734 1735 memory-region = <&slpi_mem>; 1736 1737 qcom,qmp = <&aoss_qmp>; 1738 1739 qcom,smem-states = <&slpi_smp2p_out 0>; 1740 qcom,smem-state-names = "stop"; 1741 1742 status = "disabled"; 1743 1744 glink-edge { 1745 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 1746 label = "dsps"; 1747 qcom,remote-pid = <3>; 1748 mboxes = <&apss_shared 24>; 1749 1750 fastrpc { 1751 compatible = "qcom,fastrpc"; 1752 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1753 label = "sdsp"; 1754 #address-cells = <1>; 1755 #size-cells = <0>; 1756 1757 compute-cb@1 { 1758 compatible = "qcom,fastrpc-compute-cb"; 1759 reg = <1>; 1760 iommus = <&apps_smmu 0x05a1 0x0>; 1761 }; 1762 1763 compute-cb@2 { 1764 compatible = "qcom,fastrpc-compute-cb"; 1765 reg = <2>; 1766 iommus = <&apps_smmu 0x05a2 0x0>; 1767 }; 1768 1769 compute-cb@3 { 1770 compatible = "qcom,fastrpc-compute-cb"; 1771 reg = <3>; 1772 iommus = <&apps_smmu 0x05a3 0x0>; 1773 /* note: shared-cb = <4> in downstream */ 1774 }; 1775 }; 1776 }; 1777 }; 1778 1779 gpu: gpu@2c00000 { 1780 /* 1781 * note: the amd,imageon compatible makes it possible 1782 * to use the drm/msm driver without the display node, 1783 * make sure to remove it when display node is added 1784 */ 1785 compatible = "qcom,adreno-640.1", 1786 "qcom,adreno", 1787 "amd,imageon"; 1788 1789 reg = <0 0x02c00000 0 0x40000>; 1790 reg-names = "kgsl_3d0_reg_memory"; 1791 1792 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1793 1794 iommus = <&adreno_smmu 0 0x401>; 1795 1796 operating-points-v2 = <&gpu_opp_table>; 1797 1798 qcom,gmu = <&gmu>; 1799 1800 status = "disabled"; 1801 1802 zap-shader { 1803 memory-region = <&gpu_mem>; 1804 }; 1805 1806 /* note: downstream checks gpu binning for 675 Mhz */ 1807 gpu_opp_table: opp-table { 1808 compatible = "operating-points-v2"; 1809 1810 opp-675000000 { 1811 opp-hz = /bits/ 64 <675000000>; 1812 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1813 }; 1814 1815 opp-585000000 { 1816 opp-hz = /bits/ 64 <585000000>; 1817 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1818 }; 1819 1820 opp-499200000 { 1821 opp-hz = /bits/ 64 <499200000>; 1822 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1823 }; 1824 1825 opp-427000000 { 1826 opp-hz = /bits/ 64 <427000000>; 1827 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1828 }; 1829 1830 opp-345000000 { 1831 opp-hz = /bits/ 64 <345000000>; 1832 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1833 }; 1834 1835 opp-257000000 { 1836 opp-hz = /bits/ 64 <257000000>; 1837 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1838 }; 1839 }; 1840 }; 1841 1842 gmu: gmu@2c6a000 { 1843 compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 1844 1845 reg = <0 0x02c6a000 0 0x30000>, 1846 <0 0x0b290000 0 0x10000>, 1847 <0 0x0b490000 0 0x10000>; 1848 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 1849 1850 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1852 interrupt-names = "hfi", "gmu"; 1853 1854 clocks = <&gpucc GPU_CC_AHB_CLK>, 1855 <&gpucc GPU_CC_CX_GMU_CLK>, 1856 <&gpucc GPU_CC_CXO_CLK>, 1857 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1858 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1859 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 1860 1861 power-domains = <&gpucc GPU_CX_GDSC>, 1862 <&gpucc GPU_GX_GDSC>; 1863 power-domain-names = "cx", "gx"; 1864 1865 iommus = <&adreno_smmu 5 0x400>; 1866 1867 operating-points-v2 = <&gmu_opp_table>; 1868 1869 status = "disabled"; 1870 1871 gmu_opp_table: opp-table { 1872 compatible = "operating-points-v2"; 1873 1874 opp-200000000 { 1875 opp-hz = /bits/ 64 <200000000>; 1876 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1877 }; 1878 }; 1879 }; 1880 1881 gpucc: clock-controller@2c90000 { 1882 compatible = "qcom,sm8150-gpucc"; 1883 reg = <0 0x02c90000 0 0x9000>; 1884 clocks = <&rpmhcc RPMH_CXO_CLK>, 1885 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1886 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1887 clock-names = "bi_tcxo", 1888 "gcc_gpu_gpll0_clk_src", 1889 "gcc_gpu_gpll0_div_clk_src"; 1890 #clock-cells = <1>; 1891 #reset-cells = <1>; 1892 #power-domain-cells = <1>; 1893 }; 1894 1895 adreno_smmu: iommu@2ca0000 { 1896 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 1897 reg = <0 0x02ca0000 0 0x10000>; 1898 #iommu-cells = <2>; 1899 #global-interrupts = <1>; 1900 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 1909 clocks = <&gpucc GPU_CC_AHB_CLK>, 1910 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1911 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1912 clock-names = "ahb", "bus", "iface"; 1913 1914 power-domains = <&gpucc GPU_CX_GDSC>; 1915 }; 1916 1917 tlmm: pinctrl@3100000 { 1918 compatible = "qcom,sm8150-pinctrl"; 1919 reg = <0x0 0x03100000 0x0 0x300000>, 1920 <0x0 0x03500000 0x0 0x300000>, 1921 <0x0 0x03900000 0x0 0x300000>, 1922 <0x0 0x03D00000 0x0 0x300000>; 1923 reg-names = "west", "east", "north", "south"; 1924 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1925 gpio-ranges = <&tlmm 0 0 176>; 1926 gpio-controller; 1927 #gpio-cells = <2>; 1928 interrupt-controller; 1929 #interrupt-cells = <2>; 1930 1931 qup_i2c0_default: qup-i2c0-default { 1932 mux { 1933 pins = "gpio0", "gpio1"; 1934 function = "qup0"; 1935 }; 1936 1937 config { 1938 pins = "gpio0", "gpio1"; 1939 drive-strength = <0x02>; 1940 bias-disable; 1941 }; 1942 }; 1943 1944 qup_spi0_default: qup-spi0-default { 1945 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1946 function = "qup0"; 1947 drive-strength = <6>; 1948 bias-disable; 1949 }; 1950 1951 qup_i2c1_default: qup-i2c1-default { 1952 mux { 1953 pins = "gpio114", "gpio115"; 1954 function = "qup1"; 1955 }; 1956 1957 config { 1958 pins = "gpio114", "gpio115"; 1959 drive-strength = <0x02>; 1960 bias-disable; 1961 }; 1962 }; 1963 1964 qup_spi1_default: qup-spi1-default { 1965 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 1966 function = "qup1"; 1967 drive-strength = <6>; 1968 bias-disable; 1969 }; 1970 1971 qup_i2c2_default: qup-i2c2-default { 1972 mux { 1973 pins = "gpio126", "gpio127"; 1974 function = "qup2"; 1975 }; 1976 1977 config { 1978 pins = "gpio126", "gpio127"; 1979 drive-strength = <0x02>; 1980 bias-disable; 1981 }; 1982 }; 1983 1984 qup_spi2_default: qup-spi2-default { 1985 pins = "gpio126", "gpio127", "gpio128", "gpio129"; 1986 function = "qup2"; 1987 drive-strength = <6>; 1988 bias-disable; 1989 }; 1990 1991 qup_i2c3_default: qup-i2c3-default { 1992 mux { 1993 pins = "gpio144", "gpio145"; 1994 function = "qup3"; 1995 }; 1996 1997 config { 1998 pins = "gpio144", "gpio145"; 1999 drive-strength = <0x02>; 2000 bias-disable; 2001 }; 2002 }; 2003 2004 qup_spi3_default: qup-spi3-default { 2005 pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2006 function = "qup3"; 2007 drive-strength = <6>; 2008 bias-disable; 2009 }; 2010 2011 qup_i2c4_default: qup-i2c4-default { 2012 mux { 2013 pins = "gpio51", "gpio52"; 2014 function = "qup4"; 2015 }; 2016 2017 config { 2018 pins = "gpio51", "gpio52"; 2019 drive-strength = <0x02>; 2020 bias-disable; 2021 }; 2022 }; 2023 2024 qup_spi4_default: qup-spi4-default { 2025 pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2026 function = "qup4"; 2027 drive-strength = <6>; 2028 bias-disable; 2029 }; 2030 2031 qup_i2c5_default: qup-i2c5-default { 2032 mux { 2033 pins = "gpio121", "gpio122"; 2034 function = "qup5"; 2035 }; 2036 2037 config { 2038 pins = "gpio121", "gpio122"; 2039 drive-strength = <0x02>; 2040 bias-disable; 2041 }; 2042 }; 2043 2044 qup_spi5_default: qup-spi5-default { 2045 pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2046 function = "qup5"; 2047 drive-strength = <6>; 2048 bias-disable; 2049 }; 2050 2051 qup_i2c6_default: qup-i2c6-default { 2052 mux { 2053 pins = "gpio6", "gpio7"; 2054 function = "qup6"; 2055 }; 2056 2057 config { 2058 pins = "gpio6", "gpio7"; 2059 drive-strength = <0x02>; 2060 bias-disable; 2061 }; 2062 }; 2063 2064 qup_spi6_default: qup-spi6_default { 2065 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2066 function = "qup6"; 2067 drive-strength = <6>; 2068 bias-disable; 2069 }; 2070 2071 qup_i2c7_default: qup-i2c7-default { 2072 mux { 2073 pins = "gpio98", "gpio99"; 2074 function = "qup7"; 2075 }; 2076 2077 config { 2078 pins = "gpio98", "gpio99"; 2079 drive-strength = <0x02>; 2080 bias-disable; 2081 }; 2082 }; 2083 2084 qup_spi7_default: qup-spi7_default { 2085 pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2086 function = "qup7"; 2087 drive-strength = <6>; 2088 bias-disable; 2089 }; 2090 2091 qup_i2c8_default: qup-i2c8-default { 2092 mux { 2093 pins = "gpio88", "gpio89"; 2094 function = "qup8"; 2095 }; 2096 2097 config { 2098 pins = "gpio88", "gpio89"; 2099 drive-strength = <0x02>; 2100 bias-disable; 2101 }; 2102 }; 2103 2104 qup_spi8_default: qup-spi8-default { 2105 pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2106 function = "qup8"; 2107 drive-strength = <6>; 2108 bias-disable; 2109 }; 2110 2111 qup_i2c9_default: qup-i2c9-default { 2112 mux { 2113 pins = "gpio39", "gpio40"; 2114 function = "qup9"; 2115 }; 2116 2117 config { 2118 pins = "gpio39", "gpio40"; 2119 drive-strength = <0x02>; 2120 bias-disable; 2121 }; 2122 }; 2123 2124 qup_spi9_default: qup-spi9-default { 2125 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2126 function = "qup9"; 2127 drive-strength = <6>; 2128 bias-disable; 2129 }; 2130 2131 qup_i2c10_default: qup-i2c10-default { 2132 mux { 2133 pins = "gpio9", "gpio10"; 2134 function = "qup10"; 2135 }; 2136 2137 config { 2138 pins = "gpio9", "gpio10"; 2139 drive-strength = <0x02>; 2140 bias-disable; 2141 }; 2142 }; 2143 2144 qup_spi10_default: qup-spi10-default { 2145 pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2146 function = "qup10"; 2147 drive-strength = <6>; 2148 bias-disable; 2149 }; 2150 2151 qup_i2c11_default: qup-i2c11-default { 2152 mux { 2153 pins = "gpio94", "gpio95"; 2154 function = "qup11"; 2155 }; 2156 2157 config { 2158 pins = "gpio94", "gpio95"; 2159 drive-strength = <0x02>; 2160 bias-disable; 2161 }; 2162 }; 2163 2164 qup_spi11_default: qup-spi11-default { 2165 pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2166 function = "qup11"; 2167 drive-strength = <6>; 2168 bias-disable; 2169 }; 2170 2171 qup_i2c12_default: qup-i2c12-default { 2172 mux { 2173 pins = "gpio83", "gpio84"; 2174 function = "qup12"; 2175 }; 2176 2177 config { 2178 pins = "gpio83", "gpio84"; 2179 drive-strength = <0x02>; 2180 bias-disable; 2181 }; 2182 }; 2183 2184 qup_spi12_default: qup-spi12-default { 2185 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2186 function = "qup12"; 2187 drive-strength = <6>; 2188 bias-disable; 2189 }; 2190 2191 qup_i2c13_default: qup-i2c13-default { 2192 mux { 2193 pins = "gpio43", "gpio44"; 2194 function = "qup13"; 2195 }; 2196 2197 config { 2198 pins = "gpio43", "gpio44"; 2199 drive-strength = <0x02>; 2200 bias-disable; 2201 }; 2202 }; 2203 2204 qup_spi13_default: qup-spi13-default { 2205 pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2206 function = "qup13"; 2207 drive-strength = <6>; 2208 bias-disable; 2209 }; 2210 2211 qup_i2c14_default: qup-i2c14-default { 2212 mux { 2213 pins = "gpio47", "gpio48"; 2214 function = "qup14"; 2215 }; 2216 2217 config { 2218 pins = "gpio47", "gpio48"; 2219 drive-strength = <0x02>; 2220 bias-disable; 2221 }; 2222 }; 2223 2224 qup_spi14_default: qup-spi14-default { 2225 pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2226 function = "qup14"; 2227 drive-strength = <6>; 2228 bias-disable; 2229 }; 2230 2231 qup_i2c15_default: qup-i2c15-default { 2232 mux { 2233 pins = "gpio27", "gpio28"; 2234 function = "qup15"; 2235 }; 2236 2237 config { 2238 pins = "gpio27", "gpio28"; 2239 drive-strength = <0x02>; 2240 bias-disable; 2241 }; 2242 }; 2243 2244 qup_spi15_default: qup-spi15-default { 2245 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2246 function = "qup15"; 2247 drive-strength = <6>; 2248 bias-disable; 2249 }; 2250 2251 qup_i2c16_default: qup-i2c16-default { 2252 mux { 2253 pins = "gpio86", "gpio85"; 2254 function = "qup16"; 2255 }; 2256 2257 config { 2258 pins = "gpio86", "gpio85"; 2259 drive-strength = <0x02>; 2260 bias-disable; 2261 }; 2262 }; 2263 2264 qup_spi16_default: qup-spi16-default { 2265 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2266 function = "qup16"; 2267 drive-strength = <6>; 2268 bias-disable; 2269 }; 2270 2271 qup_i2c17_default: qup-i2c17-default { 2272 mux { 2273 pins = "gpio55", "gpio56"; 2274 function = "qup17"; 2275 }; 2276 2277 config { 2278 pins = "gpio55", "gpio56"; 2279 drive-strength = <0x02>; 2280 bias-disable; 2281 }; 2282 }; 2283 2284 qup_spi17_default: qup-spi17-default { 2285 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2286 function = "qup17"; 2287 drive-strength = <6>; 2288 bias-disable; 2289 }; 2290 2291 qup_i2c18_default: qup-i2c18-default { 2292 mux { 2293 pins = "gpio23", "gpio24"; 2294 function = "qup18"; 2295 }; 2296 2297 config { 2298 pins = "gpio23", "gpio24"; 2299 drive-strength = <0x02>; 2300 bias-disable; 2301 }; 2302 }; 2303 2304 qup_spi18_default: qup-spi18-default { 2305 pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2306 function = "qup18"; 2307 drive-strength = <6>; 2308 bias-disable; 2309 }; 2310 2311 qup_i2c19_default: qup-i2c19-default { 2312 mux { 2313 pins = "gpio57", "gpio58"; 2314 function = "qup19"; 2315 }; 2316 2317 config { 2318 pins = "gpio57", "gpio58"; 2319 drive-strength = <0x02>; 2320 bias-disable; 2321 }; 2322 }; 2323 2324 qup_spi19_default: qup-spi19-default { 2325 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2326 function = "qup19"; 2327 drive-strength = <6>; 2328 bias-disable; 2329 }; 2330 }; 2331 2332 remoteproc_mpss: remoteproc@4080000 { 2333 compatible = "qcom,sm8150-mpss-pas"; 2334 reg = <0x0 0x04080000 0x0 0x4040>; 2335 2336 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2337 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2338 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2339 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2340 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2341 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2342 interrupt-names = "wdog", "fatal", "ready", "handover", 2343 "stop-ack", "shutdown-ack"; 2344 2345 clocks = <&rpmhcc RPMH_CXO_CLK>; 2346 clock-names = "xo"; 2347 2348 power-domains = <&rpmhpd 7>, 2349 <&rpmhpd 0>; 2350 power-domain-names = "cx", "mss"; 2351 2352 memory-region = <&mpss_mem>; 2353 2354 qcom,qmp = <&aoss_qmp>; 2355 2356 qcom,smem-states = <&modem_smp2p_out 0>; 2357 qcom,smem-state-names = "stop"; 2358 2359 status = "disabled"; 2360 2361 glink-edge { 2362 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2363 label = "modem"; 2364 qcom,remote-pid = <1>; 2365 mboxes = <&apss_shared 12>; 2366 }; 2367 }; 2368 2369 stm@6002000 { 2370 compatible = "arm,coresight-stm", "arm,primecell"; 2371 reg = <0 0x06002000 0 0x1000>, 2372 <0 0x16280000 0 0x180000>; 2373 reg-names = "stm-base", "stm-stimulus-base"; 2374 2375 clocks = <&aoss_qmp>; 2376 clock-names = "apb_pclk"; 2377 2378 out-ports { 2379 port { 2380 stm_out: endpoint { 2381 remote-endpoint = <&funnel0_in7>; 2382 }; 2383 }; 2384 }; 2385 }; 2386 2387 funnel@6041000 { 2388 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2389 reg = <0 0x06041000 0 0x1000>; 2390 2391 clocks = <&aoss_qmp>; 2392 clock-names = "apb_pclk"; 2393 2394 out-ports { 2395 port { 2396 funnel0_out: endpoint { 2397 remote-endpoint = <&merge_funnel_in0>; 2398 }; 2399 }; 2400 }; 2401 2402 in-ports { 2403 #address-cells = <1>; 2404 #size-cells = <0>; 2405 2406 port@7 { 2407 reg = <7>; 2408 funnel0_in7: endpoint { 2409 remote-endpoint = <&stm_out>; 2410 }; 2411 }; 2412 }; 2413 }; 2414 2415 funnel@6042000 { 2416 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2417 reg = <0 0x06042000 0 0x1000>; 2418 2419 clocks = <&aoss_qmp>; 2420 clock-names = "apb_pclk"; 2421 2422 out-ports { 2423 port { 2424 funnel1_out: endpoint { 2425 remote-endpoint = <&merge_funnel_in1>; 2426 }; 2427 }; 2428 }; 2429 2430 in-ports { 2431 #address-cells = <1>; 2432 #size-cells = <0>; 2433 2434 port@4 { 2435 reg = <4>; 2436 funnel1_in4: endpoint { 2437 remote-endpoint = <&swao_replicator_out>; 2438 }; 2439 }; 2440 }; 2441 }; 2442 2443 funnel@6043000 { 2444 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2445 reg = <0 0x06043000 0 0x1000>; 2446 2447 clocks = <&aoss_qmp>; 2448 clock-names = "apb_pclk"; 2449 2450 out-ports { 2451 port { 2452 funnel2_out: endpoint { 2453 remote-endpoint = <&merge_funnel_in2>; 2454 }; 2455 }; 2456 }; 2457 2458 in-ports { 2459 #address-cells = <1>; 2460 #size-cells = <0>; 2461 2462 port@2 { 2463 reg = <2>; 2464 funnel2_in2: endpoint { 2465 remote-endpoint = <&apss_merge_funnel_out>; 2466 }; 2467 }; 2468 }; 2469 }; 2470 2471 funnel@6045000 { 2472 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2473 reg = <0 0x06045000 0 0x1000>; 2474 2475 clocks = <&aoss_qmp>; 2476 clock-names = "apb_pclk"; 2477 2478 out-ports { 2479 port { 2480 merge_funnel_out: endpoint { 2481 remote-endpoint = <&etf_in>; 2482 }; 2483 }; 2484 }; 2485 2486 in-ports { 2487 #address-cells = <1>; 2488 #size-cells = <0>; 2489 2490 port@0 { 2491 reg = <0>; 2492 merge_funnel_in0: endpoint { 2493 remote-endpoint = <&funnel0_out>; 2494 }; 2495 }; 2496 2497 port@1 { 2498 reg = <1>; 2499 merge_funnel_in1: endpoint { 2500 remote-endpoint = <&funnel1_out>; 2501 }; 2502 }; 2503 2504 port@2 { 2505 reg = <2>; 2506 merge_funnel_in2: endpoint { 2507 remote-endpoint = <&funnel2_out>; 2508 }; 2509 }; 2510 }; 2511 }; 2512 2513 replicator@6046000 { 2514 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2515 reg = <0 0x06046000 0 0x1000>; 2516 2517 clocks = <&aoss_qmp>; 2518 clock-names = "apb_pclk"; 2519 2520 out-ports { 2521 #address-cells = <1>; 2522 #size-cells = <0>; 2523 2524 port@0 { 2525 reg = <0>; 2526 replicator_out0: endpoint { 2527 remote-endpoint = <&etr_in>; 2528 }; 2529 }; 2530 2531 port@1 { 2532 reg = <1>; 2533 replicator_out1: endpoint { 2534 remote-endpoint = <&replicator1_in>; 2535 }; 2536 }; 2537 }; 2538 2539 in-ports { 2540 port { 2541 replicator_in0: endpoint { 2542 remote-endpoint = <&etf_out>; 2543 }; 2544 }; 2545 }; 2546 }; 2547 2548 etf@6047000 { 2549 compatible = "arm,coresight-tmc", "arm,primecell"; 2550 reg = <0 0x06047000 0 0x1000>; 2551 2552 clocks = <&aoss_qmp>; 2553 clock-names = "apb_pclk"; 2554 2555 out-ports { 2556 port { 2557 etf_out: endpoint { 2558 remote-endpoint = <&replicator_in0>; 2559 }; 2560 }; 2561 }; 2562 2563 in-ports { 2564 port { 2565 etf_in: endpoint { 2566 remote-endpoint = <&merge_funnel_out>; 2567 }; 2568 }; 2569 }; 2570 }; 2571 2572 etr@6048000 { 2573 compatible = "arm,coresight-tmc", "arm,primecell"; 2574 reg = <0 0x06048000 0 0x1000>; 2575 iommus = <&apps_smmu 0x05e0 0x0>; 2576 2577 clocks = <&aoss_qmp>; 2578 clock-names = "apb_pclk"; 2579 arm,scatter-gather; 2580 2581 in-ports { 2582 port { 2583 etr_in: endpoint { 2584 remote-endpoint = <&replicator_out0>; 2585 }; 2586 }; 2587 }; 2588 }; 2589 2590 replicator@604a000 { 2591 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2592 reg = <0 0x0604a000 0 0x1000>; 2593 2594 clocks = <&aoss_qmp>; 2595 clock-names = "apb_pclk"; 2596 2597 out-ports { 2598 #address-cells = <1>; 2599 #size-cells = <0>; 2600 2601 port@1 { 2602 reg = <1>; 2603 replicator1_out: endpoint { 2604 remote-endpoint = <&swao_funnel_in>; 2605 }; 2606 }; 2607 }; 2608 2609 in-ports { 2610 #address-cells = <1>; 2611 #size-cells = <0>; 2612 2613 port@1 { 2614 reg = <1>; 2615 replicator1_in: endpoint { 2616 remote-endpoint = <&replicator_out1>; 2617 }; 2618 }; 2619 }; 2620 }; 2621 2622 funnel@6b08000 { 2623 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2624 reg = <0 0x06b08000 0 0x1000>; 2625 2626 clocks = <&aoss_qmp>; 2627 clock-names = "apb_pclk"; 2628 2629 out-ports { 2630 port { 2631 swao_funnel_out: endpoint { 2632 remote-endpoint = <&swao_etf_in>; 2633 }; 2634 }; 2635 }; 2636 2637 in-ports { 2638 #address-cells = <1>; 2639 #size-cells = <0>; 2640 2641 port@6 { 2642 reg = <6>; 2643 swao_funnel_in: endpoint { 2644 remote-endpoint = <&replicator1_out>; 2645 }; 2646 }; 2647 }; 2648 }; 2649 2650 etf@6b09000 { 2651 compatible = "arm,coresight-tmc", "arm,primecell"; 2652 reg = <0 0x06b09000 0 0x1000>; 2653 2654 clocks = <&aoss_qmp>; 2655 clock-names = "apb_pclk"; 2656 2657 out-ports { 2658 port { 2659 swao_etf_out: endpoint { 2660 remote-endpoint = <&swao_replicator_in>; 2661 }; 2662 }; 2663 }; 2664 2665 in-ports { 2666 port { 2667 swao_etf_in: endpoint { 2668 remote-endpoint = <&swao_funnel_out>; 2669 }; 2670 }; 2671 }; 2672 }; 2673 2674 replicator@6b0a000 { 2675 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2676 reg = <0 0x06b0a000 0 0x1000>; 2677 2678 clocks = <&aoss_qmp>; 2679 clock-names = "apb_pclk"; 2680 qcom,replicator-loses-context; 2681 2682 out-ports { 2683 port { 2684 swao_replicator_out: endpoint { 2685 remote-endpoint = <&funnel1_in4>; 2686 }; 2687 }; 2688 }; 2689 2690 in-ports { 2691 port { 2692 swao_replicator_in: endpoint { 2693 remote-endpoint = <&swao_etf_out>; 2694 }; 2695 }; 2696 }; 2697 }; 2698 2699 etm@7040000 { 2700 compatible = "arm,coresight-etm4x", "arm,primecell"; 2701 reg = <0 0x07040000 0 0x1000>; 2702 2703 cpu = <&CPU0>; 2704 2705 clocks = <&aoss_qmp>; 2706 clock-names = "apb_pclk"; 2707 arm,coresight-loses-context-with-cpu; 2708 qcom,skip-power-up; 2709 2710 out-ports { 2711 port { 2712 etm0_out: endpoint { 2713 remote-endpoint = <&apss_funnel_in0>; 2714 }; 2715 }; 2716 }; 2717 }; 2718 2719 etm@7140000 { 2720 compatible = "arm,coresight-etm4x", "arm,primecell"; 2721 reg = <0 0x07140000 0 0x1000>; 2722 2723 cpu = <&CPU1>; 2724 2725 clocks = <&aoss_qmp>; 2726 clock-names = "apb_pclk"; 2727 arm,coresight-loses-context-with-cpu; 2728 qcom,skip-power-up; 2729 2730 out-ports { 2731 port { 2732 etm1_out: endpoint { 2733 remote-endpoint = <&apss_funnel_in1>; 2734 }; 2735 }; 2736 }; 2737 }; 2738 2739 etm@7240000 { 2740 compatible = "arm,coresight-etm4x", "arm,primecell"; 2741 reg = <0 0x07240000 0 0x1000>; 2742 2743 cpu = <&CPU2>; 2744 2745 clocks = <&aoss_qmp>; 2746 clock-names = "apb_pclk"; 2747 arm,coresight-loses-context-with-cpu; 2748 qcom,skip-power-up; 2749 2750 out-ports { 2751 port { 2752 etm2_out: endpoint { 2753 remote-endpoint = <&apss_funnel_in2>; 2754 }; 2755 }; 2756 }; 2757 }; 2758 2759 etm@7340000 { 2760 compatible = "arm,coresight-etm4x", "arm,primecell"; 2761 reg = <0 0x07340000 0 0x1000>; 2762 2763 cpu = <&CPU3>; 2764 2765 clocks = <&aoss_qmp>; 2766 clock-names = "apb_pclk"; 2767 arm,coresight-loses-context-with-cpu; 2768 qcom,skip-power-up; 2769 2770 out-ports { 2771 port { 2772 etm3_out: endpoint { 2773 remote-endpoint = <&apss_funnel_in3>; 2774 }; 2775 }; 2776 }; 2777 }; 2778 2779 etm@7440000 { 2780 compatible = "arm,coresight-etm4x", "arm,primecell"; 2781 reg = <0 0x07440000 0 0x1000>; 2782 2783 cpu = <&CPU4>; 2784 2785 clocks = <&aoss_qmp>; 2786 clock-names = "apb_pclk"; 2787 arm,coresight-loses-context-with-cpu; 2788 qcom,skip-power-up; 2789 2790 out-ports { 2791 port { 2792 etm4_out: endpoint { 2793 remote-endpoint = <&apss_funnel_in4>; 2794 }; 2795 }; 2796 }; 2797 }; 2798 2799 etm@7540000 { 2800 compatible = "arm,coresight-etm4x", "arm,primecell"; 2801 reg = <0 0x07540000 0 0x1000>; 2802 2803 cpu = <&CPU5>; 2804 2805 clocks = <&aoss_qmp>; 2806 clock-names = "apb_pclk"; 2807 arm,coresight-loses-context-with-cpu; 2808 qcom,skip-power-up; 2809 2810 out-ports { 2811 port { 2812 etm5_out: endpoint { 2813 remote-endpoint = <&apss_funnel_in5>; 2814 }; 2815 }; 2816 }; 2817 }; 2818 2819 etm@7640000 { 2820 compatible = "arm,coresight-etm4x", "arm,primecell"; 2821 reg = <0 0x07640000 0 0x1000>; 2822 2823 cpu = <&CPU6>; 2824 2825 clocks = <&aoss_qmp>; 2826 clock-names = "apb_pclk"; 2827 arm,coresight-loses-context-with-cpu; 2828 qcom,skip-power-up; 2829 2830 out-ports { 2831 port { 2832 etm6_out: endpoint { 2833 remote-endpoint = <&apss_funnel_in6>; 2834 }; 2835 }; 2836 }; 2837 }; 2838 2839 etm@7740000 { 2840 compatible = "arm,coresight-etm4x", "arm,primecell"; 2841 reg = <0 0x07740000 0 0x1000>; 2842 2843 cpu = <&CPU7>; 2844 2845 clocks = <&aoss_qmp>; 2846 clock-names = "apb_pclk"; 2847 arm,coresight-loses-context-with-cpu; 2848 qcom,skip-power-up; 2849 2850 out-ports { 2851 port { 2852 etm7_out: endpoint { 2853 remote-endpoint = <&apss_funnel_in7>; 2854 }; 2855 }; 2856 }; 2857 }; 2858 2859 funnel@7800000 { /* APSS Funnel */ 2860 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2861 reg = <0 0x07800000 0 0x1000>; 2862 2863 clocks = <&aoss_qmp>; 2864 clock-names = "apb_pclk"; 2865 2866 out-ports { 2867 port { 2868 apss_funnel_out: endpoint { 2869 remote-endpoint = <&apss_merge_funnel_in>; 2870 }; 2871 }; 2872 }; 2873 2874 in-ports { 2875 #address-cells = <1>; 2876 #size-cells = <0>; 2877 2878 port@0 { 2879 reg = <0>; 2880 apss_funnel_in0: endpoint { 2881 remote-endpoint = <&etm0_out>; 2882 }; 2883 }; 2884 2885 port@1 { 2886 reg = <1>; 2887 apss_funnel_in1: endpoint { 2888 remote-endpoint = <&etm1_out>; 2889 }; 2890 }; 2891 2892 port@2 { 2893 reg = <2>; 2894 apss_funnel_in2: endpoint { 2895 remote-endpoint = <&etm2_out>; 2896 }; 2897 }; 2898 2899 port@3 { 2900 reg = <3>; 2901 apss_funnel_in3: endpoint { 2902 remote-endpoint = <&etm3_out>; 2903 }; 2904 }; 2905 2906 port@4 { 2907 reg = <4>; 2908 apss_funnel_in4: endpoint { 2909 remote-endpoint = <&etm4_out>; 2910 }; 2911 }; 2912 2913 port@5 { 2914 reg = <5>; 2915 apss_funnel_in5: endpoint { 2916 remote-endpoint = <&etm5_out>; 2917 }; 2918 }; 2919 2920 port@6 { 2921 reg = <6>; 2922 apss_funnel_in6: endpoint { 2923 remote-endpoint = <&etm6_out>; 2924 }; 2925 }; 2926 2927 port@7 { 2928 reg = <7>; 2929 apss_funnel_in7: endpoint { 2930 remote-endpoint = <&etm7_out>; 2931 }; 2932 }; 2933 }; 2934 }; 2935 2936 funnel@7810000 { 2937 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2938 reg = <0 0x07810000 0 0x1000>; 2939 2940 clocks = <&aoss_qmp>; 2941 clock-names = "apb_pclk"; 2942 2943 out-ports { 2944 port { 2945 apss_merge_funnel_out: endpoint { 2946 remote-endpoint = <&funnel2_in2>; 2947 }; 2948 }; 2949 }; 2950 2951 in-ports { 2952 port { 2953 apss_merge_funnel_in: endpoint { 2954 remote-endpoint = <&apss_funnel_out>; 2955 }; 2956 }; 2957 }; 2958 }; 2959 2960 remoteproc_cdsp: remoteproc@8300000 { 2961 compatible = "qcom,sm8150-cdsp-pas"; 2962 reg = <0x0 0x08300000 0x0 0x4040>; 2963 2964 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2965 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2966 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2967 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2968 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2969 interrupt-names = "wdog", "fatal", "ready", 2970 "handover", "stop-ack"; 2971 2972 clocks = <&rpmhcc RPMH_CXO_CLK>; 2973 clock-names = "xo"; 2974 2975 power-domains = <&rpmhpd 7>; 2976 2977 memory-region = <&cdsp_mem>; 2978 2979 qcom,qmp = <&aoss_qmp>; 2980 2981 qcom,smem-states = <&cdsp_smp2p_out 0>; 2982 qcom,smem-state-names = "stop"; 2983 2984 status = "disabled"; 2985 2986 glink-edge { 2987 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 2988 label = "cdsp"; 2989 qcom,remote-pid = <5>; 2990 mboxes = <&apss_shared 4>; 2991 2992 fastrpc { 2993 compatible = "qcom,fastrpc"; 2994 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2995 label = "cdsp"; 2996 #address-cells = <1>; 2997 #size-cells = <0>; 2998 2999 compute-cb@1 { 3000 compatible = "qcom,fastrpc-compute-cb"; 3001 reg = <1>; 3002 iommus = <&apps_smmu 0x1401 0x2040>, 3003 <&apps_smmu 0x1421 0x0>, 3004 <&apps_smmu 0x2001 0x420>, 3005 <&apps_smmu 0x2041 0x0>; 3006 }; 3007 3008 compute-cb@2 { 3009 compatible = "qcom,fastrpc-compute-cb"; 3010 reg = <2>; 3011 iommus = <&apps_smmu 0x2 0x3440>, 3012 <&apps_smmu 0x22 0x3400>; 3013 }; 3014 3015 compute-cb@3 { 3016 compatible = "qcom,fastrpc-compute-cb"; 3017 reg = <3>; 3018 iommus = <&apps_smmu 0x3 0x3440>, 3019 <&apps_smmu 0x1423 0x0>, 3020 <&apps_smmu 0x2023 0x0>; 3021 }; 3022 3023 compute-cb@4 { 3024 compatible = "qcom,fastrpc-compute-cb"; 3025 reg = <4>; 3026 iommus = <&apps_smmu 0x4 0x3440>, 3027 <&apps_smmu 0x24 0x3400>; 3028 }; 3029 3030 compute-cb@5 { 3031 compatible = "qcom,fastrpc-compute-cb"; 3032 reg = <5>; 3033 iommus = <&apps_smmu 0x5 0x3440>, 3034 <&apps_smmu 0x25 0x3400>; 3035 }; 3036 3037 compute-cb@6 { 3038 compatible = "qcom,fastrpc-compute-cb"; 3039 reg = <6>; 3040 iommus = <&apps_smmu 0x6 0x3460>; 3041 }; 3042 3043 compute-cb@7 { 3044 compatible = "qcom,fastrpc-compute-cb"; 3045 reg = <7>; 3046 iommus = <&apps_smmu 0x7 0x3460>; 3047 }; 3048 3049 compute-cb@8 { 3050 compatible = "qcom,fastrpc-compute-cb"; 3051 reg = <8>; 3052 iommus = <&apps_smmu 0x8 0x3460>; 3053 }; 3054 3055 /* note: secure cb9 in downstream */ 3056 }; 3057 }; 3058 }; 3059 3060 usb_1_hsphy: phy@88e2000 { 3061 compatible = "qcom,sm8150-usb-hs-phy", 3062 "qcom,usb-snps-hs-7nm-phy"; 3063 reg = <0 0x088e2000 0 0x400>; 3064 status = "disabled"; 3065 #phy-cells = <0>; 3066 3067 clocks = <&rpmhcc RPMH_CXO_CLK>; 3068 clock-names = "ref"; 3069 3070 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3071 }; 3072 3073 usb_2_hsphy: phy@88e3000 { 3074 compatible = "qcom,sm8150-usb-hs-phy", 3075 "qcom,usb-snps-hs-7nm-phy"; 3076 reg = <0 0x088e3000 0 0x400>; 3077 status = "disabled"; 3078 #phy-cells = <0>; 3079 3080 clocks = <&rpmhcc RPMH_CXO_CLK>; 3081 clock-names = "ref"; 3082 3083 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3084 }; 3085 3086 usb_1_qmpphy: phy@88e9000 { 3087 compatible = "qcom,sm8150-qmp-usb3-phy"; 3088 reg = <0 0x088e9000 0 0x18c>, 3089 <0 0x088e8000 0 0x10>; 3090 status = "disabled"; 3091 #address-cells = <2>; 3092 #size-cells = <2>; 3093 ranges; 3094 3095 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3096 <&rpmhcc RPMH_CXO_CLK>, 3097 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3098 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3099 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3100 3101 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3102 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3103 reset-names = "phy", "common"; 3104 3105 usb_1_ssphy: phy@88e9200 { 3106 reg = <0 0x088e9200 0 0x200>, 3107 <0 0x088e9400 0 0x200>, 3108 <0 0x088e9c00 0 0x218>, 3109 <0 0x088e9600 0 0x200>, 3110 <0 0x088e9800 0 0x200>, 3111 <0 0x088e9a00 0 0x100>; 3112 #clock-cells = <0>; 3113 #phy-cells = <0>; 3114 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3115 clock-names = "pipe0"; 3116 clock-output-names = "usb3_phy_pipe_clk_src"; 3117 }; 3118 }; 3119 3120 usb_2_qmpphy: phy@88eb000 { 3121 compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 3122 reg = <0 0x088eb000 0 0x200>; 3123 status = "disabled"; 3124 #address-cells = <2>; 3125 #size-cells = <2>; 3126 ranges; 3127 3128 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3129 <&rpmhcc RPMH_CXO_CLK>, 3130 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3131 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3132 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3133 3134 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3135 <&gcc GCC_USB3_PHY_SEC_BCR>; 3136 reset-names = "phy", "common"; 3137 3138 usb_2_ssphy: phy@88eb200 { 3139 reg = <0 0x088eb200 0 0x200>, 3140 <0 0x088eb400 0 0x200>, 3141 <0 0x088eb800 0 0x800>, 3142 <0 0x088eb600 0 0x200>; 3143 #clock-cells = <0>; 3144 #phy-cells = <0>; 3145 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3146 clock-names = "pipe0"; 3147 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3148 }; 3149 }; 3150 3151 dc_noc: interconnect@9160000 { 3152 compatible = "qcom,sm8150-dc-noc"; 3153 reg = <0 0x09160000 0 0x3200>; 3154 #interconnect-cells = <1>; 3155 qcom,bcm-voters = <&apps_bcm_voter>; 3156 }; 3157 3158 gem_noc: interconnect@9680000 { 3159 compatible = "qcom,sm8150-gem-noc"; 3160 reg = <0 0x09680000 0 0x3e200>; 3161 #interconnect-cells = <1>; 3162 qcom,bcm-voters = <&apps_bcm_voter>; 3163 }; 3164 3165 usb_1: usb@a6f8800 { 3166 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3167 reg = <0 0x0a6f8800 0 0x400>; 3168 status = "disabled"; 3169 #address-cells = <2>; 3170 #size-cells = <2>; 3171 ranges; 3172 dma-ranges; 3173 3174 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3175 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3176 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3177 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3178 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3179 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3180 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3181 "sleep", "xo"; 3182 3183 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3184 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3185 assigned-clock-rates = <19200000>, <200000000>; 3186 3187 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3188 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3189 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3190 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3191 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3192 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3193 3194 power-domains = <&gcc USB30_PRIM_GDSC>; 3195 3196 resets = <&gcc GCC_USB30_PRIM_BCR>; 3197 3198 usb_1_dwc3: dwc3@a600000 { 3199 compatible = "snps,dwc3"; 3200 reg = <0 0x0a600000 0 0xcd00>; 3201 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3202 iommus = <&apps_smmu 0x140 0>; 3203 snps,dis_u2_susphy_quirk; 3204 snps,dis_enblslpm_quirk; 3205 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3206 phy-names = "usb2-phy", "usb3-phy"; 3207 }; 3208 }; 3209 3210 usb_2: usb@a8f8800 { 3211 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3212 reg = <0 0x0a8f8800 0 0x400>; 3213 status = "disabled"; 3214 #address-cells = <2>; 3215 #size-cells = <2>; 3216 ranges; 3217 dma-ranges; 3218 3219 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3220 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3221 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3222 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3223 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3224 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3225 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3226 "sleep", "xo"; 3227 3228 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3229 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3230 assigned-clock-rates = <19200000>, <200000000>; 3231 3232 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3233 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 3234 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3235 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 3236 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3237 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3238 3239 power-domains = <&gcc USB30_SEC_GDSC>; 3240 3241 resets = <&gcc GCC_USB30_SEC_BCR>; 3242 3243 usb_2_dwc3: usb@a800000 { 3244 compatible = "snps,dwc3"; 3245 reg = <0 0x0a800000 0 0xcd00>; 3246 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3247 iommus = <&apps_smmu 0x160 0>; 3248 snps,dis_u2_susphy_quirk; 3249 snps,dis_enblslpm_quirk; 3250 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3251 phy-names = "usb2-phy", "usb3-phy"; 3252 }; 3253 }; 3254 3255 camnoc_virt: interconnect@ac00000 { 3256 compatible = "qcom,sm8150-camnoc-virt"; 3257 reg = <0 0x0ac00000 0 0x1000>; 3258 #interconnect-cells = <1>; 3259 qcom,bcm-voters = <&apps_bcm_voter>; 3260 }; 3261 3262 aoss_qmp: power-controller@c300000 { 3263 compatible = "qcom,sm8150-aoss-qmp"; 3264 reg = <0x0 0x0c300000 0x0 0x400>; 3265 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3266 mboxes = <&apss_shared 0>; 3267 3268 #clock-cells = <0>; 3269 }; 3270 3271 sram@c3f0000 { 3272 compatible = "qcom,rpmh-stats"; 3273 reg = <0 0x0c3f0000 0 0x400>; 3274 }; 3275 3276 tsens0: thermal-sensor@c263000 { 3277 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3278 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3279 <0 0x0c222000 0 0x1ff>; /* SROT */ 3280 #qcom,sensors = <16>; 3281 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3282 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3283 interrupt-names = "uplow", "critical"; 3284 #thermal-sensor-cells = <1>; 3285 }; 3286 3287 tsens1: thermal-sensor@c265000 { 3288 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3289 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3290 <0 0x0c223000 0 0x1ff>; /* SROT */ 3291 #qcom,sensors = <8>; 3292 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3293 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3294 interrupt-names = "uplow", "critical"; 3295 #thermal-sensor-cells = <1>; 3296 }; 3297 3298 spmi_bus: spmi@c440000 { 3299 compatible = "qcom,spmi-pmic-arb"; 3300 reg = <0x0 0x0c440000 0x0 0x0001100>, 3301 <0x0 0x0c600000 0x0 0x2000000>, 3302 <0x0 0x0e600000 0x0 0x0100000>, 3303 <0x0 0x0e700000 0x0 0x00a0000>, 3304 <0x0 0x0c40a000 0x0 0x0026000>; 3305 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3306 interrupt-names = "periph_irq"; 3307 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3308 qcom,ee = <0>; 3309 qcom,channel = <0>; 3310 #address-cells = <2>; 3311 #size-cells = <0>; 3312 interrupt-controller; 3313 #interrupt-cells = <4>; 3314 cell-index = <0>; 3315 }; 3316 3317 apps_smmu: iommu@15000000 { 3318 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 3319 reg = <0 0x15000000 0 0x100000>; 3320 #iommu-cells = <2>; 3321 #global-interrupts = <1>; 3322 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3331 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3332 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3333 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3334 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3336 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3337 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3338 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3340 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3341 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3342 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3343 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3344 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3345 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3347 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3349 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3350 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3351 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3352 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3353 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3354 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3360 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3362 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3387 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3388 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3389 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3390 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3391 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3393 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3394 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3395 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3396 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3397 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3398 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3399 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3400 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3401 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3402 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 3403 }; 3404 3405 remoteproc_adsp: remoteproc@17300000 { 3406 compatible = "qcom,sm8150-adsp-pas"; 3407 reg = <0x0 0x17300000 0x0 0x4040>; 3408 3409 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3410 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3411 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3412 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3413 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3414 interrupt-names = "wdog", "fatal", "ready", 3415 "handover", "stop-ack"; 3416 3417 clocks = <&rpmhcc RPMH_CXO_CLK>; 3418 clock-names = "xo"; 3419 3420 power-domains = <&rpmhpd 7>; 3421 3422 memory-region = <&adsp_mem>; 3423 3424 qcom,qmp = <&aoss_qmp>; 3425 3426 qcom,smem-states = <&adsp_smp2p_out 0>; 3427 qcom,smem-state-names = "stop"; 3428 3429 status = "disabled"; 3430 3431 glink-edge { 3432 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3433 label = "lpass"; 3434 qcom,remote-pid = <2>; 3435 mboxes = <&apss_shared 8>; 3436 3437 fastrpc { 3438 compatible = "qcom,fastrpc"; 3439 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3440 label = "adsp"; 3441 #address-cells = <1>; 3442 #size-cells = <0>; 3443 3444 compute-cb@3 { 3445 compatible = "qcom,fastrpc-compute-cb"; 3446 reg = <3>; 3447 iommus = <&apps_smmu 0x1b23 0x0>; 3448 }; 3449 3450 compute-cb@4 { 3451 compatible = "qcom,fastrpc-compute-cb"; 3452 reg = <4>; 3453 iommus = <&apps_smmu 0x1b24 0x0>; 3454 }; 3455 3456 compute-cb@5 { 3457 compatible = "qcom,fastrpc-compute-cb"; 3458 reg = <5>; 3459 iommus = <&apps_smmu 0x1b25 0x0>; 3460 }; 3461 }; 3462 }; 3463 }; 3464 3465 intc: interrupt-controller@17a00000 { 3466 compatible = "arm,gic-v3"; 3467 interrupt-controller; 3468 #interrupt-cells = <3>; 3469 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3470 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3471 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3472 }; 3473 3474 apss_shared: mailbox@17c00000 { 3475 compatible = "qcom,sm8150-apss-shared"; 3476 reg = <0x0 0x17c00000 0x0 0x1000>; 3477 #mbox-cells = <1>; 3478 }; 3479 3480 watchdog@17c10000 { 3481 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 3482 reg = <0 0x17c10000 0 0x1000>; 3483 clocks = <&sleep_clk>; 3484 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3485 }; 3486 3487 timer@17c20000 { 3488 #address-cells = <2>; 3489 #size-cells = <2>; 3490 ranges; 3491 compatible = "arm,armv7-timer-mem"; 3492 reg = <0x0 0x17c20000 0x0 0x1000>; 3493 clock-frequency = <19200000>; 3494 3495 frame@17c21000{ 3496 frame-number = <0>; 3497 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3499 reg = <0x0 0x17c21000 0x0 0x1000>, 3500 <0x0 0x17c22000 0x0 0x1000>; 3501 }; 3502 3503 frame@17c23000 { 3504 frame-number = <1>; 3505 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3506 reg = <0x0 0x17c23000 0x0 0x1000>; 3507 status = "disabled"; 3508 }; 3509 3510 frame@17c25000 { 3511 frame-number = <2>; 3512 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3513 reg = <0x0 0x17c25000 0x0 0x1000>; 3514 status = "disabled"; 3515 }; 3516 3517 frame@17c27000 { 3518 frame-number = <3>; 3519 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3520 reg = <0x0 0x17c26000 0x0 0x1000>; 3521 status = "disabled"; 3522 }; 3523 3524 frame@17c29000 { 3525 frame-number = <4>; 3526 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3527 reg = <0x0 0x17c29000 0x0 0x1000>; 3528 status = "disabled"; 3529 }; 3530 3531 frame@17c2b000 { 3532 frame-number = <5>; 3533 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3534 reg = <0x0 0x17c2b000 0x0 0x1000>; 3535 status = "disabled"; 3536 }; 3537 3538 frame@17c2d000 { 3539 frame-number = <6>; 3540 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3541 reg = <0x0 0x17c2d000 0x0 0x1000>; 3542 status = "disabled"; 3543 }; 3544 }; 3545 3546 apps_rsc: rsc@18200000 { 3547 label = "apps_rsc"; 3548 compatible = "qcom,rpmh-rsc"; 3549 reg = <0x0 0x18200000 0x0 0x10000>, 3550 <0x0 0x18210000 0x0 0x10000>, 3551 <0x0 0x18220000 0x0 0x10000>; 3552 reg-names = "drv-0", "drv-1", "drv-2"; 3553 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3554 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3555 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3556 qcom,tcs-offset = <0xd00>; 3557 qcom,drv-id = <2>; 3558 qcom,tcs-config = <ACTIVE_TCS 2>, 3559 <SLEEP_TCS 1>, 3560 <WAKE_TCS 1>, 3561 <CONTROL_TCS 0>; 3562 3563 rpmhcc: clock-controller { 3564 compatible = "qcom,sm8150-rpmh-clk"; 3565 #clock-cells = <1>; 3566 clock-names = "xo"; 3567 clocks = <&xo_board>; 3568 }; 3569 3570 rpmhpd: power-controller { 3571 compatible = "qcom,sm8150-rpmhpd"; 3572 #power-domain-cells = <1>; 3573 operating-points-v2 = <&rpmhpd_opp_table>; 3574 3575 rpmhpd_opp_table: opp-table { 3576 compatible = "operating-points-v2"; 3577 3578 rpmhpd_opp_ret: opp1 { 3579 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3580 }; 3581 3582 rpmhpd_opp_min_svs: opp2 { 3583 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3584 }; 3585 3586 rpmhpd_opp_low_svs: opp3 { 3587 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3588 }; 3589 3590 rpmhpd_opp_svs: opp4 { 3591 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3592 }; 3593 3594 rpmhpd_opp_svs_l1: opp5 { 3595 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3596 }; 3597 3598 rpmhpd_opp_svs_l2: opp6 { 3599 opp-level = <224>; 3600 }; 3601 3602 rpmhpd_opp_nom: opp7 { 3603 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3604 }; 3605 3606 rpmhpd_opp_nom_l1: opp8 { 3607 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3608 }; 3609 3610 rpmhpd_opp_nom_l2: opp9 { 3611 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3612 }; 3613 3614 rpmhpd_opp_turbo: opp10 { 3615 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3616 }; 3617 3618 rpmhpd_opp_turbo_l1: opp11 { 3619 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3620 }; 3621 }; 3622 }; 3623 3624 apps_bcm_voter: bcm_voter { 3625 compatible = "qcom,bcm-voter"; 3626 }; 3627 }; 3628 3629 osm_l3: interconnect@18321000 { 3630 compatible = "qcom,sm8150-osm-l3"; 3631 reg = <0 0x18321000 0 0x1400>; 3632 3633 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3634 clock-names = "xo", "alternate"; 3635 3636 #interconnect-cells = <1>; 3637 }; 3638 3639 cpufreq_hw: cpufreq@18323000 { 3640 compatible = "qcom,cpufreq-hw"; 3641 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 3642 <0 0x18327800 0 0x1400>; 3643 reg-names = "freq-domain0", "freq-domain1", 3644 "freq-domain2"; 3645 3646 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3647 clock-names = "xo", "alternate"; 3648 3649 #freq-domain-cells = <1>; 3650 }; 3651 3652 wifi: wifi@18800000 { 3653 compatible = "qcom,wcn3990-wifi"; 3654 reg = <0 0x18800000 0 0x800000>; 3655 reg-names = "membase"; 3656 memory-region = <&wlan_mem>; 3657 clock-names = "cxo_ref_clk_pin", "qdss"; 3658 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 3659 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3660 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3661 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3662 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3663 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3664 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3665 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3666 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3667 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3668 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3669 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3670 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3671 iommus = <&apps_smmu 0x0640 0x1>; 3672 status = "disabled"; 3673 }; 3674 }; 3675 3676 timer { 3677 compatible = "arm,armv8-timer"; 3678 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 3679 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 3680 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 3681 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 3682 }; 3683 3684 thermal-zones { 3685 cpu0-thermal { 3686 polling-delay-passive = <250>; 3687 polling-delay = <1000>; 3688 3689 thermal-sensors = <&tsens0 1>; 3690 3691 trips { 3692 cpu0_alert0: trip-point0 { 3693 temperature = <90000>; 3694 hysteresis = <2000>; 3695 type = "passive"; 3696 }; 3697 3698 cpu0_alert1: trip-point1 { 3699 temperature = <95000>; 3700 hysteresis = <2000>; 3701 type = "passive"; 3702 }; 3703 3704 cpu0_crit: cpu_crit { 3705 temperature = <110000>; 3706 hysteresis = <1000>; 3707 type = "critical"; 3708 }; 3709 }; 3710 3711 cooling-maps { 3712 map0 { 3713 trip = <&cpu0_alert0>; 3714 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3715 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3716 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3717 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3718 }; 3719 map1 { 3720 trip = <&cpu0_alert1>; 3721 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3722 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3723 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3724 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3725 }; 3726 }; 3727 }; 3728 3729 cpu1-thermal { 3730 polling-delay-passive = <250>; 3731 polling-delay = <1000>; 3732 3733 thermal-sensors = <&tsens0 2>; 3734 3735 trips { 3736 cpu1_alert0: trip-point0 { 3737 temperature = <90000>; 3738 hysteresis = <2000>; 3739 type = "passive"; 3740 }; 3741 3742 cpu1_alert1: trip-point1 { 3743 temperature = <95000>; 3744 hysteresis = <2000>; 3745 type = "passive"; 3746 }; 3747 3748 cpu1_crit: cpu_crit { 3749 temperature = <110000>; 3750 hysteresis = <1000>; 3751 type = "critical"; 3752 }; 3753 }; 3754 3755 cooling-maps { 3756 map0 { 3757 trip = <&cpu1_alert0>; 3758 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3759 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3760 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3761 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3762 }; 3763 map1 { 3764 trip = <&cpu1_alert1>; 3765 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3766 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3767 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3768 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3769 }; 3770 }; 3771 }; 3772 3773 cpu2-thermal { 3774 polling-delay-passive = <250>; 3775 polling-delay = <1000>; 3776 3777 thermal-sensors = <&tsens0 3>; 3778 3779 trips { 3780 cpu2_alert0: trip-point0 { 3781 temperature = <90000>; 3782 hysteresis = <2000>; 3783 type = "passive"; 3784 }; 3785 3786 cpu2_alert1: trip-point1 { 3787 temperature = <95000>; 3788 hysteresis = <2000>; 3789 type = "passive"; 3790 }; 3791 3792 cpu2_crit: cpu_crit { 3793 temperature = <110000>; 3794 hysteresis = <1000>; 3795 type = "critical"; 3796 }; 3797 }; 3798 3799 cooling-maps { 3800 map0 { 3801 trip = <&cpu2_alert0>; 3802 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3803 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3804 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3805 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3806 }; 3807 map1 { 3808 trip = <&cpu2_alert1>; 3809 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3810 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3811 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3812 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3813 }; 3814 }; 3815 }; 3816 3817 cpu3-thermal { 3818 polling-delay-passive = <250>; 3819 polling-delay = <1000>; 3820 3821 thermal-sensors = <&tsens0 4>; 3822 3823 trips { 3824 cpu3_alert0: trip-point0 { 3825 temperature = <90000>; 3826 hysteresis = <2000>; 3827 type = "passive"; 3828 }; 3829 3830 cpu3_alert1: trip-point1 { 3831 temperature = <95000>; 3832 hysteresis = <2000>; 3833 type = "passive"; 3834 }; 3835 3836 cpu3_crit: cpu_crit { 3837 temperature = <110000>; 3838 hysteresis = <1000>; 3839 type = "critical"; 3840 }; 3841 }; 3842 3843 cooling-maps { 3844 map0 { 3845 trip = <&cpu3_alert0>; 3846 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3847 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3848 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3849 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3850 }; 3851 map1 { 3852 trip = <&cpu3_alert1>; 3853 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3854 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3855 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3856 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3857 }; 3858 }; 3859 }; 3860 3861 cpu4-top-thermal { 3862 polling-delay-passive = <250>; 3863 polling-delay = <1000>; 3864 3865 thermal-sensors = <&tsens0 7>; 3866 3867 trips { 3868 cpu4_top_alert0: trip-point0 { 3869 temperature = <90000>; 3870 hysteresis = <2000>; 3871 type = "passive"; 3872 }; 3873 3874 cpu4_top_alert1: trip-point1 { 3875 temperature = <95000>; 3876 hysteresis = <2000>; 3877 type = "passive"; 3878 }; 3879 3880 cpu4_top_crit: cpu_crit { 3881 temperature = <110000>; 3882 hysteresis = <1000>; 3883 type = "critical"; 3884 }; 3885 }; 3886 3887 cooling-maps { 3888 map0 { 3889 trip = <&cpu4_top_alert0>; 3890 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3891 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3892 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3893 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3894 }; 3895 map1 { 3896 trip = <&cpu4_top_alert1>; 3897 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3898 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3899 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3900 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3901 }; 3902 }; 3903 }; 3904 3905 cpu5-top-thermal { 3906 polling-delay-passive = <250>; 3907 polling-delay = <1000>; 3908 3909 thermal-sensors = <&tsens0 8>; 3910 3911 trips { 3912 cpu5_top_alert0: trip-point0 { 3913 temperature = <90000>; 3914 hysteresis = <2000>; 3915 type = "passive"; 3916 }; 3917 3918 cpu5_top_alert1: trip-point1 { 3919 temperature = <95000>; 3920 hysteresis = <2000>; 3921 type = "passive"; 3922 }; 3923 3924 cpu5_top_crit: cpu_crit { 3925 temperature = <110000>; 3926 hysteresis = <1000>; 3927 type = "critical"; 3928 }; 3929 }; 3930 3931 cooling-maps { 3932 map0 { 3933 trip = <&cpu5_top_alert0>; 3934 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3935 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3936 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3937 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3938 }; 3939 map1 { 3940 trip = <&cpu5_top_alert1>; 3941 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3942 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3943 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3944 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3945 }; 3946 }; 3947 }; 3948 3949 cpu6-top-thermal { 3950 polling-delay-passive = <250>; 3951 polling-delay = <1000>; 3952 3953 thermal-sensors = <&tsens0 9>; 3954 3955 trips { 3956 cpu6_top_alert0: trip-point0 { 3957 temperature = <90000>; 3958 hysteresis = <2000>; 3959 type = "passive"; 3960 }; 3961 3962 cpu6_top_alert1: trip-point1 { 3963 temperature = <95000>; 3964 hysteresis = <2000>; 3965 type = "passive"; 3966 }; 3967 3968 cpu6_top_crit: cpu_crit { 3969 temperature = <110000>; 3970 hysteresis = <1000>; 3971 type = "critical"; 3972 }; 3973 }; 3974 3975 cooling-maps { 3976 map0 { 3977 trip = <&cpu6_top_alert0>; 3978 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3979 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3980 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3981 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3982 }; 3983 map1 { 3984 trip = <&cpu6_top_alert1>; 3985 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3986 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3987 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3988 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3989 }; 3990 }; 3991 }; 3992 3993 cpu7-top-thermal { 3994 polling-delay-passive = <250>; 3995 polling-delay = <1000>; 3996 3997 thermal-sensors = <&tsens0 10>; 3998 3999 trips { 4000 cpu7_top_alert0: trip-point0 { 4001 temperature = <90000>; 4002 hysteresis = <2000>; 4003 type = "passive"; 4004 }; 4005 4006 cpu7_top_alert1: trip-point1 { 4007 temperature = <95000>; 4008 hysteresis = <2000>; 4009 type = "passive"; 4010 }; 4011 4012 cpu7_top_crit: cpu_crit { 4013 temperature = <110000>; 4014 hysteresis = <1000>; 4015 type = "critical"; 4016 }; 4017 }; 4018 4019 cooling-maps { 4020 map0 { 4021 trip = <&cpu7_top_alert0>; 4022 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4023 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4024 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4025 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4026 }; 4027 map1 { 4028 trip = <&cpu7_top_alert1>; 4029 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4030 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4031 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4032 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4033 }; 4034 }; 4035 }; 4036 4037 cpu4-bottom-thermal { 4038 polling-delay-passive = <250>; 4039 polling-delay = <1000>; 4040 4041 thermal-sensors = <&tsens0 11>; 4042 4043 trips { 4044 cpu4_bottom_alert0: trip-point0 { 4045 temperature = <90000>; 4046 hysteresis = <2000>; 4047 type = "passive"; 4048 }; 4049 4050 cpu4_bottom_alert1: trip-point1 { 4051 temperature = <95000>; 4052 hysteresis = <2000>; 4053 type = "passive"; 4054 }; 4055 4056 cpu4_bottom_crit: cpu_crit { 4057 temperature = <110000>; 4058 hysteresis = <1000>; 4059 type = "critical"; 4060 }; 4061 }; 4062 4063 cooling-maps { 4064 map0 { 4065 trip = <&cpu4_bottom_alert0>; 4066 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4067 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4068 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4069 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4070 }; 4071 map1 { 4072 trip = <&cpu4_bottom_alert1>; 4073 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4074 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4075 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4076 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4077 }; 4078 }; 4079 }; 4080 4081 cpu5-bottom-thermal { 4082 polling-delay-passive = <250>; 4083 polling-delay = <1000>; 4084 4085 thermal-sensors = <&tsens0 12>; 4086 4087 trips { 4088 cpu5_bottom_alert0: trip-point0 { 4089 temperature = <90000>; 4090 hysteresis = <2000>; 4091 type = "passive"; 4092 }; 4093 4094 cpu5_bottom_alert1: trip-point1 { 4095 temperature = <95000>; 4096 hysteresis = <2000>; 4097 type = "passive"; 4098 }; 4099 4100 cpu5_bottom_crit: cpu_crit { 4101 temperature = <110000>; 4102 hysteresis = <1000>; 4103 type = "critical"; 4104 }; 4105 }; 4106 4107 cooling-maps { 4108 map0 { 4109 trip = <&cpu5_bottom_alert0>; 4110 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4111 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4112 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4113 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4114 }; 4115 map1 { 4116 trip = <&cpu5_bottom_alert1>; 4117 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4118 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4119 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4120 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4121 }; 4122 }; 4123 }; 4124 4125 cpu6-bottom-thermal { 4126 polling-delay-passive = <250>; 4127 polling-delay = <1000>; 4128 4129 thermal-sensors = <&tsens0 13>; 4130 4131 trips { 4132 cpu6_bottom_alert0: trip-point0 { 4133 temperature = <90000>; 4134 hysteresis = <2000>; 4135 type = "passive"; 4136 }; 4137 4138 cpu6_bottom_alert1: trip-point1 { 4139 temperature = <95000>; 4140 hysteresis = <2000>; 4141 type = "passive"; 4142 }; 4143 4144 cpu6_bottom_crit: cpu_crit { 4145 temperature = <110000>; 4146 hysteresis = <1000>; 4147 type = "critical"; 4148 }; 4149 }; 4150 4151 cooling-maps { 4152 map0 { 4153 trip = <&cpu6_bottom_alert0>; 4154 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4155 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4156 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4157 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4158 }; 4159 map1 { 4160 trip = <&cpu6_bottom_alert1>; 4161 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4162 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4163 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4164 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4165 }; 4166 }; 4167 }; 4168 4169 cpu7-bottom-thermal { 4170 polling-delay-passive = <250>; 4171 polling-delay = <1000>; 4172 4173 thermal-sensors = <&tsens0 14>; 4174 4175 trips { 4176 cpu7_bottom_alert0: trip-point0 { 4177 temperature = <90000>; 4178 hysteresis = <2000>; 4179 type = "passive"; 4180 }; 4181 4182 cpu7_bottom_alert1: trip-point1 { 4183 temperature = <95000>; 4184 hysteresis = <2000>; 4185 type = "passive"; 4186 }; 4187 4188 cpu7_bottom_crit: cpu_crit { 4189 temperature = <110000>; 4190 hysteresis = <1000>; 4191 type = "critical"; 4192 }; 4193 }; 4194 4195 cooling-maps { 4196 map0 { 4197 trip = <&cpu7_bottom_alert0>; 4198 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4199 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4200 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4201 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4202 }; 4203 map1 { 4204 trip = <&cpu7_bottom_alert1>; 4205 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4206 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4207 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4208 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4209 }; 4210 }; 4211 }; 4212 4213 aoss0-thermal { 4214 polling-delay-passive = <250>; 4215 polling-delay = <1000>; 4216 4217 thermal-sensors = <&tsens0 0>; 4218 4219 trips { 4220 aoss0_alert0: trip-point0 { 4221 temperature = <90000>; 4222 hysteresis = <2000>; 4223 type = "hot"; 4224 }; 4225 }; 4226 }; 4227 4228 cluster0-thermal { 4229 polling-delay-passive = <250>; 4230 polling-delay = <1000>; 4231 4232 thermal-sensors = <&tsens0 5>; 4233 4234 trips { 4235 cluster0_alert0: trip-point0 { 4236 temperature = <90000>; 4237 hysteresis = <2000>; 4238 type = "hot"; 4239 }; 4240 cluster0_crit: cluster0_crit { 4241 temperature = <110000>; 4242 hysteresis = <2000>; 4243 type = "critical"; 4244 }; 4245 }; 4246 }; 4247 4248 cluster1-thermal { 4249 polling-delay-passive = <250>; 4250 polling-delay = <1000>; 4251 4252 thermal-sensors = <&tsens0 6>; 4253 4254 trips { 4255 cluster1_alert0: trip-point0 { 4256 temperature = <90000>; 4257 hysteresis = <2000>; 4258 type = "hot"; 4259 }; 4260 cluster1_crit: cluster1_crit { 4261 temperature = <110000>; 4262 hysteresis = <2000>; 4263 type = "critical"; 4264 }; 4265 }; 4266 }; 4267 4268 gpu-thermal-top { 4269 polling-delay-passive = <250>; 4270 polling-delay = <1000>; 4271 4272 thermal-sensors = <&tsens0 15>; 4273 4274 trips { 4275 gpu1_alert0: trip-point0 { 4276 temperature = <90000>; 4277 hysteresis = <2000>; 4278 type = "hot"; 4279 }; 4280 }; 4281 }; 4282 4283 aoss1-thermal { 4284 polling-delay-passive = <250>; 4285 polling-delay = <1000>; 4286 4287 thermal-sensors = <&tsens1 0>; 4288 4289 trips { 4290 aoss1_alert0: trip-point0 { 4291 temperature = <90000>; 4292 hysteresis = <2000>; 4293 type = "hot"; 4294 }; 4295 }; 4296 }; 4297 4298 wlan-thermal { 4299 polling-delay-passive = <250>; 4300 polling-delay = <1000>; 4301 4302 thermal-sensors = <&tsens1 1>; 4303 4304 trips { 4305 wlan_alert0: trip-point0 { 4306 temperature = <90000>; 4307 hysteresis = <2000>; 4308 type = "hot"; 4309 }; 4310 }; 4311 }; 4312 4313 video-thermal { 4314 polling-delay-passive = <250>; 4315 polling-delay = <1000>; 4316 4317 thermal-sensors = <&tsens1 2>; 4318 4319 trips { 4320 video_alert0: trip-point0 { 4321 temperature = <90000>; 4322 hysteresis = <2000>; 4323 type = "hot"; 4324 }; 4325 }; 4326 }; 4327 4328 mem-thermal { 4329 polling-delay-passive = <250>; 4330 polling-delay = <1000>; 4331 4332 thermal-sensors = <&tsens1 3>; 4333 4334 trips { 4335 mem_alert0: trip-point0 { 4336 temperature = <90000>; 4337 hysteresis = <2000>; 4338 type = "hot"; 4339 }; 4340 }; 4341 }; 4342 4343 q6-hvx-thermal { 4344 polling-delay-passive = <250>; 4345 polling-delay = <1000>; 4346 4347 thermal-sensors = <&tsens1 4>; 4348 4349 trips { 4350 q6_hvx_alert0: trip-point0 { 4351 temperature = <90000>; 4352 hysteresis = <2000>; 4353 type = "hot"; 4354 }; 4355 }; 4356 }; 4357 4358 camera-thermal { 4359 polling-delay-passive = <250>; 4360 polling-delay = <1000>; 4361 4362 thermal-sensors = <&tsens1 5>; 4363 4364 trips { 4365 camera_alert0: trip-point0 { 4366 temperature = <90000>; 4367 hysteresis = <2000>; 4368 type = "hot"; 4369 }; 4370 }; 4371 }; 4372 4373 compute-thermal { 4374 polling-delay-passive = <250>; 4375 polling-delay = <1000>; 4376 4377 thermal-sensors = <&tsens1 6>; 4378 4379 trips { 4380 compute_alert0: trip-point0 { 4381 temperature = <90000>; 4382 hysteresis = <2000>; 4383 type = "hot"; 4384 }; 4385 }; 4386 }; 4387 4388 modem-thermal { 4389 polling-delay-passive = <250>; 4390 polling-delay = <1000>; 4391 4392 thermal-sensors = <&tsens1 7>; 4393 4394 trips { 4395 modem_alert0: trip-point0 { 4396 temperature = <90000>; 4397 hysteresis = <2000>; 4398 type = "hot"; 4399 }; 4400 }; 4401 }; 4402 4403 npu-thermal { 4404 polling-delay-passive = <250>; 4405 polling-delay = <1000>; 4406 4407 thermal-sensors = <&tsens1 8>; 4408 4409 trips { 4410 npu_alert0: trip-point0 { 4411 temperature = <90000>; 4412 hysteresis = <2000>; 4413 type = "hot"; 4414 }; 4415 }; 4416 }; 4417 4418 modem-vec-thermal { 4419 polling-delay-passive = <250>; 4420 polling-delay = <1000>; 4421 4422 thermal-sensors = <&tsens1 9>; 4423 4424 trips { 4425 modem_vec_alert0: trip-point0 { 4426 temperature = <90000>; 4427 hysteresis = <2000>; 4428 type = "hot"; 4429 }; 4430 }; 4431 }; 4432 4433 modem-scl-thermal { 4434 polling-delay-passive = <250>; 4435 polling-delay = <1000>; 4436 4437 thermal-sensors = <&tsens1 10>; 4438 4439 trips { 4440 modem_scl_alert0: trip-point0 { 4441 temperature = <90000>; 4442 hysteresis = <2000>; 4443 type = "hot"; 4444 }; 4445 }; 4446 }; 4447 4448 gpu-thermal-bottom { 4449 polling-delay-passive = <250>; 4450 polling-delay = <1000>; 4451 4452 thermal-sensors = <&tsens1 11>; 4453 4454 trips { 4455 gpu2_alert0: trip-point0 { 4456 temperature = <90000>; 4457 hysteresis = <2000>; 4458 type = "hot"; 4459 }; 4460 }; 4461 }; 4462 }; 4463}; 4464