1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/dma/qcom-gpi.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,dispcc-sm8150.h> 13#include <dt-bindings/clock/qcom,gcc-sm8150.h> 14#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sm8150.h> 17#include <dt-bindings/thermal/thermal.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 chosen { }; 26 27 clocks { 28 xo_board: xo-board { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <38400000>; 32 clock-output-names = "xo_board"; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32764>; 39 clock-output-names = "sleep_clk"; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 CPU0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "qcom,kryo485"; 50 reg = <0x0 0x0>; 51 clocks = <&cpufreq_hw 0>; 52 enable-method = "psci"; 53 capacity-dmips-mhz = <488>; 54 dynamic-power-coefficient = <232>; 55 next-level-cache = <&L2_0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 operating-points-v2 = <&cpu0_opp_table>; 58 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 59 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 60 power-domains = <&CPU_PD0>; 61 power-domain-names = "psci"; 62 #cooling-cells = <2>; 63 L2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 next-level-cache = <&L3_0>; 67 L3_0: l3-cache { 68 compatible = "cache"; 69 cache-level = <3>; 70 }; 71 }; 72 }; 73 74 CPU1: cpu@100 { 75 device_type = "cpu"; 76 compatible = "qcom,kryo485"; 77 reg = <0x0 0x100>; 78 clocks = <&cpufreq_hw 0>; 79 enable-method = "psci"; 80 capacity-dmips-mhz = <488>; 81 dynamic-power-coefficient = <232>; 82 next-level-cache = <&L2_100>; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 operating-points-v2 = <&cpu0_opp_table>; 85 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 86 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 87 power-domains = <&CPU_PD1>; 88 power-domain-names = "psci"; 89 #cooling-cells = <2>; 90 L2_100: l2-cache { 91 compatible = "cache"; 92 cache-level = <2>; 93 next-level-cache = <&L3_0>; 94 }; 95 }; 96 97 CPU2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "qcom,kryo485"; 100 reg = <0x0 0x200>; 101 clocks = <&cpufreq_hw 0>; 102 enable-method = "psci"; 103 capacity-dmips-mhz = <488>; 104 dynamic-power-coefficient = <232>; 105 next-level-cache = <&L2_200>; 106 qcom,freq-domain = <&cpufreq_hw 0>; 107 operating-points-v2 = <&cpu0_opp_table>; 108 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 109 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 110 power-domains = <&CPU_PD2>; 111 power-domain-names = "psci"; 112 #cooling-cells = <2>; 113 L2_200: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 next-level-cache = <&L3_0>; 117 }; 118 }; 119 120 CPU3: cpu@300 { 121 device_type = "cpu"; 122 compatible = "qcom,kryo485"; 123 reg = <0x0 0x300>; 124 clocks = <&cpufreq_hw 0>; 125 enable-method = "psci"; 126 capacity-dmips-mhz = <488>; 127 dynamic-power-coefficient = <232>; 128 next-level-cache = <&L2_300>; 129 qcom,freq-domain = <&cpufreq_hw 0>; 130 operating-points-v2 = <&cpu0_opp_table>; 131 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 132 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 133 power-domains = <&CPU_PD3>; 134 power-domain-names = "psci"; 135 #cooling-cells = <2>; 136 L2_300: l2-cache { 137 compatible = "cache"; 138 cache-level = <2>; 139 next-level-cache = <&L3_0>; 140 }; 141 }; 142 143 CPU4: cpu@400 { 144 device_type = "cpu"; 145 compatible = "qcom,kryo485"; 146 reg = <0x0 0x400>; 147 clocks = <&cpufreq_hw 1>; 148 enable-method = "psci"; 149 capacity-dmips-mhz = <1024>; 150 dynamic-power-coefficient = <369>; 151 next-level-cache = <&L2_400>; 152 qcom,freq-domain = <&cpufreq_hw 1>; 153 operating-points-v2 = <&cpu4_opp_table>; 154 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 155 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 156 power-domains = <&CPU_PD4>; 157 power-domain-names = "psci"; 158 #cooling-cells = <2>; 159 L2_400: l2-cache { 160 compatible = "cache"; 161 cache-level = <2>; 162 next-level-cache = <&L3_0>; 163 }; 164 }; 165 166 CPU5: cpu@500 { 167 device_type = "cpu"; 168 compatible = "qcom,kryo485"; 169 reg = <0x0 0x500>; 170 clocks = <&cpufreq_hw 1>; 171 enable-method = "psci"; 172 capacity-dmips-mhz = <1024>; 173 dynamic-power-coefficient = <369>; 174 next-level-cache = <&L2_500>; 175 qcom,freq-domain = <&cpufreq_hw 1>; 176 operating-points-v2 = <&cpu4_opp_table>; 177 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 178 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 179 power-domains = <&CPU_PD5>; 180 power-domain-names = "psci"; 181 #cooling-cells = <2>; 182 L2_500: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 next-level-cache = <&L3_0>; 186 }; 187 }; 188 189 CPU6: cpu@600 { 190 device_type = "cpu"; 191 compatible = "qcom,kryo485"; 192 reg = <0x0 0x600>; 193 clocks = <&cpufreq_hw 1>; 194 enable-method = "psci"; 195 capacity-dmips-mhz = <1024>; 196 dynamic-power-coefficient = <369>; 197 next-level-cache = <&L2_600>; 198 qcom,freq-domain = <&cpufreq_hw 1>; 199 operating-points-v2 = <&cpu4_opp_table>; 200 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 201 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 202 power-domains = <&CPU_PD6>; 203 power-domain-names = "psci"; 204 #cooling-cells = <2>; 205 L2_600: l2-cache { 206 compatible = "cache"; 207 cache-level = <2>; 208 next-level-cache = <&L3_0>; 209 }; 210 }; 211 212 CPU7: cpu@700 { 213 device_type = "cpu"; 214 compatible = "qcom,kryo485"; 215 reg = <0x0 0x700>; 216 clocks = <&cpufreq_hw 2>; 217 enable-method = "psci"; 218 capacity-dmips-mhz = <1024>; 219 dynamic-power-coefficient = <421>; 220 next-level-cache = <&L2_700>; 221 qcom,freq-domain = <&cpufreq_hw 2>; 222 operating-points-v2 = <&cpu7_opp_table>; 223 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 224 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 225 power-domains = <&CPU_PD7>; 226 power-domain-names = "psci"; 227 #cooling-cells = <2>; 228 L2_700: l2-cache { 229 compatible = "cache"; 230 cache-level = <2>; 231 next-level-cache = <&L3_0>; 232 }; 233 }; 234 235 cpu-map { 236 cluster0 { 237 core0 { 238 cpu = <&CPU0>; 239 }; 240 241 core1 { 242 cpu = <&CPU1>; 243 }; 244 245 core2 { 246 cpu = <&CPU2>; 247 }; 248 249 core3 { 250 cpu = <&CPU3>; 251 }; 252 253 core4 { 254 cpu = <&CPU4>; 255 }; 256 257 core5 { 258 cpu = <&CPU5>; 259 }; 260 261 core6 { 262 cpu = <&CPU6>; 263 }; 264 265 core7 { 266 cpu = <&CPU7>; 267 }; 268 }; 269 }; 270 271 idle-states { 272 entry-method = "psci"; 273 274 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 275 compatible = "arm,idle-state"; 276 idle-state-name = "little-rail-power-collapse"; 277 arm,psci-suspend-param = <0x40000004>; 278 entry-latency-us = <355>; 279 exit-latency-us = <909>; 280 min-residency-us = <3934>; 281 local-timer-stop; 282 }; 283 284 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 285 compatible = "arm,idle-state"; 286 idle-state-name = "big-rail-power-collapse"; 287 arm,psci-suspend-param = <0x40000004>; 288 entry-latency-us = <241>; 289 exit-latency-us = <1461>; 290 min-residency-us = <4488>; 291 local-timer-stop; 292 }; 293 }; 294 295 domain-idle-states { 296 CLUSTER_SLEEP_0: cluster-sleep-0 { 297 compatible = "domain-idle-state"; 298 arm,psci-suspend-param = <0x4100c244>; 299 entry-latency-us = <3263>; 300 exit-latency-us = <6562>; 301 min-residency-us = <9987>; 302 }; 303 }; 304 }; 305 306 cpu0_opp_table: opp-table-cpu0 { 307 compatible = "operating-points-v2"; 308 opp-shared; 309 310 cpu0_opp1: opp-300000000 { 311 opp-hz = /bits/ 64 <300000000>; 312 opp-peak-kBps = <800000 9600000>; 313 }; 314 315 cpu0_opp2: opp-403200000 { 316 opp-hz = /bits/ 64 <403200000>; 317 opp-peak-kBps = <800000 9600000>; 318 }; 319 320 cpu0_opp3: opp-499200000 { 321 opp-hz = /bits/ 64 <499200000>; 322 opp-peak-kBps = <800000 12902400>; 323 }; 324 325 cpu0_opp4: opp-576000000 { 326 opp-hz = /bits/ 64 <576000000>; 327 opp-peak-kBps = <800000 12902400>; 328 }; 329 330 cpu0_opp5: opp-672000000 { 331 opp-hz = /bits/ 64 <672000000>; 332 opp-peak-kBps = <800000 15974400>; 333 }; 334 335 cpu0_opp6: opp-768000000 { 336 opp-hz = /bits/ 64 <768000000>; 337 opp-peak-kBps = <1804000 19660800>; 338 }; 339 340 cpu0_opp7: opp-844800000 { 341 opp-hz = /bits/ 64 <844800000>; 342 opp-peak-kBps = <1804000 19660800>; 343 }; 344 345 cpu0_opp8: opp-940800000 { 346 opp-hz = /bits/ 64 <940800000>; 347 opp-peak-kBps = <1804000 22732800>; 348 }; 349 350 cpu0_opp9: opp-1036800000 { 351 opp-hz = /bits/ 64 <1036800000>; 352 opp-peak-kBps = <1804000 22732800>; 353 }; 354 355 cpu0_opp10: opp-1113600000 { 356 opp-hz = /bits/ 64 <1113600000>; 357 opp-peak-kBps = <2188000 25804800>; 358 }; 359 360 cpu0_opp11: opp-1209600000 { 361 opp-hz = /bits/ 64 <1209600000>; 362 opp-peak-kBps = <2188000 31948800>; 363 }; 364 365 cpu0_opp12: opp-1305600000 { 366 opp-hz = /bits/ 64 <1305600000>; 367 opp-peak-kBps = <3072000 31948800>; 368 }; 369 370 cpu0_opp13: opp-1382400000 { 371 opp-hz = /bits/ 64 <1382400000>; 372 opp-peak-kBps = <3072000 31948800>; 373 }; 374 375 cpu0_opp14: opp-1478400000 { 376 opp-hz = /bits/ 64 <1478400000>; 377 opp-peak-kBps = <3072000 31948800>; 378 }; 379 380 cpu0_opp15: opp-1555200000 { 381 opp-hz = /bits/ 64 <1555200000>; 382 opp-peak-kBps = <3072000 40550400>; 383 }; 384 385 cpu0_opp16: opp-1632000000 { 386 opp-hz = /bits/ 64 <1632000000>; 387 opp-peak-kBps = <3072000 40550400>; 388 }; 389 390 cpu0_opp17: opp-1708800000 { 391 opp-hz = /bits/ 64 <1708800000>; 392 opp-peak-kBps = <3072000 43008000>; 393 }; 394 395 cpu0_opp18: opp-1785600000 { 396 opp-hz = /bits/ 64 <1785600000>; 397 opp-peak-kBps = <3072000 43008000>; 398 }; 399 }; 400 401 cpu4_opp_table: opp-table-cpu4 { 402 compatible = "operating-points-v2"; 403 opp-shared; 404 405 cpu4_opp1: opp-710400000 { 406 opp-hz = /bits/ 64 <710400000>; 407 opp-peak-kBps = <1804000 15974400>; 408 }; 409 410 cpu4_opp2: opp-825600000 { 411 opp-hz = /bits/ 64 <825600000>; 412 opp-peak-kBps = <2188000 19660800>; 413 }; 414 415 cpu4_opp3: opp-940800000 { 416 opp-hz = /bits/ 64 <940800000>; 417 opp-peak-kBps = <2188000 22732800>; 418 }; 419 420 cpu4_opp4: opp-1056000000 { 421 opp-hz = /bits/ 64 <1056000000>; 422 opp-peak-kBps = <3072000 25804800>; 423 }; 424 425 cpu4_opp5: opp-1171200000 { 426 opp-hz = /bits/ 64 <1171200000>; 427 opp-peak-kBps = <3072000 31948800>; 428 }; 429 430 cpu4_opp6: opp-1286400000 { 431 opp-hz = /bits/ 64 <1286400000>; 432 opp-peak-kBps = <4068000 31948800>; 433 }; 434 435 cpu4_opp7: opp-1401600000 { 436 opp-hz = /bits/ 64 <1401600000>; 437 opp-peak-kBps = <4068000 31948800>; 438 }; 439 440 cpu4_opp8: opp-1497600000 { 441 opp-hz = /bits/ 64 <1497600000>; 442 opp-peak-kBps = <4068000 40550400>; 443 }; 444 445 cpu4_opp9: opp-1612800000 { 446 opp-hz = /bits/ 64 <1612800000>; 447 opp-peak-kBps = <4068000 40550400>; 448 }; 449 450 cpu4_opp10: opp-1708800000 { 451 opp-hz = /bits/ 64 <1708800000>; 452 opp-peak-kBps = <4068000 43008000>; 453 }; 454 455 cpu4_opp11: opp-1804800000 { 456 opp-hz = /bits/ 64 <1804800000>; 457 opp-peak-kBps = <6220000 43008000>; 458 }; 459 460 cpu4_opp12: opp-1920000000 { 461 opp-hz = /bits/ 64 <1920000000>; 462 opp-peak-kBps = <6220000 49152000>; 463 }; 464 465 cpu4_opp13: opp-2016000000 { 466 opp-hz = /bits/ 64 <2016000000>; 467 opp-peak-kBps = <7216000 49152000>; 468 }; 469 470 cpu4_opp14: opp-2131200000 { 471 opp-hz = /bits/ 64 <2131200000>; 472 opp-peak-kBps = <8368000 49152000>; 473 }; 474 475 cpu4_opp15: opp-2227200000 { 476 opp-hz = /bits/ 64 <2227200000>; 477 opp-peak-kBps = <8368000 51609600>; 478 }; 479 480 cpu4_opp16: opp-2323200000 { 481 opp-hz = /bits/ 64 <2323200000>; 482 opp-peak-kBps = <8368000 51609600>; 483 }; 484 485 cpu4_opp17: opp-2419200000 { 486 opp-hz = /bits/ 64 <2419200000>; 487 opp-peak-kBps = <8368000 51609600>; 488 }; 489 }; 490 491 cpu7_opp_table: opp-table-cpu7 { 492 compatible = "operating-points-v2"; 493 opp-shared; 494 495 cpu7_opp1: opp-825600000 { 496 opp-hz = /bits/ 64 <825600000>; 497 opp-peak-kBps = <2188000 19660800>; 498 }; 499 500 cpu7_opp2: opp-940800000 { 501 opp-hz = /bits/ 64 <940800000>; 502 opp-peak-kBps = <2188000 22732800>; 503 }; 504 505 cpu7_opp3: opp-1056000000 { 506 opp-hz = /bits/ 64 <1056000000>; 507 opp-peak-kBps = <3072000 25804800>; 508 }; 509 510 cpu7_opp4: opp-1171200000 { 511 opp-hz = /bits/ 64 <1171200000>; 512 opp-peak-kBps = <3072000 31948800>; 513 }; 514 515 cpu7_opp5: opp-1286400000 { 516 opp-hz = /bits/ 64 <1286400000>; 517 opp-peak-kBps = <4068000 31948800>; 518 }; 519 520 cpu7_opp6: opp-1401600000 { 521 opp-hz = /bits/ 64 <1401600000>; 522 opp-peak-kBps = <4068000 31948800>; 523 }; 524 525 cpu7_opp7: opp-1497600000 { 526 opp-hz = /bits/ 64 <1497600000>; 527 opp-peak-kBps = <4068000 40550400>; 528 }; 529 530 cpu7_opp8: opp-1612800000 { 531 opp-hz = /bits/ 64 <1612800000>; 532 opp-peak-kBps = <4068000 40550400>; 533 }; 534 535 cpu7_opp9: opp-1708800000 { 536 opp-hz = /bits/ 64 <1708800000>; 537 opp-peak-kBps = <4068000 43008000>; 538 }; 539 540 cpu7_opp10: opp-1804800000 { 541 opp-hz = /bits/ 64 <1804800000>; 542 opp-peak-kBps = <6220000 43008000>; 543 }; 544 545 cpu7_opp11: opp-1920000000 { 546 opp-hz = /bits/ 64 <1920000000>; 547 opp-peak-kBps = <6220000 49152000>; 548 }; 549 550 cpu7_opp12: opp-2016000000 { 551 opp-hz = /bits/ 64 <2016000000>; 552 opp-peak-kBps = <7216000 49152000>; 553 }; 554 555 cpu7_opp13: opp-2131200000 { 556 opp-hz = /bits/ 64 <2131200000>; 557 opp-peak-kBps = <8368000 49152000>; 558 }; 559 560 cpu7_opp14: opp-2227200000 { 561 opp-hz = /bits/ 64 <2227200000>; 562 opp-peak-kBps = <8368000 51609600>; 563 }; 564 565 cpu7_opp15: opp-2323200000 { 566 opp-hz = /bits/ 64 <2323200000>; 567 opp-peak-kBps = <8368000 51609600>; 568 }; 569 570 cpu7_opp16: opp-2419200000 { 571 opp-hz = /bits/ 64 <2419200000>; 572 opp-peak-kBps = <8368000 51609600>; 573 }; 574 575 cpu7_opp17: opp-2534400000 { 576 opp-hz = /bits/ 64 <2534400000>; 577 opp-peak-kBps = <8368000 51609600>; 578 }; 579 580 cpu7_opp18: opp-2649600000 { 581 opp-hz = /bits/ 64 <2649600000>; 582 opp-peak-kBps = <8368000 51609600>; 583 }; 584 585 cpu7_opp19: opp-2745600000 { 586 opp-hz = /bits/ 64 <2745600000>; 587 opp-peak-kBps = <8368000 51609600>; 588 }; 589 590 cpu7_opp20: opp-2841600000 { 591 opp-hz = /bits/ 64 <2841600000>; 592 opp-peak-kBps = <8368000 51609600>; 593 }; 594 }; 595 596 firmware { 597 scm: scm { 598 compatible = "qcom,scm-sm8150", "qcom,scm"; 599 #reset-cells = <1>; 600 }; 601 }; 602 603 memory@80000000 { 604 device_type = "memory"; 605 /* We expect the bootloader to fill in the size */ 606 reg = <0x0 0x80000000 0x0 0x0>; 607 }; 608 609 pmu { 610 compatible = "arm,armv8-pmuv3"; 611 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 612 }; 613 614 psci { 615 compatible = "arm,psci-1.0"; 616 method = "smc"; 617 618 CPU_PD0: power-domain-cpu0 { 619 #power-domain-cells = <0>; 620 power-domains = <&CLUSTER_PD>; 621 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 622 }; 623 624 CPU_PD1: power-domain-cpu1 { 625 #power-domain-cells = <0>; 626 power-domains = <&CLUSTER_PD>; 627 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 628 }; 629 630 CPU_PD2: power-domain-cpu2 { 631 #power-domain-cells = <0>; 632 power-domains = <&CLUSTER_PD>; 633 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 634 }; 635 636 CPU_PD3: power-domain-cpu3 { 637 #power-domain-cells = <0>; 638 power-domains = <&CLUSTER_PD>; 639 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 640 }; 641 642 CPU_PD4: power-domain-cpu4 { 643 #power-domain-cells = <0>; 644 power-domains = <&CLUSTER_PD>; 645 domain-idle-states = <&BIG_CPU_SLEEP_0>; 646 }; 647 648 CPU_PD5: power-domain-cpu5 { 649 #power-domain-cells = <0>; 650 power-domains = <&CLUSTER_PD>; 651 domain-idle-states = <&BIG_CPU_SLEEP_0>; 652 }; 653 654 CPU_PD6: power-domain-cpu6 { 655 #power-domain-cells = <0>; 656 power-domains = <&CLUSTER_PD>; 657 domain-idle-states = <&BIG_CPU_SLEEP_0>; 658 }; 659 660 CPU_PD7: power-domain-cpu7 { 661 #power-domain-cells = <0>; 662 power-domains = <&CLUSTER_PD>; 663 domain-idle-states = <&BIG_CPU_SLEEP_0>; 664 }; 665 666 CLUSTER_PD: power-domain-cpu-cluster0 { 667 #power-domain-cells = <0>; 668 domain-idle-states = <&CLUSTER_SLEEP_0>; 669 }; 670 }; 671 672 reserved-memory { 673 #address-cells = <2>; 674 #size-cells = <2>; 675 ranges; 676 677 hyp_mem: memory@85700000 { 678 reg = <0x0 0x85700000 0x0 0x600000>; 679 no-map; 680 }; 681 682 xbl_mem: memory@85d00000 { 683 reg = <0x0 0x85d00000 0x0 0x140000>; 684 no-map; 685 }; 686 687 aop_mem: memory@85f00000 { 688 reg = <0x0 0x85f00000 0x0 0x20000>; 689 no-map; 690 }; 691 692 aop_cmd_db: memory@85f20000 { 693 compatible = "qcom,cmd-db"; 694 reg = <0x0 0x85f20000 0x0 0x20000>; 695 no-map; 696 }; 697 698 smem_mem: memory@86000000 { 699 reg = <0x0 0x86000000 0x0 0x200000>; 700 no-map; 701 }; 702 703 tz_mem: memory@86200000 { 704 reg = <0x0 0x86200000 0x0 0x3900000>; 705 no-map; 706 }; 707 708 rmtfs_mem: memory@89b00000 { 709 compatible = "qcom,rmtfs-mem"; 710 reg = <0x0 0x89b00000 0x0 0x200000>; 711 no-map; 712 713 qcom,client-id = <1>; 714 qcom,vmid = <15>; 715 }; 716 717 camera_mem: memory@8b700000 { 718 reg = <0x0 0x8b700000 0x0 0x500000>; 719 no-map; 720 }; 721 722 wlan_mem: memory@8bc00000 { 723 reg = <0x0 0x8bc00000 0x0 0x180000>; 724 no-map; 725 }; 726 727 npu_mem: memory@8bd80000 { 728 reg = <0x0 0x8bd80000 0x0 0x80000>; 729 no-map; 730 }; 731 732 adsp_mem: memory@8be00000 { 733 reg = <0x0 0x8be00000 0x0 0x1a00000>; 734 no-map; 735 }; 736 737 mpss_mem: memory@8d800000 { 738 reg = <0x0 0x8d800000 0x0 0x9600000>; 739 no-map; 740 }; 741 742 venus_mem: memory@96e00000 { 743 reg = <0x0 0x96e00000 0x0 0x500000>; 744 no-map; 745 }; 746 747 slpi_mem: memory@97300000 { 748 reg = <0x0 0x97300000 0x0 0x1400000>; 749 no-map; 750 }; 751 752 ipa_fw_mem: memory@98700000 { 753 reg = <0x0 0x98700000 0x0 0x10000>; 754 no-map; 755 }; 756 757 ipa_gsi_mem: memory@98710000 { 758 reg = <0x0 0x98710000 0x0 0x5000>; 759 no-map; 760 }; 761 762 gpu_mem: memory@98715000 { 763 reg = <0x0 0x98715000 0x0 0x2000>; 764 no-map; 765 }; 766 767 spss_mem: memory@98800000 { 768 reg = <0x0 0x98800000 0x0 0x100000>; 769 no-map; 770 }; 771 772 cdsp_mem: memory@98900000 { 773 reg = <0x0 0x98900000 0x0 0x1400000>; 774 no-map; 775 }; 776 777 qseecom_mem: memory@9e400000 { 778 reg = <0x0 0x9e400000 0x0 0x1400000>; 779 no-map; 780 }; 781 }; 782 783 smem { 784 compatible = "qcom,smem"; 785 memory-region = <&smem_mem>; 786 hwlocks = <&tcsr_mutex 3>; 787 }; 788 789 smp2p-cdsp { 790 compatible = "qcom,smp2p"; 791 qcom,smem = <94>, <432>; 792 793 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 794 795 mboxes = <&apss_shared 6>; 796 797 qcom,local-pid = <0>; 798 qcom,remote-pid = <5>; 799 800 cdsp_smp2p_out: master-kernel { 801 qcom,entry-name = "master-kernel"; 802 #qcom,smem-state-cells = <1>; 803 }; 804 805 cdsp_smp2p_in: slave-kernel { 806 qcom,entry-name = "slave-kernel"; 807 808 interrupt-controller; 809 #interrupt-cells = <2>; 810 }; 811 }; 812 813 smp2p-lpass { 814 compatible = "qcom,smp2p"; 815 qcom,smem = <443>, <429>; 816 817 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 818 819 mboxes = <&apss_shared 10>; 820 821 qcom,local-pid = <0>; 822 qcom,remote-pid = <2>; 823 824 adsp_smp2p_out: master-kernel { 825 qcom,entry-name = "master-kernel"; 826 #qcom,smem-state-cells = <1>; 827 }; 828 829 adsp_smp2p_in: slave-kernel { 830 qcom,entry-name = "slave-kernel"; 831 832 interrupt-controller; 833 #interrupt-cells = <2>; 834 }; 835 }; 836 837 smp2p-mpss { 838 compatible = "qcom,smp2p"; 839 qcom,smem = <435>, <428>; 840 841 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 842 843 mboxes = <&apss_shared 14>; 844 845 qcom,local-pid = <0>; 846 qcom,remote-pid = <1>; 847 848 modem_smp2p_out: master-kernel { 849 qcom,entry-name = "master-kernel"; 850 #qcom,smem-state-cells = <1>; 851 }; 852 853 modem_smp2p_in: slave-kernel { 854 qcom,entry-name = "slave-kernel"; 855 856 interrupt-controller; 857 #interrupt-cells = <2>; 858 }; 859 }; 860 861 smp2p-slpi { 862 compatible = "qcom,smp2p"; 863 qcom,smem = <481>, <430>; 864 865 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 866 867 mboxes = <&apss_shared 26>; 868 869 qcom,local-pid = <0>; 870 qcom,remote-pid = <3>; 871 872 slpi_smp2p_out: master-kernel { 873 qcom,entry-name = "master-kernel"; 874 #qcom,smem-state-cells = <1>; 875 }; 876 877 slpi_smp2p_in: slave-kernel { 878 qcom,entry-name = "slave-kernel"; 879 880 interrupt-controller; 881 #interrupt-cells = <2>; 882 }; 883 }; 884 885 soc: soc@0 { 886 #address-cells = <2>; 887 #size-cells = <2>; 888 ranges = <0 0 0 0 0x10 0>; 889 dma-ranges = <0 0 0 0 0x10 0>; 890 compatible = "simple-bus"; 891 892 gcc: clock-controller@100000 { 893 compatible = "qcom,gcc-sm8150"; 894 reg = <0x0 0x00100000 0x0 0x1f0000>; 895 #clock-cells = <1>; 896 #reset-cells = <1>; 897 #power-domain-cells = <1>; 898 clock-names = "bi_tcxo", 899 "sleep_clk"; 900 clocks = <&rpmhcc RPMH_CXO_CLK>, 901 <&sleep_clk>; 902 }; 903 904 gpi_dma0: dma-controller@800000 { 905 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 906 reg = <0 0x00800000 0 0x60000>; 907 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 920 dma-channels = <13>; 921 dma-channel-mask = <0xfa>; 922 iommus = <&apps_smmu 0x00d6 0x0>; 923 #dma-cells = <3>; 924 status = "disabled"; 925 }; 926 927 ethernet: ethernet@20000 { 928 compatible = "qcom,sm8150-ethqos"; 929 reg = <0x0 0x00020000 0x0 0x10000>, 930 <0x0 0x00036000 0x0 0x100>; 931 reg-names = "stmmaceth", "rgmii"; 932 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 933 clocks = <&gcc GCC_EMAC_AXI_CLK>, 934 <&gcc GCC_EMAC_SLV_AHB_CLK>, 935 <&gcc GCC_EMAC_PTP_CLK>, 936 <&gcc GCC_EMAC_RGMII_CLK>; 937 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 939 interrupt-names = "macirq", "eth_lpi"; 940 941 power-domains = <&gcc EMAC_GDSC>; 942 resets = <&gcc GCC_EMAC_BCR>; 943 944 iommus = <&apps_smmu 0x3c0 0x0>; 945 946 snps,tso; 947 rx-fifo-depth = <4096>; 948 tx-fifo-depth = <4096>; 949 950 status = "disabled"; 951 }; 952 953 qfprom: efuse@784000 { 954 compatible = "qcom,sm8150-qfprom", "qcom,qfprom"; 955 reg = <0 0x00784000 0 0x8ff>; 956 #address-cells = <1>; 957 #size-cells = <1>; 958 959 gpu_speed_bin: gpu_speed_bin@133 { 960 reg = <0x133 0x1>; 961 bits = <5 3>; 962 }; 963 }; 964 965 qupv3_id_0: geniqup@8c0000 { 966 compatible = "qcom,geni-se-qup"; 967 reg = <0x0 0x008c0000 0x0 0x6000>; 968 clock-names = "m-ahb", "s-ahb"; 969 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 970 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 971 iommus = <&apps_smmu 0xc3 0x0>; 972 #address-cells = <2>; 973 #size-cells = <2>; 974 ranges; 975 status = "disabled"; 976 977 i2c0: i2c@880000 { 978 compatible = "qcom,geni-i2c"; 979 reg = <0 0x00880000 0 0x4000>; 980 clock-names = "se"; 981 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 982 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 983 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 984 dma-names = "tx", "rx"; 985 pinctrl-names = "default"; 986 pinctrl-0 = <&qup_i2c0_default>; 987 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 988 #address-cells = <1>; 989 #size-cells = <0>; 990 status = "disabled"; 991 }; 992 993 spi0: spi@880000 { 994 compatible = "qcom,geni-spi"; 995 reg = <0 0x00880000 0 0x4000>; 996 reg-names = "se"; 997 clock-names = "se"; 998 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 999 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1000 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1001 dma-names = "tx", "rx"; 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&qup_spi0_default>; 1004 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1005 spi-max-frequency = <50000000>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 status = "disabled"; 1009 }; 1010 1011 i2c1: i2c@884000 { 1012 compatible = "qcom,geni-i2c"; 1013 reg = <0 0x00884000 0 0x4000>; 1014 clock-names = "se"; 1015 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1016 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1017 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1018 dma-names = "tx", "rx"; 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&qup_i2c1_default>; 1021 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 status = "disabled"; 1025 }; 1026 1027 spi1: spi@884000 { 1028 compatible = "qcom,geni-spi"; 1029 reg = <0 0x00884000 0 0x4000>; 1030 reg-names = "se"; 1031 clock-names = "se"; 1032 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1033 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1034 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1035 dma-names = "tx", "rx"; 1036 pinctrl-names = "default"; 1037 pinctrl-0 = <&qup_spi1_default>; 1038 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1039 spi-max-frequency = <50000000>; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 status = "disabled"; 1043 }; 1044 1045 i2c2: i2c@888000 { 1046 compatible = "qcom,geni-i2c"; 1047 reg = <0 0x00888000 0 0x4000>; 1048 clock-names = "se"; 1049 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1050 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1051 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1052 dma-names = "tx", "rx"; 1053 pinctrl-names = "default"; 1054 pinctrl-0 = <&qup_i2c2_default>; 1055 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1056 #address-cells = <1>; 1057 #size-cells = <0>; 1058 status = "disabled"; 1059 }; 1060 1061 spi2: spi@888000 { 1062 compatible = "qcom,geni-spi"; 1063 reg = <0 0x00888000 0 0x4000>; 1064 reg-names = "se"; 1065 clock-names = "se"; 1066 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1067 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1068 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1069 dma-names = "tx", "rx"; 1070 pinctrl-names = "default"; 1071 pinctrl-0 = <&qup_spi2_default>; 1072 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1073 spi-max-frequency = <50000000>; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 status = "disabled"; 1077 }; 1078 1079 i2c3: i2c@88c000 { 1080 compatible = "qcom,geni-i2c"; 1081 reg = <0 0x0088c000 0 0x4000>; 1082 clock-names = "se"; 1083 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1084 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1085 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1086 dma-names = "tx", "rx"; 1087 pinctrl-names = "default"; 1088 pinctrl-0 = <&qup_i2c3_default>; 1089 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 status = "disabled"; 1093 }; 1094 1095 spi3: spi@88c000 { 1096 compatible = "qcom,geni-spi"; 1097 reg = <0 0x0088c000 0 0x4000>; 1098 reg-names = "se"; 1099 clock-names = "se"; 1100 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1101 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1102 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1103 dma-names = "tx", "rx"; 1104 pinctrl-names = "default"; 1105 pinctrl-0 = <&qup_spi3_default>; 1106 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1107 spi-max-frequency = <50000000>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 status = "disabled"; 1111 }; 1112 1113 i2c4: i2c@890000 { 1114 compatible = "qcom,geni-i2c"; 1115 reg = <0 0x00890000 0 0x4000>; 1116 clock-names = "se"; 1117 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1118 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1119 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1120 dma-names = "tx", "rx"; 1121 pinctrl-names = "default"; 1122 pinctrl-0 = <&qup_i2c4_default>; 1123 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 status = "disabled"; 1127 }; 1128 1129 spi4: spi@890000 { 1130 compatible = "qcom,geni-spi"; 1131 reg = <0 0x00890000 0 0x4000>; 1132 reg-names = "se"; 1133 clock-names = "se"; 1134 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1135 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1136 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1137 dma-names = "tx", "rx"; 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&qup_spi4_default>; 1140 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1141 spi-max-frequency = <50000000>; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 status = "disabled"; 1145 }; 1146 1147 i2c5: i2c@894000 { 1148 compatible = "qcom,geni-i2c"; 1149 reg = <0 0x00894000 0 0x4000>; 1150 clock-names = "se"; 1151 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1152 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1153 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1154 dma-names = "tx", "rx"; 1155 pinctrl-names = "default"; 1156 pinctrl-0 = <&qup_i2c5_default>; 1157 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 status = "disabled"; 1161 }; 1162 1163 spi5: spi@894000 { 1164 compatible = "qcom,geni-spi"; 1165 reg = <0 0x00894000 0 0x4000>; 1166 reg-names = "se"; 1167 clock-names = "se"; 1168 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1169 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1170 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1171 dma-names = "tx", "rx"; 1172 pinctrl-names = "default"; 1173 pinctrl-0 = <&qup_spi5_default>; 1174 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1175 spi-max-frequency = <50000000>; 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 status = "disabled"; 1179 }; 1180 1181 i2c6: i2c@898000 { 1182 compatible = "qcom,geni-i2c"; 1183 reg = <0 0x00898000 0 0x4000>; 1184 clock-names = "se"; 1185 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1186 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1187 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1188 dma-names = "tx", "rx"; 1189 pinctrl-names = "default"; 1190 pinctrl-0 = <&qup_i2c6_default>; 1191 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 status = "disabled"; 1195 }; 1196 1197 spi6: spi@898000 { 1198 compatible = "qcom,geni-spi"; 1199 reg = <0 0x00898000 0 0x4000>; 1200 reg-names = "se"; 1201 clock-names = "se"; 1202 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1203 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1204 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1205 dma-names = "tx", "rx"; 1206 pinctrl-names = "default"; 1207 pinctrl-0 = <&qup_spi6_default>; 1208 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1209 spi-max-frequency = <50000000>; 1210 #address-cells = <1>; 1211 #size-cells = <0>; 1212 status = "disabled"; 1213 }; 1214 1215 i2c7: i2c@89c000 { 1216 compatible = "qcom,geni-i2c"; 1217 reg = <0 0x0089c000 0 0x4000>; 1218 clock-names = "se"; 1219 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1220 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1221 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1222 dma-names = "tx", "rx"; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&qup_i2c7_default>; 1225 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 status = "disabled"; 1229 }; 1230 1231 spi7: spi@89c000 { 1232 compatible = "qcom,geni-spi"; 1233 reg = <0 0x0089c000 0 0x4000>; 1234 reg-names = "se"; 1235 clock-names = "se"; 1236 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1237 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1238 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1239 dma-names = "tx", "rx"; 1240 pinctrl-names = "default"; 1241 pinctrl-0 = <&qup_spi7_default>; 1242 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1243 spi-max-frequency = <50000000>; 1244 #address-cells = <1>; 1245 #size-cells = <0>; 1246 status = "disabled"; 1247 }; 1248 }; 1249 1250 gpi_dma1: dma-controller@a00000 { 1251 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1252 reg = <0 0x00a00000 0 0x60000>; 1253 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1259 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1261 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1262 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1266 dma-channels = <13>; 1267 dma-channel-mask = <0xfa>; 1268 iommus = <&apps_smmu 0x0616 0x0>; 1269 #dma-cells = <3>; 1270 status = "disabled"; 1271 }; 1272 1273 qupv3_id_1: geniqup@ac0000 { 1274 compatible = "qcom,geni-se-qup"; 1275 reg = <0x0 0x00ac0000 0x0 0x6000>; 1276 clock-names = "m-ahb", "s-ahb"; 1277 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1278 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1279 iommus = <&apps_smmu 0x603 0x0>; 1280 #address-cells = <2>; 1281 #size-cells = <2>; 1282 ranges; 1283 status = "disabled"; 1284 1285 i2c8: i2c@a80000 { 1286 compatible = "qcom,geni-i2c"; 1287 reg = <0 0x00a80000 0 0x4000>; 1288 clock-names = "se"; 1289 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1290 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1291 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1292 dma-names = "tx", "rx"; 1293 pinctrl-names = "default"; 1294 pinctrl-0 = <&qup_i2c8_default>; 1295 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 status = "disabled"; 1299 }; 1300 1301 spi8: spi@a80000 { 1302 compatible = "qcom,geni-spi"; 1303 reg = <0 0x00a80000 0 0x4000>; 1304 reg-names = "se"; 1305 clock-names = "se"; 1306 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1307 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1308 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1309 dma-names = "tx", "rx"; 1310 pinctrl-names = "default"; 1311 pinctrl-0 = <&qup_spi8_default>; 1312 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1313 spi-max-frequency = <50000000>; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 status = "disabled"; 1317 }; 1318 1319 i2c9: i2c@a84000 { 1320 compatible = "qcom,geni-i2c"; 1321 reg = <0 0x00a84000 0 0x4000>; 1322 clock-names = "se"; 1323 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1324 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1325 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1326 dma-names = "tx", "rx"; 1327 pinctrl-names = "default"; 1328 pinctrl-0 = <&qup_i2c9_default>; 1329 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 status = "disabled"; 1333 }; 1334 1335 spi9: spi@a84000 { 1336 compatible = "qcom,geni-spi"; 1337 reg = <0 0x00a84000 0 0x4000>; 1338 reg-names = "se"; 1339 clock-names = "se"; 1340 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1341 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1342 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1343 dma-names = "tx", "rx"; 1344 pinctrl-names = "default"; 1345 pinctrl-0 = <&qup_spi9_default>; 1346 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1347 spi-max-frequency = <50000000>; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 status = "disabled"; 1351 }; 1352 1353 uart9: serial@a84000 { 1354 compatible = "qcom,geni-uart"; 1355 reg = <0x0 0x00a84000 0x0 0x4000>; 1356 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1357 clock-names = "se"; 1358 pinctrl-0 = <&qup_uart9_default>; 1359 pinctrl-names = "default"; 1360 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1361 status = "disabled"; 1362 }; 1363 1364 i2c10: i2c@a88000 { 1365 compatible = "qcom,geni-i2c"; 1366 reg = <0 0x00a88000 0 0x4000>; 1367 clock-names = "se"; 1368 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1369 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1370 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1371 dma-names = "tx", "rx"; 1372 pinctrl-names = "default"; 1373 pinctrl-0 = <&qup_i2c10_default>; 1374 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1375 #address-cells = <1>; 1376 #size-cells = <0>; 1377 status = "disabled"; 1378 }; 1379 1380 spi10: spi@a88000 { 1381 compatible = "qcom,geni-spi"; 1382 reg = <0 0x00a88000 0 0x4000>; 1383 reg-names = "se"; 1384 clock-names = "se"; 1385 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1386 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1387 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1388 dma-names = "tx", "rx"; 1389 pinctrl-names = "default"; 1390 pinctrl-0 = <&qup_spi10_default>; 1391 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1392 spi-max-frequency = <50000000>; 1393 #address-cells = <1>; 1394 #size-cells = <0>; 1395 status = "disabled"; 1396 }; 1397 1398 i2c11: i2c@a8c000 { 1399 compatible = "qcom,geni-i2c"; 1400 reg = <0 0x00a8c000 0 0x4000>; 1401 clock-names = "se"; 1402 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1403 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1404 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1405 dma-names = "tx", "rx"; 1406 pinctrl-names = "default"; 1407 pinctrl-0 = <&qup_i2c11_default>; 1408 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 status = "disabled"; 1412 }; 1413 1414 spi11: spi@a8c000 { 1415 compatible = "qcom,geni-spi"; 1416 reg = <0 0x00a8c000 0 0x4000>; 1417 reg-names = "se"; 1418 clock-names = "se"; 1419 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1420 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1421 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1422 dma-names = "tx", "rx"; 1423 pinctrl-names = "default"; 1424 pinctrl-0 = <&qup_spi11_default>; 1425 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1426 spi-max-frequency = <50000000>; 1427 #address-cells = <1>; 1428 #size-cells = <0>; 1429 status = "disabled"; 1430 }; 1431 1432 uart2: serial@a90000 { 1433 compatible = "qcom,geni-debug-uart"; 1434 reg = <0x0 0x00a90000 0x0 0x4000>; 1435 clock-names = "se"; 1436 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1437 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1438 status = "disabled"; 1439 }; 1440 1441 i2c12: i2c@a90000 { 1442 compatible = "qcom,geni-i2c"; 1443 reg = <0 0x00a90000 0 0x4000>; 1444 clock-names = "se"; 1445 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1446 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1447 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1448 dma-names = "tx", "rx"; 1449 pinctrl-names = "default"; 1450 pinctrl-0 = <&qup_i2c12_default>; 1451 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1452 #address-cells = <1>; 1453 #size-cells = <0>; 1454 status = "disabled"; 1455 }; 1456 1457 spi12: spi@a90000 { 1458 compatible = "qcom,geni-spi"; 1459 reg = <0 0x00a90000 0 0x4000>; 1460 reg-names = "se"; 1461 clock-names = "se"; 1462 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1463 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1464 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1465 dma-names = "tx", "rx"; 1466 pinctrl-names = "default"; 1467 pinctrl-0 = <&qup_spi12_default>; 1468 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1469 spi-max-frequency = <50000000>; 1470 #address-cells = <1>; 1471 #size-cells = <0>; 1472 status = "disabled"; 1473 }; 1474 1475 i2c16: i2c@94000 { 1476 compatible = "qcom,geni-i2c"; 1477 reg = <0 0x00094000 0 0x4000>; 1478 clock-names = "se"; 1479 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1480 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1481 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1482 dma-names = "tx", "rx"; 1483 pinctrl-names = "default"; 1484 pinctrl-0 = <&qup_i2c16_default>; 1485 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1486 #address-cells = <1>; 1487 #size-cells = <0>; 1488 status = "disabled"; 1489 }; 1490 1491 spi16: spi@a94000 { 1492 compatible = "qcom,geni-spi"; 1493 reg = <0 0x00a94000 0 0x4000>; 1494 reg-names = "se"; 1495 clock-names = "se"; 1496 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1497 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1498 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1499 dma-names = "tx", "rx"; 1500 pinctrl-names = "default"; 1501 pinctrl-0 = <&qup_spi16_default>; 1502 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1503 spi-max-frequency = <50000000>; 1504 #address-cells = <1>; 1505 #size-cells = <0>; 1506 status = "disabled"; 1507 }; 1508 }; 1509 1510 gpi_dma2: dma-controller@c00000 { 1511 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1512 reg = <0 0x00c00000 0 0x60000>; 1513 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 1526 dma-channels = <13>; 1527 dma-channel-mask = <0xfa>; 1528 iommus = <&apps_smmu 0x07b6 0x0>; 1529 #dma-cells = <3>; 1530 status = "disabled"; 1531 }; 1532 1533 qupv3_id_2: geniqup@cc0000 { 1534 compatible = "qcom,geni-se-qup"; 1535 reg = <0x0 0x00cc0000 0x0 0x6000>; 1536 1537 clock-names = "m-ahb", "s-ahb"; 1538 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1539 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1540 iommus = <&apps_smmu 0x7a3 0x0>; 1541 #address-cells = <2>; 1542 #size-cells = <2>; 1543 ranges; 1544 status = "disabled"; 1545 1546 i2c17: i2c@c80000 { 1547 compatible = "qcom,geni-i2c"; 1548 reg = <0 0x00c80000 0 0x4000>; 1549 clock-names = "se"; 1550 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1551 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1552 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1553 dma-names = "tx", "rx"; 1554 pinctrl-names = "default"; 1555 pinctrl-0 = <&qup_i2c17_default>; 1556 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1557 #address-cells = <1>; 1558 #size-cells = <0>; 1559 status = "disabled"; 1560 }; 1561 1562 spi17: spi@c80000 { 1563 compatible = "qcom,geni-spi"; 1564 reg = <0 0x00c80000 0 0x4000>; 1565 reg-names = "se"; 1566 clock-names = "se"; 1567 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1568 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1569 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1570 dma-names = "tx", "rx"; 1571 pinctrl-names = "default"; 1572 pinctrl-0 = <&qup_spi17_default>; 1573 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1574 spi-max-frequency = <50000000>; 1575 #address-cells = <1>; 1576 #size-cells = <0>; 1577 status = "disabled"; 1578 }; 1579 1580 i2c18: i2c@c84000 { 1581 compatible = "qcom,geni-i2c"; 1582 reg = <0 0x00c84000 0 0x4000>; 1583 clock-names = "se"; 1584 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1585 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1586 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1587 dma-names = "tx", "rx"; 1588 pinctrl-names = "default"; 1589 pinctrl-0 = <&qup_i2c18_default>; 1590 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1591 #address-cells = <1>; 1592 #size-cells = <0>; 1593 status = "disabled"; 1594 }; 1595 1596 spi18: spi@c84000 { 1597 compatible = "qcom,geni-spi"; 1598 reg = <0 0x00c84000 0 0x4000>; 1599 reg-names = "se"; 1600 clock-names = "se"; 1601 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1602 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1603 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1604 dma-names = "tx", "rx"; 1605 pinctrl-names = "default"; 1606 pinctrl-0 = <&qup_spi18_default>; 1607 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1608 spi-max-frequency = <50000000>; 1609 #address-cells = <1>; 1610 #size-cells = <0>; 1611 status = "disabled"; 1612 }; 1613 1614 i2c19: i2c@c88000 { 1615 compatible = "qcom,geni-i2c"; 1616 reg = <0 0x00c88000 0 0x4000>; 1617 clock-names = "se"; 1618 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1619 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1620 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1621 dma-names = "tx", "rx"; 1622 pinctrl-names = "default"; 1623 pinctrl-0 = <&qup_i2c19_default>; 1624 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 status = "disabled"; 1628 }; 1629 1630 spi19: spi@c88000 { 1631 compatible = "qcom,geni-spi"; 1632 reg = <0 0x00c88000 0 0x4000>; 1633 reg-names = "se"; 1634 clock-names = "se"; 1635 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1636 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1637 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1638 dma-names = "tx", "rx"; 1639 pinctrl-names = "default"; 1640 pinctrl-0 = <&qup_spi19_default>; 1641 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1642 spi-max-frequency = <50000000>; 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 status = "disabled"; 1646 }; 1647 1648 i2c13: i2c@c8c000 { 1649 compatible = "qcom,geni-i2c"; 1650 reg = <0 0x00c8c000 0 0x4000>; 1651 clock-names = "se"; 1652 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1653 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1654 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1655 dma-names = "tx", "rx"; 1656 pinctrl-names = "default"; 1657 pinctrl-0 = <&qup_i2c13_default>; 1658 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 status = "disabled"; 1662 }; 1663 1664 spi13: spi@c8c000 { 1665 compatible = "qcom,geni-spi"; 1666 reg = <0 0x00c8c000 0 0x4000>; 1667 reg-names = "se"; 1668 clock-names = "se"; 1669 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1670 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1671 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1672 dma-names = "tx", "rx"; 1673 pinctrl-names = "default"; 1674 pinctrl-0 = <&qup_spi13_default>; 1675 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1676 spi-max-frequency = <50000000>; 1677 #address-cells = <1>; 1678 #size-cells = <0>; 1679 status = "disabled"; 1680 }; 1681 1682 i2c14: i2c@c90000 { 1683 compatible = "qcom,geni-i2c"; 1684 reg = <0 0x00c90000 0 0x4000>; 1685 clock-names = "se"; 1686 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1687 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1688 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1689 dma-names = "tx", "rx"; 1690 pinctrl-names = "default"; 1691 pinctrl-0 = <&qup_i2c14_default>; 1692 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1693 #address-cells = <1>; 1694 #size-cells = <0>; 1695 status = "disabled"; 1696 }; 1697 1698 spi14: spi@c90000 { 1699 compatible = "qcom,geni-spi"; 1700 reg = <0 0x00c90000 0 0x4000>; 1701 reg-names = "se"; 1702 clock-names = "se"; 1703 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1704 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1705 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1706 dma-names = "tx", "rx"; 1707 pinctrl-names = "default"; 1708 pinctrl-0 = <&qup_spi14_default>; 1709 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1710 spi-max-frequency = <50000000>; 1711 #address-cells = <1>; 1712 #size-cells = <0>; 1713 status = "disabled"; 1714 }; 1715 1716 i2c15: i2c@c94000 { 1717 compatible = "qcom,geni-i2c"; 1718 reg = <0 0x00c94000 0 0x4000>; 1719 clock-names = "se"; 1720 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1721 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1722 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1723 dma-names = "tx", "rx"; 1724 pinctrl-names = "default"; 1725 pinctrl-0 = <&qup_i2c15_default>; 1726 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1727 #address-cells = <1>; 1728 #size-cells = <0>; 1729 status = "disabled"; 1730 }; 1731 1732 spi15: spi@c94000 { 1733 compatible = "qcom,geni-spi"; 1734 reg = <0 0x00c94000 0 0x4000>; 1735 reg-names = "se"; 1736 clock-names = "se"; 1737 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1738 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1739 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1740 dma-names = "tx", "rx"; 1741 pinctrl-names = "default"; 1742 pinctrl-0 = <&qup_spi15_default>; 1743 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1744 spi-max-frequency = <50000000>; 1745 #address-cells = <1>; 1746 #size-cells = <0>; 1747 status = "disabled"; 1748 }; 1749 }; 1750 1751 config_noc: interconnect@1500000 { 1752 compatible = "qcom,sm8150-config-noc"; 1753 reg = <0 0x01500000 0 0x7400>; 1754 #interconnect-cells = <1>; 1755 qcom,bcm-voters = <&apps_bcm_voter>; 1756 }; 1757 1758 system_noc: interconnect@1620000 { 1759 compatible = "qcom,sm8150-system-noc"; 1760 reg = <0 0x01620000 0 0x19400>; 1761 #interconnect-cells = <1>; 1762 qcom,bcm-voters = <&apps_bcm_voter>; 1763 }; 1764 1765 mc_virt: interconnect@163a000 { 1766 compatible = "qcom,sm8150-mc-virt"; 1767 reg = <0 0x0163a000 0 0x1000>; 1768 #interconnect-cells = <1>; 1769 qcom,bcm-voters = <&apps_bcm_voter>; 1770 }; 1771 1772 aggre1_noc: interconnect@16e0000 { 1773 compatible = "qcom,sm8150-aggre1-noc"; 1774 reg = <0 0x016e0000 0 0xd080>; 1775 #interconnect-cells = <1>; 1776 qcom,bcm-voters = <&apps_bcm_voter>; 1777 }; 1778 1779 aggre2_noc: interconnect@1700000 { 1780 compatible = "qcom,sm8150-aggre2-noc"; 1781 reg = <0 0x01700000 0 0x20000>; 1782 #interconnect-cells = <1>; 1783 qcom,bcm-voters = <&apps_bcm_voter>; 1784 }; 1785 1786 compute_noc: interconnect@1720000 { 1787 compatible = "qcom,sm8150-compute-noc"; 1788 reg = <0 0x01720000 0 0x7000>; 1789 #interconnect-cells = <1>; 1790 qcom,bcm-voters = <&apps_bcm_voter>; 1791 }; 1792 1793 mmss_noc: interconnect@1740000 { 1794 compatible = "qcom,sm8150-mmss-noc"; 1795 reg = <0 0x01740000 0 0x1c100>; 1796 #interconnect-cells = <1>; 1797 qcom,bcm-voters = <&apps_bcm_voter>; 1798 }; 1799 1800 system-cache-controller@9200000 { 1801 compatible = "qcom,sm8150-llcc"; 1802 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 1803 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 1804 <0 0x09600000 0 0x50000>; 1805 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 1806 "llcc3_base", "llcc_broadcast_base"; 1807 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1808 }; 1809 1810 dma@10a2000 { 1811 compatible = "qcom,sm8150-dcc", "qcom,dcc"; 1812 reg = <0x0 0x010a2000 0x0 0x1000>, 1813 <0x0 0x010ad000 0x0 0x3000>; 1814 }; 1815 1816 pcie0: pci@1c00000 { 1817 compatible = "qcom,pcie-sm8150"; 1818 reg = <0 0x01c00000 0 0x3000>, 1819 <0 0x60000000 0 0xf1d>, 1820 <0 0x60000f20 0 0xa8>, 1821 <0 0x60001000 0 0x1000>, 1822 <0 0x60100000 0 0x100000>; 1823 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1824 device_type = "pci"; 1825 linux,pci-domain = <0>; 1826 bus-range = <0x00 0xff>; 1827 num-lanes = <1>; 1828 1829 #address-cells = <3>; 1830 #size-cells = <2>; 1831 1832 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1833 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1834 1835 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1836 interrupt-names = "msi"; 1837 #interrupt-cells = <1>; 1838 interrupt-map-mask = <0 0 0 0x7>; 1839 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1840 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1841 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1842 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1843 1844 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1845 <&gcc GCC_PCIE_0_AUX_CLK>, 1846 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1847 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1848 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1849 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1850 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1851 clock-names = "pipe", 1852 "aux", 1853 "cfg", 1854 "bus_master", 1855 "bus_slave", 1856 "slave_q2a", 1857 "tbu"; 1858 1859 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1860 <0x100 &apps_smmu 0x1d81 0x1>; 1861 1862 resets = <&gcc GCC_PCIE_0_BCR>; 1863 reset-names = "pci"; 1864 1865 power-domains = <&gcc PCIE_0_GDSC>; 1866 1867 phys = <&pcie0_lane>; 1868 phy-names = "pciephy"; 1869 1870 perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1871 enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1872 1873 pinctrl-names = "default"; 1874 pinctrl-0 = <&pcie0_default_state>; 1875 1876 status = "disabled"; 1877 }; 1878 1879 pcie0_phy: phy@1c06000 { 1880 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1881 reg = <0 0x01c06000 0 0x1c0>; 1882 #address-cells = <2>; 1883 #size-cells = <2>; 1884 ranges; 1885 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1886 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1887 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1888 clock-names = "aux", "cfg_ahb", "refgen"; 1889 1890 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1891 reset-names = "phy"; 1892 1893 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1894 assigned-clock-rates = <100000000>; 1895 1896 status = "disabled"; 1897 1898 pcie0_lane: phy@1c06200 { 1899 reg = <0 0x01c06200 0 0x170>, /* tx */ 1900 <0 0x01c06400 0 0x200>, /* rx */ 1901 <0 0x01c06800 0 0x1f0>, /* pcs */ 1902 <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1903 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1904 clock-names = "pipe0"; 1905 1906 #phy-cells = <0>; 1907 clock-output-names = "pcie_0_pipe_clk"; 1908 }; 1909 }; 1910 1911 pcie1: pci@1c08000 { 1912 compatible = "qcom,pcie-sm8150"; 1913 reg = <0 0x01c08000 0 0x3000>, 1914 <0 0x40000000 0 0xf1d>, 1915 <0 0x40000f20 0 0xa8>, 1916 <0 0x40001000 0 0x1000>, 1917 <0 0x40100000 0 0x100000>; 1918 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1919 device_type = "pci"; 1920 linux,pci-domain = <1>; 1921 bus-range = <0x00 0xff>; 1922 num-lanes = <2>; 1923 1924 #address-cells = <3>; 1925 #size-cells = <2>; 1926 1927 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1928 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1929 1930 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1931 interrupt-names = "msi"; 1932 #interrupt-cells = <1>; 1933 interrupt-map-mask = <0 0 0 0x7>; 1934 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1935 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1936 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1937 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1938 1939 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1940 <&gcc GCC_PCIE_1_AUX_CLK>, 1941 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1942 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1943 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1944 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1945 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1946 clock-names = "pipe", 1947 "aux", 1948 "cfg", 1949 "bus_master", 1950 "bus_slave", 1951 "slave_q2a", 1952 "tbu"; 1953 1954 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1955 assigned-clock-rates = <19200000>; 1956 1957 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1958 <0x100 &apps_smmu 0x1e01 0x1>; 1959 1960 resets = <&gcc GCC_PCIE_1_BCR>; 1961 reset-names = "pci"; 1962 1963 power-domains = <&gcc PCIE_1_GDSC>; 1964 1965 phys = <&pcie1_lane>; 1966 phy-names = "pciephy"; 1967 1968 perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; 1969 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 1970 1971 pinctrl-names = "default"; 1972 pinctrl-0 = <&pcie1_default_state>; 1973 1974 status = "disabled"; 1975 }; 1976 1977 pcie1_phy: phy@1c0e000 { 1978 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 1979 reg = <0 0x01c0e000 0 0x1c0>; 1980 #address-cells = <2>; 1981 #size-cells = <2>; 1982 ranges; 1983 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1984 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1985 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1986 clock-names = "aux", "cfg_ahb", "refgen"; 1987 1988 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1989 reset-names = "phy"; 1990 1991 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1992 assigned-clock-rates = <100000000>; 1993 1994 status = "disabled"; 1995 1996 pcie1_lane: phy@1c0e200 { 1997 reg = <0 0x01c0e200 0 0x170>, /* tx0 */ 1998 <0 0x01c0e400 0 0x200>, /* rx0 */ 1999 <0 0x01c0ea00 0 0x1f0>, /* pcs */ 2000 <0 0x01c0e600 0 0x170>, /* tx1 */ 2001 <0 0x01c0e800 0 0x200>, /* rx1 */ 2002 <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2003 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2004 clock-names = "pipe0"; 2005 2006 #phy-cells = <0>; 2007 clock-output-names = "pcie_1_pipe_clk"; 2008 }; 2009 }; 2010 2011 ufs_mem_hc: ufshc@1d84000 { 2012 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 2013 "jedec,ufs-2.0"; 2014 reg = <0 0x01d84000 0 0x2500>, 2015 <0 0x01d90000 0 0x8000>; 2016 reg-names = "std", "ice"; 2017 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2018 phys = <&ufs_mem_phy_lanes>; 2019 phy-names = "ufsphy"; 2020 lanes-per-direction = <2>; 2021 #reset-cells = <1>; 2022 resets = <&gcc GCC_UFS_PHY_BCR>; 2023 reset-names = "rst"; 2024 2025 iommus = <&apps_smmu 0x300 0>; 2026 2027 clock-names = 2028 "core_clk", 2029 "bus_aggr_clk", 2030 "iface_clk", 2031 "core_clk_unipro", 2032 "ref_clk", 2033 "tx_lane0_sync_clk", 2034 "rx_lane0_sync_clk", 2035 "rx_lane1_sync_clk", 2036 "ice_core_clk"; 2037 clocks = 2038 <&gcc GCC_UFS_PHY_AXI_CLK>, 2039 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2040 <&gcc GCC_UFS_PHY_AHB_CLK>, 2041 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2042 <&rpmhcc RPMH_CXO_CLK>, 2043 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2044 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2045 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2046 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2047 freq-table-hz = 2048 <37500000 300000000>, 2049 <0 0>, 2050 <0 0>, 2051 <37500000 300000000>, 2052 <0 0>, 2053 <0 0>, 2054 <0 0>, 2055 <0 0>, 2056 <0 300000000>; 2057 2058 status = "disabled"; 2059 }; 2060 2061 ufs_mem_phy: phy@1d87000 { 2062 compatible = "qcom,sm8150-qmp-ufs-phy"; 2063 reg = <0 0x01d87000 0 0x1c0>; 2064 #address-cells = <2>; 2065 #size-cells = <2>; 2066 ranges; 2067 clock-names = "ref", 2068 "ref_aux"; 2069 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2070 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2071 2072 power-domains = <&gcc UFS_PHY_GDSC>; 2073 2074 resets = <&ufs_mem_hc 0>; 2075 reset-names = "ufsphy"; 2076 status = "disabled"; 2077 2078 ufs_mem_phy_lanes: phy@1d87400 { 2079 reg = <0 0x01d87400 0 0x16c>, 2080 <0 0x01d87600 0 0x200>, 2081 <0 0x01d87c00 0 0x200>, 2082 <0 0x01d87800 0 0x16c>, 2083 <0 0x01d87a00 0 0x200>; 2084 #phy-cells = <0>; 2085 }; 2086 }; 2087 2088 cryptobam: dma-controller@1dc4000 { 2089 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2090 reg = <0 0x01dc4000 0 0x24000>; 2091 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2092 #dma-cells = <1>; 2093 qcom,ee = <0>; 2094 qcom,controlled-remotely; 2095 num-channels = <8>; 2096 qcom,num-ees = <2>; 2097 iommus = <&apps_smmu 0x502 0x0641>, 2098 <&apps_smmu 0x504 0x0011>, 2099 <&apps_smmu 0x506 0x0011>, 2100 <&apps_smmu 0x508 0x0011>, 2101 <&apps_smmu 0x512 0x0000>; 2102 }; 2103 2104 crypto: crypto@1dfa000 { 2105 compatible = "qcom,sm8150-qce", "qcom,qce"; 2106 reg = <0 0x01dfa000 0 0x6000>; 2107 dmas = <&cryptobam 4>, <&cryptobam 5>; 2108 dma-names = "rx", "tx"; 2109 iommus = <&apps_smmu 0x502 0x0641>, 2110 <&apps_smmu 0x504 0x0011>, 2111 <&apps_smmu 0x506 0x0011>, 2112 <&apps_smmu 0x508 0x0011>, 2113 <&apps_smmu 0x512 0x0000>; 2114 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; 2115 interconnect-names = "memory"; 2116 }; 2117 2118 tcsr_mutex: hwlock@1f40000 { 2119 compatible = "qcom,tcsr-mutex"; 2120 reg = <0x0 0x01f40000 0x0 0x20000>; 2121 #hwlock-cells = <1>; 2122 }; 2123 2124 tcsr_regs_1: syscon@1f60000 { 2125 compatible = "qcom,sm8150-tcsr", "syscon"; 2126 reg = <0x0 0x01f60000 0x0 0x20000>; 2127 }; 2128 2129 remoteproc_slpi: remoteproc@2400000 { 2130 compatible = "qcom,sm8150-slpi-pas"; 2131 reg = <0x0 0x02400000 0x0 0x4040>; 2132 2133 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 2134 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2135 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2136 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2137 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2138 interrupt-names = "wdog", "fatal", "ready", 2139 "handover", "stop-ack"; 2140 2141 clocks = <&rpmhcc RPMH_CXO_CLK>; 2142 clock-names = "xo"; 2143 2144 power-domains = <&rpmhpd SM8150_LCX>, 2145 <&rpmhpd SM8150_LMX>; 2146 power-domain-names = "lcx", "lmx"; 2147 2148 memory-region = <&slpi_mem>; 2149 2150 qcom,qmp = <&aoss_qmp>; 2151 2152 qcom,smem-states = <&slpi_smp2p_out 0>; 2153 qcom,smem-state-names = "stop"; 2154 2155 status = "disabled"; 2156 2157 glink-edge { 2158 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 2159 label = "dsps"; 2160 qcom,remote-pid = <3>; 2161 mboxes = <&apss_shared 24>; 2162 2163 fastrpc { 2164 compatible = "qcom,fastrpc"; 2165 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2166 label = "sdsp"; 2167 qcom,non-secure-domain; 2168 #address-cells = <1>; 2169 #size-cells = <0>; 2170 2171 compute-cb@1 { 2172 compatible = "qcom,fastrpc-compute-cb"; 2173 reg = <1>; 2174 iommus = <&apps_smmu 0x05a1 0x0>; 2175 }; 2176 2177 compute-cb@2 { 2178 compatible = "qcom,fastrpc-compute-cb"; 2179 reg = <2>; 2180 iommus = <&apps_smmu 0x05a2 0x0>; 2181 }; 2182 2183 compute-cb@3 { 2184 compatible = "qcom,fastrpc-compute-cb"; 2185 reg = <3>; 2186 iommus = <&apps_smmu 0x05a3 0x0>; 2187 /* note: shared-cb = <4> in downstream */ 2188 }; 2189 }; 2190 }; 2191 }; 2192 2193 gpu: gpu@2c00000 { 2194 compatible = "qcom,adreno-640.1", "qcom,adreno"; 2195 reg = <0 0x02c00000 0 0x40000>; 2196 reg-names = "kgsl_3d0_reg_memory"; 2197 2198 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2199 2200 iommus = <&adreno_smmu 0 0x401>; 2201 2202 operating-points-v2 = <&gpu_opp_table>; 2203 2204 qcom,gmu = <&gmu>; 2205 2206 nvmem-cells = <&gpu_speed_bin>; 2207 nvmem-cell-names = "speed_bin"; 2208 2209 status = "disabled"; 2210 2211 zap-shader { 2212 memory-region = <&gpu_mem>; 2213 }; 2214 2215 gpu_opp_table: opp-table { 2216 compatible = "operating-points-v2"; 2217 2218 opp-675000000 { 2219 opp-hz = /bits/ 64 <675000000>; 2220 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2221 opp-supported-hw = <0x2>; 2222 }; 2223 2224 opp-585000000 { 2225 opp-hz = /bits/ 64 <585000000>; 2226 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2227 opp-supported-hw = <0x3>; 2228 }; 2229 2230 opp-499200000 { 2231 opp-hz = /bits/ 64 <499200000>; 2232 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2233 opp-supported-hw = <0x3>; 2234 }; 2235 2236 opp-427000000 { 2237 opp-hz = /bits/ 64 <427000000>; 2238 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2239 opp-supported-hw = <0x3>; 2240 }; 2241 2242 opp-345000000 { 2243 opp-hz = /bits/ 64 <345000000>; 2244 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2245 opp-supported-hw = <0x3>; 2246 }; 2247 2248 opp-257000000 { 2249 opp-hz = /bits/ 64 <257000000>; 2250 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2251 opp-supported-hw = <0x3>; 2252 }; 2253 }; 2254 }; 2255 2256 gmu: gmu@2c6a000 { 2257 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2258 2259 reg = <0 0x02c6a000 0 0x30000>, 2260 <0 0x0b290000 0 0x10000>, 2261 <0 0x0b490000 0 0x10000>; 2262 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2263 2264 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2265 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2266 interrupt-names = "hfi", "gmu"; 2267 2268 clocks = <&gpucc GPU_CC_AHB_CLK>, 2269 <&gpucc GPU_CC_CX_GMU_CLK>, 2270 <&gpucc GPU_CC_CXO_CLK>, 2271 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2272 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2273 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2274 2275 power-domains = <&gpucc GPU_CX_GDSC>, 2276 <&gpucc GPU_GX_GDSC>; 2277 power-domain-names = "cx", "gx"; 2278 2279 iommus = <&adreno_smmu 5 0x400>; 2280 2281 operating-points-v2 = <&gmu_opp_table>; 2282 2283 status = "disabled"; 2284 2285 gmu_opp_table: opp-table { 2286 compatible = "operating-points-v2"; 2287 2288 opp-200000000 { 2289 opp-hz = /bits/ 64 <200000000>; 2290 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2291 }; 2292 }; 2293 }; 2294 2295 gpucc: clock-controller@2c90000 { 2296 compatible = "qcom,sm8150-gpucc"; 2297 reg = <0 0x02c90000 0 0x9000>; 2298 clocks = <&rpmhcc RPMH_CXO_CLK>, 2299 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2300 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2301 clock-names = "bi_tcxo", 2302 "gcc_gpu_gpll0_clk_src", 2303 "gcc_gpu_gpll0_div_clk_src"; 2304 #clock-cells = <1>; 2305 #reset-cells = <1>; 2306 #power-domain-cells = <1>; 2307 }; 2308 2309 adreno_smmu: iommu@2ca0000 { 2310 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", 2311 "qcom,smmu-500", "arm,mmu-500"; 2312 reg = <0 0x02ca0000 0 0x10000>; 2313 #iommu-cells = <2>; 2314 #global-interrupts = <1>; 2315 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2316 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2317 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2318 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2319 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2320 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2321 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2322 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2323 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2324 clocks = <&gpucc GPU_CC_AHB_CLK>, 2325 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2326 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2327 clock-names = "ahb", "bus", "iface"; 2328 2329 power-domains = <&gpucc GPU_CX_GDSC>; 2330 }; 2331 2332 tlmm: pinctrl@3100000 { 2333 compatible = "qcom,sm8150-pinctrl"; 2334 reg = <0x0 0x03100000 0x0 0x300000>, 2335 <0x0 0x03500000 0x0 0x300000>, 2336 <0x0 0x03900000 0x0 0x300000>, 2337 <0x0 0x03D00000 0x0 0x300000>; 2338 reg-names = "west", "east", "north", "south"; 2339 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2340 gpio-ranges = <&tlmm 0 0 176>; 2341 gpio-controller; 2342 #gpio-cells = <2>; 2343 interrupt-controller; 2344 #interrupt-cells = <2>; 2345 wakeup-parent = <&pdc>; 2346 2347 qup_i2c0_default: qup-i2c0-default-state { 2348 pins = "gpio0", "gpio1"; 2349 function = "qup0"; 2350 drive-strength = <0x02>; 2351 bias-disable; 2352 }; 2353 2354 qup_spi0_default: qup-spi0-default-state { 2355 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2356 function = "qup0"; 2357 drive-strength = <6>; 2358 bias-disable; 2359 }; 2360 2361 qup_i2c1_default: qup-i2c1-default-state { 2362 pins = "gpio114", "gpio115"; 2363 function = "qup1"; 2364 drive-strength = <2>; 2365 bias-disable; 2366 }; 2367 2368 qup_spi1_default: qup-spi1-default-state { 2369 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2370 function = "qup1"; 2371 drive-strength = <6>; 2372 bias-disable; 2373 }; 2374 2375 qup_i2c2_default: qup-i2c2-default-state { 2376 pins = "gpio126", "gpio127"; 2377 function = "qup2"; 2378 drive-strength = <2>; 2379 bias-disable; 2380 }; 2381 2382 qup_spi2_default: qup-spi2-default-state { 2383 pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2384 function = "qup2"; 2385 drive-strength = <6>; 2386 bias-disable; 2387 }; 2388 2389 qup_i2c3_default: qup-i2c3-default-state { 2390 pins = "gpio144", "gpio145"; 2391 function = "qup3"; 2392 drive-strength = <2>; 2393 bias-disable; 2394 }; 2395 2396 qup_spi3_default: qup-spi3-default-state { 2397 pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2398 function = "qup3"; 2399 drive-strength = <6>; 2400 bias-disable; 2401 }; 2402 2403 qup_i2c4_default: qup-i2c4-default-state { 2404 pins = "gpio51", "gpio52"; 2405 function = "qup4"; 2406 drive-strength = <2>; 2407 bias-disable; 2408 }; 2409 2410 qup_spi4_default: qup-spi4-default-state { 2411 pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2412 function = "qup4"; 2413 drive-strength = <6>; 2414 bias-disable; 2415 }; 2416 2417 qup_i2c5_default: qup-i2c5-default-state { 2418 pins = "gpio121", "gpio122"; 2419 function = "qup5"; 2420 drive-strength = <2>; 2421 bias-disable; 2422 }; 2423 2424 qup_spi5_default: qup-spi5-default-state { 2425 pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2426 function = "qup5"; 2427 drive-strength = <6>; 2428 bias-disable; 2429 }; 2430 2431 qup_i2c6_default: qup-i2c6-default-state { 2432 pins = "gpio6", "gpio7"; 2433 function = "qup6"; 2434 drive-strength = <2>; 2435 bias-disable; 2436 }; 2437 2438 qup_spi6_default: qup-spi6_default-state { 2439 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2440 function = "qup6"; 2441 drive-strength = <6>; 2442 bias-disable; 2443 }; 2444 2445 qup_i2c7_default: qup-i2c7-default-state { 2446 pins = "gpio98", "gpio99"; 2447 function = "qup7"; 2448 drive-strength = <2>; 2449 bias-disable; 2450 }; 2451 2452 qup_spi7_default: qup-spi7_default-state { 2453 pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2454 function = "qup7"; 2455 drive-strength = <6>; 2456 bias-disable; 2457 }; 2458 2459 qup_i2c8_default: qup-i2c8-default-state { 2460 pins = "gpio88", "gpio89"; 2461 function = "qup8"; 2462 drive-strength = <2>; 2463 bias-disable; 2464 }; 2465 2466 qup_spi8_default: qup-spi8-default-state { 2467 pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2468 function = "qup8"; 2469 drive-strength = <6>; 2470 bias-disable; 2471 }; 2472 2473 qup_i2c9_default: qup-i2c9-default-state { 2474 pins = "gpio39", "gpio40"; 2475 function = "qup9"; 2476 drive-strength = <2>; 2477 bias-disable; 2478 }; 2479 2480 qup_spi9_default: qup-spi9-default-state { 2481 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2482 function = "qup9"; 2483 drive-strength = <6>; 2484 bias-disable; 2485 }; 2486 2487 qup_uart9_default: qup-uart9-default-state { 2488 pins = "gpio41", "gpio42"; 2489 function = "qup9"; 2490 drive-strength = <2>; 2491 bias-disable; 2492 }; 2493 2494 qup_i2c10_default: qup-i2c10-default-state { 2495 pins = "gpio9", "gpio10"; 2496 function = "qup10"; 2497 drive-strength = <2>; 2498 bias-disable; 2499 }; 2500 2501 qup_spi10_default: qup-spi10-default-state { 2502 pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2503 function = "qup10"; 2504 drive-strength = <6>; 2505 bias-disable; 2506 }; 2507 2508 qup_i2c11_default: qup-i2c11-default-state { 2509 pins = "gpio94", "gpio95"; 2510 function = "qup11"; 2511 drive-strength = <2>; 2512 bias-disable; 2513 }; 2514 2515 qup_spi11_default: qup-spi11-default-state { 2516 pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2517 function = "qup11"; 2518 drive-strength = <6>; 2519 bias-disable; 2520 }; 2521 2522 qup_i2c12_default: qup-i2c12-default-state { 2523 pins = "gpio83", "gpio84"; 2524 function = "qup12"; 2525 drive-strength = <2>; 2526 bias-disable; 2527 }; 2528 2529 qup_spi12_default: qup-spi12-default-state { 2530 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2531 function = "qup12"; 2532 drive-strength = <6>; 2533 bias-disable; 2534 }; 2535 2536 qup_i2c13_default: qup-i2c13-default-state { 2537 pins = "gpio43", "gpio44"; 2538 function = "qup13"; 2539 drive-strength = <2>; 2540 bias-disable; 2541 }; 2542 2543 qup_spi13_default: qup-spi13-default-state { 2544 pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2545 function = "qup13"; 2546 drive-strength = <6>; 2547 bias-disable; 2548 }; 2549 2550 qup_i2c14_default: qup-i2c14-default-state { 2551 pins = "gpio47", "gpio48"; 2552 function = "qup14"; 2553 drive-strength = <2>; 2554 bias-disable; 2555 }; 2556 2557 qup_spi14_default: qup-spi14-default-state { 2558 pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2559 function = "qup14"; 2560 drive-strength = <6>; 2561 bias-disable; 2562 }; 2563 2564 qup_i2c15_default: qup-i2c15-default-state { 2565 pins = "gpio27", "gpio28"; 2566 function = "qup15"; 2567 drive-strength = <2>; 2568 bias-disable; 2569 }; 2570 2571 qup_spi15_default: qup-spi15-default-state { 2572 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2573 function = "qup15"; 2574 drive-strength = <6>; 2575 bias-disable; 2576 }; 2577 2578 qup_i2c16_default: qup-i2c16-default-state { 2579 pins = "gpio86", "gpio85"; 2580 function = "qup16"; 2581 drive-strength = <2>; 2582 bias-disable; 2583 }; 2584 2585 qup_spi16_default: qup-spi16-default-state { 2586 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2587 function = "qup16"; 2588 drive-strength = <6>; 2589 bias-disable; 2590 }; 2591 2592 qup_i2c17_default: qup-i2c17-default-state { 2593 pins = "gpio55", "gpio56"; 2594 function = "qup17"; 2595 drive-strength = <2>; 2596 bias-disable; 2597 }; 2598 2599 qup_spi17_default: qup-spi17-default-state { 2600 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2601 function = "qup17"; 2602 drive-strength = <6>; 2603 bias-disable; 2604 }; 2605 2606 qup_i2c18_default: qup-i2c18-default-state { 2607 pins = "gpio23", "gpio24"; 2608 function = "qup18"; 2609 drive-strength = <2>; 2610 bias-disable; 2611 }; 2612 2613 qup_spi18_default: qup-spi18-default-state { 2614 pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2615 function = "qup18"; 2616 drive-strength = <6>; 2617 bias-disable; 2618 }; 2619 2620 qup_i2c19_default: qup-i2c19-default-state { 2621 pins = "gpio57", "gpio58"; 2622 function = "qup19"; 2623 drive-strength = <2>; 2624 bias-disable; 2625 }; 2626 2627 qup_spi19_default: qup-spi19-default-state { 2628 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2629 function = "qup19"; 2630 drive-strength = <6>; 2631 bias-disable; 2632 }; 2633 2634 pcie0_default_state: pcie0-default-state { 2635 perst-pins { 2636 pins = "gpio35"; 2637 function = "gpio"; 2638 drive-strength = <2>; 2639 bias-pull-down; 2640 }; 2641 2642 clkreq-pins { 2643 pins = "gpio36"; 2644 function = "pci_e0"; 2645 drive-strength = <2>; 2646 bias-pull-up; 2647 }; 2648 2649 wake-pins { 2650 pins = "gpio37"; 2651 function = "gpio"; 2652 drive-strength = <2>; 2653 bias-pull-up; 2654 }; 2655 }; 2656 2657 pcie1_default_state: pcie1-default-state { 2658 perst-pins { 2659 pins = "gpio102"; 2660 function = "gpio"; 2661 drive-strength = <2>; 2662 bias-pull-down; 2663 }; 2664 2665 clkreq-pins { 2666 pins = "gpio103"; 2667 function = "pci_e1"; 2668 drive-strength = <2>; 2669 bias-pull-up; 2670 }; 2671 2672 wake-pins { 2673 pins = "gpio104"; 2674 function = "gpio"; 2675 drive-strength = <2>; 2676 bias-pull-up; 2677 }; 2678 }; 2679 }; 2680 2681 remoteproc_mpss: remoteproc@4080000 { 2682 compatible = "qcom,sm8150-mpss-pas"; 2683 reg = <0x0 0x04080000 0x0 0x4040>; 2684 2685 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2686 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2687 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2688 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2689 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2690 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2691 interrupt-names = "wdog", "fatal", "ready", "handover", 2692 "stop-ack", "shutdown-ack"; 2693 2694 clocks = <&rpmhcc RPMH_CXO_CLK>; 2695 clock-names = "xo"; 2696 2697 power-domains = <&rpmhpd SM8150_CX>, 2698 <&rpmhpd SM8150_MSS>; 2699 power-domain-names = "cx", "mss"; 2700 2701 memory-region = <&mpss_mem>; 2702 2703 qcom,qmp = <&aoss_qmp>; 2704 2705 qcom,smem-states = <&modem_smp2p_out 0>; 2706 qcom,smem-state-names = "stop"; 2707 2708 status = "disabled"; 2709 2710 glink-edge { 2711 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2712 label = "modem"; 2713 qcom,remote-pid = <1>; 2714 mboxes = <&apss_shared 12>; 2715 }; 2716 }; 2717 2718 stm@6002000 { 2719 compatible = "arm,coresight-stm", "arm,primecell"; 2720 reg = <0 0x06002000 0 0x1000>, 2721 <0 0x16280000 0 0x180000>; 2722 reg-names = "stm-base", "stm-stimulus-base"; 2723 2724 clocks = <&aoss_qmp>; 2725 clock-names = "apb_pclk"; 2726 2727 out-ports { 2728 port { 2729 stm_out: endpoint { 2730 remote-endpoint = <&funnel0_in7>; 2731 }; 2732 }; 2733 }; 2734 }; 2735 2736 funnel@6041000 { 2737 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2738 reg = <0 0x06041000 0 0x1000>; 2739 2740 clocks = <&aoss_qmp>; 2741 clock-names = "apb_pclk"; 2742 2743 out-ports { 2744 port { 2745 funnel0_out: endpoint { 2746 remote-endpoint = <&merge_funnel_in0>; 2747 }; 2748 }; 2749 }; 2750 2751 in-ports { 2752 #address-cells = <1>; 2753 #size-cells = <0>; 2754 2755 port@7 { 2756 reg = <7>; 2757 funnel0_in7: endpoint { 2758 remote-endpoint = <&stm_out>; 2759 }; 2760 }; 2761 }; 2762 }; 2763 2764 funnel@6042000 { 2765 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2766 reg = <0 0x06042000 0 0x1000>; 2767 2768 clocks = <&aoss_qmp>; 2769 clock-names = "apb_pclk"; 2770 2771 out-ports { 2772 port { 2773 funnel1_out: endpoint { 2774 remote-endpoint = <&merge_funnel_in1>; 2775 }; 2776 }; 2777 }; 2778 2779 in-ports { 2780 #address-cells = <1>; 2781 #size-cells = <0>; 2782 2783 port@4 { 2784 reg = <4>; 2785 funnel1_in4: endpoint { 2786 remote-endpoint = <&swao_replicator_out>; 2787 }; 2788 }; 2789 }; 2790 }; 2791 2792 funnel@6043000 { 2793 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2794 reg = <0 0x06043000 0 0x1000>; 2795 2796 clocks = <&aoss_qmp>; 2797 clock-names = "apb_pclk"; 2798 2799 out-ports { 2800 port { 2801 funnel2_out: endpoint { 2802 remote-endpoint = <&merge_funnel_in2>; 2803 }; 2804 }; 2805 }; 2806 2807 in-ports { 2808 #address-cells = <1>; 2809 #size-cells = <0>; 2810 2811 port@2 { 2812 reg = <2>; 2813 funnel2_in2: endpoint { 2814 remote-endpoint = <&apss_merge_funnel_out>; 2815 }; 2816 }; 2817 }; 2818 }; 2819 2820 funnel@6045000 { 2821 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2822 reg = <0 0x06045000 0 0x1000>; 2823 2824 clocks = <&aoss_qmp>; 2825 clock-names = "apb_pclk"; 2826 2827 out-ports { 2828 port { 2829 merge_funnel_out: endpoint { 2830 remote-endpoint = <&etf_in>; 2831 }; 2832 }; 2833 }; 2834 2835 in-ports { 2836 #address-cells = <1>; 2837 #size-cells = <0>; 2838 2839 port@0 { 2840 reg = <0>; 2841 merge_funnel_in0: endpoint { 2842 remote-endpoint = <&funnel0_out>; 2843 }; 2844 }; 2845 2846 port@1 { 2847 reg = <1>; 2848 merge_funnel_in1: endpoint { 2849 remote-endpoint = <&funnel1_out>; 2850 }; 2851 }; 2852 2853 port@2 { 2854 reg = <2>; 2855 merge_funnel_in2: endpoint { 2856 remote-endpoint = <&funnel2_out>; 2857 }; 2858 }; 2859 }; 2860 }; 2861 2862 replicator@6046000 { 2863 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2864 reg = <0 0x06046000 0 0x1000>; 2865 2866 clocks = <&aoss_qmp>; 2867 clock-names = "apb_pclk"; 2868 2869 out-ports { 2870 #address-cells = <1>; 2871 #size-cells = <0>; 2872 2873 port@0 { 2874 reg = <0>; 2875 replicator_out0: endpoint { 2876 remote-endpoint = <&etr_in>; 2877 }; 2878 }; 2879 2880 port@1 { 2881 reg = <1>; 2882 replicator_out1: endpoint { 2883 remote-endpoint = <&replicator1_in>; 2884 }; 2885 }; 2886 }; 2887 2888 in-ports { 2889 port { 2890 replicator_in0: endpoint { 2891 remote-endpoint = <&etf_out>; 2892 }; 2893 }; 2894 }; 2895 }; 2896 2897 etf@6047000 { 2898 compatible = "arm,coresight-tmc", "arm,primecell"; 2899 reg = <0 0x06047000 0 0x1000>; 2900 2901 clocks = <&aoss_qmp>; 2902 clock-names = "apb_pclk"; 2903 2904 out-ports { 2905 port { 2906 etf_out: endpoint { 2907 remote-endpoint = <&replicator_in0>; 2908 }; 2909 }; 2910 }; 2911 2912 in-ports { 2913 port { 2914 etf_in: endpoint { 2915 remote-endpoint = <&merge_funnel_out>; 2916 }; 2917 }; 2918 }; 2919 }; 2920 2921 etr@6048000 { 2922 compatible = "arm,coresight-tmc", "arm,primecell"; 2923 reg = <0 0x06048000 0 0x1000>; 2924 iommus = <&apps_smmu 0x05e0 0x0>; 2925 2926 clocks = <&aoss_qmp>; 2927 clock-names = "apb_pclk"; 2928 arm,scatter-gather; 2929 2930 in-ports { 2931 port { 2932 etr_in: endpoint { 2933 remote-endpoint = <&replicator_out0>; 2934 }; 2935 }; 2936 }; 2937 }; 2938 2939 replicator@604a000 { 2940 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2941 reg = <0 0x0604a000 0 0x1000>; 2942 2943 clocks = <&aoss_qmp>; 2944 clock-names = "apb_pclk"; 2945 2946 out-ports { 2947 #address-cells = <1>; 2948 #size-cells = <0>; 2949 2950 port@1 { 2951 reg = <1>; 2952 replicator1_out: endpoint { 2953 remote-endpoint = <&swao_funnel_in>; 2954 }; 2955 }; 2956 }; 2957 2958 in-ports { 2959 #address-cells = <1>; 2960 #size-cells = <0>; 2961 2962 port@1 { 2963 reg = <1>; 2964 replicator1_in: endpoint { 2965 remote-endpoint = <&replicator_out1>; 2966 }; 2967 }; 2968 }; 2969 }; 2970 2971 funnel@6b08000 { 2972 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2973 reg = <0 0x06b08000 0 0x1000>; 2974 2975 clocks = <&aoss_qmp>; 2976 clock-names = "apb_pclk"; 2977 2978 out-ports { 2979 port { 2980 swao_funnel_out: endpoint { 2981 remote-endpoint = <&swao_etf_in>; 2982 }; 2983 }; 2984 }; 2985 2986 in-ports { 2987 #address-cells = <1>; 2988 #size-cells = <0>; 2989 2990 port@6 { 2991 reg = <6>; 2992 swao_funnel_in: endpoint { 2993 remote-endpoint = <&replicator1_out>; 2994 }; 2995 }; 2996 }; 2997 }; 2998 2999 etf@6b09000 { 3000 compatible = "arm,coresight-tmc", "arm,primecell"; 3001 reg = <0 0x06b09000 0 0x1000>; 3002 3003 clocks = <&aoss_qmp>; 3004 clock-names = "apb_pclk"; 3005 3006 out-ports { 3007 port { 3008 swao_etf_out: endpoint { 3009 remote-endpoint = <&swao_replicator_in>; 3010 }; 3011 }; 3012 }; 3013 3014 in-ports { 3015 port { 3016 swao_etf_in: endpoint { 3017 remote-endpoint = <&swao_funnel_out>; 3018 }; 3019 }; 3020 }; 3021 }; 3022 3023 replicator@6b0a000 { 3024 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3025 reg = <0 0x06b0a000 0 0x1000>; 3026 3027 clocks = <&aoss_qmp>; 3028 clock-names = "apb_pclk"; 3029 qcom,replicator-loses-context; 3030 3031 out-ports { 3032 port { 3033 swao_replicator_out: endpoint { 3034 remote-endpoint = <&funnel1_in4>; 3035 }; 3036 }; 3037 }; 3038 3039 in-ports { 3040 port { 3041 swao_replicator_in: endpoint { 3042 remote-endpoint = <&swao_etf_out>; 3043 }; 3044 }; 3045 }; 3046 }; 3047 3048 etm@7040000 { 3049 compatible = "arm,coresight-etm4x", "arm,primecell"; 3050 reg = <0 0x07040000 0 0x1000>; 3051 3052 cpu = <&CPU0>; 3053 3054 clocks = <&aoss_qmp>; 3055 clock-names = "apb_pclk"; 3056 arm,coresight-loses-context-with-cpu; 3057 qcom,skip-power-up; 3058 3059 out-ports { 3060 port { 3061 etm0_out: endpoint { 3062 remote-endpoint = <&apss_funnel_in0>; 3063 }; 3064 }; 3065 }; 3066 }; 3067 3068 etm@7140000 { 3069 compatible = "arm,coresight-etm4x", "arm,primecell"; 3070 reg = <0 0x07140000 0 0x1000>; 3071 3072 cpu = <&CPU1>; 3073 3074 clocks = <&aoss_qmp>; 3075 clock-names = "apb_pclk"; 3076 arm,coresight-loses-context-with-cpu; 3077 qcom,skip-power-up; 3078 3079 out-ports { 3080 port { 3081 etm1_out: endpoint { 3082 remote-endpoint = <&apss_funnel_in1>; 3083 }; 3084 }; 3085 }; 3086 }; 3087 3088 etm@7240000 { 3089 compatible = "arm,coresight-etm4x", "arm,primecell"; 3090 reg = <0 0x07240000 0 0x1000>; 3091 3092 cpu = <&CPU2>; 3093 3094 clocks = <&aoss_qmp>; 3095 clock-names = "apb_pclk"; 3096 arm,coresight-loses-context-with-cpu; 3097 qcom,skip-power-up; 3098 3099 out-ports { 3100 port { 3101 etm2_out: endpoint { 3102 remote-endpoint = <&apss_funnel_in2>; 3103 }; 3104 }; 3105 }; 3106 }; 3107 3108 etm@7340000 { 3109 compatible = "arm,coresight-etm4x", "arm,primecell"; 3110 reg = <0 0x07340000 0 0x1000>; 3111 3112 cpu = <&CPU3>; 3113 3114 clocks = <&aoss_qmp>; 3115 clock-names = "apb_pclk"; 3116 arm,coresight-loses-context-with-cpu; 3117 qcom,skip-power-up; 3118 3119 out-ports { 3120 port { 3121 etm3_out: endpoint { 3122 remote-endpoint = <&apss_funnel_in3>; 3123 }; 3124 }; 3125 }; 3126 }; 3127 3128 etm@7440000 { 3129 compatible = "arm,coresight-etm4x", "arm,primecell"; 3130 reg = <0 0x07440000 0 0x1000>; 3131 3132 cpu = <&CPU4>; 3133 3134 clocks = <&aoss_qmp>; 3135 clock-names = "apb_pclk"; 3136 arm,coresight-loses-context-with-cpu; 3137 qcom,skip-power-up; 3138 3139 out-ports { 3140 port { 3141 etm4_out: endpoint { 3142 remote-endpoint = <&apss_funnel_in4>; 3143 }; 3144 }; 3145 }; 3146 }; 3147 3148 etm@7540000 { 3149 compatible = "arm,coresight-etm4x", "arm,primecell"; 3150 reg = <0 0x07540000 0 0x1000>; 3151 3152 cpu = <&CPU5>; 3153 3154 clocks = <&aoss_qmp>; 3155 clock-names = "apb_pclk"; 3156 arm,coresight-loses-context-with-cpu; 3157 qcom,skip-power-up; 3158 3159 out-ports { 3160 port { 3161 etm5_out: endpoint { 3162 remote-endpoint = <&apss_funnel_in5>; 3163 }; 3164 }; 3165 }; 3166 }; 3167 3168 etm@7640000 { 3169 compatible = "arm,coresight-etm4x", "arm,primecell"; 3170 reg = <0 0x07640000 0 0x1000>; 3171 3172 cpu = <&CPU6>; 3173 3174 clocks = <&aoss_qmp>; 3175 clock-names = "apb_pclk"; 3176 arm,coresight-loses-context-with-cpu; 3177 qcom,skip-power-up; 3178 3179 out-ports { 3180 port { 3181 etm6_out: endpoint { 3182 remote-endpoint = <&apss_funnel_in6>; 3183 }; 3184 }; 3185 }; 3186 }; 3187 3188 etm@7740000 { 3189 compatible = "arm,coresight-etm4x", "arm,primecell"; 3190 reg = <0 0x07740000 0 0x1000>; 3191 3192 cpu = <&CPU7>; 3193 3194 clocks = <&aoss_qmp>; 3195 clock-names = "apb_pclk"; 3196 arm,coresight-loses-context-with-cpu; 3197 qcom,skip-power-up; 3198 3199 out-ports { 3200 port { 3201 etm7_out: endpoint { 3202 remote-endpoint = <&apss_funnel_in7>; 3203 }; 3204 }; 3205 }; 3206 }; 3207 3208 funnel@7800000 { /* APSS Funnel */ 3209 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3210 reg = <0 0x07800000 0 0x1000>; 3211 3212 clocks = <&aoss_qmp>; 3213 clock-names = "apb_pclk"; 3214 3215 out-ports { 3216 port { 3217 apss_funnel_out: endpoint { 3218 remote-endpoint = <&apss_merge_funnel_in>; 3219 }; 3220 }; 3221 }; 3222 3223 in-ports { 3224 #address-cells = <1>; 3225 #size-cells = <0>; 3226 3227 port@0 { 3228 reg = <0>; 3229 apss_funnel_in0: endpoint { 3230 remote-endpoint = <&etm0_out>; 3231 }; 3232 }; 3233 3234 port@1 { 3235 reg = <1>; 3236 apss_funnel_in1: endpoint { 3237 remote-endpoint = <&etm1_out>; 3238 }; 3239 }; 3240 3241 port@2 { 3242 reg = <2>; 3243 apss_funnel_in2: endpoint { 3244 remote-endpoint = <&etm2_out>; 3245 }; 3246 }; 3247 3248 port@3 { 3249 reg = <3>; 3250 apss_funnel_in3: endpoint { 3251 remote-endpoint = <&etm3_out>; 3252 }; 3253 }; 3254 3255 port@4 { 3256 reg = <4>; 3257 apss_funnel_in4: endpoint { 3258 remote-endpoint = <&etm4_out>; 3259 }; 3260 }; 3261 3262 port@5 { 3263 reg = <5>; 3264 apss_funnel_in5: endpoint { 3265 remote-endpoint = <&etm5_out>; 3266 }; 3267 }; 3268 3269 port@6 { 3270 reg = <6>; 3271 apss_funnel_in6: endpoint { 3272 remote-endpoint = <&etm6_out>; 3273 }; 3274 }; 3275 3276 port@7 { 3277 reg = <7>; 3278 apss_funnel_in7: endpoint { 3279 remote-endpoint = <&etm7_out>; 3280 }; 3281 }; 3282 }; 3283 }; 3284 3285 funnel@7810000 { 3286 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3287 reg = <0 0x07810000 0 0x1000>; 3288 3289 clocks = <&aoss_qmp>; 3290 clock-names = "apb_pclk"; 3291 3292 out-ports { 3293 port { 3294 apss_merge_funnel_out: endpoint { 3295 remote-endpoint = <&funnel2_in2>; 3296 }; 3297 }; 3298 }; 3299 3300 in-ports { 3301 port { 3302 apss_merge_funnel_in: endpoint { 3303 remote-endpoint = <&apss_funnel_out>; 3304 }; 3305 }; 3306 }; 3307 }; 3308 3309 remoteproc_cdsp: remoteproc@8300000 { 3310 compatible = "qcom,sm8150-cdsp-pas"; 3311 reg = <0x0 0x08300000 0x0 0x4040>; 3312 3313 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3314 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3315 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3316 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3317 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3318 interrupt-names = "wdog", "fatal", "ready", 3319 "handover", "stop-ack"; 3320 3321 clocks = <&rpmhcc RPMH_CXO_CLK>; 3322 clock-names = "xo"; 3323 3324 power-domains = <&rpmhpd SM8150_CX>; 3325 3326 memory-region = <&cdsp_mem>; 3327 3328 qcom,qmp = <&aoss_qmp>; 3329 3330 qcom,smem-states = <&cdsp_smp2p_out 0>; 3331 qcom,smem-state-names = "stop"; 3332 3333 status = "disabled"; 3334 3335 glink-edge { 3336 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 3337 label = "cdsp"; 3338 qcom,remote-pid = <5>; 3339 mboxes = <&apss_shared 4>; 3340 3341 fastrpc { 3342 compatible = "qcom,fastrpc"; 3343 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3344 label = "cdsp"; 3345 qcom,non-secure-domain; 3346 #address-cells = <1>; 3347 #size-cells = <0>; 3348 3349 compute-cb@1 { 3350 compatible = "qcom,fastrpc-compute-cb"; 3351 reg = <1>; 3352 iommus = <&apps_smmu 0x1001 0x0460>; 3353 }; 3354 3355 compute-cb@2 { 3356 compatible = "qcom,fastrpc-compute-cb"; 3357 reg = <2>; 3358 iommus = <&apps_smmu 0x1002 0x0460>; 3359 }; 3360 3361 compute-cb@3 { 3362 compatible = "qcom,fastrpc-compute-cb"; 3363 reg = <3>; 3364 iommus = <&apps_smmu 0x1003 0x0460>; 3365 }; 3366 3367 compute-cb@4 { 3368 compatible = "qcom,fastrpc-compute-cb"; 3369 reg = <4>; 3370 iommus = <&apps_smmu 0x1004 0x0460>; 3371 }; 3372 3373 compute-cb@5 { 3374 compatible = "qcom,fastrpc-compute-cb"; 3375 reg = <5>; 3376 iommus = <&apps_smmu 0x1005 0x0460>; 3377 }; 3378 3379 compute-cb@6 { 3380 compatible = "qcom,fastrpc-compute-cb"; 3381 reg = <6>; 3382 iommus = <&apps_smmu 0x1006 0x0460>; 3383 }; 3384 3385 compute-cb@7 { 3386 compatible = "qcom,fastrpc-compute-cb"; 3387 reg = <7>; 3388 iommus = <&apps_smmu 0x1007 0x0460>; 3389 }; 3390 3391 compute-cb@8 { 3392 compatible = "qcom,fastrpc-compute-cb"; 3393 reg = <8>; 3394 iommus = <&apps_smmu 0x1008 0x0460>; 3395 }; 3396 3397 /* note: secure cb9 in downstream */ 3398 }; 3399 }; 3400 }; 3401 3402 usb_1_hsphy: phy@88e2000 { 3403 compatible = "qcom,sm8150-usb-hs-phy", 3404 "qcom,usb-snps-hs-7nm-phy"; 3405 reg = <0 0x088e2000 0 0x400>; 3406 status = "disabled"; 3407 #phy-cells = <0>; 3408 3409 clocks = <&rpmhcc RPMH_CXO_CLK>; 3410 clock-names = "ref"; 3411 3412 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3413 }; 3414 3415 usb_2_hsphy: phy@88e3000 { 3416 compatible = "qcom,sm8150-usb-hs-phy", 3417 "qcom,usb-snps-hs-7nm-phy"; 3418 reg = <0 0x088e3000 0 0x400>; 3419 status = "disabled"; 3420 #phy-cells = <0>; 3421 3422 clocks = <&rpmhcc RPMH_CXO_CLK>; 3423 clock-names = "ref"; 3424 3425 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3426 }; 3427 3428 usb_1_qmpphy: phy@88e9000 { 3429 compatible = "qcom,sm8150-qmp-usb3-phy"; 3430 reg = <0 0x088e9000 0 0x18c>, 3431 <0 0x088e8000 0 0x10>; 3432 status = "disabled"; 3433 #address-cells = <2>; 3434 #size-cells = <2>; 3435 ranges; 3436 3437 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3438 <&rpmhcc RPMH_CXO_CLK>, 3439 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3440 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3441 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3442 3443 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3444 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3445 reset-names = "phy", "common"; 3446 3447 usb_1_ssphy: phy@88e9200 { 3448 reg = <0 0x088e9200 0 0x200>, 3449 <0 0x088e9400 0 0x200>, 3450 <0 0x088e9c00 0 0x218>, 3451 <0 0x088e9600 0 0x200>, 3452 <0 0x088e9800 0 0x200>, 3453 <0 0x088e9a00 0 0x100>; 3454 #clock-cells = <0>; 3455 #phy-cells = <0>; 3456 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3457 clock-names = "pipe0"; 3458 clock-output-names = "usb3_phy_pipe_clk_src"; 3459 }; 3460 }; 3461 3462 usb_2_qmpphy: phy@88eb000 { 3463 compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 3464 reg = <0 0x088eb000 0 0x200>; 3465 status = "disabled"; 3466 #address-cells = <2>; 3467 #size-cells = <2>; 3468 ranges; 3469 3470 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3471 <&rpmhcc RPMH_CXO_CLK>, 3472 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3473 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3474 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3475 3476 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3477 <&gcc GCC_USB3_PHY_SEC_BCR>; 3478 reset-names = "phy", "common"; 3479 3480 usb_2_ssphy: phy@88eb200 { 3481 reg = <0 0x088eb200 0 0x200>, 3482 <0 0x088eb400 0 0x200>, 3483 <0 0x088eb800 0 0x800>, 3484 <0 0x088eb600 0 0x200>; 3485 #clock-cells = <0>; 3486 #phy-cells = <0>; 3487 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3488 clock-names = "pipe0"; 3489 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3490 }; 3491 }; 3492 3493 sdhc_2: mmc@8804000 { 3494 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3495 reg = <0 0x08804000 0 0x1000>; 3496 3497 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3499 interrupt-names = "hc_irq", "pwr_irq"; 3500 3501 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3502 <&gcc GCC_SDCC2_APPS_CLK>, 3503 <&rpmhcc RPMH_CXO_CLK>; 3504 clock-names = "iface", "core", "xo"; 3505 iommus = <&apps_smmu 0x6a0 0x0>; 3506 qcom,dll-config = <0x0007642c>; 3507 qcom,ddr-config = <0x80040868>; 3508 power-domains = <&rpmhpd 0>; 3509 operating-points-v2 = <&sdhc2_opp_table>; 3510 3511 status = "disabled"; 3512 3513 sdhc2_opp_table: opp-table { 3514 compatible = "operating-points-v2"; 3515 3516 opp-19200000 { 3517 opp-hz = /bits/ 64 <19200000>; 3518 required-opps = <&rpmhpd_opp_min_svs>; 3519 }; 3520 3521 opp-50000000 { 3522 opp-hz = /bits/ 64 <50000000>; 3523 required-opps = <&rpmhpd_opp_low_svs>; 3524 }; 3525 3526 opp-100000000 { 3527 opp-hz = /bits/ 64 <100000000>; 3528 required-opps = <&rpmhpd_opp_svs>; 3529 }; 3530 3531 opp-202000000 { 3532 opp-hz = /bits/ 64 <202000000>; 3533 required-opps = <&rpmhpd_opp_svs_l1>; 3534 }; 3535 }; 3536 }; 3537 3538 dc_noc: interconnect@9160000 { 3539 compatible = "qcom,sm8150-dc-noc"; 3540 reg = <0 0x09160000 0 0x3200>; 3541 #interconnect-cells = <1>; 3542 qcom,bcm-voters = <&apps_bcm_voter>; 3543 }; 3544 3545 gem_noc: interconnect@9680000 { 3546 compatible = "qcom,sm8150-gem-noc"; 3547 reg = <0 0x09680000 0 0x3e200>; 3548 #interconnect-cells = <1>; 3549 qcom,bcm-voters = <&apps_bcm_voter>; 3550 }; 3551 3552 usb_1: usb@a6f8800 { 3553 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3554 reg = <0 0x0a6f8800 0 0x400>; 3555 status = "disabled"; 3556 #address-cells = <2>; 3557 #size-cells = <2>; 3558 ranges; 3559 dma-ranges; 3560 3561 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3562 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3563 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3564 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3565 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3566 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3567 clock-names = "cfg_noc", 3568 "core", 3569 "iface", 3570 "sleep", 3571 "mock_utmi", 3572 "xo"; 3573 3574 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3575 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3576 assigned-clock-rates = <19200000>, <200000000>; 3577 3578 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3579 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3580 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3581 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3582 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3583 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3584 3585 power-domains = <&gcc USB30_PRIM_GDSC>; 3586 3587 resets = <&gcc GCC_USB30_PRIM_BCR>; 3588 3589 usb_1_dwc3: usb@a600000 { 3590 compatible = "snps,dwc3"; 3591 reg = <0 0x0a600000 0 0xcd00>; 3592 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3593 iommus = <&apps_smmu 0x140 0>; 3594 snps,dis_u2_susphy_quirk; 3595 snps,dis_enblslpm_quirk; 3596 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3597 phy-names = "usb2-phy", "usb3-phy"; 3598 }; 3599 }; 3600 3601 usb_2: usb@a8f8800 { 3602 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3603 reg = <0 0x0a8f8800 0 0x400>; 3604 status = "disabled"; 3605 #address-cells = <2>; 3606 #size-cells = <2>; 3607 ranges; 3608 dma-ranges; 3609 3610 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3611 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3612 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3613 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3614 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3615 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3616 clock-names = "cfg_noc", 3617 "core", 3618 "iface", 3619 "sleep", 3620 "mock_utmi", 3621 "xo"; 3622 3623 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3624 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3625 assigned-clock-rates = <19200000>, <200000000>; 3626 3627 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 3629 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3630 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 3631 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3632 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3633 3634 power-domains = <&gcc USB30_SEC_GDSC>; 3635 3636 resets = <&gcc GCC_USB30_SEC_BCR>; 3637 3638 usb_2_dwc3: usb@a800000 { 3639 compatible = "snps,dwc3"; 3640 reg = <0 0x0a800000 0 0xcd00>; 3641 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3642 iommus = <&apps_smmu 0x160 0>; 3643 snps,dis_u2_susphy_quirk; 3644 snps,dis_enblslpm_quirk; 3645 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3646 phy-names = "usb2-phy", "usb3-phy"; 3647 }; 3648 }; 3649 3650 camnoc_virt: interconnect@ac00000 { 3651 compatible = "qcom,sm8150-camnoc-virt"; 3652 reg = <0 0x0ac00000 0 0x1000>; 3653 #interconnect-cells = <1>; 3654 qcom,bcm-voters = <&apps_bcm_voter>; 3655 }; 3656 3657 mdss: display-subsystem@ae00000 { 3658 compatible = "qcom,sm8150-mdss"; 3659 reg = <0 0x0ae00000 0 0x1000>; 3660 reg-names = "mdss"; 3661 3662 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 3663 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 3664 interconnect-names = "mdp0-mem", "mdp1-mem"; 3665 3666 power-domains = <&dispcc MDSS_GDSC>; 3667 3668 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3669 <&gcc GCC_DISP_HF_AXI_CLK>, 3670 <&gcc GCC_DISP_SF_AXI_CLK>, 3671 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3672 clock-names = "iface", "bus", "nrt_bus", "core"; 3673 3674 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3675 interrupt-controller; 3676 #interrupt-cells = <1>; 3677 3678 iommus = <&apps_smmu 0x800 0x420>; 3679 3680 status = "disabled"; 3681 3682 #address-cells = <2>; 3683 #size-cells = <2>; 3684 ranges; 3685 3686 mdss_mdp: display-controller@ae01000 { 3687 compatible = "qcom,sm8150-dpu"; 3688 reg = <0 0x0ae01000 0 0x8f000>, 3689 <0 0x0aeb0000 0 0x2008>; 3690 reg-names = "mdp", "vbif"; 3691 3692 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3693 <&gcc GCC_DISP_HF_AXI_CLK>, 3694 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3695 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3696 clock-names = "iface", "bus", "core", "vsync"; 3697 3698 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3699 assigned-clock-rates = <19200000>; 3700 3701 operating-points-v2 = <&mdp_opp_table>; 3702 power-domains = <&rpmhpd SM8150_MMCX>; 3703 3704 interrupt-parent = <&mdss>; 3705 interrupts = <0>; 3706 3707 ports { 3708 #address-cells = <1>; 3709 #size-cells = <0>; 3710 3711 port@0 { 3712 reg = <0>; 3713 dpu_intf1_out: endpoint { 3714 remote-endpoint = <&mdss_dsi0_in>; 3715 }; 3716 }; 3717 3718 port@1 { 3719 reg = <1>; 3720 dpu_intf2_out: endpoint { 3721 remote-endpoint = <&mdss_dsi1_in>; 3722 }; 3723 }; 3724 }; 3725 3726 mdp_opp_table: opp-table { 3727 compatible = "operating-points-v2"; 3728 3729 opp-171428571 { 3730 opp-hz = /bits/ 64 <171428571>; 3731 required-opps = <&rpmhpd_opp_low_svs>; 3732 }; 3733 3734 opp-300000000 { 3735 opp-hz = /bits/ 64 <300000000>; 3736 required-opps = <&rpmhpd_opp_svs>; 3737 }; 3738 3739 opp-345000000 { 3740 opp-hz = /bits/ 64 <345000000>; 3741 required-opps = <&rpmhpd_opp_svs_l1>; 3742 }; 3743 3744 opp-460000000 { 3745 opp-hz = /bits/ 64 <460000000>; 3746 required-opps = <&rpmhpd_opp_nom>; 3747 }; 3748 }; 3749 }; 3750 3751 mdss_dsi0: dsi@ae94000 { 3752 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3753 reg = <0 0x0ae94000 0 0x400>; 3754 reg-names = "dsi_ctrl"; 3755 3756 interrupt-parent = <&mdss>; 3757 interrupts = <4>; 3758 3759 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3760 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3761 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3762 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3763 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3764 <&gcc GCC_DISP_HF_AXI_CLK>; 3765 clock-names = "byte", 3766 "byte_intf", 3767 "pixel", 3768 "core", 3769 "iface", 3770 "bus"; 3771 3772 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3773 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3774 assigned-clock-parents = <&mdss_dsi0_phy 0>, 3775 <&mdss_dsi0_phy 1>; 3776 3777 operating-points-v2 = <&dsi_opp_table>; 3778 power-domains = <&rpmhpd SM8150_MMCX>; 3779 3780 phys = <&mdss_dsi0_phy>; 3781 3782 status = "disabled"; 3783 3784 #address-cells = <1>; 3785 #size-cells = <0>; 3786 3787 ports { 3788 #address-cells = <1>; 3789 #size-cells = <0>; 3790 3791 port@0 { 3792 reg = <0>; 3793 mdss_dsi0_in: endpoint { 3794 remote-endpoint = <&dpu_intf1_out>; 3795 }; 3796 }; 3797 3798 port@1 { 3799 reg = <1>; 3800 mdss_dsi0_out: endpoint { 3801 }; 3802 }; 3803 }; 3804 3805 dsi_opp_table: opp-table { 3806 compatible = "operating-points-v2"; 3807 3808 opp-187500000 { 3809 opp-hz = /bits/ 64 <187500000>; 3810 required-opps = <&rpmhpd_opp_low_svs>; 3811 }; 3812 3813 opp-300000000 { 3814 opp-hz = /bits/ 64 <300000000>; 3815 required-opps = <&rpmhpd_opp_svs>; 3816 }; 3817 3818 opp-358000000 { 3819 opp-hz = /bits/ 64 <358000000>; 3820 required-opps = <&rpmhpd_opp_svs_l1>; 3821 }; 3822 }; 3823 }; 3824 3825 mdss_dsi0_phy: phy@ae94400 { 3826 compatible = "qcom,dsi-phy-7nm"; 3827 reg = <0 0x0ae94400 0 0x200>, 3828 <0 0x0ae94600 0 0x280>, 3829 <0 0x0ae94900 0 0x260>; 3830 reg-names = "dsi_phy", 3831 "dsi_phy_lane", 3832 "dsi_pll"; 3833 3834 #clock-cells = <1>; 3835 #phy-cells = <0>; 3836 3837 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3838 <&rpmhcc RPMH_CXO_CLK>; 3839 clock-names = "iface", "ref"; 3840 3841 status = "disabled"; 3842 }; 3843 3844 mdss_dsi1: dsi@ae96000 { 3845 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3846 reg = <0 0x0ae96000 0 0x400>; 3847 reg-names = "dsi_ctrl"; 3848 3849 interrupt-parent = <&mdss>; 3850 interrupts = <5>; 3851 3852 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3853 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3854 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3855 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3856 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3857 <&gcc GCC_DISP_HF_AXI_CLK>; 3858 clock-names = "byte", 3859 "byte_intf", 3860 "pixel", 3861 "core", 3862 "iface", 3863 "bus"; 3864 3865 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3866 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3867 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3868 <&mdss_dsi1_phy 1>; 3869 3870 operating-points-v2 = <&dsi_opp_table>; 3871 power-domains = <&rpmhpd SM8150_MMCX>; 3872 3873 phys = <&mdss_dsi1_phy>; 3874 3875 status = "disabled"; 3876 3877 #address-cells = <1>; 3878 #size-cells = <0>; 3879 3880 ports { 3881 #address-cells = <1>; 3882 #size-cells = <0>; 3883 3884 port@0 { 3885 reg = <0>; 3886 mdss_dsi1_in: endpoint { 3887 remote-endpoint = <&dpu_intf2_out>; 3888 }; 3889 }; 3890 3891 port@1 { 3892 reg = <1>; 3893 mdss_dsi1_out: endpoint { 3894 }; 3895 }; 3896 }; 3897 }; 3898 3899 mdss_dsi1_phy: phy@ae96400 { 3900 compatible = "qcom,dsi-phy-7nm"; 3901 reg = <0 0x0ae96400 0 0x200>, 3902 <0 0x0ae96600 0 0x280>, 3903 <0 0x0ae96900 0 0x260>; 3904 reg-names = "dsi_phy", 3905 "dsi_phy_lane", 3906 "dsi_pll"; 3907 3908 #clock-cells = <1>; 3909 #phy-cells = <0>; 3910 3911 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3912 <&rpmhcc RPMH_CXO_CLK>; 3913 clock-names = "iface", "ref"; 3914 3915 status = "disabled"; 3916 }; 3917 }; 3918 3919 dispcc: clock-controller@af00000 { 3920 compatible = "qcom,sm8150-dispcc"; 3921 reg = <0 0x0af00000 0 0x10000>; 3922 clocks = <&rpmhcc RPMH_CXO_CLK>, 3923 <&mdss_dsi0_phy 0>, 3924 <&mdss_dsi0_phy 1>, 3925 <&mdss_dsi1_phy 0>, 3926 <&mdss_dsi1_phy 1>, 3927 <0>, 3928 <0>; 3929 clock-names = "bi_tcxo", 3930 "dsi0_phy_pll_out_byteclk", 3931 "dsi0_phy_pll_out_dsiclk", 3932 "dsi1_phy_pll_out_byteclk", 3933 "dsi1_phy_pll_out_dsiclk", 3934 "dp_phy_pll_link_clk", 3935 "dp_phy_pll_vco_div_clk"; 3936 power-domains = <&rpmhpd SM8150_MMCX>; 3937 #clock-cells = <1>; 3938 #reset-cells = <1>; 3939 #power-domain-cells = <1>; 3940 }; 3941 3942 pdc: interrupt-controller@b220000 { 3943 compatible = "qcom,sm8150-pdc", "qcom,pdc"; 3944 reg = <0 0x0b220000 0 0x400>; 3945 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3946 <125 63 1>; 3947 #interrupt-cells = <2>; 3948 interrupt-parent = <&intc>; 3949 interrupt-controller; 3950 }; 3951 3952 aoss_qmp: power-management@c300000 { 3953 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 3954 reg = <0x0 0x0c300000 0x0 0x400>; 3955 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3956 mboxes = <&apss_shared 0>; 3957 3958 #clock-cells = <0>; 3959 }; 3960 3961 sram@c3f0000 { 3962 compatible = "qcom,rpmh-stats"; 3963 reg = <0 0x0c3f0000 0 0x400>; 3964 }; 3965 3966 tsens0: thermal-sensor@c263000 { 3967 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3968 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3969 <0 0x0c222000 0 0x1ff>; /* SROT */ 3970 #qcom,sensors = <16>; 3971 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3972 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3973 interrupt-names = "uplow", "critical"; 3974 #thermal-sensor-cells = <1>; 3975 }; 3976 3977 tsens1: thermal-sensor@c265000 { 3978 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3979 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3980 <0 0x0c223000 0 0x1ff>; /* SROT */ 3981 #qcom,sensors = <8>; 3982 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3983 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3984 interrupt-names = "uplow", "critical"; 3985 #thermal-sensor-cells = <1>; 3986 }; 3987 3988 spmi_bus: spmi@c440000 { 3989 compatible = "qcom,spmi-pmic-arb"; 3990 reg = <0x0 0x0c440000 0x0 0x0001100>, 3991 <0x0 0x0c600000 0x0 0x2000000>, 3992 <0x0 0x0e600000 0x0 0x0100000>, 3993 <0x0 0x0e700000 0x0 0x00a0000>, 3994 <0x0 0x0c40a000 0x0 0x0026000>; 3995 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3996 interrupt-names = "periph_irq"; 3997 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3998 qcom,ee = <0>; 3999 qcom,channel = <0>; 4000 #address-cells = <2>; 4001 #size-cells = <0>; 4002 interrupt-controller; 4003 #interrupt-cells = <4>; 4004 }; 4005 4006 apps_smmu: iommu@15000000 { 4007 compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4008 reg = <0 0x15000000 0 0x100000>; 4009 #iommu-cells = <2>; 4010 #global-interrupts = <1>; 4011 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4012 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4013 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4014 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4015 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4016 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4017 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4018 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4019 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4020 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4021 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4022 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4023 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4024 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4025 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4026 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4027 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4028 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4029 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4030 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4031 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4032 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4033 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4034 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4035 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4036 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4037 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4038 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4039 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4040 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4041 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4042 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4043 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4044 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4045 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4046 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4047 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4048 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4049 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4050 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4051 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4052 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4053 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4054 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4055 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4056 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4057 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4058 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4059 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4060 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4061 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4062 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4063 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4064 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4065 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4066 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4067 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4068 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4069 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4070 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4071 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4072 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4073 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4074 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4075 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4076 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4077 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4079 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4080 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4083 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4084 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 4092 }; 4093 4094 remoteproc_adsp: remoteproc@17300000 { 4095 compatible = "qcom,sm8150-adsp-pas"; 4096 reg = <0x0 0x17300000 0x0 0x4040>; 4097 4098 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 4099 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4100 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4101 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4102 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 4103 interrupt-names = "wdog", "fatal", "ready", 4104 "handover", "stop-ack"; 4105 4106 clocks = <&rpmhcc RPMH_CXO_CLK>; 4107 clock-names = "xo"; 4108 4109 power-domains = <&rpmhpd SM8150_CX>; 4110 4111 memory-region = <&adsp_mem>; 4112 4113 qcom,qmp = <&aoss_qmp>; 4114 4115 qcom,smem-states = <&adsp_smp2p_out 0>; 4116 qcom,smem-state-names = "stop"; 4117 4118 status = "disabled"; 4119 4120 glink-edge { 4121 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 4122 label = "lpass"; 4123 qcom,remote-pid = <2>; 4124 mboxes = <&apss_shared 8>; 4125 4126 fastrpc { 4127 compatible = "qcom,fastrpc"; 4128 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4129 label = "adsp"; 4130 qcom,non-secure-domain; 4131 #address-cells = <1>; 4132 #size-cells = <0>; 4133 4134 compute-cb@3 { 4135 compatible = "qcom,fastrpc-compute-cb"; 4136 reg = <3>; 4137 iommus = <&apps_smmu 0x1b23 0x0>; 4138 }; 4139 4140 compute-cb@4 { 4141 compatible = "qcom,fastrpc-compute-cb"; 4142 reg = <4>; 4143 iommus = <&apps_smmu 0x1b24 0x0>; 4144 }; 4145 4146 compute-cb@5 { 4147 compatible = "qcom,fastrpc-compute-cb"; 4148 reg = <5>; 4149 iommus = <&apps_smmu 0x1b25 0x0>; 4150 }; 4151 }; 4152 }; 4153 }; 4154 4155 intc: interrupt-controller@17a00000 { 4156 compatible = "arm,gic-v3"; 4157 interrupt-controller; 4158 #interrupt-cells = <3>; 4159 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4160 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4161 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4162 }; 4163 4164 apss_shared: mailbox@17c00000 { 4165 compatible = "qcom,sm8150-apss-shared", 4166 "qcom,sdm845-apss-shared"; 4167 reg = <0x0 0x17c00000 0x0 0x1000>; 4168 #mbox-cells = <1>; 4169 }; 4170 4171 watchdog@17c10000 { 4172 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 4173 reg = <0 0x17c10000 0 0x1000>; 4174 clocks = <&sleep_clk>; 4175 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4176 }; 4177 4178 timer@17c20000 { 4179 #address-cells = <1>; 4180 #size-cells = <1>; 4181 ranges = <0 0 0 0x20000000>; 4182 compatible = "arm,armv7-timer-mem"; 4183 reg = <0x0 0x17c20000 0x0 0x1000>; 4184 clock-frequency = <19200000>; 4185 4186 frame@17c21000 { 4187 frame-number = <0>; 4188 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4189 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4190 reg = <0x17c21000 0x1000>, 4191 <0x17c22000 0x1000>; 4192 }; 4193 4194 frame@17c23000 { 4195 frame-number = <1>; 4196 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4197 reg = <0x17c23000 0x1000>; 4198 status = "disabled"; 4199 }; 4200 4201 frame@17c25000 { 4202 frame-number = <2>; 4203 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4204 reg = <0x17c25000 0x1000>; 4205 status = "disabled"; 4206 }; 4207 4208 frame@17c27000 { 4209 frame-number = <3>; 4210 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4211 reg = <0x17c26000 0x1000>; 4212 status = "disabled"; 4213 }; 4214 4215 frame@17c29000 { 4216 frame-number = <4>; 4217 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4218 reg = <0x17c29000 0x1000>; 4219 status = "disabled"; 4220 }; 4221 4222 frame@17c2b000 { 4223 frame-number = <5>; 4224 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4225 reg = <0x17c2b000 0x1000>; 4226 status = "disabled"; 4227 }; 4228 4229 frame@17c2d000 { 4230 frame-number = <6>; 4231 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4232 reg = <0x17c2d000 0x1000>; 4233 status = "disabled"; 4234 }; 4235 }; 4236 4237 apps_rsc: rsc@18200000 { 4238 label = "apps_rsc"; 4239 compatible = "qcom,rpmh-rsc"; 4240 reg = <0x0 0x18200000 0x0 0x10000>, 4241 <0x0 0x18210000 0x0 0x10000>, 4242 <0x0 0x18220000 0x0 0x10000>; 4243 reg-names = "drv-0", "drv-1", "drv-2"; 4244 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4245 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4246 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4247 qcom,tcs-offset = <0xd00>; 4248 qcom,drv-id = <2>; 4249 qcom,tcs-config = <ACTIVE_TCS 2>, 4250 <SLEEP_TCS 3>, 4251 <WAKE_TCS 3>, 4252 <CONTROL_TCS 1>; 4253 power-domains = <&CLUSTER_PD>; 4254 4255 rpmhcc: clock-controller { 4256 compatible = "qcom,sm8150-rpmh-clk"; 4257 #clock-cells = <1>; 4258 clock-names = "xo"; 4259 clocks = <&xo_board>; 4260 }; 4261 4262 rpmhpd: power-controller { 4263 compatible = "qcom,sm8150-rpmhpd"; 4264 #power-domain-cells = <1>; 4265 operating-points-v2 = <&rpmhpd_opp_table>; 4266 4267 rpmhpd_opp_table: opp-table { 4268 compatible = "operating-points-v2"; 4269 4270 rpmhpd_opp_ret: opp1 { 4271 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4272 }; 4273 4274 rpmhpd_opp_min_svs: opp2 { 4275 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4276 }; 4277 4278 rpmhpd_opp_low_svs: opp3 { 4279 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4280 }; 4281 4282 rpmhpd_opp_svs: opp4 { 4283 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4284 }; 4285 4286 rpmhpd_opp_svs_l1: opp5 { 4287 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4288 }; 4289 4290 rpmhpd_opp_svs_l2: opp6 { 4291 opp-level = <224>; 4292 }; 4293 4294 rpmhpd_opp_nom: opp7 { 4295 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4296 }; 4297 4298 rpmhpd_opp_nom_l1: opp8 { 4299 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4300 }; 4301 4302 rpmhpd_opp_nom_l2: opp9 { 4303 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4304 }; 4305 4306 rpmhpd_opp_turbo: opp10 { 4307 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4308 }; 4309 4310 rpmhpd_opp_turbo_l1: opp11 { 4311 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4312 }; 4313 }; 4314 }; 4315 4316 apps_bcm_voter: bcm-voter { 4317 compatible = "qcom,bcm-voter"; 4318 }; 4319 }; 4320 4321 osm_l3: interconnect@18321000 { 4322 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4323 reg = <0 0x18321000 0 0x1400>; 4324 4325 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4326 clock-names = "xo", "alternate"; 4327 4328 #interconnect-cells = <1>; 4329 }; 4330 4331 cpufreq_hw: cpufreq@18323000 { 4332 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw"; 4333 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 4334 <0 0x18327800 0 0x1400>; 4335 reg-names = "freq-domain0", "freq-domain1", 4336 "freq-domain2"; 4337 4338 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4339 clock-names = "xo", "alternate"; 4340 4341 #freq-domain-cells = <1>; 4342 #clock-cells = <1>; 4343 }; 4344 4345 lmh_cluster1: lmh@18350800 { 4346 compatible = "qcom,sm8150-lmh"; 4347 reg = <0 0x18350800 0 0x400>; 4348 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 4349 cpus = <&CPU4>; 4350 qcom,lmh-temp-arm-millicelsius = <60000>; 4351 qcom,lmh-temp-low-millicelsius = <84500>; 4352 qcom,lmh-temp-high-millicelsius = <85000>; 4353 interrupt-controller; 4354 #interrupt-cells = <1>; 4355 }; 4356 4357 lmh_cluster0: lmh@18358800 { 4358 compatible = "qcom,sm8150-lmh"; 4359 reg = <0 0x18358800 0 0x400>; 4360 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4361 cpus = <&CPU0>; 4362 qcom,lmh-temp-arm-millicelsius = <60000>; 4363 qcom,lmh-temp-low-millicelsius = <84500>; 4364 qcom,lmh-temp-high-millicelsius = <85000>; 4365 interrupt-controller; 4366 #interrupt-cells = <1>; 4367 }; 4368 4369 wifi: wifi@18800000 { 4370 compatible = "qcom,wcn3990-wifi"; 4371 reg = <0 0x18800000 0 0x800000>; 4372 reg-names = "membase"; 4373 memory-region = <&wlan_mem>; 4374 clock-names = "cxo_ref_clk_pin", "qdss"; 4375 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 4376 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4377 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4378 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4379 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4380 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4381 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4382 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4383 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4384 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4385 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4386 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4387 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4388 iommus = <&apps_smmu 0x0640 0x1>; 4389 status = "disabled"; 4390 }; 4391 }; 4392 4393 timer { 4394 compatible = "arm,armv8-timer"; 4395 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4396 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4397 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4398 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4399 }; 4400 4401 thermal-zones { 4402 cpu0-thermal { 4403 polling-delay-passive = <250>; 4404 polling-delay = <1000>; 4405 4406 thermal-sensors = <&tsens0 1>; 4407 4408 trips { 4409 cpu0_alert0: trip-point0 { 4410 temperature = <90000>; 4411 hysteresis = <2000>; 4412 type = "passive"; 4413 }; 4414 4415 cpu0_alert1: trip-point1 { 4416 temperature = <95000>; 4417 hysteresis = <2000>; 4418 type = "passive"; 4419 }; 4420 4421 cpu0_crit: cpu-crit { 4422 temperature = <110000>; 4423 hysteresis = <1000>; 4424 type = "critical"; 4425 }; 4426 }; 4427 4428 cooling-maps { 4429 map0 { 4430 trip = <&cpu0_alert0>; 4431 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4432 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4433 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4434 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4435 }; 4436 map1 { 4437 trip = <&cpu0_alert1>; 4438 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4439 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4440 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4441 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4442 }; 4443 }; 4444 }; 4445 4446 cpu1-thermal { 4447 polling-delay-passive = <250>; 4448 polling-delay = <1000>; 4449 4450 thermal-sensors = <&tsens0 2>; 4451 4452 trips { 4453 cpu1_alert0: trip-point0 { 4454 temperature = <90000>; 4455 hysteresis = <2000>; 4456 type = "passive"; 4457 }; 4458 4459 cpu1_alert1: trip-point1 { 4460 temperature = <95000>; 4461 hysteresis = <2000>; 4462 type = "passive"; 4463 }; 4464 4465 cpu1_crit: cpu-crit { 4466 temperature = <110000>; 4467 hysteresis = <1000>; 4468 type = "critical"; 4469 }; 4470 }; 4471 4472 cooling-maps { 4473 map0 { 4474 trip = <&cpu1_alert0>; 4475 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4476 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4477 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4478 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4479 }; 4480 map1 { 4481 trip = <&cpu1_alert1>; 4482 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4483 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4484 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4485 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4486 }; 4487 }; 4488 }; 4489 4490 cpu2-thermal { 4491 polling-delay-passive = <250>; 4492 polling-delay = <1000>; 4493 4494 thermal-sensors = <&tsens0 3>; 4495 4496 trips { 4497 cpu2_alert0: trip-point0 { 4498 temperature = <90000>; 4499 hysteresis = <2000>; 4500 type = "passive"; 4501 }; 4502 4503 cpu2_alert1: trip-point1 { 4504 temperature = <95000>; 4505 hysteresis = <2000>; 4506 type = "passive"; 4507 }; 4508 4509 cpu2_crit: cpu-crit { 4510 temperature = <110000>; 4511 hysteresis = <1000>; 4512 type = "critical"; 4513 }; 4514 }; 4515 4516 cooling-maps { 4517 map0 { 4518 trip = <&cpu2_alert0>; 4519 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4520 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4521 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4522 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4523 }; 4524 map1 { 4525 trip = <&cpu2_alert1>; 4526 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4527 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4528 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4529 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4530 }; 4531 }; 4532 }; 4533 4534 cpu3-thermal { 4535 polling-delay-passive = <250>; 4536 polling-delay = <1000>; 4537 4538 thermal-sensors = <&tsens0 4>; 4539 4540 trips { 4541 cpu3_alert0: trip-point0 { 4542 temperature = <90000>; 4543 hysteresis = <2000>; 4544 type = "passive"; 4545 }; 4546 4547 cpu3_alert1: trip-point1 { 4548 temperature = <95000>; 4549 hysteresis = <2000>; 4550 type = "passive"; 4551 }; 4552 4553 cpu3_crit: cpu-crit { 4554 temperature = <110000>; 4555 hysteresis = <1000>; 4556 type = "critical"; 4557 }; 4558 }; 4559 4560 cooling-maps { 4561 map0 { 4562 trip = <&cpu3_alert0>; 4563 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4564 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4565 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4566 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4567 }; 4568 map1 { 4569 trip = <&cpu3_alert1>; 4570 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4571 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4572 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4573 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4574 }; 4575 }; 4576 }; 4577 4578 cpu4-top-thermal { 4579 polling-delay-passive = <250>; 4580 polling-delay = <1000>; 4581 4582 thermal-sensors = <&tsens0 7>; 4583 4584 trips { 4585 cpu4_top_alert0: trip-point0 { 4586 temperature = <90000>; 4587 hysteresis = <2000>; 4588 type = "passive"; 4589 }; 4590 4591 cpu4_top_alert1: trip-point1 { 4592 temperature = <95000>; 4593 hysteresis = <2000>; 4594 type = "passive"; 4595 }; 4596 4597 cpu4_top_crit: cpu-crit { 4598 temperature = <110000>; 4599 hysteresis = <1000>; 4600 type = "critical"; 4601 }; 4602 }; 4603 4604 cooling-maps { 4605 map0 { 4606 trip = <&cpu4_top_alert0>; 4607 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4608 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4609 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4610 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4611 }; 4612 map1 { 4613 trip = <&cpu4_top_alert1>; 4614 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4615 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4616 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4617 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4618 }; 4619 }; 4620 }; 4621 4622 cpu5-top-thermal { 4623 polling-delay-passive = <250>; 4624 polling-delay = <1000>; 4625 4626 thermal-sensors = <&tsens0 8>; 4627 4628 trips { 4629 cpu5_top_alert0: trip-point0 { 4630 temperature = <90000>; 4631 hysteresis = <2000>; 4632 type = "passive"; 4633 }; 4634 4635 cpu5_top_alert1: trip-point1 { 4636 temperature = <95000>; 4637 hysteresis = <2000>; 4638 type = "passive"; 4639 }; 4640 4641 cpu5_top_crit: cpu-crit { 4642 temperature = <110000>; 4643 hysteresis = <1000>; 4644 type = "critical"; 4645 }; 4646 }; 4647 4648 cooling-maps { 4649 map0 { 4650 trip = <&cpu5_top_alert0>; 4651 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4652 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4653 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4654 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4655 }; 4656 map1 { 4657 trip = <&cpu5_top_alert1>; 4658 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4659 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4660 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4661 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4662 }; 4663 }; 4664 }; 4665 4666 cpu6-top-thermal { 4667 polling-delay-passive = <250>; 4668 polling-delay = <1000>; 4669 4670 thermal-sensors = <&tsens0 9>; 4671 4672 trips { 4673 cpu6_top_alert0: trip-point0 { 4674 temperature = <90000>; 4675 hysteresis = <2000>; 4676 type = "passive"; 4677 }; 4678 4679 cpu6_top_alert1: trip-point1 { 4680 temperature = <95000>; 4681 hysteresis = <2000>; 4682 type = "passive"; 4683 }; 4684 4685 cpu6_top_crit: cpu-crit { 4686 temperature = <110000>; 4687 hysteresis = <1000>; 4688 type = "critical"; 4689 }; 4690 }; 4691 4692 cooling-maps { 4693 map0 { 4694 trip = <&cpu6_top_alert0>; 4695 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4696 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4697 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4698 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4699 }; 4700 map1 { 4701 trip = <&cpu6_top_alert1>; 4702 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4703 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4704 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4705 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4706 }; 4707 }; 4708 }; 4709 4710 cpu7-top-thermal { 4711 polling-delay-passive = <250>; 4712 polling-delay = <1000>; 4713 4714 thermal-sensors = <&tsens0 10>; 4715 4716 trips { 4717 cpu7_top_alert0: trip-point0 { 4718 temperature = <90000>; 4719 hysteresis = <2000>; 4720 type = "passive"; 4721 }; 4722 4723 cpu7_top_alert1: trip-point1 { 4724 temperature = <95000>; 4725 hysteresis = <2000>; 4726 type = "passive"; 4727 }; 4728 4729 cpu7_top_crit: cpu-crit { 4730 temperature = <110000>; 4731 hysteresis = <1000>; 4732 type = "critical"; 4733 }; 4734 }; 4735 4736 cooling-maps { 4737 map0 { 4738 trip = <&cpu7_top_alert0>; 4739 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4740 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4741 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4742 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4743 }; 4744 map1 { 4745 trip = <&cpu7_top_alert1>; 4746 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4747 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4748 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4749 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4750 }; 4751 }; 4752 }; 4753 4754 cpu4-bottom-thermal { 4755 polling-delay-passive = <250>; 4756 polling-delay = <1000>; 4757 4758 thermal-sensors = <&tsens0 11>; 4759 4760 trips { 4761 cpu4_bottom_alert0: trip-point0 { 4762 temperature = <90000>; 4763 hysteresis = <2000>; 4764 type = "passive"; 4765 }; 4766 4767 cpu4_bottom_alert1: trip-point1 { 4768 temperature = <95000>; 4769 hysteresis = <2000>; 4770 type = "passive"; 4771 }; 4772 4773 cpu4_bottom_crit: cpu-crit { 4774 temperature = <110000>; 4775 hysteresis = <1000>; 4776 type = "critical"; 4777 }; 4778 }; 4779 4780 cooling-maps { 4781 map0 { 4782 trip = <&cpu4_bottom_alert0>; 4783 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4784 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4785 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4786 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4787 }; 4788 map1 { 4789 trip = <&cpu4_bottom_alert1>; 4790 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4791 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4792 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4793 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4794 }; 4795 }; 4796 }; 4797 4798 cpu5-bottom-thermal { 4799 polling-delay-passive = <250>; 4800 polling-delay = <1000>; 4801 4802 thermal-sensors = <&tsens0 12>; 4803 4804 trips { 4805 cpu5_bottom_alert0: trip-point0 { 4806 temperature = <90000>; 4807 hysteresis = <2000>; 4808 type = "passive"; 4809 }; 4810 4811 cpu5_bottom_alert1: trip-point1 { 4812 temperature = <95000>; 4813 hysteresis = <2000>; 4814 type = "passive"; 4815 }; 4816 4817 cpu5_bottom_crit: cpu-crit { 4818 temperature = <110000>; 4819 hysteresis = <1000>; 4820 type = "critical"; 4821 }; 4822 }; 4823 4824 cooling-maps { 4825 map0 { 4826 trip = <&cpu5_bottom_alert0>; 4827 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4828 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4829 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4830 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4831 }; 4832 map1 { 4833 trip = <&cpu5_bottom_alert1>; 4834 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4835 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4836 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4837 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4838 }; 4839 }; 4840 }; 4841 4842 cpu6-bottom-thermal { 4843 polling-delay-passive = <250>; 4844 polling-delay = <1000>; 4845 4846 thermal-sensors = <&tsens0 13>; 4847 4848 trips { 4849 cpu6_bottom_alert0: trip-point0 { 4850 temperature = <90000>; 4851 hysteresis = <2000>; 4852 type = "passive"; 4853 }; 4854 4855 cpu6_bottom_alert1: trip-point1 { 4856 temperature = <95000>; 4857 hysteresis = <2000>; 4858 type = "passive"; 4859 }; 4860 4861 cpu6_bottom_crit: cpu-crit { 4862 temperature = <110000>; 4863 hysteresis = <1000>; 4864 type = "critical"; 4865 }; 4866 }; 4867 4868 cooling-maps { 4869 map0 { 4870 trip = <&cpu6_bottom_alert0>; 4871 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4872 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4873 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4874 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4875 }; 4876 map1 { 4877 trip = <&cpu6_bottom_alert1>; 4878 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4879 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4880 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4881 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4882 }; 4883 }; 4884 }; 4885 4886 cpu7-bottom-thermal { 4887 polling-delay-passive = <250>; 4888 polling-delay = <1000>; 4889 4890 thermal-sensors = <&tsens0 14>; 4891 4892 trips { 4893 cpu7_bottom_alert0: trip-point0 { 4894 temperature = <90000>; 4895 hysteresis = <2000>; 4896 type = "passive"; 4897 }; 4898 4899 cpu7_bottom_alert1: trip-point1 { 4900 temperature = <95000>; 4901 hysteresis = <2000>; 4902 type = "passive"; 4903 }; 4904 4905 cpu7_bottom_crit: cpu-crit { 4906 temperature = <110000>; 4907 hysteresis = <1000>; 4908 type = "critical"; 4909 }; 4910 }; 4911 4912 cooling-maps { 4913 map0 { 4914 trip = <&cpu7_bottom_alert0>; 4915 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4916 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4917 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4918 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4919 }; 4920 map1 { 4921 trip = <&cpu7_bottom_alert1>; 4922 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4923 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4924 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4925 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4926 }; 4927 }; 4928 }; 4929 4930 aoss0-thermal { 4931 polling-delay-passive = <250>; 4932 polling-delay = <1000>; 4933 4934 thermal-sensors = <&tsens0 0>; 4935 4936 trips { 4937 aoss0_alert0: trip-point0 { 4938 temperature = <90000>; 4939 hysteresis = <2000>; 4940 type = "hot"; 4941 }; 4942 }; 4943 }; 4944 4945 cluster0-thermal { 4946 polling-delay-passive = <250>; 4947 polling-delay = <1000>; 4948 4949 thermal-sensors = <&tsens0 5>; 4950 4951 trips { 4952 cluster0_alert0: trip-point0 { 4953 temperature = <90000>; 4954 hysteresis = <2000>; 4955 type = "hot"; 4956 }; 4957 cluster0_crit: cluster0_crit { 4958 temperature = <110000>; 4959 hysteresis = <2000>; 4960 type = "critical"; 4961 }; 4962 }; 4963 }; 4964 4965 cluster1-thermal { 4966 polling-delay-passive = <250>; 4967 polling-delay = <1000>; 4968 4969 thermal-sensors = <&tsens0 6>; 4970 4971 trips { 4972 cluster1_alert0: trip-point0 { 4973 temperature = <90000>; 4974 hysteresis = <2000>; 4975 type = "hot"; 4976 }; 4977 cluster1_crit: cluster1_crit { 4978 temperature = <110000>; 4979 hysteresis = <2000>; 4980 type = "critical"; 4981 }; 4982 }; 4983 }; 4984 4985 gpu-top-thermal { 4986 polling-delay-passive = <250>; 4987 polling-delay = <1000>; 4988 4989 thermal-sensors = <&tsens0 15>; 4990 4991 trips { 4992 gpu1_alert0: trip-point0 { 4993 temperature = <90000>; 4994 hysteresis = <2000>; 4995 type = "hot"; 4996 }; 4997 }; 4998 }; 4999 5000 aoss1-thermal { 5001 polling-delay-passive = <250>; 5002 polling-delay = <1000>; 5003 5004 thermal-sensors = <&tsens1 0>; 5005 5006 trips { 5007 aoss1_alert0: trip-point0 { 5008 temperature = <90000>; 5009 hysteresis = <2000>; 5010 type = "hot"; 5011 }; 5012 }; 5013 }; 5014 5015 wlan-thermal { 5016 polling-delay-passive = <250>; 5017 polling-delay = <1000>; 5018 5019 thermal-sensors = <&tsens1 1>; 5020 5021 trips { 5022 wlan_alert0: trip-point0 { 5023 temperature = <90000>; 5024 hysteresis = <2000>; 5025 type = "hot"; 5026 }; 5027 }; 5028 }; 5029 5030 video-thermal { 5031 polling-delay-passive = <250>; 5032 polling-delay = <1000>; 5033 5034 thermal-sensors = <&tsens1 2>; 5035 5036 trips { 5037 video_alert0: trip-point0 { 5038 temperature = <90000>; 5039 hysteresis = <2000>; 5040 type = "hot"; 5041 }; 5042 }; 5043 }; 5044 5045 mem-thermal { 5046 polling-delay-passive = <250>; 5047 polling-delay = <1000>; 5048 5049 thermal-sensors = <&tsens1 3>; 5050 5051 trips { 5052 mem_alert0: trip-point0 { 5053 temperature = <90000>; 5054 hysteresis = <2000>; 5055 type = "hot"; 5056 }; 5057 }; 5058 }; 5059 5060 q6-hvx-thermal { 5061 polling-delay-passive = <250>; 5062 polling-delay = <1000>; 5063 5064 thermal-sensors = <&tsens1 4>; 5065 5066 trips { 5067 q6_hvx_alert0: trip-point0 { 5068 temperature = <90000>; 5069 hysteresis = <2000>; 5070 type = "hot"; 5071 }; 5072 }; 5073 }; 5074 5075 camera-thermal { 5076 polling-delay-passive = <250>; 5077 polling-delay = <1000>; 5078 5079 thermal-sensors = <&tsens1 5>; 5080 5081 trips { 5082 camera_alert0: trip-point0 { 5083 temperature = <90000>; 5084 hysteresis = <2000>; 5085 type = "hot"; 5086 }; 5087 }; 5088 }; 5089 5090 compute-thermal { 5091 polling-delay-passive = <250>; 5092 polling-delay = <1000>; 5093 5094 thermal-sensors = <&tsens1 6>; 5095 5096 trips { 5097 compute_alert0: trip-point0 { 5098 temperature = <90000>; 5099 hysteresis = <2000>; 5100 type = "hot"; 5101 }; 5102 }; 5103 }; 5104 5105 modem-thermal { 5106 polling-delay-passive = <250>; 5107 polling-delay = <1000>; 5108 5109 thermal-sensors = <&tsens1 7>; 5110 5111 trips { 5112 modem_alert0: trip-point0 { 5113 temperature = <90000>; 5114 hysteresis = <2000>; 5115 type = "hot"; 5116 }; 5117 }; 5118 }; 5119 5120 npu-thermal { 5121 polling-delay-passive = <250>; 5122 polling-delay = <1000>; 5123 5124 thermal-sensors = <&tsens1 8>; 5125 5126 trips { 5127 npu_alert0: trip-point0 { 5128 temperature = <90000>; 5129 hysteresis = <2000>; 5130 type = "hot"; 5131 }; 5132 }; 5133 }; 5134 5135 modem-vec-thermal { 5136 polling-delay-passive = <250>; 5137 polling-delay = <1000>; 5138 5139 thermal-sensors = <&tsens1 9>; 5140 5141 trips { 5142 modem_vec_alert0: trip-point0 { 5143 temperature = <90000>; 5144 hysteresis = <2000>; 5145 type = "hot"; 5146 }; 5147 }; 5148 }; 5149 5150 modem-scl-thermal { 5151 polling-delay-passive = <250>; 5152 polling-delay = <1000>; 5153 5154 thermal-sensors = <&tsens1 10>; 5155 5156 trips { 5157 modem_scl_alert0: trip-point0 { 5158 temperature = <90000>; 5159 hysteresis = <2000>; 5160 type = "hot"; 5161 }; 5162 }; 5163 }; 5164 5165 gpu-bottom-thermal { 5166 polling-delay-passive = <250>; 5167 polling-delay = <1000>; 5168 5169 thermal-sensors = <&tsens1 11>; 5170 5171 trips { 5172 gpu2_alert0: trip-point0 { 5173 temperature = <90000>; 5174 hysteresis = <2000>; 5175 type = "hot"; 5176 }; 5177 }; 5178 }; 5179 }; 5180}; 5181