1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/dma/qcom-gpi.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,dispcc-sm8150.h> 13#include <dt-bindings/clock/qcom,gcc-sm8150.h> 14#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sm8150.h> 17#include <dt-bindings/thermal/thermal.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 chosen { }; 26 27 clocks { 28 xo_board: xo-board { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <38400000>; 32 clock-output-names = "xo_board"; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32764>; 39 clock-output-names = "sleep_clk"; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 CPU0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "qcom,kryo485"; 50 reg = <0x0 0x0>; 51 clocks = <&cpufreq_hw 0>; 52 enable-method = "psci"; 53 capacity-dmips-mhz = <488>; 54 dynamic-power-coefficient = <232>; 55 next-level-cache = <&L2_0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 operating-points-v2 = <&cpu0_opp_table>; 58 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 59 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 60 power-domains = <&CPU_PD0>; 61 power-domain-names = "psci"; 62 #cooling-cells = <2>; 63 L2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 cache-unified; 67 next-level-cache = <&L3_0>; 68 L3_0: l3-cache { 69 compatible = "cache"; 70 cache-level = <3>; 71 cache-unified; 72 }; 73 }; 74 }; 75 76 CPU1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "qcom,kryo485"; 79 reg = <0x0 0x100>; 80 clocks = <&cpufreq_hw 0>; 81 enable-method = "psci"; 82 capacity-dmips-mhz = <488>; 83 dynamic-power-coefficient = <232>; 84 next-level-cache = <&L2_100>; 85 qcom,freq-domain = <&cpufreq_hw 0>; 86 operating-points-v2 = <&cpu0_opp_table>; 87 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 88 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 89 power-domains = <&CPU_PD1>; 90 power-domain-names = "psci"; 91 #cooling-cells = <2>; 92 L2_100: l2-cache { 93 compatible = "cache"; 94 cache-level = <2>; 95 cache-unified; 96 next-level-cache = <&L3_0>; 97 }; 98 }; 99 100 CPU2: cpu@200 { 101 device_type = "cpu"; 102 compatible = "qcom,kryo485"; 103 reg = <0x0 0x200>; 104 clocks = <&cpufreq_hw 0>; 105 enable-method = "psci"; 106 capacity-dmips-mhz = <488>; 107 dynamic-power-coefficient = <232>; 108 next-level-cache = <&L2_200>; 109 qcom,freq-domain = <&cpufreq_hw 0>; 110 operating-points-v2 = <&cpu0_opp_table>; 111 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 112 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 113 power-domains = <&CPU_PD2>; 114 power-domain-names = "psci"; 115 #cooling-cells = <2>; 116 L2_200: l2-cache { 117 compatible = "cache"; 118 cache-level = <2>; 119 cache-unified; 120 next-level-cache = <&L3_0>; 121 }; 122 }; 123 124 CPU3: cpu@300 { 125 device_type = "cpu"; 126 compatible = "qcom,kryo485"; 127 reg = <0x0 0x300>; 128 clocks = <&cpufreq_hw 0>; 129 enable-method = "psci"; 130 capacity-dmips-mhz = <488>; 131 dynamic-power-coefficient = <232>; 132 next-level-cache = <&L2_300>; 133 qcom,freq-domain = <&cpufreq_hw 0>; 134 operating-points-v2 = <&cpu0_opp_table>; 135 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 136 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 137 power-domains = <&CPU_PD3>; 138 power-domain-names = "psci"; 139 #cooling-cells = <2>; 140 L2_300: l2-cache { 141 compatible = "cache"; 142 cache-level = <2>; 143 cache-unified; 144 next-level-cache = <&L3_0>; 145 }; 146 }; 147 148 CPU4: cpu@400 { 149 device_type = "cpu"; 150 compatible = "qcom,kryo485"; 151 reg = <0x0 0x400>; 152 clocks = <&cpufreq_hw 1>; 153 enable-method = "psci"; 154 capacity-dmips-mhz = <1024>; 155 dynamic-power-coefficient = <369>; 156 next-level-cache = <&L2_400>; 157 qcom,freq-domain = <&cpufreq_hw 1>; 158 operating-points-v2 = <&cpu4_opp_table>; 159 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 160 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 161 power-domains = <&CPU_PD4>; 162 power-domain-names = "psci"; 163 #cooling-cells = <2>; 164 L2_400: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&L3_0>; 169 }; 170 }; 171 172 CPU5: cpu@500 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo485"; 175 reg = <0x0 0x500>; 176 clocks = <&cpufreq_hw 1>; 177 enable-method = "psci"; 178 capacity-dmips-mhz = <1024>; 179 dynamic-power-coefficient = <369>; 180 next-level-cache = <&L2_500>; 181 qcom,freq-domain = <&cpufreq_hw 1>; 182 operating-points-v2 = <&cpu4_opp_table>; 183 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 184 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 185 power-domains = <&CPU_PD5>; 186 power-domain-names = "psci"; 187 #cooling-cells = <2>; 188 L2_500: l2-cache { 189 compatible = "cache"; 190 cache-level = <2>; 191 cache-unified; 192 next-level-cache = <&L3_0>; 193 }; 194 }; 195 196 CPU6: cpu@600 { 197 device_type = "cpu"; 198 compatible = "qcom,kryo485"; 199 reg = <0x0 0x600>; 200 clocks = <&cpufreq_hw 1>; 201 enable-method = "psci"; 202 capacity-dmips-mhz = <1024>; 203 dynamic-power-coefficient = <369>; 204 next-level-cache = <&L2_600>; 205 qcom,freq-domain = <&cpufreq_hw 1>; 206 operating-points-v2 = <&cpu4_opp_table>; 207 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 208 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 209 power-domains = <&CPU_PD6>; 210 power-domain-names = "psci"; 211 #cooling-cells = <2>; 212 L2_600: l2-cache { 213 compatible = "cache"; 214 cache-level = <2>; 215 cache-unified; 216 next-level-cache = <&L3_0>; 217 }; 218 }; 219 220 CPU7: cpu@700 { 221 device_type = "cpu"; 222 compatible = "qcom,kryo485"; 223 reg = <0x0 0x700>; 224 clocks = <&cpufreq_hw 2>; 225 enable-method = "psci"; 226 capacity-dmips-mhz = <1024>; 227 dynamic-power-coefficient = <421>; 228 next-level-cache = <&L2_700>; 229 qcom,freq-domain = <&cpufreq_hw 2>; 230 operating-points-v2 = <&cpu7_opp_table>; 231 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 232 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 233 power-domains = <&CPU_PD7>; 234 power-domain-names = "psci"; 235 #cooling-cells = <2>; 236 L2_700: l2-cache { 237 compatible = "cache"; 238 cache-level = <2>; 239 cache-unified; 240 next-level-cache = <&L3_0>; 241 }; 242 }; 243 244 cpu-map { 245 cluster0 { 246 core0 { 247 cpu = <&CPU0>; 248 }; 249 250 core1 { 251 cpu = <&CPU1>; 252 }; 253 254 core2 { 255 cpu = <&CPU2>; 256 }; 257 258 core3 { 259 cpu = <&CPU3>; 260 }; 261 262 core4 { 263 cpu = <&CPU4>; 264 }; 265 266 core5 { 267 cpu = <&CPU5>; 268 }; 269 270 core6 { 271 cpu = <&CPU6>; 272 }; 273 274 core7 { 275 cpu = <&CPU7>; 276 }; 277 }; 278 }; 279 280 idle-states { 281 entry-method = "psci"; 282 283 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 284 compatible = "arm,idle-state"; 285 idle-state-name = "little-rail-power-collapse"; 286 arm,psci-suspend-param = <0x40000004>; 287 entry-latency-us = <355>; 288 exit-latency-us = <909>; 289 min-residency-us = <3934>; 290 local-timer-stop; 291 }; 292 293 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 294 compatible = "arm,idle-state"; 295 idle-state-name = "big-rail-power-collapse"; 296 arm,psci-suspend-param = <0x40000004>; 297 entry-latency-us = <241>; 298 exit-latency-us = <1461>; 299 min-residency-us = <4488>; 300 local-timer-stop; 301 }; 302 }; 303 304 domain-idle-states { 305 CLUSTER_SLEEP_0: cluster-sleep-0 { 306 compatible = "domain-idle-state"; 307 arm,psci-suspend-param = <0x4100c244>; 308 entry-latency-us = <3263>; 309 exit-latency-us = <6562>; 310 min-residency-us = <9987>; 311 }; 312 }; 313 }; 314 315 cpu0_opp_table: opp-table-cpu0 { 316 compatible = "operating-points-v2"; 317 opp-shared; 318 319 cpu0_opp1: opp-300000000 { 320 opp-hz = /bits/ 64 <300000000>; 321 opp-peak-kBps = <800000 9600000>; 322 }; 323 324 cpu0_opp2: opp-403200000 { 325 opp-hz = /bits/ 64 <403200000>; 326 opp-peak-kBps = <800000 9600000>; 327 }; 328 329 cpu0_opp3: opp-499200000 { 330 opp-hz = /bits/ 64 <499200000>; 331 opp-peak-kBps = <800000 12902400>; 332 }; 333 334 cpu0_opp4: opp-576000000 { 335 opp-hz = /bits/ 64 <576000000>; 336 opp-peak-kBps = <800000 12902400>; 337 }; 338 339 cpu0_opp5: opp-672000000 { 340 opp-hz = /bits/ 64 <672000000>; 341 opp-peak-kBps = <800000 15974400>; 342 }; 343 344 cpu0_opp6: opp-768000000 { 345 opp-hz = /bits/ 64 <768000000>; 346 opp-peak-kBps = <1804000 19660800>; 347 }; 348 349 cpu0_opp7: opp-844800000 { 350 opp-hz = /bits/ 64 <844800000>; 351 opp-peak-kBps = <1804000 19660800>; 352 }; 353 354 cpu0_opp8: opp-940800000 { 355 opp-hz = /bits/ 64 <940800000>; 356 opp-peak-kBps = <1804000 22732800>; 357 }; 358 359 cpu0_opp9: opp-1036800000 { 360 opp-hz = /bits/ 64 <1036800000>; 361 opp-peak-kBps = <1804000 22732800>; 362 }; 363 364 cpu0_opp10: opp-1113600000 { 365 opp-hz = /bits/ 64 <1113600000>; 366 opp-peak-kBps = <2188000 25804800>; 367 }; 368 369 cpu0_opp11: opp-1209600000 { 370 opp-hz = /bits/ 64 <1209600000>; 371 opp-peak-kBps = <2188000 31948800>; 372 }; 373 374 cpu0_opp12: opp-1305600000 { 375 opp-hz = /bits/ 64 <1305600000>; 376 opp-peak-kBps = <3072000 31948800>; 377 }; 378 379 cpu0_opp13: opp-1382400000 { 380 opp-hz = /bits/ 64 <1382400000>; 381 opp-peak-kBps = <3072000 31948800>; 382 }; 383 384 cpu0_opp14: opp-1478400000 { 385 opp-hz = /bits/ 64 <1478400000>; 386 opp-peak-kBps = <3072000 31948800>; 387 }; 388 389 cpu0_opp15: opp-1555200000 { 390 opp-hz = /bits/ 64 <1555200000>; 391 opp-peak-kBps = <3072000 40550400>; 392 }; 393 394 cpu0_opp16: opp-1632000000 { 395 opp-hz = /bits/ 64 <1632000000>; 396 opp-peak-kBps = <3072000 40550400>; 397 }; 398 399 cpu0_opp17: opp-1708800000 { 400 opp-hz = /bits/ 64 <1708800000>; 401 opp-peak-kBps = <3072000 43008000>; 402 }; 403 404 cpu0_opp18: opp-1785600000 { 405 opp-hz = /bits/ 64 <1785600000>; 406 opp-peak-kBps = <3072000 43008000>; 407 }; 408 }; 409 410 cpu4_opp_table: opp-table-cpu4 { 411 compatible = "operating-points-v2"; 412 opp-shared; 413 414 cpu4_opp1: opp-710400000 { 415 opp-hz = /bits/ 64 <710400000>; 416 opp-peak-kBps = <1804000 15974400>; 417 }; 418 419 cpu4_opp2: opp-825600000 { 420 opp-hz = /bits/ 64 <825600000>; 421 opp-peak-kBps = <2188000 19660800>; 422 }; 423 424 cpu4_opp3: opp-940800000 { 425 opp-hz = /bits/ 64 <940800000>; 426 opp-peak-kBps = <2188000 22732800>; 427 }; 428 429 cpu4_opp4: opp-1056000000 { 430 opp-hz = /bits/ 64 <1056000000>; 431 opp-peak-kBps = <3072000 25804800>; 432 }; 433 434 cpu4_opp5: opp-1171200000 { 435 opp-hz = /bits/ 64 <1171200000>; 436 opp-peak-kBps = <3072000 31948800>; 437 }; 438 439 cpu4_opp6: opp-1286400000 { 440 opp-hz = /bits/ 64 <1286400000>; 441 opp-peak-kBps = <4068000 31948800>; 442 }; 443 444 cpu4_opp7: opp-1401600000 { 445 opp-hz = /bits/ 64 <1401600000>; 446 opp-peak-kBps = <4068000 31948800>; 447 }; 448 449 cpu4_opp8: opp-1497600000 { 450 opp-hz = /bits/ 64 <1497600000>; 451 opp-peak-kBps = <4068000 40550400>; 452 }; 453 454 cpu4_opp9: opp-1612800000 { 455 opp-hz = /bits/ 64 <1612800000>; 456 opp-peak-kBps = <4068000 40550400>; 457 }; 458 459 cpu4_opp10: opp-1708800000 { 460 opp-hz = /bits/ 64 <1708800000>; 461 opp-peak-kBps = <4068000 43008000>; 462 }; 463 464 cpu4_opp11: opp-1804800000 { 465 opp-hz = /bits/ 64 <1804800000>; 466 opp-peak-kBps = <6220000 43008000>; 467 }; 468 469 cpu4_opp12: opp-1920000000 { 470 opp-hz = /bits/ 64 <1920000000>; 471 opp-peak-kBps = <6220000 49152000>; 472 }; 473 474 cpu4_opp13: opp-2016000000 { 475 opp-hz = /bits/ 64 <2016000000>; 476 opp-peak-kBps = <7216000 49152000>; 477 }; 478 479 cpu4_opp14: opp-2131200000 { 480 opp-hz = /bits/ 64 <2131200000>; 481 opp-peak-kBps = <8368000 49152000>; 482 }; 483 484 cpu4_opp15: opp-2227200000 { 485 opp-hz = /bits/ 64 <2227200000>; 486 opp-peak-kBps = <8368000 51609600>; 487 }; 488 489 cpu4_opp16: opp-2323200000 { 490 opp-hz = /bits/ 64 <2323200000>; 491 opp-peak-kBps = <8368000 51609600>; 492 }; 493 494 cpu4_opp17: opp-2419200000 { 495 opp-hz = /bits/ 64 <2419200000>; 496 opp-peak-kBps = <8368000 51609600>; 497 }; 498 }; 499 500 cpu7_opp_table: opp-table-cpu7 { 501 compatible = "operating-points-v2"; 502 opp-shared; 503 504 cpu7_opp1: opp-825600000 { 505 opp-hz = /bits/ 64 <825600000>; 506 opp-peak-kBps = <2188000 19660800>; 507 }; 508 509 cpu7_opp2: opp-940800000 { 510 opp-hz = /bits/ 64 <940800000>; 511 opp-peak-kBps = <2188000 22732800>; 512 }; 513 514 cpu7_opp3: opp-1056000000 { 515 opp-hz = /bits/ 64 <1056000000>; 516 opp-peak-kBps = <3072000 25804800>; 517 }; 518 519 cpu7_opp4: opp-1171200000 { 520 opp-hz = /bits/ 64 <1171200000>; 521 opp-peak-kBps = <3072000 31948800>; 522 }; 523 524 cpu7_opp5: opp-1286400000 { 525 opp-hz = /bits/ 64 <1286400000>; 526 opp-peak-kBps = <4068000 31948800>; 527 }; 528 529 cpu7_opp6: opp-1401600000 { 530 opp-hz = /bits/ 64 <1401600000>; 531 opp-peak-kBps = <4068000 31948800>; 532 }; 533 534 cpu7_opp7: opp-1497600000 { 535 opp-hz = /bits/ 64 <1497600000>; 536 opp-peak-kBps = <4068000 40550400>; 537 }; 538 539 cpu7_opp8: opp-1612800000 { 540 opp-hz = /bits/ 64 <1612800000>; 541 opp-peak-kBps = <4068000 40550400>; 542 }; 543 544 cpu7_opp9: opp-1708800000 { 545 opp-hz = /bits/ 64 <1708800000>; 546 opp-peak-kBps = <4068000 43008000>; 547 }; 548 549 cpu7_opp10: opp-1804800000 { 550 opp-hz = /bits/ 64 <1804800000>; 551 opp-peak-kBps = <6220000 43008000>; 552 }; 553 554 cpu7_opp11: opp-1920000000 { 555 opp-hz = /bits/ 64 <1920000000>; 556 opp-peak-kBps = <6220000 49152000>; 557 }; 558 559 cpu7_opp12: opp-2016000000 { 560 opp-hz = /bits/ 64 <2016000000>; 561 opp-peak-kBps = <7216000 49152000>; 562 }; 563 564 cpu7_opp13: opp-2131200000 { 565 opp-hz = /bits/ 64 <2131200000>; 566 opp-peak-kBps = <8368000 49152000>; 567 }; 568 569 cpu7_opp14: opp-2227200000 { 570 opp-hz = /bits/ 64 <2227200000>; 571 opp-peak-kBps = <8368000 51609600>; 572 }; 573 574 cpu7_opp15: opp-2323200000 { 575 opp-hz = /bits/ 64 <2323200000>; 576 opp-peak-kBps = <8368000 51609600>; 577 }; 578 579 cpu7_opp16: opp-2419200000 { 580 opp-hz = /bits/ 64 <2419200000>; 581 opp-peak-kBps = <8368000 51609600>; 582 }; 583 584 cpu7_opp17: opp-2534400000 { 585 opp-hz = /bits/ 64 <2534400000>; 586 opp-peak-kBps = <8368000 51609600>; 587 }; 588 589 cpu7_opp18: opp-2649600000 { 590 opp-hz = /bits/ 64 <2649600000>; 591 opp-peak-kBps = <8368000 51609600>; 592 }; 593 594 cpu7_opp19: opp-2745600000 { 595 opp-hz = /bits/ 64 <2745600000>; 596 opp-peak-kBps = <8368000 51609600>; 597 }; 598 599 cpu7_opp20: opp-2841600000 { 600 opp-hz = /bits/ 64 <2841600000>; 601 opp-peak-kBps = <8368000 51609600>; 602 }; 603 }; 604 605 firmware { 606 scm: scm { 607 compatible = "qcom,scm-sm8150", "qcom,scm"; 608 #reset-cells = <1>; 609 }; 610 }; 611 612 memory@80000000 { 613 device_type = "memory"; 614 /* We expect the bootloader to fill in the size */ 615 reg = <0x0 0x80000000 0x0 0x0>; 616 }; 617 618 pmu { 619 compatible = "arm,armv8-pmuv3"; 620 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 621 }; 622 623 psci { 624 compatible = "arm,psci-1.0"; 625 method = "smc"; 626 627 CPU_PD0: power-domain-cpu0 { 628 #power-domain-cells = <0>; 629 power-domains = <&CLUSTER_PD>; 630 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 631 }; 632 633 CPU_PD1: power-domain-cpu1 { 634 #power-domain-cells = <0>; 635 power-domains = <&CLUSTER_PD>; 636 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 637 }; 638 639 CPU_PD2: power-domain-cpu2 { 640 #power-domain-cells = <0>; 641 power-domains = <&CLUSTER_PD>; 642 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 643 }; 644 645 CPU_PD3: power-domain-cpu3 { 646 #power-domain-cells = <0>; 647 power-domains = <&CLUSTER_PD>; 648 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 649 }; 650 651 CPU_PD4: power-domain-cpu4 { 652 #power-domain-cells = <0>; 653 power-domains = <&CLUSTER_PD>; 654 domain-idle-states = <&BIG_CPU_SLEEP_0>; 655 }; 656 657 CPU_PD5: power-domain-cpu5 { 658 #power-domain-cells = <0>; 659 power-domains = <&CLUSTER_PD>; 660 domain-idle-states = <&BIG_CPU_SLEEP_0>; 661 }; 662 663 CPU_PD6: power-domain-cpu6 { 664 #power-domain-cells = <0>; 665 power-domains = <&CLUSTER_PD>; 666 domain-idle-states = <&BIG_CPU_SLEEP_0>; 667 }; 668 669 CPU_PD7: power-domain-cpu7 { 670 #power-domain-cells = <0>; 671 power-domains = <&CLUSTER_PD>; 672 domain-idle-states = <&BIG_CPU_SLEEP_0>; 673 }; 674 675 CLUSTER_PD: power-domain-cpu-cluster0 { 676 #power-domain-cells = <0>; 677 domain-idle-states = <&CLUSTER_SLEEP_0>; 678 }; 679 }; 680 681 reserved-memory { 682 #address-cells = <2>; 683 #size-cells = <2>; 684 ranges; 685 686 hyp_mem: memory@85700000 { 687 reg = <0x0 0x85700000 0x0 0x600000>; 688 no-map; 689 }; 690 691 xbl_mem: memory@85d00000 { 692 reg = <0x0 0x85d00000 0x0 0x140000>; 693 no-map; 694 }; 695 696 aop_mem: memory@85f00000 { 697 reg = <0x0 0x85f00000 0x0 0x20000>; 698 no-map; 699 }; 700 701 aop_cmd_db: memory@85f20000 { 702 compatible = "qcom,cmd-db"; 703 reg = <0x0 0x85f20000 0x0 0x20000>; 704 no-map; 705 }; 706 707 smem_mem: memory@86000000 { 708 reg = <0x0 0x86000000 0x0 0x200000>; 709 no-map; 710 }; 711 712 tz_mem: memory@86200000 { 713 reg = <0x0 0x86200000 0x0 0x3900000>; 714 no-map; 715 }; 716 717 rmtfs_mem: memory@89b00000 { 718 compatible = "qcom,rmtfs-mem"; 719 reg = <0x0 0x89b00000 0x0 0x200000>; 720 no-map; 721 722 qcom,client-id = <1>; 723 qcom,vmid = <15>; 724 }; 725 726 camera_mem: memory@8b700000 { 727 reg = <0x0 0x8b700000 0x0 0x500000>; 728 no-map; 729 }; 730 731 wlan_mem: memory@8bc00000 { 732 reg = <0x0 0x8bc00000 0x0 0x180000>; 733 no-map; 734 }; 735 736 npu_mem: memory@8bd80000 { 737 reg = <0x0 0x8bd80000 0x0 0x80000>; 738 no-map; 739 }; 740 741 adsp_mem: memory@8be00000 { 742 reg = <0x0 0x8be00000 0x0 0x1a00000>; 743 no-map; 744 }; 745 746 mpss_mem: memory@8d800000 { 747 reg = <0x0 0x8d800000 0x0 0x9600000>; 748 no-map; 749 }; 750 751 venus_mem: memory@96e00000 { 752 reg = <0x0 0x96e00000 0x0 0x500000>; 753 no-map; 754 }; 755 756 slpi_mem: memory@97300000 { 757 reg = <0x0 0x97300000 0x0 0x1400000>; 758 no-map; 759 }; 760 761 ipa_fw_mem: memory@98700000 { 762 reg = <0x0 0x98700000 0x0 0x10000>; 763 no-map; 764 }; 765 766 ipa_gsi_mem: memory@98710000 { 767 reg = <0x0 0x98710000 0x0 0x5000>; 768 no-map; 769 }; 770 771 gpu_mem: memory@98715000 { 772 reg = <0x0 0x98715000 0x0 0x2000>; 773 no-map; 774 }; 775 776 spss_mem: memory@98800000 { 777 reg = <0x0 0x98800000 0x0 0x100000>; 778 no-map; 779 }; 780 781 cdsp_mem: memory@98900000 { 782 reg = <0x0 0x98900000 0x0 0x1400000>; 783 no-map; 784 }; 785 786 qseecom_mem: memory@9e400000 { 787 reg = <0x0 0x9e400000 0x0 0x1400000>; 788 no-map; 789 }; 790 }; 791 792 smem { 793 compatible = "qcom,smem"; 794 memory-region = <&smem_mem>; 795 hwlocks = <&tcsr_mutex 3>; 796 }; 797 798 smp2p-cdsp { 799 compatible = "qcom,smp2p"; 800 qcom,smem = <94>, <432>; 801 802 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 803 804 mboxes = <&apss_shared 6>; 805 806 qcom,local-pid = <0>; 807 qcom,remote-pid = <5>; 808 809 cdsp_smp2p_out: master-kernel { 810 qcom,entry-name = "master-kernel"; 811 #qcom,smem-state-cells = <1>; 812 }; 813 814 cdsp_smp2p_in: slave-kernel { 815 qcom,entry-name = "slave-kernel"; 816 817 interrupt-controller; 818 #interrupt-cells = <2>; 819 }; 820 }; 821 822 smp2p-lpass { 823 compatible = "qcom,smp2p"; 824 qcom,smem = <443>, <429>; 825 826 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 827 828 mboxes = <&apss_shared 10>; 829 830 qcom,local-pid = <0>; 831 qcom,remote-pid = <2>; 832 833 adsp_smp2p_out: master-kernel { 834 qcom,entry-name = "master-kernel"; 835 #qcom,smem-state-cells = <1>; 836 }; 837 838 adsp_smp2p_in: slave-kernel { 839 qcom,entry-name = "slave-kernel"; 840 841 interrupt-controller; 842 #interrupt-cells = <2>; 843 }; 844 }; 845 846 smp2p-mpss { 847 compatible = "qcom,smp2p"; 848 qcom,smem = <435>, <428>; 849 850 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 851 852 mboxes = <&apss_shared 14>; 853 854 qcom,local-pid = <0>; 855 qcom,remote-pid = <1>; 856 857 modem_smp2p_out: master-kernel { 858 qcom,entry-name = "master-kernel"; 859 #qcom,smem-state-cells = <1>; 860 }; 861 862 modem_smp2p_in: slave-kernel { 863 qcom,entry-name = "slave-kernel"; 864 865 interrupt-controller; 866 #interrupt-cells = <2>; 867 }; 868 }; 869 870 smp2p-slpi { 871 compatible = "qcom,smp2p"; 872 qcom,smem = <481>, <430>; 873 874 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 875 876 mboxes = <&apss_shared 26>; 877 878 qcom,local-pid = <0>; 879 qcom,remote-pid = <3>; 880 881 slpi_smp2p_out: master-kernel { 882 qcom,entry-name = "master-kernel"; 883 #qcom,smem-state-cells = <1>; 884 }; 885 886 slpi_smp2p_in: slave-kernel { 887 qcom,entry-name = "slave-kernel"; 888 889 interrupt-controller; 890 #interrupt-cells = <2>; 891 }; 892 }; 893 894 soc: soc@0 { 895 #address-cells = <2>; 896 #size-cells = <2>; 897 ranges = <0 0 0 0 0x10 0>; 898 dma-ranges = <0 0 0 0 0x10 0>; 899 compatible = "simple-bus"; 900 901 gcc: clock-controller@100000 { 902 compatible = "qcom,gcc-sm8150"; 903 reg = <0x0 0x00100000 0x0 0x1f0000>; 904 #clock-cells = <1>; 905 #reset-cells = <1>; 906 #power-domain-cells = <1>; 907 clock-names = "bi_tcxo", 908 "sleep_clk"; 909 clocks = <&rpmhcc RPMH_CXO_CLK>, 910 <&sleep_clk>; 911 }; 912 913 gpi_dma0: dma-controller@800000 { 914 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 915 reg = <0 0x00800000 0 0x60000>; 916 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 929 dma-channels = <13>; 930 dma-channel-mask = <0xfa>; 931 iommus = <&apps_smmu 0x00d6 0x0>; 932 #dma-cells = <3>; 933 status = "disabled"; 934 }; 935 936 ethernet: ethernet@20000 { 937 compatible = "qcom,sm8150-ethqos"; 938 reg = <0x0 0x00020000 0x0 0x10000>, 939 <0x0 0x00036000 0x0 0x100>; 940 reg-names = "stmmaceth", "rgmii"; 941 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 942 clocks = <&gcc GCC_EMAC_AXI_CLK>, 943 <&gcc GCC_EMAC_SLV_AHB_CLK>, 944 <&gcc GCC_EMAC_PTP_CLK>, 945 <&gcc GCC_EMAC_RGMII_CLK>; 946 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 948 interrupt-names = "macirq", "eth_lpi"; 949 950 power-domains = <&gcc EMAC_GDSC>; 951 resets = <&gcc GCC_EMAC_BCR>; 952 953 iommus = <&apps_smmu 0x3c0 0x0>; 954 955 snps,tso; 956 rx-fifo-depth = <4096>; 957 tx-fifo-depth = <4096>; 958 959 status = "disabled"; 960 }; 961 962 qfprom: efuse@784000 { 963 compatible = "qcom,sm8150-qfprom", "qcom,qfprom"; 964 reg = <0 0x00784000 0 0x8ff>; 965 #address-cells = <1>; 966 #size-cells = <1>; 967 968 gpu_speed_bin: gpu_speed_bin@133 { 969 reg = <0x133 0x1>; 970 bits = <5 3>; 971 }; 972 }; 973 974 qupv3_id_0: geniqup@8c0000 { 975 compatible = "qcom,geni-se-qup"; 976 reg = <0x0 0x008c0000 0x0 0x6000>; 977 clock-names = "m-ahb", "s-ahb"; 978 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 979 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 980 iommus = <&apps_smmu 0xc3 0x0>; 981 #address-cells = <2>; 982 #size-cells = <2>; 983 ranges; 984 status = "disabled"; 985 986 i2c0: i2c@880000 { 987 compatible = "qcom,geni-i2c"; 988 reg = <0 0x00880000 0 0x4000>; 989 clock-names = "se"; 990 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 991 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 992 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 993 dma-names = "tx", "rx"; 994 pinctrl-names = "default"; 995 pinctrl-0 = <&qup_i2c0_default>; 996 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 status = "disabled"; 1000 }; 1001 1002 spi0: spi@880000 { 1003 compatible = "qcom,geni-spi"; 1004 reg = <0 0x00880000 0 0x4000>; 1005 reg-names = "se"; 1006 clock-names = "se"; 1007 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1008 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1009 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1010 dma-names = "tx", "rx"; 1011 pinctrl-names = "default"; 1012 pinctrl-0 = <&qup_spi0_default>; 1013 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1014 spi-max-frequency = <50000000>; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 status = "disabled"; 1018 }; 1019 1020 i2c1: i2c@884000 { 1021 compatible = "qcom,geni-i2c"; 1022 reg = <0 0x00884000 0 0x4000>; 1023 clock-names = "se"; 1024 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1025 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1026 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1027 dma-names = "tx", "rx"; 1028 pinctrl-names = "default"; 1029 pinctrl-0 = <&qup_i2c1_default>; 1030 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 status = "disabled"; 1034 }; 1035 1036 spi1: spi@884000 { 1037 compatible = "qcom,geni-spi"; 1038 reg = <0 0x00884000 0 0x4000>; 1039 reg-names = "se"; 1040 clock-names = "se"; 1041 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1042 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1043 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1044 dma-names = "tx", "rx"; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&qup_spi1_default>; 1047 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1048 spi-max-frequency = <50000000>; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 status = "disabled"; 1052 }; 1053 1054 i2c2: i2c@888000 { 1055 compatible = "qcom,geni-i2c"; 1056 reg = <0 0x00888000 0 0x4000>; 1057 clock-names = "se"; 1058 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1059 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1060 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1061 dma-names = "tx", "rx"; 1062 pinctrl-names = "default"; 1063 pinctrl-0 = <&qup_i2c2_default>; 1064 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 status = "disabled"; 1068 }; 1069 1070 spi2: spi@888000 { 1071 compatible = "qcom,geni-spi"; 1072 reg = <0 0x00888000 0 0x4000>; 1073 reg-names = "se"; 1074 clock-names = "se"; 1075 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1076 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1077 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1078 dma-names = "tx", "rx"; 1079 pinctrl-names = "default"; 1080 pinctrl-0 = <&qup_spi2_default>; 1081 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1082 spi-max-frequency = <50000000>; 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 status = "disabled"; 1086 }; 1087 1088 i2c3: i2c@88c000 { 1089 compatible = "qcom,geni-i2c"; 1090 reg = <0 0x0088c000 0 0x4000>; 1091 clock-names = "se"; 1092 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1093 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1094 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1095 dma-names = "tx", "rx"; 1096 pinctrl-names = "default"; 1097 pinctrl-0 = <&qup_i2c3_default>; 1098 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 status = "disabled"; 1102 }; 1103 1104 spi3: spi@88c000 { 1105 compatible = "qcom,geni-spi"; 1106 reg = <0 0x0088c000 0 0x4000>; 1107 reg-names = "se"; 1108 clock-names = "se"; 1109 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1110 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1111 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1112 dma-names = "tx", "rx"; 1113 pinctrl-names = "default"; 1114 pinctrl-0 = <&qup_spi3_default>; 1115 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1116 spi-max-frequency = <50000000>; 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 status = "disabled"; 1120 }; 1121 1122 i2c4: i2c@890000 { 1123 compatible = "qcom,geni-i2c"; 1124 reg = <0 0x00890000 0 0x4000>; 1125 clock-names = "se"; 1126 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1127 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1128 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1129 dma-names = "tx", "rx"; 1130 pinctrl-names = "default"; 1131 pinctrl-0 = <&qup_i2c4_default>; 1132 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 status = "disabled"; 1136 }; 1137 1138 spi4: spi@890000 { 1139 compatible = "qcom,geni-spi"; 1140 reg = <0 0x00890000 0 0x4000>; 1141 reg-names = "se"; 1142 clock-names = "se"; 1143 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1144 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1145 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1146 dma-names = "tx", "rx"; 1147 pinctrl-names = "default"; 1148 pinctrl-0 = <&qup_spi4_default>; 1149 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1150 spi-max-frequency = <50000000>; 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 status = "disabled"; 1154 }; 1155 1156 i2c5: i2c@894000 { 1157 compatible = "qcom,geni-i2c"; 1158 reg = <0 0x00894000 0 0x4000>; 1159 clock-names = "se"; 1160 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1161 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1162 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1163 dma-names = "tx", "rx"; 1164 pinctrl-names = "default"; 1165 pinctrl-0 = <&qup_i2c5_default>; 1166 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 status = "disabled"; 1170 }; 1171 1172 spi5: spi@894000 { 1173 compatible = "qcom,geni-spi"; 1174 reg = <0 0x00894000 0 0x4000>; 1175 reg-names = "se"; 1176 clock-names = "se"; 1177 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1178 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1179 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1180 dma-names = "tx", "rx"; 1181 pinctrl-names = "default"; 1182 pinctrl-0 = <&qup_spi5_default>; 1183 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1184 spi-max-frequency = <50000000>; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 status = "disabled"; 1188 }; 1189 1190 i2c6: i2c@898000 { 1191 compatible = "qcom,geni-i2c"; 1192 reg = <0 0x00898000 0 0x4000>; 1193 clock-names = "se"; 1194 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1195 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1196 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1197 dma-names = "tx", "rx"; 1198 pinctrl-names = "default"; 1199 pinctrl-0 = <&qup_i2c6_default>; 1200 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1201 #address-cells = <1>; 1202 #size-cells = <0>; 1203 status = "disabled"; 1204 }; 1205 1206 spi6: spi@898000 { 1207 compatible = "qcom,geni-spi"; 1208 reg = <0 0x00898000 0 0x4000>; 1209 reg-names = "se"; 1210 clock-names = "se"; 1211 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1212 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1213 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1214 dma-names = "tx", "rx"; 1215 pinctrl-names = "default"; 1216 pinctrl-0 = <&qup_spi6_default>; 1217 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1218 spi-max-frequency = <50000000>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 status = "disabled"; 1222 }; 1223 1224 i2c7: i2c@89c000 { 1225 compatible = "qcom,geni-i2c"; 1226 reg = <0 0x0089c000 0 0x4000>; 1227 clock-names = "se"; 1228 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1229 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1230 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1231 dma-names = "tx", "rx"; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&qup_i2c7_default>; 1234 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1235 #address-cells = <1>; 1236 #size-cells = <0>; 1237 status = "disabled"; 1238 }; 1239 1240 spi7: spi@89c000 { 1241 compatible = "qcom,geni-spi"; 1242 reg = <0 0x0089c000 0 0x4000>; 1243 reg-names = "se"; 1244 clock-names = "se"; 1245 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1246 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1247 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1248 dma-names = "tx", "rx"; 1249 pinctrl-names = "default"; 1250 pinctrl-0 = <&qup_spi7_default>; 1251 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1252 spi-max-frequency = <50000000>; 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 status = "disabled"; 1256 }; 1257 }; 1258 1259 gpi_dma1: dma-controller@a00000 { 1260 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1261 reg = <0 0x00a00000 0 0x60000>; 1262 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1275 dma-channels = <13>; 1276 dma-channel-mask = <0xfa>; 1277 iommus = <&apps_smmu 0x0616 0x0>; 1278 #dma-cells = <3>; 1279 status = "disabled"; 1280 }; 1281 1282 qupv3_id_1: geniqup@ac0000 { 1283 compatible = "qcom,geni-se-qup"; 1284 reg = <0x0 0x00ac0000 0x0 0x6000>; 1285 clock-names = "m-ahb", "s-ahb"; 1286 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1287 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1288 iommus = <&apps_smmu 0x603 0x0>; 1289 #address-cells = <2>; 1290 #size-cells = <2>; 1291 ranges; 1292 status = "disabled"; 1293 1294 i2c8: i2c@a80000 { 1295 compatible = "qcom,geni-i2c"; 1296 reg = <0 0x00a80000 0 0x4000>; 1297 clock-names = "se"; 1298 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1299 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1300 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1301 dma-names = "tx", "rx"; 1302 pinctrl-names = "default"; 1303 pinctrl-0 = <&qup_i2c8_default>; 1304 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 status = "disabled"; 1308 }; 1309 1310 spi8: spi@a80000 { 1311 compatible = "qcom,geni-spi"; 1312 reg = <0 0x00a80000 0 0x4000>; 1313 reg-names = "se"; 1314 clock-names = "se"; 1315 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1316 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1317 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1318 dma-names = "tx", "rx"; 1319 pinctrl-names = "default"; 1320 pinctrl-0 = <&qup_spi8_default>; 1321 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1322 spi-max-frequency = <50000000>; 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 status = "disabled"; 1326 }; 1327 1328 i2c9: i2c@a84000 { 1329 compatible = "qcom,geni-i2c"; 1330 reg = <0 0x00a84000 0 0x4000>; 1331 clock-names = "se"; 1332 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1333 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1334 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1335 dma-names = "tx", "rx"; 1336 pinctrl-names = "default"; 1337 pinctrl-0 = <&qup_i2c9_default>; 1338 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 status = "disabled"; 1342 }; 1343 1344 spi9: spi@a84000 { 1345 compatible = "qcom,geni-spi"; 1346 reg = <0 0x00a84000 0 0x4000>; 1347 reg-names = "se"; 1348 clock-names = "se"; 1349 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1350 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1351 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1352 dma-names = "tx", "rx"; 1353 pinctrl-names = "default"; 1354 pinctrl-0 = <&qup_spi9_default>; 1355 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1356 spi-max-frequency = <50000000>; 1357 #address-cells = <1>; 1358 #size-cells = <0>; 1359 status = "disabled"; 1360 }; 1361 1362 uart9: serial@a84000 { 1363 compatible = "qcom,geni-uart"; 1364 reg = <0x0 0x00a84000 0x0 0x4000>; 1365 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1366 clock-names = "se"; 1367 pinctrl-0 = <&qup_uart9_default>; 1368 pinctrl-names = "default"; 1369 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1370 status = "disabled"; 1371 }; 1372 1373 i2c10: i2c@a88000 { 1374 compatible = "qcom,geni-i2c"; 1375 reg = <0 0x00a88000 0 0x4000>; 1376 clock-names = "se"; 1377 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1378 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1379 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1380 dma-names = "tx", "rx"; 1381 pinctrl-names = "default"; 1382 pinctrl-0 = <&qup_i2c10_default>; 1383 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1384 #address-cells = <1>; 1385 #size-cells = <0>; 1386 status = "disabled"; 1387 }; 1388 1389 spi10: spi@a88000 { 1390 compatible = "qcom,geni-spi"; 1391 reg = <0 0x00a88000 0 0x4000>; 1392 reg-names = "se"; 1393 clock-names = "se"; 1394 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1395 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1396 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1397 dma-names = "tx", "rx"; 1398 pinctrl-names = "default"; 1399 pinctrl-0 = <&qup_spi10_default>; 1400 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1401 spi-max-frequency = <50000000>; 1402 #address-cells = <1>; 1403 #size-cells = <0>; 1404 status = "disabled"; 1405 }; 1406 1407 i2c11: i2c@a8c000 { 1408 compatible = "qcom,geni-i2c"; 1409 reg = <0 0x00a8c000 0 0x4000>; 1410 clock-names = "se"; 1411 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1412 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1413 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1414 dma-names = "tx", "rx"; 1415 pinctrl-names = "default"; 1416 pinctrl-0 = <&qup_i2c11_default>; 1417 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1418 #address-cells = <1>; 1419 #size-cells = <0>; 1420 status = "disabled"; 1421 }; 1422 1423 spi11: spi@a8c000 { 1424 compatible = "qcom,geni-spi"; 1425 reg = <0 0x00a8c000 0 0x4000>; 1426 reg-names = "se"; 1427 clock-names = "se"; 1428 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1429 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1430 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1431 dma-names = "tx", "rx"; 1432 pinctrl-names = "default"; 1433 pinctrl-0 = <&qup_spi11_default>; 1434 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1435 spi-max-frequency = <50000000>; 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 status = "disabled"; 1439 }; 1440 1441 uart2: serial@a90000 { 1442 compatible = "qcom,geni-debug-uart"; 1443 reg = <0x0 0x00a90000 0x0 0x4000>; 1444 clock-names = "se"; 1445 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1446 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1447 status = "disabled"; 1448 }; 1449 1450 i2c12: i2c@a90000 { 1451 compatible = "qcom,geni-i2c"; 1452 reg = <0 0x00a90000 0 0x4000>; 1453 clock-names = "se"; 1454 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1455 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1456 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1457 dma-names = "tx", "rx"; 1458 pinctrl-names = "default"; 1459 pinctrl-0 = <&qup_i2c12_default>; 1460 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 status = "disabled"; 1464 }; 1465 1466 spi12: spi@a90000 { 1467 compatible = "qcom,geni-spi"; 1468 reg = <0 0x00a90000 0 0x4000>; 1469 reg-names = "se"; 1470 clock-names = "se"; 1471 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1472 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1473 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1474 dma-names = "tx", "rx"; 1475 pinctrl-names = "default"; 1476 pinctrl-0 = <&qup_spi12_default>; 1477 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1478 spi-max-frequency = <50000000>; 1479 #address-cells = <1>; 1480 #size-cells = <0>; 1481 status = "disabled"; 1482 }; 1483 1484 i2c16: i2c@94000 { 1485 compatible = "qcom,geni-i2c"; 1486 reg = <0 0x00094000 0 0x4000>; 1487 clock-names = "se"; 1488 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1489 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1490 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1491 dma-names = "tx", "rx"; 1492 pinctrl-names = "default"; 1493 pinctrl-0 = <&qup_i2c16_default>; 1494 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1495 #address-cells = <1>; 1496 #size-cells = <0>; 1497 status = "disabled"; 1498 }; 1499 1500 spi16: spi@a94000 { 1501 compatible = "qcom,geni-spi"; 1502 reg = <0 0x00a94000 0 0x4000>; 1503 reg-names = "se"; 1504 clock-names = "se"; 1505 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1506 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1507 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1508 dma-names = "tx", "rx"; 1509 pinctrl-names = "default"; 1510 pinctrl-0 = <&qup_spi16_default>; 1511 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1512 spi-max-frequency = <50000000>; 1513 #address-cells = <1>; 1514 #size-cells = <0>; 1515 status = "disabled"; 1516 }; 1517 }; 1518 1519 gpi_dma2: dma-controller@c00000 { 1520 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1521 reg = <0 0x00c00000 0 0x60000>; 1522 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 1535 dma-channels = <13>; 1536 dma-channel-mask = <0xfa>; 1537 iommus = <&apps_smmu 0x07b6 0x0>; 1538 #dma-cells = <3>; 1539 status = "disabled"; 1540 }; 1541 1542 qupv3_id_2: geniqup@cc0000 { 1543 compatible = "qcom,geni-se-qup"; 1544 reg = <0x0 0x00cc0000 0x0 0x6000>; 1545 1546 clock-names = "m-ahb", "s-ahb"; 1547 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1548 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1549 iommus = <&apps_smmu 0x7a3 0x0>; 1550 #address-cells = <2>; 1551 #size-cells = <2>; 1552 ranges; 1553 status = "disabled"; 1554 1555 i2c17: i2c@c80000 { 1556 compatible = "qcom,geni-i2c"; 1557 reg = <0 0x00c80000 0 0x4000>; 1558 clock-names = "se"; 1559 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1560 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1561 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1562 dma-names = "tx", "rx"; 1563 pinctrl-names = "default"; 1564 pinctrl-0 = <&qup_i2c17_default>; 1565 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1566 #address-cells = <1>; 1567 #size-cells = <0>; 1568 status = "disabled"; 1569 }; 1570 1571 spi17: spi@c80000 { 1572 compatible = "qcom,geni-spi"; 1573 reg = <0 0x00c80000 0 0x4000>; 1574 reg-names = "se"; 1575 clock-names = "se"; 1576 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1577 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1578 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1579 dma-names = "tx", "rx"; 1580 pinctrl-names = "default"; 1581 pinctrl-0 = <&qup_spi17_default>; 1582 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1583 spi-max-frequency = <50000000>; 1584 #address-cells = <1>; 1585 #size-cells = <0>; 1586 status = "disabled"; 1587 }; 1588 1589 i2c18: i2c@c84000 { 1590 compatible = "qcom,geni-i2c"; 1591 reg = <0 0x00c84000 0 0x4000>; 1592 clock-names = "se"; 1593 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1594 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1595 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1596 dma-names = "tx", "rx"; 1597 pinctrl-names = "default"; 1598 pinctrl-0 = <&qup_i2c18_default>; 1599 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 status = "disabled"; 1603 }; 1604 1605 spi18: spi@c84000 { 1606 compatible = "qcom,geni-spi"; 1607 reg = <0 0x00c84000 0 0x4000>; 1608 reg-names = "se"; 1609 clock-names = "se"; 1610 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1611 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1612 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1613 dma-names = "tx", "rx"; 1614 pinctrl-names = "default"; 1615 pinctrl-0 = <&qup_spi18_default>; 1616 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1617 spi-max-frequency = <50000000>; 1618 #address-cells = <1>; 1619 #size-cells = <0>; 1620 status = "disabled"; 1621 }; 1622 1623 i2c19: i2c@c88000 { 1624 compatible = "qcom,geni-i2c"; 1625 reg = <0 0x00c88000 0 0x4000>; 1626 clock-names = "se"; 1627 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1628 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1629 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1630 dma-names = "tx", "rx"; 1631 pinctrl-names = "default"; 1632 pinctrl-0 = <&qup_i2c19_default>; 1633 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1634 #address-cells = <1>; 1635 #size-cells = <0>; 1636 status = "disabled"; 1637 }; 1638 1639 spi19: spi@c88000 { 1640 compatible = "qcom,geni-spi"; 1641 reg = <0 0x00c88000 0 0x4000>; 1642 reg-names = "se"; 1643 clock-names = "se"; 1644 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1645 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1646 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1647 dma-names = "tx", "rx"; 1648 pinctrl-names = "default"; 1649 pinctrl-0 = <&qup_spi19_default>; 1650 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1651 spi-max-frequency = <50000000>; 1652 #address-cells = <1>; 1653 #size-cells = <0>; 1654 status = "disabled"; 1655 }; 1656 1657 i2c13: i2c@c8c000 { 1658 compatible = "qcom,geni-i2c"; 1659 reg = <0 0x00c8c000 0 0x4000>; 1660 clock-names = "se"; 1661 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1662 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1663 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1664 dma-names = "tx", "rx"; 1665 pinctrl-names = "default"; 1666 pinctrl-0 = <&qup_i2c13_default>; 1667 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1668 #address-cells = <1>; 1669 #size-cells = <0>; 1670 status = "disabled"; 1671 }; 1672 1673 spi13: spi@c8c000 { 1674 compatible = "qcom,geni-spi"; 1675 reg = <0 0x00c8c000 0 0x4000>; 1676 reg-names = "se"; 1677 clock-names = "se"; 1678 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1679 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1680 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1681 dma-names = "tx", "rx"; 1682 pinctrl-names = "default"; 1683 pinctrl-0 = <&qup_spi13_default>; 1684 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1685 spi-max-frequency = <50000000>; 1686 #address-cells = <1>; 1687 #size-cells = <0>; 1688 status = "disabled"; 1689 }; 1690 1691 i2c14: i2c@c90000 { 1692 compatible = "qcom,geni-i2c"; 1693 reg = <0 0x00c90000 0 0x4000>; 1694 clock-names = "se"; 1695 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1696 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1697 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1698 dma-names = "tx", "rx"; 1699 pinctrl-names = "default"; 1700 pinctrl-0 = <&qup_i2c14_default>; 1701 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1702 #address-cells = <1>; 1703 #size-cells = <0>; 1704 status = "disabled"; 1705 }; 1706 1707 spi14: spi@c90000 { 1708 compatible = "qcom,geni-spi"; 1709 reg = <0 0x00c90000 0 0x4000>; 1710 reg-names = "se"; 1711 clock-names = "se"; 1712 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1713 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1714 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1715 dma-names = "tx", "rx"; 1716 pinctrl-names = "default"; 1717 pinctrl-0 = <&qup_spi14_default>; 1718 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1719 spi-max-frequency = <50000000>; 1720 #address-cells = <1>; 1721 #size-cells = <0>; 1722 status = "disabled"; 1723 }; 1724 1725 i2c15: i2c@c94000 { 1726 compatible = "qcom,geni-i2c"; 1727 reg = <0 0x00c94000 0 0x4000>; 1728 clock-names = "se"; 1729 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1730 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1731 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1732 dma-names = "tx", "rx"; 1733 pinctrl-names = "default"; 1734 pinctrl-0 = <&qup_i2c15_default>; 1735 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1736 #address-cells = <1>; 1737 #size-cells = <0>; 1738 status = "disabled"; 1739 }; 1740 1741 spi15: spi@c94000 { 1742 compatible = "qcom,geni-spi"; 1743 reg = <0 0x00c94000 0 0x4000>; 1744 reg-names = "se"; 1745 clock-names = "se"; 1746 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1747 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1748 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1749 dma-names = "tx", "rx"; 1750 pinctrl-names = "default"; 1751 pinctrl-0 = <&qup_spi15_default>; 1752 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1753 spi-max-frequency = <50000000>; 1754 #address-cells = <1>; 1755 #size-cells = <0>; 1756 status = "disabled"; 1757 }; 1758 }; 1759 1760 config_noc: interconnect@1500000 { 1761 compatible = "qcom,sm8150-config-noc"; 1762 reg = <0 0x01500000 0 0x7400>; 1763 #interconnect-cells = <2>; 1764 qcom,bcm-voters = <&apps_bcm_voter>; 1765 }; 1766 1767 system_noc: interconnect@1620000 { 1768 compatible = "qcom,sm8150-system-noc"; 1769 reg = <0 0x01620000 0 0x19400>; 1770 #interconnect-cells = <2>; 1771 qcom,bcm-voters = <&apps_bcm_voter>; 1772 }; 1773 1774 mc_virt: interconnect@163a000 { 1775 compatible = "qcom,sm8150-mc-virt"; 1776 reg = <0 0x0163a000 0 0x1000>; 1777 #interconnect-cells = <2>; 1778 qcom,bcm-voters = <&apps_bcm_voter>; 1779 }; 1780 1781 aggre1_noc: interconnect@16e0000 { 1782 compatible = "qcom,sm8150-aggre1-noc"; 1783 reg = <0 0x016e0000 0 0xd080>; 1784 #interconnect-cells = <2>; 1785 qcom,bcm-voters = <&apps_bcm_voter>; 1786 }; 1787 1788 aggre2_noc: interconnect@1700000 { 1789 compatible = "qcom,sm8150-aggre2-noc"; 1790 reg = <0 0x01700000 0 0x20000>; 1791 #interconnect-cells = <2>; 1792 qcom,bcm-voters = <&apps_bcm_voter>; 1793 }; 1794 1795 compute_noc: interconnect@1720000 { 1796 compatible = "qcom,sm8150-compute-noc"; 1797 reg = <0 0x01720000 0 0x7000>; 1798 #interconnect-cells = <2>; 1799 qcom,bcm-voters = <&apps_bcm_voter>; 1800 }; 1801 1802 mmss_noc: interconnect@1740000 { 1803 compatible = "qcom,sm8150-mmss-noc"; 1804 reg = <0 0x01740000 0 0x1c100>; 1805 #interconnect-cells = <2>; 1806 qcom,bcm-voters = <&apps_bcm_voter>; 1807 }; 1808 1809 system-cache-controller@9200000 { 1810 compatible = "qcom,sm8150-llcc"; 1811 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 1812 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 1813 <0 0x09600000 0 0x50000>; 1814 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 1815 "llcc3_base", "llcc_broadcast_base"; 1816 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1817 }; 1818 1819 dma@10a2000 { 1820 compatible = "qcom,sm8150-dcc", "qcom,dcc"; 1821 reg = <0x0 0x010a2000 0x0 0x1000>, 1822 <0x0 0x010ad000 0x0 0x3000>; 1823 }; 1824 1825 pcie0: pci@1c00000 { 1826 compatible = "qcom,pcie-sm8150"; 1827 reg = <0 0x01c00000 0 0x3000>, 1828 <0 0x60000000 0 0xf1d>, 1829 <0 0x60000f20 0 0xa8>, 1830 <0 0x60001000 0 0x1000>, 1831 <0 0x60100000 0 0x100000>; 1832 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1833 device_type = "pci"; 1834 linux,pci-domain = <0>; 1835 bus-range = <0x00 0xff>; 1836 num-lanes = <1>; 1837 1838 #address-cells = <3>; 1839 #size-cells = <2>; 1840 1841 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1842 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1843 1844 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1845 interrupt-names = "msi"; 1846 #interrupt-cells = <1>; 1847 interrupt-map-mask = <0 0 0 0x7>; 1848 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1849 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1850 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1851 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1852 1853 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1854 <&gcc GCC_PCIE_0_AUX_CLK>, 1855 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1856 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1857 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1858 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1859 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1860 clock-names = "pipe", 1861 "aux", 1862 "cfg", 1863 "bus_master", 1864 "bus_slave", 1865 "slave_q2a", 1866 "tbu"; 1867 1868 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1869 <0x100 &apps_smmu 0x1d81 0x1>; 1870 1871 resets = <&gcc GCC_PCIE_0_BCR>; 1872 reset-names = "pci"; 1873 1874 power-domains = <&gcc PCIE_0_GDSC>; 1875 1876 phys = <&pcie0_lane>; 1877 phy-names = "pciephy"; 1878 1879 perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1880 wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1881 1882 pinctrl-names = "default"; 1883 pinctrl-0 = <&pcie0_default_state>; 1884 1885 status = "disabled"; 1886 }; 1887 1888 pcie0_phy: phy@1c06000 { 1889 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1890 reg = <0 0x01c06000 0 0x1c0>; 1891 #address-cells = <2>; 1892 #size-cells = <2>; 1893 ranges; 1894 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1895 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1896 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1897 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1898 clock-names = "aux", 1899 "cfg_ahb", 1900 "ref", 1901 "refgen"; 1902 1903 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1904 reset-names = "phy"; 1905 1906 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1907 assigned-clock-rates = <100000000>; 1908 1909 status = "disabled"; 1910 1911 pcie0_lane: phy@1c06200 { 1912 reg = <0 0x01c06200 0 0x170>, /* tx */ 1913 <0 0x01c06400 0 0x200>, /* rx */ 1914 <0 0x01c06800 0 0x1f0>, /* pcs */ 1915 <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1916 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1917 clock-names = "pipe0"; 1918 1919 #phy-cells = <0>; 1920 clock-output-names = "pcie_0_pipe_clk"; 1921 }; 1922 }; 1923 1924 pcie1: pci@1c08000 { 1925 compatible = "qcom,pcie-sm8150"; 1926 reg = <0 0x01c08000 0 0x3000>, 1927 <0 0x40000000 0 0xf1d>, 1928 <0 0x40000f20 0 0xa8>, 1929 <0 0x40001000 0 0x1000>, 1930 <0 0x40100000 0 0x100000>; 1931 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1932 device_type = "pci"; 1933 linux,pci-domain = <1>; 1934 bus-range = <0x00 0xff>; 1935 num-lanes = <2>; 1936 1937 #address-cells = <3>; 1938 #size-cells = <2>; 1939 1940 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1941 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1942 1943 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1944 interrupt-names = "msi"; 1945 #interrupt-cells = <1>; 1946 interrupt-map-mask = <0 0 0 0x7>; 1947 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1948 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1949 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1950 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1951 1952 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1953 <&gcc GCC_PCIE_1_AUX_CLK>, 1954 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1955 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1956 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1957 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1958 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1959 clock-names = "pipe", 1960 "aux", 1961 "cfg", 1962 "bus_master", 1963 "bus_slave", 1964 "slave_q2a", 1965 "tbu"; 1966 1967 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1968 assigned-clock-rates = <19200000>; 1969 1970 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1971 <0x100 &apps_smmu 0x1e01 0x1>; 1972 1973 resets = <&gcc GCC_PCIE_1_BCR>; 1974 reset-names = "pci"; 1975 1976 power-domains = <&gcc PCIE_1_GDSC>; 1977 1978 phys = <&pcie1_lane>; 1979 phy-names = "pciephy"; 1980 1981 perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; 1982 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 1983 1984 pinctrl-names = "default"; 1985 pinctrl-0 = <&pcie1_default_state>; 1986 1987 status = "disabled"; 1988 }; 1989 1990 pcie1_phy: phy@1c0e000 { 1991 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 1992 reg = <0 0x01c0e000 0 0x1c0>; 1993 #address-cells = <2>; 1994 #size-cells = <2>; 1995 ranges; 1996 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1997 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1998 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1999 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2000 clock-names = "aux", 2001 "cfg_ahb", 2002 "ref", 2003 "refgen"; 2004 2005 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2006 reset-names = "phy"; 2007 2008 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2009 assigned-clock-rates = <100000000>; 2010 2011 status = "disabled"; 2012 2013 pcie1_lane: phy@1c0e200 { 2014 reg = <0 0x01c0e200 0 0x170>, /* tx0 */ 2015 <0 0x01c0e400 0 0x200>, /* rx0 */ 2016 <0 0x01c0ea00 0 0x1f0>, /* pcs */ 2017 <0 0x01c0e600 0 0x170>, /* tx1 */ 2018 <0 0x01c0e800 0 0x200>, /* rx1 */ 2019 <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2020 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2021 clock-names = "pipe0"; 2022 2023 #phy-cells = <0>; 2024 clock-output-names = "pcie_1_pipe_clk"; 2025 }; 2026 }; 2027 2028 ufs_mem_hc: ufshc@1d84000 { 2029 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 2030 "jedec,ufs-2.0"; 2031 reg = <0 0x01d84000 0 0x2500>, 2032 <0 0x01d90000 0 0x8000>; 2033 reg-names = "std", "ice"; 2034 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2035 phys = <&ufs_mem_phy_lanes>; 2036 phy-names = "ufsphy"; 2037 lanes-per-direction = <2>; 2038 #reset-cells = <1>; 2039 resets = <&gcc GCC_UFS_PHY_BCR>; 2040 reset-names = "rst"; 2041 2042 iommus = <&apps_smmu 0x300 0>; 2043 2044 clock-names = 2045 "core_clk", 2046 "bus_aggr_clk", 2047 "iface_clk", 2048 "core_clk_unipro", 2049 "ref_clk", 2050 "tx_lane0_sync_clk", 2051 "rx_lane0_sync_clk", 2052 "rx_lane1_sync_clk", 2053 "ice_core_clk"; 2054 clocks = 2055 <&gcc GCC_UFS_PHY_AXI_CLK>, 2056 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2057 <&gcc GCC_UFS_PHY_AHB_CLK>, 2058 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2059 <&rpmhcc RPMH_CXO_CLK>, 2060 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2061 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2062 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2063 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2064 freq-table-hz = 2065 <37500000 300000000>, 2066 <0 0>, 2067 <0 0>, 2068 <37500000 300000000>, 2069 <0 0>, 2070 <0 0>, 2071 <0 0>, 2072 <0 0>, 2073 <0 300000000>; 2074 2075 status = "disabled"; 2076 }; 2077 2078 ufs_mem_phy: phy@1d87000 { 2079 compatible = "qcom,sm8150-qmp-ufs-phy"; 2080 reg = <0 0x01d87000 0 0x1c0>; 2081 #address-cells = <2>; 2082 #size-cells = <2>; 2083 ranges; 2084 clock-names = "ref", 2085 "ref_aux"; 2086 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2087 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2088 2089 power-domains = <&gcc UFS_PHY_GDSC>; 2090 2091 resets = <&ufs_mem_hc 0>; 2092 reset-names = "ufsphy"; 2093 status = "disabled"; 2094 2095 ufs_mem_phy_lanes: phy@1d87400 { 2096 reg = <0 0x01d87400 0 0x16c>, 2097 <0 0x01d87600 0 0x200>, 2098 <0 0x01d87c00 0 0x200>, 2099 <0 0x01d87800 0 0x16c>, 2100 <0 0x01d87a00 0 0x200>; 2101 #phy-cells = <0>; 2102 }; 2103 }; 2104 2105 cryptobam: dma-controller@1dc4000 { 2106 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2107 reg = <0 0x01dc4000 0 0x24000>; 2108 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2109 #dma-cells = <1>; 2110 qcom,ee = <0>; 2111 qcom,controlled-remotely; 2112 num-channels = <8>; 2113 qcom,num-ees = <2>; 2114 iommus = <&apps_smmu 0x502 0x0641>, 2115 <&apps_smmu 0x504 0x0011>, 2116 <&apps_smmu 0x506 0x0011>, 2117 <&apps_smmu 0x508 0x0011>, 2118 <&apps_smmu 0x512 0x0000>; 2119 }; 2120 2121 crypto: crypto@1dfa000 { 2122 compatible = "qcom,sm8150-qce", "qcom,qce"; 2123 reg = <0 0x01dfa000 0 0x6000>; 2124 dmas = <&cryptobam 4>, <&cryptobam 5>; 2125 dma-names = "rx", "tx"; 2126 iommus = <&apps_smmu 0x502 0x0641>, 2127 <&apps_smmu 0x504 0x0011>, 2128 <&apps_smmu 0x506 0x0011>, 2129 <&apps_smmu 0x508 0x0011>, 2130 <&apps_smmu 0x512 0x0000>; 2131 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; 2132 interconnect-names = "memory"; 2133 }; 2134 2135 tcsr_mutex: hwlock@1f40000 { 2136 compatible = "qcom,tcsr-mutex"; 2137 reg = <0x0 0x01f40000 0x0 0x20000>; 2138 #hwlock-cells = <1>; 2139 }; 2140 2141 tcsr_regs_1: syscon@1f60000 { 2142 compatible = "qcom,sm8150-tcsr", "syscon"; 2143 reg = <0x0 0x01f60000 0x0 0x20000>; 2144 }; 2145 2146 remoteproc_slpi: remoteproc@2400000 { 2147 compatible = "qcom,sm8150-slpi-pas"; 2148 reg = <0x0 0x02400000 0x0 0x4040>; 2149 2150 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 2151 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2152 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2153 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2154 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2155 interrupt-names = "wdog", "fatal", "ready", 2156 "handover", "stop-ack"; 2157 2158 clocks = <&rpmhcc RPMH_CXO_CLK>; 2159 clock-names = "xo"; 2160 2161 power-domains = <&rpmhpd SM8150_LCX>, 2162 <&rpmhpd SM8150_LMX>; 2163 power-domain-names = "lcx", "lmx"; 2164 2165 memory-region = <&slpi_mem>; 2166 2167 qcom,qmp = <&aoss_qmp>; 2168 2169 qcom,smem-states = <&slpi_smp2p_out 0>; 2170 qcom,smem-state-names = "stop"; 2171 2172 status = "disabled"; 2173 2174 glink-edge { 2175 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 2176 label = "dsps"; 2177 qcom,remote-pid = <3>; 2178 mboxes = <&apss_shared 24>; 2179 2180 fastrpc { 2181 compatible = "qcom,fastrpc"; 2182 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2183 label = "sdsp"; 2184 qcom,non-secure-domain; 2185 #address-cells = <1>; 2186 #size-cells = <0>; 2187 2188 compute-cb@1 { 2189 compatible = "qcom,fastrpc-compute-cb"; 2190 reg = <1>; 2191 iommus = <&apps_smmu 0x05a1 0x0>; 2192 }; 2193 2194 compute-cb@2 { 2195 compatible = "qcom,fastrpc-compute-cb"; 2196 reg = <2>; 2197 iommus = <&apps_smmu 0x05a2 0x0>; 2198 }; 2199 2200 compute-cb@3 { 2201 compatible = "qcom,fastrpc-compute-cb"; 2202 reg = <3>; 2203 iommus = <&apps_smmu 0x05a3 0x0>; 2204 /* note: shared-cb = <4> in downstream */ 2205 }; 2206 }; 2207 }; 2208 }; 2209 2210 gpu: gpu@2c00000 { 2211 compatible = "qcom,adreno-640.1", "qcom,adreno"; 2212 reg = <0 0x02c00000 0 0x40000>; 2213 reg-names = "kgsl_3d0_reg_memory"; 2214 2215 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2216 2217 iommus = <&adreno_smmu 0 0x401>; 2218 2219 operating-points-v2 = <&gpu_opp_table>; 2220 2221 qcom,gmu = <&gmu>; 2222 2223 nvmem-cells = <&gpu_speed_bin>; 2224 nvmem-cell-names = "speed_bin"; 2225 2226 status = "disabled"; 2227 2228 zap-shader { 2229 memory-region = <&gpu_mem>; 2230 }; 2231 2232 gpu_opp_table: opp-table { 2233 compatible = "operating-points-v2"; 2234 2235 opp-675000000 { 2236 opp-hz = /bits/ 64 <675000000>; 2237 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2238 opp-supported-hw = <0x2>; 2239 }; 2240 2241 opp-585000000 { 2242 opp-hz = /bits/ 64 <585000000>; 2243 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2244 opp-supported-hw = <0x3>; 2245 }; 2246 2247 opp-499200000 { 2248 opp-hz = /bits/ 64 <499200000>; 2249 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2250 opp-supported-hw = <0x3>; 2251 }; 2252 2253 opp-427000000 { 2254 opp-hz = /bits/ 64 <427000000>; 2255 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2256 opp-supported-hw = <0x3>; 2257 }; 2258 2259 opp-345000000 { 2260 opp-hz = /bits/ 64 <345000000>; 2261 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2262 opp-supported-hw = <0x3>; 2263 }; 2264 2265 opp-257000000 { 2266 opp-hz = /bits/ 64 <257000000>; 2267 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2268 opp-supported-hw = <0x3>; 2269 }; 2270 }; 2271 }; 2272 2273 gmu: gmu@2c6a000 { 2274 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2275 2276 reg = <0 0x02c6a000 0 0x30000>, 2277 <0 0x0b290000 0 0x10000>, 2278 <0 0x0b490000 0 0x10000>; 2279 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2280 2281 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2282 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2283 interrupt-names = "hfi", "gmu"; 2284 2285 clocks = <&gpucc GPU_CC_AHB_CLK>, 2286 <&gpucc GPU_CC_CX_GMU_CLK>, 2287 <&gpucc GPU_CC_CXO_CLK>, 2288 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2289 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2290 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2291 2292 power-domains = <&gpucc GPU_CX_GDSC>, 2293 <&gpucc GPU_GX_GDSC>; 2294 power-domain-names = "cx", "gx"; 2295 2296 iommus = <&adreno_smmu 5 0x400>; 2297 2298 operating-points-v2 = <&gmu_opp_table>; 2299 2300 status = "disabled"; 2301 2302 gmu_opp_table: opp-table { 2303 compatible = "operating-points-v2"; 2304 2305 opp-200000000 { 2306 opp-hz = /bits/ 64 <200000000>; 2307 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2308 }; 2309 }; 2310 }; 2311 2312 gpucc: clock-controller@2c90000 { 2313 compatible = "qcom,sm8150-gpucc"; 2314 reg = <0 0x02c90000 0 0x9000>; 2315 clocks = <&rpmhcc RPMH_CXO_CLK>, 2316 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2317 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2318 clock-names = "bi_tcxo", 2319 "gcc_gpu_gpll0_clk_src", 2320 "gcc_gpu_gpll0_div_clk_src"; 2321 #clock-cells = <1>; 2322 #reset-cells = <1>; 2323 #power-domain-cells = <1>; 2324 }; 2325 2326 adreno_smmu: iommu@2ca0000 { 2327 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", 2328 "qcom,smmu-500", "arm,mmu-500"; 2329 reg = <0 0x02ca0000 0 0x10000>; 2330 #iommu-cells = <2>; 2331 #global-interrupts = <1>; 2332 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2333 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2334 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2335 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2336 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2337 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2338 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2339 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2340 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2341 clocks = <&gpucc GPU_CC_AHB_CLK>, 2342 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2343 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2344 clock-names = "ahb", "bus", "iface"; 2345 2346 power-domains = <&gpucc GPU_CX_GDSC>; 2347 }; 2348 2349 tlmm: pinctrl@3100000 { 2350 compatible = "qcom,sm8150-pinctrl"; 2351 reg = <0x0 0x03100000 0x0 0x300000>, 2352 <0x0 0x03500000 0x0 0x300000>, 2353 <0x0 0x03900000 0x0 0x300000>, 2354 <0x0 0x03D00000 0x0 0x300000>; 2355 reg-names = "west", "east", "north", "south"; 2356 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2357 gpio-ranges = <&tlmm 0 0 176>; 2358 gpio-controller; 2359 #gpio-cells = <2>; 2360 interrupt-controller; 2361 #interrupt-cells = <2>; 2362 wakeup-parent = <&pdc>; 2363 2364 qup_i2c0_default: qup-i2c0-default-state { 2365 pins = "gpio0", "gpio1"; 2366 function = "qup0"; 2367 drive-strength = <0x02>; 2368 bias-disable; 2369 }; 2370 2371 qup_spi0_default: qup-spi0-default-state { 2372 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2373 function = "qup0"; 2374 drive-strength = <6>; 2375 bias-disable; 2376 }; 2377 2378 qup_i2c1_default: qup-i2c1-default-state { 2379 pins = "gpio114", "gpio115"; 2380 function = "qup1"; 2381 drive-strength = <2>; 2382 bias-disable; 2383 }; 2384 2385 qup_spi1_default: qup-spi1-default-state { 2386 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2387 function = "qup1"; 2388 drive-strength = <6>; 2389 bias-disable; 2390 }; 2391 2392 qup_i2c2_default: qup-i2c2-default-state { 2393 pins = "gpio126", "gpio127"; 2394 function = "qup2"; 2395 drive-strength = <2>; 2396 bias-disable; 2397 }; 2398 2399 qup_spi2_default: qup-spi2-default-state { 2400 pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2401 function = "qup2"; 2402 drive-strength = <6>; 2403 bias-disable; 2404 }; 2405 2406 qup_i2c3_default: qup-i2c3-default-state { 2407 pins = "gpio144", "gpio145"; 2408 function = "qup3"; 2409 drive-strength = <2>; 2410 bias-disable; 2411 }; 2412 2413 qup_spi3_default: qup-spi3-default-state { 2414 pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2415 function = "qup3"; 2416 drive-strength = <6>; 2417 bias-disable; 2418 }; 2419 2420 qup_i2c4_default: qup-i2c4-default-state { 2421 pins = "gpio51", "gpio52"; 2422 function = "qup4"; 2423 drive-strength = <2>; 2424 bias-disable; 2425 }; 2426 2427 qup_spi4_default: qup-spi4-default-state { 2428 pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2429 function = "qup4"; 2430 drive-strength = <6>; 2431 bias-disable; 2432 }; 2433 2434 qup_i2c5_default: qup-i2c5-default-state { 2435 pins = "gpio121", "gpio122"; 2436 function = "qup5"; 2437 drive-strength = <2>; 2438 bias-disable; 2439 }; 2440 2441 qup_spi5_default: qup-spi5-default-state { 2442 pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2443 function = "qup5"; 2444 drive-strength = <6>; 2445 bias-disable; 2446 }; 2447 2448 qup_i2c6_default: qup-i2c6-default-state { 2449 pins = "gpio6", "gpio7"; 2450 function = "qup6"; 2451 drive-strength = <2>; 2452 bias-disable; 2453 }; 2454 2455 qup_spi6_default: qup-spi6_default-state { 2456 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2457 function = "qup6"; 2458 drive-strength = <6>; 2459 bias-disable; 2460 }; 2461 2462 qup_i2c7_default: qup-i2c7-default-state { 2463 pins = "gpio98", "gpio99"; 2464 function = "qup7"; 2465 drive-strength = <2>; 2466 bias-disable; 2467 }; 2468 2469 qup_spi7_default: qup-spi7_default-state { 2470 pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2471 function = "qup7"; 2472 drive-strength = <6>; 2473 bias-disable; 2474 }; 2475 2476 qup_i2c8_default: qup-i2c8-default-state { 2477 pins = "gpio88", "gpio89"; 2478 function = "qup8"; 2479 drive-strength = <2>; 2480 bias-disable; 2481 }; 2482 2483 qup_spi8_default: qup-spi8-default-state { 2484 pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2485 function = "qup8"; 2486 drive-strength = <6>; 2487 bias-disable; 2488 }; 2489 2490 qup_i2c9_default: qup-i2c9-default-state { 2491 pins = "gpio39", "gpio40"; 2492 function = "qup9"; 2493 drive-strength = <2>; 2494 bias-disable; 2495 }; 2496 2497 qup_spi9_default: qup-spi9-default-state { 2498 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2499 function = "qup9"; 2500 drive-strength = <6>; 2501 bias-disable; 2502 }; 2503 2504 qup_uart9_default: qup-uart9-default-state { 2505 pins = "gpio41", "gpio42"; 2506 function = "qup9"; 2507 drive-strength = <2>; 2508 bias-disable; 2509 }; 2510 2511 qup_i2c10_default: qup-i2c10-default-state { 2512 pins = "gpio9", "gpio10"; 2513 function = "qup10"; 2514 drive-strength = <2>; 2515 bias-disable; 2516 }; 2517 2518 qup_spi10_default: qup-spi10-default-state { 2519 pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2520 function = "qup10"; 2521 drive-strength = <6>; 2522 bias-disable; 2523 }; 2524 2525 qup_i2c11_default: qup-i2c11-default-state { 2526 pins = "gpio94", "gpio95"; 2527 function = "qup11"; 2528 drive-strength = <2>; 2529 bias-disable; 2530 }; 2531 2532 qup_spi11_default: qup-spi11-default-state { 2533 pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2534 function = "qup11"; 2535 drive-strength = <6>; 2536 bias-disable; 2537 }; 2538 2539 qup_i2c12_default: qup-i2c12-default-state { 2540 pins = "gpio83", "gpio84"; 2541 function = "qup12"; 2542 drive-strength = <2>; 2543 bias-disable; 2544 }; 2545 2546 qup_spi12_default: qup-spi12-default-state { 2547 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2548 function = "qup12"; 2549 drive-strength = <6>; 2550 bias-disable; 2551 }; 2552 2553 qup_i2c13_default: qup-i2c13-default-state { 2554 pins = "gpio43", "gpio44"; 2555 function = "qup13"; 2556 drive-strength = <2>; 2557 bias-disable; 2558 }; 2559 2560 qup_spi13_default: qup-spi13-default-state { 2561 pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2562 function = "qup13"; 2563 drive-strength = <6>; 2564 bias-disable; 2565 }; 2566 2567 qup_i2c14_default: qup-i2c14-default-state { 2568 pins = "gpio47", "gpio48"; 2569 function = "qup14"; 2570 drive-strength = <2>; 2571 bias-disable; 2572 }; 2573 2574 qup_spi14_default: qup-spi14-default-state { 2575 pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2576 function = "qup14"; 2577 drive-strength = <6>; 2578 bias-disable; 2579 }; 2580 2581 qup_i2c15_default: qup-i2c15-default-state { 2582 pins = "gpio27", "gpio28"; 2583 function = "qup15"; 2584 drive-strength = <2>; 2585 bias-disable; 2586 }; 2587 2588 qup_spi15_default: qup-spi15-default-state { 2589 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2590 function = "qup15"; 2591 drive-strength = <6>; 2592 bias-disable; 2593 }; 2594 2595 qup_i2c16_default: qup-i2c16-default-state { 2596 pins = "gpio86", "gpio85"; 2597 function = "qup16"; 2598 drive-strength = <2>; 2599 bias-disable; 2600 }; 2601 2602 qup_spi16_default: qup-spi16-default-state { 2603 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2604 function = "qup16"; 2605 drive-strength = <6>; 2606 bias-disable; 2607 }; 2608 2609 qup_i2c17_default: qup-i2c17-default-state { 2610 pins = "gpio55", "gpio56"; 2611 function = "qup17"; 2612 drive-strength = <2>; 2613 bias-disable; 2614 }; 2615 2616 qup_spi17_default: qup-spi17-default-state { 2617 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2618 function = "qup17"; 2619 drive-strength = <6>; 2620 bias-disable; 2621 }; 2622 2623 qup_i2c18_default: qup-i2c18-default-state { 2624 pins = "gpio23", "gpio24"; 2625 function = "qup18"; 2626 drive-strength = <2>; 2627 bias-disable; 2628 }; 2629 2630 qup_spi18_default: qup-spi18-default-state { 2631 pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2632 function = "qup18"; 2633 drive-strength = <6>; 2634 bias-disable; 2635 }; 2636 2637 qup_i2c19_default: qup-i2c19-default-state { 2638 pins = "gpio57", "gpio58"; 2639 function = "qup19"; 2640 drive-strength = <2>; 2641 bias-disable; 2642 }; 2643 2644 qup_spi19_default: qup-spi19-default-state { 2645 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2646 function = "qup19"; 2647 drive-strength = <6>; 2648 bias-disable; 2649 }; 2650 2651 pcie0_default_state: pcie0-default-state { 2652 perst-pins { 2653 pins = "gpio35"; 2654 function = "gpio"; 2655 drive-strength = <2>; 2656 bias-pull-down; 2657 }; 2658 2659 clkreq-pins { 2660 pins = "gpio36"; 2661 function = "pci_e0"; 2662 drive-strength = <2>; 2663 bias-pull-up; 2664 }; 2665 2666 wake-pins { 2667 pins = "gpio37"; 2668 function = "gpio"; 2669 drive-strength = <2>; 2670 bias-pull-up; 2671 }; 2672 }; 2673 2674 pcie1_default_state: pcie1-default-state { 2675 perst-pins { 2676 pins = "gpio102"; 2677 function = "gpio"; 2678 drive-strength = <2>; 2679 bias-pull-down; 2680 }; 2681 2682 clkreq-pins { 2683 pins = "gpio103"; 2684 function = "pci_e1"; 2685 drive-strength = <2>; 2686 bias-pull-up; 2687 }; 2688 2689 wake-pins { 2690 pins = "gpio104"; 2691 function = "gpio"; 2692 drive-strength = <2>; 2693 bias-pull-up; 2694 }; 2695 }; 2696 }; 2697 2698 remoteproc_mpss: remoteproc@4080000 { 2699 compatible = "qcom,sm8150-mpss-pas"; 2700 reg = <0x0 0x04080000 0x0 0x4040>; 2701 2702 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2703 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2704 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2705 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2706 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2707 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2708 interrupt-names = "wdog", "fatal", "ready", "handover", 2709 "stop-ack", "shutdown-ack"; 2710 2711 clocks = <&rpmhcc RPMH_CXO_CLK>; 2712 clock-names = "xo"; 2713 2714 power-domains = <&rpmhpd SM8150_CX>, 2715 <&rpmhpd SM8150_MSS>; 2716 power-domain-names = "cx", "mss"; 2717 2718 memory-region = <&mpss_mem>; 2719 2720 qcom,qmp = <&aoss_qmp>; 2721 2722 qcom,smem-states = <&modem_smp2p_out 0>; 2723 qcom,smem-state-names = "stop"; 2724 2725 status = "disabled"; 2726 2727 glink-edge { 2728 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2729 label = "modem"; 2730 qcom,remote-pid = <1>; 2731 mboxes = <&apss_shared 12>; 2732 }; 2733 }; 2734 2735 stm@6002000 { 2736 compatible = "arm,coresight-stm", "arm,primecell"; 2737 reg = <0 0x06002000 0 0x1000>, 2738 <0 0x16280000 0 0x180000>; 2739 reg-names = "stm-base", "stm-stimulus-base"; 2740 2741 clocks = <&aoss_qmp>; 2742 clock-names = "apb_pclk"; 2743 2744 out-ports { 2745 port { 2746 stm_out: endpoint { 2747 remote-endpoint = <&funnel0_in7>; 2748 }; 2749 }; 2750 }; 2751 }; 2752 2753 funnel@6041000 { 2754 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2755 reg = <0 0x06041000 0 0x1000>; 2756 2757 clocks = <&aoss_qmp>; 2758 clock-names = "apb_pclk"; 2759 2760 out-ports { 2761 port { 2762 funnel0_out: endpoint { 2763 remote-endpoint = <&merge_funnel_in0>; 2764 }; 2765 }; 2766 }; 2767 2768 in-ports { 2769 #address-cells = <1>; 2770 #size-cells = <0>; 2771 2772 port@7 { 2773 reg = <7>; 2774 funnel0_in7: endpoint { 2775 remote-endpoint = <&stm_out>; 2776 }; 2777 }; 2778 }; 2779 }; 2780 2781 funnel@6042000 { 2782 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2783 reg = <0 0x06042000 0 0x1000>; 2784 2785 clocks = <&aoss_qmp>; 2786 clock-names = "apb_pclk"; 2787 2788 out-ports { 2789 port { 2790 funnel1_out: endpoint { 2791 remote-endpoint = <&merge_funnel_in1>; 2792 }; 2793 }; 2794 }; 2795 2796 in-ports { 2797 #address-cells = <1>; 2798 #size-cells = <0>; 2799 2800 port@4 { 2801 reg = <4>; 2802 funnel1_in4: endpoint { 2803 remote-endpoint = <&swao_replicator_out>; 2804 }; 2805 }; 2806 }; 2807 }; 2808 2809 funnel@6043000 { 2810 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2811 reg = <0 0x06043000 0 0x1000>; 2812 2813 clocks = <&aoss_qmp>; 2814 clock-names = "apb_pclk"; 2815 2816 out-ports { 2817 port { 2818 funnel2_out: endpoint { 2819 remote-endpoint = <&merge_funnel_in2>; 2820 }; 2821 }; 2822 }; 2823 2824 in-ports { 2825 #address-cells = <1>; 2826 #size-cells = <0>; 2827 2828 port@2 { 2829 reg = <2>; 2830 funnel2_in2: endpoint { 2831 remote-endpoint = <&apss_merge_funnel_out>; 2832 }; 2833 }; 2834 }; 2835 }; 2836 2837 funnel@6045000 { 2838 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2839 reg = <0 0x06045000 0 0x1000>; 2840 2841 clocks = <&aoss_qmp>; 2842 clock-names = "apb_pclk"; 2843 2844 out-ports { 2845 port { 2846 merge_funnel_out: endpoint { 2847 remote-endpoint = <&etf_in>; 2848 }; 2849 }; 2850 }; 2851 2852 in-ports { 2853 #address-cells = <1>; 2854 #size-cells = <0>; 2855 2856 port@0 { 2857 reg = <0>; 2858 merge_funnel_in0: endpoint { 2859 remote-endpoint = <&funnel0_out>; 2860 }; 2861 }; 2862 2863 port@1 { 2864 reg = <1>; 2865 merge_funnel_in1: endpoint { 2866 remote-endpoint = <&funnel1_out>; 2867 }; 2868 }; 2869 2870 port@2 { 2871 reg = <2>; 2872 merge_funnel_in2: endpoint { 2873 remote-endpoint = <&funnel2_out>; 2874 }; 2875 }; 2876 }; 2877 }; 2878 2879 replicator@6046000 { 2880 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2881 reg = <0 0x06046000 0 0x1000>; 2882 2883 clocks = <&aoss_qmp>; 2884 clock-names = "apb_pclk"; 2885 2886 out-ports { 2887 #address-cells = <1>; 2888 #size-cells = <0>; 2889 2890 port@0 { 2891 reg = <0>; 2892 replicator_out0: endpoint { 2893 remote-endpoint = <&etr_in>; 2894 }; 2895 }; 2896 2897 port@1 { 2898 reg = <1>; 2899 replicator_out1: endpoint { 2900 remote-endpoint = <&replicator1_in>; 2901 }; 2902 }; 2903 }; 2904 2905 in-ports { 2906 port { 2907 replicator_in0: endpoint { 2908 remote-endpoint = <&etf_out>; 2909 }; 2910 }; 2911 }; 2912 }; 2913 2914 etf@6047000 { 2915 compatible = "arm,coresight-tmc", "arm,primecell"; 2916 reg = <0 0x06047000 0 0x1000>; 2917 2918 clocks = <&aoss_qmp>; 2919 clock-names = "apb_pclk"; 2920 2921 out-ports { 2922 port { 2923 etf_out: endpoint { 2924 remote-endpoint = <&replicator_in0>; 2925 }; 2926 }; 2927 }; 2928 2929 in-ports { 2930 port { 2931 etf_in: endpoint { 2932 remote-endpoint = <&merge_funnel_out>; 2933 }; 2934 }; 2935 }; 2936 }; 2937 2938 etr@6048000 { 2939 compatible = "arm,coresight-tmc", "arm,primecell"; 2940 reg = <0 0x06048000 0 0x1000>; 2941 iommus = <&apps_smmu 0x05e0 0x0>; 2942 2943 clocks = <&aoss_qmp>; 2944 clock-names = "apb_pclk"; 2945 arm,scatter-gather; 2946 2947 in-ports { 2948 port { 2949 etr_in: endpoint { 2950 remote-endpoint = <&replicator_out0>; 2951 }; 2952 }; 2953 }; 2954 }; 2955 2956 replicator@604a000 { 2957 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2958 reg = <0 0x0604a000 0 0x1000>; 2959 2960 clocks = <&aoss_qmp>; 2961 clock-names = "apb_pclk"; 2962 2963 out-ports { 2964 #address-cells = <1>; 2965 #size-cells = <0>; 2966 2967 port@1 { 2968 reg = <1>; 2969 replicator1_out: endpoint { 2970 remote-endpoint = <&swao_funnel_in>; 2971 }; 2972 }; 2973 }; 2974 2975 in-ports { 2976 2977 port { 2978 replicator1_in: endpoint { 2979 remote-endpoint = <&replicator_out1>; 2980 }; 2981 }; 2982 }; 2983 }; 2984 2985 funnel@6b08000 { 2986 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2987 reg = <0 0x06b08000 0 0x1000>; 2988 2989 clocks = <&aoss_qmp>; 2990 clock-names = "apb_pclk"; 2991 2992 out-ports { 2993 port { 2994 swao_funnel_out: endpoint { 2995 remote-endpoint = <&swao_etf_in>; 2996 }; 2997 }; 2998 }; 2999 3000 in-ports { 3001 #address-cells = <1>; 3002 #size-cells = <0>; 3003 3004 port@6 { 3005 reg = <6>; 3006 swao_funnel_in: endpoint { 3007 remote-endpoint = <&replicator1_out>; 3008 }; 3009 }; 3010 }; 3011 }; 3012 3013 etf@6b09000 { 3014 compatible = "arm,coresight-tmc", "arm,primecell"; 3015 reg = <0 0x06b09000 0 0x1000>; 3016 3017 clocks = <&aoss_qmp>; 3018 clock-names = "apb_pclk"; 3019 3020 out-ports { 3021 port { 3022 swao_etf_out: endpoint { 3023 remote-endpoint = <&swao_replicator_in>; 3024 }; 3025 }; 3026 }; 3027 3028 in-ports { 3029 port { 3030 swao_etf_in: endpoint { 3031 remote-endpoint = <&swao_funnel_out>; 3032 }; 3033 }; 3034 }; 3035 }; 3036 3037 replicator@6b0a000 { 3038 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3039 reg = <0 0x06b0a000 0 0x1000>; 3040 3041 clocks = <&aoss_qmp>; 3042 clock-names = "apb_pclk"; 3043 qcom,replicator-loses-context; 3044 3045 out-ports { 3046 port { 3047 swao_replicator_out: endpoint { 3048 remote-endpoint = <&funnel1_in4>; 3049 }; 3050 }; 3051 }; 3052 3053 in-ports { 3054 port { 3055 swao_replicator_in: endpoint { 3056 remote-endpoint = <&swao_etf_out>; 3057 }; 3058 }; 3059 }; 3060 }; 3061 3062 etm@7040000 { 3063 compatible = "arm,coresight-etm4x", "arm,primecell"; 3064 reg = <0 0x07040000 0 0x1000>; 3065 3066 cpu = <&CPU0>; 3067 3068 clocks = <&aoss_qmp>; 3069 clock-names = "apb_pclk"; 3070 arm,coresight-loses-context-with-cpu; 3071 qcom,skip-power-up; 3072 3073 out-ports { 3074 port { 3075 etm0_out: endpoint { 3076 remote-endpoint = <&apss_funnel_in0>; 3077 }; 3078 }; 3079 }; 3080 }; 3081 3082 etm@7140000 { 3083 compatible = "arm,coresight-etm4x", "arm,primecell"; 3084 reg = <0 0x07140000 0 0x1000>; 3085 3086 cpu = <&CPU1>; 3087 3088 clocks = <&aoss_qmp>; 3089 clock-names = "apb_pclk"; 3090 arm,coresight-loses-context-with-cpu; 3091 qcom,skip-power-up; 3092 3093 out-ports { 3094 port { 3095 etm1_out: endpoint { 3096 remote-endpoint = <&apss_funnel_in1>; 3097 }; 3098 }; 3099 }; 3100 }; 3101 3102 etm@7240000 { 3103 compatible = "arm,coresight-etm4x", "arm,primecell"; 3104 reg = <0 0x07240000 0 0x1000>; 3105 3106 cpu = <&CPU2>; 3107 3108 clocks = <&aoss_qmp>; 3109 clock-names = "apb_pclk"; 3110 arm,coresight-loses-context-with-cpu; 3111 qcom,skip-power-up; 3112 3113 out-ports { 3114 port { 3115 etm2_out: endpoint { 3116 remote-endpoint = <&apss_funnel_in2>; 3117 }; 3118 }; 3119 }; 3120 }; 3121 3122 etm@7340000 { 3123 compatible = "arm,coresight-etm4x", "arm,primecell"; 3124 reg = <0 0x07340000 0 0x1000>; 3125 3126 cpu = <&CPU3>; 3127 3128 clocks = <&aoss_qmp>; 3129 clock-names = "apb_pclk"; 3130 arm,coresight-loses-context-with-cpu; 3131 qcom,skip-power-up; 3132 3133 out-ports { 3134 port { 3135 etm3_out: endpoint { 3136 remote-endpoint = <&apss_funnel_in3>; 3137 }; 3138 }; 3139 }; 3140 }; 3141 3142 etm@7440000 { 3143 compatible = "arm,coresight-etm4x", "arm,primecell"; 3144 reg = <0 0x07440000 0 0x1000>; 3145 3146 cpu = <&CPU4>; 3147 3148 clocks = <&aoss_qmp>; 3149 clock-names = "apb_pclk"; 3150 arm,coresight-loses-context-with-cpu; 3151 qcom,skip-power-up; 3152 3153 out-ports { 3154 port { 3155 etm4_out: endpoint { 3156 remote-endpoint = <&apss_funnel_in4>; 3157 }; 3158 }; 3159 }; 3160 }; 3161 3162 etm@7540000 { 3163 compatible = "arm,coresight-etm4x", "arm,primecell"; 3164 reg = <0 0x07540000 0 0x1000>; 3165 3166 cpu = <&CPU5>; 3167 3168 clocks = <&aoss_qmp>; 3169 clock-names = "apb_pclk"; 3170 arm,coresight-loses-context-with-cpu; 3171 qcom,skip-power-up; 3172 3173 out-ports { 3174 port { 3175 etm5_out: endpoint { 3176 remote-endpoint = <&apss_funnel_in5>; 3177 }; 3178 }; 3179 }; 3180 }; 3181 3182 etm@7640000 { 3183 compatible = "arm,coresight-etm4x", "arm,primecell"; 3184 reg = <0 0x07640000 0 0x1000>; 3185 3186 cpu = <&CPU6>; 3187 3188 clocks = <&aoss_qmp>; 3189 clock-names = "apb_pclk"; 3190 arm,coresight-loses-context-with-cpu; 3191 qcom,skip-power-up; 3192 3193 out-ports { 3194 port { 3195 etm6_out: endpoint { 3196 remote-endpoint = <&apss_funnel_in6>; 3197 }; 3198 }; 3199 }; 3200 }; 3201 3202 etm@7740000 { 3203 compatible = "arm,coresight-etm4x", "arm,primecell"; 3204 reg = <0 0x07740000 0 0x1000>; 3205 3206 cpu = <&CPU7>; 3207 3208 clocks = <&aoss_qmp>; 3209 clock-names = "apb_pclk"; 3210 arm,coresight-loses-context-with-cpu; 3211 qcom,skip-power-up; 3212 3213 out-ports { 3214 port { 3215 etm7_out: endpoint { 3216 remote-endpoint = <&apss_funnel_in7>; 3217 }; 3218 }; 3219 }; 3220 }; 3221 3222 funnel@7800000 { /* APSS Funnel */ 3223 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3224 reg = <0 0x07800000 0 0x1000>; 3225 3226 clocks = <&aoss_qmp>; 3227 clock-names = "apb_pclk"; 3228 3229 out-ports { 3230 port { 3231 apss_funnel_out: endpoint { 3232 remote-endpoint = <&apss_merge_funnel_in>; 3233 }; 3234 }; 3235 }; 3236 3237 in-ports { 3238 #address-cells = <1>; 3239 #size-cells = <0>; 3240 3241 port@0 { 3242 reg = <0>; 3243 apss_funnel_in0: endpoint { 3244 remote-endpoint = <&etm0_out>; 3245 }; 3246 }; 3247 3248 port@1 { 3249 reg = <1>; 3250 apss_funnel_in1: endpoint { 3251 remote-endpoint = <&etm1_out>; 3252 }; 3253 }; 3254 3255 port@2 { 3256 reg = <2>; 3257 apss_funnel_in2: endpoint { 3258 remote-endpoint = <&etm2_out>; 3259 }; 3260 }; 3261 3262 port@3 { 3263 reg = <3>; 3264 apss_funnel_in3: endpoint { 3265 remote-endpoint = <&etm3_out>; 3266 }; 3267 }; 3268 3269 port@4 { 3270 reg = <4>; 3271 apss_funnel_in4: endpoint { 3272 remote-endpoint = <&etm4_out>; 3273 }; 3274 }; 3275 3276 port@5 { 3277 reg = <5>; 3278 apss_funnel_in5: endpoint { 3279 remote-endpoint = <&etm5_out>; 3280 }; 3281 }; 3282 3283 port@6 { 3284 reg = <6>; 3285 apss_funnel_in6: endpoint { 3286 remote-endpoint = <&etm6_out>; 3287 }; 3288 }; 3289 3290 port@7 { 3291 reg = <7>; 3292 apss_funnel_in7: endpoint { 3293 remote-endpoint = <&etm7_out>; 3294 }; 3295 }; 3296 }; 3297 }; 3298 3299 funnel@7810000 { 3300 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3301 reg = <0 0x07810000 0 0x1000>; 3302 3303 clocks = <&aoss_qmp>; 3304 clock-names = "apb_pclk"; 3305 3306 out-ports { 3307 port { 3308 apss_merge_funnel_out: endpoint { 3309 remote-endpoint = <&funnel2_in2>; 3310 }; 3311 }; 3312 }; 3313 3314 in-ports { 3315 port { 3316 apss_merge_funnel_in: endpoint { 3317 remote-endpoint = <&apss_funnel_out>; 3318 }; 3319 }; 3320 }; 3321 }; 3322 3323 remoteproc_cdsp: remoteproc@8300000 { 3324 compatible = "qcom,sm8150-cdsp-pas"; 3325 reg = <0x0 0x08300000 0x0 0x4040>; 3326 3327 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3328 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3329 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3330 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3331 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3332 interrupt-names = "wdog", "fatal", "ready", 3333 "handover", "stop-ack"; 3334 3335 clocks = <&rpmhcc RPMH_CXO_CLK>; 3336 clock-names = "xo"; 3337 3338 power-domains = <&rpmhpd SM8150_CX>; 3339 3340 memory-region = <&cdsp_mem>; 3341 3342 qcom,qmp = <&aoss_qmp>; 3343 3344 qcom,smem-states = <&cdsp_smp2p_out 0>; 3345 qcom,smem-state-names = "stop"; 3346 3347 status = "disabled"; 3348 3349 glink-edge { 3350 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 3351 label = "cdsp"; 3352 qcom,remote-pid = <5>; 3353 mboxes = <&apss_shared 4>; 3354 3355 fastrpc { 3356 compatible = "qcom,fastrpc"; 3357 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3358 label = "cdsp"; 3359 qcom,non-secure-domain; 3360 #address-cells = <1>; 3361 #size-cells = <0>; 3362 3363 compute-cb@1 { 3364 compatible = "qcom,fastrpc-compute-cb"; 3365 reg = <1>; 3366 iommus = <&apps_smmu 0x1001 0x0460>; 3367 }; 3368 3369 compute-cb@2 { 3370 compatible = "qcom,fastrpc-compute-cb"; 3371 reg = <2>; 3372 iommus = <&apps_smmu 0x1002 0x0460>; 3373 }; 3374 3375 compute-cb@3 { 3376 compatible = "qcom,fastrpc-compute-cb"; 3377 reg = <3>; 3378 iommus = <&apps_smmu 0x1003 0x0460>; 3379 }; 3380 3381 compute-cb@4 { 3382 compatible = "qcom,fastrpc-compute-cb"; 3383 reg = <4>; 3384 iommus = <&apps_smmu 0x1004 0x0460>; 3385 }; 3386 3387 compute-cb@5 { 3388 compatible = "qcom,fastrpc-compute-cb"; 3389 reg = <5>; 3390 iommus = <&apps_smmu 0x1005 0x0460>; 3391 }; 3392 3393 compute-cb@6 { 3394 compatible = "qcom,fastrpc-compute-cb"; 3395 reg = <6>; 3396 iommus = <&apps_smmu 0x1006 0x0460>; 3397 }; 3398 3399 compute-cb@7 { 3400 compatible = "qcom,fastrpc-compute-cb"; 3401 reg = <7>; 3402 iommus = <&apps_smmu 0x1007 0x0460>; 3403 }; 3404 3405 compute-cb@8 { 3406 compatible = "qcom,fastrpc-compute-cb"; 3407 reg = <8>; 3408 iommus = <&apps_smmu 0x1008 0x0460>; 3409 }; 3410 3411 /* note: secure cb9 in downstream */ 3412 }; 3413 }; 3414 }; 3415 3416 usb_1_hsphy: phy@88e2000 { 3417 compatible = "qcom,sm8150-usb-hs-phy", 3418 "qcom,usb-snps-hs-7nm-phy"; 3419 reg = <0 0x088e2000 0 0x400>; 3420 status = "disabled"; 3421 #phy-cells = <0>; 3422 3423 clocks = <&rpmhcc RPMH_CXO_CLK>; 3424 clock-names = "ref"; 3425 3426 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3427 }; 3428 3429 usb_2_hsphy: phy@88e3000 { 3430 compatible = "qcom,sm8150-usb-hs-phy", 3431 "qcom,usb-snps-hs-7nm-phy"; 3432 reg = <0 0x088e3000 0 0x400>; 3433 status = "disabled"; 3434 #phy-cells = <0>; 3435 3436 clocks = <&rpmhcc RPMH_CXO_CLK>; 3437 clock-names = "ref"; 3438 3439 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3440 }; 3441 3442 usb_1_qmpphy: phy@88e9000 { 3443 compatible = "qcom,sm8150-qmp-usb3-phy"; 3444 reg = <0 0x088e9000 0 0x18c>, 3445 <0 0x088e8000 0 0x10>; 3446 status = "disabled"; 3447 #address-cells = <2>; 3448 #size-cells = <2>; 3449 ranges; 3450 3451 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3452 <&rpmhcc RPMH_CXO_CLK>, 3453 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3454 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3455 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3456 3457 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3458 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3459 reset-names = "phy", "common"; 3460 3461 usb_1_ssphy: phy@88e9200 { 3462 reg = <0 0x088e9200 0 0x200>, 3463 <0 0x088e9400 0 0x200>, 3464 <0 0x088e9c00 0 0x218>, 3465 <0 0x088e9600 0 0x200>, 3466 <0 0x088e9800 0 0x200>, 3467 <0 0x088e9a00 0 0x100>; 3468 #clock-cells = <0>; 3469 #phy-cells = <0>; 3470 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3471 clock-names = "pipe0"; 3472 clock-output-names = "usb3_phy_pipe_clk_src"; 3473 }; 3474 }; 3475 3476 usb_2_qmpphy: phy@88eb000 { 3477 compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 3478 reg = <0 0x088eb000 0 0x200>; 3479 status = "disabled"; 3480 #address-cells = <2>; 3481 #size-cells = <2>; 3482 ranges; 3483 3484 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3485 <&rpmhcc RPMH_CXO_CLK>, 3486 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3487 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3488 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3489 3490 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3491 <&gcc GCC_USB3_PHY_SEC_BCR>; 3492 reset-names = "phy", "common"; 3493 3494 usb_2_ssphy: phy@88eb200 { 3495 reg = <0 0x088eb200 0 0x200>, 3496 <0 0x088eb400 0 0x200>, 3497 <0 0x088eb800 0 0x800>, 3498 <0 0x088eb600 0 0x200>; 3499 #clock-cells = <0>; 3500 #phy-cells = <0>; 3501 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3502 clock-names = "pipe0"; 3503 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3504 }; 3505 }; 3506 3507 sdhc_2: mmc@8804000 { 3508 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3509 reg = <0 0x08804000 0 0x1000>; 3510 3511 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3512 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3513 interrupt-names = "hc_irq", "pwr_irq"; 3514 3515 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3516 <&gcc GCC_SDCC2_APPS_CLK>, 3517 <&rpmhcc RPMH_CXO_CLK>; 3518 clock-names = "iface", "core", "xo"; 3519 iommus = <&apps_smmu 0x6a0 0x0>; 3520 qcom,dll-config = <0x0007642c>; 3521 qcom,ddr-config = <0x80040868>; 3522 power-domains = <&rpmhpd 0>; 3523 operating-points-v2 = <&sdhc2_opp_table>; 3524 3525 status = "disabled"; 3526 3527 sdhc2_opp_table: opp-table { 3528 compatible = "operating-points-v2"; 3529 3530 opp-19200000 { 3531 opp-hz = /bits/ 64 <19200000>; 3532 required-opps = <&rpmhpd_opp_min_svs>; 3533 }; 3534 3535 opp-50000000 { 3536 opp-hz = /bits/ 64 <50000000>; 3537 required-opps = <&rpmhpd_opp_low_svs>; 3538 }; 3539 3540 opp-100000000 { 3541 opp-hz = /bits/ 64 <100000000>; 3542 required-opps = <&rpmhpd_opp_svs>; 3543 }; 3544 3545 opp-202000000 { 3546 opp-hz = /bits/ 64 <202000000>; 3547 required-opps = <&rpmhpd_opp_svs_l1>; 3548 }; 3549 }; 3550 }; 3551 3552 dc_noc: interconnect@9160000 { 3553 compatible = "qcom,sm8150-dc-noc"; 3554 reg = <0 0x09160000 0 0x3200>; 3555 #interconnect-cells = <2>; 3556 qcom,bcm-voters = <&apps_bcm_voter>; 3557 }; 3558 3559 gem_noc: interconnect@9680000 { 3560 compatible = "qcom,sm8150-gem-noc"; 3561 reg = <0 0x09680000 0 0x3e200>; 3562 #interconnect-cells = <2>; 3563 qcom,bcm-voters = <&apps_bcm_voter>; 3564 }; 3565 3566 usb_1: usb@a6f8800 { 3567 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3568 reg = <0 0x0a6f8800 0 0x400>; 3569 status = "disabled"; 3570 #address-cells = <2>; 3571 #size-cells = <2>; 3572 ranges; 3573 dma-ranges; 3574 3575 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3576 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3577 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3578 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3579 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3580 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3581 clock-names = "cfg_noc", 3582 "core", 3583 "iface", 3584 "sleep", 3585 "mock_utmi", 3586 "xo"; 3587 3588 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3589 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3590 assigned-clock-rates = <19200000>, <200000000>; 3591 3592 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3593 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 3594 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 3595 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 3596 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3597 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3598 3599 power-domains = <&gcc USB30_PRIM_GDSC>; 3600 3601 resets = <&gcc GCC_USB30_PRIM_BCR>; 3602 3603 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 3604 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 3605 interconnect-names = "usb-ddr", "apps-usb"; 3606 3607 usb_1_dwc3: usb@a600000 { 3608 compatible = "snps,dwc3"; 3609 reg = <0 0x0a600000 0 0xcd00>; 3610 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3611 iommus = <&apps_smmu 0x140 0>; 3612 snps,dis_u2_susphy_quirk; 3613 snps,dis_enblslpm_quirk; 3614 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3615 phy-names = "usb2-phy", "usb3-phy"; 3616 }; 3617 }; 3618 3619 usb_2: usb@a8f8800 { 3620 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3621 reg = <0 0x0a8f8800 0 0x400>; 3622 status = "disabled"; 3623 #address-cells = <2>; 3624 #size-cells = <2>; 3625 ranges; 3626 dma-ranges; 3627 3628 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3629 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3630 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3631 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3632 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3633 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3634 clock-names = "cfg_noc", 3635 "core", 3636 "iface", 3637 "sleep", 3638 "mock_utmi", 3639 "xo"; 3640 3641 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3642 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3643 assigned-clock-rates = <19200000>, <200000000>; 3644 3645 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3646 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, 3647 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 3648 <&pdc 11 IRQ_TYPE_EDGE_BOTH>; 3649 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3650 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3651 3652 power-domains = <&gcc USB30_SEC_GDSC>; 3653 3654 resets = <&gcc GCC_USB30_SEC_BCR>; 3655 3656 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 3657 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 3658 interconnect-names = "usb-ddr", "apps-usb"; 3659 3660 usb_2_dwc3: usb@a800000 { 3661 compatible = "snps,dwc3"; 3662 reg = <0 0x0a800000 0 0xcd00>; 3663 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3664 iommus = <&apps_smmu 0x160 0>; 3665 snps,dis_u2_susphy_quirk; 3666 snps,dis_enblslpm_quirk; 3667 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3668 phy-names = "usb2-phy", "usb3-phy"; 3669 }; 3670 }; 3671 3672 camnoc_virt: interconnect@ac00000 { 3673 compatible = "qcom,sm8150-camnoc-virt"; 3674 reg = <0 0x0ac00000 0 0x1000>; 3675 #interconnect-cells = <2>; 3676 qcom,bcm-voters = <&apps_bcm_voter>; 3677 }; 3678 3679 mdss: display-subsystem@ae00000 { 3680 compatible = "qcom,sm8150-mdss"; 3681 reg = <0 0x0ae00000 0 0x1000>; 3682 reg-names = "mdss"; 3683 3684 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 3685 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 3686 interconnect-names = "mdp0-mem", "mdp1-mem"; 3687 3688 power-domains = <&dispcc MDSS_GDSC>; 3689 3690 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3691 <&gcc GCC_DISP_HF_AXI_CLK>, 3692 <&gcc GCC_DISP_SF_AXI_CLK>, 3693 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3694 clock-names = "iface", "bus", "nrt_bus", "core"; 3695 3696 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3697 interrupt-controller; 3698 #interrupt-cells = <1>; 3699 3700 iommus = <&apps_smmu 0x800 0x420>; 3701 3702 status = "disabled"; 3703 3704 #address-cells = <2>; 3705 #size-cells = <2>; 3706 ranges; 3707 3708 mdss_mdp: display-controller@ae01000 { 3709 compatible = "qcom,sm8150-dpu"; 3710 reg = <0 0x0ae01000 0 0x8f000>, 3711 <0 0x0aeb0000 0 0x2008>; 3712 reg-names = "mdp", "vbif"; 3713 3714 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3715 <&gcc GCC_DISP_HF_AXI_CLK>, 3716 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3717 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3718 clock-names = "iface", "bus", "core", "vsync"; 3719 3720 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3721 assigned-clock-rates = <19200000>; 3722 3723 operating-points-v2 = <&mdp_opp_table>; 3724 power-domains = <&rpmhpd SM8150_MMCX>; 3725 3726 interrupt-parent = <&mdss>; 3727 interrupts = <0>; 3728 3729 ports { 3730 #address-cells = <1>; 3731 #size-cells = <0>; 3732 3733 port@0 { 3734 reg = <0>; 3735 dpu_intf1_out: endpoint { 3736 remote-endpoint = <&mdss_dsi0_in>; 3737 }; 3738 }; 3739 3740 port@1 { 3741 reg = <1>; 3742 dpu_intf2_out: endpoint { 3743 remote-endpoint = <&mdss_dsi1_in>; 3744 }; 3745 }; 3746 }; 3747 3748 mdp_opp_table: opp-table { 3749 compatible = "operating-points-v2"; 3750 3751 opp-171428571 { 3752 opp-hz = /bits/ 64 <171428571>; 3753 required-opps = <&rpmhpd_opp_low_svs>; 3754 }; 3755 3756 opp-300000000 { 3757 opp-hz = /bits/ 64 <300000000>; 3758 required-opps = <&rpmhpd_opp_svs>; 3759 }; 3760 3761 opp-345000000 { 3762 opp-hz = /bits/ 64 <345000000>; 3763 required-opps = <&rpmhpd_opp_svs_l1>; 3764 }; 3765 3766 opp-460000000 { 3767 opp-hz = /bits/ 64 <460000000>; 3768 required-opps = <&rpmhpd_opp_nom>; 3769 }; 3770 }; 3771 }; 3772 3773 mdss_dsi0: dsi@ae94000 { 3774 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3775 reg = <0 0x0ae94000 0 0x400>; 3776 reg-names = "dsi_ctrl"; 3777 3778 interrupt-parent = <&mdss>; 3779 interrupts = <4>; 3780 3781 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3782 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3783 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3784 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3785 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3786 <&gcc GCC_DISP_HF_AXI_CLK>; 3787 clock-names = "byte", 3788 "byte_intf", 3789 "pixel", 3790 "core", 3791 "iface", 3792 "bus"; 3793 3794 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3795 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3796 assigned-clock-parents = <&mdss_dsi0_phy 0>, 3797 <&mdss_dsi0_phy 1>; 3798 3799 operating-points-v2 = <&dsi_opp_table>; 3800 power-domains = <&rpmhpd SM8150_MMCX>; 3801 3802 phys = <&mdss_dsi0_phy>; 3803 3804 status = "disabled"; 3805 3806 #address-cells = <1>; 3807 #size-cells = <0>; 3808 3809 ports { 3810 #address-cells = <1>; 3811 #size-cells = <0>; 3812 3813 port@0 { 3814 reg = <0>; 3815 mdss_dsi0_in: endpoint { 3816 remote-endpoint = <&dpu_intf1_out>; 3817 }; 3818 }; 3819 3820 port@1 { 3821 reg = <1>; 3822 mdss_dsi0_out: endpoint { 3823 }; 3824 }; 3825 }; 3826 3827 dsi_opp_table: opp-table { 3828 compatible = "operating-points-v2"; 3829 3830 opp-187500000 { 3831 opp-hz = /bits/ 64 <187500000>; 3832 required-opps = <&rpmhpd_opp_low_svs>; 3833 }; 3834 3835 opp-300000000 { 3836 opp-hz = /bits/ 64 <300000000>; 3837 required-opps = <&rpmhpd_opp_svs>; 3838 }; 3839 3840 opp-358000000 { 3841 opp-hz = /bits/ 64 <358000000>; 3842 required-opps = <&rpmhpd_opp_svs_l1>; 3843 }; 3844 }; 3845 }; 3846 3847 mdss_dsi0_phy: phy@ae94400 { 3848 compatible = "qcom,dsi-phy-7nm-8150"; 3849 reg = <0 0x0ae94400 0 0x200>, 3850 <0 0x0ae94600 0 0x280>, 3851 <0 0x0ae94900 0 0x260>; 3852 reg-names = "dsi_phy", 3853 "dsi_phy_lane", 3854 "dsi_pll"; 3855 3856 #clock-cells = <1>; 3857 #phy-cells = <0>; 3858 3859 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3860 <&rpmhcc RPMH_CXO_CLK>; 3861 clock-names = "iface", "ref"; 3862 3863 status = "disabled"; 3864 }; 3865 3866 mdss_dsi1: dsi@ae96000 { 3867 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3868 reg = <0 0x0ae96000 0 0x400>; 3869 reg-names = "dsi_ctrl"; 3870 3871 interrupt-parent = <&mdss>; 3872 interrupts = <5>; 3873 3874 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3875 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3876 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3877 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3878 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3879 <&gcc GCC_DISP_HF_AXI_CLK>; 3880 clock-names = "byte", 3881 "byte_intf", 3882 "pixel", 3883 "core", 3884 "iface", 3885 "bus"; 3886 3887 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3888 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3889 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3890 <&mdss_dsi1_phy 1>; 3891 3892 operating-points-v2 = <&dsi_opp_table>; 3893 power-domains = <&rpmhpd SM8150_MMCX>; 3894 3895 phys = <&mdss_dsi1_phy>; 3896 3897 status = "disabled"; 3898 3899 #address-cells = <1>; 3900 #size-cells = <0>; 3901 3902 ports { 3903 #address-cells = <1>; 3904 #size-cells = <0>; 3905 3906 port@0 { 3907 reg = <0>; 3908 mdss_dsi1_in: endpoint { 3909 remote-endpoint = <&dpu_intf2_out>; 3910 }; 3911 }; 3912 3913 port@1 { 3914 reg = <1>; 3915 mdss_dsi1_out: endpoint { 3916 }; 3917 }; 3918 }; 3919 }; 3920 3921 mdss_dsi1_phy: phy@ae96400 { 3922 compatible = "qcom,dsi-phy-7nm-8150"; 3923 reg = <0 0x0ae96400 0 0x200>, 3924 <0 0x0ae96600 0 0x280>, 3925 <0 0x0ae96900 0 0x260>; 3926 reg-names = "dsi_phy", 3927 "dsi_phy_lane", 3928 "dsi_pll"; 3929 3930 #clock-cells = <1>; 3931 #phy-cells = <0>; 3932 3933 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3934 <&rpmhcc RPMH_CXO_CLK>; 3935 clock-names = "iface", "ref"; 3936 3937 status = "disabled"; 3938 }; 3939 }; 3940 3941 dispcc: clock-controller@af00000 { 3942 compatible = "qcom,sm8150-dispcc"; 3943 reg = <0 0x0af00000 0 0x10000>; 3944 clocks = <&rpmhcc RPMH_CXO_CLK>, 3945 <&mdss_dsi0_phy 0>, 3946 <&mdss_dsi0_phy 1>, 3947 <&mdss_dsi1_phy 0>, 3948 <&mdss_dsi1_phy 1>, 3949 <0>, 3950 <0>; 3951 clock-names = "bi_tcxo", 3952 "dsi0_phy_pll_out_byteclk", 3953 "dsi0_phy_pll_out_dsiclk", 3954 "dsi1_phy_pll_out_byteclk", 3955 "dsi1_phy_pll_out_dsiclk", 3956 "dp_phy_pll_link_clk", 3957 "dp_phy_pll_vco_div_clk"; 3958 power-domains = <&rpmhpd SM8150_MMCX>; 3959 required-opps = <&rpmhpd_opp_low_svs>; 3960 #clock-cells = <1>; 3961 #reset-cells = <1>; 3962 #power-domain-cells = <1>; 3963 }; 3964 3965 pdc: interrupt-controller@b220000 { 3966 compatible = "qcom,sm8150-pdc", "qcom,pdc"; 3967 reg = <0 0x0b220000 0 0x30000>; 3968 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3969 <125 63 1>; 3970 #interrupt-cells = <2>; 3971 interrupt-parent = <&intc>; 3972 interrupt-controller; 3973 }; 3974 3975 aoss_qmp: power-management@c300000 { 3976 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 3977 reg = <0x0 0x0c300000 0x0 0x400>; 3978 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3979 mboxes = <&apss_shared 0>; 3980 3981 #clock-cells = <0>; 3982 }; 3983 3984 sram@c3f0000 { 3985 compatible = "qcom,rpmh-stats"; 3986 reg = <0 0x0c3f0000 0 0x400>; 3987 }; 3988 3989 tsens0: thermal-sensor@c263000 { 3990 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3991 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3992 <0 0x0c222000 0 0x1ff>; /* SROT */ 3993 #qcom,sensors = <16>; 3994 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3995 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3996 interrupt-names = "uplow", "critical"; 3997 #thermal-sensor-cells = <1>; 3998 }; 3999 4000 tsens1: thermal-sensor@c265000 { 4001 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 4002 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4003 <0 0x0c223000 0 0x1ff>; /* SROT */ 4004 #qcom,sensors = <8>; 4005 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4006 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4007 interrupt-names = "uplow", "critical"; 4008 #thermal-sensor-cells = <1>; 4009 }; 4010 4011 spmi_bus: spmi@c440000 { 4012 compatible = "qcom,spmi-pmic-arb"; 4013 reg = <0x0 0x0c440000 0x0 0x0001100>, 4014 <0x0 0x0c600000 0x0 0x2000000>, 4015 <0x0 0x0e600000 0x0 0x0100000>, 4016 <0x0 0x0e700000 0x0 0x00a0000>, 4017 <0x0 0x0c40a000 0x0 0x0026000>; 4018 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4019 interrupt-names = "periph_irq"; 4020 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 4021 qcom,ee = <0>; 4022 qcom,channel = <0>; 4023 #address-cells = <2>; 4024 #size-cells = <0>; 4025 interrupt-controller; 4026 #interrupt-cells = <4>; 4027 }; 4028 4029 apps_smmu: iommu@15000000 { 4030 compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4031 reg = <0 0x15000000 0 0x100000>; 4032 #iommu-cells = <2>; 4033 #global-interrupts = <1>; 4034 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4035 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4036 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4037 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4038 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4039 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4040 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4041 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4042 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4043 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4044 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4045 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4046 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4047 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4048 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4049 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4050 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4051 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4052 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4053 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4054 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4055 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4056 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4057 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4058 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4059 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4060 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4061 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4062 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4063 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4064 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4065 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4066 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4067 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4068 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4069 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4070 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4071 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4072 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4073 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4074 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4075 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4076 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4077 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4079 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4080 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4083 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4084 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4092 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4098 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4102 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4103 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4104 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4105 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4106 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4107 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4108 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4109 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4110 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4111 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4113 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4114 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 4115 }; 4116 4117 remoteproc_adsp: remoteproc@17300000 { 4118 compatible = "qcom,sm8150-adsp-pas"; 4119 reg = <0x0 0x17300000 0x0 0x4040>; 4120 4121 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 4122 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4123 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4124 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4125 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 4126 interrupt-names = "wdog", "fatal", "ready", 4127 "handover", "stop-ack"; 4128 4129 clocks = <&rpmhcc RPMH_CXO_CLK>; 4130 clock-names = "xo"; 4131 4132 power-domains = <&rpmhpd SM8150_CX>; 4133 4134 memory-region = <&adsp_mem>; 4135 4136 qcom,qmp = <&aoss_qmp>; 4137 4138 qcom,smem-states = <&adsp_smp2p_out 0>; 4139 qcom,smem-state-names = "stop"; 4140 4141 status = "disabled"; 4142 4143 glink-edge { 4144 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 4145 label = "lpass"; 4146 qcom,remote-pid = <2>; 4147 mboxes = <&apss_shared 8>; 4148 4149 fastrpc { 4150 compatible = "qcom,fastrpc"; 4151 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4152 label = "adsp"; 4153 qcom,non-secure-domain; 4154 #address-cells = <1>; 4155 #size-cells = <0>; 4156 4157 compute-cb@3 { 4158 compatible = "qcom,fastrpc-compute-cb"; 4159 reg = <3>; 4160 iommus = <&apps_smmu 0x1b23 0x0>; 4161 }; 4162 4163 compute-cb@4 { 4164 compatible = "qcom,fastrpc-compute-cb"; 4165 reg = <4>; 4166 iommus = <&apps_smmu 0x1b24 0x0>; 4167 }; 4168 4169 compute-cb@5 { 4170 compatible = "qcom,fastrpc-compute-cb"; 4171 reg = <5>; 4172 iommus = <&apps_smmu 0x1b25 0x0>; 4173 }; 4174 }; 4175 }; 4176 }; 4177 4178 intc: interrupt-controller@17a00000 { 4179 compatible = "arm,gic-v3"; 4180 interrupt-controller; 4181 #interrupt-cells = <3>; 4182 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4183 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4184 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4185 }; 4186 4187 apss_shared: mailbox@17c00000 { 4188 compatible = "qcom,sm8150-apss-shared", 4189 "qcom,sdm845-apss-shared"; 4190 reg = <0x0 0x17c00000 0x0 0x1000>; 4191 #mbox-cells = <1>; 4192 }; 4193 4194 watchdog@17c10000 { 4195 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 4196 reg = <0 0x17c10000 0 0x1000>; 4197 clocks = <&sleep_clk>; 4198 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 4199 }; 4200 4201 timer@17c20000 { 4202 #address-cells = <1>; 4203 #size-cells = <1>; 4204 ranges = <0 0 0 0x20000000>; 4205 compatible = "arm,armv7-timer-mem"; 4206 reg = <0x0 0x17c20000 0x0 0x1000>; 4207 clock-frequency = <19200000>; 4208 4209 frame@17c21000 { 4210 frame-number = <0>; 4211 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4212 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4213 reg = <0x17c21000 0x1000>, 4214 <0x17c22000 0x1000>; 4215 }; 4216 4217 frame@17c23000 { 4218 frame-number = <1>; 4219 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4220 reg = <0x17c23000 0x1000>; 4221 status = "disabled"; 4222 }; 4223 4224 frame@17c25000 { 4225 frame-number = <2>; 4226 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4227 reg = <0x17c25000 0x1000>; 4228 status = "disabled"; 4229 }; 4230 4231 frame@17c27000 { 4232 frame-number = <3>; 4233 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4234 reg = <0x17c26000 0x1000>; 4235 status = "disabled"; 4236 }; 4237 4238 frame@17c29000 { 4239 frame-number = <4>; 4240 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4241 reg = <0x17c29000 0x1000>; 4242 status = "disabled"; 4243 }; 4244 4245 frame@17c2b000 { 4246 frame-number = <5>; 4247 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4248 reg = <0x17c2b000 0x1000>; 4249 status = "disabled"; 4250 }; 4251 4252 frame@17c2d000 { 4253 frame-number = <6>; 4254 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4255 reg = <0x17c2d000 0x1000>; 4256 status = "disabled"; 4257 }; 4258 }; 4259 4260 apps_rsc: rsc@18200000 { 4261 label = "apps_rsc"; 4262 compatible = "qcom,rpmh-rsc"; 4263 reg = <0x0 0x18200000 0x0 0x10000>, 4264 <0x0 0x18210000 0x0 0x10000>, 4265 <0x0 0x18220000 0x0 0x10000>; 4266 reg-names = "drv-0", "drv-1", "drv-2"; 4267 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4268 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4269 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4270 qcom,tcs-offset = <0xd00>; 4271 qcom,drv-id = <2>; 4272 qcom,tcs-config = <ACTIVE_TCS 2>, 4273 <SLEEP_TCS 3>, 4274 <WAKE_TCS 3>, 4275 <CONTROL_TCS 1>; 4276 power-domains = <&CLUSTER_PD>; 4277 4278 rpmhcc: clock-controller { 4279 compatible = "qcom,sm8150-rpmh-clk"; 4280 #clock-cells = <1>; 4281 clock-names = "xo"; 4282 clocks = <&xo_board>; 4283 }; 4284 4285 rpmhpd: power-controller { 4286 compatible = "qcom,sm8150-rpmhpd"; 4287 #power-domain-cells = <1>; 4288 operating-points-v2 = <&rpmhpd_opp_table>; 4289 4290 rpmhpd_opp_table: opp-table { 4291 compatible = "operating-points-v2"; 4292 4293 rpmhpd_opp_ret: opp1 { 4294 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4295 }; 4296 4297 rpmhpd_opp_min_svs: opp2 { 4298 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4299 }; 4300 4301 rpmhpd_opp_low_svs: opp3 { 4302 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4303 }; 4304 4305 rpmhpd_opp_svs: opp4 { 4306 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4307 }; 4308 4309 rpmhpd_opp_svs_l1: opp5 { 4310 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4311 }; 4312 4313 rpmhpd_opp_svs_l2: opp6 { 4314 opp-level = <224>; 4315 }; 4316 4317 rpmhpd_opp_nom: opp7 { 4318 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4319 }; 4320 4321 rpmhpd_opp_nom_l1: opp8 { 4322 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4323 }; 4324 4325 rpmhpd_opp_nom_l2: opp9 { 4326 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4327 }; 4328 4329 rpmhpd_opp_turbo: opp10 { 4330 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4331 }; 4332 4333 rpmhpd_opp_turbo_l1: opp11 { 4334 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4335 }; 4336 }; 4337 }; 4338 4339 apps_bcm_voter: bcm-voter { 4340 compatible = "qcom,bcm-voter"; 4341 }; 4342 }; 4343 4344 osm_l3: interconnect@18321000 { 4345 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4346 reg = <0 0x18321000 0 0x1400>; 4347 4348 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4349 clock-names = "xo", "alternate"; 4350 4351 #interconnect-cells = <1>; 4352 }; 4353 4354 cpufreq_hw: cpufreq@18323000 { 4355 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw"; 4356 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 4357 <0 0x18327800 0 0x1400>; 4358 reg-names = "freq-domain0", "freq-domain1", 4359 "freq-domain2"; 4360 4361 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4362 clock-names = "xo", "alternate"; 4363 4364 #freq-domain-cells = <1>; 4365 #clock-cells = <1>; 4366 }; 4367 4368 lmh_cluster1: lmh@18350800 { 4369 compatible = "qcom,sm8150-lmh"; 4370 reg = <0 0x18350800 0 0x400>; 4371 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 4372 cpus = <&CPU4>; 4373 qcom,lmh-temp-arm-millicelsius = <60000>; 4374 qcom,lmh-temp-low-millicelsius = <84500>; 4375 qcom,lmh-temp-high-millicelsius = <85000>; 4376 interrupt-controller; 4377 #interrupt-cells = <1>; 4378 }; 4379 4380 lmh_cluster0: lmh@18358800 { 4381 compatible = "qcom,sm8150-lmh"; 4382 reg = <0 0x18358800 0 0x400>; 4383 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4384 cpus = <&CPU0>; 4385 qcom,lmh-temp-arm-millicelsius = <60000>; 4386 qcom,lmh-temp-low-millicelsius = <84500>; 4387 qcom,lmh-temp-high-millicelsius = <85000>; 4388 interrupt-controller; 4389 #interrupt-cells = <1>; 4390 }; 4391 4392 wifi: wifi@18800000 { 4393 compatible = "qcom,wcn3990-wifi"; 4394 reg = <0 0x18800000 0 0x800000>; 4395 reg-names = "membase"; 4396 memory-region = <&wlan_mem>; 4397 clock-names = "cxo_ref_clk_pin", "qdss"; 4398 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 4399 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4400 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4401 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4402 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4403 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4404 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4405 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4406 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4407 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4408 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4409 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4410 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4411 iommus = <&apps_smmu 0x0640 0x1>; 4412 status = "disabled"; 4413 }; 4414 }; 4415 4416 timer { 4417 compatible = "arm,armv8-timer"; 4418 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4419 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4420 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4421 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4422 }; 4423 4424 thermal-zones { 4425 cpu0-thermal { 4426 polling-delay-passive = <250>; 4427 polling-delay = <1000>; 4428 4429 thermal-sensors = <&tsens0 1>; 4430 4431 trips { 4432 cpu0_alert0: trip-point0 { 4433 temperature = <90000>; 4434 hysteresis = <2000>; 4435 type = "passive"; 4436 }; 4437 4438 cpu0_alert1: trip-point1 { 4439 temperature = <95000>; 4440 hysteresis = <2000>; 4441 type = "passive"; 4442 }; 4443 4444 cpu0_crit: cpu-crit { 4445 temperature = <110000>; 4446 hysteresis = <1000>; 4447 type = "critical"; 4448 }; 4449 }; 4450 4451 cooling-maps { 4452 map0 { 4453 trip = <&cpu0_alert0>; 4454 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4455 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4456 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4457 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4458 }; 4459 map1 { 4460 trip = <&cpu0_alert1>; 4461 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4462 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4463 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4464 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4465 }; 4466 }; 4467 }; 4468 4469 cpu1-thermal { 4470 polling-delay-passive = <250>; 4471 polling-delay = <1000>; 4472 4473 thermal-sensors = <&tsens0 2>; 4474 4475 trips { 4476 cpu1_alert0: trip-point0 { 4477 temperature = <90000>; 4478 hysteresis = <2000>; 4479 type = "passive"; 4480 }; 4481 4482 cpu1_alert1: trip-point1 { 4483 temperature = <95000>; 4484 hysteresis = <2000>; 4485 type = "passive"; 4486 }; 4487 4488 cpu1_crit: cpu-crit { 4489 temperature = <110000>; 4490 hysteresis = <1000>; 4491 type = "critical"; 4492 }; 4493 }; 4494 4495 cooling-maps { 4496 map0 { 4497 trip = <&cpu1_alert0>; 4498 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4499 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4500 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4501 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4502 }; 4503 map1 { 4504 trip = <&cpu1_alert1>; 4505 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4506 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4507 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4508 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4509 }; 4510 }; 4511 }; 4512 4513 cpu2-thermal { 4514 polling-delay-passive = <250>; 4515 polling-delay = <1000>; 4516 4517 thermal-sensors = <&tsens0 3>; 4518 4519 trips { 4520 cpu2_alert0: trip-point0 { 4521 temperature = <90000>; 4522 hysteresis = <2000>; 4523 type = "passive"; 4524 }; 4525 4526 cpu2_alert1: trip-point1 { 4527 temperature = <95000>; 4528 hysteresis = <2000>; 4529 type = "passive"; 4530 }; 4531 4532 cpu2_crit: cpu-crit { 4533 temperature = <110000>; 4534 hysteresis = <1000>; 4535 type = "critical"; 4536 }; 4537 }; 4538 4539 cooling-maps { 4540 map0 { 4541 trip = <&cpu2_alert0>; 4542 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4543 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4544 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4545 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4546 }; 4547 map1 { 4548 trip = <&cpu2_alert1>; 4549 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4550 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4551 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4552 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4553 }; 4554 }; 4555 }; 4556 4557 cpu3-thermal { 4558 polling-delay-passive = <250>; 4559 polling-delay = <1000>; 4560 4561 thermal-sensors = <&tsens0 4>; 4562 4563 trips { 4564 cpu3_alert0: trip-point0 { 4565 temperature = <90000>; 4566 hysteresis = <2000>; 4567 type = "passive"; 4568 }; 4569 4570 cpu3_alert1: trip-point1 { 4571 temperature = <95000>; 4572 hysteresis = <2000>; 4573 type = "passive"; 4574 }; 4575 4576 cpu3_crit: cpu-crit { 4577 temperature = <110000>; 4578 hysteresis = <1000>; 4579 type = "critical"; 4580 }; 4581 }; 4582 4583 cooling-maps { 4584 map0 { 4585 trip = <&cpu3_alert0>; 4586 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4587 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4588 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4589 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4590 }; 4591 map1 { 4592 trip = <&cpu3_alert1>; 4593 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4594 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4595 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4596 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4597 }; 4598 }; 4599 }; 4600 4601 cpu4-top-thermal { 4602 polling-delay-passive = <250>; 4603 polling-delay = <1000>; 4604 4605 thermal-sensors = <&tsens0 7>; 4606 4607 trips { 4608 cpu4_top_alert0: trip-point0 { 4609 temperature = <90000>; 4610 hysteresis = <2000>; 4611 type = "passive"; 4612 }; 4613 4614 cpu4_top_alert1: trip-point1 { 4615 temperature = <95000>; 4616 hysteresis = <2000>; 4617 type = "passive"; 4618 }; 4619 4620 cpu4_top_crit: cpu-crit { 4621 temperature = <110000>; 4622 hysteresis = <1000>; 4623 type = "critical"; 4624 }; 4625 }; 4626 4627 cooling-maps { 4628 map0 { 4629 trip = <&cpu4_top_alert0>; 4630 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4631 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4632 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4633 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4634 }; 4635 map1 { 4636 trip = <&cpu4_top_alert1>; 4637 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4638 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4639 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4640 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4641 }; 4642 }; 4643 }; 4644 4645 cpu5-top-thermal { 4646 polling-delay-passive = <250>; 4647 polling-delay = <1000>; 4648 4649 thermal-sensors = <&tsens0 8>; 4650 4651 trips { 4652 cpu5_top_alert0: trip-point0 { 4653 temperature = <90000>; 4654 hysteresis = <2000>; 4655 type = "passive"; 4656 }; 4657 4658 cpu5_top_alert1: trip-point1 { 4659 temperature = <95000>; 4660 hysteresis = <2000>; 4661 type = "passive"; 4662 }; 4663 4664 cpu5_top_crit: cpu-crit { 4665 temperature = <110000>; 4666 hysteresis = <1000>; 4667 type = "critical"; 4668 }; 4669 }; 4670 4671 cooling-maps { 4672 map0 { 4673 trip = <&cpu5_top_alert0>; 4674 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4675 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4676 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4677 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4678 }; 4679 map1 { 4680 trip = <&cpu5_top_alert1>; 4681 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4682 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4683 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4684 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4685 }; 4686 }; 4687 }; 4688 4689 cpu6-top-thermal { 4690 polling-delay-passive = <250>; 4691 polling-delay = <1000>; 4692 4693 thermal-sensors = <&tsens0 9>; 4694 4695 trips { 4696 cpu6_top_alert0: trip-point0 { 4697 temperature = <90000>; 4698 hysteresis = <2000>; 4699 type = "passive"; 4700 }; 4701 4702 cpu6_top_alert1: trip-point1 { 4703 temperature = <95000>; 4704 hysteresis = <2000>; 4705 type = "passive"; 4706 }; 4707 4708 cpu6_top_crit: cpu-crit { 4709 temperature = <110000>; 4710 hysteresis = <1000>; 4711 type = "critical"; 4712 }; 4713 }; 4714 4715 cooling-maps { 4716 map0 { 4717 trip = <&cpu6_top_alert0>; 4718 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4719 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4720 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4721 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4722 }; 4723 map1 { 4724 trip = <&cpu6_top_alert1>; 4725 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4726 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4727 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4728 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4729 }; 4730 }; 4731 }; 4732 4733 cpu7-top-thermal { 4734 polling-delay-passive = <250>; 4735 polling-delay = <1000>; 4736 4737 thermal-sensors = <&tsens0 10>; 4738 4739 trips { 4740 cpu7_top_alert0: trip-point0 { 4741 temperature = <90000>; 4742 hysteresis = <2000>; 4743 type = "passive"; 4744 }; 4745 4746 cpu7_top_alert1: trip-point1 { 4747 temperature = <95000>; 4748 hysteresis = <2000>; 4749 type = "passive"; 4750 }; 4751 4752 cpu7_top_crit: cpu-crit { 4753 temperature = <110000>; 4754 hysteresis = <1000>; 4755 type = "critical"; 4756 }; 4757 }; 4758 4759 cooling-maps { 4760 map0 { 4761 trip = <&cpu7_top_alert0>; 4762 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4763 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4764 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4765 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4766 }; 4767 map1 { 4768 trip = <&cpu7_top_alert1>; 4769 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4770 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4771 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4772 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4773 }; 4774 }; 4775 }; 4776 4777 cpu4-bottom-thermal { 4778 polling-delay-passive = <250>; 4779 polling-delay = <1000>; 4780 4781 thermal-sensors = <&tsens0 11>; 4782 4783 trips { 4784 cpu4_bottom_alert0: trip-point0 { 4785 temperature = <90000>; 4786 hysteresis = <2000>; 4787 type = "passive"; 4788 }; 4789 4790 cpu4_bottom_alert1: trip-point1 { 4791 temperature = <95000>; 4792 hysteresis = <2000>; 4793 type = "passive"; 4794 }; 4795 4796 cpu4_bottom_crit: cpu-crit { 4797 temperature = <110000>; 4798 hysteresis = <1000>; 4799 type = "critical"; 4800 }; 4801 }; 4802 4803 cooling-maps { 4804 map0 { 4805 trip = <&cpu4_bottom_alert0>; 4806 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4807 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4808 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4809 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4810 }; 4811 map1 { 4812 trip = <&cpu4_bottom_alert1>; 4813 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4814 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4815 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4816 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4817 }; 4818 }; 4819 }; 4820 4821 cpu5-bottom-thermal { 4822 polling-delay-passive = <250>; 4823 polling-delay = <1000>; 4824 4825 thermal-sensors = <&tsens0 12>; 4826 4827 trips { 4828 cpu5_bottom_alert0: trip-point0 { 4829 temperature = <90000>; 4830 hysteresis = <2000>; 4831 type = "passive"; 4832 }; 4833 4834 cpu5_bottom_alert1: trip-point1 { 4835 temperature = <95000>; 4836 hysteresis = <2000>; 4837 type = "passive"; 4838 }; 4839 4840 cpu5_bottom_crit: cpu-crit { 4841 temperature = <110000>; 4842 hysteresis = <1000>; 4843 type = "critical"; 4844 }; 4845 }; 4846 4847 cooling-maps { 4848 map0 { 4849 trip = <&cpu5_bottom_alert0>; 4850 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4851 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4852 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4853 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4854 }; 4855 map1 { 4856 trip = <&cpu5_bottom_alert1>; 4857 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4858 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4859 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4860 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4861 }; 4862 }; 4863 }; 4864 4865 cpu6-bottom-thermal { 4866 polling-delay-passive = <250>; 4867 polling-delay = <1000>; 4868 4869 thermal-sensors = <&tsens0 13>; 4870 4871 trips { 4872 cpu6_bottom_alert0: trip-point0 { 4873 temperature = <90000>; 4874 hysteresis = <2000>; 4875 type = "passive"; 4876 }; 4877 4878 cpu6_bottom_alert1: trip-point1 { 4879 temperature = <95000>; 4880 hysteresis = <2000>; 4881 type = "passive"; 4882 }; 4883 4884 cpu6_bottom_crit: cpu-crit { 4885 temperature = <110000>; 4886 hysteresis = <1000>; 4887 type = "critical"; 4888 }; 4889 }; 4890 4891 cooling-maps { 4892 map0 { 4893 trip = <&cpu6_bottom_alert0>; 4894 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4895 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4896 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4897 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4898 }; 4899 map1 { 4900 trip = <&cpu6_bottom_alert1>; 4901 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4902 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4903 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4904 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4905 }; 4906 }; 4907 }; 4908 4909 cpu7-bottom-thermal { 4910 polling-delay-passive = <250>; 4911 polling-delay = <1000>; 4912 4913 thermal-sensors = <&tsens0 14>; 4914 4915 trips { 4916 cpu7_bottom_alert0: trip-point0 { 4917 temperature = <90000>; 4918 hysteresis = <2000>; 4919 type = "passive"; 4920 }; 4921 4922 cpu7_bottom_alert1: trip-point1 { 4923 temperature = <95000>; 4924 hysteresis = <2000>; 4925 type = "passive"; 4926 }; 4927 4928 cpu7_bottom_crit: cpu-crit { 4929 temperature = <110000>; 4930 hysteresis = <1000>; 4931 type = "critical"; 4932 }; 4933 }; 4934 4935 cooling-maps { 4936 map0 { 4937 trip = <&cpu7_bottom_alert0>; 4938 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4939 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4940 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4941 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4942 }; 4943 map1 { 4944 trip = <&cpu7_bottom_alert1>; 4945 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4946 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4947 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4948 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4949 }; 4950 }; 4951 }; 4952 4953 aoss0-thermal { 4954 polling-delay-passive = <250>; 4955 polling-delay = <1000>; 4956 4957 thermal-sensors = <&tsens0 0>; 4958 4959 trips { 4960 aoss0_alert0: trip-point0 { 4961 temperature = <90000>; 4962 hysteresis = <2000>; 4963 type = "hot"; 4964 }; 4965 }; 4966 }; 4967 4968 cluster0-thermal { 4969 polling-delay-passive = <250>; 4970 polling-delay = <1000>; 4971 4972 thermal-sensors = <&tsens0 5>; 4973 4974 trips { 4975 cluster0_alert0: trip-point0 { 4976 temperature = <90000>; 4977 hysteresis = <2000>; 4978 type = "hot"; 4979 }; 4980 cluster0_crit: cluster0_crit { 4981 temperature = <110000>; 4982 hysteresis = <2000>; 4983 type = "critical"; 4984 }; 4985 }; 4986 }; 4987 4988 cluster1-thermal { 4989 polling-delay-passive = <250>; 4990 polling-delay = <1000>; 4991 4992 thermal-sensors = <&tsens0 6>; 4993 4994 trips { 4995 cluster1_alert0: trip-point0 { 4996 temperature = <90000>; 4997 hysteresis = <2000>; 4998 type = "hot"; 4999 }; 5000 cluster1_crit: cluster1_crit { 5001 temperature = <110000>; 5002 hysteresis = <2000>; 5003 type = "critical"; 5004 }; 5005 }; 5006 }; 5007 5008 gpu-top-thermal { 5009 polling-delay-passive = <250>; 5010 polling-delay = <1000>; 5011 5012 thermal-sensors = <&tsens0 15>; 5013 5014 trips { 5015 gpu1_alert0: trip-point0 { 5016 temperature = <90000>; 5017 hysteresis = <2000>; 5018 type = "hot"; 5019 }; 5020 }; 5021 }; 5022 5023 aoss1-thermal { 5024 polling-delay-passive = <250>; 5025 polling-delay = <1000>; 5026 5027 thermal-sensors = <&tsens1 0>; 5028 5029 trips { 5030 aoss1_alert0: trip-point0 { 5031 temperature = <90000>; 5032 hysteresis = <2000>; 5033 type = "hot"; 5034 }; 5035 }; 5036 }; 5037 5038 wlan-thermal { 5039 polling-delay-passive = <250>; 5040 polling-delay = <1000>; 5041 5042 thermal-sensors = <&tsens1 1>; 5043 5044 trips { 5045 wlan_alert0: trip-point0 { 5046 temperature = <90000>; 5047 hysteresis = <2000>; 5048 type = "hot"; 5049 }; 5050 }; 5051 }; 5052 5053 video-thermal { 5054 polling-delay-passive = <250>; 5055 polling-delay = <1000>; 5056 5057 thermal-sensors = <&tsens1 2>; 5058 5059 trips { 5060 video_alert0: trip-point0 { 5061 temperature = <90000>; 5062 hysteresis = <2000>; 5063 type = "hot"; 5064 }; 5065 }; 5066 }; 5067 5068 mem-thermal { 5069 polling-delay-passive = <250>; 5070 polling-delay = <1000>; 5071 5072 thermal-sensors = <&tsens1 3>; 5073 5074 trips { 5075 mem_alert0: trip-point0 { 5076 temperature = <90000>; 5077 hysteresis = <2000>; 5078 type = "hot"; 5079 }; 5080 }; 5081 }; 5082 5083 q6-hvx-thermal { 5084 polling-delay-passive = <250>; 5085 polling-delay = <1000>; 5086 5087 thermal-sensors = <&tsens1 4>; 5088 5089 trips { 5090 q6_hvx_alert0: trip-point0 { 5091 temperature = <90000>; 5092 hysteresis = <2000>; 5093 type = "hot"; 5094 }; 5095 }; 5096 }; 5097 5098 camera-thermal { 5099 polling-delay-passive = <250>; 5100 polling-delay = <1000>; 5101 5102 thermal-sensors = <&tsens1 5>; 5103 5104 trips { 5105 camera_alert0: trip-point0 { 5106 temperature = <90000>; 5107 hysteresis = <2000>; 5108 type = "hot"; 5109 }; 5110 }; 5111 }; 5112 5113 compute-thermal { 5114 polling-delay-passive = <250>; 5115 polling-delay = <1000>; 5116 5117 thermal-sensors = <&tsens1 6>; 5118 5119 trips { 5120 compute_alert0: trip-point0 { 5121 temperature = <90000>; 5122 hysteresis = <2000>; 5123 type = "hot"; 5124 }; 5125 }; 5126 }; 5127 5128 modem-thermal { 5129 polling-delay-passive = <250>; 5130 polling-delay = <1000>; 5131 5132 thermal-sensors = <&tsens1 7>; 5133 5134 trips { 5135 modem_alert0: trip-point0 { 5136 temperature = <90000>; 5137 hysteresis = <2000>; 5138 type = "hot"; 5139 }; 5140 }; 5141 }; 5142 5143 npu-thermal { 5144 polling-delay-passive = <250>; 5145 polling-delay = <1000>; 5146 5147 thermal-sensors = <&tsens1 8>; 5148 5149 trips { 5150 npu_alert0: trip-point0 { 5151 temperature = <90000>; 5152 hysteresis = <2000>; 5153 type = "hot"; 5154 }; 5155 }; 5156 }; 5157 5158 modem-vec-thermal { 5159 polling-delay-passive = <250>; 5160 polling-delay = <1000>; 5161 5162 thermal-sensors = <&tsens1 9>; 5163 5164 trips { 5165 modem_vec_alert0: trip-point0 { 5166 temperature = <90000>; 5167 hysteresis = <2000>; 5168 type = "hot"; 5169 }; 5170 }; 5171 }; 5172 5173 modem-scl-thermal { 5174 polling-delay-passive = <250>; 5175 polling-delay = <1000>; 5176 5177 thermal-sensors = <&tsens1 10>; 5178 5179 trips { 5180 modem_scl_alert0: trip-point0 { 5181 temperature = <90000>; 5182 hysteresis = <2000>; 5183 type = "hot"; 5184 }; 5185 }; 5186 }; 5187 5188 gpu-bottom-thermal { 5189 polling-delay-passive = <250>; 5190 polling-delay = <1000>; 5191 5192 thermal-sensors = <&tsens1 11>; 5193 5194 trips { 5195 gpu2_alert0: trip-point0 { 5196 temperature = <90000>; 5197 hysteresis = <2000>; 5198 type = "hot"; 5199 }; 5200 }; 5201 }; 5202 }; 5203}; 5204