1e13c6d14SVinod Koul// SPDX-License-Identifier: BSD-3-Clause 2e13c6d14SVinod Koul/* 3e13c6d14SVinod Koul * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4e13c6d14SVinod Koul * Copyright (c) 2019, Linaro Limited 5e13c6d14SVinod Koul */ 6e13c6d14SVinod Koul 705006290SFelipe Balbi#include <dt-bindings/dma/qcom-gpi.h> 8e13c6d14SVinod Koul#include <dt-bindings/interrupt-controller/arm-gic.h> 949076351SSibi Sankar#include <dt-bindings/power/qcom-aoss-qmp.h> 10017e7856SSibi Sankar#include <dt-bindings/power/qcom-rpmpd.h> 11e13c6d14SVinod Koul#include <dt-bindings/soc/qcom,rpmh-rsc.h> 12e13c6d14SVinod Koul#include <dt-bindings/clock/qcom,rpmh.h> 13d6f55763SVinod Koul#include <dt-bindings/clock/qcom,gcc-sm8150.h> 14f1269916SJonathan Marek#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 15a6d435c1SSibi Sankar#include <dt-bindings/interconnect/qcom,osm-l3.h> 162b6187abSThara Gopinath#include <dt-bindings/interconnect/qcom,sm8150.h> 17d2fa630cSAmit Kucheria#include <dt-bindings/thermal/thermal.h> 18e13c6d14SVinod Koul 19e13c6d14SVinod Koul/ { 20e13c6d14SVinod Koul interrupt-parent = <&intc>; 21e13c6d14SVinod Koul 22e13c6d14SVinod Koul #address-cells = <2>; 23e13c6d14SVinod Koul #size-cells = <2>; 24e13c6d14SVinod Koul 25e13c6d14SVinod Koul chosen { }; 26e13c6d14SVinod Koul 27e13c6d14SVinod Koul clocks { 28e13c6d14SVinod Koul xo_board: xo-board { 29e13c6d14SVinod Koul compatible = "fixed-clock"; 30e13c6d14SVinod Koul #clock-cells = <0>; 31e13c6d14SVinod Koul clock-frequency = <38400000>; 32e13c6d14SVinod Koul clock-output-names = "xo_board"; 33e13c6d14SVinod Koul }; 34e13c6d14SVinod Koul 35e13c6d14SVinod Koul sleep_clk: sleep-clk { 36e13c6d14SVinod Koul compatible = "fixed-clock"; 37e13c6d14SVinod Koul #clock-cells = <0>; 38e13c6d14SVinod Koul clock-frequency = <32764>; 39e13c6d14SVinod Koul clock-output-names = "sleep_clk"; 40e13c6d14SVinod Koul }; 41e13c6d14SVinod Koul }; 42e13c6d14SVinod Koul 43e13c6d14SVinod Koul cpus { 44e13c6d14SVinod Koul #address-cells = <2>; 45e13c6d14SVinod Koul #size-cells = <0>; 46e13c6d14SVinod Koul 47e13c6d14SVinod Koul CPU0: cpu@0 { 48e13c6d14SVinod Koul device_type = "cpu"; 49e13c6d14SVinod Koul compatible = "qcom,kryo485"; 50e13c6d14SVinod Koul reg = <0x0 0x0>; 51e13c6d14SVinod Koul enable-method = "psci"; 525b2dae72SDanny Lin capacity-dmips-mhz = <488>; 535b2dae72SDanny Lin dynamic-power-coefficient = <232>; 54e13c6d14SVinod Koul next-level-cache = <&L2_0>; 55fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 562b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 572b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 582b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 59b2e3f897SDanny Lin power-domains = <&CPU_PD0>; 60b2e3f897SDanny Lin power-domain-names = "psci"; 61d2fa630cSAmit Kucheria #cooling-cells = <2>; 62e13c6d14SVinod Koul L2_0: l2-cache { 63e13c6d14SVinod Koul compatible = "cache"; 64e13c6d14SVinod Koul next-level-cache = <&L3_0>; 65e13c6d14SVinod Koul L3_0: l3-cache { 66e13c6d14SVinod Koul compatible = "cache"; 67e13c6d14SVinod Koul }; 68e13c6d14SVinod Koul }; 69e13c6d14SVinod Koul }; 70e13c6d14SVinod Koul 71e13c6d14SVinod Koul CPU1: cpu@100 { 72e13c6d14SVinod Koul device_type = "cpu"; 73e13c6d14SVinod Koul compatible = "qcom,kryo485"; 74e13c6d14SVinod Koul reg = <0x0 0x100>; 75e13c6d14SVinod Koul enable-method = "psci"; 765b2dae72SDanny Lin capacity-dmips-mhz = <488>; 775b2dae72SDanny Lin dynamic-power-coefficient = <232>; 78e13c6d14SVinod Koul next-level-cache = <&L2_100>; 79fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 802b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 812b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 822b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 83b2e3f897SDanny Lin power-domains = <&CPU_PD1>; 84b2e3f897SDanny Lin power-domain-names = "psci"; 85d2fa630cSAmit Kucheria #cooling-cells = <2>; 86e13c6d14SVinod Koul L2_100: l2-cache { 87e13c6d14SVinod Koul compatible = "cache"; 88e13c6d14SVinod Koul next-level-cache = <&L3_0>; 89e13c6d14SVinod Koul }; 90e13c6d14SVinod Koul 91e13c6d14SVinod Koul }; 92e13c6d14SVinod Koul 93e13c6d14SVinod Koul CPU2: cpu@200 { 94e13c6d14SVinod Koul device_type = "cpu"; 95e13c6d14SVinod Koul compatible = "qcom,kryo485"; 96e13c6d14SVinod Koul reg = <0x0 0x200>; 97e13c6d14SVinod Koul enable-method = "psci"; 985b2dae72SDanny Lin capacity-dmips-mhz = <488>; 995b2dae72SDanny Lin dynamic-power-coefficient = <232>; 100e13c6d14SVinod Koul next-level-cache = <&L2_200>; 101fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1022b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1032b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1042b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 105b2e3f897SDanny Lin power-domains = <&CPU_PD2>; 106b2e3f897SDanny Lin power-domain-names = "psci"; 107d2fa630cSAmit Kucheria #cooling-cells = <2>; 108e13c6d14SVinod Koul L2_200: l2-cache { 109e13c6d14SVinod Koul compatible = "cache"; 110e13c6d14SVinod Koul next-level-cache = <&L3_0>; 111e13c6d14SVinod Koul }; 112e13c6d14SVinod Koul }; 113e13c6d14SVinod Koul 114e13c6d14SVinod Koul CPU3: cpu@300 { 115e13c6d14SVinod Koul device_type = "cpu"; 116e13c6d14SVinod Koul compatible = "qcom,kryo485"; 117e13c6d14SVinod Koul reg = <0x0 0x300>; 118e13c6d14SVinod Koul enable-method = "psci"; 1195b2dae72SDanny Lin capacity-dmips-mhz = <488>; 1205b2dae72SDanny Lin dynamic-power-coefficient = <232>; 121e13c6d14SVinod Koul next-level-cache = <&L2_300>; 122fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1232b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1242b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1252b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 126b2e3f897SDanny Lin power-domains = <&CPU_PD3>; 127b2e3f897SDanny Lin power-domain-names = "psci"; 128d2fa630cSAmit Kucheria #cooling-cells = <2>; 129e13c6d14SVinod Koul L2_300: l2-cache { 130e13c6d14SVinod Koul compatible = "cache"; 131e13c6d14SVinod Koul next-level-cache = <&L3_0>; 132e13c6d14SVinod Koul }; 133e13c6d14SVinod Koul }; 134e13c6d14SVinod Koul 135e13c6d14SVinod Koul CPU4: cpu@400 { 136e13c6d14SVinod Koul device_type = "cpu"; 137e13c6d14SVinod Koul compatible = "qcom,kryo485"; 138e13c6d14SVinod Koul reg = <0x0 0x400>; 139e13c6d14SVinod Koul enable-method = "psci"; 1405b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1415b2dae72SDanny Lin dynamic-power-coefficient = <369>; 142e13c6d14SVinod Koul next-level-cache = <&L2_400>; 143fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1442b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1452b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1462b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 147b2e3f897SDanny Lin power-domains = <&CPU_PD4>; 148b2e3f897SDanny Lin power-domain-names = "psci"; 149d2fa630cSAmit Kucheria #cooling-cells = <2>; 150e13c6d14SVinod Koul L2_400: l2-cache { 151e13c6d14SVinod Koul compatible = "cache"; 152e13c6d14SVinod Koul next-level-cache = <&L3_0>; 153e13c6d14SVinod Koul }; 154e13c6d14SVinod Koul }; 155e13c6d14SVinod Koul 156e13c6d14SVinod Koul CPU5: cpu@500 { 157e13c6d14SVinod Koul device_type = "cpu"; 158e13c6d14SVinod Koul compatible = "qcom,kryo485"; 159e13c6d14SVinod Koul reg = <0x0 0x500>; 160e13c6d14SVinod Koul enable-method = "psci"; 1615b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1625b2dae72SDanny Lin dynamic-power-coefficient = <369>; 163e13c6d14SVinod Koul next-level-cache = <&L2_500>; 164fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1652b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1662b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1672b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 168b2e3f897SDanny Lin power-domains = <&CPU_PD5>; 169b2e3f897SDanny Lin power-domain-names = "psci"; 170d2fa630cSAmit Kucheria #cooling-cells = <2>; 171e13c6d14SVinod Koul L2_500: l2-cache { 172e13c6d14SVinod Koul compatible = "cache"; 173e13c6d14SVinod Koul next-level-cache = <&L3_0>; 174e13c6d14SVinod Koul }; 175e13c6d14SVinod Koul }; 176e13c6d14SVinod Koul 177e13c6d14SVinod Koul CPU6: cpu@600 { 178e13c6d14SVinod Koul device_type = "cpu"; 179e13c6d14SVinod Koul compatible = "qcom,kryo485"; 180e13c6d14SVinod Koul reg = <0x0 0x600>; 181e13c6d14SVinod Koul enable-method = "psci"; 1825b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1835b2dae72SDanny Lin dynamic-power-coefficient = <369>; 184e13c6d14SVinod Koul next-level-cache = <&L2_600>; 185fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1862b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1872b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1882b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 189b2e3f897SDanny Lin power-domains = <&CPU_PD6>; 190b2e3f897SDanny Lin power-domain-names = "psci"; 191d2fa630cSAmit Kucheria #cooling-cells = <2>; 192e13c6d14SVinod Koul L2_600: l2-cache { 193e13c6d14SVinod Koul compatible = "cache"; 194e13c6d14SVinod Koul next-level-cache = <&L3_0>; 195e13c6d14SVinod Koul }; 196e13c6d14SVinod Koul }; 197e13c6d14SVinod Koul 198e13c6d14SVinod Koul CPU7: cpu@700 { 199e13c6d14SVinod Koul device_type = "cpu"; 200e13c6d14SVinod Koul compatible = "qcom,kryo485"; 201e13c6d14SVinod Koul reg = <0x0 0x700>; 202e13c6d14SVinod Koul enable-method = "psci"; 2035b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 2045b2dae72SDanny Lin dynamic-power-coefficient = <421>; 205e13c6d14SVinod Koul next-level-cache = <&L2_700>; 206fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 2>; 2072b6187abSThara Gopinath operating-points-v2 = <&cpu7_opp_table>; 2082b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 2092b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 210b2e3f897SDanny Lin power-domains = <&CPU_PD7>; 211b2e3f897SDanny Lin power-domain-names = "psci"; 212d2fa630cSAmit Kucheria #cooling-cells = <2>; 213e13c6d14SVinod Koul L2_700: l2-cache { 214e13c6d14SVinod Koul compatible = "cache"; 215e13c6d14SVinod Koul next-level-cache = <&L3_0>; 216e13c6d14SVinod Koul }; 217e13c6d14SVinod Koul }; 218066d21bcSDanny Lin 219066d21bcSDanny Lin cpu-map { 220066d21bcSDanny Lin cluster0 { 221066d21bcSDanny Lin core0 { 222066d21bcSDanny Lin cpu = <&CPU0>; 223066d21bcSDanny Lin }; 224066d21bcSDanny Lin 225066d21bcSDanny Lin core1 { 226066d21bcSDanny Lin cpu = <&CPU1>; 227066d21bcSDanny Lin }; 228066d21bcSDanny Lin 229066d21bcSDanny Lin core2 { 230066d21bcSDanny Lin cpu = <&CPU2>; 231066d21bcSDanny Lin }; 232066d21bcSDanny Lin 233066d21bcSDanny Lin core3 { 234066d21bcSDanny Lin cpu = <&CPU3>; 235066d21bcSDanny Lin }; 236066d21bcSDanny Lin 237066d21bcSDanny Lin core4 { 238066d21bcSDanny Lin cpu = <&CPU4>; 239066d21bcSDanny Lin }; 240066d21bcSDanny Lin 241066d21bcSDanny Lin core5 { 242066d21bcSDanny Lin cpu = <&CPU5>; 243066d21bcSDanny Lin }; 244066d21bcSDanny Lin 245066d21bcSDanny Lin core6 { 246066d21bcSDanny Lin cpu = <&CPU6>; 247066d21bcSDanny Lin }; 248066d21bcSDanny Lin 249066d21bcSDanny Lin core7 { 250066d21bcSDanny Lin cpu = <&CPU7>; 251066d21bcSDanny Lin }; 252066d21bcSDanny Lin }; 253066d21bcSDanny Lin }; 25481188f58SDanny Lin 25581188f58SDanny Lin idle-states { 25681188f58SDanny Lin entry-method = "psci"; 25781188f58SDanny Lin 25881188f58SDanny Lin LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 25981188f58SDanny Lin compatible = "arm,idle-state"; 26081188f58SDanny Lin idle-state-name = "little-rail-power-collapse"; 26181188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 26281188f58SDanny Lin entry-latency-us = <355>; 26381188f58SDanny Lin exit-latency-us = <909>; 26481188f58SDanny Lin min-residency-us = <3934>; 26581188f58SDanny Lin local-timer-stop; 26681188f58SDanny Lin }; 26781188f58SDanny Lin 26881188f58SDanny Lin BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 26981188f58SDanny Lin compatible = "arm,idle-state"; 27081188f58SDanny Lin idle-state-name = "big-rail-power-collapse"; 27181188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 27281188f58SDanny Lin entry-latency-us = <241>; 27381188f58SDanny Lin exit-latency-us = <1461>; 27481188f58SDanny Lin min-residency-us = <4488>; 27581188f58SDanny Lin local-timer-stop; 27681188f58SDanny Lin }; 277b2e3f897SDanny Lin }; 27881188f58SDanny Lin 279b2e3f897SDanny Lin domain-idle-states { 28081188f58SDanny Lin CLUSTER_SLEEP_0: cluster-sleep-0 { 281b2e3f897SDanny Lin compatible = "domain-idle-state"; 28281188f58SDanny Lin idle-state-name = "cluster-power-collapse"; 283b2e3f897SDanny Lin arm,psci-suspend-param = <0x4100c244>; 28481188f58SDanny Lin entry-latency-us = <3263>; 28581188f58SDanny Lin exit-latency-us = <6562>; 28681188f58SDanny Lin min-residency-us = <9987>; 28781188f58SDanny Lin local-timer-stop; 28881188f58SDanny Lin }; 28981188f58SDanny Lin }; 290e13c6d14SVinod Koul }; 291e13c6d14SVinod Koul 2922b6187abSThara Gopinath cpu0_opp_table: cpu0_opp_table { 2932b6187abSThara Gopinath compatible = "operating-points-v2"; 2942b6187abSThara Gopinath opp-shared; 2952b6187abSThara Gopinath 2962b6187abSThara Gopinath cpu0_opp1: opp-300000000 { 2972b6187abSThara Gopinath opp-hz = /bits/ 64 <300000000>; 2982b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 2992b6187abSThara Gopinath }; 3002b6187abSThara Gopinath 3012b6187abSThara Gopinath cpu0_opp2: opp-403200000 { 3022b6187abSThara Gopinath opp-hz = /bits/ 64 <403200000>; 3032b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 3042b6187abSThara Gopinath }; 3052b6187abSThara Gopinath 3062b6187abSThara Gopinath cpu0_opp3: opp-499200000 { 3072b6187abSThara Gopinath opp-hz = /bits/ 64 <499200000>; 3082b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3092b6187abSThara Gopinath }; 3102b6187abSThara Gopinath 3112b6187abSThara Gopinath cpu0_opp4: opp-576000000 { 3122b6187abSThara Gopinath opp-hz = /bits/ 64 <576000000>; 3132b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3142b6187abSThara Gopinath }; 3152b6187abSThara Gopinath 3162b6187abSThara Gopinath cpu0_opp5: opp-672000000 { 3172b6187abSThara Gopinath opp-hz = /bits/ 64 <672000000>; 3182b6187abSThara Gopinath opp-peak-kBps = <800000 15974400>; 3192b6187abSThara Gopinath }; 3202b6187abSThara Gopinath 3212b6187abSThara Gopinath cpu0_opp6: opp-768000000 { 322*ce3b50cfSThara Gopinath opp-hz = /bits/ 64 <768000000>; 3232b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3242b6187abSThara Gopinath }; 3252b6187abSThara Gopinath 3262b6187abSThara Gopinath cpu0_opp7: opp-844800000 { 3272b6187abSThara Gopinath opp-hz = /bits/ 64 <844800000>; 3282b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3292b6187abSThara Gopinath }; 3302b6187abSThara Gopinath 3312b6187abSThara Gopinath cpu0_opp8: opp-940800000 { 3322b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 3332b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3342b6187abSThara Gopinath }; 3352b6187abSThara Gopinath 3362b6187abSThara Gopinath cpu0_opp9: opp-1036800000 { 3372b6187abSThara Gopinath opp-hz = /bits/ 64 <1036800000>; 3382b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3392b6187abSThara Gopinath }; 3402b6187abSThara Gopinath 3412b6187abSThara Gopinath cpu0_opp10: opp-1113600000 { 3422b6187abSThara Gopinath opp-hz = /bits/ 64 <1113600000>; 3432b6187abSThara Gopinath opp-peak-kBps = <2188000 25804800>; 3442b6187abSThara Gopinath }; 3452b6187abSThara Gopinath 3462b6187abSThara Gopinath cpu0_opp11: opp-1209600000 { 3472b6187abSThara Gopinath opp-hz = /bits/ 64 <1209600000>; 3482b6187abSThara Gopinath opp-peak-kBps = <2188000 31948800>; 3492b6187abSThara Gopinath }; 3502b6187abSThara Gopinath 3512b6187abSThara Gopinath cpu0_opp12: opp-1305600000 { 3522b6187abSThara Gopinath opp-hz = /bits/ 64 <1305600000>; 3532b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3542b6187abSThara Gopinath }; 3552b6187abSThara Gopinath 3562b6187abSThara Gopinath cpu0_opp13: opp-1382400000 { 3572b6187abSThara Gopinath opp-hz = /bits/ 64 <1382400000>; 3582b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3592b6187abSThara Gopinath }; 3602b6187abSThara Gopinath 3612b6187abSThara Gopinath cpu0_opp14: opp-1478400000 { 3622b6187abSThara Gopinath opp-hz = /bits/ 64 <1478400000>; 3632b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3642b6187abSThara Gopinath }; 3652b6187abSThara Gopinath 3662b6187abSThara Gopinath cpu0_opp15: opp-1555200000 { 3672b6187abSThara Gopinath opp-hz = /bits/ 64 <1555200000>; 3682b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3692b6187abSThara Gopinath }; 3702b6187abSThara Gopinath 3712b6187abSThara Gopinath cpu0_opp16: opp-1632000000 { 3722b6187abSThara Gopinath opp-hz = /bits/ 64 <1632000000>; 3732b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3742b6187abSThara Gopinath }; 3752b6187abSThara Gopinath 3762b6187abSThara Gopinath cpu0_opp17: opp-1708800000 { 3772b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 3782b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 3792b6187abSThara Gopinath }; 3802b6187abSThara Gopinath 3812b6187abSThara Gopinath cpu0_opp18: opp-1785600000 { 3822b6187abSThara Gopinath opp-hz = /bits/ 64 <1785600000>; 3832b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 3842b6187abSThara Gopinath }; 3852b6187abSThara Gopinath }; 3862b6187abSThara Gopinath 3872b6187abSThara Gopinath cpu4_opp_table: cpu4_opp_table { 3882b6187abSThara Gopinath compatible = "operating-points-v2"; 3892b6187abSThara Gopinath opp-shared; 3902b6187abSThara Gopinath 3912b6187abSThara Gopinath cpu4_opp1: opp-710400000 { 3922b6187abSThara Gopinath opp-hz = /bits/ 64 <710400000>; 3932b6187abSThara Gopinath opp-peak-kBps = <1804000 15974400>; 3942b6187abSThara Gopinath }; 3952b6187abSThara Gopinath 3962b6187abSThara Gopinath cpu4_opp2: opp-825600000 { 3972b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 3982b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 3992b6187abSThara Gopinath }; 4002b6187abSThara Gopinath 4012b6187abSThara Gopinath cpu4_opp3: opp-940800000 { 4022b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 4032b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 4042b6187abSThara Gopinath }; 4052b6187abSThara Gopinath 4062b6187abSThara Gopinath cpu4_opp4: opp-1056000000 { 4072b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 4082b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 4092b6187abSThara Gopinath }; 4102b6187abSThara Gopinath 4112b6187abSThara Gopinath cpu4_opp5: opp-1171200000 { 4122b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 4132b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 4142b6187abSThara Gopinath }; 4152b6187abSThara Gopinath 4162b6187abSThara Gopinath cpu4_opp6: opp-1286400000 { 4172b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 4182b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4192b6187abSThara Gopinath }; 4202b6187abSThara Gopinath 4212b6187abSThara Gopinath cpu4_opp7: opp-1401600000 { 4222b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 4232b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4242b6187abSThara Gopinath }; 4252b6187abSThara Gopinath 4262b6187abSThara Gopinath cpu4_opp8: opp-1497600000 { 4272b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 4282b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4292b6187abSThara Gopinath }; 4302b6187abSThara Gopinath 4312b6187abSThara Gopinath cpu4_opp9: opp-1612800000 { 4322b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 4332b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4342b6187abSThara Gopinath }; 4352b6187abSThara Gopinath 4362b6187abSThara Gopinath cpu4_opp10: opp-1708800000 { 4372b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 4382b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 4392b6187abSThara Gopinath }; 4402b6187abSThara Gopinath 4412b6187abSThara Gopinath cpu4_opp11: opp-1804800000 { 4422b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 4432b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 4442b6187abSThara Gopinath }; 4452b6187abSThara Gopinath 4462b6187abSThara Gopinath cpu4_opp12: opp-1920000000 { 4472b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 4482b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 4492b6187abSThara Gopinath }; 4502b6187abSThara Gopinath 4512b6187abSThara Gopinath cpu4_opp13: opp-2016000000 { 4522b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 4532b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 4542b6187abSThara Gopinath }; 4552b6187abSThara Gopinath 4562b6187abSThara Gopinath cpu4_opp14: opp-2131200000 { 4572b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 4582b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 4592b6187abSThara Gopinath }; 4602b6187abSThara Gopinath 4612b6187abSThara Gopinath cpu4_opp15: opp-2227200000 { 4622b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 4632b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4642b6187abSThara Gopinath }; 4652b6187abSThara Gopinath 4662b6187abSThara Gopinath cpu4_opp16: opp-2323200000 { 4672b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 4682b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4692b6187abSThara Gopinath }; 4702b6187abSThara Gopinath 4712b6187abSThara Gopinath cpu4_opp17: opp-2419200000 { 4722b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 4732b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4742b6187abSThara Gopinath }; 4752b6187abSThara Gopinath }; 4762b6187abSThara Gopinath 4772b6187abSThara Gopinath cpu7_opp_table: cpu7_opp_table { 4782b6187abSThara Gopinath compatible = "operating-points-v2"; 4792b6187abSThara Gopinath opp-shared; 4802b6187abSThara Gopinath 4812b6187abSThara Gopinath cpu7_opp1: opp-825600000 { 4822b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 4832b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 4842b6187abSThara Gopinath }; 4852b6187abSThara Gopinath 4862b6187abSThara Gopinath cpu7_opp2: opp-940800000 { 4872b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 4882b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 4892b6187abSThara Gopinath }; 4902b6187abSThara Gopinath 4912b6187abSThara Gopinath cpu7_opp3: opp-1056000000 { 4922b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 4932b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 4942b6187abSThara Gopinath }; 4952b6187abSThara Gopinath 4962b6187abSThara Gopinath cpu7_opp4: opp-1171200000 { 4972b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 4982b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 4992b6187abSThara Gopinath }; 5002b6187abSThara Gopinath 5012b6187abSThara Gopinath cpu7_opp5: opp-1286400000 { 5022b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 5032b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5042b6187abSThara Gopinath }; 5052b6187abSThara Gopinath 5062b6187abSThara Gopinath cpu7_opp6: opp-1401600000 { 5072b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 5082b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5092b6187abSThara Gopinath }; 5102b6187abSThara Gopinath 5112b6187abSThara Gopinath cpu7_opp7: opp-1497600000 { 5122b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 5132b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5142b6187abSThara Gopinath }; 5152b6187abSThara Gopinath 5162b6187abSThara Gopinath cpu7_opp8: opp-1612800000 { 5172b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 5182b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5192b6187abSThara Gopinath }; 5202b6187abSThara Gopinath 5212b6187abSThara Gopinath cpu7_opp9: opp-1708800000 { 5222b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 5232b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 5242b6187abSThara Gopinath }; 5252b6187abSThara Gopinath 5262b6187abSThara Gopinath cpu7_opp10: opp-1804800000 { 5272b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 5282b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 5292b6187abSThara Gopinath }; 5302b6187abSThara Gopinath 5312b6187abSThara Gopinath cpu7_opp11: opp-1920000000 { 5322b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 5332b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 5342b6187abSThara Gopinath }; 5352b6187abSThara Gopinath 5362b6187abSThara Gopinath cpu7_opp12: opp-2016000000 { 5372b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 5382b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 5392b6187abSThara Gopinath }; 5402b6187abSThara Gopinath 5412b6187abSThara Gopinath cpu7_opp13: opp-2131200000 { 5422b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 5432b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 5442b6187abSThara Gopinath }; 5452b6187abSThara Gopinath 5462b6187abSThara Gopinath cpu7_opp14: opp-2227200000 { 5472b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 5482b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5492b6187abSThara Gopinath }; 5502b6187abSThara Gopinath 5512b6187abSThara Gopinath cpu7_opp15: opp-2323200000 { 5522b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 5532b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5542b6187abSThara Gopinath }; 5552b6187abSThara Gopinath 5562b6187abSThara Gopinath cpu7_opp16: opp-2419200000 { 5572b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 5582b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5592b6187abSThara Gopinath }; 5602b6187abSThara Gopinath 5612b6187abSThara Gopinath cpu7_opp17: opp-2534400000 { 5622b6187abSThara Gopinath opp-hz = /bits/ 64 <2534400000>; 5632b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5642b6187abSThara Gopinath }; 5652b6187abSThara Gopinath 5662b6187abSThara Gopinath cpu7_opp18: opp-2649600000 { 5672b6187abSThara Gopinath opp-hz = /bits/ 64 <2649600000>; 5682b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5692b6187abSThara Gopinath }; 5702b6187abSThara Gopinath 5712b6187abSThara Gopinath cpu7_opp19: opp-2745600000 { 5722b6187abSThara Gopinath opp-hz = /bits/ 64 <2745600000>; 5732b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5742b6187abSThara Gopinath }; 5752b6187abSThara Gopinath 5762b6187abSThara Gopinath cpu7_opp20: opp-2841600000 { 5772b6187abSThara Gopinath opp-hz = /bits/ 64 <2841600000>; 5782b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5792b6187abSThara Gopinath }; 5802b6187abSThara Gopinath }; 5812b6187abSThara Gopinath 582e13c6d14SVinod Koul firmware { 583e13c6d14SVinod Koul scm: scm { 584e13c6d14SVinod Koul compatible = "qcom,scm-sm8150", "qcom,scm"; 585e13c6d14SVinod Koul #reset-cells = <1>; 586e13c6d14SVinod Koul }; 587e13c6d14SVinod Koul }; 588e13c6d14SVinod Koul 589d8cf9372SVinod Koul tcsr_mutex: hwlock { 590d8cf9372SVinod Koul compatible = "qcom,tcsr-mutex"; 591d8cf9372SVinod Koul syscon = <&tcsr_mutex_regs 0 0x1000>; 592d8cf9372SVinod Koul #hwlock-cells = <1>; 593d8cf9372SVinod Koul }; 594d8cf9372SVinod Koul 595e13c6d14SVinod Koul memory@80000000 { 596e13c6d14SVinod Koul device_type = "memory"; 597e13c6d14SVinod Koul /* We expect the bootloader to fill in the size */ 598e13c6d14SVinod Koul reg = <0x0 0x80000000 0x0 0x0>; 599e13c6d14SVinod Koul }; 600e13c6d14SVinod Koul 601d8cf9372SVinod Koul pmu { 602d8cf9372SVinod Koul compatible = "arm,armv8-pmuv3"; 603d8cf9372SVinod Koul interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 604d8cf9372SVinod Koul }; 605d8cf9372SVinod Koul 606e13c6d14SVinod Koul psci { 607e13c6d14SVinod Koul compatible = "arm,psci-1.0"; 608e13c6d14SVinod Koul method = "smc"; 609b2e3f897SDanny Lin 610b2e3f897SDanny Lin CPU_PD0: cpu0 { 611b2e3f897SDanny Lin #power-domain-cells = <0>; 612b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 613b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 614b2e3f897SDanny Lin }; 615b2e3f897SDanny Lin 616b2e3f897SDanny Lin CPU_PD1: cpu1 { 617b2e3f897SDanny Lin #power-domain-cells = <0>; 618b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 619b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 620b2e3f897SDanny Lin }; 621b2e3f897SDanny Lin 622b2e3f897SDanny Lin CPU_PD2: cpu2 { 623b2e3f897SDanny Lin #power-domain-cells = <0>; 624b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 625b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 626b2e3f897SDanny Lin }; 627b2e3f897SDanny Lin 628b2e3f897SDanny Lin CPU_PD3: cpu3 { 629b2e3f897SDanny Lin #power-domain-cells = <0>; 630b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 631b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 632b2e3f897SDanny Lin }; 633b2e3f897SDanny Lin 634b2e3f897SDanny Lin CPU_PD4: cpu4 { 635b2e3f897SDanny Lin #power-domain-cells = <0>; 636b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 637b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 638b2e3f897SDanny Lin }; 639b2e3f897SDanny Lin 640b2e3f897SDanny Lin CPU_PD5: cpu5 { 641b2e3f897SDanny Lin #power-domain-cells = <0>; 642b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 643b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 644b2e3f897SDanny Lin }; 645b2e3f897SDanny Lin 646b2e3f897SDanny Lin CPU_PD6: cpu6 { 647b2e3f897SDanny Lin #power-domain-cells = <0>; 648b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 649b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 650b2e3f897SDanny Lin }; 651b2e3f897SDanny Lin 652b2e3f897SDanny Lin CPU_PD7: cpu7 { 653b2e3f897SDanny Lin #power-domain-cells = <0>; 654b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 655b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 656b2e3f897SDanny Lin }; 657b2e3f897SDanny Lin 658b2e3f897SDanny Lin CLUSTER_PD: cpu-cluster0 { 659b2e3f897SDanny Lin #power-domain-cells = <0>; 660b2e3f897SDanny Lin domain-idle-states = <&CLUSTER_SLEEP_0>; 661b2e3f897SDanny Lin }; 662e13c6d14SVinod Koul }; 663e13c6d14SVinod Koul 664912c373aSVinod Koul reserved-memory { 665912c373aSVinod Koul #address-cells = <2>; 666912c373aSVinod Koul #size-cells = <2>; 667912c373aSVinod Koul ranges; 668912c373aSVinod Koul 669912c373aSVinod Koul hyp_mem: memory@85700000 { 670912c373aSVinod Koul reg = <0x0 0x85700000 0x0 0x600000>; 671912c373aSVinod Koul no-map; 672912c373aSVinod Koul }; 673912c373aSVinod Koul 674912c373aSVinod Koul xbl_mem: memory@85d00000 { 675912c373aSVinod Koul reg = <0x0 0x85d00000 0x0 0x140000>; 676912c373aSVinod Koul no-map; 677912c373aSVinod Koul }; 678912c373aSVinod Koul 679912c373aSVinod Koul aop_mem: memory@85f00000 { 680912c373aSVinod Koul reg = <0x0 0x85f00000 0x0 0x20000>; 681912c373aSVinod Koul no-map; 682912c373aSVinod Koul }; 683912c373aSVinod Koul 684912c373aSVinod Koul aop_cmd_db: memory@85f20000 { 685912c373aSVinod Koul compatible = "qcom,cmd-db"; 686912c373aSVinod Koul reg = <0x0 0x85f20000 0x0 0x20000>; 687912c373aSVinod Koul no-map; 688912c373aSVinod Koul }; 689912c373aSVinod Koul 690912c373aSVinod Koul smem_mem: memory@86000000 { 691912c373aSVinod Koul reg = <0x0 0x86000000 0x0 0x200000>; 692912c373aSVinod Koul no-map; 693912c373aSVinod Koul }; 694912c373aSVinod Koul 695912c373aSVinod Koul tz_mem: memory@86200000 { 696912c373aSVinod Koul reg = <0x0 0x86200000 0x0 0x3900000>; 697912c373aSVinod Koul no-map; 698912c373aSVinod Koul }; 699912c373aSVinod Koul 700912c373aSVinod Koul rmtfs_mem: memory@89b00000 { 701912c373aSVinod Koul compatible = "qcom,rmtfs-mem"; 702912c373aSVinod Koul reg = <0x0 0x89b00000 0x0 0x200000>; 703912c373aSVinod Koul no-map; 704912c373aSVinod Koul 705912c373aSVinod Koul qcom,client-id = <1>; 706912c373aSVinod Koul qcom,vmid = <15>; 707912c373aSVinod Koul }; 708912c373aSVinod Koul 709912c373aSVinod Koul camera_mem: memory@8b700000 { 710912c373aSVinod Koul reg = <0x0 0x8b700000 0x0 0x500000>; 711912c373aSVinod Koul no-map; 712912c373aSVinod Koul }; 713912c373aSVinod Koul 714912c373aSVinod Koul wlan_mem: memory@8bc00000 { 715912c373aSVinod Koul reg = <0x0 0x8bc00000 0x0 0x180000>; 716912c373aSVinod Koul no-map; 717912c373aSVinod Koul }; 718912c373aSVinod Koul 719912c373aSVinod Koul npu_mem: memory@8bd80000 { 720912c373aSVinod Koul reg = <0x0 0x8bd80000 0x0 0x80000>; 721912c373aSVinod Koul no-map; 722912c373aSVinod Koul }; 723912c373aSVinod Koul 724912c373aSVinod Koul adsp_mem: memory@8be00000 { 725912c373aSVinod Koul reg = <0x0 0x8be00000 0x0 0x1a00000>; 726912c373aSVinod Koul no-map; 727912c373aSVinod Koul }; 728912c373aSVinod Koul 729912c373aSVinod Koul mpss_mem: memory@8d800000 { 730912c373aSVinod Koul reg = <0x0 0x8d800000 0x0 0x9600000>; 731912c373aSVinod Koul no-map; 732912c373aSVinod Koul }; 733912c373aSVinod Koul 734912c373aSVinod Koul venus_mem: memory@96e00000 { 735912c373aSVinod Koul reg = <0x0 0x96e00000 0x0 0x500000>; 736912c373aSVinod Koul no-map; 737912c373aSVinod Koul }; 738912c373aSVinod Koul 739912c373aSVinod Koul slpi_mem: memory@97300000 { 740912c373aSVinod Koul reg = <0x0 0x97300000 0x0 0x1400000>; 741912c373aSVinod Koul no-map; 742912c373aSVinod Koul }; 743912c373aSVinod Koul 744912c373aSVinod Koul ipa_fw_mem: memory@98700000 { 745912c373aSVinod Koul reg = <0x0 0x98700000 0x0 0x10000>; 746912c373aSVinod Koul no-map; 747912c373aSVinod Koul }; 748912c373aSVinod Koul 749912c373aSVinod Koul ipa_gsi_mem: memory@98710000 { 750912c373aSVinod Koul reg = <0x0 0x98710000 0x0 0x5000>; 751912c373aSVinod Koul no-map; 752912c373aSVinod Koul }; 753912c373aSVinod Koul 754912c373aSVinod Koul gpu_mem: memory@98715000 { 755912c373aSVinod Koul reg = <0x0 0x98715000 0x0 0x2000>; 756912c373aSVinod Koul no-map; 757912c373aSVinod Koul }; 758912c373aSVinod Koul 759912c373aSVinod Koul spss_mem: memory@98800000 { 760912c373aSVinod Koul reg = <0x0 0x98800000 0x0 0x100000>; 761912c373aSVinod Koul no-map; 762912c373aSVinod Koul }; 763912c373aSVinod Koul 764912c373aSVinod Koul cdsp_mem: memory@98900000 { 765912c373aSVinod Koul reg = <0x0 0x98900000 0x0 0x1400000>; 766912c373aSVinod Koul no-map; 767912c373aSVinod Koul }; 768912c373aSVinod Koul 769912c373aSVinod Koul qseecom_mem: memory@9e400000 { 770912c373aSVinod Koul reg = <0x0 0x9e400000 0x0 0x1400000>; 771912c373aSVinod Koul no-map; 772912c373aSVinod Koul }; 773912c373aSVinod Koul }; 774912c373aSVinod Koul 775d8cf9372SVinod Koul smem { 776d8cf9372SVinod Koul compatible = "qcom,smem"; 777d8cf9372SVinod Koul memory-region = <&smem_mem>; 778d8cf9372SVinod Koul hwlocks = <&tcsr_mutex 3>; 779d8cf9372SVinod Koul }; 780d8cf9372SVinod Koul 78161025b81SSibi Sankar smp2p-cdsp { 78261025b81SSibi Sankar compatible = "qcom,smp2p"; 78361025b81SSibi Sankar qcom,smem = <94>, <432>; 78461025b81SSibi Sankar 78561025b81SSibi Sankar interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 78661025b81SSibi Sankar 78761025b81SSibi Sankar mboxes = <&apss_shared 6>; 78861025b81SSibi Sankar 78961025b81SSibi Sankar qcom,local-pid = <0>; 79061025b81SSibi Sankar qcom,remote-pid = <5>; 79161025b81SSibi Sankar 79261025b81SSibi Sankar cdsp_smp2p_out: master-kernel { 79361025b81SSibi Sankar qcom,entry-name = "master-kernel"; 79461025b81SSibi Sankar #qcom,smem-state-cells = <1>; 79561025b81SSibi Sankar }; 79661025b81SSibi Sankar 79761025b81SSibi Sankar cdsp_smp2p_in: slave-kernel { 79861025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 79961025b81SSibi Sankar 80061025b81SSibi Sankar interrupt-controller; 80161025b81SSibi Sankar #interrupt-cells = <2>; 80261025b81SSibi Sankar }; 80361025b81SSibi Sankar }; 80461025b81SSibi Sankar 80561025b81SSibi Sankar smp2p-lpass { 80661025b81SSibi Sankar compatible = "qcom,smp2p"; 80761025b81SSibi Sankar qcom,smem = <443>, <429>; 80861025b81SSibi Sankar 80961025b81SSibi Sankar interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 81061025b81SSibi Sankar 81161025b81SSibi Sankar mboxes = <&apss_shared 10>; 81261025b81SSibi Sankar 81361025b81SSibi Sankar qcom,local-pid = <0>; 81461025b81SSibi Sankar qcom,remote-pid = <2>; 81561025b81SSibi Sankar 81661025b81SSibi Sankar adsp_smp2p_out: master-kernel { 81761025b81SSibi Sankar qcom,entry-name = "master-kernel"; 81861025b81SSibi Sankar #qcom,smem-state-cells = <1>; 81961025b81SSibi Sankar }; 82061025b81SSibi Sankar 82161025b81SSibi Sankar adsp_smp2p_in: slave-kernel { 82261025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 82361025b81SSibi Sankar 82461025b81SSibi Sankar interrupt-controller; 82561025b81SSibi Sankar #interrupt-cells = <2>; 82661025b81SSibi Sankar }; 82761025b81SSibi Sankar }; 82861025b81SSibi Sankar 82961025b81SSibi Sankar smp2p-mpss { 83061025b81SSibi Sankar compatible = "qcom,smp2p"; 83161025b81SSibi Sankar qcom,smem = <435>, <428>; 83261025b81SSibi Sankar 83361025b81SSibi Sankar interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 83461025b81SSibi Sankar 83561025b81SSibi Sankar mboxes = <&apss_shared 14>; 83661025b81SSibi Sankar 83761025b81SSibi Sankar qcom,local-pid = <0>; 83861025b81SSibi Sankar qcom,remote-pid = <1>; 83961025b81SSibi Sankar 84061025b81SSibi Sankar modem_smp2p_out: master-kernel { 84161025b81SSibi Sankar qcom,entry-name = "master-kernel"; 84261025b81SSibi Sankar #qcom,smem-state-cells = <1>; 84361025b81SSibi Sankar }; 84461025b81SSibi Sankar 84561025b81SSibi Sankar modem_smp2p_in: slave-kernel { 84661025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 84761025b81SSibi Sankar 84861025b81SSibi Sankar interrupt-controller; 84961025b81SSibi Sankar #interrupt-cells = <2>; 85061025b81SSibi Sankar }; 85161025b81SSibi Sankar }; 85261025b81SSibi Sankar 85361025b81SSibi Sankar smp2p-slpi { 85461025b81SSibi Sankar compatible = "qcom,smp2p"; 85561025b81SSibi Sankar qcom,smem = <481>, <430>; 85661025b81SSibi Sankar 85761025b81SSibi Sankar interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 85861025b81SSibi Sankar 85961025b81SSibi Sankar mboxes = <&apss_shared 26>; 86061025b81SSibi Sankar 86161025b81SSibi Sankar qcom,local-pid = <0>; 86261025b81SSibi Sankar qcom,remote-pid = <3>; 86361025b81SSibi Sankar 86461025b81SSibi Sankar slpi_smp2p_out: master-kernel { 86561025b81SSibi Sankar qcom,entry-name = "master-kernel"; 86661025b81SSibi Sankar #qcom,smem-state-cells = <1>; 86761025b81SSibi Sankar }; 86861025b81SSibi Sankar 86961025b81SSibi Sankar slpi_smp2p_in: slave-kernel { 87061025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 87161025b81SSibi Sankar 87261025b81SSibi Sankar interrupt-controller; 87361025b81SSibi Sankar #interrupt-cells = <2>; 87461025b81SSibi Sankar }; 87561025b81SSibi Sankar }; 87661025b81SSibi Sankar 877e13c6d14SVinod Koul soc: soc@0 { 878e13c6d14SVinod Koul #address-cells = <2>; 879e13c6d14SVinod Koul #size-cells = <2>; 880e13c6d14SVinod Koul ranges = <0 0 0 0 0x10 0>; 881e13c6d14SVinod Koul dma-ranges = <0 0 0 0 0x10 0>; 882e13c6d14SVinod Koul compatible = "simple-bus"; 883e13c6d14SVinod Koul 884e13c6d14SVinod Koul gcc: clock-controller@100000 { 885e13c6d14SVinod Koul compatible = "qcom,gcc-sm8150"; 886e13c6d14SVinod Koul reg = <0x0 0x00100000 0x0 0x1f0000>; 887e13c6d14SVinod Koul #clock-cells = <1>; 888e13c6d14SVinod Koul #reset-cells = <1>; 889e13c6d14SVinod Koul #power-domain-cells = <1>; 890e13c6d14SVinod Koul clock-names = "bi_tcxo", 891e13c6d14SVinod Koul "sleep_clk"; 892e13c6d14SVinod Koul clocks = <&rpmhcc RPMH_CXO_CLK>, 893e13c6d14SVinod Koul <&sleep_clk>; 894e13c6d14SVinod Koul }; 895e13c6d14SVinod Koul 89605006290SFelipe Balbi gpi_dma0: dma-controller@800000 { 89705006290SFelipe Balbi compatible = "qcom,sm8150-gpi-dma"; 89805006290SFelipe Balbi reg = <0 0x800000 0 0x60000>; 89905006290SFelipe Balbi interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 90005006290SFelipe Balbi <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 90105006290SFelipe Balbi <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 90205006290SFelipe Balbi <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 90305006290SFelipe Balbi <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 90405006290SFelipe Balbi <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 90505006290SFelipe Balbi <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 90605006290SFelipe Balbi <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 90705006290SFelipe Balbi <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 90805006290SFelipe Balbi <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 90905006290SFelipe Balbi <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 91005006290SFelipe Balbi <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 91105006290SFelipe Balbi <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 91205006290SFelipe Balbi dma-channels = <13>; 91305006290SFelipe Balbi dma-channel-mask = <0xfa>; 91405006290SFelipe Balbi iommus = <&apps_smmu 0x00d6 0x0>; 91505006290SFelipe Balbi #dma-cells = <3>; 91605006290SFelipe Balbi status = "disabled"; 91705006290SFelipe Balbi }; 91805006290SFelipe Balbi 9199cf3ebd1SCaleb Connolly qupv3_id_0: geniqup@8c0000 { 9209cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 9219cf3ebd1SCaleb Connolly reg = <0x0 0x008c0000 0x0 0x6000>; 9229cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 9239cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 9249cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 9259cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0xc3 0x0>; 9269cf3ebd1SCaleb Connolly #address-cells = <2>; 9279cf3ebd1SCaleb Connolly #size-cells = <2>; 9289cf3ebd1SCaleb Connolly ranges; 9299cf3ebd1SCaleb Connolly status = "disabled"; 93081bee695SCaleb Connolly 93181bee695SCaleb Connolly i2c0: i2c@880000 { 93281bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 93381bee695SCaleb Connolly reg = <0 0x00880000 0 0x4000>; 93481bee695SCaleb Connolly clock-names = "se"; 93581bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 93681bee695SCaleb Connolly pinctrl-names = "default"; 93781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c0_default>; 93881bee695SCaleb Connolly interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 93981bee695SCaleb Connolly #address-cells = <1>; 94081bee695SCaleb Connolly #size-cells = <0>; 94181bee695SCaleb Connolly status = "disabled"; 94281bee695SCaleb Connolly }; 94381bee695SCaleb Connolly 94481bee695SCaleb Connolly i2c1: i2c@884000 { 94581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 94681bee695SCaleb Connolly reg = <0 0x00884000 0 0x4000>; 94781bee695SCaleb Connolly clock-names = "se"; 94881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 94981bee695SCaleb Connolly pinctrl-names = "default"; 95081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c1_default>; 95181bee695SCaleb Connolly interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 95281bee695SCaleb Connolly #address-cells = <1>; 95381bee695SCaleb Connolly #size-cells = <0>; 95481bee695SCaleb Connolly status = "disabled"; 95581bee695SCaleb Connolly }; 95681bee695SCaleb Connolly 95781bee695SCaleb Connolly i2c2: i2c@888000 { 95881bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 95981bee695SCaleb Connolly reg = <0 0x00888000 0 0x4000>; 96081bee695SCaleb Connolly clock-names = "se"; 96181bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 96281bee695SCaleb Connolly pinctrl-names = "default"; 96381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c2_default>; 96481bee695SCaleb Connolly interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 96581bee695SCaleb Connolly #address-cells = <1>; 96681bee695SCaleb Connolly #size-cells = <0>; 96781bee695SCaleb Connolly status = "disabled"; 96881bee695SCaleb Connolly }; 96981bee695SCaleb Connolly 97081bee695SCaleb Connolly i2c3: i2c@88c000 { 97181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 97281bee695SCaleb Connolly reg = <0 0x0088c000 0 0x4000>; 97381bee695SCaleb Connolly clock-names = "se"; 97481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 97581bee695SCaleb Connolly pinctrl-names = "default"; 97681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c3_default>; 97781bee695SCaleb Connolly interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 97881bee695SCaleb Connolly #address-cells = <1>; 97981bee695SCaleb Connolly #size-cells = <0>; 98081bee695SCaleb Connolly status = "disabled"; 98181bee695SCaleb Connolly }; 98281bee695SCaleb Connolly 98381bee695SCaleb Connolly i2c4: i2c@890000 { 98481bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 98581bee695SCaleb Connolly reg = <0 0x00890000 0 0x4000>; 98681bee695SCaleb Connolly clock-names = "se"; 98781bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 98881bee695SCaleb Connolly pinctrl-names = "default"; 98981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c4_default>; 99081bee695SCaleb Connolly interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 99181bee695SCaleb Connolly #address-cells = <1>; 99281bee695SCaleb Connolly #size-cells = <0>; 99381bee695SCaleb Connolly status = "disabled"; 99481bee695SCaleb Connolly }; 99581bee695SCaleb Connolly 99681bee695SCaleb Connolly i2c5: i2c@894000 { 99781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 99881bee695SCaleb Connolly reg = <0 0x00894000 0 0x4000>; 99981bee695SCaleb Connolly clock-names = "se"; 100081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 100181bee695SCaleb Connolly pinctrl-names = "default"; 100281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c5_default>; 100381bee695SCaleb Connolly interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 100481bee695SCaleb Connolly #address-cells = <1>; 100581bee695SCaleb Connolly #size-cells = <0>; 100681bee695SCaleb Connolly status = "disabled"; 100781bee695SCaleb Connolly }; 100881bee695SCaleb Connolly 100981bee695SCaleb Connolly i2c6: i2c@898000 { 101081bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 101181bee695SCaleb Connolly reg = <0 0x00898000 0 0x4000>; 101281bee695SCaleb Connolly clock-names = "se"; 101381bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 101481bee695SCaleb Connolly pinctrl-names = "default"; 101581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c6_default>; 101681bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 101781bee695SCaleb Connolly #address-cells = <1>; 101881bee695SCaleb Connolly #size-cells = <0>; 101981bee695SCaleb Connolly status = "disabled"; 102081bee695SCaleb Connolly }; 102181bee695SCaleb Connolly 102281bee695SCaleb Connolly i2c7: i2c@89c000 { 102381bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 102481bee695SCaleb Connolly reg = <0 0x0089c000 0 0x4000>; 102581bee695SCaleb Connolly clock-names = "se"; 102681bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 102781bee695SCaleb Connolly pinctrl-names = "default"; 102881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c7_default>; 102981bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 103081bee695SCaleb Connolly #address-cells = <1>; 103181bee695SCaleb Connolly #size-cells = <0>; 103281bee695SCaleb Connolly status = "disabled"; 103381bee695SCaleb Connolly }; 103481bee695SCaleb Connolly 10359cf3ebd1SCaleb Connolly }; 10369cf3ebd1SCaleb Connolly 103705006290SFelipe Balbi gpi_dma1: dma-controller@a00000 { 103805006290SFelipe Balbi compatible = "qcom,sm8150-gpi-dma"; 103905006290SFelipe Balbi reg = <0 0xa00000 0 0x60000>; 104005006290SFelipe Balbi interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 104105006290SFelipe Balbi <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 104205006290SFelipe Balbi <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 104305006290SFelipe Balbi <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 104405006290SFelipe Balbi <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 104505006290SFelipe Balbi <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 104605006290SFelipe Balbi <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 104705006290SFelipe Balbi <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 104805006290SFelipe Balbi <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 104905006290SFelipe Balbi <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 105005006290SFelipe Balbi <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 105105006290SFelipe Balbi <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 105205006290SFelipe Balbi <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 105305006290SFelipe Balbi dma-channels = <13>; 105405006290SFelipe Balbi dma-channel-mask = <0xfa>; 105505006290SFelipe Balbi iommus = <&apps_smmu 0x0616 0x0>; 105605006290SFelipe Balbi #dma-cells = <3>; 105705006290SFelipe Balbi status = "disabled"; 105805006290SFelipe Balbi }; 105905006290SFelipe Balbi 1060e13c6d14SVinod Koul qupv3_id_1: geniqup@ac0000 { 1061e13c6d14SVinod Koul compatible = "qcom,geni-se-qup"; 1062e13c6d14SVinod Koul reg = <0x0 0x00ac0000 0x0 0x6000>; 1063e13c6d14SVinod Koul clock-names = "m-ahb", "s-ahb"; 1064d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1065d6f55763SVinod Koul <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 10669cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x603 0x0>; 1067e13c6d14SVinod Koul #address-cells = <2>; 1068e13c6d14SVinod Koul #size-cells = <2>; 1069e13c6d14SVinod Koul ranges; 1070e13c6d14SVinod Koul status = "disabled"; 1071e13c6d14SVinod Koul 107281bee695SCaleb Connolly i2c8: i2c@a80000 { 107381bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 107481bee695SCaleb Connolly reg = <0 0x00a80000 0 0x4000>; 107581bee695SCaleb Connolly clock-names = "se"; 107681bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 107781bee695SCaleb Connolly pinctrl-names = "default"; 107881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c8_default>; 107981bee695SCaleb Connolly interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 108081bee695SCaleb Connolly #address-cells = <1>; 108181bee695SCaleb Connolly #size-cells = <0>; 108281bee695SCaleb Connolly status = "disabled"; 108381bee695SCaleb Connolly }; 108481bee695SCaleb Connolly 108581bee695SCaleb Connolly i2c9: i2c@a84000 { 108681bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 108781bee695SCaleb Connolly reg = <0 0x00a84000 0 0x4000>; 108881bee695SCaleb Connolly clock-names = "se"; 108981bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 109081bee695SCaleb Connolly pinctrl-names = "default"; 109181bee695SCaleb Connolly pinctrl-0 = <&qup_i2c9_default>; 109281bee695SCaleb Connolly interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 109381bee695SCaleb Connolly #address-cells = <1>; 109481bee695SCaleb Connolly #size-cells = <0>; 109581bee695SCaleb Connolly status = "disabled"; 109681bee695SCaleb Connolly }; 109781bee695SCaleb Connolly 109881bee695SCaleb Connolly i2c10: i2c@a88000 { 109981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 110081bee695SCaleb Connolly reg = <0 0x00a88000 0 0x4000>; 110181bee695SCaleb Connolly clock-names = "se"; 110281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 110381bee695SCaleb Connolly pinctrl-names = "default"; 110481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c10_default>; 110581bee695SCaleb Connolly interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 110681bee695SCaleb Connolly #address-cells = <1>; 110781bee695SCaleb Connolly #size-cells = <0>; 110881bee695SCaleb Connolly status = "disabled"; 110981bee695SCaleb Connolly }; 111081bee695SCaleb Connolly 111181bee695SCaleb Connolly i2c11: i2c@a8c000 { 111281bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 111381bee695SCaleb Connolly reg = <0 0x00a8c000 0 0x4000>; 111481bee695SCaleb Connolly clock-names = "se"; 111581bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 111681bee695SCaleb Connolly pinctrl-names = "default"; 111781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c11_default>; 111881bee695SCaleb Connolly interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 111981bee695SCaleb Connolly #address-cells = <1>; 112081bee695SCaleb Connolly #size-cells = <0>; 112181bee695SCaleb Connolly status = "disabled"; 112281bee695SCaleb Connolly }; 112381bee695SCaleb Connolly 1124e13c6d14SVinod Koul uart2: serial@a90000 { 1125e13c6d14SVinod Koul compatible = "qcom,geni-debug-uart"; 1126e13c6d14SVinod Koul reg = <0x0 0x00a90000 0x0 0x4000>; 1127e13c6d14SVinod Koul clock-names = "se"; 1128d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1129e13c6d14SVinod Koul interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1130e13c6d14SVinod Koul status = "disabled"; 1131e13c6d14SVinod Koul }; 113281bee695SCaleb Connolly 113381bee695SCaleb Connolly i2c12: i2c@a90000 { 113481bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 113581bee695SCaleb Connolly reg = <0 0x00a90000 0 0x4000>; 113681bee695SCaleb Connolly clock-names = "se"; 113781bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 113881bee695SCaleb Connolly pinctrl-names = "default"; 113981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c12_default>; 114081bee695SCaleb Connolly interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 114181bee695SCaleb Connolly #address-cells = <1>; 114281bee695SCaleb Connolly #size-cells = <0>; 114381bee695SCaleb Connolly status = "disabled"; 114481bee695SCaleb Connolly }; 114581bee695SCaleb Connolly 114681bee695SCaleb Connolly i2c16: i2c@94000 { 114781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 114881bee695SCaleb Connolly reg = <0 0x0094000 0 0x4000>; 114981bee695SCaleb Connolly clock-names = "se"; 115081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 115181bee695SCaleb Connolly pinctrl-names = "default"; 115281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c16_default>; 115381bee695SCaleb Connolly interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 115481bee695SCaleb Connolly #address-cells = <1>; 115581bee695SCaleb Connolly #size-cells = <0>; 115681bee695SCaleb Connolly status = "disabled"; 115781bee695SCaleb Connolly }; 1158e13c6d14SVinod Koul }; 1159e13c6d14SVinod Koul 116005006290SFelipe Balbi gpi_dma2: dma-controller@c00000 { 116105006290SFelipe Balbi compatible = "qcom,sm8150-gpi-dma"; 116205006290SFelipe Balbi reg = <0 0xc00000 0 0x60000>; 116305006290SFelipe Balbi interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 116405006290SFelipe Balbi <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 116505006290SFelipe Balbi <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 116605006290SFelipe Balbi <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 116705006290SFelipe Balbi <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 116805006290SFelipe Balbi <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 116905006290SFelipe Balbi <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 117005006290SFelipe Balbi <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 117105006290SFelipe Balbi <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 117205006290SFelipe Balbi <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 117305006290SFelipe Balbi <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 117405006290SFelipe Balbi <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 117505006290SFelipe Balbi <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 117605006290SFelipe Balbi dma-channels = <13>; 117705006290SFelipe Balbi dma-channel-mask = <0xfa>; 117805006290SFelipe Balbi iommus = <&apps_smmu 0x07b6 0x0>; 117905006290SFelipe Balbi #dma-cells = <3>; 118005006290SFelipe Balbi status = "disabled"; 118105006290SFelipe Balbi }; 118205006290SFelipe Balbi 11839cf3ebd1SCaleb Connolly qupv3_id_2: geniqup@cc0000 { 11849cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 11859cf3ebd1SCaleb Connolly reg = <0x0 0x00cc0000 0x0 0x6000>; 11869cf3ebd1SCaleb Connolly 11879cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 11889cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 11899cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 11909cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x7a3 0x0>; 11919cf3ebd1SCaleb Connolly #address-cells = <2>; 11929cf3ebd1SCaleb Connolly #size-cells = <2>; 11939cf3ebd1SCaleb Connolly ranges; 11949cf3ebd1SCaleb Connolly status = "disabled"; 119581bee695SCaleb Connolly 119681bee695SCaleb Connolly i2c17: i2c@c80000 { 119781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 119881bee695SCaleb Connolly reg = <0 0x00c80000 0 0x4000>; 119981bee695SCaleb Connolly clock-names = "se"; 120081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 120181bee695SCaleb Connolly pinctrl-names = "default"; 120281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c17_default>; 120381bee695SCaleb Connolly interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 120481bee695SCaleb Connolly #address-cells = <1>; 120581bee695SCaleb Connolly #size-cells = <0>; 120681bee695SCaleb Connolly status = "disabled"; 120781bee695SCaleb Connolly }; 120881bee695SCaleb Connolly 120981bee695SCaleb Connolly i2c18: i2c@c84000 { 121081bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 121181bee695SCaleb Connolly reg = <0 0x00c84000 0 0x4000>; 121281bee695SCaleb Connolly clock-names = "se"; 121381bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 121481bee695SCaleb Connolly pinctrl-names = "default"; 121581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c18_default>; 121681bee695SCaleb Connolly interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 121781bee695SCaleb Connolly #address-cells = <1>; 121881bee695SCaleb Connolly #size-cells = <0>; 121981bee695SCaleb Connolly status = "disabled"; 122081bee695SCaleb Connolly }; 122181bee695SCaleb Connolly 122281bee695SCaleb Connolly i2c19: i2c@c88000 { 122381bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 122481bee695SCaleb Connolly reg = <0 0x00c88000 0 0x4000>; 122581bee695SCaleb Connolly clock-names = "se"; 122681bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 122781bee695SCaleb Connolly pinctrl-names = "default"; 122881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c19_default>; 122981bee695SCaleb Connolly interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 123081bee695SCaleb Connolly #address-cells = <1>; 123181bee695SCaleb Connolly #size-cells = <0>; 123281bee695SCaleb Connolly status = "disabled"; 123381bee695SCaleb Connolly }; 123481bee695SCaleb Connolly 123581bee695SCaleb Connolly i2c13: i2c@c8c000 { 123681bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 123781bee695SCaleb Connolly reg = <0 0x00c8c000 0 0x4000>; 123881bee695SCaleb Connolly clock-names = "se"; 123981bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 124081bee695SCaleb Connolly pinctrl-names = "default"; 124181bee695SCaleb Connolly pinctrl-0 = <&qup_i2c13_default>; 124281bee695SCaleb Connolly interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 124381bee695SCaleb Connolly #address-cells = <1>; 124481bee695SCaleb Connolly #size-cells = <0>; 124581bee695SCaleb Connolly status = "disabled"; 124681bee695SCaleb Connolly }; 124781bee695SCaleb Connolly 124881bee695SCaleb Connolly i2c14: i2c@c90000 { 124981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 125081bee695SCaleb Connolly reg = <0 0x00c90000 0 0x4000>; 125181bee695SCaleb Connolly clock-names = "se"; 125281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 125381bee695SCaleb Connolly pinctrl-names = "default"; 125481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c14_default>; 125581bee695SCaleb Connolly interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 125681bee695SCaleb Connolly #address-cells = <1>; 125781bee695SCaleb Connolly #size-cells = <0>; 125881bee695SCaleb Connolly status = "disabled"; 125981bee695SCaleb Connolly }; 126081bee695SCaleb Connolly 126181bee695SCaleb Connolly i2c15: i2c@c94000 { 126281bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 126381bee695SCaleb Connolly reg = <0 0x00c94000 0 0x4000>; 126481bee695SCaleb Connolly clock-names = "se"; 126581bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 126681bee695SCaleb Connolly pinctrl-names = "default"; 126781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c15_default>; 126881bee695SCaleb Connolly interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 126981bee695SCaleb Connolly #address-cells = <1>; 127081bee695SCaleb Connolly #size-cells = <0>; 127181bee695SCaleb Connolly status = "disabled"; 127281bee695SCaleb Connolly }; 12739cf3ebd1SCaleb Connolly }; 12749cf3ebd1SCaleb Connolly 127571a2fc6eSJonathan Marek config_noc: interconnect@1500000 { 127671a2fc6eSJonathan Marek compatible = "qcom,sm8150-config-noc"; 127771a2fc6eSJonathan Marek reg = <0 0x01500000 0 0x7400>; 127871a2fc6eSJonathan Marek #interconnect-cells = <1>; 127971a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 128071a2fc6eSJonathan Marek }; 128171a2fc6eSJonathan Marek 128271a2fc6eSJonathan Marek system_noc: interconnect@1620000 { 128371a2fc6eSJonathan Marek compatible = "qcom,sm8150-system-noc"; 128471a2fc6eSJonathan Marek reg = <0 0x01620000 0 0x19400>; 128571a2fc6eSJonathan Marek #interconnect-cells = <1>; 128671a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 128771a2fc6eSJonathan Marek }; 128871a2fc6eSJonathan Marek 128971a2fc6eSJonathan Marek mc_virt: interconnect@163a000 { 129071a2fc6eSJonathan Marek compatible = "qcom,sm8150-mc-virt"; 129171a2fc6eSJonathan Marek reg = <0 0x0163a000 0 0x1000>; 129271a2fc6eSJonathan Marek #interconnect-cells = <1>; 129371a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 129471a2fc6eSJonathan Marek }; 129571a2fc6eSJonathan Marek 129671a2fc6eSJonathan Marek aggre1_noc: interconnect@16e0000 { 129771a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre1-noc"; 129871a2fc6eSJonathan Marek reg = <0 0x016e0000 0 0xd080>; 129971a2fc6eSJonathan Marek #interconnect-cells = <1>; 130071a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 130171a2fc6eSJonathan Marek }; 130271a2fc6eSJonathan Marek 130371a2fc6eSJonathan Marek aggre2_noc: interconnect@1700000 { 130471a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre2-noc"; 130571a2fc6eSJonathan Marek reg = <0 0x01700000 0 0x20000>; 130671a2fc6eSJonathan Marek #interconnect-cells = <1>; 130771a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 130871a2fc6eSJonathan Marek }; 130971a2fc6eSJonathan Marek 131071a2fc6eSJonathan Marek compute_noc: interconnect@1720000 { 131171a2fc6eSJonathan Marek compatible = "qcom,sm8150-compute-noc"; 131271a2fc6eSJonathan Marek reg = <0 0x01720000 0 0x7000>; 131371a2fc6eSJonathan Marek #interconnect-cells = <1>; 131471a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 131571a2fc6eSJonathan Marek }; 131671a2fc6eSJonathan Marek 131771a2fc6eSJonathan Marek mmss_noc: interconnect@1740000 { 131871a2fc6eSJonathan Marek compatible = "qcom,sm8150-mmss-noc"; 131971a2fc6eSJonathan Marek reg = <0 0x01740000 0 0x1c100>; 132071a2fc6eSJonathan Marek #interconnect-cells = <1>; 132171a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 132271a2fc6eSJonathan Marek }; 132371a2fc6eSJonathan Marek 1324bb1f7cf6SSouradeep Chowdhury system-cache-controller@9200000 { 1325bb1f7cf6SSouradeep Chowdhury compatible = "qcom,sm8150-llcc"; 1326bb1f7cf6SSouradeep Chowdhury reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 1327bb1f7cf6SSouradeep Chowdhury reg-names = "llcc_base", "llcc_broadcast_base"; 1328bb1f7cf6SSouradeep Chowdhury interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1329bb1f7cf6SSouradeep Chowdhury }; 1330bb1f7cf6SSouradeep Chowdhury 13313834a2e9SVinod Koul ufs_mem_hc: ufshc@1d84000 { 13323834a2e9SVinod Koul compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 13333834a2e9SVinod Koul "jedec,ufs-2.0"; 133498aee1e3SBhupesh Sharma reg = <0 0x01d84000 0 0x2500>, 133598aee1e3SBhupesh Sharma <0 0x01d90000 0 0x8000>; 133698aee1e3SBhupesh Sharma reg-names = "std", "ice"; 13373834a2e9SVinod Koul interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 13383834a2e9SVinod Koul phys = <&ufs_mem_phy_lanes>; 13393834a2e9SVinod Koul phy-names = "ufsphy"; 13403834a2e9SVinod Koul lanes-per-direction = <2>; 13413834a2e9SVinod Koul #reset-cells = <1>; 13423834a2e9SVinod Koul resets = <&gcc GCC_UFS_PHY_BCR>; 13433834a2e9SVinod Koul reset-names = "rst"; 13443834a2e9SVinod Koul 134548156232SJonathan Marek iommus = <&apps_smmu 0x300 0>; 134648156232SJonathan Marek 13473834a2e9SVinod Koul clock-names = 13483834a2e9SVinod Koul "core_clk", 13493834a2e9SVinod Koul "bus_aggr_clk", 13503834a2e9SVinod Koul "iface_clk", 13513834a2e9SVinod Koul "core_clk_unipro", 13523834a2e9SVinod Koul "ref_clk", 13533834a2e9SVinod Koul "tx_lane0_sync_clk", 13543834a2e9SVinod Koul "rx_lane0_sync_clk", 135598aee1e3SBhupesh Sharma "rx_lane1_sync_clk", 135698aee1e3SBhupesh Sharma "ice_core_clk"; 13573834a2e9SVinod Koul clocks = 13583834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AXI_CLK>, 13593834a2e9SVinod Koul <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 13603834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AHB_CLK>, 13613834a2e9SVinod Koul <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 13623834a2e9SVinod Koul <&rpmhcc RPMH_CXO_CLK>, 13633834a2e9SVinod Koul <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 13643834a2e9SVinod Koul <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 136598aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 136698aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 13673834a2e9SVinod Koul freq-table-hz = 13683834a2e9SVinod Koul <37500000 300000000>, 13693834a2e9SVinod Koul <0 0>, 13703834a2e9SVinod Koul <0 0>, 13713834a2e9SVinod Koul <37500000 300000000>, 13723834a2e9SVinod Koul <0 0>, 13733834a2e9SVinod Koul <0 0>, 13743834a2e9SVinod Koul <0 0>, 137598aee1e3SBhupesh Sharma <0 0>, 137698aee1e3SBhupesh Sharma <0 300000000>; 13773834a2e9SVinod Koul 13783834a2e9SVinod Koul status = "disabled"; 13793834a2e9SVinod Koul }; 13803834a2e9SVinod Koul 13813834a2e9SVinod Koul ufs_mem_phy: phy@1d87000 { 13823834a2e9SVinod Koul compatible = "qcom,sm8150-qmp-ufs-phy"; 1383c79ec891SVinod Koul reg = <0 0x01d87000 0 0x1c0>; 13843834a2e9SVinod Koul #address-cells = <2>; 13853834a2e9SVinod Koul #size-cells = <2>; 13863834a2e9SVinod Koul ranges; 13873834a2e9SVinod Koul clock-names = "ref", 13883834a2e9SVinod Koul "ref_aux"; 13893834a2e9SVinod Koul clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 13903834a2e9SVinod Koul <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 13913834a2e9SVinod Koul 13923834a2e9SVinod Koul resets = <&ufs_mem_hc 0>; 13933834a2e9SVinod Koul reset-names = "ufsphy"; 13943834a2e9SVinod Koul status = "disabled"; 13953834a2e9SVinod Koul 13963834a2e9SVinod Koul ufs_mem_phy_lanes: lanes@1d87400 { 13973834a2e9SVinod Koul reg = <0 0x01d87400 0 0x108>, 13983834a2e9SVinod Koul <0 0x01d87600 0 0x1e0>, 13993834a2e9SVinod Koul <0 0x01d87c00 0 0x1dc>, 14003834a2e9SVinod Koul <0 0x01d87800 0 0x108>, 14013834a2e9SVinod Koul <0 0x01d87a00 0 0x1e0>; 14023834a2e9SVinod Koul #phy-cells = <0>; 14033834a2e9SVinod Koul }; 14043834a2e9SVinod Koul }; 14053834a2e9SVinod Koul 140671a2fc6eSJonathan Marek ipa_virt: interconnect@1e00000 { 140771a2fc6eSJonathan Marek compatible = "qcom,sm8150-ipa-virt"; 140871a2fc6eSJonathan Marek reg = <0 0x01e00000 0 0x1000>; 140971a2fc6eSJonathan Marek #interconnect-cells = <1>; 141071a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 141171a2fc6eSJonathan Marek }; 141271a2fc6eSJonathan Marek 1413d8cf9372SVinod Koul tcsr_mutex_regs: syscon@1f40000 { 1414d8cf9372SVinod Koul compatible = "syscon"; 1415d8cf9372SVinod Koul reg = <0x0 0x01f40000 0x0 0x40000>; 1416d8cf9372SVinod Koul }; 1417d8cf9372SVinod Koul 141849076351SSibi Sankar remoteproc_slpi: remoteproc@2400000 { 141949076351SSibi Sankar compatible = "qcom,sm8150-slpi-pas"; 142049076351SSibi Sankar reg = <0x0 0x02400000 0x0 0x4040>; 142149076351SSibi Sankar 142249076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 142349076351SSibi Sankar <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 142449076351SSibi Sankar <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 142549076351SSibi Sankar <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 142649076351SSibi Sankar <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 142749076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 142849076351SSibi Sankar "handover", "stop-ack"; 142949076351SSibi Sankar 143049076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 143149076351SSibi Sankar clock-names = "xo"; 143249076351SSibi Sankar 143349076351SSibi Sankar power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, 1434d0770627SBjorn Andersson <&rpmhpd 3>, 1435d0770627SBjorn Andersson <&rpmhpd 2>; 143649076351SSibi Sankar power-domain-names = "load_state", "lcx", "lmx"; 143749076351SSibi Sankar 143849076351SSibi Sankar memory-region = <&slpi_mem>; 143949076351SSibi Sankar 144049076351SSibi Sankar qcom,smem-states = <&slpi_smp2p_out 0>; 144149076351SSibi Sankar qcom,smem-state-names = "stop"; 144249076351SSibi Sankar 144349076351SSibi Sankar status = "disabled"; 144449076351SSibi Sankar 144549076351SSibi Sankar glink-edge { 144649076351SSibi Sankar interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 144749076351SSibi Sankar label = "dsps"; 144849076351SSibi Sankar qcom,remote-pid = <3>; 144949076351SSibi Sankar mboxes = <&apss_shared 24>; 145049076351SSibi Sankar }; 145149076351SSibi Sankar }; 145249076351SSibi Sankar 1453f30ac26dSJonathan Marek gpu: gpu@2c00000 { 1454f30ac26dSJonathan Marek /* 1455f30ac26dSJonathan Marek * note: the amd,imageon compatible makes it possible 1456f30ac26dSJonathan Marek * to use the drm/msm driver without the display node, 1457f30ac26dSJonathan Marek * make sure to remove it when display node is added 1458f30ac26dSJonathan Marek */ 1459f30ac26dSJonathan Marek compatible = "qcom,adreno-640.1", 1460f30ac26dSJonathan Marek "qcom,adreno", 1461f30ac26dSJonathan Marek "amd,imageon"; 1462f30ac26dSJonathan Marek #stream-id-cells = <16>; 1463f30ac26dSJonathan Marek 1464f30ac26dSJonathan Marek reg = <0 0x02c00000 0 0x40000>; 1465f30ac26dSJonathan Marek reg-names = "kgsl_3d0_reg_memory"; 1466f30ac26dSJonathan Marek 1467f30ac26dSJonathan Marek interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1468f30ac26dSJonathan Marek 1469f30ac26dSJonathan Marek iommus = <&adreno_smmu 0 0x401>; 1470f30ac26dSJonathan Marek 1471f30ac26dSJonathan Marek operating-points-v2 = <&gpu_opp_table>; 1472f30ac26dSJonathan Marek 1473f30ac26dSJonathan Marek qcom,gmu = <&gmu>; 1474f30ac26dSJonathan Marek 1475b1dc3c6bSKonrad Dybcio status = "disabled"; 1476b1dc3c6bSKonrad Dybcio 1477f30ac26dSJonathan Marek zap-shader { 1478f30ac26dSJonathan Marek memory-region = <&gpu_mem>; 1479f30ac26dSJonathan Marek }; 1480f30ac26dSJonathan Marek 1481f30ac26dSJonathan Marek /* note: downstream checks gpu binning for 675 Mhz */ 1482f30ac26dSJonathan Marek gpu_opp_table: opp-table { 1483f30ac26dSJonathan Marek compatible = "operating-points-v2"; 1484f30ac26dSJonathan Marek 1485f30ac26dSJonathan Marek opp-675000000 { 1486f30ac26dSJonathan Marek opp-hz = /bits/ 64 <675000000>; 1487f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1488f30ac26dSJonathan Marek }; 1489f30ac26dSJonathan Marek 1490f30ac26dSJonathan Marek opp-585000000 { 1491f30ac26dSJonathan Marek opp-hz = /bits/ 64 <585000000>; 1492f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1493f30ac26dSJonathan Marek }; 1494f30ac26dSJonathan Marek 1495f30ac26dSJonathan Marek opp-499200000 { 1496f30ac26dSJonathan Marek opp-hz = /bits/ 64 <499200000>; 1497f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1498f30ac26dSJonathan Marek }; 1499f30ac26dSJonathan Marek 1500f30ac26dSJonathan Marek opp-427000000 { 1501f30ac26dSJonathan Marek opp-hz = /bits/ 64 <427000000>; 1502f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1503f30ac26dSJonathan Marek }; 1504f30ac26dSJonathan Marek 1505f30ac26dSJonathan Marek opp-345000000 { 1506f30ac26dSJonathan Marek opp-hz = /bits/ 64 <345000000>; 1507f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1508f30ac26dSJonathan Marek }; 1509f30ac26dSJonathan Marek 1510f30ac26dSJonathan Marek opp-257000000 { 1511f30ac26dSJonathan Marek opp-hz = /bits/ 64 <257000000>; 1512f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1513f30ac26dSJonathan Marek }; 1514f30ac26dSJonathan Marek }; 1515f30ac26dSJonathan Marek }; 1516f30ac26dSJonathan Marek 1517f30ac26dSJonathan Marek gmu: gmu@2c6a000 { 1518f30ac26dSJonathan Marek compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 1519f30ac26dSJonathan Marek 1520f30ac26dSJonathan Marek reg = <0 0x02c6a000 0 0x30000>, 1521f30ac26dSJonathan Marek <0 0x0b290000 0 0x10000>, 1522f30ac26dSJonathan Marek <0 0x0b490000 0 0x10000>; 1523f30ac26dSJonathan Marek reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 1524f30ac26dSJonathan Marek 1525f30ac26dSJonathan Marek interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1526f30ac26dSJonathan Marek <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1527f30ac26dSJonathan Marek interrupt-names = "hfi", "gmu"; 1528f30ac26dSJonathan Marek 1529f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 1530f1269916SJonathan Marek <&gpucc GPU_CC_CX_GMU_CLK>, 1531f1269916SJonathan Marek <&gpucc GPU_CC_CXO_CLK>, 1532f30ac26dSJonathan Marek <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1533f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1534f30ac26dSJonathan Marek clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 1535f30ac26dSJonathan Marek 1536f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>, 1537f1269916SJonathan Marek <&gpucc GPU_GX_GDSC>; 1538f30ac26dSJonathan Marek power-domain-names = "cx", "gx"; 1539f30ac26dSJonathan Marek 1540f30ac26dSJonathan Marek iommus = <&adreno_smmu 5 0x400>; 1541f30ac26dSJonathan Marek 1542f30ac26dSJonathan Marek operating-points-v2 = <&gmu_opp_table>; 1543f30ac26dSJonathan Marek 1544b1dc3c6bSKonrad Dybcio status = "disabled"; 1545b1dc3c6bSKonrad Dybcio 1546f30ac26dSJonathan Marek gmu_opp_table: opp-table { 1547f30ac26dSJonathan Marek compatible = "operating-points-v2"; 1548f30ac26dSJonathan Marek 1549f30ac26dSJonathan Marek opp-200000000 { 1550f30ac26dSJonathan Marek opp-hz = /bits/ 64 <200000000>; 1551f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1552f30ac26dSJonathan Marek }; 1553f30ac26dSJonathan Marek }; 1554f30ac26dSJonathan Marek }; 1555f30ac26dSJonathan Marek 1556f30ac26dSJonathan Marek gpucc: clock-controller@2c90000 { 1557f30ac26dSJonathan Marek compatible = "qcom,sm8150-gpucc"; 1558f30ac26dSJonathan Marek reg = <0 0x02c90000 0 0x9000>; 1559f30ac26dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>, 1560f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1561f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1562f30ac26dSJonathan Marek clock-names = "bi_tcxo", 1563f30ac26dSJonathan Marek "gcc_gpu_gpll0_clk_src", 1564f30ac26dSJonathan Marek "gcc_gpu_gpll0_div_clk_src"; 1565f30ac26dSJonathan Marek #clock-cells = <1>; 1566f30ac26dSJonathan Marek #reset-cells = <1>; 1567f30ac26dSJonathan Marek #power-domain-cells = <1>; 1568f30ac26dSJonathan Marek }; 1569f30ac26dSJonathan Marek 1570f30ac26dSJonathan Marek adreno_smmu: iommu@2ca0000 { 1571f30ac26dSJonathan Marek compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 1572f30ac26dSJonathan Marek reg = <0 0x02ca0000 0 0x10000>; 1573f30ac26dSJonathan Marek #iommu-cells = <2>; 1574f30ac26dSJonathan Marek #global-interrupts = <1>; 1575f30ac26dSJonathan Marek interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 1576f30ac26dSJonathan Marek <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1577f30ac26dSJonathan Marek <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1578f30ac26dSJonathan Marek <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1579f30ac26dSJonathan Marek <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1580f30ac26dSJonathan Marek <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1581f30ac26dSJonathan Marek <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1582f30ac26dSJonathan Marek <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 1583f30ac26dSJonathan Marek <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 1584f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 1585f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1586f30ac26dSJonathan Marek <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1587f30ac26dSJonathan Marek clock-names = "ahb", "bus", "iface"; 1588f30ac26dSJonathan Marek 1589f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>; 1590f30ac26dSJonathan Marek }; 1591f30ac26dSJonathan Marek 1592e13c6d14SVinod Koul tlmm: pinctrl@3100000 { 1593e13c6d14SVinod Koul compatible = "qcom,sm8150-pinctrl"; 1594e13c6d14SVinod Koul reg = <0x0 0x03100000 0x0 0x300000>, 1595e13c6d14SVinod Koul <0x0 0x03500000 0x0 0x300000>, 1596e13c6d14SVinod Koul <0x0 0x03900000 0x0 0x300000>, 1597e13c6d14SVinod Koul <0x0 0x03D00000 0x0 0x300000>; 1598e13c6d14SVinod Koul reg-names = "west", "east", "north", "south"; 1599e13c6d14SVinod Koul interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1600de3abdf3SShawn Guo gpio-ranges = <&tlmm 0 0 176>; 1601e13c6d14SVinod Koul gpio-controller; 1602e13c6d14SVinod Koul #gpio-cells = <2>; 1603e13c6d14SVinod Koul interrupt-controller; 1604e13c6d14SVinod Koul #interrupt-cells = <2>; 160581bee695SCaleb Connolly 160681bee695SCaleb Connolly qup_i2c0_default: qup-i2c0-default { 160781bee695SCaleb Connolly mux { 160881bee695SCaleb Connolly pins = "gpio0", "gpio1"; 160981bee695SCaleb Connolly function = "qup0"; 161081bee695SCaleb Connolly }; 161181bee695SCaleb Connolly 161281bee695SCaleb Connolly config { 161381bee695SCaleb Connolly pins = "gpio0", "gpio1"; 161481bee695SCaleb Connolly drive-strength = <0x02>; 161581bee695SCaleb Connolly bias-disable; 161681bee695SCaleb Connolly }; 161781bee695SCaleb Connolly }; 161881bee695SCaleb Connolly 161981bee695SCaleb Connolly qup_i2c1_default: qup-i2c1-default { 162081bee695SCaleb Connolly mux { 162181bee695SCaleb Connolly pins = "gpio114", "gpio115"; 162281bee695SCaleb Connolly function = "qup1"; 162381bee695SCaleb Connolly }; 162481bee695SCaleb Connolly 162581bee695SCaleb Connolly config { 162681bee695SCaleb Connolly pins = "gpio114", "gpio115"; 162781bee695SCaleb Connolly drive-strength = <0x02>; 162881bee695SCaleb Connolly bias-disable; 162981bee695SCaleb Connolly }; 163081bee695SCaleb Connolly }; 163181bee695SCaleb Connolly 163281bee695SCaleb Connolly qup_i2c2_default: qup-i2c2-default { 163381bee695SCaleb Connolly mux { 163481bee695SCaleb Connolly pins = "gpio126", "gpio127"; 163581bee695SCaleb Connolly function = "qup2"; 163681bee695SCaleb Connolly }; 163781bee695SCaleb Connolly 163881bee695SCaleb Connolly config { 163981bee695SCaleb Connolly pins = "gpio126", "gpio127"; 164081bee695SCaleb Connolly drive-strength = <0x02>; 164181bee695SCaleb Connolly bias-disable; 164281bee695SCaleb Connolly }; 164381bee695SCaleb Connolly }; 164481bee695SCaleb Connolly 164581bee695SCaleb Connolly qup_i2c3_default: qup-i2c3-default { 164681bee695SCaleb Connolly mux { 164781bee695SCaleb Connolly pins = "gpio144", "gpio145"; 164881bee695SCaleb Connolly function = "qup3"; 164981bee695SCaleb Connolly }; 165081bee695SCaleb Connolly 165181bee695SCaleb Connolly config { 165281bee695SCaleb Connolly pins = "gpio144", "gpio145"; 165381bee695SCaleb Connolly drive-strength = <0x02>; 165481bee695SCaleb Connolly bias-disable; 165581bee695SCaleb Connolly }; 165681bee695SCaleb Connolly }; 165781bee695SCaleb Connolly 165881bee695SCaleb Connolly qup_i2c4_default: qup-i2c4-default { 165981bee695SCaleb Connolly mux { 166081bee695SCaleb Connolly pins = "gpio51", "gpio52"; 166181bee695SCaleb Connolly function = "qup4"; 166281bee695SCaleb Connolly }; 166381bee695SCaleb Connolly 166481bee695SCaleb Connolly config { 166581bee695SCaleb Connolly pins = "gpio51", "gpio52"; 166681bee695SCaleb Connolly drive-strength = <0x02>; 166781bee695SCaleb Connolly bias-disable; 166881bee695SCaleb Connolly }; 166981bee695SCaleb Connolly }; 167081bee695SCaleb Connolly 167181bee695SCaleb Connolly qup_i2c5_default: qup-i2c5-default { 167281bee695SCaleb Connolly mux { 167381bee695SCaleb Connolly pins = "gpio121", "gpio122"; 167481bee695SCaleb Connolly function = "qup5"; 167581bee695SCaleb Connolly }; 167681bee695SCaleb Connolly 167781bee695SCaleb Connolly config { 167881bee695SCaleb Connolly pins = "gpio121", "gpio122"; 167981bee695SCaleb Connolly drive-strength = <0x02>; 168081bee695SCaleb Connolly bias-disable; 168181bee695SCaleb Connolly }; 168281bee695SCaleb Connolly }; 168381bee695SCaleb Connolly 168481bee695SCaleb Connolly qup_i2c6_default: qup-i2c6-default { 168581bee695SCaleb Connolly mux { 168681bee695SCaleb Connolly pins = "gpio6", "gpio7"; 168781bee695SCaleb Connolly function = "qup6"; 168881bee695SCaleb Connolly }; 168981bee695SCaleb Connolly 169081bee695SCaleb Connolly config { 169181bee695SCaleb Connolly pins = "gpio6", "gpio7"; 169281bee695SCaleb Connolly drive-strength = <0x02>; 169381bee695SCaleb Connolly bias-disable; 169481bee695SCaleb Connolly }; 169581bee695SCaleb Connolly }; 169681bee695SCaleb Connolly 169781bee695SCaleb Connolly qup_i2c7_default: qup-i2c7-default { 169881bee695SCaleb Connolly mux { 169981bee695SCaleb Connolly pins = "gpio98", "gpio99"; 170081bee695SCaleb Connolly function = "qup7"; 170181bee695SCaleb Connolly }; 170281bee695SCaleb Connolly 170381bee695SCaleb Connolly config { 170481bee695SCaleb Connolly pins = "gpio98", "gpio99"; 170581bee695SCaleb Connolly drive-strength = <0x02>; 170681bee695SCaleb Connolly bias-disable; 170781bee695SCaleb Connolly }; 170881bee695SCaleb Connolly }; 170981bee695SCaleb Connolly 171081bee695SCaleb Connolly qup_i2c8_default: qup-i2c8-default { 171181bee695SCaleb Connolly mux { 171281bee695SCaleb Connolly pins = "gpio88", "gpio89"; 171381bee695SCaleb Connolly function = "qup8"; 171481bee695SCaleb Connolly }; 171581bee695SCaleb Connolly 171681bee695SCaleb Connolly config { 171781bee695SCaleb Connolly pins = "gpio88", "gpio89"; 171881bee695SCaleb Connolly drive-strength = <0x02>; 171981bee695SCaleb Connolly bias-disable; 172081bee695SCaleb Connolly }; 172181bee695SCaleb Connolly }; 172281bee695SCaleb Connolly 172381bee695SCaleb Connolly qup_i2c9_default: qup-i2c9-default { 172481bee695SCaleb Connolly mux { 172581bee695SCaleb Connolly pins = "gpio39", "gpio40"; 172681bee695SCaleb Connolly function = "qup9"; 172781bee695SCaleb Connolly }; 172881bee695SCaleb Connolly 172981bee695SCaleb Connolly config { 173081bee695SCaleb Connolly pins = "gpio39", "gpio40"; 173181bee695SCaleb Connolly drive-strength = <0x02>; 173281bee695SCaleb Connolly bias-disable; 173381bee695SCaleb Connolly }; 173481bee695SCaleb Connolly }; 173581bee695SCaleb Connolly 173681bee695SCaleb Connolly qup_i2c10_default: qup-i2c10-default { 173781bee695SCaleb Connolly mux { 173881bee695SCaleb Connolly pins = "gpio9", "gpio10"; 173981bee695SCaleb Connolly function = "qup10"; 174081bee695SCaleb Connolly }; 174181bee695SCaleb Connolly 174281bee695SCaleb Connolly config { 174381bee695SCaleb Connolly pins = "gpio9", "gpio10"; 174481bee695SCaleb Connolly drive-strength = <0x02>; 174581bee695SCaleb Connolly bias-disable; 174681bee695SCaleb Connolly }; 174781bee695SCaleb Connolly }; 174881bee695SCaleb Connolly 174981bee695SCaleb Connolly qup_i2c11_default: qup-i2c11-default { 175081bee695SCaleb Connolly mux { 175181bee695SCaleb Connolly pins = "gpio94", "gpio95"; 175281bee695SCaleb Connolly function = "qup11"; 175381bee695SCaleb Connolly }; 175481bee695SCaleb Connolly 175581bee695SCaleb Connolly config { 175681bee695SCaleb Connolly pins = "gpio94", "gpio95"; 175781bee695SCaleb Connolly drive-strength = <0x02>; 175881bee695SCaleb Connolly bias-disable; 175981bee695SCaleb Connolly }; 176081bee695SCaleb Connolly }; 176181bee695SCaleb Connolly 176281bee695SCaleb Connolly qup_i2c12_default: qup-i2c12-default { 176381bee695SCaleb Connolly mux { 176481bee695SCaleb Connolly pins = "gpio83", "gpio84"; 176581bee695SCaleb Connolly function = "qup12"; 176681bee695SCaleb Connolly }; 176781bee695SCaleb Connolly 176881bee695SCaleb Connolly config { 176981bee695SCaleb Connolly pins = "gpio83", "gpio84"; 177081bee695SCaleb Connolly drive-strength = <0x02>; 177181bee695SCaleb Connolly bias-disable; 177281bee695SCaleb Connolly }; 177381bee695SCaleb Connolly }; 177481bee695SCaleb Connolly 177581bee695SCaleb Connolly qup_i2c13_default: qup-i2c13-default { 177681bee695SCaleb Connolly mux { 177781bee695SCaleb Connolly pins = "gpio43", "gpio44"; 177881bee695SCaleb Connolly function = "qup13"; 177981bee695SCaleb Connolly }; 178081bee695SCaleb Connolly 178181bee695SCaleb Connolly config { 178281bee695SCaleb Connolly pins = "gpio43", "gpio44"; 178381bee695SCaleb Connolly drive-strength = <0x02>; 178481bee695SCaleb Connolly bias-disable; 178581bee695SCaleb Connolly }; 178681bee695SCaleb Connolly }; 178781bee695SCaleb Connolly 178881bee695SCaleb Connolly qup_i2c14_default: qup-i2c14-default { 178981bee695SCaleb Connolly mux { 179081bee695SCaleb Connolly pins = "gpio47", "gpio48"; 179181bee695SCaleb Connolly function = "qup14"; 179281bee695SCaleb Connolly }; 179381bee695SCaleb Connolly 179481bee695SCaleb Connolly config { 179581bee695SCaleb Connolly pins = "gpio47", "gpio48"; 179681bee695SCaleb Connolly drive-strength = <0x02>; 179781bee695SCaleb Connolly bias-disable; 179881bee695SCaleb Connolly }; 179981bee695SCaleb Connolly }; 180081bee695SCaleb Connolly 180181bee695SCaleb Connolly qup_i2c15_default: qup-i2c15-default { 180281bee695SCaleb Connolly mux { 180381bee695SCaleb Connolly pins = "gpio27", "gpio28"; 180481bee695SCaleb Connolly function = "qup15"; 180581bee695SCaleb Connolly }; 180681bee695SCaleb Connolly 180781bee695SCaleb Connolly config { 180881bee695SCaleb Connolly pins = "gpio27", "gpio28"; 180981bee695SCaleb Connolly drive-strength = <0x02>; 181081bee695SCaleb Connolly bias-disable; 181181bee695SCaleb Connolly }; 181281bee695SCaleb Connolly }; 181381bee695SCaleb Connolly 181481bee695SCaleb Connolly qup_i2c16_default: qup-i2c16-default { 181581bee695SCaleb Connolly mux { 181681bee695SCaleb Connolly pins = "gpio86", "gpio85"; 181781bee695SCaleb Connolly function = "qup16"; 181881bee695SCaleb Connolly }; 181981bee695SCaleb Connolly 182081bee695SCaleb Connolly config { 182181bee695SCaleb Connolly pins = "gpio86", "gpio85"; 182281bee695SCaleb Connolly drive-strength = <0x02>; 182381bee695SCaleb Connolly bias-disable; 182481bee695SCaleb Connolly }; 182581bee695SCaleb Connolly }; 182681bee695SCaleb Connolly 182781bee695SCaleb Connolly qup_i2c17_default: qup-i2c17-default { 182881bee695SCaleb Connolly mux { 182981bee695SCaleb Connolly pins = "gpio55", "gpio56"; 183081bee695SCaleb Connolly function = "qup17"; 183181bee695SCaleb Connolly }; 183281bee695SCaleb Connolly 183381bee695SCaleb Connolly config { 183481bee695SCaleb Connolly pins = "gpio55", "gpio56"; 183581bee695SCaleb Connolly drive-strength = <0x02>; 183681bee695SCaleb Connolly bias-disable; 183781bee695SCaleb Connolly }; 183881bee695SCaleb Connolly }; 183981bee695SCaleb Connolly 184081bee695SCaleb Connolly qup_i2c18_default: qup-i2c18-default { 184181bee695SCaleb Connolly mux { 184281bee695SCaleb Connolly pins = "gpio23", "gpio24"; 184381bee695SCaleb Connolly function = "qup18"; 184481bee695SCaleb Connolly }; 184581bee695SCaleb Connolly 184681bee695SCaleb Connolly config { 184781bee695SCaleb Connolly pins = "gpio23", "gpio24"; 184881bee695SCaleb Connolly drive-strength = <0x02>; 184981bee695SCaleb Connolly bias-disable; 185081bee695SCaleb Connolly }; 185181bee695SCaleb Connolly }; 185281bee695SCaleb Connolly 185381bee695SCaleb Connolly qup_i2c19_default: qup-i2c19-default { 185481bee695SCaleb Connolly mux { 185581bee695SCaleb Connolly pins = "gpio57", "gpio58"; 185681bee695SCaleb Connolly function = "qup19"; 185781bee695SCaleb Connolly }; 185881bee695SCaleb Connolly 185981bee695SCaleb Connolly config { 186081bee695SCaleb Connolly pins = "gpio57", "gpio58"; 186181bee695SCaleb Connolly drive-strength = <0x02>; 186281bee695SCaleb Connolly bias-disable; 186381bee695SCaleb Connolly }; 186481bee695SCaleb Connolly }; 1865e13c6d14SVinod Koul }; 1866e13c6d14SVinod Koul 186749076351SSibi Sankar remoteproc_mpss: remoteproc@4080000 { 186849076351SSibi Sankar compatible = "qcom,sm8150-mpss-pas"; 186949076351SSibi Sankar reg = <0x0 0x04080000 0x0 0x4040>; 187049076351SSibi Sankar 187149076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 187249076351SSibi Sankar <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 187349076351SSibi Sankar <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 187449076351SSibi Sankar <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 187549076351SSibi Sankar <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 187649076351SSibi Sankar <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 187749076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", "handover", 187849076351SSibi Sankar "stop-ack", "shutdown-ack"; 187949076351SSibi Sankar 188049076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 188149076351SSibi Sankar clock-names = "xo"; 188249076351SSibi Sankar 188349076351SSibi Sankar power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, 1884d0770627SBjorn Andersson <&rpmhpd 7>, 1885d0770627SBjorn Andersson <&rpmhpd 0>; 188649076351SSibi Sankar power-domain-names = "load_state", "cx", "mss"; 188749076351SSibi Sankar 188849076351SSibi Sankar memory-region = <&mpss_mem>; 188949076351SSibi Sankar 189049076351SSibi Sankar qcom,smem-states = <&modem_smp2p_out 0>; 189149076351SSibi Sankar qcom,smem-state-names = "stop"; 189249076351SSibi Sankar 1893b1dc3c6bSKonrad Dybcio status = "disabled"; 1894b1dc3c6bSKonrad Dybcio 189549076351SSibi Sankar glink-edge { 189649076351SSibi Sankar interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 189749076351SSibi Sankar label = "modem"; 189849076351SSibi Sankar qcom,remote-pid = <1>; 189949076351SSibi Sankar mboxes = <&apss_shared 12>; 190049076351SSibi Sankar }; 190149076351SSibi Sankar }; 190249076351SSibi Sankar 190324244cefSSai Prakash Ranjan stm@6002000 { 190424244cefSSai Prakash Ranjan compatible = "arm,coresight-stm", "arm,primecell"; 190524244cefSSai Prakash Ranjan reg = <0 0x06002000 0 0x1000>, 190624244cefSSai Prakash Ranjan <0 0x16280000 0 0x180000>; 190724244cefSSai Prakash Ranjan reg-names = "stm-base", "stm-stimulus-base"; 190824244cefSSai Prakash Ranjan 190924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 191024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 191124244cefSSai Prakash Ranjan 191224244cefSSai Prakash Ranjan out-ports { 191324244cefSSai Prakash Ranjan port { 191424244cefSSai Prakash Ranjan stm_out: endpoint { 191524244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_in7>; 191624244cefSSai Prakash Ranjan }; 191724244cefSSai Prakash Ranjan }; 191824244cefSSai Prakash Ranjan }; 191924244cefSSai Prakash Ranjan }; 192024244cefSSai Prakash Ranjan 192124244cefSSai Prakash Ranjan funnel@6041000 { 192224244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 192324244cefSSai Prakash Ranjan reg = <0 0x06041000 0 0x1000>; 192424244cefSSai Prakash Ranjan 192524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 192624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 192724244cefSSai Prakash Ranjan 192824244cefSSai Prakash Ranjan out-ports { 192924244cefSSai Prakash Ranjan port { 193024244cefSSai Prakash Ranjan funnel0_out: endpoint { 193124244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in0>; 193224244cefSSai Prakash Ranjan }; 193324244cefSSai Prakash Ranjan }; 193424244cefSSai Prakash Ranjan }; 193524244cefSSai Prakash Ranjan 193624244cefSSai Prakash Ranjan in-ports { 193724244cefSSai Prakash Ranjan #address-cells = <1>; 193824244cefSSai Prakash Ranjan #size-cells = <0>; 193924244cefSSai Prakash Ranjan 194024244cefSSai Prakash Ranjan port@7 { 194124244cefSSai Prakash Ranjan reg = <7>; 194224244cefSSai Prakash Ranjan funnel0_in7: endpoint { 194324244cefSSai Prakash Ranjan remote-endpoint = <&stm_out>; 194424244cefSSai Prakash Ranjan }; 194524244cefSSai Prakash Ranjan }; 194624244cefSSai Prakash Ranjan }; 194724244cefSSai Prakash Ranjan }; 194824244cefSSai Prakash Ranjan 194924244cefSSai Prakash Ranjan funnel@6042000 { 195024244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 195124244cefSSai Prakash Ranjan reg = <0 0x06042000 0 0x1000>; 195224244cefSSai Prakash Ranjan 195324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 195424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 195524244cefSSai Prakash Ranjan 195624244cefSSai Prakash Ranjan out-ports { 195724244cefSSai Prakash Ranjan port { 195824244cefSSai Prakash Ranjan funnel1_out: endpoint { 195924244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in1>; 196024244cefSSai Prakash Ranjan }; 196124244cefSSai Prakash Ranjan }; 196224244cefSSai Prakash Ranjan }; 196324244cefSSai Prakash Ranjan 196424244cefSSai Prakash Ranjan in-ports { 196524244cefSSai Prakash Ranjan #address-cells = <1>; 196624244cefSSai Prakash Ranjan #size-cells = <0>; 196724244cefSSai Prakash Ranjan 196824244cefSSai Prakash Ranjan port@4 { 196924244cefSSai Prakash Ranjan reg = <4>; 197024244cefSSai Prakash Ranjan funnel1_in4: endpoint { 197124244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_out>; 197224244cefSSai Prakash Ranjan }; 197324244cefSSai Prakash Ranjan }; 197424244cefSSai Prakash Ranjan }; 197524244cefSSai Prakash Ranjan }; 197624244cefSSai Prakash Ranjan 197724244cefSSai Prakash Ranjan funnel@6043000 { 197824244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 197924244cefSSai Prakash Ranjan reg = <0 0x06043000 0 0x1000>; 198024244cefSSai Prakash Ranjan 198124244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 198224244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 198324244cefSSai Prakash Ranjan 198424244cefSSai Prakash Ranjan out-ports { 198524244cefSSai Prakash Ranjan port { 198624244cefSSai Prakash Ranjan funnel2_out: endpoint { 198724244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in2>; 198824244cefSSai Prakash Ranjan }; 198924244cefSSai Prakash Ranjan }; 199024244cefSSai Prakash Ranjan }; 199124244cefSSai Prakash Ranjan 199224244cefSSai Prakash Ranjan in-ports { 199324244cefSSai Prakash Ranjan #address-cells = <1>; 199424244cefSSai Prakash Ranjan #size-cells = <0>; 199524244cefSSai Prakash Ranjan 199624244cefSSai Prakash Ranjan port@2 { 199724244cefSSai Prakash Ranjan reg = <2>; 199824244cefSSai Prakash Ranjan funnel2_in2: endpoint { 199924244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_out>; 200024244cefSSai Prakash Ranjan }; 200124244cefSSai Prakash Ranjan }; 200224244cefSSai Prakash Ranjan }; 200324244cefSSai Prakash Ranjan }; 200424244cefSSai Prakash Ranjan 200524244cefSSai Prakash Ranjan funnel@6045000 { 200624244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 200724244cefSSai Prakash Ranjan reg = <0 0x06045000 0 0x1000>; 200824244cefSSai Prakash Ranjan 200924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 201024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 201124244cefSSai Prakash Ranjan 201224244cefSSai Prakash Ranjan out-ports { 201324244cefSSai Prakash Ranjan port { 201424244cefSSai Prakash Ranjan merge_funnel_out: endpoint { 201524244cefSSai Prakash Ranjan remote-endpoint = <&etf_in>; 201624244cefSSai Prakash Ranjan }; 201724244cefSSai Prakash Ranjan }; 201824244cefSSai Prakash Ranjan }; 201924244cefSSai Prakash Ranjan 202024244cefSSai Prakash Ranjan in-ports { 202124244cefSSai Prakash Ranjan #address-cells = <1>; 202224244cefSSai Prakash Ranjan #size-cells = <0>; 202324244cefSSai Prakash Ranjan 202424244cefSSai Prakash Ranjan port@0 { 202524244cefSSai Prakash Ranjan reg = <0>; 202624244cefSSai Prakash Ranjan merge_funnel_in0: endpoint { 202724244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_out>; 202824244cefSSai Prakash Ranjan }; 202924244cefSSai Prakash Ranjan }; 203024244cefSSai Prakash Ranjan 203124244cefSSai Prakash Ranjan port@1 { 203224244cefSSai Prakash Ranjan reg = <1>; 203324244cefSSai Prakash Ranjan merge_funnel_in1: endpoint { 203424244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_out>; 203524244cefSSai Prakash Ranjan }; 203624244cefSSai Prakash Ranjan }; 203724244cefSSai Prakash Ranjan 203824244cefSSai Prakash Ranjan port@2 { 203924244cefSSai Prakash Ranjan reg = <2>; 204024244cefSSai Prakash Ranjan merge_funnel_in2: endpoint { 204124244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_out>; 204224244cefSSai Prakash Ranjan }; 204324244cefSSai Prakash Ranjan }; 204424244cefSSai Prakash Ranjan }; 204524244cefSSai Prakash Ranjan }; 204624244cefSSai Prakash Ranjan 204724244cefSSai Prakash Ranjan replicator@6046000 { 204824244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 204924244cefSSai Prakash Ranjan reg = <0 0x06046000 0 0x1000>; 205024244cefSSai Prakash Ranjan 205124244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 205224244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 205324244cefSSai Prakash Ranjan 205424244cefSSai Prakash Ranjan out-ports { 205524244cefSSai Prakash Ranjan #address-cells = <1>; 205624244cefSSai Prakash Ranjan #size-cells = <0>; 205724244cefSSai Prakash Ranjan 205824244cefSSai Prakash Ranjan port@0 { 205924244cefSSai Prakash Ranjan reg = <0>; 206024244cefSSai Prakash Ranjan replicator_out0: endpoint { 206124244cefSSai Prakash Ranjan remote-endpoint = <&etr_in>; 206224244cefSSai Prakash Ranjan }; 206324244cefSSai Prakash Ranjan }; 206424244cefSSai Prakash Ranjan 206524244cefSSai Prakash Ranjan port@1 { 206624244cefSSai Prakash Ranjan reg = <1>; 206724244cefSSai Prakash Ranjan replicator_out1: endpoint { 206824244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_in>; 206924244cefSSai Prakash Ranjan }; 207024244cefSSai Prakash Ranjan }; 207124244cefSSai Prakash Ranjan }; 207224244cefSSai Prakash Ranjan 207324244cefSSai Prakash Ranjan in-ports { 207424244cefSSai Prakash Ranjan port { 207524244cefSSai Prakash Ranjan replicator_in0: endpoint { 207624244cefSSai Prakash Ranjan remote-endpoint = <&etf_out>; 207724244cefSSai Prakash Ranjan }; 207824244cefSSai Prakash Ranjan }; 207924244cefSSai Prakash Ranjan }; 208024244cefSSai Prakash Ranjan }; 208124244cefSSai Prakash Ranjan 208224244cefSSai Prakash Ranjan etf@6047000 { 208324244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 208424244cefSSai Prakash Ranjan reg = <0 0x06047000 0 0x1000>; 208524244cefSSai Prakash Ranjan 208624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 208724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 208824244cefSSai Prakash Ranjan 208924244cefSSai Prakash Ranjan out-ports { 209024244cefSSai Prakash Ranjan port { 209124244cefSSai Prakash Ranjan etf_out: endpoint { 209224244cefSSai Prakash Ranjan remote-endpoint = <&replicator_in0>; 209324244cefSSai Prakash Ranjan }; 209424244cefSSai Prakash Ranjan }; 209524244cefSSai Prakash Ranjan }; 209624244cefSSai Prakash Ranjan 209724244cefSSai Prakash Ranjan in-ports { 209824244cefSSai Prakash Ranjan port { 209924244cefSSai Prakash Ranjan etf_in: endpoint { 210024244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_out>; 210124244cefSSai Prakash Ranjan }; 210224244cefSSai Prakash Ranjan }; 210324244cefSSai Prakash Ranjan }; 210424244cefSSai Prakash Ranjan }; 210524244cefSSai Prakash Ranjan 210624244cefSSai Prakash Ranjan etr@6048000 { 210724244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 210824244cefSSai Prakash Ranjan reg = <0 0x06048000 0 0x1000>; 210924244cefSSai Prakash Ranjan iommus = <&apps_smmu 0x05e0 0x0>; 211024244cefSSai Prakash Ranjan 211124244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 211224244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 211324244cefSSai Prakash Ranjan arm,scatter-gather; 211424244cefSSai Prakash Ranjan 211524244cefSSai Prakash Ranjan in-ports { 211624244cefSSai Prakash Ranjan port { 211724244cefSSai Prakash Ranjan etr_in: endpoint { 211824244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out0>; 211924244cefSSai Prakash Ranjan }; 212024244cefSSai Prakash Ranjan }; 212124244cefSSai Prakash Ranjan }; 212224244cefSSai Prakash Ranjan }; 212324244cefSSai Prakash Ranjan 212424244cefSSai Prakash Ranjan replicator@604a000 { 212524244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 212624244cefSSai Prakash Ranjan reg = <0 0x0604a000 0 0x1000>; 212724244cefSSai Prakash Ranjan 212824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 212924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 213024244cefSSai Prakash Ranjan 213124244cefSSai Prakash Ranjan out-ports { 213224244cefSSai Prakash Ranjan #address-cells = <1>; 213324244cefSSai Prakash Ranjan #size-cells = <0>; 213424244cefSSai Prakash Ranjan 213524244cefSSai Prakash Ranjan port@1 { 213624244cefSSai Prakash Ranjan reg = <1>; 213724244cefSSai Prakash Ranjan replicator1_out: endpoint { 213824244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_in>; 213924244cefSSai Prakash Ranjan }; 214024244cefSSai Prakash Ranjan }; 214124244cefSSai Prakash Ranjan }; 214224244cefSSai Prakash Ranjan 214324244cefSSai Prakash Ranjan in-ports { 214424244cefSSai Prakash Ranjan #address-cells = <1>; 214524244cefSSai Prakash Ranjan #size-cells = <0>; 214624244cefSSai Prakash Ranjan 214724244cefSSai Prakash Ranjan port@1 { 214824244cefSSai Prakash Ranjan reg = <1>; 214924244cefSSai Prakash Ranjan replicator1_in: endpoint { 215024244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out1>; 215124244cefSSai Prakash Ranjan }; 215224244cefSSai Prakash Ranjan }; 215324244cefSSai Prakash Ranjan }; 215424244cefSSai Prakash Ranjan }; 215524244cefSSai Prakash Ranjan 215624244cefSSai Prakash Ranjan funnel@6b08000 { 215724244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 215824244cefSSai Prakash Ranjan reg = <0 0x06b08000 0 0x1000>; 215924244cefSSai Prakash Ranjan 216024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 216124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 216224244cefSSai Prakash Ranjan 216324244cefSSai Prakash Ranjan out-ports { 216424244cefSSai Prakash Ranjan port { 216524244cefSSai Prakash Ranjan swao_funnel_out: endpoint { 216624244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_in>; 216724244cefSSai Prakash Ranjan }; 216824244cefSSai Prakash Ranjan }; 216924244cefSSai Prakash Ranjan }; 217024244cefSSai Prakash Ranjan 217124244cefSSai Prakash Ranjan in-ports { 217224244cefSSai Prakash Ranjan #address-cells = <1>; 217324244cefSSai Prakash Ranjan #size-cells = <0>; 217424244cefSSai Prakash Ranjan 217524244cefSSai Prakash Ranjan port@6 { 217624244cefSSai Prakash Ranjan reg = <6>; 217724244cefSSai Prakash Ranjan swao_funnel_in: endpoint { 217824244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_out>; 217924244cefSSai Prakash Ranjan }; 218024244cefSSai Prakash Ranjan }; 218124244cefSSai Prakash Ranjan }; 218224244cefSSai Prakash Ranjan }; 218324244cefSSai Prakash Ranjan 218424244cefSSai Prakash Ranjan etf@6b09000 { 218524244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 218624244cefSSai Prakash Ranjan reg = <0 0x06b09000 0 0x1000>; 218724244cefSSai Prakash Ranjan 218824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 218924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 219024244cefSSai Prakash Ranjan 219124244cefSSai Prakash Ranjan out-ports { 219224244cefSSai Prakash Ranjan port { 219324244cefSSai Prakash Ranjan swao_etf_out: endpoint { 219424244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_in>; 219524244cefSSai Prakash Ranjan }; 219624244cefSSai Prakash Ranjan }; 219724244cefSSai Prakash Ranjan }; 219824244cefSSai Prakash Ranjan 219924244cefSSai Prakash Ranjan in-ports { 220024244cefSSai Prakash Ranjan port { 220124244cefSSai Prakash Ranjan swao_etf_in: endpoint { 220224244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_out>; 220324244cefSSai Prakash Ranjan }; 220424244cefSSai Prakash Ranjan }; 220524244cefSSai Prakash Ranjan }; 220624244cefSSai Prakash Ranjan }; 220724244cefSSai Prakash Ranjan 220824244cefSSai Prakash Ranjan replicator@6b0a000 { 220924244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 221024244cefSSai Prakash Ranjan reg = <0 0x06b0a000 0 0x1000>; 221124244cefSSai Prakash Ranjan 221224244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 221324244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 221424244cefSSai Prakash Ranjan qcom,replicator-loses-context; 221524244cefSSai Prakash Ranjan 221624244cefSSai Prakash Ranjan out-ports { 221724244cefSSai Prakash Ranjan port { 221824244cefSSai Prakash Ranjan swao_replicator_out: endpoint { 221924244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_in4>; 222024244cefSSai Prakash Ranjan }; 222124244cefSSai Prakash Ranjan }; 222224244cefSSai Prakash Ranjan }; 222324244cefSSai Prakash Ranjan 222424244cefSSai Prakash Ranjan in-ports { 222524244cefSSai Prakash Ranjan port { 222624244cefSSai Prakash Ranjan swao_replicator_in: endpoint { 222724244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_out>; 222824244cefSSai Prakash Ranjan }; 222924244cefSSai Prakash Ranjan }; 223024244cefSSai Prakash Ranjan }; 223124244cefSSai Prakash Ranjan }; 223224244cefSSai Prakash Ranjan 223324244cefSSai Prakash Ranjan etm@7040000 { 223424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 223524244cefSSai Prakash Ranjan reg = <0 0x07040000 0 0x1000>; 223624244cefSSai Prakash Ranjan 223724244cefSSai Prakash Ranjan cpu = <&CPU0>; 223824244cefSSai Prakash Ranjan 223924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 224024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 224124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 224224244cefSSai Prakash Ranjan qcom,skip-power-up; 224324244cefSSai Prakash Ranjan 224424244cefSSai Prakash Ranjan out-ports { 224524244cefSSai Prakash Ranjan port { 224624244cefSSai Prakash Ranjan etm0_out: endpoint { 224724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in0>; 224824244cefSSai Prakash Ranjan }; 224924244cefSSai Prakash Ranjan }; 225024244cefSSai Prakash Ranjan }; 225124244cefSSai Prakash Ranjan }; 225224244cefSSai Prakash Ranjan 225324244cefSSai Prakash Ranjan etm@7140000 { 225424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 225524244cefSSai Prakash Ranjan reg = <0 0x07140000 0 0x1000>; 225624244cefSSai Prakash Ranjan 225724244cefSSai Prakash Ranjan cpu = <&CPU1>; 225824244cefSSai Prakash Ranjan 225924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 226024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 226124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 226224244cefSSai Prakash Ranjan qcom,skip-power-up; 226324244cefSSai Prakash Ranjan 226424244cefSSai Prakash Ranjan out-ports { 226524244cefSSai Prakash Ranjan port { 226624244cefSSai Prakash Ranjan etm1_out: endpoint { 226724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in1>; 226824244cefSSai Prakash Ranjan }; 226924244cefSSai Prakash Ranjan }; 227024244cefSSai Prakash Ranjan }; 227124244cefSSai Prakash Ranjan }; 227224244cefSSai Prakash Ranjan 227324244cefSSai Prakash Ranjan etm@7240000 { 227424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 227524244cefSSai Prakash Ranjan reg = <0 0x07240000 0 0x1000>; 227624244cefSSai Prakash Ranjan 227724244cefSSai Prakash Ranjan cpu = <&CPU2>; 227824244cefSSai Prakash Ranjan 227924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 228024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 228124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 228224244cefSSai Prakash Ranjan qcom,skip-power-up; 228324244cefSSai Prakash Ranjan 228424244cefSSai Prakash Ranjan out-ports { 228524244cefSSai Prakash Ranjan port { 228624244cefSSai Prakash Ranjan etm2_out: endpoint { 228724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in2>; 228824244cefSSai Prakash Ranjan }; 228924244cefSSai Prakash Ranjan }; 229024244cefSSai Prakash Ranjan }; 229124244cefSSai Prakash Ranjan }; 229224244cefSSai Prakash Ranjan 229324244cefSSai Prakash Ranjan etm@7340000 { 229424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 229524244cefSSai Prakash Ranjan reg = <0 0x07340000 0 0x1000>; 229624244cefSSai Prakash Ranjan 229724244cefSSai Prakash Ranjan cpu = <&CPU3>; 229824244cefSSai Prakash Ranjan 229924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 230024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 230124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 230224244cefSSai Prakash Ranjan qcom,skip-power-up; 230324244cefSSai Prakash Ranjan 230424244cefSSai Prakash Ranjan out-ports { 230524244cefSSai Prakash Ranjan port { 230624244cefSSai Prakash Ranjan etm3_out: endpoint { 230724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in3>; 230824244cefSSai Prakash Ranjan }; 230924244cefSSai Prakash Ranjan }; 231024244cefSSai Prakash Ranjan }; 231124244cefSSai Prakash Ranjan }; 231224244cefSSai Prakash Ranjan 231324244cefSSai Prakash Ranjan etm@7440000 { 231424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 231524244cefSSai Prakash Ranjan reg = <0 0x07440000 0 0x1000>; 231624244cefSSai Prakash Ranjan 231724244cefSSai Prakash Ranjan cpu = <&CPU4>; 231824244cefSSai Prakash Ranjan 231924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 232024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 232124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 232224244cefSSai Prakash Ranjan qcom,skip-power-up; 232324244cefSSai Prakash Ranjan 232424244cefSSai Prakash Ranjan out-ports { 232524244cefSSai Prakash Ranjan port { 232624244cefSSai Prakash Ranjan etm4_out: endpoint { 232724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in4>; 232824244cefSSai Prakash Ranjan }; 232924244cefSSai Prakash Ranjan }; 233024244cefSSai Prakash Ranjan }; 233124244cefSSai Prakash Ranjan }; 233224244cefSSai Prakash Ranjan 233324244cefSSai Prakash Ranjan etm@7540000 { 233424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 233524244cefSSai Prakash Ranjan reg = <0 0x07540000 0 0x1000>; 233624244cefSSai Prakash Ranjan 233724244cefSSai Prakash Ranjan cpu = <&CPU5>; 233824244cefSSai Prakash Ranjan 233924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 234024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 234124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 234224244cefSSai Prakash Ranjan qcom,skip-power-up; 234324244cefSSai Prakash Ranjan 234424244cefSSai Prakash Ranjan out-ports { 234524244cefSSai Prakash Ranjan port { 234624244cefSSai Prakash Ranjan etm5_out: endpoint { 234724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in5>; 234824244cefSSai Prakash Ranjan }; 234924244cefSSai Prakash Ranjan }; 235024244cefSSai Prakash Ranjan }; 235124244cefSSai Prakash Ranjan }; 235224244cefSSai Prakash Ranjan 235324244cefSSai Prakash Ranjan etm@7640000 { 235424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 235524244cefSSai Prakash Ranjan reg = <0 0x07640000 0 0x1000>; 235624244cefSSai Prakash Ranjan 235724244cefSSai Prakash Ranjan cpu = <&CPU6>; 235824244cefSSai Prakash Ranjan 235924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 236024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 236124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 236224244cefSSai Prakash Ranjan qcom,skip-power-up; 236324244cefSSai Prakash Ranjan 236424244cefSSai Prakash Ranjan out-ports { 236524244cefSSai Prakash Ranjan port { 236624244cefSSai Prakash Ranjan etm6_out: endpoint { 236724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in6>; 236824244cefSSai Prakash Ranjan }; 236924244cefSSai Prakash Ranjan }; 237024244cefSSai Prakash Ranjan }; 237124244cefSSai Prakash Ranjan }; 237224244cefSSai Prakash Ranjan 237324244cefSSai Prakash Ranjan etm@7740000 { 237424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 237524244cefSSai Prakash Ranjan reg = <0 0x07740000 0 0x1000>; 237624244cefSSai Prakash Ranjan 237724244cefSSai Prakash Ranjan cpu = <&CPU7>; 237824244cefSSai Prakash Ranjan 237924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 238024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 238124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 238224244cefSSai Prakash Ranjan qcom,skip-power-up; 238324244cefSSai Prakash Ranjan 238424244cefSSai Prakash Ranjan out-ports { 238524244cefSSai Prakash Ranjan port { 238624244cefSSai Prakash Ranjan etm7_out: endpoint { 238724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in7>; 238824244cefSSai Prakash Ranjan }; 238924244cefSSai Prakash Ranjan }; 239024244cefSSai Prakash Ranjan }; 239124244cefSSai Prakash Ranjan }; 239224244cefSSai Prakash Ranjan 239324244cefSSai Prakash Ranjan funnel@7800000 { /* APSS Funnel */ 239424244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 239524244cefSSai Prakash Ranjan reg = <0 0x07800000 0 0x1000>; 239624244cefSSai Prakash Ranjan 239724244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 239824244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 239924244cefSSai Prakash Ranjan 240024244cefSSai Prakash Ranjan out-ports { 240124244cefSSai Prakash Ranjan port { 240224244cefSSai Prakash Ranjan apss_funnel_out: endpoint { 240324244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_in>; 240424244cefSSai Prakash Ranjan }; 240524244cefSSai Prakash Ranjan }; 240624244cefSSai Prakash Ranjan }; 240724244cefSSai Prakash Ranjan 240824244cefSSai Prakash Ranjan in-ports { 240924244cefSSai Prakash Ranjan #address-cells = <1>; 241024244cefSSai Prakash Ranjan #size-cells = <0>; 241124244cefSSai Prakash Ranjan 241224244cefSSai Prakash Ranjan port@0 { 241324244cefSSai Prakash Ranjan reg = <0>; 241424244cefSSai Prakash Ranjan apss_funnel_in0: endpoint { 241524244cefSSai Prakash Ranjan remote-endpoint = <&etm0_out>; 241624244cefSSai Prakash Ranjan }; 241724244cefSSai Prakash Ranjan }; 241824244cefSSai Prakash Ranjan 241924244cefSSai Prakash Ranjan port@1 { 242024244cefSSai Prakash Ranjan reg = <1>; 242124244cefSSai Prakash Ranjan apss_funnel_in1: endpoint { 242224244cefSSai Prakash Ranjan remote-endpoint = <&etm1_out>; 242324244cefSSai Prakash Ranjan }; 242424244cefSSai Prakash Ranjan }; 242524244cefSSai Prakash Ranjan 242624244cefSSai Prakash Ranjan port@2 { 242724244cefSSai Prakash Ranjan reg = <2>; 242824244cefSSai Prakash Ranjan apss_funnel_in2: endpoint { 242924244cefSSai Prakash Ranjan remote-endpoint = <&etm2_out>; 243024244cefSSai Prakash Ranjan }; 243124244cefSSai Prakash Ranjan }; 243224244cefSSai Prakash Ranjan 243324244cefSSai Prakash Ranjan port@3 { 243424244cefSSai Prakash Ranjan reg = <3>; 243524244cefSSai Prakash Ranjan apss_funnel_in3: endpoint { 243624244cefSSai Prakash Ranjan remote-endpoint = <&etm3_out>; 243724244cefSSai Prakash Ranjan }; 243824244cefSSai Prakash Ranjan }; 243924244cefSSai Prakash Ranjan 244024244cefSSai Prakash Ranjan port@4 { 244124244cefSSai Prakash Ranjan reg = <4>; 244224244cefSSai Prakash Ranjan apss_funnel_in4: endpoint { 244324244cefSSai Prakash Ranjan remote-endpoint = <&etm4_out>; 244424244cefSSai Prakash Ranjan }; 244524244cefSSai Prakash Ranjan }; 244624244cefSSai Prakash Ranjan 244724244cefSSai Prakash Ranjan port@5 { 244824244cefSSai Prakash Ranjan reg = <5>; 244924244cefSSai Prakash Ranjan apss_funnel_in5: endpoint { 245024244cefSSai Prakash Ranjan remote-endpoint = <&etm5_out>; 245124244cefSSai Prakash Ranjan }; 245224244cefSSai Prakash Ranjan }; 245324244cefSSai Prakash Ranjan 245424244cefSSai Prakash Ranjan port@6 { 245524244cefSSai Prakash Ranjan reg = <6>; 245624244cefSSai Prakash Ranjan apss_funnel_in6: endpoint { 245724244cefSSai Prakash Ranjan remote-endpoint = <&etm6_out>; 245824244cefSSai Prakash Ranjan }; 245924244cefSSai Prakash Ranjan }; 246024244cefSSai Prakash Ranjan 246124244cefSSai Prakash Ranjan port@7 { 246224244cefSSai Prakash Ranjan reg = <7>; 246324244cefSSai Prakash Ranjan apss_funnel_in7: endpoint { 246424244cefSSai Prakash Ranjan remote-endpoint = <&etm7_out>; 246524244cefSSai Prakash Ranjan }; 246624244cefSSai Prakash Ranjan }; 246724244cefSSai Prakash Ranjan }; 246824244cefSSai Prakash Ranjan }; 246924244cefSSai Prakash Ranjan 247024244cefSSai Prakash Ranjan funnel@7810000 { 247124244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 247224244cefSSai Prakash Ranjan reg = <0 0x07810000 0 0x1000>; 247324244cefSSai Prakash Ranjan 247424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 247524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 247624244cefSSai Prakash Ranjan 247724244cefSSai Prakash Ranjan out-ports { 247824244cefSSai Prakash Ranjan port { 247924244cefSSai Prakash Ranjan apss_merge_funnel_out: endpoint { 248024244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_in2>; 248124244cefSSai Prakash Ranjan }; 248224244cefSSai Prakash Ranjan }; 248324244cefSSai Prakash Ranjan }; 248424244cefSSai Prakash Ranjan 248524244cefSSai Prakash Ranjan in-ports { 248624244cefSSai Prakash Ranjan port { 248724244cefSSai Prakash Ranjan apss_merge_funnel_in: endpoint { 248824244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_out>; 248924244cefSSai Prakash Ranjan }; 249024244cefSSai Prakash Ranjan }; 249124244cefSSai Prakash Ranjan }; 249224244cefSSai Prakash Ranjan }; 249324244cefSSai Prakash Ranjan 249449076351SSibi Sankar remoteproc_cdsp: remoteproc@8300000 { 249549076351SSibi Sankar compatible = "qcom,sm8150-cdsp-pas"; 249649076351SSibi Sankar reg = <0x0 0x08300000 0x0 0x4040>; 249749076351SSibi Sankar 249849076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 249949076351SSibi Sankar <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 250049076351SSibi Sankar <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 250149076351SSibi Sankar <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 250249076351SSibi Sankar <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 250349076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 250449076351SSibi Sankar "handover", "stop-ack"; 250549076351SSibi Sankar 250649076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 250749076351SSibi Sankar clock-names = "xo"; 250849076351SSibi Sankar 250949076351SSibi Sankar power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, 2510d0770627SBjorn Andersson <&rpmhpd 7>; 251149076351SSibi Sankar power-domain-names = "load_state", "cx"; 251249076351SSibi Sankar 251349076351SSibi Sankar memory-region = <&cdsp_mem>; 251449076351SSibi Sankar 251549076351SSibi Sankar qcom,smem-states = <&cdsp_smp2p_out 0>; 251649076351SSibi Sankar qcom,smem-state-names = "stop"; 251749076351SSibi Sankar 251849076351SSibi Sankar status = "disabled"; 251949076351SSibi Sankar 252049076351SSibi Sankar glink-edge { 252149076351SSibi Sankar interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 252249076351SSibi Sankar label = "cdsp"; 252349076351SSibi Sankar qcom,remote-pid = <5>; 252449076351SSibi Sankar mboxes = <&apss_shared 4>; 252549076351SSibi Sankar }; 252649076351SSibi Sankar }; 252749076351SSibi Sankar 2528b33d2868SJack Pham usb_1_hsphy: phy@88e2000 { 2529b33d2868SJack Pham compatible = "qcom,sm8150-usb-hs-phy", 2530b33d2868SJack Pham "qcom,usb-snps-hs-7nm-phy"; 2531b33d2868SJack Pham reg = <0 0x088e2000 0 0x400>; 2532b33d2868SJack Pham status = "disabled"; 2533b33d2868SJack Pham #phy-cells = <0>; 2534b33d2868SJack Pham 2535b33d2868SJack Pham clocks = <&rpmhcc RPMH_CXO_CLK>; 2536b33d2868SJack Pham clock-names = "ref"; 2537b33d2868SJack Pham 2538b33d2868SJack Pham resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2539b33d2868SJack Pham }; 2540b33d2868SJack Pham 25410c9dde0dSJonathan Marek usb_2_hsphy: phy@88e3000 { 25420c9dde0dSJonathan Marek compatible = "qcom,sm8150-usb-hs-phy", 25430c9dde0dSJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 25440c9dde0dSJonathan Marek reg = <0 0x088e3000 0 0x400>; 25450c9dde0dSJonathan Marek status = "disabled"; 25460c9dde0dSJonathan Marek #phy-cells = <0>; 25470c9dde0dSJonathan Marek 25480c9dde0dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 25490c9dde0dSJonathan Marek clock-names = "ref"; 25500c9dde0dSJonathan Marek 25510c9dde0dSJonathan Marek resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 25520c9dde0dSJonathan Marek }; 25530c9dde0dSJonathan Marek 2554b33d2868SJack Pham usb_1_qmpphy: phy@88e9000 { 2555b33d2868SJack Pham compatible = "qcom,sm8150-qmp-usb3-phy"; 2556b33d2868SJack Pham reg = <0 0x088e9000 0 0x18c>, 2557b33d2868SJack Pham <0 0x088e8000 0 0x10>; 2558b33d2868SJack Pham reg-names = "reg-base", "dp_com"; 2559b33d2868SJack Pham status = "disabled"; 2560b33d2868SJack Pham #address-cells = <2>; 2561b33d2868SJack Pham #size-cells = <2>; 2562b33d2868SJack Pham ranges; 2563b33d2868SJack Pham 2564b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2565b33d2868SJack Pham <&rpmhcc RPMH_CXO_CLK>, 2566b33d2868SJack Pham <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2567b33d2868SJack Pham <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2568b33d2868SJack Pham clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2569b33d2868SJack Pham 2570b33d2868SJack Pham resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2571b33d2868SJack Pham <&gcc GCC_USB3_PHY_PRIM_BCR>; 2572b33d2868SJack Pham reset-names = "phy", "common"; 2573b33d2868SJack Pham 2574b33d2868SJack Pham usb_1_ssphy: lanes@88e9200 { 2575b33d2868SJack Pham reg = <0 0x088e9200 0 0x200>, 2576b33d2868SJack Pham <0 0x088e9400 0 0x200>, 2577b33d2868SJack Pham <0 0x088e9c00 0 0x218>, 2578b33d2868SJack Pham <0 0x088e9600 0 0x200>, 2579b33d2868SJack Pham <0 0x088e9800 0 0x200>, 2580b33d2868SJack Pham <0 0x088e9a00 0 0x100>; 25817178d4ccSJonathan Marek #clock-cells = <0>; 2582b33d2868SJack Pham #phy-cells = <0>; 2583b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2584b33d2868SJack Pham clock-names = "pipe0"; 2585b33d2868SJack Pham clock-output-names = "usb3_phy_pipe_clk_src"; 2586b33d2868SJack Pham }; 2587b33d2868SJack Pham }; 2588b33d2868SJack Pham 25890c9dde0dSJonathan Marek usb_2_qmpphy: phy@88eb000 { 25900c9dde0dSJonathan Marek compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 25910c9dde0dSJonathan Marek reg = <0 0x088eb000 0 0x200>; 25920c9dde0dSJonathan Marek status = "disabled"; 25930c9dde0dSJonathan Marek #address-cells = <2>; 25940c9dde0dSJonathan Marek #size-cells = <2>; 25950c9dde0dSJonathan Marek ranges; 25960c9dde0dSJonathan Marek 25970c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 25980c9dde0dSJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 25990c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>, 26000c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 26010c9dde0dSJonathan Marek clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 26020c9dde0dSJonathan Marek 26030c9dde0dSJonathan Marek resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 26040c9dde0dSJonathan Marek <&gcc GCC_USB3_PHY_SEC_BCR>; 26050c9dde0dSJonathan Marek reset-names = "phy", "common"; 26060c9dde0dSJonathan Marek 26070c9dde0dSJonathan Marek usb_2_ssphy: lane@88eb200 { 26080c9dde0dSJonathan Marek reg = <0 0x088eb200 0 0x200>, 26090c9dde0dSJonathan Marek <0 0x088eb400 0 0x200>, 26100c9dde0dSJonathan Marek <0 0x088eb800 0 0x800>, 26110c9dde0dSJonathan Marek <0 0x088eb600 0 0x200>; 26127178d4ccSJonathan Marek #clock-cells = <0>; 26130c9dde0dSJonathan Marek #phy-cells = <0>; 26140c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 26150c9dde0dSJonathan Marek clock-names = "pipe0"; 26160c9dde0dSJonathan Marek clock-output-names = "usb3_uni_phy_pipe_clk_src"; 26170c9dde0dSJonathan Marek }; 26180c9dde0dSJonathan Marek }; 26190c9dde0dSJonathan Marek 26205dc43d3bSBhupesh Sharma dc_noc: interconnect@9160000 { 26215dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-dc-noc"; 26225dc43d3bSBhupesh Sharma reg = <0 0x09160000 0 0x3200>; 26235dc43d3bSBhupesh Sharma #interconnect-cells = <1>; 26245dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 26255dc43d3bSBhupesh Sharma }; 26265dc43d3bSBhupesh Sharma 26275dc43d3bSBhupesh Sharma gem_noc: interconnect@9680000 { 26285dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-gem-noc"; 26295dc43d3bSBhupesh Sharma reg = <0 0x09680000 0 0x3e200>; 26305dc43d3bSBhupesh Sharma #interconnect-cells = <1>; 26315dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 26325dc43d3bSBhupesh Sharma }; 26335dc43d3bSBhupesh Sharma 2634b33d2868SJack Pham usb_1: usb@a6f8800 { 2635b33d2868SJack Pham compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 2636b33d2868SJack Pham reg = <0 0x0a6f8800 0 0x400>; 2637b33d2868SJack Pham status = "disabled"; 2638b33d2868SJack Pham #address-cells = <2>; 2639b33d2868SJack Pham #size-cells = <2>; 2640b33d2868SJack Pham ranges; 2641b33d2868SJack Pham dma-ranges; 2642b33d2868SJack Pham 2643b33d2868SJack Pham clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2644b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2645b33d2868SJack Pham <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2646b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2647b33d2868SJack Pham <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2648b33d2868SJack Pham <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2649b33d2868SJack Pham clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2650b33d2868SJack Pham "sleep", "xo"; 2651b33d2868SJack Pham 2652b33d2868SJack Pham assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2653b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>; 265479493db5SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 2655b33d2868SJack Pham 2656b33d2868SJack Pham interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2657b33d2868SJack Pham <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 2658b33d2868SJack Pham <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 2659b33d2868SJack Pham <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 2660b33d2868SJack Pham interrupt-names = "hs_phy_irq", "ss_phy_irq", 2661b33d2868SJack Pham "dm_hs_phy_irq", "dp_hs_phy_irq"; 2662b33d2868SJack Pham 2663b33d2868SJack Pham power-domains = <&gcc USB30_PRIM_GDSC>; 2664b33d2868SJack Pham 2665b33d2868SJack Pham resets = <&gcc GCC_USB30_PRIM_BCR>; 2666b33d2868SJack Pham 2667eb9b7bfdSSerge Semin usb_1_dwc3: usb@a600000 { 2668b33d2868SJack Pham compatible = "snps,dwc3"; 2669b33d2868SJack Pham reg = <0 0x0a600000 0 0xcd00>; 2670b33d2868SJack Pham interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 267148156232SJonathan Marek iommus = <&apps_smmu 0x140 0>; 2672b33d2868SJack Pham snps,dis_u2_susphy_quirk; 2673b33d2868SJack Pham snps,dis_enblslpm_quirk; 2674b33d2868SJack Pham phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2675b33d2868SJack Pham phy-names = "usb2-phy", "usb3-phy"; 2676b33d2868SJack Pham }; 2677b33d2868SJack Pham }; 2678b33d2868SJack Pham 26790c9dde0dSJonathan Marek usb_2: usb@a8f8800 { 26800c9dde0dSJonathan Marek compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 26810c9dde0dSJonathan Marek reg = <0 0x0a8f8800 0 0x400>; 26820c9dde0dSJonathan Marek status = "disabled"; 26830c9dde0dSJonathan Marek #address-cells = <2>; 26840c9dde0dSJonathan Marek #size-cells = <2>; 26850c9dde0dSJonathan Marek ranges; 26860c9dde0dSJonathan Marek dma-ranges; 26870c9dde0dSJonathan Marek 26880c9dde0dSJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 26890c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>, 26900c9dde0dSJonathan Marek <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 26910c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 26920c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_SLEEP_CLK>, 26930c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>; 26940c9dde0dSJonathan Marek clock-names = "cfg_noc", "core", "iface", "mock_utmi", 26950c9dde0dSJonathan Marek "sleep", "xo"; 26960c9dde0dSJonathan Marek 26970c9dde0dSJonathan Marek assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 26980c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>; 26990c9dde0dSJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 27000c9dde0dSJonathan Marek 27010c9dde0dSJonathan Marek interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 27020c9dde0dSJonathan Marek <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 27030c9dde0dSJonathan Marek <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 27040c9dde0dSJonathan Marek <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 27050c9dde0dSJonathan Marek interrupt-names = "hs_phy_irq", "ss_phy_irq", 27060c9dde0dSJonathan Marek "dm_hs_phy_irq", "dp_hs_phy_irq"; 27070c9dde0dSJonathan Marek 27080c9dde0dSJonathan Marek power-domains = <&gcc USB30_SEC_GDSC>; 27090c9dde0dSJonathan Marek 27100c9dde0dSJonathan Marek resets = <&gcc GCC_USB30_SEC_BCR>; 27110c9dde0dSJonathan Marek 27122aa2b50dSBhupesh Sharma usb_2_dwc3: usb@a800000 { 27130c9dde0dSJonathan Marek compatible = "snps,dwc3"; 27140c9dde0dSJonathan Marek reg = <0 0x0a800000 0 0xcd00>; 27150c9dde0dSJonathan Marek interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 27160c9dde0dSJonathan Marek iommus = <&apps_smmu 0x160 0>; 27170c9dde0dSJonathan Marek snps,dis_u2_susphy_quirk; 27180c9dde0dSJonathan Marek snps,dis_enblslpm_quirk; 27190c9dde0dSJonathan Marek phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 27200c9dde0dSJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 27210c9dde0dSJonathan Marek }; 27220c9dde0dSJonathan Marek }; 27230c9dde0dSJonathan Marek 27246acb71fdSJonathan Marek camnoc_virt: interconnect@ac00000 { 27256acb71fdSJonathan Marek compatible = "qcom,sm8150-camnoc-virt"; 27266acb71fdSJonathan Marek reg = <0 0x0ac00000 0 0x1000>; 27276acb71fdSJonathan Marek #interconnect-cells = <1>; 27286acb71fdSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 27296acb71fdSJonathan Marek }; 27306acb71fdSJonathan Marek 2731d8cf9372SVinod Koul aoss_qmp: power-controller@c300000 { 2732d8cf9372SVinod Koul compatible = "qcom,sm8150-aoss-qmp"; 2733d8cf9372SVinod Koul reg = <0x0 0x0c300000 0x0 0x100000>; 2734d8cf9372SVinod Koul interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 2735d8cf9372SVinod Koul mboxes = <&apss_shared 0>; 2736d8cf9372SVinod Koul 2737d8cf9372SVinod Koul #clock-cells = <0>; 2738d8cf9372SVinod Koul #power-domain-cells = <1>; 2739d8cf9372SVinod Koul }; 2740d8cf9372SVinod Koul 2741d2fa630cSAmit Kucheria tsens0: thermal-sensor@c263000 { 2742d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 2743d2fa630cSAmit Kucheria reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2744d2fa630cSAmit Kucheria <0 0x0c222000 0 0x1ff>; /* SROT */ 2745d2fa630cSAmit Kucheria #qcom,sensors = <16>; 2746d2fa630cSAmit Kucheria interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2747d2fa630cSAmit Kucheria <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2748d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 2749d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 2750d2fa630cSAmit Kucheria }; 2751d2fa630cSAmit Kucheria 2752d2fa630cSAmit Kucheria tsens1: thermal-sensor@c265000 { 2753d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 2754d2fa630cSAmit Kucheria reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2755d2fa630cSAmit Kucheria <0 0x0c223000 0 0x1ff>; /* SROT */ 2756d2fa630cSAmit Kucheria #qcom,sensors = <8>; 2757d2fa630cSAmit Kucheria interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2758d2fa630cSAmit Kucheria <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2759d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 2760d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 2761d2fa630cSAmit Kucheria }; 2762d2fa630cSAmit Kucheria 2763e13c6d14SVinod Koul spmi_bus: spmi@c440000 { 2764e13c6d14SVinod Koul compatible = "qcom,spmi-pmic-arb"; 2765e13c6d14SVinod Koul reg = <0x0 0x0c440000 0x0 0x0001100>, 2766e13c6d14SVinod Koul <0x0 0x0c600000 0x0 0x2000000>, 2767e13c6d14SVinod Koul <0x0 0x0e600000 0x0 0x0100000>, 2768e13c6d14SVinod Koul <0x0 0x0e700000 0x0 0x00a0000>, 2769e13c6d14SVinod Koul <0x0 0x0c40a000 0x0 0x0026000>; 2770e13c6d14SVinod Koul reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2771e13c6d14SVinod Koul interrupt-names = "periph_irq"; 2772e13c6d14SVinod Koul interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 2773e13c6d14SVinod Koul qcom,ee = <0>; 2774e13c6d14SVinod Koul qcom,channel = <0>; 2775e13c6d14SVinod Koul #address-cells = <2>; 2776e13c6d14SVinod Koul #size-cells = <0>; 2777e13c6d14SVinod Koul interrupt-controller; 2778e13c6d14SVinod Koul #interrupt-cells = <4>; 2779e13c6d14SVinod Koul cell-index = <0>; 2780e13c6d14SVinod Koul }; 2781e13c6d14SVinod Koul 278248156232SJonathan Marek apps_smmu: iommu@15000000 { 278348156232SJonathan Marek compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 278448156232SJonathan Marek reg = <0 0x15000000 0 0x100000>; 278548156232SJonathan Marek #iommu-cells = <2>; 278648156232SJonathan Marek #global-interrupts = <1>; 278748156232SJonathan Marek interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 278848156232SJonathan Marek <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 278948156232SJonathan Marek <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 279048156232SJonathan Marek <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 279148156232SJonathan Marek <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 279248156232SJonathan Marek <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 279348156232SJonathan Marek <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 279448156232SJonathan Marek <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 279548156232SJonathan Marek <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 279648156232SJonathan Marek <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 279748156232SJonathan Marek <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 279848156232SJonathan Marek <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 279948156232SJonathan Marek <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 280048156232SJonathan Marek <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 280148156232SJonathan Marek <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 280248156232SJonathan Marek <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 280348156232SJonathan Marek <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 280448156232SJonathan Marek <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 280548156232SJonathan Marek <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 280648156232SJonathan Marek <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 280748156232SJonathan Marek <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 280848156232SJonathan Marek <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 280948156232SJonathan Marek <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 281048156232SJonathan Marek <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 281148156232SJonathan Marek <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 281248156232SJonathan Marek <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 281348156232SJonathan Marek <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 281448156232SJonathan Marek <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 281548156232SJonathan Marek <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 281648156232SJonathan Marek <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 281748156232SJonathan Marek <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 281848156232SJonathan Marek <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 281948156232SJonathan Marek <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 282048156232SJonathan Marek <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 282148156232SJonathan Marek <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 282248156232SJonathan Marek <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 282348156232SJonathan Marek <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 282448156232SJonathan Marek <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 282548156232SJonathan Marek <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 282648156232SJonathan Marek <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 282748156232SJonathan Marek <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 282848156232SJonathan Marek <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 282948156232SJonathan Marek <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 283048156232SJonathan Marek <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 283148156232SJonathan Marek <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 283248156232SJonathan Marek <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 283348156232SJonathan Marek <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 283448156232SJonathan Marek <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 283548156232SJonathan Marek <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 283648156232SJonathan Marek <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 283748156232SJonathan Marek <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 283848156232SJonathan Marek <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 283948156232SJonathan Marek <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 284048156232SJonathan Marek <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 284148156232SJonathan Marek <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 284248156232SJonathan Marek <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 284348156232SJonathan Marek <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 284448156232SJonathan Marek <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 284548156232SJonathan Marek <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 284648156232SJonathan Marek <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 284748156232SJonathan Marek <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 284848156232SJonathan Marek <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 284948156232SJonathan Marek <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 285048156232SJonathan Marek <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 285148156232SJonathan Marek <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 285248156232SJonathan Marek <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 285348156232SJonathan Marek <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 285448156232SJonathan Marek <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 285548156232SJonathan Marek <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 285648156232SJonathan Marek <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 285748156232SJonathan Marek <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 285848156232SJonathan Marek <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 285948156232SJonathan Marek <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 286048156232SJonathan Marek <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 286148156232SJonathan Marek <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 286248156232SJonathan Marek <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 286348156232SJonathan Marek <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 286448156232SJonathan Marek <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 286548156232SJonathan Marek <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 286648156232SJonathan Marek <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 286748156232SJonathan Marek <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 286848156232SJonathan Marek }; 286948156232SJonathan Marek 287049076351SSibi Sankar remoteproc_adsp: remoteproc@17300000 { 287149076351SSibi Sankar compatible = "qcom,sm8150-adsp-pas"; 287249076351SSibi Sankar reg = <0x0 0x17300000 0x0 0x4040>; 287349076351SSibi Sankar 287449076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 287549076351SSibi Sankar <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 287649076351SSibi Sankar <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 287749076351SSibi Sankar <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 287849076351SSibi Sankar <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 287949076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 288049076351SSibi Sankar "handover", "stop-ack"; 288149076351SSibi Sankar 288249076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 288349076351SSibi Sankar clock-names = "xo"; 288449076351SSibi Sankar 288549076351SSibi Sankar power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, 2886d0770627SBjorn Andersson <&rpmhpd 7>; 288749076351SSibi Sankar power-domain-names = "load_state", "cx"; 288849076351SSibi Sankar 288949076351SSibi Sankar memory-region = <&adsp_mem>; 289049076351SSibi Sankar 289149076351SSibi Sankar qcom,smem-states = <&adsp_smp2p_out 0>; 289249076351SSibi Sankar qcom,smem-state-names = "stop"; 289349076351SSibi Sankar 289449076351SSibi Sankar status = "disabled"; 289549076351SSibi Sankar 289649076351SSibi Sankar glink-edge { 289749076351SSibi Sankar interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 289849076351SSibi Sankar label = "lpass"; 289949076351SSibi Sankar qcom,remote-pid = <2>; 290049076351SSibi Sankar mboxes = <&apss_shared 8>; 290149076351SSibi Sankar }; 290249076351SSibi Sankar }; 290349076351SSibi Sankar 2904e13c6d14SVinod Koul intc: interrupt-controller@17a00000 { 2905e13c6d14SVinod Koul compatible = "arm,gic-v3"; 2906e13c6d14SVinod Koul interrupt-controller; 2907e13c6d14SVinod Koul #interrupt-cells = <3>; 2908e13c6d14SVinod Koul reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 2909e13c6d14SVinod Koul <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 2910e13c6d14SVinod Koul interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2911e13c6d14SVinod Koul }; 2912e13c6d14SVinod Koul 2913d8cf9372SVinod Koul apss_shared: mailbox@17c00000 { 2914d8cf9372SVinod Koul compatible = "qcom,sm8150-apss-shared"; 2915d8cf9372SVinod Koul reg = <0x0 0x17c00000 0x0 0x1000>; 2916d8cf9372SVinod Koul #mbox-cells = <1>; 2917d8cf9372SVinod Koul }; 2918d8cf9372SVinod Koul 2919fb2d8150SSai Prakash Ranjan watchdog@17c10000 { 2920fb2d8150SSai Prakash Ranjan compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 2921fb2d8150SSai Prakash Ranjan reg = <0 0x17c10000 0 0x1000>; 2922fb2d8150SSai Prakash Ranjan clocks = <&sleep_clk>; 2923b094c8f8SSai Prakash Ranjan interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 2924fb2d8150SSai Prakash Ranjan }; 2925fb2d8150SSai Prakash Ranjan 2926e13c6d14SVinod Koul timer@17c20000 { 2927e13c6d14SVinod Koul #address-cells = <2>; 2928e13c6d14SVinod Koul #size-cells = <2>; 2929e13c6d14SVinod Koul ranges; 2930e13c6d14SVinod Koul compatible = "arm,armv7-timer-mem"; 2931e13c6d14SVinod Koul reg = <0x0 0x17c20000 0x0 0x1000>; 2932e13c6d14SVinod Koul clock-frequency = <19200000>; 2933e13c6d14SVinod Koul 2934e13c6d14SVinod Koul frame@17c21000{ 2935e13c6d14SVinod Koul frame-number = <0>; 2936e13c6d14SVinod Koul interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2937e13c6d14SVinod Koul <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2938e13c6d14SVinod Koul reg = <0x0 0x17c21000 0x0 0x1000>, 2939e13c6d14SVinod Koul <0x0 0x17c22000 0x0 0x1000>; 2940e13c6d14SVinod Koul }; 2941e13c6d14SVinod Koul 2942e13c6d14SVinod Koul frame@17c23000 { 2943e13c6d14SVinod Koul frame-number = <1>; 2944e13c6d14SVinod Koul interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2945e13c6d14SVinod Koul reg = <0x0 0x17c23000 0x0 0x1000>; 2946e13c6d14SVinod Koul status = "disabled"; 2947e13c6d14SVinod Koul }; 2948e13c6d14SVinod Koul 2949e13c6d14SVinod Koul frame@17c25000 { 2950e13c6d14SVinod Koul frame-number = <2>; 2951e13c6d14SVinod Koul interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2952e13c6d14SVinod Koul reg = <0x0 0x17c25000 0x0 0x1000>; 2953e13c6d14SVinod Koul status = "disabled"; 2954e13c6d14SVinod Koul }; 2955e13c6d14SVinod Koul 2956e13c6d14SVinod Koul frame@17c27000 { 2957e13c6d14SVinod Koul frame-number = <3>; 2958e13c6d14SVinod Koul interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2959e13c6d14SVinod Koul reg = <0x0 0x17c26000 0x0 0x1000>; 2960e13c6d14SVinod Koul status = "disabled"; 2961e13c6d14SVinod Koul }; 2962e13c6d14SVinod Koul 2963e13c6d14SVinod Koul frame@17c29000 { 2964e13c6d14SVinod Koul frame-number = <4>; 2965e13c6d14SVinod Koul interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2966e13c6d14SVinod Koul reg = <0x0 0x17c29000 0x0 0x1000>; 2967e13c6d14SVinod Koul status = "disabled"; 2968e13c6d14SVinod Koul }; 2969e13c6d14SVinod Koul 2970e13c6d14SVinod Koul frame@17c2b000 { 2971e13c6d14SVinod Koul frame-number = <5>; 2972e13c6d14SVinod Koul interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2973e13c6d14SVinod Koul reg = <0x0 0x17c2b000 0x0 0x1000>; 2974e13c6d14SVinod Koul status = "disabled"; 2975e13c6d14SVinod Koul }; 2976e13c6d14SVinod Koul 2977e13c6d14SVinod Koul frame@17c2d000 { 2978e13c6d14SVinod Koul frame-number = <6>; 2979e13c6d14SVinod Koul interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2980e13c6d14SVinod Koul reg = <0x0 0x17c2d000 0x0 0x1000>; 2981e13c6d14SVinod Koul status = "disabled"; 2982e13c6d14SVinod Koul }; 2983e13c6d14SVinod Koul }; 2984d8cf9372SVinod Koul 2985d8cf9372SVinod Koul apps_rsc: rsc@18200000 { 2986d8cf9372SVinod Koul label = "apps_rsc"; 2987d8cf9372SVinod Koul compatible = "qcom,rpmh-rsc"; 2988d8cf9372SVinod Koul reg = <0x0 0x18200000 0x0 0x10000>, 2989d8cf9372SVinod Koul <0x0 0x18210000 0x0 0x10000>, 2990d8cf9372SVinod Koul <0x0 0x18220000 0x0 0x10000>; 2991d8cf9372SVinod Koul reg-names = "drv-0", "drv-1", "drv-2"; 2992d8cf9372SVinod Koul interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2993d8cf9372SVinod Koul <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2994d8cf9372SVinod Koul <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2995d8cf9372SVinod Koul qcom,tcs-offset = <0xd00>; 2996d8cf9372SVinod Koul qcom,drv-id = <2>; 2997d8cf9372SVinod Koul qcom,tcs-config = <ACTIVE_TCS 2>, 2998d8cf9372SVinod Koul <SLEEP_TCS 1>, 2999d8cf9372SVinod Koul <WAKE_TCS 1>, 3000d8cf9372SVinod Koul <CONTROL_TCS 0>; 3001d8cf9372SVinod Koul 3002d8cf9372SVinod Koul rpmhcc: clock-controller { 3003d8cf9372SVinod Koul compatible = "qcom,sm8150-rpmh-clk"; 3004d8cf9372SVinod Koul #clock-cells = <1>; 3005d8cf9372SVinod Koul clock-names = "xo"; 3006d8cf9372SVinod Koul clocks = <&xo_board>; 3007d8cf9372SVinod Koul }; 3008017e7856SSibi Sankar 3009017e7856SSibi Sankar rpmhpd: power-controller { 3010017e7856SSibi Sankar compatible = "qcom,sm8150-rpmhpd"; 3011017e7856SSibi Sankar #power-domain-cells = <1>; 3012017e7856SSibi Sankar operating-points-v2 = <&rpmhpd_opp_table>; 3013017e7856SSibi Sankar 3014017e7856SSibi Sankar rpmhpd_opp_table: opp-table { 3015017e7856SSibi Sankar compatible = "operating-points-v2"; 3016017e7856SSibi Sankar 3017017e7856SSibi Sankar rpmhpd_opp_ret: opp1 { 3018017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3019017e7856SSibi Sankar }; 3020017e7856SSibi Sankar 3021017e7856SSibi Sankar rpmhpd_opp_min_svs: opp2 { 3022017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3023017e7856SSibi Sankar }; 3024017e7856SSibi Sankar 3025017e7856SSibi Sankar rpmhpd_opp_low_svs: opp3 { 3026017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3027017e7856SSibi Sankar }; 3028017e7856SSibi Sankar 3029017e7856SSibi Sankar rpmhpd_opp_svs: opp4 { 3030017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3031017e7856SSibi Sankar }; 3032017e7856SSibi Sankar 3033017e7856SSibi Sankar rpmhpd_opp_svs_l1: opp5 { 3034017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3035017e7856SSibi Sankar }; 3036017e7856SSibi Sankar 3037017e7856SSibi Sankar rpmhpd_opp_svs_l2: opp6 { 3038017e7856SSibi Sankar opp-level = <224>; 3039017e7856SSibi Sankar }; 3040017e7856SSibi Sankar 3041017e7856SSibi Sankar rpmhpd_opp_nom: opp7 { 3042017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3043017e7856SSibi Sankar }; 3044017e7856SSibi Sankar 3045017e7856SSibi Sankar rpmhpd_opp_nom_l1: opp8 { 3046017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3047017e7856SSibi Sankar }; 3048017e7856SSibi Sankar 3049017e7856SSibi Sankar rpmhpd_opp_nom_l2: opp9 { 3050017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3051017e7856SSibi Sankar }; 3052017e7856SSibi Sankar 3053017e7856SSibi Sankar rpmhpd_opp_turbo: opp10 { 3054017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3055017e7856SSibi Sankar }; 3056017e7856SSibi Sankar 3057017e7856SSibi Sankar rpmhpd_opp_turbo_l1: opp11 { 3058017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3059017e7856SSibi Sankar }; 3060017e7856SSibi Sankar }; 3061017e7856SSibi Sankar }; 306271a2fc6eSJonathan Marek 306371a2fc6eSJonathan Marek apps_bcm_voter: bcm_voter { 306471a2fc6eSJonathan Marek compatible = "qcom,bcm-voter"; 306571a2fc6eSJonathan Marek }; 3066d8cf9372SVinod Koul }; 3067fea8930bSSibi Sankar 3068a6d435c1SSibi Sankar osm_l3: interconnect@18321000 { 3069a6d435c1SSibi Sankar compatible = "qcom,sm8150-osm-l3"; 3070a6d435c1SSibi Sankar reg = <0 0x18321000 0 0x1400>; 3071a6d435c1SSibi Sankar 3072a6d435c1SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3073a6d435c1SSibi Sankar clock-names = "xo", "alternate"; 3074a6d435c1SSibi Sankar 3075a6d435c1SSibi Sankar #interconnect-cells = <1>; 3076a6d435c1SSibi Sankar }; 3077a6d435c1SSibi Sankar 3078fea8930bSSibi Sankar cpufreq_hw: cpufreq@18323000 { 3079fea8930bSSibi Sankar compatible = "qcom,cpufreq-hw"; 3080fea8930bSSibi Sankar reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 3081fea8930bSSibi Sankar <0 0x18327800 0 0x1400>; 3082fea8930bSSibi Sankar reg-names = "freq-domain0", "freq-domain1", 3083fea8930bSSibi Sankar "freq-domain2"; 3084fea8930bSSibi Sankar 3085fea8930bSSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3086fea8930bSSibi Sankar clock-names = "xo", "alternate"; 3087fea8930bSSibi Sankar 3088fea8930bSSibi Sankar #freq-domain-cells = <1>; 3089fea8930bSSibi Sankar }; 309005090bb9SJonathan Marek 309105090bb9SJonathan Marek wifi: wifi@18800000 { 309205090bb9SJonathan Marek compatible = "qcom,wcn3990-wifi"; 309305090bb9SJonathan Marek reg = <0 0x18800000 0 0x800000>; 309405090bb9SJonathan Marek reg-names = "membase"; 309505090bb9SJonathan Marek memory-region = <&wlan_mem>; 309605090bb9SJonathan Marek clock-names = "cxo_ref_clk_pin", "qdss"; 309705090bb9SJonathan Marek clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 309805090bb9SJonathan Marek interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 309905090bb9SJonathan Marek <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 310005090bb9SJonathan Marek <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 310105090bb9SJonathan Marek <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 310205090bb9SJonathan Marek <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 310305090bb9SJonathan Marek <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 310405090bb9SJonathan Marek <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 310505090bb9SJonathan Marek <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 310605090bb9SJonathan Marek <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 310705090bb9SJonathan Marek <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 310805090bb9SJonathan Marek <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 310905090bb9SJonathan Marek <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 311005090bb9SJonathan Marek iommus = <&apps_smmu 0x0640 0x1>; 311105090bb9SJonathan Marek status = "disabled"; 311205090bb9SJonathan Marek }; 3113e13c6d14SVinod Koul }; 3114e13c6d14SVinod Koul 3115e13c6d14SVinod Koul timer { 3116e13c6d14SVinod Koul compatible = "arm,armv8-timer"; 3117e13c6d14SVinod Koul interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 3118e13c6d14SVinod Koul <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 3119e13c6d14SVinod Koul <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 3120e13c6d14SVinod Koul <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 3121e13c6d14SVinod Koul }; 3122d2fa630cSAmit Kucheria 3123d2fa630cSAmit Kucheria thermal-zones { 3124d2fa630cSAmit Kucheria cpu0-thermal { 3125d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3126d2fa630cSAmit Kucheria polling-delay = <1000>; 3127d2fa630cSAmit Kucheria 3128d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 1>; 3129d2fa630cSAmit Kucheria 3130d2fa630cSAmit Kucheria trips { 3131d2fa630cSAmit Kucheria cpu0_alert0: trip-point0 { 3132d2fa630cSAmit Kucheria temperature = <90000>; 3133d2fa630cSAmit Kucheria hysteresis = <2000>; 3134d2fa630cSAmit Kucheria type = "passive"; 3135d2fa630cSAmit Kucheria }; 3136d2fa630cSAmit Kucheria 3137d2fa630cSAmit Kucheria cpu0_alert1: trip-point1 { 3138d2fa630cSAmit Kucheria temperature = <95000>; 3139d2fa630cSAmit Kucheria hysteresis = <2000>; 3140d2fa630cSAmit Kucheria type = "passive"; 3141d2fa630cSAmit Kucheria }; 3142d2fa630cSAmit Kucheria 3143d2fa630cSAmit Kucheria cpu0_crit: cpu_crit { 3144d2fa630cSAmit Kucheria temperature = <110000>; 3145d2fa630cSAmit Kucheria hysteresis = <1000>; 3146d2fa630cSAmit Kucheria type = "critical"; 3147d2fa630cSAmit Kucheria }; 3148d2fa630cSAmit Kucheria }; 3149d2fa630cSAmit Kucheria 3150d2fa630cSAmit Kucheria cooling-maps { 3151d2fa630cSAmit Kucheria map0 { 3152d2fa630cSAmit Kucheria trip = <&cpu0_alert0>; 3153d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3154d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3155d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3156d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3157d2fa630cSAmit Kucheria }; 3158d2fa630cSAmit Kucheria map1 { 3159d2fa630cSAmit Kucheria trip = <&cpu0_alert1>; 3160d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3161d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3162d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3163d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3164d2fa630cSAmit Kucheria }; 3165d2fa630cSAmit Kucheria }; 3166d2fa630cSAmit Kucheria }; 3167d2fa630cSAmit Kucheria 3168d2fa630cSAmit Kucheria cpu1-thermal { 3169d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3170d2fa630cSAmit Kucheria polling-delay = <1000>; 3171d2fa630cSAmit Kucheria 3172d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 2>; 3173d2fa630cSAmit Kucheria 3174d2fa630cSAmit Kucheria trips { 3175d2fa630cSAmit Kucheria cpu1_alert0: trip-point0 { 3176d2fa630cSAmit Kucheria temperature = <90000>; 3177d2fa630cSAmit Kucheria hysteresis = <2000>; 3178d2fa630cSAmit Kucheria type = "passive"; 3179d2fa630cSAmit Kucheria }; 3180d2fa630cSAmit Kucheria 3181d2fa630cSAmit Kucheria cpu1_alert1: trip-point1 { 3182d2fa630cSAmit Kucheria temperature = <95000>; 3183d2fa630cSAmit Kucheria hysteresis = <2000>; 3184d2fa630cSAmit Kucheria type = "passive"; 3185d2fa630cSAmit Kucheria }; 3186d2fa630cSAmit Kucheria 3187d2fa630cSAmit Kucheria cpu1_crit: cpu_crit { 3188d2fa630cSAmit Kucheria temperature = <110000>; 3189d2fa630cSAmit Kucheria hysteresis = <1000>; 3190d2fa630cSAmit Kucheria type = "critical"; 3191d2fa630cSAmit Kucheria }; 3192d2fa630cSAmit Kucheria }; 3193d2fa630cSAmit Kucheria 3194d2fa630cSAmit Kucheria cooling-maps { 3195d2fa630cSAmit Kucheria map0 { 3196d2fa630cSAmit Kucheria trip = <&cpu1_alert0>; 3197d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3198d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3199d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3200d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3201d2fa630cSAmit Kucheria }; 3202d2fa630cSAmit Kucheria map1 { 3203d2fa630cSAmit Kucheria trip = <&cpu1_alert1>; 3204d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3205d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3206d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3207d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3208d2fa630cSAmit Kucheria }; 3209d2fa630cSAmit Kucheria }; 3210d2fa630cSAmit Kucheria }; 3211d2fa630cSAmit Kucheria 3212d2fa630cSAmit Kucheria cpu2-thermal { 3213d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3214d2fa630cSAmit Kucheria polling-delay = <1000>; 3215d2fa630cSAmit Kucheria 3216d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 3>; 3217d2fa630cSAmit Kucheria 3218d2fa630cSAmit Kucheria trips { 3219d2fa630cSAmit Kucheria cpu2_alert0: trip-point0 { 3220d2fa630cSAmit Kucheria temperature = <90000>; 3221d2fa630cSAmit Kucheria hysteresis = <2000>; 3222d2fa630cSAmit Kucheria type = "passive"; 3223d2fa630cSAmit Kucheria }; 3224d2fa630cSAmit Kucheria 3225d2fa630cSAmit Kucheria cpu2_alert1: trip-point1 { 3226d2fa630cSAmit Kucheria temperature = <95000>; 3227d2fa630cSAmit Kucheria hysteresis = <2000>; 3228d2fa630cSAmit Kucheria type = "passive"; 3229d2fa630cSAmit Kucheria }; 3230d2fa630cSAmit Kucheria 3231d2fa630cSAmit Kucheria cpu2_crit: cpu_crit { 3232d2fa630cSAmit Kucheria temperature = <110000>; 3233d2fa630cSAmit Kucheria hysteresis = <1000>; 3234d2fa630cSAmit Kucheria type = "critical"; 3235d2fa630cSAmit Kucheria }; 3236d2fa630cSAmit Kucheria }; 3237d2fa630cSAmit Kucheria 3238d2fa630cSAmit Kucheria cooling-maps { 3239d2fa630cSAmit Kucheria map0 { 3240d2fa630cSAmit Kucheria trip = <&cpu2_alert0>; 3241d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3242d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3243d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3244d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3245d2fa630cSAmit Kucheria }; 3246d2fa630cSAmit Kucheria map1 { 3247d2fa630cSAmit Kucheria trip = <&cpu2_alert1>; 3248d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3249d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3250d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3251d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3252d2fa630cSAmit Kucheria }; 3253d2fa630cSAmit Kucheria }; 3254d2fa630cSAmit Kucheria }; 3255d2fa630cSAmit Kucheria 3256d2fa630cSAmit Kucheria cpu3-thermal { 3257d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3258d2fa630cSAmit Kucheria polling-delay = <1000>; 3259d2fa630cSAmit Kucheria 3260d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 4>; 3261d2fa630cSAmit Kucheria 3262d2fa630cSAmit Kucheria trips { 3263d2fa630cSAmit Kucheria cpu3_alert0: trip-point0 { 3264d2fa630cSAmit Kucheria temperature = <90000>; 3265d2fa630cSAmit Kucheria hysteresis = <2000>; 3266d2fa630cSAmit Kucheria type = "passive"; 3267d2fa630cSAmit Kucheria }; 3268d2fa630cSAmit Kucheria 3269d2fa630cSAmit Kucheria cpu3_alert1: trip-point1 { 3270d2fa630cSAmit Kucheria temperature = <95000>; 3271d2fa630cSAmit Kucheria hysteresis = <2000>; 3272d2fa630cSAmit Kucheria type = "passive"; 3273d2fa630cSAmit Kucheria }; 3274d2fa630cSAmit Kucheria 3275d2fa630cSAmit Kucheria cpu3_crit: cpu_crit { 3276d2fa630cSAmit Kucheria temperature = <110000>; 3277d2fa630cSAmit Kucheria hysteresis = <1000>; 3278d2fa630cSAmit Kucheria type = "critical"; 3279d2fa630cSAmit Kucheria }; 3280d2fa630cSAmit Kucheria }; 3281d2fa630cSAmit Kucheria 3282d2fa630cSAmit Kucheria cooling-maps { 3283d2fa630cSAmit Kucheria map0 { 3284d2fa630cSAmit Kucheria trip = <&cpu3_alert0>; 3285d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3286d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3287d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3288d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3289d2fa630cSAmit Kucheria }; 3290d2fa630cSAmit Kucheria map1 { 3291d2fa630cSAmit Kucheria trip = <&cpu3_alert1>; 3292d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3293d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3294d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3295d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3296d2fa630cSAmit Kucheria }; 3297d2fa630cSAmit Kucheria }; 3298d2fa630cSAmit Kucheria }; 3299d2fa630cSAmit Kucheria 3300d2fa630cSAmit Kucheria cpu4-top-thermal { 3301d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3302d2fa630cSAmit Kucheria polling-delay = <1000>; 3303d2fa630cSAmit Kucheria 3304d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 7>; 3305d2fa630cSAmit Kucheria 3306d2fa630cSAmit Kucheria trips { 3307d2fa630cSAmit Kucheria cpu4_top_alert0: trip-point0 { 3308d2fa630cSAmit Kucheria temperature = <90000>; 3309d2fa630cSAmit Kucheria hysteresis = <2000>; 3310d2fa630cSAmit Kucheria type = "passive"; 3311d2fa630cSAmit Kucheria }; 3312d2fa630cSAmit Kucheria 3313d2fa630cSAmit Kucheria cpu4_top_alert1: trip-point1 { 3314d2fa630cSAmit Kucheria temperature = <95000>; 3315d2fa630cSAmit Kucheria hysteresis = <2000>; 3316d2fa630cSAmit Kucheria type = "passive"; 3317d2fa630cSAmit Kucheria }; 3318d2fa630cSAmit Kucheria 3319d2fa630cSAmit Kucheria cpu4_top_crit: cpu_crit { 3320d2fa630cSAmit Kucheria temperature = <110000>; 3321d2fa630cSAmit Kucheria hysteresis = <1000>; 3322d2fa630cSAmit Kucheria type = "critical"; 3323d2fa630cSAmit Kucheria }; 3324d2fa630cSAmit Kucheria }; 3325d2fa630cSAmit Kucheria 3326d2fa630cSAmit Kucheria cooling-maps { 3327d2fa630cSAmit Kucheria map0 { 3328d2fa630cSAmit Kucheria trip = <&cpu4_top_alert0>; 3329d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3330d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3331d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3332d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3333d2fa630cSAmit Kucheria }; 3334d2fa630cSAmit Kucheria map1 { 3335d2fa630cSAmit Kucheria trip = <&cpu4_top_alert1>; 3336d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3337d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3338d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3339d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3340d2fa630cSAmit Kucheria }; 3341d2fa630cSAmit Kucheria }; 3342d2fa630cSAmit Kucheria }; 3343d2fa630cSAmit Kucheria 3344d2fa630cSAmit Kucheria cpu5-top-thermal { 3345d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3346d2fa630cSAmit Kucheria polling-delay = <1000>; 3347d2fa630cSAmit Kucheria 3348d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 8>; 3349d2fa630cSAmit Kucheria 3350d2fa630cSAmit Kucheria trips { 3351d2fa630cSAmit Kucheria cpu5_top_alert0: trip-point0 { 3352d2fa630cSAmit Kucheria temperature = <90000>; 3353d2fa630cSAmit Kucheria hysteresis = <2000>; 3354d2fa630cSAmit Kucheria type = "passive"; 3355d2fa630cSAmit Kucheria }; 3356d2fa630cSAmit Kucheria 3357d2fa630cSAmit Kucheria cpu5_top_alert1: trip-point1 { 3358d2fa630cSAmit Kucheria temperature = <95000>; 3359d2fa630cSAmit Kucheria hysteresis = <2000>; 3360d2fa630cSAmit Kucheria type = "passive"; 3361d2fa630cSAmit Kucheria }; 3362d2fa630cSAmit Kucheria 3363d2fa630cSAmit Kucheria cpu5_top_crit: cpu_crit { 3364d2fa630cSAmit Kucheria temperature = <110000>; 3365d2fa630cSAmit Kucheria hysteresis = <1000>; 3366d2fa630cSAmit Kucheria type = "critical"; 3367d2fa630cSAmit Kucheria }; 3368d2fa630cSAmit Kucheria }; 3369d2fa630cSAmit Kucheria 3370d2fa630cSAmit Kucheria cooling-maps { 3371d2fa630cSAmit Kucheria map0 { 3372d2fa630cSAmit Kucheria trip = <&cpu5_top_alert0>; 3373d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3374d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3375d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3376d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3377d2fa630cSAmit Kucheria }; 3378d2fa630cSAmit Kucheria map1 { 3379d2fa630cSAmit Kucheria trip = <&cpu5_top_alert1>; 3380d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3381d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3382d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3383d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3384d2fa630cSAmit Kucheria }; 3385d2fa630cSAmit Kucheria }; 3386d2fa630cSAmit Kucheria }; 3387d2fa630cSAmit Kucheria 3388d2fa630cSAmit Kucheria cpu6-top-thermal { 3389d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3390d2fa630cSAmit Kucheria polling-delay = <1000>; 3391d2fa630cSAmit Kucheria 3392d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 9>; 3393d2fa630cSAmit Kucheria 3394d2fa630cSAmit Kucheria trips { 3395d2fa630cSAmit Kucheria cpu6_top_alert0: trip-point0 { 3396d2fa630cSAmit Kucheria temperature = <90000>; 3397d2fa630cSAmit Kucheria hysteresis = <2000>; 3398d2fa630cSAmit Kucheria type = "passive"; 3399d2fa630cSAmit Kucheria }; 3400d2fa630cSAmit Kucheria 3401d2fa630cSAmit Kucheria cpu6_top_alert1: trip-point1 { 3402d2fa630cSAmit Kucheria temperature = <95000>; 3403d2fa630cSAmit Kucheria hysteresis = <2000>; 3404d2fa630cSAmit Kucheria type = "passive"; 3405d2fa630cSAmit Kucheria }; 3406d2fa630cSAmit Kucheria 3407d2fa630cSAmit Kucheria cpu6_top_crit: cpu_crit { 3408d2fa630cSAmit Kucheria temperature = <110000>; 3409d2fa630cSAmit Kucheria hysteresis = <1000>; 3410d2fa630cSAmit Kucheria type = "critical"; 3411d2fa630cSAmit Kucheria }; 3412d2fa630cSAmit Kucheria }; 3413d2fa630cSAmit Kucheria 3414d2fa630cSAmit Kucheria cooling-maps { 3415d2fa630cSAmit Kucheria map0 { 3416d2fa630cSAmit Kucheria trip = <&cpu6_top_alert0>; 3417d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3418d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3419d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3420d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3421d2fa630cSAmit Kucheria }; 3422d2fa630cSAmit Kucheria map1 { 3423d2fa630cSAmit Kucheria trip = <&cpu6_top_alert1>; 3424d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3425d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3426d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3427d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3428d2fa630cSAmit Kucheria }; 3429d2fa630cSAmit Kucheria }; 3430d2fa630cSAmit Kucheria }; 3431d2fa630cSAmit Kucheria 3432d2fa630cSAmit Kucheria cpu7-top-thermal { 3433d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3434d2fa630cSAmit Kucheria polling-delay = <1000>; 3435d2fa630cSAmit Kucheria 3436d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 10>; 3437d2fa630cSAmit Kucheria 3438d2fa630cSAmit Kucheria trips { 3439d2fa630cSAmit Kucheria cpu7_top_alert0: trip-point0 { 3440d2fa630cSAmit Kucheria temperature = <90000>; 3441d2fa630cSAmit Kucheria hysteresis = <2000>; 3442d2fa630cSAmit Kucheria type = "passive"; 3443d2fa630cSAmit Kucheria }; 3444d2fa630cSAmit Kucheria 3445d2fa630cSAmit Kucheria cpu7_top_alert1: trip-point1 { 3446d2fa630cSAmit Kucheria temperature = <95000>; 3447d2fa630cSAmit Kucheria hysteresis = <2000>; 3448d2fa630cSAmit Kucheria type = "passive"; 3449d2fa630cSAmit Kucheria }; 3450d2fa630cSAmit Kucheria 3451d2fa630cSAmit Kucheria cpu7_top_crit: cpu_crit { 3452d2fa630cSAmit Kucheria temperature = <110000>; 3453d2fa630cSAmit Kucheria hysteresis = <1000>; 3454d2fa630cSAmit Kucheria type = "critical"; 3455d2fa630cSAmit Kucheria }; 3456d2fa630cSAmit Kucheria }; 3457d2fa630cSAmit Kucheria 3458d2fa630cSAmit Kucheria cooling-maps { 3459d2fa630cSAmit Kucheria map0 { 3460d2fa630cSAmit Kucheria trip = <&cpu7_top_alert0>; 3461d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3462d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3463d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3464d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3465d2fa630cSAmit Kucheria }; 3466d2fa630cSAmit Kucheria map1 { 3467d2fa630cSAmit Kucheria trip = <&cpu7_top_alert1>; 3468d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3469d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3470d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3471d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3472d2fa630cSAmit Kucheria }; 3473d2fa630cSAmit Kucheria }; 3474d2fa630cSAmit Kucheria }; 3475d2fa630cSAmit Kucheria 3476d2fa630cSAmit Kucheria cpu4-bottom-thermal { 3477d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3478d2fa630cSAmit Kucheria polling-delay = <1000>; 3479d2fa630cSAmit Kucheria 3480d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 11>; 3481d2fa630cSAmit Kucheria 3482d2fa630cSAmit Kucheria trips { 3483d2fa630cSAmit Kucheria cpu4_bottom_alert0: trip-point0 { 3484d2fa630cSAmit Kucheria temperature = <90000>; 3485d2fa630cSAmit Kucheria hysteresis = <2000>; 3486d2fa630cSAmit Kucheria type = "passive"; 3487d2fa630cSAmit Kucheria }; 3488d2fa630cSAmit Kucheria 3489d2fa630cSAmit Kucheria cpu4_bottom_alert1: trip-point1 { 3490d2fa630cSAmit Kucheria temperature = <95000>; 3491d2fa630cSAmit Kucheria hysteresis = <2000>; 3492d2fa630cSAmit Kucheria type = "passive"; 3493d2fa630cSAmit Kucheria }; 3494d2fa630cSAmit Kucheria 3495d2fa630cSAmit Kucheria cpu4_bottom_crit: cpu_crit { 3496d2fa630cSAmit Kucheria temperature = <110000>; 3497d2fa630cSAmit Kucheria hysteresis = <1000>; 3498d2fa630cSAmit Kucheria type = "critical"; 3499d2fa630cSAmit Kucheria }; 3500d2fa630cSAmit Kucheria }; 3501d2fa630cSAmit Kucheria 3502d2fa630cSAmit Kucheria cooling-maps { 3503d2fa630cSAmit Kucheria map0 { 3504d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert0>; 3505d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3506d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3507d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3508d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3509d2fa630cSAmit Kucheria }; 3510d2fa630cSAmit Kucheria map1 { 3511d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert1>; 3512d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3513d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3514d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3515d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3516d2fa630cSAmit Kucheria }; 3517d2fa630cSAmit Kucheria }; 3518d2fa630cSAmit Kucheria }; 3519d2fa630cSAmit Kucheria 3520d2fa630cSAmit Kucheria cpu5-bottom-thermal { 3521d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3522d2fa630cSAmit Kucheria polling-delay = <1000>; 3523d2fa630cSAmit Kucheria 3524d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 12>; 3525d2fa630cSAmit Kucheria 3526d2fa630cSAmit Kucheria trips { 3527d2fa630cSAmit Kucheria cpu5_bottom_alert0: trip-point0 { 3528d2fa630cSAmit Kucheria temperature = <90000>; 3529d2fa630cSAmit Kucheria hysteresis = <2000>; 3530d2fa630cSAmit Kucheria type = "passive"; 3531d2fa630cSAmit Kucheria }; 3532d2fa630cSAmit Kucheria 3533d2fa630cSAmit Kucheria cpu5_bottom_alert1: trip-point1 { 3534d2fa630cSAmit Kucheria temperature = <95000>; 3535d2fa630cSAmit Kucheria hysteresis = <2000>; 3536d2fa630cSAmit Kucheria type = "passive"; 3537d2fa630cSAmit Kucheria }; 3538d2fa630cSAmit Kucheria 3539d2fa630cSAmit Kucheria cpu5_bottom_crit: cpu_crit { 3540d2fa630cSAmit Kucheria temperature = <110000>; 3541d2fa630cSAmit Kucheria hysteresis = <1000>; 3542d2fa630cSAmit Kucheria type = "critical"; 3543d2fa630cSAmit Kucheria }; 3544d2fa630cSAmit Kucheria }; 3545d2fa630cSAmit Kucheria 3546d2fa630cSAmit Kucheria cooling-maps { 3547d2fa630cSAmit Kucheria map0 { 3548d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert0>; 3549d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3550d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3551d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3552d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3553d2fa630cSAmit Kucheria }; 3554d2fa630cSAmit Kucheria map1 { 3555d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert1>; 3556d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3557d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3558d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3559d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3560d2fa630cSAmit Kucheria }; 3561d2fa630cSAmit Kucheria }; 3562d2fa630cSAmit Kucheria }; 3563d2fa630cSAmit Kucheria 3564d2fa630cSAmit Kucheria cpu6-bottom-thermal { 3565d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3566d2fa630cSAmit Kucheria polling-delay = <1000>; 3567d2fa630cSAmit Kucheria 3568d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 13>; 3569d2fa630cSAmit Kucheria 3570d2fa630cSAmit Kucheria trips { 3571d2fa630cSAmit Kucheria cpu6_bottom_alert0: trip-point0 { 3572d2fa630cSAmit Kucheria temperature = <90000>; 3573d2fa630cSAmit Kucheria hysteresis = <2000>; 3574d2fa630cSAmit Kucheria type = "passive"; 3575d2fa630cSAmit Kucheria }; 3576d2fa630cSAmit Kucheria 3577d2fa630cSAmit Kucheria cpu6_bottom_alert1: trip-point1 { 3578d2fa630cSAmit Kucheria temperature = <95000>; 3579d2fa630cSAmit Kucheria hysteresis = <2000>; 3580d2fa630cSAmit Kucheria type = "passive"; 3581d2fa630cSAmit Kucheria }; 3582d2fa630cSAmit Kucheria 3583d2fa630cSAmit Kucheria cpu6_bottom_crit: cpu_crit { 3584d2fa630cSAmit Kucheria temperature = <110000>; 3585d2fa630cSAmit Kucheria hysteresis = <1000>; 3586d2fa630cSAmit Kucheria type = "critical"; 3587d2fa630cSAmit Kucheria }; 3588d2fa630cSAmit Kucheria }; 3589d2fa630cSAmit Kucheria 3590d2fa630cSAmit Kucheria cooling-maps { 3591d2fa630cSAmit Kucheria map0 { 3592d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert0>; 3593d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3594d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3595d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3596d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3597d2fa630cSAmit Kucheria }; 3598d2fa630cSAmit Kucheria map1 { 3599d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert1>; 3600d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3601d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3602d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3603d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3604d2fa630cSAmit Kucheria }; 3605d2fa630cSAmit Kucheria }; 3606d2fa630cSAmit Kucheria }; 3607d2fa630cSAmit Kucheria 3608d2fa630cSAmit Kucheria cpu7-bottom-thermal { 3609d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3610d2fa630cSAmit Kucheria polling-delay = <1000>; 3611d2fa630cSAmit Kucheria 3612d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 14>; 3613d2fa630cSAmit Kucheria 3614d2fa630cSAmit Kucheria trips { 3615d2fa630cSAmit Kucheria cpu7_bottom_alert0: trip-point0 { 3616d2fa630cSAmit Kucheria temperature = <90000>; 3617d2fa630cSAmit Kucheria hysteresis = <2000>; 3618d2fa630cSAmit Kucheria type = "passive"; 3619d2fa630cSAmit Kucheria }; 3620d2fa630cSAmit Kucheria 3621d2fa630cSAmit Kucheria cpu7_bottom_alert1: trip-point1 { 3622d2fa630cSAmit Kucheria temperature = <95000>; 3623d2fa630cSAmit Kucheria hysteresis = <2000>; 3624d2fa630cSAmit Kucheria type = "passive"; 3625d2fa630cSAmit Kucheria }; 3626d2fa630cSAmit Kucheria 3627d2fa630cSAmit Kucheria cpu7_bottom_crit: cpu_crit { 3628d2fa630cSAmit Kucheria temperature = <110000>; 3629d2fa630cSAmit Kucheria hysteresis = <1000>; 3630d2fa630cSAmit Kucheria type = "critical"; 3631d2fa630cSAmit Kucheria }; 3632d2fa630cSAmit Kucheria }; 3633d2fa630cSAmit Kucheria 3634d2fa630cSAmit Kucheria cooling-maps { 3635d2fa630cSAmit Kucheria map0 { 3636d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert0>; 3637d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3638d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3639d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3640d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3641d2fa630cSAmit Kucheria }; 3642d2fa630cSAmit Kucheria map1 { 3643d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert1>; 3644d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3645d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3646d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3647d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3648d2fa630cSAmit Kucheria }; 3649d2fa630cSAmit Kucheria }; 3650d2fa630cSAmit Kucheria }; 3651d2fa630cSAmit Kucheria 3652d2fa630cSAmit Kucheria aoss0-thermal { 3653d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3654d2fa630cSAmit Kucheria polling-delay = <1000>; 3655d2fa630cSAmit Kucheria 3656d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 0>; 3657d2fa630cSAmit Kucheria 3658d2fa630cSAmit Kucheria trips { 3659d2fa630cSAmit Kucheria aoss0_alert0: trip-point0 { 3660d2fa630cSAmit Kucheria temperature = <90000>; 3661d2fa630cSAmit Kucheria hysteresis = <2000>; 3662d2fa630cSAmit Kucheria type = "hot"; 3663d2fa630cSAmit Kucheria }; 3664d2fa630cSAmit Kucheria }; 3665d2fa630cSAmit Kucheria }; 3666d2fa630cSAmit Kucheria 3667d2fa630cSAmit Kucheria cluster0-thermal { 3668d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3669d2fa630cSAmit Kucheria polling-delay = <1000>; 3670d2fa630cSAmit Kucheria 3671d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 5>; 3672d2fa630cSAmit Kucheria 3673d2fa630cSAmit Kucheria trips { 3674d2fa630cSAmit Kucheria cluster0_alert0: trip-point0 { 3675d2fa630cSAmit Kucheria temperature = <90000>; 3676d2fa630cSAmit Kucheria hysteresis = <2000>; 3677d2fa630cSAmit Kucheria type = "hot"; 3678d2fa630cSAmit Kucheria }; 3679d2fa630cSAmit Kucheria cluster0_crit: cluster0_crit { 3680d2fa630cSAmit Kucheria temperature = <110000>; 3681d2fa630cSAmit Kucheria hysteresis = <2000>; 3682d2fa630cSAmit Kucheria type = "critical"; 3683d2fa630cSAmit Kucheria }; 3684d2fa630cSAmit Kucheria }; 3685d2fa630cSAmit Kucheria }; 3686d2fa630cSAmit Kucheria 3687d2fa630cSAmit Kucheria cluster1-thermal { 3688d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3689d2fa630cSAmit Kucheria polling-delay = <1000>; 3690d2fa630cSAmit Kucheria 3691d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 6>; 3692d2fa630cSAmit Kucheria 3693d2fa630cSAmit Kucheria trips { 3694d2fa630cSAmit Kucheria cluster1_alert0: trip-point0 { 3695d2fa630cSAmit Kucheria temperature = <90000>; 3696d2fa630cSAmit Kucheria hysteresis = <2000>; 3697d2fa630cSAmit Kucheria type = "hot"; 3698d2fa630cSAmit Kucheria }; 3699d2fa630cSAmit Kucheria cluster1_crit: cluster1_crit { 3700d2fa630cSAmit Kucheria temperature = <110000>; 3701d2fa630cSAmit Kucheria hysteresis = <2000>; 3702d2fa630cSAmit Kucheria type = "critical"; 3703d2fa630cSAmit Kucheria }; 3704d2fa630cSAmit Kucheria }; 3705d2fa630cSAmit Kucheria }; 3706d2fa630cSAmit Kucheria 3707d2fa630cSAmit Kucheria gpu-thermal-top { 3708d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3709d2fa630cSAmit Kucheria polling-delay = <1000>; 3710d2fa630cSAmit Kucheria 3711d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 15>; 3712d2fa630cSAmit Kucheria 3713d2fa630cSAmit Kucheria trips { 3714d2fa630cSAmit Kucheria gpu1_alert0: trip-point0 { 3715d2fa630cSAmit Kucheria temperature = <90000>; 3716d2fa630cSAmit Kucheria hysteresis = <2000>; 3717d2fa630cSAmit Kucheria type = "hot"; 3718d2fa630cSAmit Kucheria }; 3719d2fa630cSAmit Kucheria }; 3720d2fa630cSAmit Kucheria }; 3721d2fa630cSAmit Kucheria 3722d2fa630cSAmit Kucheria aoss1-thermal { 3723d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3724d2fa630cSAmit Kucheria polling-delay = <1000>; 3725d2fa630cSAmit Kucheria 3726d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 0>; 3727d2fa630cSAmit Kucheria 3728d2fa630cSAmit Kucheria trips { 3729d2fa630cSAmit Kucheria aoss1_alert0: trip-point0 { 3730d2fa630cSAmit Kucheria temperature = <90000>; 3731d2fa630cSAmit Kucheria hysteresis = <2000>; 3732d2fa630cSAmit Kucheria type = "hot"; 3733d2fa630cSAmit Kucheria }; 3734d2fa630cSAmit Kucheria }; 3735d2fa630cSAmit Kucheria }; 3736d2fa630cSAmit Kucheria 3737d2fa630cSAmit Kucheria wlan-thermal { 3738d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3739d2fa630cSAmit Kucheria polling-delay = <1000>; 3740d2fa630cSAmit Kucheria 3741d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 1>; 3742d2fa630cSAmit Kucheria 3743d2fa630cSAmit Kucheria trips { 3744d2fa630cSAmit Kucheria wlan_alert0: trip-point0 { 3745d2fa630cSAmit Kucheria temperature = <90000>; 3746d2fa630cSAmit Kucheria hysteresis = <2000>; 3747d2fa630cSAmit Kucheria type = "hot"; 3748d2fa630cSAmit Kucheria }; 3749d2fa630cSAmit Kucheria }; 3750d2fa630cSAmit Kucheria }; 3751d2fa630cSAmit Kucheria 3752d2fa630cSAmit Kucheria video-thermal { 3753d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3754d2fa630cSAmit Kucheria polling-delay = <1000>; 3755d2fa630cSAmit Kucheria 3756d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 2>; 3757d2fa630cSAmit Kucheria 3758d2fa630cSAmit Kucheria trips { 3759d2fa630cSAmit Kucheria video_alert0: trip-point0 { 3760d2fa630cSAmit Kucheria temperature = <90000>; 3761d2fa630cSAmit Kucheria hysteresis = <2000>; 3762d2fa630cSAmit Kucheria type = "hot"; 3763d2fa630cSAmit Kucheria }; 3764d2fa630cSAmit Kucheria }; 3765d2fa630cSAmit Kucheria }; 3766d2fa630cSAmit Kucheria 3767d2fa630cSAmit Kucheria mem-thermal { 3768d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3769d2fa630cSAmit Kucheria polling-delay = <1000>; 3770d2fa630cSAmit Kucheria 3771d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 3>; 3772d2fa630cSAmit Kucheria 3773d2fa630cSAmit Kucheria trips { 3774d2fa630cSAmit Kucheria mem_alert0: trip-point0 { 3775d2fa630cSAmit Kucheria temperature = <90000>; 3776d2fa630cSAmit Kucheria hysteresis = <2000>; 3777d2fa630cSAmit Kucheria type = "hot"; 3778d2fa630cSAmit Kucheria }; 3779d2fa630cSAmit Kucheria }; 3780d2fa630cSAmit Kucheria }; 3781d2fa630cSAmit Kucheria 3782d2fa630cSAmit Kucheria q6-hvx-thermal { 3783d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3784d2fa630cSAmit Kucheria polling-delay = <1000>; 3785d2fa630cSAmit Kucheria 3786d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 4>; 3787d2fa630cSAmit Kucheria 3788d2fa630cSAmit Kucheria trips { 3789d2fa630cSAmit Kucheria q6_hvx_alert0: trip-point0 { 3790d2fa630cSAmit Kucheria temperature = <90000>; 3791d2fa630cSAmit Kucheria hysteresis = <2000>; 3792d2fa630cSAmit Kucheria type = "hot"; 3793d2fa630cSAmit Kucheria }; 3794d2fa630cSAmit Kucheria }; 3795d2fa630cSAmit Kucheria }; 3796d2fa630cSAmit Kucheria 3797d2fa630cSAmit Kucheria camera-thermal { 3798d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3799d2fa630cSAmit Kucheria polling-delay = <1000>; 3800d2fa630cSAmit Kucheria 3801d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 5>; 3802d2fa630cSAmit Kucheria 3803d2fa630cSAmit Kucheria trips { 3804d2fa630cSAmit Kucheria camera_alert0: trip-point0 { 3805d2fa630cSAmit Kucheria temperature = <90000>; 3806d2fa630cSAmit Kucheria hysteresis = <2000>; 3807d2fa630cSAmit Kucheria type = "hot"; 3808d2fa630cSAmit Kucheria }; 3809d2fa630cSAmit Kucheria }; 3810d2fa630cSAmit Kucheria }; 3811d2fa630cSAmit Kucheria 3812d2fa630cSAmit Kucheria compute-thermal { 3813d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3814d2fa630cSAmit Kucheria polling-delay = <1000>; 3815d2fa630cSAmit Kucheria 3816d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 6>; 3817d2fa630cSAmit Kucheria 3818d2fa630cSAmit Kucheria trips { 3819d2fa630cSAmit Kucheria compute_alert0: trip-point0 { 3820d2fa630cSAmit Kucheria temperature = <90000>; 3821d2fa630cSAmit Kucheria hysteresis = <2000>; 3822d2fa630cSAmit Kucheria type = "hot"; 3823d2fa630cSAmit Kucheria }; 3824d2fa630cSAmit Kucheria }; 3825d2fa630cSAmit Kucheria }; 3826d2fa630cSAmit Kucheria 3827d2fa630cSAmit Kucheria modem-thermal { 3828d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3829d2fa630cSAmit Kucheria polling-delay = <1000>; 3830d2fa630cSAmit Kucheria 3831d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 7>; 3832d2fa630cSAmit Kucheria 3833d2fa630cSAmit Kucheria trips { 3834d2fa630cSAmit Kucheria modem_alert0: trip-point0 { 3835d2fa630cSAmit Kucheria temperature = <90000>; 3836d2fa630cSAmit Kucheria hysteresis = <2000>; 3837d2fa630cSAmit Kucheria type = "hot"; 3838d2fa630cSAmit Kucheria }; 3839d2fa630cSAmit Kucheria }; 3840d2fa630cSAmit Kucheria }; 3841d2fa630cSAmit Kucheria 3842d2fa630cSAmit Kucheria npu-thermal { 3843d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3844d2fa630cSAmit Kucheria polling-delay = <1000>; 3845d2fa630cSAmit Kucheria 3846d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 8>; 3847d2fa630cSAmit Kucheria 3848d2fa630cSAmit Kucheria trips { 3849d2fa630cSAmit Kucheria npu_alert0: trip-point0 { 3850d2fa630cSAmit Kucheria temperature = <90000>; 3851d2fa630cSAmit Kucheria hysteresis = <2000>; 3852d2fa630cSAmit Kucheria type = "hot"; 3853d2fa630cSAmit Kucheria }; 3854d2fa630cSAmit Kucheria }; 3855d2fa630cSAmit Kucheria }; 3856d2fa630cSAmit Kucheria 3857d2fa630cSAmit Kucheria modem-vec-thermal { 3858d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3859d2fa630cSAmit Kucheria polling-delay = <1000>; 3860d2fa630cSAmit Kucheria 3861d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 9>; 3862d2fa630cSAmit Kucheria 3863d2fa630cSAmit Kucheria trips { 3864d2fa630cSAmit Kucheria modem_vec_alert0: trip-point0 { 3865d2fa630cSAmit Kucheria temperature = <90000>; 3866d2fa630cSAmit Kucheria hysteresis = <2000>; 3867d2fa630cSAmit Kucheria type = "hot"; 3868d2fa630cSAmit Kucheria }; 3869d2fa630cSAmit Kucheria }; 3870d2fa630cSAmit Kucheria }; 3871d2fa630cSAmit Kucheria 3872d2fa630cSAmit Kucheria modem-scl-thermal { 3873d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3874d2fa630cSAmit Kucheria polling-delay = <1000>; 3875d2fa630cSAmit Kucheria 3876d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 10>; 3877d2fa630cSAmit Kucheria 3878d2fa630cSAmit Kucheria trips { 3879d2fa630cSAmit Kucheria modem_scl_alert0: trip-point0 { 3880d2fa630cSAmit Kucheria temperature = <90000>; 3881d2fa630cSAmit Kucheria hysteresis = <2000>; 3882d2fa630cSAmit Kucheria type = "hot"; 3883d2fa630cSAmit Kucheria }; 3884d2fa630cSAmit Kucheria }; 3885d2fa630cSAmit Kucheria }; 3886d2fa630cSAmit Kucheria 3887d2fa630cSAmit Kucheria gpu-thermal-bottom { 3888d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3889d2fa630cSAmit Kucheria polling-delay = <1000>; 3890d2fa630cSAmit Kucheria 3891d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 11>; 3892d2fa630cSAmit Kucheria 3893d2fa630cSAmit Kucheria trips { 3894d2fa630cSAmit Kucheria gpu2_alert0: trip-point0 { 3895d2fa630cSAmit Kucheria temperature = <90000>; 3896d2fa630cSAmit Kucheria hysteresis = <2000>; 3897d2fa630cSAmit Kucheria type = "hot"; 3898d2fa630cSAmit Kucheria }; 3899d2fa630cSAmit Kucheria }; 3900d2fa630cSAmit Kucheria }; 3901d2fa630cSAmit Kucheria }; 3902e13c6d14SVinod Koul}; 3903