1e13c6d14SVinod Koul// SPDX-License-Identifier: BSD-3-Clause 2e13c6d14SVinod Koul/* 3e13c6d14SVinod Koul * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4e13c6d14SVinod Koul * Copyright (c) 2019, Linaro Limited 5e13c6d14SVinod Koul */ 6e13c6d14SVinod Koul 705006290SFelipe Balbi#include <dt-bindings/dma/qcom-gpi.h> 8e13c6d14SVinod Koul#include <dt-bindings/interrupt-controller/arm-gic.h> 9017e7856SSibi Sankar#include <dt-bindings/power/qcom-rpmpd.h> 10e13c6d14SVinod Koul#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11e13c6d14SVinod Koul#include <dt-bindings/clock/qcom,rpmh.h> 1298874a46SKonrad Dybcio#include <dt-bindings/clock/qcom,dispcc-sm8150.h> 13d6f55763SVinod Koul#include <dt-bindings/clock/qcom,gcc-sm8150.h> 14f1269916SJonathan Marek#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 15a6d435c1SSibi Sankar#include <dt-bindings/interconnect/qcom,osm-l3.h> 162b6187abSThara Gopinath#include <dt-bindings/interconnect/qcom,sm8150.h> 17d2fa630cSAmit Kucheria#include <dt-bindings/thermal/thermal.h> 18e13c6d14SVinod Koul 19e13c6d14SVinod Koul/ { 20e13c6d14SVinod Koul interrupt-parent = <&intc>; 21e13c6d14SVinod Koul 22e13c6d14SVinod Koul #address-cells = <2>; 23e13c6d14SVinod Koul #size-cells = <2>; 24e13c6d14SVinod Koul 25e13c6d14SVinod Koul chosen { }; 26e13c6d14SVinod Koul 27e13c6d14SVinod Koul clocks { 28e13c6d14SVinod Koul xo_board: xo-board { 29e13c6d14SVinod Koul compatible = "fixed-clock"; 30e13c6d14SVinod Koul #clock-cells = <0>; 31e13c6d14SVinod Koul clock-frequency = <38400000>; 32e13c6d14SVinod Koul clock-output-names = "xo_board"; 33e13c6d14SVinod Koul }; 34e13c6d14SVinod Koul 35e13c6d14SVinod Koul sleep_clk: sleep-clk { 36e13c6d14SVinod Koul compatible = "fixed-clock"; 37e13c6d14SVinod Koul #clock-cells = <0>; 38e13c6d14SVinod Koul clock-frequency = <32764>; 39e13c6d14SVinod Koul clock-output-names = "sleep_clk"; 40e13c6d14SVinod Koul }; 41e13c6d14SVinod Koul }; 42e13c6d14SVinod Koul 43e13c6d14SVinod Koul cpus { 44e13c6d14SVinod Koul #address-cells = <2>; 45e13c6d14SVinod Koul #size-cells = <0>; 46e13c6d14SVinod Koul 47e13c6d14SVinod Koul CPU0: cpu@0 { 48e13c6d14SVinod Koul device_type = "cpu"; 49e13c6d14SVinod Koul compatible = "qcom,kryo485"; 50e13c6d14SVinod Koul reg = <0x0 0x0>; 51fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 52e13c6d14SVinod Koul enable-method = "psci"; 535b2dae72SDanny Lin capacity-dmips-mhz = <488>; 545b2dae72SDanny Lin dynamic-power-coefficient = <232>; 55e13c6d14SVinod Koul next-level-cache = <&L2_0>; 56fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 572b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 582b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 592b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 60b2e3f897SDanny Lin power-domains = <&CPU_PD0>; 61b2e3f897SDanny Lin power-domain-names = "psci"; 62d2fa630cSAmit Kucheria #cooling-cells = <2>; 63e13c6d14SVinod Koul L2_0: l2-cache { 64e13c6d14SVinod Koul compatible = "cache"; 659435294cSPierre Gondois cache-level = <2>; 66e13c6d14SVinod Koul next-level-cache = <&L3_0>; 67e13c6d14SVinod Koul L3_0: l3-cache { 68e13c6d14SVinod Koul compatible = "cache"; 699435294cSPierre Gondois cache-level = <3>; 70e13c6d14SVinod Koul }; 71e13c6d14SVinod Koul }; 72e13c6d14SVinod Koul }; 73e13c6d14SVinod Koul 74e13c6d14SVinod Koul CPU1: cpu@100 { 75e13c6d14SVinod Koul device_type = "cpu"; 76e13c6d14SVinod Koul compatible = "qcom,kryo485"; 77e13c6d14SVinod Koul reg = <0x0 0x100>; 78fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 79e13c6d14SVinod Koul enable-method = "psci"; 805b2dae72SDanny Lin capacity-dmips-mhz = <488>; 815b2dae72SDanny Lin dynamic-power-coefficient = <232>; 82e13c6d14SVinod Koul next-level-cache = <&L2_100>; 83fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 842b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 852b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 862b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 87b2e3f897SDanny Lin power-domains = <&CPU_PD1>; 88b2e3f897SDanny Lin power-domain-names = "psci"; 89d2fa630cSAmit Kucheria #cooling-cells = <2>; 90e13c6d14SVinod Koul L2_100: l2-cache { 91e13c6d14SVinod Koul compatible = "cache"; 929435294cSPierre Gondois cache-level = <2>; 93e13c6d14SVinod Koul next-level-cache = <&L3_0>; 94e13c6d14SVinod Koul }; 95e13c6d14SVinod Koul }; 96e13c6d14SVinod Koul 97e13c6d14SVinod Koul CPU2: cpu@200 { 98e13c6d14SVinod Koul device_type = "cpu"; 99e13c6d14SVinod Koul compatible = "qcom,kryo485"; 100e13c6d14SVinod Koul reg = <0x0 0x200>; 101fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 102e13c6d14SVinod Koul enable-method = "psci"; 1035b2dae72SDanny Lin capacity-dmips-mhz = <488>; 1045b2dae72SDanny Lin dynamic-power-coefficient = <232>; 105e13c6d14SVinod Koul next-level-cache = <&L2_200>; 106fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1072b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1082b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1092b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 110b2e3f897SDanny Lin power-domains = <&CPU_PD2>; 111b2e3f897SDanny Lin power-domain-names = "psci"; 112d2fa630cSAmit Kucheria #cooling-cells = <2>; 113e13c6d14SVinod Koul L2_200: l2-cache { 114e13c6d14SVinod Koul compatible = "cache"; 1159435294cSPierre Gondois cache-level = <2>; 116e13c6d14SVinod Koul next-level-cache = <&L3_0>; 117e13c6d14SVinod Koul }; 118e13c6d14SVinod Koul }; 119e13c6d14SVinod Koul 120e13c6d14SVinod Koul CPU3: cpu@300 { 121e13c6d14SVinod Koul device_type = "cpu"; 122e13c6d14SVinod Koul compatible = "qcom,kryo485"; 123e13c6d14SVinod Koul reg = <0x0 0x300>; 124fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 125e13c6d14SVinod Koul enable-method = "psci"; 1265b2dae72SDanny Lin capacity-dmips-mhz = <488>; 1275b2dae72SDanny Lin dynamic-power-coefficient = <232>; 128e13c6d14SVinod Koul next-level-cache = <&L2_300>; 129fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1302b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1312b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1322b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 133b2e3f897SDanny Lin power-domains = <&CPU_PD3>; 134b2e3f897SDanny Lin power-domain-names = "psci"; 135d2fa630cSAmit Kucheria #cooling-cells = <2>; 136e13c6d14SVinod Koul L2_300: l2-cache { 137e13c6d14SVinod Koul compatible = "cache"; 1389435294cSPierre Gondois cache-level = <2>; 139e13c6d14SVinod Koul next-level-cache = <&L3_0>; 140e13c6d14SVinod Koul }; 141e13c6d14SVinod Koul }; 142e13c6d14SVinod Koul 143e13c6d14SVinod Koul CPU4: cpu@400 { 144e13c6d14SVinod Koul device_type = "cpu"; 145e13c6d14SVinod Koul compatible = "qcom,kryo485"; 146e13c6d14SVinod Koul reg = <0x0 0x400>; 147fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 1>; 148e13c6d14SVinod Koul enable-method = "psci"; 1495b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1505b2dae72SDanny Lin dynamic-power-coefficient = <369>; 151e13c6d14SVinod Koul next-level-cache = <&L2_400>; 152fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1532b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1542b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1552b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 156b2e3f897SDanny Lin power-domains = <&CPU_PD4>; 157b2e3f897SDanny Lin power-domain-names = "psci"; 158d2fa630cSAmit Kucheria #cooling-cells = <2>; 159e13c6d14SVinod Koul L2_400: l2-cache { 160e13c6d14SVinod Koul compatible = "cache"; 1619435294cSPierre Gondois cache-level = <2>; 162e13c6d14SVinod Koul next-level-cache = <&L3_0>; 163e13c6d14SVinod Koul }; 164e13c6d14SVinod Koul }; 165e13c6d14SVinod Koul 166e13c6d14SVinod Koul CPU5: cpu@500 { 167e13c6d14SVinod Koul device_type = "cpu"; 168e13c6d14SVinod Koul compatible = "qcom,kryo485"; 169e13c6d14SVinod Koul reg = <0x0 0x500>; 170fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 1>; 171e13c6d14SVinod Koul enable-method = "psci"; 1725b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1735b2dae72SDanny Lin dynamic-power-coefficient = <369>; 174e13c6d14SVinod Koul next-level-cache = <&L2_500>; 175fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1762b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1772b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1782b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 179b2e3f897SDanny Lin power-domains = <&CPU_PD5>; 180b2e3f897SDanny Lin power-domain-names = "psci"; 181d2fa630cSAmit Kucheria #cooling-cells = <2>; 182e13c6d14SVinod Koul L2_500: l2-cache { 183e13c6d14SVinod Koul compatible = "cache"; 1849435294cSPierre Gondois cache-level = <2>; 185e13c6d14SVinod Koul next-level-cache = <&L3_0>; 186e13c6d14SVinod Koul }; 187e13c6d14SVinod Koul }; 188e13c6d14SVinod Koul 189e13c6d14SVinod Koul CPU6: cpu@600 { 190e13c6d14SVinod Koul device_type = "cpu"; 191e13c6d14SVinod Koul compatible = "qcom,kryo485"; 192e13c6d14SVinod Koul reg = <0x0 0x600>; 193fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 1>; 194e13c6d14SVinod Koul enable-method = "psci"; 1955b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1965b2dae72SDanny Lin dynamic-power-coefficient = <369>; 197e13c6d14SVinod Koul next-level-cache = <&L2_600>; 198fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1992b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 2002b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 2012b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 202b2e3f897SDanny Lin power-domains = <&CPU_PD6>; 203b2e3f897SDanny Lin power-domain-names = "psci"; 204d2fa630cSAmit Kucheria #cooling-cells = <2>; 205e13c6d14SVinod Koul L2_600: l2-cache { 206e13c6d14SVinod Koul compatible = "cache"; 2079435294cSPierre Gondois cache-level = <2>; 208e13c6d14SVinod Koul next-level-cache = <&L3_0>; 209e13c6d14SVinod Koul }; 210e13c6d14SVinod Koul }; 211e13c6d14SVinod Koul 212e13c6d14SVinod Koul CPU7: cpu@700 { 213e13c6d14SVinod Koul device_type = "cpu"; 214e13c6d14SVinod Koul compatible = "qcom,kryo485"; 215e13c6d14SVinod Koul reg = <0x0 0x700>; 216fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 2>; 217e13c6d14SVinod Koul enable-method = "psci"; 2185b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 2195b2dae72SDanny Lin dynamic-power-coefficient = <421>; 220e13c6d14SVinod Koul next-level-cache = <&L2_700>; 221fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 2>; 2222b6187abSThara Gopinath operating-points-v2 = <&cpu7_opp_table>; 2232b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 2242b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 225b2e3f897SDanny Lin power-domains = <&CPU_PD7>; 226b2e3f897SDanny Lin power-domain-names = "psci"; 227d2fa630cSAmit Kucheria #cooling-cells = <2>; 228e13c6d14SVinod Koul L2_700: l2-cache { 229e13c6d14SVinod Koul compatible = "cache"; 2309435294cSPierre Gondois cache-level = <2>; 231e13c6d14SVinod Koul next-level-cache = <&L3_0>; 232e13c6d14SVinod Koul }; 233e13c6d14SVinod Koul }; 234066d21bcSDanny Lin 235066d21bcSDanny Lin cpu-map { 236066d21bcSDanny Lin cluster0 { 237066d21bcSDanny Lin core0 { 238066d21bcSDanny Lin cpu = <&CPU0>; 239066d21bcSDanny Lin }; 240066d21bcSDanny Lin 241066d21bcSDanny Lin core1 { 242066d21bcSDanny Lin cpu = <&CPU1>; 243066d21bcSDanny Lin }; 244066d21bcSDanny Lin 245066d21bcSDanny Lin core2 { 246066d21bcSDanny Lin cpu = <&CPU2>; 247066d21bcSDanny Lin }; 248066d21bcSDanny Lin 249066d21bcSDanny Lin core3 { 250066d21bcSDanny Lin cpu = <&CPU3>; 251066d21bcSDanny Lin }; 252066d21bcSDanny Lin 253066d21bcSDanny Lin core4 { 254066d21bcSDanny Lin cpu = <&CPU4>; 255066d21bcSDanny Lin }; 256066d21bcSDanny Lin 257066d21bcSDanny Lin core5 { 258066d21bcSDanny Lin cpu = <&CPU5>; 259066d21bcSDanny Lin }; 260066d21bcSDanny Lin 261066d21bcSDanny Lin core6 { 262066d21bcSDanny Lin cpu = <&CPU6>; 263066d21bcSDanny Lin }; 264066d21bcSDanny Lin 265066d21bcSDanny Lin core7 { 266066d21bcSDanny Lin cpu = <&CPU7>; 267066d21bcSDanny Lin }; 268066d21bcSDanny Lin }; 269066d21bcSDanny Lin }; 27081188f58SDanny Lin 27181188f58SDanny Lin idle-states { 27281188f58SDanny Lin entry-method = "psci"; 27381188f58SDanny Lin 27481188f58SDanny Lin LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 27581188f58SDanny Lin compatible = "arm,idle-state"; 27681188f58SDanny Lin idle-state-name = "little-rail-power-collapse"; 27781188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 27881188f58SDanny Lin entry-latency-us = <355>; 27981188f58SDanny Lin exit-latency-us = <909>; 28081188f58SDanny Lin min-residency-us = <3934>; 28181188f58SDanny Lin local-timer-stop; 28281188f58SDanny Lin }; 28381188f58SDanny Lin 28481188f58SDanny Lin BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 28581188f58SDanny Lin compatible = "arm,idle-state"; 28681188f58SDanny Lin idle-state-name = "big-rail-power-collapse"; 28781188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 28881188f58SDanny Lin entry-latency-us = <241>; 28981188f58SDanny Lin exit-latency-us = <1461>; 29081188f58SDanny Lin min-residency-us = <4488>; 29181188f58SDanny Lin local-timer-stop; 29281188f58SDanny Lin }; 293b2e3f897SDanny Lin }; 29481188f58SDanny Lin 295b2e3f897SDanny Lin domain-idle-states { 29681188f58SDanny Lin CLUSTER_SLEEP_0: cluster-sleep-0 { 297b2e3f897SDanny Lin compatible = "domain-idle-state"; 29881188f58SDanny Lin idle-state-name = "cluster-power-collapse"; 299b2e3f897SDanny Lin arm,psci-suspend-param = <0x4100c244>; 30081188f58SDanny Lin entry-latency-us = <3263>; 30181188f58SDanny Lin exit-latency-us = <6562>; 30281188f58SDanny Lin min-residency-us = <9987>; 30381188f58SDanny Lin local-timer-stop; 30481188f58SDanny Lin }; 30581188f58SDanny Lin }; 306e13c6d14SVinod Koul }; 307e13c6d14SVinod Koul 3080e3e6546SKrzysztof Kozlowski cpu0_opp_table: opp-table-cpu0 { 3092b6187abSThara Gopinath compatible = "operating-points-v2"; 3102b6187abSThara Gopinath opp-shared; 3112b6187abSThara Gopinath 3122b6187abSThara Gopinath cpu0_opp1: opp-300000000 { 3132b6187abSThara Gopinath opp-hz = /bits/ 64 <300000000>; 3142b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 3152b6187abSThara Gopinath }; 3162b6187abSThara Gopinath 3172b6187abSThara Gopinath cpu0_opp2: opp-403200000 { 3182b6187abSThara Gopinath opp-hz = /bits/ 64 <403200000>; 3192b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 3202b6187abSThara Gopinath }; 3212b6187abSThara Gopinath 3222b6187abSThara Gopinath cpu0_opp3: opp-499200000 { 3232b6187abSThara Gopinath opp-hz = /bits/ 64 <499200000>; 3242b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3252b6187abSThara Gopinath }; 3262b6187abSThara Gopinath 3272b6187abSThara Gopinath cpu0_opp4: opp-576000000 { 3282b6187abSThara Gopinath opp-hz = /bits/ 64 <576000000>; 3292b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3302b6187abSThara Gopinath }; 3312b6187abSThara Gopinath 3322b6187abSThara Gopinath cpu0_opp5: opp-672000000 { 3332b6187abSThara Gopinath opp-hz = /bits/ 64 <672000000>; 3342b6187abSThara Gopinath opp-peak-kBps = <800000 15974400>; 3352b6187abSThara Gopinath }; 3362b6187abSThara Gopinath 3372b6187abSThara Gopinath cpu0_opp6: opp-768000000 { 338ce3b50cfSThara Gopinath opp-hz = /bits/ 64 <768000000>; 3392b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3402b6187abSThara Gopinath }; 3412b6187abSThara Gopinath 3422b6187abSThara Gopinath cpu0_opp7: opp-844800000 { 3432b6187abSThara Gopinath opp-hz = /bits/ 64 <844800000>; 3442b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3452b6187abSThara Gopinath }; 3462b6187abSThara Gopinath 3472b6187abSThara Gopinath cpu0_opp8: opp-940800000 { 3482b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 3492b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3502b6187abSThara Gopinath }; 3512b6187abSThara Gopinath 3522b6187abSThara Gopinath cpu0_opp9: opp-1036800000 { 3532b6187abSThara Gopinath opp-hz = /bits/ 64 <1036800000>; 3542b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3552b6187abSThara Gopinath }; 3562b6187abSThara Gopinath 3572b6187abSThara Gopinath cpu0_opp10: opp-1113600000 { 3582b6187abSThara Gopinath opp-hz = /bits/ 64 <1113600000>; 3592b6187abSThara Gopinath opp-peak-kBps = <2188000 25804800>; 3602b6187abSThara Gopinath }; 3612b6187abSThara Gopinath 3622b6187abSThara Gopinath cpu0_opp11: opp-1209600000 { 3632b6187abSThara Gopinath opp-hz = /bits/ 64 <1209600000>; 3642b6187abSThara Gopinath opp-peak-kBps = <2188000 31948800>; 3652b6187abSThara Gopinath }; 3662b6187abSThara Gopinath 3672b6187abSThara Gopinath cpu0_opp12: opp-1305600000 { 3682b6187abSThara Gopinath opp-hz = /bits/ 64 <1305600000>; 3692b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3702b6187abSThara Gopinath }; 3712b6187abSThara Gopinath 3722b6187abSThara Gopinath cpu0_opp13: opp-1382400000 { 3732b6187abSThara Gopinath opp-hz = /bits/ 64 <1382400000>; 3742b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3752b6187abSThara Gopinath }; 3762b6187abSThara Gopinath 3772b6187abSThara Gopinath cpu0_opp14: opp-1478400000 { 3782b6187abSThara Gopinath opp-hz = /bits/ 64 <1478400000>; 3792b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3802b6187abSThara Gopinath }; 3812b6187abSThara Gopinath 3822b6187abSThara Gopinath cpu0_opp15: opp-1555200000 { 3832b6187abSThara Gopinath opp-hz = /bits/ 64 <1555200000>; 3842b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3852b6187abSThara Gopinath }; 3862b6187abSThara Gopinath 3872b6187abSThara Gopinath cpu0_opp16: opp-1632000000 { 3882b6187abSThara Gopinath opp-hz = /bits/ 64 <1632000000>; 3892b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3902b6187abSThara Gopinath }; 3912b6187abSThara Gopinath 3922b6187abSThara Gopinath cpu0_opp17: opp-1708800000 { 3932b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 3942b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 3952b6187abSThara Gopinath }; 3962b6187abSThara Gopinath 3972b6187abSThara Gopinath cpu0_opp18: opp-1785600000 { 3982b6187abSThara Gopinath opp-hz = /bits/ 64 <1785600000>; 3992b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 4002b6187abSThara Gopinath }; 4012b6187abSThara Gopinath }; 4022b6187abSThara Gopinath 4030e3e6546SKrzysztof Kozlowski cpu4_opp_table: opp-table-cpu4 { 4042b6187abSThara Gopinath compatible = "operating-points-v2"; 4052b6187abSThara Gopinath opp-shared; 4062b6187abSThara Gopinath 4072b6187abSThara Gopinath cpu4_opp1: opp-710400000 { 4082b6187abSThara Gopinath opp-hz = /bits/ 64 <710400000>; 4092b6187abSThara Gopinath opp-peak-kBps = <1804000 15974400>; 4102b6187abSThara Gopinath }; 4112b6187abSThara Gopinath 4122b6187abSThara Gopinath cpu4_opp2: opp-825600000 { 4132b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 4142b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 4152b6187abSThara Gopinath }; 4162b6187abSThara Gopinath 4172b6187abSThara Gopinath cpu4_opp3: opp-940800000 { 4182b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 4192b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 4202b6187abSThara Gopinath }; 4212b6187abSThara Gopinath 4222b6187abSThara Gopinath cpu4_opp4: opp-1056000000 { 4232b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 4242b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 4252b6187abSThara Gopinath }; 4262b6187abSThara Gopinath 4272b6187abSThara Gopinath cpu4_opp5: opp-1171200000 { 4282b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 4292b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 4302b6187abSThara Gopinath }; 4312b6187abSThara Gopinath 4322b6187abSThara Gopinath cpu4_opp6: opp-1286400000 { 4332b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 4342b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4352b6187abSThara Gopinath }; 4362b6187abSThara Gopinath 4372b6187abSThara Gopinath cpu4_opp7: opp-1401600000 { 4382b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 4392b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4402b6187abSThara Gopinath }; 4412b6187abSThara Gopinath 4422b6187abSThara Gopinath cpu4_opp8: opp-1497600000 { 4432b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 4442b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4452b6187abSThara Gopinath }; 4462b6187abSThara Gopinath 4472b6187abSThara Gopinath cpu4_opp9: opp-1612800000 { 4482b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 4492b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4502b6187abSThara Gopinath }; 4512b6187abSThara Gopinath 4522b6187abSThara Gopinath cpu4_opp10: opp-1708800000 { 4532b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 4542b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 4552b6187abSThara Gopinath }; 4562b6187abSThara Gopinath 4572b6187abSThara Gopinath cpu4_opp11: opp-1804800000 { 4582b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 4592b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 4602b6187abSThara Gopinath }; 4612b6187abSThara Gopinath 4622b6187abSThara Gopinath cpu4_opp12: opp-1920000000 { 4632b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 4642b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 4652b6187abSThara Gopinath }; 4662b6187abSThara Gopinath 4672b6187abSThara Gopinath cpu4_opp13: opp-2016000000 { 4682b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 4692b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 4702b6187abSThara Gopinath }; 4712b6187abSThara Gopinath 4722b6187abSThara Gopinath cpu4_opp14: opp-2131200000 { 4732b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 4742b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 4752b6187abSThara Gopinath }; 4762b6187abSThara Gopinath 4772b6187abSThara Gopinath cpu4_opp15: opp-2227200000 { 4782b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 4792b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4802b6187abSThara Gopinath }; 4812b6187abSThara Gopinath 4822b6187abSThara Gopinath cpu4_opp16: opp-2323200000 { 4832b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 4842b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4852b6187abSThara Gopinath }; 4862b6187abSThara Gopinath 4872b6187abSThara Gopinath cpu4_opp17: opp-2419200000 { 4882b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 4892b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4902b6187abSThara Gopinath }; 4912b6187abSThara Gopinath }; 4922b6187abSThara Gopinath 4930e3e6546SKrzysztof Kozlowski cpu7_opp_table: opp-table-cpu7 { 4942b6187abSThara Gopinath compatible = "operating-points-v2"; 4952b6187abSThara Gopinath opp-shared; 4962b6187abSThara Gopinath 4972b6187abSThara Gopinath cpu7_opp1: opp-825600000 { 4982b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 4992b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 5002b6187abSThara Gopinath }; 5012b6187abSThara Gopinath 5022b6187abSThara Gopinath cpu7_opp2: opp-940800000 { 5032b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 5042b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 5052b6187abSThara Gopinath }; 5062b6187abSThara Gopinath 5072b6187abSThara Gopinath cpu7_opp3: opp-1056000000 { 5082b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 5092b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 5102b6187abSThara Gopinath }; 5112b6187abSThara Gopinath 5122b6187abSThara Gopinath cpu7_opp4: opp-1171200000 { 5132b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 5142b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 5152b6187abSThara Gopinath }; 5162b6187abSThara Gopinath 5172b6187abSThara Gopinath cpu7_opp5: opp-1286400000 { 5182b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 5192b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5202b6187abSThara Gopinath }; 5212b6187abSThara Gopinath 5222b6187abSThara Gopinath cpu7_opp6: opp-1401600000 { 5232b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 5242b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5252b6187abSThara Gopinath }; 5262b6187abSThara Gopinath 5272b6187abSThara Gopinath cpu7_opp7: opp-1497600000 { 5282b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 5292b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5302b6187abSThara Gopinath }; 5312b6187abSThara Gopinath 5322b6187abSThara Gopinath cpu7_opp8: opp-1612800000 { 5332b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 5342b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5352b6187abSThara Gopinath }; 5362b6187abSThara Gopinath 5372b6187abSThara Gopinath cpu7_opp9: opp-1708800000 { 5382b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 5392b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 5402b6187abSThara Gopinath }; 5412b6187abSThara Gopinath 5422b6187abSThara Gopinath cpu7_opp10: opp-1804800000 { 5432b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 5442b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 5452b6187abSThara Gopinath }; 5462b6187abSThara Gopinath 5472b6187abSThara Gopinath cpu7_opp11: opp-1920000000 { 5482b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 5492b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 5502b6187abSThara Gopinath }; 5512b6187abSThara Gopinath 5522b6187abSThara Gopinath cpu7_opp12: opp-2016000000 { 5532b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 5542b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 5552b6187abSThara Gopinath }; 5562b6187abSThara Gopinath 5572b6187abSThara Gopinath cpu7_opp13: opp-2131200000 { 5582b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 5592b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 5602b6187abSThara Gopinath }; 5612b6187abSThara Gopinath 5622b6187abSThara Gopinath cpu7_opp14: opp-2227200000 { 5632b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 5642b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5652b6187abSThara Gopinath }; 5662b6187abSThara Gopinath 5672b6187abSThara Gopinath cpu7_opp15: opp-2323200000 { 5682b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 5692b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5702b6187abSThara Gopinath }; 5712b6187abSThara Gopinath 5722b6187abSThara Gopinath cpu7_opp16: opp-2419200000 { 5732b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 5742b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5752b6187abSThara Gopinath }; 5762b6187abSThara Gopinath 5772b6187abSThara Gopinath cpu7_opp17: opp-2534400000 { 5782b6187abSThara Gopinath opp-hz = /bits/ 64 <2534400000>; 5792b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5802b6187abSThara Gopinath }; 5812b6187abSThara Gopinath 5822b6187abSThara Gopinath cpu7_opp18: opp-2649600000 { 5832b6187abSThara Gopinath opp-hz = /bits/ 64 <2649600000>; 5842b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5852b6187abSThara Gopinath }; 5862b6187abSThara Gopinath 5872b6187abSThara Gopinath cpu7_opp19: opp-2745600000 { 5882b6187abSThara Gopinath opp-hz = /bits/ 64 <2745600000>; 5892b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5902b6187abSThara Gopinath }; 5912b6187abSThara Gopinath 5922b6187abSThara Gopinath cpu7_opp20: opp-2841600000 { 5932b6187abSThara Gopinath opp-hz = /bits/ 64 <2841600000>; 5942b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5952b6187abSThara Gopinath }; 5962b6187abSThara Gopinath }; 5972b6187abSThara Gopinath 598e13c6d14SVinod Koul firmware { 599e13c6d14SVinod Koul scm: scm { 600e13c6d14SVinod Koul compatible = "qcom,scm-sm8150", "qcom,scm"; 601e13c6d14SVinod Koul #reset-cells = <1>; 602e13c6d14SVinod Koul }; 603e13c6d14SVinod Koul }; 604e13c6d14SVinod Koul 605e13c6d14SVinod Koul memory@80000000 { 606e13c6d14SVinod Koul device_type = "memory"; 607e13c6d14SVinod Koul /* We expect the bootloader to fill in the size */ 608e13c6d14SVinod Koul reg = <0x0 0x80000000 0x0 0x0>; 609e13c6d14SVinod Koul }; 610e13c6d14SVinod Koul 611d8cf9372SVinod Koul pmu { 612d8cf9372SVinod Koul compatible = "arm,armv8-pmuv3"; 613d8cf9372SVinod Koul interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 614d8cf9372SVinod Koul }; 615d8cf9372SVinod Koul 616e13c6d14SVinod Koul psci { 617e13c6d14SVinod Koul compatible = "arm,psci-1.0"; 618e13c6d14SVinod Koul method = "smc"; 619b2e3f897SDanny Lin 6205ca45690SKrzysztof Kozlowski CPU_PD0: power-domain-cpu0 { 621b2e3f897SDanny Lin #power-domain-cells = <0>; 622b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 623b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 624b2e3f897SDanny Lin }; 625b2e3f897SDanny Lin 6265ca45690SKrzysztof Kozlowski CPU_PD1: power-domain-cpu1 { 627b2e3f897SDanny Lin #power-domain-cells = <0>; 628b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 629b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 630b2e3f897SDanny Lin }; 631b2e3f897SDanny Lin 6325ca45690SKrzysztof Kozlowski CPU_PD2: power-domain-cpu2 { 633b2e3f897SDanny Lin #power-domain-cells = <0>; 634b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 635b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 636b2e3f897SDanny Lin }; 637b2e3f897SDanny Lin 6385ca45690SKrzysztof Kozlowski CPU_PD3: power-domain-cpu3 { 639b2e3f897SDanny Lin #power-domain-cells = <0>; 640b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 641b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 642b2e3f897SDanny Lin }; 643b2e3f897SDanny Lin 6445ca45690SKrzysztof Kozlowski CPU_PD4: power-domain-cpu4 { 645b2e3f897SDanny Lin #power-domain-cells = <0>; 646b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 647b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 648b2e3f897SDanny Lin }; 649b2e3f897SDanny Lin 6505ca45690SKrzysztof Kozlowski CPU_PD5: power-domain-cpu5 { 651b2e3f897SDanny Lin #power-domain-cells = <0>; 652b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 653b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 654b2e3f897SDanny Lin }; 655b2e3f897SDanny Lin 6565ca45690SKrzysztof Kozlowski CPU_PD6: power-domain-cpu6 { 657b2e3f897SDanny Lin #power-domain-cells = <0>; 658b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 659b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 660b2e3f897SDanny Lin }; 661b2e3f897SDanny Lin 6625ca45690SKrzysztof Kozlowski CPU_PD7: power-domain-cpu7 { 663b2e3f897SDanny Lin #power-domain-cells = <0>; 664b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 665b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 666b2e3f897SDanny Lin }; 667b2e3f897SDanny Lin 6685ca45690SKrzysztof Kozlowski CLUSTER_PD: power-domain-cpu-cluster0 { 669b2e3f897SDanny Lin #power-domain-cells = <0>; 670b2e3f897SDanny Lin domain-idle-states = <&CLUSTER_SLEEP_0>; 671b2e3f897SDanny Lin }; 672e13c6d14SVinod Koul }; 673e13c6d14SVinod Koul 674912c373aSVinod Koul reserved-memory { 675912c373aSVinod Koul #address-cells = <2>; 676912c373aSVinod Koul #size-cells = <2>; 677912c373aSVinod Koul ranges; 678912c373aSVinod Koul 679912c373aSVinod Koul hyp_mem: memory@85700000 { 680912c373aSVinod Koul reg = <0x0 0x85700000 0x0 0x600000>; 681912c373aSVinod Koul no-map; 682912c373aSVinod Koul }; 683912c373aSVinod Koul 684912c373aSVinod Koul xbl_mem: memory@85d00000 { 685912c373aSVinod Koul reg = <0x0 0x85d00000 0x0 0x140000>; 686912c373aSVinod Koul no-map; 687912c373aSVinod Koul }; 688912c373aSVinod Koul 689912c373aSVinod Koul aop_mem: memory@85f00000 { 690912c373aSVinod Koul reg = <0x0 0x85f00000 0x0 0x20000>; 691912c373aSVinod Koul no-map; 692912c373aSVinod Koul }; 693912c373aSVinod Koul 694912c373aSVinod Koul aop_cmd_db: memory@85f20000 { 695912c373aSVinod Koul compatible = "qcom,cmd-db"; 696912c373aSVinod Koul reg = <0x0 0x85f20000 0x0 0x20000>; 697912c373aSVinod Koul no-map; 698912c373aSVinod Koul }; 699912c373aSVinod Koul 700912c373aSVinod Koul smem_mem: memory@86000000 { 701912c373aSVinod Koul reg = <0x0 0x86000000 0x0 0x200000>; 702912c373aSVinod Koul no-map; 703912c373aSVinod Koul }; 704912c373aSVinod Koul 705912c373aSVinod Koul tz_mem: memory@86200000 { 706912c373aSVinod Koul reg = <0x0 0x86200000 0x0 0x3900000>; 707912c373aSVinod Koul no-map; 708912c373aSVinod Koul }; 709912c373aSVinod Koul 710912c373aSVinod Koul rmtfs_mem: memory@89b00000 { 711912c373aSVinod Koul compatible = "qcom,rmtfs-mem"; 712912c373aSVinod Koul reg = <0x0 0x89b00000 0x0 0x200000>; 713912c373aSVinod Koul no-map; 714912c373aSVinod Koul 715912c373aSVinod Koul qcom,client-id = <1>; 716912c373aSVinod Koul qcom,vmid = <15>; 717912c373aSVinod Koul }; 718912c373aSVinod Koul 719912c373aSVinod Koul camera_mem: memory@8b700000 { 720912c373aSVinod Koul reg = <0x0 0x8b700000 0x0 0x500000>; 721912c373aSVinod Koul no-map; 722912c373aSVinod Koul }; 723912c373aSVinod Koul 724912c373aSVinod Koul wlan_mem: memory@8bc00000 { 725912c373aSVinod Koul reg = <0x0 0x8bc00000 0x0 0x180000>; 726912c373aSVinod Koul no-map; 727912c373aSVinod Koul }; 728912c373aSVinod Koul 729912c373aSVinod Koul npu_mem: memory@8bd80000 { 730912c373aSVinod Koul reg = <0x0 0x8bd80000 0x0 0x80000>; 731912c373aSVinod Koul no-map; 732912c373aSVinod Koul }; 733912c373aSVinod Koul 734912c373aSVinod Koul adsp_mem: memory@8be00000 { 735912c373aSVinod Koul reg = <0x0 0x8be00000 0x0 0x1a00000>; 736912c373aSVinod Koul no-map; 737912c373aSVinod Koul }; 738912c373aSVinod Koul 739912c373aSVinod Koul mpss_mem: memory@8d800000 { 740912c373aSVinod Koul reg = <0x0 0x8d800000 0x0 0x9600000>; 741912c373aSVinod Koul no-map; 742912c373aSVinod Koul }; 743912c373aSVinod Koul 744912c373aSVinod Koul venus_mem: memory@96e00000 { 745912c373aSVinod Koul reg = <0x0 0x96e00000 0x0 0x500000>; 746912c373aSVinod Koul no-map; 747912c373aSVinod Koul }; 748912c373aSVinod Koul 749912c373aSVinod Koul slpi_mem: memory@97300000 { 750912c373aSVinod Koul reg = <0x0 0x97300000 0x0 0x1400000>; 751912c373aSVinod Koul no-map; 752912c373aSVinod Koul }; 753912c373aSVinod Koul 754912c373aSVinod Koul ipa_fw_mem: memory@98700000 { 755912c373aSVinod Koul reg = <0x0 0x98700000 0x0 0x10000>; 756912c373aSVinod Koul no-map; 757912c373aSVinod Koul }; 758912c373aSVinod Koul 759912c373aSVinod Koul ipa_gsi_mem: memory@98710000 { 760912c373aSVinod Koul reg = <0x0 0x98710000 0x0 0x5000>; 761912c373aSVinod Koul no-map; 762912c373aSVinod Koul }; 763912c373aSVinod Koul 764912c373aSVinod Koul gpu_mem: memory@98715000 { 765912c373aSVinod Koul reg = <0x0 0x98715000 0x0 0x2000>; 766912c373aSVinod Koul no-map; 767912c373aSVinod Koul }; 768912c373aSVinod Koul 769912c373aSVinod Koul spss_mem: memory@98800000 { 770912c373aSVinod Koul reg = <0x0 0x98800000 0x0 0x100000>; 771912c373aSVinod Koul no-map; 772912c373aSVinod Koul }; 773912c373aSVinod Koul 774912c373aSVinod Koul cdsp_mem: memory@98900000 { 775912c373aSVinod Koul reg = <0x0 0x98900000 0x0 0x1400000>; 776912c373aSVinod Koul no-map; 777912c373aSVinod Koul }; 778912c373aSVinod Koul 779912c373aSVinod Koul qseecom_mem: memory@9e400000 { 780912c373aSVinod Koul reg = <0x0 0x9e400000 0x0 0x1400000>; 781912c373aSVinod Koul no-map; 782912c373aSVinod Koul }; 783912c373aSVinod Koul }; 784912c373aSVinod Koul 785d8cf9372SVinod Koul smem { 786d8cf9372SVinod Koul compatible = "qcom,smem"; 787d8cf9372SVinod Koul memory-region = <&smem_mem>; 788d8cf9372SVinod Koul hwlocks = <&tcsr_mutex 3>; 789d8cf9372SVinod Koul }; 790d8cf9372SVinod Koul 79161025b81SSibi Sankar smp2p-cdsp { 79261025b81SSibi Sankar compatible = "qcom,smp2p"; 79361025b81SSibi Sankar qcom,smem = <94>, <432>; 79461025b81SSibi Sankar 79561025b81SSibi Sankar interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 79661025b81SSibi Sankar 79761025b81SSibi Sankar mboxes = <&apss_shared 6>; 79861025b81SSibi Sankar 79961025b81SSibi Sankar qcom,local-pid = <0>; 80061025b81SSibi Sankar qcom,remote-pid = <5>; 80161025b81SSibi Sankar 80261025b81SSibi Sankar cdsp_smp2p_out: master-kernel { 80361025b81SSibi Sankar qcom,entry-name = "master-kernel"; 80461025b81SSibi Sankar #qcom,smem-state-cells = <1>; 80561025b81SSibi Sankar }; 80661025b81SSibi Sankar 80761025b81SSibi Sankar cdsp_smp2p_in: slave-kernel { 80861025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 80961025b81SSibi Sankar 81061025b81SSibi Sankar interrupt-controller; 81161025b81SSibi Sankar #interrupt-cells = <2>; 81261025b81SSibi Sankar }; 81361025b81SSibi Sankar }; 81461025b81SSibi Sankar 81561025b81SSibi Sankar smp2p-lpass { 81661025b81SSibi Sankar compatible = "qcom,smp2p"; 81761025b81SSibi Sankar qcom,smem = <443>, <429>; 81861025b81SSibi Sankar 81961025b81SSibi Sankar interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 82061025b81SSibi Sankar 82161025b81SSibi Sankar mboxes = <&apss_shared 10>; 82261025b81SSibi Sankar 82361025b81SSibi Sankar qcom,local-pid = <0>; 82461025b81SSibi Sankar qcom,remote-pid = <2>; 82561025b81SSibi Sankar 82661025b81SSibi Sankar adsp_smp2p_out: master-kernel { 82761025b81SSibi Sankar qcom,entry-name = "master-kernel"; 82861025b81SSibi Sankar #qcom,smem-state-cells = <1>; 82961025b81SSibi Sankar }; 83061025b81SSibi Sankar 83161025b81SSibi Sankar adsp_smp2p_in: slave-kernel { 83261025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 83361025b81SSibi Sankar 83461025b81SSibi Sankar interrupt-controller; 83561025b81SSibi Sankar #interrupt-cells = <2>; 83661025b81SSibi Sankar }; 83761025b81SSibi Sankar }; 83861025b81SSibi Sankar 83961025b81SSibi Sankar smp2p-mpss { 84061025b81SSibi Sankar compatible = "qcom,smp2p"; 84161025b81SSibi Sankar qcom,smem = <435>, <428>; 84261025b81SSibi Sankar 84361025b81SSibi Sankar interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 84461025b81SSibi Sankar 84561025b81SSibi Sankar mboxes = <&apss_shared 14>; 84661025b81SSibi Sankar 84761025b81SSibi Sankar qcom,local-pid = <0>; 84861025b81SSibi Sankar qcom,remote-pid = <1>; 84961025b81SSibi Sankar 85061025b81SSibi Sankar modem_smp2p_out: master-kernel { 85161025b81SSibi Sankar qcom,entry-name = "master-kernel"; 85261025b81SSibi Sankar #qcom,smem-state-cells = <1>; 85361025b81SSibi Sankar }; 85461025b81SSibi Sankar 85561025b81SSibi Sankar modem_smp2p_in: slave-kernel { 85661025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 85761025b81SSibi Sankar 85861025b81SSibi Sankar interrupt-controller; 85961025b81SSibi Sankar #interrupt-cells = <2>; 86061025b81SSibi Sankar }; 86161025b81SSibi Sankar }; 86261025b81SSibi Sankar 86361025b81SSibi Sankar smp2p-slpi { 86461025b81SSibi Sankar compatible = "qcom,smp2p"; 86561025b81SSibi Sankar qcom,smem = <481>, <430>; 86661025b81SSibi Sankar 86761025b81SSibi Sankar interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 86861025b81SSibi Sankar 86961025b81SSibi Sankar mboxes = <&apss_shared 26>; 87061025b81SSibi Sankar 87161025b81SSibi Sankar qcom,local-pid = <0>; 87261025b81SSibi Sankar qcom,remote-pid = <3>; 87361025b81SSibi Sankar 87461025b81SSibi Sankar slpi_smp2p_out: master-kernel { 87561025b81SSibi Sankar qcom,entry-name = "master-kernel"; 87661025b81SSibi Sankar #qcom,smem-state-cells = <1>; 87761025b81SSibi Sankar }; 87861025b81SSibi Sankar 87961025b81SSibi Sankar slpi_smp2p_in: slave-kernel { 88061025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 88161025b81SSibi Sankar 88261025b81SSibi Sankar interrupt-controller; 88361025b81SSibi Sankar #interrupt-cells = <2>; 88461025b81SSibi Sankar }; 88561025b81SSibi Sankar }; 88661025b81SSibi Sankar 887e13c6d14SVinod Koul soc: soc@0 { 888e13c6d14SVinod Koul #address-cells = <2>; 889e13c6d14SVinod Koul #size-cells = <2>; 890e13c6d14SVinod Koul ranges = <0 0 0 0 0x10 0>; 891e13c6d14SVinod Koul dma-ranges = <0 0 0 0 0x10 0>; 892e13c6d14SVinod Koul compatible = "simple-bus"; 893e13c6d14SVinod Koul 894e13c6d14SVinod Koul gcc: clock-controller@100000 { 895e13c6d14SVinod Koul compatible = "qcom,gcc-sm8150"; 896e13c6d14SVinod Koul reg = <0x0 0x00100000 0x0 0x1f0000>; 897e13c6d14SVinod Koul #clock-cells = <1>; 898e13c6d14SVinod Koul #reset-cells = <1>; 899e13c6d14SVinod Koul #power-domain-cells = <1>; 900e13c6d14SVinod Koul clock-names = "bi_tcxo", 901e13c6d14SVinod Koul "sleep_clk"; 902e13c6d14SVinod Koul clocks = <&rpmhcc RPMH_CXO_CLK>, 903e13c6d14SVinod Koul <&sleep_clk>; 904e13c6d14SVinod Koul }; 905e13c6d14SVinod Koul 90605006290SFelipe Balbi gpi_dma0: dma-controller@800000 { 907e7e24786SRichard Acayan compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 908f6973229SKonrad Dybcio reg = <0 0x00800000 0 0x60000>; 90905006290SFelipe Balbi interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 91005006290SFelipe Balbi <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 91105006290SFelipe Balbi <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 91205006290SFelipe Balbi <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 91305006290SFelipe Balbi <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 91405006290SFelipe Balbi <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 91505006290SFelipe Balbi <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 91605006290SFelipe Balbi <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 91705006290SFelipe Balbi <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 91805006290SFelipe Balbi <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 91905006290SFelipe Balbi <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 92005006290SFelipe Balbi <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 92105006290SFelipe Balbi <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 92205006290SFelipe Balbi dma-channels = <13>; 92305006290SFelipe Balbi dma-channel-mask = <0xfa>; 92405006290SFelipe Balbi iommus = <&apps_smmu 0x00d6 0x0>; 92505006290SFelipe Balbi #dma-cells = <3>; 92605006290SFelipe Balbi status = "disabled"; 92705006290SFelipe Balbi }; 92805006290SFelipe Balbi 92905f333b7SVinod Koul ethernet: ethernet@20000 { 93005f333b7SVinod Koul compatible = "qcom,sm8150-ethqos"; 93105f333b7SVinod Koul reg = <0x0 0x00020000 0x0 0x10000>, 93205f333b7SVinod Koul <0x0 0x00036000 0x0 0x100>; 93305f333b7SVinod Koul reg-names = "stmmaceth", "rgmii"; 93405f333b7SVinod Koul clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 93505f333b7SVinod Koul clocks = <&gcc GCC_EMAC_AXI_CLK>, 93605f333b7SVinod Koul <&gcc GCC_EMAC_SLV_AHB_CLK>, 93705f333b7SVinod Koul <&gcc GCC_EMAC_PTP_CLK>, 93805f333b7SVinod Koul <&gcc GCC_EMAC_RGMII_CLK>; 93905f333b7SVinod Koul interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 94005f333b7SVinod Koul <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 94105f333b7SVinod Koul interrupt-names = "macirq", "eth_lpi"; 94205f333b7SVinod Koul 94305f333b7SVinod Koul power-domains = <&gcc EMAC_GDSC>; 94405f333b7SVinod Koul resets = <&gcc GCC_EMAC_BCR>; 94505f333b7SVinod Koul 94651f748c6SKonrad Dybcio iommus = <&apps_smmu 0x3c0 0x0>; 94705f333b7SVinod Koul 94805f333b7SVinod Koul snps,tso; 94905f333b7SVinod Koul rx-fifo-depth = <4096>; 95005f333b7SVinod Koul tx-fifo-depth = <4096>; 95105f333b7SVinod Koul 95205f333b7SVinod Koul status = "disabled"; 95305f333b7SVinod Koul }; 95405f333b7SVinod Koul 95505f333b7SVinod Koul 9569cf3ebd1SCaleb Connolly qupv3_id_0: geniqup@8c0000 { 9579cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 9589cf3ebd1SCaleb Connolly reg = <0x0 0x008c0000 0x0 0x6000>; 9599cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 9609cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 9619cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 9629cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0xc3 0x0>; 9639cf3ebd1SCaleb Connolly #address-cells = <2>; 9649cf3ebd1SCaleb Connolly #size-cells = <2>; 9659cf3ebd1SCaleb Connolly ranges; 9669cf3ebd1SCaleb Connolly status = "disabled"; 96781bee695SCaleb Connolly 96881bee695SCaleb Connolly i2c0: i2c@880000 { 96981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 97081bee695SCaleb Connolly reg = <0 0x00880000 0 0x4000>; 97181bee695SCaleb Connolly clock-names = "se"; 97281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 973abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 974abdd4b7aSFelipe Balbi <&gpi_dma0 1 0 QCOM_GPI_I2C>; 975abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 97681bee695SCaleb Connolly pinctrl-names = "default"; 97781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c0_default>; 97881bee695SCaleb Connolly interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 97981bee695SCaleb Connolly #address-cells = <1>; 98081bee695SCaleb Connolly #size-cells = <0>; 98181bee695SCaleb Connolly status = "disabled"; 98281bee695SCaleb Connolly }; 98381bee695SCaleb Connolly 984129e1c96SFelipe Balbi spi0: spi@880000 { 985129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 986f6973229SKonrad Dybcio reg = <0 0x00880000 0 0x4000>; 987129e1c96SFelipe Balbi reg-names = "se"; 988129e1c96SFelipe Balbi clock-names = "se"; 989129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 990abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 991abdd4b7aSFelipe Balbi <&gpi_dma0 1 0 QCOM_GPI_SPI>; 992abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 993129e1c96SFelipe Balbi pinctrl-names = "default"; 994129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi0_default>; 995129e1c96SFelipe Balbi interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 996129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 997129e1c96SFelipe Balbi #address-cells = <1>; 998129e1c96SFelipe Balbi #size-cells = <0>; 999129e1c96SFelipe Balbi status = "disabled"; 1000129e1c96SFelipe Balbi }; 1001129e1c96SFelipe Balbi 100281bee695SCaleb Connolly i2c1: i2c@884000 { 100381bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 100481bee695SCaleb Connolly reg = <0 0x00884000 0 0x4000>; 100581bee695SCaleb Connolly clock-names = "se"; 100681bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1007abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1008abdd4b7aSFelipe Balbi <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1009abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 101081bee695SCaleb Connolly pinctrl-names = "default"; 101181bee695SCaleb Connolly pinctrl-0 = <&qup_i2c1_default>; 101281bee695SCaleb Connolly interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 101381bee695SCaleb Connolly #address-cells = <1>; 101481bee695SCaleb Connolly #size-cells = <0>; 101581bee695SCaleb Connolly status = "disabled"; 101681bee695SCaleb Connolly }; 101781bee695SCaleb Connolly 1018129e1c96SFelipe Balbi spi1: spi@884000 { 1019129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1020f6973229SKonrad Dybcio reg = <0 0x00884000 0 0x4000>; 1021129e1c96SFelipe Balbi reg-names = "se"; 1022129e1c96SFelipe Balbi clock-names = "se"; 1023129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1024abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1025abdd4b7aSFelipe Balbi <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1026abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1027129e1c96SFelipe Balbi pinctrl-names = "default"; 1028129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi1_default>; 1029129e1c96SFelipe Balbi interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1030129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1031129e1c96SFelipe Balbi #address-cells = <1>; 1032129e1c96SFelipe Balbi #size-cells = <0>; 1033129e1c96SFelipe Balbi status = "disabled"; 1034129e1c96SFelipe Balbi }; 1035129e1c96SFelipe Balbi 103681bee695SCaleb Connolly i2c2: i2c@888000 { 103781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 103881bee695SCaleb Connolly reg = <0 0x00888000 0 0x4000>; 103981bee695SCaleb Connolly clock-names = "se"; 104081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1041abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1042abdd4b7aSFelipe Balbi <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1043abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 104481bee695SCaleb Connolly pinctrl-names = "default"; 104581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c2_default>; 104681bee695SCaleb Connolly interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 104781bee695SCaleb Connolly #address-cells = <1>; 104881bee695SCaleb Connolly #size-cells = <0>; 104981bee695SCaleb Connolly status = "disabled"; 105081bee695SCaleb Connolly }; 105181bee695SCaleb Connolly 1052129e1c96SFelipe Balbi spi2: spi@888000 { 1053129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1054f6973229SKonrad Dybcio reg = <0 0x00888000 0 0x4000>; 1055129e1c96SFelipe Balbi reg-names = "se"; 1056129e1c96SFelipe Balbi clock-names = "se"; 1057129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1058abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1059abdd4b7aSFelipe Balbi <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1060abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1061129e1c96SFelipe Balbi pinctrl-names = "default"; 1062129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi2_default>; 1063129e1c96SFelipe Balbi interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1064129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1065129e1c96SFelipe Balbi #address-cells = <1>; 1066129e1c96SFelipe Balbi #size-cells = <0>; 1067129e1c96SFelipe Balbi status = "disabled"; 1068129e1c96SFelipe Balbi }; 1069129e1c96SFelipe Balbi 107081bee695SCaleb Connolly i2c3: i2c@88c000 { 107181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 107281bee695SCaleb Connolly reg = <0 0x0088c000 0 0x4000>; 107381bee695SCaleb Connolly clock-names = "se"; 107481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1075abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1076abdd4b7aSFelipe Balbi <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1077abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 107881bee695SCaleb Connolly pinctrl-names = "default"; 107981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c3_default>; 108081bee695SCaleb Connolly interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 108181bee695SCaleb Connolly #address-cells = <1>; 108281bee695SCaleb Connolly #size-cells = <0>; 108381bee695SCaleb Connolly status = "disabled"; 108481bee695SCaleb Connolly }; 108581bee695SCaleb Connolly 1086129e1c96SFelipe Balbi spi3: spi@88c000 { 1087129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1088f6973229SKonrad Dybcio reg = <0 0x0088c000 0 0x4000>; 1089129e1c96SFelipe Balbi reg-names = "se"; 1090129e1c96SFelipe Balbi clock-names = "se"; 1091129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1092abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1093abdd4b7aSFelipe Balbi <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1094abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1095129e1c96SFelipe Balbi pinctrl-names = "default"; 1096129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi3_default>; 1097129e1c96SFelipe Balbi interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1098129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1099129e1c96SFelipe Balbi #address-cells = <1>; 1100129e1c96SFelipe Balbi #size-cells = <0>; 1101129e1c96SFelipe Balbi status = "disabled"; 1102129e1c96SFelipe Balbi }; 1103129e1c96SFelipe Balbi 110481bee695SCaleb Connolly i2c4: i2c@890000 { 110581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 110681bee695SCaleb Connolly reg = <0 0x00890000 0 0x4000>; 110781bee695SCaleb Connolly clock-names = "se"; 110881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1109abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1110abdd4b7aSFelipe Balbi <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1111abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 111281bee695SCaleb Connolly pinctrl-names = "default"; 111381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c4_default>; 111481bee695SCaleb Connolly interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 111581bee695SCaleb Connolly #address-cells = <1>; 111681bee695SCaleb Connolly #size-cells = <0>; 111781bee695SCaleb Connolly status = "disabled"; 111881bee695SCaleb Connolly }; 111981bee695SCaleb Connolly 1120129e1c96SFelipe Balbi spi4: spi@890000 { 1121129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1122f6973229SKonrad Dybcio reg = <0 0x00890000 0 0x4000>; 1123129e1c96SFelipe Balbi reg-names = "se"; 1124129e1c96SFelipe Balbi clock-names = "se"; 1125129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1126abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1127abdd4b7aSFelipe Balbi <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1128abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1129129e1c96SFelipe Balbi pinctrl-names = "default"; 1130129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi4_default>; 1131129e1c96SFelipe Balbi interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1132129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1133129e1c96SFelipe Balbi #address-cells = <1>; 1134129e1c96SFelipe Balbi #size-cells = <0>; 1135129e1c96SFelipe Balbi status = "disabled"; 1136129e1c96SFelipe Balbi }; 1137129e1c96SFelipe Balbi 113881bee695SCaleb Connolly i2c5: i2c@894000 { 113981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 114081bee695SCaleb Connolly reg = <0 0x00894000 0 0x4000>; 114181bee695SCaleb Connolly clock-names = "se"; 114281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1143abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1144abdd4b7aSFelipe Balbi <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1145abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 114681bee695SCaleb Connolly pinctrl-names = "default"; 114781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c5_default>; 114881bee695SCaleb Connolly interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 114981bee695SCaleb Connolly #address-cells = <1>; 115081bee695SCaleb Connolly #size-cells = <0>; 115181bee695SCaleb Connolly status = "disabled"; 115281bee695SCaleb Connolly }; 115381bee695SCaleb Connolly 1154129e1c96SFelipe Balbi spi5: spi@894000 { 1155129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1156f6973229SKonrad Dybcio reg = <0 0x00894000 0 0x4000>; 1157129e1c96SFelipe Balbi reg-names = "se"; 1158129e1c96SFelipe Balbi clock-names = "se"; 1159129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1160abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1161abdd4b7aSFelipe Balbi <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1162abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1163129e1c96SFelipe Balbi pinctrl-names = "default"; 1164129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi5_default>; 1165129e1c96SFelipe Balbi interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1166129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1167129e1c96SFelipe Balbi #address-cells = <1>; 1168129e1c96SFelipe Balbi #size-cells = <0>; 1169129e1c96SFelipe Balbi status = "disabled"; 1170129e1c96SFelipe Balbi }; 1171129e1c96SFelipe Balbi 117281bee695SCaleb Connolly i2c6: i2c@898000 { 117381bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 117481bee695SCaleb Connolly reg = <0 0x00898000 0 0x4000>; 117581bee695SCaleb Connolly clock-names = "se"; 117681bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1177abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1178abdd4b7aSFelipe Balbi <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1179abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 118081bee695SCaleb Connolly pinctrl-names = "default"; 118181bee695SCaleb Connolly pinctrl-0 = <&qup_i2c6_default>; 118281bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 118381bee695SCaleb Connolly #address-cells = <1>; 118481bee695SCaleb Connolly #size-cells = <0>; 118581bee695SCaleb Connolly status = "disabled"; 118681bee695SCaleb Connolly }; 118781bee695SCaleb Connolly 1188129e1c96SFelipe Balbi spi6: spi@898000 { 1189129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1190f6973229SKonrad Dybcio reg = <0 0x00898000 0 0x4000>; 1191129e1c96SFelipe Balbi reg-names = "se"; 1192129e1c96SFelipe Balbi clock-names = "se"; 1193129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1194abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1195abdd4b7aSFelipe Balbi <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1196abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1197129e1c96SFelipe Balbi pinctrl-names = "default"; 1198129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi6_default>; 1199129e1c96SFelipe Balbi interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1200129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1201129e1c96SFelipe Balbi #address-cells = <1>; 1202129e1c96SFelipe Balbi #size-cells = <0>; 1203129e1c96SFelipe Balbi status = "disabled"; 1204129e1c96SFelipe Balbi }; 1205129e1c96SFelipe Balbi 120681bee695SCaleb Connolly i2c7: i2c@89c000 { 120781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 120881bee695SCaleb Connolly reg = <0 0x0089c000 0 0x4000>; 120981bee695SCaleb Connolly clock-names = "se"; 121081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1211abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1212abdd4b7aSFelipe Balbi <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1213abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 121481bee695SCaleb Connolly pinctrl-names = "default"; 121581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c7_default>; 121681bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 121781bee695SCaleb Connolly #address-cells = <1>; 121881bee695SCaleb Connolly #size-cells = <0>; 121981bee695SCaleb Connolly status = "disabled"; 122081bee695SCaleb Connolly }; 122181bee695SCaleb Connolly 1222129e1c96SFelipe Balbi spi7: spi@89c000 { 1223129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1224f6973229SKonrad Dybcio reg = <0 0x0089c000 0 0x4000>; 1225129e1c96SFelipe Balbi reg-names = "se"; 1226129e1c96SFelipe Balbi clock-names = "se"; 1227129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1228abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1229abdd4b7aSFelipe Balbi <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1230abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1231129e1c96SFelipe Balbi pinctrl-names = "default"; 1232129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi7_default>; 1233129e1c96SFelipe Balbi interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1234129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1235129e1c96SFelipe Balbi #address-cells = <1>; 1236129e1c96SFelipe Balbi #size-cells = <0>; 1237129e1c96SFelipe Balbi status = "disabled"; 1238129e1c96SFelipe Balbi }; 12399cf3ebd1SCaleb Connolly }; 12409cf3ebd1SCaleb Connolly 124105006290SFelipe Balbi gpi_dma1: dma-controller@a00000 { 1242e7e24786SRichard Acayan compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1243f6973229SKonrad Dybcio reg = <0 0x00a00000 0 0x60000>; 124405006290SFelipe Balbi interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 124505006290SFelipe Balbi <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 124605006290SFelipe Balbi <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 124705006290SFelipe Balbi <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 124805006290SFelipe Balbi <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 124905006290SFelipe Balbi <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 125005006290SFelipe Balbi <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 125105006290SFelipe Balbi <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 125205006290SFelipe Balbi <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 125305006290SFelipe Balbi <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 125405006290SFelipe Balbi <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 125505006290SFelipe Balbi <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 125605006290SFelipe Balbi <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 125705006290SFelipe Balbi dma-channels = <13>; 125805006290SFelipe Balbi dma-channel-mask = <0xfa>; 125905006290SFelipe Balbi iommus = <&apps_smmu 0x0616 0x0>; 126005006290SFelipe Balbi #dma-cells = <3>; 126105006290SFelipe Balbi status = "disabled"; 126205006290SFelipe Balbi }; 126305006290SFelipe Balbi 1264e13c6d14SVinod Koul qupv3_id_1: geniqup@ac0000 { 1265e13c6d14SVinod Koul compatible = "qcom,geni-se-qup"; 1266e13c6d14SVinod Koul reg = <0x0 0x00ac0000 0x0 0x6000>; 1267e13c6d14SVinod Koul clock-names = "m-ahb", "s-ahb"; 1268d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1269d6f55763SVinod Koul <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 12709cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x603 0x0>; 1271e13c6d14SVinod Koul #address-cells = <2>; 1272e13c6d14SVinod Koul #size-cells = <2>; 1273e13c6d14SVinod Koul ranges; 1274e13c6d14SVinod Koul status = "disabled"; 1275e13c6d14SVinod Koul 127681bee695SCaleb Connolly i2c8: i2c@a80000 { 127781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 127881bee695SCaleb Connolly reg = <0 0x00a80000 0 0x4000>; 127981bee695SCaleb Connolly clock-names = "se"; 128081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1281abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1282abdd4b7aSFelipe Balbi <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1283abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 128481bee695SCaleb Connolly pinctrl-names = "default"; 128581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c8_default>; 128681bee695SCaleb Connolly interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 128781bee695SCaleb Connolly #address-cells = <1>; 128881bee695SCaleb Connolly #size-cells = <0>; 128981bee695SCaleb Connolly status = "disabled"; 129081bee695SCaleb Connolly }; 129181bee695SCaleb Connolly 1292129e1c96SFelipe Balbi spi8: spi@a80000 { 1293129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1294f6973229SKonrad Dybcio reg = <0 0x00a80000 0 0x4000>; 1295129e1c96SFelipe Balbi reg-names = "se"; 1296129e1c96SFelipe Balbi clock-names = "se"; 1297129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1298abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1299abdd4b7aSFelipe Balbi <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1300abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1301129e1c96SFelipe Balbi pinctrl-names = "default"; 1302129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi8_default>; 1303129e1c96SFelipe Balbi interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1304129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1305129e1c96SFelipe Balbi #address-cells = <1>; 1306129e1c96SFelipe Balbi #size-cells = <0>; 1307129e1c96SFelipe Balbi status = "disabled"; 1308129e1c96SFelipe Balbi }; 1309129e1c96SFelipe Balbi 131081bee695SCaleb Connolly i2c9: i2c@a84000 { 131181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 131281bee695SCaleb Connolly reg = <0 0x00a84000 0 0x4000>; 131381bee695SCaleb Connolly clock-names = "se"; 131481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1315abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1316abdd4b7aSFelipe Balbi <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1317abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 131881bee695SCaleb Connolly pinctrl-names = "default"; 131981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c9_default>; 132081bee695SCaleb Connolly interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 132181bee695SCaleb Connolly #address-cells = <1>; 132281bee695SCaleb Connolly #size-cells = <0>; 132381bee695SCaleb Connolly status = "disabled"; 132481bee695SCaleb Connolly }; 132581bee695SCaleb Connolly 1326129e1c96SFelipe Balbi spi9: spi@a84000 { 1327129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1328f6973229SKonrad Dybcio reg = <0 0x00a84000 0 0x4000>; 1329129e1c96SFelipe Balbi reg-names = "se"; 1330129e1c96SFelipe Balbi clock-names = "se"; 1331129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1332abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1333abdd4b7aSFelipe Balbi <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1334abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1335129e1c96SFelipe Balbi pinctrl-names = "default"; 1336129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi9_default>; 1337129e1c96SFelipe Balbi interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1338129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1339129e1c96SFelipe Balbi #address-cells = <1>; 1340129e1c96SFelipe Balbi #size-cells = <0>; 1341129e1c96SFelipe Balbi status = "disabled"; 1342129e1c96SFelipe Balbi }; 1343129e1c96SFelipe Balbi 13449ebaa4a8SBartosz Golaszewski uart9: serial@a84000 { 134510d900a8SBartosz Golaszewski compatible = "qcom,geni-uart"; 134610d900a8SBartosz Golaszewski reg = <0x0 0x00a84000 0x0 0x4000>; 134710d900a8SBartosz Golaszewski reg-names = "se"; 134810d900a8SBartosz Golaszewski clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 134910d900a8SBartosz Golaszewski clock-names = "se"; 135010d900a8SBartosz Golaszewski pinctrl-0 = <&qup_uart9_default>; 135110d900a8SBartosz Golaszewski pinctrl-names = "default"; 135210d900a8SBartosz Golaszewski interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 135310d900a8SBartosz Golaszewski #address-cells = <1>; 135410d900a8SBartosz Golaszewski #size-cells = <0>; 135510d900a8SBartosz Golaszewski status = "disabled"; 135610d900a8SBartosz Golaszewski }; 135710d900a8SBartosz Golaszewski 135881bee695SCaleb Connolly i2c10: i2c@a88000 { 135981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 136081bee695SCaleb Connolly reg = <0 0x00a88000 0 0x4000>; 136181bee695SCaleb Connolly clock-names = "se"; 136281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1363abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1364abdd4b7aSFelipe Balbi <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1365abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 136681bee695SCaleb Connolly pinctrl-names = "default"; 136781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c10_default>; 136881bee695SCaleb Connolly interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 136981bee695SCaleb Connolly #address-cells = <1>; 137081bee695SCaleb Connolly #size-cells = <0>; 137181bee695SCaleb Connolly status = "disabled"; 137281bee695SCaleb Connolly }; 137381bee695SCaleb Connolly 1374129e1c96SFelipe Balbi spi10: spi@a88000 { 1375129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1376f6973229SKonrad Dybcio reg = <0 0x00a88000 0 0x4000>; 1377129e1c96SFelipe Balbi reg-names = "se"; 1378129e1c96SFelipe Balbi clock-names = "se"; 1379129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1380abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1381abdd4b7aSFelipe Balbi <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1382abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1383129e1c96SFelipe Balbi pinctrl-names = "default"; 1384129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi10_default>; 1385129e1c96SFelipe Balbi interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1386129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1387129e1c96SFelipe Balbi #address-cells = <1>; 1388129e1c96SFelipe Balbi #size-cells = <0>; 1389129e1c96SFelipe Balbi status = "disabled"; 1390129e1c96SFelipe Balbi }; 1391129e1c96SFelipe Balbi 139281bee695SCaleb Connolly i2c11: i2c@a8c000 { 139381bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 139481bee695SCaleb Connolly reg = <0 0x00a8c000 0 0x4000>; 139581bee695SCaleb Connolly clock-names = "se"; 139681bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1397abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1398abdd4b7aSFelipe Balbi <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1399abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 140081bee695SCaleb Connolly pinctrl-names = "default"; 140181bee695SCaleb Connolly pinctrl-0 = <&qup_i2c11_default>; 140281bee695SCaleb Connolly interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 140381bee695SCaleb Connolly #address-cells = <1>; 140481bee695SCaleb Connolly #size-cells = <0>; 140581bee695SCaleb Connolly status = "disabled"; 140681bee695SCaleb Connolly }; 140781bee695SCaleb Connolly 1408129e1c96SFelipe Balbi spi11: spi@a8c000 { 1409129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1410f6973229SKonrad Dybcio reg = <0 0x00a8c000 0 0x4000>; 1411129e1c96SFelipe Balbi reg-names = "se"; 1412129e1c96SFelipe Balbi clock-names = "se"; 1413129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1414abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1415abdd4b7aSFelipe Balbi <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1416abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1417129e1c96SFelipe Balbi pinctrl-names = "default"; 1418129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi11_default>; 1419129e1c96SFelipe Balbi interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1420129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1421129e1c96SFelipe Balbi #address-cells = <1>; 1422129e1c96SFelipe Balbi #size-cells = <0>; 1423129e1c96SFelipe Balbi status = "disabled"; 1424129e1c96SFelipe Balbi }; 1425129e1c96SFelipe Balbi 1426e13c6d14SVinod Koul uart2: serial@a90000 { 1427e13c6d14SVinod Koul compatible = "qcom,geni-debug-uart"; 1428e13c6d14SVinod Koul reg = <0x0 0x00a90000 0x0 0x4000>; 1429e13c6d14SVinod Koul clock-names = "se"; 1430d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1431e13c6d14SVinod Koul interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1432e13c6d14SVinod Koul status = "disabled"; 1433e13c6d14SVinod Koul }; 143481bee695SCaleb Connolly 143581bee695SCaleb Connolly i2c12: i2c@a90000 { 143681bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 143781bee695SCaleb Connolly reg = <0 0x00a90000 0 0x4000>; 143881bee695SCaleb Connolly clock-names = "se"; 143981bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1440abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1441abdd4b7aSFelipe Balbi <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1442abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 144381bee695SCaleb Connolly pinctrl-names = "default"; 144481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c12_default>; 144581bee695SCaleb Connolly interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 144681bee695SCaleb Connolly #address-cells = <1>; 144781bee695SCaleb Connolly #size-cells = <0>; 144881bee695SCaleb Connolly status = "disabled"; 144981bee695SCaleb Connolly }; 145081bee695SCaleb Connolly 1451129e1c96SFelipe Balbi spi12: spi@a90000 { 1452129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1453f6973229SKonrad Dybcio reg = <0 0x00a90000 0 0x4000>; 1454129e1c96SFelipe Balbi reg-names = "se"; 1455129e1c96SFelipe Balbi clock-names = "se"; 1456129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1457abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1458abdd4b7aSFelipe Balbi <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1459abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1460129e1c96SFelipe Balbi pinctrl-names = "default"; 1461129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi12_default>; 1462129e1c96SFelipe Balbi interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1463129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1464129e1c96SFelipe Balbi #address-cells = <1>; 1465129e1c96SFelipe Balbi #size-cells = <0>; 1466129e1c96SFelipe Balbi status = "disabled"; 1467129e1c96SFelipe Balbi }; 1468129e1c96SFelipe Balbi 146981bee695SCaleb Connolly i2c16: i2c@94000 { 147081bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 1471f6973229SKonrad Dybcio reg = <0 0x00094000 0 0x4000>; 147281bee695SCaleb Connolly clock-names = "se"; 147381bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1474abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1475abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1476abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 147781bee695SCaleb Connolly pinctrl-names = "default"; 147881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c16_default>; 147981bee695SCaleb Connolly interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 148081bee695SCaleb Connolly #address-cells = <1>; 148181bee695SCaleb Connolly #size-cells = <0>; 148281bee695SCaleb Connolly status = "disabled"; 148381bee695SCaleb Connolly }; 1484129e1c96SFelipe Balbi 1485129e1c96SFelipe Balbi spi16: spi@a94000 { 1486129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1487f6973229SKonrad Dybcio reg = <0 0x00a94000 0 0x4000>; 1488129e1c96SFelipe Balbi reg-names = "se"; 1489129e1c96SFelipe Balbi clock-names = "se"; 1490129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1491abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1492abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1493abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1494129e1c96SFelipe Balbi pinctrl-names = "default"; 1495129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi16_default>; 1496129e1c96SFelipe Balbi interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1497129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1498129e1c96SFelipe Balbi #address-cells = <1>; 1499129e1c96SFelipe Balbi #size-cells = <0>; 1500129e1c96SFelipe Balbi status = "disabled"; 1501129e1c96SFelipe Balbi }; 1502e13c6d14SVinod Koul }; 1503e13c6d14SVinod Koul 150405006290SFelipe Balbi gpi_dma2: dma-controller@c00000 { 1505e7e24786SRichard Acayan compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1506f6973229SKonrad Dybcio reg = <0 0x00c00000 0 0x60000>; 150705006290SFelipe Balbi interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 150805006290SFelipe Balbi <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 150905006290SFelipe Balbi <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 151005006290SFelipe Balbi <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 151105006290SFelipe Balbi <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 151205006290SFelipe Balbi <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 151305006290SFelipe Balbi <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 151405006290SFelipe Balbi <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 151505006290SFelipe Balbi <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 151605006290SFelipe Balbi <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 151705006290SFelipe Balbi <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 151805006290SFelipe Balbi <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 151905006290SFelipe Balbi <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 152005006290SFelipe Balbi dma-channels = <13>; 152105006290SFelipe Balbi dma-channel-mask = <0xfa>; 152205006290SFelipe Balbi iommus = <&apps_smmu 0x07b6 0x0>; 152305006290SFelipe Balbi #dma-cells = <3>; 152405006290SFelipe Balbi status = "disabled"; 152505006290SFelipe Balbi }; 152605006290SFelipe Balbi 15279cf3ebd1SCaleb Connolly qupv3_id_2: geniqup@cc0000 { 15289cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 15299cf3ebd1SCaleb Connolly reg = <0x0 0x00cc0000 0x0 0x6000>; 15309cf3ebd1SCaleb Connolly 15319cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 15329cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 15339cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 15349cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x7a3 0x0>; 15359cf3ebd1SCaleb Connolly #address-cells = <2>; 15369cf3ebd1SCaleb Connolly #size-cells = <2>; 15379cf3ebd1SCaleb Connolly ranges; 15389cf3ebd1SCaleb Connolly status = "disabled"; 153981bee695SCaleb Connolly 154081bee695SCaleb Connolly i2c17: i2c@c80000 { 154181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 154281bee695SCaleb Connolly reg = <0 0x00c80000 0 0x4000>; 154381bee695SCaleb Connolly clock-names = "se"; 154481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1545abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1546abdd4b7aSFelipe Balbi <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1547abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 154881bee695SCaleb Connolly pinctrl-names = "default"; 154981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c17_default>; 155081bee695SCaleb Connolly interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 155181bee695SCaleb Connolly #address-cells = <1>; 155281bee695SCaleb Connolly #size-cells = <0>; 155381bee695SCaleb Connolly status = "disabled"; 155481bee695SCaleb Connolly }; 155581bee695SCaleb Connolly 1556129e1c96SFelipe Balbi spi17: spi@c80000 { 1557129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1558f6973229SKonrad Dybcio reg = <0 0x00c80000 0 0x4000>; 1559129e1c96SFelipe Balbi reg-names = "se"; 1560129e1c96SFelipe Balbi clock-names = "se"; 1561129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1562abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1563abdd4b7aSFelipe Balbi <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1564abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1565129e1c96SFelipe Balbi pinctrl-names = "default"; 1566129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi17_default>; 1567129e1c96SFelipe Balbi interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1568129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1569129e1c96SFelipe Balbi #address-cells = <1>; 1570129e1c96SFelipe Balbi #size-cells = <0>; 1571129e1c96SFelipe Balbi status = "disabled"; 1572129e1c96SFelipe Balbi }; 1573129e1c96SFelipe Balbi 157481bee695SCaleb Connolly i2c18: i2c@c84000 { 157581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 157681bee695SCaleb Connolly reg = <0 0x00c84000 0 0x4000>; 157781bee695SCaleb Connolly clock-names = "se"; 157881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1579abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1580abdd4b7aSFelipe Balbi <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1581abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 158281bee695SCaleb Connolly pinctrl-names = "default"; 158381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c18_default>; 158481bee695SCaleb Connolly interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 158581bee695SCaleb Connolly #address-cells = <1>; 158681bee695SCaleb Connolly #size-cells = <0>; 158781bee695SCaleb Connolly status = "disabled"; 158881bee695SCaleb Connolly }; 158981bee695SCaleb Connolly 1590129e1c96SFelipe Balbi spi18: spi@c84000 { 1591129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1592f6973229SKonrad Dybcio reg = <0 0x00c84000 0 0x4000>; 1593129e1c96SFelipe Balbi reg-names = "se"; 1594129e1c96SFelipe Balbi clock-names = "se"; 1595129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1596abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1597abdd4b7aSFelipe Balbi <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1598abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1599129e1c96SFelipe Balbi pinctrl-names = "default"; 1600129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi18_default>; 1601129e1c96SFelipe Balbi interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1602129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1603129e1c96SFelipe Balbi #address-cells = <1>; 1604129e1c96SFelipe Balbi #size-cells = <0>; 1605129e1c96SFelipe Balbi status = "disabled"; 1606129e1c96SFelipe Balbi }; 1607129e1c96SFelipe Balbi 160881bee695SCaleb Connolly i2c19: i2c@c88000 { 160981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 161081bee695SCaleb Connolly reg = <0 0x00c88000 0 0x4000>; 161181bee695SCaleb Connolly clock-names = "se"; 161281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1613abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1614abdd4b7aSFelipe Balbi <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1615abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 161681bee695SCaleb Connolly pinctrl-names = "default"; 161781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c19_default>; 161881bee695SCaleb Connolly interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 161981bee695SCaleb Connolly #address-cells = <1>; 162081bee695SCaleb Connolly #size-cells = <0>; 162181bee695SCaleb Connolly status = "disabled"; 162281bee695SCaleb Connolly }; 162381bee695SCaleb Connolly 1624129e1c96SFelipe Balbi spi19: spi@c88000 { 1625129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1626f6973229SKonrad Dybcio reg = <0 0x00c88000 0 0x4000>; 1627129e1c96SFelipe Balbi reg-names = "se"; 1628129e1c96SFelipe Balbi clock-names = "se"; 1629129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1630abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1631abdd4b7aSFelipe Balbi <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1632abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1633129e1c96SFelipe Balbi pinctrl-names = "default"; 1634129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi19_default>; 1635129e1c96SFelipe Balbi interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1636129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1637129e1c96SFelipe Balbi #address-cells = <1>; 1638129e1c96SFelipe Balbi #size-cells = <0>; 1639129e1c96SFelipe Balbi status = "disabled"; 1640129e1c96SFelipe Balbi }; 1641129e1c96SFelipe Balbi 164281bee695SCaleb Connolly i2c13: i2c@c8c000 { 164381bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 164481bee695SCaleb Connolly reg = <0 0x00c8c000 0 0x4000>; 164581bee695SCaleb Connolly clock-names = "se"; 164681bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1647abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1648abdd4b7aSFelipe Balbi <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1649abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 165081bee695SCaleb Connolly pinctrl-names = "default"; 165181bee695SCaleb Connolly pinctrl-0 = <&qup_i2c13_default>; 165281bee695SCaleb Connolly interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 165381bee695SCaleb Connolly #address-cells = <1>; 165481bee695SCaleb Connolly #size-cells = <0>; 165581bee695SCaleb Connolly status = "disabled"; 165681bee695SCaleb Connolly }; 165781bee695SCaleb Connolly 1658129e1c96SFelipe Balbi spi13: spi@c8c000 { 1659129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1660f6973229SKonrad Dybcio reg = <0 0x00c8c000 0 0x4000>; 1661129e1c96SFelipe Balbi reg-names = "se"; 1662129e1c96SFelipe Balbi clock-names = "se"; 1663129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1664abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1665abdd4b7aSFelipe Balbi <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1666abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1667129e1c96SFelipe Balbi pinctrl-names = "default"; 1668129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi13_default>; 1669129e1c96SFelipe Balbi interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1670129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1671129e1c96SFelipe Balbi #address-cells = <1>; 1672129e1c96SFelipe Balbi #size-cells = <0>; 1673129e1c96SFelipe Balbi status = "disabled"; 1674129e1c96SFelipe Balbi }; 1675129e1c96SFelipe Balbi 167681bee695SCaleb Connolly i2c14: i2c@c90000 { 167781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 167881bee695SCaleb Connolly reg = <0 0x00c90000 0 0x4000>; 167981bee695SCaleb Connolly clock-names = "se"; 168081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1681abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1682abdd4b7aSFelipe Balbi <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1683abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 168481bee695SCaleb Connolly pinctrl-names = "default"; 168581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c14_default>; 168681bee695SCaleb Connolly interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 168781bee695SCaleb Connolly #address-cells = <1>; 168881bee695SCaleb Connolly #size-cells = <0>; 168981bee695SCaleb Connolly status = "disabled"; 169081bee695SCaleb Connolly }; 169181bee695SCaleb Connolly 1692129e1c96SFelipe Balbi spi14: spi@c90000 { 1693129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1694f6973229SKonrad Dybcio reg = <0 0x00c90000 0 0x4000>; 1695129e1c96SFelipe Balbi reg-names = "se"; 1696129e1c96SFelipe Balbi clock-names = "se"; 1697129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1698abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1699abdd4b7aSFelipe Balbi <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1700abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1701129e1c96SFelipe Balbi pinctrl-names = "default"; 1702129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi14_default>; 1703129e1c96SFelipe Balbi interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1704129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1705129e1c96SFelipe Balbi #address-cells = <1>; 1706129e1c96SFelipe Balbi #size-cells = <0>; 1707129e1c96SFelipe Balbi status = "disabled"; 1708129e1c96SFelipe Balbi }; 1709129e1c96SFelipe Balbi 171081bee695SCaleb Connolly i2c15: i2c@c94000 { 171181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 171281bee695SCaleb Connolly reg = <0 0x00c94000 0 0x4000>; 171381bee695SCaleb Connolly clock-names = "se"; 171481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1715abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1716abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1717abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 171881bee695SCaleb Connolly pinctrl-names = "default"; 171981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c15_default>; 172081bee695SCaleb Connolly interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 172181bee695SCaleb Connolly #address-cells = <1>; 172281bee695SCaleb Connolly #size-cells = <0>; 172381bee695SCaleb Connolly status = "disabled"; 172481bee695SCaleb Connolly }; 1725129e1c96SFelipe Balbi 1726129e1c96SFelipe Balbi spi15: spi@c94000 { 1727129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1728f6973229SKonrad Dybcio reg = <0 0x00c94000 0 0x4000>; 1729129e1c96SFelipe Balbi reg-names = "se"; 1730129e1c96SFelipe Balbi clock-names = "se"; 1731129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1732abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1733abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1734abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1735129e1c96SFelipe Balbi pinctrl-names = "default"; 1736129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi15_default>; 1737129e1c96SFelipe Balbi interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1738129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1739129e1c96SFelipe Balbi #address-cells = <1>; 1740129e1c96SFelipe Balbi #size-cells = <0>; 1741129e1c96SFelipe Balbi status = "disabled"; 1742129e1c96SFelipe Balbi }; 17439cf3ebd1SCaleb Connolly }; 17449cf3ebd1SCaleb Connolly 174571a2fc6eSJonathan Marek config_noc: interconnect@1500000 { 174671a2fc6eSJonathan Marek compatible = "qcom,sm8150-config-noc"; 174771a2fc6eSJonathan Marek reg = <0 0x01500000 0 0x7400>; 174871a2fc6eSJonathan Marek #interconnect-cells = <1>; 174971a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 175071a2fc6eSJonathan Marek }; 175171a2fc6eSJonathan Marek 175271a2fc6eSJonathan Marek system_noc: interconnect@1620000 { 175371a2fc6eSJonathan Marek compatible = "qcom,sm8150-system-noc"; 175471a2fc6eSJonathan Marek reg = <0 0x01620000 0 0x19400>; 175571a2fc6eSJonathan Marek #interconnect-cells = <1>; 175671a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 175771a2fc6eSJonathan Marek }; 175871a2fc6eSJonathan Marek 175971a2fc6eSJonathan Marek mc_virt: interconnect@163a000 { 176071a2fc6eSJonathan Marek compatible = "qcom,sm8150-mc-virt"; 176171a2fc6eSJonathan Marek reg = <0 0x0163a000 0 0x1000>; 176271a2fc6eSJonathan Marek #interconnect-cells = <1>; 176371a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 176471a2fc6eSJonathan Marek }; 176571a2fc6eSJonathan Marek 176671a2fc6eSJonathan Marek aggre1_noc: interconnect@16e0000 { 176771a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre1-noc"; 176871a2fc6eSJonathan Marek reg = <0 0x016e0000 0 0xd080>; 176971a2fc6eSJonathan Marek #interconnect-cells = <1>; 177071a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 177171a2fc6eSJonathan Marek }; 177271a2fc6eSJonathan Marek 177371a2fc6eSJonathan Marek aggre2_noc: interconnect@1700000 { 177471a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre2-noc"; 177571a2fc6eSJonathan Marek reg = <0 0x01700000 0 0x20000>; 177671a2fc6eSJonathan Marek #interconnect-cells = <1>; 177771a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 177871a2fc6eSJonathan Marek }; 177971a2fc6eSJonathan Marek 178071a2fc6eSJonathan Marek compute_noc: interconnect@1720000 { 178171a2fc6eSJonathan Marek compatible = "qcom,sm8150-compute-noc"; 178271a2fc6eSJonathan Marek reg = <0 0x01720000 0 0x7000>; 178371a2fc6eSJonathan Marek #interconnect-cells = <1>; 178471a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 178571a2fc6eSJonathan Marek }; 178671a2fc6eSJonathan Marek 178771a2fc6eSJonathan Marek mmss_noc: interconnect@1740000 { 178871a2fc6eSJonathan Marek compatible = "qcom,sm8150-mmss-noc"; 178971a2fc6eSJonathan Marek reg = <0 0x01740000 0 0x1c100>; 179071a2fc6eSJonathan Marek #interconnect-cells = <1>; 179171a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 179271a2fc6eSJonathan Marek }; 179371a2fc6eSJonathan Marek 1794bb1f7cf6SSouradeep Chowdhury system-cache-controller@9200000 { 1795bb1f7cf6SSouradeep Chowdhury compatible = "qcom,sm8150-llcc"; 1796c5ccf8d3SManivannan Sadhasivam reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 1797c5ccf8d3SManivannan Sadhasivam <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 1798c5ccf8d3SManivannan Sadhasivam <0 0x09600000 0 0x50000>; 1799c5ccf8d3SManivannan Sadhasivam reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 1800c5ccf8d3SManivannan Sadhasivam "llcc3_base", "llcc_broadcast_base"; 1801bb1f7cf6SSouradeep Chowdhury interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1802bb1f7cf6SSouradeep Chowdhury }; 1803bb1f7cf6SSouradeep Chowdhury 1804d4b94c82SSouradeep Chowdhury dma@10a2000 { 1805d4b94c82SSouradeep Chowdhury compatible = "qcom,sm8150-dcc", "qcom,dcc"; 1806d4b94c82SSouradeep Chowdhury reg = <0x0 0x010a2000 0x0 0x1000>, 1807d4b94c82SSouradeep Chowdhury <0x0 0x010ad000 0x0 0x3000>; 1808d4b94c82SSouradeep Chowdhury }; 1809d4b94c82SSouradeep Chowdhury 1810a1c86c68SBhupesh Sharma pcie0: pci@1c00000 { 1811a1c86c68SBhupesh Sharma compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1812a1c86c68SBhupesh Sharma reg = <0 0x01c00000 0 0x3000>, 1813a1c86c68SBhupesh Sharma <0 0x60000000 0 0xf1d>, 1814a1c86c68SBhupesh Sharma <0 0x60000f20 0 0xa8>, 1815a1c86c68SBhupesh Sharma <0 0x60001000 0 0x1000>, 1816a1c86c68SBhupesh Sharma <0 0x60100000 0 0x100000>; 1817a1c86c68SBhupesh Sharma reg-names = "parf", "dbi", "elbi", "atu", "config"; 1818a1c86c68SBhupesh Sharma device_type = "pci"; 1819a1c86c68SBhupesh Sharma linux,pci-domain = <0>; 1820a1c86c68SBhupesh Sharma bus-range = <0x00 0xff>; 1821a1c86c68SBhupesh Sharma num-lanes = <1>; 1822a1c86c68SBhupesh Sharma 1823a1c86c68SBhupesh Sharma #address-cells = <3>; 1824a1c86c68SBhupesh Sharma #size-cells = <2>; 1825a1c86c68SBhupesh Sharma 1826422b110bSManivannan Sadhasivam ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1827422b110bSManivannan Sadhasivam <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1828a1c86c68SBhupesh Sharma 1829a1c86c68SBhupesh Sharma interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1830a1c86c68SBhupesh Sharma interrupt-names = "msi"; 1831a1c86c68SBhupesh Sharma #interrupt-cells = <1>; 1832a1c86c68SBhupesh Sharma interrupt-map-mask = <0 0 0 0x7>; 1833a1c86c68SBhupesh Sharma interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1834a1c86c68SBhupesh Sharma <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1835a1c86c68SBhupesh Sharma <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1836a1c86c68SBhupesh Sharma <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1837a1c86c68SBhupesh Sharma 1838a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1839a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_AUX_CLK>, 1840a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1841a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1842a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1843a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1844a1c86c68SBhupesh Sharma <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1845a1c86c68SBhupesh Sharma clock-names = "pipe", 1846a1c86c68SBhupesh Sharma "aux", 1847a1c86c68SBhupesh Sharma "cfg", 1848a1c86c68SBhupesh Sharma "bus_master", 1849a1c86c68SBhupesh Sharma "bus_slave", 1850a1c86c68SBhupesh Sharma "slave_q2a", 1851a1c86c68SBhupesh Sharma "tbu"; 1852a1c86c68SBhupesh Sharma 1853a1c86c68SBhupesh Sharma iommus = <&apps_smmu 0x1d80 0x7f>; 1854a1c86c68SBhupesh Sharma iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1855a1c86c68SBhupesh Sharma <0x100 &apps_smmu 0x1d81 0x1>; 1856a1c86c68SBhupesh Sharma 1857a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_0_BCR>; 1858a1c86c68SBhupesh Sharma reset-names = "pci"; 1859a1c86c68SBhupesh Sharma 1860a1c86c68SBhupesh Sharma power-domains = <&gcc PCIE_0_GDSC>; 1861a1c86c68SBhupesh Sharma 1862a1c86c68SBhupesh Sharma phys = <&pcie0_lane>; 1863a1c86c68SBhupesh Sharma phy-names = "pciephy"; 1864a1c86c68SBhupesh Sharma 1865a1c86c68SBhupesh Sharma perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1866a1c86c68SBhupesh Sharma enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1867a1c86c68SBhupesh Sharma 1868a1c86c68SBhupesh Sharma pinctrl-names = "default"; 1869a1c86c68SBhupesh Sharma pinctrl-0 = <&pcie0_default_state>; 1870a1c86c68SBhupesh Sharma 1871a1c86c68SBhupesh Sharma status = "disabled"; 1872a1c86c68SBhupesh Sharma }; 1873a1c86c68SBhupesh Sharma 1874a1c86c68SBhupesh Sharma pcie0_phy: phy@1c06000 { 1875a1c86c68SBhupesh Sharma compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1876a1c86c68SBhupesh Sharma reg = <0 0x01c06000 0 0x1c0>; 1877a1c86c68SBhupesh Sharma #address-cells = <2>; 1878a1c86c68SBhupesh Sharma #size-cells = <2>; 1879a1c86c68SBhupesh Sharma ranges; 1880a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1881a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1882a1c86c68SBhupesh Sharma <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1883a1c86c68SBhupesh Sharma clock-names = "aux", "cfg_ahb", "refgen"; 1884a1c86c68SBhupesh Sharma 1885a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1886a1c86c68SBhupesh Sharma reset-names = "phy"; 1887a1c86c68SBhupesh Sharma 1888a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1889a1c86c68SBhupesh Sharma assigned-clock-rates = <100000000>; 1890a1c86c68SBhupesh Sharma 1891a1c86c68SBhupesh Sharma status = "disabled"; 1892a1c86c68SBhupesh Sharma 1893a1c86c68SBhupesh Sharma pcie0_lane: phy@1c06200 { 1894f6973229SKonrad Dybcio reg = <0 0x01c06200 0 0x170>, /* tx */ 1895f6973229SKonrad Dybcio <0 0x01c06400 0 0x200>, /* rx */ 1896f6973229SKonrad Dybcio <0 0x01c06800 0 0x1f0>, /* pcs */ 1897f6973229SKonrad Dybcio <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1898a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1899a1c86c68SBhupesh Sharma clock-names = "pipe0"; 1900a1c86c68SBhupesh Sharma 1901a1c86c68SBhupesh Sharma #phy-cells = <0>; 1902a1c86c68SBhupesh Sharma clock-output-names = "pcie_0_pipe_clk"; 1903a1c86c68SBhupesh Sharma }; 1904a1c86c68SBhupesh Sharma }; 1905a1c86c68SBhupesh Sharma 1906a1c86c68SBhupesh Sharma pcie1: pci@1c08000 { 1907a1c86c68SBhupesh Sharma compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1908a1c86c68SBhupesh Sharma reg = <0 0x01c08000 0 0x3000>, 1909a1c86c68SBhupesh Sharma <0 0x40000000 0 0xf1d>, 1910a1c86c68SBhupesh Sharma <0 0x40000f20 0 0xa8>, 1911a1c86c68SBhupesh Sharma <0 0x40001000 0 0x1000>, 1912a1c86c68SBhupesh Sharma <0 0x40100000 0 0x100000>; 1913a1c86c68SBhupesh Sharma reg-names = "parf", "dbi", "elbi", "atu", "config"; 1914a1c86c68SBhupesh Sharma device_type = "pci"; 1915a1c86c68SBhupesh Sharma linux,pci-domain = <1>; 1916a1c86c68SBhupesh Sharma bus-range = <0x00 0xff>; 1917a1c86c68SBhupesh Sharma num-lanes = <2>; 1918a1c86c68SBhupesh Sharma 1919a1c86c68SBhupesh Sharma #address-cells = <3>; 1920a1c86c68SBhupesh Sharma #size-cells = <2>; 1921a1c86c68SBhupesh Sharma 1922422b110bSManivannan Sadhasivam ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1923a1c86c68SBhupesh Sharma <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1924a1c86c68SBhupesh Sharma 1925a1c86c68SBhupesh Sharma interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1926a1c86c68SBhupesh Sharma interrupt-names = "msi"; 1927a1c86c68SBhupesh Sharma #interrupt-cells = <1>; 1928a1c86c68SBhupesh Sharma interrupt-map-mask = <0 0 0 0x7>; 1929a1c86c68SBhupesh Sharma interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1930a1c86c68SBhupesh Sharma <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1931a1c86c68SBhupesh Sharma <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1932a1c86c68SBhupesh Sharma <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1933a1c86c68SBhupesh Sharma 1934a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1935a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_AUX_CLK>, 1936a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1937a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1938a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1939a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1940a1c86c68SBhupesh Sharma <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1941a1c86c68SBhupesh Sharma clock-names = "pipe", 1942a1c86c68SBhupesh Sharma "aux", 1943a1c86c68SBhupesh Sharma "cfg", 1944a1c86c68SBhupesh Sharma "bus_master", 1945a1c86c68SBhupesh Sharma "bus_slave", 1946a1c86c68SBhupesh Sharma "slave_q2a", 1947a1c86c68SBhupesh Sharma "tbu"; 1948a1c86c68SBhupesh Sharma 1949a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1950a1c86c68SBhupesh Sharma assigned-clock-rates = <19200000>; 1951a1c86c68SBhupesh Sharma 1952a1c86c68SBhupesh Sharma iommus = <&apps_smmu 0x1e00 0x7f>; 1953a1c86c68SBhupesh Sharma iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1954a1c86c68SBhupesh Sharma <0x100 &apps_smmu 0x1e01 0x1>; 1955a1c86c68SBhupesh Sharma 1956a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_1_BCR>; 1957a1c86c68SBhupesh Sharma reset-names = "pci"; 1958a1c86c68SBhupesh Sharma 1959a1c86c68SBhupesh Sharma power-domains = <&gcc PCIE_1_GDSC>; 1960a1c86c68SBhupesh Sharma 1961a1c86c68SBhupesh Sharma phys = <&pcie1_lane>; 1962a1c86c68SBhupesh Sharma phy-names = "pciephy"; 1963a1c86c68SBhupesh Sharma 1964a1c86c68SBhupesh Sharma perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; 1965a1c86c68SBhupesh Sharma enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 1966a1c86c68SBhupesh Sharma 1967a1c86c68SBhupesh Sharma pinctrl-names = "default"; 1968a1c86c68SBhupesh Sharma pinctrl-0 = <&pcie1_default_state>; 1969a1c86c68SBhupesh Sharma 1970a1c86c68SBhupesh Sharma status = "disabled"; 1971a1c86c68SBhupesh Sharma }; 1972a1c86c68SBhupesh Sharma 1973a1c86c68SBhupesh Sharma pcie1_phy: phy@1c0e000 { 1974a1c86c68SBhupesh Sharma compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 1975a1c86c68SBhupesh Sharma reg = <0 0x01c0e000 0 0x1c0>; 1976a1c86c68SBhupesh Sharma #address-cells = <2>; 1977a1c86c68SBhupesh Sharma #size-cells = <2>; 1978a1c86c68SBhupesh Sharma ranges; 1979a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1980a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1981a1c86c68SBhupesh Sharma <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1982a1c86c68SBhupesh Sharma clock-names = "aux", "cfg_ahb", "refgen"; 1983a1c86c68SBhupesh Sharma 1984a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1985a1c86c68SBhupesh Sharma reset-names = "phy"; 1986a1c86c68SBhupesh Sharma 1987a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1988a1c86c68SBhupesh Sharma assigned-clock-rates = <100000000>; 1989a1c86c68SBhupesh Sharma 1990a1c86c68SBhupesh Sharma status = "disabled"; 1991a1c86c68SBhupesh Sharma 1992a1c86c68SBhupesh Sharma pcie1_lane: phy@1c0e200 { 1993f6973229SKonrad Dybcio reg = <0 0x01c0e200 0 0x170>, /* tx0 */ 1994f6973229SKonrad Dybcio <0 0x01c0e400 0 0x200>, /* rx0 */ 1995f6973229SKonrad Dybcio <0 0x01c0ea00 0 0x1f0>, /* pcs */ 1996f6973229SKonrad Dybcio <0 0x01c0e600 0 0x170>, /* tx1 */ 1997f6973229SKonrad Dybcio <0 0x01c0e800 0 0x200>, /* rx1 */ 1998f6973229SKonrad Dybcio <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1999a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2000a1c86c68SBhupesh Sharma clock-names = "pipe0"; 2001a1c86c68SBhupesh Sharma 2002a1c86c68SBhupesh Sharma #phy-cells = <0>; 2003a1c86c68SBhupesh Sharma clock-output-names = "pcie_1_pipe_clk"; 2004a1c86c68SBhupesh Sharma }; 2005a1c86c68SBhupesh Sharma }; 2006a1c86c68SBhupesh Sharma 20073834a2e9SVinod Koul ufs_mem_hc: ufshc@1d84000 { 20083834a2e9SVinod Koul compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 20093834a2e9SVinod Koul "jedec,ufs-2.0"; 201098aee1e3SBhupesh Sharma reg = <0 0x01d84000 0 0x2500>, 201198aee1e3SBhupesh Sharma <0 0x01d90000 0 0x8000>; 201298aee1e3SBhupesh Sharma reg-names = "std", "ice"; 20133834a2e9SVinod Koul interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 20143834a2e9SVinod Koul phys = <&ufs_mem_phy_lanes>; 20153834a2e9SVinod Koul phy-names = "ufsphy"; 20163834a2e9SVinod Koul lanes-per-direction = <2>; 20173834a2e9SVinod Koul #reset-cells = <1>; 20183834a2e9SVinod Koul resets = <&gcc GCC_UFS_PHY_BCR>; 20193834a2e9SVinod Koul reset-names = "rst"; 20203834a2e9SVinod Koul 202148156232SJonathan Marek iommus = <&apps_smmu 0x300 0>; 202248156232SJonathan Marek 20233834a2e9SVinod Koul clock-names = 20243834a2e9SVinod Koul "core_clk", 20253834a2e9SVinod Koul "bus_aggr_clk", 20263834a2e9SVinod Koul "iface_clk", 20273834a2e9SVinod Koul "core_clk_unipro", 20283834a2e9SVinod Koul "ref_clk", 20293834a2e9SVinod Koul "tx_lane0_sync_clk", 20303834a2e9SVinod Koul "rx_lane0_sync_clk", 203198aee1e3SBhupesh Sharma "rx_lane1_sync_clk", 203298aee1e3SBhupesh Sharma "ice_core_clk"; 20333834a2e9SVinod Koul clocks = 20343834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AXI_CLK>, 20353834a2e9SVinod Koul <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 20363834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AHB_CLK>, 20373834a2e9SVinod Koul <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 20383834a2e9SVinod Koul <&rpmhcc RPMH_CXO_CLK>, 20393834a2e9SVinod Koul <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 20403834a2e9SVinod Koul <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 204198aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 204298aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 20433834a2e9SVinod Koul freq-table-hz = 20443834a2e9SVinod Koul <37500000 300000000>, 20453834a2e9SVinod Koul <0 0>, 20463834a2e9SVinod Koul <0 0>, 20473834a2e9SVinod Koul <37500000 300000000>, 20483834a2e9SVinod Koul <0 0>, 20493834a2e9SVinod Koul <0 0>, 20503834a2e9SVinod Koul <0 0>, 205198aee1e3SBhupesh Sharma <0 0>, 205298aee1e3SBhupesh Sharma <0 300000000>; 20533834a2e9SVinod Koul 20543834a2e9SVinod Koul status = "disabled"; 20553834a2e9SVinod Koul }; 20563834a2e9SVinod Koul 20573834a2e9SVinod Koul ufs_mem_phy: phy@1d87000 { 20583834a2e9SVinod Koul compatible = "qcom,sm8150-qmp-ufs-phy"; 2059c79ec891SVinod Koul reg = <0 0x01d87000 0 0x1c0>; 20603834a2e9SVinod Koul #address-cells = <2>; 20613834a2e9SVinod Koul #size-cells = <2>; 20623834a2e9SVinod Koul ranges; 20633834a2e9SVinod Koul clock-names = "ref", 20643834a2e9SVinod Koul "ref_aux"; 20653834a2e9SVinod Koul clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 20663834a2e9SVinod Koul <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 20673834a2e9SVinod Koul 2068fe75b0c4SBhupesh Sharma power-domains = <&gcc UFS_PHY_GDSC>; 2069fe75b0c4SBhupesh Sharma 20703834a2e9SVinod Koul resets = <&ufs_mem_hc 0>; 20713834a2e9SVinod Koul reset-names = "ufsphy"; 20723834a2e9SVinod Koul status = "disabled"; 20733834a2e9SVinod Koul 20741351512fSShawn Guo ufs_mem_phy_lanes: phy@1d87400 { 207536a31b3aSJohan Hovold reg = <0 0x01d87400 0 0x16c>, 207636a31b3aSJohan Hovold <0 0x01d87600 0 0x200>, 207736a31b3aSJohan Hovold <0 0x01d87c00 0 0x200>, 207836a31b3aSJohan Hovold <0 0x01d87800 0 0x16c>, 207936a31b3aSJohan Hovold <0 0x01d87a00 0 0x200>; 20803834a2e9SVinod Koul #phy-cells = <0>; 20813834a2e9SVinod Koul }; 20823834a2e9SVinod Koul }; 20833834a2e9SVinod Koul 2084c752d491SKrzysztof Kozlowski tcsr_mutex: hwlock@1f40000 { 2085c752d491SKrzysztof Kozlowski compatible = "qcom,tcsr-mutex"; 208686d7c946SKrzysztof Kozlowski reg = <0x0 0x01f40000 0x0 0x20000>; 2087c752d491SKrzysztof Kozlowski #hwlock-cells = <1>; 208886d7c946SKrzysztof Kozlowski }; 208986d7c946SKrzysztof Kozlowski 2090d0909bf4SJohan Hovold tcsr_regs_1: syscon@1f60000 { 209186d7c946SKrzysztof Kozlowski compatible = "qcom,sm8150-tcsr", "syscon"; 209286d7c946SKrzysztof Kozlowski reg = <0x0 0x01f60000 0x0 0x20000>; 2093d8cf9372SVinod Koul }; 2094d8cf9372SVinod Koul 209549076351SSibi Sankar remoteproc_slpi: remoteproc@2400000 { 209649076351SSibi Sankar compatible = "qcom,sm8150-slpi-pas"; 209749076351SSibi Sankar reg = <0x0 0x02400000 0x0 0x4040>; 209849076351SSibi Sankar 209949076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 210049076351SSibi Sankar <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 210149076351SSibi Sankar <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 210249076351SSibi Sankar <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 210349076351SSibi Sankar <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 210449076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 210549076351SSibi Sankar "handover", "stop-ack"; 210649076351SSibi Sankar 210749076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 210849076351SSibi Sankar clock-names = "xo"; 210949076351SSibi Sankar 2110a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_LCX>, 2111a94ed9f3SKonrad Dybcio <&rpmhpd SM8150_LMX>; 2112d9d327f6SSibi Sankar power-domain-names = "lcx", "lmx"; 211349076351SSibi Sankar 211449076351SSibi Sankar memory-region = <&slpi_mem>; 211549076351SSibi Sankar 2116d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 2117d9d327f6SSibi Sankar 211849076351SSibi Sankar qcom,smem-states = <&slpi_smp2p_out 0>; 211949076351SSibi Sankar qcom,smem-state-names = "stop"; 212049076351SSibi Sankar 212149076351SSibi Sankar status = "disabled"; 212249076351SSibi Sankar 212349076351SSibi Sankar glink-edge { 212449076351SSibi Sankar interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 212549076351SSibi Sankar label = "dsps"; 212649076351SSibi Sankar qcom,remote-pid = <3>; 212749076351SSibi Sankar mboxes = <&apss_shared 24>; 212881729330SBhupesh Sharma 212981729330SBhupesh Sharma fastrpc { 213081729330SBhupesh Sharma compatible = "qcom,fastrpc"; 213181729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 213281729330SBhupesh Sharma label = "sdsp"; 21338c8ce95bSJeya R qcom,non-secure-domain; 213481729330SBhupesh Sharma #address-cells = <1>; 213581729330SBhupesh Sharma #size-cells = <0>; 213681729330SBhupesh Sharma 213781729330SBhupesh Sharma compute-cb@1 { 213881729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 213981729330SBhupesh Sharma reg = <1>; 214081729330SBhupesh Sharma iommus = <&apps_smmu 0x05a1 0x0>; 214181729330SBhupesh Sharma }; 214281729330SBhupesh Sharma 214381729330SBhupesh Sharma compute-cb@2 { 214481729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 214581729330SBhupesh Sharma reg = <2>; 214681729330SBhupesh Sharma iommus = <&apps_smmu 0x05a2 0x0>; 214781729330SBhupesh Sharma }; 214881729330SBhupesh Sharma 214981729330SBhupesh Sharma compute-cb@3 { 215081729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 215181729330SBhupesh Sharma reg = <3>; 215281729330SBhupesh Sharma iommus = <&apps_smmu 0x05a3 0x0>; 215381729330SBhupesh Sharma /* note: shared-cb = <4> in downstream */ 215481729330SBhupesh Sharma }; 215581729330SBhupesh Sharma }; 215649076351SSibi Sankar }; 215749076351SSibi Sankar }; 215849076351SSibi Sankar 2159f30ac26dSJonathan Marek gpu: gpu@2c00000 { 2160f30ac26dSJonathan Marek /* 2161f30ac26dSJonathan Marek * note: the amd,imageon compatible makes it possible 2162f30ac26dSJonathan Marek * to use the drm/msm driver without the display node, 2163f30ac26dSJonathan Marek * make sure to remove it when display node is added 2164f30ac26dSJonathan Marek */ 2165f30ac26dSJonathan Marek compatible = "qcom,adreno-640.1", 2166f30ac26dSJonathan Marek "qcom,adreno", 2167f30ac26dSJonathan Marek "amd,imageon"; 2168f30ac26dSJonathan Marek 2169f30ac26dSJonathan Marek reg = <0 0x02c00000 0 0x40000>; 2170f30ac26dSJonathan Marek reg-names = "kgsl_3d0_reg_memory"; 2171f30ac26dSJonathan Marek 2172f30ac26dSJonathan Marek interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2173f30ac26dSJonathan Marek 2174f30ac26dSJonathan Marek iommus = <&adreno_smmu 0 0x401>; 2175f30ac26dSJonathan Marek 2176f30ac26dSJonathan Marek operating-points-v2 = <&gpu_opp_table>; 2177f30ac26dSJonathan Marek 2178f30ac26dSJonathan Marek qcom,gmu = <&gmu>; 2179f30ac26dSJonathan Marek 2180b1dc3c6bSKonrad Dybcio status = "disabled"; 2181b1dc3c6bSKonrad Dybcio 2182f30ac26dSJonathan Marek zap-shader { 2183f30ac26dSJonathan Marek memory-region = <&gpu_mem>; 2184f30ac26dSJonathan Marek }; 2185f30ac26dSJonathan Marek 2186f30ac26dSJonathan Marek /* note: downstream checks gpu binning for 675 Mhz */ 2187f30ac26dSJonathan Marek gpu_opp_table: opp-table { 2188f30ac26dSJonathan Marek compatible = "operating-points-v2"; 2189f30ac26dSJonathan Marek 2190f30ac26dSJonathan Marek opp-675000000 { 2191f30ac26dSJonathan Marek opp-hz = /bits/ 64 <675000000>; 2192f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2193f30ac26dSJonathan Marek }; 2194f30ac26dSJonathan Marek 2195f30ac26dSJonathan Marek opp-585000000 { 2196f30ac26dSJonathan Marek opp-hz = /bits/ 64 <585000000>; 2197f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2198f30ac26dSJonathan Marek }; 2199f30ac26dSJonathan Marek 2200f30ac26dSJonathan Marek opp-499200000 { 2201f30ac26dSJonathan Marek opp-hz = /bits/ 64 <499200000>; 2202f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2203f30ac26dSJonathan Marek }; 2204f30ac26dSJonathan Marek 2205f30ac26dSJonathan Marek opp-427000000 { 2206f30ac26dSJonathan Marek opp-hz = /bits/ 64 <427000000>; 2207f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2208f30ac26dSJonathan Marek }; 2209f30ac26dSJonathan Marek 2210f30ac26dSJonathan Marek opp-345000000 { 2211f30ac26dSJonathan Marek opp-hz = /bits/ 64 <345000000>; 2212f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2213f30ac26dSJonathan Marek }; 2214f30ac26dSJonathan Marek 2215f30ac26dSJonathan Marek opp-257000000 { 2216f30ac26dSJonathan Marek opp-hz = /bits/ 64 <257000000>; 2217f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2218f30ac26dSJonathan Marek }; 2219f30ac26dSJonathan Marek }; 2220f30ac26dSJonathan Marek }; 2221f30ac26dSJonathan Marek 2222f30ac26dSJonathan Marek gmu: gmu@2c6a000 { 2223f30ac26dSJonathan Marek compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2224f30ac26dSJonathan Marek 2225f30ac26dSJonathan Marek reg = <0 0x02c6a000 0 0x30000>, 2226f30ac26dSJonathan Marek <0 0x0b290000 0 0x10000>, 2227f30ac26dSJonathan Marek <0 0x0b490000 0 0x10000>; 2228f30ac26dSJonathan Marek reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2229f30ac26dSJonathan Marek 2230f30ac26dSJonathan Marek interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2231f30ac26dSJonathan Marek <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2232f30ac26dSJonathan Marek interrupt-names = "hfi", "gmu"; 2233f30ac26dSJonathan Marek 2234f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 2235f1269916SJonathan Marek <&gpucc GPU_CC_CX_GMU_CLK>, 2236f1269916SJonathan Marek <&gpucc GPU_CC_CXO_CLK>, 2237f30ac26dSJonathan Marek <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2238f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2239f30ac26dSJonathan Marek clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2240f30ac26dSJonathan Marek 2241f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>, 2242f1269916SJonathan Marek <&gpucc GPU_GX_GDSC>; 2243f30ac26dSJonathan Marek power-domain-names = "cx", "gx"; 2244f30ac26dSJonathan Marek 2245f30ac26dSJonathan Marek iommus = <&adreno_smmu 5 0x400>; 2246f30ac26dSJonathan Marek 2247f30ac26dSJonathan Marek operating-points-v2 = <&gmu_opp_table>; 2248f30ac26dSJonathan Marek 2249b1dc3c6bSKonrad Dybcio status = "disabled"; 2250b1dc3c6bSKonrad Dybcio 2251f30ac26dSJonathan Marek gmu_opp_table: opp-table { 2252f30ac26dSJonathan Marek compatible = "operating-points-v2"; 2253f30ac26dSJonathan Marek 2254f30ac26dSJonathan Marek opp-200000000 { 2255f30ac26dSJonathan Marek opp-hz = /bits/ 64 <200000000>; 2256f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2257f30ac26dSJonathan Marek }; 2258f30ac26dSJonathan Marek }; 2259f30ac26dSJonathan Marek }; 2260f30ac26dSJonathan Marek 2261f30ac26dSJonathan Marek gpucc: clock-controller@2c90000 { 2262f30ac26dSJonathan Marek compatible = "qcom,sm8150-gpucc"; 2263f30ac26dSJonathan Marek reg = <0 0x02c90000 0 0x9000>; 2264f30ac26dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>, 2265f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2266f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2267f30ac26dSJonathan Marek clock-names = "bi_tcxo", 2268f30ac26dSJonathan Marek "gcc_gpu_gpll0_clk_src", 2269f30ac26dSJonathan Marek "gcc_gpu_gpll0_div_clk_src"; 2270f30ac26dSJonathan Marek #clock-cells = <1>; 2271f30ac26dSJonathan Marek #reset-cells = <1>; 2272f30ac26dSJonathan Marek #power-domain-cells = <1>; 2273f30ac26dSJonathan Marek }; 2274f30ac26dSJonathan Marek 2275f30ac26dSJonathan Marek adreno_smmu: iommu@2ca0000 { 22763e5c0025SKonrad Dybcio compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", 22773e5c0025SKonrad Dybcio "qcom,smmu-500", "arm,mmu-500"; 2278f30ac26dSJonathan Marek reg = <0 0x02ca0000 0 0x10000>; 2279f30ac26dSJonathan Marek #iommu-cells = <2>; 2280f30ac26dSJonathan Marek #global-interrupts = <1>; 2281f30ac26dSJonathan Marek interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2282f30ac26dSJonathan Marek <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2283f30ac26dSJonathan Marek <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2284f30ac26dSJonathan Marek <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2285f30ac26dSJonathan Marek <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2286f30ac26dSJonathan Marek <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2287f30ac26dSJonathan Marek <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2288f30ac26dSJonathan Marek <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2289f30ac26dSJonathan Marek <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2290f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 2291f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2292f30ac26dSJonathan Marek <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2293f30ac26dSJonathan Marek clock-names = "ahb", "bus", "iface"; 2294f30ac26dSJonathan Marek 2295f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>; 2296f30ac26dSJonathan Marek }; 2297f30ac26dSJonathan Marek 2298e13c6d14SVinod Koul tlmm: pinctrl@3100000 { 2299e13c6d14SVinod Koul compatible = "qcom,sm8150-pinctrl"; 2300e13c6d14SVinod Koul reg = <0x0 0x03100000 0x0 0x300000>, 2301e13c6d14SVinod Koul <0x0 0x03500000 0x0 0x300000>, 2302e13c6d14SVinod Koul <0x0 0x03900000 0x0 0x300000>, 2303e13c6d14SVinod Koul <0x0 0x03D00000 0x0 0x300000>; 2304e13c6d14SVinod Koul reg-names = "west", "east", "north", "south"; 2305e13c6d14SVinod Koul interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2306de3abdf3SShawn Guo gpio-ranges = <&tlmm 0 0 176>; 2307e13c6d14SVinod Koul gpio-controller; 2308e13c6d14SVinod Koul #gpio-cells = <2>; 2309e13c6d14SVinod Koul interrupt-controller; 2310e13c6d14SVinod Koul #interrupt-cells = <2>; 23116127d8e4SBhupesh Sharma wakeup-parent = <&pdc>; 231281bee695SCaleb Connolly 2313028fe09cSKrzysztof Kozlowski qup_i2c0_default: qup-i2c0-default-state { 231481bee695SCaleb Connolly pins = "gpio0", "gpio1"; 231581bee695SCaleb Connolly function = "qup0"; 231681bee695SCaleb Connolly drive-strength = <0x02>; 231781bee695SCaleb Connolly bias-disable; 231881bee695SCaleb Connolly }; 231981bee695SCaleb Connolly 2320028fe09cSKrzysztof Kozlowski qup_spi0_default: qup-spi0-default-state { 2321129e1c96SFelipe Balbi pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2322129e1c96SFelipe Balbi function = "qup0"; 2323129e1c96SFelipe Balbi drive-strength = <6>; 2324129e1c96SFelipe Balbi bias-disable; 2325129e1c96SFelipe Balbi }; 2326129e1c96SFelipe Balbi 2327028fe09cSKrzysztof Kozlowski qup_i2c1_default: qup-i2c1-default-state { 232881bee695SCaleb Connolly pins = "gpio114", "gpio115"; 232981bee695SCaleb Connolly function = "qup1"; 2330028fe09cSKrzysztof Kozlowski drive-strength = <2>; 233181bee695SCaleb Connolly bias-disable; 233281bee695SCaleb Connolly }; 233381bee695SCaleb Connolly 2334028fe09cSKrzysztof Kozlowski qup_spi1_default: qup-spi1-default-state { 2335129e1c96SFelipe Balbi pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2336129e1c96SFelipe Balbi function = "qup1"; 2337129e1c96SFelipe Balbi drive-strength = <6>; 2338129e1c96SFelipe Balbi bias-disable; 2339129e1c96SFelipe Balbi }; 2340129e1c96SFelipe Balbi 2341028fe09cSKrzysztof Kozlowski qup_i2c2_default: qup-i2c2-default-state { 234281bee695SCaleb Connolly pins = "gpio126", "gpio127"; 234381bee695SCaleb Connolly function = "qup2"; 2344028fe09cSKrzysztof Kozlowski drive-strength = <2>; 234581bee695SCaleb Connolly bias-disable; 234681bee695SCaleb Connolly }; 234781bee695SCaleb Connolly 2348028fe09cSKrzysztof Kozlowski qup_spi2_default: qup-spi2-default-state { 2349129e1c96SFelipe Balbi pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2350129e1c96SFelipe Balbi function = "qup2"; 2351129e1c96SFelipe Balbi drive-strength = <6>; 2352129e1c96SFelipe Balbi bias-disable; 2353129e1c96SFelipe Balbi }; 2354129e1c96SFelipe Balbi 2355028fe09cSKrzysztof Kozlowski qup_i2c3_default: qup-i2c3-default-state { 235681bee695SCaleb Connolly pins = "gpio144", "gpio145"; 235781bee695SCaleb Connolly function = "qup3"; 2358028fe09cSKrzysztof Kozlowski drive-strength = <2>; 235981bee695SCaleb Connolly bias-disable; 236081bee695SCaleb Connolly }; 236181bee695SCaleb Connolly 2362028fe09cSKrzysztof Kozlowski qup_spi3_default: qup-spi3-default-state { 2363129e1c96SFelipe Balbi pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2364129e1c96SFelipe Balbi function = "qup3"; 2365129e1c96SFelipe Balbi drive-strength = <6>; 2366129e1c96SFelipe Balbi bias-disable; 2367129e1c96SFelipe Balbi }; 2368129e1c96SFelipe Balbi 2369028fe09cSKrzysztof Kozlowski qup_i2c4_default: qup-i2c4-default-state { 237081bee695SCaleb Connolly pins = "gpio51", "gpio52"; 237181bee695SCaleb Connolly function = "qup4"; 2372028fe09cSKrzysztof Kozlowski drive-strength = <2>; 237381bee695SCaleb Connolly bias-disable; 237481bee695SCaleb Connolly }; 237581bee695SCaleb Connolly 2376028fe09cSKrzysztof Kozlowski qup_spi4_default: qup-spi4-default-state { 2377129e1c96SFelipe Balbi pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2378129e1c96SFelipe Balbi function = "qup4"; 2379129e1c96SFelipe Balbi drive-strength = <6>; 2380129e1c96SFelipe Balbi bias-disable; 2381129e1c96SFelipe Balbi }; 2382129e1c96SFelipe Balbi 2383028fe09cSKrzysztof Kozlowski qup_i2c5_default: qup-i2c5-default-state { 238481bee695SCaleb Connolly pins = "gpio121", "gpio122"; 238581bee695SCaleb Connolly function = "qup5"; 2386028fe09cSKrzysztof Kozlowski drive-strength = <2>; 238781bee695SCaleb Connolly bias-disable; 238881bee695SCaleb Connolly }; 238981bee695SCaleb Connolly 2390028fe09cSKrzysztof Kozlowski qup_spi5_default: qup-spi5-default-state { 2391129e1c96SFelipe Balbi pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2392129e1c96SFelipe Balbi function = "qup5"; 2393129e1c96SFelipe Balbi drive-strength = <6>; 2394129e1c96SFelipe Balbi bias-disable; 2395129e1c96SFelipe Balbi }; 2396129e1c96SFelipe Balbi 2397028fe09cSKrzysztof Kozlowski qup_i2c6_default: qup-i2c6-default-state { 239881bee695SCaleb Connolly pins = "gpio6", "gpio7"; 239981bee695SCaleb Connolly function = "qup6"; 2400028fe09cSKrzysztof Kozlowski drive-strength = <2>; 240181bee695SCaleb Connolly bias-disable; 240281bee695SCaleb Connolly }; 240381bee695SCaleb Connolly 2404028fe09cSKrzysztof Kozlowski qup_spi6_default: qup-spi6_default-state { 2405129e1c96SFelipe Balbi pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2406129e1c96SFelipe Balbi function = "qup6"; 2407129e1c96SFelipe Balbi drive-strength = <6>; 2408129e1c96SFelipe Balbi bias-disable; 2409129e1c96SFelipe Balbi }; 2410129e1c96SFelipe Balbi 2411028fe09cSKrzysztof Kozlowski qup_i2c7_default: qup-i2c7-default-state { 241281bee695SCaleb Connolly pins = "gpio98", "gpio99"; 241381bee695SCaleb Connolly function = "qup7"; 2414028fe09cSKrzysztof Kozlowski drive-strength = <2>; 241581bee695SCaleb Connolly bias-disable; 241681bee695SCaleb Connolly }; 241781bee695SCaleb Connolly 2418028fe09cSKrzysztof Kozlowski qup_spi7_default: qup-spi7_default-state { 2419129e1c96SFelipe Balbi pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2420129e1c96SFelipe Balbi function = "qup7"; 2421129e1c96SFelipe Balbi drive-strength = <6>; 2422129e1c96SFelipe Balbi bias-disable; 2423129e1c96SFelipe Balbi }; 2424129e1c96SFelipe Balbi 2425028fe09cSKrzysztof Kozlowski qup_i2c8_default: qup-i2c8-default-state { 242681bee695SCaleb Connolly pins = "gpio88", "gpio89"; 242781bee695SCaleb Connolly function = "qup8"; 2428028fe09cSKrzysztof Kozlowski drive-strength = <2>; 242981bee695SCaleb Connolly bias-disable; 243081bee695SCaleb Connolly }; 243181bee695SCaleb Connolly 2432028fe09cSKrzysztof Kozlowski qup_spi8_default: qup-spi8-default-state { 2433129e1c96SFelipe Balbi pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2434129e1c96SFelipe Balbi function = "qup8"; 2435129e1c96SFelipe Balbi drive-strength = <6>; 2436129e1c96SFelipe Balbi bias-disable; 2437129e1c96SFelipe Balbi }; 2438129e1c96SFelipe Balbi 2439028fe09cSKrzysztof Kozlowski qup_i2c9_default: qup-i2c9-default-state { 244081bee695SCaleb Connolly pins = "gpio39", "gpio40"; 244181bee695SCaleb Connolly function = "qup9"; 2442028fe09cSKrzysztof Kozlowski drive-strength = <2>; 244381bee695SCaleb Connolly bias-disable; 244481bee695SCaleb Connolly }; 244581bee695SCaleb Connolly 2446028fe09cSKrzysztof Kozlowski qup_spi9_default: qup-spi9-default-state { 2447129e1c96SFelipe Balbi pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2448129e1c96SFelipe Balbi function = "qup9"; 2449129e1c96SFelipe Balbi drive-strength = <6>; 2450129e1c96SFelipe Balbi bias-disable; 2451129e1c96SFelipe Balbi }; 2452129e1c96SFelipe Balbi 245310d900a8SBartosz Golaszewski qup_uart9_default: qup-uart9-default-state { 245410d900a8SBartosz Golaszewski pins = "gpio41", "gpio42"; 245510d900a8SBartosz Golaszewski function = "qup9"; 245610d900a8SBartosz Golaszewski drive-strength = <2>; 245710d900a8SBartosz Golaszewski bias-disable; 245810d900a8SBartosz Golaszewski }; 245910d900a8SBartosz Golaszewski 2460028fe09cSKrzysztof Kozlowski qup_i2c10_default: qup-i2c10-default-state { 246181bee695SCaleb Connolly pins = "gpio9", "gpio10"; 246281bee695SCaleb Connolly function = "qup10"; 2463028fe09cSKrzysztof Kozlowski drive-strength = <2>; 246481bee695SCaleb Connolly bias-disable; 246581bee695SCaleb Connolly }; 246681bee695SCaleb Connolly 2467028fe09cSKrzysztof Kozlowski qup_spi10_default: qup-spi10-default-state { 2468129e1c96SFelipe Balbi pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2469129e1c96SFelipe Balbi function = "qup10"; 2470129e1c96SFelipe Balbi drive-strength = <6>; 2471129e1c96SFelipe Balbi bias-disable; 2472129e1c96SFelipe Balbi }; 2473129e1c96SFelipe Balbi 2474028fe09cSKrzysztof Kozlowski qup_i2c11_default: qup-i2c11-default-state { 247581bee695SCaleb Connolly pins = "gpio94", "gpio95"; 247681bee695SCaleb Connolly function = "qup11"; 2477028fe09cSKrzysztof Kozlowski drive-strength = <2>; 247881bee695SCaleb Connolly bias-disable; 247981bee695SCaleb Connolly }; 248081bee695SCaleb Connolly 2481028fe09cSKrzysztof Kozlowski qup_spi11_default: qup-spi11-default-state { 2482129e1c96SFelipe Balbi pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2483129e1c96SFelipe Balbi function = "qup11"; 2484129e1c96SFelipe Balbi drive-strength = <6>; 2485129e1c96SFelipe Balbi bias-disable; 2486129e1c96SFelipe Balbi }; 2487129e1c96SFelipe Balbi 2488028fe09cSKrzysztof Kozlowski qup_i2c12_default: qup-i2c12-default-state { 248981bee695SCaleb Connolly pins = "gpio83", "gpio84"; 249081bee695SCaleb Connolly function = "qup12"; 2491028fe09cSKrzysztof Kozlowski drive-strength = <2>; 249281bee695SCaleb Connolly bias-disable; 249381bee695SCaleb Connolly }; 249481bee695SCaleb Connolly 2495028fe09cSKrzysztof Kozlowski qup_spi12_default: qup-spi12-default-state { 2496129e1c96SFelipe Balbi pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2497129e1c96SFelipe Balbi function = "qup12"; 2498129e1c96SFelipe Balbi drive-strength = <6>; 2499129e1c96SFelipe Balbi bias-disable; 2500129e1c96SFelipe Balbi }; 2501129e1c96SFelipe Balbi 2502028fe09cSKrzysztof Kozlowski qup_i2c13_default: qup-i2c13-default-state { 250381bee695SCaleb Connolly pins = "gpio43", "gpio44"; 250481bee695SCaleb Connolly function = "qup13"; 2505028fe09cSKrzysztof Kozlowski drive-strength = <2>; 250681bee695SCaleb Connolly bias-disable; 250781bee695SCaleb Connolly }; 250881bee695SCaleb Connolly 2509028fe09cSKrzysztof Kozlowski qup_spi13_default: qup-spi13-default-state { 2510129e1c96SFelipe Balbi pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2511129e1c96SFelipe Balbi function = "qup13"; 2512129e1c96SFelipe Balbi drive-strength = <6>; 2513129e1c96SFelipe Balbi bias-disable; 2514129e1c96SFelipe Balbi }; 2515129e1c96SFelipe Balbi 2516028fe09cSKrzysztof Kozlowski qup_i2c14_default: qup-i2c14-default-state { 251781bee695SCaleb Connolly pins = "gpio47", "gpio48"; 251881bee695SCaleb Connolly function = "qup14"; 2519028fe09cSKrzysztof Kozlowski drive-strength = <2>; 252081bee695SCaleb Connolly bias-disable; 252181bee695SCaleb Connolly }; 252281bee695SCaleb Connolly 2523028fe09cSKrzysztof Kozlowski qup_spi14_default: qup-spi14-default-state { 2524129e1c96SFelipe Balbi pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2525129e1c96SFelipe Balbi function = "qup14"; 2526129e1c96SFelipe Balbi drive-strength = <6>; 2527129e1c96SFelipe Balbi bias-disable; 2528129e1c96SFelipe Balbi }; 2529129e1c96SFelipe Balbi 2530028fe09cSKrzysztof Kozlowski qup_i2c15_default: qup-i2c15-default-state { 253181bee695SCaleb Connolly pins = "gpio27", "gpio28"; 253281bee695SCaleb Connolly function = "qup15"; 2533028fe09cSKrzysztof Kozlowski drive-strength = <2>; 253481bee695SCaleb Connolly bias-disable; 253581bee695SCaleb Connolly }; 253681bee695SCaleb Connolly 2537028fe09cSKrzysztof Kozlowski qup_spi15_default: qup-spi15-default-state { 2538129e1c96SFelipe Balbi pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2539129e1c96SFelipe Balbi function = "qup15"; 2540129e1c96SFelipe Balbi drive-strength = <6>; 2541129e1c96SFelipe Balbi bias-disable; 2542129e1c96SFelipe Balbi }; 2543129e1c96SFelipe Balbi 2544028fe09cSKrzysztof Kozlowski qup_i2c16_default: qup-i2c16-default-state { 254581bee695SCaleb Connolly pins = "gpio86", "gpio85"; 254681bee695SCaleb Connolly function = "qup16"; 2547028fe09cSKrzysztof Kozlowski drive-strength = <2>; 254881bee695SCaleb Connolly bias-disable; 254981bee695SCaleb Connolly }; 255081bee695SCaleb Connolly 2551028fe09cSKrzysztof Kozlowski qup_spi16_default: qup-spi16-default-state { 2552129e1c96SFelipe Balbi pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2553129e1c96SFelipe Balbi function = "qup16"; 2554129e1c96SFelipe Balbi drive-strength = <6>; 2555129e1c96SFelipe Balbi bias-disable; 2556129e1c96SFelipe Balbi }; 2557129e1c96SFelipe Balbi 2558028fe09cSKrzysztof Kozlowski qup_i2c17_default: qup-i2c17-default-state { 255981bee695SCaleb Connolly pins = "gpio55", "gpio56"; 256081bee695SCaleb Connolly function = "qup17"; 2561028fe09cSKrzysztof Kozlowski drive-strength = <2>; 256281bee695SCaleb Connolly bias-disable; 256381bee695SCaleb Connolly }; 256481bee695SCaleb Connolly 2565028fe09cSKrzysztof Kozlowski qup_spi17_default: qup-spi17-default-state { 2566129e1c96SFelipe Balbi pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2567129e1c96SFelipe Balbi function = "qup17"; 2568129e1c96SFelipe Balbi drive-strength = <6>; 2569129e1c96SFelipe Balbi bias-disable; 2570129e1c96SFelipe Balbi }; 2571129e1c96SFelipe Balbi 2572028fe09cSKrzysztof Kozlowski qup_i2c18_default: qup-i2c18-default-state { 257381bee695SCaleb Connolly pins = "gpio23", "gpio24"; 257481bee695SCaleb Connolly function = "qup18"; 2575028fe09cSKrzysztof Kozlowski drive-strength = <2>; 257681bee695SCaleb Connolly bias-disable; 257781bee695SCaleb Connolly }; 257881bee695SCaleb Connolly 2579028fe09cSKrzysztof Kozlowski qup_spi18_default: qup-spi18-default-state { 2580129e1c96SFelipe Balbi pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2581129e1c96SFelipe Balbi function = "qup18"; 2582129e1c96SFelipe Balbi drive-strength = <6>; 2583129e1c96SFelipe Balbi bias-disable; 2584129e1c96SFelipe Balbi }; 2585129e1c96SFelipe Balbi 2586028fe09cSKrzysztof Kozlowski qup_i2c19_default: qup-i2c19-default-state { 258781bee695SCaleb Connolly pins = "gpio57", "gpio58"; 258881bee695SCaleb Connolly function = "qup19"; 2589028fe09cSKrzysztof Kozlowski drive-strength = <2>; 259081bee695SCaleb Connolly bias-disable; 259181bee695SCaleb Connolly }; 2592129e1c96SFelipe Balbi 2593028fe09cSKrzysztof Kozlowski qup_spi19_default: qup-spi19-default-state { 2594129e1c96SFelipe Balbi pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2595129e1c96SFelipe Balbi function = "qup19"; 2596129e1c96SFelipe Balbi drive-strength = <6>; 2597129e1c96SFelipe Balbi bias-disable; 2598129e1c96SFelipe Balbi }; 2599a1c86c68SBhupesh Sharma 2600028fe09cSKrzysztof Kozlowski pcie0_default_state: pcie0-default-state { 2601028fe09cSKrzysztof Kozlowski perst-pins { 2602a1c86c68SBhupesh Sharma pins = "gpio35"; 2603a1c86c68SBhupesh Sharma function = "gpio"; 2604a1c86c68SBhupesh Sharma drive-strength = <2>; 2605a1c86c68SBhupesh Sharma bias-pull-down; 2606a1c86c68SBhupesh Sharma }; 2607a1c86c68SBhupesh Sharma 2608028fe09cSKrzysztof Kozlowski clkreq-pins { 2609a1c86c68SBhupesh Sharma pins = "gpio36"; 2610a1c86c68SBhupesh Sharma function = "pci_e0"; 2611a1c86c68SBhupesh Sharma drive-strength = <2>; 2612a1c86c68SBhupesh Sharma bias-pull-up; 2613a1c86c68SBhupesh Sharma }; 2614a1c86c68SBhupesh Sharma 2615028fe09cSKrzysztof Kozlowski wake-pins { 2616a1c86c68SBhupesh Sharma pins = "gpio37"; 2617a1c86c68SBhupesh Sharma function = "gpio"; 2618a1c86c68SBhupesh Sharma drive-strength = <2>; 2619a1c86c68SBhupesh Sharma bias-pull-up; 2620a1c86c68SBhupesh Sharma }; 2621a1c86c68SBhupesh Sharma }; 2622a1c86c68SBhupesh Sharma 2623028fe09cSKrzysztof Kozlowski pcie1_default_state: pcie1-default-state { 2624028fe09cSKrzysztof Kozlowski perst-pins { 2625a1c86c68SBhupesh Sharma pins = "gpio102"; 2626a1c86c68SBhupesh Sharma function = "gpio"; 2627a1c86c68SBhupesh Sharma drive-strength = <2>; 2628a1c86c68SBhupesh Sharma bias-pull-down; 2629a1c86c68SBhupesh Sharma }; 2630a1c86c68SBhupesh Sharma 2631028fe09cSKrzysztof Kozlowski clkreq-pins { 2632a1c86c68SBhupesh Sharma pins = "gpio103"; 2633a1c86c68SBhupesh Sharma function = "pci_e1"; 2634a1c86c68SBhupesh Sharma drive-strength = <2>; 2635a1c86c68SBhupesh Sharma bias-pull-up; 2636a1c86c68SBhupesh Sharma }; 2637a1c86c68SBhupesh Sharma 2638028fe09cSKrzysztof Kozlowski wake-pins { 2639a1c86c68SBhupesh Sharma pins = "gpio104"; 2640a1c86c68SBhupesh Sharma function = "gpio"; 2641a1c86c68SBhupesh Sharma drive-strength = <2>; 2642a1c86c68SBhupesh Sharma bias-pull-up; 2643a1c86c68SBhupesh Sharma }; 2644a1c86c68SBhupesh Sharma }; 2645e13c6d14SVinod Koul }; 2646e13c6d14SVinod Koul 264749076351SSibi Sankar remoteproc_mpss: remoteproc@4080000 { 264849076351SSibi Sankar compatible = "qcom,sm8150-mpss-pas"; 264949076351SSibi Sankar reg = <0x0 0x04080000 0x0 0x4040>; 265049076351SSibi Sankar 265149076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 265249076351SSibi Sankar <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 265349076351SSibi Sankar <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 265449076351SSibi Sankar <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 265549076351SSibi Sankar <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 265649076351SSibi Sankar <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 265749076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", "handover", 265849076351SSibi Sankar "stop-ack", "shutdown-ack"; 265949076351SSibi Sankar 266049076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 266149076351SSibi Sankar clock-names = "xo"; 266249076351SSibi Sankar 2663a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_CX>, 2664a94ed9f3SKonrad Dybcio <&rpmhpd SM8150_MSS>; 2665d9d327f6SSibi Sankar power-domain-names = "cx", "mss"; 266649076351SSibi Sankar 266749076351SSibi Sankar memory-region = <&mpss_mem>; 266849076351SSibi Sankar 2669d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 2670d9d327f6SSibi Sankar 267149076351SSibi Sankar qcom,smem-states = <&modem_smp2p_out 0>; 267249076351SSibi Sankar qcom,smem-state-names = "stop"; 267349076351SSibi Sankar 2674b1dc3c6bSKonrad Dybcio status = "disabled"; 2675b1dc3c6bSKonrad Dybcio 267649076351SSibi Sankar glink-edge { 267749076351SSibi Sankar interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 267849076351SSibi Sankar label = "modem"; 267949076351SSibi Sankar qcom,remote-pid = <1>; 268049076351SSibi Sankar mboxes = <&apss_shared 12>; 268149076351SSibi Sankar }; 268249076351SSibi Sankar }; 268349076351SSibi Sankar 268424244cefSSai Prakash Ranjan stm@6002000 { 268524244cefSSai Prakash Ranjan compatible = "arm,coresight-stm", "arm,primecell"; 268624244cefSSai Prakash Ranjan reg = <0 0x06002000 0 0x1000>, 268724244cefSSai Prakash Ranjan <0 0x16280000 0 0x180000>; 268824244cefSSai Prakash Ranjan reg-names = "stm-base", "stm-stimulus-base"; 268924244cefSSai Prakash Ranjan 269024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 269124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 269224244cefSSai Prakash Ranjan 269324244cefSSai Prakash Ranjan out-ports { 269424244cefSSai Prakash Ranjan port { 269524244cefSSai Prakash Ranjan stm_out: endpoint { 269624244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_in7>; 269724244cefSSai Prakash Ranjan }; 269824244cefSSai Prakash Ranjan }; 269924244cefSSai Prakash Ranjan }; 270024244cefSSai Prakash Ranjan }; 270124244cefSSai Prakash Ranjan 270224244cefSSai Prakash Ranjan funnel@6041000 { 270324244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 270424244cefSSai Prakash Ranjan reg = <0 0x06041000 0 0x1000>; 270524244cefSSai Prakash Ranjan 270624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 270724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 270824244cefSSai Prakash Ranjan 270924244cefSSai Prakash Ranjan out-ports { 271024244cefSSai Prakash Ranjan port { 271124244cefSSai Prakash Ranjan funnel0_out: endpoint { 271224244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in0>; 271324244cefSSai Prakash Ranjan }; 271424244cefSSai Prakash Ranjan }; 271524244cefSSai Prakash Ranjan }; 271624244cefSSai Prakash Ranjan 271724244cefSSai Prakash Ranjan in-ports { 271824244cefSSai Prakash Ranjan #address-cells = <1>; 271924244cefSSai Prakash Ranjan #size-cells = <0>; 272024244cefSSai Prakash Ranjan 272124244cefSSai Prakash Ranjan port@7 { 272224244cefSSai Prakash Ranjan reg = <7>; 272324244cefSSai Prakash Ranjan funnel0_in7: endpoint { 272424244cefSSai Prakash Ranjan remote-endpoint = <&stm_out>; 272524244cefSSai Prakash Ranjan }; 272624244cefSSai Prakash Ranjan }; 272724244cefSSai Prakash Ranjan }; 272824244cefSSai Prakash Ranjan }; 272924244cefSSai Prakash Ranjan 273024244cefSSai Prakash Ranjan funnel@6042000 { 273124244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 273224244cefSSai Prakash Ranjan reg = <0 0x06042000 0 0x1000>; 273324244cefSSai Prakash Ranjan 273424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 273524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 273624244cefSSai Prakash Ranjan 273724244cefSSai Prakash Ranjan out-ports { 273824244cefSSai Prakash Ranjan port { 273924244cefSSai Prakash Ranjan funnel1_out: endpoint { 274024244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in1>; 274124244cefSSai Prakash Ranjan }; 274224244cefSSai Prakash Ranjan }; 274324244cefSSai Prakash Ranjan }; 274424244cefSSai Prakash Ranjan 274524244cefSSai Prakash Ranjan in-ports { 274624244cefSSai Prakash Ranjan #address-cells = <1>; 274724244cefSSai Prakash Ranjan #size-cells = <0>; 274824244cefSSai Prakash Ranjan 274924244cefSSai Prakash Ranjan port@4 { 275024244cefSSai Prakash Ranjan reg = <4>; 275124244cefSSai Prakash Ranjan funnel1_in4: endpoint { 275224244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_out>; 275324244cefSSai Prakash Ranjan }; 275424244cefSSai Prakash Ranjan }; 275524244cefSSai Prakash Ranjan }; 275624244cefSSai Prakash Ranjan }; 275724244cefSSai Prakash Ranjan 275824244cefSSai Prakash Ranjan funnel@6043000 { 275924244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 276024244cefSSai Prakash Ranjan reg = <0 0x06043000 0 0x1000>; 276124244cefSSai Prakash Ranjan 276224244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 276324244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 276424244cefSSai Prakash Ranjan 276524244cefSSai Prakash Ranjan out-ports { 276624244cefSSai Prakash Ranjan port { 276724244cefSSai Prakash Ranjan funnel2_out: endpoint { 276824244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in2>; 276924244cefSSai Prakash Ranjan }; 277024244cefSSai Prakash Ranjan }; 277124244cefSSai Prakash Ranjan }; 277224244cefSSai Prakash Ranjan 277324244cefSSai Prakash Ranjan in-ports { 277424244cefSSai Prakash Ranjan #address-cells = <1>; 277524244cefSSai Prakash Ranjan #size-cells = <0>; 277624244cefSSai Prakash Ranjan 277724244cefSSai Prakash Ranjan port@2 { 277824244cefSSai Prakash Ranjan reg = <2>; 277924244cefSSai Prakash Ranjan funnel2_in2: endpoint { 278024244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_out>; 278124244cefSSai Prakash Ranjan }; 278224244cefSSai Prakash Ranjan }; 278324244cefSSai Prakash Ranjan }; 278424244cefSSai Prakash Ranjan }; 278524244cefSSai Prakash Ranjan 278624244cefSSai Prakash Ranjan funnel@6045000 { 278724244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 278824244cefSSai Prakash Ranjan reg = <0 0x06045000 0 0x1000>; 278924244cefSSai Prakash Ranjan 279024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 279124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 279224244cefSSai Prakash Ranjan 279324244cefSSai Prakash Ranjan out-ports { 279424244cefSSai Prakash Ranjan port { 279524244cefSSai Prakash Ranjan merge_funnel_out: endpoint { 279624244cefSSai Prakash Ranjan remote-endpoint = <&etf_in>; 279724244cefSSai Prakash Ranjan }; 279824244cefSSai Prakash Ranjan }; 279924244cefSSai Prakash Ranjan }; 280024244cefSSai Prakash Ranjan 280124244cefSSai Prakash Ranjan in-ports { 280224244cefSSai Prakash Ranjan #address-cells = <1>; 280324244cefSSai Prakash Ranjan #size-cells = <0>; 280424244cefSSai Prakash Ranjan 280524244cefSSai Prakash Ranjan port@0 { 280624244cefSSai Prakash Ranjan reg = <0>; 280724244cefSSai Prakash Ranjan merge_funnel_in0: endpoint { 280824244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_out>; 280924244cefSSai Prakash Ranjan }; 281024244cefSSai Prakash Ranjan }; 281124244cefSSai Prakash Ranjan 281224244cefSSai Prakash Ranjan port@1 { 281324244cefSSai Prakash Ranjan reg = <1>; 281424244cefSSai Prakash Ranjan merge_funnel_in1: endpoint { 281524244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_out>; 281624244cefSSai Prakash Ranjan }; 281724244cefSSai Prakash Ranjan }; 281824244cefSSai Prakash Ranjan 281924244cefSSai Prakash Ranjan port@2 { 282024244cefSSai Prakash Ranjan reg = <2>; 282124244cefSSai Prakash Ranjan merge_funnel_in2: endpoint { 282224244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_out>; 282324244cefSSai Prakash Ranjan }; 282424244cefSSai Prakash Ranjan }; 282524244cefSSai Prakash Ranjan }; 282624244cefSSai Prakash Ranjan }; 282724244cefSSai Prakash Ranjan 282824244cefSSai Prakash Ranjan replicator@6046000 { 282924244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 283024244cefSSai Prakash Ranjan reg = <0 0x06046000 0 0x1000>; 283124244cefSSai Prakash Ranjan 283224244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 283324244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 283424244cefSSai Prakash Ranjan 283524244cefSSai Prakash Ranjan out-ports { 283624244cefSSai Prakash Ranjan #address-cells = <1>; 283724244cefSSai Prakash Ranjan #size-cells = <0>; 283824244cefSSai Prakash Ranjan 283924244cefSSai Prakash Ranjan port@0 { 284024244cefSSai Prakash Ranjan reg = <0>; 284124244cefSSai Prakash Ranjan replicator_out0: endpoint { 284224244cefSSai Prakash Ranjan remote-endpoint = <&etr_in>; 284324244cefSSai Prakash Ranjan }; 284424244cefSSai Prakash Ranjan }; 284524244cefSSai Prakash Ranjan 284624244cefSSai Prakash Ranjan port@1 { 284724244cefSSai Prakash Ranjan reg = <1>; 284824244cefSSai Prakash Ranjan replicator_out1: endpoint { 284924244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_in>; 285024244cefSSai Prakash Ranjan }; 285124244cefSSai Prakash Ranjan }; 285224244cefSSai Prakash Ranjan }; 285324244cefSSai Prakash Ranjan 285424244cefSSai Prakash Ranjan in-ports { 285524244cefSSai Prakash Ranjan port { 285624244cefSSai Prakash Ranjan replicator_in0: endpoint { 285724244cefSSai Prakash Ranjan remote-endpoint = <&etf_out>; 285824244cefSSai Prakash Ranjan }; 285924244cefSSai Prakash Ranjan }; 286024244cefSSai Prakash Ranjan }; 286124244cefSSai Prakash Ranjan }; 286224244cefSSai Prakash Ranjan 286324244cefSSai Prakash Ranjan etf@6047000 { 286424244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 286524244cefSSai Prakash Ranjan reg = <0 0x06047000 0 0x1000>; 286624244cefSSai Prakash Ranjan 286724244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 286824244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 286924244cefSSai Prakash Ranjan 287024244cefSSai Prakash Ranjan out-ports { 287124244cefSSai Prakash Ranjan port { 287224244cefSSai Prakash Ranjan etf_out: endpoint { 287324244cefSSai Prakash Ranjan remote-endpoint = <&replicator_in0>; 287424244cefSSai Prakash Ranjan }; 287524244cefSSai Prakash Ranjan }; 287624244cefSSai Prakash Ranjan }; 287724244cefSSai Prakash Ranjan 287824244cefSSai Prakash Ranjan in-ports { 287924244cefSSai Prakash Ranjan port { 288024244cefSSai Prakash Ranjan etf_in: endpoint { 288124244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_out>; 288224244cefSSai Prakash Ranjan }; 288324244cefSSai Prakash Ranjan }; 288424244cefSSai Prakash Ranjan }; 288524244cefSSai Prakash Ranjan }; 288624244cefSSai Prakash Ranjan 288724244cefSSai Prakash Ranjan etr@6048000 { 288824244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 288924244cefSSai Prakash Ranjan reg = <0 0x06048000 0 0x1000>; 289024244cefSSai Prakash Ranjan iommus = <&apps_smmu 0x05e0 0x0>; 289124244cefSSai Prakash Ranjan 289224244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 289324244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 289424244cefSSai Prakash Ranjan arm,scatter-gather; 289524244cefSSai Prakash Ranjan 289624244cefSSai Prakash Ranjan in-ports { 289724244cefSSai Prakash Ranjan port { 289824244cefSSai Prakash Ranjan etr_in: endpoint { 289924244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out0>; 290024244cefSSai Prakash Ranjan }; 290124244cefSSai Prakash Ranjan }; 290224244cefSSai Prakash Ranjan }; 290324244cefSSai Prakash Ranjan }; 290424244cefSSai Prakash Ranjan 290524244cefSSai Prakash Ranjan replicator@604a000 { 290624244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 290724244cefSSai Prakash Ranjan reg = <0 0x0604a000 0 0x1000>; 290824244cefSSai Prakash Ranjan 290924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 291024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 291124244cefSSai Prakash Ranjan 291224244cefSSai Prakash Ranjan out-ports { 291324244cefSSai Prakash Ranjan #address-cells = <1>; 291424244cefSSai Prakash Ranjan #size-cells = <0>; 291524244cefSSai Prakash Ranjan 291624244cefSSai Prakash Ranjan port@1 { 291724244cefSSai Prakash Ranjan reg = <1>; 291824244cefSSai Prakash Ranjan replicator1_out: endpoint { 291924244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_in>; 292024244cefSSai Prakash Ranjan }; 292124244cefSSai Prakash Ranjan }; 292224244cefSSai Prakash Ranjan }; 292324244cefSSai Prakash Ranjan 292424244cefSSai Prakash Ranjan in-ports { 292524244cefSSai Prakash Ranjan #address-cells = <1>; 292624244cefSSai Prakash Ranjan #size-cells = <0>; 292724244cefSSai Prakash Ranjan 292824244cefSSai Prakash Ranjan port@1 { 292924244cefSSai Prakash Ranjan reg = <1>; 293024244cefSSai Prakash Ranjan replicator1_in: endpoint { 293124244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out1>; 293224244cefSSai Prakash Ranjan }; 293324244cefSSai Prakash Ranjan }; 293424244cefSSai Prakash Ranjan }; 293524244cefSSai Prakash Ranjan }; 293624244cefSSai Prakash Ranjan 293724244cefSSai Prakash Ranjan funnel@6b08000 { 293824244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 293924244cefSSai Prakash Ranjan reg = <0 0x06b08000 0 0x1000>; 294024244cefSSai Prakash Ranjan 294124244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 294224244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 294324244cefSSai Prakash Ranjan 294424244cefSSai Prakash Ranjan out-ports { 294524244cefSSai Prakash Ranjan port { 294624244cefSSai Prakash Ranjan swao_funnel_out: endpoint { 294724244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_in>; 294824244cefSSai Prakash Ranjan }; 294924244cefSSai Prakash Ranjan }; 295024244cefSSai Prakash Ranjan }; 295124244cefSSai Prakash Ranjan 295224244cefSSai Prakash Ranjan in-ports { 295324244cefSSai Prakash Ranjan #address-cells = <1>; 295424244cefSSai Prakash Ranjan #size-cells = <0>; 295524244cefSSai Prakash Ranjan 295624244cefSSai Prakash Ranjan port@6 { 295724244cefSSai Prakash Ranjan reg = <6>; 295824244cefSSai Prakash Ranjan swao_funnel_in: endpoint { 295924244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_out>; 296024244cefSSai Prakash Ranjan }; 296124244cefSSai Prakash Ranjan }; 296224244cefSSai Prakash Ranjan }; 296324244cefSSai Prakash Ranjan }; 296424244cefSSai Prakash Ranjan 296524244cefSSai Prakash Ranjan etf@6b09000 { 296624244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 296724244cefSSai Prakash Ranjan reg = <0 0x06b09000 0 0x1000>; 296824244cefSSai Prakash Ranjan 296924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 297024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 297124244cefSSai Prakash Ranjan 297224244cefSSai Prakash Ranjan out-ports { 297324244cefSSai Prakash Ranjan port { 297424244cefSSai Prakash Ranjan swao_etf_out: endpoint { 297524244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_in>; 297624244cefSSai Prakash Ranjan }; 297724244cefSSai Prakash Ranjan }; 297824244cefSSai Prakash Ranjan }; 297924244cefSSai Prakash Ranjan 298024244cefSSai Prakash Ranjan in-ports { 298124244cefSSai Prakash Ranjan port { 298224244cefSSai Prakash Ranjan swao_etf_in: endpoint { 298324244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_out>; 298424244cefSSai Prakash Ranjan }; 298524244cefSSai Prakash Ranjan }; 298624244cefSSai Prakash Ranjan }; 298724244cefSSai Prakash Ranjan }; 298824244cefSSai Prakash Ranjan 298924244cefSSai Prakash Ranjan replicator@6b0a000 { 299024244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 299124244cefSSai Prakash Ranjan reg = <0 0x06b0a000 0 0x1000>; 299224244cefSSai Prakash Ranjan 299324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 299424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 299524244cefSSai Prakash Ranjan qcom,replicator-loses-context; 299624244cefSSai Prakash Ranjan 299724244cefSSai Prakash Ranjan out-ports { 299824244cefSSai Prakash Ranjan port { 299924244cefSSai Prakash Ranjan swao_replicator_out: endpoint { 300024244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_in4>; 300124244cefSSai Prakash Ranjan }; 300224244cefSSai Prakash Ranjan }; 300324244cefSSai Prakash Ranjan }; 300424244cefSSai Prakash Ranjan 300524244cefSSai Prakash Ranjan in-ports { 300624244cefSSai Prakash Ranjan port { 300724244cefSSai Prakash Ranjan swao_replicator_in: endpoint { 300824244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_out>; 300924244cefSSai Prakash Ranjan }; 301024244cefSSai Prakash Ranjan }; 301124244cefSSai Prakash Ranjan }; 301224244cefSSai Prakash Ranjan }; 301324244cefSSai Prakash Ranjan 301424244cefSSai Prakash Ranjan etm@7040000 { 301524244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 301624244cefSSai Prakash Ranjan reg = <0 0x07040000 0 0x1000>; 301724244cefSSai Prakash Ranjan 301824244cefSSai Prakash Ranjan cpu = <&CPU0>; 301924244cefSSai Prakash Ranjan 302024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 302124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 302224244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 302324244cefSSai Prakash Ranjan qcom,skip-power-up; 302424244cefSSai Prakash Ranjan 302524244cefSSai Prakash Ranjan out-ports { 302624244cefSSai Prakash Ranjan port { 302724244cefSSai Prakash Ranjan etm0_out: endpoint { 302824244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in0>; 302924244cefSSai Prakash Ranjan }; 303024244cefSSai Prakash Ranjan }; 303124244cefSSai Prakash Ranjan }; 303224244cefSSai Prakash Ranjan }; 303324244cefSSai Prakash Ranjan 303424244cefSSai Prakash Ranjan etm@7140000 { 303524244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 303624244cefSSai Prakash Ranjan reg = <0 0x07140000 0 0x1000>; 303724244cefSSai Prakash Ranjan 303824244cefSSai Prakash Ranjan cpu = <&CPU1>; 303924244cefSSai Prakash Ranjan 304024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 304124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 304224244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 304324244cefSSai Prakash Ranjan qcom,skip-power-up; 304424244cefSSai Prakash Ranjan 304524244cefSSai Prakash Ranjan out-ports { 304624244cefSSai Prakash Ranjan port { 304724244cefSSai Prakash Ranjan etm1_out: endpoint { 304824244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in1>; 304924244cefSSai Prakash Ranjan }; 305024244cefSSai Prakash Ranjan }; 305124244cefSSai Prakash Ranjan }; 305224244cefSSai Prakash Ranjan }; 305324244cefSSai Prakash Ranjan 305424244cefSSai Prakash Ranjan etm@7240000 { 305524244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 305624244cefSSai Prakash Ranjan reg = <0 0x07240000 0 0x1000>; 305724244cefSSai Prakash Ranjan 305824244cefSSai Prakash Ranjan cpu = <&CPU2>; 305924244cefSSai Prakash Ranjan 306024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 306124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 306224244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 306324244cefSSai Prakash Ranjan qcom,skip-power-up; 306424244cefSSai Prakash Ranjan 306524244cefSSai Prakash Ranjan out-ports { 306624244cefSSai Prakash Ranjan port { 306724244cefSSai Prakash Ranjan etm2_out: endpoint { 306824244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in2>; 306924244cefSSai Prakash Ranjan }; 307024244cefSSai Prakash Ranjan }; 307124244cefSSai Prakash Ranjan }; 307224244cefSSai Prakash Ranjan }; 307324244cefSSai Prakash Ranjan 307424244cefSSai Prakash Ranjan etm@7340000 { 307524244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 307624244cefSSai Prakash Ranjan reg = <0 0x07340000 0 0x1000>; 307724244cefSSai Prakash Ranjan 307824244cefSSai Prakash Ranjan cpu = <&CPU3>; 307924244cefSSai Prakash Ranjan 308024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 308124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 308224244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 308324244cefSSai Prakash Ranjan qcom,skip-power-up; 308424244cefSSai Prakash Ranjan 308524244cefSSai Prakash Ranjan out-ports { 308624244cefSSai Prakash Ranjan port { 308724244cefSSai Prakash Ranjan etm3_out: endpoint { 308824244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in3>; 308924244cefSSai Prakash Ranjan }; 309024244cefSSai Prakash Ranjan }; 309124244cefSSai Prakash Ranjan }; 309224244cefSSai Prakash Ranjan }; 309324244cefSSai Prakash Ranjan 309424244cefSSai Prakash Ranjan etm@7440000 { 309524244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 309624244cefSSai Prakash Ranjan reg = <0 0x07440000 0 0x1000>; 309724244cefSSai Prakash Ranjan 309824244cefSSai Prakash Ranjan cpu = <&CPU4>; 309924244cefSSai Prakash Ranjan 310024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 310124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 310224244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 310324244cefSSai Prakash Ranjan qcom,skip-power-up; 310424244cefSSai Prakash Ranjan 310524244cefSSai Prakash Ranjan out-ports { 310624244cefSSai Prakash Ranjan port { 310724244cefSSai Prakash Ranjan etm4_out: endpoint { 310824244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in4>; 310924244cefSSai Prakash Ranjan }; 311024244cefSSai Prakash Ranjan }; 311124244cefSSai Prakash Ranjan }; 311224244cefSSai Prakash Ranjan }; 311324244cefSSai Prakash Ranjan 311424244cefSSai Prakash Ranjan etm@7540000 { 311524244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 311624244cefSSai Prakash Ranjan reg = <0 0x07540000 0 0x1000>; 311724244cefSSai Prakash Ranjan 311824244cefSSai Prakash Ranjan cpu = <&CPU5>; 311924244cefSSai Prakash Ranjan 312024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 312124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 312224244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 312324244cefSSai Prakash Ranjan qcom,skip-power-up; 312424244cefSSai Prakash Ranjan 312524244cefSSai Prakash Ranjan out-ports { 312624244cefSSai Prakash Ranjan port { 312724244cefSSai Prakash Ranjan etm5_out: endpoint { 312824244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in5>; 312924244cefSSai Prakash Ranjan }; 313024244cefSSai Prakash Ranjan }; 313124244cefSSai Prakash Ranjan }; 313224244cefSSai Prakash Ranjan }; 313324244cefSSai Prakash Ranjan 313424244cefSSai Prakash Ranjan etm@7640000 { 313524244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 313624244cefSSai Prakash Ranjan reg = <0 0x07640000 0 0x1000>; 313724244cefSSai Prakash Ranjan 313824244cefSSai Prakash Ranjan cpu = <&CPU6>; 313924244cefSSai Prakash Ranjan 314024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 314124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 314224244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 314324244cefSSai Prakash Ranjan qcom,skip-power-up; 314424244cefSSai Prakash Ranjan 314524244cefSSai Prakash Ranjan out-ports { 314624244cefSSai Prakash Ranjan port { 314724244cefSSai Prakash Ranjan etm6_out: endpoint { 314824244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in6>; 314924244cefSSai Prakash Ranjan }; 315024244cefSSai Prakash Ranjan }; 315124244cefSSai Prakash Ranjan }; 315224244cefSSai Prakash Ranjan }; 315324244cefSSai Prakash Ranjan 315424244cefSSai Prakash Ranjan etm@7740000 { 315524244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 315624244cefSSai Prakash Ranjan reg = <0 0x07740000 0 0x1000>; 315724244cefSSai Prakash Ranjan 315824244cefSSai Prakash Ranjan cpu = <&CPU7>; 315924244cefSSai Prakash Ranjan 316024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 316124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 316224244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 316324244cefSSai Prakash Ranjan qcom,skip-power-up; 316424244cefSSai Prakash Ranjan 316524244cefSSai Prakash Ranjan out-ports { 316624244cefSSai Prakash Ranjan port { 316724244cefSSai Prakash Ranjan etm7_out: endpoint { 316824244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in7>; 316924244cefSSai Prakash Ranjan }; 317024244cefSSai Prakash Ranjan }; 317124244cefSSai Prakash Ranjan }; 317224244cefSSai Prakash Ranjan }; 317324244cefSSai Prakash Ranjan 317424244cefSSai Prakash Ranjan funnel@7800000 { /* APSS Funnel */ 317524244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 317624244cefSSai Prakash Ranjan reg = <0 0x07800000 0 0x1000>; 317724244cefSSai Prakash Ranjan 317824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 317924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 318024244cefSSai Prakash Ranjan 318124244cefSSai Prakash Ranjan out-ports { 318224244cefSSai Prakash Ranjan port { 318324244cefSSai Prakash Ranjan apss_funnel_out: endpoint { 318424244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_in>; 318524244cefSSai Prakash Ranjan }; 318624244cefSSai Prakash Ranjan }; 318724244cefSSai Prakash Ranjan }; 318824244cefSSai Prakash Ranjan 318924244cefSSai Prakash Ranjan in-ports { 319024244cefSSai Prakash Ranjan #address-cells = <1>; 319124244cefSSai Prakash Ranjan #size-cells = <0>; 319224244cefSSai Prakash Ranjan 319324244cefSSai Prakash Ranjan port@0 { 319424244cefSSai Prakash Ranjan reg = <0>; 319524244cefSSai Prakash Ranjan apss_funnel_in0: endpoint { 319624244cefSSai Prakash Ranjan remote-endpoint = <&etm0_out>; 319724244cefSSai Prakash Ranjan }; 319824244cefSSai Prakash Ranjan }; 319924244cefSSai Prakash Ranjan 320024244cefSSai Prakash Ranjan port@1 { 320124244cefSSai Prakash Ranjan reg = <1>; 320224244cefSSai Prakash Ranjan apss_funnel_in1: endpoint { 320324244cefSSai Prakash Ranjan remote-endpoint = <&etm1_out>; 320424244cefSSai Prakash Ranjan }; 320524244cefSSai Prakash Ranjan }; 320624244cefSSai Prakash Ranjan 320724244cefSSai Prakash Ranjan port@2 { 320824244cefSSai Prakash Ranjan reg = <2>; 320924244cefSSai Prakash Ranjan apss_funnel_in2: endpoint { 321024244cefSSai Prakash Ranjan remote-endpoint = <&etm2_out>; 321124244cefSSai Prakash Ranjan }; 321224244cefSSai Prakash Ranjan }; 321324244cefSSai Prakash Ranjan 321424244cefSSai Prakash Ranjan port@3 { 321524244cefSSai Prakash Ranjan reg = <3>; 321624244cefSSai Prakash Ranjan apss_funnel_in3: endpoint { 321724244cefSSai Prakash Ranjan remote-endpoint = <&etm3_out>; 321824244cefSSai Prakash Ranjan }; 321924244cefSSai Prakash Ranjan }; 322024244cefSSai Prakash Ranjan 322124244cefSSai Prakash Ranjan port@4 { 322224244cefSSai Prakash Ranjan reg = <4>; 322324244cefSSai Prakash Ranjan apss_funnel_in4: endpoint { 322424244cefSSai Prakash Ranjan remote-endpoint = <&etm4_out>; 322524244cefSSai Prakash Ranjan }; 322624244cefSSai Prakash Ranjan }; 322724244cefSSai Prakash Ranjan 322824244cefSSai Prakash Ranjan port@5 { 322924244cefSSai Prakash Ranjan reg = <5>; 323024244cefSSai Prakash Ranjan apss_funnel_in5: endpoint { 323124244cefSSai Prakash Ranjan remote-endpoint = <&etm5_out>; 323224244cefSSai Prakash Ranjan }; 323324244cefSSai Prakash Ranjan }; 323424244cefSSai Prakash Ranjan 323524244cefSSai Prakash Ranjan port@6 { 323624244cefSSai Prakash Ranjan reg = <6>; 323724244cefSSai Prakash Ranjan apss_funnel_in6: endpoint { 323824244cefSSai Prakash Ranjan remote-endpoint = <&etm6_out>; 323924244cefSSai Prakash Ranjan }; 324024244cefSSai Prakash Ranjan }; 324124244cefSSai Prakash Ranjan 324224244cefSSai Prakash Ranjan port@7 { 324324244cefSSai Prakash Ranjan reg = <7>; 324424244cefSSai Prakash Ranjan apss_funnel_in7: endpoint { 324524244cefSSai Prakash Ranjan remote-endpoint = <&etm7_out>; 324624244cefSSai Prakash Ranjan }; 324724244cefSSai Prakash Ranjan }; 324824244cefSSai Prakash Ranjan }; 324924244cefSSai Prakash Ranjan }; 325024244cefSSai Prakash Ranjan 325124244cefSSai Prakash Ranjan funnel@7810000 { 325224244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 325324244cefSSai Prakash Ranjan reg = <0 0x07810000 0 0x1000>; 325424244cefSSai Prakash Ranjan 325524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 325624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 325724244cefSSai Prakash Ranjan 325824244cefSSai Prakash Ranjan out-ports { 325924244cefSSai Prakash Ranjan port { 326024244cefSSai Prakash Ranjan apss_merge_funnel_out: endpoint { 326124244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_in2>; 326224244cefSSai Prakash Ranjan }; 326324244cefSSai Prakash Ranjan }; 326424244cefSSai Prakash Ranjan }; 326524244cefSSai Prakash Ranjan 326624244cefSSai Prakash Ranjan in-ports { 326724244cefSSai Prakash Ranjan port { 326824244cefSSai Prakash Ranjan apss_merge_funnel_in: endpoint { 326924244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_out>; 327024244cefSSai Prakash Ranjan }; 327124244cefSSai Prakash Ranjan }; 327224244cefSSai Prakash Ranjan }; 327324244cefSSai Prakash Ranjan }; 327424244cefSSai Prakash Ranjan 327549076351SSibi Sankar remoteproc_cdsp: remoteproc@8300000 { 327649076351SSibi Sankar compatible = "qcom,sm8150-cdsp-pas"; 327749076351SSibi Sankar reg = <0x0 0x08300000 0x0 0x4040>; 327849076351SSibi Sankar 327949076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 328049076351SSibi Sankar <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 328149076351SSibi Sankar <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 328249076351SSibi Sankar <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 328349076351SSibi Sankar <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 328449076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 328549076351SSibi Sankar "handover", "stop-ack"; 328649076351SSibi Sankar 328749076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 328849076351SSibi Sankar clock-names = "xo"; 328949076351SSibi Sankar 3290a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_CX>; 329149076351SSibi Sankar 329249076351SSibi Sankar memory-region = <&cdsp_mem>; 329349076351SSibi Sankar 3294d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 3295d9d327f6SSibi Sankar 329649076351SSibi Sankar qcom,smem-states = <&cdsp_smp2p_out 0>; 329749076351SSibi Sankar qcom,smem-state-names = "stop"; 329849076351SSibi Sankar 329949076351SSibi Sankar status = "disabled"; 330049076351SSibi Sankar 330149076351SSibi Sankar glink-edge { 330249076351SSibi Sankar interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 330349076351SSibi Sankar label = "cdsp"; 330449076351SSibi Sankar qcom,remote-pid = <5>; 330549076351SSibi Sankar mboxes = <&apss_shared 4>; 330681729330SBhupesh Sharma 330781729330SBhupesh Sharma fastrpc { 330881729330SBhupesh Sharma compatible = "qcom,fastrpc"; 330981729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 331081729330SBhupesh Sharma label = "cdsp"; 33118c8ce95bSJeya R qcom,non-secure-domain; 331281729330SBhupesh Sharma #address-cells = <1>; 331381729330SBhupesh Sharma #size-cells = <0>; 331481729330SBhupesh Sharma 331581729330SBhupesh Sharma compute-cb@1 { 331681729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 331781729330SBhupesh Sharma reg = <1>; 33181d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1001 0x0460>; 331981729330SBhupesh Sharma }; 332081729330SBhupesh Sharma 332181729330SBhupesh Sharma compute-cb@2 { 332281729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 332381729330SBhupesh Sharma reg = <2>; 33241d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1002 0x0460>; 332581729330SBhupesh Sharma }; 332681729330SBhupesh Sharma 332781729330SBhupesh Sharma compute-cb@3 { 332881729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 332981729330SBhupesh Sharma reg = <3>; 33301d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1003 0x0460>; 333181729330SBhupesh Sharma }; 333281729330SBhupesh Sharma 333381729330SBhupesh Sharma compute-cb@4 { 333481729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 333581729330SBhupesh Sharma reg = <4>; 33361d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1004 0x0460>; 333781729330SBhupesh Sharma }; 333881729330SBhupesh Sharma 333981729330SBhupesh Sharma compute-cb@5 { 334081729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 334181729330SBhupesh Sharma reg = <5>; 33421d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1005 0x0460>; 334381729330SBhupesh Sharma }; 334481729330SBhupesh Sharma 334581729330SBhupesh Sharma compute-cb@6 { 334681729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 334781729330SBhupesh Sharma reg = <6>; 33481d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1006 0x0460>; 334981729330SBhupesh Sharma }; 335081729330SBhupesh Sharma 335181729330SBhupesh Sharma compute-cb@7 { 335281729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 335381729330SBhupesh Sharma reg = <7>; 33541d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1007 0x0460>; 335581729330SBhupesh Sharma }; 335681729330SBhupesh Sharma 335781729330SBhupesh Sharma compute-cb@8 { 335881729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 335981729330SBhupesh Sharma reg = <8>; 33601d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1008 0x0460>; 336181729330SBhupesh Sharma }; 336281729330SBhupesh Sharma 336381729330SBhupesh Sharma /* note: secure cb9 in downstream */ 336481729330SBhupesh Sharma }; 336549076351SSibi Sankar }; 336649076351SSibi Sankar }; 336749076351SSibi Sankar 3368b33d2868SJack Pham usb_1_hsphy: phy@88e2000 { 3369b33d2868SJack Pham compatible = "qcom,sm8150-usb-hs-phy", 3370b33d2868SJack Pham "qcom,usb-snps-hs-7nm-phy"; 3371b33d2868SJack Pham reg = <0 0x088e2000 0 0x400>; 3372b33d2868SJack Pham status = "disabled"; 3373b33d2868SJack Pham #phy-cells = <0>; 3374b33d2868SJack Pham 3375b33d2868SJack Pham clocks = <&rpmhcc RPMH_CXO_CLK>; 3376b33d2868SJack Pham clock-names = "ref"; 3377b33d2868SJack Pham 3378b33d2868SJack Pham resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3379b33d2868SJack Pham }; 3380b33d2868SJack Pham 33810c9dde0dSJonathan Marek usb_2_hsphy: phy@88e3000 { 33820c9dde0dSJonathan Marek compatible = "qcom,sm8150-usb-hs-phy", 33830c9dde0dSJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 33840c9dde0dSJonathan Marek reg = <0 0x088e3000 0 0x400>; 33850c9dde0dSJonathan Marek status = "disabled"; 33860c9dde0dSJonathan Marek #phy-cells = <0>; 33870c9dde0dSJonathan Marek 33880c9dde0dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 33890c9dde0dSJonathan Marek clock-names = "ref"; 33900c9dde0dSJonathan Marek 33910c9dde0dSJonathan Marek resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 33920c9dde0dSJonathan Marek }; 33930c9dde0dSJonathan Marek 3394b33d2868SJack Pham usb_1_qmpphy: phy@88e9000 { 3395b33d2868SJack Pham compatible = "qcom,sm8150-qmp-usb3-phy"; 3396b33d2868SJack Pham reg = <0 0x088e9000 0 0x18c>, 3397b33d2868SJack Pham <0 0x088e8000 0 0x10>; 3398b33d2868SJack Pham status = "disabled"; 3399b33d2868SJack Pham #address-cells = <2>; 3400b33d2868SJack Pham #size-cells = <2>; 3401b33d2868SJack Pham ranges; 3402b33d2868SJack Pham 3403b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3404b33d2868SJack Pham <&rpmhcc RPMH_CXO_CLK>, 3405b33d2868SJack Pham <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3406b33d2868SJack Pham <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3407b33d2868SJack Pham clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3408b33d2868SJack Pham 3409b33d2868SJack Pham resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3410b33d2868SJack Pham <&gcc GCC_USB3_PHY_PRIM_BCR>; 3411b33d2868SJack Pham reset-names = "phy", "common"; 3412b33d2868SJack Pham 34131351512fSShawn Guo usb_1_ssphy: phy@88e9200 { 3414b33d2868SJack Pham reg = <0 0x088e9200 0 0x200>, 3415b33d2868SJack Pham <0 0x088e9400 0 0x200>, 3416b33d2868SJack Pham <0 0x088e9c00 0 0x218>, 3417b33d2868SJack Pham <0 0x088e9600 0 0x200>, 3418b33d2868SJack Pham <0 0x088e9800 0 0x200>, 3419b33d2868SJack Pham <0 0x088e9a00 0 0x100>; 34207178d4ccSJonathan Marek #clock-cells = <0>; 3421b33d2868SJack Pham #phy-cells = <0>; 3422b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3423b33d2868SJack Pham clock-names = "pipe0"; 3424b33d2868SJack Pham clock-output-names = "usb3_phy_pipe_clk_src"; 3425b33d2868SJack Pham }; 3426b33d2868SJack Pham }; 3427b33d2868SJack Pham 34280c9dde0dSJonathan Marek usb_2_qmpphy: phy@88eb000 { 34290c9dde0dSJonathan Marek compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 34300c9dde0dSJonathan Marek reg = <0 0x088eb000 0 0x200>; 34310c9dde0dSJonathan Marek status = "disabled"; 34320c9dde0dSJonathan Marek #address-cells = <2>; 34330c9dde0dSJonathan Marek #size-cells = <2>; 34340c9dde0dSJonathan Marek ranges; 34350c9dde0dSJonathan Marek 34360c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 34370c9dde0dSJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 34380c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>, 34390c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 34400c9dde0dSJonathan Marek clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 34410c9dde0dSJonathan Marek 34420c9dde0dSJonathan Marek resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 34430c9dde0dSJonathan Marek <&gcc GCC_USB3_PHY_SEC_BCR>; 34440c9dde0dSJonathan Marek reset-names = "phy", "common"; 34450c9dde0dSJonathan Marek 34461351512fSShawn Guo usb_2_ssphy: phy@88eb200 { 34470c9dde0dSJonathan Marek reg = <0 0x088eb200 0 0x200>, 34480c9dde0dSJonathan Marek <0 0x088eb400 0 0x200>, 34490c9dde0dSJonathan Marek <0 0x088eb800 0 0x800>, 34500c9dde0dSJonathan Marek <0 0x088eb600 0 0x200>; 34517178d4ccSJonathan Marek #clock-cells = <0>; 34520c9dde0dSJonathan Marek #phy-cells = <0>; 34530c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 34540c9dde0dSJonathan Marek clock-names = "pipe0"; 34550c9dde0dSJonathan Marek clock-output-names = "usb3_uni_phy_pipe_clk_src"; 34560c9dde0dSJonathan Marek }; 34570c9dde0dSJonathan Marek }; 34580c9dde0dSJonathan Marek 345996bb736fSBhupesh Sharma sdhc_2: mmc@8804000 { 3460876644c7SBhupesh Sharma compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3461876644c7SBhupesh Sharma reg = <0 0x08804000 0 0x1000>; 3462876644c7SBhupesh Sharma 3463876644c7SBhupesh Sharma interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3464876644c7SBhupesh Sharma <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3465876644c7SBhupesh Sharma interrupt-names = "hc_irq", "pwr_irq"; 3466876644c7SBhupesh Sharma 3467876644c7SBhupesh Sharma clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3468876644c7SBhupesh Sharma <&gcc GCC_SDCC2_APPS_CLK>, 3469876644c7SBhupesh Sharma <&rpmhcc RPMH_CXO_CLK>; 3470876644c7SBhupesh Sharma clock-names = "iface", "core", "xo"; 347195830090SBhupesh Sharma iommus = <&apps_smmu 0x6a0 0x0>; 3472876644c7SBhupesh Sharma qcom,dll-config = <0x0007642c>; 3473876644c7SBhupesh Sharma qcom,ddr-config = <0x80040868>; 3474876644c7SBhupesh Sharma power-domains = <&rpmhpd 0>; 3475876644c7SBhupesh Sharma operating-points-v2 = <&sdhc2_opp_table>; 3476876644c7SBhupesh Sharma 3477876644c7SBhupesh Sharma status = "disabled"; 3478876644c7SBhupesh Sharma 34790e3e6546SKrzysztof Kozlowski sdhc2_opp_table: opp-table { 3480876644c7SBhupesh Sharma compatible = "operating-points-v2"; 3481876644c7SBhupesh Sharma 3482876644c7SBhupesh Sharma opp-19200000 { 3483876644c7SBhupesh Sharma opp-hz = /bits/ 64 <19200000>; 3484876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_min_svs>; 3485876644c7SBhupesh Sharma }; 3486876644c7SBhupesh Sharma 3487876644c7SBhupesh Sharma opp-50000000 { 3488876644c7SBhupesh Sharma opp-hz = /bits/ 64 <50000000>; 3489876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_low_svs>; 3490876644c7SBhupesh Sharma }; 3491876644c7SBhupesh Sharma 3492876644c7SBhupesh Sharma opp-100000000 { 3493876644c7SBhupesh Sharma opp-hz = /bits/ 64 <100000000>; 3494876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_svs>; 3495876644c7SBhupesh Sharma }; 3496876644c7SBhupesh Sharma 3497876644c7SBhupesh Sharma opp-202000000 { 3498876644c7SBhupesh Sharma opp-hz = /bits/ 64 <202000000>; 3499876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_svs_l1>; 3500876644c7SBhupesh Sharma }; 3501876644c7SBhupesh Sharma }; 3502876644c7SBhupesh Sharma }; 3503876644c7SBhupesh Sharma 35045dc43d3bSBhupesh Sharma dc_noc: interconnect@9160000 { 35055dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-dc-noc"; 35065dc43d3bSBhupesh Sharma reg = <0 0x09160000 0 0x3200>; 35075dc43d3bSBhupesh Sharma #interconnect-cells = <1>; 35085dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 35095dc43d3bSBhupesh Sharma }; 35105dc43d3bSBhupesh Sharma 35115dc43d3bSBhupesh Sharma gem_noc: interconnect@9680000 { 35125dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-gem-noc"; 35135dc43d3bSBhupesh Sharma reg = <0 0x09680000 0 0x3e200>; 35145dc43d3bSBhupesh Sharma #interconnect-cells = <1>; 35155dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 35165dc43d3bSBhupesh Sharma }; 35175dc43d3bSBhupesh Sharma 3518b33d2868SJack Pham usb_1: usb@a6f8800 { 3519b33d2868SJack Pham compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3520b33d2868SJack Pham reg = <0 0x0a6f8800 0 0x400>; 3521b33d2868SJack Pham status = "disabled"; 3522b33d2868SJack Pham #address-cells = <2>; 3523b33d2868SJack Pham #size-cells = <2>; 3524b33d2868SJack Pham ranges; 3525b33d2868SJack Pham dma-ranges; 3526b33d2868SJack Pham 3527b33d2868SJack Pham clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3528b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3529b33d2868SJack Pham <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3530b33d2868SJack Pham <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 35318d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3532b33d2868SJack Pham <&gcc GCC_USB3_SEC_CLKREF_CLK>; 35338d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 35348d5fd4e4SKrzysztof Kozlowski "core", 35358d5fd4e4SKrzysztof Kozlowski "iface", 35368d5fd4e4SKrzysztof Kozlowski "sleep", 35378d5fd4e4SKrzysztof Kozlowski "mock_utmi", 35388d5fd4e4SKrzysztof Kozlowski "xo"; 3539b33d2868SJack Pham 3540b33d2868SJack Pham assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3541b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>; 354279493db5SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 3543b33d2868SJack Pham 3544b33d2868SJack Pham interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3545b33d2868SJack Pham <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3546b33d2868SJack Pham <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3547b33d2868SJack Pham <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3548b33d2868SJack Pham interrupt-names = "hs_phy_irq", "ss_phy_irq", 3549b33d2868SJack Pham "dm_hs_phy_irq", "dp_hs_phy_irq"; 3550b33d2868SJack Pham 3551b33d2868SJack Pham power-domains = <&gcc USB30_PRIM_GDSC>; 3552b33d2868SJack Pham 3553b33d2868SJack Pham resets = <&gcc GCC_USB30_PRIM_BCR>; 3554b33d2868SJack Pham 3555b77a1c4dSKrzysztof Kozlowski usb_1_dwc3: usb@a600000 { 3556b33d2868SJack Pham compatible = "snps,dwc3"; 3557b33d2868SJack Pham reg = <0 0x0a600000 0 0xcd00>; 3558b33d2868SJack Pham interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 355948156232SJonathan Marek iommus = <&apps_smmu 0x140 0>; 3560b33d2868SJack Pham snps,dis_u2_susphy_quirk; 3561b33d2868SJack Pham snps,dis_enblslpm_quirk; 3562b33d2868SJack Pham phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3563b33d2868SJack Pham phy-names = "usb2-phy", "usb3-phy"; 3564b33d2868SJack Pham }; 3565b33d2868SJack Pham }; 3566b33d2868SJack Pham 35670c9dde0dSJonathan Marek usb_2: usb@a8f8800 { 35680c9dde0dSJonathan Marek compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 35690c9dde0dSJonathan Marek reg = <0 0x0a8f8800 0 0x400>; 35700c9dde0dSJonathan Marek status = "disabled"; 35710c9dde0dSJonathan Marek #address-cells = <2>; 35720c9dde0dSJonathan Marek #size-cells = <2>; 35730c9dde0dSJonathan Marek ranges; 35740c9dde0dSJonathan Marek dma-ranges; 35750c9dde0dSJonathan Marek 35760c9dde0dSJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 35770c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>, 35780c9dde0dSJonathan Marek <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 35790c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_SLEEP_CLK>, 35808d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 35810c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>; 35828d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 35838d5fd4e4SKrzysztof Kozlowski "core", 35848d5fd4e4SKrzysztof Kozlowski "iface", 35858d5fd4e4SKrzysztof Kozlowski "sleep", 35868d5fd4e4SKrzysztof Kozlowski "mock_utmi", 35878d5fd4e4SKrzysztof Kozlowski "xo"; 35880c9dde0dSJonathan Marek 35890c9dde0dSJonathan Marek assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 35900c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>; 35910c9dde0dSJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 35920c9dde0dSJonathan Marek 35930c9dde0dSJonathan Marek interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 35940c9dde0dSJonathan Marek <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 35950c9dde0dSJonathan Marek <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 35960c9dde0dSJonathan Marek <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 35970c9dde0dSJonathan Marek interrupt-names = "hs_phy_irq", "ss_phy_irq", 35980c9dde0dSJonathan Marek "dm_hs_phy_irq", "dp_hs_phy_irq"; 35990c9dde0dSJonathan Marek 36000c9dde0dSJonathan Marek power-domains = <&gcc USB30_SEC_GDSC>; 36010c9dde0dSJonathan Marek 36020c9dde0dSJonathan Marek resets = <&gcc GCC_USB30_SEC_BCR>; 36030c9dde0dSJonathan Marek 36042aa2b50dSBhupesh Sharma usb_2_dwc3: usb@a800000 { 36050c9dde0dSJonathan Marek compatible = "snps,dwc3"; 36060c9dde0dSJonathan Marek reg = <0 0x0a800000 0 0xcd00>; 36070c9dde0dSJonathan Marek interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 36080c9dde0dSJonathan Marek iommus = <&apps_smmu 0x160 0>; 36090c9dde0dSJonathan Marek snps,dis_u2_susphy_quirk; 36100c9dde0dSJonathan Marek snps,dis_enblslpm_quirk; 36110c9dde0dSJonathan Marek phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 36120c9dde0dSJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 36130c9dde0dSJonathan Marek }; 36140c9dde0dSJonathan Marek }; 36150c9dde0dSJonathan Marek 36166acb71fdSJonathan Marek camnoc_virt: interconnect@ac00000 { 36176acb71fdSJonathan Marek compatible = "qcom,sm8150-camnoc-virt"; 36186acb71fdSJonathan Marek reg = <0 0x0ac00000 0 0x1000>; 36196acb71fdSJonathan Marek #interconnect-cells = <1>; 36206acb71fdSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 36216acb71fdSJonathan Marek }; 36226acb71fdSJonathan Marek 362398874a46SKonrad Dybcio mdss: display-subsystem@ae00000 { 362498874a46SKonrad Dybcio compatible = "qcom,sm8150-mdss"; 362598874a46SKonrad Dybcio reg = <0 0x0ae00000 0 0x1000>; 362698874a46SKonrad Dybcio reg-names = "mdss"; 362798874a46SKonrad Dybcio 362898874a46SKonrad Dybcio interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 362998874a46SKonrad Dybcio <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 363098874a46SKonrad Dybcio interconnect-names = "mdp0-mem", "mdp1-mem"; 363198874a46SKonrad Dybcio 363298874a46SKonrad Dybcio power-domains = <&dispcc MDSS_GDSC>; 363398874a46SKonrad Dybcio 363498874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 363598874a46SKonrad Dybcio <&gcc GCC_DISP_HF_AXI_CLK>, 363698874a46SKonrad Dybcio <&gcc GCC_DISP_SF_AXI_CLK>, 363798874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_MDP_CLK>; 363898874a46SKonrad Dybcio clock-names = "iface", "bus", "nrt_bus", "core"; 363998874a46SKonrad Dybcio 364098874a46SKonrad Dybcio interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 364198874a46SKonrad Dybcio interrupt-controller; 364298874a46SKonrad Dybcio #interrupt-cells = <1>; 364398874a46SKonrad Dybcio 364498874a46SKonrad Dybcio iommus = <&apps_smmu 0x800 0x420>; 364598874a46SKonrad Dybcio 364698874a46SKonrad Dybcio status = "disabled"; 364798874a46SKonrad Dybcio 364898874a46SKonrad Dybcio #address-cells = <2>; 364998874a46SKonrad Dybcio #size-cells = <2>; 365098874a46SKonrad Dybcio ranges; 365198874a46SKonrad Dybcio 365298874a46SKonrad Dybcio mdss_mdp: display-controller@ae01000 { 365398874a46SKonrad Dybcio compatible = "qcom,sm8150-dpu"; 365498874a46SKonrad Dybcio reg = <0 0x0ae01000 0 0x8f000>, 365598874a46SKonrad Dybcio <0 0x0aeb0000 0 0x2008>; 365698874a46SKonrad Dybcio reg-names = "mdp", "vbif"; 365798874a46SKonrad Dybcio 365898874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 365998874a46SKonrad Dybcio <&gcc GCC_DISP_HF_AXI_CLK>, 366098874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_MDP_CLK>, 366198874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 366298874a46SKonrad Dybcio clock-names = "iface", "bus", "core", "vsync"; 366398874a46SKonrad Dybcio 366498874a46SKonrad Dybcio assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 366598874a46SKonrad Dybcio assigned-clock-rates = <19200000>; 366698874a46SKonrad Dybcio 366798874a46SKonrad Dybcio operating-points-v2 = <&mdp_opp_table>; 366898874a46SKonrad Dybcio power-domains = <&rpmhpd SM8150_MMCX>; 366998874a46SKonrad Dybcio 367098874a46SKonrad Dybcio interrupt-parent = <&mdss>; 367198874a46SKonrad Dybcio interrupts = <0>; 367298874a46SKonrad Dybcio 367398874a46SKonrad Dybcio ports { 367498874a46SKonrad Dybcio #address-cells = <1>; 367598874a46SKonrad Dybcio #size-cells = <0>; 367698874a46SKonrad Dybcio 367798874a46SKonrad Dybcio port@0 { 367898874a46SKonrad Dybcio reg = <0>; 367998874a46SKonrad Dybcio dpu_intf1_out: endpoint { 368098874a46SKonrad Dybcio remote-endpoint = <&mdss_dsi0_in>; 368198874a46SKonrad Dybcio }; 368298874a46SKonrad Dybcio }; 368398874a46SKonrad Dybcio 368498874a46SKonrad Dybcio port@1 { 368598874a46SKonrad Dybcio reg = <1>; 368698874a46SKonrad Dybcio dpu_intf2_out: endpoint { 368798874a46SKonrad Dybcio remote-endpoint = <&mdss_dsi1_in>; 368898874a46SKonrad Dybcio }; 368998874a46SKonrad Dybcio }; 369098874a46SKonrad Dybcio }; 369198874a46SKonrad Dybcio 369298874a46SKonrad Dybcio mdp_opp_table: opp-table { 369398874a46SKonrad Dybcio compatible = "operating-points-v2"; 369498874a46SKonrad Dybcio 369598874a46SKonrad Dybcio opp-171428571 { 369698874a46SKonrad Dybcio opp-hz = /bits/ 64 <171428571>; 369798874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_low_svs>; 369898874a46SKonrad Dybcio }; 369998874a46SKonrad Dybcio 370098874a46SKonrad Dybcio opp-300000000 { 370198874a46SKonrad Dybcio opp-hz = /bits/ 64 <300000000>; 370298874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_svs>; 370398874a46SKonrad Dybcio }; 370498874a46SKonrad Dybcio 370598874a46SKonrad Dybcio opp-345000000 { 370698874a46SKonrad Dybcio opp-hz = /bits/ 64 <345000000>; 370798874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_svs_l1>; 370898874a46SKonrad Dybcio }; 370998874a46SKonrad Dybcio 371098874a46SKonrad Dybcio opp-460000000 { 371198874a46SKonrad Dybcio opp-hz = /bits/ 64 <460000000>; 371298874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_nom>; 371398874a46SKonrad Dybcio }; 371498874a46SKonrad Dybcio }; 371598874a46SKonrad Dybcio }; 371698874a46SKonrad Dybcio 371798874a46SKonrad Dybcio mdss_dsi0: dsi@ae94000 { 3718b0b8b34aSDmitry Baryshkov compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 371998874a46SKonrad Dybcio reg = <0 0x0ae94000 0 0x400>; 372098874a46SKonrad Dybcio reg-names = "dsi_ctrl"; 372198874a46SKonrad Dybcio 372298874a46SKonrad Dybcio interrupt-parent = <&mdss>; 372398874a46SKonrad Dybcio interrupts = <4>; 372498874a46SKonrad Dybcio 372598874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 372698874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 372798874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 372898874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_ESC0_CLK>, 372998874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_AHB_CLK>, 373098874a46SKonrad Dybcio <&gcc GCC_DISP_HF_AXI_CLK>; 373198874a46SKonrad Dybcio clock-names = "byte", 373298874a46SKonrad Dybcio "byte_intf", 373398874a46SKonrad Dybcio "pixel", 373498874a46SKonrad Dybcio "core", 373598874a46SKonrad Dybcio "iface", 373698874a46SKonrad Dybcio "bus"; 373798874a46SKonrad Dybcio 373898874a46SKonrad Dybcio assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 373998874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 374098874a46SKonrad Dybcio assigned-clock-parents = <&mdss_dsi0_phy 0>, 374198874a46SKonrad Dybcio <&mdss_dsi0_phy 1>; 374298874a46SKonrad Dybcio 374398874a46SKonrad Dybcio operating-points-v2 = <&dsi_opp_table>; 374498874a46SKonrad Dybcio power-domains = <&rpmhpd SM8150_MMCX>; 374598874a46SKonrad Dybcio 374698874a46SKonrad Dybcio phys = <&mdss_dsi0_phy>; 374798874a46SKonrad Dybcio 374898874a46SKonrad Dybcio status = "disabled"; 374998874a46SKonrad Dybcio 375098874a46SKonrad Dybcio #address-cells = <1>; 375198874a46SKonrad Dybcio #size-cells = <0>; 375298874a46SKonrad Dybcio 375398874a46SKonrad Dybcio ports { 375498874a46SKonrad Dybcio #address-cells = <1>; 375598874a46SKonrad Dybcio #size-cells = <0>; 375698874a46SKonrad Dybcio 375798874a46SKonrad Dybcio port@0 { 375898874a46SKonrad Dybcio reg = <0>; 375998874a46SKonrad Dybcio mdss_dsi0_in: endpoint { 376098874a46SKonrad Dybcio remote-endpoint = <&dpu_intf1_out>; 376198874a46SKonrad Dybcio }; 376298874a46SKonrad Dybcio }; 376398874a46SKonrad Dybcio 376498874a46SKonrad Dybcio port@1 { 376598874a46SKonrad Dybcio reg = <1>; 376698874a46SKonrad Dybcio mdss_dsi0_out: endpoint { 376798874a46SKonrad Dybcio }; 376898874a46SKonrad Dybcio }; 376998874a46SKonrad Dybcio }; 377098874a46SKonrad Dybcio 377198874a46SKonrad Dybcio dsi_opp_table: opp-table { 377298874a46SKonrad Dybcio compatible = "operating-points-v2"; 377398874a46SKonrad Dybcio 377498874a46SKonrad Dybcio opp-187500000 { 377598874a46SKonrad Dybcio opp-hz = /bits/ 64 <187500000>; 377698874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_low_svs>; 377798874a46SKonrad Dybcio }; 377898874a46SKonrad Dybcio 377998874a46SKonrad Dybcio opp-300000000 { 378098874a46SKonrad Dybcio opp-hz = /bits/ 64 <300000000>; 378198874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_svs>; 378298874a46SKonrad Dybcio }; 378398874a46SKonrad Dybcio 378498874a46SKonrad Dybcio opp-358000000 { 378598874a46SKonrad Dybcio opp-hz = /bits/ 64 <358000000>; 378698874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_svs_l1>; 378798874a46SKonrad Dybcio }; 378898874a46SKonrad Dybcio }; 378998874a46SKonrad Dybcio }; 379098874a46SKonrad Dybcio 379198874a46SKonrad Dybcio mdss_dsi0_phy: phy@ae94400 { 379298874a46SKonrad Dybcio compatible = "qcom,dsi-phy-7nm"; 379398874a46SKonrad Dybcio reg = <0 0x0ae94400 0 0x200>, 379498874a46SKonrad Dybcio <0 0x0ae94600 0 0x280>, 379598874a46SKonrad Dybcio <0 0x0ae94900 0 0x260>; 379698874a46SKonrad Dybcio reg-names = "dsi_phy", 379798874a46SKonrad Dybcio "dsi_phy_lane", 379898874a46SKonrad Dybcio "dsi_pll"; 379998874a46SKonrad Dybcio 380098874a46SKonrad Dybcio #clock-cells = <1>; 380198874a46SKonrad Dybcio #phy-cells = <0>; 380298874a46SKonrad Dybcio 380398874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 380498874a46SKonrad Dybcio <&rpmhcc RPMH_CXO_CLK>; 380598874a46SKonrad Dybcio clock-names = "iface", "ref"; 380698874a46SKonrad Dybcio 380798874a46SKonrad Dybcio status = "disabled"; 380898874a46SKonrad Dybcio }; 380998874a46SKonrad Dybcio 381098874a46SKonrad Dybcio mdss_dsi1: dsi@ae96000 { 3811b0b8b34aSDmitry Baryshkov compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 381298874a46SKonrad Dybcio reg = <0 0x0ae96000 0 0x400>; 381398874a46SKonrad Dybcio reg-names = "dsi_ctrl"; 381498874a46SKonrad Dybcio 381598874a46SKonrad Dybcio interrupt-parent = <&mdss>; 381698874a46SKonrad Dybcio interrupts = <5>; 381798874a46SKonrad Dybcio 381898874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 381998874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 382098874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 382198874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_ESC1_CLK>, 382298874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_AHB_CLK>, 382398874a46SKonrad Dybcio <&gcc GCC_DISP_HF_AXI_CLK>; 382498874a46SKonrad Dybcio clock-names = "byte", 382598874a46SKonrad Dybcio "byte_intf", 382698874a46SKonrad Dybcio "pixel", 382798874a46SKonrad Dybcio "core", 382898874a46SKonrad Dybcio "iface", 382998874a46SKonrad Dybcio "bus"; 383098874a46SKonrad Dybcio 383198874a46SKonrad Dybcio assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 383298874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 383398874a46SKonrad Dybcio assigned-clock-parents = <&mdss_dsi1_phy 0>, 383498874a46SKonrad Dybcio <&mdss_dsi1_phy 1>; 383598874a46SKonrad Dybcio 383698874a46SKonrad Dybcio operating-points-v2 = <&dsi_opp_table>; 383798874a46SKonrad Dybcio power-domains = <&rpmhpd SM8150_MMCX>; 383898874a46SKonrad Dybcio 383998874a46SKonrad Dybcio phys = <&mdss_dsi1_phy>; 384098874a46SKonrad Dybcio 384198874a46SKonrad Dybcio status = "disabled"; 384298874a46SKonrad Dybcio 384398874a46SKonrad Dybcio #address-cells = <1>; 384498874a46SKonrad Dybcio #size-cells = <0>; 384598874a46SKonrad Dybcio 384698874a46SKonrad Dybcio ports { 384798874a46SKonrad Dybcio #address-cells = <1>; 384898874a46SKonrad Dybcio #size-cells = <0>; 384998874a46SKonrad Dybcio 385098874a46SKonrad Dybcio port@0 { 385198874a46SKonrad Dybcio reg = <0>; 385298874a46SKonrad Dybcio mdss_dsi1_in: endpoint { 385398874a46SKonrad Dybcio remote-endpoint = <&dpu_intf2_out>; 385498874a46SKonrad Dybcio }; 385598874a46SKonrad Dybcio }; 385698874a46SKonrad Dybcio 385798874a46SKonrad Dybcio port@1 { 385898874a46SKonrad Dybcio reg = <1>; 385998874a46SKonrad Dybcio mdss_dsi1_out: endpoint { 386098874a46SKonrad Dybcio }; 386198874a46SKonrad Dybcio }; 386298874a46SKonrad Dybcio }; 386398874a46SKonrad Dybcio }; 386498874a46SKonrad Dybcio 386598874a46SKonrad Dybcio mdss_dsi1_phy: phy@ae96400 { 386698874a46SKonrad Dybcio compatible = "qcom,dsi-phy-7nm"; 386798874a46SKonrad Dybcio reg = <0 0x0ae96400 0 0x200>, 386898874a46SKonrad Dybcio <0 0x0ae96600 0 0x280>, 386998874a46SKonrad Dybcio <0 0x0ae96900 0 0x260>; 387098874a46SKonrad Dybcio reg-names = "dsi_phy", 387198874a46SKonrad Dybcio "dsi_phy_lane", 387298874a46SKonrad Dybcio "dsi_pll"; 387398874a46SKonrad Dybcio 387498874a46SKonrad Dybcio #clock-cells = <1>; 387598874a46SKonrad Dybcio #phy-cells = <0>; 387698874a46SKonrad Dybcio 387798874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 387898874a46SKonrad Dybcio <&rpmhcc RPMH_CXO_CLK>; 387998874a46SKonrad Dybcio clock-names = "iface", "ref"; 388098874a46SKonrad Dybcio 388198874a46SKonrad Dybcio status = "disabled"; 388298874a46SKonrad Dybcio }; 388398874a46SKonrad Dybcio }; 388498874a46SKonrad Dybcio 38852ef3bb17SKonrad Dybcio dispcc: clock-controller@af00000 { 38862ef3bb17SKonrad Dybcio compatible = "qcom,sm8150-dispcc"; 38872ef3bb17SKonrad Dybcio reg = <0 0x0af00000 0 0x10000>; 38882ef3bb17SKonrad Dybcio clocks = <&rpmhcc RPMH_CXO_CLK>, 388998874a46SKonrad Dybcio <&mdss_dsi0_phy 0>, 389098874a46SKonrad Dybcio <&mdss_dsi0_phy 1>, 389198874a46SKonrad Dybcio <&mdss_dsi1_phy 0>, 389298874a46SKonrad Dybcio <&mdss_dsi1_phy 1>, 38932ef3bb17SKonrad Dybcio <0>, 38942ef3bb17SKonrad Dybcio <0>; 38952ef3bb17SKonrad Dybcio clock-names = "bi_tcxo", 38962ef3bb17SKonrad Dybcio "dsi0_phy_pll_out_byteclk", 38972ef3bb17SKonrad Dybcio "dsi0_phy_pll_out_dsiclk", 38982ef3bb17SKonrad Dybcio "dsi1_phy_pll_out_byteclk", 38992ef3bb17SKonrad Dybcio "dsi1_phy_pll_out_dsiclk", 39002ef3bb17SKonrad Dybcio "dp_phy_pll_link_clk", 39012ef3bb17SKonrad Dybcio "dp_phy_pll_vco_div_clk"; 39022ef3bb17SKonrad Dybcio power-domains = <&rpmhpd SM8150_MMCX>; 39032ef3bb17SKonrad Dybcio #clock-cells = <1>; 39042ef3bb17SKonrad Dybcio #reset-cells = <1>; 39052ef3bb17SKonrad Dybcio #power-domain-cells = <1>; 39062ef3bb17SKonrad Dybcio }; 39072ef3bb17SKonrad Dybcio 3908397ad946SBhupesh Sharma pdc: interrupt-controller@b220000 { 3909397ad946SBhupesh Sharma compatible = "qcom,sm8150-pdc", "qcom,pdc"; 3910397ad946SBhupesh Sharma reg = <0 0x0b220000 0 0x400>; 3911397ad946SBhupesh Sharma qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3912397ad946SBhupesh Sharma <125 63 1>; 3913397ad946SBhupesh Sharma #interrupt-cells = <2>; 3914397ad946SBhupesh Sharma interrupt-parent = <&intc>; 3915397ad946SBhupesh Sharma interrupt-controller; 3916397ad946SBhupesh Sharma }; 3917397ad946SBhupesh Sharma 3918bb99820dSKrzysztof Kozlowski aoss_qmp: power-management@c300000 { 39196ba93ba9SKrzysztof Kozlowski compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 392047cb6a06SMaulik Shah reg = <0x0 0x0c300000 0x0 0x400>; 3921d8cf9372SVinod Koul interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3922d8cf9372SVinod Koul mboxes = <&apss_shared 0>; 3923d8cf9372SVinod Koul 3924d8cf9372SVinod Koul #clock-cells = <0>; 3925d8cf9372SVinod Koul }; 3926d8cf9372SVinod Koul 392747cb6a06SMaulik Shah sram@c3f0000 { 392847cb6a06SMaulik Shah compatible = "qcom,rpmh-stats"; 392947cb6a06SMaulik Shah reg = <0 0x0c3f0000 0 0x400>; 393047cb6a06SMaulik Shah }; 393147cb6a06SMaulik Shah 3932d2fa630cSAmit Kucheria tsens0: thermal-sensor@c263000 { 3933d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3934d2fa630cSAmit Kucheria reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3935d2fa630cSAmit Kucheria <0 0x0c222000 0 0x1ff>; /* SROT */ 3936d2fa630cSAmit Kucheria #qcom,sensors = <16>; 3937d2fa630cSAmit Kucheria interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3938d2fa630cSAmit Kucheria <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3939d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 3940d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 3941d2fa630cSAmit Kucheria }; 3942d2fa630cSAmit Kucheria 3943d2fa630cSAmit Kucheria tsens1: thermal-sensor@c265000 { 3944d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3945d2fa630cSAmit Kucheria reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3946d2fa630cSAmit Kucheria <0 0x0c223000 0 0x1ff>; /* SROT */ 3947d2fa630cSAmit Kucheria #qcom,sensors = <8>; 3948d2fa630cSAmit Kucheria interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3949d2fa630cSAmit Kucheria <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3950d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 3951d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 3952d2fa630cSAmit Kucheria }; 3953d2fa630cSAmit Kucheria 3954e13c6d14SVinod Koul spmi_bus: spmi@c440000 { 3955e13c6d14SVinod Koul compatible = "qcom,spmi-pmic-arb"; 3956e13c6d14SVinod Koul reg = <0x0 0x0c440000 0x0 0x0001100>, 3957e13c6d14SVinod Koul <0x0 0x0c600000 0x0 0x2000000>, 3958e13c6d14SVinod Koul <0x0 0x0e600000 0x0 0x0100000>, 3959e13c6d14SVinod Koul <0x0 0x0e700000 0x0 0x00a0000>, 3960e13c6d14SVinod Koul <0x0 0x0c40a000 0x0 0x0026000>; 3961e13c6d14SVinod Koul reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3962e13c6d14SVinod Koul interrupt-names = "periph_irq"; 3963e13c6d14SVinod Koul interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3964e13c6d14SVinod Koul qcom,ee = <0>; 3965e13c6d14SVinod Koul qcom,channel = <0>; 3966e13c6d14SVinod Koul #address-cells = <2>; 3967e13c6d14SVinod Koul #size-cells = <0>; 3968e13c6d14SVinod Koul interrupt-controller; 3969e13c6d14SVinod Koul #interrupt-cells = <4>; 3970e13c6d14SVinod Koul }; 3971e13c6d14SVinod Koul 397248156232SJonathan Marek apps_smmu: iommu@15000000 { 397348156232SJonathan Marek compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 397448156232SJonathan Marek reg = <0 0x15000000 0 0x100000>; 397548156232SJonathan Marek #iommu-cells = <2>; 397648156232SJonathan Marek #global-interrupts = <1>; 397748156232SJonathan Marek interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 397848156232SJonathan Marek <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 397948156232SJonathan Marek <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 398048156232SJonathan Marek <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 398148156232SJonathan Marek <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 398248156232SJonathan Marek <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 398348156232SJonathan Marek <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 398448156232SJonathan Marek <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 398548156232SJonathan Marek <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 398648156232SJonathan Marek <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 398748156232SJonathan Marek <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 398848156232SJonathan Marek <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 398948156232SJonathan Marek <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 399048156232SJonathan Marek <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 399148156232SJonathan Marek <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 399248156232SJonathan Marek <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 399348156232SJonathan Marek <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 399448156232SJonathan Marek <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 399548156232SJonathan Marek <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 399648156232SJonathan Marek <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 399748156232SJonathan Marek <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 399848156232SJonathan Marek <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 399948156232SJonathan Marek <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 400048156232SJonathan Marek <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 400148156232SJonathan Marek <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 400248156232SJonathan Marek <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 400348156232SJonathan Marek <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 400448156232SJonathan Marek <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 400548156232SJonathan Marek <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 400648156232SJonathan Marek <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 400748156232SJonathan Marek <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 400848156232SJonathan Marek <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 400948156232SJonathan Marek <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 401048156232SJonathan Marek <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 401148156232SJonathan Marek <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 401248156232SJonathan Marek <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 401348156232SJonathan Marek <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 401448156232SJonathan Marek <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 401548156232SJonathan Marek <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 401648156232SJonathan Marek <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 401748156232SJonathan Marek <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 401848156232SJonathan Marek <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 401948156232SJonathan Marek <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 402048156232SJonathan Marek <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 402148156232SJonathan Marek <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 402248156232SJonathan Marek <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 402348156232SJonathan Marek <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 402448156232SJonathan Marek <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 402548156232SJonathan Marek <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 402648156232SJonathan Marek <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 402748156232SJonathan Marek <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 402848156232SJonathan Marek <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 402948156232SJonathan Marek <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 403048156232SJonathan Marek <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 403148156232SJonathan Marek <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 403248156232SJonathan Marek <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 403348156232SJonathan Marek <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 403448156232SJonathan Marek <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 403548156232SJonathan Marek <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 403648156232SJonathan Marek <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 403748156232SJonathan Marek <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 403848156232SJonathan Marek <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 403948156232SJonathan Marek <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 404048156232SJonathan Marek <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 404148156232SJonathan Marek <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 404248156232SJonathan Marek <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 404348156232SJonathan Marek <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 404448156232SJonathan Marek <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 404548156232SJonathan Marek <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 404648156232SJonathan Marek <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 404748156232SJonathan Marek <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 404848156232SJonathan Marek <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 404948156232SJonathan Marek <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 405048156232SJonathan Marek <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 405148156232SJonathan Marek <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 405248156232SJonathan Marek <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 405348156232SJonathan Marek <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 405448156232SJonathan Marek <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 405548156232SJonathan Marek <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 405648156232SJonathan Marek <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 405748156232SJonathan Marek <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 405848156232SJonathan Marek }; 405948156232SJonathan Marek 406049076351SSibi Sankar remoteproc_adsp: remoteproc@17300000 { 406149076351SSibi Sankar compatible = "qcom,sm8150-adsp-pas"; 406249076351SSibi Sankar reg = <0x0 0x17300000 0x0 0x4040>; 406349076351SSibi Sankar 406449076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 406549076351SSibi Sankar <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 406649076351SSibi Sankar <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 406749076351SSibi Sankar <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 406849076351SSibi Sankar <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 406949076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 407049076351SSibi Sankar "handover", "stop-ack"; 407149076351SSibi Sankar 407249076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 407349076351SSibi Sankar clock-names = "xo"; 407449076351SSibi Sankar 4075a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_CX>; 407649076351SSibi Sankar 407749076351SSibi Sankar memory-region = <&adsp_mem>; 407849076351SSibi Sankar 4079d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 4080d9d327f6SSibi Sankar 408149076351SSibi Sankar qcom,smem-states = <&adsp_smp2p_out 0>; 408249076351SSibi Sankar qcom,smem-state-names = "stop"; 408349076351SSibi Sankar 408449076351SSibi Sankar status = "disabled"; 408549076351SSibi Sankar 408649076351SSibi Sankar glink-edge { 408749076351SSibi Sankar interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 408849076351SSibi Sankar label = "lpass"; 408949076351SSibi Sankar qcom,remote-pid = <2>; 409049076351SSibi Sankar mboxes = <&apss_shared 8>; 409181729330SBhupesh Sharma 409281729330SBhupesh Sharma fastrpc { 409381729330SBhupesh Sharma compatible = "qcom,fastrpc"; 409481729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 409581729330SBhupesh Sharma label = "adsp"; 40968c8ce95bSJeya R qcom,non-secure-domain; 409781729330SBhupesh Sharma #address-cells = <1>; 409881729330SBhupesh Sharma #size-cells = <0>; 409981729330SBhupesh Sharma 410081729330SBhupesh Sharma compute-cb@3 { 410181729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 410281729330SBhupesh Sharma reg = <3>; 410381729330SBhupesh Sharma iommus = <&apps_smmu 0x1b23 0x0>; 410481729330SBhupesh Sharma }; 410581729330SBhupesh Sharma 410681729330SBhupesh Sharma compute-cb@4 { 410781729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 410881729330SBhupesh Sharma reg = <4>; 410981729330SBhupesh Sharma iommus = <&apps_smmu 0x1b24 0x0>; 411081729330SBhupesh Sharma }; 411181729330SBhupesh Sharma 411281729330SBhupesh Sharma compute-cb@5 { 411381729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 411481729330SBhupesh Sharma reg = <5>; 411581729330SBhupesh Sharma iommus = <&apps_smmu 0x1b25 0x0>; 411681729330SBhupesh Sharma }; 411781729330SBhupesh Sharma }; 411849076351SSibi Sankar }; 411949076351SSibi Sankar }; 412049076351SSibi Sankar 4121e13c6d14SVinod Koul intc: interrupt-controller@17a00000 { 4122e13c6d14SVinod Koul compatible = "arm,gic-v3"; 4123e13c6d14SVinod Koul interrupt-controller; 4124e13c6d14SVinod Koul #interrupt-cells = <3>; 4125e13c6d14SVinod Koul reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4126e13c6d14SVinod Koul <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4127e13c6d14SVinod Koul interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4128e13c6d14SVinod Koul }; 4129e13c6d14SVinod Koul 4130d8cf9372SVinod Koul apss_shared: mailbox@17c00000 { 4131d8cf9372SVinod Koul compatible = "qcom,sm8150-apss-shared"; 4132d8cf9372SVinod Koul reg = <0x0 0x17c00000 0x0 0x1000>; 4133d8cf9372SVinod Koul #mbox-cells = <1>; 4134d8cf9372SVinod Koul }; 4135d8cf9372SVinod Koul 4136fb2d8150SSai Prakash Ranjan watchdog@17c10000 { 4137fb2d8150SSai Prakash Ranjan compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 4138fb2d8150SSai Prakash Ranjan reg = <0 0x17c10000 0 0x1000>; 4139fb2d8150SSai Prakash Ranjan clocks = <&sleep_clk>; 4140b094c8f8SSai Prakash Ranjan interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4141fb2d8150SSai Prakash Ranjan }; 4142fb2d8150SSai Prakash Ranjan 4143e13c6d14SVinod Koul timer@17c20000 { 4144458ebdbbSDavid Heidelberg #address-cells = <1>; 4145458ebdbbSDavid Heidelberg #size-cells = <1>; 4146458ebdbbSDavid Heidelberg ranges = <0 0 0 0x20000000>; 4147e13c6d14SVinod Koul compatible = "arm,armv7-timer-mem"; 4148e13c6d14SVinod Koul reg = <0x0 0x17c20000 0x0 0x1000>; 4149e13c6d14SVinod Koul clock-frequency = <19200000>; 4150e13c6d14SVinod Koul 4151e13c6d14SVinod Koul frame@17c21000 { 4152e13c6d14SVinod Koul frame-number = <0>; 4153e13c6d14SVinod Koul interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4154e13c6d14SVinod Koul <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4155458ebdbbSDavid Heidelberg reg = <0x17c21000 0x1000>, 4156458ebdbbSDavid Heidelberg <0x17c22000 0x1000>; 4157e13c6d14SVinod Koul }; 4158e13c6d14SVinod Koul 4159e13c6d14SVinod Koul frame@17c23000 { 4160e13c6d14SVinod Koul frame-number = <1>; 4161e13c6d14SVinod Koul interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4162458ebdbbSDavid Heidelberg reg = <0x17c23000 0x1000>; 4163e13c6d14SVinod Koul status = "disabled"; 4164e13c6d14SVinod Koul }; 4165e13c6d14SVinod Koul 4166e13c6d14SVinod Koul frame@17c25000 { 4167e13c6d14SVinod Koul frame-number = <2>; 4168e13c6d14SVinod Koul interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4169458ebdbbSDavid Heidelberg reg = <0x17c25000 0x1000>; 4170e13c6d14SVinod Koul status = "disabled"; 4171e13c6d14SVinod Koul }; 4172e13c6d14SVinod Koul 4173e13c6d14SVinod Koul frame@17c27000 { 4174e13c6d14SVinod Koul frame-number = <3>; 4175e13c6d14SVinod Koul interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4176458ebdbbSDavid Heidelberg reg = <0x17c26000 0x1000>; 4177e13c6d14SVinod Koul status = "disabled"; 4178e13c6d14SVinod Koul }; 4179e13c6d14SVinod Koul 4180e13c6d14SVinod Koul frame@17c29000 { 4181e13c6d14SVinod Koul frame-number = <4>; 4182e13c6d14SVinod Koul interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4183458ebdbbSDavid Heidelberg reg = <0x17c29000 0x1000>; 4184e13c6d14SVinod Koul status = "disabled"; 4185e13c6d14SVinod Koul }; 4186e13c6d14SVinod Koul 4187e13c6d14SVinod Koul frame@17c2b000 { 4188e13c6d14SVinod Koul frame-number = <5>; 4189e13c6d14SVinod Koul interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4190458ebdbbSDavid Heidelberg reg = <0x17c2b000 0x1000>; 4191e13c6d14SVinod Koul status = "disabled"; 4192e13c6d14SVinod Koul }; 4193e13c6d14SVinod Koul 4194e13c6d14SVinod Koul frame@17c2d000 { 4195e13c6d14SVinod Koul frame-number = <6>; 4196e13c6d14SVinod Koul interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4197458ebdbbSDavid Heidelberg reg = <0x17c2d000 0x1000>; 4198e13c6d14SVinod Koul status = "disabled"; 4199e13c6d14SVinod Koul }; 4200e13c6d14SVinod Koul }; 4201d8cf9372SVinod Koul 4202d8cf9372SVinod Koul apps_rsc: rsc@18200000 { 4203d8cf9372SVinod Koul label = "apps_rsc"; 4204d8cf9372SVinod Koul compatible = "qcom,rpmh-rsc"; 4205d8cf9372SVinod Koul reg = <0x0 0x18200000 0x0 0x10000>, 4206d8cf9372SVinod Koul <0x0 0x18210000 0x0 0x10000>, 4207d8cf9372SVinod Koul <0x0 0x18220000 0x0 0x10000>; 4208d8cf9372SVinod Koul reg-names = "drv-0", "drv-1", "drv-2"; 4209d8cf9372SVinod Koul interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4210d8cf9372SVinod Koul <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4211d8cf9372SVinod Koul <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4212d8cf9372SVinod Koul qcom,tcs-offset = <0xd00>; 4213d8cf9372SVinod Koul qcom,drv-id = <2>; 4214d8cf9372SVinod Koul qcom,tcs-config = <ACTIVE_TCS 2>, 421517ac8af6SMaulik Shah <SLEEP_TCS 3>, 421617ac8af6SMaulik Shah <WAKE_TCS 3>, 421717ac8af6SMaulik Shah <CONTROL_TCS 1>; 42182ffa0ca4SMaulik Shah power-domains = <&CLUSTER_PD>; 4219d8cf9372SVinod Koul 4220d8cf9372SVinod Koul rpmhcc: clock-controller { 4221d8cf9372SVinod Koul compatible = "qcom,sm8150-rpmh-clk"; 4222d8cf9372SVinod Koul #clock-cells = <1>; 4223d8cf9372SVinod Koul clock-names = "xo"; 4224d8cf9372SVinod Koul clocks = <&xo_board>; 4225d8cf9372SVinod Koul }; 4226017e7856SSibi Sankar 4227017e7856SSibi Sankar rpmhpd: power-controller { 4228017e7856SSibi Sankar compatible = "qcom,sm8150-rpmhpd"; 4229017e7856SSibi Sankar #power-domain-cells = <1>; 4230017e7856SSibi Sankar operating-points-v2 = <&rpmhpd_opp_table>; 4231017e7856SSibi Sankar 4232017e7856SSibi Sankar rpmhpd_opp_table: opp-table { 4233017e7856SSibi Sankar compatible = "operating-points-v2"; 4234017e7856SSibi Sankar 4235017e7856SSibi Sankar rpmhpd_opp_ret: opp1 { 4236017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4237017e7856SSibi Sankar }; 4238017e7856SSibi Sankar 4239017e7856SSibi Sankar rpmhpd_opp_min_svs: opp2 { 4240017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4241017e7856SSibi Sankar }; 4242017e7856SSibi Sankar 4243017e7856SSibi Sankar rpmhpd_opp_low_svs: opp3 { 4244017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4245017e7856SSibi Sankar }; 4246017e7856SSibi Sankar 4247017e7856SSibi Sankar rpmhpd_opp_svs: opp4 { 4248017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4249017e7856SSibi Sankar }; 4250017e7856SSibi Sankar 4251017e7856SSibi Sankar rpmhpd_opp_svs_l1: opp5 { 4252017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4253017e7856SSibi Sankar }; 4254017e7856SSibi Sankar 4255017e7856SSibi Sankar rpmhpd_opp_svs_l2: opp6 { 4256017e7856SSibi Sankar opp-level = <224>; 4257017e7856SSibi Sankar }; 4258017e7856SSibi Sankar 4259017e7856SSibi Sankar rpmhpd_opp_nom: opp7 { 4260017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4261017e7856SSibi Sankar }; 4262017e7856SSibi Sankar 4263017e7856SSibi Sankar rpmhpd_opp_nom_l1: opp8 { 4264017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4265017e7856SSibi Sankar }; 4266017e7856SSibi Sankar 4267017e7856SSibi Sankar rpmhpd_opp_nom_l2: opp9 { 4268017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4269017e7856SSibi Sankar }; 4270017e7856SSibi Sankar 4271017e7856SSibi Sankar rpmhpd_opp_turbo: opp10 { 4272017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4273017e7856SSibi Sankar }; 4274017e7856SSibi Sankar 4275017e7856SSibi Sankar rpmhpd_opp_turbo_l1: opp11 { 4276017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4277017e7856SSibi Sankar }; 4278017e7856SSibi Sankar }; 4279017e7856SSibi Sankar }; 428071a2fc6eSJonathan Marek 4281fc0e7dd6SKrzysztof Kozlowski apps_bcm_voter: bcm-voter { 428271a2fc6eSJonathan Marek compatible = "qcom,bcm-voter"; 428371a2fc6eSJonathan Marek }; 4284d8cf9372SVinod Koul }; 4285fea8930bSSibi Sankar 4286a6d435c1SSibi Sankar osm_l3: interconnect@18321000 { 4287a0289a10SBjorn Andersson compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4288a6d435c1SSibi Sankar reg = <0 0x18321000 0 0x1400>; 4289a6d435c1SSibi Sankar 4290a6d435c1SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4291a6d435c1SSibi Sankar clock-names = "xo", "alternate"; 4292a6d435c1SSibi Sankar 4293a6d435c1SSibi Sankar #interconnect-cells = <1>; 4294a6d435c1SSibi Sankar }; 4295a6d435c1SSibi Sankar 4296fea8930bSSibi Sankar cpufreq_hw: cpufreq@18323000 { 4297*b2e1f870SKonrad Dybcio compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw"; 4298fea8930bSSibi Sankar reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 4299fea8930bSSibi Sankar <0 0x18327800 0 0x1400>; 4300fea8930bSSibi Sankar reg-names = "freq-domain0", "freq-domain1", 4301fea8930bSSibi Sankar "freq-domain2"; 4302fea8930bSSibi Sankar 4303fea8930bSSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4304fea8930bSSibi Sankar clock-names = "xo", "alternate"; 4305fea8930bSSibi Sankar 4306fea8930bSSibi Sankar #freq-domain-cells = <1>; 4307fc725894SManivannan Sadhasivam #clock-cells = <1>; 4308fea8930bSSibi Sankar }; 430905090bb9SJonathan Marek 43102ffcfe79SThara Gopinath lmh_cluster1: lmh@18350800 { 43112ffcfe79SThara Gopinath compatible = "qcom,sm8150-lmh"; 43122ffcfe79SThara Gopinath reg = <0 0x18350800 0 0x400>; 43132ffcfe79SThara Gopinath interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 43142ffcfe79SThara Gopinath cpus = <&CPU4>; 43152ffcfe79SThara Gopinath qcom,lmh-temp-arm-millicelsius = <60000>; 43162ffcfe79SThara Gopinath qcom,lmh-temp-low-millicelsius = <84500>; 43172ffcfe79SThara Gopinath qcom,lmh-temp-high-millicelsius = <85000>; 43182ffcfe79SThara Gopinath interrupt-controller; 43192ffcfe79SThara Gopinath #interrupt-cells = <1>; 43202ffcfe79SThara Gopinath }; 43212ffcfe79SThara Gopinath 43222ffcfe79SThara Gopinath lmh_cluster0: lmh@18358800 { 43232ffcfe79SThara Gopinath compatible = "qcom,sm8150-lmh"; 43242ffcfe79SThara Gopinath reg = <0 0x18358800 0 0x400>; 43252ffcfe79SThara Gopinath interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 43262ffcfe79SThara Gopinath cpus = <&CPU0>; 43272ffcfe79SThara Gopinath qcom,lmh-temp-arm-millicelsius = <60000>; 43282ffcfe79SThara Gopinath qcom,lmh-temp-low-millicelsius = <84500>; 43292ffcfe79SThara Gopinath qcom,lmh-temp-high-millicelsius = <85000>; 43302ffcfe79SThara Gopinath interrupt-controller; 43312ffcfe79SThara Gopinath #interrupt-cells = <1>; 43322ffcfe79SThara Gopinath }; 43332ffcfe79SThara Gopinath 433405090bb9SJonathan Marek wifi: wifi@18800000 { 433505090bb9SJonathan Marek compatible = "qcom,wcn3990-wifi"; 433605090bb9SJonathan Marek reg = <0 0x18800000 0 0x800000>; 433705090bb9SJonathan Marek reg-names = "membase"; 433805090bb9SJonathan Marek memory-region = <&wlan_mem>; 433905090bb9SJonathan Marek clock-names = "cxo_ref_clk_pin", "qdss"; 434005090bb9SJonathan Marek clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 434105090bb9SJonathan Marek interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 434205090bb9SJonathan Marek <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 434305090bb9SJonathan Marek <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 434405090bb9SJonathan Marek <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 434505090bb9SJonathan Marek <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 434605090bb9SJonathan Marek <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 434705090bb9SJonathan Marek <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 434805090bb9SJonathan Marek <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 434905090bb9SJonathan Marek <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 435005090bb9SJonathan Marek <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 435105090bb9SJonathan Marek <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 435205090bb9SJonathan Marek <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 435305090bb9SJonathan Marek iommus = <&apps_smmu 0x0640 0x1>; 435405090bb9SJonathan Marek status = "disabled"; 435505090bb9SJonathan Marek }; 4356e13c6d14SVinod Koul }; 4357e13c6d14SVinod Koul 4358e13c6d14SVinod Koul timer { 4359e13c6d14SVinod Koul compatible = "arm,armv8-timer"; 4360e13c6d14SVinod Koul interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4361e13c6d14SVinod Koul <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4362e13c6d14SVinod Koul <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4363e13c6d14SVinod Koul <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4364e13c6d14SVinod Koul }; 4365d2fa630cSAmit Kucheria 4366d2fa630cSAmit Kucheria thermal-zones { 4367d2fa630cSAmit Kucheria cpu0-thermal { 4368d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4369d2fa630cSAmit Kucheria polling-delay = <1000>; 4370d2fa630cSAmit Kucheria 4371d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 1>; 4372d2fa630cSAmit Kucheria 4373d2fa630cSAmit Kucheria trips { 4374d2fa630cSAmit Kucheria cpu0_alert0: trip-point0 { 4375d2fa630cSAmit Kucheria temperature = <90000>; 4376d2fa630cSAmit Kucheria hysteresis = <2000>; 4377d2fa630cSAmit Kucheria type = "passive"; 4378d2fa630cSAmit Kucheria }; 4379d2fa630cSAmit Kucheria 4380d2fa630cSAmit Kucheria cpu0_alert1: trip-point1 { 4381d2fa630cSAmit Kucheria temperature = <95000>; 4382d2fa630cSAmit Kucheria hysteresis = <2000>; 4383d2fa630cSAmit Kucheria type = "passive"; 4384d2fa630cSAmit Kucheria }; 4385d2fa630cSAmit Kucheria 43861364acc3SKrzysztof Kozlowski cpu0_crit: cpu-crit { 4387d2fa630cSAmit Kucheria temperature = <110000>; 4388d2fa630cSAmit Kucheria hysteresis = <1000>; 4389d2fa630cSAmit Kucheria type = "critical"; 4390d2fa630cSAmit Kucheria }; 4391d2fa630cSAmit Kucheria }; 4392d2fa630cSAmit Kucheria 4393d2fa630cSAmit Kucheria cooling-maps { 4394d2fa630cSAmit Kucheria map0 { 4395d2fa630cSAmit Kucheria trip = <&cpu0_alert0>; 4396d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4397d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4398d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4399d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4400d2fa630cSAmit Kucheria }; 4401d2fa630cSAmit Kucheria map1 { 4402d2fa630cSAmit Kucheria trip = <&cpu0_alert1>; 4403d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4404d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4405d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4406d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4407d2fa630cSAmit Kucheria }; 4408d2fa630cSAmit Kucheria }; 4409d2fa630cSAmit Kucheria }; 4410d2fa630cSAmit Kucheria 4411d2fa630cSAmit Kucheria cpu1-thermal { 4412d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4413d2fa630cSAmit Kucheria polling-delay = <1000>; 4414d2fa630cSAmit Kucheria 4415d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 2>; 4416d2fa630cSAmit Kucheria 4417d2fa630cSAmit Kucheria trips { 4418d2fa630cSAmit Kucheria cpu1_alert0: trip-point0 { 4419d2fa630cSAmit Kucheria temperature = <90000>; 4420d2fa630cSAmit Kucheria hysteresis = <2000>; 4421d2fa630cSAmit Kucheria type = "passive"; 4422d2fa630cSAmit Kucheria }; 4423d2fa630cSAmit Kucheria 4424d2fa630cSAmit Kucheria cpu1_alert1: trip-point1 { 4425d2fa630cSAmit Kucheria temperature = <95000>; 4426d2fa630cSAmit Kucheria hysteresis = <2000>; 4427d2fa630cSAmit Kucheria type = "passive"; 4428d2fa630cSAmit Kucheria }; 4429d2fa630cSAmit Kucheria 44301364acc3SKrzysztof Kozlowski cpu1_crit: cpu-crit { 4431d2fa630cSAmit Kucheria temperature = <110000>; 4432d2fa630cSAmit Kucheria hysteresis = <1000>; 4433d2fa630cSAmit Kucheria type = "critical"; 4434d2fa630cSAmit Kucheria }; 4435d2fa630cSAmit Kucheria }; 4436d2fa630cSAmit Kucheria 4437d2fa630cSAmit Kucheria cooling-maps { 4438d2fa630cSAmit Kucheria map0 { 4439d2fa630cSAmit Kucheria trip = <&cpu1_alert0>; 4440d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4441d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4442d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4443d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4444d2fa630cSAmit Kucheria }; 4445d2fa630cSAmit Kucheria map1 { 4446d2fa630cSAmit Kucheria trip = <&cpu1_alert1>; 4447d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4448d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4449d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4450d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4451d2fa630cSAmit Kucheria }; 4452d2fa630cSAmit Kucheria }; 4453d2fa630cSAmit Kucheria }; 4454d2fa630cSAmit Kucheria 4455d2fa630cSAmit Kucheria cpu2-thermal { 4456d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4457d2fa630cSAmit Kucheria polling-delay = <1000>; 4458d2fa630cSAmit Kucheria 4459d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 3>; 4460d2fa630cSAmit Kucheria 4461d2fa630cSAmit Kucheria trips { 4462d2fa630cSAmit Kucheria cpu2_alert0: trip-point0 { 4463d2fa630cSAmit Kucheria temperature = <90000>; 4464d2fa630cSAmit Kucheria hysteresis = <2000>; 4465d2fa630cSAmit Kucheria type = "passive"; 4466d2fa630cSAmit Kucheria }; 4467d2fa630cSAmit Kucheria 4468d2fa630cSAmit Kucheria cpu2_alert1: trip-point1 { 4469d2fa630cSAmit Kucheria temperature = <95000>; 4470d2fa630cSAmit Kucheria hysteresis = <2000>; 4471d2fa630cSAmit Kucheria type = "passive"; 4472d2fa630cSAmit Kucheria }; 4473d2fa630cSAmit Kucheria 44741364acc3SKrzysztof Kozlowski cpu2_crit: cpu-crit { 4475d2fa630cSAmit Kucheria temperature = <110000>; 4476d2fa630cSAmit Kucheria hysteresis = <1000>; 4477d2fa630cSAmit Kucheria type = "critical"; 4478d2fa630cSAmit Kucheria }; 4479d2fa630cSAmit Kucheria }; 4480d2fa630cSAmit Kucheria 4481d2fa630cSAmit Kucheria cooling-maps { 4482d2fa630cSAmit Kucheria map0 { 4483d2fa630cSAmit Kucheria trip = <&cpu2_alert0>; 4484d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4485d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4486d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4487d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4488d2fa630cSAmit Kucheria }; 4489d2fa630cSAmit Kucheria map1 { 4490d2fa630cSAmit Kucheria trip = <&cpu2_alert1>; 4491d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4492d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4493d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4494d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4495d2fa630cSAmit Kucheria }; 4496d2fa630cSAmit Kucheria }; 4497d2fa630cSAmit Kucheria }; 4498d2fa630cSAmit Kucheria 4499d2fa630cSAmit Kucheria cpu3-thermal { 4500d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4501d2fa630cSAmit Kucheria polling-delay = <1000>; 4502d2fa630cSAmit Kucheria 4503d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 4>; 4504d2fa630cSAmit Kucheria 4505d2fa630cSAmit Kucheria trips { 4506d2fa630cSAmit Kucheria cpu3_alert0: trip-point0 { 4507d2fa630cSAmit Kucheria temperature = <90000>; 4508d2fa630cSAmit Kucheria hysteresis = <2000>; 4509d2fa630cSAmit Kucheria type = "passive"; 4510d2fa630cSAmit Kucheria }; 4511d2fa630cSAmit Kucheria 4512d2fa630cSAmit Kucheria cpu3_alert1: trip-point1 { 4513d2fa630cSAmit Kucheria temperature = <95000>; 4514d2fa630cSAmit Kucheria hysteresis = <2000>; 4515d2fa630cSAmit Kucheria type = "passive"; 4516d2fa630cSAmit Kucheria }; 4517d2fa630cSAmit Kucheria 45181364acc3SKrzysztof Kozlowski cpu3_crit: cpu-crit { 4519d2fa630cSAmit Kucheria temperature = <110000>; 4520d2fa630cSAmit Kucheria hysteresis = <1000>; 4521d2fa630cSAmit Kucheria type = "critical"; 4522d2fa630cSAmit Kucheria }; 4523d2fa630cSAmit Kucheria }; 4524d2fa630cSAmit Kucheria 4525d2fa630cSAmit Kucheria cooling-maps { 4526d2fa630cSAmit Kucheria map0 { 4527d2fa630cSAmit Kucheria trip = <&cpu3_alert0>; 4528d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4529d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4530d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4531d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4532d2fa630cSAmit Kucheria }; 4533d2fa630cSAmit Kucheria map1 { 4534d2fa630cSAmit Kucheria trip = <&cpu3_alert1>; 4535d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4536d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4537d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4538d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4539d2fa630cSAmit Kucheria }; 4540d2fa630cSAmit Kucheria }; 4541d2fa630cSAmit Kucheria }; 4542d2fa630cSAmit Kucheria 4543d2fa630cSAmit Kucheria cpu4-top-thermal { 4544d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4545d2fa630cSAmit Kucheria polling-delay = <1000>; 4546d2fa630cSAmit Kucheria 4547d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 7>; 4548d2fa630cSAmit Kucheria 4549d2fa630cSAmit Kucheria trips { 4550d2fa630cSAmit Kucheria cpu4_top_alert0: trip-point0 { 4551d2fa630cSAmit Kucheria temperature = <90000>; 4552d2fa630cSAmit Kucheria hysteresis = <2000>; 4553d2fa630cSAmit Kucheria type = "passive"; 4554d2fa630cSAmit Kucheria }; 4555d2fa630cSAmit Kucheria 4556d2fa630cSAmit Kucheria cpu4_top_alert1: trip-point1 { 4557d2fa630cSAmit Kucheria temperature = <95000>; 4558d2fa630cSAmit Kucheria hysteresis = <2000>; 4559d2fa630cSAmit Kucheria type = "passive"; 4560d2fa630cSAmit Kucheria }; 4561d2fa630cSAmit Kucheria 45621364acc3SKrzysztof Kozlowski cpu4_top_crit: cpu-crit { 4563d2fa630cSAmit Kucheria temperature = <110000>; 4564d2fa630cSAmit Kucheria hysteresis = <1000>; 4565d2fa630cSAmit Kucheria type = "critical"; 4566d2fa630cSAmit Kucheria }; 4567d2fa630cSAmit Kucheria }; 4568d2fa630cSAmit Kucheria 4569d2fa630cSAmit Kucheria cooling-maps { 4570d2fa630cSAmit Kucheria map0 { 4571d2fa630cSAmit Kucheria trip = <&cpu4_top_alert0>; 4572d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4573d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4574d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4575d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4576d2fa630cSAmit Kucheria }; 4577d2fa630cSAmit Kucheria map1 { 4578d2fa630cSAmit Kucheria trip = <&cpu4_top_alert1>; 4579d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4580d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4581d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4582d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4583d2fa630cSAmit Kucheria }; 4584d2fa630cSAmit Kucheria }; 4585d2fa630cSAmit Kucheria }; 4586d2fa630cSAmit Kucheria 4587d2fa630cSAmit Kucheria cpu5-top-thermal { 4588d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4589d2fa630cSAmit Kucheria polling-delay = <1000>; 4590d2fa630cSAmit Kucheria 4591d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 8>; 4592d2fa630cSAmit Kucheria 4593d2fa630cSAmit Kucheria trips { 4594d2fa630cSAmit Kucheria cpu5_top_alert0: trip-point0 { 4595d2fa630cSAmit Kucheria temperature = <90000>; 4596d2fa630cSAmit Kucheria hysteresis = <2000>; 4597d2fa630cSAmit Kucheria type = "passive"; 4598d2fa630cSAmit Kucheria }; 4599d2fa630cSAmit Kucheria 4600d2fa630cSAmit Kucheria cpu5_top_alert1: trip-point1 { 4601d2fa630cSAmit Kucheria temperature = <95000>; 4602d2fa630cSAmit Kucheria hysteresis = <2000>; 4603d2fa630cSAmit Kucheria type = "passive"; 4604d2fa630cSAmit Kucheria }; 4605d2fa630cSAmit Kucheria 46061364acc3SKrzysztof Kozlowski cpu5_top_crit: cpu-crit { 4607d2fa630cSAmit Kucheria temperature = <110000>; 4608d2fa630cSAmit Kucheria hysteresis = <1000>; 4609d2fa630cSAmit Kucheria type = "critical"; 4610d2fa630cSAmit Kucheria }; 4611d2fa630cSAmit Kucheria }; 4612d2fa630cSAmit Kucheria 4613d2fa630cSAmit Kucheria cooling-maps { 4614d2fa630cSAmit Kucheria map0 { 4615d2fa630cSAmit Kucheria trip = <&cpu5_top_alert0>; 4616d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4617d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4618d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4619d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4620d2fa630cSAmit Kucheria }; 4621d2fa630cSAmit Kucheria map1 { 4622d2fa630cSAmit Kucheria trip = <&cpu5_top_alert1>; 4623d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4624d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4625d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4626d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4627d2fa630cSAmit Kucheria }; 4628d2fa630cSAmit Kucheria }; 4629d2fa630cSAmit Kucheria }; 4630d2fa630cSAmit Kucheria 4631d2fa630cSAmit Kucheria cpu6-top-thermal { 4632d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4633d2fa630cSAmit Kucheria polling-delay = <1000>; 4634d2fa630cSAmit Kucheria 4635d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 9>; 4636d2fa630cSAmit Kucheria 4637d2fa630cSAmit Kucheria trips { 4638d2fa630cSAmit Kucheria cpu6_top_alert0: trip-point0 { 4639d2fa630cSAmit Kucheria temperature = <90000>; 4640d2fa630cSAmit Kucheria hysteresis = <2000>; 4641d2fa630cSAmit Kucheria type = "passive"; 4642d2fa630cSAmit Kucheria }; 4643d2fa630cSAmit Kucheria 4644d2fa630cSAmit Kucheria cpu6_top_alert1: trip-point1 { 4645d2fa630cSAmit Kucheria temperature = <95000>; 4646d2fa630cSAmit Kucheria hysteresis = <2000>; 4647d2fa630cSAmit Kucheria type = "passive"; 4648d2fa630cSAmit Kucheria }; 4649d2fa630cSAmit Kucheria 46501364acc3SKrzysztof Kozlowski cpu6_top_crit: cpu-crit { 4651d2fa630cSAmit Kucheria temperature = <110000>; 4652d2fa630cSAmit Kucheria hysteresis = <1000>; 4653d2fa630cSAmit Kucheria type = "critical"; 4654d2fa630cSAmit Kucheria }; 4655d2fa630cSAmit Kucheria }; 4656d2fa630cSAmit Kucheria 4657d2fa630cSAmit Kucheria cooling-maps { 4658d2fa630cSAmit Kucheria map0 { 4659d2fa630cSAmit Kucheria trip = <&cpu6_top_alert0>; 4660d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4661d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4662d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4663d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4664d2fa630cSAmit Kucheria }; 4665d2fa630cSAmit Kucheria map1 { 4666d2fa630cSAmit Kucheria trip = <&cpu6_top_alert1>; 4667d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4668d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4669d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4670d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4671d2fa630cSAmit Kucheria }; 4672d2fa630cSAmit Kucheria }; 4673d2fa630cSAmit Kucheria }; 4674d2fa630cSAmit Kucheria 4675d2fa630cSAmit Kucheria cpu7-top-thermal { 4676d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4677d2fa630cSAmit Kucheria polling-delay = <1000>; 4678d2fa630cSAmit Kucheria 4679d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 10>; 4680d2fa630cSAmit Kucheria 4681d2fa630cSAmit Kucheria trips { 4682d2fa630cSAmit Kucheria cpu7_top_alert0: trip-point0 { 4683d2fa630cSAmit Kucheria temperature = <90000>; 4684d2fa630cSAmit Kucheria hysteresis = <2000>; 4685d2fa630cSAmit Kucheria type = "passive"; 4686d2fa630cSAmit Kucheria }; 4687d2fa630cSAmit Kucheria 4688d2fa630cSAmit Kucheria cpu7_top_alert1: trip-point1 { 4689d2fa630cSAmit Kucheria temperature = <95000>; 4690d2fa630cSAmit Kucheria hysteresis = <2000>; 4691d2fa630cSAmit Kucheria type = "passive"; 4692d2fa630cSAmit Kucheria }; 4693d2fa630cSAmit Kucheria 46941364acc3SKrzysztof Kozlowski cpu7_top_crit: cpu-crit { 4695d2fa630cSAmit Kucheria temperature = <110000>; 4696d2fa630cSAmit Kucheria hysteresis = <1000>; 4697d2fa630cSAmit Kucheria type = "critical"; 4698d2fa630cSAmit Kucheria }; 4699d2fa630cSAmit Kucheria }; 4700d2fa630cSAmit Kucheria 4701d2fa630cSAmit Kucheria cooling-maps { 4702d2fa630cSAmit Kucheria map0 { 4703d2fa630cSAmit Kucheria trip = <&cpu7_top_alert0>; 4704d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4705d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4706d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4707d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4708d2fa630cSAmit Kucheria }; 4709d2fa630cSAmit Kucheria map1 { 4710d2fa630cSAmit Kucheria trip = <&cpu7_top_alert1>; 4711d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4712d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4713d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4714d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4715d2fa630cSAmit Kucheria }; 4716d2fa630cSAmit Kucheria }; 4717d2fa630cSAmit Kucheria }; 4718d2fa630cSAmit Kucheria 4719d2fa630cSAmit Kucheria cpu4-bottom-thermal { 4720d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4721d2fa630cSAmit Kucheria polling-delay = <1000>; 4722d2fa630cSAmit Kucheria 4723d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 11>; 4724d2fa630cSAmit Kucheria 4725d2fa630cSAmit Kucheria trips { 4726d2fa630cSAmit Kucheria cpu4_bottom_alert0: trip-point0 { 4727d2fa630cSAmit Kucheria temperature = <90000>; 4728d2fa630cSAmit Kucheria hysteresis = <2000>; 4729d2fa630cSAmit Kucheria type = "passive"; 4730d2fa630cSAmit Kucheria }; 4731d2fa630cSAmit Kucheria 4732d2fa630cSAmit Kucheria cpu4_bottom_alert1: trip-point1 { 4733d2fa630cSAmit Kucheria temperature = <95000>; 4734d2fa630cSAmit Kucheria hysteresis = <2000>; 4735d2fa630cSAmit Kucheria type = "passive"; 4736d2fa630cSAmit Kucheria }; 4737d2fa630cSAmit Kucheria 47381364acc3SKrzysztof Kozlowski cpu4_bottom_crit: cpu-crit { 4739d2fa630cSAmit Kucheria temperature = <110000>; 4740d2fa630cSAmit Kucheria hysteresis = <1000>; 4741d2fa630cSAmit Kucheria type = "critical"; 4742d2fa630cSAmit Kucheria }; 4743d2fa630cSAmit Kucheria }; 4744d2fa630cSAmit Kucheria 4745d2fa630cSAmit Kucheria cooling-maps { 4746d2fa630cSAmit Kucheria map0 { 4747d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert0>; 4748d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4749d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4750d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4751d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4752d2fa630cSAmit Kucheria }; 4753d2fa630cSAmit Kucheria map1 { 4754d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert1>; 4755d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4756d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4757d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4758d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4759d2fa630cSAmit Kucheria }; 4760d2fa630cSAmit Kucheria }; 4761d2fa630cSAmit Kucheria }; 4762d2fa630cSAmit Kucheria 4763d2fa630cSAmit Kucheria cpu5-bottom-thermal { 4764d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4765d2fa630cSAmit Kucheria polling-delay = <1000>; 4766d2fa630cSAmit Kucheria 4767d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 12>; 4768d2fa630cSAmit Kucheria 4769d2fa630cSAmit Kucheria trips { 4770d2fa630cSAmit Kucheria cpu5_bottom_alert0: trip-point0 { 4771d2fa630cSAmit Kucheria temperature = <90000>; 4772d2fa630cSAmit Kucheria hysteresis = <2000>; 4773d2fa630cSAmit Kucheria type = "passive"; 4774d2fa630cSAmit Kucheria }; 4775d2fa630cSAmit Kucheria 4776d2fa630cSAmit Kucheria cpu5_bottom_alert1: trip-point1 { 4777d2fa630cSAmit Kucheria temperature = <95000>; 4778d2fa630cSAmit Kucheria hysteresis = <2000>; 4779d2fa630cSAmit Kucheria type = "passive"; 4780d2fa630cSAmit Kucheria }; 4781d2fa630cSAmit Kucheria 47821364acc3SKrzysztof Kozlowski cpu5_bottom_crit: cpu-crit { 4783d2fa630cSAmit Kucheria temperature = <110000>; 4784d2fa630cSAmit Kucheria hysteresis = <1000>; 4785d2fa630cSAmit Kucheria type = "critical"; 4786d2fa630cSAmit Kucheria }; 4787d2fa630cSAmit Kucheria }; 4788d2fa630cSAmit Kucheria 4789d2fa630cSAmit Kucheria cooling-maps { 4790d2fa630cSAmit Kucheria map0 { 4791d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert0>; 4792d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4793d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4794d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4795d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4796d2fa630cSAmit Kucheria }; 4797d2fa630cSAmit Kucheria map1 { 4798d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert1>; 4799d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4800d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4801d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4802d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4803d2fa630cSAmit Kucheria }; 4804d2fa630cSAmit Kucheria }; 4805d2fa630cSAmit Kucheria }; 4806d2fa630cSAmit Kucheria 4807d2fa630cSAmit Kucheria cpu6-bottom-thermal { 4808d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4809d2fa630cSAmit Kucheria polling-delay = <1000>; 4810d2fa630cSAmit Kucheria 4811d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 13>; 4812d2fa630cSAmit Kucheria 4813d2fa630cSAmit Kucheria trips { 4814d2fa630cSAmit Kucheria cpu6_bottom_alert0: trip-point0 { 4815d2fa630cSAmit Kucheria temperature = <90000>; 4816d2fa630cSAmit Kucheria hysteresis = <2000>; 4817d2fa630cSAmit Kucheria type = "passive"; 4818d2fa630cSAmit Kucheria }; 4819d2fa630cSAmit Kucheria 4820d2fa630cSAmit Kucheria cpu6_bottom_alert1: trip-point1 { 4821d2fa630cSAmit Kucheria temperature = <95000>; 4822d2fa630cSAmit Kucheria hysteresis = <2000>; 4823d2fa630cSAmit Kucheria type = "passive"; 4824d2fa630cSAmit Kucheria }; 4825d2fa630cSAmit Kucheria 48261364acc3SKrzysztof Kozlowski cpu6_bottom_crit: cpu-crit { 4827d2fa630cSAmit Kucheria temperature = <110000>; 4828d2fa630cSAmit Kucheria hysteresis = <1000>; 4829d2fa630cSAmit Kucheria type = "critical"; 4830d2fa630cSAmit Kucheria }; 4831d2fa630cSAmit Kucheria }; 4832d2fa630cSAmit Kucheria 4833d2fa630cSAmit Kucheria cooling-maps { 4834d2fa630cSAmit Kucheria map0 { 4835d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert0>; 4836d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4837d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4838d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4839d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4840d2fa630cSAmit Kucheria }; 4841d2fa630cSAmit Kucheria map1 { 4842d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert1>; 4843d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4844d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4845d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4846d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4847d2fa630cSAmit Kucheria }; 4848d2fa630cSAmit Kucheria }; 4849d2fa630cSAmit Kucheria }; 4850d2fa630cSAmit Kucheria 4851d2fa630cSAmit Kucheria cpu7-bottom-thermal { 4852d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4853d2fa630cSAmit Kucheria polling-delay = <1000>; 4854d2fa630cSAmit Kucheria 4855d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 14>; 4856d2fa630cSAmit Kucheria 4857d2fa630cSAmit Kucheria trips { 4858d2fa630cSAmit Kucheria cpu7_bottom_alert0: trip-point0 { 4859d2fa630cSAmit Kucheria temperature = <90000>; 4860d2fa630cSAmit Kucheria hysteresis = <2000>; 4861d2fa630cSAmit Kucheria type = "passive"; 4862d2fa630cSAmit Kucheria }; 4863d2fa630cSAmit Kucheria 4864d2fa630cSAmit Kucheria cpu7_bottom_alert1: trip-point1 { 4865d2fa630cSAmit Kucheria temperature = <95000>; 4866d2fa630cSAmit Kucheria hysteresis = <2000>; 4867d2fa630cSAmit Kucheria type = "passive"; 4868d2fa630cSAmit Kucheria }; 4869d2fa630cSAmit Kucheria 48701364acc3SKrzysztof Kozlowski cpu7_bottom_crit: cpu-crit { 4871d2fa630cSAmit Kucheria temperature = <110000>; 4872d2fa630cSAmit Kucheria hysteresis = <1000>; 4873d2fa630cSAmit Kucheria type = "critical"; 4874d2fa630cSAmit Kucheria }; 4875d2fa630cSAmit Kucheria }; 4876d2fa630cSAmit Kucheria 4877d2fa630cSAmit Kucheria cooling-maps { 4878d2fa630cSAmit Kucheria map0 { 4879d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert0>; 4880d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4881d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4882d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4883d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4884d2fa630cSAmit Kucheria }; 4885d2fa630cSAmit Kucheria map1 { 4886d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert1>; 4887d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4888d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4889d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4890d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4891d2fa630cSAmit Kucheria }; 4892d2fa630cSAmit Kucheria }; 4893d2fa630cSAmit Kucheria }; 4894d2fa630cSAmit Kucheria 4895d2fa630cSAmit Kucheria aoss0-thermal { 4896d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4897d2fa630cSAmit Kucheria polling-delay = <1000>; 4898d2fa630cSAmit Kucheria 4899d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 0>; 4900d2fa630cSAmit Kucheria 4901d2fa630cSAmit Kucheria trips { 4902d2fa630cSAmit Kucheria aoss0_alert0: trip-point0 { 4903d2fa630cSAmit Kucheria temperature = <90000>; 4904d2fa630cSAmit Kucheria hysteresis = <2000>; 4905d2fa630cSAmit Kucheria type = "hot"; 4906d2fa630cSAmit Kucheria }; 4907d2fa630cSAmit Kucheria }; 4908d2fa630cSAmit Kucheria }; 4909d2fa630cSAmit Kucheria 4910d2fa630cSAmit Kucheria cluster0-thermal { 4911d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4912d2fa630cSAmit Kucheria polling-delay = <1000>; 4913d2fa630cSAmit Kucheria 4914d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 5>; 4915d2fa630cSAmit Kucheria 4916d2fa630cSAmit Kucheria trips { 4917d2fa630cSAmit Kucheria cluster0_alert0: trip-point0 { 4918d2fa630cSAmit Kucheria temperature = <90000>; 4919d2fa630cSAmit Kucheria hysteresis = <2000>; 4920d2fa630cSAmit Kucheria type = "hot"; 4921d2fa630cSAmit Kucheria }; 4922d2fa630cSAmit Kucheria cluster0_crit: cluster0_crit { 4923d2fa630cSAmit Kucheria temperature = <110000>; 4924d2fa630cSAmit Kucheria hysteresis = <2000>; 4925d2fa630cSAmit Kucheria type = "critical"; 4926d2fa630cSAmit Kucheria }; 4927d2fa630cSAmit Kucheria }; 4928d2fa630cSAmit Kucheria }; 4929d2fa630cSAmit Kucheria 4930d2fa630cSAmit Kucheria cluster1-thermal { 4931d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4932d2fa630cSAmit Kucheria polling-delay = <1000>; 4933d2fa630cSAmit Kucheria 4934d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 6>; 4935d2fa630cSAmit Kucheria 4936d2fa630cSAmit Kucheria trips { 4937d2fa630cSAmit Kucheria cluster1_alert0: trip-point0 { 4938d2fa630cSAmit Kucheria temperature = <90000>; 4939d2fa630cSAmit Kucheria hysteresis = <2000>; 4940d2fa630cSAmit Kucheria type = "hot"; 4941d2fa630cSAmit Kucheria }; 4942d2fa630cSAmit Kucheria cluster1_crit: cluster1_crit { 4943d2fa630cSAmit Kucheria temperature = <110000>; 4944d2fa630cSAmit Kucheria hysteresis = <2000>; 4945d2fa630cSAmit Kucheria type = "critical"; 4946d2fa630cSAmit Kucheria }; 4947d2fa630cSAmit Kucheria }; 4948d2fa630cSAmit Kucheria }; 4949d2fa630cSAmit Kucheria 49507be1c395SDavid Heidelberg gpu-top-thermal { 4951d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4952d2fa630cSAmit Kucheria polling-delay = <1000>; 4953d2fa630cSAmit Kucheria 4954d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 15>; 4955d2fa630cSAmit Kucheria 4956d2fa630cSAmit Kucheria trips { 4957d2fa630cSAmit Kucheria gpu1_alert0: trip-point0 { 4958d2fa630cSAmit Kucheria temperature = <90000>; 4959d2fa630cSAmit Kucheria hysteresis = <2000>; 4960d2fa630cSAmit Kucheria type = "hot"; 4961d2fa630cSAmit Kucheria }; 4962d2fa630cSAmit Kucheria }; 4963d2fa630cSAmit Kucheria }; 4964d2fa630cSAmit Kucheria 4965d2fa630cSAmit Kucheria aoss1-thermal { 4966d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4967d2fa630cSAmit Kucheria polling-delay = <1000>; 4968d2fa630cSAmit Kucheria 4969d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 0>; 4970d2fa630cSAmit Kucheria 4971d2fa630cSAmit Kucheria trips { 4972d2fa630cSAmit Kucheria aoss1_alert0: trip-point0 { 4973d2fa630cSAmit Kucheria temperature = <90000>; 4974d2fa630cSAmit Kucheria hysteresis = <2000>; 4975d2fa630cSAmit Kucheria type = "hot"; 4976d2fa630cSAmit Kucheria }; 4977d2fa630cSAmit Kucheria }; 4978d2fa630cSAmit Kucheria }; 4979d2fa630cSAmit Kucheria 4980d2fa630cSAmit Kucheria wlan-thermal { 4981d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4982d2fa630cSAmit Kucheria polling-delay = <1000>; 4983d2fa630cSAmit Kucheria 4984d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 1>; 4985d2fa630cSAmit Kucheria 4986d2fa630cSAmit Kucheria trips { 4987d2fa630cSAmit Kucheria wlan_alert0: trip-point0 { 4988d2fa630cSAmit Kucheria temperature = <90000>; 4989d2fa630cSAmit Kucheria hysteresis = <2000>; 4990d2fa630cSAmit Kucheria type = "hot"; 4991d2fa630cSAmit Kucheria }; 4992d2fa630cSAmit Kucheria }; 4993d2fa630cSAmit Kucheria }; 4994d2fa630cSAmit Kucheria 4995d2fa630cSAmit Kucheria video-thermal { 4996d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4997d2fa630cSAmit Kucheria polling-delay = <1000>; 4998d2fa630cSAmit Kucheria 4999d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 2>; 5000d2fa630cSAmit Kucheria 5001d2fa630cSAmit Kucheria trips { 5002d2fa630cSAmit Kucheria video_alert0: trip-point0 { 5003d2fa630cSAmit Kucheria temperature = <90000>; 5004d2fa630cSAmit Kucheria hysteresis = <2000>; 5005d2fa630cSAmit Kucheria type = "hot"; 5006d2fa630cSAmit Kucheria }; 5007d2fa630cSAmit Kucheria }; 5008d2fa630cSAmit Kucheria }; 5009d2fa630cSAmit Kucheria 5010d2fa630cSAmit Kucheria mem-thermal { 5011d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5012d2fa630cSAmit Kucheria polling-delay = <1000>; 5013d2fa630cSAmit Kucheria 5014d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 3>; 5015d2fa630cSAmit Kucheria 5016d2fa630cSAmit Kucheria trips { 5017d2fa630cSAmit Kucheria mem_alert0: trip-point0 { 5018d2fa630cSAmit Kucheria temperature = <90000>; 5019d2fa630cSAmit Kucheria hysteresis = <2000>; 5020d2fa630cSAmit Kucheria type = "hot"; 5021d2fa630cSAmit Kucheria }; 5022d2fa630cSAmit Kucheria }; 5023d2fa630cSAmit Kucheria }; 5024d2fa630cSAmit Kucheria 5025d2fa630cSAmit Kucheria q6-hvx-thermal { 5026d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5027d2fa630cSAmit Kucheria polling-delay = <1000>; 5028d2fa630cSAmit Kucheria 5029d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 4>; 5030d2fa630cSAmit Kucheria 5031d2fa630cSAmit Kucheria trips { 5032d2fa630cSAmit Kucheria q6_hvx_alert0: trip-point0 { 5033d2fa630cSAmit Kucheria temperature = <90000>; 5034d2fa630cSAmit Kucheria hysteresis = <2000>; 5035d2fa630cSAmit Kucheria type = "hot"; 5036d2fa630cSAmit Kucheria }; 5037d2fa630cSAmit Kucheria }; 5038d2fa630cSAmit Kucheria }; 5039d2fa630cSAmit Kucheria 5040d2fa630cSAmit Kucheria camera-thermal { 5041d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5042d2fa630cSAmit Kucheria polling-delay = <1000>; 5043d2fa630cSAmit Kucheria 5044d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 5>; 5045d2fa630cSAmit Kucheria 5046d2fa630cSAmit Kucheria trips { 5047d2fa630cSAmit Kucheria camera_alert0: trip-point0 { 5048d2fa630cSAmit Kucheria temperature = <90000>; 5049d2fa630cSAmit Kucheria hysteresis = <2000>; 5050d2fa630cSAmit Kucheria type = "hot"; 5051d2fa630cSAmit Kucheria }; 5052d2fa630cSAmit Kucheria }; 5053d2fa630cSAmit Kucheria }; 5054d2fa630cSAmit Kucheria 5055d2fa630cSAmit Kucheria compute-thermal { 5056d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5057d2fa630cSAmit Kucheria polling-delay = <1000>; 5058d2fa630cSAmit Kucheria 5059d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 6>; 5060d2fa630cSAmit Kucheria 5061d2fa630cSAmit Kucheria trips { 5062d2fa630cSAmit Kucheria compute_alert0: trip-point0 { 5063d2fa630cSAmit Kucheria temperature = <90000>; 5064d2fa630cSAmit Kucheria hysteresis = <2000>; 5065d2fa630cSAmit Kucheria type = "hot"; 5066d2fa630cSAmit Kucheria }; 5067d2fa630cSAmit Kucheria }; 5068d2fa630cSAmit Kucheria }; 5069d2fa630cSAmit Kucheria 5070d2fa630cSAmit Kucheria modem-thermal { 5071d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5072d2fa630cSAmit Kucheria polling-delay = <1000>; 5073d2fa630cSAmit Kucheria 5074d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 7>; 5075d2fa630cSAmit Kucheria 5076d2fa630cSAmit Kucheria trips { 5077d2fa630cSAmit Kucheria modem_alert0: trip-point0 { 5078d2fa630cSAmit Kucheria temperature = <90000>; 5079d2fa630cSAmit Kucheria hysteresis = <2000>; 5080d2fa630cSAmit Kucheria type = "hot"; 5081d2fa630cSAmit Kucheria }; 5082d2fa630cSAmit Kucheria }; 5083d2fa630cSAmit Kucheria }; 5084d2fa630cSAmit Kucheria 5085d2fa630cSAmit Kucheria npu-thermal { 5086d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5087d2fa630cSAmit Kucheria polling-delay = <1000>; 5088d2fa630cSAmit Kucheria 5089d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 8>; 5090d2fa630cSAmit Kucheria 5091d2fa630cSAmit Kucheria trips { 5092d2fa630cSAmit Kucheria npu_alert0: trip-point0 { 5093d2fa630cSAmit Kucheria temperature = <90000>; 5094d2fa630cSAmit Kucheria hysteresis = <2000>; 5095d2fa630cSAmit Kucheria type = "hot"; 5096d2fa630cSAmit Kucheria }; 5097d2fa630cSAmit Kucheria }; 5098d2fa630cSAmit Kucheria }; 5099d2fa630cSAmit Kucheria 5100d2fa630cSAmit Kucheria modem-vec-thermal { 5101d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5102d2fa630cSAmit Kucheria polling-delay = <1000>; 5103d2fa630cSAmit Kucheria 5104d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 9>; 5105d2fa630cSAmit Kucheria 5106d2fa630cSAmit Kucheria trips { 5107d2fa630cSAmit Kucheria modem_vec_alert0: trip-point0 { 5108d2fa630cSAmit Kucheria temperature = <90000>; 5109d2fa630cSAmit Kucheria hysteresis = <2000>; 5110d2fa630cSAmit Kucheria type = "hot"; 5111d2fa630cSAmit Kucheria }; 5112d2fa630cSAmit Kucheria }; 5113d2fa630cSAmit Kucheria }; 5114d2fa630cSAmit Kucheria 5115d2fa630cSAmit Kucheria modem-scl-thermal { 5116d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5117d2fa630cSAmit Kucheria polling-delay = <1000>; 5118d2fa630cSAmit Kucheria 5119d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 10>; 5120d2fa630cSAmit Kucheria 5121d2fa630cSAmit Kucheria trips { 5122d2fa630cSAmit Kucheria modem_scl_alert0: trip-point0 { 5123d2fa630cSAmit Kucheria temperature = <90000>; 5124d2fa630cSAmit Kucheria hysteresis = <2000>; 5125d2fa630cSAmit Kucheria type = "hot"; 5126d2fa630cSAmit Kucheria }; 5127d2fa630cSAmit Kucheria }; 5128d2fa630cSAmit Kucheria }; 5129d2fa630cSAmit Kucheria 51307be1c395SDavid Heidelberg gpu-bottom-thermal { 5131d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5132d2fa630cSAmit Kucheria polling-delay = <1000>; 5133d2fa630cSAmit Kucheria 5134d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 11>; 5135d2fa630cSAmit Kucheria 5136d2fa630cSAmit Kucheria trips { 5137d2fa630cSAmit Kucheria gpu2_alert0: trip-point0 { 5138d2fa630cSAmit Kucheria temperature = <90000>; 5139d2fa630cSAmit Kucheria hysteresis = <2000>; 5140d2fa630cSAmit Kucheria type = "hot"; 5141d2fa630cSAmit Kucheria }; 5142d2fa630cSAmit Kucheria }; 5143d2fa630cSAmit Kucheria }; 5144d2fa630cSAmit Kucheria }; 5145e13c6d14SVinod Koul}; 5146