1e13c6d14SVinod Koul// SPDX-License-Identifier: BSD-3-Clause 2e13c6d14SVinod Koul/* 3e13c6d14SVinod Koul * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4e13c6d14SVinod Koul * Copyright (c) 2019, Linaro Limited 5e13c6d14SVinod Koul */ 6e13c6d14SVinod Koul 705006290SFelipe Balbi#include <dt-bindings/dma/qcom-gpi.h> 8e13c6d14SVinod Koul#include <dt-bindings/interrupt-controller/arm-gic.h> 9017e7856SSibi Sankar#include <dt-bindings/power/qcom-rpmpd.h> 10e13c6d14SVinod Koul#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11e13c6d14SVinod Koul#include <dt-bindings/clock/qcom,rpmh.h> 12d6f55763SVinod Koul#include <dt-bindings/clock/qcom,gcc-sm8150.h> 13f1269916SJonathan Marek#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 14a6d435c1SSibi Sankar#include <dt-bindings/interconnect/qcom,osm-l3.h> 152b6187abSThara Gopinath#include <dt-bindings/interconnect/qcom,sm8150.h> 16d2fa630cSAmit Kucheria#include <dt-bindings/thermal/thermal.h> 17e13c6d14SVinod Koul 18e13c6d14SVinod Koul/ { 19e13c6d14SVinod Koul interrupt-parent = <&intc>; 20e13c6d14SVinod Koul 21e13c6d14SVinod Koul #address-cells = <2>; 22e13c6d14SVinod Koul #size-cells = <2>; 23e13c6d14SVinod Koul 24e13c6d14SVinod Koul chosen { }; 25e13c6d14SVinod Koul 26e13c6d14SVinod Koul clocks { 27e13c6d14SVinod Koul xo_board: xo-board { 28e13c6d14SVinod Koul compatible = "fixed-clock"; 29e13c6d14SVinod Koul #clock-cells = <0>; 30e13c6d14SVinod Koul clock-frequency = <38400000>; 31e13c6d14SVinod Koul clock-output-names = "xo_board"; 32e13c6d14SVinod Koul }; 33e13c6d14SVinod Koul 34e13c6d14SVinod Koul sleep_clk: sleep-clk { 35e13c6d14SVinod Koul compatible = "fixed-clock"; 36e13c6d14SVinod Koul #clock-cells = <0>; 37e13c6d14SVinod Koul clock-frequency = <32764>; 38e13c6d14SVinod Koul clock-output-names = "sleep_clk"; 39e13c6d14SVinod Koul }; 40e13c6d14SVinod Koul }; 41e13c6d14SVinod Koul 42e13c6d14SVinod Koul cpus { 43e13c6d14SVinod Koul #address-cells = <2>; 44e13c6d14SVinod Koul #size-cells = <0>; 45e13c6d14SVinod Koul 46e13c6d14SVinod Koul CPU0: cpu@0 { 47e13c6d14SVinod Koul device_type = "cpu"; 48e13c6d14SVinod Koul compatible = "qcom,kryo485"; 49e13c6d14SVinod Koul reg = <0x0 0x0>; 50e13c6d14SVinod Koul enable-method = "psci"; 515b2dae72SDanny Lin capacity-dmips-mhz = <488>; 525b2dae72SDanny Lin dynamic-power-coefficient = <232>; 53e13c6d14SVinod Koul next-level-cache = <&L2_0>; 54fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 552b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 562b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 572b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 58b2e3f897SDanny Lin power-domains = <&CPU_PD0>; 59b2e3f897SDanny Lin power-domain-names = "psci"; 60d2fa630cSAmit Kucheria #cooling-cells = <2>; 61e13c6d14SVinod Koul L2_0: l2-cache { 62e13c6d14SVinod Koul compatible = "cache"; 63*9435294cSPierre Gondois cache-level = <2>; 64e13c6d14SVinod Koul next-level-cache = <&L3_0>; 65e13c6d14SVinod Koul L3_0: l3-cache { 66e13c6d14SVinod Koul compatible = "cache"; 67*9435294cSPierre Gondois cache-level = <3>; 68e13c6d14SVinod Koul }; 69e13c6d14SVinod Koul }; 70e13c6d14SVinod Koul }; 71e13c6d14SVinod Koul 72e13c6d14SVinod Koul CPU1: cpu@100 { 73e13c6d14SVinod Koul device_type = "cpu"; 74e13c6d14SVinod Koul compatible = "qcom,kryo485"; 75e13c6d14SVinod Koul reg = <0x0 0x100>; 76e13c6d14SVinod Koul enable-method = "psci"; 775b2dae72SDanny Lin capacity-dmips-mhz = <488>; 785b2dae72SDanny Lin dynamic-power-coefficient = <232>; 79e13c6d14SVinod Koul next-level-cache = <&L2_100>; 80fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 812b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 822b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 832b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 84b2e3f897SDanny Lin power-domains = <&CPU_PD1>; 85b2e3f897SDanny Lin power-domain-names = "psci"; 86d2fa630cSAmit Kucheria #cooling-cells = <2>; 87e13c6d14SVinod Koul L2_100: l2-cache { 88e13c6d14SVinod Koul compatible = "cache"; 89*9435294cSPierre Gondois cache-level = <2>; 90e13c6d14SVinod Koul next-level-cache = <&L3_0>; 91e13c6d14SVinod Koul }; 92e13c6d14SVinod Koul 93e13c6d14SVinod Koul }; 94e13c6d14SVinod Koul 95e13c6d14SVinod Koul CPU2: cpu@200 { 96e13c6d14SVinod Koul device_type = "cpu"; 97e13c6d14SVinod Koul compatible = "qcom,kryo485"; 98e13c6d14SVinod Koul reg = <0x0 0x200>; 99e13c6d14SVinod Koul enable-method = "psci"; 1005b2dae72SDanny Lin capacity-dmips-mhz = <488>; 1015b2dae72SDanny Lin dynamic-power-coefficient = <232>; 102e13c6d14SVinod Koul next-level-cache = <&L2_200>; 103fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1042b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1052b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1062b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 107b2e3f897SDanny Lin power-domains = <&CPU_PD2>; 108b2e3f897SDanny Lin power-domain-names = "psci"; 109d2fa630cSAmit Kucheria #cooling-cells = <2>; 110e13c6d14SVinod Koul L2_200: l2-cache { 111e13c6d14SVinod Koul compatible = "cache"; 112*9435294cSPierre Gondois cache-level = <2>; 113e13c6d14SVinod Koul next-level-cache = <&L3_0>; 114e13c6d14SVinod Koul }; 115e13c6d14SVinod Koul }; 116e13c6d14SVinod Koul 117e13c6d14SVinod Koul CPU3: cpu@300 { 118e13c6d14SVinod Koul device_type = "cpu"; 119e13c6d14SVinod Koul compatible = "qcom,kryo485"; 120e13c6d14SVinod Koul reg = <0x0 0x300>; 121e13c6d14SVinod Koul enable-method = "psci"; 1225b2dae72SDanny Lin capacity-dmips-mhz = <488>; 1235b2dae72SDanny Lin dynamic-power-coefficient = <232>; 124e13c6d14SVinod Koul next-level-cache = <&L2_300>; 125fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1262b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1272b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1282b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 129b2e3f897SDanny Lin power-domains = <&CPU_PD3>; 130b2e3f897SDanny Lin power-domain-names = "psci"; 131d2fa630cSAmit Kucheria #cooling-cells = <2>; 132e13c6d14SVinod Koul L2_300: l2-cache { 133e13c6d14SVinod Koul compatible = "cache"; 134*9435294cSPierre Gondois cache-level = <2>; 135e13c6d14SVinod Koul next-level-cache = <&L3_0>; 136e13c6d14SVinod Koul }; 137e13c6d14SVinod Koul }; 138e13c6d14SVinod Koul 139e13c6d14SVinod Koul CPU4: cpu@400 { 140e13c6d14SVinod Koul device_type = "cpu"; 141e13c6d14SVinod Koul compatible = "qcom,kryo485"; 142e13c6d14SVinod Koul reg = <0x0 0x400>; 143e13c6d14SVinod Koul enable-method = "psci"; 1445b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1455b2dae72SDanny Lin dynamic-power-coefficient = <369>; 146e13c6d14SVinod Koul next-level-cache = <&L2_400>; 147fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1482b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1492b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1502b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 151b2e3f897SDanny Lin power-domains = <&CPU_PD4>; 152b2e3f897SDanny Lin power-domain-names = "psci"; 153d2fa630cSAmit Kucheria #cooling-cells = <2>; 154e13c6d14SVinod Koul L2_400: l2-cache { 155e13c6d14SVinod Koul compatible = "cache"; 156*9435294cSPierre Gondois cache-level = <2>; 157e13c6d14SVinod Koul next-level-cache = <&L3_0>; 158e13c6d14SVinod Koul }; 159e13c6d14SVinod Koul }; 160e13c6d14SVinod Koul 161e13c6d14SVinod Koul CPU5: cpu@500 { 162e13c6d14SVinod Koul device_type = "cpu"; 163e13c6d14SVinod Koul compatible = "qcom,kryo485"; 164e13c6d14SVinod Koul reg = <0x0 0x500>; 165e13c6d14SVinod Koul enable-method = "psci"; 1665b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1675b2dae72SDanny Lin dynamic-power-coefficient = <369>; 168e13c6d14SVinod Koul next-level-cache = <&L2_500>; 169fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1702b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1712b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1722b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 173b2e3f897SDanny Lin power-domains = <&CPU_PD5>; 174b2e3f897SDanny Lin power-domain-names = "psci"; 175d2fa630cSAmit Kucheria #cooling-cells = <2>; 176e13c6d14SVinod Koul L2_500: l2-cache { 177e13c6d14SVinod Koul compatible = "cache"; 178*9435294cSPierre Gondois cache-level = <2>; 179e13c6d14SVinod Koul next-level-cache = <&L3_0>; 180e13c6d14SVinod Koul }; 181e13c6d14SVinod Koul }; 182e13c6d14SVinod Koul 183e13c6d14SVinod Koul CPU6: cpu@600 { 184e13c6d14SVinod Koul device_type = "cpu"; 185e13c6d14SVinod Koul compatible = "qcom,kryo485"; 186e13c6d14SVinod Koul reg = <0x0 0x600>; 187e13c6d14SVinod Koul enable-method = "psci"; 1885b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1895b2dae72SDanny Lin dynamic-power-coefficient = <369>; 190e13c6d14SVinod Koul next-level-cache = <&L2_600>; 191fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1922b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1932b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1942b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 195b2e3f897SDanny Lin power-domains = <&CPU_PD6>; 196b2e3f897SDanny Lin power-domain-names = "psci"; 197d2fa630cSAmit Kucheria #cooling-cells = <2>; 198e13c6d14SVinod Koul L2_600: l2-cache { 199e13c6d14SVinod Koul compatible = "cache"; 200*9435294cSPierre Gondois cache-level = <2>; 201e13c6d14SVinod Koul next-level-cache = <&L3_0>; 202e13c6d14SVinod Koul }; 203e13c6d14SVinod Koul }; 204e13c6d14SVinod Koul 205e13c6d14SVinod Koul CPU7: cpu@700 { 206e13c6d14SVinod Koul device_type = "cpu"; 207e13c6d14SVinod Koul compatible = "qcom,kryo485"; 208e13c6d14SVinod Koul reg = <0x0 0x700>; 209e13c6d14SVinod Koul enable-method = "psci"; 2105b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 2115b2dae72SDanny Lin dynamic-power-coefficient = <421>; 212e13c6d14SVinod Koul next-level-cache = <&L2_700>; 213fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 2>; 2142b6187abSThara Gopinath operating-points-v2 = <&cpu7_opp_table>; 2152b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 2162b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 217b2e3f897SDanny Lin power-domains = <&CPU_PD7>; 218b2e3f897SDanny Lin power-domain-names = "psci"; 219d2fa630cSAmit Kucheria #cooling-cells = <2>; 220e13c6d14SVinod Koul L2_700: l2-cache { 221e13c6d14SVinod Koul compatible = "cache"; 222*9435294cSPierre Gondois cache-level = <2>; 223e13c6d14SVinod Koul next-level-cache = <&L3_0>; 224e13c6d14SVinod Koul }; 225e13c6d14SVinod Koul }; 226066d21bcSDanny Lin 227066d21bcSDanny Lin cpu-map { 228066d21bcSDanny Lin cluster0 { 229066d21bcSDanny Lin core0 { 230066d21bcSDanny Lin cpu = <&CPU0>; 231066d21bcSDanny Lin }; 232066d21bcSDanny Lin 233066d21bcSDanny Lin core1 { 234066d21bcSDanny Lin cpu = <&CPU1>; 235066d21bcSDanny Lin }; 236066d21bcSDanny Lin 237066d21bcSDanny Lin core2 { 238066d21bcSDanny Lin cpu = <&CPU2>; 239066d21bcSDanny Lin }; 240066d21bcSDanny Lin 241066d21bcSDanny Lin core3 { 242066d21bcSDanny Lin cpu = <&CPU3>; 243066d21bcSDanny Lin }; 244066d21bcSDanny Lin 245066d21bcSDanny Lin core4 { 246066d21bcSDanny Lin cpu = <&CPU4>; 247066d21bcSDanny Lin }; 248066d21bcSDanny Lin 249066d21bcSDanny Lin core5 { 250066d21bcSDanny Lin cpu = <&CPU5>; 251066d21bcSDanny Lin }; 252066d21bcSDanny Lin 253066d21bcSDanny Lin core6 { 254066d21bcSDanny Lin cpu = <&CPU6>; 255066d21bcSDanny Lin }; 256066d21bcSDanny Lin 257066d21bcSDanny Lin core7 { 258066d21bcSDanny Lin cpu = <&CPU7>; 259066d21bcSDanny Lin }; 260066d21bcSDanny Lin }; 261066d21bcSDanny Lin }; 26281188f58SDanny Lin 26381188f58SDanny Lin idle-states { 26481188f58SDanny Lin entry-method = "psci"; 26581188f58SDanny Lin 26681188f58SDanny Lin LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 26781188f58SDanny Lin compatible = "arm,idle-state"; 26881188f58SDanny Lin idle-state-name = "little-rail-power-collapse"; 26981188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 27081188f58SDanny Lin entry-latency-us = <355>; 27181188f58SDanny Lin exit-latency-us = <909>; 27281188f58SDanny Lin min-residency-us = <3934>; 27381188f58SDanny Lin local-timer-stop; 27481188f58SDanny Lin }; 27581188f58SDanny Lin 27681188f58SDanny Lin BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 27781188f58SDanny Lin compatible = "arm,idle-state"; 27881188f58SDanny Lin idle-state-name = "big-rail-power-collapse"; 27981188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 28081188f58SDanny Lin entry-latency-us = <241>; 28181188f58SDanny Lin exit-latency-us = <1461>; 28281188f58SDanny Lin min-residency-us = <4488>; 28381188f58SDanny Lin local-timer-stop; 28481188f58SDanny Lin }; 285b2e3f897SDanny Lin }; 28681188f58SDanny Lin 287b2e3f897SDanny Lin domain-idle-states { 28881188f58SDanny Lin CLUSTER_SLEEP_0: cluster-sleep-0 { 289b2e3f897SDanny Lin compatible = "domain-idle-state"; 29081188f58SDanny Lin idle-state-name = "cluster-power-collapse"; 291b2e3f897SDanny Lin arm,psci-suspend-param = <0x4100c244>; 29281188f58SDanny Lin entry-latency-us = <3263>; 29381188f58SDanny Lin exit-latency-us = <6562>; 29481188f58SDanny Lin min-residency-us = <9987>; 29581188f58SDanny Lin local-timer-stop; 29681188f58SDanny Lin }; 29781188f58SDanny Lin }; 298e13c6d14SVinod Koul }; 299e13c6d14SVinod Koul 3000e3e6546SKrzysztof Kozlowski cpu0_opp_table: opp-table-cpu0 { 3012b6187abSThara Gopinath compatible = "operating-points-v2"; 3022b6187abSThara Gopinath opp-shared; 3032b6187abSThara Gopinath 3042b6187abSThara Gopinath cpu0_opp1: opp-300000000 { 3052b6187abSThara Gopinath opp-hz = /bits/ 64 <300000000>; 3062b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 3072b6187abSThara Gopinath }; 3082b6187abSThara Gopinath 3092b6187abSThara Gopinath cpu0_opp2: opp-403200000 { 3102b6187abSThara Gopinath opp-hz = /bits/ 64 <403200000>; 3112b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 3122b6187abSThara Gopinath }; 3132b6187abSThara Gopinath 3142b6187abSThara Gopinath cpu0_opp3: opp-499200000 { 3152b6187abSThara Gopinath opp-hz = /bits/ 64 <499200000>; 3162b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3172b6187abSThara Gopinath }; 3182b6187abSThara Gopinath 3192b6187abSThara Gopinath cpu0_opp4: opp-576000000 { 3202b6187abSThara Gopinath opp-hz = /bits/ 64 <576000000>; 3212b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3222b6187abSThara Gopinath }; 3232b6187abSThara Gopinath 3242b6187abSThara Gopinath cpu0_opp5: opp-672000000 { 3252b6187abSThara Gopinath opp-hz = /bits/ 64 <672000000>; 3262b6187abSThara Gopinath opp-peak-kBps = <800000 15974400>; 3272b6187abSThara Gopinath }; 3282b6187abSThara Gopinath 3292b6187abSThara Gopinath cpu0_opp6: opp-768000000 { 330ce3b50cfSThara Gopinath opp-hz = /bits/ 64 <768000000>; 3312b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3322b6187abSThara Gopinath }; 3332b6187abSThara Gopinath 3342b6187abSThara Gopinath cpu0_opp7: opp-844800000 { 3352b6187abSThara Gopinath opp-hz = /bits/ 64 <844800000>; 3362b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3372b6187abSThara Gopinath }; 3382b6187abSThara Gopinath 3392b6187abSThara Gopinath cpu0_opp8: opp-940800000 { 3402b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 3412b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3422b6187abSThara Gopinath }; 3432b6187abSThara Gopinath 3442b6187abSThara Gopinath cpu0_opp9: opp-1036800000 { 3452b6187abSThara Gopinath opp-hz = /bits/ 64 <1036800000>; 3462b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3472b6187abSThara Gopinath }; 3482b6187abSThara Gopinath 3492b6187abSThara Gopinath cpu0_opp10: opp-1113600000 { 3502b6187abSThara Gopinath opp-hz = /bits/ 64 <1113600000>; 3512b6187abSThara Gopinath opp-peak-kBps = <2188000 25804800>; 3522b6187abSThara Gopinath }; 3532b6187abSThara Gopinath 3542b6187abSThara Gopinath cpu0_opp11: opp-1209600000 { 3552b6187abSThara Gopinath opp-hz = /bits/ 64 <1209600000>; 3562b6187abSThara Gopinath opp-peak-kBps = <2188000 31948800>; 3572b6187abSThara Gopinath }; 3582b6187abSThara Gopinath 3592b6187abSThara Gopinath cpu0_opp12: opp-1305600000 { 3602b6187abSThara Gopinath opp-hz = /bits/ 64 <1305600000>; 3612b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3622b6187abSThara Gopinath }; 3632b6187abSThara Gopinath 3642b6187abSThara Gopinath cpu0_opp13: opp-1382400000 { 3652b6187abSThara Gopinath opp-hz = /bits/ 64 <1382400000>; 3662b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3672b6187abSThara Gopinath }; 3682b6187abSThara Gopinath 3692b6187abSThara Gopinath cpu0_opp14: opp-1478400000 { 3702b6187abSThara Gopinath opp-hz = /bits/ 64 <1478400000>; 3712b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3722b6187abSThara Gopinath }; 3732b6187abSThara Gopinath 3742b6187abSThara Gopinath cpu0_opp15: opp-1555200000 { 3752b6187abSThara Gopinath opp-hz = /bits/ 64 <1555200000>; 3762b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3772b6187abSThara Gopinath }; 3782b6187abSThara Gopinath 3792b6187abSThara Gopinath cpu0_opp16: opp-1632000000 { 3802b6187abSThara Gopinath opp-hz = /bits/ 64 <1632000000>; 3812b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3822b6187abSThara Gopinath }; 3832b6187abSThara Gopinath 3842b6187abSThara Gopinath cpu0_opp17: opp-1708800000 { 3852b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 3862b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 3872b6187abSThara Gopinath }; 3882b6187abSThara Gopinath 3892b6187abSThara Gopinath cpu0_opp18: opp-1785600000 { 3902b6187abSThara Gopinath opp-hz = /bits/ 64 <1785600000>; 3912b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 3922b6187abSThara Gopinath }; 3932b6187abSThara Gopinath }; 3942b6187abSThara Gopinath 3950e3e6546SKrzysztof Kozlowski cpu4_opp_table: opp-table-cpu4 { 3962b6187abSThara Gopinath compatible = "operating-points-v2"; 3972b6187abSThara Gopinath opp-shared; 3982b6187abSThara Gopinath 3992b6187abSThara Gopinath cpu4_opp1: opp-710400000 { 4002b6187abSThara Gopinath opp-hz = /bits/ 64 <710400000>; 4012b6187abSThara Gopinath opp-peak-kBps = <1804000 15974400>; 4022b6187abSThara Gopinath }; 4032b6187abSThara Gopinath 4042b6187abSThara Gopinath cpu4_opp2: opp-825600000 { 4052b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 4062b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 4072b6187abSThara Gopinath }; 4082b6187abSThara Gopinath 4092b6187abSThara Gopinath cpu4_opp3: opp-940800000 { 4102b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 4112b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 4122b6187abSThara Gopinath }; 4132b6187abSThara Gopinath 4142b6187abSThara Gopinath cpu4_opp4: opp-1056000000 { 4152b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 4162b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 4172b6187abSThara Gopinath }; 4182b6187abSThara Gopinath 4192b6187abSThara Gopinath cpu4_opp5: opp-1171200000 { 4202b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 4212b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 4222b6187abSThara Gopinath }; 4232b6187abSThara Gopinath 4242b6187abSThara Gopinath cpu4_opp6: opp-1286400000 { 4252b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 4262b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4272b6187abSThara Gopinath }; 4282b6187abSThara Gopinath 4292b6187abSThara Gopinath cpu4_opp7: opp-1401600000 { 4302b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 4312b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4322b6187abSThara Gopinath }; 4332b6187abSThara Gopinath 4342b6187abSThara Gopinath cpu4_opp8: opp-1497600000 { 4352b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 4362b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4372b6187abSThara Gopinath }; 4382b6187abSThara Gopinath 4392b6187abSThara Gopinath cpu4_opp9: opp-1612800000 { 4402b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 4412b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4422b6187abSThara Gopinath }; 4432b6187abSThara Gopinath 4442b6187abSThara Gopinath cpu4_opp10: opp-1708800000 { 4452b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 4462b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 4472b6187abSThara Gopinath }; 4482b6187abSThara Gopinath 4492b6187abSThara Gopinath cpu4_opp11: opp-1804800000 { 4502b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 4512b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 4522b6187abSThara Gopinath }; 4532b6187abSThara Gopinath 4542b6187abSThara Gopinath cpu4_opp12: opp-1920000000 { 4552b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 4562b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 4572b6187abSThara Gopinath }; 4582b6187abSThara Gopinath 4592b6187abSThara Gopinath cpu4_opp13: opp-2016000000 { 4602b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 4612b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 4622b6187abSThara Gopinath }; 4632b6187abSThara Gopinath 4642b6187abSThara Gopinath cpu4_opp14: opp-2131200000 { 4652b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 4662b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 4672b6187abSThara Gopinath }; 4682b6187abSThara Gopinath 4692b6187abSThara Gopinath cpu4_opp15: opp-2227200000 { 4702b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 4712b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4722b6187abSThara Gopinath }; 4732b6187abSThara Gopinath 4742b6187abSThara Gopinath cpu4_opp16: opp-2323200000 { 4752b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 4762b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4772b6187abSThara Gopinath }; 4782b6187abSThara Gopinath 4792b6187abSThara Gopinath cpu4_opp17: opp-2419200000 { 4802b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 4812b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4822b6187abSThara Gopinath }; 4832b6187abSThara Gopinath }; 4842b6187abSThara Gopinath 4850e3e6546SKrzysztof Kozlowski cpu7_opp_table: opp-table-cpu7 { 4862b6187abSThara Gopinath compatible = "operating-points-v2"; 4872b6187abSThara Gopinath opp-shared; 4882b6187abSThara Gopinath 4892b6187abSThara Gopinath cpu7_opp1: opp-825600000 { 4902b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 4912b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 4922b6187abSThara Gopinath }; 4932b6187abSThara Gopinath 4942b6187abSThara Gopinath cpu7_opp2: opp-940800000 { 4952b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 4962b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 4972b6187abSThara Gopinath }; 4982b6187abSThara Gopinath 4992b6187abSThara Gopinath cpu7_opp3: opp-1056000000 { 5002b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 5012b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 5022b6187abSThara Gopinath }; 5032b6187abSThara Gopinath 5042b6187abSThara Gopinath cpu7_opp4: opp-1171200000 { 5052b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 5062b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 5072b6187abSThara Gopinath }; 5082b6187abSThara Gopinath 5092b6187abSThara Gopinath cpu7_opp5: opp-1286400000 { 5102b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 5112b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5122b6187abSThara Gopinath }; 5132b6187abSThara Gopinath 5142b6187abSThara Gopinath cpu7_opp6: opp-1401600000 { 5152b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 5162b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5172b6187abSThara Gopinath }; 5182b6187abSThara Gopinath 5192b6187abSThara Gopinath cpu7_opp7: opp-1497600000 { 5202b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 5212b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5222b6187abSThara Gopinath }; 5232b6187abSThara Gopinath 5242b6187abSThara Gopinath cpu7_opp8: opp-1612800000 { 5252b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 5262b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5272b6187abSThara Gopinath }; 5282b6187abSThara Gopinath 5292b6187abSThara Gopinath cpu7_opp9: opp-1708800000 { 5302b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 5312b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 5322b6187abSThara Gopinath }; 5332b6187abSThara Gopinath 5342b6187abSThara Gopinath cpu7_opp10: opp-1804800000 { 5352b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 5362b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 5372b6187abSThara Gopinath }; 5382b6187abSThara Gopinath 5392b6187abSThara Gopinath cpu7_opp11: opp-1920000000 { 5402b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 5412b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 5422b6187abSThara Gopinath }; 5432b6187abSThara Gopinath 5442b6187abSThara Gopinath cpu7_opp12: opp-2016000000 { 5452b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 5462b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 5472b6187abSThara Gopinath }; 5482b6187abSThara Gopinath 5492b6187abSThara Gopinath cpu7_opp13: opp-2131200000 { 5502b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 5512b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 5522b6187abSThara Gopinath }; 5532b6187abSThara Gopinath 5542b6187abSThara Gopinath cpu7_opp14: opp-2227200000 { 5552b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 5562b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5572b6187abSThara Gopinath }; 5582b6187abSThara Gopinath 5592b6187abSThara Gopinath cpu7_opp15: opp-2323200000 { 5602b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 5612b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5622b6187abSThara Gopinath }; 5632b6187abSThara Gopinath 5642b6187abSThara Gopinath cpu7_opp16: opp-2419200000 { 5652b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 5662b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5672b6187abSThara Gopinath }; 5682b6187abSThara Gopinath 5692b6187abSThara Gopinath cpu7_opp17: opp-2534400000 { 5702b6187abSThara Gopinath opp-hz = /bits/ 64 <2534400000>; 5712b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5722b6187abSThara Gopinath }; 5732b6187abSThara Gopinath 5742b6187abSThara Gopinath cpu7_opp18: opp-2649600000 { 5752b6187abSThara Gopinath opp-hz = /bits/ 64 <2649600000>; 5762b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5772b6187abSThara Gopinath }; 5782b6187abSThara Gopinath 5792b6187abSThara Gopinath cpu7_opp19: opp-2745600000 { 5802b6187abSThara Gopinath opp-hz = /bits/ 64 <2745600000>; 5812b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5822b6187abSThara Gopinath }; 5832b6187abSThara Gopinath 5842b6187abSThara Gopinath cpu7_opp20: opp-2841600000 { 5852b6187abSThara Gopinath opp-hz = /bits/ 64 <2841600000>; 5862b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5872b6187abSThara Gopinath }; 5882b6187abSThara Gopinath }; 5892b6187abSThara Gopinath 590e13c6d14SVinod Koul firmware { 591e13c6d14SVinod Koul scm: scm { 592e13c6d14SVinod Koul compatible = "qcom,scm-sm8150", "qcom,scm"; 593e13c6d14SVinod Koul #reset-cells = <1>; 594e13c6d14SVinod Koul }; 595e13c6d14SVinod Koul }; 596e13c6d14SVinod Koul 597e13c6d14SVinod Koul memory@80000000 { 598e13c6d14SVinod Koul device_type = "memory"; 599e13c6d14SVinod Koul /* We expect the bootloader to fill in the size */ 600e13c6d14SVinod Koul reg = <0x0 0x80000000 0x0 0x0>; 601e13c6d14SVinod Koul }; 602e13c6d14SVinod Koul 603d8cf9372SVinod Koul pmu { 604d8cf9372SVinod Koul compatible = "arm,armv8-pmuv3"; 605d8cf9372SVinod Koul interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 606d8cf9372SVinod Koul }; 607d8cf9372SVinod Koul 608e13c6d14SVinod Koul psci { 609e13c6d14SVinod Koul compatible = "arm,psci-1.0"; 610e13c6d14SVinod Koul method = "smc"; 611b2e3f897SDanny Lin 612b2e3f897SDanny Lin CPU_PD0: cpu0 { 613b2e3f897SDanny Lin #power-domain-cells = <0>; 614b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 615b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 616b2e3f897SDanny Lin }; 617b2e3f897SDanny Lin 618b2e3f897SDanny Lin CPU_PD1: cpu1 { 619b2e3f897SDanny Lin #power-domain-cells = <0>; 620b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 621b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 622b2e3f897SDanny Lin }; 623b2e3f897SDanny Lin 624b2e3f897SDanny Lin CPU_PD2: cpu2 { 625b2e3f897SDanny Lin #power-domain-cells = <0>; 626b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 627b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 628b2e3f897SDanny Lin }; 629b2e3f897SDanny Lin 630b2e3f897SDanny Lin CPU_PD3: cpu3 { 631b2e3f897SDanny Lin #power-domain-cells = <0>; 632b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 633b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 634b2e3f897SDanny Lin }; 635b2e3f897SDanny Lin 636b2e3f897SDanny Lin CPU_PD4: cpu4 { 637b2e3f897SDanny Lin #power-domain-cells = <0>; 638b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 639b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 640b2e3f897SDanny Lin }; 641b2e3f897SDanny Lin 642b2e3f897SDanny Lin CPU_PD5: cpu5 { 643b2e3f897SDanny Lin #power-domain-cells = <0>; 644b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 645b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 646b2e3f897SDanny Lin }; 647b2e3f897SDanny Lin 648b2e3f897SDanny Lin CPU_PD6: cpu6 { 649b2e3f897SDanny Lin #power-domain-cells = <0>; 650b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 651b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 652b2e3f897SDanny Lin }; 653b2e3f897SDanny Lin 654b2e3f897SDanny Lin CPU_PD7: cpu7 { 655b2e3f897SDanny Lin #power-domain-cells = <0>; 656b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 657b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 658b2e3f897SDanny Lin }; 659b2e3f897SDanny Lin 660b2e3f897SDanny Lin CLUSTER_PD: cpu-cluster0 { 661b2e3f897SDanny Lin #power-domain-cells = <0>; 662b2e3f897SDanny Lin domain-idle-states = <&CLUSTER_SLEEP_0>; 663b2e3f897SDanny Lin }; 664e13c6d14SVinod Koul }; 665e13c6d14SVinod Koul 666912c373aSVinod Koul reserved-memory { 667912c373aSVinod Koul #address-cells = <2>; 668912c373aSVinod Koul #size-cells = <2>; 669912c373aSVinod Koul ranges; 670912c373aSVinod Koul 671912c373aSVinod Koul hyp_mem: memory@85700000 { 672912c373aSVinod Koul reg = <0x0 0x85700000 0x0 0x600000>; 673912c373aSVinod Koul no-map; 674912c373aSVinod Koul }; 675912c373aSVinod Koul 676912c373aSVinod Koul xbl_mem: memory@85d00000 { 677912c373aSVinod Koul reg = <0x0 0x85d00000 0x0 0x140000>; 678912c373aSVinod Koul no-map; 679912c373aSVinod Koul }; 680912c373aSVinod Koul 681912c373aSVinod Koul aop_mem: memory@85f00000 { 682912c373aSVinod Koul reg = <0x0 0x85f00000 0x0 0x20000>; 683912c373aSVinod Koul no-map; 684912c373aSVinod Koul }; 685912c373aSVinod Koul 686912c373aSVinod Koul aop_cmd_db: memory@85f20000 { 687912c373aSVinod Koul compatible = "qcom,cmd-db"; 688912c373aSVinod Koul reg = <0x0 0x85f20000 0x0 0x20000>; 689912c373aSVinod Koul no-map; 690912c373aSVinod Koul }; 691912c373aSVinod Koul 692912c373aSVinod Koul smem_mem: memory@86000000 { 693912c373aSVinod Koul reg = <0x0 0x86000000 0x0 0x200000>; 694912c373aSVinod Koul no-map; 695912c373aSVinod Koul }; 696912c373aSVinod Koul 697912c373aSVinod Koul tz_mem: memory@86200000 { 698912c373aSVinod Koul reg = <0x0 0x86200000 0x0 0x3900000>; 699912c373aSVinod Koul no-map; 700912c373aSVinod Koul }; 701912c373aSVinod Koul 702912c373aSVinod Koul rmtfs_mem: memory@89b00000 { 703912c373aSVinod Koul compatible = "qcom,rmtfs-mem"; 704912c373aSVinod Koul reg = <0x0 0x89b00000 0x0 0x200000>; 705912c373aSVinod Koul no-map; 706912c373aSVinod Koul 707912c373aSVinod Koul qcom,client-id = <1>; 708912c373aSVinod Koul qcom,vmid = <15>; 709912c373aSVinod Koul }; 710912c373aSVinod Koul 711912c373aSVinod Koul camera_mem: memory@8b700000 { 712912c373aSVinod Koul reg = <0x0 0x8b700000 0x0 0x500000>; 713912c373aSVinod Koul no-map; 714912c373aSVinod Koul }; 715912c373aSVinod Koul 716912c373aSVinod Koul wlan_mem: memory@8bc00000 { 717912c373aSVinod Koul reg = <0x0 0x8bc00000 0x0 0x180000>; 718912c373aSVinod Koul no-map; 719912c373aSVinod Koul }; 720912c373aSVinod Koul 721912c373aSVinod Koul npu_mem: memory@8bd80000 { 722912c373aSVinod Koul reg = <0x0 0x8bd80000 0x0 0x80000>; 723912c373aSVinod Koul no-map; 724912c373aSVinod Koul }; 725912c373aSVinod Koul 726912c373aSVinod Koul adsp_mem: memory@8be00000 { 727912c373aSVinod Koul reg = <0x0 0x8be00000 0x0 0x1a00000>; 728912c373aSVinod Koul no-map; 729912c373aSVinod Koul }; 730912c373aSVinod Koul 731912c373aSVinod Koul mpss_mem: memory@8d800000 { 732912c373aSVinod Koul reg = <0x0 0x8d800000 0x0 0x9600000>; 733912c373aSVinod Koul no-map; 734912c373aSVinod Koul }; 735912c373aSVinod Koul 736912c373aSVinod Koul venus_mem: memory@96e00000 { 737912c373aSVinod Koul reg = <0x0 0x96e00000 0x0 0x500000>; 738912c373aSVinod Koul no-map; 739912c373aSVinod Koul }; 740912c373aSVinod Koul 741912c373aSVinod Koul slpi_mem: memory@97300000 { 742912c373aSVinod Koul reg = <0x0 0x97300000 0x0 0x1400000>; 743912c373aSVinod Koul no-map; 744912c373aSVinod Koul }; 745912c373aSVinod Koul 746912c373aSVinod Koul ipa_fw_mem: memory@98700000 { 747912c373aSVinod Koul reg = <0x0 0x98700000 0x0 0x10000>; 748912c373aSVinod Koul no-map; 749912c373aSVinod Koul }; 750912c373aSVinod Koul 751912c373aSVinod Koul ipa_gsi_mem: memory@98710000 { 752912c373aSVinod Koul reg = <0x0 0x98710000 0x0 0x5000>; 753912c373aSVinod Koul no-map; 754912c373aSVinod Koul }; 755912c373aSVinod Koul 756912c373aSVinod Koul gpu_mem: memory@98715000 { 757912c373aSVinod Koul reg = <0x0 0x98715000 0x0 0x2000>; 758912c373aSVinod Koul no-map; 759912c373aSVinod Koul }; 760912c373aSVinod Koul 761912c373aSVinod Koul spss_mem: memory@98800000 { 762912c373aSVinod Koul reg = <0x0 0x98800000 0x0 0x100000>; 763912c373aSVinod Koul no-map; 764912c373aSVinod Koul }; 765912c373aSVinod Koul 766912c373aSVinod Koul cdsp_mem: memory@98900000 { 767912c373aSVinod Koul reg = <0x0 0x98900000 0x0 0x1400000>; 768912c373aSVinod Koul no-map; 769912c373aSVinod Koul }; 770912c373aSVinod Koul 771912c373aSVinod Koul qseecom_mem: memory@9e400000 { 772912c373aSVinod Koul reg = <0x0 0x9e400000 0x0 0x1400000>; 773912c373aSVinod Koul no-map; 774912c373aSVinod Koul }; 775912c373aSVinod Koul }; 776912c373aSVinod Koul 777d8cf9372SVinod Koul smem { 778d8cf9372SVinod Koul compatible = "qcom,smem"; 779d8cf9372SVinod Koul memory-region = <&smem_mem>; 780d8cf9372SVinod Koul hwlocks = <&tcsr_mutex 3>; 781d8cf9372SVinod Koul }; 782d8cf9372SVinod Koul 78361025b81SSibi Sankar smp2p-cdsp { 78461025b81SSibi Sankar compatible = "qcom,smp2p"; 78561025b81SSibi Sankar qcom,smem = <94>, <432>; 78661025b81SSibi Sankar 78761025b81SSibi Sankar interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 78861025b81SSibi Sankar 78961025b81SSibi Sankar mboxes = <&apss_shared 6>; 79061025b81SSibi Sankar 79161025b81SSibi Sankar qcom,local-pid = <0>; 79261025b81SSibi Sankar qcom,remote-pid = <5>; 79361025b81SSibi Sankar 79461025b81SSibi Sankar cdsp_smp2p_out: master-kernel { 79561025b81SSibi Sankar qcom,entry-name = "master-kernel"; 79661025b81SSibi Sankar #qcom,smem-state-cells = <1>; 79761025b81SSibi Sankar }; 79861025b81SSibi Sankar 79961025b81SSibi Sankar cdsp_smp2p_in: slave-kernel { 80061025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 80161025b81SSibi Sankar 80261025b81SSibi Sankar interrupt-controller; 80361025b81SSibi Sankar #interrupt-cells = <2>; 80461025b81SSibi Sankar }; 80561025b81SSibi Sankar }; 80661025b81SSibi Sankar 80761025b81SSibi Sankar smp2p-lpass { 80861025b81SSibi Sankar compatible = "qcom,smp2p"; 80961025b81SSibi Sankar qcom,smem = <443>, <429>; 81061025b81SSibi Sankar 81161025b81SSibi Sankar interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 81261025b81SSibi Sankar 81361025b81SSibi Sankar mboxes = <&apss_shared 10>; 81461025b81SSibi Sankar 81561025b81SSibi Sankar qcom,local-pid = <0>; 81661025b81SSibi Sankar qcom,remote-pid = <2>; 81761025b81SSibi Sankar 81861025b81SSibi Sankar adsp_smp2p_out: master-kernel { 81961025b81SSibi Sankar qcom,entry-name = "master-kernel"; 82061025b81SSibi Sankar #qcom,smem-state-cells = <1>; 82161025b81SSibi Sankar }; 82261025b81SSibi Sankar 82361025b81SSibi Sankar adsp_smp2p_in: slave-kernel { 82461025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 82561025b81SSibi Sankar 82661025b81SSibi Sankar interrupt-controller; 82761025b81SSibi Sankar #interrupt-cells = <2>; 82861025b81SSibi Sankar }; 82961025b81SSibi Sankar }; 83061025b81SSibi Sankar 83161025b81SSibi Sankar smp2p-mpss { 83261025b81SSibi Sankar compatible = "qcom,smp2p"; 83361025b81SSibi Sankar qcom,smem = <435>, <428>; 83461025b81SSibi Sankar 83561025b81SSibi Sankar interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 83661025b81SSibi Sankar 83761025b81SSibi Sankar mboxes = <&apss_shared 14>; 83861025b81SSibi Sankar 83961025b81SSibi Sankar qcom,local-pid = <0>; 84061025b81SSibi Sankar qcom,remote-pid = <1>; 84161025b81SSibi Sankar 84261025b81SSibi Sankar modem_smp2p_out: master-kernel { 84361025b81SSibi Sankar qcom,entry-name = "master-kernel"; 84461025b81SSibi Sankar #qcom,smem-state-cells = <1>; 84561025b81SSibi Sankar }; 84661025b81SSibi Sankar 84761025b81SSibi Sankar modem_smp2p_in: slave-kernel { 84861025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 84961025b81SSibi Sankar 85061025b81SSibi Sankar interrupt-controller; 85161025b81SSibi Sankar #interrupt-cells = <2>; 85261025b81SSibi Sankar }; 85361025b81SSibi Sankar }; 85461025b81SSibi Sankar 85561025b81SSibi Sankar smp2p-slpi { 85661025b81SSibi Sankar compatible = "qcom,smp2p"; 85761025b81SSibi Sankar qcom,smem = <481>, <430>; 85861025b81SSibi Sankar 85961025b81SSibi Sankar interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 86061025b81SSibi Sankar 86161025b81SSibi Sankar mboxes = <&apss_shared 26>; 86261025b81SSibi Sankar 86361025b81SSibi Sankar qcom,local-pid = <0>; 86461025b81SSibi Sankar qcom,remote-pid = <3>; 86561025b81SSibi Sankar 86661025b81SSibi Sankar slpi_smp2p_out: master-kernel { 86761025b81SSibi Sankar qcom,entry-name = "master-kernel"; 86861025b81SSibi Sankar #qcom,smem-state-cells = <1>; 86961025b81SSibi Sankar }; 87061025b81SSibi Sankar 87161025b81SSibi Sankar slpi_smp2p_in: slave-kernel { 87261025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 87361025b81SSibi Sankar 87461025b81SSibi Sankar interrupt-controller; 87561025b81SSibi Sankar #interrupt-cells = <2>; 87661025b81SSibi Sankar }; 87761025b81SSibi Sankar }; 87861025b81SSibi Sankar 879e13c6d14SVinod Koul soc: soc@0 { 880e13c6d14SVinod Koul #address-cells = <2>; 881e13c6d14SVinod Koul #size-cells = <2>; 882e13c6d14SVinod Koul ranges = <0 0 0 0 0x10 0>; 883e13c6d14SVinod Koul dma-ranges = <0 0 0 0 0x10 0>; 884e13c6d14SVinod Koul compatible = "simple-bus"; 885e13c6d14SVinod Koul 886e13c6d14SVinod Koul gcc: clock-controller@100000 { 887e13c6d14SVinod Koul compatible = "qcom,gcc-sm8150"; 888e13c6d14SVinod Koul reg = <0x0 0x00100000 0x0 0x1f0000>; 889e13c6d14SVinod Koul #clock-cells = <1>; 890e13c6d14SVinod Koul #reset-cells = <1>; 891e13c6d14SVinod Koul #power-domain-cells = <1>; 892e13c6d14SVinod Koul clock-names = "bi_tcxo", 893e13c6d14SVinod Koul "sleep_clk"; 894e13c6d14SVinod Koul clocks = <&rpmhcc RPMH_CXO_CLK>, 895e13c6d14SVinod Koul <&sleep_clk>; 896e13c6d14SVinod Koul }; 897e13c6d14SVinod Koul 89805006290SFelipe Balbi gpi_dma0: dma-controller@800000 { 899e7e24786SRichard Acayan compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 90005006290SFelipe Balbi reg = <0 0x800000 0 0x60000>; 90105006290SFelipe Balbi interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 90205006290SFelipe Balbi <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 90305006290SFelipe Balbi <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 90405006290SFelipe Balbi <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 90505006290SFelipe Balbi <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 90605006290SFelipe Balbi <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 90705006290SFelipe Balbi <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 90805006290SFelipe Balbi <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 90905006290SFelipe Balbi <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 91005006290SFelipe Balbi <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 91105006290SFelipe Balbi <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 91205006290SFelipe Balbi <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 91305006290SFelipe Balbi <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 91405006290SFelipe Balbi dma-channels = <13>; 91505006290SFelipe Balbi dma-channel-mask = <0xfa>; 91605006290SFelipe Balbi iommus = <&apps_smmu 0x00d6 0x0>; 91705006290SFelipe Balbi #dma-cells = <3>; 91805006290SFelipe Balbi status = "disabled"; 91905006290SFelipe Balbi }; 92005006290SFelipe Balbi 92105f333b7SVinod Koul ethernet: ethernet@20000 { 92205f333b7SVinod Koul compatible = "qcom,sm8150-ethqos"; 92305f333b7SVinod Koul reg = <0x0 0x00020000 0x0 0x10000>, 92405f333b7SVinod Koul <0x0 0x00036000 0x0 0x100>; 92505f333b7SVinod Koul reg-names = "stmmaceth", "rgmii"; 92605f333b7SVinod Koul clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 92705f333b7SVinod Koul clocks = <&gcc GCC_EMAC_AXI_CLK>, 92805f333b7SVinod Koul <&gcc GCC_EMAC_SLV_AHB_CLK>, 92905f333b7SVinod Koul <&gcc GCC_EMAC_PTP_CLK>, 93005f333b7SVinod Koul <&gcc GCC_EMAC_RGMII_CLK>; 93105f333b7SVinod Koul interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 93205f333b7SVinod Koul <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 93305f333b7SVinod Koul interrupt-names = "macirq", "eth_lpi"; 93405f333b7SVinod Koul 93505f333b7SVinod Koul power-domains = <&gcc EMAC_GDSC>; 93605f333b7SVinod Koul resets = <&gcc GCC_EMAC_BCR>; 93705f333b7SVinod Koul 93851f748c6SKonrad Dybcio iommus = <&apps_smmu 0x3c0 0x0>; 93905f333b7SVinod Koul 94005f333b7SVinod Koul snps,tso; 94105f333b7SVinod Koul rx-fifo-depth = <4096>; 94205f333b7SVinod Koul tx-fifo-depth = <4096>; 94305f333b7SVinod Koul 94405f333b7SVinod Koul status = "disabled"; 94505f333b7SVinod Koul }; 94605f333b7SVinod Koul 94705f333b7SVinod Koul 9489cf3ebd1SCaleb Connolly qupv3_id_0: geniqup@8c0000 { 9499cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 9509cf3ebd1SCaleb Connolly reg = <0x0 0x008c0000 0x0 0x6000>; 9519cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 9529cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 9539cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 9549cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0xc3 0x0>; 9559cf3ebd1SCaleb Connolly #address-cells = <2>; 9569cf3ebd1SCaleb Connolly #size-cells = <2>; 9579cf3ebd1SCaleb Connolly ranges; 9589cf3ebd1SCaleb Connolly status = "disabled"; 95981bee695SCaleb Connolly 96081bee695SCaleb Connolly i2c0: i2c@880000 { 96181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 96281bee695SCaleb Connolly reg = <0 0x00880000 0 0x4000>; 96381bee695SCaleb Connolly clock-names = "se"; 96481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 965abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 966abdd4b7aSFelipe Balbi <&gpi_dma0 1 0 QCOM_GPI_I2C>; 967abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 96881bee695SCaleb Connolly pinctrl-names = "default"; 96981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c0_default>; 97081bee695SCaleb Connolly interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 97181bee695SCaleb Connolly #address-cells = <1>; 97281bee695SCaleb Connolly #size-cells = <0>; 97381bee695SCaleb Connolly status = "disabled"; 97481bee695SCaleb Connolly }; 97581bee695SCaleb Connolly 976129e1c96SFelipe Balbi spi0: spi@880000 { 977129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 978129e1c96SFelipe Balbi reg = <0 0x880000 0 0x4000>; 979129e1c96SFelipe Balbi reg-names = "se"; 980129e1c96SFelipe Balbi clock-names = "se"; 981129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 982abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 983abdd4b7aSFelipe Balbi <&gpi_dma0 1 0 QCOM_GPI_SPI>; 984abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 985129e1c96SFelipe Balbi pinctrl-names = "default"; 986129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi0_default>; 987129e1c96SFelipe Balbi interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 988129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 989129e1c96SFelipe Balbi #address-cells = <1>; 990129e1c96SFelipe Balbi #size-cells = <0>; 991129e1c96SFelipe Balbi status = "disabled"; 992129e1c96SFelipe Balbi }; 993129e1c96SFelipe Balbi 99481bee695SCaleb Connolly i2c1: i2c@884000 { 99581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 99681bee695SCaleb Connolly reg = <0 0x00884000 0 0x4000>; 99781bee695SCaleb Connolly clock-names = "se"; 99881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 999abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1000abdd4b7aSFelipe Balbi <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1001abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 100281bee695SCaleb Connolly pinctrl-names = "default"; 100381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c1_default>; 100481bee695SCaleb Connolly interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 100581bee695SCaleb Connolly #address-cells = <1>; 100681bee695SCaleb Connolly #size-cells = <0>; 100781bee695SCaleb Connolly status = "disabled"; 100881bee695SCaleb Connolly }; 100981bee695SCaleb Connolly 1010129e1c96SFelipe Balbi spi1: spi@884000 { 1011129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1012129e1c96SFelipe Balbi reg = <0 0x884000 0 0x4000>; 1013129e1c96SFelipe Balbi reg-names = "se"; 1014129e1c96SFelipe Balbi clock-names = "se"; 1015129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1016abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1017abdd4b7aSFelipe Balbi <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1018abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1019129e1c96SFelipe Balbi pinctrl-names = "default"; 1020129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi1_default>; 1021129e1c96SFelipe Balbi interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1022129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1023129e1c96SFelipe Balbi #address-cells = <1>; 1024129e1c96SFelipe Balbi #size-cells = <0>; 1025129e1c96SFelipe Balbi status = "disabled"; 1026129e1c96SFelipe Balbi }; 1027129e1c96SFelipe Balbi 102881bee695SCaleb Connolly i2c2: i2c@888000 { 102981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 103081bee695SCaleb Connolly reg = <0 0x00888000 0 0x4000>; 103181bee695SCaleb Connolly clock-names = "se"; 103281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1033abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1034abdd4b7aSFelipe Balbi <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1035abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 103681bee695SCaleb Connolly pinctrl-names = "default"; 103781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c2_default>; 103881bee695SCaleb Connolly interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 103981bee695SCaleb Connolly #address-cells = <1>; 104081bee695SCaleb Connolly #size-cells = <0>; 104181bee695SCaleb Connolly status = "disabled"; 104281bee695SCaleb Connolly }; 104381bee695SCaleb Connolly 1044129e1c96SFelipe Balbi spi2: spi@888000 { 1045129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1046129e1c96SFelipe Balbi reg = <0 0x888000 0 0x4000>; 1047129e1c96SFelipe Balbi reg-names = "se"; 1048129e1c96SFelipe Balbi clock-names = "se"; 1049129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1050abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1051abdd4b7aSFelipe Balbi <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1052abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1053129e1c96SFelipe Balbi pinctrl-names = "default"; 1054129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi2_default>; 1055129e1c96SFelipe Balbi interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1056129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1057129e1c96SFelipe Balbi #address-cells = <1>; 1058129e1c96SFelipe Balbi #size-cells = <0>; 1059129e1c96SFelipe Balbi status = "disabled"; 1060129e1c96SFelipe Balbi }; 1061129e1c96SFelipe Balbi 106281bee695SCaleb Connolly i2c3: i2c@88c000 { 106381bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 106481bee695SCaleb Connolly reg = <0 0x0088c000 0 0x4000>; 106581bee695SCaleb Connolly clock-names = "se"; 106681bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1067abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1068abdd4b7aSFelipe Balbi <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1069abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 107081bee695SCaleb Connolly pinctrl-names = "default"; 107181bee695SCaleb Connolly pinctrl-0 = <&qup_i2c3_default>; 107281bee695SCaleb Connolly interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 107381bee695SCaleb Connolly #address-cells = <1>; 107481bee695SCaleb Connolly #size-cells = <0>; 107581bee695SCaleb Connolly status = "disabled"; 107681bee695SCaleb Connolly }; 107781bee695SCaleb Connolly 1078129e1c96SFelipe Balbi spi3: spi@88c000 { 1079129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1080129e1c96SFelipe Balbi reg = <0 0x88c000 0 0x4000>; 1081129e1c96SFelipe Balbi reg-names = "se"; 1082129e1c96SFelipe Balbi clock-names = "se"; 1083129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1084abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1085abdd4b7aSFelipe Balbi <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1086abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1087129e1c96SFelipe Balbi pinctrl-names = "default"; 1088129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi3_default>; 1089129e1c96SFelipe Balbi interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1090129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1091129e1c96SFelipe Balbi #address-cells = <1>; 1092129e1c96SFelipe Balbi #size-cells = <0>; 1093129e1c96SFelipe Balbi status = "disabled"; 1094129e1c96SFelipe Balbi }; 1095129e1c96SFelipe Balbi 109681bee695SCaleb Connolly i2c4: i2c@890000 { 109781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 109881bee695SCaleb Connolly reg = <0 0x00890000 0 0x4000>; 109981bee695SCaleb Connolly clock-names = "se"; 110081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1101abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1102abdd4b7aSFelipe Balbi <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1103abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 110481bee695SCaleb Connolly pinctrl-names = "default"; 110581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c4_default>; 110681bee695SCaleb Connolly interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 110781bee695SCaleb Connolly #address-cells = <1>; 110881bee695SCaleb Connolly #size-cells = <0>; 110981bee695SCaleb Connolly status = "disabled"; 111081bee695SCaleb Connolly }; 111181bee695SCaleb Connolly 1112129e1c96SFelipe Balbi spi4: spi@890000 { 1113129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1114129e1c96SFelipe Balbi reg = <0 0x890000 0 0x4000>; 1115129e1c96SFelipe Balbi reg-names = "se"; 1116129e1c96SFelipe Balbi clock-names = "se"; 1117129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1118abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1119abdd4b7aSFelipe Balbi <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1120abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1121129e1c96SFelipe Balbi pinctrl-names = "default"; 1122129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi4_default>; 1123129e1c96SFelipe Balbi interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1124129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1125129e1c96SFelipe Balbi #address-cells = <1>; 1126129e1c96SFelipe Balbi #size-cells = <0>; 1127129e1c96SFelipe Balbi status = "disabled"; 1128129e1c96SFelipe Balbi }; 1129129e1c96SFelipe Balbi 113081bee695SCaleb Connolly i2c5: i2c@894000 { 113181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 113281bee695SCaleb Connolly reg = <0 0x00894000 0 0x4000>; 113381bee695SCaleb Connolly clock-names = "se"; 113481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1135abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1136abdd4b7aSFelipe Balbi <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1137abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 113881bee695SCaleb Connolly pinctrl-names = "default"; 113981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c5_default>; 114081bee695SCaleb Connolly interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 114181bee695SCaleb Connolly #address-cells = <1>; 114281bee695SCaleb Connolly #size-cells = <0>; 114381bee695SCaleb Connolly status = "disabled"; 114481bee695SCaleb Connolly }; 114581bee695SCaleb Connolly 1146129e1c96SFelipe Balbi spi5: spi@894000 { 1147129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1148129e1c96SFelipe Balbi reg = <0 0x894000 0 0x4000>; 1149129e1c96SFelipe Balbi reg-names = "se"; 1150129e1c96SFelipe Balbi clock-names = "se"; 1151129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1152abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1153abdd4b7aSFelipe Balbi <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1154abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1155129e1c96SFelipe Balbi pinctrl-names = "default"; 1156129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi5_default>; 1157129e1c96SFelipe Balbi interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1158129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1159129e1c96SFelipe Balbi #address-cells = <1>; 1160129e1c96SFelipe Balbi #size-cells = <0>; 1161129e1c96SFelipe Balbi status = "disabled"; 1162129e1c96SFelipe Balbi }; 1163129e1c96SFelipe Balbi 116481bee695SCaleb Connolly i2c6: i2c@898000 { 116581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 116681bee695SCaleb Connolly reg = <0 0x00898000 0 0x4000>; 116781bee695SCaleb Connolly clock-names = "se"; 116881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1169abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1170abdd4b7aSFelipe Balbi <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1171abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 117281bee695SCaleb Connolly pinctrl-names = "default"; 117381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c6_default>; 117481bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 117581bee695SCaleb Connolly #address-cells = <1>; 117681bee695SCaleb Connolly #size-cells = <0>; 117781bee695SCaleb Connolly status = "disabled"; 117881bee695SCaleb Connolly }; 117981bee695SCaleb Connolly 1180129e1c96SFelipe Balbi spi6: spi@898000 { 1181129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1182129e1c96SFelipe Balbi reg = <0 0x898000 0 0x4000>; 1183129e1c96SFelipe Balbi reg-names = "se"; 1184129e1c96SFelipe Balbi clock-names = "se"; 1185129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1186abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1187abdd4b7aSFelipe Balbi <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1188abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1189129e1c96SFelipe Balbi pinctrl-names = "default"; 1190129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi6_default>; 1191129e1c96SFelipe Balbi interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1192129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1193129e1c96SFelipe Balbi #address-cells = <1>; 1194129e1c96SFelipe Balbi #size-cells = <0>; 1195129e1c96SFelipe Balbi status = "disabled"; 1196129e1c96SFelipe Balbi }; 1197129e1c96SFelipe Balbi 119881bee695SCaleb Connolly i2c7: i2c@89c000 { 119981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 120081bee695SCaleb Connolly reg = <0 0x0089c000 0 0x4000>; 120181bee695SCaleb Connolly clock-names = "se"; 120281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1203abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1204abdd4b7aSFelipe Balbi <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1205abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 120681bee695SCaleb Connolly pinctrl-names = "default"; 120781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c7_default>; 120881bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 120981bee695SCaleb Connolly #address-cells = <1>; 121081bee695SCaleb Connolly #size-cells = <0>; 121181bee695SCaleb Connolly status = "disabled"; 121281bee695SCaleb Connolly }; 121381bee695SCaleb Connolly 1214129e1c96SFelipe Balbi spi7: spi@89c000 { 1215129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1216129e1c96SFelipe Balbi reg = <0 0x89c000 0 0x4000>; 1217129e1c96SFelipe Balbi reg-names = "se"; 1218129e1c96SFelipe Balbi clock-names = "se"; 1219129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1220abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1221abdd4b7aSFelipe Balbi <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1222abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1223129e1c96SFelipe Balbi pinctrl-names = "default"; 1224129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi7_default>; 1225129e1c96SFelipe Balbi interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1226129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1227129e1c96SFelipe Balbi #address-cells = <1>; 1228129e1c96SFelipe Balbi #size-cells = <0>; 1229129e1c96SFelipe Balbi status = "disabled"; 1230129e1c96SFelipe Balbi }; 12319cf3ebd1SCaleb Connolly }; 12329cf3ebd1SCaleb Connolly 123305006290SFelipe Balbi gpi_dma1: dma-controller@a00000 { 1234e7e24786SRichard Acayan compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 123505006290SFelipe Balbi reg = <0 0xa00000 0 0x60000>; 123605006290SFelipe Balbi interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 123705006290SFelipe Balbi <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 123805006290SFelipe Balbi <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 123905006290SFelipe Balbi <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 124005006290SFelipe Balbi <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 124105006290SFelipe Balbi <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 124205006290SFelipe Balbi <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 124305006290SFelipe Balbi <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 124405006290SFelipe Balbi <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 124505006290SFelipe Balbi <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 124605006290SFelipe Balbi <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 124705006290SFelipe Balbi <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 124805006290SFelipe Balbi <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 124905006290SFelipe Balbi dma-channels = <13>; 125005006290SFelipe Balbi dma-channel-mask = <0xfa>; 125105006290SFelipe Balbi iommus = <&apps_smmu 0x0616 0x0>; 125205006290SFelipe Balbi #dma-cells = <3>; 125305006290SFelipe Balbi status = "disabled"; 125405006290SFelipe Balbi }; 125505006290SFelipe Balbi 1256e13c6d14SVinod Koul qupv3_id_1: geniqup@ac0000 { 1257e13c6d14SVinod Koul compatible = "qcom,geni-se-qup"; 1258e13c6d14SVinod Koul reg = <0x0 0x00ac0000 0x0 0x6000>; 1259e13c6d14SVinod Koul clock-names = "m-ahb", "s-ahb"; 1260d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1261d6f55763SVinod Koul <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 12629cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x603 0x0>; 1263e13c6d14SVinod Koul #address-cells = <2>; 1264e13c6d14SVinod Koul #size-cells = <2>; 1265e13c6d14SVinod Koul ranges; 1266e13c6d14SVinod Koul status = "disabled"; 1267e13c6d14SVinod Koul 126881bee695SCaleb Connolly i2c8: i2c@a80000 { 126981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 127081bee695SCaleb Connolly reg = <0 0x00a80000 0 0x4000>; 127181bee695SCaleb Connolly clock-names = "se"; 127281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1273abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1274abdd4b7aSFelipe Balbi <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1275abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 127681bee695SCaleb Connolly pinctrl-names = "default"; 127781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c8_default>; 127881bee695SCaleb Connolly interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 127981bee695SCaleb Connolly #address-cells = <1>; 128081bee695SCaleb Connolly #size-cells = <0>; 128181bee695SCaleb Connolly status = "disabled"; 128281bee695SCaleb Connolly }; 128381bee695SCaleb Connolly 1284129e1c96SFelipe Balbi spi8: spi@a80000 { 1285129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1286129e1c96SFelipe Balbi reg = <0 0xa80000 0 0x4000>; 1287129e1c96SFelipe Balbi reg-names = "se"; 1288129e1c96SFelipe Balbi clock-names = "se"; 1289129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1290abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1291abdd4b7aSFelipe Balbi <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1292abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1293129e1c96SFelipe Balbi pinctrl-names = "default"; 1294129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi8_default>; 1295129e1c96SFelipe Balbi interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1296129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1297129e1c96SFelipe Balbi #address-cells = <1>; 1298129e1c96SFelipe Balbi #size-cells = <0>; 1299129e1c96SFelipe Balbi status = "disabled"; 1300129e1c96SFelipe Balbi }; 1301129e1c96SFelipe Balbi 130281bee695SCaleb Connolly i2c9: i2c@a84000 { 130381bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 130481bee695SCaleb Connolly reg = <0 0x00a84000 0 0x4000>; 130581bee695SCaleb Connolly clock-names = "se"; 130681bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1307abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1308abdd4b7aSFelipe Balbi <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1309abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 131081bee695SCaleb Connolly pinctrl-names = "default"; 131181bee695SCaleb Connolly pinctrl-0 = <&qup_i2c9_default>; 131281bee695SCaleb Connolly interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 131381bee695SCaleb Connolly #address-cells = <1>; 131481bee695SCaleb Connolly #size-cells = <0>; 131581bee695SCaleb Connolly status = "disabled"; 131681bee695SCaleb Connolly }; 131781bee695SCaleb Connolly 1318129e1c96SFelipe Balbi spi9: spi@a84000 { 1319129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1320129e1c96SFelipe Balbi reg = <0 0xa84000 0 0x4000>; 1321129e1c96SFelipe Balbi reg-names = "se"; 1322129e1c96SFelipe Balbi clock-names = "se"; 1323129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1324abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1325abdd4b7aSFelipe Balbi <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1326abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1327129e1c96SFelipe Balbi pinctrl-names = "default"; 1328129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi9_default>; 1329129e1c96SFelipe Balbi interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1330129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1331129e1c96SFelipe Balbi #address-cells = <1>; 1332129e1c96SFelipe Balbi #size-cells = <0>; 1333129e1c96SFelipe Balbi status = "disabled"; 1334129e1c96SFelipe Balbi }; 1335129e1c96SFelipe Balbi 133681bee695SCaleb Connolly i2c10: i2c@a88000 { 133781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 133881bee695SCaleb Connolly reg = <0 0x00a88000 0 0x4000>; 133981bee695SCaleb Connolly clock-names = "se"; 134081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1341abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1342abdd4b7aSFelipe Balbi <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1343abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 134481bee695SCaleb Connolly pinctrl-names = "default"; 134581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c10_default>; 134681bee695SCaleb Connolly interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 134781bee695SCaleb Connolly #address-cells = <1>; 134881bee695SCaleb Connolly #size-cells = <0>; 134981bee695SCaleb Connolly status = "disabled"; 135081bee695SCaleb Connolly }; 135181bee695SCaleb Connolly 1352129e1c96SFelipe Balbi spi10: spi@a88000 { 1353129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1354129e1c96SFelipe Balbi reg = <0 0xa88000 0 0x4000>; 1355129e1c96SFelipe Balbi reg-names = "se"; 1356129e1c96SFelipe Balbi clock-names = "se"; 1357129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1358abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1359abdd4b7aSFelipe Balbi <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1360abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1361129e1c96SFelipe Balbi pinctrl-names = "default"; 1362129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi10_default>; 1363129e1c96SFelipe Balbi interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1364129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1365129e1c96SFelipe Balbi #address-cells = <1>; 1366129e1c96SFelipe Balbi #size-cells = <0>; 1367129e1c96SFelipe Balbi status = "disabled"; 1368129e1c96SFelipe Balbi }; 1369129e1c96SFelipe Balbi 137081bee695SCaleb Connolly i2c11: i2c@a8c000 { 137181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 137281bee695SCaleb Connolly reg = <0 0x00a8c000 0 0x4000>; 137381bee695SCaleb Connolly clock-names = "se"; 137481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1375abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1376abdd4b7aSFelipe Balbi <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1377abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 137881bee695SCaleb Connolly pinctrl-names = "default"; 137981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c11_default>; 138081bee695SCaleb Connolly interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 138181bee695SCaleb Connolly #address-cells = <1>; 138281bee695SCaleb Connolly #size-cells = <0>; 138381bee695SCaleb Connolly status = "disabled"; 138481bee695SCaleb Connolly }; 138581bee695SCaleb Connolly 1386129e1c96SFelipe Balbi spi11: spi@a8c000 { 1387129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1388129e1c96SFelipe Balbi reg = <0 0xa8c000 0 0x4000>; 1389129e1c96SFelipe Balbi reg-names = "se"; 1390129e1c96SFelipe Balbi clock-names = "se"; 1391129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1392abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1393abdd4b7aSFelipe Balbi <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1394abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1395129e1c96SFelipe Balbi pinctrl-names = "default"; 1396129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi11_default>; 1397129e1c96SFelipe Balbi interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1398129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1399129e1c96SFelipe Balbi #address-cells = <1>; 1400129e1c96SFelipe Balbi #size-cells = <0>; 1401129e1c96SFelipe Balbi status = "disabled"; 1402129e1c96SFelipe Balbi }; 1403129e1c96SFelipe Balbi 1404e13c6d14SVinod Koul uart2: serial@a90000 { 1405e13c6d14SVinod Koul compatible = "qcom,geni-debug-uart"; 1406e13c6d14SVinod Koul reg = <0x0 0x00a90000 0x0 0x4000>; 1407e13c6d14SVinod Koul clock-names = "se"; 1408d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1409e13c6d14SVinod Koul interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1410e13c6d14SVinod Koul status = "disabled"; 1411e13c6d14SVinod Koul }; 141281bee695SCaleb Connolly 141381bee695SCaleb Connolly i2c12: i2c@a90000 { 141481bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 141581bee695SCaleb Connolly reg = <0 0x00a90000 0 0x4000>; 141681bee695SCaleb Connolly clock-names = "se"; 141781bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1418abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1419abdd4b7aSFelipe Balbi <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1420abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 142181bee695SCaleb Connolly pinctrl-names = "default"; 142281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c12_default>; 142381bee695SCaleb Connolly interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 142481bee695SCaleb Connolly #address-cells = <1>; 142581bee695SCaleb Connolly #size-cells = <0>; 142681bee695SCaleb Connolly status = "disabled"; 142781bee695SCaleb Connolly }; 142881bee695SCaleb Connolly 1429129e1c96SFelipe Balbi spi12: spi@a90000 { 1430129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1431129e1c96SFelipe Balbi reg = <0 0xa90000 0 0x4000>; 1432129e1c96SFelipe Balbi reg-names = "se"; 1433129e1c96SFelipe Balbi clock-names = "se"; 1434129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1435abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1436abdd4b7aSFelipe Balbi <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1437abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1438129e1c96SFelipe Balbi pinctrl-names = "default"; 1439129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi12_default>; 1440129e1c96SFelipe Balbi interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1441129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1442129e1c96SFelipe Balbi #address-cells = <1>; 1443129e1c96SFelipe Balbi #size-cells = <0>; 1444129e1c96SFelipe Balbi status = "disabled"; 1445129e1c96SFelipe Balbi }; 1446129e1c96SFelipe Balbi 144781bee695SCaleb Connolly i2c16: i2c@94000 { 144881bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 144981bee695SCaleb Connolly reg = <0 0x0094000 0 0x4000>; 145081bee695SCaleb Connolly clock-names = "se"; 145181bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1452abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1453abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1454abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 145581bee695SCaleb Connolly pinctrl-names = "default"; 145681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c16_default>; 145781bee695SCaleb Connolly interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 145881bee695SCaleb Connolly #address-cells = <1>; 145981bee695SCaleb Connolly #size-cells = <0>; 146081bee695SCaleb Connolly status = "disabled"; 146181bee695SCaleb Connolly }; 1462129e1c96SFelipe Balbi 1463129e1c96SFelipe Balbi spi16: spi@a94000 { 1464129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1465129e1c96SFelipe Balbi reg = <0 0xa94000 0 0x4000>; 1466129e1c96SFelipe Balbi reg-names = "se"; 1467129e1c96SFelipe Balbi clock-names = "se"; 1468129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1469abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1470abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1471abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1472129e1c96SFelipe Balbi pinctrl-names = "default"; 1473129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi16_default>; 1474129e1c96SFelipe Balbi interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1475129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1476129e1c96SFelipe Balbi #address-cells = <1>; 1477129e1c96SFelipe Balbi #size-cells = <0>; 1478129e1c96SFelipe Balbi status = "disabled"; 1479129e1c96SFelipe Balbi }; 1480e13c6d14SVinod Koul }; 1481e13c6d14SVinod Koul 148205006290SFelipe Balbi gpi_dma2: dma-controller@c00000 { 1483e7e24786SRichard Acayan compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 148405006290SFelipe Balbi reg = <0 0xc00000 0 0x60000>; 148505006290SFelipe Balbi interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 148605006290SFelipe Balbi <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 148705006290SFelipe Balbi <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 148805006290SFelipe Balbi <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 148905006290SFelipe Balbi <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 149005006290SFelipe Balbi <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 149105006290SFelipe Balbi <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 149205006290SFelipe Balbi <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 149305006290SFelipe Balbi <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 149405006290SFelipe Balbi <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 149505006290SFelipe Balbi <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 149605006290SFelipe Balbi <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 149705006290SFelipe Balbi <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 149805006290SFelipe Balbi dma-channels = <13>; 149905006290SFelipe Balbi dma-channel-mask = <0xfa>; 150005006290SFelipe Balbi iommus = <&apps_smmu 0x07b6 0x0>; 150105006290SFelipe Balbi #dma-cells = <3>; 150205006290SFelipe Balbi status = "disabled"; 150305006290SFelipe Balbi }; 150405006290SFelipe Balbi 15059cf3ebd1SCaleb Connolly qupv3_id_2: geniqup@cc0000 { 15069cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 15079cf3ebd1SCaleb Connolly reg = <0x0 0x00cc0000 0x0 0x6000>; 15089cf3ebd1SCaleb Connolly 15099cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 15109cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 15119cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 15129cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x7a3 0x0>; 15139cf3ebd1SCaleb Connolly #address-cells = <2>; 15149cf3ebd1SCaleb Connolly #size-cells = <2>; 15159cf3ebd1SCaleb Connolly ranges; 15169cf3ebd1SCaleb Connolly status = "disabled"; 151781bee695SCaleb Connolly 151881bee695SCaleb Connolly i2c17: i2c@c80000 { 151981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 152081bee695SCaleb Connolly reg = <0 0x00c80000 0 0x4000>; 152181bee695SCaleb Connolly clock-names = "se"; 152281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1523abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1524abdd4b7aSFelipe Balbi <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1525abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 152681bee695SCaleb Connolly pinctrl-names = "default"; 152781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c17_default>; 152881bee695SCaleb Connolly interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 152981bee695SCaleb Connolly #address-cells = <1>; 153081bee695SCaleb Connolly #size-cells = <0>; 153181bee695SCaleb Connolly status = "disabled"; 153281bee695SCaleb Connolly }; 153381bee695SCaleb Connolly 1534129e1c96SFelipe Balbi spi17: spi@c80000 { 1535129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1536129e1c96SFelipe Balbi reg = <0 0xc80000 0 0x4000>; 1537129e1c96SFelipe Balbi reg-names = "se"; 1538129e1c96SFelipe Balbi clock-names = "se"; 1539129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1540abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1541abdd4b7aSFelipe Balbi <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1542abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1543129e1c96SFelipe Balbi pinctrl-names = "default"; 1544129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi17_default>; 1545129e1c96SFelipe Balbi interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1546129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1547129e1c96SFelipe Balbi #address-cells = <1>; 1548129e1c96SFelipe Balbi #size-cells = <0>; 1549129e1c96SFelipe Balbi status = "disabled"; 1550129e1c96SFelipe Balbi }; 1551129e1c96SFelipe Balbi 155281bee695SCaleb Connolly i2c18: i2c@c84000 { 155381bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 155481bee695SCaleb Connolly reg = <0 0x00c84000 0 0x4000>; 155581bee695SCaleb Connolly clock-names = "se"; 155681bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1557abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1558abdd4b7aSFelipe Balbi <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1559abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 156081bee695SCaleb Connolly pinctrl-names = "default"; 156181bee695SCaleb Connolly pinctrl-0 = <&qup_i2c18_default>; 156281bee695SCaleb Connolly interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 156381bee695SCaleb Connolly #address-cells = <1>; 156481bee695SCaleb Connolly #size-cells = <0>; 156581bee695SCaleb Connolly status = "disabled"; 156681bee695SCaleb Connolly }; 156781bee695SCaleb Connolly 1568129e1c96SFelipe Balbi spi18: spi@c84000 { 1569129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1570129e1c96SFelipe Balbi reg = <0 0xc84000 0 0x4000>; 1571129e1c96SFelipe Balbi reg-names = "se"; 1572129e1c96SFelipe Balbi clock-names = "se"; 1573129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1574abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1575abdd4b7aSFelipe Balbi <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1576abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1577129e1c96SFelipe Balbi pinctrl-names = "default"; 1578129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi18_default>; 1579129e1c96SFelipe Balbi interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1580129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1581129e1c96SFelipe Balbi #address-cells = <1>; 1582129e1c96SFelipe Balbi #size-cells = <0>; 1583129e1c96SFelipe Balbi status = "disabled"; 1584129e1c96SFelipe Balbi }; 1585129e1c96SFelipe Balbi 158681bee695SCaleb Connolly i2c19: i2c@c88000 { 158781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 158881bee695SCaleb Connolly reg = <0 0x00c88000 0 0x4000>; 158981bee695SCaleb Connolly clock-names = "se"; 159081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1591abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1592abdd4b7aSFelipe Balbi <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1593abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 159481bee695SCaleb Connolly pinctrl-names = "default"; 159581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c19_default>; 159681bee695SCaleb Connolly interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 159781bee695SCaleb Connolly #address-cells = <1>; 159881bee695SCaleb Connolly #size-cells = <0>; 159981bee695SCaleb Connolly status = "disabled"; 160081bee695SCaleb Connolly }; 160181bee695SCaleb Connolly 1602129e1c96SFelipe Balbi spi19: spi@c88000 { 1603129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1604129e1c96SFelipe Balbi reg = <0 0xc88000 0 0x4000>; 1605129e1c96SFelipe Balbi reg-names = "se"; 1606129e1c96SFelipe Balbi clock-names = "se"; 1607129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1608abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1609abdd4b7aSFelipe Balbi <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1610abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1611129e1c96SFelipe Balbi pinctrl-names = "default"; 1612129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi19_default>; 1613129e1c96SFelipe Balbi interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1614129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1615129e1c96SFelipe Balbi #address-cells = <1>; 1616129e1c96SFelipe Balbi #size-cells = <0>; 1617129e1c96SFelipe Balbi status = "disabled"; 1618129e1c96SFelipe Balbi }; 1619129e1c96SFelipe Balbi 162081bee695SCaleb Connolly i2c13: i2c@c8c000 { 162181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 162281bee695SCaleb Connolly reg = <0 0x00c8c000 0 0x4000>; 162381bee695SCaleb Connolly clock-names = "se"; 162481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1625abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1626abdd4b7aSFelipe Balbi <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1627abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 162881bee695SCaleb Connolly pinctrl-names = "default"; 162981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c13_default>; 163081bee695SCaleb Connolly interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 163181bee695SCaleb Connolly #address-cells = <1>; 163281bee695SCaleb Connolly #size-cells = <0>; 163381bee695SCaleb Connolly status = "disabled"; 163481bee695SCaleb Connolly }; 163581bee695SCaleb Connolly 1636129e1c96SFelipe Balbi spi13: spi@c8c000 { 1637129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1638129e1c96SFelipe Balbi reg = <0 0xc8c000 0 0x4000>; 1639129e1c96SFelipe Balbi reg-names = "se"; 1640129e1c96SFelipe Balbi clock-names = "se"; 1641129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1642abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1643abdd4b7aSFelipe Balbi <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1644abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1645129e1c96SFelipe Balbi pinctrl-names = "default"; 1646129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi13_default>; 1647129e1c96SFelipe Balbi interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1648129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1649129e1c96SFelipe Balbi #address-cells = <1>; 1650129e1c96SFelipe Balbi #size-cells = <0>; 1651129e1c96SFelipe Balbi status = "disabled"; 1652129e1c96SFelipe Balbi }; 1653129e1c96SFelipe Balbi 165481bee695SCaleb Connolly i2c14: i2c@c90000 { 165581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 165681bee695SCaleb Connolly reg = <0 0x00c90000 0 0x4000>; 165781bee695SCaleb Connolly clock-names = "se"; 165881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1659abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1660abdd4b7aSFelipe Balbi <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1661abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 166281bee695SCaleb Connolly pinctrl-names = "default"; 166381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c14_default>; 166481bee695SCaleb Connolly interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 166581bee695SCaleb Connolly #address-cells = <1>; 166681bee695SCaleb Connolly #size-cells = <0>; 166781bee695SCaleb Connolly status = "disabled"; 166881bee695SCaleb Connolly }; 166981bee695SCaleb Connolly 1670129e1c96SFelipe Balbi spi14: spi@c90000 { 1671129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1672129e1c96SFelipe Balbi reg = <0 0xc90000 0 0x4000>; 1673129e1c96SFelipe Balbi reg-names = "se"; 1674129e1c96SFelipe Balbi clock-names = "se"; 1675129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1676abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1677abdd4b7aSFelipe Balbi <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1678abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1679129e1c96SFelipe Balbi pinctrl-names = "default"; 1680129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi14_default>; 1681129e1c96SFelipe Balbi interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1682129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1683129e1c96SFelipe Balbi #address-cells = <1>; 1684129e1c96SFelipe Balbi #size-cells = <0>; 1685129e1c96SFelipe Balbi status = "disabled"; 1686129e1c96SFelipe Balbi }; 1687129e1c96SFelipe Balbi 168881bee695SCaleb Connolly i2c15: i2c@c94000 { 168981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 169081bee695SCaleb Connolly reg = <0 0x00c94000 0 0x4000>; 169181bee695SCaleb Connolly clock-names = "se"; 169281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1693abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1694abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1695abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 169681bee695SCaleb Connolly pinctrl-names = "default"; 169781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c15_default>; 169881bee695SCaleb Connolly interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 169981bee695SCaleb Connolly #address-cells = <1>; 170081bee695SCaleb Connolly #size-cells = <0>; 170181bee695SCaleb Connolly status = "disabled"; 170281bee695SCaleb Connolly }; 1703129e1c96SFelipe Balbi 1704129e1c96SFelipe Balbi spi15: spi@c94000 { 1705129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1706129e1c96SFelipe Balbi reg = <0 0xc94000 0 0x4000>; 1707129e1c96SFelipe Balbi reg-names = "se"; 1708129e1c96SFelipe Balbi clock-names = "se"; 1709129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1710abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1711abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1712abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1713129e1c96SFelipe Balbi pinctrl-names = "default"; 1714129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi15_default>; 1715129e1c96SFelipe Balbi interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1716129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1717129e1c96SFelipe Balbi #address-cells = <1>; 1718129e1c96SFelipe Balbi #size-cells = <0>; 1719129e1c96SFelipe Balbi status = "disabled"; 1720129e1c96SFelipe Balbi }; 17219cf3ebd1SCaleb Connolly }; 17229cf3ebd1SCaleb Connolly 172371a2fc6eSJonathan Marek config_noc: interconnect@1500000 { 172471a2fc6eSJonathan Marek compatible = "qcom,sm8150-config-noc"; 172571a2fc6eSJonathan Marek reg = <0 0x01500000 0 0x7400>; 172671a2fc6eSJonathan Marek #interconnect-cells = <1>; 172771a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 172871a2fc6eSJonathan Marek }; 172971a2fc6eSJonathan Marek 173071a2fc6eSJonathan Marek system_noc: interconnect@1620000 { 173171a2fc6eSJonathan Marek compatible = "qcom,sm8150-system-noc"; 173271a2fc6eSJonathan Marek reg = <0 0x01620000 0 0x19400>; 173371a2fc6eSJonathan Marek #interconnect-cells = <1>; 173471a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 173571a2fc6eSJonathan Marek }; 173671a2fc6eSJonathan Marek 173771a2fc6eSJonathan Marek mc_virt: interconnect@163a000 { 173871a2fc6eSJonathan Marek compatible = "qcom,sm8150-mc-virt"; 173971a2fc6eSJonathan Marek reg = <0 0x0163a000 0 0x1000>; 174071a2fc6eSJonathan Marek #interconnect-cells = <1>; 174171a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 174271a2fc6eSJonathan Marek }; 174371a2fc6eSJonathan Marek 174471a2fc6eSJonathan Marek aggre1_noc: interconnect@16e0000 { 174571a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre1-noc"; 174671a2fc6eSJonathan Marek reg = <0 0x016e0000 0 0xd080>; 174771a2fc6eSJonathan Marek #interconnect-cells = <1>; 174871a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 174971a2fc6eSJonathan Marek }; 175071a2fc6eSJonathan Marek 175171a2fc6eSJonathan Marek aggre2_noc: interconnect@1700000 { 175271a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre2-noc"; 175371a2fc6eSJonathan Marek reg = <0 0x01700000 0 0x20000>; 175471a2fc6eSJonathan Marek #interconnect-cells = <1>; 175571a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 175671a2fc6eSJonathan Marek }; 175771a2fc6eSJonathan Marek 175871a2fc6eSJonathan Marek compute_noc: interconnect@1720000 { 175971a2fc6eSJonathan Marek compatible = "qcom,sm8150-compute-noc"; 176071a2fc6eSJonathan Marek reg = <0 0x01720000 0 0x7000>; 176171a2fc6eSJonathan Marek #interconnect-cells = <1>; 176271a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 176371a2fc6eSJonathan Marek }; 176471a2fc6eSJonathan Marek 176571a2fc6eSJonathan Marek mmss_noc: interconnect@1740000 { 176671a2fc6eSJonathan Marek compatible = "qcom,sm8150-mmss-noc"; 176771a2fc6eSJonathan Marek reg = <0 0x01740000 0 0x1c100>; 176871a2fc6eSJonathan Marek #interconnect-cells = <1>; 176971a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 177071a2fc6eSJonathan Marek }; 177171a2fc6eSJonathan Marek 1772bb1f7cf6SSouradeep Chowdhury system-cache-controller@9200000 { 1773bb1f7cf6SSouradeep Chowdhury compatible = "qcom,sm8150-llcc"; 1774bb1f7cf6SSouradeep Chowdhury reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 1775bb1f7cf6SSouradeep Chowdhury reg-names = "llcc_base", "llcc_broadcast_base"; 1776bb1f7cf6SSouradeep Chowdhury interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1777bb1f7cf6SSouradeep Chowdhury }; 1778bb1f7cf6SSouradeep Chowdhury 1779d4b94c82SSouradeep Chowdhury dma@10a2000 { 1780d4b94c82SSouradeep Chowdhury compatible = "qcom,sm8150-dcc", "qcom,dcc"; 1781d4b94c82SSouradeep Chowdhury reg = <0x0 0x010a2000 0x0 0x1000>, 1782d4b94c82SSouradeep Chowdhury <0x0 0x010ad000 0x0 0x3000>; 1783d4b94c82SSouradeep Chowdhury }; 1784d4b94c82SSouradeep Chowdhury 1785a1c86c68SBhupesh Sharma pcie0: pci@1c00000 { 1786a1c86c68SBhupesh Sharma compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1787a1c86c68SBhupesh Sharma reg = <0 0x01c00000 0 0x3000>, 1788a1c86c68SBhupesh Sharma <0 0x60000000 0 0xf1d>, 1789a1c86c68SBhupesh Sharma <0 0x60000f20 0 0xa8>, 1790a1c86c68SBhupesh Sharma <0 0x60001000 0 0x1000>, 1791a1c86c68SBhupesh Sharma <0 0x60100000 0 0x100000>; 1792a1c86c68SBhupesh Sharma reg-names = "parf", "dbi", "elbi", "atu", "config"; 1793a1c86c68SBhupesh Sharma device_type = "pci"; 1794a1c86c68SBhupesh Sharma linux,pci-domain = <0>; 1795a1c86c68SBhupesh Sharma bus-range = <0x00 0xff>; 1796a1c86c68SBhupesh Sharma num-lanes = <1>; 1797a1c86c68SBhupesh Sharma 1798a1c86c68SBhupesh Sharma #address-cells = <3>; 1799a1c86c68SBhupesh Sharma #size-cells = <2>; 1800a1c86c68SBhupesh Sharma 1801a1c86c68SBhupesh Sharma ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1802a1c86c68SBhupesh Sharma <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1803a1c86c68SBhupesh Sharma 1804a1c86c68SBhupesh Sharma interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1805a1c86c68SBhupesh Sharma interrupt-names = "msi"; 1806a1c86c68SBhupesh Sharma #interrupt-cells = <1>; 1807a1c86c68SBhupesh Sharma interrupt-map-mask = <0 0 0 0x7>; 1808a1c86c68SBhupesh Sharma interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1809a1c86c68SBhupesh Sharma <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1810a1c86c68SBhupesh Sharma <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1811a1c86c68SBhupesh Sharma <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1812a1c86c68SBhupesh Sharma 1813a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1814a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_AUX_CLK>, 1815a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1816a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1817a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1818a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1819a1c86c68SBhupesh Sharma <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1820a1c86c68SBhupesh Sharma clock-names = "pipe", 1821a1c86c68SBhupesh Sharma "aux", 1822a1c86c68SBhupesh Sharma "cfg", 1823a1c86c68SBhupesh Sharma "bus_master", 1824a1c86c68SBhupesh Sharma "bus_slave", 1825a1c86c68SBhupesh Sharma "slave_q2a", 1826a1c86c68SBhupesh Sharma "tbu"; 1827a1c86c68SBhupesh Sharma 1828a1c86c68SBhupesh Sharma iommus = <&apps_smmu 0x1d80 0x7f>; 1829a1c86c68SBhupesh Sharma iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1830a1c86c68SBhupesh Sharma <0x100 &apps_smmu 0x1d81 0x1>; 1831a1c86c68SBhupesh Sharma 1832a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_0_BCR>; 1833a1c86c68SBhupesh Sharma reset-names = "pci"; 1834a1c86c68SBhupesh Sharma 1835a1c86c68SBhupesh Sharma power-domains = <&gcc PCIE_0_GDSC>; 1836a1c86c68SBhupesh Sharma 1837a1c86c68SBhupesh Sharma phys = <&pcie0_lane>; 1838a1c86c68SBhupesh Sharma phy-names = "pciephy"; 1839a1c86c68SBhupesh Sharma 1840a1c86c68SBhupesh Sharma perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1841a1c86c68SBhupesh Sharma enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1842a1c86c68SBhupesh Sharma 1843a1c86c68SBhupesh Sharma pinctrl-names = "default"; 1844a1c86c68SBhupesh Sharma pinctrl-0 = <&pcie0_default_state>; 1845a1c86c68SBhupesh Sharma 1846a1c86c68SBhupesh Sharma status = "disabled"; 1847a1c86c68SBhupesh Sharma }; 1848a1c86c68SBhupesh Sharma 1849a1c86c68SBhupesh Sharma pcie0_phy: phy@1c06000 { 1850a1c86c68SBhupesh Sharma compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1851a1c86c68SBhupesh Sharma reg = <0 0x01c06000 0 0x1c0>; 1852a1c86c68SBhupesh Sharma #address-cells = <2>; 1853a1c86c68SBhupesh Sharma #size-cells = <2>; 1854a1c86c68SBhupesh Sharma ranges; 1855a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1856a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1857a1c86c68SBhupesh Sharma <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1858a1c86c68SBhupesh Sharma clock-names = "aux", "cfg_ahb", "refgen"; 1859a1c86c68SBhupesh Sharma 1860a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1861a1c86c68SBhupesh Sharma reset-names = "phy"; 1862a1c86c68SBhupesh Sharma 1863a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1864a1c86c68SBhupesh Sharma assigned-clock-rates = <100000000>; 1865a1c86c68SBhupesh Sharma 1866a1c86c68SBhupesh Sharma status = "disabled"; 1867a1c86c68SBhupesh Sharma 1868a1c86c68SBhupesh Sharma pcie0_lane: phy@1c06200 { 1869a1c86c68SBhupesh Sharma reg = <0 0x1c06200 0 0x170>, /* tx */ 1870a1c86c68SBhupesh Sharma <0 0x1c06400 0 0x200>, /* rx */ 1871a1c86c68SBhupesh Sharma <0 0x1c06800 0 0x1f0>, /* pcs */ 1872a1c86c68SBhupesh Sharma <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1873a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1874a1c86c68SBhupesh Sharma clock-names = "pipe0"; 1875a1c86c68SBhupesh Sharma 1876a1c86c68SBhupesh Sharma #phy-cells = <0>; 1877a1c86c68SBhupesh Sharma clock-output-names = "pcie_0_pipe_clk"; 1878a1c86c68SBhupesh Sharma }; 1879a1c86c68SBhupesh Sharma }; 1880a1c86c68SBhupesh Sharma 1881a1c86c68SBhupesh Sharma pcie1: pci@1c08000 { 1882a1c86c68SBhupesh Sharma compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1883a1c86c68SBhupesh Sharma reg = <0 0x01c08000 0 0x3000>, 1884a1c86c68SBhupesh Sharma <0 0x40000000 0 0xf1d>, 1885a1c86c68SBhupesh Sharma <0 0x40000f20 0 0xa8>, 1886a1c86c68SBhupesh Sharma <0 0x40001000 0 0x1000>, 1887a1c86c68SBhupesh Sharma <0 0x40100000 0 0x100000>; 1888a1c86c68SBhupesh Sharma reg-names = "parf", "dbi", "elbi", "atu", "config"; 1889a1c86c68SBhupesh Sharma device_type = "pci"; 1890a1c86c68SBhupesh Sharma linux,pci-domain = <1>; 1891a1c86c68SBhupesh Sharma bus-range = <0x00 0xff>; 1892a1c86c68SBhupesh Sharma num-lanes = <2>; 1893a1c86c68SBhupesh Sharma 1894a1c86c68SBhupesh Sharma #address-cells = <3>; 1895a1c86c68SBhupesh Sharma #size-cells = <2>; 1896a1c86c68SBhupesh Sharma 1897a1c86c68SBhupesh Sharma ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1898a1c86c68SBhupesh Sharma <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1899a1c86c68SBhupesh Sharma 1900a1c86c68SBhupesh Sharma interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1901a1c86c68SBhupesh Sharma interrupt-names = "msi"; 1902a1c86c68SBhupesh Sharma #interrupt-cells = <1>; 1903a1c86c68SBhupesh Sharma interrupt-map-mask = <0 0 0 0x7>; 1904a1c86c68SBhupesh Sharma interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1905a1c86c68SBhupesh Sharma <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1906a1c86c68SBhupesh Sharma <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1907a1c86c68SBhupesh Sharma <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1908a1c86c68SBhupesh Sharma 1909a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1910a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_AUX_CLK>, 1911a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1912a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1913a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1914a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1915a1c86c68SBhupesh Sharma <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1916a1c86c68SBhupesh Sharma clock-names = "pipe", 1917a1c86c68SBhupesh Sharma "aux", 1918a1c86c68SBhupesh Sharma "cfg", 1919a1c86c68SBhupesh Sharma "bus_master", 1920a1c86c68SBhupesh Sharma "bus_slave", 1921a1c86c68SBhupesh Sharma "slave_q2a", 1922a1c86c68SBhupesh Sharma "tbu"; 1923a1c86c68SBhupesh Sharma 1924a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1925a1c86c68SBhupesh Sharma assigned-clock-rates = <19200000>; 1926a1c86c68SBhupesh Sharma 1927a1c86c68SBhupesh Sharma iommus = <&apps_smmu 0x1e00 0x7f>; 1928a1c86c68SBhupesh Sharma iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1929a1c86c68SBhupesh Sharma <0x100 &apps_smmu 0x1e01 0x1>; 1930a1c86c68SBhupesh Sharma 1931a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_1_BCR>; 1932a1c86c68SBhupesh Sharma reset-names = "pci"; 1933a1c86c68SBhupesh Sharma 1934a1c86c68SBhupesh Sharma power-domains = <&gcc PCIE_1_GDSC>; 1935a1c86c68SBhupesh Sharma 1936a1c86c68SBhupesh Sharma phys = <&pcie1_lane>; 1937a1c86c68SBhupesh Sharma phy-names = "pciephy"; 1938a1c86c68SBhupesh Sharma 1939a1c86c68SBhupesh Sharma perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; 1940a1c86c68SBhupesh Sharma enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 1941a1c86c68SBhupesh Sharma 1942a1c86c68SBhupesh Sharma pinctrl-names = "default"; 1943a1c86c68SBhupesh Sharma pinctrl-0 = <&pcie1_default_state>; 1944a1c86c68SBhupesh Sharma 1945a1c86c68SBhupesh Sharma status = "disabled"; 1946a1c86c68SBhupesh Sharma }; 1947a1c86c68SBhupesh Sharma 1948a1c86c68SBhupesh Sharma pcie1_phy: phy@1c0e000 { 1949a1c86c68SBhupesh Sharma compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 1950a1c86c68SBhupesh Sharma reg = <0 0x01c0e000 0 0x1c0>; 1951a1c86c68SBhupesh Sharma #address-cells = <2>; 1952a1c86c68SBhupesh Sharma #size-cells = <2>; 1953a1c86c68SBhupesh Sharma ranges; 1954a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1955a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1956a1c86c68SBhupesh Sharma <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1957a1c86c68SBhupesh Sharma clock-names = "aux", "cfg_ahb", "refgen"; 1958a1c86c68SBhupesh Sharma 1959a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1960a1c86c68SBhupesh Sharma reset-names = "phy"; 1961a1c86c68SBhupesh Sharma 1962a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1963a1c86c68SBhupesh Sharma assigned-clock-rates = <100000000>; 1964a1c86c68SBhupesh Sharma 1965a1c86c68SBhupesh Sharma status = "disabled"; 1966a1c86c68SBhupesh Sharma 1967a1c86c68SBhupesh Sharma pcie1_lane: phy@1c0e200 { 1968a1c86c68SBhupesh Sharma reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1969a1c86c68SBhupesh Sharma <0 0x1c0e400 0 0x200>, /* rx0 */ 1970a1c86c68SBhupesh Sharma <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1971a1c86c68SBhupesh Sharma <0 0x1c0e600 0 0x170>, /* tx1 */ 1972a1c86c68SBhupesh Sharma <0 0x1c0e800 0 0x200>, /* rx1 */ 1973a1c86c68SBhupesh Sharma <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1974a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1975a1c86c68SBhupesh Sharma clock-names = "pipe0"; 1976a1c86c68SBhupesh Sharma 1977a1c86c68SBhupesh Sharma #phy-cells = <0>; 1978a1c86c68SBhupesh Sharma clock-output-names = "pcie_1_pipe_clk"; 1979a1c86c68SBhupesh Sharma }; 1980a1c86c68SBhupesh Sharma }; 1981a1c86c68SBhupesh Sharma 19823834a2e9SVinod Koul ufs_mem_hc: ufshc@1d84000 { 19833834a2e9SVinod Koul compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 19843834a2e9SVinod Koul "jedec,ufs-2.0"; 198598aee1e3SBhupesh Sharma reg = <0 0x01d84000 0 0x2500>, 198698aee1e3SBhupesh Sharma <0 0x01d90000 0 0x8000>; 198798aee1e3SBhupesh Sharma reg-names = "std", "ice"; 19883834a2e9SVinod Koul interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 19893834a2e9SVinod Koul phys = <&ufs_mem_phy_lanes>; 19903834a2e9SVinod Koul phy-names = "ufsphy"; 19913834a2e9SVinod Koul lanes-per-direction = <2>; 19923834a2e9SVinod Koul #reset-cells = <1>; 19933834a2e9SVinod Koul resets = <&gcc GCC_UFS_PHY_BCR>; 19943834a2e9SVinod Koul reset-names = "rst"; 19953834a2e9SVinod Koul 199648156232SJonathan Marek iommus = <&apps_smmu 0x300 0>; 199748156232SJonathan Marek 19983834a2e9SVinod Koul clock-names = 19993834a2e9SVinod Koul "core_clk", 20003834a2e9SVinod Koul "bus_aggr_clk", 20013834a2e9SVinod Koul "iface_clk", 20023834a2e9SVinod Koul "core_clk_unipro", 20033834a2e9SVinod Koul "ref_clk", 20043834a2e9SVinod Koul "tx_lane0_sync_clk", 20053834a2e9SVinod Koul "rx_lane0_sync_clk", 200698aee1e3SBhupesh Sharma "rx_lane1_sync_clk", 200798aee1e3SBhupesh Sharma "ice_core_clk"; 20083834a2e9SVinod Koul clocks = 20093834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AXI_CLK>, 20103834a2e9SVinod Koul <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 20113834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AHB_CLK>, 20123834a2e9SVinod Koul <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 20133834a2e9SVinod Koul <&rpmhcc RPMH_CXO_CLK>, 20143834a2e9SVinod Koul <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 20153834a2e9SVinod Koul <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 201698aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 201798aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 20183834a2e9SVinod Koul freq-table-hz = 20193834a2e9SVinod Koul <37500000 300000000>, 20203834a2e9SVinod Koul <0 0>, 20213834a2e9SVinod Koul <0 0>, 20223834a2e9SVinod Koul <37500000 300000000>, 20233834a2e9SVinod Koul <0 0>, 20243834a2e9SVinod Koul <0 0>, 20253834a2e9SVinod Koul <0 0>, 202698aee1e3SBhupesh Sharma <0 0>, 202798aee1e3SBhupesh Sharma <0 300000000>; 20283834a2e9SVinod Koul 20293834a2e9SVinod Koul status = "disabled"; 20303834a2e9SVinod Koul }; 20313834a2e9SVinod Koul 20323834a2e9SVinod Koul ufs_mem_phy: phy@1d87000 { 20333834a2e9SVinod Koul compatible = "qcom,sm8150-qmp-ufs-phy"; 2034c79ec891SVinod Koul reg = <0 0x01d87000 0 0x1c0>; 20353834a2e9SVinod Koul #address-cells = <2>; 20363834a2e9SVinod Koul #size-cells = <2>; 20373834a2e9SVinod Koul ranges; 20383834a2e9SVinod Koul clock-names = "ref", 20393834a2e9SVinod Koul "ref_aux"; 20403834a2e9SVinod Koul clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 20413834a2e9SVinod Koul <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 20423834a2e9SVinod Koul 2043fe75b0c4SBhupesh Sharma power-domains = <&gcc UFS_PHY_GDSC>; 2044fe75b0c4SBhupesh Sharma 20453834a2e9SVinod Koul resets = <&ufs_mem_hc 0>; 20463834a2e9SVinod Koul reset-names = "ufsphy"; 20473834a2e9SVinod Koul status = "disabled"; 20483834a2e9SVinod Koul 20491351512fSShawn Guo ufs_mem_phy_lanes: phy@1d87400 { 205036a31b3aSJohan Hovold reg = <0 0x01d87400 0 0x16c>, 205136a31b3aSJohan Hovold <0 0x01d87600 0 0x200>, 205236a31b3aSJohan Hovold <0 0x01d87c00 0 0x200>, 205336a31b3aSJohan Hovold <0 0x01d87800 0 0x16c>, 205436a31b3aSJohan Hovold <0 0x01d87a00 0 0x200>; 20553834a2e9SVinod Koul #phy-cells = <0>; 20563834a2e9SVinod Koul }; 20573834a2e9SVinod Koul }; 20583834a2e9SVinod Koul 205971a2fc6eSJonathan Marek ipa_virt: interconnect@1e00000 { 206071a2fc6eSJonathan Marek compatible = "qcom,sm8150-ipa-virt"; 206171a2fc6eSJonathan Marek reg = <0 0x01e00000 0 0x1000>; 206271a2fc6eSJonathan Marek #interconnect-cells = <1>; 206371a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 206471a2fc6eSJonathan Marek }; 206571a2fc6eSJonathan Marek 2066c752d491SKrzysztof Kozlowski tcsr_mutex: hwlock@1f40000 { 2067c752d491SKrzysztof Kozlowski compatible = "qcom,tcsr-mutex"; 206886d7c946SKrzysztof Kozlowski reg = <0x0 0x01f40000 0x0 0x20000>; 2069c752d491SKrzysztof Kozlowski #hwlock-cells = <1>; 207086d7c946SKrzysztof Kozlowski }; 207186d7c946SKrzysztof Kozlowski 2072d0909bf4SJohan Hovold tcsr_regs_1: syscon@1f60000 { 207386d7c946SKrzysztof Kozlowski compatible = "qcom,sm8150-tcsr", "syscon"; 207486d7c946SKrzysztof Kozlowski reg = <0x0 0x01f60000 0x0 0x20000>; 2075d8cf9372SVinod Koul }; 2076d8cf9372SVinod Koul 207749076351SSibi Sankar remoteproc_slpi: remoteproc@2400000 { 207849076351SSibi Sankar compatible = "qcom,sm8150-slpi-pas"; 207949076351SSibi Sankar reg = <0x0 0x02400000 0x0 0x4040>; 208049076351SSibi Sankar 208149076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 208249076351SSibi Sankar <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 208349076351SSibi Sankar <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 208449076351SSibi Sankar <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 208549076351SSibi Sankar <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 208649076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 208749076351SSibi Sankar "handover", "stop-ack"; 208849076351SSibi Sankar 208949076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 209049076351SSibi Sankar clock-names = "xo"; 209149076351SSibi Sankar 2092a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_LCX>, 2093a94ed9f3SKonrad Dybcio <&rpmhpd SM8150_LMX>; 2094d9d327f6SSibi Sankar power-domain-names = "lcx", "lmx"; 209549076351SSibi Sankar 209649076351SSibi Sankar memory-region = <&slpi_mem>; 209749076351SSibi Sankar 2098d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 2099d9d327f6SSibi Sankar 210049076351SSibi Sankar qcom,smem-states = <&slpi_smp2p_out 0>; 210149076351SSibi Sankar qcom,smem-state-names = "stop"; 210249076351SSibi Sankar 210349076351SSibi Sankar status = "disabled"; 210449076351SSibi Sankar 210549076351SSibi Sankar glink-edge { 210649076351SSibi Sankar interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 210749076351SSibi Sankar label = "dsps"; 210849076351SSibi Sankar qcom,remote-pid = <3>; 210949076351SSibi Sankar mboxes = <&apss_shared 24>; 211081729330SBhupesh Sharma 211181729330SBhupesh Sharma fastrpc { 211281729330SBhupesh Sharma compatible = "qcom,fastrpc"; 211381729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 211481729330SBhupesh Sharma label = "sdsp"; 21158c8ce95bSJeya R qcom,non-secure-domain; 211681729330SBhupesh Sharma #address-cells = <1>; 211781729330SBhupesh Sharma #size-cells = <0>; 211881729330SBhupesh Sharma 211981729330SBhupesh Sharma compute-cb@1 { 212081729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 212181729330SBhupesh Sharma reg = <1>; 212281729330SBhupesh Sharma iommus = <&apps_smmu 0x05a1 0x0>; 212381729330SBhupesh Sharma }; 212481729330SBhupesh Sharma 212581729330SBhupesh Sharma compute-cb@2 { 212681729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 212781729330SBhupesh Sharma reg = <2>; 212881729330SBhupesh Sharma iommus = <&apps_smmu 0x05a2 0x0>; 212981729330SBhupesh Sharma }; 213081729330SBhupesh Sharma 213181729330SBhupesh Sharma compute-cb@3 { 213281729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 213381729330SBhupesh Sharma reg = <3>; 213481729330SBhupesh Sharma iommus = <&apps_smmu 0x05a3 0x0>; 213581729330SBhupesh Sharma /* note: shared-cb = <4> in downstream */ 213681729330SBhupesh Sharma }; 213781729330SBhupesh Sharma }; 213849076351SSibi Sankar }; 213949076351SSibi Sankar }; 214049076351SSibi Sankar 2141f30ac26dSJonathan Marek gpu: gpu@2c00000 { 2142f30ac26dSJonathan Marek /* 2143f30ac26dSJonathan Marek * note: the amd,imageon compatible makes it possible 2144f30ac26dSJonathan Marek * to use the drm/msm driver without the display node, 2145f30ac26dSJonathan Marek * make sure to remove it when display node is added 2146f30ac26dSJonathan Marek */ 2147f30ac26dSJonathan Marek compatible = "qcom,adreno-640.1", 2148f30ac26dSJonathan Marek "qcom,adreno", 2149f30ac26dSJonathan Marek "amd,imageon"; 2150f30ac26dSJonathan Marek 2151f30ac26dSJonathan Marek reg = <0 0x02c00000 0 0x40000>; 2152f30ac26dSJonathan Marek reg-names = "kgsl_3d0_reg_memory"; 2153f30ac26dSJonathan Marek 2154f30ac26dSJonathan Marek interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2155f30ac26dSJonathan Marek 2156f30ac26dSJonathan Marek iommus = <&adreno_smmu 0 0x401>; 2157f30ac26dSJonathan Marek 2158f30ac26dSJonathan Marek operating-points-v2 = <&gpu_opp_table>; 2159f30ac26dSJonathan Marek 2160f30ac26dSJonathan Marek qcom,gmu = <&gmu>; 2161f30ac26dSJonathan Marek 2162b1dc3c6bSKonrad Dybcio status = "disabled"; 2163b1dc3c6bSKonrad Dybcio 2164f30ac26dSJonathan Marek zap-shader { 2165f30ac26dSJonathan Marek memory-region = <&gpu_mem>; 2166f30ac26dSJonathan Marek }; 2167f30ac26dSJonathan Marek 2168f30ac26dSJonathan Marek /* note: downstream checks gpu binning for 675 Mhz */ 2169f30ac26dSJonathan Marek gpu_opp_table: opp-table { 2170f30ac26dSJonathan Marek compatible = "operating-points-v2"; 2171f30ac26dSJonathan Marek 2172f30ac26dSJonathan Marek opp-675000000 { 2173f30ac26dSJonathan Marek opp-hz = /bits/ 64 <675000000>; 2174f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2175f30ac26dSJonathan Marek }; 2176f30ac26dSJonathan Marek 2177f30ac26dSJonathan Marek opp-585000000 { 2178f30ac26dSJonathan Marek opp-hz = /bits/ 64 <585000000>; 2179f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2180f30ac26dSJonathan Marek }; 2181f30ac26dSJonathan Marek 2182f30ac26dSJonathan Marek opp-499200000 { 2183f30ac26dSJonathan Marek opp-hz = /bits/ 64 <499200000>; 2184f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2185f30ac26dSJonathan Marek }; 2186f30ac26dSJonathan Marek 2187f30ac26dSJonathan Marek opp-427000000 { 2188f30ac26dSJonathan Marek opp-hz = /bits/ 64 <427000000>; 2189f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2190f30ac26dSJonathan Marek }; 2191f30ac26dSJonathan Marek 2192f30ac26dSJonathan Marek opp-345000000 { 2193f30ac26dSJonathan Marek opp-hz = /bits/ 64 <345000000>; 2194f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2195f30ac26dSJonathan Marek }; 2196f30ac26dSJonathan Marek 2197f30ac26dSJonathan Marek opp-257000000 { 2198f30ac26dSJonathan Marek opp-hz = /bits/ 64 <257000000>; 2199f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2200f30ac26dSJonathan Marek }; 2201f30ac26dSJonathan Marek }; 2202f30ac26dSJonathan Marek }; 2203f30ac26dSJonathan Marek 2204f30ac26dSJonathan Marek gmu: gmu@2c6a000 { 2205f30ac26dSJonathan Marek compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2206f30ac26dSJonathan Marek 2207f30ac26dSJonathan Marek reg = <0 0x02c6a000 0 0x30000>, 2208f30ac26dSJonathan Marek <0 0x0b290000 0 0x10000>, 2209f30ac26dSJonathan Marek <0 0x0b490000 0 0x10000>; 2210f30ac26dSJonathan Marek reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2211f30ac26dSJonathan Marek 2212f30ac26dSJonathan Marek interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2213f30ac26dSJonathan Marek <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2214f30ac26dSJonathan Marek interrupt-names = "hfi", "gmu"; 2215f30ac26dSJonathan Marek 2216f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 2217f1269916SJonathan Marek <&gpucc GPU_CC_CX_GMU_CLK>, 2218f1269916SJonathan Marek <&gpucc GPU_CC_CXO_CLK>, 2219f30ac26dSJonathan Marek <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2220f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2221f30ac26dSJonathan Marek clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2222f30ac26dSJonathan Marek 2223f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>, 2224f1269916SJonathan Marek <&gpucc GPU_GX_GDSC>; 2225f30ac26dSJonathan Marek power-domain-names = "cx", "gx"; 2226f30ac26dSJonathan Marek 2227f30ac26dSJonathan Marek iommus = <&adreno_smmu 5 0x400>; 2228f30ac26dSJonathan Marek 2229f30ac26dSJonathan Marek operating-points-v2 = <&gmu_opp_table>; 2230f30ac26dSJonathan Marek 2231b1dc3c6bSKonrad Dybcio status = "disabled"; 2232b1dc3c6bSKonrad Dybcio 2233f30ac26dSJonathan Marek gmu_opp_table: opp-table { 2234f30ac26dSJonathan Marek compatible = "operating-points-v2"; 2235f30ac26dSJonathan Marek 2236f30ac26dSJonathan Marek opp-200000000 { 2237f30ac26dSJonathan Marek opp-hz = /bits/ 64 <200000000>; 2238f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2239f30ac26dSJonathan Marek }; 2240f30ac26dSJonathan Marek }; 2241f30ac26dSJonathan Marek }; 2242f30ac26dSJonathan Marek 2243f30ac26dSJonathan Marek gpucc: clock-controller@2c90000 { 2244f30ac26dSJonathan Marek compatible = "qcom,sm8150-gpucc"; 2245f30ac26dSJonathan Marek reg = <0 0x02c90000 0 0x9000>; 2246f30ac26dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>, 2247f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2248f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2249f30ac26dSJonathan Marek clock-names = "bi_tcxo", 2250f30ac26dSJonathan Marek "gcc_gpu_gpll0_clk_src", 2251f30ac26dSJonathan Marek "gcc_gpu_gpll0_div_clk_src"; 2252f30ac26dSJonathan Marek #clock-cells = <1>; 2253f30ac26dSJonathan Marek #reset-cells = <1>; 2254f30ac26dSJonathan Marek #power-domain-cells = <1>; 2255f30ac26dSJonathan Marek }; 2256f30ac26dSJonathan Marek 2257f30ac26dSJonathan Marek adreno_smmu: iommu@2ca0000 { 2258c34bef62SMarijn Suijten compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2259f30ac26dSJonathan Marek reg = <0 0x02ca0000 0 0x10000>; 2260f30ac26dSJonathan Marek #iommu-cells = <2>; 2261f30ac26dSJonathan Marek #global-interrupts = <1>; 2262f30ac26dSJonathan Marek interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2263f30ac26dSJonathan Marek <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2264f30ac26dSJonathan Marek <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2265f30ac26dSJonathan Marek <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2266f30ac26dSJonathan Marek <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2267f30ac26dSJonathan Marek <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2268f30ac26dSJonathan Marek <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2269f30ac26dSJonathan Marek <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2270f30ac26dSJonathan Marek <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2271f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 2272f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2273f30ac26dSJonathan Marek <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2274f30ac26dSJonathan Marek clock-names = "ahb", "bus", "iface"; 2275f30ac26dSJonathan Marek 2276f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>; 2277f30ac26dSJonathan Marek }; 2278f30ac26dSJonathan Marek 2279e13c6d14SVinod Koul tlmm: pinctrl@3100000 { 2280e13c6d14SVinod Koul compatible = "qcom,sm8150-pinctrl"; 2281e13c6d14SVinod Koul reg = <0x0 0x03100000 0x0 0x300000>, 2282e13c6d14SVinod Koul <0x0 0x03500000 0x0 0x300000>, 2283e13c6d14SVinod Koul <0x0 0x03900000 0x0 0x300000>, 2284e13c6d14SVinod Koul <0x0 0x03D00000 0x0 0x300000>; 2285e13c6d14SVinod Koul reg-names = "west", "east", "north", "south"; 2286e13c6d14SVinod Koul interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2287de3abdf3SShawn Guo gpio-ranges = <&tlmm 0 0 176>; 2288e13c6d14SVinod Koul gpio-controller; 2289e13c6d14SVinod Koul #gpio-cells = <2>; 2290e13c6d14SVinod Koul interrupt-controller; 2291e13c6d14SVinod Koul #interrupt-cells = <2>; 22926127d8e4SBhupesh Sharma wakeup-parent = <&pdc>; 229381bee695SCaleb Connolly 2294028fe09cSKrzysztof Kozlowski qup_i2c0_default: qup-i2c0-default-state { 229581bee695SCaleb Connolly pins = "gpio0", "gpio1"; 229681bee695SCaleb Connolly function = "qup0"; 229781bee695SCaleb Connolly drive-strength = <0x02>; 229881bee695SCaleb Connolly bias-disable; 229981bee695SCaleb Connolly }; 230081bee695SCaleb Connolly 2301028fe09cSKrzysztof Kozlowski qup_spi0_default: qup-spi0-default-state { 2302129e1c96SFelipe Balbi pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2303129e1c96SFelipe Balbi function = "qup0"; 2304129e1c96SFelipe Balbi drive-strength = <6>; 2305129e1c96SFelipe Balbi bias-disable; 2306129e1c96SFelipe Balbi }; 2307129e1c96SFelipe Balbi 2308028fe09cSKrzysztof Kozlowski qup_i2c1_default: qup-i2c1-default-state { 230981bee695SCaleb Connolly pins = "gpio114", "gpio115"; 231081bee695SCaleb Connolly function = "qup1"; 2311028fe09cSKrzysztof Kozlowski drive-strength = <2>; 231281bee695SCaleb Connolly bias-disable; 231381bee695SCaleb Connolly }; 231481bee695SCaleb Connolly 2315028fe09cSKrzysztof Kozlowski qup_spi1_default: qup-spi1-default-state { 2316129e1c96SFelipe Balbi pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2317129e1c96SFelipe Balbi function = "qup1"; 2318129e1c96SFelipe Balbi drive-strength = <6>; 2319129e1c96SFelipe Balbi bias-disable; 2320129e1c96SFelipe Balbi }; 2321129e1c96SFelipe Balbi 2322028fe09cSKrzysztof Kozlowski qup_i2c2_default: qup-i2c2-default-state { 232381bee695SCaleb Connolly pins = "gpio126", "gpio127"; 232481bee695SCaleb Connolly function = "qup2"; 2325028fe09cSKrzysztof Kozlowski drive-strength = <2>; 232681bee695SCaleb Connolly bias-disable; 232781bee695SCaleb Connolly }; 232881bee695SCaleb Connolly 2329028fe09cSKrzysztof Kozlowski qup_spi2_default: qup-spi2-default-state { 2330129e1c96SFelipe Balbi pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2331129e1c96SFelipe Balbi function = "qup2"; 2332129e1c96SFelipe Balbi drive-strength = <6>; 2333129e1c96SFelipe Balbi bias-disable; 2334129e1c96SFelipe Balbi }; 2335129e1c96SFelipe Balbi 2336028fe09cSKrzysztof Kozlowski qup_i2c3_default: qup-i2c3-default-state { 233781bee695SCaleb Connolly pins = "gpio144", "gpio145"; 233881bee695SCaleb Connolly function = "qup3"; 2339028fe09cSKrzysztof Kozlowski drive-strength = <2>; 234081bee695SCaleb Connolly bias-disable; 234181bee695SCaleb Connolly }; 234281bee695SCaleb Connolly 2343028fe09cSKrzysztof Kozlowski qup_spi3_default: qup-spi3-default-state { 2344129e1c96SFelipe Balbi pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2345129e1c96SFelipe Balbi function = "qup3"; 2346129e1c96SFelipe Balbi drive-strength = <6>; 2347129e1c96SFelipe Balbi bias-disable; 2348129e1c96SFelipe Balbi }; 2349129e1c96SFelipe Balbi 2350028fe09cSKrzysztof Kozlowski qup_i2c4_default: qup-i2c4-default-state { 235181bee695SCaleb Connolly pins = "gpio51", "gpio52"; 235281bee695SCaleb Connolly function = "qup4"; 2353028fe09cSKrzysztof Kozlowski drive-strength = <2>; 235481bee695SCaleb Connolly bias-disable; 235581bee695SCaleb Connolly }; 235681bee695SCaleb Connolly 2357028fe09cSKrzysztof Kozlowski qup_spi4_default: qup-spi4-default-state { 2358129e1c96SFelipe Balbi pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2359129e1c96SFelipe Balbi function = "qup4"; 2360129e1c96SFelipe Balbi drive-strength = <6>; 2361129e1c96SFelipe Balbi bias-disable; 2362129e1c96SFelipe Balbi }; 2363129e1c96SFelipe Balbi 2364028fe09cSKrzysztof Kozlowski qup_i2c5_default: qup-i2c5-default-state { 236581bee695SCaleb Connolly pins = "gpio121", "gpio122"; 236681bee695SCaleb Connolly function = "qup5"; 2367028fe09cSKrzysztof Kozlowski drive-strength = <2>; 236881bee695SCaleb Connolly bias-disable; 236981bee695SCaleb Connolly }; 237081bee695SCaleb Connolly 2371028fe09cSKrzysztof Kozlowski qup_spi5_default: qup-spi5-default-state { 2372129e1c96SFelipe Balbi pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2373129e1c96SFelipe Balbi function = "qup5"; 2374129e1c96SFelipe Balbi drive-strength = <6>; 2375129e1c96SFelipe Balbi bias-disable; 2376129e1c96SFelipe Balbi }; 2377129e1c96SFelipe Balbi 2378028fe09cSKrzysztof Kozlowski qup_i2c6_default: qup-i2c6-default-state { 237981bee695SCaleb Connolly pins = "gpio6", "gpio7"; 238081bee695SCaleb Connolly function = "qup6"; 2381028fe09cSKrzysztof Kozlowski drive-strength = <2>; 238281bee695SCaleb Connolly bias-disable; 238381bee695SCaleb Connolly }; 238481bee695SCaleb Connolly 2385028fe09cSKrzysztof Kozlowski qup_spi6_default: qup-spi6_default-state { 2386129e1c96SFelipe Balbi pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2387129e1c96SFelipe Balbi function = "qup6"; 2388129e1c96SFelipe Balbi drive-strength = <6>; 2389129e1c96SFelipe Balbi bias-disable; 2390129e1c96SFelipe Balbi }; 2391129e1c96SFelipe Balbi 2392028fe09cSKrzysztof Kozlowski qup_i2c7_default: qup-i2c7-default-state { 239381bee695SCaleb Connolly pins = "gpio98", "gpio99"; 239481bee695SCaleb Connolly function = "qup7"; 2395028fe09cSKrzysztof Kozlowski drive-strength = <2>; 239681bee695SCaleb Connolly bias-disable; 239781bee695SCaleb Connolly }; 239881bee695SCaleb Connolly 2399028fe09cSKrzysztof Kozlowski qup_spi7_default: qup-spi7_default-state { 2400129e1c96SFelipe Balbi pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2401129e1c96SFelipe Balbi function = "qup7"; 2402129e1c96SFelipe Balbi drive-strength = <6>; 2403129e1c96SFelipe Balbi bias-disable; 2404129e1c96SFelipe Balbi }; 2405129e1c96SFelipe Balbi 2406028fe09cSKrzysztof Kozlowski qup_i2c8_default: qup-i2c8-default-state { 240781bee695SCaleb Connolly pins = "gpio88", "gpio89"; 240881bee695SCaleb Connolly function = "qup8"; 2409028fe09cSKrzysztof Kozlowski drive-strength = <2>; 241081bee695SCaleb Connolly bias-disable; 241181bee695SCaleb Connolly }; 241281bee695SCaleb Connolly 2413028fe09cSKrzysztof Kozlowski qup_spi8_default: qup-spi8-default-state { 2414129e1c96SFelipe Balbi pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2415129e1c96SFelipe Balbi function = "qup8"; 2416129e1c96SFelipe Balbi drive-strength = <6>; 2417129e1c96SFelipe Balbi bias-disable; 2418129e1c96SFelipe Balbi }; 2419129e1c96SFelipe Balbi 2420028fe09cSKrzysztof Kozlowski qup_i2c9_default: qup-i2c9-default-state { 242181bee695SCaleb Connolly pins = "gpio39", "gpio40"; 242281bee695SCaleb Connolly function = "qup9"; 2423028fe09cSKrzysztof Kozlowski drive-strength = <2>; 242481bee695SCaleb Connolly bias-disable; 242581bee695SCaleb Connolly }; 242681bee695SCaleb Connolly 2427028fe09cSKrzysztof Kozlowski qup_spi9_default: qup-spi9-default-state { 2428129e1c96SFelipe Balbi pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2429129e1c96SFelipe Balbi function = "qup9"; 2430129e1c96SFelipe Balbi drive-strength = <6>; 2431129e1c96SFelipe Balbi bias-disable; 2432129e1c96SFelipe Balbi }; 2433129e1c96SFelipe Balbi 2434028fe09cSKrzysztof Kozlowski qup_i2c10_default: qup-i2c10-default-state { 243581bee695SCaleb Connolly pins = "gpio9", "gpio10"; 243681bee695SCaleb Connolly function = "qup10"; 2437028fe09cSKrzysztof Kozlowski drive-strength = <2>; 243881bee695SCaleb Connolly bias-disable; 243981bee695SCaleb Connolly }; 244081bee695SCaleb Connolly 2441028fe09cSKrzysztof Kozlowski qup_spi10_default: qup-spi10-default-state { 2442129e1c96SFelipe Balbi pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2443129e1c96SFelipe Balbi function = "qup10"; 2444129e1c96SFelipe Balbi drive-strength = <6>; 2445129e1c96SFelipe Balbi bias-disable; 2446129e1c96SFelipe Balbi }; 2447129e1c96SFelipe Balbi 2448028fe09cSKrzysztof Kozlowski qup_i2c11_default: qup-i2c11-default-state { 244981bee695SCaleb Connolly pins = "gpio94", "gpio95"; 245081bee695SCaleb Connolly function = "qup11"; 2451028fe09cSKrzysztof Kozlowski drive-strength = <2>; 245281bee695SCaleb Connolly bias-disable; 245381bee695SCaleb Connolly }; 245481bee695SCaleb Connolly 2455028fe09cSKrzysztof Kozlowski qup_spi11_default: qup-spi11-default-state { 2456129e1c96SFelipe Balbi pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2457129e1c96SFelipe Balbi function = "qup11"; 2458129e1c96SFelipe Balbi drive-strength = <6>; 2459129e1c96SFelipe Balbi bias-disable; 2460129e1c96SFelipe Balbi }; 2461129e1c96SFelipe Balbi 2462028fe09cSKrzysztof Kozlowski qup_i2c12_default: qup-i2c12-default-state { 246381bee695SCaleb Connolly pins = "gpio83", "gpio84"; 246481bee695SCaleb Connolly function = "qup12"; 2465028fe09cSKrzysztof Kozlowski drive-strength = <2>; 246681bee695SCaleb Connolly bias-disable; 246781bee695SCaleb Connolly }; 246881bee695SCaleb Connolly 2469028fe09cSKrzysztof Kozlowski qup_spi12_default: qup-spi12-default-state { 2470129e1c96SFelipe Balbi pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2471129e1c96SFelipe Balbi function = "qup12"; 2472129e1c96SFelipe Balbi drive-strength = <6>; 2473129e1c96SFelipe Balbi bias-disable; 2474129e1c96SFelipe Balbi }; 2475129e1c96SFelipe Balbi 2476028fe09cSKrzysztof Kozlowski qup_i2c13_default: qup-i2c13-default-state { 247781bee695SCaleb Connolly pins = "gpio43", "gpio44"; 247881bee695SCaleb Connolly function = "qup13"; 2479028fe09cSKrzysztof Kozlowski drive-strength = <2>; 248081bee695SCaleb Connolly bias-disable; 248181bee695SCaleb Connolly }; 248281bee695SCaleb Connolly 2483028fe09cSKrzysztof Kozlowski qup_spi13_default: qup-spi13-default-state { 2484129e1c96SFelipe Balbi pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2485129e1c96SFelipe Balbi function = "qup13"; 2486129e1c96SFelipe Balbi drive-strength = <6>; 2487129e1c96SFelipe Balbi bias-disable; 2488129e1c96SFelipe Balbi }; 2489129e1c96SFelipe Balbi 2490028fe09cSKrzysztof Kozlowski qup_i2c14_default: qup-i2c14-default-state { 249181bee695SCaleb Connolly pins = "gpio47", "gpio48"; 249281bee695SCaleb Connolly function = "qup14"; 2493028fe09cSKrzysztof Kozlowski drive-strength = <2>; 249481bee695SCaleb Connolly bias-disable; 249581bee695SCaleb Connolly }; 249681bee695SCaleb Connolly 2497028fe09cSKrzysztof Kozlowski qup_spi14_default: qup-spi14-default-state { 2498129e1c96SFelipe Balbi pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2499129e1c96SFelipe Balbi function = "qup14"; 2500129e1c96SFelipe Balbi drive-strength = <6>; 2501129e1c96SFelipe Balbi bias-disable; 2502129e1c96SFelipe Balbi }; 2503129e1c96SFelipe Balbi 2504028fe09cSKrzysztof Kozlowski qup_i2c15_default: qup-i2c15-default-state { 250581bee695SCaleb Connolly pins = "gpio27", "gpio28"; 250681bee695SCaleb Connolly function = "qup15"; 2507028fe09cSKrzysztof Kozlowski drive-strength = <2>; 250881bee695SCaleb Connolly bias-disable; 250981bee695SCaleb Connolly }; 251081bee695SCaleb Connolly 2511028fe09cSKrzysztof Kozlowski qup_spi15_default: qup-spi15-default-state { 2512129e1c96SFelipe Balbi pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2513129e1c96SFelipe Balbi function = "qup15"; 2514129e1c96SFelipe Balbi drive-strength = <6>; 2515129e1c96SFelipe Balbi bias-disable; 2516129e1c96SFelipe Balbi }; 2517129e1c96SFelipe Balbi 2518028fe09cSKrzysztof Kozlowski qup_i2c16_default: qup-i2c16-default-state { 251981bee695SCaleb Connolly pins = "gpio86", "gpio85"; 252081bee695SCaleb Connolly function = "qup16"; 2521028fe09cSKrzysztof Kozlowski drive-strength = <2>; 252281bee695SCaleb Connolly bias-disable; 252381bee695SCaleb Connolly }; 252481bee695SCaleb Connolly 2525028fe09cSKrzysztof Kozlowski qup_spi16_default: qup-spi16-default-state { 2526129e1c96SFelipe Balbi pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2527129e1c96SFelipe Balbi function = "qup16"; 2528129e1c96SFelipe Balbi drive-strength = <6>; 2529129e1c96SFelipe Balbi bias-disable; 2530129e1c96SFelipe Balbi }; 2531129e1c96SFelipe Balbi 2532028fe09cSKrzysztof Kozlowski qup_i2c17_default: qup-i2c17-default-state { 253381bee695SCaleb Connolly pins = "gpio55", "gpio56"; 253481bee695SCaleb Connolly function = "qup17"; 2535028fe09cSKrzysztof Kozlowski drive-strength = <2>; 253681bee695SCaleb Connolly bias-disable; 253781bee695SCaleb Connolly }; 253881bee695SCaleb Connolly 2539028fe09cSKrzysztof Kozlowski qup_spi17_default: qup-spi17-default-state { 2540129e1c96SFelipe Balbi pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2541129e1c96SFelipe Balbi function = "qup17"; 2542129e1c96SFelipe Balbi drive-strength = <6>; 2543129e1c96SFelipe Balbi bias-disable; 2544129e1c96SFelipe Balbi }; 2545129e1c96SFelipe Balbi 2546028fe09cSKrzysztof Kozlowski qup_i2c18_default: qup-i2c18-default-state { 254781bee695SCaleb Connolly pins = "gpio23", "gpio24"; 254881bee695SCaleb Connolly function = "qup18"; 2549028fe09cSKrzysztof Kozlowski drive-strength = <2>; 255081bee695SCaleb Connolly bias-disable; 255181bee695SCaleb Connolly }; 255281bee695SCaleb Connolly 2553028fe09cSKrzysztof Kozlowski qup_spi18_default: qup-spi18-default-state { 2554129e1c96SFelipe Balbi pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2555129e1c96SFelipe Balbi function = "qup18"; 2556129e1c96SFelipe Balbi drive-strength = <6>; 2557129e1c96SFelipe Balbi bias-disable; 2558129e1c96SFelipe Balbi }; 2559129e1c96SFelipe Balbi 2560028fe09cSKrzysztof Kozlowski qup_i2c19_default: qup-i2c19-default-state { 256181bee695SCaleb Connolly pins = "gpio57", "gpio58"; 256281bee695SCaleb Connolly function = "qup19"; 2563028fe09cSKrzysztof Kozlowski drive-strength = <2>; 256481bee695SCaleb Connolly bias-disable; 256581bee695SCaleb Connolly }; 2566129e1c96SFelipe Balbi 2567028fe09cSKrzysztof Kozlowski qup_spi19_default: qup-spi19-default-state { 2568129e1c96SFelipe Balbi pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2569129e1c96SFelipe Balbi function = "qup19"; 2570129e1c96SFelipe Balbi drive-strength = <6>; 2571129e1c96SFelipe Balbi bias-disable; 2572129e1c96SFelipe Balbi }; 2573a1c86c68SBhupesh Sharma 2574028fe09cSKrzysztof Kozlowski pcie0_default_state: pcie0-default-state { 2575028fe09cSKrzysztof Kozlowski perst-pins { 2576a1c86c68SBhupesh Sharma pins = "gpio35"; 2577a1c86c68SBhupesh Sharma function = "gpio"; 2578a1c86c68SBhupesh Sharma drive-strength = <2>; 2579a1c86c68SBhupesh Sharma bias-pull-down; 2580a1c86c68SBhupesh Sharma }; 2581a1c86c68SBhupesh Sharma 2582028fe09cSKrzysztof Kozlowski clkreq-pins { 2583a1c86c68SBhupesh Sharma pins = "gpio36"; 2584a1c86c68SBhupesh Sharma function = "pci_e0"; 2585a1c86c68SBhupesh Sharma drive-strength = <2>; 2586a1c86c68SBhupesh Sharma bias-pull-up; 2587a1c86c68SBhupesh Sharma }; 2588a1c86c68SBhupesh Sharma 2589028fe09cSKrzysztof Kozlowski wake-pins { 2590a1c86c68SBhupesh Sharma pins = "gpio37"; 2591a1c86c68SBhupesh Sharma function = "gpio"; 2592a1c86c68SBhupesh Sharma drive-strength = <2>; 2593a1c86c68SBhupesh Sharma bias-pull-up; 2594a1c86c68SBhupesh Sharma }; 2595a1c86c68SBhupesh Sharma }; 2596a1c86c68SBhupesh Sharma 2597028fe09cSKrzysztof Kozlowski pcie1_default_state: pcie1-default-state { 2598028fe09cSKrzysztof Kozlowski perst-pins { 2599a1c86c68SBhupesh Sharma pins = "gpio102"; 2600a1c86c68SBhupesh Sharma function = "gpio"; 2601a1c86c68SBhupesh Sharma drive-strength = <2>; 2602a1c86c68SBhupesh Sharma bias-pull-down; 2603a1c86c68SBhupesh Sharma }; 2604a1c86c68SBhupesh Sharma 2605028fe09cSKrzysztof Kozlowski clkreq-pins { 2606a1c86c68SBhupesh Sharma pins = "gpio103"; 2607a1c86c68SBhupesh Sharma function = "pci_e1"; 2608a1c86c68SBhupesh Sharma drive-strength = <2>; 2609a1c86c68SBhupesh Sharma bias-pull-up; 2610a1c86c68SBhupesh Sharma }; 2611a1c86c68SBhupesh Sharma 2612028fe09cSKrzysztof Kozlowski wake-pins { 2613a1c86c68SBhupesh Sharma pins = "gpio104"; 2614a1c86c68SBhupesh Sharma function = "gpio"; 2615a1c86c68SBhupesh Sharma drive-strength = <2>; 2616a1c86c68SBhupesh Sharma bias-pull-up; 2617a1c86c68SBhupesh Sharma }; 2618a1c86c68SBhupesh Sharma }; 2619e13c6d14SVinod Koul }; 2620e13c6d14SVinod Koul 262149076351SSibi Sankar remoteproc_mpss: remoteproc@4080000 { 262249076351SSibi Sankar compatible = "qcom,sm8150-mpss-pas"; 262349076351SSibi Sankar reg = <0x0 0x04080000 0x0 0x4040>; 262449076351SSibi Sankar 262549076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 262649076351SSibi Sankar <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 262749076351SSibi Sankar <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 262849076351SSibi Sankar <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 262949076351SSibi Sankar <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 263049076351SSibi Sankar <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 263149076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", "handover", 263249076351SSibi Sankar "stop-ack", "shutdown-ack"; 263349076351SSibi Sankar 263449076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 263549076351SSibi Sankar clock-names = "xo"; 263649076351SSibi Sankar 2637a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_CX>, 2638a94ed9f3SKonrad Dybcio <&rpmhpd SM8150_MSS>; 2639d9d327f6SSibi Sankar power-domain-names = "cx", "mss"; 264049076351SSibi Sankar 264149076351SSibi Sankar memory-region = <&mpss_mem>; 264249076351SSibi Sankar 2643d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 2644d9d327f6SSibi Sankar 264549076351SSibi Sankar qcom,smem-states = <&modem_smp2p_out 0>; 264649076351SSibi Sankar qcom,smem-state-names = "stop"; 264749076351SSibi Sankar 2648b1dc3c6bSKonrad Dybcio status = "disabled"; 2649b1dc3c6bSKonrad Dybcio 265049076351SSibi Sankar glink-edge { 265149076351SSibi Sankar interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 265249076351SSibi Sankar label = "modem"; 265349076351SSibi Sankar qcom,remote-pid = <1>; 265449076351SSibi Sankar mboxes = <&apss_shared 12>; 265549076351SSibi Sankar }; 265649076351SSibi Sankar }; 265749076351SSibi Sankar 265824244cefSSai Prakash Ranjan stm@6002000 { 265924244cefSSai Prakash Ranjan compatible = "arm,coresight-stm", "arm,primecell"; 266024244cefSSai Prakash Ranjan reg = <0 0x06002000 0 0x1000>, 266124244cefSSai Prakash Ranjan <0 0x16280000 0 0x180000>; 266224244cefSSai Prakash Ranjan reg-names = "stm-base", "stm-stimulus-base"; 266324244cefSSai Prakash Ranjan 266424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 266524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 266624244cefSSai Prakash Ranjan 266724244cefSSai Prakash Ranjan out-ports { 266824244cefSSai Prakash Ranjan port { 266924244cefSSai Prakash Ranjan stm_out: endpoint { 267024244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_in7>; 267124244cefSSai Prakash Ranjan }; 267224244cefSSai Prakash Ranjan }; 267324244cefSSai Prakash Ranjan }; 267424244cefSSai Prakash Ranjan }; 267524244cefSSai Prakash Ranjan 267624244cefSSai Prakash Ranjan funnel@6041000 { 267724244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 267824244cefSSai Prakash Ranjan reg = <0 0x06041000 0 0x1000>; 267924244cefSSai Prakash Ranjan 268024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 268124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 268224244cefSSai Prakash Ranjan 268324244cefSSai Prakash Ranjan out-ports { 268424244cefSSai Prakash Ranjan port { 268524244cefSSai Prakash Ranjan funnel0_out: endpoint { 268624244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in0>; 268724244cefSSai Prakash Ranjan }; 268824244cefSSai Prakash Ranjan }; 268924244cefSSai Prakash Ranjan }; 269024244cefSSai Prakash Ranjan 269124244cefSSai Prakash Ranjan in-ports { 269224244cefSSai Prakash Ranjan #address-cells = <1>; 269324244cefSSai Prakash Ranjan #size-cells = <0>; 269424244cefSSai Prakash Ranjan 269524244cefSSai Prakash Ranjan port@7 { 269624244cefSSai Prakash Ranjan reg = <7>; 269724244cefSSai Prakash Ranjan funnel0_in7: endpoint { 269824244cefSSai Prakash Ranjan remote-endpoint = <&stm_out>; 269924244cefSSai Prakash Ranjan }; 270024244cefSSai Prakash Ranjan }; 270124244cefSSai Prakash Ranjan }; 270224244cefSSai Prakash Ranjan }; 270324244cefSSai Prakash Ranjan 270424244cefSSai Prakash Ranjan funnel@6042000 { 270524244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 270624244cefSSai Prakash Ranjan reg = <0 0x06042000 0 0x1000>; 270724244cefSSai Prakash Ranjan 270824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 270924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 271024244cefSSai Prakash Ranjan 271124244cefSSai Prakash Ranjan out-ports { 271224244cefSSai Prakash Ranjan port { 271324244cefSSai Prakash Ranjan funnel1_out: endpoint { 271424244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in1>; 271524244cefSSai Prakash Ranjan }; 271624244cefSSai Prakash Ranjan }; 271724244cefSSai Prakash Ranjan }; 271824244cefSSai Prakash Ranjan 271924244cefSSai Prakash Ranjan in-ports { 272024244cefSSai Prakash Ranjan #address-cells = <1>; 272124244cefSSai Prakash Ranjan #size-cells = <0>; 272224244cefSSai Prakash Ranjan 272324244cefSSai Prakash Ranjan port@4 { 272424244cefSSai Prakash Ranjan reg = <4>; 272524244cefSSai Prakash Ranjan funnel1_in4: endpoint { 272624244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_out>; 272724244cefSSai Prakash Ranjan }; 272824244cefSSai Prakash Ranjan }; 272924244cefSSai Prakash Ranjan }; 273024244cefSSai Prakash Ranjan }; 273124244cefSSai Prakash Ranjan 273224244cefSSai Prakash Ranjan funnel@6043000 { 273324244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 273424244cefSSai Prakash Ranjan reg = <0 0x06043000 0 0x1000>; 273524244cefSSai Prakash Ranjan 273624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 273724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 273824244cefSSai Prakash Ranjan 273924244cefSSai Prakash Ranjan out-ports { 274024244cefSSai Prakash Ranjan port { 274124244cefSSai Prakash Ranjan funnel2_out: endpoint { 274224244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in2>; 274324244cefSSai Prakash Ranjan }; 274424244cefSSai Prakash Ranjan }; 274524244cefSSai Prakash Ranjan }; 274624244cefSSai Prakash Ranjan 274724244cefSSai Prakash Ranjan in-ports { 274824244cefSSai Prakash Ranjan #address-cells = <1>; 274924244cefSSai Prakash Ranjan #size-cells = <0>; 275024244cefSSai Prakash Ranjan 275124244cefSSai Prakash Ranjan port@2 { 275224244cefSSai Prakash Ranjan reg = <2>; 275324244cefSSai Prakash Ranjan funnel2_in2: endpoint { 275424244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_out>; 275524244cefSSai Prakash Ranjan }; 275624244cefSSai Prakash Ranjan }; 275724244cefSSai Prakash Ranjan }; 275824244cefSSai Prakash Ranjan }; 275924244cefSSai Prakash Ranjan 276024244cefSSai Prakash Ranjan funnel@6045000 { 276124244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 276224244cefSSai Prakash Ranjan reg = <0 0x06045000 0 0x1000>; 276324244cefSSai Prakash Ranjan 276424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 276524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 276624244cefSSai Prakash Ranjan 276724244cefSSai Prakash Ranjan out-ports { 276824244cefSSai Prakash Ranjan port { 276924244cefSSai Prakash Ranjan merge_funnel_out: endpoint { 277024244cefSSai Prakash Ranjan remote-endpoint = <&etf_in>; 277124244cefSSai Prakash Ranjan }; 277224244cefSSai Prakash Ranjan }; 277324244cefSSai Prakash Ranjan }; 277424244cefSSai Prakash Ranjan 277524244cefSSai Prakash Ranjan in-ports { 277624244cefSSai Prakash Ranjan #address-cells = <1>; 277724244cefSSai Prakash Ranjan #size-cells = <0>; 277824244cefSSai Prakash Ranjan 277924244cefSSai Prakash Ranjan port@0 { 278024244cefSSai Prakash Ranjan reg = <0>; 278124244cefSSai Prakash Ranjan merge_funnel_in0: endpoint { 278224244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_out>; 278324244cefSSai Prakash Ranjan }; 278424244cefSSai Prakash Ranjan }; 278524244cefSSai Prakash Ranjan 278624244cefSSai Prakash Ranjan port@1 { 278724244cefSSai Prakash Ranjan reg = <1>; 278824244cefSSai Prakash Ranjan merge_funnel_in1: endpoint { 278924244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_out>; 279024244cefSSai Prakash Ranjan }; 279124244cefSSai Prakash Ranjan }; 279224244cefSSai Prakash Ranjan 279324244cefSSai Prakash Ranjan port@2 { 279424244cefSSai Prakash Ranjan reg = <2>; 279524244cefSSai Prakash Ranjan merge_funnel_in2: endpoint { 279624244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_out>; 279724244cefSSai Prakash Ranjan }; 279824244cefSSai Prakash Ranjan }; 279924244cefSSai Prakash Ranjan }; 280024244cefSSai Prakash Ranjan }; 280124244cefSSai Prakash Ranjan 280224244cefSSai Prakash Ranjan replicator@6046000 { 280324244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 280424244cefSSai Prakash Ranjan reg = <0 0x06046000 0 0x1000>; 280524244cefSSai Prakash Ranjan 280624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 280724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 280824244cefSSai Prakash Ranjan 280924244cefSSai Prakash Ranjan out-ports { 281024244cefSSai Prakash Ranjan #address-cells = <1>; 281124244cefSSai Prakash Ranjan #size-cells = <0>; 281224244cefSSai Prakash Ranjan 281324244cefSSai Prakash Ranjan port@0 { 281424244cefSSai Prakash Ranjan reg = <0>; 281524244cefSSai Prakash Ranjan replicator_out0: endpoint { 281624244cefSSai Prakash Ranjan remote-endpoint = <&etr_in>; 281724244cefSSai Prakash Ranjan }; 281824244cefSSai Prakash Ranjan }; 281924244cefSSai Prakash Ranjan 282024244cefSSai Prakash Ranjan port@1 { 282124244cefSSai Prakash Ranjan reg = <1>; 282224244cefSSai Prakash Ranjan replicator_out1: endpoint { 282324244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_in>; 282424244cefSSai Prakash Ranjan }; 282524244cefSSai Prakash Ranjan }; 282624244cefSSai Prakash Ranjan }; 282724244cefSSai Prakash Ranjan 282824244cefSSai Prakash Ranjan in-ports { 282924244cefSSai Prakash Ranjan port { 283024244cefSSai Prakash Ranjan replicator_in0: endpoint { 283124244cefSSai Prakash Ranjan remote-endpoint = <&etf_out>; 283224244cefSSai Prakash Ranjan }; 283324244cefSSai Prakash Ranjan }; 283424244cefSSai Prakash Ranjan }; 283524244cefSSai Prakash Ranjan }; 283624244cefSSai Prakash Ranjan 283724244cefSSai Prakash Ranjan etf@6047000 { 283824244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 283924244cefSSai Prakash Ranjan reg = <0 0x06047000 0 0x1000>; 284024244cefSSai Prakash Ranjan 284124244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 284224244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 284324244cefSSai Prakash Ranjan 284424244cefSSai Prakash Ranjan out-ports { 284524244cefSSai Prakash Ranjan port { 284624244cefSSai Prakash Ranjan etf_out: endpoint { 284724244cefSSai Prakash Ranjan remote-endpoint = <&replicator_in0>; 284824244cefSSai Prakash Ranjan }; 284924244cefSSai Prakash Ranjan }; 285024244cefSSai Prakash Ranjan }; 285124244cefSSai Prakash Ranjan 285224244cefSSai Prakash Ranjan in-ports { 285324244cefSSai Prakash Ranjan port { 285424244cefSSai Prakash Ranjan etf_in: endpoint { 285524244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_out>; 285624244cefSSai Prakash Ranjan }; 285724244cefSSai Prakash Ranjan }; 285824244cefSSai Prakash Ranjan }; 285924244cefSSai Prakash Ranjan }; 286024244cefSSai Prakash Ranjan 286124244cefSSai Prakash Ranjan etr@6048000 { 286224244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 286324244cefSSai Prakash Ranjan reg = <0 0x06048000 0 0x1000>; 286424244cefSSai Prakash Ranjan iommus = <&apps_smmu 0x05e0 0x0>; 286524244cefSSai Prakash Ranjan 286624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 286724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 286824244cefSSai Prakash Ranjan arm,scatter-gather; 286924244cefSSai Prakash Ranjan 287024244cefSSai Prakash Ranjan in-ports { 287124244cefSSai Prakash Ranjan port { 287224244cefSSai Prakash Ranjan etr_in: endpoint { 287324244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out0>; 287424244cefSSai Prakash Ranjan }; 287524244cefSSai Prakash Ranjan }; 287624244cefSSai Prakash Ranjan }; 287724244cefSSai Prakash Ranjan }; 287824244cefSSai Prakash Ranjan 287924244cefSSai Prakash Ranjan replicator@604a000 { 288024244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 288124244cefSSai Prakash Ranjan reg = <0 0x0604a000 0 0x1000>; 288224244cefSSai Prakash Ranjan 288324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 288424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 288524244cefSSai Prakash Ranjan 288624244cefSSai Prakash Ranjan out-ports { 288724244cefSSai Prakash Ranjan #address-cells = <1>; 288824244cefSSai Prakash Ranjan #size-cells = <0>; 288924244cefSSai Prakash Ranjan 289024244cefSSai Prakash Ranjan port@1 { 289124244cefSSai Prakash Ranjan reg = <1>; 289224244cefSSai Prakash Ranjan replicator1_out: endpoint { 289324244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_in>; 289424244cefSSai Prakash Ranjan }; 289524244cefSSai Prakash Ranjan }; 289624244cefSSai Prakash Ranjan }; 289724244cefSSai Prakash Ranjan 289824244cefSSai Prakash Ranjan in-ports { 289924244cefSSai Prakash Ranjan #address-cells = <1>; 290024244cefSSai Prakash Ranjan #size-cells = <0>; 290124244cefSSai Prakash Ranjan 290224244cefSSai Prakash Ranjan port@1 { 290324244cefSSai Prakash Ranjan reg = <1>; 290424244cefSSai Prakash Ranjan replicator1_in: endpoint { 290524244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out1>; 290624244cefSSai Prakash Ranjan }; 290724244cefSSai Prakash Ranjan }; 290824244cefSSai Prakash Ranjan }; 290924244cefSSai Prakash Ranjan }; 291024244cefSSai Prakash Ranjan 291124244cefSSai Prakash Ranjan funnel@6b08000 { 291224244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 291324244cefSSai Prakash Ranjan reg = <0 0x06b08000 0 0x1000>; 291424244cefSSai Prakash Ranjan 291524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 291624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 291724244cefSSai Prakash Ranjan 291824244cefSSai Prakash Ranjan out-ports { 291924244cefSSai Prakash Ranjan port { 292024244cefSSai Prakash Ranjan swao_funnel_out: endpoint { 292124244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_in>; 292224244cefSSai Prakash Ranjan }; 292324244cefSSai Prakash Ranjan }; 292424244cefSSai Prakash Ranjan }; 292524244cefSSai Prakash Ranjan 292624244cefSSai Prakash Ranjan in-ports { 292724244cefSSai Prakash Ranjan #address-cells = <1>; 292824244cefSSai Prakash Ranjan #size-cells = <0>; 292924244cefSSai Prakash Ranjan 293024244cefSSai Prakash Ranjan port@6 { 293124244cefSSai Prakash Ranjan reg = <6>; 293224244cefSSai Prakash Ranjan swao_funnel_in: endpoint { 293324244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_out>; 293424244cefSSai Prakash Ranjan }; 293524244cefSSai Prakash Ranjan }; 293624244cefSSai Prakash Ranjan }; 293724244cefSSai Prakash Ranjan }; 293824244cefSSai Prakash Ranjan 293924244cefSSai Prakash Ranjan etf@6b09000 { 294024244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 294124244cefSSai Prakash Ranjan reg = <0 0x06b09000 0 0x1000>; 294224244cefSSai Prakash Ranjan 294324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 294424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 294524244cefSSai Prakash Ranjan 294624244cefSSai Prakash Ranjan out-ports { 294724244cefSSai Prakash Ranjan port { 294824244cefSSai Prakash Ranjan swao_etf_out: endpoint { 294924244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_in>; 295024244cefSSai Prakash Ranjan }; 295124244cefSSai Prakash Ranjan }; 295224244cefSSai Prakash Ranjan }; 295324244cefSSai Prakash Ranjan 295424244cefSSai Prakash Ranjan in-ports { 295524244cefSSai Prakash Ranjan port { 295624244cefSSai Prakash Ranjan swao_etf_in: endpoint { 295724244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_out>; 295824244cefSSai Prakash Ranjan }; 295924244cefSSai Prakash Ranjan }; 296024244cefSSai Prakash Ranjan }; 296124244cefSSai Prakash Ranjan }; 296224244cefSSai Prakash Ranjan 296324244cefSSai Prakash Ranjan replicator@6b0a000 { 296424244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 296524244cefSSai Prakash Ranjan reg = <0 0x06b0a000 0 0x1000>; 296624244cefSSai Prakash Ranjan 296724244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 296824244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 296924244cefSSai Prakash Ranjan qcom,replicator-loses-context; 297024244cefSSai Prakash Ranjan 297124244cefSSai Prakash Ranjan out-ports { 297224244cefSSai Prakash Ranjan port { 297324244cefSSai Prakash Ranjan swao_replicator_out: endpoint { 297424244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_in4>; 297524244cefSSai Prakash Ranjan }; 297624244cefSSai Prakash Ranjan }; 297724244cefSSai Prakash Ranjan }; 297824244cefSSai Prakash Ranjan 297924244cefSSai Prakash Ranjan in-ports { 298024244cefSSai Prakash Ranjan port { 298124244cefSSai Prakash Ranjan swao_replicator_in: endpoint { 298224244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_out>; 298324244cefSSai Prakash Ranjan }; 298424244cefSSai Prakash Ranjan }; 298524244cefSSai Prakash Ranjan }; 298624244cefSSai Prakash Ranjan }; 298724244cefSSai Prakash Ranjan 298824244cefSSai Prakash Ranjan etm@7040000 { 298924244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 299024244cefSSai Prakash Ranjan reg = <0 0x07040000 0 0x1000>; 299124244cefSSai Prakash Ranjan 299224244cefSSai Prakash Ranjan cpu = <&CPU0>; 299324244cefSSai Prakash Ranjan 299424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 299524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 299624244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 299724244cefSSai Prakash Ranjan qcom,skip-power-up; 299824244cefSSai Prakash Ranjan 299924244cefSSai Prakash Ranjan out-ports { 300024244cefSSai Prakash Ranjan port { 300124244cefSSai Prakash Ranjan etm0_out: endpoint { 300224244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in0>; 300324244cefSSai Prakash Ranjan }; 300424244cefSSai Prakash Ranjan }; 300524244cefSSai Prakash Ranjan }; 300624244cefSSai Prakash Ranjan }; 300724244cefSSai Prakash Ranjan 300824244cefSSai Prakash Ranjan etm@7140000 { 300924244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 301024244cefSSai Prakash Ranjan reg = <0 0x07140000 0 0x1000>; 301124244cefSSai Prakash Ranjan 301224244cefSSai Prakash Ranjan cpu = <&CPU1>; 301324244cefSSai Prakash Ranjan 301424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 301524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 301624244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 301724244cefSSai Prakash Ranjan qcom,skip-power-up; 301824244cefSSai Prakash Ranjan 301924244cefSSai Prakash Ranjan out-ports { 302024244cefSSai Prakash Ranjan port { 302124244cefSSai Prakash Ranjan etm1_out: endpoint { 302224244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in1>; 302324244cefSSai Prakash Ranjan }; 302424244cefSSai Prakash Ranjan }; 302524244cefSSai Prakash Ranjan }; 302624244cefSSai Prakash Ranjan }; 302724244cefSSai Prakash Ranjan 302824244cefSSai Prakash Ranjan etm@7240000 { 302924244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 303024244cefSSai Prakash Ranjan reg = <0 0x07240000 0 0x1000>; 303124244cefSSai Prakash Ranjan 303224244cefSSai Prakash Ranjan cpu = <&CPU2>; 303324244cefSSai Prakash Ranjan 303424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 303524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 303624244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 303724244cefSSai Prakash Ranjan qcom,skip-power-up; 303824244cefSSai Prakash Ranjan 303924244cefSSai Prakash Ranjan out-ports { 304024244cefSSai Prakash Ranjan port { 304124244cefSSai Prakash Ranjan etm2_out: endpoint { 304224244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in2>; 304324244cefSSai Prakash Ranjan }; 304424244cefSSai Prakash Ranjan }; 304524244cefSSai Prakash Ranjan }; 304624244cefSSai Prakash Ranjan }; 304724244cefSSai Prakash Ranjan 304824244cefSSai Prakash Ranjan etm@7340000 { 304924244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 305024244cefSSai Prakash Ranjan reg = <0 0x07340000 0 0x1000>; 305124244cefSSai Prakash Ranjan 305224244cefSSai Prakash Ranjan cpu = <&CPU3>; 305324244cefSSai Prakash Ranjan 305424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 305524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 305624244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 305724244cefSSai Prakash Ranjan qcom,skip-power-up; 305824244cefSSai Prakash Ranjan 305924244cefSSai Prakash Ranjan out-ports { 306024244cefSSai Prakash Ranjan port { 306124244cefSSai Prakash Ranjan etm3_out: endpoint { 306224244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in3>; 306324244cefSSai Prakash Ranjan }; 306424244cefSSai Prakash Ranjan }; 306524244cefSSai Prakash Ranjan }; 306624244cefSSai Prakash Ranjan }; 306724244cefSSai Prakash Ranjan 306824244cefSSai Prakash Ranjan etm@7440000 { 306924244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 307024244cefSSai Prakash Ranjan reg = <0 0x07440000 0 0x1000>; 307124244cefSSai Prakash Ranjan 307224244cefSSai Prakash Ranjan cpu = <&CPU4>; 307324244cefSSai Prakash Ranjan 307424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 307524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 307624244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 307724244cefSSai Prakash Ranjan qcom,skip-power-up; 307824244cefSSai Prakash Ranjan 307924244cefSSai Prakash Ranjan out-ports { 308024244cefSSai Prakash Ranjan port { 308124244cefSSai Prakash Ranjan etm4_out: endpoint { 308224244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in4>; 308324244cefSSai Prakash Ranjan }; 308424244cefSSai Prakash Ranjan }; 308524244cefSSai Prakash Ranjan }; 308624244cefSSai Prakash Ranjan }; 308724244cefSSai Prakash Ranjan 308824244cefSSai Prakash Ranjan etm@7540000 { 308924244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 309024244cefSSai Prakash Ranjan reg = <0 0x07540000 0 0x1000>; 309124244cefSSai Prakash Ranjan 309224244cefSSai Prakash Ranjan cpu = <&CPU5>; 309324244cefSSai Prakash Ranjan 309424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 309524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 309624244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 309724244cefSSai Prakash Ranjan qcom,skip-power-up; 309824244cefSSai Prakash Ranjan 309924244cefSSai Prakash Ranjan out-ports { 310024244cefSSai Prakash Ranjan port { 310124244cefSSai Prakash Ranjan etm5_out: endpoint { 310224244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in5>; 310324244cefSSai Prakash Ranjan }; 310424244cefSSai Prakash Ranjan }; 310524244cefSSai Prakash Ranjan }; 310624244cefSSai Prakash Ranjan }; 310724244cefSSai Prakash Ranjan 310824244cefSSai Prakash Ranjan etm@7640000 { 310924244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 311024244cefSSai Prakash Ranjan reg = <0 0x07640000 0 0x1000>; 311124244cefSSai Prakash Ranjan 311224244cefSSai Prakash Ranjan cpu = <&CPU6>; 311324244cefSSai Prakash Ranjan 311424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 311524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 311624244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 311724244cefSSai Prakash Ranjan qcom,skip-power-up; 311824244cefSSai Prakash Ranjan 311924244cefSSai Prakash Ranjan out-ports { 312024244cefSSai Prakash Ranjan port { 312124244cefSSai Prakash Ranjan etm6_out: endpoint { 312224244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in6>; 312324244cefSSai Prakash Ranjan }; 312424244cefSSai Prakash Ranjan }; 312524244cefSSai Prakash Ranjan }; 312624244cefSSai Prakash Ranjan }; 312724244cefSSai Prakash Ranjan 312824244cefSSai Prakash Ranjan etm@7740000 { 312924244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 313024244cefSSai Prakash Ranjan reg = <0 0x07740000 0 0x1000>; 313124244cefSSai Prakash Ranjan 313224244cefSSai Prakash Ranjan cpu = <&CPU7>; 313324244cefSSai Prakash Ranjan 313424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 313524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 313624244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 313724244cefSSai Prakash Ranjan qcom,skip-power-up; 313824244cefSSai Prakash Ranjan 313924244cefSSai Prakash Ranjan out-ports { 314024244cefSSai Prakash Ranjan port { 314124244cefSSai Prakash Ranjan etm7_out: endpoint { 314224244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in7>; 314324244cefSSai Prakash Ranjan }; 314424244cefSSai Prakash Ranjan }; 314524244cefSSai Prakash Ranjan }; 314624244cefSSai Prakash Ranjan }; 314724244cefSSai Prakash Ranjan 314824244cefSSai Prakash Ranjan funnel@7800000 { /* APSS Funnel */ 314924244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 315024244cefSSai Prakash Ranjan reg = <0 0x07800000 0 0x1000>; 315124244cefSSai Prakash Ranjan 315224244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 315324244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 315424244cefSSai Prakash Ranjan 315524244cefSSai Prakash Ranjan out-ports { 315624244cefSSai Prakash Ranjan port { 315724244cefSSai Prakash Ranjan apss_funnel_out: endpoint { 315824244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_in>; 315924244cefSSai Prakash Ranjan }; 316024244cefSSai Prakash Ranjan }; 316124244cefSSai Prakash Ranjan }; 316224244cefSSai Prakash Ranjan 316324244cefSSai Prakash Ranjan in-ports { 316424244cefSSai Prakash Ranjan #address-cells = <1>; 316524244cefSSai Prakash Ranjan #size-cells = <0>; 316624244cefSSai Prakash Ranjan 316724244cefSSai Prakash Ranjan port@0 { 316824244cefSSai Prakash Ranjan reg = <0>; 316924244cefSSai Prakash Ranjan apss_funnel_in0: endpoint { 317024244cefSSai Prakash Ranjan remote-endpoint = <&etm0_out>; 317124244cefSSai Prakash Ranjan }; 317224244cefSSai Prakash Ranjan }; 317324244cefSSai Prakash Ranjan 317424244cefSSai Prakash Ranjan port@1 { 317524244cefSSai Prakash Ranjan reg = <1>; 317624244cefSSai Prakash Ranjan apss_funnel_in1: endpoint { 317724244cefSSai Prakash Ranjan remote-endpoint = <&etm1_out>; 317824244cefSSai Prakash Ranjan }; 317924244cefSSai Prakash Ranjan }; 318024244cefSSai Prakash Ranjan 318124244cefSSai Prakash Ranjan port@2 { 318224244cefSSai Prakash Ranjan reg = <2>; 318324244cefSSai Prakash Ranjan apss_funnel_in2: endpoint { 318424244cefSSai Prakash Ranjan remote-endpoint = <&etm2_out>; 318524244cefSSai Prakash Ranjan }; 318624244cefSSai Prakash Ranjan }; 318724244cefSSai Prakash Ranjan 318824244cefSSai Prakash Ranjan port@3 { 318924244cefSSai Prakash Ranjan reg = <3>; 319024244cefSSai Prakash Ranjan apss_funnel_in3: endpoint { 319124244cefSSai Prakash Ranjan remote-endpoint = <&etm3_out>; 319224244cefSSai Prakash Ranjan }; 319324244cefSSai Prakash Ranjan }; 319424244cefSSai Prakash Ranjan 319524244cefSSai Prakash Ranjan port@4 { 319624244cefSSai Prakash Ranjan reg = <4>; 319724244cefSSai Prakash Ranjan apss_funnel_in4: endpoint { 319824244cefSSai Prakash Ranjan remote-endpoint = <&etm4_out>; 319924244cefSSai Prakash Ranjan }; 320024244cefSSai Prakash Ranjan }; 320124244cefSSai Prakash Ranjan 320224244cefSSai Prakash Ranjan port@5 { 320324244cefSSai Prakash Ranjan reg = <5>; 320424244cefSSai Prakash Ranjan apss_funnel_in5: endpoint { 320524244cefSSai Prakash Ranjan remote-endpoint = <&etm5_out>; 320624244cefSSai Prakash Ranjan }; 320724244cefSSai Prakash Ranjan }; 320824244cefSSai Prakash Ranjan 320924244cefSSai Prakash Ranjan port@6 { 321024244cefSSai Prakash Ranjan reg = <6>; 321124244cefSSai Prakash Ranjan apss_funnel_in6: endpoint { 321224244cefSSai Prakash Ranjan remote-endpoint = <&etm6_out>; 321324244cefSSai Prakash Ranjan }; 321424244cefSSai Prakash Ranjan }; 321524244cefSSai Prakash Ranjan 321624244cefSSai Prakash Ranjan port@7 { 321724244cefSSai Prakash Ranjan reg = <7>; 321824244cefSSai Prakash Ranjan apss_funnel_in7: endpoint { 321924244cefSSai Prakash Ranjan remote-endpoint = <&etm7_out>; 322024244cefSSai Prakash Ranjan }; 322124244cefSSai Prakash Ranjan }; 322224244cefSSai Prakash Ranjan }; 322324244cefSSai Prakash Ranjan }; 322424244cefSSai Prakash Ranjan 322524244cefSSai Prakash Ranjan funnel@7810000 { 322624244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 322724244cefSSai Prakash Ranjan reg = <0 0x07810000 0 0x1000>; 322824244cefSSai Prakash Ranjan 322924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 323024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 323124244cefSSai Prakash Ranjan 323224244cefSSai Prakash Ranjan out-ports { 323324244cefSSai Prakash Ranjan port { 323424244cefSSai Prakash Ranjan apss_merge_funnel_out: endpoint { 323524244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_in2>; 323624244cefSSai Prakash Ranjan }; 323724244cefSSai Prakash Ranjan }; 323824244cefSSai Prakash Ranjan }; 323924244cefSSai Prakash Ranjan 324024244cefSSai Prakash Ranjan in-ports { 324124244cefSSai Prakash Ranjan port { 324224244cefSSai Prakash Ranjan apss_merge_funnel_in: endpoint { 324324244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_out>; 324424244cefSSai Prakash Ranjan }; 324524244cefSSai Prakash Ranjan }; 324624244cefSSai Prakash Ranjan }; 324724244cefSSai Prakash Ranjan }; 324824244cefSSai Prakash Ranjan 324949076351SSibi Sankar remoteproc_cdsp: remoteproc@8300000 { 325049076351SSibi Sankar compatible = "qcom,sm8150-cdsp-pas"; 325149076351SSibi Sankar reg = <0x0 0x08300000 0x0 0x4040>; 325249076351SSibi Sankar 325349076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 325449076351SSibi Sankar <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 325549076351SSibi Sankar <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 325649076351SSibi Sankar <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 325749076351SSibi Sankar <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 325849076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 325949076351SSibi Sankar "handover", "stop-ack"; 326049076351SSibi Sankar 326149076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 326249076351SSibi Sankar clock-names = "xo"; 326349076351SSibi Sankar 3264a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_CX>; 326549076351SSibi Sankar 326649076351SSibi Sankar memory-region = <&cdsp_mem>; 326749076351SSibi Sankar 3268d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 3269d9d327f6SSibi Sankar 327049076351SSibi Sankar qcom,smem-states = <&cdsp_smp2p_out 0>; 327149076351SSibi Sankar qcom,smem-state-names = "stop"; 327249076351SSibi Sankar 327349076351SSibi Sankar status = "disabled"; 327449076351SSibi Sankar 327549076351SSibi Sankar glink-edge { 327649076351SSibi Sankar interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 327749076351SSibi Sankar label = "cdsp"; 327849076351SSibi Sankar qcom,remote-pid = <5>; 327949076351SSibi Sankar mboxes = <&apss_shared 4>; 328081729330SBhupesh Sharma 328181729330SBhupesh Sharma fastrpc { 328281729330SBhupesh Sharma compatible = "qcom,fastrpc"; 328381729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 328481729330SBhupesh Sharma label = "cdsp"; 32858c8ce95bSJeya R qcom,non-secure-domain; 328681729330SBhupesh Sharma #address-cells = <1>; 328781729330SBhupesh Sharma #size-cells = <0>; 328881729330SBhupesh Sharma 328981729330SBhupesh Sharma compute-cb@1 { 329081729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 329181729330SBhupesh Sharma reg = <1>; 32921d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1001 0x0460>; 329381729330SBhupesh Sharma }; 329481729330SBhupesh Sharma 329581729330SBhupesh Sharma compute-cb@2 { 329681729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 329781729330SBhupesh Sharma reg = <2>; 32981d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1002 0x0460>; 329981729330SBhupesh Sharma }; 330081729330SBhupesh Sharma 330181729330SBhupesh Sharma compute-cb@3 { 330281729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 330381729330SBhupesh Sharma reg = <3>; 33041d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1003 0x0460>; 330581729330SBhupesh Sharma }; 330681729330SBhupesh Sharma 330781729330SBhupesh Sharma compute-cb@4 { 330881729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 330981729330SBhupesh Sharma reg = <4>; 33101d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1004 0x0460>; 331181729330SBhupesh Sharma }; 331281729330SBhupesh Sharma 331381729330SBhupesh Sharma compute-cb@5 { 331481729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 331581729330SBhupesh Sharma reg = <5>; 33161d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1005 0x0460>; 331781729330SBhupesh Sharma }; 331881729330SBhupesh Sharma 331981729330SBhupesh Sharma compute-cb@6 { 332081729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 332181729330SBhupesh Sharma reg = <6>; 33221d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1006 0x0460>; 332381729330SBhupesh Sharma }; 332481729330SBhupesh Sharma 332581729330SBhupesh Sharma compute-cb@7 { 332681729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 332781729330SBhupesh Sharma reg = <7>; 33281d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1007 0x0460>; 332981729330SBhupesh Sharma }; 333081729330SBhupesh Sharma 333181729330SBhupesh Sharma compute-cb@8 { 333281729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 333381729330SBhupesh Sharma reg = <8>; 33341d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1008 0x0460>; 333581729330SBhupesh Sharma }; 333681729330SBhupesh Sharma 333781729330SBhupesh Sharma /* note: secure cb9 in downstream */ 333881729330SBhupesh Sharma }; 333949076351SSibi Sankar }; 334049076351SSibi Sankar }; 334149076351SSibi Sankar 3342b33d2868SJack Pham usb_1_hsphy: phy@88e2000 { 3343b33d2868SJack Pham compatible = "qcom,sm8150-usb-hs-phy", 3344b33d2868SJack Pham "qcom,usb-snps-hs-7nm-phy"; 3345b33d2868SJack Pham reg = <0 0x088e2000 0 0x400>; 3346b33d2868SJack Pham status = "disabled"; 3347b33d2868SJack Pham #phy-cells = <0>; 3348b33d2868SJack Pham 3349b33d2868SJack Pham clocks = <&rpmhcc RPMH_CXO_CLK>; 3350b33d2868SJack Pham clock-names = "ref"; 3351b33d2868SJack Pham 3352b33d2868SJack Pham resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3353b33d2868SJack Pham }; 3354b33d2868SJack Pham 33550c9dde0dSJonathan Marek usb_2_hsphy: phy@88e3000 { 33560c9dde0dSJonathan Marek compatible = "qcom,sm8150-usb-hs-phy", 33570c9dde0dSJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 33580c9dde0dSJonathan Marek reg = <0 0x088e3000 0 0x400>; 33590c9dde0dSJonathan Marek status = "disabled"; 33600c9dde0dSJonathan Marek #phy-cells = <0>; 33610c9dde0dSJonathan Marek 33620c9dde0dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 33630c9dde0dSJonathan Marek clock-names = "ref"; 33640c9dde0dSJonathan Marek 33650c9dde0dSJonathan Marek resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 33660c9dde0dSJonathan Marek }; 33670c9dde0dSJonathan Marek 3368b33d2868SJack Pham usb_1_qmpphy: phy@88e9000 { 3369b33d2868SJack Pham compatible = "qcom,sm8150-qmp-usb3-phy"; 3370b33d2868SJack Pham reg = <0 0x088e9000 0 0x18c>, 3371b33d2868SJack Pham <0 0x088e8000 0 0x10>; 3372b33d2868SJack Pham status = "disabled"; 3373b33d2868SJack Pham #address-cells = <2>; 3374b33d2868SJack Pham #size-cells = <2>; 3375b33d2868SJack Pham ranges; 3376b33d2868SJack Pham 3377b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3378b33d2868SJack Pham <&rpmhcc RPMH_CXO_CLK>, 3379b33d2868SJack Pham <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3380b33d2868SJack Pham <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3381b33d2868SJack Pham clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3382b33d2868SJack Pham 3383b33d2868SJack Pham resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3384b33d2868SJack Pham <&gcc GCC_USB3_PHY_PRIM_BCR>; 3385b33d2868SJack Pham reset-names = "phy", "common"; 3386b33d2868SJack Pham 33871351512fSShawn Guo usb_1_ssphy: phy@88e9200 { 3388b33d2868SJack Pham reg = <0 0x088e9200 0 0x200>, 3389b33d2868SJack Pham <0 0x088e9400 0 0x200>, 3390b33d2868SJack Pham <0 0x088e9c00 0 0x218>, 3391b33d2868SJack Pham <0 0x088e9600 0 0x200>, 3392b33d2868SJack Pham <0 0x088e9800 0 0x200>, 3393b33d2868SJack Pham <0 0x088e9a00 0 0x100>; 33947178d4ccSJonathan Marek #clock-cells = <0>; 3395b33d2868SJack Pham #phy-cells = <0>; 3396b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3397b33d2868SJack Pham clock-names = "pipe0"; 3398b33d2868SJack Pham clock-output-names = "usb3_phy_pipe_clk_src"; 3399b33d2868SJack Pham }; 3400b33d2868SJack Pham }; 3401b33d2868SJack Pham 34020c9dde0dSJonathan Marek usb_2_qmpphy: phy@88eb000 { 34030c9dde0dSJonathan Marek compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 34040c9dde0dSJonathan Marek reg = <0 0x088eb000 0 0x200>; 34050c9dde0dSJonathan Marek status = "disabled"; 34060c9dde0dSJonathan Marek #address-cells = <2>; 34070c9dde0dSJonathan Marek #size-cells = <2>; 34080c9dde0dSJonathan Marek ranges; 34090c9dde0dSJonathan Marek 34100c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 34110c9dde0dSJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 34120c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>, 34130c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 34140c9dde0dSJonathan Marek clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 34150c9dde0dSJonathan Marek 34160c9dde0dSJonathan Marek resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 34170c9dde0dSJonathan Marek <&gcc GCC_USB3_PHY_SEC_BCR>; 34180c9dde0dSJonathan Marek reset-names = "phy", "common"; 34190c9dde0dSJonathan Marek 34201351512fSShawn Guo usb_2_ssphy: phy@88eb200 { 34210c9dde0dSJonathan Marek reg = <0 0x088eb200 0 0x200>, 34220c9dde0dSJonathan Marek <0 0x088eb400 0 0x200>, 34230c9dde0dSJonathan Marek <0 0x088eb800 0 0x800>, 34240c9dde0dSJonathan Marek <0 0x088eb600 0 0x200>; 34257178d4ccSJonathan Marek #clock-cells = <0>; 34260c9dde0dSJonathan Marek #phy-cells = <0>; 34270c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 34280c9dde0dSJonathan Marek clock-names = "pipe0"; 34290c9dde0dSJonathan Marek clock-output-names = "usb3_uni_phy_pipe_clk_src"; 34300c9dde0dSJonathan Marek }; 34310c9dde0dSJonathan Marek }; 34320c9dde0dSJonathan Marek 343396bb736fSBhupesh Sharma sdhc_2: mmc@8804000 { 3434876644c7SBhupesh Sharma compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3435876644c7SBhupesh Sharma reg = <0 0x08804000 0 0x1000>; 3436876644c7SBhupesh Sharma 3437876644c7SBhupesh Sharma interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3438876644c7SBhupesh Sharma <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3439876644c7SBhupesh Sharma interrupt-names = "hc_irq", "pwr_irq"; 3440876644c7SBhupesh Sharma 3441876644c7SBhupesh Sharma clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3442876644c7SBhupesh Sharma <&gcc GCC_SDCC2_APPS_CLK>, 3443876644c7SBhupesh Sharma <&rpmhcc RPMH_CXO_CLK>; 3444876644c7SBhupesh Sharma clock-names = "iface", "core", "xo"; 344595830090SBhupesh Sharma iommus = <&apps_smmu 0x6a0 0x0>; 3446876644c7SBhupesh Sharma qcom,dll-config = <0x0007642c>; 3447876644c7SBhupesh Sharma qcom,ddr-config = <0x80040868>; 3448876644c7SBhupesh Sharma power-domains = <&rpmhpd 0>; 3449876644c7SBhupesh Sharma operating-points-v2 = <&sdhc2_opp_table>; 3450876644c7SBhupesh Sharma 3451876644c7SBhupesh Sharma status = "disabled"; 3452876644c7SBhupesh Sharma 34530e3e6546SKrzysztof Kozlowski sdhc2_opp_table: opp-table { 3454876644c7SBhupesh Sharma compatible = "operating-points-v2"; 3455876644c7SBhupesh Sharma 3456876644c7SBhupesh Sharma opp-19200000 { 3457876644c7SBhupesh Sharma opp-hz = /bits/ 64 <19200000>; 3458876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_min_svs>; 3459876644c7SBhupesh Sharma }; 3460876644c7SBhupesh Sharma 3461876644c7SBhupesh Sharma opp-50000000 { 3462876644c7SBhupesh Sharma opp-hz = /bits/ 64 <50000000>; 3463876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_low_svs>; 3464876644c7SBhupesh Sharma }; 3465876644c7SBhupesh Sharma 3466876644c7SBhupesh Sharma opp-100000000 { 3467876644c7SBhupesh Sharma opp-hz = /bits/ 64 <100000000>; 3468876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_svs>; 3469876644c7SBhupesh Sharma }; 3470876644c7SBhupesh Sharma 3471876644c7SBhupesh Sharma opp-202000000 { 3472876644c7SBhupesh Sharma opp-hz = /bits/ 64 <202000000>; 3473876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_svs_l1>; 3474876644c7SBhupesh Sharma }; 3475876644c7SBhupesh Sharma }; 3476876644c7SBhupesh Sharma }; 3477876644c7SBhupesh Sharma 34785dc43d3bSBhupesh Sharma dc_noc: interconnect@9160000 { 34795dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-dc-noc"; 34805dc43d3bSBhupesh Sharma reg = <0 0x09160000 0 0x3200>; 34815dc43d3bSBhupesh Sharma #interconnect-cells = <1>; 34825dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 34835dc43d3bSBhupesh Sharma }; 34845dc43d3bSBhupesh Sharma 34855dc43d3bSBhupesh Sharma gem_noc: interconnect@9680000 { 34865dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-gem-noc"; 34875dc43d3bSBhupesh Sharma reg = <0 0x09680000 0 0x3e200>; 34885dc43d3bSBhupesh Sharma #interconnect-cells = <1>; 34895dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 34905dc43d3bSBhupesh Sharma }; 34915dc43d3bSBhupesh Sharma 3492b33d2868SJack Pham usb_1: usb@a6f8800 { 3493b33d2868SJack Pham compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3494b33d2868SJack Pham reg = <0 0x0a6f8800 0 0x400>; 3495b33d2868SJack Pham status = "disabled"; 3496b33d2868SJack Pham #address-cells = <2>; 3497b33d2868SJack Pham #size-cells = <2>; 3498b33d2868SJack Pham ranges; 3499b33d2868SJack Pham dma-ranges; 3500b33d2868SJack Pham 3501b33d2868SJack Pham clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3502b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3503b33d2868SJack Pham <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3504b33d2868SJack Pham <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 35058d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3506b33d2868SJack Pham <&gcc GCC_USB3_SEC_CLKREF_CLK>; 35078d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 35088d5fd4e4SKrzysztof Kozlowski "core", 35098d5fd4e4SKrzysztof Kozlowski "iface", 35108d5fd4e4SKrzysztof Kozlowski "sleep", 35118d5fd4e4SKrzysztof Kozlowski "mock_utmi", 35128d5fd4e4SKrzysztof Kozlowski "xo"; 3513b33d2868SJack Pham 3514b33d2868SJack Pham assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3515b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>; 351679493db5SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 3517b33d2868SJack Pham 3518b33d2868SJack Pham interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3519b33d2868SJack Pham <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3520b33d2868SJack Pham <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3521b33d2868SJack Pham <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3522b33d2868SJack Pham interrupt-names = "hs_phy_irq", "ss_phy_irq", 3523b33d2868SJack Pham "dm_hs_phy_irq", "dp_hs_phy_irq"; 3524b33d2868SJack Pham 3525b33d2868SJack Pham power-domains = <&gcc USB30_PRIM_GDSC>; 3526b33d2868SJack Pham 3527b33d2868SJack Pham resets = <&gcc GCC_USB30_PRIM_BCR>; 3528b33d2868SJack Pham 3529b77a1c4dSKrzysztof Kozlowski usb_1_dwc3: usb@a600000 { 3530b33d2868SJack Pham compatible = "snps,dwc3"; 3531b33d2868SJack Pham reg = <0 0x0a600000 0 0xcd00>; 3532b33d2868SJack Pham interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 353348156232SJonathan Marek iommus = <&apps_smmu 0x140 0>; 3534b33d2868SJack Pham snps,dis_u2_susphy_quirk; 3535b33d2868SJack Pham snps,dis_enblslpm_quirk; 3536b33d2868SJack Pham phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3537b33d2868SJack Pham phy-names = "usb2-phy", "usb3-phy"; 3538b33d2868SJack Pham }; 3539b33d2868SJack Pham }; 3540b33d2868SJack Pham 35410c9dde0dSJonathan Marek usb_2: usb@a8f8800 { 35420c9dde0dSJonathan Marek compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 35430c9dde0dSJonathan Marek reg = <0 0x0a8f8800 0 0x400>; 35440c9dde0dSJonathan Marek status = "disabled"; 35450c9dde0dSJonathan Marek #address-cells = <2>; 35460c9dde0dSJonathan Marek #size-cells = <2>; 35470c9dde0dSJonathan Marek ranges; 35480c9dde0dSJonathan Marek dma-ranges; 35490c9dde0dSJonathan Marek 35500c9dde0dSJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 35510c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>, 35520c9dde0dSJonathan Marek <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 35530c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_SLEEP_CLK>, 35548d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 35550c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>; 35568d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 35578d5fd4e4SKrzysztof Kozlowski "core", 35588d5fd4e4SKrzysztof Kozlowski "iface", 35598d5fd4e4SKrzysztof Kozlowski "sleep", 35608d5fd4e4SKrzysztof Kozlowski "mock_utmi", 35618d5fd4e4SKrzysztof Kozlowski "xo"; 35620c9dde0dSJonathan Marek 35630c9dde0dSJonathan Marek assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 35640c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>; 35650c9dde0dSJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 35660c9dde0dSJonathan Marek 35670c9dde0dSJonathan Marek interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 35680c9dde0dSJonathan Marek <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 35690c9dde0dSJonathan Marek <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 35700c9dde0dSJonathan Marek <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 35710c9dde0dSJonathan Marek interrupt-names = "hs_phy_irq", "ss_phy_irq", 35720c9dde0dSJonathan Marek "dm_hs_phy_irq", "dp_hs_phy_irq"; 35730c9dde0dSJonathan Marek 35740c9dde0dSJonathan Marek power-domains = <&gcc USB30_SEC_GDSC>; 35750c9dde0dSJonathan Marek 35760c9dde0dSJonathan Marek resets = <&gcc GCC_USB30_SEC_BCR>; 35770c9dde0dSJonathan Marek 35782aa2b50dSBhupesh Sharma usb_2_dwc3: usb@a800000 { 35790c9dde0dSJonathan Marek compatible = "snps,dwc3"; 35800c9dde0dSJonathan Marek reg = <0 0x0a800000 0 0xcd00>; 35810c9dde0dSJonathan Marek interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 35820c9dde0dSJonathan Marek iommus = <&apps_smmu 0x160 0>; 35830c9dde0dSJonathan Marek snps,dis_u2_susphy_quirk; 35840c9dde0dSJonathan Marek snps,dis_enblslpm_quirk; 35850c9dde0dSJonathan Marek phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 35860c9dde0dSJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 35870c9dde0dSJonathan Marek }; 35880c9dde0dSJonathan Marek }; 35890c9dde0dSJonathan Marek 35906acb71fdSJonathan Marek camnoc_virt: interconnect@ac00000 { 35916acb71fdSJonathan Marek compatible = "qcom,sm8150-camnoc-virt"; 35926acb71fdSJonathan Marek reg = <0 0x0ac00000 0 0x1000>; 35936acb71fdSJonathan Marek #interconnect-cells = <1>; 35946acb71fdSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 35956acb71fdSJonathan Marek }; 35966acb71fdSJonathan Marek 3597397ad946SBhupesh Sharma pdc: interrupt-controller@b220000 { 3598397ad946SBhupesh Sharma compatible = "qcom,sm8150-pdc", "qcom,pdc"; 3599397ad946SBhupesh Sharma reg = <0 0x0b220000 0 0x400>; 3600397ad946SBhupesh Sharma qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3601397ad946SBhupesh Sharma <125 63 1>; 3602397ad946SBhupesh Sharma #interrupt-cells = <2>; 3603397ad946SBhupesh Sharma interrupt-parent = <&intc>; 3604397ad946SBhupesh Sharma interrupt-controller; 3605397ad946SBhupesh Sharma }; 3606397ad946SBhupesh Sharma 3607d8cf9372SVinod Koul aoss_qmp: power-controller@c300000 { 36086ba93ba9SKrzysztof Kozlowski compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 360947cb6a06SMaulik Shah reg = <0x0 0x0c300000 0x0 0x400>; 3610d8cf9372SVinod Koul interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3611d8cf9372SVinod Koul mboxes = <&apss_shared 0>; 3612d8cf9372SVinod Koul 3613d8cf9372SVinod Koul #clock-cells = <0>; 3614d8cf9372SVinod Koul }; 3615d8cf9372SVinod Koul 361647cb6a06SMaulik Shah sram@c3f0000 { 361747cb6a06SMaulik Shah compatible = "qcom,rpmh-stats"; 361847cb6a06SMaulik Shah reg = <0 0x0c3f0000 0 0x400>; 361947cb6a06SMaulik Shah }; 362047cb6a06SMaulik Shah 3621d2fa630cSAmit Kucheria tsens0: thermal-sensor@c263000 { 3622d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3623d2fa630cSAmit Kucheria reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3624d2fa630cSAmit Kucheria <0 0x0c222000 0 0x1ff>; /* SROT */ 3625d2fa630cSAmit Kucheria #qcom,sensors = <16>; 3626d2fa630cSAmit Kucheria interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3627d2fa630cSAmit Kucheria <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3628d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 3629d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 3630d2fa630cSAmit Kucheria }; 3631d2fa630cSAmit Kucheria 3632d2fa630cSAmit Kucheria tsens1: thermal-sensor@c265000 { 3633d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3634d2fa630cSAmit Kucheria reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3635d2fa630cSAmit Kucheria <0 0x0c223000 0 0x1ff>; /* SROT */ 3636d2fa630cSAmit Kucheria #qcom,sensors = <8>; 3637d2fa630cSAmit Kucheria interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3638d2fa630cSAmit Kucheria <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3639d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 3640d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 3641d2fa630cSAmit Kucheria }; 3642d2fa630cSAmit Kucheria 3643e13c6d14SVinod Koul spmi_bus: spmi@c440000 { 3644e13c6d14SVinod Koul compatible = "qcom,spmi-pmic-arb"; 3645e13c6d14SVinod Koul reg = <0x0 0x0c440000 0x0 0x0001100>, 3646e13c6d14SVinod Koul <0x0 0x0c600000 0x0 0x2000000>, 3647e13c6d14SVinod Koul <0x0 0x0e600000 0x0 0x0100000>, 3648e13c6d14SVinod Koul <0x0 0x0e700000 0x0 0x00a0000>, 3649e13c6d14SVinod Koul <0x0 0x0c40a000 0x0 0x0026000>; 3650e13c6d14SVinod Koul reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3651e13c6d14SVinod Koul interrupt-names = "periph_irq"; 3652e13c6d14SVinod Koul interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3653e13c6d14SVinod Koul qcom,ee = <0>; 3654e13c6d14SVinod Koul qcom,channel = <0>; 3655e13c6d14SVinod Koul #address-cells = <2>; 3656e13c6d14SVinod Koul #size-cells = <0>; 3657e13c6d14SVinod Koul interrupt-controller; 3658e13c6d14SVinod Koul #interrupt-cells = <4>; 3659e13c6d14SVinod Koul cell-index = <0>; 3660e13c6d14SVinod Koul }; 3661e13c6d14SVinod Koul 366248156232SJonathan Marek apps_smmu: iommu@15000000 { 366348156232SJonathan Marek compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 366448156232SJonathan Marek reg = <0 0x15000000 0 0x100000>; 366548156232SJonathan Marek #iommu-cells = <2>; 366648156232SJonathan Marek #global-interrupts = <1>; 366748156232SJonathan Marek interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 366848156232SJonathan Marek <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 366948156232SJonathan Marek <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 367048156232SJonathan Marek <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 367148156232SJonathan Marek <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 367248156232SJonathan Marek <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 367348156232SJonathan Marek <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 367448156232SJonathan Marek <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 367548156232SJonathan Marek <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 367648156232SJonathan Marek <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 367748156232SJonathan Marek <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 367848156232SJonathan Marek <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 367948156232SJonathan Marek <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 368048156232SJonathan Marek <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 368148156232SJonathan Marek <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 368248156232SJonathan Marek <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 368348156232SJonathan Marek <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 368448156232SJonathan Marek <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 368548156232SJonathan Marek <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 368648156232SJonathan Marek <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 368748156232SJonathan Marek <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 368848156232SJonathan Marek <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 368948156232SJonathan Marek <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 369048156232SJonathan Marek <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 369148156232SJonathan Marek <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 369248156232SJonathan Marek <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 369348156232SJonathan Marek <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 369448156232SJonathan Marek <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 369548156232SJonathan Marek <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 369648156232SJonathan Marek <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 369748156232SJonathan Marek <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 369848156232SJonathan Marek <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 369948156232SJonathan Marek <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 370048156232SJonathan Marek <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 370148156232SJonathan Marek <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 370248156232SJonathan Marek <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 370348156232SJonathan Marek <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 370448156232SJonathan Marek <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 370548156232SJonathan Marek <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 370648156232SJonathan Marek <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 370748156232SJonathan Marek <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 370848156232SJonathan Marek <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 370948156232SJonathan Marek <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 371048156232SJonathan Marek <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 371148156232SJonathan Marek <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 371248156232SJonathan Marek <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 371348156232SJonathan Marek <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 371448156232SJonathan Marek <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 371548156232SJonathan Marek <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 371648156232SJonathan Marek <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 371748156232SJonathan Marek <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 371848156232SJonathan Marek <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 371948156232SJonathan Marek <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 372048156232SJonathan Marek <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 372148156232SJonathan Marek <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 372248156232SJonathan Marek <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 372348156232SJonathan Marek <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 372448156232SJonathan Marek <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 372548156232SJonathan Marek <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 372648156232SJonathan Marek <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 372748156232SJonathan Marek <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 372848156232SJonathan Marek <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 372948156232SJonathan Marek <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 373048156232SJonathan Marek <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 373148156232SJonathan Marek <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 373248156232SJonathan Marek <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 373348156232SJonathan Marek <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 373448156232SJonathan Marek <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 373548156232SJonathan Marek <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 373648156232SJonathan Marek <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 373748156232SJonathan Marek <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 373848156232SJonathan Marek <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 373948156232SJonathan Marek <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 374048156232SJonathan Marek <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 374148156232SJonathan Marek <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 374248156232SJonathan Marek <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 374348156232SJonathan Marek <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 374448156232SJonathan Marek <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 374548156232SJonathan Marek <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 374648156232SJonathan Marek <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 374748156232SJonathan Marek <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 374848156232SJonathan Marek }; 374948156232SJonathan Marek 375049076351SSibi Sankar remoteproc_adsp: remoteproc@17300000 { 375149076351SSibi Sankar compatible = "qcom,sm8150-adsp-pas"; 375249076351SSibi Sankar reg = <0x0 0x17300000 0x0 0x4040>; 375349076351SSibi Sankar 375449076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 375549076351SSibi Sankar <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 375649076351SSibi Sankar <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 375749076351SSibi Sankar <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 375849076351SSibi Sankar <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 375949076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 376049076351SSibi Sankar "handover", "stop-ack"; 376149076351SSibi Sankar 376249076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 376349076351SSibi Sankar clock-names = "xo"; 376449076351SSibi Sankar 3765a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_CX>; 376649076351SSibi Sankar 376749076351SSibi Sankar memory-region = <&adsp_mem>; 376849076351SSibi Sankar 3769d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 3770d9d327f6SSibi Sankar 377149076351SSibi Sankar qcom,smem-states = <&adsp_smp2p_out 0>; 377249076351SSibi Sankar qcom,smem-state-names = "stop"; 377349076351SSibi Sankar 377449076351SSibi Sankar status = "disabled"; 377549076351SSibi Sankar 377649076351SSibi Sankar glink-edge { 377749076351SSibi Sankar interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 377849076351SSibi Sankar label = "lpass"; 377949076351SSibi Sankar qcom,remote-pid = <2>; 378049076351SSibi Sankar mboxes = <&apss_shared 8>; 378181729330SBhupesh Sharma 378281729330SBhupesh Sharma fastrpc { 378381729330SBhupesh Sharma compatible = "qcom,fastrpc"; 378481729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 378581729330SBhupesh Sharma label = "adsp"; 37868c8ce95bSJeya R qcom,non-secure-domain; 378781729330SBhupesh Sharma #address-cells = <1>; 378881729330SBhupesh Sharma #size-cells = <0>; 378981729330SBhupesh Sharma 379081729330SBhupesh Sharma compute-cb@3 { 379181729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 379281729330SBhupesh Sharma reg = <3>; 379381729330SBhupesh Sharma iommus = <&apps_smmu 0x1b23 0x0>; 379481729330SBhupesh Sharma }; 379581729330SBhupesh Sharma 379681729330SBhupesh Sharma compute-cb@4 { 379781729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 379881729330SBhupesh Sharma reg = <4>; 379981729330SBhupesh Sharma iommus = <&apps_smmu 0x1b24 0x0>; 380081729330SBhupesh Sharma }; 380181729330SBhupesh Sharma 380281729330SBhupesh Sharma compute-cb@5 { 380381729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 380481729330SBhupesh Sharma reg = <5>; 380581729330SBhupesh Sharma iommus = <&apps_smmu 0x1b25 0x0>; 380681729330SBhupesh Sharma }; 380781729330SBhupesh Sharma }; 380849076351SSibi Sankar }; 380949076351SSibi Sankar }; 381049076351SSibi Sankar 3811e13c6d14SVinod Koul intc: interrupt-controller@17a00000 { 3812e13c6d14SVinod Koul compatible = "arm,gic-v3"; 3813e13c6d14SVinod Koul interrupt-controller; 3814e13c6d14SVinod Koul #interrupt-cells = <3>; 3815e13c6d14SVinod Koul reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3816e13c6d14SVinod Koul <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3817e13c6d14SVinod Koul interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3818e13c6d14SVinod Koul }; 3819e13c6d14SVinod Koul 3820d8cf9372SVinod Koul apss_shared: mailbox@17c00000 { 3821d8cf9372SVinod Koul compatible = "qcom,sm8150-apss-shared"; 3822d8cf9372SVinod Koul reg = <0x0 0x17c00000 0x0 0x1000>; 3823d8cf9372SVinod Koul #mbox-cells = <1>; 3824d8cf9372SVinod Koul }; 3825d8cf9372SVinod Koul 3826fb2d8150SSai Prakash Ranjan watchdog@17c10000 { 3827fb2d8150SSai Prakash Ranjan compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 3828fb2d8150SSai Prakash Ranjan reg = <0 0x17c10000 0 0x1000>; 3829fb2d8150SSai Prakash Ranjan clocks = <&sleep_clk>; 3830b094c8f8SSai Prakash Ranjan interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3831fb2d8150SSai Prakash Ranjan }; 3832fb2d8150SSai Prakash Ranjan 3833e13c6d14SVinod Koul timer@17c20000 { 3834458ebdbbSDavid Heidelberg #address-cells = <1>; 3835458ebdbbSDavid Heidelberg #size-cells = <1>; 3836458ebdbbSDavid Heidelberg ranges = <0 0 0 0x20000000>; 3837e13c6d14SVinod Koul compatible = "arm,armv7-timer-mem"; 3838e13c6d14SVinod Koul reg = <0x0 0x17c20000 0x0 0x1000>; 3839e13c6d14SVinod Koul clock-frequency = <19200000>; 3840e13c6d14SVinod Koul 3841e13c6d14SVinod Koul frame@17c21000{ 3842e13c6d14SVinod Koul frame-number = <0>; 3843e13c6d14SVinod Koul interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3844e13c6d14SVinod Koul <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3845458ebdbbSDavid Heidelberg reg = <0x17c21000 0x1000>, 3846458ebdbbSDavid Heidelberg <0x17c22000 0x1000>; 3847e13c6d14SVinod Koul }; 3848e13c6d14SVinod Koul 3849e13c6d14SVinod Koul frame@17c23000 { 3850e13c6d14SVinod Koul frame-number = <1>; 3851e13c6d14SVinod Koul interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3852458ebdbbSDavid Heidelberg reg = <0x17c23000 0x1000>; 3853e13c6d14SVinod Koul status = "disabled"; 3854e13c6d14SVinod Koul }; 3855e13c6d14SVinod Koul 3856e13c6d14SVinod Koul frame@17c25000 { 3857e13c6d14SVinod Koul frame-number = <2>; 3858e13c6d14SVinod Koul interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3859458ebdbbSDavid Heidelberg reg = <0x17c25000 0x1000>; 3860e13c6d14SVinod Koul status = "disabled"; 3861e13c6d14SVinod Koul }; 3862e13c6d14SVinod Koul 3863e13c6d14SVinod Koul frame@17c27000 { 3864e13c6d14SVinod Koul frame-number = <3>; 3865e13c6d14SVinod Koul interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3866458ebdbbSDavid Heidelberg reg = <0x17c26000 0x1000>; 3867e13c6d14SVinod Koul status = "disabled"; 3868e13c6d14SVinod Koul }; 3869e13c6d14SVinod Koul 3870e13c6d14SVinod Koul frame@17c29000 { 3871e13c6d14SVinod Koul frame-number = <4>; 3872e13c6d14SVinod Koul interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3873458ebdbbSDavid Heidelberg reg = <0x17c29000 0x1000>; 3874e13c6d14SVinod Koul status = "disabled"; 3875e13c6d14SVinod Koul }; 3876e13c6d14SVinod Koul 3877e13c6d14SVinod Koul frame@17c2b000 { 3878e13c6d14SVinod Koul frame-number = <5>; 3879e13c6d14SVinod Koul interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3880458ebdbbSDavid Heidelberg reg = <0x17c2b000 0x1000>; 3881e13c6d14SVinod Koul status = "disabled"; 3882e13c6d14SVinod Koul }; 3883e13c6d14SVinod Koul 3884e13c6d14SVinod Koul frame@17c2d000 { 3885e13c6d14SVinod Koul frame-number = <6>; 3886e13c6d14SVinod Koul interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3887458ebdbbSDavid Heidelberg reg = <0x17c2d000 0x1000>; 3888e13c6d14SVinod Koul status = "disabled"; 3889e13c6d14SVinod Koul }; 3890e13c6d14SVinod Koul }; 3891d8cf9372SVinod Koul 3892d8cf9372SVinod Koul apps_rsc: rsc@18200000 { 3893d8cf9372SVinod Koul label = "apps_rsc"; 3894d8cf9372SVinod Koul compatible = "qcom,rpmh-rsc"; 3895d8cf9372SVinod Koul reg = <0x0 0x18200000 0x0 0x10000>, 3896d8cf9372SVinod Koul <0x0 0x18210000 0x0 0x10000>, 3897d8cf9372SVinod Koul <0x0 0x18220000 0x0 0x10000>; 3898d8cf9372SVinod Koul reg-names = "drv-0", "drv-1", "drv-2"; 3899d8cf9372SVinod Koul interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3900d8cf9372SVinod Koul <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3901d8cf9372SVinod Koul <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3902d8cf9372SVinod Koul qcom,tcs-offset = <0xd00>; 3903d8cf9372SVinod Koul qcom,drv-id = <2>; 3904d8cf9372SVinod Koul qcom,tcs-config = <ACTIVE_TCS 2>, 390517ac8af6SMaulik Shah <SLEEP_TCS 3>, 390617ac8af6SMaulik Shah <WAKE_TCS 3>, 390717ac8af6SMaulik Shah <CONTROL_TCS 1>; 39082ffa0ca4SMaulik Shah power-domains = <&CLUSTER_PD>; 3909d8cf9372SVinod Koul 3910d8cf9372SVinod Koul rpmhcc: clock-controller { 3911d8cf9372SVinod Koul compatible = "qcom,sm8150-rpmh-clk"; 3912d8cf9372SVinod Koul #clock-cells = <1>; 3913d8cf9372SVinod Koul clock-names = "xo"; 3914d8cf9372SVinod Koul clocks = <&xo_board>; 3915d8cf9372SVinod Koul }; 3916017e7856SSibi Sankar 3917017e7856SSibi Sankar rpmhpd: power-controller { 3918017e7856SSibi Sankar compatible = "qcom,sm8150-rpmhpd"; 3919017e7856SSibi Sankar #power-domain-cells = <1>; 3920017e7856SSibi Sankar operating-points-v2 = <&rpmhpd_opp_table>; 3921017e7856SSibi Sankar 3922017e7856SSibi Sankar rpmhpd_opp_table: opp-table { 3923017e7856SSibi Sankar compatible = "operating-points-v2"; 3924017e7856SSibi Sankar 3925017e7856SSibi Sankar rpmhpd_opp_ret: opp1 { 3926017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3927017e7856SSibi Sankar }; 3928017e7856SSibi Sankar 3929017e7856SSibi Sankar rpmhpd_opp_min_svs: opp2 { 3930017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3931017e7856SSibi Sankar }; 3932017e7856SSibi Sankar 3933017e7856SSibi Sankar rpmhpd_opp_low_svs: opp3 { 3934017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3935017e7856SSibi Sankar }; 3936017e7856SSibi Sankar 3937017e7856SSibi Sankar rpmhpd_opp_svs: opp4 { 3938017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3939017e7856SSibi Sankar }; 3940017e7856SSibi Sankar 3941017e7856SSibi Sankar rpmhpd_opp_svs_l1: opp5 { 3942017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3943017e7856SSibi Sankar }; 3944017e7856SSibi Sankar 3945017e7856SSibi Sankar rpmhpd_opp_svs_l2: opp6 { 3946017e7856SSibi Sankar opp-level = <224>; 3947017e7856SSibi Sankar }; 3948017e7856SSibi Sankar 3949017e7856SSibi Sankar rpmhpd_opp_nom: opp7 { 3950017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3951017e7856SSibi Sankar }; 3952017e7856SSibi Sankar 3953017e7856SSibi Sankar rpmhpd_opp_nom_l1: opp8 { 3954017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3955017e7856SSibi Sankar }; 3956017e7856SSibi Sankar 3957017e7856SSibi Sankar rpmhpd_opp_nom_l2: opp9 { 3958017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3959017e7856SSibi Sankar }; 3960017e7856SSibi Sankar 3961017e7856SSibi Sankar rpmhpd_opp_turbo: opp10 { 3962017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3963017e7856SSibi Sankar }; 3964017e7856SSibi Sankar 3965017e7856SSibi Sankar rpmhpd_opp_turbo_l1: opp11 { 3966017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3967017e7856SSibi Sankar }; 3968017e7856SSibi Sankar }; 3969017e7856SSibi Sankar }; 397071a2fc6eSJonathan Marek 3971fc0e7dd6SKrzysztof Kozlowski apps_bcm_voter: bcm-voter { 397271a2fc6eSJonathan Marek compatible = "qcom,bcm-voter"; 397371a2fc6eSJonathan Marek }; 3974d8cf9372SVinod Koul }; 3975fea8930bSSibi Sankar 3976a6d435c1SSibi Sankar osm_l3: interconnect@18321000 { 3977a0289a10SBjorn Andersson compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3"; 3978a6d435c1SSibi Sankar reg = <0 0x18321000 0 0x1400>; 3979a6d435c1SSibi Sankar 3980a6d435c1SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3981a6d435c1SSibi Sankar clock-names = "xo", "alternate"; 3982a6d435c1SSibi Sankar 3983a6d435c1SSibi Sankar #interconnect-cells = <1>; 3984a6d435c1SSibi Sankar }; 3985a6d435c1SSibi Sankar 3986fea8930bSSibi Sankar cpufreq_hw: cpufreq@18323000 { 3987fea8930bSSibi Sankar compatible = "qcom,cpufreq-hw"; 3988fea8930bSSibi Sankar reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 3989fea8930bSSibi Sankar <0 0x18327800 0 0x1400>; 3990fea8930bSSibi Sankar reg-names = "freq-domain0", "freq-domain1", 3991fea8930bSSibi Sankar "freq-domain2"; 3992fea8930bSSibi Sankar 3993fea8930bSSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3994fea8930bSSibi Sankar clock-names = "xo", "alternate"; 3995fea8930bSSibi Sankar 3996fea8930bSSibi Sankar #freq-domain-cells = <1>; 3997fea8930bSSibi Sankar }; 399805090bb9SJonathan Marek 39992ffcfe79SThara Gopinath lmh_cluster1: lmh@18350800 { 40002ffcfe79SThara Gopinath compatible = "qcom,sm8150-lmh"; 40012ffcfe79SThara Gopinath reg = <0 0x18350800 0 0x400>; 40022ffcfe79SThara Gopinath interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 40032ffcfe79SThara Gopinath cpus = <&CPU4>; 40042ffcfe79SThara Gopinath qcom,lmh-temp-arm-millicelsius = <60000>; 40052ffcfe79SThara Gopinath qcom,lmh-temp-low-millicelsius = <84500>; 40062ffcfe79SThara Gopinath qcom,lmh-temp-high-millicelsius = <85000>; 40072ffcfe79SThara Gopinath interrupt-controller; 40082ffcfe79SThara Gopinath #interrupt-cells = <1>; 40092ffcfe79SThara Gopinath }; 40102ffcfe79SThara Gopinath 40112ffcfe79SThara Gopinath lmh_cluster0: lmh@18358800 { 40122ffcfe79SThara Gopinath compatible = "qcom,sm8150-lmh"; 40132ffcfe79SThara Gopinath reg = <0 0x18358800 0 0x400>; 40142ffcfe79SThara Gopinath interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 40152ffcfe79SThara Gopinath cpus = <&CPU0>; 40162ffcfe79SThara Gopinath qcom,lmh-temp-arm-millicelsius = <60000>; 40172ffcfe79SThara Gopinath qcom,lmh-temp-low-millicelsius = <84500>; 40182ffcfe79SThara Gopinath qcom,lmh-temp-high-millicelsius = <85000>; 40192ffcfe79SThara Gopinath interrupt-controller; 40202ffcfe79SThara Gopinath #interrupt-cells = <1>; 40212ffcfe79SThara Gopinath }; 40222ffcfe79SThara Gopinath 402305090bb9SJonathan Marek wifi: wifi@18800000 { 402405090bb9SJonathan Marek compatible = "qcom,wcn3990-wifi"; 402505090bb9SJonathan Marek reg = <0 0x18800000 0 0x800000>; 402605090bb9SJonathan Marek reg-names = "membase"; 402705090bb9SJonathan Marek memory-region = <&wlan_mem>; 402805090bb9SJonathan Marek clock-names = "cxo_ref_clk_pin", "qdss"; 402905090bb9SJonathan Marek clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 403005090bb9SJonathan Marek interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 403105090bb9SJonathan Marek <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 403205090bb9SJonathan Marek <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 403305090bb9SJonathan Marek <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 403405090bb9SJonathan Marek <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 403505090bb9SJonathan Marek <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 403605090bb9SJonathan Marek <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 403705090bb9SJonathan Marek <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 403805090bb9SJonathan Marek <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 403905090bb9SJonathan Marek <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 404005090bb9SJonathan Marek <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 404105090bb9SJonathan Marek <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 404205090bb9SJonathan Marek iommus = <&apps_smmu 0x0640 0x1>; 404305090bb9SJonathan Marek status = "disabled"; 404405090bb9SJonathan Marek }; 4045e13c6d14SVinod Koul }; 4046e13c6d14SVinod Koul 4047e13c6d14SVinod Koul timer { 4048e13c6d14SVinod Koul compatible = "arm,armv8-timer"; 4049e13c6d14SVinod Koul interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4050e13c6d14SVinod Koul <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4051e13c6d14SVinod Koul <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4052e13c6d14SVinod Koul <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4053e13c6d14SVinod Koul }; 4054d2fa630cSAmit Kucheria 4055d2fa630cSAmit Kucheria thermal-zones { 4056d2fa630cSAmit Kucheria cpu0-thermal { 4057d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4058d2fa630cSAmit Kucheria polling-delay = <1000>; 4059d2fa630cSAmit Kucheria 4060d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 1>; 4061d2fa630cSAmit Kucheria 4062d2fa630cSAmit Kucheria trips { 4063d2fa630cSAmit Kucheria cpu0_alert0: trip-point0 { 4064d2fa630cSAmit Kucheria temperature = <90000>; 4065d2fa630cSAmit Kucheria hysteresis = <2000>; 4066d2fa630cSAmit Kucheria type = "passive"; 4067d2fa630cSAmit Kucheria }; 4068d2fa630cSAmit Kucheria 4069d2fa630cSAmit Kucheria cpu0_alert1: trip-point1 { 4070d2fa630cSAmit Kucheria temperature = <95000>; 4071d2fa630cSAmit Kucheria hysteresis = <2000>; 4072d2fa630cSAmit Kucheria type = "passive"; 4073d2fa630cSAmit Kucheria }; 4074d2fa630cSAmit Kucheria 4075d2fa630cSAmit Kucheria cpu0_crit: cpu_crit { 4076d2fa630cSAmit Kucheria temperature = <110000>; 4077d2fa630cSAmit Kucheria hysteresis = <1000>; 4078d2fa630cSAmit Kucheria type = "critical"; 4079d2fa630cSAmit Kucheria }; 4080d2fa630cSAmit Kucheria }; 4081d2fa630cSAmit Kucheria 4082d2fa630cSAmit Kucheria cooling-maps { 4083d2fa630cSAmit Kucheria map0 { 4084d2fa630cSAmit Kucheria trip = <&cpu0_alert0>; 4085d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4086d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4087d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4088d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4089d2fa630cSAmit Kucheria }; 4090d2fa630cSAmit Kucheria map1 { 4091d2fa630cSAmit Kucheria trip = <&cpu0_alert1>; 4092d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4093d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4094d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4095d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4096d2fa630cSAmit Kucheria }; 4097d2fa630cSAmit Kucheria }; 4098d2fa630cSAmit Kucheria }; 4099d2fa630cSAmit Kucheria 4100d2fa630cSAmit Kucheria cpu1-thermal { 4101d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4102d2fa630cSAmit Kucheria polling-delay = <1000>; 4103d2fa630cSAmit Kucheria 4104d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 2>; 4105d2fa630cSAmit Kucheria 4106d2fa630cSAmit Kucheria trips { 4107d2fa630cSAmit Kucheria cpu1_alert0: trip-point0 { 4108d2fa630cSAmit Kucheria temperature = <90000>; 4109d2fa630cSAmit Kucheria hysteresis = <2000>; 4110d2fa630cSAmit Kucheria type = "passive"; 4111d2fa630cSAmit Kucheria }; 4112d2fa630cSAmit Kucheria 4113d2fa630cSAmit Kucheria cpu1_alert1: trip-point1 { 4114d2fa630cSAmit Kucheria temperature = <95000>; 4115d2fa630cSAmit Kucheria hysteresis = <2000>; 4116d2fa630cSAmit Kucheria type = "passive"; 4117d2fa630cSAmit Kucheria }; 4118d2fa630cSAmit Kucheria 4119d2fa630cSAmit Kucheria cpu1_crit: cpu_crit { 4120d2fa630cSAmit Kucheria temperature = <110000>; 4121d2fa630cSAmit Kucheria hysteresis = <1000>; 4122d2fa630cSAmit Kucheria type = "critical"; 4123d2fa630cSAmit Kucheria }; 4124d2fa630cSAmit Kucheria }; 4125d2fa630cSAmit Kucheria 4126d2fa630cSAmit Kucheria cooling-maps { 4127d2fa630cSAmit Kucheria map0 { 4128d2fa630cSAmit Kucheria trip = <&cpu1_alert0>; 4129d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4130d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4131d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4132d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4133d2fa630cSAmit Kucheria }; 4134d2fa630cSAmit Kucheria map1 { 4135d2fa630cSAmit Kucheria trip = <&cpu1_alert1>; 4136d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4137d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4138d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4139d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4140d2fa630cSAmit Kucheria }; 4141d2fa630cSAmit Kucheria }; 4142d2fa630cSAmit Kucheria }; 4143d2fa630cSAmit Kucheria 4144d2fa630cSAmit Kucheria cpu2-thermal { 4145d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4146d2fa630cSAmit Kucheria polling-delay = <1000>; 4147d2fa630cSAmit Kucheria 4148d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 3>; 4149d2fa630cSAmit Kucheria 4150d2fa630cSAmit Kucheria trips { 4151d2fa630cSAmit Kucheria cpu2_alert0: trip-point0 { 4152d2fa630cSAmit Kucheria temperature = <90000>; 4153d2fa630cSAmit Kucheria hysteresis = <2000>; 4154d2fa630cSAmit Kucheria type = "passive"; 4155d2fa630cSAmit Kucheria }; 4156d2fa630cSAmit Kucheria 4157d2fa630cSAmit Kucheria cpu2_alert1: trip-point1 { 4158d2fa630cSAmit Kucheria temperature = <95000>; 4159d2fa630cSAmit Kucheria hysteresis = <2000>; 4160d2fa630cSAmit Kucheria type = "passive"; 4161d2fa630cSAmit Kucheria }; 4162d2fa630cSAmit Kucheria 4163d2fa630cSAmit Kucheria cpu2_crit: cpu_crit { 4164d2fa630cSAmit Kucheria temperature = <110000>; 4165d2fa630cSAmit Kucheria hysteresis = <1000>; 4166d2fa630cSAmit Kucheria type = "critical"; 4167d2fa630cSAmit Kucheria }; 4168d2fa630cSAmit Kucheria }; 4169d2fa630cSAmit Kucheria 4170d2fa630cSAmit Kucheria cooling-maps { 4171d2fa630cSAmit Kucheria map0 { 4172d2fa630cSAmit Kucheria trip = <&cpu2_alert0>; 4173d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4174d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4175d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4176d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4177d2fa630cSAmit Kucheria }; 4178d2fa630cSAmit Kucheria map1 { 4179d2fa630cSAmit Kucheria trip = <&cpu2_alert1>; 4180d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4181d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4182d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4183d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4184d2fa630cSAmit Kucheria }; 4185d2fa630cSAmit Kucheria }; 4186d2fa630cSAmit Kucheria }; 4187d2fa630cSAmit Kucheria 4188d2fa630cSAmit Kucheria cpu3-thermal { 4189d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4190d2fa630cSAmit Kucheria polling-delay = <1000>; 4191d2fa630cSAmit Kucheria 4192d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 4>; 4193d2fa630cSAmit Kucheria 4194d2fa630cSAmit Kucheria trips { 4195d2fa630cSAmit Kucheria cpu3_alert0: trip-point0 { 4196d2fa630cSAmit Kucheria temperature = <90000>; 4197d2fa630cSAmit Kucheria hysteresis = <2000>; 4198d2fa630cSAmit Kucheria type = "passive"; 4199d2fa630cSAmit Kucheria }; 4200d2fa630cSAmit Kucheria 4201d2fa630cSAmit Kucheria cpu3_alert1: trip-point1 { 4202d2fa630cSAmit Kucheria temperature = <95000>; 4203d2fa630cSAmit Kucheria hysteresis = <2000>; 4204d2fa630cSAmit Kucheria type = "passive"; 4205d2fa630cSAmit Kucheria }; 4206d2fa630cSAmit Kucheria 4207d2fa630cSAmit Kucheria cpu3_crit: cpu_crit { 4208d2fa630cSAmit Kucheria temperature = <110000>; 4209d2fa630cSAmit Kucheria hysteresis = <1000>; 4210d2fa630cSAmit Kucheria type = "critical"; 4211d2fa630cSAmit Kucheria }; 4212d2fa630cSAmit Kucheria }; 4213d2fa630cSAmit Kucheria 4214d2fa630cSAmit Kucheria cooling-maps { 4215d2fa630cSAmit Kucheria map0 { 4216d2fa630cSAmit Kucheria trip = <&cpu3_alert0>; 4217d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4218d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4219d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4220d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4221d2fa630cSAmit Kucheria }; 4222d2fa630cSAmit Kucheria map1 { 4223d2fa630cSAmit Kucheria trip = <&cpu3_alert1>; 4224d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4225d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4226d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4227d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4228d2fa630cSAmit Kucheria }; 4229d2fa630cSAmit Kucheria }; 4230d2fa630cSAmit Kucheria }; 4231d2fa630cSAmit Kucheria 4232d2fa630cSAmit Kucheria cpu4-top-thermal { 4233d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4234d2fa630cSAmit Kucheria polling-delay = <1000>; 4235d2fa630cSAmit Kucheria 4236d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 7>; 4237d2fa630cSAmit Kucheria 4238d2fa630cSAmit Kucheria trips { 4239d2fa630cSAmit Kucheria cpu4_top_alert0: trip-point0 { 4240d2fa630cSAmit Kucheria temperature = <90000>; 4241d2fa630cSAmit Kucheria hysteresis = <2000>; 4242d2fa630cSAmit Kucheria type = "passive"; 4243d2fa630cSAmit Kucheria }; 4244d2fa630cSAmit Kucheria 4245d2fa630cSAmit Kucheria cpu4_top_alert1: trip-point1 { 4246d2fa630cSAmit Kucheria temperature = <95000>; 4247d2fa630cSAmit Kucheria hysteresis = <2000>; 4248d2fa630cSAmit Kucheria type = "passive"; 4249d2fa630cSAmit Kucheria }; 4250d2fa630cSAmit Kucheria 4251d2fa630cSAmit Kucheria cpu4_top_crit: cpu_crit { 4252d2fa630cSAmit Kucheria temperature = <110000>; 4253d2fa630cSAmit Kucheria hysteresis = <1000>; 4254d2fa630cSAmit Kucheria type = "critical"; 4255d2fa630cSAmit Kucheria }; 4256d2fa630cSAmit Kucheria }; 4257d2fa630cSAmit Kucheria 4258d2fa630cSAmit Kucheria cooling-maps { 4259d2fa630cSAmit Kucheria map0 { 4260d2fa630cSAmit Kucheria trip = <&cpu4_top_alert0>; 4261d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4262d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4263d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4264d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4265d2fa630cSAmit Kucheria }; 4266d2fa630cSAmit Kucheria map1 { 4267d2fa630cSAmit Kucheria trip = <&cpu4_top_alert1>; 4268d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4269d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4270d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4271d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4272d2fa630cSAmit Kucheria }; 4273d2fa630cSAmit Kucheria }; 4274d2fa630cSAmit Kucheria }; 4275d2fa630cSAmit Kucheria 4276d2fa630cSAmit Kucheria cpu5-top-thermal { 4277d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4278d2fa630cSAmit Kucheria polling-delay = <1000>; 4279d2fa630cSAmit Kucheria 4280d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 8>; 4281d2fa630cSAmit Kucheria 4282d2fa630cSAmit Kucheria trips { 4283d2fa630cSAmit Kucheria cpu5_top_alert0: trip-point0 { 4284d2fa630cSAmit Kucheria temperature = <90000>; 4285d2fa630cSAmit Kucheria hysteresis = <2000>; 4286d2fa630cSAmit Kucheria type = "passive"; 4287d2fa630cSAmit Kucheria }; 4288d2fa630cSAmit Kucheria 4289d2fa630cSAmit Kucheria cpu5_top_alert1: trip-point1 { 4290d2fa630cSAmit Kucheria temperature = <95000>; 4291d2fa630cSAmit Kucheria hysteresis = <2000>; 4292d2fa630cSAmit Kucheria type = "passive"; 4293d2fa630cSAmit Kucheria }; 4294d2fa630cSAmit Kucheria 4295d2fa630cSAmit Kucheria cpu5_top_crit: cpu_crit { 4296d2fa630cSAmit Kucheria temperature = <110000>; 4297d2fa630cSAmit Kucheria hysteresis = <1000>; 4298d2fa630cSAmit Kucheria type = "critical"; 4299d2fa630cSAmit Kucheria }; 4300d2fa630cSAmit Kucheria }; 4301d2fa630cSAmit Kucheria 4302d2fa630cSAmit Kucheria cooling-maps { 4303d2fa630cSAmit Kucheria map0 { 4304d2fa630cSAmit Kucheria trip = <&cpu5_top_alert0>; 4305d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4306d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4307d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4308d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4309d2fa630cSAmit Kucheria }; 4310d2fa630cSAmit Kucheria map1 { 4311d2fa630cSAmit Kucheria trip = <&cpu5_top_alert1>; 4312d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4313d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4314d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4315d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4316d2fa630cSAmit Kucheria }; 4317d2fa630cSAmit Kucheria }; 4318d2fa630cSAmit Kucheria }; 4319d2fa630cSAmit Kucheria 4320d2fa630cSAmit Kucheria cpu6-top-thermal { 4321d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4322d2fa630cSAmit Kucheria polling-delay = <1000>; 4323d2fa630cSAmit Kucheria 4324d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 9>; 4325d2fa630cSAmit Kucheria 4326d2fa630cSAmit Kucheria trips { 4327d2fa630cSAmit Kucheria cpu6_top_alert0: trip-point0 { 4328d2fa630cSAmit Kucheria temperature = <90000>; 4329d2fa630cSAmit Kucheria hysteresis = <2000>; 4330d2fa630cSAmit Kucheria type = "passive"; 4331d2fa630cSAmit Kucheria }; 4332d2fa630cSAmit Kucheria 4333d2fa630cSAmit Kucheria cpu6_top_alert1: trip-point1 { 4334d2fa630cSAmit Kucheria temperature = <95000>; 4335d2fa630cSAmit Kucheria hysteresis = <2000>; 4336d2fa630cSAmit Kucheria type = "passive"; 4337d2fa630cSAmit Kucheria }; 4338d2fa630cSAmit Kucheria 4339d2fa630cSAmit Kucheria cpu6_top_crit: cpu_crit { 4340d2fa630cSAmit Kucheria temperature = <110000>; 4341d2fa630cSAmit Kucheria hysteresis = <1000>; 4342d2fa630cSAmit Kucheria type = "critical"; 4343d2fa630cSAmit Kucheria }; 4344d2fa630cSAmit Kucheria }; 4345d2fa630cSAmit Kucheria 4346d2fa630cSAmit Kucheria cooling-maps { 4347d2fa630cSAmit Kucheria map0 { 4348d2fa630cSAmit Kucheria trip = <&cpu6_top_alert0>; 4349d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4350d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4351d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4352d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4353d2fa630cSAmit Kucheria }; 4354d2fa630cSAmit Kucheria map1 { 4355d2fa630cSAmit Kucheria trip = <&cpu6_top_alert1>; 4356d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4357d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4358d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4359d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4360d2fa630cSAmit Kucheria }; 4361d2fa630cSAmit Kucheria }; 4362d2fa630cSAmit Kucheria }; 4363d2fa630cSAmit Kucheria 4364d2fa630cSAmit Kucheria cpu7-top-thermal { 4365d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4366d2fa630cSAmit Kucheria polling-delay = <1000>; 4367d2fa630cSAmit Kucheria 4368d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 10>; 4369d2fa630cSAmit Kucheria 4370d2fa630cSAmit Kucheria trips { 4371d2fa630cSAmit Kucheria cpu7_top_alert0: trip-point0 { 4372d2fa630cSAmit Kucheria temperature = <90000>; 4373d2fa630cSAmit Kucheria hysteresis = <2000>; 4374d2fa630cSAmit Kucheria type = "passive"; 4375d2fa630cSAmit Kucheria }; 4376d2fa630cSAmit Kucheria 4377d2fa630cSAmit Kucheria cpu7_top_alert1: trip-point1 { 4378d2fa630cSAmit Kucheria temperature = <95000>; 4379d2fa630cSAmit Kucheria hysteresis = <2000>; 4380d2fa630cSAmit Kucheria type = "passive"; 4381d2fa630cSAmit Kucheria }; 4382d2fa630cSAmit Kucheria 4383d2fa630cSAmit Kucheria cpu7_top_crit: cpu_crit { 4384d2fa630cSAmit Kucheria temperature = <110000>; 4385d2fa630cSAmit Kucheria hysteresis = <1000>; 4386d2fa630cSAmit Kucheria type = "critical"; 4387d2fa630cSAmit Kucheria }; 4388d2fa630cSAmit Kucheria }; 4389d2fa630cSAmit Kucheria 4390d2fa630cSAmit Kucheria cooling-maps { 4391d2fa630cSAmit Kucheria map0 { 4392d2fa630cSAmit Kucheria trip = <&cpu7_top_alert0>; 4393d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4394d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4395d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4396d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4397d2fa630cSAmit Kucheria }; 4398d2fa630cSAmit Kucheria map1 { 4399d2fa630cSAmit Kucheria trip = <&cpu7_top_alert1>; 4400d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4401d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4402d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4403d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4404d2fa630cSAmit Kucheria }; 4405d2fa630cSAmit Kucheria }; 4406d2fa630cSAmit Kucheria }; 4407d2fa630cSAmit Kucheria 4408d2fa630cSAmit Kucheria cpu4-bottom-thermal { 4409d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4410d2fa630cSAmit Kucheria polling-delay = <1000>; 4411d2fa630cSAmit Kucheria 4412d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 11>; 4413d2fa630cSAmit Kucheria 4414d2fa630cSAmit Kucheria trips { 4415d2fa630cSAmit Kucheria cpu4_bottom_alert0: trip-point0 { 4416d2fa630cSAmit Kucheria temperature = <90000>; 4417d2fa630cSAmit Kucheria hysteresis = <2000>; 4418d2fa630cSAmit Kucheria type = "passive"; 4419d2fa630cSAmit Kucheria }; 4420d2fa630cSAmit Kucheria 4421d2fa630cSAmit Kucheria cpu4_bottom_alert1: trip-point1 { 4422d2fa630cSAmit Kucheria temperature = <95000>; 4423d2fa630cSAmit Kucheria hysteresis = <2000>; 4424d2fa630cSAmit Kucheria type = "passive"; 4425d2fa630cSAmit Kucheria }; 4426d2fa630cSAmit Kucheria 4427d2fa630cSAmit Kucheria cpu4_bottom_crit: cpu_crit { 4428d2fa630cSAmit Kucheria temperature = <110000>; 4429d2fa630cSAmit Kucheria hysteresis = <1000>; 4430d2fa630cSAmit Kucheria type = "critical"; 4431d2fa630cSAmit Kucheria }; 4432d2fa630cSAmit Kucheria }; 4433d2fa630cSAmit Kucheria 4434d2fa630cSAmit Kucheria cooling-maps { 4435d2fa630cSAmit Kucheria map0 { 4436d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert0>; 4437d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4438d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4439d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4440d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4441d2fa630cSAmit Kucheria }; 4442d2fa630cSAmit Kucheria map1 { 4443d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert1>; 4444d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4445d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4446d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4447d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4448d2fa630cSAmit Kucheria }; 4449d2fa630cSAmit Kucheria }; 4450d2fa630cSAmit Kucheria }; 4451d2fa630cSAmit Kucheria 4452d2fa630cSAmit Kucheria cpu5-bottom-thermal { 4453d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4454d2fa630cSAmit Kucheria polling-delay = <1000>; 4455d2fa630cSAmit Kucheria 4456d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 12>; 4457d2fa630cSAmit Kucheria 4458d2fa630cSAmit Kucheria trips { 4459d2fa630cSAmit Kucheria cpu5_bottom_alert0: trip-point0 { 4460d2fa630cSAmit Kucheria temperature = <90000>; 4461d2fa630cSAmit Kucheria hysteresis = <2000>; 4462d2fa630cSAmit Kucheria type = "passive"; 4463d2fa630cSAmit Kucheria }; 4464d2fa630cSAmit Kucheria 4465d2fa630cSAmit Kucheria cpu5_bottom_alert1: trip-point1 { 4466d2fa630cSAmit Kucheria temperature = <95000>; 4467d2fa630cSAmit Kucheria hysteresis = <2000>; 4468d2fa630cSAmit Kucheria type = "passive"; 4469d2fa630cSAmit Kucheria }; 4470d2fa630cSAmit Kucheria 4471d2fa630cSAmit Kucheria cpu5_bottom_crit: cpu_crit { 4472d2fa630cSAmit Kucheria temperature = <110000>; 4473d2fa630cSAmit Kucheria hysteresis = <1000>; 4474d2fa630cSAmit Kucheria type = "critical"; 4475d2fa630cSAmit Kucheria }; 4476d2fa630cSAmit Kucheria }; 4477d2fa630cSAmit Kucheria 4478d2fa630cSAmit Kucheria cooling-maps { 4479d2fa630cSAmit Kucheria map0 { 4480d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert0>; 4481d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4482d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4483d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4484d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4485d2fa630cSAmit Kucheria }; 4486d2fa630cSAmit Kucheria map1 { 4487d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert1>; 4488d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4489d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4490d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4491d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4492d2fa630cSAmit Kucheria }; 4493d2fa630cSAmit Kucheria }; 4494d2fa630cSAmit Kucheria }; 4495d2fa630cSAmit Kucheria 4496d2fa630cSAmit Kucheria cpu6-bottom-thermal { 4497d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4498d2fa630cSAmit Kucheria polling-delay = <1000>; 4499d2fa630cSAmit Kucheria 4500d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 13>; 4501d2fa630cSAmit Kucheria 4502d2fa630cSAmit Kucheria trips { 4503d2fa630cSAmit Kucheria cpu6_bottom_alert0: trip-point0 { 4504d2fa630cSAmit Kucheria temperature = <90000>; 4505d2fa630cSAmit Kucheria hysteresis = <2000>; 4506d2fa630cSAmit Kucheria type = "passive"; 4507d2fa630cSAmit Kucheria }; 4508d2fa630cSAmit Kucheria 4509d2fa630cSAmit Kucheria cpu6_bottom_alert1: trip-point1 { 4510d2fa630cSAmit Kucheria temperature = <95000>; 4511d2fa630cSAmit Kucheria hysteresis = <2000>; 4512d2fa630cSAmit Kucheria type = "passive"; 4513d2fa630cSAmit Kucheria }; 4514d2fa630cSAmit Kucheria 4515d2fa630cSAmit Kucheria cpu6_bottom_crit: cpu_crit { 4516d2fa630cSAmit Kucheria temperature = <110000>; 4517d2fa630cSAmit Kucheria hysteresis = <1000>; 4518d2fa630cSAmit Kucheria type = "critical"; 4519d2fa630cSAmit Kucheria }; 4520d2fa630cSAmit Kucheria }; 4521d2fa630cSAmit Kucheria 4522d2fa630cSAmit Kucheria cooling-maps { 4523d2fa630cSAmit Kucheria map0 { 4524d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert0>; 4525d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4526d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4527d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4528d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4529d2fa630cSAmit Kucheria }; 4530d2fa630cSAmit Kucheria map1 { 4531d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert1>; 4532d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4533d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4534d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4535d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4536d2fa630cSAmit Kucheria }; 4537d2fa630cSAmit Kucheria }; 4538d2fa630cSAmit Kucheria }; 4539d2fa630cSAmit Kucheria 4540d2fa630cSAmit Kucheria cpu7-bottom-thermal { 4541d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4542d2fa630cSAmit Kucheria polling-delay = <1000>; 4543d2fa630cSAmit Kucheria 4544d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 14>; 4545d2fa630cSAmit Kucheria 4546d2fa630cSAmit Kucheria trips { 4547d2fa630cSAmit Kucheria cpu7_bottom_alert0: trip-point0 { 4548d2fa630cSAmit Kucheria temperature = <90000>; 4549d2fa630cSAmit Kucheria hysteresis = <2000>; 4550d2fa630cSAmit Kucheria type = "passive"; 4551d2fa630cSAmit Kucheria }; 4552d2fa630cSAmit Kucheria 4553d2fa630cSAmit Kucheria cpu7_bottom_alert1: trip-point1 { 4554d2fa630cSAmit Kucheria temperature = <95000>; 4555d2fa630cSAmit Kucheria hysteresis = <2000>; 4556d2fa630cSAmit Kucheria type = "passive"; 4557d2fa630cSAmit Kucheria }; 4558d2fa630cSAmit Kucheria 4559d2fa630cSAmit Kucheria cpu7_bottom_crit: cpu_crit { 4560d2fa630cSAmit Kucheria temperature = <110000>; 4561d2fa630cSAmit Kucheria hysteresis = <1000>; 4562d2fa630cSAmit Kucheria type = "critical"; 4563d2fa630cSAmit Kucheria }; 4564d2fa630cSAmit Kucheria }; 4565d2fa630cSAmit Kucheria 4566d2fa630cSAmit Kucheria cooling-maps { 4567d2fa630cSAmit Kucheria map0 { 4568d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert0>; 4569d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4570d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4571d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4572d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4573d2fa630cSAmit Kucheria }; 4574d2fa630cSAmit Kucheria map1 { 4575d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert1>; 4576d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4577d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4578d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4579d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4580d2fa630cSAmit Kucheria }; 4581d2fa630cSAmit Kucheria }; 4582d2fa630cSAmit Kucheria }; 4583d2fa630cSAmit Kucheria 4584d2fa630cSAmit Kucheria aoss0-thermal { 4585d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4586d2fa630cSAmit Kucheria polling-delay = <1000>; 4587d2fa630cSAmit Kucheria 4588d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 0>; 4589d2fa630cSAmit Kucheria 4590d2fa630cSAmit Kucheria trips { 4591d2fa630cSAmit Kucheria aoss0_alert0: trip-point0 { 4592d2fa630cSAmit Kucheria temperature = <90000>; 4593d2fa630cSAmit Kucheria hysteresis = <2000>; 4594d2fa630cSAmit Kucheria type = "hot"; 4595d2fa630cSAmit Kucheria }; 4596d2fa630cSAmit Kucheria }; 4597d2fa630cSAmit Kucheria }; 4598d2fa630cSAmit Kucheria 4599d2fa630cSAmit Kucheria cluster0-thermal { 4600d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4601d2fa630cSAmit Kucheria polling-delay = <1000>; 4602d2fa630cSAmit Kucheria 4603d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 5>; 4604d2fa630cSAmit Kucheria 4605d2fa630cSAmit Kucheria trips { 4606d2fa630cSAmit Kucheria cluster0_alert0: trip-point0 { 4607d2fa630cSAmit Kucheria temperature = <90000>; 4608d2fa630cSAmit Kucheria hysteresis = <2000>; 4609d2fa630cSAmit Kucheria type = "hot"; 4610d2fa630cSAmit Kucheria }; 4611d2fa630cSAmit Kucheria cluster0_crit: cluster0_crit { 4612d2fa630cSAmit Kucheria temperature = <110000>; 4613d2fa630cSAmit Kucheria hysteresis = <2000>; 4614d2fa630cSAmit Kucheria type = "critical"; 4615d2fa630cSAmit Kucheria }; 4616d2fa630cSAmit Kucheria }; 4617d2fa630cSAmit Kucheria }; 4618d2fa630cSAmit Kucheria 4619d2fa630cSAmit Kucheria cluster1-thermal { 4620d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4621d2fa630cSAmit Kucheria polling-delay = <1000>; 4622d2fa630cSAmit Kucheria 4623d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 6>; 4624d2fa630cSAmit Kucheria 4625d2fa630cSAmit Kucheria trips { 4626d2fa630cSAmit Kucheria cluster1_alert0: trip-point0 { 4627d2fa630cSAmit Kucheria temperature = <90000>; 4628d2fa630cSAmit Kucheria hysteresis = <2000>; 4629d2fa630cSAmit Kucheria type = "hot"; 4630d2fa630cSAmit Kucheria }; 4631d2fa630cSAmit Kucheria cluster1_crit: cluster1_crit { 4632d2fa630cSAmit Kucheria temperature = <110000>; 4633d2fa630cSAmit Kucheria hysteresis = <2000>; 4634d2fa630cSAmit Kucheria type = "critical"; 4635d2fa630cSAmit Kucheria }; 4636d2fa630cSAmit Kucheria }; 4637d2fa630cSAmit Kucheria }; 4638d2fa630cSAmit Kucheria 46397be1c395SDavid Heidelberg gpu-top-thermal { 4640d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4641d2fa630cSAmit Kucheria polling-delay = <1000>; 4642d2fa630cSAmit Kucheria 4643d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 15>; 4644d2fa630cSAmit Kucheria 4645d2fa630cSAmit Kucheria trips { 4646d2fa630cSAmit Kucheria gpu1_alert0: trip-point0 { 4647d2fa630cSAmit Kucheria temperature = <90000>; 4648d2fa630cSAmit Kucheria hysteresis = <2000>; 4649d2fa630cSAmit Kucheria type = "hot"; 4650d2fa630cSAmit Kucheria }; 4651d2fa630cSAmit Kucheria }; 4652d2fa630cSAmit Kucheria }; 4653d2fa630cSAmit Kucheria 4654d2fa630cSAmit Kucheria aoss1-thermal { 4655d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4656d2fa630cSAmit Kucheria polling-delay = <1000>; 4657d2fa630cSAmit Kucheria 4658d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 0>; 4659d2fa630cSAmit Kucheria 4660d2fa630cSAmit Kucheria trips { 4661d2fa630cSAmit Kucheria aoss1_alert0: trip-point0 { 4662d2fa630cSAmit Kucheria temperature = <90000>; 4663d2fa630cSAmit Kucheria hysteresis = <2000>; 4664d2fa630cSAmit Kucheria type = "hot"; 4665d2fa630cSAmit Kucheria }; 4666d2fa630cSAmit Kucheria }; 4667d2fa630cSAmit Kucheria }; 4668d2fa630cSAmit Kucheria 4669d2fa630cSAmit Kucheria wlan-thermal { 4670d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4671d2fa630cSAmit Kucheria polling-delay = <1000>; 4672d2fa630cSAmit Kucheria 4673d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 1>; 4674d2fa630cSAmit Kucheria 4675d2fa630cSAmit Kucheria trips { 4676d2fa630cSAmit Kucheria wlan_alert0: trip-point0 { 4677d2fa630cSAmit Kucheria temperature = <90000>; 4678d2fa630cSAmit Kucheria hysteresis = <2000>; 4679d2fa630cSAmit Kucheria type = "hot"; 4680d2fa630cSAmit Kucheria }; 4681d2fa630cSAmit Kucheria }; 4682d2fa630cSAmit Kucheria }; 4683d2fa630cSAmit Kucheria 4684d2fa630cSAmit Kucheria video-thermal { 4685d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4686d2fa630cSAmit Kucheria polling-delay = <1000>; 4687d2fa630cSAmit Kucheria 4688d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 2>; 4689d2fa630cSAmit Kucheria 4690d2fa630cSAmit Kucheria trips { 4691d2fa630cSAmit Kucheria video_alert0: trip-point0 { 4692d2fa630cSAmit Kucheria temperature = <90000>; 4693d2fa630cSAmit Kucheria hysteresis = <2000>; 4694d2fa630cSAmit Kucheria type = "hot"; 4695d2fa630cSAmit Kucheria }; 4696d2fa630cSAmit Kucheria }; 4697d2fa630cSAmit Kucheria }; 4698d2fa630cSAmit Kucheria 4699d2fa630cSAmit Kucheria mem-thermal { 4700d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4701d2fa630cSAmit Kucheria polling-delay = <1000>; 4702d2fa630cSAmit Kucheria 4703d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 3>; 4704d2fa630cSAmit Kucheria 4705d2fa630cSAmit Kucheria trips { 4706d2fa630cSAmit Kucheria mem_alert0: trip-point0 { 4707d2fa630cSAmit Kucheria temperature = <90000>; 4708d2fa630cSAmit Kucheria hysteresis = <2000>; 4709d2fa630cSAmit Kucheria type = "hot"; 4710d2fa630cSAmit Kucheria }; 4711d2fa630cSAmit Kucheria }; 4712d2fa630cSAmit Kucheria }; 4713d2fa630cSAmit Kucheria 4714d2fa630cSAmit Kucheria q6-hvx-thermal { 4715d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4716d2fa630cSAmit Kucheria polling-delay = <1000>; 4717d2fa630cSAmit Kucheria 4718d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 4>; 4719d2fa630cSAmit Kucheria 4720d2fa630cSAmit Kucheria trips { 4721d2fa630cSAmit Kucheria q6_hvx_alert0: trip-point0 { 4722d2fa630cSAmit Kucheria temperature = <90000>; 4723d2fa630cSAmit Kucheria hysteresis = <2000>; 4724d2fa630cSAmit Kucheria type = "hot"; 4725d2fa630cSAmit Kucheria }; 4726d2fa630cSAmit Kucheria }; 4727d2fa630cSAmit Kucheria }; 4728d2fa630cSAmit Kucheria 4729d2fa630cSAmit Kucheria camera-thermal { 4730d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4731d2fa630cSAmit Kucheria polling-delay = <1000>; 4732d2fa630cSAmit Kucheria 4733d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 5>; 4734d2fa630cSAmit Kucheria 4735d2fa630cSAmit Kucheria trips { 4736d2fa630cSAmit Kucheria camera_alert0: trip-point0 { 4737d2fa630cSAmit Kucheria temperature = <90000>; 4738d2fa630cSAmit Kucheria hysteresis = <2000>; 4739d2fa630cSAmit Kucheria type = "hot"; 4740d2fa630cSAmit Kucheria }; 4741d2fa630cSAmit Kucheria }; 4742d2fa630cSAmit Kucheria }; 4743d2fa630cSAmit Kucheria 4744d2fa630cSAmit Kucheria compute-thermal { 4745d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4746d2fa630cSAmit Kucheria polling-delay = <1000>; 4747d2fa630cSAmit Kucheria 4748d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 6>; 4749d2fa630cSAmit Kucheria 4750d2fa630cSAmit Kucheria trips { 4751d2fa630cSAmit Kucheria compute_alert0: trip-point0 { 4752d2fa630cSAmit Kucheria temperature = <90000>; 4753d2fa630cSAmit Kucheria hysteresis = <2000>; 4754d2fa630cSAmit Kucheria type = "hot"; 4755d2fa630cSAmit Kucheria }; 4756d2fa630cSAmit Kucheria }; 4757d2fa630cSAmit Kucheria }; 4758d2fa630cSAmit Kucheria 4759d2fa630cSAmit Kucheria modem-thermal { 4760d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4761d2fa630cSAmit Kucheria polling-delay = <1000>; 4762d2fa630cSAmit Kucheria 4763d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 7>; 4764d2fa630cSAmit Kucheria 4765d2fa630cSAmit Kucheria trips { 4766d2fa630cSAmit Kucheria modem_alert0: trip-point0 { 4767d2fa630cSAmit Kucheria temperature = <90000>; 4768d2fa630cSAmit Kucheria hysteresis = <2000>; 4769d2fa630cSAmit Kucheria type = "hot"; 4770d2fa630cSAmit Kucheria }; 4771d2fa630cSAmit Kucheria }; 4772d2fa630cSAmit Kucheria }; 4773d2fa630cSAmit Kucheria 4774d2fa630cSAmit Kucheria npu-thermal { 4775d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4776d2fa630cSAmit Kucheria polling-delay = <1000>; 4777d2fa630cSAmit Kucheria 4778d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 8>; 4779d2fa630cSAmit Kucheria 4780d2fa630cSAmit Kucheria trips { 4781d2fa630cSAmit Kucheria npu_alert0: trip-point0 { 4782d2fa630cSAmit Kucheria temperature = <90000>; 4783d2fa630cSAmit Kucheria hysteresis = <2000>; 4784d2fa630cSAmit Kucheria type = "hot"; 4785d2fa630cSAmit Kucheria }; 4786d2fa630cSAmit Kucheria }; 4787d2fa630cSAmit Kucheria }; 4788d2fa630cSAmit Kucheria 4789d2fa630cSAmit Kucheria modem-vec-thermal { 4790d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4791d2fa630cSAmit Kucheria polling-delay = <1000>; 4792d2fa630cSAmit Kucheria 4793d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 9>; 4794d2fa630cSAmit Kucheria 4795d2fa630cSAmit Kucheria trips { 4796d2fa630cSAmit Kucheria modem_vec_alert0: trip-point0 { 4797d2fa630cSAmit Kucheria temperature = <90000>; 4798d2fa630cSAmit Kucheria hysteresis = <2000>; 4799d2fa630cSAmit Kucheria type = "hot"; 4800d2fa630cSAmit Kucheria }; 4801d2fa630cSAmit Kucheria }; 4802d2fa630cSAmit Kucheria }; 4803d2fa630cSAmit Kucheria 4804d2fa630cSAmit Kucheria modem-scl-thermal { 4805d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4806d2fa630cSAmit Kucheria polling-delay = <1000>; 4807d2fa630cSAmit Kucheria 4808d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 10>; 4809d2fa630cSAmit Kucheria 4810d2fa630cSAmit Kucheria trips { 4811d2fa630cSAmit Kucheria modem_scl_alert0: trip-point0 { 4812d2fa630cSAmit Kucheria temperature = <90000>; 4813d2fa630cSAmit Kucheria hysteresis = <2000>; 4814d2fa630cSAmit Kucheria type = "hot"; 4815d2fa630cSAmit Kucheria }; 4816d2fa630cSAmit Kucheria }; 4817d2fa630cSAmit Kucheria }; 4818d2fa630cSAmit Kucheria 48197be1c395SDavid Heidelberg gpu-bottom-thermal { 4820d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4821d2fa630cSAmit Kucheria polling-delay = <1000>; 4822d2fa630cSAmit Kucheria 4823d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 11>; 4824d2fa630cSAmit Kucheria 4825d2fa630cSAmit Kucheria trips { 4826d2fa630cSAmit Kucheria gpu2_alert0: trip-point0 { 4827d2fa630cSAmit Kucheria temperature = <90000>; 4828d2fa630cSAmit Kucheria hysteresis = <2000>; 4829d2fa630cSAmit Kucheria type = "hot"; 4830d2fa630cSAmit Kucheria }; 4831d2fa630cSAmit Kucheria }; 4832d2fa630cSAmit Kucheria }; 4833d2fa630cSAmit Kucheria }; 4834e13c6d14SVinod Koul}; 4835