1e13c6d14SVinod Koul// SPDX-License-Identifier: BSD-3-Clause 2e13c6d14SVinod Koul/* 3e13c6d14SVinod Koul * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4e13c6d14SVinod Koul * Copyright (c) 2019, Linaro Limited 5e13c6d14SVinod Koul */ 6e13c6d14SVinod Koul 705006290SFelipe Balbi#include <dt-bindings/dma/qcom-gpi.h> 8e13c6d14SVinod Koul#include <dt-bindings/interrupt-controller/arm-gic.h> 9017e7856SSibi Sankar#include <dt-bindings/power/qcom-rpmpd.h> 10e13c6d14SVinod Koul#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11e13c6d14SVinod Koul#include <dt-bindings/clock/qcom,rpmh.h> 12d6f55763SVinod Koul#include <dt-bindings/clock/qcom,gcc-sm8150.h> 13f1269916SJonathan Marek#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 14a6d435c1SSibi Sankar#include <dt-bindings/interconnect/qcom,osm-l3.h> 152b6187abSThara Gopinath#include <dt-bindings/interconnect/qcom,sm8150.h> 16d2fa630cSAmit Kucheria#include <dt-bindings/thermal/thermal.h> 17e13c6d14SVinod Koul 18e13c6d14SVinod Koul/ { 19e13c6d14SVinod Koul interrupt-parent = <&intc>; 20e13c6d14SVinod Koul 21e13c6d14SVinod Koul #address-cells = <2>; 22e13c6d14SVinod Koul #size-cells = <2>; 23e13c6d14SVinod Koul 24e13c6d14SVinod Koul chosen { }; 25e13c6d14SVinod Koul 26e13c6d14SVinod Koul clocks { 27e13c6d14SVinod Koul xo_board: xo-board { 28e13c6d14SVinod Koul compatible = "fixed-clock"; 29e13c6d14SVinod Koul #clock-cells = <0>; 30e13c6d14SVinod Koul clock-frequency = <38400000>; 31e13c6d14SVinod Koul clock-output-names = "xo_board"; 32e13c6d14SVinod Koul }; 33e13c6d14SVinod Koul 34e13c6d14SVinod Koul sleep_clk: sleep-clk { 35e13c6d14SVinod Koul compatible = "fixed-clock"; 36e13c6d14SVinod Koul #clock-cells = <0>; 37e13c6d14SVinod Koul clock-frequency = <32764>; 38e13c6d14SVinod Koul clock-output-names = "sleep_clk"; 39e13c6d14SVinod Koul }; 40e13c6d14SVinod Koul }; 41e13c6d14SVinod Koul 42e13c6d14SVinod Koul cpus { 43e13c6d14SVinod Koul #address-cells = <2>; 44e13c6d14SVinod Koul #size-cells = <0>; 45e13c6d14SVinod Koul 46e13c6d14SVinod Koul CPU0: cpu@0 { 47e13c6d14SVinod Koul device_type = "cpu"; 48e13c6d14SVinod Koul compatible = "qcom,kryo485"; 49e13c6d14SVinod Koul reg = <0x0 0x0>; 50e13c6d14SVinod Koul enable-method = "psci"; 515b2dae72SDanny Lin capacity-dmips-mhz = <488>; 525b2dae72SDanny Lin dynamic-power-coefficient = <232>; 53e13c6d14SVinod Koul next-level-cache = <&L2_0>; 54fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 552b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 562b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 572b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 58b2e3f897SDanny Lin power-domains = <&CPU_PD0>; 59b2e3f897SDanny Lin power-domain-names = "psci"; 60d2fa630cSAmit Kucheria #cooling-cells = <2>; 61e13c6d14SVinod Koul L2_0: l2-cache { 62e13c6d14SVinod Koul compatible = "cache"; 63e13c6d14SVinod Koul next-level-cache = <&L3_0>; 64e13c6d14SVinod Koul L3_0: l3-cache { 65e13c6d14SVinod Koul compatible = "cache"; 66e13c6d14SVinod Koul }; 67e13c6d14SVinod Koul }; 68e13c6d14SVinod Koul }; 69e13c6d14SVinod Koul 70e13c6d14SVinod Koul CPU1: cpu@100 { 71e13c6d14SVinod Koul device_type = "cpu"; 72e13c6d14SVinod Koul compatible = "qcom,kryo485"; 73e13c6d14SVinod Koul reg = <0x0 0x100>; 74e13c6d14SVinod Koul enable-method = "psci"; 755b2dae72SDanny Lin capacity-dmips-mhz = <488>; 765b2dae72SDanny Lin dynamic-power-coefficient = <232>; 77e13c6d14SVinod Koul next-level-cache = <&L2_100>; 78fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 792b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 802b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 812b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 82b2e3f897SDanny Lin power-domains = <&CPU_PD1>; 83b2e3f897SDanny Lin power-domain-names = "psci"; 84d2fa630cSAmit Kucheria #cooling-cells = <2>; 85e13c6d14SVinod Koul L2_100: l2-cache { 86e13c6d14SVinod Koul compatible = "cache"; 87e13c6d14SVinod Koul next-level-cache = <&L3_0>; 88e13c6d14SVinod Koul }; 89e13c6d14SVinod Koul 90e13c6d14SVinod Koul }; 91e13c6d14SVinod Koul 92e13c6d14SVinod Koul CPU2: cpu@200 { 93e13c6d14SVinod Koul device_type = "cpu"; 94e13c6d14SVinod Koul compatible = "qcom,kryo485"; 95e13c6d14SVinod Koul reg = <0x0 0x200>; 96e13c6d14SVinod Koul enable-method = "psci"; 975b2dae72SDanny Lin capacity-dmips-mhz = <488>; 985b2dae72SDanny Lin dynamic-power-coefficient = <232>; 99e13c6d14SVinod Koul next-level-cache = <&L2_200>; 100fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1012b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1022b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1032b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 104b2e3f897SDanny Lin power-domains = <&CPU_PD2>; 105b2e3f897SDanny Lin power-domain-names = "psci"; 106d2fa630cSAmit Kucheria #cooling-cells = <2>; 107e13c6d14SVinod Koul L2_200: l2-cache { 108e13c6d14SVinod Koul compatible = "cache"; 109e13c6d14SVinod Koul next-level-cache = <&L3_0>; 110e13c6d14SVinod Koul }; 111e13c6d14SVinod Koul }; 112e13c6d14SVinod Koul 113e13c6d14SVinod Koul CPU3: cpu@300 { 114e13c6d14SVinod Koul device_type = "cpu"; 115e13c6d14SVinod Koul compatible = "qcom,kryo485"; 116e13c6d14SVinod Koul reg = <0x0 0x300>; 117e13c6d14SVinod Koul enable-method = "psci"; 1185b2dae72SDanny Lin capacity-dmips-mhz = <488>; 1195b2dae72SDanny Lin dynamic-power-coefficient = <232>; 120e13c6d14SVinod Koul next-level-cache = <&L2_300>; 121fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1222b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1232b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1242b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 125b2e3f897SDanny Lin power-domains = <&CPU_PD3>; 126b2e3f897SDanny Lin power-domain-names = "psci"; 127d2fa630cSAmit Kucheria #cooling-cells = <2>; 128e13c6d14SVinod Koul L2_300: l2-cache { 129e13c6d14SVinod Koul compatible = "cache"; 130e13c6d14SVinod Koul next-level-cache = <&L3_0>; 131e13c6d14SVinod Koul }; 132e13c6d14SVinod Koul }; 133e13c6d14SVinod Koul 134e13c6d14SVinod Koul CPU4: cpu@400 { 135e13c6d14SVinod Koul device_type = "cpu"; 136e13c6d14SVinod Koul compatible = "qcom,kryo485"; 137e13c6d14SVinod Koul reg = <0x0 0x400>; 138e13c6d14SVinod Koul enable-method = "psci"; 1395b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1405b2dae72SDanny Lin dynamic-power-coefficient = <369>; 141e13c6d14SVinod Koul next-level-cache = <&L2_400>; 142fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1432b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1442b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1452b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 146b2e3f897SDanny Lin power-domains = <&CPU_PD4>; 147b2e3f897SDanny Lin power-domain-names = "psci"; 148d2fa630cSAmit Kucheria #cooling-cells = <2>; 149e13c6d14SVinod Koul L2_400: l2-cache { 150e13c6d14SVinod Koul compatible = "cache"; 151e13c6d14SVinod Koul next-level-cache = <&L3_0>; 152e13c6d14SVinod Koul }; 153e13c6d14SVinod Koul }; 154e13c6d14SVinod Koul 155e13c6d14SVinod Koul CPU5: cpu@500 { 156e13c6d14SVinod Koul device_type = "cpu"; 157e13c6d14SVinod Koul compatible = "qcom,kryo485"; 158e13c6d14SVinod Koul reg = <0x0 0x500>; 159e13c6d14SVinod Koul enable-method = "psci"; 1605b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1615b2dae72SDanny Lin dynamic-power-coefficient = <369>; 162e13c6d14SVinod Koul next-level-cache = <&L2_500>; 163fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1642b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1652b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1662b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 167b2e3f897SDanny Lin power-domains = <&CPU_PD5>; 168b2e3f897SDanny Lin power-domain-names = "psci"; 169d2fa630cSAmit Kucheria #cooling-cells = <2>; 170e13c6d14SVinod Koul L2_500: l2-cache { 171e13c6d14SVinod Koul compatible = "cache"; 172e13c6d14SVinod Koul next-level-cache = <&L3_0>; 173e13c6d14SVinod Koul }; 174e13c6d14SVinod Koul }; 175e13c6d14SVinod Koul 176e13c6d14SVinod Koul CPU6: cpu@600 { 177e13c6d14SVinod Koul device_type = "cpu"; 178e13c6d14SVinod Koul compatible = "qcom,kryo485"; 179e13c6d14SVinod Koul reg = <0x0 0x600>; 180e13c6d14SVinod Koul enable-method = "psci"; 1815b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1825b2dae72SDanny Lin dynamic-power-coefficient = <369>; 183e13c6d14SVinod Koul next-level-cache = <&L2_600>; 184fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1852b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1862b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1872b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 188b2e3f897SDanny Lin power-domains = <&CPU_PD6>; 189b2e3f897SDanny Lin power-domain-names = "psci"; 190d2fa630cSAmit Kucheria #cooling-cells = <2>; 191e13c6d14SVinod Koul L2_600: l2-cache { 192e13c6d14SVinod Koul compatible = "cache"; 193e13c6d14SVinod Koul next-level-cache = <&L3_0>; 194e13c6d14SVinod Koul }; 195e13c6d14SVinod Koul }; 196e13c6d14SVinod Koul 197e13c6d14SVinod Koul CPU7: cpu@700 { 198e13c6d14SVinod Koul device_type = "cpu"; 199e13c6d14SVinod Koul compatible = "qcom,kryo485"; 200e13c6d14SVinod Koul reg = <0x0 0x700>; 201e13c6d14SVinod Koul enable-method = "psci"; 2025b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 2035b2dae72SDanny Lin dynamic-power-coefficient = <421>; 204e13c6d14SVinod Koul next-level-cache = <&L2_700>; 205fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 2>; 2062b6187abSThara Gopinath operating-points-v2 = <&cpu7_opp_table>; 2072b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 2082b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 209b2e3f897SDanny Lin power-domains = <&CPU_PD7>; 210b2e3f897SDanny Lin power-domain-names = "psci"; 211d2fa630cSAmit Kucheria #cooling-cells = <2>; 212e13c6d14SVinod Koul L2_700: l2-cache { 213e13c6d14SVinod Koul compatible = "cache"; 214e13c6d14SVinod Koul next-level-cache = <&L3_0>; 215e13c6d14SVinod Koul }; 216e13c6d14SVinod Koul }; 217066d21bcSDanny Lin 218066d21bcSDanny Lin cpu-map { 219066d21bcSDanny Lin cluster0 { 220066d21bcSDanny Lin core0 { 221066d21bcSDanny Lin cpu = <&CPU0>; 222066d21bcSDanny Lin }; 223066d21bcSDanny Lin 224066d21bcSDanny Lin core1 { 225066d21bcSDanny Lin cpu = <&CPU1>; 226066d21bcSDanny Lin }; 227066d21bcSDanny Lin 228066d21bcSDanny Lin core2 { 229066d21bcSDanny Lin cpu = <&CPU2>; 230066d21bcSDanny Lin }; 231066d21bcSDanny Lin 232066d21bcSDanny Lin core3 { 233066d21bcSDanny Lin cpu = <&CPU3>; 234066d21bcSDanny Lin }; 235066d21bcSDanny Lin 236066d21bcSDanny Lin core4 { 237066d21bcSDanny Lin cpu = <&CPU4>; 238066d21bcSDanny Lin }; 239066d21bcSDanny Lin 240066d21bcSDanny Lin core5 { 241066d21bcSDanny Lin cpu = <&CPU5>; 242066d21bcSDanny Lin }; 243066d21bcSDanny Lin 244066d21bcSDanny Lin core6 { 245066d21bcSDanny Lin cpu = <&CPU6>; 246066d21bcSDanny Lin }; 247066d21bcSDanny Lin 248066d21bcSDanny Lin core7 { 249066d21bcSDanny Lin cpu = <&CPU7>; 250066d21bcSDanny Lin }; 251066d21bcSDanny Lin }; 252066d21bcSDanny Lin }; 25381188f58SDanny Lin 25481188f58SDanny Lin idle-states { 25581188f58SDanny Lin entry-method = "psci"; 25681188f58SDanny Lin 25781188f58SDanny Lin LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 25881188f58SDanny Lin compatible = "arm,idle-state"; 25981188f58SDanny Lin idle-state-name = "little-rail-power-collapse"; 26081188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 26181188f58SDanny Lin entry-latency-us = <355>; 26281188f58SDanny Lin exit-latency-us = <909>; 26381188f58SDanny Lin min-residency-us = <3934>; 26481188f58SDanny Lin local-timer-stop; 26581188f58SDanny Lin }; 26681188f58SDanny Lin 26781188f58SDanny Lin BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 26881188f58SDanny Lin compatible = "arm,idle-state"; 26981188f58SDanny Lin idle-state-name = "big-rail-power-collapse"; 27081188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 27181188f58SDanny Lin entry-latency-us = <241>; 27281188f58SDanny Lin exit-latency-us = <1461>; 27381188f58SDanny Lin min-residency-us = <4488>; 27481188f58SDanny Lin local-timer-stop; 27581188f58SDanny Lin }; 276b2e3f897SDanny Lin }; 27781188f58SDanny Lin 278b2e3f897SDanny Lin domain-idle-states { 27981188f58SDanny Lin CLUSTER_SLEEP_0: cluster-sleep-0 { 280b2e3f897SDanny Lin compatible = "domain-idle-state"; 28181188f58SDanny Lin idle-state-name = "cluster-power-collapse"; 282b2e3f897SDanny Lin arm,psci-suspend-param = <0x4100c244>; 28381188f58SDanny Lin entry-latency-us = <3263>; 28481188f58SDanny Lin exit-latency-us = <6562>; 28581188f58SDanny Lin min-residency-us = <9987>; 28681188f58SDanny Lin local-timer-stop; 28781188f58SDanny Lin }; 28881188f58SDanny Lin }; 289e13c6d14SVinod Koul }; 290e13c6d14SVinod Koul 2912b6187abSThara Gopinath cpu0_opp_table: cpu0_opp_table { 2922b6187abSThara Gopinath compatible = "operating-points-v2"; 2932b6187abSThara Gopinath opp-shared; 2942b6187abSThara Gopinath 2952b6187abSThara Gopinath cpu0_opp1: opp-300000000 { 2962b6187abSThara Gopinath opp-hz = /bits/ 64 <300000000>; 2972b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 2982b6187abSThara Gopinath }; 2992b6187abSThara Gopinath 3002b6187abSThara Gopinath cpu0_opp2: opp-403200000 { 3012b6187abSThara Gopinath opp-hz = /bits/ 64 <403200000>; 3022b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 3032b6187abSThara Gopinath }; 3042b6187abSThara Gopinath 3052b6187abSThara Gopinath cpu0_opp3: opp-499200000 { 3062b6187abSThara Gopinath opp-hz = /bits/ 64 <499200000>; 3072b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3082b6187abSThara Gopinath }; 3092b6187abSThara Gopinath 3102b6187abSThara Gopinath cpu0_opp4: opp-576000000 { 3112b6187abSThara Gopinath opp-hz = /bits/ 64 <576000000>; 3122b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3132b6187abSThara Gopinath }; 3142b6187abSThara Gopinath 3152b6187abSThara Gopinath cpu0_opp5: opp-672000000 { 3162b6187abSThara Gopinath opp-hz = /bits/ 64 <672000000>; 3172b6187abSThara Gopinath opp-peak-kBps = <800000 15974400>; 3182b6187abSThara Gopinath }; 3192b6187abSThara Gopinath 3202b6187abSThara Gopinath cpu0_opp6: opp-768000000 { 321ce3b50cfSThara Gopinath opp-hz = /bits/ 64 <768000000>; 3222b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3232b6187abSThara Gopinath }; 3242b6187abSThara Gopinath 3252b6187abSThara Gopinath cpu0_opp7: opp-844800000 { 3262b6187abSThara Gopinath opp-hz = /bits/ 64 <844800000>; 3272b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3282b6187abSThara Gopinath }; 3292b6187abSThara Gopinath 3302b6187abSThara Gopinath cpu0_opp8: opp-940800000 { 3312b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 3322b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3332b6187abSThara Gopinath }; 3342b6187abSThara Gopinath 3352b6187abSThara Gopinath cpu0_opp9: opp-1036800000 { 3362b6187abSThara Gopinath opp-hz = /bits/ 64 <1036800000>; 3372b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3382b6187abSThara Gopinath }; 3392b6187abSThara Gopinath 3402b6187abSThara Gopinath cpu0_opp10: opp-1113600000 { 3412b6187abSThara Gopinath opp-hz = /bits/ 64 <1113600000>; 3422b6187abSThara Gopinath opp-peak-kBps = <2188000 25804800>; 3432b6187abSThara Gopinath }; 3442b6187abSThara Gopinath 3452b6187abSThara Gopinath cpu0_opp11: opp-1209600000 { 3462b6187abSThara Gopinath opp-hz = /bits/ 64 <1209600000>; 3472b6187abSThara Gopinath opp-peak-kBps = <2188000 31948800>; 3482b6187abSThara Gopinath }; 3492b6187abSThara Gopinath 3502b6187abSThara Gopinath cpu0_opp12: opp-1305600000 { 3512b6187abSThara Gopinath opp-hz = /bits/ 64 <1305600000>; 3522b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3532b6187abSThara Gopinath }; 3542b6187abSThara Gopinath 3552b6187abSThara Gopinath cpu0_opp13: opp-1382400000 { 3562b6187abSThara Gopinath opp-hz = /bits/ 64 <1382400000>; 3572b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3582b6187abSThara Gopinath }; 3592b6187abSThara Gopinath 3602b6187abSThara Gopinath cpu0_opp14: opp-1478400000 { 3612b6187abSThara Gopinath opp-hz = /bits/ 64 <1478400000>; 3622b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3632b6187abSThara Gopinath }; 3642b6187abSThara Gopinath 3652b6187abSThara Gopinath cpu0_opp15: opp-1555200000 { 3662b6187abSThara Gopinath opp-hz = /bits/ 64 <1555200000>; 3672b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3682b6187abSThara Gopinath }; 3692b6187abSThara Gopinath 3702b6187abSThara Gopinath cpu0_opp16: opp-1632000000 { 3712b6187abSThara Gopinath opp-hz = /bits/ 64 <1632000000>; 3722b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3732b6187abSThara Gopinath }; 3742b6187abSThara Gopinath 3752b6187abSThara Gopinath cpu0_opp17: opp-1708800000 { 3762b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 3772b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 3782b6187abSThara Gopinath }; 3792b6187abSThara Gopinath 3802b6187abSThara Gopinath cpu0_opp18: opp-1785600000 { 3812b6187abSThara Gopinath opp-hz = /bits/ 64 <1785600000>; 3822b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 3832b6187abSThara Gopinath }; 3842b6187abSThara Gopinath }; 3852b6187abSThara Gopinath 3862b6187abSThara Gopinath cpu4_opp_table: cpu4_opp_table { 3872b6187abSThara Gopinath compatible = "operating-points-v2"; 3882b6187abSThara Gopinath opp-shared; 3892b6187abSThara Gopinath 3902b6187abSThara Gopinath cpu4_opp1: opp-710400000 { 3912b6187abSThara Gopinath opp-hz = /bits/ 64 <710400000>; 3922b6187abSThara Gopinath opp-peak-kBps = <1804000 15974400>; 3932b6187abSThara Gopinath }; 3942b6187abSThara Gopinath 3952b6187abSThara Gopinath cpu4_opp2: opp-825600000 { 3962b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 3972b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 3982b6187abSThara Gopinath }; 3992b6187abSThara Gopinath 4002b6187abSThara Gopinath cpu4_opp3: opp-940800000 { 4012b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 4022b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 4032b6187abSThara Gopinath }; 4042b6187abSThara Gopinath 4052b6187abSThara Gopinath cpu4_opp4: opp-1056000000 { 4062b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 4072b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 4082b6187abSThara Gopinath }; 4092b6187abSThara Gopinath 4102b6187abSThara Gopinath cpu4_opp5: opp-1171200000 { 4112b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 4122b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 4132b6187abSThara Gopinath }; 4142b6187abSThara Gopinath 4152b6187abSThara Gopinath cpu4_opp6: opp-1286400000 { 4162b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 4172b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4182b6187abSThara Gopinath }; 4192b6187abSThara Gopinath 4202b6187abSThara Gopinath cpu4_opp7: opp-1401600000 { 4212b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 4222b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4232b6187abSThara Gopinath }; 4242b6187abSThara Gopinath 4252b6187abSThara Gopinath cpu4_opp8: opp-1497600000 { 4262b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 4272b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4282b6187abSThara Gopinath }; 4292b6187abSThara Gopinath 4302b6187abSThara Gopinath cpu4_opp9: opp-1612800000 { 4312b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 4322b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4332b6187abSThara Gopinath }; 4342b6187abSThara Gopinath 4352b6187abSThara Gopinath cpu4_opp10: opp-1708800000 { 4362b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 4372b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 4382b6187abSThara Gopinath }; 4392b6187abSThara Gopinath 4402b6187abSThara Gopinath cpu4_opp11: opp-1804800000 { 4412b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 4422b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 4432b6187abSThara Gopinath }; 4442b6187abSThara Gopinath 4452b6187abSThara Gopinath cpu4_opp12: opp-1920000000 { 4462b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 4472b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 4482b6187abSThara Gopinath }; 4492b6187abSThara Gopinath 4502b6187abSThara Gopinath cpu4_opp13: opp-2016000000 { 4512b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 4522b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 4532b6187abSThara Gopinath }; 4542b6187abSThara Gopinath 4552b6187abSThara Gopinath cpu4_opp14: opp-2131200000 { 4562b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 4572b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 4582b6187abSThara Gopinath }; 4592b6187abSThara Gopinath 4602b6187abSThara Gopinath cpu4_opp15: opp-2227200000 { 4612b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 4622b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4632b6187abSThara Gopinath }; 4642b6187abSThara Gopinath 4652b6187abSThara Gopinath cpu4_opp16: opp-2323200000 { 4662b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 4672b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4682b6187abSThara Gopinath }; 4692b6187abSThara Gopinath 4702b6187abSThara Gopinath cpu4_opp17: opp-2419200000 { 4712b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 4722b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4732b6187abSThara Gopinath }; 4742b6187abSThara Gopinath }; 4752b6187abSThara Gopinath 4762b6187abSThara Gopinath cpu7_opp_table: cpu7_opp_table { 4772b6187abSThara Gopinath compatible = "operating-points-v2"; 4782b6187abSThara Gopinath opp-shared; 4792b6187abSThara Gopinath 4802b6187abSThara Gopinath cpu7_opp1: opp-825600000 { 4812b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 4822b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 4832b6187abSThara Gopinath }; 4842b6187abSThara Gopinath 4852b6187abSThara Gopinath cpu7_opp2: opp-940800000 { 4862b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 4872b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 4882b6187abSThara Gopinath }; 4892b6187abSThara Gopinath 4902b6187abSThara Gopinath cpu7_opp3: opp-1056000000 { 4912b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 4922b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 4932b6187abSThara Gopinath }; 4942b6187abSThara Gopinath 4952b6187abSThara Gopinath cpu7_opp4: opp-1171200000 { 4962b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 4972b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 4982b6187abSThara Gopinath }; 4992b6187abSThara Gopinath 5002b6187abSThara Gopinath cpu7_opp5: opp-1286400000 { 5012b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 5022b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5032b6187abSThara Gopinath }; 5042b6187abSThara Gopinath 5052b6187abSThara Gopinath cpu7_opp6: opp-1401600000 { 5062b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 5072b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5082b6187abSThara Gopinath }; 5092b6187abSThara Gopinath 5102b6187abSThara Gopinath cpu7_opp7: opp-1497600000 { 5112b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 5122b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5132b6187abSThara Gopinath }; 5142b6187abSThara Gopinath 5152b6187abSThara Gopinath cpu7_opp8: opp-1612800000 { 5162b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 5172b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5182b6187abSThara Gopinath }; 5192b6187abSThara Gopinath 5202b6187abSThara Gopinath cpu7_opp9: opp-1708800000 { 5212b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 5222b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 5232b6187abSThara Gopinath }; 5242b6187abSThara Gopinath 5252b6187abSThara Gopinath cpu7_opp10: opp-1804800000 { 5262b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 5272b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 5282b6187abSThara Gopinath }; 5292b6187abSThara Gopinath 5302b6187abSThara Gopinath cpu7_opp11: opp-1920000000 { 5312b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 5322b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 5332b6187abSThara Gopinath }; 5342b6187abSThara Gopinath 5352b6187abSThara Gopinath cpu7_opp12: opp-2016000000 { 5362b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 5372b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 5382b6187abSThara Gopinath }; 5392b6187abSThara Gopinath 5402b6187abSThara Gopinath cpu7_opp13: opp-2131200000 { 5412b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 5422b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 5432b6187abSThara Gopinath }; 5442b6187abSThara Gopinath 5452b6187abSThara Gopinath cpu7_opp14: opp-2227200000 { 5462b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 5472b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5482b6187abSThara Gopinath }; 5492b6187abSThara Gopinath 5502b6187abSThara Gopinath cpu7_opp15: opp-2323200000 { 5512b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 5522b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5532b6187abSThara Gopinath }; 5542b6187abSThara Gopinath 5552b6187abSThara Gopinath cpu7_opp16: opp-2419200000 { 5562b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 5572b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5582b6187abSThara Gopinath }; 5592b6187abSThara Gopinath 5602b6187abSThara Gopinath cpu7_opp17: opp-2534400000 { 5612b6187abSThara Gopinath opp-hz = /bits/ 64 <2534400000>; 5622b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5632b6187abSThara Gopinath }; 5642b6187abSThara Gopinath 5652b6187abSThara Gopinath cpu7_opp18: opp-2649600000 { 5662b6187abSThara Gopinath opp-hz = /bits/ 64 <2649600000>; 5672b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5682b6187abSThara Gopinath }; 5692b6187abSThara Gopinath 5702b6187abSThara Gopinath cpu7_opp19: opp-2745600000 { 5712b6187abSThara Gopinath opp-hz = /bits/ 64 <2745600000>; 5722b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5732b6187abSThara Gopinath }; 5742b6187abSThara Gopinath 5752b6187abSThara Gopinath cpu7_opp20: opp-2841600000 { 5762b6187abSThara Gopinath opp-hz = /bits/ 64 <2841600000>; 5772b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5782b6187abSThara Gopinath }; 5792b6187abSThara Gopinath }; 5802b6187abSThara Gopinath 581e13c6d14SVinod Koul firmware { 582e13c6d14SVinod Koul scm: scm { 583e13c6d14SVinod Koul compatible = "qcom,scm-sm8150", "qcom,scm"; 584e13c6d14SVinod Koul #reset-cells = <1>; 585e13c6d14SVinod Koul }; 586e13c6d14SVinod Koul }; 587e13c6d14SVinod Koul 588d8cf9372SVinod Koul tcsr_mutex: hwlock { 589d8cf9372SVinod Koul compatible = "qcom,tcsr-mutex"; 590d8cf9372SVinod Koul syscon = <&tcsr_mutex_regs 0 0x1000>; 591d8cf9372SVinod Koul #hwlock-cells = <1>; 592d8cf9372SVinod Koul }; 593d8cf9372SVinod Koul 594e13c6d14SVinod Koul memory@80000000 { 595e13c6d14SVinod Koul device_type = "memory"; 596e13c6d14SVinod Koul /* We expect the bootloader to fill in the size */ 597e13c6d14SVinod Koul reg = <0x0 0x80000000 0x0 0x0>; 598e13c6d14SVinod Koul }; 599e13c6d14SVinod Koul 600d8cf9372SVinod Koul pmu { 601d8cf9372SVinod Koul compatible = "arm,armv8-pmuv3"; 602d8cf9372SVinod Koul interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 603d8cf9372SVinod Koul }; 604d8cf9372SVinod Koul 605e13c6d14SVinod Koul psci { 606e13c6d14SVinod Koul compatible = "arm,psci-1.0"; 607e13c6d14SVinod Koul method = "smc"; 608b2e3f897SDanny Lin 609b2e3f897SDanny Lin CPU_PD0: cpu0 { 610b2e3f897SDanny Lin #power-domain-cells = <0>; 611b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 612b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 613b2e3f897SDanny Lin }; 614b2e3f897SDanny Lin 615b2e3f897SDanny Lin CPU_PD1: cpu1 { 616b2e3f897SDanny Lin #power-domain-cells = <0>; 617b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 618b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 619b2e3f897SDanny Lin }; 620b2e3f897SDanny Lin 621b2e3f897SDanny Lin CPU_PD2: cpu2 { 622b2e3f897SDanny Lin #power-domain-cells = <0>; 623b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 624b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 625b2e3f897SDanny Lin }; 626b2e3f897SDanny Lin 627b2e3f897SDanny Lin CPU_PD3: cpu3 { 628b2e3f897SDanny Lin #power-domain-cells = <0>; 629b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 630b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 631b2e3f897SDanny Lin }; 632b2e3f897SDanny Lin 633b2e3f897SDanny Lin CPU_PD4: cpu4 { 634b2e3f897SDanny Lin #power-domain-cells = <0>; 635b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 636b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 637b2e3f897SDanny Lin }; 638b2e3f897SDanny Lin 639b2e3f897SDanny Lin CPU_PD5: cpu5 { 640b2e3f897SDanny Lin #power-domain-cells = <0>; 641b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 642b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 643b2e3f897SDanny Lin }; 644b2e3f897SDanny Lin 645b2e3f897SDanny Lin CPU_PD6: cpu6 { 646b2e3f897SDanny Lin #power-domain-cells = <0>; 647b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 648b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 649b2e3f897SDanny Lin }; 650b2e3f897SDanny Lin 651b2e3f897SDanny Lin CPU_PD7: cpu7 { 652b2e3f897SDanny Lin #power-domain-cells = <0>; 653b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 654b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 655b2e3f897SDanny Lin }; 656b2e3f897SDanny Lin 657b2e3f897SDanny Lin CLUSTER_PD: cpu-cluster0 { 658b2e3f897SDanny Lin #power-domain-cells = <0>; 659b2e3f897SDanny Lin domain-idle-states = <&CLUSTER_SLEEP_0>; 660b2e3f897SDanny Lin }; 661e13c6d14SVinod Koul }; 662e13c6d14SVinod Koul 663912c373aSVinod Koul reserved-memory { 664912c373aSVinod Koul #address-cells = <2>; 665912c373aSVinod Koul #size-cells = <2>; 666912c373aSVinod Koul ranges; 667912c373aSVinod Koul 668912c373aSVinod Koul hyp_mem: memory@85700000 { 669912c373aSVinod Koul reg = <0x0 0x85700000 0x0 0x600000>; 670912c373aSVinod Koul no-map; 671912c373aSVinod Koul }; 672912c373aSVinod Koul 673912c373aSVinod Koul xbl_mem: memory@85d00000 { 674912c373aSVinod Koul reg = <0x0 0x85d00000 0x0 0x140000>; 675912c373aSVinod Koul no-map; 676912c373aSVinod Koul }; 677912c373aSVinod Koul 678912c373aSVinod Koul aop_mem: memory@85f00000 { 679912c373aSVinod Koul reg = <0x0 0x85f00000 0x0 0x20000>; 680912c373aSVinod Koul no-map; 681912c373aSVinod Koul }; 682912c373aSVinod Koul 683912c373aSVinod Koul aop_cmd_db: memory@85f20000 { 684912c373aSVinod Koul compatible = "qcom,cmd-db"; 685912c373aSVinod Koul reg = <0x0 0x85f20000 0x0 0x20000>; 686912c373aSVinod Koul no-map; 687912c373aSVinod Koul }; 688912c373aSVinod Koul 689912c373aSVinod Koul smem_mem: memory@86000000 { 690912c373aSVinod Koul reg = <0x0 0x86000000 0x0 0x200000>; 691912c373aSVinod Koul no-map; 692912c373aSVinod Koul }; 693912c373aSVinod Koul 694912c373aSVinod Koul tz_mem: memory@86200000 { 695912c373aSVinod Koul reg = <0x0 0x86200000 0x0 0x3900000>; 696912c373aSVinod Koul no-map; 697912c373aSVinod Koul }; 698912c373aSVinod Koul 699912c373aSVinod Koul rmtfs_mem: memory@89b00000 { 700912c373aSVinod Koul compatible = "qcom,rmtfs-mem"; 701912c373aSVinod Koul reg = <0x0 0x89b00000 0x0 0x200000>; 702912c373aSVinod Koul no-map; 703912c373aSVinod Koul 704912c373aSVinod Koul qcom,client-id = <1>; 705912c373aSVinod Koul qcom,vmid = <15>; 706912c373aSVinod Koul }; 707912c373aSVinod Koul 708912c373aSVinod Koul camera_mem: memory@8b700000 { 709912c373aSVinod Koul reg = <0x0 0x8b700000 0x0 0x500000>; 710912c373aSVinod Koul no-map; 711912c373aSVinod Koul }; 712912c373aSVinod Koul 713912c373aSVinod Koul wlan_mem: memory@8bc00000 { 714912c373aSVinod Koul reg = <0x0 0x8bc00000 0x0 0x180000>; 715912c373aSVinod Koul no-map; 716912c373aSVinod Koul }; 717912c373aSVinod Koul 718912c373aSVinod Koul npu_mem: memory@8bd80000 { 719912c373aSVinod Koul reg = <0x0 0x8bd80000 0x0 0x80000>; 720912c373aSVinod Koul no-map; 721912c373aSVinod Koul }; 722912c373aSVinod Koul 723912c373aSVinod Koul adsp_mem: memory@8be00000 { 724912c373aSVinod Koul reg = <0x0 0x8be00000 0x0 0x1a00000>; 725912c373aSVinod Koul no-map; 726912c373aSVinod Koul }; 727912c373aSVinod Koul 728912c373aSVinod Koul mpss_mem: memory@8d800000 { 729912c373aSVinod Koul reg = <0x0 0x8d800000 0x0 0x9600000>; 730912c373aSVinod Koul no-map; 731912c373aSVinod Koul }; 732912c373aSVinod Koul 733912c373aSVinod Koul venus_mem: memory@96e00000 { 734912c373aSVinod Koul reg = <0x0 0x96e00000 0x0 0x500000>; 735912c373aSVinod Koul no-map; 736912c373aSVinod Koul }; 737912c373aSVinod Koul 738912c373aSVinod Koul slpi_mem: memory@97300000 { 739912c373aSVinod Koul reg = <0x0 0x97300000 0x0 0x1400000>; 740912c373aSVinod Koul no-map; 741912c373aSVinod Koul }; 742912c373aSVinod Koul 743912c373aSVinod Koul ipa_fw_mem: memory@98700000 { 744912c373aSVinod Koul reg = <0x0 0x98700000 0x0 0x10000>; 745912c373aSVinod Koul no-map; 746912c373aSVinod Koul }; 747912c373aSVinod Koul 748912c373aSVinod Koul ipa_gsi_mem: memory@98710000 { 749912c373aSVinod Koul reg = <0x0 0x98710000 0x0 0x5000>; 750912c373aSVinod Koul no-map; 751912c373aSVinod Koul }; 752912c373aSVinod Koul 753912c373aSVinod Koul gpu_mem: memory@98715000 { 754912c373aSVinod Koul reg = <0x0 0x98715000 0x0 0x2000>; 755912c373aSVinod Koul no-map; 756912c373aSVinod Koul }; 757912c373aSVinod Koul 758912c373aSVinod Koul spss_mem: memory@98800000 { 759912c373aSVinod Koul reg = <0x0 0x98800000 0x0 0x100000>; 760912c373aSVinod Koul no-map; 761912c373aSVinod Koul }; 762912c373aSVinod Koul 763912c373aSVinod Koul cdsp_mem: memory@98900000 { 764912c373aSVinod Koul reg = <0x0 0x98900000 0x0 0x1400000>; 765912c373aSVinod Koul no-map; 766912c373aSVinod Koul }; 767912c373aSVinod Koul 768912c373aSVinod Koul qseecom_mem: memory@9e400000 { 769912c373aSVinod Koul reg = <0x0 0x9e400000 0x0 0x1400000>; 770912c373aSVinod Koul no-map; 771912c373aSVinod Koul }; 772912c373aSVinod Koul }; 773912c373aSVinod Koul 774d8cf9372SVinod Koul smem { 775d8cf9372SVinod Koul compatible = "qcom,smem"; 776d8cf9372SVinod Koul memory-region = <&smem_mem>; 777d8cf9372SVinod Koul hwlocks = <&tcsr_mutex 3>; 778d8cf9372SVinod Koul }; 779d8cf9372SVinod Koul 78061025b81SSibi Sankar smp2p-cdsp { 78161025b81SSibi Sankar compatible = "qcom,smp2p"; 78261025b81SSibi Sankar qcom,smem = <94>, <432>; 78361025b81SSibi Sankar 78461025b81SSibi Sankar interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 78561025b81SSibi Sankar 78661025b81SSibi Sankar mboxes = <&apss_shared 6>; 78761025b81SSibi Sankar 78861025b81SSibi Sankar qcom,local-pid = <0>; 78961025b81SSibi Sankar qcom,remote-pid = <5>; 79061025b81SSibi Sankar 79161025b81SSibi Sankar cdsp_smp2p_out: master-kernel { 79261025b81SSibi Sankar qcom,entry-name = "master-kernel"; 79361025b81SSibi Sankar #qcom,smem-state-cells = <1>; 79461025b81SSibi Sankar }; 79561025b81SSibi Sankar 79661025b81SSibi Sankar cdsp_smp2p_in: slave-kernel { 79761025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 79861025b81SSibi Sankar 79961025b81SSibi Sankar interrupt-controller; 80061025b81SSibi Sankar #interrupt-cells = <2>; 80161025b81SSibi Sankar }; 80261025b81SSibi Sankar }; 80361025b81SSibi Sankar 80461025b81SSibi Sankar smp2p-lpass { 80561025b81SSibi Sankar compatible = "qcom,smp2p"; 80661025b81SSibi Sankar qcom,smem = <443>, <429>; 80761025b81SSibi Sankar 80861025b81SSibi Sankar interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 80961025b81SSibi Sankar 81061025b81SSibi Sankar mboxes = <&apss_shared 10>; 81161025b81SSibi Sankar 81261025b81SSibi Sankar qcom,local-pid = <0>; 81361025b81SSibi Sankar qcom,remote-pid = <2>; 81461025b81SSibi Sankar 81561025b81SSibi Sankar adsp_smp2p_out: master-kernel { 81661025b81SSibi Sankar qcom,entry-name = "master-kernel"; 81761025b81SSibi Sankar #qcom,smem-state-cells = <1>; 81861025b81SSibi Sankar }; 81961025b81SSibi Sankar 82061025b81SSibi Sankar adsp_smp2p_in: slave-kernel { 82161025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 82261025b81SSibi Sankar 82361025b81SSibi Sankar interrupt-controller; 82461025b81SSibi Sankar #interrupt-cells = <2>; 82561025b81SSibi Sankar }; 82661025b81SSibi Sankar }; 82761025b81SSibi Sankar 82861025b81SSibi Sankar smp2p-mpss { 82961025b81SSibi Sankar compatible = "qcom,smp2p"; 83061025b81SSibi Sankar qcom,smem = <435>, <428>; 83161025b81SSibi Sankar 83261025b81SSibi Sankar interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 83361025b81SSibi Sankar 83461025b81SSibi Sankar mboxes = <&apss_shared 14>; 83561025b81SSibi Sankar 83661025b81SSibi Sankar qcom,local-pid = <0>; 83761025b81SSibi Sankar qcom,remote-pid = <1>; 83861025b81SSibi Sankar 83961025b81SSibi Sankar modem_smp2p_out: master-kernel { 84061025b81SSibi Sankar qcom,entry-name = "master-kernel"; 84161025b81SSibi Sankar #qcom,smem-state-cells = <1>; 84261025b81SSibi Sankar }; 84361025b81SSibi Sankar 84461025b81SSibi Sankar modem_smp2p_in: slave-kernel { 84561025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 84661025b81SSibi Sankar 84761025b81SSibi Sankar interrupt-controller; 84861025b81SSibi Sankar #interrupt-cells = <2>; 84961025b81SSibi Sankar }; 85061025b81SSibi Sankar }; 85161025b81SSibi Sankar 85261025b81SSibi Sankar smp2p-slpi { 85361025b81SSibi Sankar compatible = "qcom,smp2p"; 85461025b81SSibi Sankar qcom,smem = <481>, <430>; 85561025b81SSibi Sankar 85661025b81SSibi Sankar interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 85761025b81SSibi Sankar 85861025b81SSibi Sankar mboxes = <&apss_shared 26>; 85961025b81SSibi Sankar 86061025b81SSibi Sankar qcom,local-pid = <0>; 86161025b81SSibi Sankar qcom,remote-pid = <3>; 86261025b81SSibi Sankar 86361025b81SSibi Sankar slpi_smp2p_out: master-kernel { 86461025b81SSibi Sankar qcom,entry-name = "master-kernel"; 86561025b81SSibi Sankar #qcom,smem-state-cells = <1>; 86661025b81SSibi Sankar }; 86761025b81SSibi Sankar 86861025b81SSibi Sankar slpi_smp2p_in: slave-kernel { 86961025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 87061025b81SSibi Sankar 87161025b81SSibi Sankar interrupt-controller; 87261025b81SSibi Sankar #interrupt-cells = <2>; 87361025b81SSibi Sankar }; 87461025b81SSibi Sankar }; 87561025b81SSibi Sankar 876e13c6d14SVinod Koul soc: soc@0 { 877e13c6d14SVinod Koul #address-cells = <2>; 878e13c6d14SVinod Koul #size-cells = <2>; 879e13c6d14SVinod Koul ranges = <0 0 0 0 0x10 0>; 880e13c6d14SVinod Koul dma-ranges = <0 0 0 0 0x10 0>; 881e13c6d14SVinod Koul compatible = "simple-bus"; 882e13c6d14SVinod Koul 883e13c6d14SVinod Koul gcc: clock-controller@100000 { 884e13c6d14SVinod Koul compatible = "qcom,gcc-sm8150"; 885e13c6d14SVinod Koul reg = <0x0 0x00100000 0x0 0x1f0000>; 886e13c6d14SVinod Koul #clock-cells = <1>; 887e13c6d14SVinod Koul #reset-cells = <1>; 888e13c6d14SVinod Koul #power-domain-cells = <1>; 889e13c6d14SVinod Koul clock-names = "bi_tcxo", 890e13c6d14SVinod Koul "sleep_clk"; 891e13c6d14SVinod Koul clocks = <&rpmhcc RPMH_CXO_CLK>, 892e13c6d14SVinod Koul <&sleep_clk>; 893e13c6d14SVinod Koul }; 894e13c6d14SVinod Koul 89505006290SFelipe Balbi gpi_dma0: dma-controller@800000 { 89605006290SFelipe Balbi compatible = "qcom,sm8150-gpi-dma"; 89705006290SFelipe Balbi reg = <0 0x800000 0 0x60000>; 89805006290SFelipe Balbi interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 89905006290SFelipe Balbi <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 90005006290SFelipe Balbi <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 90105006290SFelipe Balbi <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 90205006290SFelipe Balbi <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 90305006290SFelipe Balbi <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 90405006290SFelipe Balbi <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 90505006290SFelipe Balbi <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 90605006290SFelipe Balbi <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 90705006290SFelipe Balbi <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 90805006290SFelipe Balbi <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 90905006290SFelipe Balbi <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 91005006290SFelipe Balbi <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 91105006290SFelipe Balbi dma-channels = <13>; 91205006290SFelipe Balbi dma-channel-mask = <0xfa>; 91305006290SFelipe Balbi iommus = <&apps_smmu 0x00d6 0x0>; 91405006290SFelipe Balbi #dma-cells = <3>; 91505006290SFelipe Balbi status = "disabled"; 91605006290SFelipe Balbi }; 91705006290SFelipe Balbi 9189cf3ebd1SCaleb Connolly qupv3_id_0: geniqup@8c0000 { 9199cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 9209cf3ebd1SCaleb Connolly reg = <0x0 0x008c0000 0x0 0x6000>; 9219cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 9229cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 9239cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 9249cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0xc3 0x0>; 9259cf3ebd1SCaleb Connolly #address-cells = <2>; 9269cf3ebd1SCaleb Connolly #size-cells = <2>; 9279cf3ebd1SCaleb Connolly ranges; 9289cf3ebd1SCaleb Connolly status = "disabled"; 92981bee695SCaleb Connolly 93081bee695SCaleb Connolly i2c0: i2c@880000 { 93181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 93281bee695SCaleb Connolly reg = <0 0x00880000 0 0x4000>; 93381bee695SCaleb Connolly clock-names = "se"; 93481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 93581bee695SCaleb Connolly pinctrl-names = "default"; 93681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c0_default>; 93781bee695SCaleb Connolly interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 93881bee695SCaleb Connolly #address-cells = <1>; 93981bee695SCaleb Connolly #size-cells = <0>; 94081bee695SCaleb Connolly status = "disabled"; 94181bee695SCaleb Connolly }; 94281bee695SCaleb Connolly 943129e1c96SFelipe Balbi spi0: spi@880000 { 944129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 945129e1c96SFelipe Balbi reg = <0 0x880000 0 0x4000>; 946129e1c96SFelipe Balbi reg-names = "se"; 947129e1c96SFelipe Balbi clock-names = "se"; 948129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 949129e1c96SFelipe Balbi pinctrl-names = "default"; 950129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi0_default>; 951129e1c96SFelipe Balbi interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 952129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 953129e1c96SFelipe Balbi #address-cells = <1>; 954129e1c96SFelipe Balbi #size-cells = <0>; 955129e1c96SFelipe Balbi status = "disabled"; 956129e1c96SFelipe Balbi }; 957129e1c96SFelipe Balbi 95881bee695SCaleb Connolly i2c1: i2c@884000 { 95981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 96081bee695SCaleb Connolly reg = <0 0x00884000 0 0x4000>; 96181bee695SCaleb Connolly clock-names = "se"; 96281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 96381bee695SCaleb Connolly pinctrl-names = "default"; 96481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c1_default>; 96581bee695SCaleb Connolly interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 96681bee695SCaleb Connolly #address-cells = <1>; 96781bee695SCaleb Connolly #size-cells = <0>; 96881bee695SCaleb Connolly status = "disabled"; 96981bee695SCaleb Connolly }; 97081bee695SCaleb Connolly 971129e1c96SFelipe Balbi spi1: spi@884000 { 972129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 973129e1c96SFelipe Balbi reg = <0 0x884000 0 0x4000>; 974129e1c96SFelipe Balbi reg-names = "se"; 975129e1c96SFelipe Balbi clock-names = "se"; 976129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 977129e1c96SFelipe Balbi pinctrl-names = "default"; 978129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi1_default>; 979129e1c96SFelipe Balbi interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 980129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 981129e1c96SFelipe Balbi #address-cells = <1>; 982129e1c96SFelipe Balbi #size-cells = <0>; 983129e1c96SFelipe Balbi status = "disabled"; 984129e1c96SFelipe Balbi }; 985129e1c96SFelipe Balbi 98681bee695SCaleb Connolly i2c2: i2c@888000 { 98781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 98881bee695SCaleb Connolly reg = <0 0x00888000 0 0x4000>; 98981bee695SCaleb Connolly clock-names = "se"; 99081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 99181bee695SCaleb Connolly pinctrl-names = "default"; 99281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c2_default>; 99381bee695SCaleb Connolly interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 99481bee695SCaleb Connolly #address-cells = <1>; 99581bee695SCaleb Connolly #size-cells = <0>; 99681bee695SCaleb Connolly status = "disabled"; 99781bee695SCaleb Connolly }; 99881bee695SCaleb Connolly 999129e1c96SFelipe Balbi spi2: spi@888000 { 1000129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1001129e1c96SFelipe Balbi reg = <0 0x888000 0 0x4000>; 1002129e1c96SFelipe Balbi reg-names = "se"; 1003129e1c96SFelipe Balbi clock-names = "se"; 1004129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1005129e1c96SFelipe Balbi pinctrl-names = "default"; 1006129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi2_default>; 1007129e1c96SFelipe Balbi interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1008129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1009129e1c96SFelipe Balbi #address-cells = <1>; 1010129e1c96SFelipe Balbi #size-cells = <0>; 1011129e1c96SFelipe Balbi status = "disabled"; 1012129e1c96SFelipe Balbi }; 1013129e1c96SFelipe Balbi 101481bee695SCaleb Connolly i2c3: i2c@88c000 { 101581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 101681bee695SCaleb Connolly reg = <0 0x0088c000 0 0x4000>; 101781bee695SCaleb Connolly clock-names = "se"; 101881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 101981bee695SCaleb Connolly pinctrl-names = "default"; 102081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c3_default>; 102181bee695SCaleb Connolly interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 102281bee695SCaleb Connolly #address-cells = <1>; 102381bee695SCaleb Connolly #size-cells = <0>; 102481bee695SCaleb Connolly status = "disabled"; 102581bee695SCaleb Connolly }; 102681bee695SCaleb Connolly 1027129e1c96SFelipe Balbi spi3: spi@88c000 { 1028129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1029129e1c96SFelipe Balbi reg = <0 0x88c000 0 0x4000>; 1030129e1c96SFelipe Balbi reg-names = "se"; 1031129e1c96SFelipe Balbi clock-names = "se"; 1032129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1033129e1c96SFelipe Balbi pinctrl-names = "default"; 1034129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi3_default>; 1035129e1c96SFelipe Balbi interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1036129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1037129e1c96SFelipe Balbi #address-cells = <1>; 1038129e1c96SFelipe Balbi #size-cells = <0>; 1039129e1c96SFelipe Balbi status = "disabled"; 1040129e1c96SFelipe Balbi }; 1041129e1c96SFelipe Balbi 104281bee695SCaleb Connolly i2c4: i2c@890000 { 104381bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 104481bee695SCaleb Connolly reg = <0 0x00890000 0 0x4000>; 104581bee695SCaleb Connolly clock-names = "se"; 104681bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 104781bee695SCaleb Connolly pinctrl-names = "default"; 104881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c4_default>; 104981bee695SCaleb Connolly interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 105081bee695SCaleb Connolly #address-cells = <1>; 105181bee695SCaleb Connolly #size-cells = <0>; 105281bee695SCaleb Connolly status = "disabled"; 105381bee695SCaleb Connolly }; 105481bee695SCaleb Connolly 1055129e1c96SFelipe Balbi spi4: spi@890000 { 1056129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1057129e1c96SFelipe Balbi reg = <0 0x890000 0 0x4000>; 1058129e1c96SFelipe Balbi reg-names = "se"; 1059129e1c96SFelipe Balbi clock-names = "se"; 1060129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1061129e1c96SFelipe Balbi pinctrl-names = "default"; 1062129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi4_default>; 1063129e1c96SFelipe Balbi interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1064129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1065129e1c96SFelipe Balbi #address-cells = <1>; 1066129e1c96SFelipe Balbi #size-cells = <0>; 1067129e1c96SFelipe Balbi status = "disabled"; 1068129e1c96SFelipe Balbi }; 1069129e1c96SFelipe Balbi 107081bee695SCaleb Connolly i2c5: i2c@894000 { 107181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 107281bee695SCaleb Connolly reg = <0 0x00894000 0 0x4000>; 107381bee695SCaleb Connolly clock-names = "se"; 107481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 107581bee695SCaleb Connolly pinctrl-names = "default"; 107681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c5_default>; 107781bee695SCaleb Connolly interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 107881bee695SCaleb Connolly #address-cells = <1>; 107981bee695SCaleb Connolly #size-cells = <0>; 108081bee695SCaleb Connolly status = "disabled"; 108181bee695SCaleb Connolly }; 108281bee695SCaleb Connolly 1083129e1c96SFelipe Balbi spi5: spi@894000 { 1084129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1085129e1c96SFelipe Balbi reg = <0 0x894000 0 0x4000>; 1086129e1c96SFelipe Balbi reg-names = "se"; 1087129e1c96SFelipe Balbi clock-names = "se"; 1088129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1089129e1c96SFelipe Balbi pinctrl-names = "default"; 1090129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi5_default>; 1091129e1c96SFelipe Balbi interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1092129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1093129e1c96SFelipe Balbi #address-cells = <1>; 1094129e1c96SFelipe Balbi #size-cells = <0>; 1095129e1c96SFelipe Balbi status = "disabled"; 1096129e1c96SFelipe Balbi }; 1097129e1c96SFelipe Balbi 109881bee695SCaleb Connolly i2c6: i2c@898000 { 109981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 110081bee695SCaleb Connolly reg = <0 0x00898000 0 0x4000>; 110181bee695SCaleb Connolly clock-names = "se"; 110281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 110381bee695SCaleb Connolly pinctrl-names = "default"; 110481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c6_default>; 110581bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 110681bee695SCaleb Connolly #address-cells = <1>; 110781bee695SCaleb Connolly #size-cells = <0>; 110881bee695SCaleb Connolly status = "disabled"; 110981bee695SCaleb Connolly }; 111081bee695SCaleb Connolly 1111129e1c96SFelipe Balbi spi6: spi@898000 { 1112129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1113129e1c96SFelipe Balbi reg = <0 0x898000 0 0x4000>; 1114129e1c96SFelipe Balbi reg-names = "se"; 1115129e1c96SFelipe Balbi clock-names = "se"; 1116129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1117129e1c96SFelipe Balbi pinctrl-names = "default"; 1118129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi6_default>; 1119129e1c96SFelipe Balbi interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1120129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1121129e1c96SFelipe Balbi #address-cells = <1>; 1122129e1c96SFelipe Balbi #size-cells = <0>; 1123129e1c96SFelipe Balbi status = "disabled"; 1124129e1c96SFelipe Balbi }; 1125129e1c96SFelipe Balbi 112681bee695SCaleb Connolly i2c7: i2c@89c000 { 112781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 112881bee695SCaleb Connolly reg = <0 0x0089c000 0 0x4000>; 112981bee695SCaleb Connolly clock-names = "se"; 113081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 113181bee695SCaleb Connolly pinctrl-names = "default"; 113281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c7_default>; 113381bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 113481bee695SCaleb Connolly #address-cells = <1>; 113581bee695SCaleb Connolly #size-cells = <0>; 113681bee695SCaleb Connolly status = "disabled"; 113781bee695SCaleb Connolly }; 113881bee695SCaleb Connolly 1139129e1c96SFelipe Balbi spi7: spi@89c000 { 1140129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1141129e1c96SFelipe Balbi reg = <0 0x89c000 0 0x4000>; 1142129e1c96SFelipe Balbi reg-names = "se"; 1143129e1c96SFelipe Balbi clock-names = "se"; 1144129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1145129e1c96SFelipe Balbi pinctrl-names = "default"; 1146129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi7_default>; 1147129e1c96SFelipe Balbi interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1148129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1149129e1c96SFelipe Balbi #address-cells = <1>; 1150129e1c96SFelipe Balbi #size-cells = <0>; 1151129e1c96SFelipe Balbi status = "disabled"; 1152129e1c96SFelipe Balbi }; 11539cf3ebd1SCaleb Connolly }; 11549cf3ebd1SCaleb Connolly 115505006290SFelipe Balbi gpi_dma1: dma-controller@a00000 { 115605006290SFelipe Balbi compatible = "qcom,sm8150-gpi-dma"; 115705006290SFelipe Balbi reg = <0 0xa00000 0 0x60000>; 115805006290SFelipe Balbi interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 115905006290SFelipe Balbi <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 116005006290SFelipe Balbi <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 116105006290SFelipe Balbi <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 116205006290SFelipe Balbi <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 116305006290SFelipe Balbi <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 116405006290SFelipe Balbi <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 116505006290SFelipe Balbi <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 116605006290SFelipe Balbi <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 116705006290SFelipe Balbi <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 116805006290SFelipe Balbi <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 116905006290SFelipe Balbi <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 117005006290SFelipe Balbi <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 117105006290SFelipe Balbi dma-channels = <13>; 117205006290SFelipe Balbi dma-channel-mask = <0xfa>; 117305006290SFelipe Balbi iommus = <&apps_smmu 0x0616 0x0>; 117405006290SFelipe Balbi #dma-cells = <3>; 117505006290SFelipe Balbi status = "disabled"; 117605006290SFelipe Balbi }; 117705006290SFelipe Balbi 1178e13c6d14SVinod Koul qupv3_id_1: geniqup@ac0000 { 1179e13c6d14SVinod Koul compatible = "qcom,geni-se-qup"; 1180e13c6d14SVinod Koul reg = <0x0 0x00ac0000 0x0 0x6000>; 1181e13c6d14SVinod Koul clock-names = "m-ahb", "s-ahb"; 1182d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1183d6f55763SVinod Koul <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 11849cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x603 0x0>; 1185e13c6d14SVinod Koul #address-cells = <2>; 1186e13c6d14SVinod Koul #size-cells = <2>; 1187e13c6d14SVinod Koul ranges; 1188e13c6d14SVinod Koul status = "disabled"; 1189e13c6d14SVinod Koul 119081bee695SCaleb Connolly i2c8: i2c@a80000 { 119181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 119281bee695SCaleb Connolly reg = <0 0x00a80000 0 0x4000>; 119381bee695SCaleb Connolly clock-names = "se"; 119481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 119581bee695SCaleb Connolly pinctrl-names = "default"; 119681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c8_default>; 119781bee695SCaleb Connolly interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 119881bee695SCaleb Connolly #address-cells = <1>; 119981bee695SCaleb Connolly #size-cells = <0>; 120081bee695SCaleb Connolly status = "disabled"; 120181bee695SCaleb Connolly }; 120281bee695SCaleb Connolly 1203129e1c96SFelipe Balbi spi8: spi@a80000 { 1204129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1205129e1c96SFelipe Balbi reg = <0 0xa80000 0 0x4000>; 1206129e1c96SFelipe Balbi reg-names = "se"; 1207129e1c96SFelipe Balbi clock-names = "se"; 1208129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1209129e1c96SFelipe Balbi pinctrl-names = "default"; 1210129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi8_default>; 1211129e1c96SFelipe Balbi interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1212129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1213129e1c96SFelipe Balbi #address-cells = <1>; 1214129e1c96SFelipe Balbi #size-cells = <0>; 1215129e1c96SFelipe Balbi status = "disabled"; 1216129e1c96SFelipe Balbi }; 1217129e1c96SFelipe Balbi 121881bee695SCaleb Connolly i2c9: i2c@a84000 { 121981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 122081bee695SCaleb Connolly reg = <0 0x00a84000 0 0x4000>; 122181bee695SCaleb Connolly clock-names = "se"; 122281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 122381bee695SCaleb Connolly pinctrl-names = "default"; 122481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c9_default>; 122581bee695SCaleb Connolly interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 122681bee695SCaleb Connolly #address-cells = <1>; 122781bee695SCaleb Connolly #size-cells = <0>; 122881bee695SCaleb Connolly status = "disabled"; 122981bee695SCaleb Connolly }; 123081bee695SCaleb Connolly 1231129e1c96SFelipe Balbi spi9: spi@a84000 { 1232129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1233129e1c96SFelipe Balbi reg = <0 0xa84000 0 0x4000>; 1234129e1c96SFelipe Balbi reg-names = "se"; 1235129e1c96SFelipe Balbi clock-names = "se"; 1236129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1237129e1c96SFelipe Balbi pinctrl-names = "default"; 1238129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi9_default>; 1239129e1c96SFelipe Balbi interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1240129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1241129e1c96SFelipe Balbi #address-cells = <1>; 1242129e1c96SFelipe Balbi #size-cells = <0>; 1243129e1c96SFelipe Balbi status = "disabled"; 1244129e1c96SFelipe Balbi }; 1245129e1c96SFelipe Balbi 124681bee695SCaleb Connolly i2c10: i2c@a88000 { 124781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 124881bee695SCaleb Connolly reg = <0 0x00a88000 0 0x4000>; 124981bee695SCaleb Connolly clock-names = "se"; 125081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 125181bee695SCaleb Connolly pinctrl-names = "default"; 125281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c10_default>; 125381bee695SCaleb Connolly interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 125481bee695SCaleb Connolly #address-cells = <1>; 125581bee695SCaleb Connolly #size-cells = <0>; 125681bee695SCaleb Connolly status = "disabled"; 125781bee695SCaleb Connolly }; 125881bee695SCaleb Connolly 1259129e1c96SFelipe Balbi spi10: spi@a88000 { 1260129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1261129e1c96SFelipe Balbi reg = <0 0xa88000 0 0x4000>; 1262129e1c96SFelipe Balbi reg-names = "se"; 1263129e1c96SFelipe Balbi clock-names = "se"; 1264129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1265129e1c96SFelipe Balbi pinctrl-names = "default"; 1266129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi10_default>; 1267129e1c96SFelipe Balbi interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1268129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1269129e1c96SFelipe Balbi #address-cells = <1>; 1270129e1c96SFelipe Balbi #size-cells = <0>; 1271129e1c96SFelipe Balbi status = "disabled"; 1272129e1c96SFelipe Balbi }; 1273129e1c96SFelipe Balbi 127481bee695SCaleb Connolly i2c11: i2c@a8c000 { 127581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 127681bee695SCaleb Connolly reg = <0 0x00a8c000 0 0x4000>; 127781bee695SCaleb Connolly clock-names = "se"; 127881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 127981bee695SCaleb Connolly pinctrl-names = "default"; 128081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c11_default>; 128181bee695SCaleb Connolly interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 128281bee695SCaleb Connolly #address-cells = <1>; 128381bee695SCaleb Connolly #size-cells = <0>; 128481bee695SCaleb Connolly status = "disabled"; 128581bee695SCaleb Connolly }; 128681bee695SCaleb Connolly 1287129e1c96SFelipe Balbi spi11: spi@a8c000 { 1288129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1289129e1c96SFelipe Balbi reg = <0 0xa8c000 0 0x4000>; 1290129e1c96SFelipe Balbi reg-names = "se"; 1291129e1c96SFelipe Balbi clock-names = "se"; 1292129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1293129e1c96SFelipe Balbi pinctrl-names = "default"; 1294129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi11_default>; 1295129e1c96SFelipe Balbi interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1296129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1297129e1c96SFelipe Balbi #address-cells = <1>; 1298129e1c96SFelipe Balbi #size-cells = <0>; 1299129e1c96SFelipe Balbi status = "disabled"; 1300129e1c96SFelipe Balbi }; 1301129e1c96SFelipe Balbi 1302e13c6d14SVinod Koul uart2: serial@a90000 { 1303e13c6d14SVinod Koul compatible = "qcom,geni-debug-uart"; 1304e13c6d14SVinod Koul reg = <0x0 0x00a90000 0x0 0x4000>; 1305e13c6d14SVinod Koul clock-names = "se"; 1306d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1307e13c6d14SVinod Koul interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1308e13c6d14SVinod Koul status = "disabled"; 1309e13c6d14SVinod Koul }; 131081bee695SCaleb Connolly 131181bee695SCaleb Connolly i2c12: i2c@a90000 { 131281bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 131381bee695SCaleb Connolly reg = <0 0x00a90000 0 0x4000>; 131481bee695SCaleb Connolly clock-names = "se"; 131581bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 131681bee695SCaleb Connolly pinctrl-names = "default"; 131781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c12_default>; 131881bee695SCaleb Connolly interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 131981bee695SCaleb Connolly #address-cells = <1>; 132081bee695SCaleb Connolly #size-cells = <0>; 132181bee695SCaleb Connolly status = "disabled"; 132281bee695SCaleb Connolly }; 132381bee695SCaleb Connolly 1324129e1c96SFelipe Balbi spi12: spi@a90000 { 1325129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1326129e1c96SFelipe Balbi reg = <0 0xa90000 0 0x4000>; 1327129e1c96SFelipe Balbi reg-names = "se"; 1328129e1c96SFelipe Balbi clock-names = "se"; 1329129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1330129e1c96SFelipe Balbi pinctrl-names = "default"; 1331129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi12_default>; 1332129e1c96SFelipe Balbi interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1333129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1334129e1c96SFelipe Balbi #address-cells = <1>; 1335129e1c96SFelipe Balbi #size-cells = <0>; 1336129e1c96SFelipe Balbi status = "disabled"; 1337129e1c96SFelipe Balbi }; 1338129e1c96SFelipe Balbi 133981bee695SCaleb Connolly i2c16: i2c@94000 { 134081bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 134181bee695SCaleb Connolly reg = <0 0x0094000 0 0x4000>; 134281bee695SCaleb Connolly clock-names = "se"; 134381bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 134481bee695SCaleb Connolly pinctrl-names = "default"; 134581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c16_default>; 134681bee695SCaleb Connolly interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 134781bee695SCaleb Connolly #address-cells = <1>; 134881bee695SCaleb Connolly #size-cells = <0>; 134981bee695SCaleb Connolly status = "disabled"; 135081bee695SCaleb Connolly }; 1351129e1c96SFelipe Balbi 1352129e1c96SFelipe Balbi spi16: spi@a94000 { 1353129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1354129e1c96SFelipe Balbi reg = <0 0xa94000 0 0x4000>; 1355129e1c96SFelipe Balbi reg-names = "se"; 1356129e1c96SFelipe Balbi clock-names = "se"; 1357129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1358129e1c96SFelipe Balbi pinctrl-names = "default"; 1359129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi16_default>; 1360129e1c96SFelipe Balbi interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1361129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1362129e1c96SFelipe Balbi #address-cells = <1>; 1363129e1c96SFelipe Balbi #size-cells = <0>; 1364129e1c96SFelipe Balbi status = "disabled"; 1365129e1c96SFelipe Balbi }; 1366e13c6d14SVinod Koul }; 1367e13c6d14SVinod Koul 136805006290SFelipe Balbi gpi_dma2: dma-controller@c00000 { 136905006290SFelipe Balbi compatible = "qcom,sm8150-gpi-dma"; 137005006290SFelipe Balbi reg = <0 0xc00000 0 0x60000>; 137105006290SFelipe Balbi interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 137205006290SFelipe Balbi <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 137305006290SFelipe Balbi <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 137405006290SFelipe Balbi <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 137505006290SFelipe Balbi <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 137605006290SFelipe Balbi <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 137705006290SFelipe Balbi <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 137805006290SFelipe Balbi <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 137905006290SFelipe Balbi <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 138005006290SFelipe Balbi <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 138105006290SFelipe Balbi <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 138205006290SFelipe Balbi <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 138305006290SFelipe Balbi <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 138405006290SFelipe Balbi dma-channels = <13>; 138505006290SFelipe Balbi dma-channel-mask = <0xfa>; 138605006290SFelipe Balbi iommus = <&apps_smmu 0x07b6 0x0>; 138705006290SFelipe Balbi #dma-cells = <3>; 138805006290SFelipe Balbi status = "disabled"; 138905006290SFelipe Balbi }; 139005006290SFelipe Balbi 13919cf3ebd1SCaleb Connolly qupv3_id_2: geniqup@cc0000 { 13929cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 13939cf3ebd1SCaleb Connolly reg = <0x0 0x00cc0000 0x0 0x6000>; 13949cf3ebd1SCaleb Connolly 13959cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 13969cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 13979cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 13989cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x7a3 0x0>; 13999cf3ebd1SCaleb Connolly #address-cells = <2>; 14009cf3ebd1SCaleb Connolly #size-cells = <2>; 14019cf3ebd1SCaleb Connolly ranges; 14029cf3ebd1SCaleb Connolly status = "disabled"; 140381bee695SCaleb Connolly 140481bee695SCaleb Connolly i2c17: i2c@c80000 { 140581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 140681bee695SCaleb Connolly reg = <0 0x00c80000 0 0x4000>; 140781bee695SCaleb Connolly clock-names = "se"; 140881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 140981bee695SCaleb Connolly pinctrl-names = "default"; 141081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c17_default>; 141181bee695SCaleb Connolly interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 141281bee695SCaleb Connolly #address-cells = <1>; 141381bee695SCaleb Connolly #size-cells = <0>; 141481bee695SCaleb Connolly status = "disabled"; 141581bee695SCaleb Connolly }; 141681bee695SCaleb Connolly 1417129e1c96SFelipe Balbi spi17: spi@c80000 { 1418129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1419129e1c96SFelipe Balbi reg = <0 0xc80000 0 0x4000>; 1420129e1c96SFelipe Balbi reg-names = "se"; 1421129e1c96SFelipe Balbi clock-names = "se"; 1422129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1423129e1c96SFelipe Balbi pinctrl-names = "default"; 1424129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi17_default>; 1425129e1c96SFelipe Balbi interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1426129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1427129e1c96SFelipe Balbi #address-cells = <1>; 1428129e1c96SFelipe Balbi #size-cells = <0>; 1429129e1c96SFelipe Balbi status = "disabled"; 1430129e1c96SFelipe Balbi }; 1431129e1c96SFelipe Balbi 143281bee695SCaleb Connolly i2c18: i2c@c84000 { 143381bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 143481bee695SCaleb Connolly reg = <0 0x00c84000 0 0x4000>; 143581bee695SCaleb Connolly clock-names = "se"; 143681bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 143781bee695SCaleb Connolly pinctrl-names = "default"; 143881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c18_default>; 143981bee695SCaleb Connolly interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 144081bee695SCaleb Connolly #address-cells = <1>; 144181bee695SCaleb Connolly #size-cells = <0>; 144281bee695SCaleb Connolly status = "disabled"; 144381bee695SCaleb Connolly }; 144481bee695SCaleb Connolly 1445129e1c96SFelipe Balbi spi18: spi@c84000 { 1446129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1447129e1c96SFelipe Balbi reg = <0 0xc84000 0 0x4000>; 1448129e1c96SFelipe Balbi reg-names = "se"; 1449129e1c96SFelipe Balbi clock-names = "se"; 1450129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1451129e1c96SFelipe Balbi pinctrl-names = "default"; 1452129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi18_default>; 1453129e1c96SFelipe Balbi interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1454129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1455129e1c96SFelipe Balbi #address-cells = <1>; 1456129e1c96SFelipe Balbi #size-cells = <0>; 1457129e1c96SFelipe Balbi status = "disabled"; 1458129e1c96SFelipe Balbi }; 1459129e1c96SFelipe Balbi 146081bee695SCaleb Connolly i2c19: i2c@c88000 { 146181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 146281bee695SCaleb Connolly reg = <0 0x00c88000 0 0x4000>; 146381bee695SCaleb Connolly clock-names = "se"; 146481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 146581bee695SCaleb Connolly pinctrl-names = "default"; 146681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c19_default>; 146781bee695SCaleb Connolly interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 146881bee695SCaleb Connolly #address-cells = <1>; 146981bee695SCaleb Connolly #size-cells = <0>; 147081bee695SCaleb Connolly status = "disabled"; 147181bee695SCaleb Connolly }; 147281bee695SCaleb Connolly 1473129e1c96SFelipe Balbi spi19: spi@c88000 { 1474129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1475129e1c96SFelipe Balbi reg = <0 0xc88000 0 0x4000>; 1476129e1c96SFelipe Balbi reg-names = "se"; 1477129e1c96SFelipe Balbi clock-names = "se"; 1478129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1479129e1c96SFelipe Balbi pinctrl-names = "default"; 1480129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi19_default>; 1481129e1c96SFelipe Balbi interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1482129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1483129e1c96SFelipe Balbi #address-cells = <1>; 1484129e1c96SFelipe Balbi #size-cells = <0>; 1485129e1c96SFelipe Balbi status = "disabled"; 1486129e1c96SFelipe Balbi }; 1487129e1c96SFelipe Balbi 148881bee695SCaleb Connolly i2c13: i2c@c8c000 { 148981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 149081bee695SCaleb Connolly reg = <0 0x00c8c000 0 0x4000>; 149181bee695SCaleb Connolly clock-names = "se"; 149281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 149381bee695SCaleb Connolly pinctrl-names = "default"; 149481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c13_default>; 149581bee695SCaleb Connolly interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 149681bee695SCaleb Connolly #address-cells = <1>; 149781bee695SCaleb Connolly #size-cells = <0>; 149881bee695SCaleb Connolly status = "disabled"; 149981bee695SCaleb Connolly }; 150081bee695SCaleb Connolly 1501129e1c96SFelipe Balbi spi13: spi@c8c000 { 1502129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1503129e1c96SFelipe Balbi reg = <0 0xc8c000 0 0x4000>; 1504129e1c96SFelipe Balbi reg-names = "se"; 1505129e1c96SFelipe Balbi clock-names = "se"; 1506129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1507129e1c96SFelipe Balbi pinctrl-names = "default"; 1508129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi13_default>; 1509129e1c96SFelipe Balbi interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1510129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1511129e1c96SFelipe Balbi #address-cells = <1>; 1512129e1c96SFelipe Balbi #size-cells = <0>; 1513129e1c96SFelipe Balbi status = "disabled"; 1514129e1c96SFelipe Balbi }; 1515129e1c96SFelipe Balbi 151681bee695SCaleb Connolly i2c14: i2c@c90000 { 151781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 151881bee695SCaleb Connolly reg = <0 0x00c90000 0 0x4000>; 151981bee695SCaleb Connolly clock-names = "se"; 152081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 152181bee695SCaleb Connolly pinctrl-names = "default"; 152281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c14_default>; 152381bee695SCaleb Connolly interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 152481bee695SCaleb Connolly #address-cells = <1>; 152581bee695SCaleb Connolly #size-cells = <0>; 152681bee695SCaleb Connolly status = "disabled"; 152781bee695SCaleb Connolly }; 152881bee695SCaleb Connolly 1529129e1c96SFelipe Balbi spi14: spi@c90000 { 1530129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1531129e1c96SFelipe Balbi reg = <0 0xc90000 0 0x4000>; 1532129e1c96SFelipe Balbi reg-names = "se"; 1533129e1c96SFelipe Balbi clock-names = "se"; 1534129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1535129e1c96SFelipe Balbi pinctrl-names = "default"; 1536129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi14_default>; 1537129e1c96SFelipe Balbi interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1538129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1539129e1c96SFelipe Balbi #address-cells = <1>; 1540129e1c96SFelipe Balbi #size-cells = <0>; 1541129e1c96SFelipe Balbi status = "disabled"; 1542129e1c96SFelipe Balbi }; 1543129e1c96SFelipe Balbi 154481bee695SCaleb Connolly i2c15: i2c@c94000 { 154581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 154681bee695SCaleb Connolly reg = <0 0x00c94000 0 0x4000>; 154781bee695SCaleb Connolly clock-names = "se"; 154881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 154981bee695SCaleb Connolly pinctrl-names = "default"; 155081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c15_default>; 155181bee695SCaleb Connolly interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 155281bee695SCaleb Connolly #address-cells = <1>; 155381bee695SCaleb Connolly #size-cells = <0>; 155481bee695SCaleb Connolly status = "disabled"; 155581bee695SCaleb Connolly }; 1556129e1c96SFelipe Balbi 1557129e1c96SFelipe Balbi spi15: spi@c94000 { 1558129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1559129e1c96SFelipe Balbi reg = <0 0xc94000 0 0x4000>; 1560129e1c96SFelipe Balbi reg-names = "se"; 1561129e1c96SFelipe Balbi clock-names = "se"; 1562129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1563129e1c96SFelipe Balbi pinctrl-names = "default"; 1564129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi15_default>; 1565129e1c96SFelipe Balbi interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1566129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1567129e1c96SFelipe Balbi #address-cells = <1>; 1568129e1c96SFelipe Balbi #size-cells = <0>; 1569129e1c96SFelipe Balbi status = "disabled"; 1570129e1c96SFelipe Balbi }; 15719cf3ebd1SCaleb Connolly }; 15729cf3ebd1SCaleb Connolly 157371a2fc6eSJonathan Marek config_noc: interconnect@1500000 { 157471a2fc6eSJonathan Marek compatible = "qcom,sm8150-config-noc"; 157571a2fc6eSJonathan Marek reg = <0 0x01500000 0 0x7400>; 157671a2fc6eSJonathan Marek #interconnect-cells = <1>; 157771a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 157871a2fc6eSJonathan Marek }; 157971a2fc6eSJonathan Marek 158071a2fc6eSJonathan Marek system_noc: interconnect@1620000 { 158171a2fc6eSJonathan Marek compatible = "qcom,sm8150-system-noc"; 158271a2fc6eSJonathan Marek reg = <0 0x01620000 0 0x19400>; 158371a2fc6eSJonathan Marek #interconnect-cells = <1>; 158471a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 158571a2fc6eSJonathan Marek }; 158671a2fc6eSJonathan Marek 158771a2fc6eSJonathan Marek mc_virt: interconnect@163a000 { 158871a2fc6eSJonathan Marek compatible = "qcom,sm8150-mc-virt"; 158971a2fc6eSJonathan Marek reg = <0 0x0163a000 0 0x1000>; 159071a2fc6eSJonathan Marek #interconnect-cells = <1>; 159171a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 159271a2fc6eSJonathan Marek }; 159371a2fc6eSJonathan Marek 159471a2fc6eSJonathan Marek aggre1_noc: interconnect@16e0000 { 159571a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre1-noc"; 159671a2fc6eSJonathan Marek reg = <0 0x016e0000 0 0xd080>; 159771a2fc6eSJonathan Marek #interconnect-cells = <1>; 159871a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 159971a2fc6eSJonathan Marek }; 160071a2fc6eSJonathan Marek 160171a2fc6eSJonathan Marek aggre2_noc: interconnect@1700000 { 160271a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre2-noc"; 160371a2fc6eSJonathan Marek reg = <0 0x01700000 0 0x20000>; 160471a2fc6eSJonathan Marek #interconnect-cells = <1>; 160571a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 160671a2fc6eSJonathan Marek }; 160771a2fc6eSJonathan Marek 160871a2fc6eSJonathan Marek compute_noc: interconnect@1720000 { 160971a2fc6eSJonathan Marek compatible = "qcom,sm8150-compute-noc"; 161071a2fc6eSJonathan Marek reg = <0 0x01720000 0 0x7000>; 161171a2fc6eSJonathan Marek #interconnect-cells = <1>; 161271a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 161371a2fc6eSJonathan Marek }; 161471a2fc6eSJonathan Marek 161571a2fc6eSJonathan Marek mmss_noc: interconnect@1740000 { 161671a2fc6eSJonathan Marek compatible = "qcom,sm8150-mmss-noc"; 161771a2fc6eSJonathan Marek reg = <0 0x01740000 0 0x1c100>; 161871a2fc6eSJonathan Marek #interconnect-cells = <1>; 161971a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 162071a2fc6eSJonathan Marek }; 162171a2fc6eSJonathan Marek 1622bb1f7cf6SSouradeep Chowdhury system-cache-controller@9200000 { 1623bb1f7cf6SSouradeep Chowdhury compatible = "qcom,sm8150-llcc"; 1624bb1f7cf6SSouradeep Chowdhury reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 1625bb1f7cf6SSouradeep Chowdhury reg-names = "llcc_base", "llcc_broadcast_base"; 1626bb1f7cf6SSouradeep Chowdhury interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1627bb1f7cf6SSouradeep Chowdhury }; 1628bb1f7cf6SSouradeep Chowdhury 16293834a2e9SVinod Koul ufs_mem_hc: ufshc@1d84000 { 16303834a2e9SVinod Koul compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 16313834a2e9SVinod Koul "jedec,ufs-2.0"; 163298aee1e3SBhupesh Sharma reg = <0 0x01d84000 0 0x2500>, 163398aee1e3SBhupesh Sharma <0 0x01d90000 0 0x8000>; 163498aee1e3SBhupesh Sharma reg-names = "std", "ice"; 16353834a2e9SVinod Koul interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 16363834a2e9SVinod Koul phys = <&ufs_mem_phy_lanes>; 16373834a2e9SVinod Koul phy-names = "ufsphy"; 16383834a2e9SVinod Koul lanes-per-direction = <2>; 16393834a2e9SVinod Koul #reset-cells = <1>; 16403834a2e9SVinod Koul resets = <&gcc GCC_UFS_PHY_BCR>; 16413834a2e9SVinod Koul reset-names = "rst"; 16423834a2e9SVinod Koul 164348156232SJonathan Marek iommus = <&apps_smmu 0x300 0>; 164448156232SJonathan Marek 16453834a2e9SVinod Koul clock-names = 16463834a2e9SVinod Koul "core_clk", 16473834a2e9SVinod Koul "bus_aggr_clk", 16483834a2e9SVinod Koul "iface_clk", 16493834a2e9SVinod Koul "core_clk_unipro", 16503834a2e9SVinod Koul "ref_clk", 16513834a2e9SVinod Koul "tx_lane0_sync_clk", 16523834a2e9SVinod Koul "rx_lane0_sync_clk", 165398aee1e3SBhupesh Sharma "rx_lane1_sync_clk", 165498aee1e3SBhupesh Sharma "ice_core_clk"; 16553834a2e9SVinod Koul clocks = 16563834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AXI_CLK>, 16573834a2e9SVinod Koul <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 16583834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AHB_CLK>, 16593834a2e9SVinod Koul <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 16603834a2e9SVinod Koul <&rpmhcc RPMH_CXO_CLK>, 16613834a2e9SVinod Koul <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 16623834a2e9SVinod Koul <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 166398aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 166498aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 16653834a2e9SVinod Koul freq-table-hz = 16663834a2e9SVinod Koul <37500000 300000000>, 16673834a2e9SVinod Koul <0 0>, 16683834a2e9SVinod Koul <0 0>, 16693834a2e9SVinod Koul <37500000 300000000>, 16703834a2e9SVinod Koul <0 0>, 16713834a2e9SVinod Koul <0 0>, 16723834a2e9SVinod Koul <0 0>, 167398aee1e3SBhupesh Sharma <0 0>, 167498aee1e3SBhupesh Sharma <0 300000000>; 16753834a2e9SVinod Koul 16763834a2e9SVinod Koul status = "disabled"; 16773834a2e9SVinod Koul }; 16783834a2e9SVinod Koul 16793834a2e9SVinod Koul ufs_mem_phy: phy@1d87000 { 16803834a2e9SVinod Koul compatible = "qcom,sm8150-qmp-ufs-phy"; 1681c79ec891SVinod Koul reg = <0 0x01d87000 0 0x1c0>; 16823834a2e9SVinod Koul #address-cells = <2>; 16833834a2e9SVinod Koul #size-cells = <2>; 16843834a2e9SVinod Koul ranges; 16853834a2e9SVinod Koul clock-names = "ref", 16863834a2e9SVinod Koul "ref_aux"; 16873834a2e9SVinod Koul clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 16883834a2e9SVinod Koul <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 16893834a2e9SVinod Koul 16903834a2e9SVinod Koul resets = <&ufs_mem_hc 0>; 16913834a2e9SVinod Koul reset-names = "ufsphy"; 16923834a2e9SVinod Koul status = "disabled"; 16933834a2e9SVinod Koul 16941351512fSShawn Guo ufs_mem_phy_lanes: phy@1d87400 { 16953834a2e9SVinod Koul reg = <0 0x01d87400 0 0x108>, 16963834a2e9SVinod Koul <0 0x01d87600 0 0x1e0>, 16973834a2e9SVinod Koul <0 0x01d87c00 0 0x1dc>, 16983834a2e9SVinod Koul <0 0x01d87800 0 0x108>, 16993834a2e9SVinod Koul <0 0x01d87a00 0 0x1e0>; 17003834a2e9SVinod Koul #phy-cells = <0>; 17013834a2e9SVinod Koul }; 17023834a2e9SVinod Koul }; 17033834a2e9SVinod Koul 170471a2fc6eSJonathan Marek ipa_virt: interconnect@1e00000 { 170571a2fc6eSJonathan Marek compatible = "qcom,sm8150-ipa-virt"; 170671a2fc6eSJonathan Marek reg = <0 0x01e00000 0 0x1000>; 170771a2fc6eSJonathan Marek #interconnect-cells = <1>; 170871a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 170971a2fc6eSJonathan Marek }; 171071a2fc6eSJonathan Marek 1711d8cf9372SVinod Koul tcsr_mutex_regs: syscon@1f40000 { 1712d8cf9372SVinod Koul compatible = "syscon"; 1713d8cf9372SVinod Koul reg = <0x0 0x01f40000 0x0 0x40000>; 1714d8cf9372SVinod Koul }; 1715d8cf9372SVinod Koul 171649076351SSibi Sankar remoteproc_slpi: remoteproc@2400000 { 171749076351SSibi Sankar compatible = "qcom,sm8150-slpi-pas"; 171849076351SSibi Sankar reg = <0x0 0x02400000 0x0 0x4040>; 171949076351SSibi Sankar 172049076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 172149076351SSibi Sankar <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 172249076351SSibi Sankar <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 172349076351SSibi Sankar <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 172449076351SSibi Sankar <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 172549076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 172649076351SSibi Sankar "handover", "stop-ack"; 172749076351SSibi Sankar 172849076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 172949076351SSibi Sankar clock-names = "xo"; 173049076351SSibi Sankar 1731d9d327f6SSibi Sankar power-domains = <&rpmhpd 3>, 1732d0770627SBjorn Andersson <&rpmhpd 2>; 1733d9d327f6SSibi Sankar power-domain-names = "lcx", "lmx"; 173449076351SSibi Sankar 173549076351SSibi Sankar memory-region = <&slpi_mem>; 173649076351SSibi Sankar 1737d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 1738d9d327f6SSibi Sankar 173949076351SSibi Sankar qcom,smem-states = <&slpi_smp2p_out 0>; 174049076351SSibi Sankar qcom,smem-state-names = "stop"; 174149076351SSibi Sankar 174249076351SSibi Sankar status = "disabled"; 174349076351SSibi Sankar 174449076351SSibi Sankar glink-edge { 174549076351SSibi Sankar interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 174649076351SSibi Sankar label = "dsps"; 174749076351SSibi Sankar qcom,remote-pid = <3>; 174849076351SSibi Sankar mboxes = <&apss_shared 24>; 174981729330SBhupesh Sharma 175081729330SBhupesh Sharma fastrpc { 175181729330SBhupesh Sharma compatible = "qcom,fastrpc"; 175281729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 175381729330SBhupesh Sharma label = "sdsp"; 1754*8c8ce95bSJeya R qcom,non-secure-domain; 175581729330SBhupesh Sharma #address-cells = <1>; 175681729330SBhupesh Sharma #size-cells = <0>; 175781729330SBhupesh Sharma 175881729330SBhupesh Sharma compute-cb@1 { 175981729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 176081729330SBhupesh Sharma reg = <1>; 176181729330SBhupesh Sharma iommus = <&apps_smmu 0x05a1 0x0>; 176281729330SBhupesh Sharma }; 176381729330SBhupesh Sharma 176481729330SBhupesh Sharma compute-cb@2 { 176581729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 176681729330SBhupesh Sharma reg = <2>; 176781729330SBhupesh Sharma iommus = <&apps_smmu 0x05a2 0x0>; 176881729330SBhupesh Sharma }; 176981729330SBhupesh Sharma 177081729330SBhupesh Sharma compute-cb@3 { 177181729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 177281729330SBhupesh Sharma reg = <3>; 177381729330SBhupesh Sharma iommus = <&apps_smmu 0x05a3 0x0>; 177481729330SBhupesh Sharma /* note: shared-cb = <4> in downstream */ 177581729330SBhupesh Sharma }; 177681729330SBhupesh Sharma }; 177749076351SSibi Sankar }; 177849076351SSibi Sankar }; 177949076351SSibi Sankar 1780f30ac26dSJonathan Marek gpu: gpu@2c00000 { 1781f30ac26dSJonathan Marek /* 1782f30ac26dSJonathan Marek * note: the amd,imageon compatible makes it possible 1783f30ac26dSJonathan Marek * to use the drm/msm driver without the display node, 1784f30ac26dSJonathan Marek * make sure to remove it when display node is added 1785f30ac26dSJonathan Marek */ 1786f30ac26dSJonathan Marek compatible = "qcom,adreno-640.1", 1787f30ac26dSJonathan Marek "qcom,adreno", 1788f30ac26dSJonathan Marek "amd,imageon"; 1789f30ac26dSJonathan Marek 1790f30ac26dSJonathan Marek reg = <0 0x02c00000 0 0x40000>; 1791f30ac26dSJonathan Marek reg-names = "kgsl_3d0_reg_memory"; 1792f30ac26dSJonathan Marek 1793f30ac26dSJonathan Marek interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1794f30ac26dSJonathan Marek 1795f30ac26dSJonathan Marek iommus = <&adreno_smmu 0 0x401>; 1796f30ac26dSJonathan Marek 1797f30ac26dSJonathan Marek operating-points-v2 = <&gpu_opp_table>; 1798f30ac26dSJonathan Marek 1799f30ac26dSJonathan Marek qcom,gmu = <&gmu>; 1800f30ac26dSJonathan Marek 1801b1dc3c6bSKonrad Dybcio status = "disabled"; 1802b1dc3c6bSKonrad Dybcio 1803f30ac26dSJonathan Marek zap-shader { 1804f30ac26dSJonathan Marek memory-region = <&gpu_mem>; 1805f30ac26dSJonathan Marek }; 1806f30ac26dSJonathan Marek 1807f30ac26dSJonathan Marek /* note: downstream checks gpu binning for 675 Mhz */ 1808f30ac26dSJonathan Marek gpu_opp_table: opp-table { 1809f30ac26dSJonathan Marek compatible = "operating-points-v2"; 1810f30ac26dSJonathan Marek 1811f30ac26dSJonathan Marek opp-675000000 { 1812f30ac26dSJonathan Marek opp-hz = /bits/ 64 <675000000>; 1813f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1814f30ac26dSJonathan Marek }; 1815f30ac26dSJonathan Marek 1816f30ac26dSJonathan Marek opp-585000000 { 1817f30ac26dSJonathan Marek opp-hz = /bits/ 64 <585000000>; 1818f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1819f30ac26dSJonathan Marek }; 1820f30ac26dSJonathan Marek 1821f30ac26dSJonathan Marek opp-499200000 { 1822f30ac26dSJonathan Marek opp-hz = /bits/ 64 <499200000>; 1823f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1824f30ac26dSJonathan Marek }; 1825f30ac26dSJonathan Marek 1826f30ac26dSJonathan Marek opp-427000000 { 1827f30ac26dSJonathan Marek opp-hz = /bits/ 64 <427000000>; 1828f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1829f30ac26dSJonathan Marek }; 1830f30ac26dSJonathan Marek 1831f30ac26dSJonathan Marek opp-345000000 { 1832f30ac26dSJonathan Marek opp-hz = /bits/ 64 <345000000>; 1833f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1834f30ac26dSJonathan Marek }; 1835f30ac26dSJonathan Marek 1836f30ac26dSJonathan Marek opp-257000000 { 1837f30ac26dSJonathan Marek opp-hz = /bits/ 64 <257000000>; 1838f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1839f30ac26dSJonathan Marek }; 1840f30ac26dSJonathan Marek }; 1841f30ac26dSJonathan Marek }; 1842f30ac26dSJonathan Marek 1843f30ac26dSJonathan Marek gmu: gmu@2c6a000 { 1844f30ac26dSJonathan Marek compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 1845f30ac26dSJonathan Marek 1846f30ac26dSJonathan Marek reg = <0 0x02c6a000 0 0x30000>, 1847f30ac26dSJonathan Marek <0 0x0b290000 0 0x10000>, 1848f30ac26dSJonathan Marek <0 0x0b490000 0 0x10000>; 1849f30ac26dSJonathan Marek reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 1850f30ac26dSJonathan Marek 1851f30ac26dSJonathan Marek interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1852f30ac26dSJonathan Marek <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1853f30ac26dSJonathan Marek interrupt-names = "hfi", "gmu"; 1854f30ac26dSJonathan Marek 1855f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 1856f1269916SJonathan Marek <&gpucc GPU_CC_CX_GMU_CLK>, 1857f1269916SJonathan Marek <&gpucc GPU_CC_CXO_CLK>, 1858f30ac26dSJonathan Marek <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1859f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1860f30ac26dSJonathan Marek clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 1861f30ac26dSJonathan Marek 1862f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>, 1863f1269916SJonathan Marek <&gpucc GPU_GX_GDSC>; 1864f30ac26dSJonathan Marek power-domain-names = "cx", "gx"; 1865f30ac26dSJonathan Marek 1866f30ac26dSJonathan Marek iommus = <&adreno_smmu 5 0x400>; 1867f30ac26dSJonathan Marek 1868f30ac26dSJonathan Marek operating-points-v2 = <&gmu_opp_table>; 1869f30ac26dSJonathan Marek 1870b1dc3c6bSKonrad Dybcio status = "disabled"; 1871b1dc3c6bSKonrad Dybcio 1872f30ac26dSJonathan Marek gmu_opp_table: opp-table { 1873f30ac26dSJonathan Marek compatible = "operating-points-v2"; 1874f30ac26dSJonathan Marek 1875f30ac26dSJonathan Marek opp-200000000 { 1876f30ac26dSJonathan Marek opp-hz = /bits/ 64 <200000000>; 1877f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1878f30ac26dSJonathan Marek }; 1879f30ac26dSJonathan Marek }; 1880f30ac26dSJonathan Marek }; 1881f30ac26dSJonathan Marek 1882f30ac26dSJonathan Marek gpucc: clock-controller@2c90000 { 1883f30ac26dSJonathan Marek compatible = "qcom,sm8150-gpucc"; 1884f30ac26dSJonathan Marek reg = <0 0x02c90000 0 0x9000>; 1885f30ac26dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>, 1886f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1887f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1888f30ac26dSJonathan Marek clock-names = "bi_tcxo", 1889f30ac26dSJonathan Marek "gcc_gpu_gpll0_clk_src", 1890f30ac26dSJonathan Marek "gcc_gpu_gpll0_div_clk_src"; 1891f30ac26dSJonathan Marek #clock-cells = <1>; 1892f30ac26dSJonathan Marek #reset-cells = <1>; 1893f30ac26dSJonathan Marek #power-domain-cells = <1>; 1894f30ac26dSJonathan Marek }; 1895f30ac26dSJonathan Marek 1896f30ac26dSJonathan Marek adreno_smmu: iommu@2ca0000 { 1897f30ac26dSJonathan Marek compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 1898f30ac26dSJonathan Marek reg = <0 0x02ca0000 0 0x10000>; 1899f30ac26dSJonathan Marek #iommu-cells = <2>; 1900f30ac26dSJonathan Marek #global-interrupts = <1>; 1901f30ac26dSJonathan Marek interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 1902f30ac26dSJonathan Marek <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1903f30ac26dSJonathan Marek <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1904f30ac26dSJonathan Marek <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1905f30ac26dSJonathan Marek <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1906f30ac26dSJonathan Marek <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1907f30ac26dSJonathan Marek <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1908f30ac26dSJonathan Marek <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 1909f30ac26dSJonathan Marek <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 1910f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 1911f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1912f30ac26dSJonathan Marek <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1913f30ac26dSJonathan Marek clock-names = "ahb", "bus", "iface"; 1914f30ac26dSJonathan Marek 1915f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>; 1916f30ac26dSJonathan Marek }; 1917f30ac26dSJonathan Marek 1918e13c6d14SVinod Koul tlmm: pinctrl@3100000 { 1919e13c6d14SVinod Koul compatible = "qcom,sm8150-pinctrl"; 1920e13c6d14SVinod Koul reg = <0x0 0x03100000 0x0 0x300000>, 1921e13c6d14SVinod Koul <0x0 0x03500000 0x0 0x300000>, 1922e13c6d14SVinod Koul <0x0 0x03900000 0x0 0x300000>, 1923e13c6d14SVinod Koul <0x0 0x03D00000 0x0 0x300000>; 1924e13c6d14SVinod Koul reg-names = "west", "east", "north", "south"; 1925e13c6d14SVinod Koul interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1926de3abdf3SShawn Guo gpio-ranges = <&tlmm 0 0 176>; 1927e13c6d14SVinod Koul gpio-controller; 1928e13c6d14SVinod Koul #gpio-cells = <2>; 1929e13c6d14SVinod Koul interrupt-controller; 1930e13c6d14SVinod Koul #interrupt-cells = <2>; 193181bee695SCaleb Connolly 193281bee695SCaleb Connolly qup_i2c0_default: qup-i2c0-default { 193381bee695SCaleb Connolly mux { 193481bee695SCaleb Connolly pins = "gpio0", "gpio1"; 193581bee695SCaleb Connolly function = "qup0"; 193681bee695SCaleb Connolly }; 193781bee695SCaleb Connolly 193881bee695SCaleb Connolly config { 193981bee695SCaleb Connolly pins = "gpio0", "gpio1"; 194081bee695SCaleb Connolly drive-strength = <0x02>; 194181bee695SCaleb Connolly bias-disable; 194281bee695SCaleb Connolly }; 194381bee695SCaleb Connolly }; 194481bee695SCaleb Connolly 1945129e1c96SFelipe Balbi qup_spi0_default: qup-spi0-default { 1946129e1c96SFelipe Balbi pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1947129e1c96SFelipe Balbi function = "qup0"; 1948129e1c96SFelipe Balbi drive-strength = <6>; 1949129e1c96SFelipe Balbi bias-disable; 1950129e1c96SFelipe Balbi }; 1951129e1c96SFelipe Balbi 195281bee695SCaleb Connolly qup_i2c1_default: qup-i2c1-default { 195381bee695SCaleb Connolly mux { 195481bee695SCaleb Connolly pins = "gpio114", "gpio115"; 195581bee695SCaleb Connolly function = "qup1"; 195681bee695SCaleb Connolly }; 195781bee695SCaleb Connolly 195881bee695SCaleb Connolly config { 195981bee695SCaleb Connolly pins = "gpio114", "gpio115"; 196081bee695SCaleb Connolly drive-strength = <0x02>; 196181bee695SCaleb Connolly bias-disable; 196281bee695SCaleb Connolly }; 196381bee695SCaleb Connolly }; 196481bee695SCaleb Connolly 1965129e1c96SFelipe Balbi qup_spi1_default: qup-spi1-default { 1966129e1c96SFelipe Balbi pins = "gpio114", "gpio115", "gpio116", "gpio117"; 1967129e1c96SFelipe Balbi function = "qup1"; 1968129e1c96SFelipe Balbi drive-strength = <6>; 1969129e1c96SFelipe Balbi bias-disable; 1970129e1c96SFelipe Balbi }; 1971129e1c96SFelipe Balbi 197281bee695SCaleb Connolly qup_i2c2_default: qup-i2c2-default { 197381bee695SCaleb Connolly mux { 197481bee695SCaleb Connolly pins = "gpio126", "gpio127"; 197581bee695SCaleb Connolly function = "qup2"; 197681bee695SCaleb Connolly }; 197781bee695SCaleb Connolly 197881bee695SCaleb Connolly config { 197981bee695SCaleb Connolly pins = "gpio126", "gpio127"; 198081bee695SCaleb Connolly drive-strength = <0x02>; 198181bee695SCaleb Connolly bias-disable; 198281bee695SCaleb Connolly }; 198381bee695SCaleb Connolly }; 198481bee695SCaleb Connolly 1985129e1c96SFelipe Balbi qup_spi2_default: qup-spi2-default { 1986129e1c96SFelipe Balbi pins = "gpio126", "gpio127", "gpio128", "gpio129"; 1987129e1c96SFelipe Balbi function = "qup2"; 1988129e1c96SFelipe Balbi drive-strength = <6>; 1989129e1c96SFelipe Balbi bias-disable; 1990129e1c96SFelipe Balbi }; 1991129e1c96SFelipe Balbi 199281bee695SCaleb Connolly qup_i2c3_default: qup-i2c3-default { 199381bee695SCaleb Connolly mux { 199481bee695SCaleb Connolly pins = "gpio144", "gpio145"; 199581bee695SCaleb Connolly function = "qup3"; 199681bee695SCaleb Connolly }; 199781bee695SCaleb Connolly 199881bee695SCaleb Connolly config { 199981bee695SCaleb Connolly pins = "gpio144", "gpio145"; 200081bee695SCaleb Connolly drive-strength = <0x02>; 200181bee695SCaleb Connolly bias-disable; 200281bee695SCaleb Connolly }; 200381bee695SCaleb Connolly }; 200481bee695SCaleb Connolly 2005129e1c96SFelipe Balbi qup_spi3_default: qup-spi3-default { 2006129e1c96SFelipe Balbi pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2007129e1c96SFelipe Balbi function = "qup3"; 2008129e1c96SFelipe Balbi drive-strength = <6>; 2009129e1c96SFelipe Balbi bias-disable; 2010129e1c96SFelipe Balbi }; 2011129e1c96SFelipe Balbi 201281bee695SCaleb Connolly qup_i2c4_default: qup-i2c4-default { 201381bee695SCaleb Connolly mux { 201481bee695SCaleb Connolly pins = "gpio51", "gpio52"; 201581bee695SCaleb Connolly function = "qup4"; 201681bee695SCaleb Connolly }; 201781bee695SCaleb Connolly 201881bee695SCaleb Connolly config { 201981bee695SCaleb Connolly pins = "gpio51", "gpio52"; 202081bee695SCaleb Connolly drive-strength = <0x02>; 202181bee695SCaleb Connolly bias-disable; 202281bee695SCaleb Connolly }; 202381bee695SCaleb Connolly }; 202481bee695SCaleb Connolly 2025129e1c96SFelipe Balbi qup_spi4_default: qup-spi4-default { 2026129e1c96SFelipe Balbi pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2027129e1c96SFelipe Balbi function = "qup4"; 2028129e1c96SFelipe Balbi drive-strength = <6>; 2029129e1c96SFelipe Balbi bias-disable; 2030129e1c96SFelipe Balbi }; 2031129e1c96SFelipe Balbi 203281bee695SCaleb Connolly qup_i2c5_default: qup-i2c5-default { 203381bee695SCaleb Connolly mux { 203481bee695SCaleb Connolly pins = "gpio121", "gpio122"; 203581bee695SCaleb Connolly function = "qup5"; 203681bee695SCaleb Connolly }; 203781bee695SCaleb Connolly 203881bee695SCaleb Connolly config { 203981bee695SCaleb Connolly pins = "gpio121", "gpio122"; 204081bee695SCaleb Connolly drive-strength = <0x02>; 204181bee695SCaleb Connolly bias-disable; 204281bee695SCaleb Connolly }; 204381bee695SCaleb Connolly }; 204481bee695SCaleb Connolly 2045129e1c96SFelipe Balbi qup_spi5_default: qup-spi5-default { 2046129e1c96SFelipe Balbi pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2047129e1c96SFelipe Balbi function = "qup5"; 2048129e1c96SFelipe Balbi drive-strength = <6>; 2049129e1c96SFelipe Balbi bias-disable; 2050129e1c96SFelipe Balbi }; 2051129e1c96SFelipe Balbi 205281bee695SCaleb Connolly qup_i2c6_default: qup-i2c6-default { 205381bee695SCaleb Connolly mux { 205481bee695SCaleb Connolly pins = "gpio6", "gpio7"; 205581bee695SCaleb Connolly function = "qup6"; 205681bee695SCaleb Connolly }; 205781bee695SCaleb Connolly 205881bee695SCaleb Connolly config { 205981bee695SCaleb Connolly pins = "gpio6", "gpio7"; 206081bee695SCaleb Connolly drive-strength = <0x02>; 206181bee695SCaleb Connolly bias-disable; 206281bee695SCaleb Connolly }; 206381bee695SCaleb Connolly }; 206481bee695SCaleb Connolly 2065129e1c96SFelipe Balbi qup_spi6_default: qup-spi6_default { 2066129e1c96SFelipe Balbi pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2067129e1c96SFelipe Balbi function = "qup6"; 2068129e1c96SFelipe Balbi drive-strength = <6>; 2069129e1c96SFelipe Balbi bias-disable; 2070129e1c96SFelipe Balbi }; 2071129e1c96SFelipe Balbi 207281bee695SCaleb Connolly qup_i2c7_default: qup-i2c7-default { 207381bee695SCaleb Connolly mux { 207481bee695SCaleb Connolly pins = "gpio98", "gpio99"; 207581bee695SCaleb Connolly function = "qup7"; 207681bee695SCaleb Connolly }; 207781bee695SCaleb Connolly 207881bee695SCaleb Connolly config { 207981bee695SCaleb Connolly pins = "gpio98", "gpio99"; 208081bee695SCaleb Connolly drive-strength = <0x02>; 208181bee695SCaleb Connolly bias-disable; 208281bee695SCaleb Connolly }; 208381bee695SCaleb Connolly }; 208481bee695SCaleb Connolly 2085129e1c96SFelipe Balbi qup_spi7_default: qup-spi7_default { 2086129e1c96SFelipe Balbi pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2087129e1c96SFelipe Balbi function = "qup7"; 2088129e1c96SFelipe Balbi drive-strength = <6>; 2089129e1c96SFelipe Balbi bias-disable; 2090129e1c96SFelipe Balbi }; 2091129e1c96SFelipe Balbi 209281bee695SCaleb Connolly qup_i2c8_default: qup-i2c8-default { 209381bee695SCaleb Connolly mux { 209481bee695SCaleb Connolly pins = "gpio88", "gpio89"; 209581bee695SCaleb Connolly function = "qup8"; 209681bee695SCaleb Connolly }; 209781bee695SCaleb Connolly 209881bee695SCaleb Connolly config { 209981bee695SCaleb Connolly pins = "gpio88", "gpio89"; 210081bee695SCaleb Connolly drive-strength = <0x02>; 210181bee695SCaleb Connolly bias-disable; 210281bee695SCaleb Connolly }; 210381bee695SCaleb Connolly }; 210481bee695SCaleb Connolly 2105129e1c96SFelipe Balbi qup_spi8_default: qup-spi8-default { 2106129e1c96SFelipe Balbi pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2107129e1c96SFelipe Balbi function = "qup8"; 2108129e1c96SFelipe Balbi drive-strength = <6>; 2109129e1c96SFelipe Balbi bias-disable; 2110129e1c96SFelipe Balbi }; 2111129e1c96SFelipe Balbi 211281bee695SCaleb Connolly qup_i2c9_default: qup-i2c9-default { 211381bee695SCaleb Connolly mux { 211481bee695SCaleb Connolly pins = "gpio39", "gpio40"; 211581bee695SCaleb Connolly function = "qup9"; 211681bee695SCaleb Connolly }; 211781bee695SCaleb Connolly 211881bee695SCaleb Connolly config { 211981bee695SCaleb Connolly pins = "gpio39", "gpio40"; 212081bee695SCaleb Connolly drive-strength = <0x02>; 212181bee695SCaleb Connolly bias-disable; 212281bee695SCaleb Connolly }; 212381bee695SCaleb Connolly }; 212481bee695SCaleb Connolly 2125129e1c96SFelipe Balbi qup_spi9_default: qup-spi9-default { 2126129e1c96SFelipe Balbi pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2127129e1c96SFelipe Balbi function = "qup9"; 2128129e1c96SFelipe Balbi drive-strength = <6>; 2129129e1c96SFelipe Balbi bias-disable; 2130129e1c96SFelipe Balbi }; 2131129e1c96SFelipe Balbi 213281bee695SCaleb Connolly qup_i2c10_default: qup-i2c10-default { 213381bee695SCaleb Connolly mux { 213481bee695SCaleb Connolly pins = "gpio9", "gpio10"; 213581bee695SCaleb Connolly function = "qup10"; 213681bee695SCaleb Connolly }; 213781bee695SCaleb Connolly 213881bee695SCaleb Connolly config { 213981bee695SCaleb Connolly pins = "gpio9", "gpio10"; 214081bee695SCaleb Connolly drive-strength = <0x02>; 214181bee695SCaleb Connolly bias-disable; 214281bee695SCaleb Connolly }; 214381bee695SCaleb Connolly }; 214481bee695SCaleb Connolly 2145129e1c96SFelipe Balbi qup_spi10_default: qup-spi10-default { 2146129e1c96SFelipe Balbi pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2147129e1c96SFelipe Balbi function = "qup10"; 2148129e1c96SFelipe Balbi drive-strength = <6>; 2149129e1c96SFelipe Balbi bias-disable; 2150129e1c96SFelipe Balbi }; 2151129e1c96SFelipe Balbi 215281bee695SCaleb Connolly qup_i2c11_default: qup-i2c11-default { 215381bee695SCaleb Connolly mux { 215481bee695SCaleb Connolly pins = "gpio94", "gpio95"; 215581bee695SCaleb Connolly function = "qup11"; 215681bee695SCaleb Connolly }; 215781bee695SCaleb Connolly 215881bee695SCaleb Connolly config { 215981bee695SCaleb Connolly pins = "gpio94", "gpio95"; 216081bee695SCaleb Connolly drive-strength = <0x02>; 216181bee695SCaleb Connolly bias-disable; 216281bee695SCaleb Connolly }; 216381bee695SCaleb Connolly }; 216481bee695SCaleb Connolly 2165129e1c96SFelipe Balbi qup_spi11_default: qup-spi11-default { 2166129e1c96SFelipe Balbi pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2167129e1c96SFelipe Balbi function = "qup11"; 2168129e1c96SFelipe Balbi drive-strength = <6>; 2169129e1c96SFelipe Balbi bias-disable; 2170129e1c96SFelipe Balbi }; 2171129e1c96SFelipe Balbi 217281bee695SCaleb Connolly qup_i2c12_default: qup-i2c12-default { 217381bee695SCaleb Connolly mux { 217481bee695SCaleb Connolly pins = "gpio83", "gpio84"; 217581bee695SCaleb Connolly function = "qup12"; 217681bee695SCaleb Connolly }; 217781bee695SCaleb Connolly 217881bee695SCaleb Connolly config { 217981bee695SCaleb Connolly pins = "gpio83", "gpio84"; 218081bee695SCaleb Connolly drive-strength = <0x02>; 218181bee695SCaleb Connolly bias-disable; 218281bee695SCaleb Connolly }; 218381bee695SCaleb Connolly }; 218481bee695SCaleb Connolly 2185129e1c96SFelipe Balbi qup_spi12_default: qup-spi12-default { 2186129e1c96SFelipe Balbi pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2187129e1c96SFelipe Balbi function = "qup12"; 2188129e1c96SFelipe Balbi drive-strength = <6>; 2189129e1c96SFelipe Balbi bias-disable; 2190129e1c96SFelipe Balbi }; 2191129e1c96SFelipe Balbi 219281bee695SCaleb Connolly qup_i2c13_default: qup-i2c13-default { 219381bee695SCaleb Connolly mux { 219481bee695SCaleb Connolly pins = "gpio43", "gpio44"; 219581bee695SCaleb Connolly function = "qup13"; 219681bee695SCaleb Connolly }; 219781bee695SCaleb Connolly 219881bee695SCaleb Connolly config { 219981bee695SCaleb Connolly pins = "gpio43", "gpio44"; 220081bee695SCaleb Connolly drive-strength = <0x02>; 220181bee695SCaleb Connolly bias-disable; 220281bee695SCaleb Connolly }; 220381bee695SCaleb Connolly }; 220481bee695SCaleb Connolly 2205129e1c96SFelipe Balbi qup_spi13_default: qup-spi13-default { 2206129e1c96SFelipe Balbi pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2207129e1c96SFelipe Balbi function = "qup13"; 2208129e1c96SFelipe Balbi drive-strength = <6>; 2209129e1c96SFelipe Balbi bias-disable; 2210129e1c96SFelipe Balbi }; 2211129e1c96SFelipe Balbi 221281bee695SCaleb Connolly qup_i2c14_default: qup-i2c14-default { 221381bee695SCaleb Connolly mux { 221481bee695SCaleb Connolly pins = "gpio47", "gpio48"; 221581bee695SCaleb Connolly function = "qup14"; 221681bee695SCaleb Connolly }; 221781bee695SCaleb Connolly 221881bee695SCaleb Connolly config { 221981bee695SCaleb Connolly pins = "gpio47", "gpio48"; 222081bee695SCaleb Connolly drive-strength = <0x02>; 222181bee695SCaleb Connolly bias-disable; 222281bee695SCaleb Connolly }; 222381bee695SCaleb Connolly }; 222481bee695SCaleb Connolly 2225129e1c96SFelipe Balbi qup_spi14_default: qup-spi14-default { 2226129e1c96SFelipe Balbi pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2227129e1c96SFelipe Balbi function = "qup14"; 2228129e1c96SFelipe Balbi drive-strength = <6>; 2229129e1c96SFelipe Balbi bias-disable; 2230129e1c96SFelipe Balbi }; 2231129e1c96SFelipe Balbi 223281bee695SCaleb Connolly qup_i2c15_default: qup-i2c15-default { 223381bee695SCaleb Connolly mux { 223481bee695SCaleb Connolly pins = "gpio27", "gpio28"; 223581bee695SCaleb Connolly function = "qup15"; 223681bee695SCaleb Connolly }; 223781bee695SCaleb Connolly 223881bee695SCaleb Connolly config { 223981bee695SCaleb Connolly pins = "gpio27", "gpio28"; 224081bee695SCaleb Connolly drive-strength = <0x02>; 224181bee695SCaleb Connolly bias-disable; 224281bee695SCaleb Connolly }; 224381bee695SCaleb Connolly }; 224481bee695SCaleb Connolly 2245129e1c96SFelipe Balbi qup_spi15_default: qup-spi15-default { 2246129e1c96SFelipe Balbi pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2247129e1c96SFelipe Balbi function = "qup15"; 2248129e1c96SFelipe Balbi drive-strength = <6>; 2249129e1c96SFelipe Balbi bias-disable; 2250129e1c96SFelipe Balbi }; 2251129e1c96SFelipe Balbi 225281bee695SCaleb Connolly qup_i2c16_default: qup-i2c16-default { 225381bee695SCaleb Connolly mux { 225481bee695SCaleb Connolly pins = "gpio86", "gpio85"; 225581bee695SCaleb Connolly function = "qup16"; 225681bee695SCaleb Connolly }; 225781bee695SCaleb Connolly 225881bee695SCaleb Connolly config { 225981bee695SCaleb Connolly pins = "gpio86", "gpio85"; 226081bee695SCaleb Connolly drive-strength = <0x02>; 226181bee695SCaleb Connolly bias-disable; 226281bee695SCaleb Connolly }; 226381bee695SCaleb Connolly }; 226481bee695SCaleb Connolly 2265129e1c96SFelipe Balbi qup_spi16_default: qup-spi16-default { 2266129e1c96SFelipe Balbi pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2267129e1c96SFelipe Balbi function = "qup16"; 2268129e1c96SFelipe Balbi drive-strength = <6>; 2269129e1c96SFelipe Balbi bias-disable; 2270129e1c96SFelipe Balbi }; 2271129e1c96SFelipe Balbi 227281bee695SCaleb Connolly qup_i2c17_default: qup-i2c17-default { 227381bee695SCaleb Connolly mux { 227481bee695SCaleb Connolly pins = "gpio55", "gpio56"; 227581bee695SCaleb Connolly function = "qup17"; 227681bee695SCaleb Connolly }; 227781bee695SCaleb Connolly 227881bee695SCaleb Connolly config { 227981bee695SCaleb Connolly pins = "gpio55", "gpio56"; 228081bee695SCaleb Connolly drive-strength = <0x02>; 228181bee695SCaleb Connolly bias-disable; 228281bee695SCaleb Connolly }; 228381bee695SCaleb Connolly }; 228481bee695SCaleb Connolly 2285129e1c96SFelipe Balbi qup_spi17_default: qup-spi17-default { 2286129e1c96SFelipe Balbi pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2287129e1c96SFelipe Balbi function = "qup17"; 2288129e1c96SFelipe Balbi drive-strength = <6>; 2289129e1c96SFelipe Balbi bias-disable; 2290129e1c96SFelipe Balbi }; 2291129e1c96SFelipe Balbi 229281bee695SCaleb Connolly qup_i2c18_default: qup-i2c18-default { 229381bee695SCaleb Connolly mux { 229481bee695SCaleb Connolly pins = "gpio23", "gpio24"; 229581bee695SCaleb Connolly function = "qup18"; 229681bee695SCaleb Connolly }; 229781bee695SCaleb Connolly 229881bee695SCaleb Connolly config { 229981bee695SCaleb Connolly pins = "gpio23", "gpio24"; 230081bee695SCaleb Connolly drive-strength = <0x02>; 230181bee695SCaleb Connolly bias-disable; 230281bee695SCaleb Connolly }; 230381bee695SCaleb Connolly }; 230481bee695SCaleb Connolly 2305129e1c96SFelipe Balbi qup_spi18_default: qup-spi18-default { 2306129e1c96SFelipe Balbi pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2307129e1c96SFelipe Balbi function = "qup18"; 2308129e1c96SFelipe Balbi drive-strength = <6>; 2309129e1c96SFelipe Balbi bias-disable; 2310129e1c96SFelipe Balbi }; 2311129e1c96SFelipe Balbi 231281bee695SCaleb Connolly qup_i2c19_default: qup-i2c19-default { 231381bee695SCaleb Connolly mux { 231481bee695SCaleb Connolly pins = "gpio57", "gpio58"; 231581bee695SCaleb Connolly function = "qup19"; 231681bee695SCaleb Connolly }; 231781bee695SCaleb Connolly 231881bee695SCaleb Connolly config { 231981bee695SCaleb Connolly pins = "gpio57", "gpio58"; 232081bee695SCaleb Connolly drive-strength = <0x02>; 232181bee695SCaleb Connolly bias-disable; 232281bee695SCaleb Connolly }; 232381bee695SCaleb Connolly }; 2324129e1c96SFelipe Balbi 2325129e1c96SFelipe Balbi qup_spi19_default: qup-spi19-default { 2326129e1c96SFelipe Balbi pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2327129e1c96SFelipe Balbi function = "qup19"; 2328129e1c96SFelipe Balbi drive-strength = <6>; 2329129e1c96SFelipe Balbi bias-disable; 2330129e1c96SFelipe Balbi }; 2331e13c6d14SVinod Koul }; 2332e13c6d14SVinod Koul 233349076351SSibi Sankar remoteproc_mpss: remoteproc@4080000 { 233449076351SSibi Sankar compatible = "qcom,sm8150-mpss-pas"; 233549076351SSibi Sankar reg = <0x0 0x04080000 0x0 0x4040>; 233649076351SSibi Sankar 233749076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 233849076351SSibi Sankar <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 233949076351SSibi Sankar <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 234049076351SSibi Sankar <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 234149076351SSibi Sankar <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 234249076351SSibi Sankar <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 234349076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", "handover", 234449076351SSibi Sankar "stop-ack", "shutdown-ack"; 234549076351SSibi Sankar 234649076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 234749076351SSibi Sankar clock-names = "xo"; 234849076351SSibi Sankar 2349d9d327f6SSibi Sankar power-domains = <&rpmhpd 7>, 2350d0770627SBjorn Andersson <&rpmhpd 0>; 2351d9d327f6SSibi Sankar power-domain-names = "cx", "mss"; 235249076351SSibi Sankar 235349076351SSibi Sankar memory-region = <&mpss_mem>; 235449076351SSibi Sankar 2355d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 2356d9d327f6SSibi Sankar 235749076351SSibi Sankar qcom,smem-states = <&modem_smp2p_out 0>; 235849076351SSibi Sankar qcom,smem-state-names = "stop"; 235949076351SSibi Sankar 2360b1dc3c6bSKonrad Dybcio status = "disabled"; 2361b1dc3c6bSKonrad Dybcio 236249076351SSibi Sankar glink-edge { 236349076351SSibi Sankar interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 236449076351SSibi Sankar label = "modem"; 236549076351SSibi Sankar qcom,remote-pid = <1>; 236649076351SSibi Sankar mboxes = <&apss_shared 12>; 236749076351SSibi Sankar }; 236849076351SSibi Sankar }; 236949076351SSibi Sankar 237024244cefSSai Prakash Ranjan stm@6002000 { 237124244cefSSai Prakash Ranjan compatible = "arm,coresight-stm", "arm,primecell"; 237224244cefSSai Prakash Ranjan reg = <0 0x06002000 0 0x1000>, 237324244cefSSai Prakash Ranjan <0 0x16280000 0 0x180000>; 237424244cefSSai Prakash Ranjan reg-names = "stm-base", "stm-stimulus-base"; 237524244cefSSai Prakash Ranjan 237624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 237724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 237824244cefSSai Prakash Ranjan 237924244cefSSai Prakash Ranjan out-ports { 238024244cefSSai Prakash Ranjan port { 238124244cefSSai Prakash Ranjan stm_out: endpoint { 238224244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_in7>; 238324244cefSSai Prakash Ranjan }; 238424244cefSSai Prakash Ranjan }; 238524244cefSSai Prakash Ranjan }; 238624244cefSSai Prakash Ranjan }; 238724244cefSSai Prakash Ranjan 238824244cefSSai Prakash Ranjan funnel@6041000 { 238924244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 239024244cefSSai Prakash Ranjan reg = <0 0x06041000 0 0x1000>; 239124244cefSSai Prakash Ranjan 239224244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 239324244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 239424244cefSSai Prakash Ranjan 239524244cefSSai Prakash Ranjan out-ports { 239624244cefSSai Prakash Ranjan port { 239724244cefSSai Prakash Ranjan funnel0_out: endpoint { 239824244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in0>; 239924244cefSSai Prakash Ranjan }; 240024244cefSSai Prakash Ranjan }; 240124244cefSSai Prakash Ranjan }; 240224244cefSSai Prakash Ranjan 240324244cefSSai Prakash Ranjan in-ports { 240424244cefSSai Prakash Ranjan #address-cells = <1>; 240524244cefSSai Prakash Ranjan #size-cells = <0>; 240624244cefSSai Prakash Ranjan 240724244cefSSai Prakash Ranjan port@7 { 240824244cefSSai Prakash Ranjan reg = <7>; 240924244cefSSai Prakash Ranjan funnel0_in7: endpoint { 241024244cefSSai Prakash Ranjan remote-endpoint = <&stm_out>; 241124244cefSSai Prakash Ranjan }; 241224244cefSSai Prakash Ranjan }; 241324244cefSSai Prakash Ranjan }; 241424244cefSSai Prakash Ranjan }; 241524244cefSSai Prakash Ranjan 241624244cefSSai Prakash Ranjan funnel@6042000 { 241724244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 241824244cefSSai Prakash Ranjan reg = <0 0x06042000 0 0x1000>; 241924244cefSSai Prakash Ranjan 242024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 242124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 242224244cefSSai Prakash Ranjan 242324244cefSSai Prakash Ranjan out-ports { 242424244cefSSai Prakash Ranjan port { 242524244cefSSai Prakash Ranjan funnel1_out: endpoint { 242624244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in1>; 242724244cefSSai Prakash Ranjan }; 242824244cefSSai Prakash Ranjan }; 242924244cefSSai Prakash Ranjan }; 243024244cefSSai Prakash Ranjan 243124244cefSSai Prakash Ranjan in-ports { 243224244cefSSai Prakash Ranjan #address-cells = <1>; 243324244cefSSai Prakash Ranjan #size-cells = <0>; 243424244cefSSai Prakash Ranjan 243524244cefSSai Prakash Ranjan port@4 { 243624244cefSSai Prakash Ranjan reg = <4>; 243724244cefSSai Prakash Ranjan funnel1_in4: endpoint { 243824244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_out>; 243924244cefSSai Prakash Ranjan }; 244024244cefSSai Prakash Ranjan }; 244124244cefSSai Prakash Ranjan }; 244224244cefSSai Prakash Ranjan }; 244324244cefSSai Prakash Ranjan 244424244cefSSai Prakash Ranjan funnel@6043000 { 244524244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 244624244cefSSai Prakash Ranjan reg = <0 0x06043000 0 0x1000>; 244724244cefSSai Prakash Ranjan 244824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 244924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 245024244cefSSai Prakash Ranjan 245124244cefSSai Prakash Ranjan out-ports { 245224244cefSSai Prakash Ranjan port { 245324244cefSSai Prakash Ranjan funnel2_out: endpoint { 245424244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in2>; 245524244cefSSai Prakash Ranjan }; 245624244cefSSai Prakash Ranjan }; 245724244cefSSai Prakash Ranjan }; 245824244cefSSai Prakash Ranjan 245924244cefSSai Prakash Ranjan in-ports { 246024244cefSSai Prakash Ranjan #address-cells = <1>; 246124244cefSSai Prakash Ranjan #size-cells = <0>; 246224244cefSSai Prakash Ranjan 246324244cefSSai Prakash Ranjan port@2 { 246424244cefSSai Prakash Ranjan reg = <2>; 246524244cefSSai Prakash Ranjan funnel2_in2: endpoint { 246624244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_out>; 246724244cefSSai Prakash Ranjan }; 246824244cefSSai Prakash Ranjan }; 246924244cefSSai Prakash Ranjan }; 247024244cefSSai Prakash Ranjan }; 247124244cefSSai Prakash Ranjan 247224244cefSSai Prakash Ranjan funnel@6045000 { 247324244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 247424244cefSSai Prakash Ranjan reg = <0 0x06045000 0 0x1000>; 247524244cefSSai Prakash Ranjan 247624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 247724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 247824244cefSSai Prakash Ranjan 247924244cefSSai Prakash Ranjan out-ports { 248024244cefSSai Prakash Ranjan port { 248124244cefSSai Prakash Ranjan merge_funnel_out: endpoint { 248224244cefSSai Prakash Ranjan remote-endpoint = <&etf_in>; 248324244cefSSai Prakash Ranjan }; 248424244cefSSai Prakash Ranjan }; 248524244cefSSai Prakash Ranjan }; 248624244cefSSai Prakash Ranjan 248724244cefSSai Prakash Ranjan in-ports { 248824244cefSSai Prakash Ranjan #address-cells = <1>; 248924244cefSSai Prakash Ranjan #size-cells = <0>; 249024244cefSSai Prakash Ranjan 249124244cefSSai Prakash Ranjan port@0 { 249224244cefSSai Prakash Ranjan reg = <0>; 249324244cefSSai Prakash Ranjan merge_funnel_in0: endpoint { 249424244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_out>; 249524244cefSSai Prakash Ranjan }; 249624244cefSSai Prakash Ranjan }; 249724244cefSSai Prakash Ranjan 249824244cefSSai Prakash Ranjan port@1 { 249924244cefSSai Prakash Ranjan reg = <1>; 250024244cefSSai Prakash Ranjan merge_funnel_in1: endpoint { 250124244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_out>; 250224244cefSSai Prakash Ranjan }; 250324244cefSSai Prakash Ranjan }; 250424244cefSSai Prakash Ranjan 250524244cefSSai Prakash Ranjan port@2 { 250624244cefSSai Prakash Ranjan reg = <2>; 250724244cefSSai Prakash Ranjan merge_funnel_in2: endpoint { 250824244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_out>; 250924244cefSSai Prakash Ranjan }; 251024244cefSSai Prakash Ranjan }; 251124244cefSSai Prakash Ranjan }; 251224244cefSSai Prakash Ranjan }; 251324244cefSSai Prakash Ranjan 251424244cefSSai Prakash Ranjan replicator@6046000 { 251524244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 251624244cefSSai Prakash Ranjan reg = <0 0x06046000 0 0x1000>; 251724244cefSSai Prakash Ranjan 251824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 251924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 252024244cefSSai Prakash Ranjan 252124244cefSSai Prakash Ranjan out-ports { 252224244cefSSai Prakash Ranjan #address-cells = <1>; 252324244cefSSai Prakash Ranjan #size-cells = <0>; 252424244cefSSai Prakash Ranjan 252524244cefSSai Prakash Ranjan port@0 { 252624244cefSSai Prakash Ranjan reg = <0>; 252724244cefSSai Prakash Ranjan replicator_out0: endpoint { 252824244cefSSai Prakash Ranjan remote-endpoint = <&etr_in>; 252924244cefSSai Prakash Ranjan }; 253024244cefSSai Prakash Ranjan }; 253124244cefSSai Prakash Ranjan 253224244cefSSai Prakash Ranjan port@1 { 253324244cefSSai Prakash Ranjan reg = <1>; 253424244cefSSai Prakash Ranjan replicator_out1: endpoint { 253524244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_in>; 253624244cefSSai Prakash Ranjan }; 253724244cefSSai Prakash Ranjan }; 253824244cefSSai Prakash Ranjan }; 253924244cefSSai Prakash Ranjan 254024244cefSSai Prakash Ranjan in-ports { 254124244cefSSai Prakash Ranjan port { 254224244cefSSai Prakash Ranjan replicator_in0: endpoint { 254324244cefSSai Prakash Ranjan remote-endpoint = <&etf_out>; 254424244cefSSai Prakash Ranjan }; 254524244cefSSai Prakash Ranjan }; 254624244cefSSai Prakash Ranjan }; 254724244cefSSai Prakash Ranjan }; 254824244cefSSai Prakash Ranjan 254924244cefSSai Prakash Ranjan etf@6047000 { 255024244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 255124244cefSSai Prakash Ranjan reg = <0 0x06047000 0 0x1000>; 255224244cefSSai Prakash Ranjan 255324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 255424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 255524244cefSSai Prakash Ranjan 255624244cefSSai Prakash Ranjan out-ports { 255724244cefSSai Prakash Ranjan port { 255824244cefSSai Prakash Ranjan etf_out: endpoint { 255924244cefSSai Prakash Ranjan remote-endpoint = <&replicator_in0>; 256024244cefSSai Prakash Ranjan }; 256124244cefSSai Prakash Ranjan }; 256224244cefSSai Prakash Ranjan }; 256324244cefSSai Prakash Ranjan 256424244cefSSai Prakash Ranjan in-ports { 256524244cefSSai Prakash Ranjan port { 256624244cefSSai Prakash Ranjan etf_in: endpoint { 256724244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_out>; 256824244cefSSai Prakash Ranjan }; 256924244cefSSai Prakash Ranjan }; 257024244cefSSai Prakash Ranjan }; 257124244cefSSai Prakash Ranjan }; 257224244cefSSai Prakash Ranjan 257324244cefSSai Prakash Ranjan etr@6048000 { 257424244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 257524244cefSSai Prakash Ranjan reg = <0 0x06048000 0 0x1000>; 257624244cefSSai Prakash Ranjan iommus = <&apps_smmu 0x05e0 0x0>; 257724244cefSSai Prakash Ranjan 257824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 257924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 258024244cefSSai Prakash Ranjan arm,scatter-gather; 258124244cefSSai Prakash Ranjan 258224244cefSSai Prakash Ranjan in-ports { 258324244cefSSai Prakash Ranjan port { 258424244cefSSai Prakash Ranjan etr_in: endpoint { 258524244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out0>; 258624244cefSSai Prakash Ranjan }; 258724244cefSSai Prakash Ranjan }; 258824244cefSSai Prakash Ranjan }; 258924244cefSSai Prakash Ranjan }; 259024244cefSSai Prakash Ranjan 259124244cefSSai Prakash Ranjan replicator@604a000 { 259224244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 259324244cefSSai Prakash Ranjan reg = <0 0x0604a000 0 0x1000>; 259424244cefSSai Prakash Ranjan 259524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 259624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 259724244cefSSai Prakash Ranjan 259824244cefSSai Prakash Ranjan out-ports { 259924244cefSSai Prakash Ranjan #address-cells = <1>; 260024244cefSSai Prakash Ranjan #size-cells = <0>; 260124244cefSSai Prakash Ranjan 260224244cefSSai Prakash Ranjan port@1 { 260324244cefSSai Prakash Ranjan reg = <1>; 260424244cefSSai Prakash Ranjan replicator1_out: endpoint { 260524244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_in>; 260624244cefSSai Prakash Ranjan }; 260724244cefSSai Prakash Ranjan }; 260824244cefSSai Prakash Ranjan }; 260924244cefSSai Prakash Ranjan 261024244cefSSai Prakash Ranjan in-ports { 261124244cefSSai Prakash Ranjan #address-cells = <1>; 261224244cefSSai Prakash Ranjan #size-cells = <0>; 261324244cefSSai Prakash Ranjan 261424244cefSSai Prakash Ranjan port@1 { 261524244cefSSai Prakash Ranjan reg = <1>; 261624244cefSSai Prakash Ranjan replicator1_in: endpoint { 261724244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out1>; 261824244cefSSai Prakash Ranjan }; 261924244cefSSai Prakash Ranjan }; 262024244cefSSai Prakash Ranjan }; 262124244cefSSai Prakash Ranjan }; 262224244cefSSai Prakash Ranjan 262324244cefSSai Prakash Ranjan funnel@6b08000 { 262424244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 262524244cefSSai Prakash Ranjan reg = <0 0x06b08000 0 0x1000>; 262624244cefSSai Prakash Ranjan 262724244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 262824244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 262924244cefSSai Prakash Ranjan 263024244cefSSai Prakash Ranjan out-ports { 263124244cefSSai Prakash Ranjan port { 263224244cefSSai Prakash Ranjan swao_funnel_out: endpoint { 263324244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_in>; 263424244cefSSai Prakash Ranjan }; 263524244cefSSai Prakash Ranjan }; 263624244cefSSai Prakash Ranjan }; 263724244cefSSai Prakash Ranjan 263824244cefSSai Prakash Ranjan in-ports { 263924244cefSSai Prakash Ranjan #address-cells = <1>; 264024244cefSSai Prakash Ranjan #size-cells = <0>; 264124244cefSSai Prakash Ranjan 264224244cefSSai Prakash Ranjan port@6 { 264324244cefSSai Prakash Ranjan reg = <6>; 264424244cefSSai Prakash Ranjan swao_funnel_in: endpoint { 264524244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_out>; 264624244cefSSai Prakash Ranjan }; 264724244cefSSai Prakash Ranjan }; 264824244cefSSai Prakash Ranjan }; 264924244cefSSai Prakash Ranjan }; 265024244cefSSai Prakash Ranjan 265124244cefSSai Prakash Ranjan etf@6b09000 { 265224244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 265324244cefSSai Prakash Ranjan reg = <0 0x06b09000 0 0x1000>; 265424244cefSSai Prakash Ranjan 265524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 265624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 265724244cefSSai Prakash Ranjan 265824244cefSSai Prakash Ranjan out-ports { 265924244cefSSai Prakash Ranjan port { 266024244cefSSai Prakash Ranjan swao_etf_out: endpoint { 266124244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_in>; 266224244cefSSai Prakash Ranjan }; 266324244cefSSai Prakash Ranjan }; 266424244cefSSai Prakash Ranjan }; 266524244cefSSai Prakash Ranjan 266624244cefSSai Prakash Ranjan in-ports { 266724244cefSSai Prakash Ranjan port { 266824244cefSSai Prakash Ranjan swao_etf_in: endpoint { 266924244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_out>; 267024244cefSSai Prakash Ranjan }; 267124244cefSSai Prakash Ranjan }; 267224244cefSSai Prakash Ranjan }; 267324244cefSSai Prakash Ranjan }; 267424244cefSSai Prakash Ranjan 267524244cefSSai Prakash Ranjan replicator@6b0a000 { 267624244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 267724244cefSSai Prakash Ranjan reg = <0 0x06b0a000 0 0x1000>; 267824244cefSSai Prakash Ranjan 267924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 268024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 268124244cefSSai Prakash Ranjan qcom,replicator-loses-context; 268224244cefSSai Prakash Ranjan 268324244cefSSai Prakash Ranjan out-ports { 268424244cefSSai Prakash Ranjan port { 268524244cefSSai Prakash Ranjan swao_replicator_out: endpoint { 268624244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_in4>; 268724244cefSSai Prakash Ranjan }; 268824244cefSSai Prakash Ranjan }; 268924244cefSSai Prakash Ranjan }; 269024244cefSSai Prakash Ranjan 269124244cefSSai Prakash Ranjan in-ports { 269224244cefSSai Prakash Ranjan port { 269324244cefSSai Prakash Ranjan swao_replicator_in: endpoint { 269424244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_out>; 269524244cefSSai Prakash Ranjan }; 269624244cefSSai Prakash Ranjan }; 269724244cefSSai Prakash Ranjan }; 269824244cefSSai Prakash Ranjan }; 269924244cefSSai Prakash Ranjan 270024244cefSSai Prakash Ranjan etm@7040000 { 270124244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 270224244cefSSai Prakash Ranjan reg = <0 0x07040000 0 0x1000>; 270324244cefSSai Prakash Ranjan 270424244cefSSai Prakash Ranjan cpu = <&CPU0>; 270524244cefSSai Prakash Ranjan 270624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 270724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 270824244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 270924244cefSSai Prakash Ranjan qcom,skip-power-up; 271024244cefSSai Prakash Ranjan 271124244cefSSai Prakash Ranjan out-ports { 271224244cefSSai Prakash Ranjan port { 271324244cefSSai Prakash Ranjan etm0_out: endpoint { 271424244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in0>; 271524244cefSSai Prakash Ranjan }; 271624244cefSSai Prakash Ranjan }; 271724244cefSSai Prakash Ranjan }; 271824244cefSSai Prakash Ranjan }; 271924244cefSSai Prakash Ranjan 272024244cefSSai Prakash Ranjan etm@7140000 { 272124244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 272224244cefSSai Prakash Ranjan reg = <0 0x07140000 0 0x1000>; 272324244cefSSai Prakash Ranjan 272424244cefSSai Prakash Ranjan cpu = <&CPU1>; 272524244cefSSai Prakash Ranjan 272624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 272724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 272824244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 272924244cefSSai Prakash Ranjan qcom,skip-power-up; 273024244cefSSai Prakash Ranjan 273124244cefSSai Prakash Ranjan out-ports { 273224244cefSSai Prakash Ranjan port { 273324244cefSSai Prakash Ranjan etm1_out: endpoint { 273424244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in1>; 273524244cefSSai Prakash Ranjan }; 273624244cefSSai Prakash Ranjan }; 273724244cefSSai Prakash Ranjan }; 273824244cefSSai Prakash Ranjan }; 273924244cefSSai Prakash Ranjan 274024244cefSSai Prakash Ranjan etm@7240000 { 274124244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 274224244cefSSai Prakash Ranjan reg = <0 0x07240000 0 0x1000>; 274324244cefSSai Prakash Ranjan 274424244cefSSai Prakash Ranjan cpu = <&CPU2>; 274524244cefSSai Prakash Ranjan 274624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 274724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 274824244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 274924244cefSSai Prakash Ranjan qcom,skip-power-up; 275024244cefSSai Prakash Ranjan 275124244cefSSai Prakash Ranjan out-ports { 275224244cefSSai Prakash Ranjan port { 275324244cefSSai Prakash Ranjan etm2_out: endpoint { 275424244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in2>; 275524244cefSSai Prakash Ranjan }; 275624244cefSSai Prakash Ranjan }; 275724244cefSSai Prakash Ranjan }; 275824244cefSSai Prakash Ranjan }; 275924244cefSSai Prakash Ranjan 276024244cefSSai Prakash Ranjan etm@7340000 { 276124244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 276224244cefSSai Prakash Ranjan reg = <0 0x07340000 0 0x1000>; 276324244cefSSai Prakash Ranjan 276424244cefSSai Prakash Ranjan cpu = <&CPU3>; 276524244cefSSai Prakash Ranjan 276624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 276724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 276824244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 276924244cefSSai Prakash Ranjan qcom,skip-power-up; 277024244cefSSai Prakash Ranjan 277124244cefSSai Prakash Ranjan out-ports { 277224244cefSSai Prakash Ranjan port { 277324244cefSSai Prakash Ranjan etm3_out: endpoint { 277424244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in3>; 277524244cefSSai Prakash Ranjan }; 277624244cefSSai Prakash Ranjan }; 277724244cefSSai Prakash Ranjan }; 277824244cefSSai Prakash Ranjan }; 277924244cefSSai Prakash Ranjan 278024244cefSSai Prakash Ranjan etm@7440000 { 278124244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 278224244cefSSai Prakash Ranjan reg = <0 0x07440000 0 0x1000>; 278324244cefSSai Prakash Ranjan 278424244cefSSai Prakash Ranjan cpu = <&CPU4>; 278524244cefSSai Prakash Ranjan 278624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 278724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 278824244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 278924244cefSSai Prakash Ranjan qcom,skip-power-up; 279024244cefSSai Prakash Ranjan 279124244cefSSai Prakash Ranjan out-ports { 279224244cefSSai Prakash Ranjan port { 279324244cefSSai Prakash Ranjan etm4_out: endpoint { 279424244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in4>; 279524244cefSSai Prakash Ranjan }; 279624244cefSSai Prakash Ranjan }; 279724244cefSSai Prakash Ranjan }; 279824244cefSSai Prakash Ranjan }; 279924244cefSSai Prakash Ranjan 280024244cefSSai Prakash Ranjan etm@7540000 { 280124244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 280224244cefSSai Prakash Ranjan reg = <0 0x07540000 0 0x1000>; 280324244cefSSai Prakash Ranjan 280424244cefSSai Prakash Ranjan cpu = <&CPU5>; 280524244cefSSai Prakash Ranjan 280624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 280724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 280824244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 280924244cefSSai Prakash Ranjan qcom,skip-power-up; 281024244cefSSai Prakash Ranjan 281124244cefSSai Prakash Ranjan out-ports { 281224244cefSSai Prakash Ranjan port { 281324244cefSSai Prakash Ranjan etm5_out: endpoint { 281424244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in5>; 281524244cefSSai Prakash Ranjan }; 281624244cefSSai Prakash Ranjan }; 281724244cefSSai Prakash Ranjan }; 281824244cefSSai Prakash Ranjan }; 281924244cefSSai Prakash Ranjan 282024244cefSSai Prakash Ranjan etm@7640000 { 282124244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 282224244cefSSai Prakash Ranjan reg = <0 0x07640000 0 0x1000>; 282324244cefSSai Prakash Ranjan 282424244cefSSai Prakash Ranjan cpu = <&CPU6>; 282524244cefSSai Prakash Ranjan 282624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 282724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 282824244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 282924244cefSSai Prakash Ranjan qcom,skip-power-up; 283024244cefSSai Prakash Ranjan 283124244cefSSai Prakash Ranjan out-ports { 283224244cefSSai Prakash Ranjan port { 283324244cefSSai Prakash Ranjan etm6_out: endpoint { 283424244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in6>; 283524244cefSSai Prakash Ranjan }; 283624244cefSSai Prakash Ranjan }; 283724244cefSSai Prakash Ranjan }; 283824244cefSSai Prakash Ranjan }; 283924244cefSSai Prakash Ranjan 284024244cefSSai Prakash Ranjan etm@7740000 { 284124244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 284224244cefSSai Prakash Ranjan reg = <0 0x07740000 0 0x1000>; 284324244cefSSai Prakash Ranjan 284424244cefSSai Prakash Ranjan cpu = <&CPU7>; 284524244cefSSai Prakash Ranjan 284624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 284724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 284824244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 284924244cefSSai Prakash Ranjan qcom,skip-power-up; 285024244cefSSai Prakash Ranjan 285124244cefSSai Prakash Ranjan out-ports { 285224244cefSSai Prakash Ranjan port { 285324244cefSSai Prakash Ranjan etm7_out: endpoint { 285424244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in7>; 285524244cefSSai Prakash Ranjan }; 285624244cefSSai Prakash Ranjan }; 285724244cefSSai Prakash Ranjan }; 285824244cefSSai Prakash Ranjan }; 285924244cefSSai Prakash Ranjan 286024244cefSSai Prakash Ranjan funnel@7800000 { /* APSS Funnel */ 286124244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 286224244cefSSai Prakash Ranjan reg = <0 0x07800000 0 0x1000>; 286324244cefSSai Prakash Ranjan 286424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 286524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 286624244cefSSai Prakash Ranjan 286724244cefSSai Prakash Ranjan out-ports { 286824244cefSSai Prakash Ranjan port { 286924244cefSSai Prakash Ranjan apss_funnel_out: endpoint { 287024244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_in>; 287124244cefSSai Prakash Ranjan }; 287224244cefSSai Prakash Ranjan }; 287324244cefSSai Prakash Ranjan }; 287424244cefSSai Prakash Ranjan 287524244cefSSai Prakash Ranjan in-ports { 287624244cefSSai Prakash Ranjan #address-cells = <1>; 287724244cefSSai Prakash Ranjan #size-cells = <0>; 287824244cefSSai Prakash Ranjan 287924244cefSSai Prakash Ranjan port@0 { 288024244cefSSai Prakash Ranjan reg = <0>; 288124244cefSSai Prakash Ranjan apss_funnel_in0: endpoint { 288224244cefSSai Prakash Ranjan remote-endpoint = <&etm0_out>; 288324244cefSSai Prakash Ranjan }; 288424244cefSSai Prakash Ranjan }; 288524244cefSSai Prakash Ranjan 288624244cefSSai Prakash Ranjan port@1 { 288724244cefSSai Prakash Ranjan reg = <1>; 288824244cefSSai Prakash Ranjan apss_funnel_in1: endpoint { 288924244cefSSai Prakash Ranjan remote-endpoint = <&etm1_out>; 289024244cefSSai Prakash Ranjan }; 289124244cefSSai Prakash Ranjan }; 289224244cefSSai Prakash Ranjan 289324244cefSSai Prakash Ranjan port@2 { 289424244cefSSai Prakash Ranjan reg = <2>; 289524244cefSSai Prakash Ranjan apss_funnel_in2: endpoint { 289624244cefSSai Prakash Ranjan remote-endpoint = <&etm2_out>; 289724244cefSSai Prakash Ranjan }; 289824244cefSSai Prakash Ranjan }; 289924244cefSSai Prakash Ranjan 290024244cefSSai Prakash Ranjan port@3 { 290124244cefSSai Prakash Ranjan reg = <3>; 290224244cefSSai Prakash Ranjan apss_funnel_in3: endpoint { 290324244cefSSai Prakash Ranjan remote-endpoint = <&etm3_out>; 290424244cefSSai Prakash Ranjan }; 290524244cefSSai Prakash Ranjan }; 290624244cefSSai Prakash Ranjan 290724244cefSSai Prakash Ranjan port@4 { 290824244cefSSai Prakash Ranjan reg = <4>; 290924244cefSSai Prakash Ranjan apss_funnel_in4: endpoint { 291024244cefSSai Prakash Ranjan remote-endpoint = <&etm4_out>; 291124244cefSSai Prakash Ranjan }; 291224244cefSSai Prakash Ranjan }; 291324244cefSSai Prakash Ranjan 291424244cefSSai Prakash Ranjan port@5 { 291524244cefSSai Prakash Ranjan reg = <5>; 291624244cefSSai Prakash Ranjan apss_funnel_in5: endpoint { 291724244cefSSai Prakash Ranjan remote-endpoint = <&etm5_out>; 291824244cefSSai Prakash Ranjan }; 291924244cefSSai Prakash Ranjan }; 292024244cefSSai Prakash Ranjan 292124244cefSSai Prakash Ranjan port@6 { 292224244cefSSai Prakash Ranjan reg = <6>; 292324244cefSSai Prakash Ranjan apss_funnel_in6: endpoint { 292424244cefSSai Prakash Ranjan remote-endpoint = <&etm6_out>; 292524244cefSSai Prakash Ranjan }; 292624244cefSSai Prakash Ranjan }; 292724244cefSSai Prakash Ranjan 292824244cefSSai Prakash Ranjan port@7 { 292924244cefSSai Prakash Ranjan reg = <7>; 293024244cefSSai Prakash Ranjan apss_funnel_in7: endpoint { 293124244cefSSai Prakash Ranjan remote-endpoint = <&etm7_out>; 293224244cefSSai Prakash Ranjan }; 293324244cefSSai Prakash Ranjan }; 293424244cefSSai Prakash Ranjan }; 293524244cefSSai Prakash Ranjan }; 293624244cefSSai Prakash Ranjan 293724244cefSSai Prakash Ranjan funnel@7810000 { 293824244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 293924244cefSSai Prakash Ranjan reg = <0 0x07810000 0 0x1000>; 294024244cefSSai Prakash Ranjan 294124244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 294224244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 294324244cefSSai Prakash Ranjan 294424244cefSSai Prakash Ranjan out-ports { 294524244cefSSai Prakash Ranjan port { 294624244cefSSai Prakash Ranjan apss_merge_funnel_out: endpoint { 294724244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_in2>; 294824244cefSSai Prakash Ranjan }; 294924244cefSSai Prakash Ranjan }; 295024244cefSSai Prakash Ranjan }; 295124244cefSSai Prakash Ranjan 295224244cefSSai Prakash Ranjan in-ports { 295324244cefSSai Prakash Ranjan port { 295424244cefSSai Prakash Ranjan apss_merge_funnel_in: endpoint { 295524244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_out>; 295624244cefSSai Prakash Ranjan }; 295724244cefSSai Prakash Ranjan }; 295824244cefSSai Prakash Ranjan }; 295924244cefSSai Prakash Ranjan }; 296024244cefSSai Prakash Ranjan 296149076351SSibi Sankar remoteproc_cdsp: remoteproc@8300000 { 296249076351SSibi Sankar compatible = "qcom,sm8150-cdsp-pas"; 296349076351SSibi Sankar reg = <0x0 0x08300000 0x0 0x4040>; 296449076351SSibi Sankar 296549076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 296649076351SSibi Sankar <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 296749076351SSibi Sankar <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 296849076351SSibi Sankar <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 296949076351SSibi Sankar <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 297049076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 297149076351SSibi Sankar "handover", "stop-ack"; 297249076351SSibi Sankar 297349076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 297449076351SSibi Sankar clock-names = "xo"; 297549076351SSibi Sankar 2976d9d327f6SSibi Sankar power-domains = <&rpmhpd 7>; 297749076351SSibi Sankar 297849076351SSibi Sankar memory-region = <&cdsp_mem>; 297949076351SSibi Sankar 2980d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 2981d9d327f6SSibi Sankar 298249076351SSibi Sankar qcom,smem-states = <&cdsp_smp2p_out 0>; 298349076351SSibi Sankar qcom,smem-state-names = "stop"; 298449076351SSibi Sankar 298549076351SSibi Sankar status = "disabled"; 298649076351SSibi Sankar 298749076351SSibi Sankar glink-edge { 298849076351SSibi Sankar interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 298949076351SSibi Sankar label = "cdsp"; 299049076351SSibi Sankar qcom,remote-pid = <5>; 299149076351SSibi Sankar mboxes = <&apss_shared 4>; 299281729330SBhupesh Sharma 299381729330SBhupesh Sharma fastrpc { 299481729330SBhupesh Sharma compatible = "qcom,fastrpc"; 299581729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 299681729330SBhupesh Sharma label = "cdsp"; 2997*8c8ce95bSJeya R qcom,non-secure-domain; 299881729330SBhupesh Sharma #address-cells = <1>; 299981729330SBhupesh Sharma #size-cells = <0>; 300081729330SBhupesh Sharma 300181729330SBhupesh Sharma compute-cb@1 { 300281729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 300381729330SBhupesh Sharma reg = <1>; 300481729330SBhupesh Sharma iommus = <&apps_smmu 0x1401 0x2040>, 300581729330SBhupesh Sharma <&apps_smmu 0x1421 0x0>, 300681729330SBhupesh Sharma <&apps_smmu 0x2001 0x420>, 300781729330SBhupesh Sharma <&apps_smmu 0x2041 0x0>; 300881729330SBhupesh Sharma }; 300981729330SBhupesh Sharma 301081729330SBhupesh Sharma compute-cb@2 { 301181729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 301281729330SBhupesh Sharma reg = <2>; 301381729330SBhupesh Sharma iommus = <&apps_smmu 0x2 0x3440>, 301481729330SBhupesh Sharma <&apps_smmu 0x22 0x3400>; 301581729330SBhupesh Sharma }; 301681729330SBhupesh Sharma 301781729330SBhupesh Sharma compute-cb@3 { 301881729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 301981729330SBhupesh Sharma reg = <3>; 302081729330SBhupesh Sharma iommus = <&apps_smmu 0x3 0x3440>, 302181729330SBhupesh Sharma <&apps_smmu 0x1423 0x0>, 302281729330SBhupesh Sharma <&apps_smmu 0x2023 0x0>; 302381729330SBhupesh Sharma }; 302481729330SBhupesh Sharma 302581729330SBhupesh Sharma compute-cb@4 { 302681729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 302781729330SBhupesh Sharma reg = <4>; 302881729330SBhupesh Sharma iommus = <&apps_smmu 0x4 0x3440>, 302981729330SBhupesh Sharma <&apps_smmu 0x24 0x3400>; 303081729330SBhupesh Sharma }; 303181729330SBhupesh Sharma 303281729330SBhupesh Sharma compute-cb@5 { 303381729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 303481729330SBhupesh Sharma reg = <5>; 303581729330SBhupesh Sharma iommus = <&apps_smmu 0x5 0x3440>, 303681729330SBhupesh Sharma <&apps_smmu 0x25 0x3400>; 303781729330SBhupesh Sharma }; 303881729330SBhupesh Sharma 303981729330SBhupesh Sharma compute-cb@6 { 304081729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 304181729330SBhupesh Sharma reg = <6>; 304281729330SBhupesh Sharma iommus = <&apps_smmu 0x6 0x3460>; 304381729330SBhupesh Sharma }; 304481729330SBhupesh Sharma 304581729330SBhupesh Sharma compute-cb@7 { 304681729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 304781729330SBhupesh Sharma reg = <7>; 304881729330SBhupesh Sharma iommus = <&apps_smmu 0x7 0x3460>; 304981729330SBhupesh Sharma }; 305081729330SBhupesh Sharma 305181729330SBhupesh Sharma compute-cb@8 { 305281729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 305381729330SBhupesh Sharma reg = <8>; 305481729330SBhupesh Sharma iommus = <&apps_smmu 0x8 0x3460>; 305581729330SBhupesh Sharma }; 305681729330SBhupesh Sharma 305781729330SBhupesh Sharma /* note: secure cb9 in downstream */ 305881729330SBhupesh Sharma }; 305949076351SSibi Sankar }; 306049076351SSibi Sankar }; 306149076351SSibi Sankar 3062b33d2868SJack Pham usb_1_hsphy: phy@88e2000 { 3063b33d2868SJack Pham compatible = "qcom,sm8150-usb-hs-phy", 3064b33d2868SJack Pham "qcom,usb-snps-hs-7nm-phy"; 3065b33d2868SJack Pham reg = <0 0x088e2000 0 0x400>; 3066b33d2868SJack Pham status = "disabled"; 3067b33d2868SJack Pham #phy-cells = <0>; 3068b33d2868SJack Pham 3069b33d2868SJack Pham clocks = <&rpmhcc RPMH_CXO_CLK>; 3070b33d2868SJack Pham clock-names = "ref"; 3071b33d2868SJack Pham 3072b33d2868SJack Pham resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3073b33d2868SJack Pham }; 3074b33d2868SJack Pham 30750c9dde0dSJonathan Marek usb_2_hsphy: phy@88e3000 { 30760c9dde0dSJonathan Marek compatible = "qcom,sm8150-usb-hs-phy", 30770c9dde0dSJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 30780c9dde0dSJonathan Marek reg = <0 0x088e3000 0 0x400>; 30790c9dde0dSJonathan Marek status = "disabled"; 30800c9dde0dSJonathan Marek #phy-cells = <0>; 30810c9dde0dSJonathan Marek 30820c9dde0dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 30830c9dde0dSJonathan Marek clock-names = "ref"; 30840c9dde0dSJonathan Marek 30850c9dde0dSJonathan Marek resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 30860c9dde0dSJonathan Marek }; 30870c9dde0dSJonathan Marek 3088b33d2868SJack Pham usb_1_qmpphy: phy@88e9000 { 3089b33d2868SJack Pham compatible = "qcom,sm8150-qmp-usb3-phy"; 3090b33d2868SJack Pham reg = <0 0x088e9000 0 0x18c>, 3091b33d2868SJack Pham <0 0x088e8000 0 0x10>; 3092b33d2868SJack Pham status = "disabled"; 3093b33d2868SJack Pham #address-cells = <2>; 3094b33d2868SJack Pham #size-cells = <2>; 3095b33d2868SJack Pham ranges; 3096b33d2868SJack Pham 3097b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3098b33d2868SJack Pham <&rpmhcc RPMH_CXO_CLK>, 3099b33d2868SJack Pham <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3100b33d2868SJack Pham <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3101b33d2868SJack Pham clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3102b33d2868SJack Pham 3103b33d2868SJack Pham resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3104b33d2868SJack Pham <&gcc GCC_USB3_PHY_PRIM_BCR>; 3105b33d2868SJack Pham reset-names = "phy", "common"; 3106b33d2868SJack Pham 31071351512fSShawn Guo usb_1_ssphy: phy@88e9200 { 3108b33d2868SJack Pham reg = <0 0x088e9200 0 0x200>, 3109b33d2868SJack Pham <0 0x088e9400 0 0x200>, 3110b33d2868SJack Pham <0 0x088e9c00 0 0x218>, 3111b33d2868SJack Pham <0 0x088e9600 0 0x200>, 3112b33d2868SJack Pham <0 0x088e9800 0 0x200>, 3113b33d2868SJack Pham <0 0x088e9a00 0 0x100>; 31147178d4ccSJonathan Marek #clock-cells = <0>; 3115b33d2868SJack Pham #phy-cells = <0>; 3116b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3117b33d2868SJack Pham clock-names = "pipe0"; 3118b33d2868SJack Pham clock-output-names = "usb3_phy_pipe_clk_src"; 3119b33d2868SJack Pham }; 3120b33d2868SJack Pham }; 3121b33d2868SJack Pham 31220c9dde0dSJonathan Marek usb_2_qmpphy: phy@88eb000 { 31230c9dde0dSJonathan Marek compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 31240c9dde0dSJonathan Marek reg = <0 0x088eb000 0 0x200>; 31250c9dde0dSJonathan Marek status = "disabled"; 31260c9dde0dSJonathan Marek #address-cells = <2>; 31270c9dde0dSJonathan Marek #size-cells = <2>; 31280c9dde0dSJonathan Marek ranges; 31290c9dde0dSJonathan Marek 31300c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 31310c9dde0dSJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 31320c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>, 31330c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 31340c9dde0dSJonathan Marek clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 31350c9dde0dSJonathan Marek 31360c9dde0dSJonathan Marek resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 31370c9dde0dSJonathan Marek <&gcc GCC_USB3_PHY_SEC_BCR>; 31380c9dde0dSJonathan Marek reset-names = "phy", "common"; 31390c9dde0dSJonathan Marek 31401351512fSShawn Guo usb_2_ssphy: phy@88eb200 { 31410c9dde0dSJonathan Marek reg = <0 0x088eb200 0 0x200>, 31420c9dde0dSJonathan Marek <0 0x088eb400 0 0x200>, 31430c9dde0dSJonathan Marek <0 0x088eb800 0 0x800>, 31440c9dde0dSJonathan Marek <0 0x088eb600 0 0x200>; 31457178d4ccSJonathan Marek #clock-cells = <0>; 31460c9dde0dSJonathan Marek #phy-cells = <0>; 31470c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 31480c9dde0dSJonathan Marek clock-names = "pipe0"; 31490c9dde0dSJonathan Marek clock-output-names = "usb3_uni_phy_pipe_clk_src"; 31500c9dde0dSJonathan Marek }; 31510c9dde0dSJonathan Marek }; 31520c9dde0dSJonathan Marek 31535dc43d3bSBhupesh Sharma dc_noc: interconnect@9160000 { 31545dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-dc-noc"; 31555dc43d3bSBhupesh Sharma reg = <0 0x09160000 0 0x3200>; 31565dc43d3bSBhupesh Sharma #interconnect-cells = <1>; 31575dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 31585dc43d3bSBhupesh Sharma }; 31595dc43d3bSBhupesh Sharma 31605dc43d3bSBhupesh Sharma gem_noc: interconnect@9680000 { 31615dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-gem-noc"; 31625dc43d3bSBhupesh Sharma reg = <0 0x09680000 0 0x3e200>; 31635dc43d3bSBhupesh Sharma #interconnect-cells = <1>; 31645dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 31655dc43d3bSBhupesh Sharma }; 31665dc43d3bSBhupesh Sharma 3167b33d2868SJack Pham usb_1: usb@a6f8800 { 3168b33d2868SJack Pham compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3169b33d2868SJack Pham reg = <0 0x0a6f8800 0 0x400>; 3170b33d2868SJack Pham status = "disabled"; 3171b33d2868SJack Pham #address-cells = <2>; 3172b33d2868SJack Pham #size-cells = <2>; 3173b33d2868SJack Pham ranges; 3174b33d2868SJack Pham dma-ranges; 3175b33d2868SJack Pham 3176b33d2868SJack Pham clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3177b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3178b33d2868SJack Pham <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3179b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3180b33d2868SJack Pham <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3181b33d2868SJack Pham <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3182b33d2868SJack Pham clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3183b33d2868SJack Pham "sleep", "xo"; 3184b33d2868SJack Pham 3185b33d2868SJack Pham assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3186b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>; 318779493db5SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 3188b33d2868SJack Pham 3189b33d2868SJack Pham interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3190b33d2868SJack Pham <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3191b33d2868SJack Pham <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3192b33d2868SJack Pham <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3193b33d2868SJack Pham interrupt-names = "hs_phy_irq", "ss_phy_irq", 3194b33d2868SJack Pham "dm_hs_phy_irq", "dp_hs_phy_irq"; 3195b33d2868SJack Pham 3196b33d2868SJack Pham power-domains = <&gcc USB30_PRIM_GDSC>; 3197b33d2868SJack Pham 3198b33d2868SJack Pham resets = <&gcc GCC_USB30_PRIM_BCR>; 3199b33d2868SJack Pham 32001f958f3dSGreg Kroah-Hartman usb_1_dwc3: dwc3@a600000 { 3201b33d2868SJack Pham compatible = "snps,dwc3"; 3202b33d2868SJack Pham reg = <0 0x0a600000 0 0xcd00>; 3203b33d2868SJack Pham interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 320448156232SJonathan Marek iommus = <&apps_smmu 0x140 0>; 3205b33d2868SJack Pham snps,dis_u2_susphy_quirk; 3206b33d2868SJack Pham snps,dis_enblslpm_quirk; 3207b33d2868SJack Pham phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3208b33d2868SJack Pham phy-names = "usb2-phy", "usb3-phy"; 3209b33d2868SJack Pham }; 3210b33d2868SJack Pham }; 3211b33d2868SJack Pham 32120c9dde0dSJonathan Marek usb_2: usb@a8f8800 { 32130c9dde0dSJonathan Marek compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 32140c9dde0dSJonathan Marek reg = <0 0x0a8f8800 0 0x400>; 32150c9dde0dSJonathan Marek status = "disabled"; 32160c9dde0dSJonathan Marek #address-cells = <2>; 32170c9dde0dSJonathan Marek #size-cells = <2>; 32180c9dde0dSJonathan Marek ranges; 32190c9dde0dSJonathan Marek dma-ranges; 32200c9dde0dSJonathan Marek 32210c9dde0dSJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 32220c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>, 32230c9dde0dSJonathan Marek <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 32240c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 32250c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_SLEEP_CLK>, 32260c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>; 32270c9dde0dSJonathan Marek clock-names = "cfg_noc", "core", "iface", "mock_utmi", 32280c9dde0dSJonathan Marek "sleep", "xo"; 32290c9dde0dSJonathan Marek 32300c9dde0dSJonathan Marek assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 32310c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>; 32320c9dde0dSJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 32330c9dde0dSJonathan Marek 32340c9dde0dSJonathan Marek interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 32350c9dde0dSJonathan Marek <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 32360c9dde0dSJonathan Marek <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 32370c9dde0dSJonathan Marek <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 32380c9dde0dSJonathan Marek interrupt-names = "hs_phy_irq", "ss_phy_irq", 32390c9dde0dSJonathan Marek "dm_hs_phy_irq", "dp_hs_phy_irq"; 32400c9dde0dSJonathan Marek 32410c9dde0dSJonathan Marek power-domains = <&gcc USB30_SEC_GDSC>; 32420c9dde0dSJonathan Marek 32430c9dde0dSJonathan Marek resets = <&gcc GCC_USB30_SEC_BCR>; 32440c9dde0dSJonathan Marek 32452aa2b50dSBhupesh Sharma usb_2_dwc3: usb@a800000 { 32460c9dde0dSJonathan Marek compatible = "snps,dwc3"; 32470c9dde0dSJonathan Marek reg = <0 0x0a800000 0 0xcd00>; 32480c9dde0dSJonathan Marek interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 32490c9dde0dSJonathan Marek iommus = <&apps_smmu 0x160 0>; 32500c9dde0dSJonathan Marek snps,dis_u2_susphy_quirk; 32510c9dde0dSJonathan Marek snps,dis_enblslpm_quirk; 32520c9dde0dSJonathan Marek phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 32530c9dde0dSJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 32540c9dde0dSJonathan Marek }; 32550c9dde0dSJonathan Marek }; 32560c9dde0dSJonathan Marek 32576acb71fdSJonathan Marek camnoc_virt: interconnect@ac00000 { 32586acb71fdSJonathan Marek compatible = "qcom,sm8150-camnoc-virt"; 32596acb71fdSJonathan Marek reg = <0 0x0ac00000 0 0x1000>; 32606acb71fdSJonathan Marek #interconnect-cells = <1>; 32616acb71fdSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 32626acb71fdSJonathan Marek }; 32636acb71fdSJonathan Marek 3264d8cf9372SVinod Koul aoss_qmp: power-controller@c300000 { 3265d8cf9372SVinod Koul compatible = "qcom,sm8150-aoss-qmp"; 326647cb6a06SMaulik Shah reg = <0x0 0x0c300000 0x0 0x400>; 3267d8cf9372SVinod Koul interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3268d8cf9372SVinod Koul mboxes = <&apss_shared 0>; 3269d8cf9372SVinod Koul 3270d8cf9372SVinod Koul #clock-cells = <0>; 3271d8cf9372SVinod Koul }; 3272d8cf9372SVinod Koul 327347cb6a06SMaulik Shah sram@c3f0000 { 327447cb6a06SMaulik Shah compatible = "qcom,rpmh-stats"; 327547cb6a06SMaulik Shah reg = <0 0x0c3f0000 0 0x400>; 327647cb6a06SMaulik Shah }; 327747cb6a06SMaulik Shah 3278d2fa630cSAmit Kucheria tsens0: thermal-sensor@c263000 { 3279d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3280d2fa630cSAmit Kucheria reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3281d2fa630cSAmit Kucheria <0 0x0c222000 0 0x1ff>; /* SROT */ 3282d2fa630cSAmit Kucheria #qcom,sensors = <16>; 3283d2fa630cSAmit Kucheria interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3284d2fa630cSAmit Kucheria <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3285d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 3286d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 3287d2fa630cSAmit Kucheria }; 3288d2fa630cSAmit Kucheria 3289d2fa630cSAmit Kucheria tsens1: thermal-sensor@c265000 { 3290d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3291d2fa630cSAmit Kucheria reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3292d2fa630cSAmit Kucheria <0 0x0c223000 0 0x1ff>; /* SROT */ 3293d2fa630cSAmit Kucheria #qcom,sensors = <8>; 3294d2fa630cSAmit Kucheria interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3295d2fa630cSAmit Kucheria <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3296d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 3297d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 3298d2fa630cSAmit Kucheria }; 3299d2fa630cSAmit Kucheria 3300e13c6d14SVinod Koul spmi_bus: spmi@c440000 { 3301e13c6d14SVinod Koul compatible = "qcom,spmi-pmic-arb"; 3302e13c6d14SVinod Koul reg = <0x0 0x0c440000 0x0 0x0001100>, 3303e13c6d14SVinod Koul <0x0 0x0c600000 0x0 0x2000000>, 3304e13c6d14SVinod Koul <0x0 0x0e600000 0x0 0x0100000>, 3305e13c6d14SVinod Koul <0x0 0x0e700000 0x0 0x00a0000>, 3306e13c6d14SVinod Koul <0x0 0x0c40a000 0x0 0x0026000>; 3307e13c6d14SVinod Koul reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3308e13c6d14SVinod Koul interrupt-names = "periph_irq"; 3309e13c6d14SVinod Koul interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3310e13c6d14SVinod Koul qcom,ee = <0>; 3311e13c6d14SVinod Koul qcom,channel = <0>; 3312e13c6d14SVinod Koul #address-cells = <2>; 3313e13c6d14SVinod Koul #size-cells = <0>; 3314e13c6d14SVinod Koul interrupt-controller; 3315e13c6d14SVinod Koul #interrupt-cells = <4>; 3316e13c6d14SVinod Koul cell-index = <0>; 3317e13c6d14SVinod Koul }; 3318e13c6d14SVinod Koul 331948156232SJonathan Marek apps_smmu: iommu@15000000 { 332048156232SJonathan Marek compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 332148156232SJonathan Marek reg = <0 0x15000000 0 0x100000>; 332248156232SJonathan Marek #iommu-cells = <2>; 332348156232SJonathan Marek #global-interrupts = <1>; 332448156232SJonathan Marek interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 332548156232SJonathan Marek <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 332648156232SJonathan Marek <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 332748156232SJonathan Marek <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 332848156232SJonathan Marek <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 332948156232SJonathan Marek <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 333048156232SJonathan Marek <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 333148156232SJonathan Marek <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 333248156232SJonathan Marek <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 333348156232SJonathan Marek <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 333448156232SJonathan Marek <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 333548156232SJonathan Marek <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 333648156232SJonathan Marek <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 333748156232SJonathan Marek <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 333848156232SJonathan Marek <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 333948156232SJonathan Marek <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 334048156232SJonathan Marek <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 334148156232SJonathan Marek <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 334248156232SJonathan Marek <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 334348156232SJonathan Marek <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 334448156232SJonathan Marek <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 334548156232SJonathan Marek <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 334648156232SJonathan Marek <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 334748156232SJonathan Marek <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 334848156232SJonathan Marek <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 334948156232SJonathan Marek <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 335048156232SJonathan Marek <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 335148156232SJonathan Marek <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 335248156232SJonathan Marek <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 335348156232SJonathan Marek <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 335448156232SJonathan Marek <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 335548156232SJonathan Marek <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 335648156232SJonathan Marek <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 335748156232SJonathan Marek <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 335848156232SJonathan Marek <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 335948156232SJonathan Marek <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 336048156232SJonathan Marek <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 336148156232SJonathan Marek <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 336248156232SJonathan Marek <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 336348156232SJonathan Marek <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 336448156232SJonathan Marek <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 336548156232SJonathan Marek <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 336648156232SJonathan Marek <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 336748156232SJonathan Marek <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 336848156232SJonathan Marek <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 336948156232SJonathan Marek <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 337048156232SJonathan Marek <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 337148156232SJonathan Marek <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 337248156232SJonathan Marek <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 337348156232SJonathan Marek <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 337448156232SJonathan Marek <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 337548156232SJonathan Marek <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 337648156232SJonathan Marek <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 337748156232SJonathan Marek <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 337848156232SJonathan Marek <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 337948156232SJonathan Marek <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 338048156232SJonathan Marek <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 338148156232SJonathan Marek <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 338248156232SJonathan Marek <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 338348156232SJonathan Marek <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 338448156232SJonathan Marek <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 338548156232SJonathan Marek <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 338648156232SJonathan Marek <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 338748156232SJonathan Marek <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 338848156232SJonathan Marek <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 338948156232SJonathan Marek <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 339048156232SJonathan Marek <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 339148156232SJonathan Marek <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 339248156232SJonathan Marek <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 339348156232SJonathan Marek <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 339448156232SJonathan Marek <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 339548156232SJonathan Marek <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 339648156232SJonathan Marek <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 339748156232SJonathan Marek <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 339848156232SJonathan Marek <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 339948156232SJonathan Marek <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 340048156232SJonathan Marek <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 340148156232SJonathan Marek <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 340248156232SJonathan Marek <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 340348156232SJonathan Marek <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 340448156232SJonathan Marek <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 340548156232SJonathan Marek }; 340648156232SJonathan Marek 340749076351SSibi Sankar remoteproc_adsp: remoteproc@17300000 { 340849076351SSibi Sankar compatible = "qcom,sm8150-adsp-pas"; 340949076351SSibi Sankar reg = <0x0 0x17300000 0x0 0x4040>; 341049076351SSibi Sankar 341149076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 341249076351SSibi Sankar <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 341349076351SSibi Sankar <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 341449076351SSibi Sankar <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 341549076351SSibi Sankar <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 341649076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 341749076351SSibi Sankar "handover", "stop-ack"; 341849076351SSibi Sankar 341949076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 342049076351SSibi Sankar clock-names = "xo"; 342149076351SSibi Sankar 3422d9d327f6SSibi Sankar power-domains = <&rpmhpd 7>; 342349076351SSibi Sankar 342449076351SSibi Sankar memory-region = <&adsp_mem>; 342549076351SSibi Sankar 3426d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 3427d9d327f6SSibi Sankar 342849076351SSibi Sankar qcom,smem-states = <&adsp_smp2p_out 0>; 342949076351SSibi Sankar qcom,smem-state-names = "stop"; 343049076351SSibi Sankar 343149076351SSibi Sankar status = "disabled"; 343249076351SSibi Sankar 343349076351SSibi Sankar glink-edge { 343449076351SSibi Sankar interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 343549076351SSibi Sankar label = "lpass"; 343649076351SSibi Sankar qcom,remote-pid = <2>; 343749076351SSibi Sankar mboxes = <&apss_shared 8>; 343881729330SBhupesh Sharma 343981729330SBhupesh Sharma fastrpc { 344081729330SBhupesh Sharma compatible = "qcom,fastrpc"; 344181729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 344281729330SBhupesh Sharma label = "adsp"; 3443*8c8ce95bSJeya R qcom,non-secure-domain; 344481729330SBhupesh Sharma #address-cells = <1>; 344581729330SBhupesh Sharma #size-cells = <0>; 344681729330SBhupesh Sharma 344781729330SBhupesh Sharma compute-cb@3 { 344881729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 344981729330SBhupesh Sharma reg = <3>; 345081729330SBhupesh Sharma iommus = <&apps_smmu 0x1b23 0x0>; 345181729330SBhupesh Sharma }; 345281729330SBhupesh Sharma 345381729330SBhupesh Sharma compute-cb@4 { 345481729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 345581729330SBhupesh Sharma reg = <4>; 345681729330SBhupesh Sharma iommus = <&apps_smmu 0x1b24 0x0>; 345781729330SBhupesh Sharma }; 345881729330SBhupesh Sharma 345981729330SBhupesh Sharma compute-cb@5 { 346081729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 346181729330SBhupesh Sharma reg = <5>; 346281729330SBhupesh Sharma iommus = <&apps_smmu 0x1b25 0x0>; 346381729330SBhupesh Sharma }; 346481729330SBhupesh Sharma }; 346549076351SSibi Sankar }; 346649076351SSibi Sankar }; 346749076351SSibi Sankar 3468e13c6d14SVinod Koul intc: interrupt-controller@17a00000 { 3469e13c6d14SVinod Koul compatible = "arm,gic-v3"; 3470e13c6d14SVinod Koul interrupt-controller; 3471e13c6d14SVinod Koul #interrupt-cells = <3>; 3472e13c6d14SVinod Koul reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3473e13c6d14SVinod Koul <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3474e13c6d14SVinod Koul interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3475e13c6d14SVinod Koul }; 3476e13c6d14SVinod Koul 3477d8cf9372SVinod Koul apss_shared: mailbox@17c00000 { 3478d8cf9372SVinod Koul compatible = "qcom,sm8150-apss-shared"; 3479d8cf9372SVinod Koul reg = <0x0 0x17c00000 0x0 0x1000>; 3480d8cf9372SVinod Koul #mbox-cells = <1>; 3481d8cf9372SVinod Koul }; 3482d8cf9372SVinod Koul 3483fb2d8150SSai Prakash Ranjan watchdog@17c10000 { 3484fb2d8150SSai Prakash Ranjan compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 3485fb2d8150SSai Prakash Ranjan reg = <0 0x17c10000 0 0x1000>; 3486fb2d8150SSai Prakash Ranjan clocks = <&sleep_clk>; 3487b094c8f8SSai Prakash Ranjan interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3488fb2d8150SSai Prakash Ranjan }; 3489fb2d8150SSai Prakash Ranjan 3490e13c6d14SVinod Koul timer@17c20000 { 3491e13c6d14SVinod Koul #address-cells = <2>; 3492e13c6d14SVinod Koul #size-cells = <2>; 3493e13c6d14SVinod Koul ranges; 3494e13c6d14SVinod Koul compatible = "arm,armv7-timer-mem"; 3495e13c6d14SVinod Koul reg = <0x0 0x17c20000 0x0 0x1000>; 3496e13c6d14SVinod Koul clock-frequency = <19200000>; 3497e13c6d14SVinod Koul 3498e13c6d14SVinod Koul frame@17c21000{ 3499e13c6d14SVinod Koul frame-number = <0>; 3500e13c6d14SVinod Koul interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3501e13c6d14SVinod Koul <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3502e13c6d14SVinod Koul reg = <0x0 0x17c21000 0x0 0x1000>, 3503e13c6d14SVinod Koul <0x0 0x17c22000 0x0 0x1000>; 3504e13c6d14SVinod Koul }; 3505e13c6d14SVinod Koul 3506e13c6d14SVinod Koul frame@17c23000 { 3507e13c6d14SVinod Koul frame-number = <1>; 3508e13c6d14SVinod Koul interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3509e13c6d14SVinod Koul reg = <0x0 0x17c23000 0x0 0x1000>; 3510e13c6d14SVinod Koul status = "disabled"; 3511e13c6d14SVinod Koul }; 3512e13c6d14SVinod Koul 3513e13c6d14SVinod Koul frame@17c25000 { 3514e13c6d14SVinod Koul frame-number = <2>; 3515e13c6d14SVinod Koul interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3516e13c6d14SVinod Koul reg = <0x0 0x17c25000 0x0 0x1000>; 3517e13c6d14SVinod Koul status = "disabled"; 3518e13c6d14SVinod Koul }; 3519e13c6d14SVinod Koul 3520e13c6d14SVinod Koul frame@17c27000 { 3521e13c6d14SVinod Koul frame-number = <3>; 3522e13c6d14SVinod Koul interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3523e13c6d14SVinod Koul reg = <0x0 0x17c26000 0x0 0x1000>; 3524e13c6d14SVinod Koul status = "disabled"; 3525e13c6d14SVinod Koul }; 3526e13c6d14SVinod Koul 3527e13c6d14SVinod Koul frame@17c29000 { 3528e13c6d14SVinod Koul frame-number = <4>; 3529e13c6d14SVinod Koul interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3530e13c6d14SVinod Koul reg = <0x0 0x17c29000 0x0 0x1000>; 3531e13c6d14SVinod Koul status = "disabled"; 3532e13c6d14SVinod Koul }; 3533e13c6d14SVinod Koul 3534e13c6d14SVinod Koul frame@17c2b000 { 3535e13c6d14SVinod Koul frame-number = <5>; 3536e13c6d14SVinod Koul interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3537e13c6d14SVinod Koul reg = <0x0 0x17c2b000 0x0 0x1000>; 3538e13c6d14SVinod Koul status = "disabled"; 3539e13c6d14SVinod Koul }; 3540e13c6d14SVinod Koul 3541e13c6d14SVinod Koul frame@17c2d000 { 3542e13c6d14SVinod Koul frame-number = <6>; 3543e13c6d14SVinod Koul interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3544e13c6d14SVinod Koul reg = <0x0 0x17c2d000 0x0 0x1000>; 3545e13c6d14SVinod Koul status = "disabled"; 3546e13c6d14SVinod Koul }; 3547e13c6d14SVinod Koul }; 3548d8cf9372SVinod Koul 3549d8cf9372SVinod Koul apps_rsc: rsc@18200000 { 3550d8cf9372SVinod Koul label = "apps_rsc"; 3551d8cf9372SVinod Koul compatible = "qcom,rpmh-rsc"; 3552d8cf9372SVinod Koul reg = <0x0 0x18200000 0x0 0x10000>, 3553d8cf9372SVinod Koul <0x0 0x18210000 0x0 0x10000>, 3554d8cf9372SVinod Koul <0x0 0x18220000 0x0 0x10000>; 3555d8cf9372SVinod Koul reg-names = "drv-0", "drv-1", "drv-2"; 3556d8cf9372SVinod Koul interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3557d8cf9372SVinod Koul <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3558d8cf9372SVinod Koul <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3559d8cf9372SVinod Koul qcom,tcs-offset = <0xd00>; 3560d8cf9372SVinod Koul qcom,drv-id = <2>; 3561d8cf9372SVinod Koul qcom,tcs-config = <ACTIVE_TCS 2>, 3562d8cf9372SVinod Koul <SLEEP_TCS 1>, 3563d8cf9372SVinod Koul <WAKE_TCS 1>, 3564d8cf9372SVinod Koul <CONTROL_TCS 0>; 3565d8cf9372SVinod Koul 3566d8cf9372SVinod Koul rpmhcc: clock-controller { 3567d8cf9372SVinod Koul compatible = "qcom,sm8150-rpmh-clk"; 3568d8cf9372SVinod Koul #clock-cells = <1>; 3569d8cf9372SVinod Koul clock-names = "xo"; 3570d8cf9372SVinod Koul clocks = <&xo_board>; 3571d8cf9372SVinod Koul }; 3572017e7856SSibi Sankar 3573017e7856SSibi Sankar rpmhpd: power-controller { 3574017e7856SSibi Sankar compatible = "qcom,sm8150-rpmhpd"; 3575017e7856SSibi Sankar #power-domain-cells = <1>; 3576017e7856SSibi Sankar operating-points-v2 = <&rpmhpd_opp_table>; 3577017e7856SSibi Sankar 3578017e7856SSibi Sankar rpmhpd_opp_table: opp-table { 3579017e7856SSibi Sankar compatible = "operating-points-v2"; 3580017e7856SSibi Sankar 3581017e7856SSibi Sankar rpmhpd_opp_ret: opp1 { 3582017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3583017e7856SSibi Sankar }; 3584017e7856SSibi Sankar 3585017e7856SSibi Sankar rpmhpd_opp_min_svs: opp2 { 3586017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3587017e7856SSibi Sankar }; 3588017e7856SSibi Sankar 3589017e7856SSibi Sankar rpmhpd_opp_low_svs: opp3 { 3590017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3591017e7856SSibi Sankar }; 3592017e7856SSibi Sankar 3593017e7856SSibi Sankar rpmhpd_opp_svs: opp4 { 3594017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3595017e7856SSibi Sankar }; 3596017e7856SSibi Sankar 3597017e7856SSibi Sankar rpmhpd_opp_svs_l1: opp5 { 3598017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3599017e7856SSibi Sankar }; 3600017e7856SSibi Sankar 3601017e7856SSibi Sankar rpmhpd_opp_svs_l2: opp6 { 3602017e7856SSibi Sankar opp-level = <224>; 3603017e7856SSibi Sankar }; 3604017e7856SSibi Sankar 3605017e7856SSibi Sankar rpmhpd_opp_nom: opp7 { 3606017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3607017e7856SSibi Sankar }; 3608017e7856SSibi Sankar 3609017e7856SSibi Sankar rpmhpd_opp_nom_l1: opp8 { 3610017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3611017e7856SSibi Sankar }; 3612017e7856SSibi Sankar 3613017e7856SSibi Sankar rpmhpd_opp_nom_l2: opp9 { 3614017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3615017e7856SSibi Sankar }; 3616017e7856SSibi Sankar 3617017e7856SSibi Sankar rpmhpd_opp_turbo: opp10 { 3618017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3619017e7856SSibi Sankar }; 3620017e7856SSibi Sankar 3621017e7856SSibi Sankar rpmhpd_opp_turbo_l1: opp11 { 3622017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3623017e7856SSibi Sankar }; 3624017e7856SSibi Sankar }; 3625017e7856SSibi Sankar }; 362671a2fc6eSJonathan Marek 362771a2fc6eSJonathan Marek apps_bcm_voter: bcm_voter { 362871a2fc6eSJonathan Marek compatible = "qcom,bcm-voter"; 362971a2fc6eSJonathan Marek }; 3630d8cf9372SVinod Koul }; 3631fea8930bSSibi Sankar 3632a6d435c1SSibi Sankar osm_l3: interconnect@18321000 { 3633a6d435c1SSibi Sankar compatible = "qcom,sm8150-osm-l3"; 3634a6d435c1SSibi Sankar reg = <0 0x18321000 0 0x1400>; 3635a6d435c1SSibi Sankar 3636a6d435c1SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3637a6d435c1SSibi Sankar clock-names = "xo", "alternate"; 3638a6d435c1SSibi Sankar 3639a6d435c1SSibi Sankar #interconnect-cells = <1>; 3640a6d435c1SSibi Sankar }; 3641a6d435c1SSibi Sankar 3642fea8930bSSibi Sankar cpufreq_hw: cpufreq@18323000 { 3643fea8930bSSibi Sankar compatible = "qcom,cpufreq-hw"; 3644fea8930bSSibi Sankar reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 3645fea8930bSSibi Sankar <0 0x18327800 0 0x1400>; 3646fea8930bSSibi Sankar reg-names = "freq-domain0", "freq-domain1", 3647fea8930bSSibi Sankar "freq-domain2"; 3648fea8930bSSibi Sankar 3649fea8930bSSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3650fea8930bSSibi Sankar clock-names = "xo", "alternate"; 3651fea8930bSSibi Sankar 3652fea8930bSSibi Sankar #freq-domain-cells = <1>; 3653fea8930bSSibi Sankar }; 365405090bb9SJonathan Marek 365505090bb9SJonathan Marek wifi: wifi@18800000 { 365605090bb9SJonathan Marek compatible = "qcom,wcn3990-wifi"; 365705090bb9SJonathan Marek reg = <0 0x18800000 0 0x800000>; 365805090bb9SJonathan Marek reg-names = "membase"; 365905090bb9SJonathan Marek memory-region = <&wlan_mem>; 366005090bb9SJonathan Marek clock-names = "cxo_ref_clk_pin", "qdss"; 366105090bb9SJonathan Marek clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 366205090bb9SJonathan Marek interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 366305090bb9SJonathan Marek <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 366405090bb9SJonathan Marek <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 366505090bb9SJonathan Marek <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 366605090bb9SJonathan Marek <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 366705090bb9SJonathan Marek <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 366805090bb9SJonathan Marek <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 366905090bb9SJonathan Marek <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 367005090bb9SJonathan Marek <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 367105090bb9SJonathan Marek <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 367205090bb9SJonathan Marek <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 367305090bb9SJonathan Marek <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 367405090bb9SJonathan Marek iommus = <&apps_smmu 0x0640 0x1>; 367505090bb9SJonathan Marek status = "disabled"; 367605090bb9SJonathan Marek }; 3677e13c6d14SVinod Koul }; 3678e13c6d14SVinod Koul 3679e13c6d14SVinod Koul timer { 3680e13c6d14SVinod Koul compatible = "arm,armv8-timer"; 3681e13c6d14SVinod Koul interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 3682e13c6d14SVinod Koul <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 3683e13c6d14SVinod Koul <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 3684e13c6d14SVinod Koul <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 3685e13c6d14SVinod Koul }; 3686d2fa630cSAmit Kucheria 3687d2fa630cSAmit Kucheria thermal-zones { 3688d2fa630cSAmit Kucheria cpu0-thermal { 3689d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3690d2fa630cSAmit Kucheria polling-delay = <1000>; 3691d2fa630cSAmit Kucheria 3692d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 1>; 3693d2fa630cSAmit Kucheria 3694d2fa630cSAmit Kucheria trips { 3695d2fa630cSAmit Kucheria cpu0_alert0: trip-point0 { 3696d2fa630cSAmit Kucheria temperature = <90000>; 3697d2fa630cSAmit Kucheria hysteresis = <2000>; 3698d2fa630cSAmit Kucheria type = "passive"; 3699d2fa630cSAmit Kucheria }; 3700d2fa630cSAmit Kucheria 3701d2fa630cSAmit Kucheria cpu0_alert1: trip-point1 { 3702d2fa630cSAmit Kucheria temperature = <95000>; 3703d2fa630cSAmit Kucheria hysteresis = <2000>; 3704d2fa630cSAmit Kucheria type = "passive"; 3705d2fa630cSAmit Kucheria }; 3706d2fa630cSAmit Kucheria 3707d2fa630cSAmit Kucheria cpu0_crit: cpu_crit { 3708d2fa630cSAmit Kucheria temperature = <110000>; 3709d2fa630cSAmit Kucheria hysteresis = <1000>; 3710d2fa630cSAmit Kucheria type = "critical"; 3711d2fa630cSAmit Kucheria }; 3712d2fa630cSAmit Kucheria }; 3713d2fa630cSAmit Kucheria 3714d2fa630cSAmit Kucheria cooling-maps { 3715d2fa630cSAmit Kucheria map0 { 3716d2fa630cSAmit Kucheria trip = <&cpu0_alert0>; 3717d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3718d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3719d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3720d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3721d2fa630cSAmit Kucheria }; 3722d2fa630cSAmit Kucheria map1 { 3723d2fa630cSAmit Kucheria trip = <&cpu0_alert1>; 3724d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3725d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3726d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3727d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3728d2fa630cSAmit Kucheria }; 3729d2fa630cSAmit Kucheria }; 3730d2fa630cSAmit Kucheria }; 3731d2fa630cSAmit Kucheria 3732d2fa630cSAmit Kucheria cpu1-thermal { 3733d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3734d2fa630cSAmit Kucheria polling-delay = <1000>; 3735d2fa630cSAmit Kucheria 3736d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 2>; 3737d2fa630cSAmit Kucheria 3738d2fa630cSAmit Kucheria trips { 3739d2fa630cSAmit Kucheria cpu1_alert0: trip-point0 { 3740d2fa630cSAmit Kucheria temperature = <90000>; 3741d2fa630cSAmit Kucheria hysteresis = <2000>; 3742d2fa630cSAmit Kucheria type = "passive"; 3743d2fa630cSAmit Kucheria }; 3744d2fa630cSAmit Kucheria 3745d2fa630cSAmit Kucheria cpu1_alert1: trip-point1 { 3746d2fa630cSAmit Kucheria temperature = <95000>; 3747d2fa630cSAmit Kucheria hysteresis = <2000>; 3748d2fa630cSAmit Kucheria type = "passive"; 3749d2fa630cSAmit Kucheria }; 3750d2fa630cSAmit Kucheria 3751d2fa630cSAmit Kucheria cpu1_crit: cpu_crit { 3752d2fa630cSAmit Kucheria temperature = <110000>; 3753d2fa630cSAmit Kucheria hysteresis = <1000>; 3754d2fa630cSAmit Kucheria type = "critical"; 3755d2fa630cSAmit Kucheria }; 3756d2fa630cSAmit Kucheria }; 3757d2fa630cSAmit Kucheria 3758d2fa630cSAmit Kucheria cooling-maps { 3759d2fa630cSAmit Kucheria map0 { 3760d2fa630cSAmit Kucheria trip = <&cpu1_alert0>; 3761d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3762d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3763d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3764d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3765d2fa630cSAmit Kucheria }; 3766d2fa630cSAmit Kucheria map1 { 3767d2fa630cSAmit Kucheria trip = <&cpu1_alert1>; 3768d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3769d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3770d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3771d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3772d2fa630cSAmit Kucheria }; 3773d2fa630cSAmit Kucheria }; 3774d2fa630cSAmit Kucheria }; 3775d2fa630cSAmit Kucheria 3776d2fa630cSAmit Kucheria cpu2-thermal { 3777d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3778d2fa630cSAmit Kucheria polling-delay = <1000>; 3779d2fa630cSAmit Kucheria 3780d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 3>; 3781d2fa630cSAmit Kucheria 3782d2fa630cSAmit Kucheria trips { 3783d2fa630cSAmit Kucheria cpu2_alert0: trip-point0 { 3784d2fa630cSAmit Kucheria temperature = <90000>; 3785d2fa630cSAmit Kucheria hysteresis = <2000>; 3786d2fa630cSAmit Kucheria type = "passive"; 3787d2fa630cSAmit Kucheria }; 3788d2fa630cSAmit Kucheria 3789d2fa630cSAmit Kucheria cpu2_alert1: trip-point1 { 3790d2fa630cSAmit Kucheria temperature = <95000>; 3791d2fa630cSAmit Kucheria hysteresis = <2000>; 3792d2fa630cSAmit Kucheria type = "passive"; 3793d2fa630cSAmit Kucheria }; 3794d2fa630cSAmit Kucheria 3795d2fa630cSAmit Kucheria cpu2_crit: cpu_crit { 3796d2fa630cSAmit Kucheria temperature = <110000>; 3797d2fa630cSAmit Kucheria hysteresis = <1000>; 3798d2fa630cSAmit Kucheria type = "critical"; 3799d2fa630cSAmit Kucheria }; 3800d2fa630cSAmit Kucheria }; 3801d2fa630cSAmit Kucheria 3802d2fa630cSAmit Kucheria cooling-maps { 3803d2fa630cSAmit Kucheria map0 { 3804d2fa630cSAmit Kucheria trip = <&cpu2_alert0>; 3805d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3806d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3807d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3808d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3809d2fa630cSAmit Kucheria }; 3810d2fa630cSAmit Kucheria map1 { 3811d2fa630cSAmit Kucheria trip = <&cpu2_alert1>; 3812d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3813d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3814d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3815d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3816d2fa630cSAmit Kucheria }; 3817d2fa630cSAmit Kucheria }; 3818d2fa630cSAmit Kucheria }; 3819d2fa630cSAmit Kucheria 3820d2fa630cSAmit Kucheria cpu3-thermal { 3821d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3822d2fa630cSAmit Kucheria polling-delay = <1000>; 3823d2fa630cSAmit Kucheria 3824d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 4>; 3825d2fa630cSAmit Kucheria 3826d2fa630cSAmit Kucheria trips { 3827d2fa630cSAmit Kucheria cpu3_alert0: trip-point0 { 3828d2fa630cSAmit Kucheria temperature = <90000>; 3829d2fa630cSAmit Kucheria hysteresis = <2000>; 3830d2fa630cSAmit Kucheria type = "passive"; 3831d2fa630cSAmit Kucheria }; 3832d2fa630cSAmit Kucheria 3833d2fa630cSAmit Kucheria cpu3_alert1: trip-point1 { 3834d2fa630cSAmit Kucheria temperature = <95000>; 3835d2fa630cSAmit Kucheria hysteresis = <2000>; 3836d2fa630cSAmit Kucheria type = "passive"; 3837d2fa630cSAmit Kucheria }; 3838d2fa630cSAmit Kucheria 3839d2fa630cSAmit Kucheria cpu3_crit: cpu_crit { 3840d2fa630cSAmit Kucheria temperature = <110000>; 3841d2fa630cSAmit Kucheria hysteresis = <1000>; 3842d2fa630cSAmit Kucheria type = "critical"; 3843d2fa630cSAmit Kucheria }; 3844d2fa630cSAmit Kucheria }; 3845d2fa630cSAmit Kucheria 3846d2fa630cSAmit Kucheria cooling-maps { 3847d2fa630cSAmit Kucheria map0 { 3848d2fa630cSAmit Kucheria trip = <&cpu3_alert0>; 3849d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3850d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3851d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3852d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3853d2fa630cSAmit Kucheria }; 3854d2fa630cSAmit Kucheria map1 { 3855d2fa630cSAmit Kucheria trip = <&cpu3_alert1>; 3856d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3857d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3858d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3859d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3860d2fa630cSAmit Kucheria }; 3861d2fa630cSAmit Kucheria }; 3862d2fa630cSAmit Kucheria }; 3863d2fa630cSAmit Kucheria 3864d2fa630cSAmit Kucheria cpu4-top-thermal { 3865d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3866d2fa630cSAmit Kucheria polling-delay = <1000>; 3867d2fa630cSAmit Kucheria 3868d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 7>; 3869d2fa630cSAmit Kucheria 3870d2fa630cSAmit Kucheria trips { 3871d2fa630cSAmit Kucheria cpu4_top_alert0: trip-point0 { 3872d2fa630cSAmit Kucheria temperature = <90000>; 3873d2fa630cSAmit Kucheria hysteresis = <2000>; 3874d2fa630cSAmit Kucheria type = "passive"; 3875d2fa630cSAmit Kucheria }; 3876d2fa630cSAmit Kucheria 3877d2fa630cSAmit Kucheria cpu4_top_alert1: trip-point1 { 3878d2fa630cSAmit Kucheria temperature = <95000>; 3879d2fa630cSAmit Kucheria hysteresis = <2000>; 3880d2fa630cSAmit Kucheria type = "passive"; 3881d2fa630cSAmit Kucheria }; 3882d2fa630cSAmit Kucheria 3883d2fa630cSAmit Kucheria cpu4_top_crit: cpu_crit { 3884d2fa630cSAmit Kucheria temperature = <110000>; 3885d2fa630cSAmit Kucheria hysteresis = <1000>; 3886d2fa630cSAmit Kucheria type = "critical"; 3887d2fa630cSAmit Kucheria }; 3888d2fa630cSAmit Kucheria }; 3889d2fa630cSAmit Kucheria 3890d2fa630cSAmit Kucheria cooling-maps { 3891d2fa630cSAmit Kucheria map0 { 3892d2fa630cSAmit Kucheria trip = <&cpu4_top_alert0>; 3893d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3894d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3895d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3896d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3897d2fa630cSAmit Kucheria }; 3898d2fa630cSAmit Kucheria map1 { 3899d2fa630cSAmit Kucheria trip = <&cpu4_top_alert1>; 3900d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3901d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3902d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3903d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3904d2fa630cSAmit Kucheria }; 3905d2fa630cSAmit Kucheria }; 3906d2fa630cSAmit Kucheria }; 3907d2fa630cSAmit Kucheria 3908d2fa630cSAmit Kucheria cpu5-top-thermal { 3909d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3910d2fa630cSAmit Kucheria polling-delay = <1000>; 3911d2fa630cSAmit Kucheria 3912d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 8>; 3913d2fa630cSAmit Kucheria 3914d2fa630cSAmit Kucheria trips { 3915d2fa630cSAmit Kucheria cpu5_top_alert0: trip-point0 { 3916d2fa630cSAmit Kucheria temperature = <90000>; 3917d2fa630cSAmit Kucheria hysteresis = <2000>; 3918d2fa630cSAmit Kucheria type = "passive"; 3919d2fa630cSAmit Kucheria }; 3920d2fa630cSAmit Kucheria 3921d2fa630cSAmit Kucheria cpu5_top_alert1: trip-point1 { 3922d2fa630cSAmit Kucheria temperature = <95000>; 3923d2fa630cSAmit Kucheria hysteresis = <2000>; 3924d2fa630cSAmit Kucheria type = "passive"; 3925d2fa630cSAmit Kucheria }; 3926d2fa630cSAmit Kucheria 3927d2fa630cSAmit Kucheria cpu5_top_crit: cpu_crit { 3928d2fa630cSAmit Kucheria temperature = <110000>; 3929d2fa630cSAmit Kucheria hysteresis = <1000>; 3930d2fa630cSAmit Kucheria type = "critical"; 3931d2fa630cSAmit Kucheria }; 3932d2fa630cSAmit Kucheria }; 3933d2fa630cSAmit Kucheria 3934d2fa630cSAmit Kucheria cooling-maps { 3935d2fa630cSAmit Kucheria map0 { 3936d2fa630cSAmit Kucheria trip = <&cpu5_top_alert0>; 3937d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3938d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3939d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3940d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3941d2fa630cSAmit Kucheria }; 3942d2fa630cSAmit Kucheria map1 { 3943d2fa630cSAmit Kucheria trip = <&cpu5_top_alert1>; 3944d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3945d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3946d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3947d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3948d2fa630cSAmit Kucheria }; 3949d2fa630cSAmit Kucheria }; 3950d2fa630cSAmit Kucheria }; 3951d2fa630cSAmit Kucheria 3952d2fa630cSAmit Kucheria cpu6-top-thermal { 3953d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3954d2fa630cSAmit Kucheria polling-delay = <1000>; 3955d2fa630cSAmit Kucheria 3956d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 9>; 3957d2fa630cSAmit Kucheria 3958d2fa630cSAmit Kucheria trips { 3959d2fa630cSAmit Kucheria cpu6_top_alert0: trip-point0 { 3960d2fa630cSAmit Kucheria temperature = <90000>; 3961d2fa630cSAmit Kucheria hysteresis = <2000>; 3962d2fa630cSAmit Kucheria type = "passive"; 3963d2fa630cSAmit Kucheria }; 3964d2fa630cSAmit Kucheria 3965d2fa630cSAmit Kucheria cpu6_top_alert1: trip-point1 { 3966d2fa630cSAmit Kucheria temperature = <95000>; 3967d2fa630cSAmit Kucheria hysteresis = <2000>; 3968d2fa630cSAmit Kucheria type = "passive"; 3969d2fa630cSAmit Kucheria }; 3970d2fa630cSAmit Kucheria 3971d2fa630cSAmit Kucheria cpu6_top_crit: cpu_crit { 3972d2fa630cSAmit Kucheria temperature = <110000>; 3973d2fa630cSAmit Kucheria hysteresis = <1000>; 3974d2fa630cSAmit Kucheria type = "critical"; 3975d2fa630cSAmit Kucheria }; 3976d2fa630cSAmit Kucheria }; 3977d2fa630cSAmit Kucheria 3978d2fa630cSAmit Kucheria cooling-maps { 3979d2fa630cSAmit Kucheria map0 { 3980d2fa630cSAmit Kucheria trip = <&cpu6_top_alert0>; 3981d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3982d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3983d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3984d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3985d2fa630cSAmit Kucheria }; 3986d2fa630cSAmit Kucheria map1 { 3987d2fa630cSAmit Kucheria trip = <&cpu6_top_alert1>; 3988d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3989d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3990d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3991d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3992d2fa630cSAmit Kucheria }; 3993d2fa630cSAmit Kucheria }; 3994d2fa630cSAmit Kucheria }; 3995d2fa630cSAmit Kucheria 3996d2fa630cSAmit Kucheria cpu7-top-thermal { 3997d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3998d2fa630cSAmit Kucheria polling-delay = <1000>; 3999d2fa630cSAmit Kucheria 4000d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 10>; 4001d2fa630cSAmit Kucheria 4002d2fa630cSAmit Kucheria trips { 4003d2fa630cSAmit Kucheria cpu7_top_alert0: trip-point0 { 4004d2fa630cSAmit Kucheria temperature = <90000>; 4005d2fa630cSAmit Kucheria hysteresis = <2000>; 4006d2fa630cSAmit Kucheria type = "passive"; 4007d2fa630cSAmit Kucheria }; 4008d2fa630cSAmit Kucheria 4009d2fa630cSAmit Kucheria cpu7_top_alert1: trip-point1 { 4010d2fa630cSAmit Kucheria temperature = <95000>; 4011d2fa630cSAmit Kucheria hysteresis = <2000>; 4012d2fa630cSAmit Kucheria type = "passive"; 4013d2fa630cSAmit Kucheria }; 4014d2fa630cSAmit Kucheria 4015d2fa630cSAmit Kucheria cpu7_top_crit: cpu_crit { 4016d2fa630cSAmit Kucheria temperature = <110000>; 4017d2fa630cSAmit Kucheria hysteresis = <1000>; 4018d2fa630cSAmit Kucheria type = "critical"; 4019d2fa630cSAmit Kucheria }; 4020d2fa630cSAmit Kucheria }; 4021d2fa630cSAmit Kucheria 4022d2fa630cSAmit Kucheria cooling-maps { 4023d2fa630cSAmit Kucheria map0 { 4024d2fa630cSAmit Kucheria trip = <&cpu7_top_alert0>; 4025d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4026d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4027d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4028d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4029d2fa630cSAmit Kucheria }; 4030d2fa630cSAmit Kucheria map1 { 4031d2fa630cSAmit Kucheria trip = <&cpu7_top_alert1>; 4032d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4033d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4034d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4035d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4036d2fa630cSAmit Kucheria }; 4037d2fa630cSAmit Kucheria }; 4038d2fa630cSAmit Kucheria }; 4039d2fa630cSAmit Kucheria 4040d2fa630cSAmit Kucheria cpu4-bottom-thermal { 4041d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4042d2fa630cSAmit Kucheria polling-delay = <1000>; 4043d2fa630cSAmit Kucheria 4044d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 11>; 4045d2fa630cSAmit Kucheria 4046d2fa630cSAmit Kucheria trips { 4047d2fa630cSAmit Kucheria cpu4_bottom_alert0: trip-point0 { 4048d2fa630cSAmit Kucheria temperature = <90000>; 4049d2fa630cSAmit Kucheria hysteresis = <2000>; 4050d2fa630cSAmit Kucheria type = "passive"; 4051d2fa630cSAmit Kucheria }; 4052d2fa630cSAmit Kucheria 4053d2fa630cSAmit Kucheria cpu4_bottom_alert1: trip-point1 { 4054d2fa630cSAmit Kucheria temperature = <95000>; 4055d2fa630cSAmit Kucheria hysteresis = <2000>; 4056d2fa630cSAmit Kucheria type = "passive"; 4057d2fa630cSAmit Kucheria }; 4058d2fa630cSAmit Kucheria 4059d2fa630cSAmit Kucheria cpu4_bottom_crit: cpu_crit { 4060d2fa630cSAmit Kucheria temperature = <110000>; 4061d2fa630cSAmit Kucheria hysteresis = <1000>; 4062d2fa630cSAmit Kucheria type = "critical"; 4063d2fa630cSAmit Kucheria }; 4064d2fa630cSAmit Kucheria }; 4065d2fa630cSAmit Kucheria 4066d2fa630cSAmit Kucheria cooling-maps { 4067d2fa630cSAmit Kucheria map0 { 4068d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert0>; 4069d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4070d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4071d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4072d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4073d2fa630cSAmit Kucheria }; 4074d2fa630cSAmit Kucheria map1 { 4075d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert1>; 4076d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4077d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4078d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4079d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4080d2fa630cSAmit Kucheria }; 4081d2fa630cSAmit Kucheria }; 4082d2fa630cSAmit Kucheria }; 4083d2fa630cSAmit Kucheria 4084d2fa630cSAmit Kucheria cpu5-bottom-thermal { 4085d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4086d2fa630cSAmit Kucheria polling-delay = <1000>; 4087d2fa630cSAmit Kucheria 4088d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 12>; 4089d2fa630cSAmit Kucheria 4090d2fa630cSAmit Kucheria trips { 4091d2fa630cSAmit Kucheria cpu5_bottom_alert0: trip-point0 { 4092d2fa630cSAmit Kucheria temperature = <90000>; 4093d2fa630cSAmit Kucheria hysteresis = <2000>; 4094d2fa630cSAmit Kucheria type = "passive"; 4095d2fa630cSAmit Kucheria }; 4096d2fa630cSAmit Kucheria 4097d2fa630cSAmit Kucheria cpu5_bottom_alert1: trip-point1 { 4098d2fa630cSAmit Kucheria temperature = <95000>; 4099d2fa630cSAmit Kucheria hysteresis = <2000>; 4100d2fa630cSAmit Kucheria type = "passive"; 4101d2fa630cSAmit Kucheria }; 4102d2fa630cSAmit Kucheria 4103d2fa630cSAmit Kucheria cpu5_bottom_crit: cpu_crit { 4104d2fa630cSAmit Kucheria temperature = <110000>; 4105d2fa630cSAmit Kucheria hysteresis = <1000>; 4106d2fa630cSAmit Kucheria type = "critical"; 4107d2fa630cSAmit Kucheria }; 4108d2fa630cSAmit Kucheria }; 4109d2fa630cSAmit Kucheria 4110d2fa630cSAmit Kucheria cooling-maps { 4111d2fa630cSAmit Kucheria map0 { 4112d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert0>; 4113d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4114d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4115d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4116d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4117d2fa630cSAmit Kucheria }; 4118d2fa630cSAmit Kucheria map1 { 4119d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert1>; 4120d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4121d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4122d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4123d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4124d2fa630cSAmit Kucheria }; 4125d2fa630cSAmit Kucheria }; 4126d2fa630cSAmit Kucheria }; 4127d2fa630cSAmit Kucheria 4128d2fa630cSAmit Kucheria cpu6-bottom-thermal { 4129d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4130d2fa630cSAmit Kucheria polling-delay = <1000>; 4131d2fa630cSAmit Kucheria 4132d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 13>; 4133d2fa630cSAmit Kucheria 4134d2fa630cSAmit Kucheria trips { 4135d2fa630cSAmit Kucheria cpu6_bottom_alert0: trip-point0 { 4136d2fa630cSAmit Kucheria temperature = <90000>; 4137d2fa630cSAmit Kucheria hysteresis = <2000>; 4138d2fa630cSAmit Kucheria type = "passive"; 4139d2fa630cSAmit Kucheria }; 4140d2fa630cSAmit Kucheria 4141d2fa630cSAmit Kucheria cpu6_bottom_alert1: trip-point1 { 4142d2fa630cSAmit Kucheria temperature = <95000>; 4143d2fa630cSAmit Kucheria hysteresis = <2000>; 4144d2fa630cSAmit Kucheria type = "passive"; 4145d2fa630cSAmit Kucheria }; 4146d2fa630cSAmit Kucheria 4147d2fa630cSAmit Kucheria cpu6_bottom_crit: cpu_crit { 4148d2fa630cSAmit Kucheria temperature = <110000>; 4149d2fa630cSAmit Kucheria hysteresis = <1000>; 4150d2fa630cSAmit Kucheria type = "critical"; 4151d2fa630cSAmit Kucheria }; 4152d2fa630cSAmit Kucheria }; 4153d2fa630cSAmit Kucheria 4154d2fa630cSAmit Kucheria cooling-maps { 4155d2fa630cSAmit Kucheria map0 { 4156d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert0>; 4157d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4158d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4159d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4160d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4161d2fa630cSAmit Kucheria }; 4162d2fa630cSAmit Kucheria map1 { 4163d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert1>; 4164d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4165d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4166d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4167d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4168d2fa630cSAmit Kucheria }; 4169d2fa630cSAmit Kucheria }; 4170d2fa630cSAmit Kucheria }; 4171d2fa630cSAmit Kucheria 4172d2fa630cSAmit Kucheria cpu7-bottom-thermal { 4173d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4174d2fa630cSAmit Kucheria polling-delay = <1000>; 4175d2fa630cSAmit Kucheria 4176d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 14>; 4177d2fa630cSAmit Kucheria 4178d2fa630cSAmit Kucheria trips { 4179d2fa630cSAmit Kucheria cpu7_bottom_alert0: trip-point0 { 4180d2fa630cSAmit Kucheria temperature = <90000>; 4181d2fa630cSAmit Kucheria hysteresis = <2000>; 4182d2fa630cSAmit Kucheria type = "passive"; 4183d2fa630cSAmit Kucheria }; 4184d2fa630cSAmit Kucheria 4185d2fa630cSAmit Kucheria cpu7_bottom_alert1: trip-point1 { 4186d2fa630cSAmit Kucheria temperature = <95000>; 4187d2fa630cSAmit Kucheria hysteresis = <2000>; 4188d2fa630cSAmit Kucheria type = "passive"; 4189d2fa630cSAmit Kucheria }; 4190d2fa630cSAmit Kucheria 4191d2fa630cSAmit Kucheria cpu7_bottom_crit: cpu_crit { 4192d2fa630cSAmit Kucheria temperature = <110000>; 4193d2fa630cSAmit Kucheria hysteresis = <1000>; 4194d2fa630cSAmit Kucheria type = "critical"; 4195d2fa630cSAmit Kucheria }; 4196d2fa630cSAmit Kucheria }; 4197d2fa630cSAmit Kucheria 4198d2fa630cSAmit Kucheria cooling-maps { 4199d2fa630cSAmit Kucheria map0 { 4200d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert0>; 4201d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4202d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4203d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4204d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4205d2fa630cSAmit Kucheria }; 4206d2fa630cSAmit Kucheria map1 { 4207d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert1>; 4208d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4209d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4210d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4211d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4212d2fa630cSAmit Kucheria }; 4213d2fa630cSAmit Kucheria }; 4214d2fa630cSAmit Kucheria }; 4215d2fa630cSAmit Kucheria 4216d2fa630cSAmit Kucheria aoss0-thermal { 4217d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4218d2fa630cSAmit Kucheria polling-delay = <1000>; 4219d2fa630cSAmit Kucheria 4220d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 0>; 4221d2fa630cSAmit Kucheria 4222d2fa630cSAmit Kucheria trips { 4223d2fa630cSAmit Kucheria aoss0_alert0: trip-point0 { 4224d2fa630cSAmit Kucheria temperature = <90000>; 4225d2fa630cSAmit Kucheria hysteresis = <2000>; 4226d2fa630cSAmit Kucheria type = "hot"; 4227d2fa630cSAmit Kucheria }; 4228d2fa630cSAmit Kucheria }; 4229d2fa630cSAmit Kucheria }; 4230d2fa630cSAmit Kucheria 4231d2fa630cSAmit Kucheria cluster0-thermal { 4232d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4233d2fa630cSAmit Kucheria polling-delay = <1000>; 4234d2fa630cSAmit Kucheria 4235d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 5>; 4236d2fa630cSAmit Kucheria 4237d2fa630cSAmit Kucheria trips { 4238d2fa630cSAmit Kucheria cluster0_alert0: trip-point0 { 4239d2fa630cSAmit Kucheria temperature = <90000>; 4240d2fa630cSAmit Kucheria hysteresis = <2000>; 4241d2fa630cSAmit Kucheria type = "hot"; 4242d2fa630cSAmit Kucheria }; 4243d2fa630cSAmit Kucheria cluster0_crit: cluster0_crit { 4244d2fa630cSAmit Kucheria temperature = <110000>; 4245d2fa630cSAmit Kucheria hysteresis = <2000>; 4246d2fa630cSAmit Kucheria type = "critical"; 4247d2fa630cSAmit Kucheria }; 4248d2fa630cSAmit Kucheria }; 4249d2fa630cSAmit Kucheria }; 4250d2fa630cSAmit Kucheria 4251d2fa630cSAmit Kucheria cluster1-thermal { 4252d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4253d2fa630cSAmit Kucheria polling-delay = <1000>; 4254d2fa630cSAmit Kucheria 4255d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 6>; 4256d2fa630cSAmit Kucheria 4257d2fa630cSAmit Kucheria trips { 4258d2fa630cSAmit Kucheria cluster1_alert0: trip-point0 { 4259d2fa630cSAmit Kucheria temperature = <90000>; 4260d2fa630cSAmit Kucheria hysteresis = <2000>; 4261d2fa630cSAmit Kucheria type = "hot"; 4262d2fa630cSAmit Kucheria }; 4263d2fa630cSAmit Kucheria cluster1_crit: cluster1_crit { 4264d2fa630cSAmit Kucheria temperature = <110000>; 4265d2fa630cSAmit Kucheria hysteresis = <2000>; 4266d2fa630cSAmit Kucheria type = "critical"; 4267d2fa630cSAmit Kucheria }; 4268d2fa630cSAmit Kucheria }; 4269d2fa630cSAmit Kucheria }; 4270d2fa630cSAmit Kucheria 4271d2fa630cSAmit Kucheria gpu-thermal-top { 4272d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4273d2fa630cSAmit Kucheria polling-delay = <1000>; 4274d2fa630cSAmit Kucheria 4275d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 15>; 4276d2fa630cSAmit Kucheria 4277d2fa630cSAmit Kucheria trips { 4278d2fa630cSAmit Kucheria gpu1_alert0: trip-point0 { 4279d2fa630cSAmit Kucheria temperature = <90000>; 4280d2fa630cSAmit Kucheria hysteresis = <2000>; 4281d2fa630cSAmit Kucheria type = "hot"; 4282d2fa630cSAmit Kucheria }; 4283d2fa630cSAmit Kucheria }; 4284d2fa630cSAmit Kucheria }; 4285d2fa630cSAmit Kucheria 4286d2fa630cSAmit Kucheria aoss1-thermal { 4287d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4288d2fa630cSAmit Kucheria polling-delay = <1000>; 4289d2fa630cSAmit Kucheria 4290d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 0>; 4291d2fa630cSAmit Kucheria 4292d2fa630cSAmit Kucheria trips { 4293d2fa630cSAmit Kucheria aoss1_alert0: trip-point0 { 4294d2fa630cSAmit Kucheria temperature = <90000>; 4295d2fa630cSAmit Kucheria hysteresis = <2000>; 4296d2fa630cSAmit Kucheria type = "hot"; 4297d2fa630cSAmit Kucheria }; 4298d2fa630cSAmit Kucheria }; 4299d2fa630cSAmit Kucheria }; 4300d2fa630cSAmit Kucheria 4301d2fa630cSAmit Kucheria wlan-thermal { 4302d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4303d2fa630cSAmit Kucheria polling-delay = <1000>; 4304d2fa630cSAmit Kucheria 4305d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 1>; 4306d2fa630cSAmit Kucheria 4307d2fa630cSAmit Kucheria trips { 4308d2fa630cSAmit Kucheria wlan_alert0: trip-point0 { 4309d2fa630cSAmit Kucheria temperature = <90000>; 4310d2fa630cSAmit Kucheria hysteresis = <2000>; 4311d2fa630cSAmit Kucheria type = "hot"; 4312d2fa630cSAmit Kucheria }; 4313d2fa630cSAmit Kucheria }; 4314d2fa630cSAmit Kucheria }; 4315d2fa630cSAmit Kucheria 4316d2fa630cSAmit Kucheria video-thermal { 4317d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4318d2fa630cSAmit Kucheria polling-delay = <1000>; 4319d2fa630cSAmit Kucheria 4320d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 2>; 4321d2fa630cSAmit Kucheria 4322d2fa630cSAmit Kucheria trips { 4323d2fa630cSAmit Kucheria video_alert0: trip-point0 { 4324d2fa630cSAmit Kucheria temperature = <90000>; 4325d2fa630cSAmit Kucheria hysteresis = <2000>; 4326d2fa630cSAmit Kucheria type = "hot"; 4327d2fa630cSAmit Kucheria }; 4328d2fa630cSAmit Kucheria }; 4329d2fa630cSAmit Kucheria }; 4330d2fa630cSAmit Kucheria 4331d2fa630cSAmit Kucheria mem-thermal { 4332d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4333d2fa630cSAmit Kucheria polling-delay = <1000>; 4334d2fa630cSAmit Kucheria 4335d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 3>; 4336d2fa630cSAmit Kucheria 4337d2fa630cSAmit Kucheria trips { 4338d2fa630cSAmit Kucheria mem_alert0: trip-point0 { 4339d2fa630cSAmit Kucheria temperature = <90000>; 4340d2fa630cSAmit Kucheria hysteresis = <2000>; 4341d2fa630cSAmit Kucheria type = "hot"; 4342d2fa630cSAmit Kucheria }; 4343d2fa630cSAmit Kucheria }; 4344d2fa630cSAmit Kucheria }; 4345d2fa630cSAmit Kucheria 4346d2fa630cSAmit Kucheria q6-hvx-thermal { 4347d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4348d2fa630cSAmit Kucheria polling-delay = <1000>; 4349d2fa630cSAmit Kucheria 4350d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 4>; 4351d2fa630cSAmit Kucheria 4352d2fa630cSAmit Kucheria trips { 4353d2fa630cSAmit Kucheria q6_hvx_alert0: trip-point0 { 4354d2fa630cSAmit Kucheria temperature = <90000>; 4355d2fa630cSAmit Kucheria hysteresis = <2000>; 4356d2fa630cSAmit Kucheria type = "hot"; 4357d2fa630cSAmit Kucheria }; 4358d2fa630cSAmit Kucheria }; 4359d2fa630cSAmit Kucheria }; 4360d2fa630cSAmit Kucheria 4361d2fa630cSAmit Kucheria camera-thermal { 4362d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4363d2fa630cSAmit Kucheria polling-delay = <1000>; 4364d2fa630cSAmit Kucheria 4365d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 5>; 4366d2fa630cSAmit Kucheria 4367d2fa630cSAmit Kucheria trips { 4368d2fa630cSAmit Kucheria camera_alert0: trip-point0 { 4369d2fa630cSAmit Kucheria temperature = <90000>; 4370d2fa630cSAmit Kucheria hysteresis = <2000>; 4371d2fa630cSAmit Kucheria type = "hot"; 4372d2fa630cSAmit Kucheria }; 4373d2fa630cSAmit Kucheria }; 4374d2fa630cSAmit Kucheria }; 4375d2fa630cSAmit Kucheria 4376d2fa630cSAmit Kucheria compute-thermal { 4377d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4378d2fa630cSAmit Kucheria polling-delay = <1000>; 4379d2fa630cSAmit Kucheria 4380d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 6>; 4381d2fa630cSAmit Kucheria 4382d2fa630cSAmit Kucheria trips { 4383d2fa630cSAmit Kucheria compute_alert0: trip-point0 { 4384d2fa630cSAmit Kucheria temperature = <90000>; 4385d2fa630cSAmit Kucheria hysteresis = <2000>; 4386d2fa630cSAmit Kucheria type = "hot"; 4387d2fa630cSAmit Kucheria }; 4388d2fa630cSAmit Kucheria }; 4389d2fa630cSAmit Kucheria }; 4390d2fa630cSAmit Kucheria 4391d2fa630cSAmit Kucheria modem-thermal { 4392d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4393d2fa630cSAmit Kucheria polling-delay = <1000>; 4394d2fa630cSAmit Kucheria 4395d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 7>; 4396d2fa630cSAmit Kucheria 4397d2fa630cSAmit Kucheria trips { 4398d2fa630cSAmit Kucheria modem_alert0: trip-point0 { 4399d2fa630cSAmit Kucheria temperature = <90000>; 4400d2fa630cSAmit Kucheria hysteresis = <2000>; 4401d2fa630cSAmit Kucheria type = "hot"; 4402d2fa630cSAmit Kucheria }; 4403d2fa630cSAmit Kucheria }; 4404d2fa630cSAmit Kucheria }; 4405d2fa630cSAmit Kucheria 4406d2fa630cSAmit Kucheria npu-thermal { 4407d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4408d2fa630cSAmit Kucheria polling-delay = <1000>; 4409d2fa630cSAmit Kucheria 4410d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 8>; 4411d2fa630cSAmit Kucheria 4412d2fa630cSAmit Kucheria trips { 4413d2fa630cSAmit Kucheria npu_alert0: trip-point0 { 4414d2fa630cSAmit Kucheria temperature = <90000>; 4415d2fa630cSAmit Kucheria hysteresis = <2000>; 4416d2fa630cSAmit Kucheria type = "hot"; 4417d2fa630cSAmit Kucheria }; 4418d2fa630cSAmit Kucheria }; 4419d2fa630cSAmit Kucheria }; 4420d2fa630cSAmit Kucheria 4421d2fa630cSAmit Kucheria modem-vec-thermal { 4422d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4423d2fa630cSAmit Kucheria polling-delay = <1000>; 4424d2fa630cSAmit Kucheria 4425d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 9>; 4426d2fa630cSAmit Kucheria 4427d2fa630cSAmit Kucheria trips { 4428d2fa630cSAmit Kucheria modem_vec_alert0: trip-point0 { 4429d2fa630cSAmit Kucheria temperature = <90000>; 4430d2fa630cSAmit Kucheria hysteresis = <2000>; 4431d2fa630cSAmit Kucheria type = "hot"; 4432d2fa630cSAmit Kucheria }; 4433d2fa630cSAmit Kucheria }; 4434d2fa630cSAmit Kucheria }; 4435d2fa630cSAmit Kucheria 4436d2fa630cSAmit Kucheria modem-scl-thermal { 4437d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4438d2fa630cSAmit Kucheria polling-delay = <1000>; 4439d2fa630cSAmit Kucheria 4440d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 10>; 4441d2fa630cSAmit Kucheria 4442d2fa630cSAmit Kucheria trips { 4443d2fa630cSAmit Kucheria modem_scl_alert0: trip-point0 { 4444d2fa630cSAmit Kucheria temperature = <90000>; 4445d2fa630cSAmit Kucheria hysteresis = <2000>; 4446d2fa630cSAmit Kucheria type = "hot"; 4447d2fa630cSAmit Kucheria }; 4448d2fa630cSAmit Kucheria }; 4449d2fa630cSAmit Kucheria }; 4450d2fa630cSAmit Kucheria 4451d2fa630cSAmit Kucheria gpu-thermal-bottom { 4452d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4453d2fa630cSAmit Kucheria polling-delay = <1000>; 4454d2fa630cSAmit Kucheria 4455d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 11>; 4456d2fa630cSAmit Kucheria 4457d2fa630cSAmit Kucheria trips { 4458d2fa630cSAmit Kucheria gpu2_alert0: trip-point0 { 4459d2fa630cSAmit Kucheria temperature = <90000>; 4460d2fa630cSAmit Kucheria hysteresis = <2000>; 4461d2fa630cSAmit Kucheria type = "hot"; 4462d2fa630cSAmit Kucheria }; 4463d2fa630cSAmit Kucheria }; 4464d2fa630cSAmit Kucheria }; 4465d2fa630cSAmit Kucheria }; 4466e13c6d14SVinod Koul}; 4467