1e13c6d14SVinod Koul// SPDX-License-Identifier: BSD-3-Clause 2e13c6d14SVinod Koul/* 3e13c6d14SVinod Koul * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4e13c6d14SVinod Koul * Copyright (c) 2019, Linaro Limited 5e13c6d14SVinod Koul */ 6e13c6d14SVinod Koul 7e13c6d14SVinod Koul#include <dt-bindings/interrupt-controller/arm-gic.h> 849076351SSibi Sankar#include <dt-bindings/power/qcom-aoss-qmp.h> 9017e7856SSibi Sankar#include <dt-bindings/power/qcom-rpmpd.h> 10e13c6d14SVinod Koul#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11e13c6d14SVinod Koul#include <dt-bindings/clock/qcom,rpmh.h> 12d6f55763SVinod Koul#include <dt-bindings/clock/qcom,gcc-sm8150.h> 13f1269916SJonathan Marek#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 14a6d435c1SSibi Sankar#include <dt-bindings/interconnect/qcom,osm-l3.h> 15d2fa630cSAmit Kucheria#include <dt-bindings/thermal/thermal.h> 16e13c6d14SVinod Koul 17e13c6d14SVinod Koul/ { 18e13c6d14SVinod Koul interrupt-parent = <&intc>; 19e13c6d14SVinod Koul 20e13c6d14SVinod Koul #address-cells = <2>; 21e13c6d14SVinod Koul #size-cells = <2>; 22e13c6d14SVinod Koul 23e13c6d14SVinod Koul chosen { }; 24e13c6d14SVinod Koul 25e13c6d14SVinod Koul clocks { 26e13c6d14SVinod Koul xo_board: xo-board { 27e13c6d14SVinod Koul compatible = "fixed-clock"; 28e13c6d14SVinod Koul #clock-cells = <0>; 29e13c6d14SVinod Koul clock-frequency = <38400000>; 30e13c6d14SVinod Koul clock-output-names = "xo_board"; 31e13c6d14SVinod Koul }; 32e13c6d14SVinod Koul 33e13c6d14SVinod Koul sleep_clk: sleep-clk { 34e13c6d14SVinod Koul compatible = "fixed-clock"; 35e13c6d14SVinod Koul #clock-cells = <0>; 36e13c6d14SVinod Koul clock-frequency = <32764>; 37e13c6d14SVinod Koul clock-output-names = "sleep_clk"; 38e13c6d14SVinod Koul }; 39e13c6d14SVinod Koul }; 40e13c6d14SVinod Koul 41e13c6d14SVinod Koul cpus { 42e13c6d14SVinod Koul #address-cells = <2>; 43e13c6d14SVinod Koul #size-cells = <0>; 44e13c6d14SVinod Koul 45e13c6d14SVinod Koul CPU0: cpu@0 { 46e13c6d14SVinod Koul device_type = "cpu"; 47e13c6d14SVinod Koul compatible = "qcom,kryo485"; 48e13c6d14SVinod Koul reg = <0x0 0x0>; 49e13c6d14SVinod Koul enable-method = "psci"; 505b2dae72SDanny Lin capacity-dmips-mhz = <488>; 515b2dae72SDanny Lin dynamic-power-coefficient = <232>; 52e13c6d14SVinod Koul next-level-cache = <&L2_0>; 53fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 54b2e3f897SDanny Lin power-domains = <&CPU_PD0>; 55b2e3f897SDanny Lin power-domain-names = "psci"; 56d2fa630cSAmit Kucheria #cooling-cells = <2>; 57e13c6d14SVinod Koul L2_0: l2-cache { 58e13c6d14SVinod Koul compatible = "cache"; 59e13c6d14SVinod Koul next-level-cache = <&L3_0>; 60e13c6d14SVinod Koul L3_0: l3-cache { 61e13c6d14SVinod Koul compatible = "cache"; 62e13c6d14SVinod Koul }; 63e13c6d14SVinod Koul }; 64e13c6d14SVinod Koul }; 65e13c6d14SVinod Koul 66e13c6d14SVinod Koul CPU1: cpu@100 { 67e13c6d14SVinod Koul device_type = "cpu"; 68e13c6d14SVinod Koul compatible = "qcom,kryo485"; 69e13c6d14SVinod Koul reg = <0x0 0x100>; 70e13c6d14SVinod Koul enable-method = "psci"; 715b2dae72SDanny Lin capacity-dmips-mhz = <488>; 725b2dae72SDanny Lin dynamic-power-coefficient = <232>; 73e13c6d14SVinod Koul next-level-cache = <&L2_100>; 74fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 75b2e3f897SDanny Lin power-domains = <&CPU_PD1>; 76b2e3f897SDanny Lin power-domain-names = "psci"; 77d2fa630cSAmit Kucheria #cooling-cells = <2>; 78e13c6d14SVinod Koul L2_100: l2-cache { 79e13c6d14SVinod Koul compatible = "cache"; 80e13c6d14SVinod Koul next-level-cache = <&L3_0>; 81e13c6d14SVinod Koul }; 82e13c6d14SVinod Koul 83e13c6d14SVinod Koul }; 84e13c6d14SVinod Koul 85e13c6d14SVinod Koul CPU2: cpu@200 { 86e13c6d14SVinod Koul device_type = "cpu"; 87e13c6d14SVinod Koul compatible = "qcom,kryo485"; 88e13c6d14SVinod Koul reg = <0x0 0x200>; 89e13c6d14SVinod Koul enable-method = "psci"; 905b2dae72SDanny Lin capacity-dmips-mhz = <488>; 915b2dae72SDanny Lin dynamic-power-coefficient = <232>; 92e13c6d14SVinod Koul next-level-cache = <&L2_200>; 93fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 94b2e3f897SDanny Lin power-domains = <&CPU_PD2>; 95b2e3f897SDanny Lin power-domain-names = "psci"; 96d2fa630cSAmit Kucheria #cooling-cells = <2>; 97e13c6d14SVinod Koul L2_200: l2-cache { 98e13c6d14SVinod Koul compatible = "cache"; 99e13c6d14SVinod Koul next-level-cache = <&L3_0>; 100e13c6d14SVinod Koul }; 101e13c6d14SVinod Koul }; 102e13c6d14SVinod Koul 103e13c6d14SVinod Koul CPU3: cpu@300 { 104e13c6d14SVinod Koul device_type = "cpu"; 105e13c6d14SVinod Koul compatible = "qcom,kryo485"; 106e13c6d14SVinod Koul reg = <0x0 0x300>; 107e13c6d14SVinod Koul enable-method = "psci"; 1085b2dae72SDanny Lin capacity-dmips-mhz = <488>; 1095b2dae72SDanny Lin dynamic-power-coefficient = <232>; 110e13c6d14SVinod Koul next-level-cache = <&L2_300>; 111fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 112b2e3f897SDanny Lin power-domains = <&CPU_PD3>; 113b2e3f897SDanny Lin power-domain-names = "psci"; 114d2fa630cSAmit Kucheria #cooling-cells = <2>; 115e13c6d14SVinod Koul L2_300: l2-cache { 116e13c6d14SVinod Koul compatible = "cache"; 117e13c6d14SVinod Koul next-level-cache = <&L3_0>; 118e13c6d14SVinod Koul }; 119e13c6d14SVinod Koul }; 120e13c6d14SVinod Koul 121e13c6d14SVinod Koul CPU4: cpu@400 { 122e13c6d14SVinod Koul device_type = "cpu"; 123e13c6d14SVinod Koul compatible = "qcom,kryo485"; 124e13c6d14SVinod Koul reg = <0x0 0x400>; 125e13c6d14SVinod Koul enable-method = "psci"; 1265b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1275b2dae72SDanny Lin dynamic-power-coefficient = <369>; 128e13c6d14SVinod Koul next-level-cache = <&L2_400>; 129fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 130b2e3f897SDanny Lin power-domains = <&CPU_PD4>; 131b2e3f897SDanny Lin power-domain-names = "psci"; 132d2fa630cSAmit Kucheria #cooling-cells = <2>; 133e13c6d14SVinod Koul L2_400: l2-cache { 134e13c6d14SVinod Koul compatible = "cache"; 135e13c6d14SVinod Koul next-level-cache = <&L3_0>; 136e13c6d14SVinod Koul }; 137e13c6d14SVinod Koul }; 138e13c6d14SVinod Koul 139e13c6d14SVinod Koul CPU5: cpu@500 { 140e13c6d14SVinod Koul device_type = "cpu"; 141e13c6d14SVinod Koul compatible = "qcom,kryo485"; 142e13c6d14SVinod Koul reg = <0x0 0x500>; 143e13c6d14SVinod Koul enable-method = "psci"; 1445b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1455b2dae72SDanny Lin dynamic-power-coefficient = <369>; 146e13c6d14SVinod Koul next-level-cache = <&L2_500>; 147fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 148b2e3f897SDanny Lin power-domains = <&CPU_PD5>; 149b2e3f897SDanny Lin power-domain-names = "psci"; 150d2fa630cSAmit Kucheria #cooling-cells = <2>; 151e13c6d14SVinod Koul L2_500: l2-cache { 152e13c6d14SVinod Koul compatible = "cache"; 153e13c6d14SVinod Koul next-level-cache = <&L3_0>; 154e13c6d14SVinod Koul }; 155e13c6d14SVinod Koul }; 156e13c6d14SVinod Koul 157e13c6d14SVinod Koul CPU6: cpu@600 { 158e13c6d14SVinod Koul device_type = "cpu"; 159e13c6d14SVinod Koul compatible = "qcom,kryo485"; 160e13c6d14SVinod Koul reg = <0x0 0x600>; 161e13c6d14SVinod Koul enable-method = "psci"; 1625b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1635b2dae72SDanny Lin dynamic-power-coefficient = <369>; 164e13c6d14SVinod Koul next-level-cache = <&L2_600>; 165fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 166b2e3f897SDanny Lin power-domains = <&CPU_PD6>; 167b2e3f897SDanny Lin power-domain-names = "psci"; 168d2fa630cSAmit Kucheria #cooling-cells = <2>; 169e13c6d14SVinod Koul L2_600: l2-cache { 170e13c6d14SVinod Koul compatible = "cache"; 171e13c6d14SVinod Koul next-level-cache = <&L3_0>; 172e13c6d14SVinod Koul }; 173e13c6d14SVinod Koul }; 174e13c6d14SVinod Koul 175e13c6d14SVinod Koul CPU7: cpu@700 { 176e13c6d14SVinod Koul device_type = "cpu"; 177e13c6d14SVinod Koul compatible = "qcom,kryo485"; 178e13c6d14SVinod Koul reg = <0x0 0x700>; 179e13c6d14SVinod Koul enable-method = "psci"; 1805b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1815b2dae72SDanny Lin dynamic-power-coefficient = <421>; 182e13c6d14SVinod Koul next-level-cache = <&L2_700>; 183fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 2>; 184b2e3f897SDanny Lin power-domains = <&CPU_PD7>; 185b2e3f897SDanny Lin power-domain-names = "psci"; 186d2fa630cSAmit Kucheria #cooling-cells = <2>; 187e13c6d14SVinod Koul L2_700: l2-cache { 188e13c6d14SVinod Koul compatible = "cache"; 189e13c6d14SVinod Koul next-level-cache = <&L3_0>; 190e13c6d14SVinod Koul }; 191e13c6d14SVinod Koul }; 192066d21bcSDanny Lin 193066d21bcSDanny Lin cpu-map { 194066d21bcSDanny Lin cluster0 { 195066d21bcSDanny Lin core0 { 196066d21bcSDanny Lin cpu = <&CPU0>; 197066d21bcSDanny Lin }; 198066d21bcSDanny Lin 199066d21bcSDanny Lin core1 { 200066d21bcSDanny Lin cpu = <&CPU1>; 201066d21bcSDanny Lin }; 202066d21bcSDanny Lin 203066d21bcSDanny Lin core2 { 204066d21bcSDanny Lin cpu = <&CPU2>; 205066d21bcSDanny Lin }; 206066d21bcSDanny Lin 207066d21bcSDanny Lin core3 { 208066d21bcSDanny Lin cpu = <&CPU3>; 209066d21bcSDanny Lin }; 210066d21bcSDanny Lin 211066d21bcSDanny Lin core4 { 212066d21bcSDanny Lin cpu = <&CPU4>; 213066d21bcSDanny Lin }; 214066d21bcSDanny Lin 215066d21bcSDanny Lin core5 { 216066d21bcSDanny Lin cpu = <&CPU5>; 217066d21bcSDanny Lin }; 218066d21bcSDanny Lin 219066d21bcSDanny Lin core6 { 220066d21bcSDanny Lin cpu = <&CPU6>; 221066d21bcSDanny Lin }; 222066d21bcSDanny Lin 223066d21bcSDanny Lin core7 { 224066d21bcSDanny Lin cpu = <&CPU7>; 225066d21bcSDanny Lin }; 226066d21bcSDanny Lin }; 227066d21bcSDanny Lin }; 22881188f58SDanny Lin 22981188f58SDanny Lin idle-states { 23081188f58SDanny Lin entry-method = "psci"; 23181188f58SDanny Lin 23281188f58SDanny Lin LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 23381188f58SDanny Lin compatible = "arm,idle-state"; 23481188f58SDanny Lin idle-state-name = "little-rail-power-collapse"; 23581188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 23681188f58SDanny Lin entry-latency-us = <355>; 23781188f58SDanny Lin exit-latency-us = <909>; 23881188f58SDanny Lin min-residency-us = <3934>; 23981188f58SDanny Lin local-timer-stop; 24081188f58SDanny Lin }; 24181188f58SDanny Lin 24281188f58SDanny Lin BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 24381188f58SDanny Lin compatible = "arm,idle-state"; 24481188f58SDanny Lin idle-state-name = "big-rail-power-collapse"; 24581188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 24681188f58SDanny Lin entry-latency-us = <241>; 24781188f58SDanny Lin exit-latency-us = <1461>; 24881188f58SDanny Lin min-residency-us = <4488>; 24981188f58SDanny Lin local-timer-stop; 25081188f58SDanny Lin }; 251b2e3f897SDanny Lin }; 25281188f58SDanny Lin 253b2e3f897SDanny Lin domain-idle-states { 25481188f58SDanny Lin CLUSTER_SLEEP_0: cluster-sleep-0 { 255b2e3f897SDanny Lin compatible = "domain-idle-state"; 25681188f58SDanny Lin idle-state-name = "cluster-power-collapse"; 257b2e3f897SDanny Lin arm,psci-suspend-param = <0x4100c244>; 25881188f58SDanny Lin entry-latency-us = <3263>; 25981188f58SDanny Lin exit-latency-us = <6562>; 26081188f58SDanny Lin min-residency-us = <9987>; 26181188f58SDanny Lin local-timer-stop; 26281188f58SDanny Lin }; 26381188f58SDanny Lin }; 264e13c6d14SVinod Koul }; 265e13c6d14SVinod Koul 266e13c6d14SVinod Koul firmware { 267e13c6d14SVinod Koul scm: scm { 268e13c6d14SVinod Koul compatible = "qcom,scm-sm8150", "qcom,scm"; 269e13c6d14SVinod Koul #reset-cells = <1>; 270e13c6d14SVinod Koul }; 271e13c6d14SVinod Koul }; 272e13c6d14SVinod Koul 273d8cf9372SVinod Koul tcsr_mutex: hwlock { 274d8cf9372SVinod Koul compatible = "qcom,tcsr-mutex"; 275d8cf9372SVinod Koul syscon = <&tcsr_mutex_regs 0 0x1000>; 276d8cf9372SVinod Koul #hwlock-cells = <1>; 277d8cf9372SVinod Koul }; 278d8cf9372SVinod Koul 279e13c6d14SVinod Koul memory@80000000 { 280e13c6d14SVinod Koul device_type = "memory"; 281e13c6d14SVinod Koul /* We expect the bootloader to fill in the size */ 282e13c6d14SVinod Koul reg = <0x0 0x80000000 0x0 0x0>; 283e13c6d14SVinod Koul }; 284e13c6d14SVinod Koul 285d8cf9372SVinod Koul pmu { 286d8cf9372SVinod Koul compatible = "arm,armv8-pmuv3"; 287d8cf9372SVinod Koul interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 288d8cf9372SVinod Koul }; 289d8cf9372SVinod Koul 290e13c6d14SVinod Koul psci { 291e13c6d14SVinod Koul compatible = "arm,psci-1.0"; 292e13c6d14SVinod Koul method = "smc"; 293b2e3f897SDanny Lin 294b2e3f897SDanny Lin CPU_PD0: cpu0 { 295b2e3f897SDanny Lin #power-domain-cells = <0>; 296b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 297b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 298b2e3f897SDanny Lin }; 299b2e3f897SDanny Lin 300b2e3f897SDanny Lin CPU_PD1: cpu1 { 301b2e3f897SDanny Lin #power-domain-cells = <0>; 302b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 303b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 304b2e3f897SDanny Lin }; 305b2e3f897SDanny Lin 306b2e3f897SDanny Lin CPU_PD2: cpu2 { 307b2e3f897SDanny Lin #power-domain-cells = <0>; 308b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 309b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 310b2e3f897SDanny Lin }; 311b2e3f897SDanny Lin 312b2e3f897SDanny Lin CPU_PD3: cpu3 { 313b2e3f897SDanny Lin #power-domain-cells = <0>; 314b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 315b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 316b2e3f897SDanny Lin }; 317b2e3f897SDanny Lin 318b2e3f897SDanny Lin CPU_PD4: cpu4 { 319b2e3f897SDanny Lin #power-domain-cells = <0>; 320b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 321b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 322b2e3f897SDanny Lin }; 323b2e3f897SDanny Lin 324b2e3f897SDanny Lin CPU_PD5: cpu5 { 325b2e3f897SDanny Lin #power-domain-cells = <0>; 326b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 327b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 328b2e3f897SDanny Lin }; 329b2e3f897SDanny Lin 330b2e3f897SDanny Lin CPU_PD6: cpu6 { 331b2e3f897SDanny Lin #power-domain-cells = <0>; 332b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 333b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 334b2e3f897SDanny Lin }; 335b2e3f897SDanny Lin 336b2e3f897SDanny Lin CPU_PD7: cpu7 { 337b2e3f897SDanny Lin #power-domain-cells = <0>; 338b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 339b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 340b2e3f897SDanny Lin }; 341b2e3f897SDanny Lin 342b2e3f897SDanny Lin CLUSTER_PD: cpu-cluster0 { 343b2e3f897SDanny Lin #power-domain-cells = <0>; 344b2e3f897SDanny Lin domain-idle-states = <&CLUSTER_SLEEP_0>; 345b2e3f897SDanny Lin }; 346e13c6d14SVinod Koul }; 347e13c6d14SVinod Koul 348912c373aSVinod Koul reserved-memory { 349912c373aSVinod Koul #address-cells = <2>; 350912c373aSVinod Koul #size-cells = <2>; 351912c373aSVinod Koul ranges; 352912c373aSVinod Koul 353912c373aSVinod Koul hyp_mem: memory@85700000 { 354912c373aSVinod Koul reg = <0x0 0x85700000 0x0 0x600000>; 355912c373aSVinod Koul no-map; 356912c373aSVinod Koul }; 357912c373aSVinod Koul 358912c373aSVinod Koul xbl_mem: memory@85d00000 { 359912c373aSVinod Koul reg = <0x0 0x85d00000 0x0 0x140000>; 360912c373aSVinod Koul no-map; 361912c373aSVinod Koul }; 362912c373aSVinod Koul 363912c373aSVinod Koul aop_mem: memory@85f00000 { 364912c373aSVinod Koul reg = <0x0 0x85f00000 0x0 0x20000>; 365912c373aSVinod Koul no-map; 366912c373aSVinod Koul }; 367912c373aSVinod Koul 368912c373aSVinod Koul aop_cmd_db: memory@85f20000 { 369912c373aSVinod Koul compatible = "qcom,cmd-db"; 370912c373aSVinod Koul reg = <0x0 0x85f20000 0x0 0x20000>; 371912c373aSVinod Koul no-map; 372912c373aSVinod Koul }; 373912c373aSVinod Koul 374912c373aSVinod Koul smem_mem: memory@86000000 { 375912c373aSVinod Koul reg = <0x0 0x86000000 0x0 0x200000>; 376912c373aSVinod Koul no-map; 377912c373aSVinod Koul }; 378912c373aSVinod Koul 379912c373aSVinod Koul tz_mem: memory@86200000 { 380912c373aSVinod Koul reg = <0x0 0x86200000 0x0 0x3900000>; 381912c373aSVinod Koul no-map; 382912c373aSVinod Koul }; 383912c373aSVinod Koul 384912c373aSVinod Koul rmtfs_mem: memory@89b00000 { 385912c373aSVinod Koul compatible = "qcom,rmtfs-mem"; 386912c373aSVinod Koul reg = <0x0 0x89b00000 0x0 0x200000>; 387912c373aSVinod Koul no-map; 388912c373aSVinod Koul 389912c373aSVinod Koul qcom,client-id = <1>; 390912c373aSVinod Koul qcom,vmid = <15>; 391912c373aSVinod Koul }; 392912c373aSVinod Koul 393912c373aSVinod Koul camera_mem: memory@8b700000 { 394912c373aSVinod Koul reg = <0x0 0x8b700000 0x0 0x500000>; 395912c373aSVinod Koul no-map; 396912c373aSVinod Koul }; 397912c373aSVinod Koul 398912c373aSVinod Koul wlan_mem: memory@8bc00000 { 399912c373aSVinod Koul reg = <0x0 0x8bc00000 0x0 0x180000>; 400912c373aSVinod Koul no-map; 401912c373aSVinod Koul }; 402912c373aSVinod Koul 403912c373aSVinod Koul npu_mem: memory@8bd80000 { 404912c373aSVinod Koul reg = <0x0 0x8bd80000 0x0 0x80000>; 405912c373aSVinod Koul no-map; 406912c373aSVinod Koul }; 407912c373aSVinod Koul 408912c373aSVinod Koul adsp_mem: memory@8be00000 { 409912c373aSVinod Koul reg = <0x0 0x8be00000 0x0 0x1a00000>; 410912c373aSVinod Koul no-map; 411912c373aSVinod Koul }; 412912c373aSVinod Koul 413912c373aSVinod Koul mpss_mem: memory@8d800000 { 414912c373aSVinod Koul reg = <0x0 0x8d800000 0x0 0x9600000>; 415912c373aSVinod Koul no-map; 416912c373aSVinod Koul }; 417912c373aSVinod Koul 418912c373aSVinod Koul venus_mem: memory@96e00000 { 419912c373aSVinod Koul reg = <0x0 0x96e00000 0x0 0x500000>; 420912c373aSVinod Koul no-map; 421912c373aSVinod Koul }; 422912c373aSVinod Koul 423912c373aSVinod Koul slpi_mem: memory@97300000 { 424912c373aSVinod Koul reg = <0x0 0x97300000 0x0 0x1400000>; 425912c373aSVinod Koul no-map; 426912c373aSVinod Koul }; 427912c373aSVinod Koul 428912c373aSVinod Koul ipa_fw_mem: memory@98700000 { 429912c373aSVinod Koul reg = <0x0 0x98700000 0x0 0x10000>; 430912c373aSVinod Koul no-map; 431912c373aSVinod Koul }; 432912c373aSVinod Koul 433912c373aSVinod Koul ipa_gsi_mem: memory@98710000 { 434912c373aSVinod Koul reg = <0x0 0x98710000 0x0 0x5000>; 435912c373aSVinod Koul no-map; 436912c373aSVinod Koul }; 437912c373aSVinod Koul 438912c373aSVinod Koul gpu_mem: memory@98715000 { 439912c373aSVinod Koul reg = <0x0 0x98715000 0x0 0x2000>; 440912c373aSVinod Koul no-map; 441912c373aSVinod Koul }; 442912c373aSVinod Koul 443912c373aSVinod Koul spss_mem: memory@98800000 { 444912c373aSVinod Koul reg = <0x0 0x98800000 0x0 0x100000>; 445912c373aSVinod Koul no-map; 446912c373aSVinod Koul }; 447912c373aSVinod Koul 448912c373aSVinod Koul cdsp_mem: memory@98900000 { 449912c373aSVinod Koul reg = <0x0 0x98900000 0x0 0x1400000>; 450912c373aSVinod Koul no-map; 451912c373aSVinod Koul }; 452912c373aSVinod Koul 453912c373aSVinod Koul qseecom_mem: memory@9e400000 { 454912c373aSVinod Koul reg = <0x0 0x9e400000 0x0 0x1400000>; 455912c373aSVinod Koul no-map; 456912c373aSVinod Koul }; 457912c373aSVinod Koul }; 458912c373aSVinod Koul 459d8cf9372SVinod Koul smem { 460d8cf9372SVinod Koul compatible = "qcom,smem"; 461d8cf9372SVinod Koul memory-region = <&smem_mem>; 462d8cf9372SVinod Koul hwlocks = <&tcsr_mutex 3>; 463d8cf9372SVinod Koul }; 464d8cf9372SVinod Koul 46561025b81SSibi Sankar smp2p-cdsp { 46661025b81SSibi Sankar compatible = "qcom,smp2p"; 46761025b81SSibi Sankar qcom,smem = <94>, <432>; 46861025b81SSibi Sankar 46961025b81SSibi Sankar interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 47061025b81SSibi Sankar 47161025b81SSibi Sankar mboxes = <&apss_shared 6>; 47261025b81SSibi Sankar 47361025b81SSibi Sankar qcom,local-pid = <0>; 47461025b81SSibi Sankar qcom,remote-pid = <5>; 47561025b81SSibi Sankar 47661025b81SSibi Sankar cdsp_smp2p_out: master-kernel { 47761025b81SSibi Sankar qcom,entry-name = "master-kernel"; 47861025b81SSibi Sankar #qcom,smem-state-cells = <1>; 47961025b81SSibi Sankar }; 48061025b81SSibi Sankar 48161025b81SSibi Sankar cdsp_smp2p_in: slave-kernel { 48261025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 48361025b81SSibi Sankar 48461025b81SSibi Sankar interrupt-controller; 48561025b81SSibi Sankar #interrupt-cells = <2>; 48661025b81SSibi Sankar }; 48761025b81SSibi Sankar }; 48861025b81SSibi Sankar 48961025b81SSibi Sankar smp2p-lpass { 49061025b81SSibi Sankar compatible = "qcom,smp2p"; 49161025b81SSibi Sankar qcom,smem = <443>, <429>; 49261025b81SSibi Sankar 49361025b81SSibi Sankar interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 49461025b81SSibi Sankar 49561025b81SSibi Sankar mboxes = <&apss_shared 10>; 49661025b81SSibi Sankar 49761025b81SSibi Sankar qcom,local-pid = <0>; 49861025b81SSibi Sankar qcom,remote-pid = <2>; 49961025b81SSibi Sankar 50061025b81SSibi Sankar adsp_smp2p_out: master-kernel { 50161025b81SSibi Sankar qcom,entry-name = "master-kernel"; 50261025b81SSibi Sankar #qcom,smem-state-cells = <1>; 50361025b81SSibi Sankar }; 50461025b81SSibi Sankar 50561025b81SSibi Sankar adsp_smp2p_in: slave-kernel { 50661025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 50761025b81SSibi Sankar 50861025b81SSibi Sankar interrupt-controller; 50961025b81SSibi Sankar #interrupt-cells = <2>; 51061025b81SSibi Sankar }; 51161025b81SSibi Sankar }; 51261025b81SSibi Sankar 51361025b81SSibi Sankar smp2p-mpss { 51461025b81SSibi Sankar compatible = "qcom,smp2p"; 51561025b81SSibi Sankar qcom,smem = <435>, <428>; 51661025b81SSibi Sankar 51761025b81SSibi Sankar interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 51861025b81SSibi Sankar 51961025b81SSibi Sankar mboxes = <&apss_shared 14>; 52061025b81SSibi Sankar 52161025b81SSibi Sankar qcom,local-pid = <0>; 52261025b81SSibi Sankar qcom,remote-pid = <1>; 52361025b81SSibi Sankar 52461025b81SSibi Sankar modem_smp2p_out: master-kernel { 52561025b81SSibi Sankar qcom,entry-name = "master-kernel"; 52661025b81SSibi Sankar #qcom,smem-state-cells = <1>; 52761025b81SSibi Sankar }; 52861025b81SSibi Sankar 52961025b81SSibi Sankar modem_smp2p_in: slave-kernel { 53061025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 53161025b81SSibi Sankar 53261025b81SSibi Sankar interrupt-controller; 53361025b81SSibi Sankar #interrupt-cells = <2>; 53461025b81SSibi Sankar }; 53561025b81SSibi Sankar }; 53661025b81SSibi Sankar 53761025b81SSibi Sankar smp2p-slpi { 53861025b81SSibi Sankar compatible = "qcom,smp2p"; 53961025b81SSibi Sankar qcom,smem = <481>, <430>; 54061025b81SSibi Sankar 54161025b81SSibi Sankar interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 54261025b81SSibi Sankar 54361025b81SSibi Sankar mboxes = <&apss_shared 26>; 54461025b81SSibi Sankar 54561025b81SSibi Sankar qcom,local-pid = <0>; 54661025b81SSibi Sankar qcom,remote-pid = <3>; 54761025b81SSibi Sankar 54861025b81SSibi Sankar slpi_smp2p_out: master-kernel { 54961025b81SSibi Sankar qcom,entry-name = "master-kernel"; 55061025b81SSibi Sankar #qcom,smem-state-cells = <1>; 55161025b81SSibi Sankar }; 55261025b81SSibi Sankar 55361025b81SSibi Sankar slpi_smp2p_in: slave-kernel { 55461025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 55561025b81SSibi Sankar 55661025b81SSibi Sankar interrupt-controller; 55761025b81SSibi Sankar #interrupt-cells = <2>; 55861025b81SSibi Sankar }; 55961025b81SSibi Sankar }; 56061025b81SSibi Sankar 561e13c6d14SVinod Koul soc: soc@0 { 562e13c6d14SVinod Koul #address-cells = <2>; 563e13c6d14SVinod Koul #size-cells = <2>; 564e13c6d14SVinod Koul ranges = <0 0 0 0 0x10 0>; 565e13c6d14SVinod Koul dma-ranges = <0 0 0 0 0x10 0>; 566e13c6d14SVinod Koul compatible = "simple-bus"; 567e13c6d14SVinod Koul 568e13c6d14SVinod Koul gcc: clock-controller@100000 { 569e13c6d14SVinod Koul compatible = "qcom,gcc-sm8150"; 570e13c6d14SVinod Koul reg = <0x0 0x00100000 0x0 0x1f0000>; 571e13c6d14SVinod Koul #clock-cells = <1>; 572e13c6d14SVinod Koul #reset-cells = <1>; 573e13c6d14SVinod Koul #power-domain-cells = <1>; 574e13c6d14SVinod Koul clock-names = "bi_tcxo", 575e13c6d14SVinod Koul "sleep_clk"; 576e13c6d14SVinod Koul clocks = <&rpmhcc RPMH_CXO_CLK>, 577e13c6d14SVinod Koul <&sleep_clk>; 578e13c6d14SVinod Koul }; 579e13c6d14SVinod Koul 5809cf3ebd1SCaleb Connolly qupv3_id_0: geniqup@8c0000 { 5819cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 5829cf3ebd1SCaleb Connolly reg = <0x0 0x008c0000 0x0 0x6000>; 5839cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 5849cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 5859cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 5869cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0xc3 0x0>; 5879cf3ebd1SCaleb Connolly #address-cells = <2>; 5889cf3ebd1SCaleb Connolly #size-cells = <2>; 5899cf3ebd1SCaleb Connolly ranges; 5909cf3ebd1SCaleb Connolly status = "disabled"; 59181bee695SCaleb Connolly 59281bee695SCaleb Connolly i2c0: i2c@880000 { 59381bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 59481bee695SCaleb Connolly reg = <0 0x00880000 0 0x4000>; 59581bee695SCaleb Connolly clock-names = "se"; 59681bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 59781bee695SCaleb Connolly pinctrl-names = "default"; 59881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c0_default>; 59981bee695SCaleb Connolly interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 60081bee695SCaleb Connolly #address-cells = <1>; 60181bee695SCaleb Connolly #size-cells = <0>; 60281bee695SCaleb Connolly status = "disabled"; 60381bee695SCaleb Connolly }; 60481bee695SCaleb Connolly 60581bee695SCaleb Connolly i2c1: i2c@884000 { 60681bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 60781bee695SCaleb Connolly reg = <0 0x00884000 0 0x4000>; 60881bee695SCaleb Connolly clock-names = "se"; 60981bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 61081bee695SCaleb Connolly pinctrl-names = "default"; 61181bee695SCaleb Connolly pinctrl-0 = <&qup_i2c1_default>; 61281bee695SCaleb Connolly interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 61381bee695SCaleb Connolly #address-cells = <1>; 61481bee695SCaleb Connolly #size-cells = <0>; 61581bee695SCaleb Connolly status = "disabled"; 61681bee695SCaleb Connolly }; 61781bee695SCaleb Connolly 61881bee695SCaleb Connolly i2c2: i2c@888000 { 61981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 62081bee695SCaleb Connolly reg = <0 0x00888000 0 0x4000>; 62181bee695SCaleb Connolly clock-names = "se"; 62281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 62381bee695SCaleb Connolly pinctrl-names = "default"; 62481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c2_default>; 62581bee695SCaleb Connolly interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 62681bee695SCaleb Connolly #address-cells = <1>; 62781bee695SCaleb Connolly #size-cells = <0>; 62881bee695SCaleb Connolly status = "disabled"; 62981bee695SCaleb Connolly }; 63081bee695SCaleb Connolly 63181bee695SCaleb Connolly i2c3: i2c@88c000 { 63281bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 63381bee695SCaleb Connolly reg = <0 0x0088c000 0 0x4000>; 63481bee695SCaleb Connolly clock-names = "se"; 63581bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 63681bee695SCaleb Connolly pinctrl-names = "default"; 63781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c3_default>; 63881bee695SCaleb Connolly interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 63981bee695SCaleb Connolly #address-cells = <1>; 64081bee695SCaleb Connolly #size-cells = <0>; 64181bee695SCaleb Connolly status = "disabled"; 64281bee695SCaleb Connolly }; 64381bee695SCaleb Connolly 64481bee695SCaleb Connolly i2c4: i2c@890000 { 64581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 64681bee695SCaleb Connolly reg = <0 0x00890000 0 0x4000>; 64781bee695SCaleb Connolly clock-names = "se"; 64881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 64981bee695SCaleb Connolly pinctrl-names = "default"; 65081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c4_default>; 65181bee695SCaleb Connolly interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 65281bee695SCaleb Connolly #address-cells = <1>; 65381bee695SCaleb Connolly #size-cells = <0>; 65481bee695SCaleb Connolly status = "disabled"; 65581bee695SCaleb Connolly }; 65681bee695SCaleb Connolly 65781bee695SCaleb Connolly i2c5: i2c@894000 { 65881bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 65981bee695SCaleb Connolly reg = <0 0x00894000 0 0x4000>; 66081bee695SCaleb Connolly clock-names = "se"; 66181bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 66281bee695SCaleb Connolly pinctrl-names = "default"; 66381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c5_default>; 66481bee695SCaleb Connolly interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 66581bee695SCaleb Connolly #address-cells = <1>; 66681bee695SCaleb Connolly #size-cells = <0>; 66781bee695SCaleb Connolly status = "disabled"; 66881bee695SCaleb Connolly }; 66981bee695SCaleb Connolly 67081bee695SCaleb Connolly i2c6: i2c@898000 { 67181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 67281bee695SCaleb Connolly reg = <0 0x00898000 0 0x4000>; 67381bee695SCaleb Connolly clock-names = "se"; 67481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 67581bee695SCaleb Connolly pinctrl-names = "default"; 67681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c6_default>; 67781bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 67881bee695SCaleb Connolly #address-cells = <1>; 67981bee695SCaleb Connolly #size-cells = <0>; 68081bee695SCaleb Connolly status = "disabled"; 68181bee695SCaleb Connolly }; 68281bee695SCaleb Connolly 68381bee695SCaleb Connolly i2c7: i2c@89c000 { 68481bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 68581bee695SCaleb Connolly reg = <0 0x0089c000 0 0x4000>; 68681bee695SCaleb Connolly clock-names = "se"; 68781bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 68881bee695SCaleb Connolly pinctrl-names = "default"; 68981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c7_default>; 69081bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 69181bee695SCaleb Connolly #address-cells = <1>; 69281bee695SCaleb Connolly #size-cells = <0>; 69381bee695SCaleb Connolly status = "disabled"; 69481bee695SCaleb Connolly }; 69581bee695SCaleb Connolly 6969cf3ebd1SCaleb Connolly }; 6979cf3ebd1SCaleb Connolly 698e13c6d14SVinod Koul qupv3_id_1: geniqup@ac0000 { 699e13c6d14SVinod Koul compatible = "qcom,geni-se-qup"; 700e13c6d14SVinod Koul reg = <0x0 0x00ac0000 0x0 0x6000>; 701e13c6d14SVinod Koul clock-names = "m-ahb", "s-ahb"; 702d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 703d6f55763SVinod Koul <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 7049cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x603 0x0>; 705e13c6d14SVinod Koul #address-cells = <2>; 706e13c6d14SVinod Koul #size-cells = <2>; 707e13c6d14SVinod Koul ranges; 708e13c6d14SVinod Koul status = "disabled"; 709e13c6d14SVinod Koul 71081bee695SCaleb Connolly i2c8: i2c@a80000 { 71181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 71281bee695SCaleb Connolly reg = <0 0x00a80000 0 0x4000>; 71381bee695SCaleb Connolly clock-names = "se"; 71481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 71581bee695SCaleb Connolly pinctrl-names = "default"; 71681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c8_default>; 71781bee695SCaleb Connolly interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 71881bee695SCaleb Connolly #address-cells = <1>; 71981bee695SCaleb Connolly #size-cells = <0>; 72081bee695SCaleb Connolly status = "disabled"; 72181bee695SCaleb Connolly }; 72281bee695SCaleb Connolly 72381bee695SCaleb Connolly i2c9: i2c@a84000 { 72481bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 72581bee695SCaleb Connolly reg = <0 0x00a84000 0 0x4000>; 72681bee695SCaleb Connolly clock-names = "se"; 72781bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 72881bee695SCaleb Connolly pinctrl-names = "default"; 72981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c9_default>; 73081bee695SCaleb Connolly interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 73181bee695SCaleb Connolly #address-cells = <1>; 73281bee695SCaleb Connolly #size-cells = <0>; 73381bee695SCaleb Connolly status = "disabled"; 73481bee695SCaleb Connolly }; 73581bee695SCaleb Connolly 73681bee695SCaleb Connolly i2c10: i2c@a88000 { 73781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 73881bee695SCaleb Connolly reg = <0 0x00a88000 0 0x4000>; 73981bee695SCaleb Connolly clock-names = "se"; 74081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 74181bee695SCaleb Connolly pinctrl-names = "default"; 74281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c10_default>; 74381bee695SCaleb Connolly interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 74481bee695SCaleb Connolly #address-cells = <1>; 74581bee695SCaleb Connolly #size-cells = <0>; 74681bee695SCaleb Connolly status = "disabled"; 74781bee695SCaleb Connolly }; 74881bee695SCaleb Connolly 74981bee695SCaleb Connolly i2c11: i2c@a8c000 { 75081bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 75181bee695SCaleb Connolly reg = <0 0x00a8c000 0 0x4000>; 75281bee695SCaleb Connolly clock-names = "se"; 75381bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 75481bee695SCaleb Connolly pinctrl-names = "default"; 75581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c11_default>; 75681bee695SCaleb Connolly interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 75781bee695SCaleb Connolly #address-cells = <1>; 75881bee695SCaleb Connolly #size-cells = <0>; 75981bee695SCaleb Connolly status = "disabled"; 76081bee695SCaleb Connolly }; 76181bee695SCaleb Connolly 762e13c6d14SVinod Koul uart2: serial@a90000 { 763e13c6d14SVinod Koul compatible = "qcom,geni-debug-uart"; 764e13c6d14SVinod Koul reg = <0x0 0x00a90000 0x0 0x4000>; 765e13c6d14SVinod Koul clock-names = "se"; 766d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 767e13c6d14SVinod Koul interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 768e13c6d14SVinod Koul status = "disabled"; 769e13c6d14SVinod Koul }; 77081bee695SCaleb Connolly 77181bee695SCaleb Connolly i2c12: i2c@a90000 { 77281bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 77381bee695SCaleb Connolly reg = <0 0x00a90000 0 0x4000>; 77481bee695SCaleb Connolly clock-names = "se"; 77581bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 77681bee695SCaleb Connolly pinctrl-names = "default"; 77781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c12_default>; 77881bee695SCaleb Connolly interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 77981bee695SCaleb Connolly #address-cells = <1>; 78081bee695SCaleb Connolly #size-cells = <0>; 78181bee695SCaleb Connolly status = "disabled"; 78281bee695SCaleb Connolly }; 78381bee695SCaleb Connolly 78481bee695SCaleb Connolly i2c16: i2c@94000 { 78581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 78681bee695SCaleb Connolly reg = <0 0x0094000 0 0x4000>; 78781bee695SCaleb Connolly clock-names = "se"; 78881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 78981bee695SCaleb Connolly pinctrl-names = "default"; 79081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c16_default>; 79181bee695SCaleb Connolly interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 79281bee695SCaleb Connolly #address-cells = <1>; 79381bee695SCaleb Connolly #size-cells = <0>; 79481bee695SCaleb Connolly status = "disabled"; 79581bee695SCaleb Connolly }; 796e13c6d14SVinod Koul }; 797e13c6d14SVinod Koul 7989cf3ebd1SCaleb Connolly qupv3_id_2: geniqup@cc0000 { 7999cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 8009cf3ebd1SCaleb Connolly reg = <0x0 0x00cc0000 0x0 0x6000>; 8019cf3ebd1SCaleb Connolly 8029cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 8039cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 8049cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 8059cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x7a3 0x0>; 8069cf3ebd1SCaleb Connolly #address-cells = <2>; 8079cf3ebd1SCaleb Connolly #size-cells = <2>; 8089cf3ebd1SCaleb Connolly ranges; 8099cf3ebd1SCaleb Connolly status = "disabled"; 81081bee695SCaleb Connolly 81181bee695SCaleb Connolly i2c17: i2c@c80000 { 81281bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 81381bee695SCaleb Connolly reg = <0 0x00c80000 0 0x4000>; 81481bee695SCaleb Connolly clock-names = "se"; 81581bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 81681bee695SCaleb Connolly pinctrl-names = "default"; 81781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c17_default>; 81881bee695SCaleb Connolly interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 81981bee695SCaleb Connolly #address-cells = <1>; 82081bee695SCaleb Connolly #size-cells = <0>; 82181bee695SCaleb Connolly status = "disabled"; 82281bee695SCaleb Connolly }; 82381bee695SCaleb Connolly 82481bee695SCaleb Connolly i2c18: i2c@c84000 { 82581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 82681bee695SCaleb Connolly reg = <0 0x00c84000 0 0x4000>; 82781bee695SCaleb Connolly clock-names = "se"; 82881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 82981bee695SCaleb Connolly pinctrl-names = "default"; 83081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c18_default>; 83181bee695SCaleb Connolly interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 83281bee695SCaleb Connolly #address-cells = <1>; 83381bee695SCaleb Connolly #size-cells = <0>; 83481bee695SCaleb Connolly status = "disabled"; 83581bee695SCaleb Connolly }; 83681bee695SCaleb Connolly 83781bee695SCaleb Connolly i2c19: i2c@c88000 { 83881bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 83981bee695SCaleb Connolly reg = <0 0x00c88000 0 0x4000>; 84081bee695SCaleb Connolly clock-names = "se"; 84181bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 84281bee695SCaleb Connolly pinctrl-names = "default"; 84381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c19_default>; 84481bee695SCaleb Connolly interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 84581bee695SCaleb Connolly #address-cells = <1>; 84681bee695SCaleb Connolly #size-cells = <0>; 84781bee695SCaleb Connolly status = "disabled"; 84881bee695SCaleb Connolly }; 84981bee695SCaleb Connolly 85081bee695SCaleb Connolly i2c13: i2c@c8c000 { 85181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 85281bee695SCaleb Connolly reg = <0 0x00c8c000 0 0x4000>; 85381bee695SCaleb Connolly clock-names = "se"; 85481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 85581bee695SCaleb Connolly pinctrl-names = "default"; 85681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c13_default>; 85781bee695SCaleb Connolly interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 85881bee695SCaleb Connolly #address-cells = <1>; 85981bee695SCaleb Connolly #size-cells = <0>; 86081bee695SCaleb Connolly status = "disabled"; 86181bee695SCaleb Connolly }; 86281bee695SCaleb Connolly 86381bee695SCaleb Connolly i2c14: i2c@c90000 { 86481bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 86581bee695SCaleb Connolly reg = <0 0x00c90000 0 0x4000>; 86681bee695SCaleb Connolly clock-names = "se"; 86781bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 86881bee695SCaleb Connolly pinctrl-names = "default"; 86981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c14_default>; 87081bee695SCaleb Connolly interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 87181bee695SCaleb Connolly #address-cells = <1>; 87281bee695SCaleb Connolly #size-cells = <0>; 87381bee695SCaleb Connolly status = "disabled"; 87481bee695SCaleb Connolly }; 87581bee695SCaleb Connolly 87681bee695SCaleb Connolly i2c15: i2c@c94000 { 87781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 87881bee695SCaleb Connolly reg = <0 0x00c94000 0 0x4000>; 87981bee695SCaleb Connolly clock-names = "se"; 88081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 88181bee695SCaleb Connolly pinctrl-names = "default"; 88281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c15_default>; 88381bee695SCaleb Connolly interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 88481bee695SCaleb Connolly #address-cells = <1>; 88581bee695SCaleb Connolly #size-cells = <0>; 88681bee695SCaleb Connolly status = "disabled"; 88781bee695SCaleb Connolly }; 8889cf3ebd1SCaleb Connolly }; 8899cf3ebd1SCaleb Connolly 89071a2fc6eSJonathan Marek config_noc: interconnect@1500000 { 89171a2fc6eSJonathan Marek compatible = "qcom,sm8150-config-noc"; 89271a2fc6eSJonathan Marek reg = <0 0x01500000 0 0x7400>; 89371a2fc6eSJonathan Marek #interconnect-cells = <1>; 89471a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 89571a2fc6eSJonathan Marek }; 89671a2fc6eSJonathan Marek 89771a2fc6eSJonathan Marek system_noc: interconnect@1620000 { 89871a2fc6eSJonathan Marek compatible = "qcom,sm8150-system-noc"; 89971a2fc6eSJonathan Marek reg = <0 0x01620000 0 0x19400>; 90071a2fc6eSJonathan Marek #interconnect-cells = <1>; 90171a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 90271a2fc6eSJonathan Marek }; 90371a2fc6eSJonathan Marek 90471a2fc6eSJonathan Marek mc_virt: interconnect@163a000 { 90571a2fc6eSJonathan Marek compatible = "qcom,sm8150-mc-virt"; 90671a2fc6eSJonathan Marek reg = <0 0x0163a000 0 0x1000>; 90771a2fc6eSJonathan Marek #interconnect-cells = <1>; 90871a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 90971a2fc6eSJonathan Marek }; 91071a2fc6eSJonathan Marek 91171a2fc6eSJonathan Marek aggre1_noc: interconnect@16e0000 { 91271a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre1-noc"; 91371a2fc6eSJonathan Marek reg = <0 0x016e0000 0 0xd080>; 91471a2fc6eSJonathan Marek #interconnect-cells = <1>; 91571a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 91671a2fc6eSJonathan Marek }; 91771a2fc6eSJonathan Marek 91871a2fc6eSJonathan Marek aggre2_noc: interconnect@1700000 { 91971a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre2-noc"; 92071a2fc6eSJonathan Marek reg = <0 0x01700000 0 0x20000>; 92171a2fc6eSJonathan Marek #interconnect-cells = <1>; 92271a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 92371a2fc6eSJonathan Marek }; 92471a2fc6eSJonathan Marek 92571a2fc6eSJonathan Marek compute_noc: interconnect@1720000 { 92671a2fc6eSJonathan Marek compatible = "qcom,sm8150-compute-noc"; 92771a2fc6eSJonathan Marek reg = <0 0x01720000 0 0x7000>; 92871a2fc6eSJonathan Marek #interconnect-cells = <1>; 92971a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 93071a2fc6eSJonathan Marek }; 93171a2fc6eSJonathan Marek 93271a2fc6eSJonathan Marek mmss_noc: interconnect@1740000 { 93371a2fc6eSJonathan Marek compatible = "qcom,sm8150-mmss-noc"; 93471a2fc6eSJonathan Marek reg = <0 0x01740000 0 0x1c100>; 93571a2fc6eSJonathan Marek #interconnect-cells = <1>; 93671a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 93771a2fc6eSJonathan Marek }; 93871a2fc6eSJonathan Marek 939bb1f7cf6SSouradeep Chowdhury system-cache-controller@9200000 { 940bb1f7cf6SSouradeep Chowdhury compatible = "qcom,sm8150-llcc"; 941bb1f7cf6SSouradeep Chowdhury reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 942bb1f7cf6SSouradeep Chowdhury reg-names = "llcc_base", "llcc_broadcast_base"; 943bb1f7cf6SSouradeep Chowdhury interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 944bb1f7cf6SSouradeep Chowdhury }; 945bb1f7cf6SSouradeep Chowdhury 9463834a2e9SVinod Koul ufs_mem_hc: ufshc@1d84000 { 9473834a2e9SVinod Koul compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 9483834a2e9SVinod Koul "jedec,ufs-2.0"; 9493834a2e9SVinod Koul reg = <0 0x01d84000 0 0x2500>; 9503834a2e9SVinod Koul interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 9513834a2e9SVinod Koul phys = <&ufs_mem_phy_lanes>; 9523834a2e9SVinod Koul phy-names = "ufsphy"; 9533834a2e9SVinod Koul lanes-per-direction = <2>; 9543834a2e9SVinod Koul #reset-cells = <1>; 9553834a2e9SVinod Koul resets = <&gcc GCC_UFS_PHY_BCR>; 9563834a2e9SVinod Koul reset-names = "rst"; 9573834a2e9SVinod Koul 95848156232SJonathan Marek iommus = <&apps_smmu 0x300 0>; 95948156232SJonathan Marek 9603834a2e9SVinod Koul clock-names = 9613834a2e9SVinod Koul "core_clk", 9623834a2e9SVinod Koul "bus_aggr_clk", 9633834a2e9SVinod Koul "iface_clk", 9643834a2e9SVinod Koul "core_clk_unipro", 9653834a2e9SVinod Koul "ref_clk", 9663834a2e9SVinod Koul "tx_lane0_sync_clk", 9673834a2e9SVinod Koul "rx_lane0_sync_clk", 9683834a2e9SVinod Koul "rx_lane1_sync_clk"; 9693834a2e9SVinod Koul clocks = 9703834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AXI_CLK>, 9713834a2e9SVinod Koul <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 9723834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AHB_CLK>, 9733834a2e9SVinod Koul <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 9743834a2e9SVinod Koul <&rpmhcc RPMH_CXO_CLK>, 9753834a2e9SVinod Koul <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 9763834a2e9SVinod Koul <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 9773834a2e9SVinod Koul <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 9783834a2e9SVinod Koul freq-table-hz = 9793834a2e9SVinod Koul <37500000 300000000>, 9803834a2e9SVinod Koul <0 0>, 9813834a2e9SVinod Koul <0 0>, 9823834a2e9SVinod Koul <37500000 300000000>, 9833834a2e9SVinod Koul <0 0>, 9843834a2e9SVinod Koul <0 0>, 9853834a2e9SVinod Koul <0 0>, 9863834a2e9SVinod Koul <0 0>; 9873834a2e9SVinod Koul 9883834a2e9SVinod Koul status = "disabled"; 9893834a2e9SVinod Koul }; 9903834a2e9SVinod Koul 9913834a2e9SVinod Koul ufs_mem_phy: phy@1d87000 { 9923834a2e9SVinod Koul compatible = "qcom,sm8150-qmp-ufs-phy"; 993c79ec891SVinod Koul reg = <0 0x01d87000 0 0x1c0>; 9943834a2e9SVinod Koul #address-cells = <2>; 9953834a2e9SVinod Koul #size-cells = <2>; 9963834a2e9SVinod Koul ranges; 9973834a2e9SVinod Koul clock-names = "ref", 9983834a2e9SVinod Koul "ref_aux"; 9993834a2e9SVinod Koul clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 10003834a2e9SVinod Koul <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 10013834a2e9SVinod Koul 10023834a2e9SVinod Koul resets = <&ufs_mem_hc 0>; 10033834a2e9SVinod Koul reset-names = "ufsphy"; 10043834a2e9SVinod Koul status = "disabled"; 10053834a2e9SVinod Koul 10063834a2e9SVinod Koul ufs_mem_phy_lanes: lanes@1d87400 { 10073834a2e9SVinod Koul reg = <0 0x01d87400 0 0x108>, 10083834a2e9SVinod Koul <0 0x01d87600 0 0x1e0>, 10093834a2e9SVinod Koul <0 0x01d87c00 0 0x1dc>, 10103834a2e9SVinod Koul <0 0x01d87800 0 0x108>, 10113834a2e9SVinod Koul <0 0x01d87a00 0 0x1e0>; 10123834a2e9SVinod Koul #phy-cells = <0>; 10133834a2e9SVinod Koul }; 10143834a2e9SVinod Koul }; 10153834a2e9SVinod Koul 101671a2fc6eSJonathan Marek ipa_virt: interconnect@1e00000 { 101771a2fc6eSJonathan Marek compatible = "qcom,sm8150-ipa-virt"; 101871a2fc6eSJonathan Marek reg = <0 0x01e00000 0 0x1000>; 101971a2fc6eSJonathan Marek #interconnect-cells = <1>; 102071a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 102171a2fc6eSJonathan Marek }; 102271a2fc6eSJonathan Marek 1023d8cf9372SVinod Koul tcsr_mutex_regs: syscon@1f40000 { 1024d8cf9372SVinod Koul compatible = "syscon"; 1025d8cf9372SVinod Koul reg = <0x0 0x01f40000 0x0 0x40000>; 1026d8cf9372SVinod Koul }; 1027d8cf9372SVinod Koul 102849076351SSibi Sankar remoteproc_slpi: remoteproc@2400000 { 102949076351SSibi Sankar compatible = "qcom,sm8150-slpi-pas"; 103049076351SSibi Sankar reg = <0x0 0x02400000 0x0 0x4040>; 103149076351SSibi Sankar 103249076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 103349076351SSibi Sankar <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 103449076351SSibi Sankar <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 103549076351SSibi Sankar <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 103649076351SSibi Sankar <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 103749076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 103849076351SSibi Sankar "handover", "stop-ack"; 103949076351SSibi Sankar 104049076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 104149076351SSibi Sankar clock-names = "xo"; 104249076351SSibi Sankar 104349076351SSibi Sankar power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, 1044d0770627SBjorn Andersson <&rpmhpd 3>, 1045d0770627SBjorn Andersson <&rpmhpd 2>; 104649076351SSibi Sankar power-domain-names = "load_state", "lcx", "lmx"; 104749076351SSibi Sankar 104849076351SSibi Sankar memory-region = <&slpi_mem>; 104949076351SSibi Sankar 105049076351SSibi Sankar qcom,smem-states = <&slpi_smp2p_out 0>; 105149076351SSibi Sankar qcom,smem-state-names = "stop"; 105249076351SSibi Sankar 105349076351SSibi Sankar status = "disabled"; 105449076351SSibi Sankar 105549076351SSibi Sankar glink-edge { 105649076351SSibi Sankar interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 105749076351SSibi Sankar label = "dsps"; 105849076351SSibi Sankar qcom,remote-pid = <3>; 105949076351SSibi Sankar mboxes = <&apss_shared 24>; 106049076351SSibi Sankar }; 106149076351SSibi Sankar }; 106249076351SSibi Sankar 1063f30ac26dSJonathan Marek gpu: gpu@2c00000 { 1064f30ac26dSJonathan Marek /* 1065f30ac26dSJonathan Marek * note: the amd,imageon compatible makes it possible 1066f30ac26dSJonathan Marek * to use the drm/msm driver without the display node, 1067f30ac26dSJonathan Marek * make sure to remove it when display node is added 1068f30ac26dSJonathan Marek */ 1069f30ac26dSJonathan Marek compatible = "qcom,adreno-640.1", 1070f30ac26dSJonathan Marek "qcom,adreno", 1071f30ac26dSJonathan Marek "amd,imageon"; 1072f30ac26dSJonathan Marek #stream-id-cells = <16>; 1073f30ac26dSJonathan Marek 1074f30ac26dSJonathan Marek reg = <0 0x02c00000 0 0x40000>; 1075f30ac26dSJonathan Marek reg-names = "kgsl_3d0_reg_memory"; 1076f30ac26dSJonathan Marek 1077f30ac26dSJonathan Marek interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1078f30ac26dSJonathan Marek 1079f30ac26dSJonathan Marek iommus = <&adreno_smmu 0 0x401>; 1080f30ac26dSJonathan Marek 1081f30ac26dSJonathan Marek operating-points-v2 = <&gpu_opp_table>; 1082f30ac26dSJonathan Marek 1083f30ac26dSJonathan Marek qcom,gmu = <&gmu>; 1084f30ac26dSJonathan Marek 1085f30ac26dSJonathan Marek zap-shader { 1086f30ac26dSJonathan Marek memory-region = <&gpu_mem>; 1087f30ac26dSJonathan Marek }; 1088f30ac26dSJonathan Marek 1089f30ac26dSJonathan Marek /* note: downstream checks gpu binning for 675 Mhz */ 1090f30ac26dSJonathan Marek gpu_opp_table: opp-table { 1091f30ac26dSJonathan Marek compatible = "operating-points-v2"; 1092f30ac26dSJonathan Marek 1093f30ac26dSJonathan Marek opp-675000000 { 1094f30ac26dSJonathan Marek opp-hz = /bits/ 64 <675000000>; 1095f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1096f30ac26dSJonathan Marek }; 1097f30ac26dSJonathan Marek 1098f30ac26dSJonathan Marek opp-585000000 { 1099f30ac26dSJonathan Marek opp-hz = /bits/ 64 <585000000>; 1100f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1101f30ac26dSJonathan Marek }; 1102f30ac26dSJonathan Marek 1103f30ac26dSJonathan Marek opp-499200000 { 1104f30ac26dSJonathan Marek opp-hz = /bits/ 64 <499200000>; 1105f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1106f30ac26dSJonathan Marek }; 1107f30ac26dSJonathan Marek 1108f30ac26dSJonathan Marek opp-427000000 { 1109f30ac26dSJonathan Marek opp-hz = /bits/ 64 <427000000>; 1110f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1111f30ac26dSJonathan Marek }; 1112f30ac26dSJonathan Marek 1113f30ac26dSJonathan Marek opp-345000000 { 1114f30ac26dSJonathan Marek opp-hz = /bits/ 64 <345000000>; 1115f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1116f30ac26dSJonathan Marek }; 1117f30ac26dSJonathan Marek 1118f30ac26dSJonathan Marek opp-257000000 { 1119f30ac26dSJonathan Marek opp-hz = /bits/ 64 <257000000>; 1120f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1121f30ac26dSJonathan Marek }; 1122f30ac26dSJonathan Marek }; 1123f30ac26dSJonathan Marek }; 1124f30ac26dSJonathan Marek 1125f30ac26dSJonathan Marek gmu: gmu@2c6a000 { 1126f30ac26dSJonathan Marek compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 1127f30ac26dSJonathan Marek 1128f30ac26dSJonathan Marek reg = <0 0x02c6a000 0 0x30000>, 1129f30ac26dSJonathan Marek <0 0x0b290000 0 0x10000>, 1130f30ac26dSJonathan Marek <0 0x0b490000 0 0x10000>; 1131f30ac26dSJonathan Marek reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 1132f30ac26dSJonathan Marek 1133f30ac26dSJonathan Marek interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1134f30ac26dSJonathan Marek <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1135f30ac26dSJonathan Marek interrupt-names = "hfi", "gmu"; 1136f30ac26dSJonathan Marek 1137f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 1138f1269916SJonathan Marek <&gpucc GPU_CC_CX_GMU_CLK>, 1139f1269916SJonathan Marek <&gpucc GPU_CC_CXO_CLK>, 1140f30ac26dSJonathan Marek <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1141f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1142f30ac26dSJonathan Marek clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 1143f30ac26dSJonathan Marek 1144f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>, 1145f1269916SJonathan Marek <&gpucc GPU_GX_GDSC>; 1146f30ac26dSJonathan Marek power-domain-names = "cx", "gx"; 1147f30ac26dSJonathan Marek 1148f30ac26dSJonathan Marek iommus = <&adreno_smmu 5 0x400>; 1149f30ac26dSJonathan Marek 1150f30ac26dSJonathan Marek operating-points-v2 = <&gmu_opp_table>; 1151f30ac26dSJonathan Marek 1152f30ac26dSJonathan Marek gmu_opp_table: opp-table { 1153f30ac26dSJonathan Marek compatible = "operating-points-v2"; 1154f30ac26dSJonathan Marek 1155f30ac26dSJonathan Marek opp-200000000 { 1156f30ac26dSJonathan Marek opp-hz = /bits/ 64 <200000000>; 1157f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1158f30ac26dSJonathan Marek }; 1159f30ac26dSJonathan Marek }; 1160f30ac26dSJonathan Marek }; 1161f30ac26dSJonathan Marek 1162f30ac26dSJonathan Marek gpucc: clock-controller@2c90000 { 1163f30ac26dSJonathan Marek compatible = "qcom,sm8150-gpucc"; 1164f30ac26dSJonathan Marek reg = <0 0x02c90000 0 0x9000>; 1165f30ac26dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>, 1166f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1167f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1168f30ac26dSJonathan Marek clock-names = "bi_tcxo", 1169f30ac26dSJonathan Marek "gcc_gpu_gpll0_clk_src", 1170f30ac26dSJonathan Marek "gcc_gpu_gpll0_div_clk_src"; 1171f30ac26dSJonathan Marek #clock-cells = <1>; 1172f30ac26dSJonathan Marek #reset-cells = <1>; 1173f30ac26dSJonathan Marek #power-domain-cells = <1>; 1174f30ac26dSJonathan Marek }; 1175f30ac26dSJonathan Marek 1176f30ac26dSJonathan Marek adreno_smmu: iommu@2ca0000 { 1177f30ac26dSJonathan Marek compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 1178f30ac26dSJonathan Marek reg = <0 0x02ca0000 0 0x10000>; 1179f30ac26dSJonathan Marek #iommu-cells = <2>; 1180f30ac26dSJonathan Marek #global-interrupts = <1>; 1181f30ac26dSJonathan Marek interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 1182f30ac26dSJonathan Marek <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1183f30ac26dSJonathan Marek <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1184f30ac26dSJonathan Marek <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1185f30ac26dSJonathan Marek <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1186f30ac26dSJonathan Marek <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1187f30ac26dSJonathan Marek <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1188f30ac26dSJonathan Marek <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 1189f30ac26dSJonathan Marek <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 1190f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 1191f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1192f30ac26dSJonathan Marek <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1193f30ac26dSJonathan Marek clock-names = "ahb", "bus", "iface"; 1194f30ac26dSJonathan Marek 1195f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>; 1196f30ac26dSJonathan Marek }; 1197f30ac26dSJonathan Marek 1198e13c6d14SVinod Koul tlmm: pinctrl@3100000 { 1199e13c6d14SVinod Koul compatible = "qcom,sm8150-pinctrl"; 1200e13c6d14SVinod Koul reg = <0x0 0x03100000 0x0 0x300000>, 1201e13c6d14SVinod Koul <0x0 0x03500000 0x0 0x300000>, 1202e13c6d14SVinod Koul <0x0 0x03900000 0x0 0x300000>, 1203e13c6d14SVinod Koul <0x0 0x03D00000 0x0 0x300000>; 1204e13c6d14SVinod Koul reg-names = "west", "east", "north", "south"; 1205e13c6d14SVinod Koul interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1206de3abdf3SShawn Guo gpio-ranges = <&tlmm 0 0 176>; 1207e13c6d14SVinod Koul gpio-controller; 1208e13c6d14SVinod Koul #gpio-cells = <2>; 1209e13c6d14SVinod Koul interrupt-controller; 1210e13c6d14SVinod Koul #interrupt-cells = <2>; 121181bee695SCaleb Connolly 121281bee695SCaleb Connolly qup_i2c0_default: qup-i2c0-default { 121381bee695SCaleb Connolly mux { 121481bee695SCaleb Connolly pins = "gpio0", "gpio1"; 121581bee695SCaleb Connolly function = "qup0"; 121681bee695SCaleb Connolly }; 121781bee695SCaleb Connolly 121881bee695SCaleb Connolly config { 121981bee695SCaleb Connolly pins = "gpio0", "gpio1"; 122081bee695SCaleb Connolly drive-strength = <0x02>; 122181bee695SCaleb Connolly bias-disable; 122281bee695SCaleb Connolly }; 122381bee695SCaleb Connolly }; 122481bee695SCaleb Connolly 122581bee695SCaleb Connolly qup_i2c1_default: qup-i2c1-default { 122681bee695SCaleb Connolly mux { 122781bee695SCaleb Connolly pins = "gpio114", "gpio115"; 122881bee695SCaleb Connolly function = "qup1"; 122981bee695SCaleb Connolly }; 123081bee695SCaleb Connolly 123181bee695SCaleb Connolly config { 123281bee695SCaleb Connolly pins = "gpio114", "gpio115"; 123381bee695SCaleb Connolly drive-strength = <0x02>; 123481bee695SCaleb Connolly bias-disable; 123581bee695SCaleb Connolly }; 123681bee695SCaleb Connolly }; 123781bee695SCaleb Connolly 123881bee695SCaleb Connolly qup_i2c2_default: qup-i2c2-default { 123981bee695SCaleb Connolly mux { 124081bee695SCaleb Connolly pins = "gpio126", "gpio127"; 124181bee695SCaleb Connolly function = "qup2"; 124281bee695SCaleb Connolly }; 124381bee695SCaleb Connolly 124481bee695SCaleb Connolly config { 124581bee695SCaleb Connolly pins = "gpio126", "gpio127"; 124681bee695SCaleb Connolly drive-strength = <0x02>; 124781bee695SCaleb Connolly bias-disable; 124881bee695SCaleb Connolly }; 124981bee695SCaleb Connolly }; 125081bee695SCaleb Connolly 125181bee695SCaleb Connolly qup_i2c3_default: qup-i2c3-default { 125281bee695SCaleb Connolly mux { 125381bee695SCaleb Connolly pins = "gpio144", "gpio145"; 125481bee695SCaleb Connolly function = "qup3"; 125581bee695SCaleb Connolly }; 125681bee695SCaleb Connolly 125781bee695SCaleb Connolly config { 125881bee695SCaleb Connolly pins = "gpio144", "gpio145"; 125981bee695SCaleb Connolly drive-strength = <0x02>; 126081bee695SCaleb Connolly bias-disable; 126181bee695SCaleb Connolly }; 126281bee695SCaleb Connolly }; 126381bee695SCaleb Connolly 126481bee695SCaleb Connolly qup_i2c4_default: qup-i2c4-default { 126581bee695SCaleb Connolly mux { 126681bee695SCaleb Connolly pins = "gpio51", "gpio52"; 126781bee695SCaleb Connolly function = "qup4"; 126881bee695SCaleb Connolly }; 126981bee695SCaleb Connolly 127081bee695SCaleb Connolly config { 127181bee695SCaleb Connolly pins = "gpio51", "gpio52"; 127281bee695SCaleb Connolly drive-strength = <0x02>; 127381bee695SCaleb Connolly bias-disable; 127481bee695SCaleb Connolly }; 127581bee695SCaleb Connolly }; 127681bee695SCaleb Connolly 127781bee695SCaleb Connolly qup_i2c5_default: qup-i2c5-default { 127881bee695SCaleb Connolly mux { 127981bee695SCaleb Connolly pins = "gpio121", "gpio122"; 128081bee695SCaleb Connolly function = "qup5"; 128181bee695SCaleb Connolly }; 128281bee695SCaleb Connolly 128381bee695SCaleb Connolly config { 128481bee695SCaleb Connolly pins = "gpio121", "gpio122"; 128581bee695SCaleb Connolly drive-strength = <0x02>; 128681bee695SCaleb Connolly bias-disable; 128781bee695SCaleb Connolly }; 128881bee695SCaleb Connolly }; 128981bee695SCaleb Connolly 129081bee695SCaleb Connolly qup_i2c6_default: qup-i2c6-default { 129181bee695SCaleb Connolly mux { 129281bee695SCaleb Connolly pins = "gpio6", "gpio7"; 129381bee695SCaleb Connolly function = "qup6"; 129481bee695SCaleb Connolly }; 129581bee695SCaleb Connolly 129681bee695SCaleb Connolly config { 129781bee695SCaleb Connolly pins = "gpio6", "gpio7"; 129881bee695SCaleb Connolly drive-strength = <0x02>; 129981bee695SCaleb Connolly bias-disable; 130081bee695SCaleb Connolly }; 130181bee695SCaleb Connolly }; 130281bee695SCaleb Connolly 130381bee695SCaleb Connolly qup_i2c7_default: qup-i2c7-default { 130481bee695SCaleb Connolly mux { 130581bee695SCaleb Connolly pins = "gpio98", "gpio99"; 130681bee695SCaleb Connolly function = "qup7"; 130781bee695SCaleb Connolly }; 130881bee695SCaleb Connolly 130981bee695SCaleb Connolly config { 131081bee695SCaleb Connolly pins = "gpio98", "gpio99"; 131181bee695SCaleb Connolly drive-strength = <0x02>; 131281bee695SCaleb Connolly bias-disable; 131381bee695SCaleb Connolly }; 131481bee695SCaleb Connolly }; 131581bee695SCaleb Connolly 131681bee695SCaleb Connolly qup_i2c8_default: qup-i2c8-default { 131781bee695SCaleb Connolly mux { 131881bee695SCaleb Connolly pins = "gpio88", "gpio89"; 131981bee695SCaleb Connolly function = "qup8"; 132081bee695SCaleb Connolly }; 132181bee695SCaleb Connolly 132281bee695SCaleb Connolly config { 132381bee695SCaleb Connolly pins = "gpio88", "gpio89"; 132481bee695SCaleb Connolly drive-strength = <0x02>; 132581bee695SCaleb Connolly bias-disable; 132681bee695SCaleb Connolly }; 132781bee695SCaleb Connolly }; 132881bee695SCaleb Connolly 132981bee695SCaleb Connolly qup_i2c9_default: qup-i2c9-default { 133081bee695SCaleb Connolly mux { 133181bee695SCaleb Connolly pins = "gpio39", "gpio40"; 133281bee695SCaleb Connolly function = "qup9"; 133381bee695SCaleb Connolly }; 133481bee695SCaleb Connolly 133581bee695SCaleb Connolly config { 133681bee695SCaleb Connolly pins = "gpio39", "gpio40"; 133781bee695SCaleb Connolly drive-strength = <0x02>; 133881bee695SCaleb Connolly bias-disable; 133981bee695SCaleb Connolly }; 134081bee695SCaleb Connolly }; 134181bee695SCaleb Connolly 134281bee695SCaleb Connolly qup_i2c10_default: qup-i2c10-default { 134381bee695SCaleb Connolly mux { 134481bee695SCaleb Connolly pins = "gpio9", "gpio10"; 134581bee695SCaleb Connolly function = "qup10"; 134681bee695SCaleb Connolly }; 134781bee695SCaleb Connolly 134881bee695SCaleb Connolly config { 134981bee695SCaleb Connolly pins = "gpio9", "gpio10"; 135081bee695SCaleb Connolly drive-strength = <0x02>; 135181bee695SCaleb Connolly bias-disable; 135281bee695SCaleb Connolly }; 135381bee695SCaleb Connolly }; 135481bee695SCaleb Connolly 135581bee695SCaleb Connolly qup_i2c11_default: qup-i2c11-default { 135681bee695SCaleb Connolly mux { 135781bee695SCaleb Connolly pins = "gpio94", "gpio95"; 135881bee695SCaleb Connolly function = "qup11"; 135981bee695SCaleb Connolly }; 136081bee695SCaleb Connolly 136181bee695SCaleb Connolly config { 136281bee695SCaleb Connolly pins = "gpio94", "gpio95"; 136381bee695SCaleb Connolly drive-strength = <0x02>; 136481bee695SCaleb Connolly bias-disable; 136581bee695SCaleb Connolly }; 136681bee695SCaleb Connolly }; 136781bee695SCaleb Connolly 136881bee695SCaleb Connolly qup_i2c12_default: qup-i2c12-default { 136981bee695SCaleb Connolly mux { 137081bee695SCaleb Connolly pins = "gpio83", "gpio84"; 137181bee695SCaleb Connolly function = "qup12"; 137281bee695SCaleb Connolly }; 137381bee695SCaleb Connolly 137481bee695SCaleb Connolly config { 137581bee695SCaleb Connolly pins = "gpio83", "gpio84"; 137681bee695SCaleb Connolly drive-strength = <0x02>; 137781bee695SCaleb Connolly bias-disable; 137881bee695SCaleb Connolly }; 137981bee695SCaleb Connolly }; 138081bee695SCaleb Connolly 138181bee695SCaleb Connolly qup_i2c13_default: qup-i2c13-default { 138281bee695SCaleb Connolly mux { 138381bee695SCaleb Connolly pins = "gpio43", "gpio44"; 138481bee695SCaleb Connolly function = "qup13"; 138581bee695SCaleb Connolly }; 138681bee695SCaleb Connolly 138781bee695SCaleb Connolly config { 138881bee695SCaleb Connolly pins = "gpio43", "gpio44"; 138981bee695SCaleb Connolly drive-strength = <0x02>; 139081bee695SCaleb Connolly bias-disable; 139181bee695SCaleb Connolly }; 139281bee695SCaleb Connolly }; 139381bee695SCaleb Connolly 139481bee695SCaleb Connolly qup_i2c14_default: qup-i2c14-default { 139581bee695SCaleb Connolly mux { 139681bee695SCaleb Connolly pins = "gpio47", "gpio48"; 139781bee695SCaleb Connolly function = "qup14"; 139881bee695SCaleb Connolly }; 139981bee695SCaleb Connolly 140081bee695SCaleb Connolly config { 140181bee695SCaleb Connolly pins = "gpio47", "gpio48"; 140281bee695SCaleb Connolly drive-strength = <0x02>; 140381bee695SCaleb Connolly bias-disable; 140481bee695SCaleb Connolly }; 140581bee695SCaleb Connolly }; 140681bee695SCaleb Connolly 140781bee695SCaleb Connolly qup_i2c15_default: qup-i2c15-default { 140881bee695SCaleb Connolly mux { 140981bee695SCaleb Connolly pins = "gpio27", "gpio28"; 141081bee695SCaleb Connolly function = "qup15"; 141181bee695SCaleb Connolly }; 141281bee695SCaleb Connolly 141381bee695SCaleb Connolly config { 141481bee695SCaleb Connolly pins = "gpio27", "gpio28"; 141581bee695SCaleb Connolly drive-strength = <0x02>; 141681bee695SCaleb Connolly bias-disable; 141781bee695SCaleb Connolly }; 141881bee695SCaleb Connolly }; 141981bee695SCaleb Connolly 142081bee695SCaleb Connolly qup_i2c16_default: qup-i2c16-default { 142181bee695SCaleb Connolly mux { 142281bee695SCaleb Connolly pins = "gpio86", "gpio85"; 142381bee695SCaleb Connolly function = "qup16"; 142481bee695SCaleb Connolly }; 142581bee695SCaleb Connolly 142681bee695SCaleb Connolly config { 142781bee695SCaleb Connolly pins = "gpio86", "gpio85"; 142881bee695SCaleb Connolly drive-strength = <0x02>; 142981bee695SCaleb Connolly bias-disable; 143081bee695SCaleb Connolly }; 143181bee695SCaleb Connolly }; 143281bee695SCaleb Connolly 143381bee695SCaleb Connolly qup_i2c17_default: qup-i2c17-default { 143481bee695SCaleb Connolly mux { 143581bee695SCaleb Connolly pins = "gpio55", "gpio56"; 143681bee695SCaleb Connolly function = "qup17"; 143781bee695SCaleb Connolly }; 143881bee695SCaleb Connolly 143981bee695SCaleb Connolly config { 144081bee695SCaleb Connolly pins = "gpio55", "gpio56"; 144181bee695SCaleb Connolly drive-strength = <0x02>; 144281bee695SCaleb Connolly bias-disable; 144381bee695SCaleb Connolly }; 144481bee695SCaleb Connolly }; 144581bee695SCaleb Connolly 144681bee695SCaleb Connolly qup_i2c18_default: qup-i2c18-default { 144781bee695SCaleb Connolly mux { 144881bee695SCaleb Connolly pins = "gpio23", "gpio24"; 144981bee695SCaleb Connolly function = "qup18"; 145081bee695SCaleb Connolly }; 145181bee695SCaleb Connolly 145281bee695SCaleb Connolly config { 145381bee695SCaleb Connolly pins = "gpio23", "gpio24"; 145481bee695SCaleb Connolly drive-strength = <0x02>; 145581bee695SCaleb Connolly bias-disable; 145681bee695SCaleb Connolly }; 145781bee695SCaleb Connolly }; 145881bee695SCaleb Connolly 145981bee695SCaleb Connolly qup_i2c19_default: qup-i2c19-default { 146081bee695SCaleb Connolly mux { 146181bee695SCaleb Connolly pins = "gpio57", "gpio58"; 146281bee695SCaleb Connolly function = "qup19"; 146381bee695SCaleb Connolly }; 146481bee695SCaleb Connolly 146581bee695SCaleb Connolly config { 146681bee695SCaleb Connolly pins = "gpio57", "gpio58"; 146781bee695SCaleb Connolly drive-strength = <0x02>; 146881bee695SCaleb Connolly bias-disable; 146981bee695SCaleb Connolly }; 147081bee695SCaleb Connolly }; 1471e13c6d14SVinod Koul }; 1472e13c6d14SVinod Koul 147349076351SSibi Sankar remoteproc_mpss: remoteproc@4080000 { 147449076351SSibi Sankar compatible = "qcom,sm8150-mpss-pas"; 147549076351SSibi Sankar reg = <0x0 0x04080000 0x0 0x4040>; 147649076351SSibi Sankar 147749076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 147849076351SSibi Sankar <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 147949076351SSibi Sankar <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 148049076351SSibi Sankar <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 148149076351SSibi Sankar <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 148249076351SSibi Sankar <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 148349076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", "handover", 148449076351SSibi Sankar "stop-ack", "shutdown-ack"; 148549076351SSibi Sankar 148649076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 148749076351SSibi Sankar clock-names = "xo"; 148849076351SSibi Sankar 148949076351SSibi Sankar power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, 1490d0770627SBjorn Andersson <&rpmhpd 7>, 1491d0770627SBjorn Andersson <&rpmhpd 0>; 149249076351SSibi Sankar power-domain-names = "load_state", "cx", "mss"; 149349076351SSibi Sankar 149449076351SSibi Sankar memory-region = <&mpss_mem>; 149549076351SSibi Sankar 149649076351SSibi Sankar qcom,smem-states = <&modem_smp2p_out 0>; 149749076351SSibi Sankar qcom,smem-state-names = "stop"; 149849076351SSibi Sankar 149949076351SSibi Sankar glink-edge { 150049076351SSibi Sankar interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 150149076351SSibi Sankar label = "modem"; 150249076351SSibi Sankar qcom,remote-pid = <1>; 150349076351SSibi Sankar mboxes = <&apss_shared 12>; 150449076351SSibi Sankar }; 150549076351SSibi Sankar }; 150649076351SSibi Sankar 150724244cefSSai Prakash Ranjan stm@6002000 { 150824244cefSSai Prakash Ranjan compatible = "arm,coresight-stm", "arm,primecell"; 150924244cefSSai Prakash Ranjan reg = <0 0x06002000 0 0x1000>, 151024244cefSSai Prakash Ranjan <0 0x16280000 0 0x180000>; 151124244cefSSai Prakash Ranjan reg-names = "stm-base", "stm-stimulus-base"; 151224244cefSSai Prakash Ranjan 151324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 151424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 151524244cefSSai Prakash Ranjan 151624244cefSSai Prakash Ranjan out-ports { 151724244cefSSai Prakash Ranjan port { 151824244cefSSai Prakash Ranjan stm_out: endpoint { 151924244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_in7>; 152024244cefSSai Prakash Ranjan }; 152124244cefSSai Prakash Ranjan }; 152224244cefSSai Prakash Ranjan }; 152324244cefSSai Prakash Ranjan }; 152424244cefSSai Prakash Ranjan 152524244cefSSai Prakash Ranjan funnel@6041000 { 152624244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 152724244cefSSai Prakash Ranjan reg = <0 0x06041000 0 0x1000>; 152824244cefSSai Prakash Ranjan 152924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 153024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 153124244cefSSai Prakash Ranjan 153224244cefSSai Prakash Ranjan out-ports { 153324244cefSSai Prakash Ranjan port { 153424244cefSSai Prakash Ranjan funnel0_out: endpoint { 153524244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in0>; 153624244cefSSai Prakash Ranjan }; 153724244cefSSai Prakash Ranjan }; 153824244cefSSai Prakash Ranjan }; 153924244cefSSai Prakash Ranjan 154024244cefSSai Prakash Ranjan in-ports { 154124244cefSSai Prakash Ranjan #address-cells = <1>; 154224244cefSSai Prakash Ranjan #size-cells = <0>; 154324244cefSSai Prakash Ranjan 154424244cefSSai Prakash Ranjan port@7 { 154524244cefSSai Prakash Ranjan reg = <7>; 154624244cefSSai Prakash Ranjan funnel0_in7: endpoint { 154724244cefSSai Prakash Ranjan remote-endpoint = <&stm_out>; 154824244cefSSai Prakash Ranjan }; 154924244cefSSai Prakash Ranjan }; 155024244cefSSai Prakash Ranjan }; 155124244cefSSai Prakash Ranjan }; 155224244cefSSai Prakash Ranjan 155324244cefSSai Prakash Ranjan funnel@6042000 { 155424244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 155524244cefSSai Prakash Ranjan reg = <0 0x06042000 0 0x1000>; 155624244cefSSai Prakash Ranjan 155724244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 155824244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 155924244cefSSai Prakash Ranjan 156024244cefSSai Prakash Ranjan out-ports { 156124244cefSSai Prakash Ranjan port { 156224244cefSSai Prakash Ranjan funnel1_out: endpoint { 156324244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in1>; 156424244cefSSai Prakash Ranjan }; 156524244cefSSai Prakash Ranjan }; 156624244cefSSai Prakash Ranjan }; 156724244cefSSai Prakash Ranjan 156824244cefSSai Prakash Ranjan in-ports { 156924244cefSSai Prakash Ranjan #address-cells = <1>; 157024244cefSSai Prakash Ranjan #size-cells = <0>; 157124244cefSSai Prakash Ranjan 157224244cefSSai Prakash Ranjan port@4 { 157324244cefSSai Prakash Ranjan reg = <4>; 157424244cefSSai Prakash Ranjan funnel1_in4: endpoint { 157524244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_out>; 157624244cefSSai Prakash Ranjan }; 157724244cefSSai Prakash Ranjan }; 157824244cefSSai Prakash Ranjan }; 157924244cefSSai Prakash Ranjan }; 158024244cefSSai Prakash Ranjan 158124244cefSSai Prakash Ranjan funnel@6043000 { 158224244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 158324244cefSSai Prakash Ranjan reg = <0 0x06043000 0 0x1000>; 158424244cefSSai Prakash Ranjan 158524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 158624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 158724244cefSSai Prakash Ranjan 158824244cefSSai Prakash Ranjan out-ports { 158924244cefSSai Prakash Ranjan port { 159024244cefSSai Prakash Ranjan funnel2_out: endpoint { 159124244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in2>; 159224244cefSSai Prakash Ranjan }; 159324244cefSSai Prakash Ranjan }; 159424244cefSSai Prakash Ranjan }; 159524244cefSSai Prakash Ranjan 159624244cefSSai Prakash Ranjan in-ports { 159724244cefSSai Prakash Ranjan #address-cells = <1>; 159824244cefSSai Prakash Ranjan #size-cells = <0>; 159924244cefSSai Prakash Ranjan 160024244cefSSai Prakash Ranjan port@2 { 160124244cefSSai Prakash Ranjan reg = <2>; 160224244cefSSai Prakash Ranjan funnel2_in2: endpoint { 160324244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_out>; 160424244cefSSai Prakash Ranjan }; 160524244cefSSai Prakash Ranjan }; 160624244cefSSai Prakash Ranjan }; 160724244cefSSai Prakash Ranjan }; 160824244cefSSai Prakash Ranjan 160924244cefSSai Prakash Ranjan funnel@6045000 { 161024244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 161124244cefSSai Prakash Ranjan reg = <0 0x06045000 0 0x1000>; 161224244cefSSai Prakash Ranjan 161324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 161424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 161524244cefSSai Prakash Ranjan 161624244cefSSai Prakash Ranjan out-ports { 161724244cefSSai Prakash Ranjan port { 161824244cefSSai Prakash Ranjan merge_funnel_out: endpoint { 161924244cefSSai Prakash Ranjan remote-endpoint = <&etf_in>; 162024244cefSSai Prakash Ranjan }; 162124244cefSSai Prakash Ranjan }; 162224244cefSSai Prakash Ranjan }; 162324244cefSSai Prakash Ranjan 162424244cefSSai Prakash Ranjan in-ports { 162524244cefSSai Prakash Ranjan #address-cells = <1>; 162624244cefSSai Prakash Ranjan #size-cells = <0>; 162724244cefSSai Prakash Ranjan 162824244cefSSai Prakash Ranjan port@0 { 162924244cefSSai Prakash Ranjan reg = <0>; 163024244cefSSai Prakash Ranjan merge_funnel_in0: endpoint { 163124244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_out>; 163224244cefSSai Prakash Ranjan }; 163324244cefSSai Prakash Ranjan }; 163424244cefSSai Prakash Ranjan 163524244cefSSai Prakash Ranjan port@1 { 163624244cefSSai Prakash Ranjan reg = <1>; 163724244cefSSai Prakash Ranjan merge_funnel_in1: endpoint { 163824244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_out>; 163924244cefSSai Prakash Ranjan }; 164024244cefSSai Prakash Ranjan }; 164124244cefSSai Prakash Ranjan 164224244cefSSai Prakash Ranjan port@2 { 164324244cefSSai Prakash Ranjan reg = <2>; 164424244cefSSai Prakash Ranjan merge_funnel_in2: endpoint { 164524244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_out>; 164624244cefSSai Prakash Ranjan }; 164724244cefSSai Prakash Ranjan }; 164824244cefSSai Prakash Ranjan }; 164924244cefSSai Prakash Ranjan }; 165024244cefSSai Prakash Ranjan 165124244cefSSai Prakash Ranjan replicator@6046000 { 165224244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 165324244cefSSai Prakash Ranjan reg = <0 0x06046000 0 0x1000>; 165424244cefSSai Prakash Ranjan 165524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 165624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 165724244cefSSai Prakash Ranjan 165824244cefSSai Prakash Ranjan out-ports { 165924244cefSSai Prakash Ranjan #address-cells = <1>; 166024244cefSSai Prakash Ranjan #size-cells = <0>; 166124244cefSSai Prakash Ranjan 166224244cefSSai Prakash Ranjan port@0 { 166324244cefSSai Prakash Ranjan reg = <0>; 166424244cefSSai Prakash Ranjan replicator_out0: endpoint { 166524244cefSSai Prakash Ranjan remote-endpoint = <&etr_in>; 166624244cefSSai Prakash Ranjan }; 166724244cefSSai Prakash Ranjan }; 166824244cefSSai Prakash Ranjan 166924244cefSSai Prakash Ranjan port@1 { 167024244cefSSai Prakash Ranjan reg = <1>; 167124244cefSSai Prakash Ranjan replicator_out1: endpoint { 167224244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_in>; 167324244cefSSai Prakash Ranjan }; 167424244cefSSai Prakash Ranjan }; 167524244cefSSai Prakash Ranjan }; 167624244cefSSai Prakash Ranjan 167724244cefSSai Prakash Ranjan in-ports { 167824244cefSSai Prakash Ranjan port { 167924244cefSSai Prakash Ranjan replicator_in0: endpoint { 168024244cefSSai Prakash Ranjan remote-endpoint = <&etf_out>; 168124244cefSSai Prakash Ranjan }; 168224244cefSSai Prakash Ranjan }; 168324244cefSSai Prakash Ranjan }; 168424244cefSSai Prakash Ranjan }; 168524244cefSSai Prakash Ranjan 168624244cefSSai Prakash Ranjan etf@6047000 { 168724244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 168824244cefSSai Prakash Ranjan reg = <0 0x06047000 0 0x1000>; 168924244cefSSai Prakash Ranjan 169024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 169124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 169224244cefSSai Prakash Ranjan 169324244cefSSai Prakash Ranjan out-ports { 169424244cefSSai Prakash Ranjan port { 169524244cefSSai Prakash Ranjan etf_out: endpoint { 169624244cefSSai Prakash Ranjan remote-endpoint = <&replicator_in0>; 169724244cefSSai Prakash Ranjan }; 169824244cefSSai Prakash Ranjan }; 169924244cefSSai Prakash Ranjan }; 170024244cefSSai Prakash Ranjan 170124244cefSSai Prakash Ranjan in-ports { 170224244cefSSai Prakash Ranjan port { 170324244cefSSai Prakash Ranjan etf_in: endpoint { 170424244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_out>; 170524244cefSSai Prakash Ranjan }; 170624244cefSSai Prakash Ranjan }; 170724244cefSSai Prakash Ranjan }; 170824244cefSSai Prakash Ranjan }; 170924244cefSSai Prakash Ranjan 171024244cefSSai Prakash Ranjan etr@6048000 { 171124244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 171224244cefSSai Prakash Ranjan reg = <0 0x06048000 0 0x1000>; 171324244cefSSai Prakash Ranjan iommus = <&apps_smmu 0x05e0 0x0>; 171424244cefSSai Prakash Ranjan 171524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 171624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 171724244cefSSai Prakash Ranjan arm,scatter-gather; 171824244cefSSai Prakash Ranjan 171924244cefSSai Prakash Ranjan in-ports { 172024244cefSSai Prakash Ranjan port { 172124244cefSSai Prakash Ranjan etr_in: endpoint { 172224244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out0>; 172324244cefSSai Prakash Ranjan }; 172424244cefSSai Prakash Ranjan }; 172524244cefSSai Prakash Ranjan }; 172624244cefSSai Prakash Ranjan }; 172724244cefSSai Prakash Ranjan 172824244cefSSai Prakash Ranjan replicator@604a000 { 172924244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 173024244cefSSai Prakash Ranjan reg = <0 0x0604a000 0 0x1000>; 173124244cefSSai Prakash Ranjan 173224244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 173324244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 173424244cefSSai Prakash Ranjan 173524244cefSSai Prakash Ranjan out-ports { 173624244cefSSai Prakash Ranjan #address-cells = <1>; 173724244cefSSai Prakash Ranjan #size-cells = <0>; 173824244cefSSai Prakash Ranjan 173924244cefSSai Prakash Ranjan port@1 { 174024244cefSSai Prakash Ranjan reg = <1>; 174124244cefSSai Prakash Ranjan replicator1_out: endpoint { 174224244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_in>; 174324244cefSSai Prakash Ranjan }; 174424244cefSSai Prakash Ranjan }; 174524244cefSSai Prakash Ranjan }; 174624244cefSSai Prakash Ranjan 174724244cefSSai Prakash Ranjan in-ports { 174824244cefSSai Prakash Ranjan #address-cells = <1>; 174924244cefSSai Prakash Ranjan #size-cells = <0>; 175024244cefSSai Prakash Ranjan 175124244cefSSai Prakash Ranjan port@1 { 175224244cefSSai Prakash Ranjan reg = <1>; 175324244cefSSai Prakash Ranjan replicator1_in: endpoint { 175424244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out1>; 175524244cefSSai Prakash Ranjan }; 175624244cefSSai Prakash Ranjan }; 175724244cefSSai Prakash Ranjan }; 175824244cefSSai Prakash Ranjan }; 175924244cefSSai Prakash Ranjan 176024244cefSSai Prakash Ranjan funnel@6b08000 { 176124244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 176224244cefSSai Prakash Ranjan reg = <0 0x06b08000 0 0x1000>; 176324244cefSSai Prakash Ranjan 176424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 176524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 176624244cefSSai Prakash Ranjan 176724244cefSSai Prakash Ranjan out-ports { 176824244cefSSai Prakash Ranjan port { 176924244cefSSai Prakash Ranjan swao_funnel_out: endpoint { 177024244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_in>; 177124244cefSSai Prakash Ranjan }; 177224244cefSSai Prakash Ranjan }; 177324244cefSSai Prakash Ranjan }; 177424244cefSSai Prakash Ranjan 177524244cefSSai Prakash Ranjan in-ports { 177624244cefSSai Prakash Ranjan #address-cells = <1>; 177724244cefSSai Prakash Ranjan #size-cells = <0>; 177824244cefSSai Prakash Ranjan 177924244cefSSai Prakash Ranjan port@6 { 178024244cefSSai Prakash Ranjan reg = <6>; 178124244cefSSai Prakash Ranjan swao_funnel_in: endpoint { 178224244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_out>; 178324244cefSSai Prakash Ranjan }; 178424244cefSSai Prakash Ranjan }; 178524244cefSSai Prakash Ranjan }; 178624244cefSSai Prakash Ranjan }; 178724244cefSSai Prakash Ranjan 178824244cefSSai Prakash Ranjan etf@6b09000 { 178924244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 179024244cefSSai Prakash Ranjan reg = <0 0x06b09000 0 0x1000>; 179124244cefSSai Prakash Ranjan 179224244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 179324244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 179424244cefSSai Prakash Ranjan 179524244cefSSai Prakash Ranjan out-ports { 179624244cefSSai Prakash Ranjan port { 179724244cefSSai Prakash Ranjan swao_etf_out: endpoint { 179824244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_in>; 179924244cefSSai Prakash Ranjan }; 180024244cefSSai Prakash Ranjan }; 180124244cefSSai Prakash Ranjan }; 180224244cefSSai Prakash Ranjan 180324244cefSSai Prakash Ranjan in-ports { 180424244cefSSai Prakash Ranjan port { 180524244cefSSai Prakash Ranjan swao_etf_in: endpoint { 180624244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_out>; 180724244cefSSai Prakash Ranjan }; 180824244cefSSai Prakash Ranjan }; 180924244cefSSai Prakash Ranjan }; 181024244cefSSai Prakash Ranjan }; 181124244cefSSai Prakash Ranjan 181224244cefSSai Prakash Ranjan replicator@6b0a000 { 181324244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 181424244cefSSai Prakash Ranjan reg = <0 0x06b0a000 0 0x1000>; 181524244cefSSai Prakash Ranjan 181624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 181724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 181824244cefSSai Prakash Ranjan qcom,replicator-loses-context; 181924244cefSSai Prakash Ranjan 182024244cefSSai Prakash Ranjan out-ports { 182124244cefSSai Prakash Ranjan port { 182224244cefSSai Prakash Ranjan swao_replicator_out: endpoint { 182324244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_in4>; 182424244cefSSai Prakash Ranjan }; 182524244cefSSai Prakash Ranjan }; 182624244cefSSai Prakash Ranjan }; 182724244cefSSai Prakash Ranjan 182824244cefSSai Prakash Ranjan in-ports { 182924244cefSSai Prakash Ranjan port { 183024244cefSSai Prakash Ranjan swao_replicator_in: endpoint { 183124244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_out>; 183224244cefSSai Prakash Ranjan }; 183324244cefSSai Prakash Ranjan }; 183424244cefSSai Prakash Ranjan }; 183524244cefSSai Prakash Ranjan }; 183624244cefSSai Prakash Ranjan 183724244cefSSai Prakash Ranjan etm@7040000 { 183824244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 183924244cefSSai Prakash Ranjan reg = <0 0x07040000 0 0x1000>; 184024244cefSSai Prakash Ranjan 184124244cefSSai Prakash Ranjan cpu = <&CPU0>; 184224244cefSSai Prakash Ranjan 184324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 184424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 184524244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 184624244cefSSai Prakash Ranjan qcom,skip-power-up; 184724244cefSSai Prakash Ranjan 184824244cefSSai Prakash Ranjan out-ports { 184924244cefSSai Prakash Ranjan port { 185024244cefSSai Prakash Ranjan etm0_out: endpoint { 185124244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in0>; 185224244cefSSai Prakash Ranjan }; 185324244cefSSai Prakash Ranjan }; 185424244cefSSai Prakash Ranjan }; 185524244cefSSai Prakash Ranjan }; 185624244cefSSai Prakash Ranjan 185724244cefSSai Prakash Ranjan etm@7140000 { 185824244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 185924244cefSSai Prakash Ranjan reg = <0 0x07140000 0 0x1000>; 186024244cefSSai Prakash Ranjan 186124244cefSSai Prakash Ranjan cpu = <&CPU1>; 186224244cefSSai Prakash Ranjan 186324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 186424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 186524244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 186624244cefSSai Prakash Ranjan qcom,skip-power-up; 186724244cefSSai Prakash Ranjan 186824244cefSSai Prakash Ranjan out-ports { 186924244cefSSai Prakash Ranjan port { 187024244cefSSai Prakash Ranjan etm1_out: endpoint { 187124244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in1>; 187224244cefSSai Prakash Ranjan }; 187324244cefSSai Prakash Ranjan }; 187424244cefSSai Prakash Ranjan }; 187524244cefSSai Prakash Ranjan }; 187624244cefSSai Prakash Ranjan 187724244cefSSai Prakash Ranjan etm@7240000 { 187824244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 187924244cefSSai Prakash Ranjan reg = <0 0x07240000 0 0x1000>; 188024244cefSSai Prakash Ranjan 188124244cefSSai Prakash Ranjan cpu = <&CPU2>; 188224244cefSSai Prakash Ranjan 188324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 188424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 188524244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 188624244cefSSai Prakash Ranjan qcom,skip-power-up; 188724244cefSSai Prakash Ranjan 188824244cefSSai Prakash Ranjan out-ports { 188924244cefSSai Prakash Ranjan port { 189024244cefSSai Prakash Ranjan etm2_out: endpoint { 189124244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in2>; 189224244cefSSai Prakash Ranjan }; 189324244cefSSai Prakash Ranjan }; 189424244cefSSai Prakash Ranjan }; 189524244cefSSai Prakash Ranjan }; 189624244cefSSai Prakash Ranjan 189724244cefSSai Prakash Ranjan etm@7340000 { 189824244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 189924244cefSSai Prakash Ranjan reg = <0 0x07340000 0 0x1000>; 190024244cefSSai Prakash Ranjan 190124244cefSSai Prakash Ranjan cpu = <&CPU3>; 190224244cefSSai Prakash Ranjan 190324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 190424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 190524244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 190624244cefSSai Prakash Ranjan qcom,skip-power-up; 190724244cefSSai Prakash Ranjan 190824244cefSSai Prakash Ranjan out-ports { 190924244cefSSai Prakash Ranjan port { 191024244cefSSai Prakash Ranjan etm3_out: endpoint { 191124244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in3>; 191224244cefSSai Prakash Ranjan }; 191324244cefSSai Prakash Ranjan }; 191424244cefSSai Prakash Ranjan }; 191524244cefSSai Prakash Ranjan }; 191624244cefSSai Prakash Ranjan 191724244cefSSai Prakash Ranjan etm@7440000 { 191824244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 191924244cefSSai Prakash Ranjan reg = <0 0x07440000 0 0x1000>; 192024244cefSSai Prakash Ranjan 192124244cefSSai Prakash Ranjan cpu = <&CPU4>; 192224244cefSSai Prakash Ranjan 192324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 192424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 192524244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 192624244cefSSai Prakash Ranjan qcom,skip-power-up; 192724244cefSSai Prakash Ranjan 192824244cefSSai Prakash Ranjan out-ports { 192924244cefSSai Prakash Ranjan port { 193024244cefSSai Prakash Ranjan etm4_out: endpoint { 193124244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in4>; 193224244cefSSai Prakash Ranjan }; 193324244cefSSai Prakash Ranjan }; 193424244cefSSai Prakash Ranjan }; 193524244cefSSai Prakash Ranjan }; 193624244cefSSai Prakash Ranjan 193724244cefSSai Prakash Ranjan etm@7540000 { 193824244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 193924244cefSSai Prakash Ranjan reg = <0 0x07540000 0 0x1000>; 194024244cefSSai Prakash Ranjan 194124244cefSSai Prakash Ranjan cpu = <&CPU5>; 194224244cefSSai Prakash Ranjan 194324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 194424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 194524244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 194624244cefSSai Prakash Ranjan qcom,skip-power-up; 194724244cefSSai Prakash Ranjan 194824244cefSSai Prakash Ranjan out-ports { 194924244cefSSai Prakash Ranjan port { 195024244cefSSai Prakash Ranjan etm5_out: endpoint { 195124244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in5>; 195224244cefSSai Prakash Ranjan }; 195324244cefSSai Prakash Ranjan }; 195424244cefSSai Prakash Ranjan }; 195524244cefSSai Prakash Ranjan }; 195624244cefSSai Prakash Ranjan 195724244cefSSai Prakash Ranjan etm@7640000 { 195824244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 195924244cefSSai Prakash Ranjan reg = <0 0x07640000 0 0x1000>; 196024244cefSSai Prakash Ranjan 196124244cefSSai Prakash Ranjan cpu = <&CPU6>; 196224244cefSSai Prakash Ranjan 196324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 196424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 196524244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 196624244cefSSai Prakash Ranjan qcom,skip-power-up; 196724244cefSSai Prakash Ranjan 196824244cefSSai Prakash Ranjan out-ports { 196924244cefSSai Prakash Ranjan port { 197024244cefSSai Prakash Ranjan etm6_out: endpoint { 197124244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in6>; 197224244cefSSai Prakash Ranjan }; 197324244cefSSai Prakash Ranjan }; 197424244cefSSai Prakash Ranjan }; 197524244cefSSai Prakash Ranjan }; 197624244cefSSai Prakash Ranjan 197724244cefSSai Prakash Ranjan etm@7740000 { 197824244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 197924244cefSSai Prakash Ranjan reg = <0 0x07740000 0 0x1000>; 198024244cefSSai Prakash Ranjan 198124244cefSSai Prakash Ranjan cpu = <&CPU7>; 198224244cefSSai Prakash Ranjan 198324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 198424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 198524244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 198624244cefSSai Prakash Ranjan qcom,skip-power-up; 198724244cefSSai Prakash Ranjan 198824244cefSSai Prakash Ranjan out-ports { 198924244cefSSai Prakash Ranjan port { 199024244cefSSai Prakash Ranjan etm7_out: endpoint { 199124244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in7>; 199224244cefSSai Prakash Ranjan }; 199324244cefSSai Prakash Ranjan }; 199424244cefSSai Prakash Ranjan }; 199524244cefSSai Prakash Ranjan }; 199624244cefSSai Prakash Ranjan 199724244cefSSai Prakash Ranjan funnel@7800000 { /* APSS Funnel */ 199824244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 199924244cefSSai Prakash Ranjan reg = <0 0x07800000 0 0x1000>; 200024244cefSSai Prakash Ranjan 200124244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 200224244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 200324244cefSSai Prakash Ranjan 200424244cefSSai Prakash Ranjan out-ports { 200524244cefSSai Prakash Ranjan port { 200624244cefSSai Prakash Ranjan apss_funnel_out: endpoint { 200724244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_in>; 200824244cefSSai Prakash Ranjan }; 200924244cefSSai Prakash Ranjan }; 201024244cefSSai Prakash Ranjan }; 201124244cefSSai Prakash Ranjan 201224244cefSSai Prakash Ranjan in-ports { 201324244cefSSai Prakash Ranjan #address-cells = <1>; 201424244cefSSai Prakash Ranjan #size-cells = <0>; 201524244cefSSai Prakash Ranjan 201624244cefSSai Prakash Ranjan port@0 { 201724244cefSSai Prakash Ranjan reg = <0>; 201824244cefSSai Prakash Ranjan apss_funnel_in0: endpoint { 201924244cefSSai Prakash Ranjan remote-endpoint = <&etm0_out>; 202024244cefSSai Prakash Ranjan }; 202124244cefSSai Prakash Ranjan }; 202224244cefSSai Prakash Ranjan 202324244cefSSai Prakash Ranjan port@1 { 202424244cefSSai Prakash Ranjan reg = <1>; 202524244cefSSai Prakash Ranjan apss_funnel_in1: endpoint { 202624244cefSSai Prakash Ranjan remote-endpoint = <&etm1_out>; 202724244cefSSai Prakash Ranjan }; 202824244cefSSai Prakash Ranjan }; 202924244cefSSai Prakash Ranjan 203024244cefSSai Prakash Ranjan port@2 { 203124244cefSSai Prakash Ranjan reg = <2>; 203224244cefSSai Prakash Ranjan apss_funnel_in2: endpoint { 203324244cefSSai Prakash Ranjan remote-endpoint = <&etm2_out>; 203424244cefSSai Prakash Ranjan }; 203524244cefSSai Prakash Ranjan }; 203624244cefSSai Prakash Ranjan 203724244cefSSai Prakash Ranjan port@3 { 203824244cefSSai Prakash Ranjan reg = <3>; 203924244cefSSai Prakash Ranjan apss_funnel_in3: endpoint { 204024244cefSSai Prakash Ranjan remote-endpoint = <&etm3_out>; 204124244cefSSai Prakash Ranjan }; 204224244cefSSai Prakash Ranjan }; 204324244cefSSai Prakash Ranjan 204424244cefSSai Prakash Ranjan port@4 { 204524244cefSSai Prakash Ranjan reg = <4>; 204624244cefSSai Prakash Ranjan apss_funnel_in4: endpoint { 204724244cefSSai Prakash Ranjan remote-endpoint = <&etm4_out>; 204824244cefSSai Prakash Ranjan }; 204924244cefSSai Prakash Ranjan }; 205024244cefSSai Prakash Ranjan 205124244cefSSai Prakash Ranjan port@5 { 205224244cefSSai Prakash Ranjan reg = <5>; 205324244cefSSai Prakash Ranjan apss_funnel_in5: endpoint { 205424244cefSSai Prakash Ranjan remote-endpoint = <&etm5_out>; 205524244cefSSai Prakash Ranjan }; 205624244cefSSai Prakash Ranjan }; 205724244cefSSai Prakash Ranjan 205824244cefSSai Prakash Ranjan port@6 { 205924244cefSSai Prakash Ranjan reg = <6>; 206024244cefSSai Prakash Ranjan apss_funnel_in6: endpoint { 206124244cefSSai Prakash Ranjan remote-endpoint = <&etm6_out>; 206224244cefSSai Prakash Ranjan }; 206324244cefSSai Prakash Ranjan }; 206424244cefSSai Prakash Ranjan 206524244cefSSai Prakash Ranjan port@7 { 206624244cefSSai Prakash Ranjan reg = <7>; 206724244cefSSai Prakash Ranjan apss_funnel_in7: endpoint { 206824244cefSSai Prakash Ranjan remote-endpoint = <&etm7_out>; 206924244cefSSai Prakash Ranjan }; 207024244cefSSai Prakash Ranjan }; 207124244cefSSai Prakash Ranjan }; 207224244cefSSai Prakash Ranjan }; 207324244cefSSai Prakash Ranjan 207424244cefSSai Prakash Ranjan funnel@7810000 { 207524244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 207624244cefSSai Prakash Ranjan reg = <0 0x07810000 0 0x1000>; 207724244cefSSai Prakash Ranjan 207824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 207924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 208024244cefSSai Prakash Ranjan 208124244cefSSai Prakash Ranjan out-ports { 208224244cefSSai Prakash Ranjan port { 208324244cefSSai Prakash Ranjan apss_merge_funnel_out: endpoint { 208424244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_in2>; 208524244cefSSai Prakash Ranjan }; 208624244cefSSai Prakash Ranjan }; 208724244cefSSai Prakash Ranjan }; 208824244cefSSai Prakash Ranjan 208924244cefSSai Prakash Ranjan in-ports { 209024244cefSSai Prakash Ranjan port { 209124244cefSSai Prakash Ranjan apss_merge_funnel_in: endpoint { 209224244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_out>; 209324244cefSSai Prakash Ranjan }; 209424244cefSSai Prakash Ranjan }; 209524244cefSSai Prakash Ranjan }; 209624244cefSSai Prakash Ranjan }; 209724244cefSSai Prakash Ranjan 209849076351SSibi Sankar remoteproc_cdsp: remoteproc@8300000 { 209949076351SSibi Sankar compatible = "qcom,sm8150-cdsp-pas"; 210049076351SSibi Sankar reg = <0x0 0x08300000 0x0 0x4040>; 210149076351SSibi Sankar 210249076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 210349076351SSibi Sankar <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 210449076351SSibi Sankar <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 210549076351SSibi Sankar <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 210649076351SSibi Sankar <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 210749076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 210849076351SSibi Sankar "handover", "stop-ack"; 210949076351SSibi Sankar 211049076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 211149076351SSibi Sankar clock-names = "xo"; 211249076351SSibi Sankar 211349076351SSibi Sankar power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, 2114d0770627SBjorn Andersson <&rpmhpd 7>; 211549076351SSibi Sankar power-domain-names = "load_state", "cx"; 211649076351SSibi Sankar 211749076351SSibi Sankar memory-region = <&cdsp_mem>; 211849076351SSibi Sankar 211949076351SSibi Sankar qcom,smem-states = <&cdsp_smp2p_out 0>; 212049076351SSibi Sankar qcom,smem-state-names = "stop"; 212149076351SSibi Sankar 212249076351SSibi Sankar status = "disabled"; 212349076351SSibi Sankar 212449076351SSibi Sankar glink-edge { 212549076351SSibi Sankar interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 212649076351SSibi Sankar label = "cdsp"; 212749076351SSibi Sankar qcom,remote-pid = <5>; 212849076351SSibi Sankar mboxes = <&apss_shared 4>; 212949076351SSibi Sankar }; 213049076351SSibi Sankar }; 213149076351SSibi Sankar 2132b33d2868SJack Pham usb_1_hsphy: phy@88e2000 { 2133b33d2868SJack Pham compatible = "qcom,sm8150-usb-hs-phy", 2134b33d2868SJack Pham "qcom,usb-snps-hs-7nm-phy"; 2135b33d2868SJack Pham reg = <0 0x088e2000 0 0x400>; 2136b33d2868SJack Pham status = "disabled"; 2137b33d2868SJack Pham #phy-cells = <0>; 2138b33d2868SJack Pham 2139b33d2868SJack Pham clocks = <&rpmhcc RPMH_CXO_CLK>; 2140b33d2868SJack Pham clock-names = "ref"; 2141b33d2868SJack Pham 2142b33d2868SJack Pham resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2143b33d2868SJack Pham }; 2144b33d2868SJack Pham 21450c9dde0dSJonathan Marek usb_2_hsphy: phy@88e3000 { 21460c9dde0dSJonathan Marek compatible = "qcom,sm8150-usb-hs-phy", 21470c9dde0dSJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 21480c9dde0dSJonathan Marek reg = <0 0x088e3000 0 0x400>; 21490c9dde0dSJonathan Marek status = "disabled"; 21500c9dde0dSJonathan Marek #phy-cells = <0>; 21510c9dde0dSJonathan Marek 21520c9dde0dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 21530c9dde0dSJonathan Marek clock-names = "ref"; 21540c9dde0dSJonathan Marek 21550c9dde0dSJonathan Marek resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 21560c9dde0dSJonathan Marek }; 21570c9dde0dSJonathan Marek 2158b33d2868SJack Pham usb_1_qmpphy: phy@88e9000 { 2159b33d2868SJack Pham compatible = "qcom,sm8150-qmp-usb3-phy"; 2160b33d2868SJack Pham reg = <0 0x088e9000 0 0x18c>, 2161b33d2868SJack Pham <0 0x088e8000 0 0x10>; 2162b33d2868SJack Pham reg-names = "reg-base", "dp_com"; 2163b33d2868SJack Pham status = "disabled"; 2164b33d2868SJack Pham #address-cells = <2>; 2165b33d2868SJack Pham #size-cells = <2>; 2166b33d2868SJack Pham ranges; 2167b33d2868SJack Pham 2168b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2169b33d2868SJack Pham <&rpmhcc RPMH_CXO_CLK>, 2170b33d2868SJack Pham <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2171b33d2868SJack Pham <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2172b33d2868SJack Pham clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2173b33d2868SJack Pham 2174b33d2868SJack Pham resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2175b33d2868SJack Pham <&gcc GCC_USB3_PHY_PRIM_BCR>; 2176b33d2868SJack Pham reset-names = "phy", "common"; 2177b33d2868SJack Pham 2178b33d2868SJack Pham usb_1_ssphy: lanes@88e9200 { 2179b33d2868SJack Pham reg = <0 0x088e9200 0 0x200>, 2180b33d2868SJack Pham <0 0x088e9400 0 0x200>, 2181b33d2868SJack Pham <0 0x088e9c00 0 0x218>, 2182b33d2868SJack Pham <0 0x088e9600 0 0x200>, 2183b33d2868SJack Pham <0 0x088e9800 0 0x200>, 2184b33d2868SJack Pham <0 0x088e9a00 0 0x100>; 2185*7178d4ccSJonathan Marek #clock-cells = <0>; 2186b33d2868SJack Pham #phy-cells = <0>; 2187b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2188b33d2868SJack Pham clock-names = "pipe0"; 2189b33d2868SJack Pham clock-output-names = "usb3_phy_pipe_clk_src"; 2190b33d2868SJack Pham }; 2191b33d2868SJack Pham }; 2192b33d2868SJack Pham 219371a2fc6eSJonathan Marek dc_noc: interconnect@9160000 { 219471a2fc6eSJonathan Marek compatible = "qcom,sm8150-dc-noc"; 219571a2fc6eSJonathan Marek reg = <0 0x09160000 0 0x3200>; 219671a2fc6eSJonathan Marek #interconnect-cells = <1>; 219771a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 219871a2fc6eSJonathan Marek }; 219971a2fc6eSJonathan Marek 220071a2fc6eSJonathan Marek gem_noc: interconnect@9680000 { 220171a2fc6eSJonathan Marek compatible = "qcom,sm8150-gem-noc"; 220271a2fc6eSJonathan Marek reg = <0 0x09680000 0 0x3e200>; 220371a2fc6eSJonathan Marek #interconnect-cells = <1>; 220471a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 220571a2fc6eSJonathan Marek }; 220671a2fc6eSJonathan Marek 22070c9dde0dSJonathan Marek usb_2_qmpphy: phy@88eb000 { 22080c9dde0dSJonathan Marek compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 22090c9dde0dSJonathan Marek reg = <0 0x088eb000 0 0x200>; 22100c9dde0dSJonathan Marek status = "disabled"; 22110c9dde0dSJonathan Marek #address-cells = <2>; 22120c9dde0dSJonathan Marek #size-cells = <2>; 22130c9dde0dSJonathan Marek ranges; 22140c9dde0dSJonathan Marek 22150c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 22160c9dde0dSJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 22170c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>, 22180c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 22190c9dde0dSJonathan Marek clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 22200c9dde0dSJonathan Marek 22210c9dde0dSJonathan Marek resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 22220c9dde0dSJonathan Marek <&gcc GCC_USB3_PHY_SEC_BCR>; 22230c9dde0dSJonathan Marek reset-names = "phy", "common"; 22240c9dde0dSJonathan Marek 22250c9dde0dSJonathan Marek usb_2_ssphy: lane@88eb200 { 22260c9dde0dSJonathan Marek reg = <0 0x088eb200 0 0x200>, 22270c9dde0dSJonathan Marek <0 0x088eb400 0 0x200>, 22280c9dde0dSJonathan Marek <0 0x088eb800 0 0x800>, 22290c9dde0dSJonathan Marek <0 0x088eb600 0 0x200>; 2230*7178d4ccSJonathan Marek #clock-cells = <0>; 22310c9dde0dSJonathan Marek #phy-cells = <0>; 22320c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 22330c9dde0dSJonathan Marek clock-names = "pipe0"; 22340c9dde0dSJonathan Marek clock-output-names = "usb3_uni_phy_pipe_clk_src"; 22350c9dde0dSJonathan Marek }; 22360c9dde0dSJonathan Marek }; 22370c9dde0dSJonathan Marek 2238b33d2868SJack Pham usb_1: usb@a6f8800 { 2239b33d2868SJack Pham compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 2240b33d2868SJack Pham reg = <0 0x0a6f8800 0 0x400>; 2241b33d2868SJack Pham status = "disabled"; 2242b33d2868SJack Pham #address-cells = <2>; 2243b33d2868SJack Pham #size-cells = <2>; 2244b33d2868SJack Pham ranges; 2245b33d2868SJack Pham dma-ranges; 2246b33d2868SJack Pham 2247b33d2868SJack Pham clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2248b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2249b33d2868SJack Pham <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2250b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2251b33d2868SJack Pham <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2252b33d2868SJack Pham <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2253b33d2868SJack Pham clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2254b33d2868SJack Pham "sleep", "xo"; 2255b33d2868SJack Pham 2256b33d2868SJack Pham assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2257b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>; 225879493db5SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 2259b33d2868SJack Pham 2260b33d2868SJack Pham interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2261b33d2868SJack Pham <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 2262b33d2868SJack Pham <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 2263b33d2868SJack Pham <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 2264b33d2868SJack Pham interrupt-names = "hs_phy_irq", "ss_phy_irq", 2265b33d2868SJack Pham "dm_hs_phy_irq", "dp_hs_phy_irq"; 2266b33d2868SJack Pham 2267b33d2868SJack Pham power-domains = <&gcc USB30_PRIM_GDSC>; 2268b33d2868SJack Pham 2269b33d2868SJack Pham resets = <&gcc GCC_USB30_PRIM_BCR>; 2270b33d2868SJack Pham 2271b33d2868SJack Pham usb_1_dwc3: dwc3@a600000 { 2272b33d2868SJack Pham compatible = "snps,dwc3"; 2273b33d2868SJack Pham reg = <0 0x0a600000 0 0xcd00>; 2274b33d2868SJack Pham interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 227548156232SJonathan Marek iommus = <&apps_smmu 0x140 0>; 2276b33d2868SJack Pham snps,dis_u2_susphy_quirk; 2277b33d2868SJack Pham snps,dis_enblslpm_quirk; 2278b33d2868SJack Pham phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2279b33d2868SJack Pham phy-names = "usb2-phy", "usb3-phy"; 2280b33d2868SJack Pham }; 2281b33d2868SJack Pham }; 2282b33d2868SJack Pham 22830c9dde0dSJonathan Marek usb_2: usb@a8f8800 { 22840c9dde0dSJonathan Marek compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 22850c9dde0dSJonathan Marek reg = <0 0x0a8f8800 0 0x400>; 22860c9dde0dSJonathan Marek status = "disabled"; 22870c9dde0dSJonathan Marek #address-cells = <2>; 22880c9dde0dSJonathan Marek #size-cells = <2>; 22890c9dde0dSJonathan Marek ranges; 22900c9dde0dSJonathan Marek dma-ranges; 22910c9dde0dSJonathan Marek 22920c9dde0dSJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 22930c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>, 22940c9dde0dSJonathan Marek <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 22950c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 22960c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_SLEEP_CLK>, 22970c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>; 22980c9dde0dSJonathan Marek clock-names = "cfg_noc", "core", "iface", "mock_utmi", 22990c9dde0dSJonathan Marek "sleep", "xo"; 23000c9dde0dSJonathan Marek 23010c9dde0dSJonathan Marek assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 23020c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>; 23030c9dde0dSJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 23040c9dde0dSJonathan Marek 23050c9dde0dSJonathan Marek interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 23060c9dde0dSJonathan Marek <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 23070c9dde0dSJonathan Marek <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 23080c9dde0dSJonathan Marek <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 23090c9dde0dSJonathan Marek interrupt-names = "hs_phy_irq", "ss_phy_irq", 23100c9dde0dSJonathan Marek "dm_hs_phy_irq", "dp_hs_phy_irq"; 23110c9dde0dSJonathan Marek 23120c9dde0dSJonathan Marek power-domains = <&gcc USB30_SEC_GDSC>; 23130c9dde0dSJonathan Marek 23140c9dde0dSJonathan Marek resets = <&gcc GCC_USB30_SEC_BCR>; 23150c9dde0dSJonathan Marek 23160c9dde0dSJonathan Marek usb_2_dwc3: dwc3@a800000 { 23170c9dde0dSJonathan Marek compatible = "snps,dwc3"; 23180c9dde0dSJonathan Marek reg = <0 0x0a800000 0 0xcd00>; 23190c9dde0dSJonathan Marek interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 23200c9dde0dSJonathan Marek iommus = <&apps_smmu 0x160 0>; 23210c9dde0dSJonathan Marek snps,dis_u2_susphy_quirk; 23220c9dde0dSJonathan Marek snps,dis_enblslpm_quirk; 23230c9dde0dSJonathan Marek phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 23240c9dde0dSJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 23250c9dde0dSJonathan Marek }; 23260c9dde0dSJonathan Marek }; 23270c9dde0dSJonathan Marek 23286acb71fdSJonathan Marek camnoc_virt: interconnect@ac00000 { 23296acb71fdSJonathan Marek compatible = "qcom,sm8150-camnoc-virt"; 23306acb71fdSJonathan Marek reg = <0 0x0ac00000 0 0x1000>; 23316acb71fdSJonathan Marek #interconnect-cells = <1>; 23326acb71fdSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 23336acb71fdSJonathan Marek }; 23346acb71fdSJonathan Marek 2335d8cf9372SVinod Koul aoss_qmp: power-controller@c300000 { 2336d8cf9372SVinod Koul compatible = "qcom,sm8150-aoss-qmp"; 2337d8cf9372SVinod Koul reg = <0x0 0x0c300000 0x0 0x100000>; 2338d8cf9372SVinod Koul interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 2339d8cf9372SVinod Koul mboxes = <&apss_shared 0>; 2340d8cf9372SVinod Koul 2341d8cf9372SVinod Koul #clock-cells = <0>; 2342d8cf9372SVinod Koul #power-domain-cells = <1>; 2343d8cf9372SVinod Koul }; 2344d8cf9372SVinod Koul 2345d2fa630cSAmit Kucheria tsens0: thermal-sensor@c263000 { 2346d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 2347d2fa630cSAmit Kucheria reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2348d2fa630cSAmit Kucheria <0 0x0c222000 0 0x1ff>; /* SROT */ 2349d2fa630cSAmit Kucheria #qcom,sensors = <16>; 2350d2fa630cSAmit Kucheria interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2351d2fa630cSAmit Kucheria <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2352d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 2353d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 2354d2fa630cSAmit Kucheria }; 2355d2fa630cSAmit Kucheria 2356d2fa630cSAmit Kucheria tsens1: thermal-sensor@c265000 { 2357d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 2358d2fa630cSAmit Kucheria reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2359d2fa630cSAmit Kucheria <0 0x0c223000 0 0x1ff>; /* SROT */ 2360d2fa630cSAmit Kucheria #qcom,sensors = <8>; 2361d2fa630cSAmit Kucheria interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2362d2fa630cSAmit Kucheria <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2363d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 2364d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 2365d2fa630cSAmit Kucheria }; 2366d2fa630cSAmit Kucheria 2367e13c6d14SVinod Koul spmi_bus: spmi@c440000 { 2368e13c6d14SVinod Koul compatible = "qcom,spmi-pmic-arb"; 2369e13c6d14SVinod Koul reg = <0x0 0x0c440000 0x0 0x0001100>, 2370e13c6d14SVinod Koul <0x0 0x0c600000 0x0 0x2000000>, 2371e13c6d14SVinod Koul <0x0 0x0e600000 0x0 0x0100000>, 2372e13c6d14SVinod Koul <0x0 0x0e700000 0x0 0x00a0000>, 2373e13c6d14SVinod Koul <0x0 0x0c40a000 0x0 0x0026000>; 2374e13c6d14SVinod Koul reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2375e13c6d14SVinod Koul interrupt-names = "periph_irq"; 2376e13c6d14SVinod Koul interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 2377e13c6d14SVinod Koul qcom,ee = <0>; 2378e13c6d14SVinod Koul qcom,channel = <0>; 2379e13c6d14SVinod Koul #address-cells = <2>; 2380e13c6d14SVinod Koul #size-cells = <0>; 2381e13c6d14SVinod Koul interrupt-controller; 2382e13c6d14SVinod Koul #interrupt-cells = <4>; 2383e13c6d14SVinod Koul cell-index = <0>; 2384e13c6d14SVinod Koul }; 2385e13c6d14SVinod Koul 238648156232SJonathan Marek apps_smmu: iommu@15000000 { 238748156232SJonathan Marek compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 238848156232SJonathan Marek reg = <0 0x15000000 0 0x100000>; 238948156232SJonathan Marek #iommu-cells = <2>; 239048156232SJonathan Marek #global-interrupts = <1>; 239148156232SJonathan Marek interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 239248156232SJonathan Marek <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 239348156232SJonathan Marek <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 239448156232SJonathan Marek <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 239548156232SJonathan Marek <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 239648156232SJonathan Marek <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 239748156232SJonathan Marek <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 239848156232SJonathan Marek <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 239948156232SJonathan Marek <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 240048156232SJonathan Marek <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 240148156232SJonathan Marek <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 240248156232SJonathan Marek <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 240348156232SJonathan Marek <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 240448156232SJonathan Marek <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 240548156232SJonathan Marek <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 240648156232SJonathan Marek <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 240748156232SJonathan Marek <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 240848156232SJonathan Marek <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 240948156232SJonathan Marek <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 241048156232SJonathan Marek <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 241148156232SJonathan Marek <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 241248156232SJonathan Marek <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 241348156232SJonathan Marek <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 241448156232SJonathan Marek <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 241548156232SJonathan Marek <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 241648156232SJonathan Marek <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 241748156232SJonathan Marek <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 241848156232SJonathan Marek <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 241948156232SJonathan Marek <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 242048156232SJonathan Marek <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 242148156232SJonathan Marek <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 242248156232SJonathan Marek <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 242348156232SJonathan Marek <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 242448156232SJonathan Marek <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 242548156232SJonathan Marek <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 242648156232SJonathan Marek <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 242748156232SJonathan Marek <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 242848156232SJonathan Marek <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 242948156232SJonathan Marek <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 243048156232SJonathan Marek <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 243148156232SJonathan Marek <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 243248156232SJonathan Marek <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 243348156232SJonathan Marek <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 243448156232SJonathan Marek <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 243548156232SJonathan Marek <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 243648156232SJonathan Marek <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 243748156232SJonathan Marek <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 243848156232SJonathan Marek <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 243948156232SJonathan Marek <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 244048156232SJonathan Marek <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 244148156232SJonathan Marek <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 244248156232SJonathan Marek <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 244348156232SJonathan Marek <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 244448156232SJonathan Marek <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 244548156232SJonathan Marek <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 244648156232SJonathan Marek <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 244748156232SJonathan Marek <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 244848156232SJonathan Marek <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 244948156232SJonathan Marek <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 245048156232SJonathan Marek <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 245148156232SJonathan Marek <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 245248156232SJonathan Marek <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 245348156232SJonathan Marek <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 245448156232SJonathan Marek <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 245548156232SJonathan Marek <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 245648156232SJonathan Marek <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 245748156232SJonathan Marek <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 245848156232SJonathan Marek <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 245948156232SJonathan Marek <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 246048156232SJonathan Marek <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 246148156232SJonathan Marek <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 246248156232SJonathan Marek <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 246348156232SJonathan Marek <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 246448156232SJonathan Marek <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 246548156232SJonathan Marek <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 246648156232SJonathan Marek <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 246748156232SJonathan Marek <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 246848156232SJonathan Marek <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 246948156232SJonathan Marek <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 247048156232SJonathan Marek <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 247148156232SJonathan Marek <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 247248156232SJonathan Marek }; 247348156232SJonathan Marek 247449076351SSibi Sankar remoteproc_adsp: remoteproc@17300000 { 247549076351SSibi Sankar compatible = "qcom,sm8150-adsp-pas"; 247649076351SSibi Sankar reg = <0x0 0x17300000 0x0 0x4040>; 247749076351SSibi Sankar 247849076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 247949076351SSibi Sankar <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 248049076351SSibi Sankar <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 248149076351SSibi Sankar <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 248249076351SSibi Sankar <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 248349076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 248449076351SSibi Sankar "handover", "stop-ack"; 248549076351SSibi Sankar 248649076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 248749076351SSibi Sankar clock-names = "xo"; 248849076351SSibi Sankar 248949076351SSibi Sankar power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, 2490d0770627SBjorn Andersson <&rpmhpd 7>; 249149076351SSibi Sankar power-domain-names = "load_state", "cx"; 249249076351SSibi Sankar 249349076351SSibi Sankar memory-region = <&adsp_mem>; 249449076351SSibi Sankar 249549076351SSibi Sankar qcom,smem-states = <&adsp_smp2p_out 0>; 249649076351SSibi Sankar qcom,smem-state-names = "stop"; 249749076351SSibi Sankar 249849076351SSibi Sankar status = "disabled"; 249949076351SSibi Sankar 250049076351SSibi Sankar glink-edge { 250149076351SSibi Sankar interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 250249076351SSibi Sankar label = "lpass"; 250349076351SSibi Sankar qcom,remote-pid = <2>; 250449076351SSibi Sankar mboxes = <&apss_shared 8>; 250549076351SSibi Sankar }; 250649076351SSibi Sankar }; 250749076351SSibi Sankar 2508e13c6d14SVinod Koul intc: interrupt-controller@17a00000 { 2509e13c6d14SVinod Koul compatible = "arm,gic-v3"; 2510e13c6d14SVinod Koul interrupt-controller; 2511e13c6d14SVinod Koul #interrupt-cells = <3>; 2512e13c6d14SVinod Koul reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 2513e13c6d14SVinod Koul <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 2514e13c6d14SVinod Koul interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2515e13c6d14SVinod Koul }; 2516e13c6d14SVinod Koul 2517d8cf9372SVinod Koul apss_shared: mailbox@17c00000 { 2518d8cf9372SVinod Koul compatible = "qcom,sm8150-apss-shared"; 2519d8cf9372SVinod Koul reg = <0x0 0x17c00000 0x0 0x1000>; 2520d8cf9372SVinod Koul #mbox-cells = <1>; 2521d8cf9372SVinod Koul }; 2522d8cf9372SVinod Koul 2523fb2d8150SSai Prakash Ranjan watchdog@17c10000 { 2524fb2d8150SSai Prakash Ranjan compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 2525fb2d8150SSai Prakash Ranjan reg = <0 0x17c10000 0 0x1000>; 2526fb2d8150SSai Prakash Ranjan clocks = <&sleep_clk>; 2527b094c8f8SSai Prakash Ranjan interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 2528fb2d8150SSai Prakash Ranjan }; 2529fb2d8150SSai Prakash Ranjan 2530e13c6d14SVinod Koul timer@17c20000 { 2531e13c6d14SVinod Koul #address-cells = <2>; 2532e13c6d14SVinod Koul #size-cells = <2>; 2533e13c6d14SVinod Koul ranges; 2534e13c6d14SVinod Koul compatible = "arm,armv7-timer-mem"; 2535e13c6d14SVinod Koul reg = <0x0 0x17c20000 0x0 0x1000>; 2536e13c6d14SVinod Koul clock-frequency = <19200000>; 2537e13c6d14SVinod Koul 2538e13c6d14SVinod Koul frame@17c21000{ 2539e13c6d14SVinod Koul frame-number = <0>; 2540e13c6d14SVinod Koul interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2541e13c6d14SVinod Koul <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2542e13c6d14SVinod Koul reg = <0x0 0x17c21000 0x0 0x1000>, 2543e13c6d14SVinod Koul <0x0 0x17c22000 0x0 0x1000>; 2544e13c6d14SVinod Koul }; 2545e13c6d14SVinod Koul 2546e13c6d14SVinod Koul frame@17c23000 { 2547e13c6d14SVinod Koul frame-number = <1>; 2548e13c6d14SVinod Koul interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2549e13c6d14SVinod Koul reg = <0x0 0x17c23000 0x0 0x1000>; 2550e13c6d14SVinod Koul status = "disabled"; 2551e13c6d14SVinod Koul }; 2552e13c6d14SVinod Koul 2553e13c6d14SVinod Koul frame@17c25000 { 2554e13c6d14SVinod Koul frame-number = <2>; 2555e13c6d14SVinod Koul interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2556e13c6d14SVinod Koul reg = <0x0 0x17c25000 0x0 0x1000>; 2557e13c6d14SVinod Koul status = "disabled"; 2558e13c6d14SVinod Koul }; 2559e13c6d14SVinod Koul 2560e13c6d14SVinod Koul frame@17c27000 { 2561e13c6d14SVinod Koul frame-number = <3>; 2562e13c6d14SVinod Koul interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2563e13c6d14SVinod Koul reg = <0x0 0x17c26000 0x0 0x1000>; 2564e13c6d14SVinod Koul status = "disabled"; 2565e13c6d14SVinod Koul }; 2566e13c6d14SVinod Koul 2567e13c6d14SVinod Koul frame@17c29000 { 2568e13c6d14SVinod Koul frame-number = <4>; 2569e13c6d14SVinod Koul interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2570e13c6d14SVinod Koul reg = <0x0 0x17c29000 0x0 0x1000>; 2571e13c6d14SVinod Koul status = "disabled"; 2572e13c6d14SVinod Koul }; 2573e13c6d14SVinod Koul 2574e13c6d14SVinod Koul frame@17c2b000 { 2575e13c6d14SVinod Koul frame-number = <5>; 2576e13c6d14SVinod Koul interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2577e13c6d14SVinod Koul reg = <0x0 0x17c2b000 0x0 0x1000>; 2578e13c6d14SVinod Koul status = "disabled"; 2579e13c6d14SVinod Koul }; 2580e13c6d14SVinod Koul 2581e13c6d14SVinod Koul frame@17c2d000 { 2582e13c6d14SVinod Koul frame-number = <6>; 2583e13c6d14SVinod Koul interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2584e13c6d14SVinod Koul reg = <0x0 0x17c2d000 0x0 0x1000>; 2585e13c6d14SVinod Koul status = "disabled"; 2586e13c6d14SVinod Koul }; 2587e13c6d14SVinod Koul }; 2588d8cf9372SVinod Koul 2589d8cf9372SVinod Koul apps_rsc: rsc@18200000 { 2590d8cf9372SVinod Koul label = "apps_rsc"; 2591d8cf9372SVinod Koul compatible = "qcom,rpmh-rsc"; 2592d8cf9372SVinod Koul reg = <0x0 0x18200000 0x0 0x10000>, 2593d8cf9372SVinod Koul <0x0 0x18210000 0x0 0x10000>, 2594d8cf9372SVinod Koul <0x0 0x18220000 0x0 0x10000>; 2595d8cf9372SVinod Koul reg-names = "drv-0", "drv-1", "drv-2"; 2596d8cf9372SVinod Koul interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2597d8cf9372SVinod Koul <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2598d8cf9372SVinod Koul <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2599d8cf9372SVinod Koul qcom,tcs-offset = <0xd00>; 2600d8cf9372SVinod Koul qcom,drv-id = <2>; 2601d8cf9372SVinod Koul qcom,tcs-config = <ACTIVE_TCS 2>, 2602d8cf9372SVinod Koul <SLEEP_TCS 1>, 2603d8cf9372SVinod Koul <WAKE_TCS 1>, 2604d8cf9372SVinod Koul <CONTROL_TCS 0>; 2605d8cf9372SVinod Koul 2606d8cf9372SVinod Koul rpmhcc: clock-controller { 2607d8cf9372SVinod Koul compatible = "qcom,sm8150-rpmh-clk"; 2608d8cf9372SVinod Koul #clock-cells = <1>; 2609d8cf9372SVinod Koul clock-names = "xo"; 2610d8cf9372SVinod Koul clocks = <&xo_board>; 2611d8cf9372SVinod Koul }; 2612017e7856SSibi Sankar 2613017e7856SSibi Sankar rpmhpd: power-controller { 2614017e7856SSibi Sankar compatible = "qcom,sm8150-rpmhpd"; 2615017e7856SSibi Sankar #power-domain-cells = <1>; 2616017e7856SSibi Sankar operating-points-v2 = <&rpmhpd_opp_table>; 2617017e7856SSibi Sankar 2618017e7856SSibi Sankar rpmhpd_opp_table: opp-table { 2619017e7856SSibi Sankar compatible = "operating-points-v2"; 2620017e7856SSibi Sankar 2621017e7856SSibi Sankar rpmhpd_opp_ret: opp1 { 2622017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2623017e7856SSibi Sankar }; 2624017e7856SSibi Sankar 2625017e7856SSibi Sankar rpmhpd_opp_min_svs: opp2 { 2626017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2627017e7856SSibi Sankar }; 2628017e7856SSibi Sankar 2629017e7856SSibi Sankar rpmhpd_opp_low_svs: opp3 { 2630017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2631017e7856SSibi Sankar }; 2632017e7856SSibi Sankar 2633017e7856SSibi Sankar rpmhpd_opp_svs: opp4 { 2634017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2635017e7856SSibi Sankar }; 2636017e7856SSibi Sankar 2637017e7856SSibi Sankar rpmhpd_opp_svs_l1: opp5 { 2638017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2639017e7856SSibi Sankar }; 2640017e7856SSibi Sankar 2641017e7856SSibi Sankar rpmhpd_opp_svs_l2: opp6 { 2642017e7856SSibi Sankar opp-level = <224>; 2643017e7856SSibi Sankar }; 2644017e7856SSibi Sankar 2645017e7856SSibi Sankar rpmhpd_opp_nom: opp7 { 2646017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2647017e7856SSibi Sankar }; 2648017e7856SSibi Sankar 2649017e7856SSibi Sankar rpmhpd_opp_nom_l1: opp8 { 2650017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2651017e7856SSibi Sankar }; 2652017e7856SSibi Sankar 2653017e7856SSibi Sankar rpmhpd_opp_nom_l2: opp9 { 2654017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2655017e7856SSibi Sankar }; 2656017e7856SSibi Sankar 2657017e7856SSibi Sankar rpmhpd_opp_turbo: opp10 { 2658017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2659017e7856SSibi Sankar }; 2660017e7856SSibi Sankar 2661017e7856SSibi Sankar rpmhpd_opp_turbo_l1: opp11 { 2662017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2663017e7856SSibi Sankar }; 2664017e7856SSibi Sankar }; 2665017e7856SSibi Sankar }; 266671a2fc6eSJonathan Marek 266771a2fc6eSJonathan Marek apps_bcm_voter: bcm_voter { 266871a2fc6eSJonathan Marek compatible = "qcom,bcm-voter"; 266971a2fc6eSJonathan Marek }; 2670d8cf9372SVinod Koul }; 2671fea8930bSSibi Sankar 2672a6d435c1SSibi Sankar osm_l3: interconnect@18321000 { 2673a6d435c1SSibi Sankar compatible = "qcom,sm8150-osm-l3"; 2674a6d435c1SSibi Sankar reg = <0 0x18321000 0 0x1400>; 2675a6d435c1SSibi Sankar 2676a6d435c1SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2677a6d435c1SSibi Sankar clock-names = "xo", "alternate"; 2678a6d435c1SSibi Sankar 2679a6d435c1SSibi Sankar #interconnect-cells = <1>; 2680a6d435c1SSibi Sankar }; 2681a6d435c1SSibi Sankar 2682fea8930bSSibi Sankar cpufreq_hw: cpufreq@18323000 { 2683fea8930bSSibi Sankar compatible = "qcom,cpufreq-hw"; 2684fea8930bSSibi Sankar reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 2685fea8930bSSibi Sankar <0 0x18327800 0 0x1400>; 2686fea8930bSSibi Sankar reg-names = "freq-domain0", "freq-domain1", 2687fea8930bSSibi Sankar "freq-domain2"; 2688fea8930bSSibi Sankar 2689fea8930bSSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2690fea8930bSSibi Sankar clock-names = "xo", "alternate"; 2691fea8930bSSibi Sankar 2692fea8930bSSibi Sankar #freq-domain-cells = <1>; 2693fea8930bSSibi Sankar }; 269405090bb9SJonathan Marek 269505090bb9SJonathan Marek wifi: wifi@18800000 { 269605090bb9SJonathan Marek compatible = "qcom,wcn3990-wifi"; 269705090bb9SJonathan Marek reg = <0 0x18800000 0 0x800000>; 269805090bb9SJonathan Marek reg-names = "membase"; 269905090bb9SJonathan Marek memory-region = <&wlan_mem>; 270005090bb9SJonathan Marek clock-names = "cxo_ref_clk_pin", "qdss"; 270105090bb9SJonathan Marek clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 270205090bb9SJonathan Marek interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 270305090bb9SJonathan Marek <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 270405090bb9SJonathan Marek <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 270505090bb9SJonathan Marek <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 270605090bb9SJonathan Marek <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 270705090bb9SJonathan Marek <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 270805090bb9SJonathan Marek <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 270905090bb9SJonathan Marek <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 271005090bb9SJonathan Marek <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 271105090bb9SJonathan Marek <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 271205090bb9SJonathan Marek <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 271305090bb9SJonathan Marek <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 271405090bb9SJonathan Marek iommus = <&apps_smmu 0x0640 0x1>; 271505090bb9SJonathan Marek status = "disabled"; 271605090bb9SJonathan Marek }; 2717e13c6d14SVinod Koul }; 2718e13c6d14SVinod Koul 2719e13c6d14SVinod Koul timer { 2720e13c6d14SVinod Koul compatible = "arm,armv8-timer"; 2721e13c6d14SVinod Koul interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 2722e13c6d14SVinod Koul <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 2723e13c6d14SVinod Koul <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 2724e13c6d14SVinod Koul <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 2725e13c6d14SVinod Koul }; 2726d2fa630cSAmit Kucheria 2727d2fa630cSAmit Kucheria thermal-zones { 2728d2fa630cSAmit Kucheria cpu0-thermal { 2729d2fa630cSAmit Kucheria polling-delay-passive = <250>; 2730d2fa630cSAmit Kucheria polling-delay = <1000>; 2731d2fa630cSAmit Kucheria 2732d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 1>; 2733d2fa630cSAmit Kucheria 2734d2fa630cSAmit Kucheria trips { 2735d2fa630cSAmit Kucheria cpu0_alert0: trip-point0 { 2736d2fa630cSAmit Kucheria temperature = <90000>; 2737d2fa630cSAmit Kucheria hysteresis = <2000>; 2738d2fa630cSAmit Kucheria type = "passive"; 2739d2fa630cSAmit Kucheria }; 2740d2fa630cSAmit Kucheria 2741d2fa630cSAmit Kucheria cpu0_alert1: trip-point1 { 2742d2fa630cSAmit Kucheria temperature = <95000>; 2743d2fa630cSAmit Kucheria hysteresis = <2000>; 2744d2fa630cSAmit Kucheria type = "passive"; 2745d2fa630cSAmit Kucheria }; 2746d2fa630cSAmit Kucheria 2747d2fa630cSAmit Kucheria cpu0_crit: cpu_crit { 2748d2fa630cSAmit Kucheria temperature = <110000>; 2749d2fa630cSAmit Kucheria hysteresis = <1000>; 2750d2fa630cSAmit Kucheria type = "critical"; 2751d2fa630cSAmit Kucheria }; 2752d2fa630cSAmit Kucheria }; 2753d2fa630cSAmit Kucheria 2754d2fa630cSAmit Kucheria cooling-maps { 2755d2fa630cSAmit Kucheria map0 { 2756d2fa630cSAmit Kucheria trip = <&cpu0_alert0>; 2757d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2758d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2759d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2760d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2761d2fa630cSAmit Kucheria }; 2762d2fa630cSAmit Kucheria map1 { 2763d2fa630cSAmit Kucheria trip = <&cpu0_alert1>; 2764d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2765d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2766d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2767d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2768d2fa630cSAmit Kucheria }; 2769d2fa630cSAmit Kucheria }; 2770d2fa630cSAmit Kucheria }; 2771d2fa630cSAmit Kucheria 2772d2fa630cSAmit Kucheria cpu1-thermal { 2773d2fa630cSAmit Kucheria polling-delay-passive = <250>; 2774d2fa630cSAmit Kucheria polling-delay = <1000>; 2775d2fa630cSAmit Kucheria 2776d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 2>; 2777d2fa630cSAmit Kucheria 2778d2fa630cSAmit Kucheria trips { 2779d2fa630cSAmit Kucheria cpu1_alert0: trip-point0 { 2780d2fa630cSAmit Kucheria temperature = <90000>; 2781d2fa630cSAmit Kucheria hysteresis = <2000>; 2782d2fa630cSAmit Kucheria type = "passive"; 2783d2fa630cSAmit Kucheria }; 2784d2fa630cSAmit Kucheria 2785d2fa630cSAmit Kucheria cpu1_alert1: trip-point1 { 2786d2fa630cSAmit Kucheria temperature = <95000>; 2787d2fa630cSAmit Kucheria hysteresis = <2000>; 2788d2fa630cSAmit Kucheria type = "passive"; 2789d2fa630cSAmit Kucheria }; 2790d2fa630cSAmit Kucheria 2791d2fa630cSAmit Kucheria cpu1_crit: cpu_crit { 2792d2fa630cSAmit Kucheria temperature = <110000>; 2793d2fa630cSAmit Kucheria hysteresis = <1000>; 2794d2fa630cSAmit Kucheria type = "critical"; 2795d2fa630cSAmit Kucheria }; 2796d2fa630cSAmit Kucheria }; 2797d2fa630cSAmit Kucheria 2798d2fa630cSAmit Kucheria cooling-maps { 2799d2fa630cSAmit Kucheria map0 { 2800d2fa630cSAmit Kucheria trip = <&cpu1_alert0>; 2801d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2802d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2803d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2804d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2805d2fa630cSAmit Kucheria }; 2806d2fa630cSAmit Kucheria map1 { 2807d2fa630cSAmit Kucheria trip = <&cpu1_alert1>; 2808d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2809d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2810d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2811d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2812d2fa630cSAmit Kucheria }; 2813d2fa630cSAmit Kucheria }; 2814d2fa630cSAmit Kucheria }; 2815d2fa630cSAmit Kucheria 2816d2fa630cSAmit Kucheria cpu2-thermal { 2817d2fa630cSAmit Kucheria polling-delay-passive = <250>; 2818d2fa630cSAmit Kucheria polling-delay = <1000>; 2819d2fa630cSAmit Kucheria 2820d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 3>; 2821d2fa630cSAmit Kucheria 2822d2fa630cSAmit Kucheria trips { 2823d2fa630cSAmit Kucheria cpu2_alert0: trip-point0 { 2824d2fa630cSAmit Kucheria temperature = <90000>; 2825d2fa630cSAmit Kucheria hysteresis = <2000>; 2826d2fa630cSAmit Kucheria type = "passive"; 2827d2fa630cSAmit Kucheria }; 2828d2fa630cSAmit Kucheria 2829d2fa630cSAmit Kucheria cpu2_alert1: trip-point1 { 2830d2fa630cSAmit Kucheria temperature = <95000>; 2831d2fa630cSAmit Kucheria hysteresis = <2000>; 2832d2fa630cSAmit Kucheria type = "passive"; 2833d2fa630cSAmit Kucheria }; 2834d2fa630cSAmit Kucheria 2835d2fa630cSAmit Kucheria cpu2_crit: cpu_crit { 2836d2fa630cSAmit Kucheria temperature = <110000>; 2837d2fa630cSAmit Kucheria hysteresis = <1000>; 2838d2fa630cSAmit Kucheria type = "critical"; 2839d2fa630cSAmit Kucheria }; 2840d2fa630cSAmit Kucheria }; 2841d2fa630cSAmit Kucheria 2842d2fa630cSAmit Kucheria cooling-maps { 2843d2fa630cSAmit Kucheria map0 { 2844d2fa630cSAmit Kucheria trip = <&cpu2_alert0>; 2845d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2846d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2847d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2848d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2849d2fa630cSAmit Kucheria }; 2850d2fa630cSAmit Kucheria map1 { 2851d2fa630cSAmit Kucheria trip = <&cpu2_alert1>; 2852d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2853d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2854d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2855d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2856d2fa630cSAmit Kucheria }; 2857d2fa630cSAmit Kucheria }; 2858d2fa630cSAmit Kucheria }; 2859d2fa630cSAmit Kucheria 2860d2fa630cSAmit Kucheria cpu3-thermal { 2861d2fa630cSAmit Kucheria polling-delay-passive = <250>; 2862d2fa630cSAmit Kucheria polling-delay = <1000>; 2863d2fa630cSAmit Kucheria 2864d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 4>; 2865d2fa630cSAmit Kucheria 2866d2fa630cSAmit Kucheria trips { 2867d2fa630cSAmit Kucheria cpu3_alert0: trip-point0 { 2868d2fa630cSAmit Kucheria temperature = <90000>; 2869d2fa630cSAmit Kucheria hysteresis = <2000>; 2870d2fa630cSAmit Kucheria type = "passive"; 2871d2fa630cSAmit Kucheria }; 2872d2fa630cSAmit Kucheria 2873d2fa630cSAmit Kucheria cpu3_alert1: trip-point1 { 2874d2fa630cSAmit Kucheria temperature = <95000>; 2875d2fa630cSAmit Kucheria hysteresis = <2000>; 2876d2fa630cSAmit Kucheria type = "passive"; 2877d2fa630cSAmit Kucheria }; 2878d2fa630cSAmit Kucheria 2879d2fa630cSAmit Kucheria cpu3_crit: cpu_crit { 2880d2fa630cSAmit Kucheria temperature = <110000>; 2881d2fa630cSAmit Kucheria hysteresis = <1000>; 2882d2fa630cSAmit Kucheria type = "critical"; 2883d2fa630cSAmit Kucheria }; 2884d2fa630cSAmit Kucheria }; 2885d2fa630cSAmit Kucheria 2886d2fa630cSAmit Kucheria cooling-maps { 2887d2fa630cSAmit Kucheria map0 { 2888d2fa630cSAmit Kucheria trip = <&cpu3_alert0>; 2889d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2890d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2891d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2892d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2893d2fa630cSAmit Kucheria }; 2894d2fa630cSAmit Kucheria map1 { 2895d2fa630cSAmit Kucheria trip = <&cpu3_alert1>; 2896d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2897d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2898d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2899d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2900d2fa630cSAmit Kucheria }; 2901d2fa630cSAmit Kucheria }; 2902d2fa630cSAmit Kucheria }; 2903d2fa630cSAmit Kucheria 2904d2fa630cSAmit Kucheria cpu4-top-thermal { 2905d2fa630cSAmit Kucheria polling-delay-passive = <250>; 2906d2fa630cSAmit Kucheria polling-delay = <1000>; 2907d2fa630cSAmit Kucheria 2908d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 7>; 2909d2fa630cSAmit Kucheria 2910d2fa630cSAmit Kucheria trips { 2911d2fa630cSAmit Kucheria cpu4_top_alert0: trip-point0 { 2912d2fa630cSAmit Kucheria temperature = <90000>; 2913d2fa630cSAmit Kucheria hysteresis = <2000>; 2914d2fa630cSAmit Kucheria type = "passive"; 2915d2fa630cSAmit Kucheria }; 2916d2fa630cSAmit Kucheria 2917d2fa630cSAmit Kucheria cpu4_top_alert1: trip-point1 { 2918d2fa630cSAmit Kucheria temperature = <95000>; 2919d2fa630cSAmit Kucheria hysteresis = <2000>; 2920d2fa630cSAmit Kucheria type = "passive"; 2921d2fa630cSAmit Kucheria }; 2922d2fa630cSAmit Kucheria 2923d2fa630cSAmit Kucheria cpu4_top_crit: cpu_crit { 2924d2fa630cSAmit Kucheria temperature = <110000>; 2925d2fa630cSAmit Kucheria hysteresis = <1000>; 2926d2fa630cSAmit Kucheria type = "critical"; 2927d2fa630cSAmit Kucheria }; 2928d2fa630cSAmit Kucheria }; 2929d2fa630cSAmit Kucheria 2930d2fa630cSAmit Kucheria cooling-maps { 2931d2fa630cSAmit Kucheria map0 { 2932d2fa630cSAmit Kucheria trip = <&cpu4_top_alert0>; 2933d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2934d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2935d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2936d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2937d2fa630cSAmit Kucheria }; 2938d2fa630cSAmit Kucheria map1 { 2939d2fa630cSAmit Kucheria trip = <&cpu4_top_alert1>; 2940d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2941d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2942d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2943d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2944d2fa630cSAmit Kucheria }; 2945d2fa630cSAmit Kucheria }; 2946d2fa630cSAmit Kucheria }; 2947d2fa630cSAmit Kucheria 2948d2fa630cSAmit Kucheria cpu5-top-thermal { 2949d2fa630cSAmit Kucheria polling-delay-passive = <250>; 2950d2fa630cSAmit Kucheria polling-delay = <1000>; 2951d2fa630cSAmit Kucheria 2952d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 8>; 2953d2fa630cSAmit Kucheria 2954d2fa630cSAmit Kucheria trips { 2955d2fa630cSAmit Kucheria cpu5_top_alert0: trip-point0 { 2956d2fa630cSAmit Kucheria temperature = <90000>; 2957d2fa630cSAmit Kucheria hysteresis = <2000>; 2958d2fa630cSAmit Kucheria type = "passive"; 2959d2fa630cSAmit Kucheria }; 2960d2fa630cSAmit Kucheria 2961d2fa630cSAmit Kucheria cpu5_top_alert1: trip-point1 { 2962d2fa630cSAmit Kucheria temperature = <95000>; 2963d2fa630cSAmit Kucheria hysteresis = <2000>; 2964d2fa630cSAmit Kucheria type = "passive"; 2965d2fa630cSAmit Kucheria }; 2966d2fa630cSAmit Kucheria 2967d2fa630cSAmit Kucheria cpu5_top_crit: cpu_crit { 2968d2fa630cSAmit Kucheria temperature = <110000>; 2969d2fa630cSAmit Kucheria hysteresis = <1000>; 2970d2fa630cSAmit Kucheria type = "critical"; 2971d2fa630cSAmit Kucheria }; 2972d2fa630cSAmit Kucheria }; 2973d2fa630cSAmit Kucheria 2974d2fa630cSAmit Kucheria cooling-maps { 2975d2fa630cSAmit Kucheria map0 { 2976d2fa630cSAmit Kucheria trip = <&cpu5_top_alert0>; 2977d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2978d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2979d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2980d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2981d2fa630cSAmit Kucheria }; 2982d2fa630cSAmit Kucheria map1 { 2983d2fa630cSAmit Kucheria trip = <&cpu5_top_alert1>; 2984d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2985d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2986d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2987d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2988d2fa630cSAmit Kucheria }; 2989d2fa630cSAmit Kucheria }; 2990d2fa630cSAmit Kucheria }; 2991d2fa630cSAmit Kucheria 2992d2fa630cSAmit Kucheria cpu6-top-thermal { 2993d2fa630cSAmit Kucheria polling-delay-passive = <250>; 2994d2fa630cSAmit Kucheria polling-delay = <1000>; 2995d2fa630cSAmit Kucheria 2996d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 9>; 2997d2fa630cSAmit Kucheria 2998d2fa630cSAmit Kucheria trips { 2999d2fa630cSAmit Kucheria cpu6_top_alert0: trip-point0 { 3000d2fa630cSAmit Kucheria temperature = <90000>; 3001d2fa630cSAmit Kucheria hysteresis = <2000>; 3002d2fa630cSAmit Kucheria type = "passive"; 3003d2fa630cSAmit Kucheria }; 3004d2fa630cSAmit Kucheria 3005d2fa630cSAmit Kucheria cpu6_top_alert1: trip-point1 { 3006d2fa630cSAmit Kucheria temperature = <95000>; 3007d2fa630cSAmit Kucheria hysteresis = <2000>; 3008d2fa630cSAmit Kucheria type = "passive"; 3009d2fa630cSAmit Kucheria }; 3010d2fa630cSAmit Kucheria 3011d2fa630cSAmit Kucheria cpu6_top_crit: cpu_crit { 3012d2fa630cSAmit Kucheria temperature = <110000>; 3013d2fa630cSAmit Kucheria hysteresis = <1000>; 3014d2fa630cSAmit Kucheria type = "critical"; 3015d2fa630cSAmit Kucheria }; 3016d2fa630cSAmit Kucheria }; 3017d2fa630cSAmit Kucheria 3018d2fa630cSAmit Kucheria cooling-maps { 3019d2fa630cSAmit Kucheria map0 { 3020d2fa630cSAmit Kucheria trip = <&cpu6_top_alert0>; 3021d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3022d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3023d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3024d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3025d2fa630cSAmit Kucheria }; 3026d2fa630cSAmit Kucheria map1 { 3027d2fa630cSAmit Kucheria trip = <&cpu6_top_alert1>; 3028d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3029d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3030d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3031d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3032d2fa630cSAmit Kucheria }; 3033d2fa630cSAmit Kucheria }; 3034d2fa630cSAmit Kucheria }; 3035d2fa630cSAmit Kucheria 3036d2fa630cSAmit Kucheria cpu7-top-thermal { 3037d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3038d2fa630cSAmit Kucheria polling-delay = <1000>; 3039d2fa630cSAmit Kucheria 3040d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 10>; 3041d2fa630cSAmit Kucheria 3042d2fa630cSAmit Kucheria trips { 3043d2fa630cSAmit Kucheria cpu7_top_alert0: trip-point0 { 3044d2fa630cSAmit Kucheria temperature = <90000>; 3045d2fa630cSAmit Kucheria hysteresis = <2000>; 3046d2fa630cSAmit Kucheria type = "passive"; 3047d2fa630cSAmit Kucheria }; 3048d2fa630cSAmit Kucheria 3049d2fa630cSAmit Kucheria cpu7_top_alert1: trip-point1 { 3050d2fa630cSAmit Kucheria temperature = <95000>; 3051d2fa630cSAmit Kucheria hysteresis = <2000>; 3052d2fa630cSAmit Kucheria type = "passive"; 3053d2fa630cSAmit Kucheria }; 3054d2fa630cSAmit Kucheria 3055d2fa630cSAmit Kucheria cpu7_top_crit: cpu_crit { 3056d2fa630cSAmit Kucheria temperature = <110000>; 3057d2fa630cSAmit Kucheria hysteresis = <1000>; 3058d2fa630cSAmit Kucheria type = "critical"; 3059d2fa630cSAmit Kucheria }; 3060d2fa630cSAmit Kucheria }; 3061d2fa630cSAmit Kucheria 3062d2fa630cSAmit Kucheria cooling-maps { 3063d2fa630cSAmit Kucheria map0 { 3064d2fa630cSAmit Kucheria trip = <&cpu7_top_alert0>; 3065d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3066d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3067d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3068d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3069d2fa630cSAmit Kucheria }; 3070d2fa630cSAmit Kucheria map1 { 3071d2fa630cSAmit Kucheria trip = <&cpu7_top_alert1>; 3072d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3073d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3074d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3075d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3076d2fa630cSAmit Kucheria }; 3077d2fa630cSAmit Kucheria }; 3078d2fa630cSAmit Kucheria }; 3079d2fa630cSAmit Kucheria 3080d2fa630cSAmit Kucheria cpu4-bottom-thermal { 3081d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3082d2fa630cSAmit Kucheria polling-delay = <1000>; 3083d2fa630cSAmit Kucheria 3084d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 11>; 3085d2fa630cSAmit Kucheria 3086d2fa630cSAmit Kucheria trips { 3087d2fa630cSAmit Kucheria cpu4_bottom_alert0: trip-point0 { 3088d2fa630cSAmit Kucheria temperature = <90000>; 3089d2fa630cSAmit Kucheria hysteresis = <2000>; 3090d2fa630cSAmit Kucheria type = "passive"; 3091d2fa630cSAmit Kucheria }; 3092d2fa630cSAmit Kucheria 3093d2fa630cSAmit Kucheria cpu4_bottom_alert1: trip-point1 { 3094d2fa630cSAmit Kucheria temperature = <95000>; 3095d2fa630cSAmit Kucheria hysteresis = <2000>; 3096d2fa630cSAmit Kucheria type = "passive"; 3097d2fa630cSAmit Kucheria }; 3098d2fa630cSAmit Kucheria 3099d2fa630cSAmit Kucheria cpu4_bottom_crit: cpu_crit { 3100d2fa630cSAmit Kucheria temperature = <110000>; 3101d2fa630cSAmit Kucheria hysteresis = <1000>; 3102d2fa630cSAmit Kucheria type = "critical"; 3103d2fa630cSAmit Kucheria }; 3104d2fa630cSAmit Kucheria }; 3105d2fa630cSAmit Kucheria 3106d2fa630cSAmit Kucheria cooling-maps { 3107d2fa630cSAmit Kucheria map0 { 3108d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert0>; 3109d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3110d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3111d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3112d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3113d2fa630cSAmit Kucheria }; 3114d2fa630cSAmit Kucheria map1 { 3115d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert1>; 3116d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3117d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3118d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3119d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3120d2fa630cSAmit Kucheria }; 3121d2fa630cSAmit Kucheria }; 3122d2fa630cSAmit Kucheria }; 3123d2fa630cSAmit Kucheria 3124d2fa630cSAmit Kucheria cpu5-bottom-thermal { 3125d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3126d2fa630cSAmit Kucheria polling-delay = <1000>; 3127d2fa630cSAmit Kucheria 3128d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 12>; 3129d2fa630cSAmit Kucheria 3130d2fa630cSAmit Kucheria trips { 3131d2fa630cSAmit Kucheria cpu5_bottom_alert0: trip-point0 { 3132d2fa630cSAmit Kucheria temperature = <90000>; 3133d2fa630cSAmit Kucheria hysteresis = <2000>; 3134d2fa630cSAmit Kucheria type = "passive"; 3135d2fa630cSAmit Kucheria }; 3136d2fa630cSAmit Kucheria 3137d2fa630cSAmit Kucheria cpu5_bottom_alert1: trip-point1 { 3138d2fa630cSAmit Kucheria temperature = <95000>; 3139d2fa630cSAmit Kucheria hysteresis = <2000>; 3140d2fa630cSAmit Kucheria type = "passive"; 3141d2fa630cSAmit Kucheria }; 3142d2fa630cSAmit Kucheria 3143d2fa630cSAmit Kucheria cpu5_bottom_crit: cpu_crit { 3144d2fa630cSAmit Kucheria temperature = <110000>; 3145d2fa630cSAmit Kucheria hysteresis = <1000>; 3146d2fa630cSAmit Kucheria type = "critical"; 3147d2fa630cSAmit Kucheria }; 3148d2fa630cSAmit Kucheria }; 3149d2fa630cSAmit Kucheria 3150d2fa630cSAmit Kucheria cooling-maps { 3151d2fa630cSAmit Kucheria map0 { 3152d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert0>; 3153d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3154d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3155d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3156d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3157d2fa630cSAmit Kucheria }; 3158d2fa630cSAmit Kucheria map1 { 3159d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert1>; 3160d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3161d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3162d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3163d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3164d2fa630cSAmit Kucheria }; 3165d2fa630cSAmit Kucheria }; 3166d2fa630cSAmit Kucheria }; 3167d2fa630cSAmit Kucheria 3168d2fa630cSAmit Kucheria cpu6-bottom-thermal { 3169d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3170d2fa630cSAmit Kucheria polling-delay = <1000>; 3171d2fa630cSAmit Kucheria 3172d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 13>; 3173d2fa630cSAmit Kucheria 3174d2fa630cSAmit Kucheria trips { 3175d2fa630cSAmit Kucheria cpu6_bottom_alert0: trip-point0 { 3176d2fa630cSAmit Kucheria temperature = <90000>; 3177d2fa630cSAmit Kucheria hysteresis = <2000>; 3178d2fa630cSAmit Kucheria type = "passive"; 3179d2fa630cSAmit Kucheria }; 3180d2fa630cSAmit Kucheria 3181d2fa630cSAmit Kucheria cpu6_bottom_alert1: trip-point1 { 3182d2fa630cSAmit Kucheria temperature = <95000>; 3183d2fa630cSAmit Kucheria hysteresis = <2000>; 3184d2fa630cSAmit Kucheria type = "passive"; 3185d2fa630cSAmit Kucheria }; 3186d2fa630cSAmit Kucheria 3187d2fa630cSAmit Kucheria cpu6_bottom_crit: cpu_crit { 3188d2fa630cSAmit Kucheria temperature = <110000>; 3189d2fa630cSAmit Kucheria hysteresis = <1000>; 3190d2fa630cSAmit Kucheria type = "critical"; 3191d2fa630cSAmit Kucheria }; 3192d2fa630cSAmit Kucheria }; 3193d2fa630cSAmit Kucheria 3194d2fa630cSAmit Kucheria cooling-maps { 3195d2fa630cSAmit Kucheria map0 { 3196d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert0>; 3197d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3198d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3199d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3200d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3201d2fa630cSAmit Kucheria }; 3202d2fa630cSAmit Kucheria map1 { 3203d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert1>; 3204d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3205d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3206d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3207d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3208d2fa630cSAmit Kucheria }; 3209d2fa630cSAmit Kucheria }; 3210d2fa630cSAmit Kucheria }; 3211d2fa630cSAmit Kucheria 3212d2fa630cSAmit Kucheria cpu7-bottom-thermal { 3213d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3214d2fa630cSAmit Kucheria polling-delay = <1000>; 3215d2fa630cSAmit Kucheria 3216d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 14>; 3217d2fa630cSAmit Kucheria 3218d2fa630cSAmit Kucheria trips { 3219d2fa630cSAmit Kucheria cpu7_bottom_alert0: trip-point0 { 3220d2fa630cSAmit Kucheria temperature = <90000>; 3221d2fa630cSAmit Kucheria hysteresis = <2000>; 3222d2fa630cSAmit Kucheria type = "passive"; 3223d2fa630cSAmit Kucheria }; 3224d2fa630cSAmit Kucheria 3225d2fa630cSAmit Kucheria cpu7_bottom_alert1: trip-point1 { 3226d2fa630cSAmit Kucheria temperature = <95000>; 3227d2fa630cSAmit Kucheria hysteresis = <2000>; 3228d2fa630cSAmit Kucheria type = "passive"; 3229d2fa630cSAmit Kucheria }; 3230d2fa630cSAmit Kucheria 3231d2fa630cSAmit Kucheria cpu7_bottom_crit: cpu_crit { 3232d2fa630cSAmit Kucheria temperature = <110000>; 3233d2fa630cSAmit Kucheria hysteresis = <1000>; 3234d2fa630cSAmit Kucheria type = "critical"; 3235d2fa630cSAmit Kucheria }; 3236d2fa630cSAmit Kucheria }; 3237d2fa630cSAmit Kucheria 3238d2fa630cSAmit Kucheria cooling-maps { 3239d2fa630cSAmit Kucheria map0 { 3240d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert0>; 3241d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3242d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3243d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3244d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3245d2fa630cSAmit Kucheria }; 3246d2fa630cSAmit Kucheria map1 { 3247d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert1>; 3248d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3249d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3250d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3251d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3252d2fa630cSAmit Kucheria }; 3253d2fa630cSAmit Kucheria }; 3254d2fa630cSAmit Kucheria }; 3255d2fa630cSAmit Kucheria 3256d2fa630cSAmit Kucheria aoss0-thermal { 3257d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3258d2fa630cSAmit Kucheria polling-delay = <1000>; 3259d2fa630cSAmit Kucheria 3260d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 0>; 3261d2fa630cSAmit Kucheria 3262d2fa630cSAmit Kucheria trips { 3263d2fa630cSAmit Kucheria aoss0_alert0: trip-point0 { 3264d2fa630cSAmit Kucheria temperature = <90000>; 3265d2fa630cSAmit Kucheria hysteresis = <2000>; 3266d2fa630cSAmit Kucheria type = "hot"; 3267d2fa630cSAmit Kucheria }; 3268d2fa630cSAmit Kucheria }; 3269d2fa630cSAmit Kucheria }; 3270d2fa630cSAmit Kucheria 3271d2fa630cSAmit Kucheria cluster0-thermal { 3272d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3273d2fa630cSAmit Kucheria polling-delay = <1000>; 3274d2fa630cSAmit Kucheria 3275d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 5>; 3276d2fa630cSAmit Kucheria 3277d2fa630cSAmit Kucheria trips { 3278d2fa630cSAmit Kucheria cluster0_alert0: trip-point0 { 3279d2fa630cSAmit Kucheria temperature = <90000>; 3280d2fa630cSAmit Kucheria hysteresis = <2000>; 3281d2fa630cSAmit Kucheria type = "hot"; 3282d2fa630cSAmit Kucheria }; 3283d2fa630cSAmit Kucheria cluster0_crit: cluster0_crit { 3284d2fa630cSAmit Kucheria temperature = <110000>; 3285d2fa630cSAmit Kucheria hysteresis = <2000>; 3286d2fa630cSAmit Kucheria type = "critical"; 3287d2fa630cSAmit Kucheria }; 3288d2fa630cSAmit Kucheria }; 3289d2fa630cSAmit Kucheria }; 3290d2fa630cSAmit Kucheria 3291d2fa630cSAmit Kucheria cluster1-thermal { 3292d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3293d2fa630cSAmit Kucheria polling-delay = <1000>; 3294d2fa630cSAmit Kucheria 3295d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 6>; 3296d2fa630cSAmit Kucheria 3297d2fa630cSAmit Kucheria trips { 3298d2fa630cSAmit Kucheria cluster1_alert0: trip-point0 { 3299d2fa630cSAmit Kucheria temperature = <90000>; 3300d2fa630cSAmit Kucheria hysteresis = <2000>; 3301d2fa630cSAmit Kucheria type = "hot"; 3302d2fa630cSAmit Kucheria }; 3303d2fa630cSAmit Kucheria cluster1_crit: cluster1_crit { 3304d2fa630cSAmit Kucheria temperature = <110000>; 3305d2fa630cSAmit Kucheria hysteresis = <2000>; 3306d2fa630cSAmit Kucheria type = "critical"; 3307d2fa630cSAmit Kucheria }; 3308d2fa630cSAmit Kucheria }; 3309d2fa630cSAmit Kucheria }; 3310d2fa630cSAmit Kucheria 3311d2fa630cSAmit Kucheria gpu-thermal-top { 3312d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3313d2fa630cSAmit Kucheria polling-delay = <1000>; 3314d2fa630cSAmit Kucheria 3315d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 15>; 3316d2fa630cSAmit Kucheria 3317d2fa630cSAmit Kucheria trips { 3318d2fa630cSAmit Kucheria gpu1_alert0: trip-point0 { 3319d2fa630cSAmit Kucheria temperature = <90000>; 3320d2fa630cSAmit Kucheria hysteresis = <2000>; 3321d2fa630cSAmit Kucheria type = "hot"; 3322d2fa630cSAmit Kucheria }; 3323d2fa630cSAmit Kucheria }; 3324d2fa630cSAmit Kucheria }; 3325d2fa630cSAmit Kucheria 3326d2fa630cSAmit Kucheria aoss1-thermal { 3327d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3328d2fa630cSAmit Kucheria polling-delay = <1000>; 3329d2fa630cSAmit Kucheria 3330d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 0>; 3331d2fa630cSAmit Kucheria 3332d2fa630cSAmit Kucheria trips { 3333d2fa630cSAmit Kucheria aoss1_alert0: trip-point0 { 3334d2fa630cSAmit Kucheria temperature = <90000>; 3335d2fa630cSAmit Kucheria hysteresis = <2000>; 3336d2fa630cSAmit Kucheria type = "hot"; 3337d2fa630cSAmit Kucheria }; 3338d2fa630cSAmit Kucheria }; 3339d2fa630cSAmit Kucheria }; 3340d2fa630cSAmit Kucheria 3341d2fa630cSAmit Kucheria wlan-thermal { 3342d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3343d2fa630cSAmit Kucheria polling-delay = <1000>; 3344d2fa630cSAmit Kucheria 3345d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 1>; 3346d2fa630cSAmit Kucheria 3347d2fa630cSAmit Kucheria trips { 3348d2fa630cSAmit Kucheria wlan_alert0: trip-point0 { 3349d2fa630cSAmit Kucheria temperature = <90000>; 3350d2fa630cSAmit Kucheria hysteresis = <2000>; 3351d2fa630cSAmit Kucheria type = "hot"; 3352d2fa630cSAmit Kucheria }; 3353d2fa630cSAmit Kucheria }; 3354d2fa630cSAmit Kucheria }; 3355d2fa630cSAmit Kucheria 3356d2fa630cSAmit Kucheria video-thermal { 3357d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3358d2fa630cSAmit Kucheria polling-delay = <1000>; 3359d2fa630cSAmit Kucheria 3360d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 2>; 3361d2fa630cSAmit Kucheria 3362d2fa630cSAmit Kucheria trips { 3363d2fa630cSAmit Kucheria video_alert0: trip-point0 { 3364d2fa630cSAmit Kucheria temperature = <90000>; 3365d2fa630cSAmit Kucheria hysteresis = <2000>; 3366d2fa630cSAmit Kucheria type = "hot"; 3367d2fa630cSAmit Kucheria }; 3368d2fa630cSAmit Kucheria }; 3369d2fa630cSAmit Kucheria }; 3370d2fa630cSAmit Kucheria 3371d2fa630cSAmit Kucheria mem-thermal { 3372d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3373d2fa630cSAmit Kucheria polling-delay = <1000>; 3374d2fa630cSAmit Kucheria 3375d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 3>; 3376d2fa630cSAmit Kucheria 3377d2fa630cSAmit Kucheria trips { 3378d2fa630cSAmit Kucheria mem_alert0: trip-point0 { 3379d2fa630cSAmit Kucheria temperature = <90000>; 3380d2fa630cSAmit Kucheria hysteresis = <2000>; 3381d2fa630cSAmit Kucheria type = "hot"; 3382d2fa630cSAmit Kucheria }; 3383d2fa630cSAmit Kucheria }; 3384d2fa630cSAmit Kucheria }; 3385d2fa630cSAmit Kucheria 3386d2fa630cSAmit Kucheria q6-hvx-thermal { 3387d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3388d2fa630cSAmit Kucheria polling-delay = <1000>; 3389d2fa630cSAmit Kucheria 3390d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 4>; 3391d2fa630cSAmit Kucheria 3392d2fa630cSAmit Kucheria trips { 3393d2fa630cSAmit Kucheria q6_hvx_alert0: trip-point0 { 3394d2fa630cSAmit Kucheria temperature = <90000>; 3395d2fa630cSAmit Kucheria hysteresis = <2000>; 3396d2fa630cSAmit Kucheria type = "hot"; 3397d2fa630cSAmit Kucheria }; 3398d2fa630cSAmit Kucheria }; 3399d2fa630cSAmit Kucheria }; 3400d2fa630cSAmit Kucheria 3401d2fa630cSAmit Kucheria camera-thermal { 3402d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3403d2fa630cSAmit Kucheria polling-delay = <1000>; 3404d2fa630cSAmit Kucheria 3405d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 5>; 3406d2fa630cSAmit Kucheria 3407d2fa630cSAmit Kucheria trips { 3408d2fa630cSAmit Kucheria camera_alert0: trip-point0 { 3409d2fa630cSAmit Kucheria temperature = <90000>; 3410d2fa630cSAmit Kucheria hysteresis = <2000>; 3411d2fa630cSAmit Kucheria type = "hot"; 3412d2fa630cSAmit Kucheria }; 3413d2fa630cSAmit Kucheria }; 3414d2fa630cSAmit Kucheria }; 3415d2fa630cSAmit Kucheria 3416d2fa630cSAmit Kucheria compute-thermal { 3417d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3418d2fa630cSAmit Kucheria polling-delay = <1000>; 3419d2fa630cSAmit Kucheria 3420d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 6>; 3421d2fa630cSAmit Kucheria 3422d2fa630cSAmit Kucheria trips { 3423d2fa630cSAmit Kucheria compute_alert0: trip-point0 { 3424d2fa630cSAmit Kucheria temperature = <90000>; 3425d2fa630cSAmit Kucheria hysteresis = <2000>; 3426d2fa630cSAmit Kucheria type = "hot"; 3427d2fa630cSAmit Kucheria }; 3428d2fa630cSAmit Kucheria }; 3429d2fa630cSAmit Kucheria }; 3430d2fa630cSAmit Kucheria 3431d2fa630cSAmit Kucheria modem-thermal { 3432d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3433d2fa630cSAmit Kucheria polling-delay = <1000>; 3434d2fa630cSAmit Kucheria 3435d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 7>; 3436d2fa630cSAmit Kucheria 3437d2fa630cSAmit Kucheria trips { 3438d2fa630cSAmit Kucheria modem_alert0: trip-point0 { 3439d2fa630cSAmit Kucheria temperature = <90000>; 3440d2fa630cSAmit Kucheria hysteresis = <2000>; 3441d2fa630cSAmit Kucheria type = "hot"; 3442d2fa630cSAmit Kucheria }; 3443d2fa630cSAmit Kucheria }; 3444d2fa630cSAmit Kucheria }; 3445d2fa630cSAmit Kucheria 3446d2fa630cSAmit Kucheria npu-thermal { 3447d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3448d2fa630cSAmit Kucheria polling-delay = <1000>; 3449d2fa630cSAmit Kucheria 3450d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 8>; 3451d2fa630cSAmit Kucheria 3452d2fa630cSAmit Kucheria trips { 3453d2fa630cSAmit Kucheria npu_alert0: trip-point0 { 3454d2fa630cSAmit Kucheria temperature = <90000>; 3455d2fa630cSAmit Kucheria hysteresis = <2000>; 3456d2fa630cSAmit Kucheria type = "hot"; 3457d2fa630cSAmit Kucheria }; 3458d2fa630cSAmit Kucheria }; 3459d2fa630cSAmit Kucheria }; 3460d2fa630cSAmit Kucheria 3461d2fa630cSAmit Kucheria modem-vec-thermal { 3462d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3463d2fa630cSAmit Kucheria polling-delay = <1000>; 3464d2fa630cSAmit Kucheria 3465d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 9>; 3466d2fa630cSAmit Kucheria 3467d2fa630cSAmit Kucheria trips { 3468d2fa630cSAmit Kucheria modem_vec_alert0: trip-point0 { 3469d2fa630cSAmit Kucheria temperature = <90000>; 3470d2fa630cSAmit Kucheria hysteresis = <2000>; 3471d2fa630cSAmit Kucheria type = "hot"; 3472d2fa630cSAmit Kucheria }; 3473d2fa630cSAmit Kucheria }; 3474d2fa630cSAmit Kucheria }; 3475d2fa630cSAmit Kucheria 3476d2fa630cSAmit Kucheria modem-scl-thermal { 3477d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3478d2fa630cSAmit Kucheria polling-delay = <1000>; 3479d2fa630cSAmit Kucheria 3480d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 10>; 3481d2fa630cSAmit Kucheria 3482d2fa630cSAmit Kucheria trips { 3483d2fa630cSAmit Kucheria modem_scl_alert0: trip-point0 { 3484d2fa630cSAmit Kucheria temperature = <90000>; 3485d2fa630cSAmit Kucheria hysteresis = <2000>; 3486d2fa630cSAmit Kucheria type = "hot"; 3487d2fa630cSAmit Kucheria }; 3488d2fa630cSAmit Kucheria }; 3489d2fa630cSAmit Kucheria }; 3490d2fa630cSAmit Kucheria 3491d2fa630cSAmit Kucheria gpu-thermal-bottom { 3492d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3493d2fa630cSAmit Kucheria polling-delay = <1000>; 3494d2fa630cSAmit Kucheria 3495d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 11>; 3496d2fa630cSAmit Kucheria 3497d2fa630cSAmit Kucheria trips { 3498d2fa630cSAmit Kucheria gpu2_alert0: trip-point0 { 3499d2fa630cSAmit Kucheria temperature = <90000>; 3500d2fa630cSAmit Kucheria hysteresis = <2000>; 3501d2fa630cSAmit Kucheria type = "hot"; 3502d2fa630cSAmit Kucheria }; 3503d2fa630cSAmit Kucheria }; 3504d2fa630cSAmit Kucheria }; 3505d2fa630cSAmit Kucheria }; 3506e13c6d14SVinod Koul}; 3507