1e13c6d14SVinod Koul// SPDX-License-Identifier: BSD-3-Clause 2e13c6d14SVinod Koul/* 3e13c6d14SVinod Koul * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4e13c6d14SVinod Koul * Copyright (c) 2019, Linaro Limited 5e13c6d14SVinod Koul */ 6e13c6d14SVinod Koul 705006290SFelipe Balbi#include <dt-bindings/dma/qcom-gpi.h> 8e13c6d14SVinod Koul#include <dt-bindings/interrupt-controller/arm-gic.h> 9017e7856SSibi Sankar#include <dt-bindings/power/qcom-rpmpd.h> 10e13c6d14SVinod Koul#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11e13c6d14SVinod Koul#include <dt-bindings/clock/qcom,rpmh.h> 12d6f55763SVinod Koul#include <dt-bindings/clock/qcom,gcc-sm8150.h> 13f1269916SJonathan Marek#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 14a6d435c1SSibi Sankar#include <dt-bindings/interconnect/qcom,osm-l3.h> 152b6187abSThara Gopinath#include <dt-bindings/interconnect/qcom,sm8150.h> 16d2fa630cSAmit Kucheria#include <dt-bindings/thermal/thermal.h> 17e13c6d14SVinod Koul 18e13c6d14SVinod Koul/ { 19e13c6d14SVinod Koul interrupt-parent = <&intc>; 20e13c6d14SVinod Koul 21e13c6d14SVinod Koul #address-cells = <2>; 22e13c6d14SVinod Koul #size-cells = <2>; 23e13c6d14SVinod Koul 24e13c6d14SVinod Koul chosen { }; 25e13c6d14SVinod Koul 26e13c6d14SVinod Koul clocks { 27e13c6d14SVinod Koul xo_board: xo-board { 28e13c6d14SVinod Koul compatible = "fixed-clock"; 29e13c6d14SVinod Koul #clock-cells = <0>; 30e13c6d14SVinod Koul clock-frequency = <38400000>; 31e13c6d14SVinod Koul clock-output-names = "xo_board"; 32e13c6d14SVinod Koul }; 33e13c6d14SVinod Koul 34e13c6d14SVinod Koul sleep_clk: sleep-clk { 35e13c6d14SVinod Koul compatible = "fixed-clock"; 36e13c6d14SVinod Koul #clock-cells = <0>; 37e13c6d14SVinod Koul clock-frequency = <32764>; 38e13c6d14SVinod Koul clock-output-names = "sleep_clk"; 39e13c6d14SVinod Koul }; 40e13c6d14SVinod Koul }; 41e13c6d14SVinod Koul 42e13c6d14SVinod Koul cpus { 43e13c6d14SVinod Koul #address-cells = <2>; 44e13c6d14SVinod Koul #size-cells = <0>; 45e13c6d14SVinod Koul 46e13c6d14SVinod Koul CPU0: cpu@0 { 47e13c6d14SVinod Koul device_type = "cpu"; 48e13c6d14SVinod Koul compatible = "qcom,kryo485"; 49e13c6d14SVinod Koul reg = <0x0 0x0>; 50e13c6d14SVinod Koul enable-method = "psci"; 515b2dae72SDanny Lin capacity-dmips-mhz = <488>; 525b2dae72SDanny Lin dynamic-power-coefficient = <232>; 53e13c6d14SVinod Koul next-level-cache = <&L2_0>; 54fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 552b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 562b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 572b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 58b2e3f897SDanny Lin power-domains = <&CPU_PD0>; 59b2e3f897SDanny Lin power-domain-names = "psci"; 60d2fa630cSAmit Kucheria #cooling-cells = <2>; 61e13c6d14SVinod Koul L2_0: l2-cache { 62e13c6d14SVinod Koul compatible = "cache"; 63e13c6d14SVinod Koul next-level-cache = <&L3_0>; 64e13c6d14SVinod Koul L3_0: l3-cache { 65e13c6d14SVinod Koul compatible = "cache"; 66e13c6d14SVinod Koul }; 67e13c6d14SVinod Koul }; 68e13c6d14SVinod Koul }; 69e13c6d14SVinod Koul 70e13c6d14SVinod Koul CPU1: cpu@100 { 71e13c6d14SVinod Koul device_type = "cpu"; 72e13c6d14SVinod Koul compatible = "qcom,kryo485"; 73e13c6d14SVinod Koul reg = <0x0 0x100>; 74e13c6d14SVinod Koul enable-method = "psci"; 755b2dae72SDanny Lin capacity-dmips-mhz = <488>; 765b2dae72SDanny Lin dynamic-power-coefficient = <232>; 77e13c6d14SVinod Koul next-level-cache = <&L2_100>; 78fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 792b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 802b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 812b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 82b2e3f897SDanny Lin power-domains = <&CPU_PD1>; 83b2e3f897SDanny Lin power-domain-names = "psci"; 84d2fa630cSAmit Kucheria #cooling-cells = <2>; 85e13c6d14SVinod Koul L2_100: l2-cache { 86e13c6d14SVinod Koul compatible = "cache"; 87e13c6d14SVinod Koul next-level-cache = <&L3_0>; 88e13c6d14SVinod Koul }; 89e13c6d14SVinod Koul 90e13c6d14SVinod Koul }; 91e13c6d14SVinod Koul 92e13c6d14SVinod Koul CPU2: cpu@200 { 93e13c6d14SVinod Koul device_type = "cpu"; 94e13c6d14SVinod Koul compatible = "qcom,kryo485"; 95e13c6d14SVinod Koul reg = <0x0 0x200>; 96e13c6d14SVinod Koul enable-method = "psci"; 975b2dae72SDanny Lin capacity-dmips-mhz = <488>; 985b2dae72SDanny Lin dynamic-power-coefficient = <232>; 99e13c6d14SVinod Koul next-level-cache = <&L2_200>; 100fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1012b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1022b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1032b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 104b2e3f897SDanny Lin power-domains = <&CPU_PD2>; 105b2e3f897SDanny Lin power-domain-names = "psci"; 106d2fa630cSAmit Kucheria #cooling-cells = <2>; 107e13c6d14SVinod Koul L2_200: l2-cache { 108e13c6d14SVinod Koul compatible = "cache"; 109e13c6d14SVinod Koul next-level-cache = <&L3_0>; 110e13c6d14SVinod Koul }; 111e13c6d14SVinod Koul }; 112e13c6d14SVinod Koul 113e13c6d14SVinod Koul CPU3: cpu@300 { 114e13c6d14SVinod Koul device_type = "cpu"; 115e13c6d14SVinod Koul compatible = "qcom,kryo485"; 116e13c6d14SVinod Koul reg = <0x0 0x300>; 117e13c6d14SVinod Koul enable-method = "psci"; 1185b2dae72SDanny Lin capacity-dmips-mhz = <488>; 1195b2dae72SDanny Lin dynamic-power-coefficient = <232>; 120e13c6d14SVinod Koul next-level-cache = <&L2_300>; 121fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1222b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1232b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1242b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 125b2e3f897SDanny Lin power-domains = <&CPU_PD3>; 126b2e3f897SDanny Lin power-domain-names = "psci"; 127d2fa630cSAmit Kucheria #cooling-cells = <2>; 128e13c6d14SVinod Koul L2_300: l2-cache { 129e13c6d14SVinod Koul compatible = "cache"; 130e13c6d14SVinod Koul next-level-cache = <&L3_0>; 131e13c6d14SVinod Koul }; 132e13c6d14SVinod Koul }; 133e13c6d14SVinod Koul 134e13c6d14SVinod Koul CPU4: cpu@400 { 135e13c6d14SVinod Koul device_type = "cpu"; 136e13c6d14SVinod Koul compatible = "qcom,kryo485"; 137e13c6d14SVinod Koul reg = <0x0 0x400>; 138e13c6d14SVinod Koul enable-method = "psci"; 1395b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1405b2dae72SDanny Lin dynamic-power-coefficient = <369>; 141e13c6d14SVinod Koul next-level-cache = <&L2_400>; 142fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1432b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1442b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1452b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 146b2e3f897SDanny Lin power-domains = <&CPU_PD4>; 147b2e3f897SDanny Lin power-domain-names = "psci"; 148d2fa630cSAmit Kucheria #cooling-cells = <2>; 149e13c6d14SVinod Koul L2_400: l2-cache { 150e13c6d14SVinod Koul compatible = "cache"; 151e13c6d14SVinod Koul next-level-cache = <&L3_0>; 152e13c6d14SVinod Koul }; 153e13c6d14SVinod Koul }; 154e13c6d14SVinod Koul 155e13c6d14SVinod Koul CPU5: cpu@500 { 156e13c6d14SVinod Koul device_type = "cpu"; 157e13c6d14SVinod Koul compatible = "qcom,kryo485"; 158e13c6d14SVinod Koul reg = <0x0 0x500>; 159e13c6d14SVinod Koul enable-method = "psci"; 1605b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1615b2dae72SDanny Lin dynamic-power-coefficient = <369>; 162e13c6d14SVinod Koul next-level-cache = <&L2_500>; 163fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1642b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1652b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1662b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 167b2e3f897SDanny Lin power-domains = <&CPU_PD5>; 168b2e3f897SDanny Lin power-domain-names = "psci"; 169d2fa630cSAmit Kucheria #cooling-cells = <2>; 170e13c6d14SVinod Koul L2_500: l2-cache { 171e13c6d14SVinod Koul compatible = "cache"; 172e13c6d14SVinod Koul next-level-cache = <&L3_0>; 173e13c6d14SVinod Koul }; 174e13c6d14SVinod Koul }; 175e13c6d14SVinod Koul 176e13c6d14SVinod Koul CPU6: cpu@600 { 177e13c6d14SVinod Koul device_type = "cpu"; 178e13c6d14SVinod Koul compatible = "qcom,kryo485"; 179e13c6d14SVinod Koul reg = <0x0 0x600>; 180e13c6d14SVinod Koul enable-method = "psci"; 1815b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1825b2dae72SDanny Lin dynamic-power-coefficient = <369>; 183e13c6d14SVinod Koul next-level-cache = <&L2_600>; 184fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1852b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1862b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1872b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 188b2e3f897SDanny Lin power-domains = <&CPU_PD6>; 189b2e3f897SDanny Lin power-domain-names = "psci"; 190d2fa630cSAmit Kucheria #cooling-cells = <2>; 191e13c6d14SVinod Koul L2_600: l2-cache { 192e13c6d14SVinod Koul compatible = "cache"; 193e13c6d14SVinod Koul next-level-cache = <&L3_0>; 194e13c6d14SVinod Koul }; 195e13c6d14SVinod Koul }; 196e13c6d14SVinod Koul 197e13c6d14SVinod Koul CPU7: cpu@700 { 198e13c6d14SVinod Koul device_type = "cpu"; 199e13c6d14SVinod Koul compatible = "qcom,kryo485"; 200e13c6d14SVinod Koul reg = <0x0 0x700>; 201e13c6d14SVinod Koul enable-method = "psci"; 2025b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 2035b2dae72SDanny Lin dynamic-power-coefficient = <421>; 204e13c6d14SVinod Koul next-level-cache = <&L2_700>; 205fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 2>; 2062b6187abSThara Gopinath operating-points-v2 = <&cpu7_opp_table>; 2072b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 2082b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 209b2e3f897SDanny Lin power-domains = <&CPU_PD7>; 210b2e3f897SDanny Lin power-domain-names = "psci"; 211d2fa630cSAmit Kucheria #cooling-cells = <2>; 212e13c6d14SVinod Koul L2_700: l2-cache { 213e13c6d14SVinod Koul compatible = "cache"; 214e13c6d14SVinod Koul next-level-cache = <&L3_0>; 215e13c6d14SVinod Koul }; 216e13c6d14SVinod Koul }; 217066d21bcSDanny Lin 218066d21bcSDanny Lin cpu-map { 219066d21bcSDanny Lin cluster0 { 220066d21bcSDanny Lin core0 { 221066d21bcSDanny Lin cpu = <&CPU0>; 222066d21bcSDanny Lin }; 223066d21bcSDanny Lin 224066d21bcSDanny Lin core1 { 225066d21bcSDanny Lin cpu = <&CPU1>; 226066d21bcSDanny Lin }; 227066d21bcSDanny Lin 228066d21bcSDanny Lin core2 { 229066d21bcSDanny Lin cpu = <&CPU2>; 230066d21bcSDanny Lin }; 231066d21bcSDanny Lin 232066d21bcSDanny Lin core3 { 233066d21bcSDanny Lin cpu = <&CPU3>; 234066d21bcSDanny Lin }; 235066d21bcSDanny Lin 236066d21bcSDanny Lin core4 { 237066d21bcSDanny Lin cpu = <&CPU4>; 238066d21bcSDanny Lin }; 239066d21bcSDanny Lin 240066d21bcSDanny Lin core5 { 241066d21bcSDanny Lin cpu = <&CPU5>; 242066d21bcSDanny Lin }; 243066d21bcSDanny Lin 244066d21bcSDanny Lin core6 { 245066d21bcSDanny Lin cpu = <&CPU6>; 246066d21bcSDanny Lin }; 247066d21bcSDanny Lin 248066d21bcSDanny Lin core7 { 249066d21bcSDanny Lin cpu = <&CPU7>; 250066d21bcSDanny Lin }; 251066d21bcSDanny Lin }; 252066d21bcSDanny Lin }; 25381188f58SDanny Lin 25481188f58SDanny Lin idle-states { 25581188f58SDanny Lin entry-method = "psci"; 25681188f58SDanny Lin 25781188f58SDanny Lin LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 25881188f58SDanny Lin compatible = "arm,idle-state"; 25981188f58SDanny Lin idle-state-name = "little-rail-power-collapse"; 26081188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 26181188f58SDanny Lin entry-latency-us = <355>; 26281188f58SDanny Lin exit-latency-us = <909>; 26381188f58SDanny Lin min-residency-us = <3934>; 26481188f58SDanny Lin local-timer-stop; 26581188f58SDanny Lin }; 26681188f58SDanny Lin 26781188f58SDanny Lin BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 26881188f58SDanny Lin compatible = "arm,idle-state"; 26981188f58SDanny Lin idle-state-name = "big-rail-power-collapse"; 27081188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 27181188f58SDanny Lin entry-latency-us = <241>; 27281188f58SDanny Lin exit-latency-us = <1461>; 27381188f58SDanny Lin min-residency-us = <4488>; 27481188f58SDanny Lin local-timer-stop; 27581188f58SDanny Lin }; 276b2e3f897SDanny Lin }; 27781188f58SDanny Lin 278b2e3f897SDanny Lin domain-idle-states { 27981188f58SDanny Lin CLUSTER_SLEEP_0: cluster-sleep-0 { 280b2e3f897SDanny Lin compatible = "domain-idle-state"; 28181188f58SDanny Lin idle-state-name = "cluster-power-collapse"; 282b2e3f897SDanny Lin arm,psci-suspend-param = <0x4100c244>; 28381188f58SDanny Lin entry-latency-us = <3263>; 28481188f58SDanny Lin exit-latency-us = <6562>; 28581188f58SDanny Lin min-residency-us = <9987>; 28681188f58SDanny Lin local-timer-stop; 28781188f58SDanny Lin }; 28881188f58SDanny Lin }; 289e13c6d14SVinod Koul }; 290e13c6d14SVinod Koul 2912b6187abSThara Gopinath cpu0_opp_table: cpu0_opp_table { 2922b6187abSThara Gopinath compatible = "operating-points-v2"; 2932b6187abSThara Gopinath opp-shared; 2942b6187abSThara Gopinath 2952b6187abSThara Gopinath cpu0_opp1: opp-300000000 { 2962b6187abSThara Gopinath opp-hz = /bits/ 64 <300000000>; 2972b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 2982b6187abSThara Gopinath }; 2992b6187abSThara Gopinath 3002b6187abSThara Gopinath cpu0_opp2: opp-403200000 { 3012b6187abSThara Gopinath opp-hz = /bits/ 64 <403200000>; 3022b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 3032b6187abSThara Gopinath }; 3042b6187abSThara Gopinath 3052b6187abSThara Gopinath cpu0_opp3: opp-499200000 { 3062b6187abSThara Gopinath opp-hz = /bits/ 64 <499200000>; 3072b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3082b6187abSThara Gopinath }; 3092b6187abSThara Gopinath 3102b6187abSThara Gopinath cpu0_opp4: opp-576000000 { 3112b6187abSThara Gopinath opp-hz = /bits/ 64 <576000000>; 3122b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3132b6187abSThara Gopinath }; 3142b6187abSThara Gopinath 3152b6187abSThara Gopinath cpu0_opp5: opp-672000000 { 3162b6187abSThara Gopinath opp-hz = /bits/ 64 <672000000>; 3172b6187abSThara Gopinath opp-peak-kBps = <800000 15974400>; 3182b6187abSThara Gopinath }; 3192b6187abSThara Gopinath 3202b6187abSThara Gopinath cpu0_opp6: opp-768000000 { 321ce3b50cfSThara Gopinath opp-hz = /bits/ 64 <768000000>; 3222b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3232b6187abSThara Gopinath }; 3242b6187abSThara Gopinath 3252b6187abSThara Gopinath cpu0_opp7: opp-844800000 { 3262b6187abSThara Gopinath opp-hz = /bits/ 64 <844800000>; 3272b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3282b6187abSThara Gopinath }; 3292b6187abSThara Gopinath 3302b6187abSThara Gopinath cpu0_opp8: opp-940800000 { 3312b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 3322b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3332b6187abSThara Gopinath }; 3342b6187abSThara Gopinath 3352b6187abSThara Gopinath cpu0_opp9: opp-1036800000 { 3362b6187abSThara Gopinath opp-hz = /bits/ 64 <1036800000>; 3372b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3382b6187abSThara Gopinath }; 3392b6187abSThara Gopinath 3402b6187abSThara Gopinath cpu0_opp10: opp-1113600000 { 3412b6187abSThara Gopinath opp-hz = /bits/ 64 <1113600000>; 3422b6187abSThara Gopinath opp-peak-kBps = <2188000 25804800>; 3432b6187abSThara Gopinath }; 3442b6187abSThara Gopinath 3452b6187abSThara Gopinath cpu0_opp11: opp-1209600000 { 3462b6187abSThara Gopinath opp-hz = /bits/ 64 <1209600000>; 3472b6187abSThara Gopinath opp-peak-kBps = <2188000 31948800>; 3482b6187abSThara Gopinath }; 3492b6187abSThara Gopinath 3502b6187abSThara Gopinath cpu0_opp12: opp-1305600000 { 3512b6187abSThara Gopinath opp-hz = /bits/ 64 <1305600000>; 3522b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3532b6187abSThara Gopinath }; 3542b6187abSThara Gopinath 3552b6187abSThara Gopinath cpu0_opp13: opp-1382400000 { 3562b6187abSThara Gopinath opp-hz = /bits/ 64 <1382400000>; 3572b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3582b6187abSThara Gopinath }; 3592b6187abSThara Gopinath 3602b6187abSThara Gopinath cpu0_opp14: opp-1478400000 { 3612b6187abSThara Gopinath opp-hz = /bits/ 64 <1478400000>; 3622b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3632b6187abSThara Gopinath }; 3642b6187abSThara Gopinath 3652b6187abSThara Gopinath cpu0_opp15: opp-1555200000 { 3662b6187abSThara Gopinath opp-hz = /bits/ 64 <1555200000>; 3672b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3682b6187abSThara Gopinath }; 3692b6187abSThara Gopinath 3702b6187abSThara Gopinath cpu0_opp16: opp-1632000000 { 3712b6187abSThara Gopinath opp-hz = /bits/ 64 <1632000000>; 3722b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3732b6187abSThara Gopinath }; 3742b6187abSThara Gopinath 3752b6187abSThara Gopinath cpu0_opp17: opp-1708800000 { 3762b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 3772b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 3782b6187abSThara Gopinath }; 3792b6187abSThara Gopinath 3802b6187abSThara Gopinath cpu0_opp18: opp-1785600000 { 3812b6187abSThara Gopinath opp-hz = /bits/ 64 <1785600000>; 3822b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 3832b6187abSThara Gopinath }; 3842b6187abSThara Gopinath }; 3852b6187abSThara Gopinath 3862b6187abSThara Gopinath cpu4_opp_table: cpu4_opp_table { 3872b6187abSThara Gopinath compatible = "operating-points-v2"; 3882b6187abSThara Gopinath opp-shared; 3892b6187abSThara Gopinath 3902b6187abSThara Gopinath cpu4_opp1: opp-710400000 { 3912b6187abSThara Gopinath opp-hz = /bits/ 64 <710400000>; 3922b6187abSThara Gopinath opp-peak-kBps = <1804000 15974400>; 3932b6187abSThara Gopinath }; 3942b6187abSThara Gopinath 3952b6187abSThara Gopinath cpu4_opp2: opp-825600000 { 3962b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 3972b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 3982b6187abSThara Gopinath }; 3992b6187abSThara Gopinath 4002b6187abSThara Gopinath cpu4_opp3: opp-940800000 { 4012b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 4022b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 4032b6187abSThara Gopinath }; 4042b6187abSThara Gopinath 4052b6187abSThara Gopinath cpu4_opp4: opp-1056000000 { 4062b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 4072b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 4082b6187abSThara Gopinath }; 4092b6187abSThara Gopinath 4102b6187abSThara Gopinath cpu4_opp5: opp-1171200000 { 4112b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 4122b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 4132b6187abSThara Gopinath }; 4142b6187abSThara Gopinath 4152b6187abSThara Gopinath cpu4_opp6: opp-1286400000 { 4162b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 4172b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4182b6187abSThara Gopinath }; 4192b6187abSThara Gopinath 4202b6187abSThara Gopinath cpu4_opp7: opp-1401600000 { 4212b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 4222b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4232b6187abSThara Gopinath }; 4242b6187abSThara Gopinath 4252b6187abSThara Gopinath cpu4_opp8: opp-1497600000 { 4262b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 4272b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4282b6187abSThara Gopinath }; 4292b6187abSThara Gopinath 4302b6187abSThara Gopinath cpu4_opp9: opp-1612800000 { 4312b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 4322b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4332b6187abSThara Gopinath }; 4342b6187abSThara Gopinath 4352b6187abSThara Gopinath cpu4_opp10: opp-1708800000 { 4362b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 4372b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 4382b6187abSThara Gopinath }; 4392b6187abSThara Gopinath 4402b6187abSThara Gopinath cpu4_opp11: opp-1804800000 { 4412b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 4422b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 4432b6187abSThara Gopinath }; 4442b6187abSThara Gopinath 4452b6187abSThara Gopinath cpu4_opp12: opp-1920000000 { 4462b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 4472b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 4482b6187abSThara Gopinath }; 4492b6187abSThara Gopinath 4502b6187abSThara Gopinath cpu4_opp13: opp-2016000000 { 4512b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 4522b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 4532b6187abSThara Gopinath }; 4542b6187abSThara Gopinath 4552b6187abSThara Gopinath cpu4_opp14: opp-2131200000 { 4562b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 4572b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 4582b6187abSThara Gopinath }; 4592b6187abSThara Gopinath 4602b6187abSThara Gopinath cpu4_opp15: opp-2227200000 { 4612b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 4622b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4632b6187abSThara Gopinath }; 4642b6187abSThara Gopinath 4652b6187abSThara Gopinath cpu4_opp16: opp-2323200000 { 4662b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 4672b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4682b6187abSThara Gopinath }; 4692b6187abSThara Gopinath 4702b6187abSThara Gopinath cpu4_opp17: opp-2419200000 { 4712b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 4722b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4732b6187abSThara Gopinath }; 4742b6187abSThara Gopinath }; 4752b6187abSThara Gopinath 4762b6187abSThara Gopinath cpu7_opp_table: cpu7_opp_table { 4772b6187abSThara Gopinath compatible = "operating-points-v2"; 4782b6187abSThara Gopinath opp-shared; 4792b6187abSThara Gopinath 4802b6187abSThara Gopinath cpu7_opp1: opp-825600000 { 4812b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 4822b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 4832b6187abSThara Gopinath }; 4842b6187abSThara Gopinath 4852b6187abSThara Gopinath cpu7_opp2: opp-940800000 { 4862b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 4872b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 4882b6187abSThara Gopinath }; 4892b6187abSThara Gopinath 4902b6187abSThara Gopinath cpu7_opp3: opp-1056000000 { 4912b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 4922b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 4932b6187abSThara Gopinath }; 4942b6187abSThara Gopinath 4952b6187abSThara Gopinath cpu7_opp4: opp-1171200000 { 4962b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 4972b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 4982b6187abSThara Gopinath }; 4992b6187abSThara Gopinath 5002b6187abSThara Gopinath cpu7_opp5: opp-1286400000 { 5012b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 5022b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5032b6187abSThara Gopinath }; 5042b6187abSThara Gopinath 5052b6187abSThara Gopinath cpu7_opp6: opp-1401600000 { 5062b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 5072b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5082b6187abSThara Gopinath }; 5092b6187abSThara Gopinath 5102b6187abSThara Gopinath cpu7_opp7: opp-1497600000 { 5112b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 5122b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5132b6187abSThara Gopinath }; 5142b6187abSThara Gopinath 5152b6187abSThara Gopinath cpu7_opp8: opp-1612800000 { 5162b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 5172b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5182b6187abSThara Gopinath }; 5192b6187abSThara Gopinath 5202b6187abSThara Gopinath cpu7_opp9: opp-1708800000 { 5212b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 5222b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 5232b6187abSThara Gopinath }; 5242b6187abSThara Gopinath 5252b6187abSThara Gopinath cpu7_opp10: opp-1804800000 { 5262b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 5272b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 5282b6187abSThara Gopinath }; 5292b6187abSThara Gopinath 5302b6187abSThara Gopinath cpu7_opp11: opp-1920000000 { 5312b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 5322b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 5332b6187abSThara Gopinath }; 5342b6187abSThara Gopinath 5352b6187abSThara Gopinath cpu7_opp12: opp-2016000000 { 5362b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 5372b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 5382b6187abSThara Gopinath }; 5392b6187abSThara Gopinath 5402b6187abSThara Gopinath cpu7_opp13: opp-2131200000 { 5412b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 5422b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 5432b6187abSThara Gopinath }; 5442b6187abSThara Gopinath 5452b6187abSThara Gopinath cpu7_opp14: opp-2227200000 { 5462b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 5472b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5482b6187abSThara Gopinath }; 5492b6187abSThara Gopinath 5502b6187abSThara Gopinath cpu7_opp15: opp-2323200000 { 5512b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 5522b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5532b6187abSThara Gopinath }; 5542b6187abSThara Gopinath 5552b6187abSThara Gopinath cpu7_opp16: opp-2419200000 { 5562b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 5572b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5582b6187abSThara Gopinath }; 5592b6187abSThara Gopinath 5602b6187abSThara Gopinath cpu7_opp17: opp-2534400000 { 5612b6187abSThara Gopinath opp-hz = /bits/ 64 <2534400000>; 5622b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5632b6187abSThara Gopinath }; 5642b6187abSThara Gopinath 5652b6187abSThara Gopinath cpu7_opp18: opp-2649600000 { 5662b6187abSThara Gopinath opp-hz = /bits/ 64 <2649600000>; 5672b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5682b6187abSThara Gopinath }; 5692b6187abSThara Gopinath 5702b6187abSThara Gopinath cpu7_opp19: opp-2745600000 { 5712b6187abSThara Gopinath opp-hz = /bits/ 64 <2745600000>; 5722b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5732b6187abSThara Gopinath }; 5742b6187abSThara Gopinath 5752b6187abSThara Gopinath cpu7_opp20: opp-2841600000 { 5762b6187abSThara Gopinath opp-hz = /bits/ 64 <2841600000>; 5772b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5782b6187abSThara Gopinath }; 5792b6187abSThara Gopinath }; 5802b6187abSThara Gopinath 581e13c6d14SVinod Koul firmware { 582e13c6d14SVinod Koul scm: scm { 583e13c6d14SVinod Koul compatible = "qcom,scm-sm8150", "qcom,scm"; 584e13c6d14SVinod Koul #reset-cells = <1>; 585e13c6d14SVinod Koul }; 586e13c6d14SVinod Koul }; 587e13c6d14SVinod Koul 588d8cf9372SVinod Koul tcsr_mutex: hwlock { 589d8cf9372SVinod Koul compatible = "qcom,tcsr-mutex"; 590d8cf9372SVinod Koul syscon = <&tcsr_mutex_regs 0 0x1000>; 591d8cf9372SVinod Koul #hwlock-cells = <1>; 592d8cf9372SVinod Koul }; 593d8cf9372SVinod Koul 594e13c6d14SVinod Koul memory@80000000 { 595e13c6d14SVinod Koul device_type = "memory"; 596e13c6d14SVinod Koul /* We expect the bootloader to fill in the size */ 597e13c6d14SVinod Koul reg = <0x0 0x80000000 0x0 0x0>; 598e13c6d14SVinod Koul }; 599e13c6d14SVinod Koul 600d8cf9372SVinod Koul pmu { 601d8cf9372SVinod Koul compatible = "arm,armv8-pmuv3"; 602d8cf9372SVinod Koul interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 603d8cf9372SVinod Koul }; 604d8cf9372SVinod Koul 605e13c6d14SVinod Koul psci { 606e13c6d14SVinod Koul compatible = "arm,psci-1.0"; 607e13c6d14SVinod Koul method = "smc"; 608b2e3f897SDanny Lin 609b2e3f897SDanny Lin CPU_PD0: cpu0 { 610b2e3f897SDanny Lin #power-domain-cells = <0>; 611b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 612b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 613b2e3f897SDanny Lin }; 614b2e3f897SDanny Lin 615b2e3f897SDanny Lin CPU_PD1: cpu1 { 616b2e3f897SDanny Lin #power-domain-cells = <0>; 617b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 618b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 619b2e3f897SDanny Lin }; 620b2e3f897SDanny Lin 621b2e3f897SDanny Lin CPU_PD2: cpu2 { 622b2e3f897SDanny Lin #power-domain-cells = <0>; 623b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 624b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 625b2e3f897SDanny Lin }; 626b2e3f897SDanny Lin 627b2e3f897SDanny Lin CPU_PD3: cpu3 { 628b2e3f897SDanny Lin #power-domain-cells = <0>; 629b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 630b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 631b2e3f897SDanny Lin }; 632b2e3f897SDanny Lin 633b2e3f897SDanny Lin CPU_PD4: cpu4 { 634b2e3f897SDanny Lin #power-domain-cells = <0>; 635b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 636b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 637b2e3f897SDanny Lin }; 638b2e3f897SDanny Lin 639b2e3f897SDanny Lin CPU_PD5: cpu5 { 640b2e3f897SDanny Lin #power-domain-cells = <0>; 641b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 642b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 643b2e3f897SDanny Lin }; 644b2e3f897SDanny Lin 645b2e3f897SDanny Lin CPU_PD6: cpu6 { 646b2e3f897SDanny Lin #power-domain-cells = <0>; 647b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 648b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 649b2e3f897SDanny Lin }; 650b2e3f897SDanny Lin 651b2e3f897SDanny Lin CPU_PD7: cpu7 { 652b2e3f897SDanny Lin #power-domain-cells = <0>; 653b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 654b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 655b2e3f897SDanny Lin }; 656b2e3f897SDanny Lin 657b2e3f897SDanny Lin CLUSTER_PD: cpu-cluster0 { 658b2e3f897SDanny Lin #power-domain-cells = <0>; 659b2e3f897SDanny Lin domain-idle-states = <&CLUSTER_SLEEP_0>; 660b2e3f897SDanny Lin }; 661e13c6d14SVinod Koul }; 662e13c6d14SVinod Koul 663912c373aSVinod Koul reserved-memory { 664912c373aSVinod Koul #address-cells = <2>; 665912c373aSVinod Koul #size-cells = <2>; 666912c373aSVinod Koul ranges; 667912c373aSVinod Koul 668912c373aSVinod Koul hyp_mem: memory@85700000 { 669912c373aSVinod Koul reg = <0x0 0x85700000 0x0 0x600000>; 670912c373aSVinod Koul no-map; 671912c373aSVinod Koul }; 672912c373aSVinod Koul 673912c373aSVinod Koul xbl_mem: memory@85d00000 { 674912c373aSVinod Koul reg = <0x0 0x85d00000 0x0 0x140000>; 675912c373aSVinod Koul no-map; 676912c373aSVinod Koul }; 677912c373aSVinod Koul 678912c373aSVinod Koul aop_mem: memory@85f00000 { 679912c373aSVinod Koul reg = <0x0 0x85f00000 0x0 0x20000>; 680912c373aSVinod Koul no-map; 681912c373aSVinod Koul }; 682912c373aSVinod Koul 683912c373aSVinod Koul aop_cmd_db: memory@85f20000 { 684912c373aSVinod Koul compatible = "qcom,cmd-db"; 685912c373aSVinod Koul reg = <0x0 0x85f20000 0x0 0x20000>; 686912c373aSVinod Koul no-map; 687912c373aSVinod Koul }; 688912c373aSVinod Koul 689912c373aSVinod Koul smem_mem: memory@86000000 { 690912c373aSVinod Koul reg = <0x0 0x86000000 0x0 0x200000>; 691912c373aSVinod Koul no-map; 692912c373aSVinod Koul }; 693912c373aSVinod Koul 694912c373aSVinod Koul tz_mem: memory@86200000 { 695912c373aSVinod Koul reg = <0x0 0x86200000 0x0 0x3900000>; 696912c373aSVinod Koul no-map; 697912c373aSVinod Koul }; 698912c373aSVinod Koul 699912c373aSVinod Koul rmtfs_mem: memory@89b00000 { 700912c373aSVinod Koul compatible = "qcom,rmtfs-mem"; 701912c373aSVinod Koul reg = <0x0 0x89b00000 0x0 0x200000>; 702912c373aSVinod Koul no-map; 703912c373aSVinod Koul 704912c373aSVinod Koul qcom,client-id = <1>; 705912c373aSVinod Koul qcom,vmid = <15>; 706912c373aSVinod Koul }; 707912c373aSVinod Koul 708912c373aSVinod Koul camera_mem: memory@8b700000 { 709912c373aSVinod Koul reg = <0x0 0x8b700000 0x0 0x500000>; 710912c373aSVinod Koul no-map; 711912c373aSVinod Koul }; 712912c373aSVinod Koul 713912c373aSVinod Koul wlan_mem: memory@8bc00000 { 714912c373aSVinod Koul reg = <0x0 0x8bc00000 0x0 0x180000>; 715912c373aSVinod Koul no-map; 716912c373aSVinod Koul }; 717912c373aSVinod Koul 718912c373aSVinod Koul npu_mem: memory@8bd80000 { 719912c373aSVinod Koul reg = <0x0 0x8bd80000 0x0 0x80000>; 720912c373aSVinod Koul no-map; 721912c373aSVinod Koul }; 722912c373aSVinod Koul 723912c373aSVinod Koul adsp_mem: memory@8be00000 { 724912c373aSVinod Koul reg = <0x0 0x8be00000 0x0 0x1a00000>; 725912c373aSVinod Koul no-map; 726912c373aSVinod Koul }; 727912c373aSVinod Koul 728912c373aSVinod Koul mpss_mem: memory@8d800000 { 729912c373aSVinod Koul reg = <0x0 0x8d800000 0x0 0x9600000>; 730912c373aSVinod Koul no-map; 731912c373aSVinod Koul }; 732912c373aSVinod Koul 733912c373aSVinod Koul venus_mem: memory@96e00000 { 734912c373aSVinod Koul reg = <0x0 0x96e00000 0x0 0x500000>; 735912c373aSVinod Koul no-map; 736912c373aSVinod Koul }; 737912c373aSVinod Koul 738912c373aSVinod Koul slpi_mem: memory@97300000 { 739912c373aSVinod Koul reg = <0x0 0x97300000 0x0 0x1400000>; 740912c373aSVinod Koul no-map; 741912c373aSVinod Koul }; 742912c373aSVinod Koul 743912c373aSVinod Koul ipa_fw_mem: memory@98700000 { 744912c373aSVinod Koul reg = <0x0 0x98700000 0x0 0x10000>; 745912c373aSVinod Koul no-map; 746912c373aSVinod Koul }; 747912c373aSVinod Koul 748912c373aSVinod Koul ipa_gsi_mem: memory@98710000 { 749912c373aSVinod Koul reg = <0x0 0x98710000 0x0 0x5000>; 750912c373aSVinod Koul no-map; 751912c373aSVinod Koul }; 752912c373aSVinod Koul 753912c373aSVinod Koul gpu_mem: memory@98715000 { 754912c373aSVinod Koul reg = <0x0 0x98715000 0x0 0x2000>; 755912c373aSVinod Koul no-map; 756912c373aSVinod Koul }; 757912c373aSVinod Koul 758912c373aSVinod Koul spss_mem: memory@98800000 { 759912c373aSVinod Koul reg = <0x0 0x98800000 0x0 0x100000>; 760912c373aSVinod Koul no-map; 761912c373aSVinod Koul }; 762912c373aSVinod Koul 763912c373aSVinod Koul cdsp_mem: memory@98900000 { 764912c373aSVinod Koul reg = <0x0 0x98900000 0x0 0x1400000>; 765912c373aSVinod Koul no-map; 766912c373aSVinod Koul }; 767912c373aSVinod Koul 768912c373aSVinod Koul qseecom_mem: memory@9e400000 { 769912c373aSVinod Koul reg = <0x0 0x9e400000 0x0 0x1400000>; 770912c373aSVinod Koul no-map; 771912c373aSVinod Koul }; 772912c373aSVinod Koul }; 773912c373aSVinod Koul 774d8cf9372SVinod Koul smem { 775d8cf9372SVinod Koul compatible = "qcom,smem"; 776d8cf9372SVinod Koul memory-region = <&smem_mem>; 777d8cf9372SVinod Koul hwlocks = <&tcsr_mutex 3>; 778d8cf9372SVinod Koul }; 779d8cf9372SVinod Koul 78061025b81SSibi Sankar smp2p-cdsp { 78161025b81SSibi Sankar compatible = "qcom,smp2p"; 78261025b81SSibi Sankar qcom,smem = <94>, <432>; 78361025b81SSibi Sankar 78461025b81SSibi Sankar interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 78561025b81SSibi Sankar 78661025b81SSibi Sankar mboxes = <&apss_shared 6>; 78761025b81SSibi Sankar 78861025b81SSibi Sankar qcom,local-pid = <0>; 78961025b81SSibi Sankar qcom,remote-pid = <5>; 79061025b81SSibi Sankar 79161025b81SSibi Sankar cdsp_smp2p_out: master-kernel { 79261025b81SSibi Sankar qcom,entry-name = "master-kernel"; 79361025b81SSibi Sankar #qcom,smem-state-cells = <1>; 79461025b81SSibi Sankar }; 79561025b81SSibi Sankar 79661025b81SSibi Sankar cdsp_smp2p_in: slave-kernel { 79761025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 79861025b81SSibi Sankar 79961025b81SSibi Sankar interrupt-controller; 80061025b81SSibi Sankar #interrupt-cells = <2>; 80161025b81SSibi Sankar }; 80261025b81SSibi Sankar }; 80361025b81SSibi Sankar 80461025b81SSibi Sankar smp2p-lpass { 80561025b81SSibi Sankar compatible = "qcom,smp2p"; 80661025b81SSibi Sankar qcom,smem = <443>, <429>; 80761025b81SSibi Sankar 80861025b81SSibi Sankar interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 80961025b81SSibi Sankar 81061025b81SSibi Sankar mboxes = <&apss_shared 10>; 81161025b81SSibi Sankar 81261025b81SSibi Sankar qcom,local-pid = <0>; 81361025b81SSibi Sankar qcom,remote-pid = <2>; 81461025b81SSibi Sankar 81561025b81SSibi Sankar adsp_smp2p_out: master-kernel { 81661025b81SSibi Sankar qcom,entry-name = "master-kernel"; 81761025b81SSibi Sankar #qcom,smem-state-cells = <1>; 81861025b81SSibi Sankar }; 81961025b81SSibi Sankar 82061025b81SSibi Sankar adsp_smp2p_in: slave-kernel { 82161025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 82261025b81SSibi Sankar 82361025b81SSibi Sankar interrupt-controller; 82461025b81SSibi Sankar #interrupt-cells = <2>; 82561025b81SSibi Sankar }; 82661025b81SSibi Sankar }; 82761025b81SSibi Sankar 82861025b81SSibi Sankar smp2p-mpss { 82961025b81SSibi Sankar compatible = "qcom,smp2p"; 83061025b81SSibi Sankar qcom,smem = <435>, <428>; 83161025b81SSibi Sankar 83261025b81SSibi Sankar interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 83361025b81SSibi Sankar 83461025b81SSibi Sankar mboxes = <&apss_shared 14>; 83561025b81SSibi Sankar 83661025b81SSibi Sankar qcom,local-pid = <0>; 83761025b81SSibi Sankar qcom,remote-pid = <1>; 83861025b81SSibi Sankar 83961025b81SSibi Sankar modem_smp2p_out: master-kernel { 84061025b81SSibi Sankar qcom,entry-name = "master-kernel"; 84161025b81SSibi Sankar #qcom,smem-state-cells = <1>; 84261025b81SSibi Sankar }; 84361025b81SSibi Sankar 84461025b81SSibi Sankar modem_smp2p_in: slave-kernel { 84561025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 84661025b81SSibi Sankar 84761025b81SSibi Sankar interrupt-controller; 84861025b81SSibi Sankar #interrupt-cells = <2>; 84961025b81SSibi Sankar }; 85061025b81SSibi Sankar }; 85161025b81SSibi Sankar 85261025b81SSibi Sankar smp2p-slpi { 85361025b81SSibi Sankar compatible = "qcom,smp2p"; 85461025b81SSibi Sankar qcom,smem = <481>, <430>; 85561025b81SSibi Sankar 85661025b81SSibi Sankar interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 85761025b81SSibi Sankar 85861025b81SSibi Sankar mboxes = <&apss_shared 26>; 85961025b81SSibi Sankar 86061025b81SSibi Sankar qcom,local-pid = <0>; 86161025b81SSibi Sankar qcom,remote-pid = <3>; 86261025b81SSibi Sankar 86361025b81SSibi Sankar slpi_smp2p_out: master-kernel { 86461025b81SSibi Sankar qcom,entry-name = "master-kernel"; 86561025b81SSibi Sankar #qcom,smem-state-cells = <1>; 86661025b81SSibi Sankar }; 86761025b81SSibi Sankar 86861025b81SSibi Sankar slpi_smp2p_in: slave-kernel { 86961025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 87061025b81SSibi Sankar 87161025b81SSibi Sankar interrupt-controller; 87261025b81SSibi Sankar #interrupt-cells = <2>; 87361025b81SSibi Sankar }; 87461025b81SSibi Sankar }; 87561025b81SSibi Sankar 876e13c6d14SVinod Koul soc: soc@0 { 877e13c6d14SVinod Koul #address-cells = <2>; 878e13c6d14SVinod Koul #size-cells = <2>; 879e13c6d14SVinod Koul ranges = <0 0 0 0 0x10 0>; 880e13c6d14SVinod Koul dma-ranges = <0 0 0 0 0x10 0>; 881e13c6d14SVinod Koul compatible = "simple-bus"; 882e13c6d14SVinod Koul 883e13c6d14SVinod Koul gcc: clock-controller@100000 { 884e13c6d14SVinod Koul compatible = "qcom,gcc-sm8150"; 885e13c6d14SVinod Koul reg = <0x0 0x00100000 0x0 0x1f0000>; 886e13c6d14SVinod Koul #clock-cells = <1>; 887e13c6d14SVinod Koul #reset-cells = <1>; 888e13c6d14SVinod Koul #power-domain-cells = <1>; 889e13c6d14SVinod Koul clock-names = "bi_tcxo", 890e13c6d14SVinod Koul "sleep_clk"; 891e13c6d14SVinod Koul clocks = <&rpmhcc RPMH_CXO_CLK>, 892e13c6d14SVinod Koul <&sleep_clk>; 893e13c6d14SVinod Koul }; 894e13c6d14SVinod Koul 89505006290SFelipe Balbi gpi_dma0: dma-controller@800000 { 89605006290SFelipe Balbi compatible = "qcom,sm8150-gpi-dma"; 89705006290SFelipe Balbi reg = <0 0x800000 0 0x60000>; 89805006290SFelipe Balbi interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 89905006290SFelipe Balbi <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 90005006290SFelipe Balbi <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 90105006290SFelipe Balbi <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 90205006290SFelipe Balbi <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 90305006290SFelipe Balbi <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 90405006290SFelipe Balbi <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 90505006290SFelipe Balbi <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 90605006290SFelipe Balbi <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 90705006290SFelipe Balbi <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 90805006290SFelipe Balbi <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 90905006290SFelipe Balbi <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 91005006290SFelipe Balbi <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 91105006290SFelipe Balbi dma-channels = <13>; 91205006290SFelipe Balbi dma-channel-mask = <0xfa>; 91305006290SFelipe Balbi iommus = <&apps_smmu 0x00d6 0x0>; 91405006290SFelipe Balbi #dma-cells = <3>; 91505006290SFelipe Balbi status = "disabled"; 91605006290SFelipe Balbi }; 91705006290SFelipe Balbi 9189cf3ebd1SCaleb Connolly qupv3_id_0: geniqup@8c0000 { 9199cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 9209cf3ebd1SCaleb Connolly reg = <0x0 0x008c0000 0x0 0x6000>; 9219cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 9229cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 9239cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 9249cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0xc3 0x0>; 9259cf3ebd1SCaleb Connolly #address-cells = <2>; 9269cf3ebd1SCaleb Connolly #size-cells = <2>; 9279cf3ebd1SCaleb Connolly ranges; 9289cf3ebd1SCaleb Connolly status = "disabled"; 92981bee695SCaleb Connolly 93081bee695SCaleb Connolly i2c0: i2c@880000 { 93181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 93281bee695SCaleb Connolly reg = <0 0x00880000 0 0x4000>; 93381bee695SCaleb Connolly clock-names = "se"; 93481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 935abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 936abdd4b7aSFelipe Balbi <&gpi_dma0 1 0 QCOM_GPI_I2C>; 937abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 93881bee695SCaleb Connolly pinctrl-names = "default"; 93981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c0_default>; 94081bee695SCaleb Connolly interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 94181bee695SCaleb Connolly #address-cells = <1>; 94281bee695SCaleb Connolly #size-cells = <0>; 94381bee695SCaleb Connolly status = "disabled"; 94481bee695SCaleb Connolly }; 94581bee695SCaleb Connolly 946129e1c96SFelipe Balbi spi0: spi@880000 { 947129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 948129e1c96SFelipe Balbi reg = <0 0x880000 0 0x4000>; 949129e1c96SFelipe Balbi reg-names = "se"; 950129e1c96SFelipe Balbi clock-names = "se"; 951129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 952abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 953abdd4b7aSFelipe Balbi <&gpi_dma0 1 0 QCOM_GPI_SPI>; 954abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 955129e1c96SFelipe Balbi pinctrl-names = "default"; 956129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi0_default>; 957129e1c96SFelipe Balbi interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 958129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 959129e1c96SFelipe Balbi #address-cells = <1>; 960129e1c96SFelipe Balbi #size-cells = <0>; 961129e1c96SFelipe Balbi status = "disabled"; 962129e1c96SFelipe Balbi }; 963129e1c96SFelipe Balbi 96481bee695SCaleb Connolly i2c1: i2c@884000 { 96581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 96681bee695SCaleb Connolly reg = <0 0x00884000 0 0x4000>; 96781bee695SCaleb Connolly clock-names = "se"; 96881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 969abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 970abdd4b7aSFelipe Balbi <&gpi_dma0 1 1 QCOM_GPI_I2C>; 971abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 97281bee695SCaleb Connolly pinctrl-names = "default"; 97381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c1_default>; 97481bee695SCaleb Connolly interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 97581bee695SCaleb Connolly #address-cells = <1>; 97681bee695SCaleb Connolly #size-cells = <0>; 97781bee695SCaleb Connolly status = "disabled"; 97881bee695SCaleb Connolly }; 97981bee695SCaleb Connolly 980129e1c96SFelipe Balbi spi1: spi@884000 { 981129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 982129e1c96SFelipe Balbi reg = <0 0x884000 0 0x4000>; 983129e1c96SFelipe Balbi reg-names = "se"; 984129e1c96SFelipe Balbi clock-names = "se"; 985129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 986abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 987abdd4b7aSFelipe Balbi <&gpi_dma0 1 1 QCOM_GPI_SPI>; 988abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 989129e1c96SFelipe Balbi pinctrl-names = "default"; 990129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi1_default>; 991129e1c96SFelipe Balbi interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 992129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 993129e1c96SFelipe Balbi #address-cells = <1>; 994129e1c96SFelipe Balbi #size-cells = <0>; 995129e1c96SFelipe Balbi status = "disabled"; 996129e1c96SFelipe Balbi }; 997129e1c96SFelipe Balbi 99881bee695SCaleb Connolly i2c2: i2c@888000 { 99981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 100081bee695SCaleb Connolly reg = <0 0x00888000 0 0x4000>; 100181bee695SCaleb Connolly clock-names = "se"; 100281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1003abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1004abdd4b7aSFelipe Balbi <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1005abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 100681bee695SCaleb Connolly pinctrl-names = "default"; 100781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c2_default>; 100881bee695SCaleb Connolly interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 100981bee695SCaleb Connolly #address-cells = <1>; 101081bee695SCaleb Connolly #size-cells = <0>; 101181bee695SCaleb Connolly status = "disabled"; 101281bee695SCaleb Connolly }; 101381bee695SCaleb Connolly 1014129e1c96SFelipe Balbi spi2: spi@888000 { 1015129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1016129e1c96SFelipe Balbi reg = <0 0x888000 0 0x4000>; 1017129e1c96SFelipe Balbi reg-names = "se"; 1018129e1c96SFelipe Balbi clock-names = "se"; 1019129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1020abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1021abdd4b7aSFelipe Balbi <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1022abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1023129e1c96SFelipe Balbi pinctrl-names = "default"; 1024129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi2_default>; 1025129e1c96SFelipe Balbi interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1026129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1027129e1c96SFelipe Balbi #address-cells = <1>; 1028129e1c96SFelipe Balbi #size-cells = <0>; 1029129e1c96SFelipe Balbi status = "disabled"; 1030129e1c96SFelipe Balbi }; 1031129e1c96SFelipe Balbi 103281bee695SCaleb Connolly i2c3: i2c@88c000 { 103381bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 103481bee695SCaleb Connolly reg = <0 0x0088c000 0 0x4000>; 103581bee695SCaleb Connolly clock-names = "se"; 103681bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1037abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1038abdd4b7aSFelipe Balbi <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1039abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 104081bee695SCaleb Connolly pinctrl-names = "default"; 104181bee695SCaleb Connolly pinctrl-0 = <&qup_i2c3_default>; 104281bee695SCaleb Connolly interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 104381bee695SCaleb Connolly #address-cells = <1>; 104481bee695SCaleb Connolly #size-cells = <0>; 104581bee695SCaleb Connolly status = "disabled"; 104681bee695SCaleb Connolly }; 104781bee695SCaleb Connolly 1048129e1c96SFelipe Balbi spi3: spi@88c000 { 1049129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1050129e1c96SFelipe Balbi reg = <0 0x88c000 0 0x4000>; 1051129e1c96SFelipe Balbi reg-names = "se"; 1052129e1c96SFelipe Balbi clock-names = "se"; 1053129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1054abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1055abdd4b7aSFelipe Balbi <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1056abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1057129e1c96SFelipe Balbi pinctrl-names = "default"; 1058129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi3_default>; 1059129e1c96SFelipe Balbi interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1060129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1061129e1c96SFelipe Balbi #address-cells = <1>; 1062129e1c96SFelipe Balbi #size-cells = <0>; 1063129e1c96SFelipe Balbi status = "disabled"; 1064129e1c96SFelipe Balbi }; 1065129e1c96SFelipe Balbi 106681bee695SCaleb Connolly i2c4: i2c@890000 { 106781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 106881bee695SCaleb Connolly reg = <0 0x00890000 0 0x4000>; 106981bee695SCaleb Connolly clock-names = "se"; 107081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1071abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1072abdd4b7aSFelipe Balbi <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1073abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 107481bee695SCaleb Connolly pinctrl-names = "default"; 107581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c4_default>; 107681bee695SCaleb Connolly interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 107781bee695SCaleb Connolly #address-cells = <1>; 107881bee695SCaleb Connolly #size-cells = <0>; 107981bee695SCaleb Connolly status = "disabled"; 108081bee695SCaleb Connolly }; 108181bee695SCaleb Connolly 1082129e1c96SFelipe Balbi spi4: spi@890000 { 1083129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1084129e1c96SFelipe Balbi reg = <0 0x890000 0 0x4000>; 1085129e1c96SFelipe Balbi reg-names = "se"; 1086129e1c96SFelipe Balbi clock-names = "se"; 1087129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1088abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1089abdd4b7aSFelipe Balbi <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1090abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1091129e1c96SFelipe Balbi pinctrl-names = "default"; 1092129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi4_default>; 1093129e1c96SFelipe Balbi interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1094129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1095129e1c96SFelipe Balbi #address-cells = <1>; 1096129e1c96SFelipe Balbi #size-cells = <0>; 1097129e1c96SFelipe Balbi status = "disabled"; 1098129e1c96SFelipe Balbi }; 1099129e1c96SFelipe Balbi 110081bee695SCaleb Connolly i2c5: i2c@894000 { 110181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 110281bee695SCaleb Connolly reg = <0 0x00894000 0 0x4000>; 110381bee695SCaleb Connolly clock-names = "se"; 110481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1105abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1106abdd4b7aSFelipe Balbi <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1107abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 110881bee695SCaleb Connolly pinctrl-names = "default"; 110981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c5_default>; 111081bee695SCaleb Connolly interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 111181bee695SCaleb Connolly #address-cells = <1>; 111281bee695SCaleb Connolly #size-cells = <0>; 111381bee695SCaleb Connolly status = "disabled"; 111481bee695SCaleb Connolly }; 111581bee695SCaleb Connolly 1116129e1c96SFelipe Balbi spi5: spi@894000 { 1117129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1118129e1c96SFelipe Balbi reg = <0 0x894000 0 0x4000>; 1119129e1c96SFelipe Balbi reg-names = "se"; 1120129e1c96SFelipe Balbi clock-names = "se"; 1121129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1122abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1123abdd4b7aSFelipe Balbi <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1124abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1125129e1c96SFelipe Balbi pinctrl-names = "default"; 1126129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi5_default>; 1127129e1c96SFelipe Balbi interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1128129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1129129e1c96SFelipe Balbi #address-cells = <1>; 1130129e1c96SFelipe Balbi #size-cells = <0>; 1131129e1c96SFelipe Balbi status = "disabled"; 1132129e1c96SFelipe Balbi }; 1133129e1c96SFelipe Balbi 113481bee695SCaleb Connolly i2c6: i2c@898000 { 113581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 113681bee695SCaleb Connolly reg = <0 0x00898000 0 0x4000>; 113781bee695SCaleb Connolly clock-names = "se"; 113881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1139abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1140abdd4b7aSFelipe Balbi <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1141abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 114281bee695SCaleb Connolly pinctrl-names = "default"; 114381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c6_default>; 114481bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 114581bee695SCaleb Connolly #address-cells = <1>; 114681bee695SCaleb Connolly #size-cells = <0>; 114781bee695SCaleb Connolly status = "disabled"; 114881bee695SCaleb Connolly }; 114981bee695SCaleb Connolly 1150129e1c96SFelipe Balbi spi6: spi@898000 { 1151129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1152129e1c96SFelipe Balbi reg = <0 0x898000 0 0x4000>; 1153129e1c96SFelipe Balbi reg-names = "se"; 1154129e1c96SFelipe Balbi clock-names = "se"; 1155129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1156abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1157abdd4b7aSFelipe Balbi <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1158abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1159129e1c96SFelipe Balbi pinctrl-names = "default"; 1160129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi6_default>; 1161129e1c96SFelipe Balbi interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1162129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1163129e1c96SFelipe Balbi #address-cells = <1>; 1164129e1c96SFelipe Balbi #size-cells = <0>; 1165129e1c96SFelipe Balbi status = "disabled"; 1166129e1c96SFelipe Balbi }; 1167129e1c96SFelipe Balbi 116881bee695SCaleb Connolly i2c7: i2c@89c000 { 116981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 117081bee695SCaleb Connolly reg = <0 0x0089c000 0 0x4000>; 117181bee695SCaleb Connolly clock-names = "se"; 117281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1173abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1174abdd4b7aSFelipe Balbi <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1175abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 117681bee695SCaleb Connolly pinctrl-names = "default"; 117781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c7_default>; 117881bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 117981bee695SCaleb Connolly #address-cells = <1>; 118081bee695SCaleb Connolly #size-cells = <0>; 118181bee695SCaleb Connolly status = "disabled"; 118281bee695SCaleb Connolly }; 118381bee695SCaleb Connolly 1184129e1c96SFelipe Balbi spi7: spi@89c000 { 1185129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1186129e1c96SFelipe Balbi reg = <0 0x89c000 0 0x4000>; 1187129e1c96SFelipe Balbi reg-names = "se"; 1188129e1c96SFelipe Balbi clock-names = "se"; 1189129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1190abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1191abdd4b7aSFelipe Balbi <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1192abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1193129e1c96SFelipe Balbi pinctrl-names = "default"; 1194129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi7_default>; 1195129e1c96SFelipe Balbi interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1196129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1197129e1c96SFelipe Balbi #address-cells = <1>; 1198129e1c96SFelipe Balbi #size-cells = <0>; 1199129e1c96SFelipe Balbi status = "disabled"; 1200129e1c96SFelipe Balbi }; 12019cf3ebd1SCaleb Connolly }; 12029cf3ebd1SCaleb Connolly 120305006290SFelipe Balbi gpi_dma1: dma-controller@a00000 { 120405006290SFelipe Balbi compatible = "qcom,sm8150-gpi-dma"; 120505006290SFelipe Balbi reg = <0 0xa00000 0 0x60000>; 120605006290SFelipe Balbi interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 120705006290SFelipe Balbi <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 120805006290SFelipe Balbi <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 120905006290SFelipe Balbi <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 121005006290SFelipe Balbi <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 121105006290SFelipe Balbi <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 121205006290SFelipe Balbi <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 121305006290SFelipe Balbi <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 121405006290SFelipe Balbi <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 121505006290SFelipe Balbi <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 121605006290SFelipe Balbi <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 121705006290SFelipe Balbi <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 121805006290SFelipe Balbi <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 121905006290SFelipe Balbi dma-channels = <13>; 122005006290SFelipe Balbi dma-channel-mask = <0xfa>; 122105006290SFelipe Balbi iommus = <&apps_smmu 0x0616 0x0>; 122205006290SFelipe Balbi #dma-cells = <3>; 122305006290SFelipe Balbi status = "disabled"; 122405006290SFelipe Balbi }; 122505006290SFelipe Balbi 1226e13c6d14SVinod Koul qupv3_id_1: geniqup@ac0000 { 1227e13c6d14SVinod Koul compatible = "qcom,geni-se-qup"; 1228e13c6d14SVinod Koul reg = <0x0 0x00ac0000 0x0 0x6000>; 1229e13c6d14SVinod Koul clock-names = "m-ahb", "s-ahb"; 1230d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1231d6f55763SVinod Koul <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 12329cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x603 0x0>; 1233e13c6d14SVinod Koul #address-cells = <2>; 1234e13c6d14SVinod Koul #size-cells = <2>; 1235e13c6d14SVinod Koul ranges; 1236e13c6d14SVinod Koul status = "disabled"; 1237e13c6d14SVinod Koul 123881bee695SCaleb Connolly i2c8: i2c@a80000 { 123981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 124081bee695SCaleb Connolly reg = <0 0x00a80000 0 0x4000>; 124181bee695SCaleb Connolly clock-names = "se"; 124281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1243abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1244abdd4b7aSFelipe Balbi <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1245abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 124681bee695SCaleb Connolly pinctrl-names = "default"; 124781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c8_default>; 124881bee695SCaleb Connolly interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 124981bee695SCaleb Connolly #address-cells = <1>; 125081bee695SCaleb Connolly #size-cells = <0>; 125181bee695SCaleb Connolly status = "disabled"; 125281bee695SCaleb Connolly }; 125381bee695SCaleb Connolly 1254129e1c96SFelipe Balbi spi8: spi@a80000 { 1255129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1256129e1c96SFelipe Balbi reg = <0 0xa80000 0 0x4000>; 1257129e1c96SFelipe Balbi reg-names = "se"; 1258129e1c96SFelipe Balbi clock-names = "se"; 1259129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1260abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1261abdd4b7aSFelipe Balbi <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1262abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1263129e1c96SFelipe Balbi pinctrl-names = "default"; 1264129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi8_default>; 1265129e1c96SFelipe Balbi interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1266129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1267129e1c96SFelipe Balbi #address-cells = <1>; 1268129e1c96SFelipe Balbi #size-cells = <0>; 1269129e1c96SFelipe Balbi status = "disabled"; 1270129e1c96SFelipe Balbi }; 1271129e1c96SFelipe Balbi 127281bee695SCaleb Connolly i2c9: i2c@a84000 { 127381bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 127481bee695SCaleb Connolly reg = <0 0x00a84000 0 0x4000>; 127581bee695SCaleb Connolly clock-names = "se"; 127681bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1277abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1278abdd4b7aSFelipe Balbi <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1279abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 128081bee695SCaleb Connolly pinctrl-names = "default"; 128181bee695SCaleb Connolly pinctrl-0 = <&qup_i2c9_default>; 128281bee695SCaleb Connolly interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 128381bee695SCaleb Connolly #address-cells = <1>; 128481bee695SCaleb Connolly #size-cells = <0>; 128581bee695SCaleb Connolly status = "disabled"; 128681bee695SCaleb Connolly }; 128781bee695SCaleb Connolly 1288129e1c96SFelipe Balbi spi9: spi@a84000 { 1289129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1290129e1c96SFelipe Balbi reg = <0 0xa84000 0 0x4000>; 1291129e1c96SFelipe Balbi reg-names = "se"; 1292129e1c96SFelipe Balbi clock-names = "se"; 1293129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1294abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1295abdd4b7aSFelipe Balbi <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1296abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1297129e1c96SFelipe Balbi pinctrl-names = "default"; 1298129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi9_default>; 1299129e1c96SFelipe Balbi interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1300129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1301129e1c96SFelipe Balbi #address-cells = <1>; 1302129e1c96SFelipe Balbi #size-cells = <0>; 1303129e1c96SFelipe Balbi status = "disabled"; 1304129e1c96SFelipe Balbi }; 1305129e1c96SFelipe Balbi 130681bee695SCaleb Connolly i2c10: i2c@a88000 { 130781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 130881bee695SCaleb Connolly reg = <0 0x00a88000 0 0x4000>; 130981bee695SCaleb Connolly clock-names = "se"; 131081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1311abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1312abdd4b7aSFelipe Balbi <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1313abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 131481bee695SCaleb Connolly pinctrl-names = "default"; 131581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c10_default>; 131681bee695SCaleb Connolly interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 131781bee695SCaleb Connolly #address-cells = <1>; 131881bee695SCaleb Connolly #size-cells = <0>; 131981bee695SCaleb Connolly status = "disabled"; 132081bee695SCaleb Connolly }; 132181bee695SCaleb Connolly 1322129e1c96SFelipe Balbi spi10: spi@a88000 { 1323129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1324129e1c96SFelipe Balbi reg = <0 0xa88000 0 0x4000>; 1325129e1c96SFelipe Balbi reg-names = "se"; 1326129e1c96SFelipe Balbi clock-names = "se"; 1327129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1328abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1329abdd4b7aSFelipe Balbi <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1330abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1331129e1c96SFelipe Balbi pinctrl-names = "default"; 1332129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi10_default>; 1333129e1c96SFelipe Balbi interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1334129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1335129e1c96SFelipe Balbi #address-cells = <1>; 1336129e1c96SFelipe Balbi #size-cells = <0>; 1337129e1c96SFelipe Balbi status = "disabled"; 1338129e1c96SFelipe Balbi }; 1339129e1c96SFelipe Balbi 134081bee695SCaleb Connolly i2c11: i2c@a8c000 { 134181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 134281bee695SCaleb Connolly reg = <0 0x00a8c000 0 0x4000>; 134381bee695SCaleb Connolly clock-names = "se"; 134481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1345abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1346abdd4b7aSFelipe Balbi <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1347abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 134881bee695SCaleb Connolly pinctrl-names = "default"; 134981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c11_default>; 135081bee695SCaleb Connolly interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 135181bee695SCaleb Connolly #address-cells = <1>; 135281bee695SCaleb Connolly #size-cells = <0>; 135381bee695SCaleb Connolly status = "disabled"; 135481bee695SCaleb Connolly }; 135581bee695SCaleb Connolly 1356129e1c96SFelipe Balbi spi11: spi@a8c000 { 1357129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1358129e1c96SFelipe Balbi reg = <0 0xa8c000 0 0x4000>; 1359129e1c96SFelipe Balbi reg-names = "se"; 1360129e1c96SFelipe Balbi clock-names = "se"; 1361129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1362abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1363abdd4b7aSFelipe Balbi <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1364abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1365129e1c96SFelipe Balbi pinctrl-names = "default"; 1366129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi11_default>; 1367129e1c96SFelipe Balbi interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1368129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1369129e1c96SFelipe Balbi #address-cells = <1>; 1370129e1c96SFelipe Balbi #size-cells = <0>; 1371129e1c96SFelipe Balbi status = "disabled"; 1372129e1c96SFelipe Balbi }; 1373129e1c96SFelipe Balbi 1374e13c6d14SVinod Koul uart2: serial@a90000 { 1375e13c6d14SVinod Koul compatible = "qcom,geni-debug-uart"; 1376e13c6d14SVinod Koul reg = <0x0 0x00a90000 0x0 0x4000>; 1377e13c6d14SVinod Koul clock-names = "se"; 1378d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1379e13c6d14SVinod Koul interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1380e13c6d14SVinod Koul status = "disabled"; 1381e13c6d14SVinod Koul }; 138281bee695SCaleb Connolly 138381bee695SCaleb Connolly i2c12: i2c@a90000 { 138481bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 138581bee695SCaleb Connolly reg = <0 0x00a90000 0 0x4000>; 138681bee695SCaleb Connolly clock-names = "se"; 138781bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1388abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1389abdd4b7aSFelipe Balbi <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1390abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 139181bee695SCaleb Connolly pinctrl-names = "default"; 139281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c12_default>; 139381bee695SCaleb Connolly interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 139481bee695SCaleb Connolly #address-cells = <1>; 139581bee695SCaleb Connolly #size-cells = <0>; 139681bee695SCaleb Connolly status = "disabled"; 139781bee695SCaleb Connolly }; 139881bee695SCaleb Connolly 1399129e1c96SFelipe Balbi spi12: spi@a90000 { 1400129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1401129e1c96SFelipe Balbi reg = <0 0xa90000 0 0x4000>; 1402129e1c96SFelipe Balbi reg-names = "se"; 1403129e1c96SFelipe Balbi clock-names = "se"; 1404129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1405abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1406abdd4b7aSFelipe Balbi <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1407abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1408129e1c96SFelipe Balbi pinctrl-names = "default"; 1409129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi12_default>; 1410129e1c96SFelipe Balbi interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1411129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1412129e1c96SFelipe Balbi #address-cells = <1>; 1413129e1c96SFelipe Balbi #size-cells = <0>; 1414129e1c96SFelipe Balbi status = "disabled"; 1415129e1c96SFelipe Balbi }; 1416129e1c96SFelipe Balbi 141781bee695SCaleb Connolly i2c16: i2c@94000 { 141881bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 141981bee695SCaleb Connolly reg = <0 0x0094000 0 0x4000>; 142081bee695SCaleb Connolly clock-names = "se"; 142181bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1422abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1423abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1424abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 142581bee695SCaleb Connolly pinctrl-names = "default"; 142681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c16_default>; 142781bee695SCaleb Connolly interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 142881bee695SCaleb Connolly #address-cells = <1>; 142981bee695SCaleb Connolly #size-cells = <0>; 143081bee695SCaleb Connolly status = "disabled"; 143181bee695SCaleb Connolly }; 1432129e1c96SFelipe Balbi 1433129e1c96SFelipe Balbi spi16: spi@a94000 { 1434129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1435129e1c96SFelipe Balbi reg = <0 0xa94000 0 0x4000>; 1436129e1c96SFelipe Balbi reg-names = "se"; 1437129e1c96SFelipe Balbi clock-names = "se"; 1438129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1439abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1440abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1441abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1442129e1c96SFelipe Balbi pinctrl-names = "default"; 1443129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi16_default>; 1444129e1c96SFelipe Balbi interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1445129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1446129e1c96SFelipe Balbi #address-cells = <1>; 1447129e1c96SFelipe Balbi #size-cells = <0>; 1448129e1c96SFelipe Balbi status = "disabled"; 1449129e1c96SFelipe Balbi }; 1450e13c6d14SVinod Koul }; 1451e13c6d14SVinod Koul 145205006290SFelipe Balbi gpi_dma2: dma-controller@c00000 { 145305006290SFelipe Balbi compatible = "qcom,sm8150-gpi-dma"; 145405006290SFelipe Balbi reg = <0 0xc00000 0 0x60000>; 145505006290SFelipe Balbi interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 145605006290SFelipe Balbi <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 145705006290SFelipe Balbi <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 145805006290SFelipe Balbi <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 145905006290SFelipe Balbi <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 146005006290SFelipe Balbi <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 146105006290SFelipe Balbi <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 146205006290SFelipe Balbi <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 146305006290SFelipe Balbi <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 146405006290SFelipe Balbi <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 146505006290SFelipe Balbi <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 146605006290SFelipe Balbi <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 146705006290SFelipe Balbi <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 146805006290SFelipe Balbi dma-channels = <13>; 146905006290SFelipe Balbi dma-channel-mask = <0xfa>; 147005006290SFelipe Balbi iommus = <&apps_smmu 0x07b6 0x0>; 147105006290SFelipe Balbi #dma-cells = <3>; 147205006290SFelipe Balbi status = "disabled"; 147305006290SFelipe Balbi }; 147405006290SFelipe Balbi 14759cf3ebd1SCaleb Connolly qupv3_id_2: geniqup@cc0000 { 14769cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 14779cf3ebd1SCaleb Connolly reg = <0x0 0x00cc0000 0x0 0x6000>; 14789cf3ebd1SCaleb Connolly 14799cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 14809cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 14819cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 14829cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x7a3 0x0>; 14839cf3ebd1SCaleb Connolly #address-cells = <2>; 14849cf3ebd1SCaleb Connolly #size-cells = <2>; 14859cf3ebd1SCaleb Connolly ranges; 14869cf3ebd1SCaleb Connolly status = "disabled"; 148781bee695SCaleb Connolly 148881bee695SCaleb Connolly i2c17: i2c@c80000 { 148981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 149081bee695SCaleb Connolly reg = <0 0x00c80000 0 0x4000>; 149181bee695SCaleb Connolly clock-names = "se"; 149281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1493abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1494abdd4b7aSFelipe Balbi <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1495abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 149681bee695SCaleb Connolly pinctrl-names = "default"; 149781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c17_default>; 149881bee695SCaleb Connolly interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 149981bee695SCaleb Connolly #address-cells = <1>; 150081bee695SCaleb Connolly #size-cells = <0>; 150181bee695SCaleb Connolly status = "disabled"; 150281bee695SCaleb Connolly }; 150381bee695SCaleb Connolly 1504129e1c96SFelipe Balbi spi17: spi@c80000 { 1505129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1506129e1c96SFelipe Balbi reg = <0 0xc80000 0 0x4000>; 1507129e1c96SFelipe Balbi reg-names = "se"; 1508129e1c96SFelipe Balbi clock-names = "se"; 1509129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1510abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1511abdd4b7aSFelipe Balbi <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1512abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1513129e1c96SFelipe Balbi pinctrl-names = "default"; 1514129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi17_default>; 1515129e1c96SFelipe Balbi interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1516129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1517129e1c96SFelipe Balbi #address-cells = <1>; 1518129e1c96SFelipe Balbi #size-cells = <0>; 1519129e1c96SFelipe Balbi status = "disabled"; 1520129e1c96SFelipe Balbi }; 1521129e1c96SFelipe Balbi 152281bee695SCaleb Connolly i2c18: i2c@c84000 { 152381bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 152481bee695SCaleb Connolly reg = <0 0x00c84000 0 0x4000>; 152581bee695SCaleb Connolly clock-names = "se"; 152681bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1527abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1528abdd4b7aSFelipe Balbi <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1529abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 153081bee695SCaleb Connolly pinctrl-names = "default"; 153181bee695SCaleb Connolly pinctrl-0 = <&qup_i2c18_default>; 153281bee695SCaleb Connolly interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 153381bee695SCaleb Connolly #address-cells = <1>; 153481bee695SCaleb Connolly #size-cells = <0>; 153581bee695SCaleb Connolly status = "disabled"; 153681bee695SCaleb Connolly }; 153781bee695SCaleb Connolly 1538129e1c96SFelipe Balbi spi18: spi@c84000 { 1539129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1540129e1c96SFelipe Balbi reg = <0 0xc84000 0 0x4000>; 1541129e1c96SFelipe Balbi reg-names = "se"; 1542129e1c96SFelipe Balbi clock-names = "se"; 1543129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1544abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1545abdd4b7aSFelipe Balbi <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1546abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1547129e1c96SFelipe Balbi pinctrl-names = "default"; 1548129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi18_default>; 1549129e1c96SFelipe Balbi interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1550129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1551129e1c96SFelipe Balbi #address-cells = <1>; 1552129e1c96SFelipe Balbi #size-cells = <0>; 1553129e1c96SFelipe Balbi status = "disabled"; 1554129e1c96SFelipe Balbi }; 1555129e1c96SFelipe Balbi 155681bee695SCaleb Connolly i2c19: i2c@c88000 { 155781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 155881bee695SCaleb Connolly reg = <0 0x00c88000 0 0x4000>; 155981bee695SCaleb Connolly clock-names = "se"; 156081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1561abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1562abdd4b7aSFelipe Balbi <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1563abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 156481bee695SCaleb Connolly pinctrl-names = "default"; 156581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c19_default>; 156681bee695SCaleb Connolly interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 156781bee695SCaleb Connolly #address-cells = <1>; 156881bee695SCaleb Connolly #size-cells = <0>; 156981bee695SCaleb Connolly status = "disabled"; 157081bee695SCaleb Connolly }; 157181bee695SCaleb Connolly 1572129e1c96SFelipe Balbi spi19: spi@c88000 { 1573129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1574129e1c96SFelipe Balbi reg = <0 0xc88000 0 0x4000>; 1575129e1c96SFelipe Balbi reg-names = "se"; 1576129e1c96SFelipe Balbi clock-names = "se"; 1577129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1578abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1579abdd4b7aSFelipe Balbi <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1580abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1581129e1c96SFelipe Balbi pinctrl-names = "default"; 1582129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi19_default>; 1583129e1c96SFelipe Balbi interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1584129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1585129e1c96SFelipe Balbi #address-cells = <1>; 1586129e1c96SFelipe Balbi #size-cells = <0>; 1587129e1c96SFelipe Balbi status = "disabled"; 1588129e1c96SFelipe Balbi }; 1589129e1c96SFelipe Balbi 159081bee695SCaleb Connolly i2c13: i2c@c8c000 { 159181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 159281bee695SCaleb Connolly reg = <0 0x00c8c000 0 0x4000>; 159381bee695SCaleb Connolly clock-names = "se"; 159481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1595abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1596abdd4b7aSFelipe Balbi <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1597abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 159881bee695SCaleb Connolly pinctrl-names = "default"; 159981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c13_default>; 160081bee695SCaleb Connolly interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 160181bee695SCaleb Connolly #address-cells = <1>; 160281bee695SCaleb Connolly #size-cells = <0>; 160381bee695SCaleb Connolly status = "disabled"; 160481bee695SCaleb Connolly }; 160581bee695SCaleb Connolly 1606129e1c96SFelipe Balbi spi13: spi@c8c000 { 1607129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1608129e1c96SFelipe Balbi reg = <0 0xc8c000 0 0x4000>; 1609129e1c96SFelipe Balbi reg-names = "se"; 1610129e1c96SFelipe Balbi clock-names = "se"; 1611129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1612abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1613abdd4b7aSFelipe Balbi <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1614abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1615129e1c96SFelipe Balbi pinctrl-names = "default"; 1616129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi13_default>; 1617129e1c96SFelipe Balbi interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1618129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1619129e1c96SFelipe Balbi #address-cells = <1>; 1620129e1c96SFelipe Balbi #size-cells = <0>; 1621129e1c96SFelipe Balbi status = "disabled"; 1622129e1c96SFelipe Balbi }; 1623129e1c96SFelipe Balbi 162481bee695SCaleb Connolly i2c14: i2c@c90000 { 162581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 162681bee695SCaleb Connolly reg = <0 0x00c90000 0 0x4000>; 162781bee695SCaleb Connolly clock-names = "se"; 162881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1629abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1630abdd4b7aSFelipe Balbi <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1631abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 163281bee695SCaleb Connolly pinctrl-names = "default"; 163381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c14_default>; 163481bee695SCaleb Connolly interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 163581bee695SCaleb Connolly #address-cells = <1>; 163681bee695SCaleb Connolly #size-cells = <0>; 163781bee695SCaleb Connolly status = "disabled"; 163881bee695SCaleb Connolly }; 163981bee695SCaleb Connolly 1640129e1c96SFelipe Balbi spi14: spi@c90000 { 1641129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1642129e1c96SFelipe Balbi reg = <0 0xc90000 0 0x4000>; 1643129e1c96SFelipe Balbi reg-names = "se"; 1644129e1c96SFelipe Balbi clock-names = "se"; 1645129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1646abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1647abdd4b7aSFelipe Balbi <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1648abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1649129e1c96SFelipe Balbi pinctrl-names = "default"; 1650129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi14_default>; 1651129e1c96SFelipe Balbi interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1652129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1653129e1c96SFelipe Balbi #address-cells = <1>; 1654129e1c96SFelipe Balbi #size-cells = <0>; 1655129e1c96SFelipe Balbi status = "disabled"; 1656129e1c96SFelipe Balbi }; 1657129e1c96SFelipe Balbi 165881bee695SCaleb Connolly i2c15: i2c@c94000 { 165981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 166081bee695SCaleb Connolly reg = <0 0x00c94000 0 0x4000>; 166181bee695SCaleb Connolly clock-names = "se"; 166281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1663abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1664abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1665abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 166681bee695SCaleb Connolly pinctrl-names = "default"; 166781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c15_default>; 166881bee695SCaleb Connolly interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 166981bee695SCaleb Connolly #address-cells = <1>; 167081bee695SCaleb Connolly #size-cells = <0>; 167181bee695SCaleb Connolly status = "disabled"; 167281bee695SCaleb Connolly }; 1673129e1c96SFelipe Balbi 1674129e1c96SFelipe Balbi spi15: spi@c94000 { 1675129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1676129e1c96SFelipe Balbi reg = <0 0xc94000 0 0x4000>; 1677129e1c96SFelipe Balbi reg-names = "se"; 1678129e1c96SFelipe Balbi clock-names = "se"; 1679129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1680abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1681abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1682abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1683129e1c96SFelipe Balbi pinctrl-names = "default"; 1684129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi15_default>; 1685129e1c96SFelipe Balbi interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1686129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1687129e1c96SFelipe Balbi #address-cells = <1>; 1688129e1c96SFelipe Balbi #size-cells = <0>; 1689129e1c96SFelipe Balbi status = "disabled"; 1690129e1c96SFelipe Balbi }; 16919cf3ebd1SCaleb Connolly }; 16929cf3ebd1SCaleb Connolly 169371a2fc6eSJonathan Marek config_noc: interconnect@1500000 { 169471a2fc6eSJonathan Marek compatible = "qcom,sm8150-config-noc"; 169571a2fc6eSJonathan Marek reg = <0 0x01500000 0 0x7400>; 169671a2fc6eSJonathan Marek #interconnect-cells = <1>; 169771a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 169871a2fc6eSJonathan Marek }; 169971a2fc6eSJonathan Marek 170071a2fc6eSJonathan Marek system_noc: interconnect@1620000 { 170171a2fc6eSJonathan Marek compatible = "qcom,sm8150-system-noc"; 170271a2fc6eSJonathan Marek reg = <0 0x01620000 0 0x19400>; 170371a2fc6eSJonathan Marek #interconnect-cells = <1>; 170471a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 170571a2fc6eSJonathan Marek }; 170671a2fc6eSJonathan Marek 170771a2fc6eSJonathan Marek mc_virt: interconnect@163a000 { 170871a2fc6eSJonathan Marek compatible = "qcom,sm8150-mc-virt"; 170971a2fc6eSJonathan Marek reg = <0 0x0163a000 0 0x1000>; 171071a2fc6eSJonathan Marek #interconnect-cells = <1>; 171171a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 171271a2fc6eSJonathan Marek }; 171371a2fc6eSJonathan Marek 171471a2fc6eSJonathan Marek aggre1_noc: interconnect@16e0000 { 171571a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre1-noc"; 171671a2fc6eSJonathan Marek reg = <0 0x016e0000 0 0xd080>; 171771a2fc6eSJonathan Marek #interconnect-cells = <1>; 171871a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 171971a2fc6eSJonathan Marek }; 172071a2fc6eSJonathan Marek 172171a2fc6eSJonathan Marek aggre2_noc: interconnect@1700000 { 172271a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre2-noc"; 172371a2fc6eSJonathan Marek reg = <0 0x01700000 0 0x20000>; 172471a2fc6eSJonathan Marek #interconnect-cells = <1>; 172571a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 172671a2fc6eSJonathan Marek }; 172771a2fc6eSJonathan Marek 172871a2fc6eSJonathan Marek compute_noc: interconnect@1720000 { 172971a2fc6eSJonathan Marek compatible = "qcom,sm8150-compute-noc"; 173071a2fc6eSJonathan Marek reg = <0 0x01720000 0 0x7000>; 173171a2fc6eSJonathan Marek #interconnect-cells = <1>; 173271a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 173371a2fc6eSJonathan Marek }; 173471a2fc6eSJonathan Marek 173571a2fc6eSJonathan Marek mmss_noc: interconnect@1740000 { 173671a2fc6eSJonathan Marek compatible = "qcom,sm8150-mmss-noc"; 173771a2fc6eSJonathan Marek reg = <0 0x01740000 0 0x1c100>; 173871a2fc6eSJonathan Marek #interconnect-cells = <1>; 173971a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 174071a2fc6eSJonathan Marek }; 174171a2fc6eSJonathan Marek 1742bb1f7cf6SSouradeep Chowdhury system-cache-controller@9200000 { 1743bb1f7cf6SSouradeep Chowdhury compatible = "qcom,sm8150-llcc"; 1744bb1f7cf6SSouradeep Chowdhury reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 1745bb1f7cf6SSouradeep Chowdhury reg-names = "llcc_base", "llcc_broadcast_base"; 1746bb1f7cf6SSouradeep Chowdhury interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1747bb1f7cf6SSouradeep Chowdhury }; 1748bb1f7cf6SSouradeep Chowdhury 17493834a2e9SVinod Koul ufs_mem_hc: ufshc@1d84000 { 17503834a2e9SVinod Koul compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 17513834a2e9SVinod Koul "jedec,ufs-2.0"; 175298aee1e3SBhupesh Sharma reg = <0 0x01d84000 0 0x2500>, 175398aee1e3SBhupesh Sharma <0 0x01d90000 0 0x8000>; 175498aee1e3SBhupesh Sharma reg-names = "std", "ice"; 17553834a2e9SVinod Koul interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 17563834a2e9SVinod Koul phys = <&ufs_mem_phy_lanes>; 17573834a2e9SVinod Koul phy-names = "ufsphy"; 17583834a2e9SVinod Koul lanes-per-direction = <2>; 17593834a2e9SVinod Koul #reset-cells = <1>; 17603834a2e9SVinod Koul resets = <&gcc GCC_UFS_PHY_BCR>; 17613834a2e9SVinod Koul reset-names = "rst"; 17623834a2e9SVinod Koul 176348156232SJonathan Marek iommus = <&apps_smmu 0x300 0>; 176448156232SJonathan Marek 17653834a2e9SVinod Koul clock-names = 17663834a2e9SVinod Koul "core_clk", 17673834a2e9SVinod Koul "bus_aggr_clk", 17683834a2e9SVinod Koul "iface_clk", 17693834a2e9SVinod Koul "core_clk_unipro", 17703834a2e9SVinod Koul "ref_clk", 17713834a2e9SVinod Koul "tx_lane0_sync_clk", 17723834a2e9SVinod Koul "rx_lane0_sync_clk", 177398aee1e3SBhupesh Sharma "rx_lane1_sync_clk", 177498aee1e3SBhupesh Sharma "ice_core_clk"; 17753834a2e9SVinod Koul clocks = 17763834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AXI_CLK>, 17773834a2e9SVinod Koul <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 17783834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AHB_CLK>, 17793834a2e9SVinod Koul <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 17803834a2e9SVinod Koul <&rpmhcc RPMH_CXO_CLK>, 17813834a2e9SVinod Koul <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 17823834a2e9SVinod Koul <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 178398aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 178498aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 17853834a2e9SVinod Koul freq-table-hz = 17863834a2e9SVinod Koul <37500000 300000000>, 17873834a2e9SVinod Koul <0 0>, 17883834a2e9SVinod Koul <0 0>, 17893834a2e9SVinod Koul <37500000 300000000>, 17903834a2e9SVinod Koul <0 0>, 17913834a2e9SVinod Koul <0 0>, 17923834a2e9SVinod Koul <0 0>, 179398aee1e3SBhupesh Sharma <0 0>, 179498aee1e3SBhupesh Sharma <0 300000000>; 17953834a2e9SVinod Koul 17963834a2e9SVinod Koul status = "disabled"; 17973834a2e9SVinod Koul }; 17983834a2e9SVinod Koul 17993834a2e9SVinod Koul ufs_mem_phy: phy@1d87000 { 18003834a2e9SVinod Koul compatible = "qcom,sm8150-qmp-ufs-phy"; 1801c79ec891SVinod Koul reg = <0 0x01d87000 0 0x1c0>; 18023834a2e9SVinod Koul #address-cells = <2>; 18033834a2e9SVinod Koul #size-cells = <2>; 18043834a2e9SVinod Koul ranges; 18053834a2e9SVinod Koul clock-names = "ref", 18063834a2e9SVinod Koul "ref_aux"; 18073834a2e9SVinod Koul clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 18083834a2e9SVinod Koul <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 18093834a2e9SVinod Koul 18103834a2e9SVinod Koul resets = <&ufs_mem_hc 0>; 18113834a2e9SVinod Koul reset-names = "ufsphy"; 18123834a2e9SVinod Koul status = "disabled"; 18133834a2e9SVinod Koul 18141351512fSShawn Guo ufs_mem_phy_lanes: phy@1d87400 { 18153834a2e9SVinod Koul reg = <0 0x01d87400 0 0x108>, 18163834a2e9SVinod Koul <0 0x01d87600 0 0x1e0>, 18173834a2e9SVinod Koul <0 0x01d87c00 0 0x1dc>, 18183834a2e9SVinod Koul <0 0x01d87800 0 0x108>, 18193834a2e9SVinod Koul <0 0x01d87a00 0 0x1e0>; 18203834a2e9SVinod Koul #phy-cells = <0>; 18213834a2e9SVinod Koul }; 18223834a2e9SVinod Koul }; 18233834a2e9SVinod Koul 182471a2fc6eSJonathan Marek ipa_virt: interconnect@1e00000 { 182571a2fc6eSJonathan Marek compatible = "qcom,sm8150-ipa-virt"; 182671a2fc6eSJonathan Marek reg = <0 0x01e00000 0 0x1000>; 182771a2fc6eSJonathan Marek #interconnect-cells = <1>; 182871a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 182971a2fc6eSJonathan Marek }; 183071a2fc6eSJonathan Marek 1831d8cf9372SVinod Koul tcsr_mutex_regs: syscon@1f40000 { 1832d8cf9372SVinod Koul compatible = "syscon"; 1833d8cf9372SVinod Koul reg = <0x0 0x01f40000 0x0 0x40000>; 1834d8cf9372SVinod Koul }; 1835d8cf9372SVinod Koul 183649076351SSibi Sankar remoteproc_slpi: remoteproc@2400000 { 183749076351SSibi Sankar compatible = "qcom,sm8150-slpi-pas"; 183849076351SSibi Sankar reg = <0x0 0x02400000 0x0 0x4040>; 183949076351SSibi Sankar 184049076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 184149076351SSibi Sankar <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 184249076351SSibi Sankar <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 184349076351SSibi Sankar <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 184449076351SSibi Sankar <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 184549076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 184649076351SSibi Sankar "handover", "stop-ack"; 184749076351SSibi Sankar 184849076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 184949076351SSibi Sankar clock-names = "xo"; 185049076351SSibi Sankar 1851d9d327f6SSibi Sankar power-domains = <&rpmhpd 3>, 1852d0770627SBjorn Andersson <&rpmhpd 2>; 1853d9d327f6SSibi Sankar power-domain-names = "lcx", "lmx"; 185449076351SSibi Sankar 185549076351SSibi Sankar memory-region = <&slpi_mem>; 185649076351SSibi Sankar 1857d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 1858d9d327f6SSibi Sankar 185949076351SSibi Sankar qcom,smem-states = <&slpi_smp2p_out 0>; 186049076351SSibi Sankar qcom,smem-state-names = "stop"; 186149076351SSibi Sankar 186249076351SSibi Sankar status = "disabled"; 186349076351SSibi Sankar 186449076351SSibi Sankar glink-edge { 186549076351SSibi Sankar interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 186649076351SSibi Sankar label = "dsps"; 186749076351SSibi Sankar qcom,remote-pid = <3>; 186849076351SSibi Sankar mboxes = <&apss_shared 24>; 186981729330SBhupesh Sharma 187081729330SBhupesh Sharma fastrpc { 187181729330SBhupesh Sharma compatible = "qcom,fastrpc"; 187281729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 187381729330SBhupesh Sharma label = "sdsp"; 187481729330SBhupesh Sharma #address-cells = <1>; 187581729330SBhupesh Sharma #size-cells = <0>; 187681729330SBhupesh Sharma 187781729330SBhupesh Sharma compute-cb@1 { 187881729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 187981729330SBhupesh Sharma reg = <1>; 188081729330SBhupesh Sharma iommus = <&apps_smmu 0x05a1 0x0>; 188181729330SBhupesh Sharma }; 188281729330SBhupesh Sharma 188381729330SBhupesh Sharma compute-cb@2 { 188481729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 188581729330SBhupesh Sharma reg = <2>; 188681729330SBhupesh Sharma iommus = <&apps_smmu 0x05a2 0x0>; 188781729330SBhupesh Sharma }; 188881729330SBhupesh Sharma 188981729330SBhupesh Sharma compute-cb@3 { 189081729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 189181729330SBhupesh Sharma reg = <3>; 189281729330SBhupesh Sharma iommus = <&apps_smmu 0x05a3 0x0>; 189381729330SBhupesh Sharma /* note: shared-cb = <4> in downstream */ 189481729330SBhupesh Sharma }; 189581729330SBhupesh Sharma }; 189649076351SSibi Sankar }; 189749076351SSibi Sankar }; 189849076351SSibi Sankar 1899f30ac26dSJonathan Marek gpu: gpu@2c00000 { 1900f30ac26dSJonathan Marek /* 1901f30ac26dSJonathan Marek * note: the amd,imageon compatible makes it possible 1902f30ac26dSJonathan Marek * to use the drm/msm driver without the display node, 1903f30ac26dSJonathan Marek * make sure to remove it when display node is added 1904f30ac26dSJonathan Marek */ 1905f30ac26dSJonathan Marek compatible = "qcom,adreno-640.1", 1906f30ac26dSJonathan Marek "qcom,adreno", 1907f30ac26dSJonathan Marek "amd,imageon"; 1908f30ac26dSJonathan Marek 1909f30ac26dSJonathan Marek reg = <0 0x02c00000 0 0x40000>; 1910f30ac26dSJonathan Marek reg-names = "kgsl_3d0_reg_memory"; 1911f30ac26dSJonathan Marek 1912f30ac26dSJonathan Marek interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1913f30ac26dSJonathan Marek 1914f30ac26dSJonathan Marek iommus = <&adreno_smmu 0 0x401>; 1915f30ac26dSJonathan Marek 1916f30ac26dSJonathan Marek operating-points-v2 = <&gpu_opp_table>; 1917f30ac26dSJonathan Marek 1918f30ac26dSJonathan Marek qcom,gmu = <&gmu>; 1919f30ac26dSJonathan Marek 1920b1dc3c6bSKonrad Dybcio status = "disabled"; 1921b1dc3c6bSKonrad Dybcio 1922f30ac26dSJonathan Marek zap-shader { 1923f30ac26dSJonathan Marek memory-region = <&gpu_mem>; 1924f30ac26dSJonathan Marek }; 1925f30ac26dSJonathan Marek 1926f30ac26dSJonathan Marek /* note: downstream checks gpu binning for 675 Mhz */ 1927f30ac26dSJonathan Marek gpu_opp_table: opp-table { 1928f30ac26dSJonathan Marek compatible = "operating-points-v2"; 1929f30ac26dSJonathan Marek 1930f30ac26dSJonathan Marek opp-675000000 { 1931f30ac26dSJonathan Marek opp-hz = /bits/ 64 <675000000>; 1932f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1933f30ac26dSJonathan Marek }; 1934f30ac26dSJonathan Marek 1935f30ac26dSJonathan Marek opp-585000000 { 1936f30ac26dSJonathan Marek opp-hz = /bits/ 64 <585000000>; 1937f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1938f30ac26dSJonathan Marek }; 1939f30ac26dSJonathan Marek 1940f30ac26dSJonathan Marek opp-499200000 { 1941f30ac26dSJonathan Marek opp-hz = /bits/ 64 <499200000>; 1942f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1943f30ac26dSJonathan Marek }; 1944f30ac26dSJonathan Marek 1945f30ac26dSJonathan Marek opp-427000000 { 1946f30ac26dSJonathan Marek opp-hz = /bits/ 64 <427000000>; 1947f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1948f30ac26dSJonathan Marek }; 1949f30ac26dSJonathan Marek 1950f30ac26dSJonathan Marek opp-345000000 { 1951f30ac26dSJonathan Marek opp-hz = /bits/ 64 <345000000>; 1952f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1953f30ac26dSJonathan Marek }; 1954f30ac26dSJonathan Marek 1955f30ac26dSJonathan Marek opp-257000000 { 1956f30ac26dSJonathan Marek opp-hz = /bits/ 64 <257000000>; 1957f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1958f30ac26dSJonathan Marek }; 1959f30ac26dSJonathan Marek }; 1960f30ac26dSJonathan Marek }; 1961f30ac26dSJonathan Marek 1962f30ac26dSJonathan Marek gmu: gmu@2c6a000 { 1963f30ac26dSJonathan Marek compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 1964f30ac26dSJonathan Marek 1965f30ac26dSJonathan Marek reg = <0 0x02c6a000 0 0x30000>, 1966f30ac26dSJonathan Marek <0 0x0b290000 0 0x10000>, 1967f30ac26dSJonathan Marek <0 0x0b490000 0 0x10000>; 1968f30ac26dSJonathan Marek reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 1969f30ac26dSJonathan Marek 1970f30ac26dSJonathan Marek interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1971f30ac26dSJonathan Marek <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1972f30ac26dSJonathan Marek interrupt-names = "hfi", "gmu"; 1973f30ac26dSJonathan Marek 1974f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 1975f1269916SJonathan Marek <&gpucc GPU_CC_CX_GMU_CLK>, 1976f1269916SJonathan Marek <&gpucc GPU_CC_CXO_CLK>, 1977f30ac26dSJonathan Marek <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1978f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1979f30ac26dSJonathan Marek clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 1980f30ac26dSJonathan Marek 1981f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>, 1982f1269916SJonathan Marek <&gpucc GPU_GX_GDSC>; 1983f30ac26dSJonathan Marek power-domain-names = "cx", "gx"; 1984f30ac26dSJonathan Marek 1985f30ac26dSJonathan Marek iommus = <&adreno_smmu 5 0x400>; 1986f30ac26dSJonathan Marek 1987f30ac26dSJonathan Marek operating-points-v2 = <&gmu_opp_table>; 1988f30ac26dSJonathan Marek 1989b1dc3c6bSKonrad Dybcio status = "disabled"; 1990b1dc3c6bSKonrad Dybcio 1991f30ac26dSJonathan Marek gmu_opp_table: opp-table { 1992f30ac26dSJonathan Marek compatible = "operating-points-v2"; 1993f30ac26dSJonathan Marek 1994f30ac26dSJonathan Marek opp-200000000 { 1995f30ac26dSJonathan Marek opp-hz = /bits/ 64 <200000000>; 1996f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1997f30ac26dSJonathan Marek }; 1998f30ac26dSJonathan Marek }; 1999f30ac26dSJonathan Marek }; 2000f30ac26dSJonathan Marek 2001f30ac26dSJonathan Marek gpucc: clock-controller@2c90000 { 2002f30ac26dSJonathan Marek compatible = "qcom,sm8150-gpucc"; 2003f30ac26dSJonathan Marek reg = <0 0x02c90000 0 0x9000>; 2004f30ac26dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>, 2005f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2006f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2007f30ac26dSJonathan Marek clock-names = "bi_tcxo", 2008f30ac26dSJonathan Marek "gcc_gpu_gpll0_clk_src", 2009f30ac26dSJonathan Marek "gcc_gpu_gpll0_div_clk_src"; 2010f30ac26dSJonathan Marek #clock-cells = <1>; 2011f30ac26dSJonathan Marek #reset-cells = <1>; 2012f30ac26dSJonathan Marek #power-domain-cells = <1>; 2013f30ac26dSJonathan Marek }; 2014f30ac26dSJonathan Marek 2015f30ac26dSJonathan Marek adreno_smmu: iommu@2ca0000 { 2016f30ac26dSJonathan Marek compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 2017f30ac26dSJonathan Marek reg = <0 0x02ca0000 0 0x10000>; 2018f30ac26dSJonathan Marek #iommu-cells = <2>; 2019f30ac26dSJonathan Marek #global-interrupts = <1>; 2020f30ac26dSJonathan Marek interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2021f30ac26dSJonathan Marek <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2022f30ac26dSJonathan Marek <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2023f30ac26dSJonathan Marek <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2024f30ac26dSJonathan Marek <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2025f30ac26dSJonathan Marek <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2026f30ac26dSJonathan Marek <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2027f30ac26dSJonathan Marek <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2028f30ac26dSJonathan Marek <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2029f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 2030f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2031f30ac26dSJonathan Marek <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2032f30ac26dSJonathan Marek clock-names = "ahb", "bus", "iface"; 2033f30ac26dSJonathan Marek 2034f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>; 2035f30ac26dSJonathan Marek }; 2036f30ac26dSJonathan Marek 2037e13c6d14SVinod Koul tlmm: pinctrl@3100000 { 2038e13c6d14SVinod Koul compatible = "qcom,sm8150-pinctrl"; 2039e13c6d14SVinod Koul reg = <0x0 0x03100000 0x0 0x300000>, 2040e13c6d14SVinod Koul <0x0 0x03500000 0x0 0x300000>, 2041e13c6d14SVinod Koul <0x0 0x03900000 0x0 0x300000>, 2042e13c6d14SVinod Koul <0x0 0x03D00000 0x0 0x300000>; 2043e13c6d14SVinod Koul reg-names = "west", "east", "north", "south"; 2044e13c6d14SVinod Koul interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2045de3abdf3SShawn Guo gpio-ranges = <&tlmm 0 0 176>; 2046e13c6d14SVinod Koul gpio-controller; 2047e13c6d14SVinod Koul #gpio-cells = <2>; 2048e13c6d14SVinod Koul interrupt-controller; 2049e13c6d14SVinod Koul #interrupt-cells = <2>; 205081bee695SCaleb Connolly 205181bee695SCaleb Connolly qup_i2c0_default: qup-i2c0-default { 205281bee695SCaleb Connolly mux { 205381bee695SCaleb Connolly pins = "gpio0", "gpio1"; 205481bee695SCaleb Connolly function = "qup0"; 205581bee695SCaleb Connolly }; 205681bee695SCaleb Connolly 205781bee695SCaleb Connolly config { 205881bee695SCaleb Connolly pins = "gpio0", "gpio1"; 205981bee695SCaleb Connolly drive-strength = <0x02>; 206081bee695SCaleb Connolly bias-disable; 206181bee695SCaleb Connolly }; 206281bee695SCaleb Connolly }; 206381bee695SCaleb Connolly 2064129e1c96SFelipe Balbi qup_spi0_default: qup-spi0-default { 2065129e1c96SFelipe Balbi pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2066129e1c96SFelipe Balbi function = "qup0"; 2067129e1c96SFelipe Balbi drive-strength = <6>; 2068129e1c96SFelipe Balbi bias-disable; 2069129e1c96SFelipe Balbi }; 2070129e1c96SFelipe Balbi 207181bee695SCaleb Connolly qup_i2c1_default: qup-i2c1-default { 207281bee695SCaleb Connolly mux { 207381bee695SCaleb Connolly pins = "gpio114", "gpio115"; 207481bee695SCaleb Connolly function = "qup1"; 207581bee695SCaleb Connolly }; 207681bee695SCaleb Connolly 207781bee695SCaleb Connolly config { 207881bee695SCaleb Connolly pins = "gpio114", "gpio115"; 207981bee695SCaleb Connolly drive-strength = <0x02>; 208081bee695SCaleb Connolly bias-disable; 208181bee695SCaleb Connolly }; 208281bee695SCaleb Connolly }; 208381bee695SCaleb Connolly 2084129e1c96SFelipe Balbi qup_spi1_default: qup-spi1-default { 2085129e1c96SFelipe Balbi pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2086129e1c96SFelipe Balbi function = "qup1"; 2087129e1c96SFelipe Balbi drive-strength = <6>; 2088129e1c96SFelipe Balbi bias-disable; 2089129e1c96SFelipe Balbi }; 2090129e1c96SFelipe Balbi 209181bee695SCaleb Connolly qup_i2c2_default: qup-i2c2-default { 209281bee695SCaleb Connolly mux { 209381bee695SCaleb Connolly pins = "gpio126", "gpio127"; 209481bee695SCaleb Connolly function = "qup2"; 209581bee695SCaleb Connolly }; 209681bee695SCaleb Connolly 209781bee695SCaleb Connolly config { 209881bee695SCaleb Connolly pins = "gpio126", "gpio127"; 209981bee695SCaleb Connolly drive-strength = <0x02>; 210081bee695SCaleb Connolly bias-disable; 210181bee695SCaleb Connolly }; 210281bee695SCaleb Connolly }; 210381bee695SCaleb Connolly 2104129e1c96SFelipe Balbi qup_spi2_default: qup-spi2-default { 2105129e1c96SFelipe Balbi pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2106129e1c96SFelipe Balbi function = "qup2"; 2107129e1c96SFelipe Balbi drive-strength = <6>; 2108129e1c96SFelipe Balbi bias-disable; 2109129e1c96SFelipe Balbi }; 2110129e1c96SFelipe Balbi 211181bee695SCaleb Connolly qup_i2c3_default: qup-i2c3-default { 211281bee695SCaleb Connolly mux { 211381bee695SCaleb Connolly pins = "gpio144", "gpio145"; 211481bee695SCaleb Connolly function = "qup3"; 211581bee695SCaleb Connolly }; 211681bee695SCaleb Connolly 211781bee695SCaleb Connolly config { 211881bee695SCaleb Connolly pins = "gpio144", "gpio145"; 211981bee695SCaleb Connolly drive-strength = <0x02>; 212081bee695SCaleb Connolly bias-disable; 212181bee695SCaleb Connolly }; 212281bee695SCaleb Connolly }; 212381bee695SCaleb Connolly 2124129e1c96SFelipe Balbi qup_spi3_default: qup-spi3-default { 2125129e1c96SFelipe Balbi pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2126129e1c96SFelipe Balbi function = "qup3"; 2127129e1c96SFelipe Balbi drive-strength = <6>; 2128129e1c96SFelipe Balbi bias-disable; 2129129e1c96SFelipe Balbi }; 2130129e1c96SFelipe Balbi 213181bee695SCaleb Connolly qup_i2c4_default: qup-i2c4-default { 213281bee695SCaleb Connolly mux { 213381bee695SCaleb Connolly pins = "gpio51", "gpio52"; 213481bee695SCaleb Connolly function = "qup4"; 213581bee695SCaleb Connolly }; 213681bee695SCaleb Connolly 213781bee695SCaleb Connolly config { 213881bee695SCaleb Connolly pins = "gpio51", "gpio52"; 213981bee695SCaleb Connolly drive-strength = <0x02>; 214081bee695SCaleb Connolly bias-disable; 214181bee695SCaleb Connolly }; 214281bee695SCaleb Connolly }; 214381bee695SCaleb Connolly 2144129e1c96SFelipe Balbi qup_spi4_default: qup-spi4-default { 2145129e1c96SFelipe Balbi pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2146129e1c96SFelipe Balbi function = "qup4"; 2147129e1c96SFelipe Balbi drive-strength = <6>; 2148129e1c96SFelipe Balbi bias-disable; 2149129e1c96SFelipe Balbi }; 2150129e1c96SFelipe Balbi 215181bee695SCaleb Connolly qup_i2c5_default: qup-i2c5-default { 215281bee695SCaleb Connolly mux { 215381bee695SCaleb Connolly pins = "gpio121", "gpio122"; 215481bee695SCaleb Connolly function = "qup5"; 215581bee695SCaleb Connolly }; 215681bee695SCaleb Connolly 215781bee695SCaleb Connolly config { 215881bee695SCaleb Connolly pins = "gpio121", "gpio122"; 215981bee695SCaleb Connolly drive-strength = <0x02>; 216081bee695SCaleb Connolly bias-disable; 216181bee695SCaleb Connolly }; 216281bee695SCaleb Connolly }; 216381bee695SCaleb Connolly 2164129e1c96SFelipe Balbi qup_spi5_default: qup-spi5-default { 2165129e1c96SFelipe Balbi pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2166129e1c96SFelipe Balbi function = "qup5"; 2167129e1c96SFelipe Balbi drive-strength = <6>; 2168129e1c96SFelipe Balbi bias-disable; 2169129e1c96SFelipe Balbi }; 2170129e1c96SFelipe Balbi 217181bee695SCaleb Connolly qup_i2c6_default: qup-i2c6-default { 217281bee695SCaleb Connolly mux { 217381bee695SCaleb Connolly pins = "gpio6", "gpio7"; 217481bee695SCaleb Connolly function = "qup6"; 217581bee695SCaleb Connolly }; 217681bee695SCaleb Connolly 217781bee695SCaleb Connolly config { 217881bee695SCaleb Connolly pins = "gpio6", "gpio7"; 217981bee695SCaleb Connolly drive-strength = <0x02>; 218081bee695SCaleb Connolly bias-disable; 218181bee695SCaleb Connolly }; 218281bee695SCaleb Connolly }; 218381bee695SCaleb Connolly 2184129e1c96SFelipe Balbi qup_spi6_default: qup-spi6_default { 2185129e1c96SFelipe Balbi pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2186129e1c96SFelipe Balbi function = "qup6"; 2187129e1c96SFelipe Balbi drive-strength = <6>; 2188129e1c96SFelipe Balbi bias-disable; 2189129e1c96SFelipe Balbi }; 2190129e1c96SFelipe Balbi 219181bee695SCaleb Connolly qup_i2c7_default: qup-i2c7-default { 219281bee695SCaleb Connolly mux { 219381bee695SCaleb Connolly pins = "gpio98", "gpio99"; 219481bee695SCaleb Connolly function = "qup7"; 219581bee695SCaleb Connolly }; 219681bee695SCaleb Connolly 219781bee695SCaleb Connolly config { 219881bee695SCaleb Connolly pins = "gpio98", "gpio99"; 219981bee695SCaleb Connolly drive-strength = <0x02>; 220081bee695SCaleb Connolly bias-disable; 220181bee695SCaleb Connolly }; 220281bee695SCaleb Connolly }; 220381bee695SCaleb Connolly 2204129e1c96SFelipe Balbi qup_spi7_default: qup-spi7_default { 2205129e1c96SFelipe Balbi pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2206129e1c96SFelipe Balbi function = "qup7"; 2207129e1c96SFelipe Balbi drive-strength = <6>; 2208129e1c96SFelipe Balbi bias-disable; 2209129e1c96SFelipe Balbi }; 2210129e1c96SFelipe Balbi 221181bee695SCaleb Connolly qup_i2c8_default: qup-i2c8-default { 221281bee695SCaleb Connolly mux { 221381bee695SCaleb Connolly pins = "gpio88", "gpio89"; 221481bee695SCaleb Connolly function = "qup8"; 221581bee695SCaleb Connolly }; 221681bee695SCaleb Connolly 221781bee695SCaleb Connolly config { 221881bee695SCaleb Connolly pins = "gpio88", "gpio89"; 221981bee695SCaleb Connolly drive-strength = <0x02>; 222081bee695SCaleb Connolly bias-disable; 222181bee695SCaleb Connolly }; 222281bee695SCaleb Connolly }; 222381bee695SCaleb Connolly 2224129e1c96SFelipe Balbi qup_spi8_default: qup-spi8-default { 2225129e1c96SFelipe Balbi pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2226129e1c96SFelipe Balbi function = "qup8"; 2227129e1c96SFelipe Balbi drive-strength = <6>; 2228129e1c96SFelipe Balbi bias-disable; 2229129e1c96SFelipe Balbi }; 2230129e1c96SFelipe Balbi 223181bee695SCaleb Connolly qup_i2c9_default: qup-i2c9-default { 223281bee695SCaleb Connolly mux { 223381bee695SCaleb Connolly pins = "gpio39", "gpio40"; 223481bee695SCaleb Connolly function = "qup9"; 223581bee695SCaleb Connolly }; 223681bee695SCaleb Connolly 223781bee695SCaleb Connolly config { 223881bee695SCaleb Connolly pins = "gpio39", "gpio40"; 223981bee695SCaleb Connolly drive-strength = <0x02>; 224081bee695SCaleb Connolly bias-disable; 224181bee695SCaleb Connolly }; 224281bee695SCaleb Connolly }; 224381bee695SCaleb Connolly 2244129e1c96SFelipe Balbi qup_spi9_default: qup-spi9-default { 2245129e1c96SFelipe Balbi pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2246129e1c96SFelipe Balbi function = "qup9"; 2247129e1c96SFelipe Balbi drive-strength = <6>; 2248129e1c96SFelipe Balbi bias-disable; 2249129e1c96SFelipe Balbi }; 2250129e1c96SFelipe Balbi 225181bee695SCaleb Connolly qup_i2c10_default: qup-i2c10-default { 225281bee695SCaleb Connolly mux { 225381bee695SCaleb Connolly pins = "gpio9", "gpio10"; 225481bee695SCaleb Connolly function = "qup10"; 225581bee695SCaleb Connolly }; 225681bee695SCaleb Connolly 225781bee695SCaleb Connolly config { 225881bee695SCaleb Connolly pins = "gpio9", "gpio10"; 225981bee695SCaleb Connolly drive-strength = <0x02>; 226081bee695SCaleb Connolly bias-disable; 226181bee695SCaleb Connolly }; 226281bee695SCaleb Connolly }; 226381bee695SCaleb Connolly 2264129e1c96SFelipe Balbi qup_spi10_default: qup-spi10-default { 2265129e1c96SFelipe Balbi pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2266129e1c96SFelipe Balbi function = "qup10"; 2267129e1c96SFelipe Balbi drive-strength = <6>; 2268129e1c96SFelipe Balbi bias-disable; 2269129e1c96SFelipe Balbi }; 2270129e1c96SFelipe Balbi 227181bee695SCaleb Connolly qup_i2c11_default: qup-i2c11-default { 227281bee695SCaleb Connolly mux { 227381bee695SCaleb Connolly pins = "gpio94", "gpio95"; 227481bee695SCaleb Connolly function = "qup11"; 227581bee695SCaleb Connolly }; 227681bee695SCaleb Connolly 227781bee695SCaleb Connolly config { 227881bee695SCaleb Connolly pins = "gpio94", "gpio95"; 227981bee695SCaleb Connolly drive-strength = <0x02>; 228081bee695SCaleb Connolly bias-disable; 228181bee695SCaleb Connolly }; 228281bee695SCaleb Connolly }; 228381bee695SCaleb Connolly 2284129e1c96SFelipe Balbi qup_spi11_default: qup-spi11-default { 2285129e1c96SFelipe Balbi pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2286129e1c96SFelipe Balbi function = "qup11"; 2287129e1c96SFelipe Balbi drive-strength = <6>; 2288129e1c96SFelipe Balbi bias-disable; 2289129e1c96SFelipe Balbi }; 2290129e1c96SFelipe Balbi 229181bee695SCaleb Connolly qup_i2c12_default: qup-i2c12-default { 229281bee695SCaleb Connolly mux { 229381bee695SCaleb Connolly pins = "gpio83", "gpio84"; 229481bee695SCaleb Connolly function = "qup12"; 229581bee695SCaleb Connolly }; 229681bee695SCaleb Connolly 229781bee695SCaleb Connolly config { 229881bee695SCaleb Connolly pins = "gpio83", "gpio84"; 229981bee695SCaleb Connolly drive-strength = <0x02>; 230081bee695SCaleb Connolly bias-disable; 230181bee695SCaleb Connolly }; 230281bee695SCaleb Connolly }; 230381bee695SCaleb Connolly 2304129e1c96SFelipe Balbi qup_spi12_default: qup-spi12-default { 2305129e1c96SFelipe Balbi pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2306129e1c96SFelipe Balbi function = "qup12"; 2307129e1c96SFelipe Balbi drive-strength = <6>; 2308129e1c96SFelipe Balbi bias-disable; 2309129e1c96SFelipe Balbi }; 2310129e1c96SFelipe Balbi 231181bee695SCaleb Connolly qup_i2c13_default: qup-i2c13-default { 231281bee695SCaleb Connolly mux { 231381bee695SCaleb Connolly pins = "gpio43", "gpio44"; 231481bee695SCaleb Connolly function = "qup13"; 231581bee695SCaleb Connolly }; 231681bee695SCaleb Connolly 231781bee695SCaleb Connolly config { 231881bee695SCaleb Connolly pins = "gpio43", "gpio44"; 231981bee695SCaleb Connolly drive-strength = <0x02>; 232081bee695SCaleb Connolly bias-disable; 232181bee695SCaleb Connolly }; 232281bee695SCaleb Connolly }; 232381bee695SCaleb Connolly 2324129e1c96SFelipe Balbi qup_spi13_default: qup-spi13-default { 2325129e1c96SFelipe Balbi pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2326129e1c96SFelipe Balbi function = "qup13"; 2327129e1c96SFelipe Balbi drive-strength = <6>; 2328129e1c96SFelipe Balbi bias-disable; 2329129e1c96SFelipe Balbi }; 2330129e1c96SFelipe Balbi 233181bee695SCaleb Connolly qup_i2c14_default: qup-i2c14-default { 233281bee695SCaleb Connolly mux { 233381bee695SCaleb Connolly pins = "gpio47", "gpio48"; 233481bee695SCaleb Connolly function = "qup14"; 233581bee695SCaleb Connolly }; 233681bee695SCaleb Connolly 233781bee695SCaleb Connolly config { 233881bee695SCaleb Connolly pins = "gpio47", "gpio48"; 233981bee695SCaleb Connolly drive-strength = <0x02>; 234081bee695SCaleb Connolly bias-disable; 234181bee695SCaleb Connolly }; 234281bee695SCaleb Connolly }; 234381bee695SCaleb Connolly 2344129e1c96SFelipe Balbi qup_spi14_default: qup-spi14-default { 2345129e1c96SFelipe Balbi pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2346129e1c96SFelipe Balbi function = "qup14"; 2347129e1c96SFelipe Balbi drive-strength = <6>; 2348129e1c96SFelipe Balbi bias-disable; 2349129e1c96SFelipe Balbi }; 2350129e1c96SFelipe Balbi 235181bee695SCaleb Connolly qup_i2c15_default: qup-i2c15-default { 235281bee695SCaleb Connolly mux { 235381bee695SCaleb Connolly pins = "gpio27", "gpio28"; 235481bee695SCaleb Connolly function = "qup15"; 235581bee695SCaleb Connolly }; 235681bee695SCaleb Connolly 235781bee695SCaleb Connolly config { 235881bee695SCaleb Connolly pins = "gpio27", "gpio28"; 235981bee695SCaleb Connolly drive-strength = <0x02>; 236081bee695SCaleb Connolly bias-disable; 236181bee695SCaleb Connolly }; 236281bee695SCaleb Connolly }; 236381bee695SCaleb Connolly 2364129e1c96SFelipe Balbi qup_spi15_default: qup-spi15-default { 2365129e1c96SFelipe Balbi pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2366129e1c96SFelipe Balbi function = "qup15"; 2367129e1c96SFelipe Balbi drive-strength = <6>; 2368129e1c96SFelipe Balbi bias-disable; 2369129e1c96SFelipe Balbi }; 2370129e1c96SFelipe Balbi 237181bee695SCaleb Connolly qup_i2c16_default: qup-i2c16-default { 237281bee695SCaleb Connolly mux { 237381bee695SCaleb Connolly pins = "gpio86", "gpio85"; 237481bee695SCaleb Connolly function = "qup16"; 237581bee695SCaleb Connolly }; 237681bee695SCaleb Connolly 237781bee695SCaleb Connolly config { 237881bee695SCaleb Connolly pins = "gpio86", "gpio85"; 237981bee695SCaleb Connolly drive-strength = <0x02>; 238081bee695SCaleb Connolly bias-disable; 238181bee695SCaleb Connolly }; 238281bee695SCaleb Connolly }; 238381bee695SCaleb Connolly 2384129e1c96SFelipe Balbi qup_spi16_default: qup-spi16-default { 2385129e1c96SFelipe Balbi pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2386129e1c96SFelipe Balbi function = "qup16"; 2387129e1c96SFelipe Balbi drive-strength = <6>; 2388129e1c96SFelipe Balbi bias-disable; 2389129e1c96SFelipe Balbi }; 2390129e1c96SFelipe Balbi 239181bee695SCaleb Connolly qup_i2c17_default: qup-i2c17-default { 239281bee695SCaleb Connolly mux { 239381bee695SCaleb Connolly pins = "gpio55", "gpio56"; 239481bee695SCaleb Connolly function = "qup17"; 239581bee695SCaleb Connolly }; 239681bee695SCaleb Connolly 239781bee695SCaleb Connolly config { 239881bee695SCaleb Connolly pins = "gpio55", "gpio56"; 239981bee695SCaleb Connolly drive-strength = <0x02>; 240081bee695SCaleb Connolly bias-disable; 240181bee695SCaleb Connolly }; 240281bee695SCaleb Connolly }; 240381bee695SCaleb Connolly 2404129e1c96SFelipe Balbi qup_spi17_default: qup-spi17-default { 2405129e1c96SFelipe Balbi pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2406129e1c96SFelipe Balbi function = "qup17"; 2407129e1c96SFelipe Balbi drive-strength = <6>; 2408129e1c96SFelipe Balbi bias-disable; 2409129e1c96SFelipe Balbi }; 2410129e1c96SFelipe Balbi 241181bee695SCaleb Connolly qup_i2c18_default: qup-i2c18-default { 241281bee695SCaleb Connolly mux { 241381bee695SCaleb Connolly pins = "gpio23", "gpio24"; 241481bee695SCaleb Connolly function = "qup18"; 241581bee695SCaleb Connolly }; 241681bee695SCaleb Connolly 241781bee695SCaleb Connolly config { 241881bee695SCaleb Connolly pins = "gpio23", "gpio24"; 241981bee695SCaleb Connolly drive-strength = <0x02>; 242081bee695SCaleb Connolly bias-disable; 242181bee695SCaleb Connolly }; 242281bee695SCaleb Connolly }; 242381bee695SCaleb Connolly 2424129e1c96SFelipe Balbi qup_spi18_default: qup-spi18-default { 2425129e1c96SFelipe Balbi pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2426129e1c96SFelipe Balbi function = "qup18"; 2427129e1c96SFelipe Balbi drive-strength = <6>; 2428129e1c96SFelipe Balbi bias-disable; 2429129e1c96SFelipe Balbi }; 2430129e1c96SFelipe Balbi 243181bee695SCaleb Connolly qup_i2c19_default: qup-i2c19-default { 243281bee695SCaleb Connolly mux { 243381bee695SCaleb Connolly pins = "gpio57", "gpio58"; 243481bee695SCaleb Connolly function = "qup19"; 243581bee695SCaleb Connolly }; 243681bee695SCaleb Connolly 243781bee695SCaleb Connolly config { 243881bee695SCaleb Connolly pins = "gpio57", "gpio58"; 243981bee695SCaleb Connolly drive-strength = <0x02>; 244081bee695SCaleb Connolly bias-disable; 244181bee695SCaleb Connolly }; 244281bee695SCaleb Connolly }; 2443129e1c96SFelipe Balbi 2444129e1c96SFelipe Balbi qup_spi19_default: qup-spi19-default { 2445129e1c96SFelipe Balbi pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2446129e1c96SFelipe Balbi function = "qup19"; 2447129e1c96SFelipe Balbi drive-strength = <6>; 2448129e1c96SFelipe Balbi bias-disable; 2449129e1c96SFelipe Balbi }; 2450e13c6d14SVinod Koul }; 2451e13c6d14SVinod Koul 245249076351SSibi Sankar remoteproc_mpss: remoteproc@4080000 { 245349076351SSibi Sankar compatible = "qcom,sm8150-mpss-pas"; 245449076351SSibi Sankar reg = <0x0 0x04080000 0x0 0x4040>; 245549076351SSibi Sankar 245649076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 245749076351SSibi Sankar <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 245849076351SSibi Sankar <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 245949076351SSibi Sankar <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 246049076351SSibi Sankar <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 246149076351SSibi Sankar <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 246249076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", "handover", 246349076351SSibi Sankar "stop-ack", "shutdown-ack"; 246449076351SSibi Sankar 246549076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 246649076351SSibi Sankar clock-names = "xo"; 246749076351SSibi Sankar 2468d9d327f6SSibi Sankar power-domains = <&rpmhpd 7>, 2469d0770627SBjorn Andersson <&rpmhpd 0>; 2470d9d327f6SSibi Sankar power-domain-names = "cx", "mss"; 247149076351SSibi Sankar 247249076351SSibi Sankar memory-region = <&mpss_mem>; 247349076351SSibi Sankar 2474d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 2475d9d327f6SSibi Sankar 247649076351SSibi Sankar qcom,smem-states = <&modem_smp2p_out 0>; 247749076351SSibi Sankar qcom,smem-state-names = "stop"; 247849076351SSibi Sankar 2479b1dc3c6bSKonrad Dybcio status = "disabled"; 2480b1dc3c6bSKonrad Dybcio 248149076351SSibi Sankar glink-edge { 248249076351SSibi Sankar interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 248349076351SSibi Sankar label = "modem"; 248449076351SSibi Sankar qcom,remote-pid = <1>; 248549076351SSibi Sankar mboxes = <&apss_shared 12>; 248649076351SSibi Sankar }; 248749076351SSibi Sankar }; 248849076351SSibi Sankar 248924244cefSSai Prakash Ranjan stm@6002000 { 249024244cefSSai Prakash Ranjan compatible = "arm,coresight-stm", "arm,primecell"; 249124244cefSSai Prakash Ranjan reg = <0 0x06002000 0 0x1000>, 249224244cefSSai Prakash Ranjan <0 0x16280000 0 0x180000>; 249324244cefSSai Prakash Ranjan reg-names = "stm-base", "stm-stimulus-base"; 249424244cefSSai Prakash Ranjan 249524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 249624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 249724244cefSSai Prakash Ranjan 249824244cefSSai Prakash Ranjan out-ports { 249924244cefSSai Prakash Ranjan port { 250024244cefSSai Prakash Ranjan stm_out: endpoint { 250124244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_in7>; 250224244cefSSai Prakash Ranjan }; 250324244cefSSai Prakash Ranjan }; 250424244cefSSai Prakash Ranjan }; 250524244cefSSai Prakash Ranjan }; 250624244cefSSai Prakash Ranjan 250724244cefSSai Prakash Ranjan funnel@6041000 { 250824244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 250924244cefSSai Prakash Ranjan reg = <0 0x06041000 0 0x1000>; 251024244cefSSai Prakash Ranjan 251124244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 251224244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 251324244cefSSai Prakash Ranjan 251424244cefSSai Prakash Ranjan out-ports { 251524244cefSSai Prakash Ranjan port { 251624244cefSSai Prakash Ranjan funnel0_out: endpoint { 251724244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in0>; 251824244cefSSai Prakash Ranjan }; 251924244cefSSai Prakash Ranjan }; 252024244cefSSai Prakash Ranjan }; 252124244cefSSai Prakash Ranjan 252224244cefSSai Prakash Ranjan in-ports { 252324244cefSSai Prakash Ranjan #address-cells = <1>; 252424244cefSSai Prakash Ranjan #size-cells = <0>; 252524244cefSSai Prakash Ranjan 252624244cefSSai Prakash Ranjan port@7 { 252724244cefSSai Prakash Ranjan reg = <7>; 252824244cefSSai Prakash Ranjan funnel0_in7: endpoint { 252924244cefSSai Prakash Ranjan remote-endpoint = <&stm_out>; 253024244cefSSai Prakash Ranjan }; 253124244cefSSai Prakash Ranjan }; 253224244cefSSai Prakash Ranjan }; 253324244cefSSai Prakash Ranjan }; 253424244cefSSai Prakash Ranjan 253524244cefSSai Prakash Ranjan funnel@6042000 { 253624244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 253724244cefSSai Prakash Ranjan reg = <0 0x06042000 0 0x1000>; 253824244cefSSai Prakash Ranjan 253924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 254024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 254124244cefSSai Prakash Ranjan 254224244cefSSai Prakash Ranjan out-ports { 254324244cefSSai Prakash Ranjan port { 254424244cefSSai Prakash Ranjan funnel1_out: endpoint { 254524244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in1>; 254624244cefSSai Prakash Ranjan }; 254724244cefSSai Prakash Ranjan }; 254824244cefSSai Prakash Ranjan }; 254924244cefSSai Prakash Ranjan 255024244cefSSai Prakash Ranjan in-ports { 255124244cefSSai Prakash Ranjan #address-cells = <1>; 255224244cefSSai Prakash Ranjan #size-cells = <0>; 255324244cefSSai Prakash Ranjan 255424244cefSSai Prakash Ranjan port@4 { 255524244cefSSai Prakash Ranjan reg = <4>; 255624244cefSSai Prakash Ranjan funnel1_in4: endpoint { 255724244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_out>; 255824244cefSSai Prakash Ranjan }; 255924244cefSSai Prakash Ranjan }; 256024244cefSSai Prakash Ranjan }; 256124244cefSSai Prakash Ranjan }; 256224244cefSSai Prakash Ranjan 256324244cefSSai Prakash Ranjan funnel@6043000 { 256424244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 256524244cefSSai Prakash Ranjan reg = <0 0x06043000 0 0x1000>; 256624244cefSSai Prakash Ranjan 256724244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 256824244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 256924244cefSSai Prakash Ranjan 257024244cefSSai Prakash Ranjan out-ports { 257124244cefSSai Prakash Ranjan port { 257224244cefSSai Prakash Ranjan funnel2_out: endpoint { 257324244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in2>; 257424244cefSSai Prakash Ranjan }; 257524244cefSSai Prakash Ranjan }; 257624244cefSSai Prakash Ranjan }; 257724244cefSSai Prakash Ranjan 257824244cefSSai Prakash Ranjan in-ports { 257924244cefSSai Prakash Ranjan #address-cells = <1>; 258024244cefSSai Prakash Ranjan #size-cells = <0>; 258124244cefSSai Prakash Ranjan 258224244cefSSai Prakash Ranjan port@2 { 258324244cefSSai Prakash Ranjan reg = <2>; 258424244cefSSai Prakash Ranjan funnel2_in2: endpoint { 258524244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_out>; 258624244cefSSai Prakash Ranjan }; 258724244cefSSai Prakash Ranjan }; 258824244cefSSai Prakash Ranjan }; 258924244cefSSai Prakash Ranjan }; 259024244cefSSai Prakash Ranjan 259124244cefSSai Prakash Ranjan funnel@6045000 { 259224244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 259324244cefSSai Prakash Ranjan reg = <0 0x06045000 0 0x1000>; 259424244cefSSai Prakash Ranjan 259524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 259624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 259724244cefSSai Prakash Ranjan 259824244cefSSai Prakash Ranjan out-ports { 259924244cefSSai Prakash Ranjan port { 260024244cefSSai Prakash Ranjan merge_funnel_out: endpoint { 260124244cefSSai Prakash Ranjan remote-endpoint = <&etf_in>; 260224244cefSSai Prakash Ranjan }; 260324244cefSSai Prakash Ranjan }; 260424244cefSSai Prakash Ranjan }; 260524244cefSSai Prakash Ranjan 260624244cefSSai Prakash Ranjan in-ports { 260724244cefSSai Prakash Ranjan #address-cells = <1>; 260824244cefSSai Prakash Ranjan #size-cells = <0>; 260924244cefSSai Prakash Ranjan 261024244cefSSai Prakash Ranjan port@0 { 261124244cefSSai Prakash Ranjan reg = <0>; 261224244cefSSai Prakash Ranjan merge_funnel_in0: endpoint { 261324244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_out>; 261424244cefSSai Prakash Ranjan }; 261524244cefSSai Prakash Ranjan }; 261624244cefSSai Prakash Ranjan 261724244cefSSai Prakash Ranjan port@1 { 261824244cefSSai Prakash Ranjan reg = <1>; 261924244cefSSai Prakash Ranjan merge_funnel_in1: endpoint { 262024244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_out>; 262124244cefSSai Prakash Ranjan }; 262224244cefSSai Prakash Ranjan }; 262324244cefSSai Prakash Ranjan 262424244cefSSai Prakash Ranjan port@2 { 262524244cefSSai Prakash Ranjan reg = <2>; 262624244cefSSai Prakash Ranjan merge_funnel_in2: endpoint { 262724244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_out>; 262824244cefSSai Prakash Ranjan }; 262924244cefSSai Prakash Ranjan }; 263024244cefSSai Prakash Ranjan }; 263124244cefSSai Prakash Ranjan }; 263224244cefSSai Prakash Ranjan 263324244cefSSai Prakash Ranjan replicator@6046000 { 263424244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 263524244cefSSai Prakash Ranjan reg = <0 0x06046000 0 0x1000>; 263624244cefSSai Prakash Ranjan 263724244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 263824244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 263924244cefSSai Prakash Ranjan 264024244cefSSai Prakash Ranjan out-ports { 264124244cefSSai Prakash Ranjan #address-cells = <1>; 264224244cefSSai Prakash Ranjan #size-cells = <0>; 264324244cefSSai Prakash Ranjan 264424244cefSSai Prakash Ranjan port@0 { 264524244cefSSai Prakash Ranjan reg = <0>; 264624244cefSSai Prakash Ranjan replicator_out0: endpoint { 264724244cefSSai Prakash Ranjan remote-endpoint = <&etr_in>; 264824244cefSSai Prakash Ranjan }; 264924244cefSSai Prakash Ranjan }; 265024244cefSSai Prakash Ranjan 265124244cefSSai Prakash Ranjan port@1 { 265224244cefSSai Prakash Ranjan reg = <1>; 265324244cefSSai Prakash Ranjan replicator_out1: endpoint { 265424244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_in>; 265524244cefSSai Prakash Ranjan }; 265624244cefSSai Prakash Ranjan }; 265724244cefSSai Prakash Ranjan }; 265824244cefSSai Prakash Ranjan 265924244cefSSai Prakash Ranjan in-ports { 266024244cefSSai Prakash Ranjan port { 266124244cefSSai Prakash Ranjan replicator_in0: endpoint { 266224244cefSSai Prakash Ranjan remote-endpoint = <&etf_out>; 266324244cefSSai Prakash Ranjan }; 266424244cefSSai Prakash Ranjan }; 266524244cefSSai Prakash Ranjan }; 266624244cefSSai Prakash Ranjan }; 266724244cefSSai Prakash Ranjan 266824244cefSSai Prakash Ranjan etf@6047000 { 266924244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 267024244cefSSai Prakash Ranjan reg = <0 0x06047000 0 0x1000>; 267124244cefSSai Prakash Ranjan 267224244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 267324244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 267424244cefSSai Prakash Ranjan 267524244cefSSai Prakash Ranjan out-ports { 267624244cefSSai Prakash Ranjan port { 267724244cefSSai Prakash Ranjan etf_out: endpoint { 267824244cefSSai Prakash Ranjan remote-endpoint = <&replicator_in0>; 267924244cefSSai Prakash Ranjan }; 268024244cefSSai Prakash Ranjan }; 268124244cefSSai Prakash Ranjan }; 268224244cefSSai Prakash Ranjan 268324244cefSSai Prakash Ranjan in-ports { 268424244cefSSai Prakash Ranjan port { 268524244cefSSai Prakash Ranjan etf_in: endpoint { 268624244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_out>; 268724244cefSSai Prakash Ranjan }; 268824244cefSSai Prakash Ranjan }; 268924244cefSSai Prakash Ranjan }; 269024244cefSSai Prakash Ranjan }; 269124244cefSSai Prakash Ranjan 269224244cefSSai Prakash Ranjan etr@6048000 { 269324244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 269424244cefSSai Prakash Ranjan reg = <0 0x06048000 0 0x1000>; 269524244cefSSai Prakash Ranjan iommus = <&apps_smmu 0x05e0 0x0>; 269624244cefSSai Prakash Ranjan 269724244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 269824244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 269924244cefSSai Prakash Ranjan arm,scatter-gather; 270024244cefSSai Prakash Ranjan 270124244cefSSai Prakash Ranjan in-ports { 270224244cefSSai Prakash Ranjan port { 270324244cefSSai Prakash Ranjan etr_in: endpoint { 270424244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out0>; 270524244cefSSai Prakash Ranjan }; 270624244cefSSai Prakash Ranjan }; 270724244cefSSai Prakash Ranjan }; 270824244cefSSai Prakash Ranjan }; 270924244cefSSai Prakash Ranjan 271024244cefSSai Prakash Ranjan replicator@604a000 { 271124244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 271224244cefSSai Prakash Ranjan reg = <0 0x0604a000 0 0x1000>; 271324244cefSSai Prakash Ranjan 271424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 271524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 271624244cefSSai Prakash Ranjan 271724244cefSSai Prakash Ranjan out-ports { 271824244cefSSai Prakash Ranjan #address-cells = <1>; 271924244cefSSai Prakash Ranjan #size-cells = <0>; 272024244cefSSai Prakash Ranjan 272124244cefSSai Prakash Ranjan port@1 { 272224244cefSSai Prakash Ranjan reg = <1>; 272324244cefSSai Prakash Ranjan replicator1_out: endpoint { 272424244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_in>; 272524244cefSSai Prakash Ranjan }; 272624244cefSSai Prakash Ranjan }; 272724244cefSSai Prakash Ranjan }; 272824244cefSSai Prakash Ranjan 272924244cefSSai Prakash Ranjan in-ports { 273024244cefSSai Prakash Ranjan #address-cells = <1>; 273124244cefSSai Prakash Ranjan #size-cells = <0>; 273224244cefSSai Prakash Ranjan 273324244cefSSai Prakash Ranjan port@1 { 273424244cefSSai Prakash Ranjan reg = <1>; 273524244cefSSai Prakash Ranjan replicator1_in: endpoint { 273624244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out1>; 273724244cefSSai Prakash Ranjan }; 273824244cefSSai Prakash Ranjan }; 273924244cefSSai Prakash Ranjan }; 274024244cefSSai Prakash Ranjan }; 274124244cefSSai Prakash Ranjan 274224244cefSSai Prakash Ranjan funnel@6b08000 { 274324244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 274424244cefSSai Prakash Ranjan reg = <0 0x06b08000 0 0x1000>; 274524244cefSSai Prakash Ranjan 274624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 274724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 274824244cefSSai Prakash Ranjan 274924244cefSSai Prakash Ranjan out-ports { 275024244cefSSai Prakash Ranjan port { 275124244cefSSai Prakash Ranjan swao_funnel_out: endpoint { 275224244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_in>; 275324244cefSSai Prakash Ranjan }; 275424244cefSSai Prakash Ranjan }; 275524244cefSSai Prakash Ranjan }; 275624244cefSSai Prakash Ranjan 275724244cefSSai Prakash Ranjan in-ports { 275824244cefSSai Prakash Ranjan #address-cells = <1>; 275924244cefSSai Prakash Ranjan #size-cells = <0>; 276024244cefSSai Prakash Ranjan 276124244cefSSai Prakash Ranjan port@6 { 276224244cefSSai Prakash Ranjan reg = <6>; 276324244cefSSai Prakash Ranjan swao_funnel_in: endpoint { 276424244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_out>; 276524244cefSSai Prakash Ranjan }; 276624244cefSSai Prakash Ranjan }; 276724244cefSSai Prakash Ranjan }; 276824244cefSSai Prakash Ranjan }; 276924244cefSSai Prakash Ranjan 277024244cefSSai Prakash Ranjan etf@6b09000 { 277124244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 277224244cefSSai Prakash Ranjan reg = <0 0x06b09000 0 0x1000>; 277324244cefSSai Prakash Ranjan 277424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 277524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 277624244cefSSai Prakash Ranjan 277724244cefSSai Prakash Ranjan out-ports { 277824244cefSSai Prakash Ranjan port { 277924244cefSSai Prakash Ranjan swao_etf_out: endpoint { 278024244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_in>; 278124244cefSSai Prakash Ranjan }; 278224244cefSSai Prakash Ranjan }; 278324244cefSSai Prakash Ranjan }; 278424244cefSSai Prakash Ranjan 278524244cefSSai Prakash Ranjan in-ports { 278624244cefSSai Prakash Ranjan port { 278724244cefSSai Prakash Ranjan swao_etf_in: endpoint { 278824244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_out>; 278924244cefSSai Prakash Ranjan }; 279024244cefSSai Prakash Ranjan }; 279124244cefSSai Prakash Ranjan }; 279224244cefSSai Prakash Ranjan }; 279324244cefSSai Prakash Ranjan 279424244cefSSai Prakash Ranjan replicator@6b0a000 { 279524244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 279624244cefSSai Prakash Ranjan reg = <0 0x06b0a000 0 0x1000>; 279724244cefSSai Prakash Ranjan 279824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 279924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 280024244cefSSai Prakash Ranjan qcom,replicator-loses-context; 280124244cefSSai Prakash Ranjan 280224244cefSSai Prakash Ranjan out-ports { 280324244cefSSai Prakash Ranjan port { 280424244cefSSai Prakash Ranjan swao_replicator_out: endpoint { 280524244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_in4>; 280624244cefSSai Prakash Ranjan }; 280724244cefSSai Prakash Ranjan }; 280824244cefSSai Prakash Ranjan }; 280924244cefSSai Prakash Ranjan 281024244cefSSai Prakash Ranjan in-ports { 281124244cefSSai Prakash Ranjan port { 281224244cefSSai Prakash Ranjan swao_replicator_in: endpoint { 281324244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_out>; 281424244cefSSai Prakash Ranjan }; 281524244cefSSai Prakash Ranjan }; 281624244cefSSai Prakash Ranjan }; 281724244cefSSai Prakash Ranjan }; 281824244cefSSai Prakash Ranjan 281924244cefSSai Prakash Ranjan etm@7040000 { 282024244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 282124244cefSSai Prakash Ranjan reg = <0 0x07040000 0 0x1000>; 282224244cefSSai Prakash Ranjan 282324244cefSSai Prakash Ranjan cpu = <&CPU0>; 282424244cefSSai Prakash Ranjan 282524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 282624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 282724244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 282824244cefSSai Prakash Ranjan qcom,skip-power-up; 282924244cefSSai Prakash Ranjan 283024244cefSSai Prakash Ranjan out-ports { 283124244cefSSai Prakash Ranjan port { 283224244cefSSai Prakash Ranjan etm0_out: endpoint { 283324244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in0>; 283424244cefSSai Prakash Ranjan }; 283524244cefSSai Prakash Ranjan }; 283624244cefSSai Prakash Ranjan }; 283724244cefSSai Prakash Ranjan }; 283824244cefSSai Prakash Ranjan 283924244cefSSai Prakash Ranjan etm@7140000 { 284024244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 284124244cefSSai Prakash Ranjan reg = <0 0x07140000 0 0x1000>; 284224244cefSSai Prakash Ranjan 284324244cefSSai Prakash Ranjan cpu = <&CPU1>; 284424244cefSSai Prakash Ranjan 284524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 284624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 284724244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 284824244cefSSai Prakash Ranjan qcom,skip-power-up; 284924244cefSSai Prakash Ranjan 285024244cefSSai Prakash Ranjan out-ports { 285124244cefSSai Prakash Ranjan port { 285224244cefSSai Prakash Ranjan etm1_out: endpoint { 285324244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in1>; 285424244cefSSai Prakash Ranjan }; 285524244cefSSai Prakash Ranjan }; 285624244cefSSai Prakash Ranjan }; 285724244cefSSai Prakash Ranjan }; 285824244cefSSai Prakash Ranjan 285924244cefSSai Prakash Ranjan etm@7240000 { 286024244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 286124244cefSSai Prakash Ranjan reg = <0 0x07240000 0 0x1000>; 286224244cefSSai Prakash Ranjan 286324244cefSSai Prakash Ranjan cpu = <&CPU2>; 286424244cefSSai Prakash Ranjan 286524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 286624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 286724244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 286824244cefSSai Prakash Ranjan qcom,skip-power-up; 286924244cefSSai Prakash Ranjan 287024244cefSSai Prakash Ranjan out-ports { 287124244cefSSai Prakash Ranjan port { 287224244cefSSai Prakash Ranjan etm2_out: endpoint { 287324244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in2>; 287424244cefSSai Prakash Ranjan }; 287524244cefSSai Prakash Ranjan }; 287624244cefSSai Prakash Ranjan }; 287724244cefSSai Prakash Ranjan }; 287824244cefSSai Prakash Ranjan 287924244cefSSai Prakash Ranjan etm@7340000 { 288024244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 288124244cefSSai Prakash Ranjan reg = <0 0x07340000 0 0x1000>; 288224244cefSSai Prakash Ranjan 288324244cefSSai Prakash Ranjan cpu = <&CPU3>; 288424244cefSSai Prakash Ranjan 288524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 288624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 288724244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 288824244cefSSai Prakash Ranjan qcom,skip-power-up; 288924244cefSSai Prakash Ranjan 289024244cefSSai Prakash Ranjan out-ports { 289124244cefSSai Prakash Ranjan port { 289224244cefSSai Prakash Ranjan etm3_out: endpoint { 289324244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in3>; 289424244cefSSai Prakash Ranjan }; 289524244cefSSai Prakash Ranjan }; 289624244cefSSai Prakash Ranjan }; 289724244cefSSai Prakash Ranjan }; 289824244cefSSai Prakash Ranjan 289924244cefSSai Prakash Ranjan etm@7440000 { 290024244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 290124244cefSSai Prakash Ranjan reg = <0 0x07440000 0 0x1000>; 290224244cefSSai Prakash Ranjan 290324244cefSSai Prakash Ranjan cpu = <&CPU4>; 290424244cefSSai Prakash Ranjan 290524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 290624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 290724244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 290824244cefSSai Prakash Ranjan qcom,skip-power-up; 290924244cefSSai Prakash Ranjan 291024244cefSSai Prakash Ranjan out-ports { 291124244cefSSai Prakash Ranjan port { 291224244cefSSai Prakash Ranjan etm4_out: endpoint { 291324244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in4>; 291424244cefSSai Prakash Ranjan }; 291524244cefSSai Prakash Ranjan }; 291624244cefSSai Prakash Ranjan }; 291724244cefSSai Prakash Ranjan }; 291824244cefSSai Prakash Ranjan 291924244cefSSai Prakash Ranjan etm@7540000 { 292024244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 292124244cefSSai Prakash Ranjan reg = <0 0x07540000 0 0x1000>; 292224244cefSSai Prakash Ranjan 292324244cefSSai Prakash Ranjan cpu = <&CPU5>; 292424244cefSSai Prakash Ranjan 292524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 292624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 292724244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 292824244cefSSai Prakash Ranjan qcom,skip-power-up; 292924244cefSSai Prakash Ranjan 293024244cefSSai Prakash Ranjan out-ports { 293124244cefSSai Prakash Ranjan port { 293224244cefSSai Prakash Ranjan etm5_out: endpoint { 293324244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in5>; 293424244cefSSai Prakash Ranjan }; 293524244cefSSai Prakash Ranjan }; 293624244cefSSai Prakash Ranjan }; 293724244cefSSai Prakash Ranjan }; 293824244cefSSai Prakash Ranjan 293924244cefSSai Prakash Ranjan etm@7640000 { 294024244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 294124244cefSSai Prakash Ranjan reg = <0 0x07640000 0 0x1000>; 294224244cefSSai Prakash Ranjan 294324244cefSSai Prakash Ranjan cpu = <&CPU6>; 294424244cefSSai Prakash Ranjan 294524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 294624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 294724244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 294824244cefSSai Prakash Ranjan qcom,skip-power-up; 294924244cefSSai Prakash Ranjan 295024244cefSSai Prakash Ranjan out-ports { 295124244cefSSai Prakash Ranjan port { 295224244cefSSai Prakash Ranjan etm6_out: endpoint { 295324244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in6>; 295424244cefSSai Prakash Ranjan }; 295524244cefSSai Prakash Ranjan }; 295624244cefSSai Prakash Ranjan }; 295724244cefSSai Prakash Ranjan }; 295824244cefSSai Prakash Ranjan 295924244cefSSai Prakash Ranjan etm@7740000 { 296024244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 296124244cefSSai Prakash Ranjan reg = <0 0x07740000 0 0x1000>; 296224244cefSSai Prakash Ranjan 296324244cefSSai Prakash Ranjan cpu = <&CPU7>; 296424244cefSSai Prakash Ranjan 296524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 296624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 296724244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 296824244cefSSai Prakash Ranjan qcom,skip-power-up; 296924244cefSSai Prakash Ranjan 297024244cefSSai Prakash Ranjan out-ports { 297124244cefSSai Prakash Ranjan port { 297224244cefSSai Prakash Ranjan etm7_out: endpoint { 297324244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in7>; 297424244cefSSai Prakash Ranjan }; 297524244cefSSai Prakash Ranjan }; 297624244cefSSai Prakash Ranjan }; 297724244cefSSai Prakash Ranjan }; 297824244cefSSai Prakash Ranjan 297924244cefSSai Prakash Ranjan funnel@7800000 { /* APSS Funnel */ 298024244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 298124244cefSSai Prakash Ranjan reg = <0 0x07800000 0 0x1000>; 298224244cefSSai Prakash Ranjan 298324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 298424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 298524244cefSSai Prakash Ranjan 298624244cefSSai Prakash Ranjan out-ports { 298724244cefSSai Prakash Ranjan port { 298824244cefSSai Prakash Ranjan apss_funnel_out: endpoint { 298924244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_in>; 299024244cefSSai Prakash Ranjan }; 299124244cefSSai Prakash Ranjan }; 299224244cefSSai Prakash Ranjan }; 299324244cefSSai Prakash Ranjan 299424244cefSSai Prakash Ranjan in-ports { 299524244cefSSai Prakash Ranjan #address-cells = <1>; 299624244cefSSai Prakash Ranjan #size-cells = <0>; 299724244cefSSai Prakash Ranjan 299824244cefSSai Prakash Ranjan port@0 { 299924244cefSSai Prakash Ranjan reg = <0>; 300024244cefSSai Prakash Ranjan apss_funnel_in0: endpoint { 300124244cefSSai Prakash Ranjan remote-endpoint = <&etm0_out>; 300224244cefSSai Prakash Ranjan }; 300324244cefSSai Prakash Ranjan }; 300424244cefSSai Prakash Ranjan 300524244cefSSai Prakash Ranjan port@1 { 300624244cefSSai Prakash Ranjan reg = <1>; 300724244cefSSai Prakash Ranjan apss_funnel_in1: endpoint { 300824244cefSSai Prakash Ranjan remote-endpoint = <&etm1_out>; 300924244cefSSai Prakash Ranjan }; 301024244cefSSai Prakash Ranjan }; 301124244cefSSai Prakash Ranjan 301224244cefSSai Prakash Ranjan port@2 { 301324244cefSSai Prakash Ranjan reg = <2>; 301424244cefSSai Prakash Ranjan apss_funnel_in2: endpoint { 301524244cefSSai Prakash Ranjan remote-endpoint = <&etm2_out>; 301624244cefSSai Prakash Ranjan }; 301724244cefSSai Prakash Ranjan }; 301824244cefSSai Prakash Ranjan 301924244cefSSai Prakash Ranjan port@3 { 302024244cefSSai Prakash Ranjan reg = <3>; 302124244cefSSai Prakash Ranjan apss_funnel_in3: endpoint { 302224244cefSSai Prakash Ranjan remote-endpoint = <&etm3_out>; 302324244cefSSai Prakash Ranjan }; 302424244cefSSai Prakash Ranjan }; 302524244cefSSai Prakash Ranjan 302624244cefSSai Prakash Ranjan port@4 { 302724244cefSSai Prakash Ranjan reg = <4>; 302824244cefSSai Prakash Ranjan apss_funnel_in4: endpoint { 302924244cefSSai Prakash Ranjan remote-endpoint = <&etm4_out>; 303024244cefSSai Prakash Ranjan }; 303124244cefSSai Prakash Ranjan }; 303224244cefSSai Prakash Ranjan 303324244cefSSai Prakash Ranjan port@5 { 303424244cefSSai Prakash Ranjan reg = <5>; 303524244cefSSai Prakash Ranjan apss_funnel_in5: endpoint { 303624244cefSSai Prakash Ranjan remote-endpoint = <&etm5_out>; 303724244cefSSai Prakash Ranjan }; 303824244cefSSai Prakash Ranjan }; 303924244cefSSai Prakash Ranjan 304024244cefSSai Prakash Ranjan port@6 { 304124244cefSSai Prakash Ranjan reg = <6>; 304224244cefSSai Prakash Ranjan apss_funnel_in6: endpoint { 304324244cefSSai Prakash Ranjan remote-endpoint = <&etm6_out>; 304424244cefSSai Prakash Ranjan }; 304524244cefSSai Prakash Ranjan }; 304624244cefSSai Prakash Ranjan 304724244cefSSai Prakash Ranjan port@7 { 304824244cefSSai Prakash Ranjan reg = <7>; 304924244cefSSai Prakash Ranjan apss_funnel_in7: endpoint { 305024244cefSSai Prakash Ranjan remote-endpoint = <&etm7_out>; 305124244cefSSai Prakash Ranjan }; 305224244cefSSai Prakash Ranjan }; 305324244cefSSai Prakash Ranjan }; 305424244cefSSai Prakash Ranjan }; 305524244cefSSai Prakash Ranjan 305624244cefSSai Prakash Ranjan funnel@7810000 { 305724244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 305824244cefSSai Prakash Ranjan reg = <0 0x07810000 0 0x1000>; 305924244cefSSai Prakash Ranjan 306024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 306124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 306224244cefSSai Prakash Ranjan 306324244cefSSai Prakash Ranjan out-ports { 306424244cefSSai Prakash Ranjan port { 306524244cefSSai Prakash Ranjan apss_merge_funnel_out: endpoint { 306624244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_in2>; 306724244cefSSai Prakash Ranjan }; 306824244cefSSai Prakash Ranjan }; 306924244cefSSai Prakash Ranjan }; 307024244cefSSai Prakash Ranjan 307124244cefSSai Prakash Ranjan in-ports { 307224244cefSSai Prakash Ranjan port { 307324244cefSSai Prakash Ranjan apss_merge_funnel_in: endpoint { 307424244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_out>; 307524244cefSSai Prakash Ranjan }; 307624244cefSSai Prakash Ranjan }; 307724244cefSSai Prakash Ranjan }; 307824244cefSSai Prakash Ranjan }; 307924244cefSSai Prakash Ranjan 308049076351SSibi Sankar remoteproc_cdsp: remoteproc@8300000 { 308149076351SSibi Sankar compatible = "qcom,sm8150-cdsp-pas"; 308249076351SSibi Sankar reg = <0x0 0x08300000 0x0 0x4040>; 308349076351SSibi Sankar 308449076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 308549076351SSibi Sankar <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 308649076351SSibi Sankar <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 308749076351SSibi Sankar <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 308849076351SSibi Sankar <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 308949076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 309049076351SSibi Sankar "handover", "stop-ack"; 309149076351SSibi Sankar 309249076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 309349076351SSibi Sankar clock-names = "xo"; 309449076351SSibi Sankar 3095d9d327f6SSibi Sankar power-domains = <&rpmhpd 7>; 309649076351SSibi Sankar 309749076351SSibi Sankar memory-region = <&cdsp_mem>; 309849076351SSibi Sankar 3099d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 3100d9d327f6SSibi Sankar 310149076351SSibi Sankar qcom,smem-states = <&cdsp_smp2p_out 0>; 310249076351SSibi Sankar qcom,smem-state-names = "stop"; 310349076351SSibi Sankar 310449076351SSibi Sankar status = "disabled"; 310549076351SSibi Sankar 310649076351SSibi Sankar glink-edge { 310749076351SSibi Sankar interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 310849076351SSibi Sankar label = "cdsp"; 310949076351SSibi Sankar qcom,remote-pid = <5>; 311049076351SSibi Sankar mboxes = <&apss_shared 4>; 311181729330SBhupesh Sharma 311281729330SBhupesh Sharma fastrpc { 311381729330SBhupesh Sharma compatible = "qcom,fastrpc"; 311481729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 311581729330SBhupesh Sharma label = "cdsp"; 311681729330SBhupesh Sharma #address-cells = <1>; 311781729330SBhupesh Sharma #size-cells = <0>; 311881729330SBhupesh Sharma 311981729330SBhupesh Sharma compute-cb@1 { 312081729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 312181729330SBhupesh Sharma reg = <1>; 312281729330SBhupesh Sharma iommus = <&apps_smmu 0x1401 0x2040>, 312381729330SBhupesh Sharma <&apps_smmu 0x1421 0x0>, 312481729330SBhupesh Sharma <&apps_smmu 0x2001 0x420>, 312581729330SBhupesh Sharma <&apps_smmu 0x2041 0x0>; 312681729330SBhupesh Sharma }; 312781729330SBhupesh Sharma 312881729330SBhupesh Sharma compute-cb@2 { 312981729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 313081729330SBhupesh Sharma reg = <2>; 313181729330SBhupesh Sharma iommus = <&apps_smmu 0x2 0x3440>, 313281729330SBhupesh Sharma <&apps_smmu 0x22 0x3400>; 313381729330SBhupesh Sharma }; 313481729330SBhupesh Sharma 313581729330SBhupesh Sharma compute-cb@3 { 313681729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 313781729330SBhupesh Sharma reg = <3>; 313881729330SBhupesh Sharma iommus = <&apps_smmu 0x3 0x3440>, 313981729330SBhupesh Sharma <&apps_smmu 0x1423 0x0>, 314081729330SBhupesh Sharma <&apps_smmu 0x2023 0x0>; 314181729330SBhupesh Sharma }; 314281729330SBhupesh Sharma 314381729330SBhupesh Sharma compute-cb@4 { 314481729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 314581729330SBhupesh Sharma reg = <4>; 314681729330SBhupesh Sharma iommus = <&apps_smmu 0x4 0x3440>, 314781729330SBhupesh Sharma <&apps_smmu 0x24 0x3400>; 314881729330SBhupesh Sharma }; 314981729330SBhupesh Sharma 315081729330SBhupesh Sharma compute-cb@5 { 315181729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 315281729330SBhupesh Sharma reg = <5>; 315381729330SBhupesh Sharma iommus = <&apps_smmu 0x5 0x3440>, 315481729330SBhupesh Sharma <&apps_smmu 0x25 0x3400>; 315581729330SBhupesh Sharma }; 315681729330SBhupesh Sharma 315781729330SBhupesh Sharma compute-cb@6 { 315881729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 315981729330SBhupesh Sharma reg = <6>; 316081729330SBhupesh Sharma iommus = <&apps_smmu 0x6 0x3460>; 316181729330SBhupesh Sharma }; 316281729330SBhupesh Sharma 316381729330SBhupesh Sharma compute-cb@7 { 316481729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 316581729330SBhupesh Sharma reg = <7>; 316681729330SBhupesh Sharma iommus = <&apps_smmu 0x7 0x3460>; 316781729330SBhupesh Sharma }; 316881729330SBhupesh Sharma 316981729330SBhupesh Sharma compute-cb@8 { 317081729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 317181729330SBhupesh Sharma reg = <8>; 317281729330SBhupesh Sharma iommus = <&apps_smmu 0x8 0x3460>; 317381729330SBhupesh Sharma }; 317481729330SBhupesh Sharma 317581729330SBhupesh Sharma /* note: secure cb9 in downstream */ 317681729330SBhupesh Sharma }; 317749076351SSibi Sankar }; 317849076351SSibi Sankar }; 317949076351SSibi Sankar 3180b33d2868SJack Pham usb_1_hsphy: phy@88e2000 { 3181b33d2868SJack Pham compatible = "qcom,sm8150-usb-hs-phy", 3182b33d2868SJack Pham "qcom,usb-snps-hs-7nm-phy"; 3183b33d2868SJack Pham reg = <0 0x088e2000 0 0x400>; 3184b33d2868SJack Pham status = "disabled"; 3185b33d2868SJack Pham #phy-cells = <0>; 3186b33d2868SJack Pham 3187b33d2868SJack Pham clocks = <&rpmhcc RPMH_CXO_CLK>; 3188b33d2868SJack Pham clock-names = "ref"; 3189b33d2868SJack Pham 3190b33d2868SJack Pham resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3191b33d2868SJack Pham }; 3192b33d2868SJack Pham 31930c9dde0dSJonathan Marek usb_2_hsphy: phy@88e3000 { 31940c9dde0dSJonathan Marek compatible = "qcom,sm8150-usb-hs-phy", 31950c9dde0dSJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 31960c9dde0dSJonathan Marek reg = <0 0x088e3000 0 0x400>; 31970c9dde0dSJonathan Marek status = "disabled"; 31980c9dde0dSJonathan Marek #phy-cells = <0>; 31990c9dde0dSJonathan Marek 32000c9dde0dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 32010c9dde0dSJonathan Marek clock-names = "ref"; 32020c9dde0dSJonathan Marek 32030c9dde0dSJonathan Marek resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 32040c9dde0dSJonathan Marek }; 32050c9dde0dSJonathan Marek 3206b33d2868SJack Pham usb_1_qmpphy: phy@88e9000 { 3207b33d2868SJack Pham compatible = "qcom,sm8150-qmp-usb3-phy"; 3208b33d2868SJack Pham reg = <0 0x088e9000 0 0x18c>, 3209b33d2868SJack Pham <0 0x088e8000 0 0x10>; 3210b33d2868SJack Pham status = "disabled"; 3211b33d2868SJack Pham #address-cells = <2>; 3212b33d2868SJack Pham #size-cells = <2>; 3213b33d2868SJack Pham ranges; 3214b33d2868SJack Pham 3215b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3216b33d2868SJack Pham <&rpmhcc RPMH_CXO_CLK>, 3217b33d2868SJack Pham <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3218b33d2868SJack Pham <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3219b33d2868SJack Pham clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3220b33d2868SJack Pham 3221b33d2868SJack Pham resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3222b33d2868SJack Pham <&gcc GCC_USB3_PHY_PRIM_BCR>; 3223b33d2868SJack Pham reset-names = "phy", "common"; 3224b33d2868SJack Pham 32251351512fSShawn Guo usb_1_ssphy: phy@88e9200 { 3226b33d2868SJack Pham reg = <0 0x088e9200 0 0x200>, 3227b33d2868SJack Pham <0 0x088e9400 0 0x200>, 3228b33d2868SJack Pham <0 0x088e9c00 0 0x218>, 3229b33d2868SJack Pham <0 0x088e9600 0 0x200>, 3230b33d2868SJack Pham <0 0x088e9800 0 0x200>, 3231b33d2868SJack Pham <0 0x088e9a00 0 0x100>; 32327178d4ccSJonathan Marek #clock-cells = <0>; 3233b33d2868SJack Pham #phy-cells = <0>; 3234b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3235b33d2868SJack Pham clock-names = "pipe0"; 3236b33d2868SJack Pham clock-output-names = "usb3_phy_pipe_clk_src"; 3237b33d2868SJack Pham }; 3238b33d2868SJack Pham }; 3239b33d2868SJack Pham 32400c9dde0dSJonathan Marek usb_2_qmpphy: phy@88eb000 { 32410c9dde0dSJonathan Marek compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 32420c9dde0dSJonathan Marek reg = <0 0x088eb000 0 0x200>; 32430c9dde0dSJonathan Marek status = "disabled"; 32440c9dde0dSJonathan Marek #address-cells = <2>; 32450c9dde0dSJonathan Marek #size-cells = <2>; 32460c9dde0dSJonathan Marek ranges; 32470c9dde0dSJonathan Marek 32480c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 32490c9dde0dSJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 32500c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>, 32510c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 32520c9dde0dSJonathan Marek clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 32530c9dde0dSJonathan Marek 32540c9dde0dSJonathan Marek resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 32550c9dde0dSJonathan Marek <&gcc GCC_USB3_PHY_SEC_BCR>; 32560c9dde0dSJonathan Marek reset-names = "phy", "common"; 32570c9dde0dSJonathan Marek 32581351512fSShawn Guo usb_2_ssphy: phy@88eb200 { 32590c9dde0dSJonathan Marek reg = <0 0x088eb200 0 0x200>, 32600c9dde0dSJonathan Marek <0 0x088eb400 0 0x200>, 32610c9dde0dSJonathan Marek <0 0x088eb800 0 0x800>, 32620c9dde0dSJonathan Marek <0 0x088eb600 0 0x200>; 32637178d4ccSJonathan Marek #clock-cells = <0>; 32640c9dde0dSJonathan Marek #phy-cells = <0>; 32650c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 32660c9dde0dSJonathan Marek clock-names = "pipe0"; 32670c9dde0dSJonathan Marek clock-output-names = "usb3_uni_phy_pipe_clk_src"; 32680c9dde0dSJonathan Marek }; 32690c9dde0dSJonathan Marek }; 32700c9dde0dSJonathan Marek 32715dc43d3bSBhupesh Sharma dc_noc: interconnect@9160000 { 32725dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-dc-noc"; 32735dc43d3bSBhupesh Sharma reg = <0 0x09160000 0 0x3200>; 32745dc43d3bSBhupesh Sharma #interconnect-cells = <1>; 32755dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 32765dc43d3bSBhupesh Sharma }; 32775dc43d3bSBhupesh Sharma 32785dc43d3bSBhupesh Sharma gem_noc: interconnect@9680000 { 32795dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-gem-noc"; 32805dc43d3bSBhupesh Sharma reg = <0 0x09680000 0 0x3e200>; 32815dc43d3bSBhupesh Sharma #interconnect-cells = <1>; 32825dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 32835dc43d3bSBhupesh Sharma }; 32845dc43d3bSBhupesh Sharma 3285b33d2868SJack Pham usb_1: usb@a6f8800 { 3286b33d2868SJack Pham compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3287b33d2868SJack Pham reg = <0 0x0a6f8800 0 0x400>; 3288b33d2868SJack Pham status = "disabled"; 3289b33d2868SJack Pham #address-cells = <2>; 3290b33d2868SJack Pham #size-cells = <2>; 3291b33d2868SJack Pham ranges; 3292b33d2868SJack Pham dma-ranges; 3293b33d2868SJack Pham 3294b33d2868SJack Pham clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3295b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3296b33d2868SJack Pham <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3297b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3298b33d2868SJack Pham <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3299b33d2868SJack Pham <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3300b33d2868SJack Pham clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3301b33d2868SJack Pham "sleep", "xo"; 3302b33d2868SJack Pham 3303b33d2868SJack Pham assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3304b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>; 330579493db5SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 3306b33d2868SJack Pham 3307b33d2868SJack Pham interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3308b33d2868SJack Pham <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3309b33d2868SJack Pham <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3310b33d2868SJack Pham <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3311b33d2868SJack Pham interrupt-names = "hs_phy_irq", "ss_phy_irq", 3312b33d2868SJack Pham "dm_hs_phy_irq", "dp_hs_phy_irq"; 3313b33d2868SJack Pham 3314b33d2868SJack Pham power-domains = <&gcc USB30_PRIM_GDSC>; 3315b33d2868SJack Pham 3316b33d2868SJack Pham resets = <&gcc GCC_USB30_PRIM_BCR>; 3317b33d2868SJack Pham 33181f958f3dSGreg Kroah-Hartman usb_1_dwc3: dwc3@a600000 { 3319b33d2868SJack Pham compatible = "snps,dwc3"; 3320b33d2868SJack Pham reg = <0 0x0a600000 0 0xcd00>; 3321b33d2868SJack Pham interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 332248156232SJonathan Marek iommus = <&apps_smmu 0x140 0>; 3323b33d2868SJack Pham snps,dis_u2_susphy_quirk; 3324b33d2868SJack Pham snps,dis_enblslpm_quirk; 3325b33d2868SJack Pham phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3326b33d2868SJack Pham phy-names = "usb2-phy", "usb3-phy"; 3327b33d2868SJack Pham }; 3328b33d2868SJack Pham }; 3329b33d2868SJack Pham 33300c9dde0dSJonathan Marek usb_2: usb@a8f8800 { 33310c9dde0dSJonathan Marek compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 33320c9dde0dSJonathan Marek reg = <0 0x0a8f8800 0 0x400>; 33330c9dde0dSJonathan Marek status = "disabled"; 33340c9dde0dSJonathan Marek #address-cells = <2>; 33350c9dde0dSJonathan Marek #size-cells = <2>; 33360c9dde0dSJonathan Marek ranges; 33370c9dde0dSJonathan Marek dma-ranges; 33380c9dde0dSJonathan Marek 33390c9dde0dSJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 33400c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>, 33410c9dde0dSJonathan Marek <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 33420c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 33430c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_SLEEP_CLK>, 33440c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>; 33450c9dde0dSJonathan Marek clock-names = "cfg_noc", "core", "iface", "mock_utmi", 33460c9dde0dSJonathan Marek "sleep", "xo"; 33470c9dde0dSJonathan Marek 33480c9dde0dSJonathan Marek assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 33490c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>; 33500c9dde0dSJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 33510c9dde0dSJonathan Marek 33520c9dde0dSJonathan Marek interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 33530c9dde0dSJonathan Marek <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 33540c9dde0dSJonathan Marek <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 33550c9dde0dSJonathan Marek <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 33560c9dde0dSJonathan Marek interrupt-names = "hs_phy_irq", "ss_phy_irq", 33570c9dde0dSJonathan Marek "dm_hs_phy_irq", "dp_hs_phy_irq"; 33580c9dde0dSJonathan Marek 33590c9dde0dSJonathan Marek power-domains = <&gcc USB30_SEC_GDSC>; 33600c9dde0dSJonathan Marek 33610c9dde0dSJonathan Marek resets = <&gcc GCC_USB30_SEC_BCR>; 33620c9dde0dSJonathan Marek 33632aa2b50dSBhupesh Sharma usb_2_dwc3: usb@a800000 { 33640c9dde0dSJonathan Marek compatible = "snps,dwc3"; 33650c9dde0dSJonathan Marek reg = <0 0x0a800000 0 0xcd00>; 33660c9dde0dSJonathan Marek interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 33670c9dde0dSJonathan Marek iommus = <&apps_smmu 0x160 0>; 33680c9dde0dSJonathan Marek snps,dis_u2_susphy_quirk; 33690c9dde0dSJonathan Marek snps,dis_enblslpm_quirk; 33700c9dde0dSJonathan Marek phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 33710c9dde0dSJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 33720c9dde0dSJonathan Marek }; 33730c9dde0dSJonathan Marek }; 33740c9dde0dSJonathan Marek 33756acb71fdSJonathan Marek camnoc_virt: interconnect@ac00000 { 33766acb71fdSJonathan Marek compatible = "qcom,sm8150-camnoc-virt"; 33776acb71fdSJonathan Marek reg = <0 0x0ac00000 0 0x1000>; 33786acb71fdSJonathan Marek #interconnect-cells = <1>; 33796acb71fdSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 33806acb71fdSJonathan Marek }; 33816acb71fdSJonathan Marek 3382d8cf9372SVinod Koul aoss_qmp: power-controller@c300000 { 3383d8cf9372SVinod Koul compatible = "qcom,sm8150-aoss-qmp"; 338447cb6a06SMaulik Shah reg = <0x0 0x0c300000 0x0 0x400>; 3385d8cf9372SVinod Koul interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3386d8cf9372SVinod Koul mboxes = <&apss_shared 0>; 3387d8cf9372SVinod Koul 3388d8cf9372SVinod Koul #clock-cells = <0>; 3389d8cf9372SVinod Koul }; 3390d8cf9372SVinod Koul 339147cb6a06SMaulik Shah sram@c3f0000 { 339247cb6a06SMaulik Shah compatible = "qcom,rpmh-stats"; 339347cb6a06SMaulik Shah reg = <0 0x0c3f0000 0 0x400>; 339447cb6a06SMaulik Shah }; 339547cb6a06SMaulik Shah 3396d2fa630cSAmit Kucheria tsens0: thermal-sensor@c263000 { 3397d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3398d2fa630cSAmit Kucheria reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3399d2fa630cSAmit Kucheria <0 0x0c222000 0 0x1ff>; /* SROT */ 3400d2fa630cSAmit Kucheria #qcom,sensors = <16>; 3401d2fa630cSAmit Kucheria interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3402d2fa630cSAmit Kucheria <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3403d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 3404d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 3405d2fa630cSAmit Kucheria }; 3406d2fa630cSAmit Kucheria 3407d2fa630cSAmit Kucheria tsens1: thermal-sensor@c265000 { 3408d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3409d2fa630cSAmit Kucheria reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3410d2fa630cSAmit Kucheria <0 0x0c223000 0 0x1ff>; /* SROT */ 3411d2fa630cSAmit Kucheria #qcom,sensors = <8>; 3412d2fa630cSAmit Kucheria interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3413d2fa630cSAmit Kucheria <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3414d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 3415d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 3416d2fa630cSAmit Kucheria }; 3417d2fa630cSAmit Kucheria 3418e13c6d14SVinod Koul spmi_bus: spmi@c440000 { 3419e13c6d14SVinod Koul compatible = "qcom,spmi-pmic-arb"; 3420e13c6d14SVinod Koul reg = <0x0 0x0c440000 0x0 0x0001100>, 3421e13c6d14SVinod Koul <0x0 0x0c600000 0x0 0x2000000>, 3422e13c6d14SVinod Koul <0x0 0x0e600000 0x0 0x0100000>, 3423e13c6d14SVinod Koul <0x0 0x0e700000 0x0 0x00a0000>, 3424e13c6d14SVinod Koul <0x0 0x0c40a000 0x0 0x0026000>; 3425e13c6d14SVinod Koul reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3426e13c6d14SVinod Koul interrupt-names = "periph_irq"; 3427e13c6d14SVinod Koul interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3428e13c6d14SVinod Koul qcom,ee = <0>; 3429e13c6d14SVinod Koul qcom,channel = <0>; 3430e13c6d14SVinod Koul #address-cells = <2>; 3431e13c6d14SVinod Koul #size-cells = <0>; 3432e13c6d14SVinod Koul interrupt-controller; 3433e13c6d14SVinod Koul #interrupt-cells = <4>; 3434e13c6d14SVinod Koul cell-index = <0>; 3435e13c6d14SVinod Koul }; 3436e13c6d14SVinod Koul 343748156232SJonathan Marek apps_smmu: iommu@15000000 { 343848156232SJonathan Marek compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 343948156232SJonathan Marek reg = <0 0x15000000 0 0x100000>; 344048156232SJonathan Marek #iommu-cells = <2>; 344148156232SJonathan Marek #global-interrupts = <1>; 344248156232SJonathan Marek interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 344348156232SJonathan Marek <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 344448156232SJonathan Marek <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 344548156232SJonathan Marek <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 344648156232SJonathan Marek <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 344748156232SJonathan Marek <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 344848156232SJonathan Marek <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 344948156232SJonathan Marek <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 345048156232SJonathan Marek <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 345148156232SJonathan Marek <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 345248156232SJonathan Marek <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 345348156232SJonathan Marek <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 345448156232SJonathan Marek <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 345548156232SJonathan Marek <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 345648156232SJonathan Marek <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 345748156232SJonathan Marek <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 345848156232SJonathan Marek <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 345948156232SJonathan Marek <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 346048156232SJonathan Marek <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 346148156232SJonathan Marek <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 346248156232SJonathan Marek <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 346348156232SJonathan Marek <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 346448156232SJonathan Marek <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 346548156232SJonathan Marek <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 346648156232SJonathan Marek <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 346748156232SJonathan Marek <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 346848156232SJonathan Marek <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 346948156232SJonathan Marek <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 347048156232SJonathan Marek <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 347148156232SJonathan Marek <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 347248156232SJonathan Marek <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 347348156232SJonathan Marek <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 347448156232SJonathan Marek <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 347548156232SJonathan Marek <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 347648156232SJonathan Marek <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 347748156232SJonathan Marek <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 347848156232SJonathan Marek <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 347948156232SJonathan Marek <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 348048156232SJonathan Marek <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 348148156232SJonathan Marek <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 348248156232SJonathan Marek <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 348348156232SJonathan Marek <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 348448156232SJonathan Marek <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 348548156232SJonathan Marek <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 348648156232SJonathan Marek <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 348748156232SJonathan Marek <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 348848156232SJonathan Marek <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 348948156232SJonathan Marek <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 349048156232SJonathan Marek <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 349148156232SJonathan Marek <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 349248156232SJonathan Marek <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 349348156232SJonathan Marek <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 349448156232SJonathan Marek <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 349548156232SJonathan Marek <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 349648156232SJonathan Marek <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 349748156232SJonathan Marek <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 349848156232SJonathan Marek <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 349948156232SJonathan Marek <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 350048156232SJonathan Marek <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 350148156232SJonathan Marek <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 350248156232SJonathan Marek <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 350348156232SJonathan Marek <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 350448156232SJonathan Marek <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 350548156232SJonathan Marek <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 350648156232SJonathan Marek <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 350748156232SJonathan Marek <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 350848156232SJonathan Marek <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 350948156232SJonathan Marek <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 351048156232SJonathan Marek <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 351148156232SJonathan Marek <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 351248156232SJonathan Marek <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 351348156232SJonathan Marek <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 351448156232SJonathan Marek <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 351548156232SJonathan Marek <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 351648156232SJonathan Marek <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 351748156232SJonathan Marek <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 351848156232SJonathan Marek <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 351948156232SJonathan Marek <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 352048156232SJonathan Marek <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 352148156232SJonathan Marek <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 352248156232SJonathan Marek <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 352348156232SJonathan Marek }; 352448156232SJonathan Marek 352549076351SSibi Sankar remoteproc_adsp: remoteproc@17300000 { 352649076351SSibi Sankar compatible = "qcom,sm8150-adsp-pas"; 352749076351SSibi Sankar reg = <0x0 0x17300000 0x0 0x4040>; 352849076351SSibi Sankar 352949076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 353049076351SSibi Sankar <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 353149076351SSibi Sankar <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 353249076351SSibi Sankar <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 353349076351SSibi Sankar <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 353449076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 353549076351SSibi Sankar "handover", "stop-ack"; 353649076351SSibi Sankar 353749076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 353849076351SSibi Sankar clock-names = "xo"; 353949076351SSibi Sankar 3540d9d327f6SSibi Sankar power-domains = <&rpmhpd 7>; 354149076351SSibi Sankar 354249076351SSibi Sankar memory-region = <&adsp_mem>; 354349076351SSibi Sankar 3544d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 3545d9d327f6SSibi Sankar 354649076351SSibi Sankar qcom,smem-states = <&adsp_smp2p_out 0>; 354749076351SSibi Sankar qcom,smem-state-names = "stop"; 354849076351SSibi Sankar 354949076351SSibi Sankar status = "disabled"; 355049076351SSibi Sankar 355149076351SSibi Sankar glink-edge { 355249076351SSibi Sankar interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 355349076351SSibi Sankar label = "lpass"; 355449076351SSibi Sankar qcom,remote-pid = <2>; 355549076351SSibi Sankar mboxes = <&apss_shared 8>; 355681729330SBhupesh Sharma 355781729330SBhupesh Sharma fastrpc { 355881729330SBhupesh Sharma compatible = "qcom,fastrpc"; 355981729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 356081729330SBhupesh Sharma label = "adsp"; 356181729330SBhupesh Sharma #address-cells = <1>; 356281729330SBhupesh Sharma #size-cells = <0>; 356381729330SBhupesh Sharma 356481729330SBhupesh Sharma compute-cb@3 { 356581729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 356681729330SBhupesh Sharma reg = <3>; 356781729330SBhupesh Sharma iommus = <&apps_smmu 0x1b23 0x0>; 356881729330SBhupesh Sharma }; 356981729330SBhupesh Sharma 357081729330SBhupesh Sharma compute-cb@4 { 357181729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 357281729330SBhupesh Sharma reg = <4>; 357381729330SBhupesh Sharma iommus = <&apps_smmu 0x1b24 0x0>; 357481729330SBhupesh Sharma }; 357581729330SBhupesh Sharma 357681729330SBhupesh Sharma compute-cb@5 { 357781729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 357881729330SBhupesh Sharma reg = <5>; 357981729330SBhupesh Sharma iommus = <&apps_smmu 0x1b25 0x0>; 358081729330SBhupesh Sharma }; 358181729330SBhupesh Sharma }; 358249076351SSibi Sankar }; 358349076351SSibi Sankar }; 358449076351SSibi Sankar 3585e13c6d14SVinod Koul intc: interrupt-controller@17a00000 { 3586e13c6d14SVinod Koul compatible = "arm,gic-v3"; 3587e13c6d14SVinod Koul interrupt-controller; 3588e13c6d14SVinod Koul #interrupt-cells = <3>; 3589e13c6d14SVinod Koul reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3590e13c6d14SVinod Koul <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3591e13c6d14SVinod Koul interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3592e13c6d14SVinod Koul }; 3593e13c6d14SVinod Koul 3594d8cf9372SVinod Koul apss_shared: mailbox@17c00000 { 3595d8cf9372SVinod Koul compatible = "qcom,sm8150-apss-shared"; 3596d8cf9372SVinod Koul reg = <0x0 0x17c00000 0x0 0x1000>; 3597d8cf9372SVinod Koul #mbox-cells = <1>; 3598d8cf9372SVinod Koul }; 3599d8cf9372SVinod Koul 3600fb2d8150SSai Prakash Ranjan watchdog@17c10000 { 3601fb2d8150SSai Prakash Ranjan compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 3602fb2d8150SSai Prakash Ranjan reg = <0 0x17c10000 0 0x1000>; 3603fb2d8150SSai Prakash Ranjan clocks = <&sleep_clk>; 3604b094c8f8SSai Prakash Ranjan interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3605fb2d8150SSai Prakash Ranjan }; 3606fb2d8150SSai Prakash Ranjan 3607e13c6d14SVinod Koul timer@17c20000 { 3608e13c6d14SVinod Koul #address-cells = <2>; 3609e13c6d14SVinod Koul #size-cells = <2>; 3610e13c6d14SVinod Koul ranges; 3611e13c6d14SVinod Koul compatible = "arm,armv7-timer-mem"; 3612e13c6d14SVinod Koul reg = <0x0 0x17c20000 0x0 0x1000>; 3613e13c6d14SVinod Koul clock-frequency = <19200000>; 3614e13c6d14SVinod Koul 3615e13c6d14SVinod Koul frame@17c21000{ 3616e13c6d14SVinod Koul frame-number = <0>; 3617e13c6d14SVinod Koul interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3618e13c6d14SVinod Koul <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3619e13c6d14SVinod Koul reg = <0x0 0x17c21000 0x0 0x1000>, 3620e13c6d14SVinod Koul <0x0 0x17c22000 0x0 0x1000>; 3621e13c6d14SVinod Koul }; 3622e13c6d14SVinod Koul 3623e13c6d14SVinod Koul frame@17c23000 { 3624e13c6d14SVinod Koul frame-number = <1>; 3625e13c6d14SVinod Koul interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3626e13c6d14SVinod Koul reg = <0x0 0x17c23000 0x0 0x1000>; 3627e13c6d14SVinod Koul status = "disabled"; 3628e13c6d14SVinod Koul }; 3629e13c6d14SVinod Koul 3630e13c6d14SVinod Koul frame@17c25000 { 3631e13c6d14SVinod Koul frame-number = <2>; 3632e13c6d14SVinod Koul interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3633e13c6d14SVinod Koul reg = <0x0 0x17c25000 0x0 0x1000>; 3634e13c6d14SVinod Koul status = "disabled"; 3635e13c6d14SVinod Koul }; 3636e13c6d14SVinod Koul 3637e13c6d14SVinod Koul frame@17c27000 { 3638e13c6d14SVinod Koul frame-number = <3>; 3639e13c6d14SVinod Koul interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3640e13c6d14SVinod Koul reg = <0x0 0x17c26000 0x0 0x1000>; 3641e13c6d14SVinod Koul status = "disabled"; 3642e13c6d14SVinod Koul }; 3643e13c6d14SVinod Koul 3644e13c6d14SVinod Koul frame@17c29000 { 3645e13c6d14SVinod Koul frame-number = <4>; 3646e13c6d14SVinod Koul interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3647e13c6d14SVinod Koul reg = <0x0 0x17c29000 0x0 0x1000>; 3648e13c6d14SVinod Koul status = "disabled"; 3649e13c6d14SVinod Koul }; 3650e13c6d14SVinod Koul 3651e13c6d14SVinod Koul frame@17c2b000 { 3652e13c6d14SVinod Koul frame-number = <5>; 3653e13c6d14SVinod Koul interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3654e13c6d14SVinod Koul reg = <0x0 0x17c2b000 0x0 0x1000>; 3655e13c6d14SVinod Koul status = "disabled"; 3656e13c6d14SVinod Koul }; 3657e13c6d14SVinod Koul 3658e13c6d14SVinod Koul frame@17c2d000 { 3659e13c6d14SVinod Koul frame-number = <6>; 3660e13c6d14SVinod Koul interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3661e13c6d14SVinod Koul reg = <0x0 0x17c2d000 0x0 0x1000>; 3662e13c6d14SVinod Koul status = "disabled"; 3663e13c6d14SVinod Koul }; 3664e13c6d14SVinod Koul }; 3665d8cf9372SVinod Koul 3666d8cf9372SVinod Koul apps_rsc: rsc@18200000 { 3667d8cf9372SVinod Koul label = "apps_rsc"; 3668d8cf9372SVinod Koul compatible = "qcom,rpmh-rsc"; 3669d8cf9372SVinod Koul reg = <0x0 0x18200000 0x0 0x10000>, 3670d8cf9372SVinod Koul <0x0 0x18210000 0x0 0x10000>, 3671d8cf9372SVinod Koul <0x0 0x18220000 0x0 0x10000>; 3672d8cf9372SVinod Koul reg-names = "drv-0", "drv-1", "drv-2"; 3673d8cf9372SVinod Koul interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3674d8cf9372SVinod Koul <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3675d8cf9372SVinod Koul <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3676d8cf9372SVinod Koul qcom,tcs-offset = <0xd00>; 3677d8cf9372SVinod Koul qcom,drv-id = <2>; 3678d8cf9372SVinod Koul qcom,tcs-config = <ACTIVE_TCS 2>, 3679d8cf9372SVinod Koul <SLEEP_TCS 1>, 3680d8cf9372SVinod Koul <WAKE_TCS 1>, 3681d8cf9372SVinod Koul <CONTROL_TCS 0>; 3682d8cf9372SVinod Koul 3683d8cf9372SVinod Koul rpmhcc: clock-controller { 3684d8cf9372SVinod Koul compatible = "qcom,sm8150-rpmh-clk"; 3685d8cf9372SVinod Koul #clock-cells = <1>; 3686d8cf9372SVinod Koul clock-names = "xo"; 3687d8cf9372SVinod Koul clocks = <&xo_board>; 3688d8cf9372SVinod Koul }; 3689017e7856SSibi Sankar 3690017e7856SSibi Sankar rpmhpd: power-controller { 3691017e7856SSibi Sankar compatible = "qcom,sm8150-rpmhpd"; 3692017e7856SSibi Sankar #power-domain-cells = <1>; 3693017e7856SSibi Sankar operating-points-v2 = <&rpmhpd_opp_table>; 3694017e7856SSibi Sankar 3695017e7856SSibi Sankar rpmhpd_opp_table: opp-table { 3696017e7856SSibi Sankar compatible = "operating-points-v2"; 3697017e7856SSibi Sankar 3698017e7856SSibi Sankar rpmhpd_opp_ret: opp1 { 3699017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3700017e7856SSibi Sankar }; 3701017e7856SSibi Sankar 3702017e7856SSibi Sankar rpmhpd_opp_min_svs: opp2 { 3703017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3704017e7856SSibi Sankar }; 3705017e7856SSibi Sankar 3706017e7856SSibi Sankar rpmhpd_opp_low_svs: opp3 { 3707017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3708017e7856SSibi Sankar }; 3709017e7856SSibi Sankar 3710017e7856SSibi Sankar rpmhpd_opp_svs: opp4 { 3711017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3712017e7856SSibi Sankar }; 3713017e7856SSibi Sankar 3714017e7856SSibi Sankar rpmhpd_opp_svs_l1: opp5 { 3715017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3716017e7856SSibi Sankar }; 3717017e7856SSibi Sankar 3718017e7856SSibi Sankar rpmhpd_opp_svs_l2: opp6 { 3719017e7856SSibi Sankar opp-level = <224>; 3720017e7856SSibi Sankar }; 3721017e7856SSibi Sankar 3722017e7856SSibi Sankar rpmhpd_opp_nom: opp7 { 3723017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3724017e7856SSibi Sankar }; 3725017e7856SSibi Sankar 3726017e7856SSibi Sankar rpmhpd_opp_nom_l1: opp8 { 3727017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3728017e7856SSibi Sankar }; 3729017e7856SSibi Sankar 3730017e7856SSibi Sankar rpmhpd_opp_nom_l2: opp9 { 3731017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3732017e7856SSibi Sankar }; 3733017e7856SSibi Sankar 3734017e7856SSibi Sankar rpmhpd_opp_turbo: opp10 { 3735017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3736017e7856SSibi Sankar }; 3737017e7856SSibi Sankar 3738017e7856SSibi Sankar rpmhpd_opp_turbo_l1: opp11 { 3739017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3740017e7856SSibi Sankar }; 3741017e7856SSibi Sankar }; 3742017e7856SSibi Sankar }; 374371a2fc6eSJonathan Marek 374471a2fc6eSJonathan Marek apps_bcm_voter: bcm_voter { 374571a2fc6eSJonathan Marek compatible = "qcom,bcm-voter"; 374671a2fc6eSJonathan Marek }; 3747d8cf9372SVinod Koul }; 3748fea8930bSSibi Sankar 3749a6d435c1SSibi Sankar osm_l3: interconnect@18321000 { 3750a6d435c1SSibi Sankar compatible = "qcom,sm8150-osm-l3"; 3751a6d435c1SSibi Sankar reg = <0 0x18321000 0 0x1400>; 3752a6d435c1SSibi Sankar 3753a6d435c1SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3754a6d435c1SSibi Sankar clock-names = "xo", "alternate"; 3755a6d435c1SSibi Sankar 3756a6d435c1SSibi Sankar #interconnect-cells = <1>; 3757a6d435c1SSibi Sankar }; 3758a6d435c1SSibi Sankar 3759fea8930bSSibi Sankar cpufreq_hw: cpufreq@18323000 { 3760fea8930bSSibi Sankar compatible = "qcom,cpufreq-hw"; 3761fea8930bSSibi Sankar reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 3762fea8930bSSibi Sankar <0 0x18327800 0 0x1400>; 3763fea8930bSSibi Sankar reg-names = "freq-domain0", "freq-domain1", 3764fea8930bSSibi Sankar "freq-domain2"; 3765fea8930bSSibi Sankar 3766fea8930bSSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3767fea8930bSSibi Sankar clock-names = "xo", "alternate"; 3768fea8930bSSibi Sankar 3769fea8930bSSibi Sankar #freq-domain-cells = <1>; 3770fea8930bSSibi Sankar }; 377105090bb9SJonathan Marek 3772*2ffcfe79SThara Gopinath lmh_cluster1: lmh@18350800 { 3773*2ffcfe79SThara Gopinath compatible = "qcom,sm8150-lmh"; 3774*2ffcfe79SThara Gopinath reg = <0 0x18350800 0 0x400>; 3775*2ffcfe79SThara Gopinath interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3776*2ffcfe79SThara Gopinath cpus = <&CPU4>; 3777*2ffcfe79SThara Gopinath qcom,lmh-temp-arm-millicelsius = <60000>; 3778*2ffcfe79SThara Gopinath qcom,lmh-temp-low-millicelsius = <84500>; 3779*2ffcfe79SThara Gopinath qcom,lmh-temp-high-millicelsius = <85000>; 3780*2ffcfe79SThara Gopinath interrupt-controller; 3781*2ffcfe79SThara Gopinath #interrupt-cells = <1>; 3782*2ffcfe79SThara Gopinath }; 3783*2ffcfe79SThara Gopinath 3784*2ffcfe79SThara Gopinath lmh_cluster0: lmh@18358800 { 3785*2ffcfe79SThara Gopinath compatible = "qcom,sm8150-lmh"; 3786*2ffcfe79SThara Gopinath reg = <0 0x18358800 0 0x400>; 3787*2ffcfe79SThara Gopinath interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3788*2ffcfe79SThara Gopinath cpus = <&CPU0>; 3789*2ffcfe79SThara Gopinath qcom,lmh-temp-arm-millicelsius = <60000>; 3790*2ffcfe79SThara Gopinath qcom,lmh-temp-low-millicelsius = <84500>; 3791*2ffcfe79SThara Gopinath qcom,lmh-temp-high-millicelsius = <85000>; 3792*2ffcfe79SThara Gopinath interrupt-controller; 3793*2ffcfe79SThara Gopinath #interrupt-cells = <1>; 3794*2ffcfe79SThara Gopinath }; 3795*2ffcfe79SThara Gopinath 379605090bb9SJonathan Marek wifi: wifi@18800000 { 379705090bb9SJonathan Marek compatible = "qcom,wcn3990-wifi"; 379805090bb9SJonathan Marek reg = <0 0x18800000 0 0x800000>; 379905090bb9SJonathan Marek reg-names = "membase"; 380005090bb9SJonathan Marek memory-region = <&wlan_mem>; 380105090bb9SJonathan Marek clock-names = "cxo_ref_clk_pin", "qdss"; 380205090bb9SJonathan Marek clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 380305090bb9SJonathan Marek interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 380405090bb9SJonathan Marek <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 380505090bb9SJonathan Marek <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 380605090bb9SJonathan Marek <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 380705090bb9SJonathan Marek <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 380805090bb9SJonathan Marek <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 380905090bb9SJonathan Marek <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 381005090bb9SJonathan Marek <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 381105090bb9SJonathan Marek <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 381205090bb9SJonathan Marek <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 381305090bb9SJonathan Marek <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 381405090bb9SJonathan Marek <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 381505090bb9SJonathan Marek iommus = <&apps_smmu 0x0640 0x1>; 381605090bb9SJonathan Marek status = "disabled"; 381705090bb9SJonathan Marek }; 3818e13c6d14SVinod Koul }; 3819e13c6d14SVinod Koul 3820e13c6d14SVinod Koul timer { 3821e13c6d14SVinod Koul compatible = "arm,armv8-timer"; 3822e13c6d14SVinod Koul interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 3823e13c6d14SVinod Koul <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 3824e13c6d14SVinod Koul <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 3825e13c6d14SVinod Koul <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 3826e13c6d14SVinod Koul }; 3827d2fa630cSAmit Kucheria 3828d2fa630cSAmit Kucheria thermal-zones { 3829d2fa630cSAmit Kucheria cpu0-thermal { 3830d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3831d2fa630cSAmit Kucheria polling-delay = <1000>; 3832d2fa630cSAmit Kucheria 3833d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 1>; 3834d2fa630cSAmit Kucheria 3835d2fa630cSAmit Kucheria trips { 3836d2fa630cSAmit Kucheria cpu0_alert0: trip-point0 { 3837d2fa630cSAmit Kucheria temperature = <90000>; 3838d2fa630cSAmit Kucheria hysteresis = <2000>; 3839d2fa630cSAmit Kucheria type = "passive"; 3840d2fa630cSAmit Kucheria }; 3841d2fa630cSAmit Kucheria 3842d2fa630cSAmit Kucheria cpu0_alert1: trip-point1 { 3843d2fa630cSAmit Kucheria temperature = <95000>; 3844d2fa630cSAmit Kucheria hysteresis = <2000>; 3845d2fa630cSAmit Kucheria type = "passive"; 3846d2fa630cSAmit Kucheria }; 3847d2fa630cSAmit Kucheria 3848d2fa630cSAmit Kucheria cpu0_crit: cpu_crit { 3849d2fa630cSAmit Kucheria temperature = <110000>; 3850d2fa630cSAmit Kucheria hysteresis = <1000>; 3851d2fa630cSAmit Kucheria type = "critical"; 3852d2fa630cSAmit Kucheria }; 3853d2fa630cSAmit Kucheria }; 3854d2fa630cSAmit Kucheria 3855d2fa630cSAmit Kucheria cooling-maps { 3856d2fa630cSAmit Kucheria map0 { 3857d2fa630cSAmit Kucheria trip = <&cpu0_alert0>; 3858d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3859d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3860d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3861d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3862d2fa630cSAmit Kucheria }; 3863d2fa630cSAmit Kucheria map1 { 3864d2fa630cSAmit Kucheria trip = <&cpu0_alert1>; 3865d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3866d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3867d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3868d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3869d2fa630cSAmit Kucheria }; 3870d2fa630cSAmit Kucheria }; 3871d2fa630cSAmit Kucheria }; 3872d2fa630cSAmit Kucheria 3873d2fa630cSAmit Kucheria cpu1-thermal { 3874d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3875d2fa630cSAmit Kucheria polling-delay = <1000>; 3876d2fa630cSAmit Kucheria 3877d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 2>; 3878d2fa630cSAmit Kucheria 3879d2fa630cSAmit Kucheria trips { 3880d2fa630cSAmit Kucheria cpu1_alert0: trip-point0 { 3881d2fa630cSAmit Kucheria temperature = <90000>; 3882d2fa630cSAmit Kucheria hysteresis = <2000>; 3883d2fa630cSAmit Kucheria type = "passive"; 3884d2fa630cSAmit Kucheria }; 3885d2fa630cSAmit Kucheria 3886d2fa630cSAmit Kucheria cpu1_alert1: trip-point1 { 3887d2fa630cSAmit Kucheria temperature = <95000>; 3888d2fa630cSAmit Kucheria hysteresis = <2000>; 3889d2fa630cSAmit Kucheria type = "passive"; 3890d2fa630cSAmit Kucheria }; 3891d2fa630cSAmit Kucheria 3892d2fa630cSAmit Kucheria cpu1_crit: cpu_crit { 3893d2fa630cSAmit Kucheria temperature = <110000>; 3894d2fa630cSAmit Kucheria hysteresis = <1000>; 3895d2fa630cSAmit Kucheria type = "critical"; 3896d2fa630cSAmit Kucheria }; 3897d2fa630cSAmit Kucheria }; 3898d2fa630cSAmit Kucheria 3899d2fa630cSAmit Kucheria cooling-maps { 3900d2fa630cSAmit Kucheria map0 { 3901d2fa630cSAmit Kucheria trip = <&cpu1_alert0>; 3902d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3903d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3904d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3905d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3906d2fa630cSAmit Kucheria }; 3907d2fa630cSAmit Kucheria map1 { 3908d2fa630cSAmit Kucheria trip = <&cpu1_alert1>; 3909d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3910d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3911d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3912d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3913d2fa630cSAmit Kucheria }; 3914d2fa630cSAmit Kucheria }; 3915d2fa630cSAmit Kucheria }; 3916d2fa630cSAmit Kucheria 3917d2fa630cSAmit Kucheria cpu2-thermal { 3918d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3919d2fa630cSAmit Kucheria polling-delay = <1000>; 3920d2fa630cSAmit Kucheria 3921d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 3>; 3922d2fa630cSAmit Kucheria 3923d2fa630cSAmit Kucheria trips { 3924d2fa630cSAmit Kucheria cpu2_alert0: trip-point0 { 3925d2fa630cSAmit Kucheria temperature = <90000>; 3926d2fa630cSAmit Kucheria hysteresis = <2000>; 3927d2fa630cSAmit Kucheria type = "passive"; 3928d2fa630cSAmit Kucheria }; 3929d2fa630cSAmit Kucheria 3930d2fa630cSAmit Kucheria cpu2_alert1: trip-point1 { 3931d2fa630cSAmit Kucheria temperature = <95000>; 3932d2fa630cSAmit Kucheria hysteresis = <2000>; 3933d2fa630cSAmit Kucheria type = "passive"; 3934d2fa630cSAmit Kucheria }; 3935d2fa630cSAmit Kucheria 3936d2fa630cSAmit Kucheria cpu2_crit: cpu_crit { 3937d2fa630cSAmit Kucheria temperature = <110000>; 3938d2fa630cSAmit Kucheria hysteresis = <1000>; 3939d2fa630cSAmit Kucheria type = "critical"; 3940d2fa630cSAmit Kucheria }; 3941d2fa630cSAmit Kucheria }; 3942d2fa630cSAmit Kucheria 3943d2fa630cSAmit Kucheria cooling-maps { 3944d2fa630cSAmit Kucheria map0 { 3945d2fa630cSAmit Kucheria trip = <&cpu2_alert0>; 3946d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3947d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3948d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3949d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3950d2fa630cSAmit Kucheria }; 3951d2fa630cSAmit Kucheria map1 { 3952d2fa630cSAmit Kucheria trip = <&cpu2_alert1>; 3953d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3954d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3955d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3956d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3957d2fa630cSAmit Kucheria }; 3958d2fa630cSAmit Kucheria }; 3959d2fa630cSAmit Kucheria }; 3960d2fa630cSAmit Kucheria 3961d2fa630cSAmit Kucheria cpu3-thermal { 3962d2fa630cSAmit Kucheria polling-delay-passive = <250>; 3963d2fa630cSAmit Kucheria polling-delay = <1000>; 3964d2fa630cSAmit Kucheria 3965d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 4>; 3966d2fa630cSAmit Kucheria 3967d2fa630cSAmit Kucheria trips { 3968d2fa630cSAmit Kucheria cpu3_alert0: trip-point0 { 3969d2fa630cSAmit Kucheria temperature = <90000>; 3970d2fa630cSAmit Kucheria hysteresis = <2000>; 3971d2fa630cSAmit Kucheria type = "passive"; 3972d2fa630cSAmit Kucheria }; 3973d2fa630cSAmit Kucheria 3974d2fa630cSAmit Kucheria cpu3_alert1: trip-point1 { 3975d2fa630cSAmit Kucheria temperature = <95000>; 3976d2fa630cSAmit Kucheria hysteresis = <2000>; 3977d2fa630cSAmit Kucheria type = "passive"; 3978d2fa630cSAmit Kucheria }; 3979d2fa630cSAmit Kucheria 3980d2fa630cSAmit Kucheria cpu3_crit: cpu_crit { 3981d2fa630cSAmit Kucheria temperature = <110000>; 3982d2fa630cSAmit Kucheria hysteresis = <1000>; 3983d2fa630cSAmit Kucheria type = "critical"; 3984d2fa630cSAmit Kucheria }; 3985d2fa630cSAmit Kucheria }; 3986d2fa630cSAmit Kucheria 3987d2fa630cSAmit Kucheria cooling-maps { 3988d2fa630cSAmit Kucheria map0 { 3989d2fa630cSAmit Kucheria trip = <&cpu3_alert0>; 3990d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3991d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3992d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3993d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3994d2fa630cSAmit Kucheria }; 3995d2fa630cSAmit Kucheria map1 { 3996d2fa630cSAmit Kucheria trip = <&cpu3_alert1>; 3997d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3998d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3999d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4000d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4001d2fa630cSAmit Kucheria }; 4002d2fa630cSAmit Kucheria }; 4003d2fa630cSAmit Kucheria }; 4004d2fa630cSAmit Kucheria 4005d2fa630cSAmit Kucheria cpu4-top-thermal { 4006d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4007d2fa630cSAmit Kucheria polling-delay = <1000>; 4008d2fa630cSAmit Kucheria 4009d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 7>; 4010d2fa630cSAmit Kucheria 4011d2fa630cSAmit Kucheria trips { 4012d2fa630cSAmit Kucheria cpu4_top_alert0: trip-point0 { 4013d2fa630cSAmit Kucheria temperature = <90000>; 4014d2fa630cSAmit Kucheria hysteresis = <2000>; 4015d2fa630cSAmit Kucheria type = "passive"; 4016d2fa630cSAmit Kucheria }; 4017d2fa630cSAmit Kucheria 4018d2fa630cSAmit Kucheria cpu4_top_alert1: trip-point1 { 4019d2fa630cSAmit Kucheria temperature = <95000>; 4020d2fa630cSAmit Kucheria hysteresis = <2000>; 4021d2fa630cSAmit Kucheria type = "passive"; 4022d2fa630cSAmit Kucheria }; 4023d2fa630cSAmit Kucheria 4024d2fa630cSAmit Kucheria cpu4_top_crit: cpu_crit { 4025d2fa630cSAmit Kucheria temperature = <110000>; 4026d2fa630cSAmit Kucheria hysteresis = <1000>; 4027d2fa630cSAmit Kucheria type = "critical"; 4028d2fa630cSAmit Kucheria }; 4029d2fa630cSAmit Kucheria }; 4030d2fa630cSAmit Kucheria 4031d2fa630cSAmit Kucheria cooling-maps { 4032d2fa630cSAmit Kucheria map0 { 4033d2fa630cSAmit Kucheria trip = <&cpu4_top_alert0>; 4034d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4035d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4036d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4037d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4038d2fa630cSAmit Kucheria }; 4039d2fa630cSAmit Kucheria map1 { 4040d2fa630cSAmit Kucheria trip = <&cpu4_top_alert1>; 4041d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4042d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4043d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4044d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4045d2fa630cSAmit Kucheria }; 4046d2fa630cSAmit Kucheria }; 4047d2fa630cSAmit Kucheria }; 4048d2fa630cSAmit Kucheria 4049d2fa630cSAmit Kucheria cpu5-top-thermal { 4050d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4051d2fa630cSAmit Kucheria polling-delay = <1000>; 4052d2fa630cSAmit Kucheria 4053d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 8>; 4054d2fa630cSAmit Kucheria 4055d2fa630cSAmit Kucheria trips { 4056d2fa630cSAmit Kucheria cpu5_top_alert0: trip-point0 { 4057d2fa630cSAmit Kucheria temperature = <90000>; 4058d2fa630cSAmit Kucheria hysteresis = <2000>; 4059d2fa630cSAmit Kucheria type = "passive"; 4060d2fa630cSAmit Kucheria }; 4061d2fa630cSAmit Kucheria 4062d2fa630cSAmit Kucheria cpu5_top_alert1: trip-point1 { 4063d2fa630cSAmit Kucheria temperature = <95000>; 4064d2fa630cSAmit Kucheria hysteresis = <2000>; 4065d2fa630cSAmit Kucheria type = "passive"; 4066d2fa630cSAmit Kucheria }; 4067d2fa630cSAmit Kucheria 4068d2fa630cSAmit Kucheria cpu5_top_crit: cpu_crit { 4069d2fa630cSAmit Kucheria temperature = <110000>; 4070d2fa630cSAmit Kucheria hysteresis = <1000>; 4071d2fa630cSAmit Kucheria type = "critical"; 4072d2fa630cSAmit Kucheria }; 4073d2fa630cSAmit Kucheria }; 4074d2fa630cSAmit Kucheria 4075d2fa630cSAmit Kucheria cooling-maps { 4076d2fa630cSAmit Kucheria map0 { 4077d2fa630cSAmit Kucheria trip = <&cpu5_top_alert0>; 4078d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4079d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4080d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4081d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4082d2fa630cSAmit Kucheria }; 4083d2fa630cSAmit Kucheria map1 { 4084d2fa630cSAmit Kucheria trip = <&cpu5_top_alert1>; 4085d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4086d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4087d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4088d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4089d2fa630cSAmit Kucheria }; 4090d2fa630cSAmit Kucheria }; 4091d2fa630cSAmit Kucheria }; 4092d2fa630cSAmit Kucheria 4093d2fa630cSAmit Kucheria cpu6-top-thermal { 4094d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4095d2fa630cSAmit Kucheria polling-delay = <1000>; 4096d2fa630cSAmit Kucheria 4097d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 9>; 4098d2fa630cSAmit Kucheria 4099d2fa630cSAmit Kucheria trips { 4100d2fa630cSAmit Kucheria cpu6_top_alert0: trip-point0 { 4101d2fa630cSAmit Kucheria temperature = <90000>; 4102d2fa630cSAmit Kucheria hysteresis = <2000>; 4103d2fa630cSAmit Kucheria type = "passive"; 4104d2fa630cSAmit Kucheria }; 4105d2fa630cSAmit Kucheria 4106d2fa630cSAmit Kucheria cpu6_top_alert1: trip-point1 { 4107d2fa630cSAmit Kucheria temperature = <95000>; 4108d2fa630cSAmit Kucheria hysteresis = <2000>; 4109d2fa630cSAmit Kucheria type = "passive"; 4110d2fa630cSAmit Kucheria }; 4111d2fa630cSAmit Kucheria 4112d2fa630cSAmit Kucheria cpu6_top_crit: cpu_crit { 4113d2fa630cSAmit Kucheria temperature = <110000>; 4114d2fa630cSAmit Kucheria hysteresis = <1000>; 4115d2fa630cSAmit Kucheria type = "critical"; 4116d2fa630cSAmit Kucheria }; 4117d2fa630cSAmit Kucheria }; 4118d2fa630cSAmit Kucheria 4119d2fa630cSAmit Kucheria cooling-maps { 4120d2fa630cSAmit Kucheria map0 { 4121d2fa630cSAmit Kucheria trip = <&cpu6_top_alert0>; 4122d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4123d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4124d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4125d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4126d2fa630cSAmit Kucheria }; 4127d2fa630cSAmit Kucheria map1 { 4128d2fa630cSAmit Kucheria trip = <&cpu6_top_alert1>; 4129d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4130d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4131d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4132d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4133d2fa630cSAmit Kucheria }; 4134d2fa630cSAmit Kucheria }; 4135d2fa630cSAmit Kucheria }; 4136d2fa630cSAmit Kucheria 4137d2fa630cSAmit Kucheria cpu7-top-thermal { 4138d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4139d2fa630cSAmit Kucheria polling-delay = <1000>; 4140d2fa630cSAmit Kucheria 4141d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 10>; 4142d2fa630cSAmit Kucheria 4143d2fa630cSAmit Kucheria trips { 4144d2fa630cSAmit Kucheria cpu7_top_alert0: trip-point0 { 4145d2fa630cSAmit Kucheria temperature = <90000>; 4146d2fa630cSAmit Kucheria hysteresis = <2000>; 4147d2fa630cSAmit Kucheria type = "passive"; 4148d2fa630cSAmit Kucheria }; 4149d2fa630cSAmit Kucheria 4150d2fa630cSAmit Kucheria cpu7_top_alert1: trip-point1 { 4151d2fa630cSAmit Kucheria temperature = <95000>; 4152d2fa630cSAmit Kucheria hysteresis = <2000>; 4153d2fa630cSAmit Kucheria type = "passive"; 4154d2fa630cSAmit Kucheria }; 4155d2fa630cSAmit Kucheria 4156d2fa630cSAmit Kucheria cpu7_top_crit: cpu_crit { 4157d2fa630cSAmit Kucheria temperature = <110000>; 4158d2fa630cSAmit Kucheria hysteresis = <1000>; 4159d2fa630cSAmit Kucheria type = "critical"; 4160d2fa630cSAmit Kucheria }; 4161d2fa630cSAmit Kucheria }; 4162d2fa630cSAmit Kucheria 4163d2fa630cSAmit Kucheria cooling-maps { 4164d2fa630cSAmit Kucheria map0 { 4165d2fa630cSAmit Kucheria trip = <&cpu7_top_alert0>; 4166d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4167d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4168d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4169d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4170d2fa630cSAmit Kucheria }; 4171d2fa630cSAmit Kucheria map1 { 4172d2fa630cSAmit Kucheria trip = <&cpu7_top_alert1>; 4173d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4174d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4175d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4176d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4177d2fa630cSAmit Kucheria }; 4178d2fa630cSAmit Kucheria }; 4179d2fa630cSAmit Kucheria }; 4180d2fa630cSAmit Kucheria 4181d2fa630cSAmit Kucheria cpu4-bottom-thermal { 4182d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4183d2fa630cSAmit Kucheria polling-delay = <1000>; 4184d2fa630cSAmit Kucheria 4185d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 11>; 4186d2fa630cSAmit Kucheria 4187d2fa630cSAmit Kucheria trips { 4188d2fa630cSAmit Kucheria cpu4_bottom_alert0: trip-point0 { 4189d2fa630cSAmit Kucheria temperature = <90000>; 4190d2fa630cSAmit Kucheria hysteresis = <2000>; 4191d2fa630cSAmit Kucheria type = "passive"; 4192d2fa630cSAmit Kucheria }; 4193d2fa630cSAmit Kucheria 4194d2fa630cSAmit Kucheria cpu4_bottom_alert1: trip-point1 { 4195d2fa630cSAmit Kucheria temperature = <95000>; 4196d2fa630cSAmit Kucheria hysteresis = <2000>; 4197d2fa630cSAmit Kucheria type = "passive"; 4198d2fa630cSAmit Kucheria }; 4199d2fa630cSAmit Kucheria 4200d2fa630cSAmit Kucheria cpu4_bottom_crit: cpu_crit { 4201d2fa630cSAmit Kucheria temperature = <110000>; 4202d2fa630cSAmit Kucheria hysteresis = <1000>; 4203d2fa630cSAmit Kucheria type = "critical"; 4204d2fa630cSAmit Kucheria }; 4205d2fa630cSAmit Kucheria }; 4206d2fa630cSAmit Kucheria 4207d2fa630cSAmit Kucheria cooling-maps { 4208d2fa630cSAmit Kucheria map0 { 4209d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert0>; 4210d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4211d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4212d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4213d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4214d2fa630cSAmit Kucheria }; 4215d2fa630cSAmit Kucheria map1 { 4216d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert1>; 4217d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4218d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4219d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4220d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4221d2fa630cSAmit Kucheria }; 4222d2fa630cSAmit Kucheria }; 4223d2fa630cSAmit Kucheria }; 4224d2fa630cSAmit Kucheria 4225d2fa630cSAmit Kucheria cpu5-bottom-thermal { 4226d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4227d2fa630cSAmit Kucheria polling-delay = <1000>; 4228d2fa630cSAmit Kucheria 4229d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 12>; 4230d2fa630cSAmit Kucheria 4231d2fa630cSAmit Kucheria trips { 4232d2fa630cSAmit Kucheria cpu5_bottom_alert0: trip-point0 { 4233d2fa630cSAmit Kucheria temperature = <90000>; 4234d2fa630cSAmit Kucheria hysteresis = <2000>; 4235d2fa630cSAmit Kucheria type = "passive"; 4236d2fa630cSAmit Kucheria }; 4237d2fa630cSAmit Kucheria 4238d2fa630cSAmit Kucheria cpu5_bottom_alert1: trip-point1 { 4239d2fa630cSAmit Kucheria temperature = <95000>; 4240d2fa630cSAmit Kucheria hysteresis = <2000>; 4241d2fa630cSAmit Kucheria type = "passive"; 4242d2fa630cSAmit Kucheria }; 4243d2fa630cSAmit Kucheria 4244d2fa630cSAmit Kucheria cpu5_bottom_crit: cpu_crit { 4245d2fa630cSAmit Kucheria temperature = <110000>; 4246d2fa630cSAmit Kucheria hysteresis = <1000>; 4247d2fa630cSAmit Kucheria type = "critical"; 4248d2fa630cSAmit Kucheria }; 4249d2fa630cSAmit Kucheria }; 4250d2fa630cSAmit Kucheria 4251d2fa630cSAmit Kucheria cooling-maps { 4252d2fa630cSAmit Kucheria map0 { 4253d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert0>; 4254d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4255d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4256d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4257d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4258d2fa630cSAmit Kucheria }; 4259d2fa630cSAmit Kucheria map1 { 4260d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert1>; 4261d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4262d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4263d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4264d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4265d2fa630cSAmit Kucheria }; 4266d2fa630cSAmit Kucheria }; 4267d2fa630cSAmit Kucheria }; 4268d2fa630cSAmit Kucheria 4269d2fa630cSAmit Kucheria cpu6-bottom-thermal { 4270d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4271d2fa630cSAmit Kucheria polling-delay = <1000>; 4272d2fa630cSAmit Kucheria 4273d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 13>; 4274d2fa630cSAmit Kucheria 4275d2fa630cSAmit Kucheria trips { 4276d2fa630cSAmit Kucheria cpu6_bottom_alert0: trip-point0 { 4277d2fa630cSAmit Kucheria temperature = <90000>; 4278d2fa630cSAmit Kucheria hysteresis = <2000>; 4279d2fa630cSAmit Kucheria type = "passive"; 4280d2fa630cSAmit Kucheria }; 4281d2fa630cSAmit Kucheria 4282d2fa630cSAmit Kucheria cpu6_bottom_alert1: trip-point1 { 4283d2fa630cSAmit Kucheria temperature = <95000>; 4284d2fa630cSAmit Kucheria hysteresis = <2000>; 4285d2fa630cSAmit Kucheria type = "passive"; 4286d2fa630cSAmit Kucheria }; 4287d2fa630cSAmit Kucheria 4288d2fa630cSAmit Kucheria cpu6_bottom_crit: cpu_crit { 4289d2fa630cSAmit Kucheria temperature = <110000>; 4290d2fa630cSAmit Kucheria hysteresis = <1000>; 4291d2fa630cSAmit Kucheria type = "critical"; 4292d2fa630cSAmit Kucheria }; 4293d2fa630cSAmit Kucheria }; 4294d2fa630cSAmit Kucheria 4295d2fa630cSAmit Kucheria cooling-maps { 4296d2fa630cSAmit Kucheria map0 { 4297d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert0>; 4298d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4299d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4300d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4301d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4302d2fa630cSAmit Kucheria }; 4303d2fa630cSAmit Kucheria map1 { 4304d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert1>; 4305d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4306d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4307d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4308d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4309d2fa630cSAmit Kucheria }; 4310d2fa630cSAmit Kucheria }; 4311d2fa630cSAmit Kucheria }; 4312d2fa630cSAmit Kucheria 4313d2fa630cSAmit Kucheria cpu7-bottom-thermal { 4314d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4315d2fa630cSAmit Kucheria polling-delay = <1000>; 4316d2fa630cSAmit Kucheria 4317d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 14>; 4318d2fa630cSAmit Kucheria 4319d2fa630cSAmit Kucheria trips { 4320d2fa630cSAmit Kucheria cpu7_bottom_alert0: trip-point0 { 4321d2fa630cSAmit Kucheria temperature = <90000>; 4322d2fa630cSAmit Kucheria hysteresis = <2000>; 4323d2fa630cSAmit Kucheria type = "passive"; 4324d2fa630cSAmit Kucheria }; 4325d2fa630cSAmit Kucheria 4326d2fa630cSAmit Kucheria cpu7_bottom_alert1: trip-point1 { 4327d2fa630cSAmit Kucheria temperature = <95000>; 4328d2fa630cSAmit Kucheria hysteresis = <2000>; 4329d2fa630cSAmit Kucheria type = "passive"; 4330d2fa630cSAmit Kucheria }; 4331d2fa630cSAmit Kucheria 4332d2fa630cSAmit Kucheria cpu7_bottom_crit: cpu_crit { 4333d2fa630cSAmit Kucheria temperature = <110000>; 4334d2fa630cSAmit Kucheria hysteresis = <1000>; 4335d2fa630cSAmit Kucheria type = "critical"; 4336d2fa630cSAmit Kucheria }; 4337d2fa630cSAmit Kucheria }; 4338d2fa630cSAmit Kucheria 4339d2fa630cSAmit Kucheria cooling-maps { 4340d2fa630cSAmit Kucheria map0 { 4341d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert0>; 4342d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4343d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4344d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4345d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4346d2fa630cSAmit Kucheria }; 4347d2fa630cSAmit Kucheria map1 { 4348d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert1>; 4349d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4350d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4351d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4352d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4353d2fa630cSAmit Kucheria }; 4354d2fa630cSAmit Kucheria }; 4355d2fa630cSAmit Kucheria }; 4356d2fa630cSAmit Kucheria 4357d2fa630cSAmit Kucheria aoss0-thermal { 4358d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4359d2fa630cSAmit Kucheria polling-delay = <1000>; 4360d2fa630cSAmit Kucheria 4361d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 0>; 4362d2fa630cSAmit Kucheria 4363d2fa630cSAmit Kucheria trips { 4364d2fa630cSAmit Kucheria aoss0_alert0: trip-point0 { 4365d2fa630cSAmit Kucheria temperature = <90000>; 4366d2fa630cSAmit Kucheria hysteresis = <2000>; 4367d2fa630cSAmit Kucheria type = "hot"; 4368d2fa630cSAmit Kucheria }; 4369d2fa630cSAmit Kucheria }; 4370d2fa630cSAmit Kucheria }; 4371d2fa630cSAmit Kucheria 4372d2fa630cSAmit Kucheria cluster0-thermal { 4373d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4374d2fa630cSAmit Kucheria polling-delay = <1000>; 4375d2fa630cSAmit Kucheria 4376d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 5>; 4377d2fa630cSAmit Kucheria 4378d2fa630cSAmit Kucheria trips { 4379d2fa630cSAmit Kucheria cluster0_alert0: trip-point0 { 4380d2fa630cSAmit Kucheria temperature = <90000>; 4381d2fa630cSAmit Kucheria hysteresis = <2000>; 4382d2fa630cSAmit Kucheria type = "hot"; 4383d2fa630cSAmit Kucheria }; 4384d2fa630cSAmit Kucheria cluster0_crit: cluster0_crit { 4385d2fa630cSAmit Kucheria temperature = <110000>; 4386d2fa630cSAmit Kucheria hysteresis = <2000>; 4387d2fa630cSAmit Kucheria type = "critical"; 4388d2fa630cSAmit Kucheria }; 4389d2fa630cSAmit Kucheria }; 4390d2fa630cSAmit Kucheria }; 4391d2fa630cSAmit Kucheria 4392d2fa630cSAmit Kucheria cluster1-thermal { 4393d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4394d2fa630cSAmit Kucheria polling-delay = <1000>; 4395d2fa630cSAmit Kucheria 4396d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 6>; 4397d2fa630cSAmit Kucheria 4398d2fa630cSAmit Kucheria trips { 4399d2fa630cSAmit Kucheria cluster1_alert0: trip-point0 { 4400d2fa630cSAmit Kucheria temperature = <90000>; 4401d2fa630cSAmit Kucheria hysteresis = <2000>; 4402d2fa630cSAmit Kucheria type = "hot"; 4403d2fa630cSAmit Kucheria }; 4404d2fa630cSAmit Kucheria cluster1_crit: cluster1_crit { 4405d2fa630cSAmit Kucheria temperature = <110000>; 4406d2fa630cSAmit Kucheria hysteresis = <2000>; 4407d2fa630cSAmit Kucheria type = "critical"; 4408d2fa630cSAmit Kucheria }; 4409d2fa630cSAmit Kucheria }; 4410d2fa630cSAmit Kucheria }; 4411d2fa630cSAmit Kucheria 44127be1c395SDavid Heidelberg gpu-top-thermal { 4413d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4414d2fa630cSAmit Kucheria polling-delay = <1000>; 4415d2fa630cSAmit Kucheria 4416d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 15>; 4417d2fa630cSAmit Kucheria 4418d2fa630cSAmit Kucheria trips { 4419d2fa630cSAmit Kucheria gpu1_alert0: trip-point0 { 4420d2fa630cSAmit Kucheria temperature = <90000>; 4421d2fa630cSAmit Kucheria hysteresis = <2000>; 4422d2fa630cSAmit Kucheria type = "hot"; 4423d2fa630cSAmit Kucheria }; 4424d2fa630cSAmit Kucheria }; 4425d2fa630cSAmit Kucheria }; 4426d2fa630cSAmit Kucheria 4427d2fa630cSAmit Kucheria aoss1-thermal { 4428d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4429d2fa630cSAmit Kucheria polling-delay = <1000>; 4430d2fa630cSAmit Kucheria 4431d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 0>; 4432d2fa630cSAmit Kucheria 4433d2fa630cSAmit Kucheria trips { 4434d2fa630cSAmit Kucheria aoss1_alert0: trip-point0 { 4435d2fa630cSAmit Kucheria temperature = <90000>; 4436d2fa630cSAmit Kucheria hysteresis = <2000>; 4437d2fa630cSAmit Kucheria type = "hot"; 4438d2fa630cSAmit Kucheria }; 4439d2fa630cSAmit Kucheria }; 4440d2fa630cSAmit Kucheria }; 4441d2fa630cSAmit Kucheria 4442d2fa630cSAmit Kucheria wlan-thermal { 4443d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4444d2fa630cSAmit Kucheria polling-delay = <1000>; 4445d2fa630cSAmit Kucheria 4446d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 1>; 4447d2fa630cSAmit Kucheria 4448d2fa630cSAmit Kucheria trips { 4449d2fa630cSAmit Kucheria wlan_alert0: trip-point0 { 4450d2fa630cSAmit Kucheria temperature = <90000>; 4451d2fa630cSAmit Kucheria hysteresis = <2000>; 4452d2fa630cSAmit Kucheria type = "hot"; 4453d2fa630cSAmit Kucheria }; 4454d2fa630cSAmit Kucheria }; 4455d2fa630cSAmit Kucheria }; 4456d2fa630cSAmit Kucheria 4457d2fa630cSAmit Kucheria video-thermal { 4458d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4459d2fa630cSAmit Kucheria polling-delay = <1000>; 4460d2fa630cSAmit Kucheria 4461d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 2>; 4462d2fa630cSAmit Kucheria 4463d2fa630cSAmit Kucheria trips { 4464d2fa630cSAmit Kucheria video_alert0: trip-point0 { 4465d2fa630cSAmit Kucheria temperature = <90000>; 4466d2fa630cSAmit Kucheria hysteresis = <2000>; 4467d2fa630cSAmit Kucheria type = "hot"; 4468d2fa630cSAmit Kucheria }; 4469d2fa630cSAmit Kucheria }; 4470d2fa630cSAmit Kucheria }; 4471d2fa630cSAmit Kucheria 4472d2fa630cSAmit Kucheria mem-thermal { 4473d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4474d2fa630cSAmit Kucheria polling-delay = <1000>; 4475d2fa630cSAmit Kucheria 4476d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 3>; 4477d2fa630cSAmit Kucheria 4478d2fa630cSAmit Kucheria trips { 4479d2fa630cSAmit Kucheria mem_alert0: trip-point0 { 4480d2fa630cSAmit Kucheria temperature = <90000>; 4481d2fa630cSAmit Kucheria hysteresis = <2000>; 4482d2fa630cSAmit Kucheria type = "hot"; 4483d2fa630cSAmit Kucheria }; 4484d2fa630cSAmit Kucheria }; 4485d2fa630cSAmit Kucheria }; 4486d2fa630cSAmit Kucheria 4487d2fa630cSAmit Kucheria q6-hvx-thermal { 4488d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4489d2fa630cSAmit Kucheria polling-delay = <1000>; 4490d2fa630cSAmit Kucheria 4491d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 4>; 4492d2fa630cSAmit Kucheria 4493d2fa630cSAmit Kucheria trips { 4494d2fa630cSAmit Kucheria q6_hvx_alert0: trip-point0 { 4495d2fa630cSAmit Kucheria temperature = <90000>; 4496d2fa630cSAmit Kucheria hysteresis = <2000>; 4497d2fa630cSAmit Kucheria type = "hot"; 4498d2fa630cSAmit Kucheria }; 4499d2fa630cSAmit Kucheria }; 4500d2fa630cSAmit Kucheria }; 4501d2fa630cSAmit Kucheria 4502d2fa630cSAmit Kucheria camera-thermal { 4503d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4504d2fa630cSAmit Kucheria polling-delay = <1000>; 4505d2fa630cSAmit Kucheria 4506d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 5>; 4507d2fa630cSAmit Kucheria 4508d2fa630cSAmit Kucheria trips { 4509d2fa630cSAmit Kucheria camera_alert0: trip-point0 { 4510d2fa630cSAmit Kucheria temperature = <90000>; 4511d2fa630cSAmit Kucheria hysteresis = <2000>; 4512d2fa630cSAmit Kucheria type = "hot"; 4513d2fa630cSAmit Kucheria }; 4514d2fa630cSAmit Kucheria }; 4515d2fa630cSAmit Kucheria }; 4516d2fa630cSAmit Kucheria 4517d2fa630cSAmit Kucheria compute-thermal { 4518d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4519d2fa630cSAmit Kucheria polling-delay = <1000>; 4520d2fa630cSAmit Kucheria 4521d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 6>; 4522d2fa630cSAmit Kucheria 4523d2fa630cSAmit Kucheria trips { 4524d2fa630cSAmit Kucheria compute_alert0: trip-point0 { 4525d2fa630cSAmit Kucheria temperature = <90000>; 4526d2fa630cSAmit Kucheria hysteresis = <2000>; 4527d2fa630cSAmit Kucheria type = "hot"; 4528d2fa630cSAmit Kucheria }; 4529d2fa630cSAmit Kucheria }; 4530d2fa630cSAmit Kucheria }; 4531d2fa630cSAmit Kucheria 4532d2fa630cSAmit Kucheria modem-thermal { 4533d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4534d2fa630cSAmit Kucheria polling-delay = <1000>; 4535d2fa630cSAmit Kucheria 4536d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 7>; 4537d2fa630cSAmit Kucheria 4538d2fa630cSAmit Kucheria trips { 4539d2fa630cSAmit Kucheria modem_alert0: trip-point0 { 4540d2fa630cSAmit Kucheria temperature = <90000>; 4541d2fa630cSAmit Kucheria hysteresis = <2000>; 4542d2fa630cSAmit Kucheria type = "hot"; 4543d2fa630cSAmit Kucheria }; 4544d2fa630cSAmit Kucheria }; 4545d2fa630cSAmit Kucheria }; 4546d2fa630cSAmit Kucheria 4547d2fa630cSAmit Kucheria npu-thermal { 4548d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4549d2fa630cSAmit Kucheria polling-delay = <1000>; 4550d2fa630cSAmit Kucheria 4551d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 8>; 4552d2fa630cSAmit Kucheria 4553d2fa630cSAmit Kucheria trips { 4554d2fa630cSAmit Kucheria npu_alert0: trip-point0 { 4555d2fa630cSAmit Kucheria temperature = <90000>; 4556d2fa630cSAmit Kucheria hysteresis = <2000>; 4557d2fa630cSAmit Kucheria type = "hot"; 4558d2fa630cSAmit Kucheria }; 4559d2fa630cSAmit Kucheria }; 4560d2fa630cSAmit Kucheria }; 4561d2fa630cSAmit Kucheria 4562d2fa630cSAmit Kucheria modem-vec-thermal { 4563d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4564d2fa630cSAmit Kucheria polling-delay = <1000>; 4565d2fa630cSAmit Kucheria 4566d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 9>; 4567d2fa630cSAmit Kucheria 4568d2fa630cSAmit Kucheria trips { 4569d2fa630cSAmit Kucheria modem_vec_alert0: trip-point0 { 4570d2fa630cSAmit Kucheria temperature = <90000>; 4571d2fa630cSAmit Kucheria hysteresis = <2000>; 4572d2fa630cSAmit Kucheria type = "hot"; 4573d2fa630cSAmit Kucheria }; 4574d2fa630cSAmit Kucheria }; 4575d2fa630cSAmit Kucheria }; 4576d2fa630cSAmit Kucheria 4577d2fa630cSAmit Kucheria modem-scl-thermal { 4578d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4579d2fa630cSAmit Kucheria polling-delay = <1000>; 4580d2fa630cSAmit Kucheria 4581d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 10>; 4582d2fa630cSAmit Kucheria 4583d2fa630cSAmit Kucheria trips { 4584d2fa630cSAmit Kucheria modem_scl_alert0: trip-point0 { 4585d2fa630cSAmit Kucheria temperature = <90000>; 4586d2fa630cSAmit Kucheria hysteresis = <2000>; 4587d2fa630cSAmit Kucheria type = "hot"; 4588d2fa630cSAmit Kucheria }; 4589d2fa630cSAmit Kucheria }; 4590d2fa630cSAmit Kucheria }; 4591d2fa630cSAmit Kucheria 45927be1c395SDavid Heidelberg gpu-bottom-thermal { 4593d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4594d2fa630cSAmit Kucheria polling-delay = <1000>; 4595d2fa630cSAmit Kucheria 4596d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 11>; 4597d2fa630cSAmit Kucheria 4598d2fa630cSAmit Kucheria trips { 4599d2fa630cSAmit Kucheria gpu2_alert0: trip-point0 { 4600d2fa630cSAmit Kucheria temperature = <90000>; 4601d2fa630cSAmit Kucheria hysteresis = <2000>; 4602d2fa630cSAmit Kucheria type = "hot"; 4603d2fa630cSAmit Kucheria }; 4604d2fa630cSAmit Kucheria }; 4605d2fa630cSAmit Kucheria }; 4606d2fa630cSAmit Kucheria }; 4607e13c6d14SVinod Koul}; 4608