1e13c6d14SVinod Koul// SPDX-License-Identifier: BSD-3-Clause 2e13c6d14SVinod Koul/* 3e13c6d14SVinod Koul * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4e13c6d14SVinod Koul * Copyright (c) 2019, Linaro Limited 5e13c6d14SVinod Koul */ 6e13c6d14SVinod Koul 705006290SFelipe Balbi#include <dt-bindings/dma/qcom-gpi.h> 8e13c6d14SVinod Koul#include <dt-bindings/interrupt-controller/arm-gic.h> 9017e7856SSibi Sankar#include <dt-bindings/power/qcom-rpmpd.h> 10e13c6d14SVinod Koul#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11e13c6d14SVinod Koul#include <dt-bindings/clock/qcom,rpmh.h> 12d6f55763SVinod Koul#include <dt-bindings/clock/qcom,gcc-sm8150.h> 13f1269916SJonathan Marek#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 14a6d435c1SSibi Sankar#include <dt-bindings/interconnect/qcom,osm-l3.h> 152b6187abSThara Gopinath#include <dt-bindings/interconnect/qcom,sm8150.h> 16d2fa630cSAmit Kucheria#include <dt-bindings/thermal/thermal.h> 17e13c6d14SVinod Koul 18e13c6d14SVinod Koul/ { 19e13c6d14SVinod Koul interrupt-parent = <&intc>; 20e13c6d14SVinod Koul 21e13c6d14SVinod Koul #address-cells = <2>; 22e13c6d14SVinod Koul #size-cells = <2>; 23e13c6d14SVinod Koul 24e13c6d14SVinod Koul chosen { }; 25e13c6d14SVinod Koul 26e13c6d14SVinod Koul clocks { 27e13c6d14SVinod Koul xo_board: xo-board { 28e13c6d14SVinod Koul compatible = "fixed-clock"; 29e13c6d14SVinod Koul #clock-cells = <0>; 30e13c6d14SVinod Koul clock-frequency = <38400000>; 31e13c6d14SVinod Koul clock-output-names = "xo_board"; 32e13c6d14SVinod Koul }; 33e13c6d14SVinod Koul 34e13c6d14SVinod Koul sleep_clk: sleep-clk { 35e13c6d14SVinod Koul compatible = "fixed-clock"; 36e13c6d14SVinod Koul #clock-cells = <0>; 37e13c6d14SVinod Koul clock-frequency = <32764>; 38e13c6d14SVinod Koul clock-output-names = "sleep_clk"; 39e13c6d14SVinod Koul }; 40e13c6d14SVinod Koul }; 41e13c6d14SVinod Koul 42e13c6d14SVinod Koul cpus { 43e13c6d14SVinod Koul #address-cells = <2>; 44e13c6d14SVinod Koul #size-cells = <0>; 45e13c6d14SVinod Koul 46e13c6d14SVinod Koul CPU0: cpu@0 { 47e13c6d14SVinod Koul device_type = "cpu"; 48e13c6d14SVinod Koul compatible = "qcom,kryo485"; 49e13c6d14SVinod Koul reg = <0x0 0x0>; 50e13c6d14SVinod Koul enable-method = "psci"; 515b2dae72SDanny Lin capacity-dmips-mhz = <488>; 525b2dae72SDanny Lin dynamic-power-coefficient = <232>; 53e13c6d14SVinod Koul next-level-cache = <&L2_0>; 54fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 552b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 562b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 572b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 58b2e3f897SDanny Lin power-domains = <&CPU_PD0>; 59b2e3f897SDanny Lin power-domain-names = "psci"; 60d2fa630cSAmit Kucheria #cooling-cells = <2>; 61e13c6d14SVinod Koul L2_0: l2-cache { 62e13c6d14SVinod Koul compatible = "cache"; 63e13c6d14SVinod Koul next-level-cache = <&L3_0>; 64e13c6d14SVinod Koul L3_0: l3-cache { 65e13c6d14SVinod Koul compatible = "cache"; 66e13c6d14SVinod Koul }; 67e13c6d14SVinod Koul }; 68e13c6d14SVinod Koul }; 69e13c6d14SVinod Koul 70e13c6d14SVinod Koul CPU1: cpu@100 { 71e13c6d14SVinod Koul device_type = "cpu"; 72e13c6d14SVinod Koul compatible = "qcom,kryo485"; 73e13c6d14SVinod Koul reg = <0x0 0x100>; 74e13c6d14SVinod Koul enable-method = "psci"; 755b2dae72SDanny Lin capacity-dmips-mhz = <488>; 765b2dae72SDanny Lin dynamic-power-coefficient = <232>; 77e13c6d14SVinod Koul next-level-cache = <&L2_100>; 78fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 792b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 802b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 812b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 82b2e3f897SDanny Lin power-domains = <&CPU_PD1>; 83b2e3f897SDanny Lin power-domain-names = "psci"; 84d2fa630cSAmit Kucheria #cooling-cells = <2>; 85e13c6d14SVinod Koul L2_100: l2-cache { 86e13c6d14SVinod Koul compatible = "cache"; 87e13c6d14SVinod Koul next-level-cache = <&L3_0>; 88e13c6d14SVinod Koul }; 89e13c6d14SVinod Koul 90e13c6d14SVinod Koul }; 91e13c6d14SVinod Koul 92e13c6d14SVinod Koul CPU2: cpu@200 { 93e13c6d14SVinod Koul device_type = "cpu"; 94e13c6d14SVinod Koul compatible = "qcom,kryo485"; 95e13c6d14SVinod Koul reg = <0x0 0x200>; 96e13c6d14SVinod Koul enable-method = "psci"; 975b2dae72SDanny Lin capacity-dmips-mhz = <488>; 985b2dae72SDanny Lin dynamic-power-coefficient = <232>; 99e13c6d14SVinod Koul next-level-cache = <&L2_200>; 100fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1012b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1022b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1032b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 104b2e3f897SDanny Lin power-domains = <&CPU_PD2>; 105b2e3f897SDanny Lin power-domain-names = "psci"; 106d2fa630cSAmit Kucheria #cooling-cells = <2>; 107e13c6d14SVinod Koul L2_200: l2-cache { 108e13c6d14SVinod Koul compatible = "cache"; 109e13c6d14SVinod Koul next-level-cache = <&L3_0>; 110e13c6d14SVinod Koul }; 111e13c6d14SVinod Koul }; 112e13c6d14SVinod Koul 113e13c6d14SVinod Koul CPU3: cpu@300 { 114e13c6d14SVinod Koul device_type = "cpu"; 115e13c6d14SVinod Koul compatible = "qcom,kryo485"; 116e13c6d14SVinod Koul reg = <0x0 0x300>; 117e13c6d14SVinod Koul enable-method = "psci"; 1185b2dae72SDanny Lin capacity-dmips-mhz = <488>; 1195b2dae72SDanny Lin dynamic-power-coefficient = <232>; 120e13c6d14SVinod Koul next-level-cache = <&L2_300>; 121fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1222b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1232b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1242b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 125b2e3f897SDanny Lin power-domains = <&CPU_PD3>; 126b2e3f897SDanny Lin power-domain-names = "psci"; 127d2fa630cSAmit Kucheria #cooling-cells = <2>; 128e13c6d14SVinod Koul L2_300: l2-cache { 129e13c6d14SVinod Koul compatible = "cache"; 130e13c6d14SVinod Koul next-level-cache = <&L3_0>; 131e13c6d14SVinod Koul }; 132e13c6d14SVinod Koul }; 133e13c6d14SVinod Koul 134e13c6d14SVinod Koul CPU4: cpu@400 { 135e13c6d14SVinod Koul device_type = "cpu"; 136e13c6d14SVinod Koul compatible = "qcom,kryo485"; 137e13c6d14SVinod Koul reg = <0x0 0x400>; 138e13c6d14SVinod Koul enable-method = "psci"; 1395b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1405b2dae72SDanny Lin dynamic-power-coefficient = <369>; 141e13c6d14SVinod Koul next-level-cache = <&L2_400>; 142fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1432b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1442b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1452b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 146b2e3f897SDanny Lin power-domains = <&CPU_PD4>; 147b2e3f897SDanny Lin power-domain-names = "psci"; 148d2fa630cSAmit Kucheria #cooling-cells = <2>; 149e13c6d14SVinod Koul L2_400: l2-cache { 150e13c6d14SVinod Koul compatible = "cache"; 151e13c6d14SVinod Koul next-level-cache = <&L3_0>; 152e13c6d14SVinod Koul }; 153e13c6d14SVinod Koul }; 154e13c6d14SVinod Koul 155e13c6d14SVinod Koul CPU5: cpu@500 { 156e13c6d14SVinod Koul device_type = "cpu"; 157e13c6d14SVinod Koul compatible = "qcom,kryo485"; 158e13c6d14SVinod Koul reg = <0x0 0x500>; 159e13c6d14SVinod Koul enable-method = "psci"; 1605b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1615b2dae72SDanny Lin dynamic-power-coefficient = <369>; 162e13c6d14SVinod Koul next-level-cache = <&L2_500>; 163fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1642b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1652b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1662b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 167b2e3f897SDanny Lin power-domains = <&CPU_PD5>; 168b2e3f897SDanny Lin power-domain-names = "psci"; 169d2fa630cSAmit Kucheria #cooling-cells = <2>; 170e13c6d14SVinod Koul L2_500: l2-cache { 171e13c6d14SVinod Koul compatible = "cache"; 172e13c6d14SVinod Koul next-level-cache = <&L3_0>; 173e13c6d14SVinod Koul }; 174e13c6d14SVinod Koul }; 175e13c6d14SVinod Koul 176e13c6d14SVinod Koul CPU6: cpu@600 { 177e13c6d14SVinod Koul device_type = "cpu"; 178e13c6d14SVinod Koul compatible = "qcom,kryo485"; 179e13c6d14SVinod Koul reg = <0x0 0x600>; 180e13c6d14SVinod Koul enable-method = "psci"; 1815b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1825b2dae72SDanny Lin dynamic-power-coefficient = <369>; 183e13c6d14SVinod Koul next-level-cache = <&L2_600>; 184fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1852b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1862b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1872b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 188b2e3f897SDanny Lin power-domains = <&CPU_PD6>; 189b2e3f897SDanny Lin power-domain-names = "psci"; 190d2fa630cSAmit Kucheria #cooling-cells = <2>; 191e13c6d14SVinod Koul L2_600: l2-cache { 192e13c6d14SVinod Koul compatible = "cache"; 193e13c6d14SVinod Koul next-level-cache = <&L3_0>; 194e13c6d14SVinod Koul }; 195e13c6d14SVinod Koul }; 196e13c6d14SVinod Koul 197e13c6d14SVinod Koul CPU7: cpu@700 { 198e13c6d14SVinod Koul device_type = "cpu"; 199e13c6d14SVinod Koul compatible = "qcom,kryo485"; 200e13c6d14SVinod Koul reg = <0x0 0x700>; 201e13c6d14SVinod Koul enable-method = "psci"; 2025b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 2035b2dae72SDanny Lin dynamic-power-coefficient = <421>; 204e13c6d14SVinod Koul next-level-cache = <&L2_700>; 205fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 2>; 2062b6187abSThara Gopinath operating-points-v2 = <&cpu7_opp_table>; 2072b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 2082b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 209b2e3f897SDanny Lin power-domains = <&CPU_PD7>; 210b2e3f897SDanny Lin power-domain-names = "psci"; 211d2fa630cSAmit Kucheria #cooling-cells = <2>; 212e13c6d14SVinod Koul L2_700: l2-cache { 213e13c6d14SVinod Koul compatible = "cache"; 214e13c6d14SVinod Koul next-level-cache = <&L3_0>; 215e13c6d14SVinod Koul }; 216e13c6d14SVinod Koul }; 217066d21bcSDanny Lin 218066d21bcSDanny Lin cpu-map { 219066d21bcSDanny Lin cluster0 { 220066d21bcSDanny Lin core0 { 221066d21bcSDanny Lin cpu = <&CPU0>; 222066d21bcSDanny Lin }; 223066d21bcSDanny Lin 224066d21bcSDanny Lin core1 { 225066d21bcSDanny Lin cpu = <&CPU1>; 226066d21bcSDanny Lin }; 227066d21bcSDanny Lin 228066d21bcSDanny Lin core2 { 229066d21bcSDanny Lin cpu = <&CPU2>; 230066d21bcSDanny Lin }; 231066d21bcSDanny Lin 232066d21bcSDanny Lin core3 { 233066d21bcSDanny Lin cpu = <&CPU3>; 234066d21bcSDanny Lin }; 235066d21bcSDanny Lin 236066d21bcSDanny Lin core4 { 237066d21bcSDanny Lin cpu = <&CPU4>; 238066d21bcSDanny Lin }; 239066d21bcSDanny Lin 240066d21bcSDanny Lin core5 { 241066d21bcSDanny Lin cpu = <&CPU5>; 242066d21bcSDanny Lin }; 243066d21bcSDanny Lin 244066d21bcSDanny Lin core6 { 245066d21bcSDanny Lin cpu = <&CPU6>; 246066d21bcSDanny Lin }; 247066d21bcSDanny Lin 248066d21bcSDanny Lin core7 { 249066d21bcSDanny Lin cpu = <&CPU7>; 250066d21bcSDanny Lin }; 251066d21bcSDanny Lin }; 252066d21bcSDanny Lin }; 25381188f58SDanny Lin 25481188f58SDanny Lin idle-states { 25581188f58SDanny Lin entry-method = "psci"; 25681188f58SDanny Lin 25781188f58SDanny Lin LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 25881188f58SDanny Lin compatible = "arm,idle-state"; 25981188f58SDanny Lin idle-state-name = "little-rail-power-collapse"; 26081188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 26181188f58SDanny Lin entry-latency-us = <355>; 26281188f58SDanny Lin exit-latency-us = <909>; 26381188f58SDanny Lin min-residency-us = <3934>; 26481188f58SDanny Lin local-timer-stop; 26581188f58SDanny Lin }; 26681188f58SDanny Lin 26781188f58SDanny Lin BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 26881188f58SDanny Lin compatible = "arm,idle-state"; 26981188f58SDanny Lin idle-state-name = "big-rail-power-collapse"; 27081188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 27181188f58SDanny Lin entry-latency-us = <241>; 27281188f58SDanny Lin exit-latency-us = <1461>; 27381188f58SDanny Lin min-residency-us = <4488>; 27481188f58SDanny Lin local-timer-stop; 27581188f58SDanny Lin }; 276b2e3f897SDanny Lin }; 27781188f58SDanny Lin 278b2e3f897SDanny Lin domain-idle-states { 27981188f58SDanny Lin CLUSTER_SLEEP_0: cluster-sleep-0 { 280b2e3f897SDanny Lin compatible = "domain-idle-state"; 28181188f58SDanny Lin idle-state-name = "cluster-power-collapse"; 282b2e3f897SDanny Lin arm,psci-suspend-param = <0x4100c244>; 28381188f58SDanny Lin entry-latency-us = <3263>; 28481188f58SDanny Lin exit-latency-us = <6562>; 28581188f58SDanny Lin min-residency-us = <9987>; 28681188f58SDanny Lin local-timer-stop; 28781188f58SDanny Lin }; 28881188f58SDanny Lin }; 289e13c6d14SVinod Koul }; 290e13c6d14SVinod Koul 2910e3e6546SKrzysztof Kozlowski cpu0_opp_table: opp-table-cpu0 { 2922b6187abSThara Gopinath compatible = "operating-points-v2"; 2932b6187abSThara Gopinath opp-shared; 2942b6187abSThara Gopinath 2952b6187abSThara Gopinath cpu0_opp1: opp-300000000 { 2962b6187abSThara Gopinath opp-hz = /bits/ 64 <300000000>; 2972b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 2982b6187abSThara Gopinath }; 2992b6187abSThara Gopinath 3002b6187abSThara Gopinath cpu0_opp2: opp-403200000 { 3012b6187abSThara Gopinath opp-hz = /bits/ 64 <403200000>; 3022b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 3032b6187abSThara Gopinath }; 3042b6187abSThara Gopinath 3052b6187abSThara Gopinath cpu0_opp3: opp-499200000 { 3062b6187abSThara Gopinath opp-hz = /bits/ 64 <499200000>; 3072b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3082b6187abSThara Gopinath }; 3092b6187abSThara Gopinath 3102b6187abSThara Gopinath cpu0_opp4: opp-576000000 { 3112b6187abSThara Gopinath opp-hz = /bits/ 64 <576000000>; 3122b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3132b6187abSThara Gopinath }; 3142b6187abSThara Gopinath 3152b6187abSThara Gopinath cpu0_opp5: opp-672000000 { 3162b6187abSThara Gopinath opp-hz = /bits/ 64 <672000000>; 3172b6187abSThara Gopinath opp-peak-kBps = <800000 15974400>; 3182b6187abSThara Gopinath }; 3192b6187abSThara Gopinath 3202b6187abSThara Gopinath cpu0_opp6: opp-768000000 { 321ce3b50cfSThara Gopinath opp-hz = /bits/ 64 <768000000>; 3222b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3232b6187abSThara Gopinath }; 3242b6187abSThara Gopinath 3252b6187abSThara Gopinath cpu0_opp7: opp-844800000 { 3262b6187abSThara Gopinath opp-hz = /bits/ 64 <844800000>; 3272b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3282b6187abSThara Gopinath }; 3292b6187abSThara Gopinath 3302b6187abSThara Gopinath cpu0_opp8: opp-940800000 { 3312b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 3322b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3332b6187abSThara Gopinath }; 3342b6187abSThara Gopinath 3352b6187abSThara Gopinath cpu0_opp9: opp-1036800000 { 3362b6187abSThara Gopinath opp-hz = /bits/ 64 <1036800000>; 3372b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3382b6187abSThara Gopinath }; 3392b6187abSThara Gopinath 3402b6187abSThara Gopinath cpu0_opp10: opp-1113600000 { 3412b6187abSThara Gopinath opp-hz = /bits/ 64 <1113600000>; 3422b6187abSThara Gopinath opp-peak-kBps = <2188000 25804800>; 3432b6187abSThara Gopinath }; 3442b6187abSThara Gopinath 3452b6187abSThara Gopinath cpu0_opp11: opp-1209600000 { 3462b6187abSThara Gopinath opp-hz = /bits/ 64 <1209600000>; 3472b6187abSThara Gopinath opp-peak-kBps = <2188000 31948800>; 3482b6187abSThara Gopinath }; 3492b6187abSThara Gopinath 3502b6187abSThara Gopinath cpu0_opp12: opp-1305600000 { 3512b6187abSThara Gopinath opp-hz = /bits/ 64 <1305600000>; 3522b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3532b6187abSThara Gopinath }; 3542b6187abSThara Gopinath 3552b6187abSThara Gopinath cpu0_opp13: opp-1382400000 { 3562b6187abSThara Gopinath opp-hz = /bits/ 64 <1382400000>; 3572b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3582b6187abSThara Gopinath }; 3592b6187abSThara Gopinath 3602b6187abSThara Gopinath cpu0_opp14: opp-1478400000 { 3612b6187abSThara Gopinath opp-hz = /bits/ 64 <1478400000>; 3622b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3632b6187abSThara Gopinath }; 3642b6187abSThara Gopinath 3652b6187abSThara Gopinath cpu0_opp15: opp-1555200000 { 3662b6187abSThara Gopinath opp-hz = /bits/ 64 <1555200000>; 3672b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3682b6187abSThara Gopinath }; 3692b6187abSThara Gopinath 3702b6187abSThara Gopinath cpu0_opp16: opp-1632000000 { 3712b6187abSThara Gopinath opp-hz = /bits/ 64 <1632000000>; 3722b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3732b6187abSThara Gopinath }; 3742b6187abSThara Gopinath 3752b6187abSThara Gopinath cpu0_opp17: opp-1708800000 { 3762b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 3772b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 3782b6187abSThara Gopinath }; 3792b6187abSThara Gopinath 3802b6187abSThara Gopinath cpu0_opp18: opp-1785600000 { 3812b6187abSThara Gopinath opp-hz = /bits/ 64 <1785600000>; 3822b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 3832b6187abSThara Gopinath }; 3842b6187abSThara Gopinath }; 3852b6187abSThara Gopinath 3860e3e6546SKrzysztof Kozlowski cpu4_opp_table: opp-table-cpu4 { 3872b6187abSThara Gopinath compatible = "operating-points-v2"; 3882b6187abSThara Gopinath opp-shared; 3892b6187abSThara Gopinath 3902b6187abSThara Gopinath cpu4_opp1: opp-710400000 { 3912b6187abSThara Gopinath opp-hz = /bits/ 64 <710400000>; 3922b6187abSThara Gopinath opp-peak-kBps = <1804000 15974400>; 3932b6187abSThara Gopinath }; 3942b6187abSThara Gopinath 3952b6187abSThara Gopinath cpu4_opp2: opp-825600000 { 3962b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 3972b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 3982b6187abSThara Gopinath }; 3992b6187abSThara Gopinath 4002b6187abSThara Gopinath cpu4_opp3: opp-940800000 { 4012b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 4022b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 4032b6187abSThara Gopinath }; 4042b6187abSThara Gopinath 4052b6187abSThara Gopinath cpu4_opp4: opp-1056000000 { 4062b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 4072b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 4082b6187abSThara Gopinath }; 4092b6187abSThara Gopinath 4102b6187abSThara Gopinath cpu4_opp5: opp-1171200000 { 4112b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 4122b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 4132b6187abSThara Gopinath }; 4142b6187abSThara Gopinath 4152b6187abSThara Gopinath cpu4_opp6: opp-1286400000 { 4162b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 4172b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4182b6187abSThara Gopinath }; 4192b6187abSThara Gopinath 4202b6187abSThara Gopinath cpu4_opp7: opp-1401600000 { 4212b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 4222b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4232b6187abSThara Gopinath }; 4242b6187abSThara Gopinath 4252b6187abSThara Gopinath cpu4_opp8: opp-1497600000 { 4262b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 4272b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4282b6187abSThara Gopinath }; 4292b6187abSThara Gopinath 4302b6187abSThara Gopinath cpu4_opp9: opp-1612800000 { 4312b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 4322b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4332b6187abSThara Gopinath }; 4342b6187abSThara Gopinath 4352b6187abSThara Gopinath cpu4_opp10: opp-1708800000 { 4362b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 4372b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 4382b6187abSThara Gopinath }; 4392b6187abSThara Gopinath 4402b6187abSThara Gopinath cpu4_opp11: opp-1804800000 { 4412b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 4422b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 4432b6187abSThara Gopinath }; 4442b6187abSThara Gopinath 4452b6187abSThara Gopinath cpu4_opp12: opp-1920000000 { 4462b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 4472b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 4482b6187abSThara Gopinath }; 4492b6187abSThara Gopinath 4502b6187abSThara Gopinath cpu4_opp13: opp-2016000000 { 4512b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 4522b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 4532b6187abSThara Gopinath }; 4542b6187abSThara Gopinath 4552b6187abSThara Gopinath cpu4_opp14: opp-2131200000 { 4562b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 4572b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 4582b6187abSThara Gopinath }; 4592b6187abSThara Gopinath 4602b6187abSThara Gopinath cpu4_opp15: opp-2227200000 { 4612b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 4622b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4632b6187abSThara Gopinath }; 4642b6187abSThara Gopinath 4652b6187abSThara Gopinath cpu4_opp16: opp-2323200000 { 4662b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 4672b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4682b6187abSThara Gopinath }; 4692b6187abSThara Gopinath 4702b6187abSThara Gopinath cpu4_opp17: opp-2419200000 { 4712b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 4722b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4732b6187abSThara Gopinath }; 4742b6187abSThara Gopinath }; 4752b6187abSThara Gopinath 4760e3e6546SKrzysztof Kozlowski cpu7_opp_table: opp-table-cpu7 { 4772b6187abSThara Gopinath compatible = "operating-points-v2"; 4782b6187abSThara Gopinath opp-shared; 4792b6187abSThara Gopinath 4802b6187abSThara Gopinath cpu7_opp1: opp-825600000 { 4812b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 4822b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 4832b6187abSThara Gopinath }; 4842b6187abSThara Gopinath 4852b6187abSThara Gopinath cpu7_opp2: opp-940800000 { 4862b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 4872b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 4882b6187abSThara Gopinath }; 4892b6187abSThara Gopinath 4902b6187abSThara Gopinath cpu7_opp3: opp-1056000000 { 4912b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 4922b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 4932b6187abSThara Gopinath }; 4942b6187abSThara Gopinath 4952b6187abSThara Gopinath cpu7_opp4: opp-1171200000 { 4962b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 4972b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 4982b6187abSThara Gopinath }; 4992b6187abSThara Gopinath 5002b6187abSThara Gopinath cpu7_opp5: opp-1286400000 { 5012b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 5022b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5032b6187abSThara Gopinath }; 5042b6187abSThara Gopinath 5052b6187abSThara Gopinath cpu7_opp6: opp-1401600000 { 5062b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 5072b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5082b6187abSThara Gopinath }; 5092b6187abSThara Gopinath 5102b6187abSThara Gopinath cpu7_opp7: opp-1497600000 { 5112b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 5122b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5132b6187abSThara Gopinath }; 5142b6187abSThara Gopinath 5152b6187abSThara Gopinath cpu7_opp8: opp-1612800000 { 5162b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 5172b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5182b6187abSThara Gopinath }; 5192b6187abSThara Gopinath 5202b6187abSThara Gopinath cpu7_opp9: opp-1708800000 { 5212b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 5222b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 5232b6187abSThara Gopinath }; 5242b6187abSThara Gopinath 5252b6187abSThara Gopinath cpu7_opp10: opp-1804800000 { 5262b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 5272b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 5282b6187abSThara Gopinath }; 5292b6187abSThara Gopinath 5302b6187abSThara Gopinath cpu7_opp11: opp-1920000000 { 5312b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 5322b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 5332b6187abSThara Gopinath }; 5342b6187abSThara Gopinath 5352b6187abSThara Gopinath cpu7_opp12: opp-2016000000 { 5362b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 5372b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 5382b6187abSThara Gopinath }; 5392b6187abSThara Gopinath 5402b6187abSThara Gopinath cpu7_opp13: opp-2131200000 { 5412b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 5422b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 5432b6187abSThara Gopinath }; 5442b6187abSThara Gopinath 5452b6187abSThara Gopinath cpu7_opp14: opp-2227200000 { 5462b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 5472b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5482b6187abSThara Gopinath }; 5492b6187abSThara Gopinath 5502b6187abSThara Gopinath cpu7_opp15: opp-2323200000 { 5512b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 5522b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5532b6187abSThara Gopinath }; 5542b6187abSThara Gopinath 5552b6187abSThara Gopinath cpu7_opp16: opp-2419200000 { 5562b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 5572b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5582b6187abSThara Gopinath }; 5592b6187abSThara Gopinath 5602b6187abSThara Gopinath cpu7_opp17: opp-2534400000 { 5612b6187abSThara Gopinath opp-hz = /bits/ 64 <2534400000>; 5622b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5632b6187abSThara Gopinath }; 5642b6187abSThara Gopinath 5652b6187abSThara Gopinath cpu7_opp18: opp-2649600000 { 5662b6187abSThara Gopinath opp-hz = /bits/ 64 <2649600000>; 5672b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5682b6187abSThara Gopinath }; 5692b6187abSThara Gopinath 5702b6187abSThara Gopinath cpu7_opp19: opp-2745600000 { 5712b6187abSThara Gopinath opp-hz = /bits/ 64 <2745600000>; 5722b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5732b6187abSThara Gopinath }; 5742b6187abSThara Gopinath 5752b6187abSThara Gopinath cpu7_opp20: opp-2841600000 { 5762b6187abSThara Gopinath opp-hz = /bits/ 64 <2841600000>; 5772b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5782b6187abSThara Gopinath }; 5792b6187abSThara Gopinath }; 5802b6187abSThara Gopinath 581e13c6d14SVinod Koul firmware { 582e13c6d14SVinod Koul scm: scm { 583e13c6d14SVinod Koul compatible = "qcom,scm-sm8150", "qcom,scm"; 584e13c6d14SVinod Koul #reset-cells = <1>; 585e13c6d14SVinod Koul }; 586e13c6d14SVinod Koul }; 587e13c6d14SVinod Koul 588e13c6d14SVinod Koul memory@80000000 { 589e13c6d14SVinod Koul device_type = "memory"; 590e13c6d14SVinod Koul /* We expect the bootloader to fill in the size */ 591e13c6d14SVinod Koul reg = <0x0 0x80000000 0x0 0x0>; 592e13c6d14SVinod Koul }; 593e13c6d14SVinod Koul 594d8cf9372SVinod Koul pmu { 595d8cf9372SVinod Koul compatible = "arm,armv8-pmuv3"; 596d8cf9372SVinod Koul interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 597d8cf9372SVinod Koul }; 598d8cf9372SVinod Koul 599e13c6d14SVinod Koul psci { 600e13c6d14SVinod Koul compatible = "arm,psci-1.0"; 601e13c6d14SVinod Koul method = "smc"; 602b2e3f897SDanny Lin 603b2e3f897SDanny Lin CPU_PD0: cpu0 { 604b2e3f897SDanny Lin #power-domain-cells = <0>; 605b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 606b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 607b2e3f897SDanny Lin }; 608b2e3f897SDanny Lin 609b2e3f897SDanny Lin CPU_PD1: cpu1 { 610b2e3f897SDanny Lin #power-domain-cells = <0>; 611b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 612b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 613b2e3f897SDanny Lin }; 614b2e3f897SDanny Lin 615b2e3f897SDanny Lin CPU_PD2: cpu2 { 616b2e3f897SDanny Lin #power-domain-cells = <0>; 617b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 618b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 619b2e3f897SDanny Lin }; 620b2e3f897SDanny Lin 621b2e3f897SDanny Lin CPU_PD3: cpu3 { 622b2e3f897SDanny Lin #power-domain-cells = <0>; 623b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 624b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 625b2e3f897SDanny Lin }; 626b2e3f897SDanny Lin 627b2e3f897SDanny Lin CPU_PD4: cpu4 { 628b2e3f897SDanny Lin #power-domain-cells = <0>; 629b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 630b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 631b2e3f897SDanny Lin }; 632b2e3f897SDanny Lin 633b2e3f897SDanny Lin CPU_PD5: cpu5 { 634b2e3f897SDanny Lin #power-domain-cells = <0>; 635b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 636b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 637b2e3f897SDanny Lin }; 638b2e3f897SDanny Lin 639b2e3f897SDanny Lin CPU_PD6: cpu6 { 640b2e3f897SDanny Lin #power-domain-cells = <0>; 641b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 642b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 643b2e3f897SDanny Lin }; 644b2e3f897SDanny Lin 645b2e3f897SDanny Lin CPU_PD7: cpu7 { 646b2e3f897SDanny Lin #power-domain-cells = <0>; 647b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 648b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 649b2e3f897SDanny Lin }; 650b2e3f897SDanny Lin 651b2e3f897SDanny Lin CLUSTER_PD: cpu-cluster0 { 652b2e3f897SDanny Lin #power-domain-cells = <0>; 653b2e3f897SDanny Lin domain-idle-states = <&CLUSTER_SLEEP_0>; 654b2e3f897SDanny Lin }; 655e13c6d14SVinod Koul }; 656e13c6d14SVinod Koul 657912c373aSVinod Koul reserved-memory { 658912c373aSVinod Koul #address-cells = <2>; 659912c373aSVinod Koul #size-cells = <2>; 660912c373aSVinod Koul ranges; 661912c373aSVinod Koul 662912c373aSVinod Koul hyp_mem: memory@85700000 { 663912c373aSVinod Koul reg = <0x0 0x85700000 0x0 0x600000>; 664912c373aSVinod Koul no-map; 665912c373aSVinod Koul }; 666912c373aSVinod Koul 667912c373aSVinod Koul xbl_mem: memory@85d00000 { 668912c373aSVinod Koul reg = <0x0 0x85d00000 0x0 0x140000>; 669912c373aSVinod Koul no-map; 670912c373aSVinod Koul }; 671912c373aSVinod Koul 672912c373aSVinod Koul aop_mem: memory@85f00000 { 673912c373aSVinod Koul reg = <0x0 0x85f00000 0x0 0x20000>; 674912c373aSVinod Koul no-map; 675912c373aSVinod Koul }; 676912c373aSVinod Koul 677912c373aSVinod Koul aop_cmd_db: memory@85f20000 { 678912c373aSVinod Koul compatible = "qcom,cmd-db"; 679912c373aSVinod Koul reg = <0x0 0x85f20000 0x0 0x20000>; 680912c373aSVinod Koul no-map; 681912c373aSVinod Koul }; 682912c373aSVinod Koul 683912c373aSVinod Koul smem_mem: memory@86000000 { 684912c373aSVinod Koul reg = <0x0 0x86000000 0x0 0x200000>; 685912c373aSVinod Koul no-map; 686912c373aSVinod Koul }; 687912c373aSVinod Koul 688912c373aSVinod Koul tz_mem: memory@86200000 { 689912c373aSVinod Koul reg = <0x0 0x86200000 0x0 0x3900000>; 690912c373aSVinod Koul no-map; 691912c373aSVinod Koul }; 692912c373aSVinod Koul 693912c373aSVinod Koul rmtfs_mem: memory@89b00000 { 694912c373aSVinod Koul compatible = "qcom,rmtfs-mem"; 695912c373aSVinod Koul reg = <0x0 0x89b00000 0x0 0x200000>; 696912c373aSVinod Koul no-map; 697912c373aSVinod Koul 698912c373aSVinod Koul qcom,client-id = <1>; 699912c373aSVinod Koul qcom,vmid = <15>; 700912c373aSVinod Koul }; 701912c373aSVinod Koul 702912c373aSVinod Koul camera_mem: memory@8b700000 { 703912c373aSVinod Koul reg = <0x0 0x8b700000 0x0 0x500000>; 704912c373aSVinod Koul no-map; 705912c373aSVinod Koul }; 706912c373aSVinod Koul 707912c373aSVinod Koul wlan_mem: memory@8bc00000 { 708912c373aSVinod Koul reg = <0x0 0x8bc00000 0x0 0x180000>; 709912c373aSVinod Koul no-map; 710912c373aSVinod Koul }; 711912c373aSVinod Koul 712912c373aSVinod Koul npu_mem: memory@8bd80000 { 713912c373aSVinod Koul reg = <0x0 0x8bd80000 0x0 0x80000>; 714912c373aSVinod Koul no-map; 715912c373aSVinod Koul }; 716912c373aSVinod Koul 717912c373aSVinod Koul adsp_mem: memory@8be00000 { 718912c373aSVinod Koul reg = <0x0 0x8be00000 0x0 0x1a00000>; 719912c373aSVinod Koul no-map; 720912c373aSVinod Koul }; 721912c373aSVinod Koul 722912c373aSVinod Koul mpss_mem: memory@8d800000 { 723912c373aSVinod Koul reg = <0x0 0x8d800000 0x0 0x9600000>; 724912c373aSVinod Koul no-map; 725912c373aSVinod Koul }; 726912c373aSVinod Koul 727912c373aSVinod Koul venus_mem: memory@96e00000 { 728912c373aSVinod Koul reg = <0x0 0x96e00000 0x0 0x500000>; 729912c373aSVinod Koul no-map; 730912c373aSVinod Koul }; 731912c373aSVinod Koul 732912c373aSVinod Koul slpi_mem: memory@97300000 { 733912c373aSVinod Koul reg = <0x0 0x97300000 0x0 0x1400000>; 734912c373aSVinod Koul no-map; 735912c373aSVinod Koul }; 736912c373aSVinod Koul 737912c373aSVinod Koul ipa_fw_mem: memory@98700000 { 738912c373aSVinod Koul reg = <0x0 0x98700000 0x0 0x10000>; 739912c373aSVinod Koul no-map; 740912c373aSVinod Koul }; 741912c373aSVinod Koul 742912c373aSVinod Koul ipa_gsi_mem: memory@98710000 { 743912c373aSVinod Koul reg = <0x0 0x98710000 0x0 0x5000>; 744912c373aSVinod Koul no-map; 745912c373aSVinod Koul }; 746912c373aSVinod Koul 747912c373aSVinod Koul gpu_mem: memory@98715000 { 748912c373aSVinod Koul reg = <0x0 0x98715000 0x0 0x2000>; 749912c373aSVinod Koul no-map; 750912c373aSVinod Koul }; 751912c373aSVinod Koul 752912c373aSVinod Koul spss_mem: memory@98800000 { 753912c373aSVinod Koul reg = <0x0 0x98800000 0x0 0x100000>; 754912c373aSVinod Koul no-map; 755912c373aSVinod Koul }; 756912c373aSVinod Koul 757912c373aSVinod Koul cdsp_mem: memory@98900000 { 758912c373aSVinod Koul reg = <0x0 0x98900000 0x0 0x1400000>; 759912c373aSVinod Koul no-map; 760912c373aSVinod Koul }; 761912c373aSVinod Koul 762912c373aSVinod Koul qseecom_mem: memory@9e400000 { 763912c373aSVinod Koul reg = <0x0 0x9e400000 0x0 0x1400000>; 764912c373aSVinod Koul no-map; 765912c373aSVinod Koul }; 766912c373aSVinod Koul }; 767912c373aSVinod Koul 768d8cf9372SVinod Koul smem { 769d8cf9372SVinod Koul compatible = "qcom,smem"; 770d8cf9372SVinod Koul memory-region = <&smem_mem>; 771d8cf9372SVinod Koul hwlocks = <&tcsr_mutex 3>; 772d8cf9372SVinod Koul }; 773d8cf9372SVinod Koul 77461025b81SSibi Sankar smp2p-cdsp { 77561025b81SSibi Sankar compatible = "qcom,smp2p"; 77661025b81SSibi Sankar qcom,smem = <94>, <432>; 77761025b81SSibi Sankar 77861025b81SSibi Sankar interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 77961025b81SSibi Sankar 78061025b81SSibi Sankar mboxes = <&apss_shared 6>; 78161025b81SSibi Sankar 78261025b81SSibi Sankar qcom,local-pid = <0>; 78361025b81SSibi Sankar qcom,remote-pid = <5>; 78461025b81SSibi Sankar 78561025b81SSibi Sankar cdsp_smp2p_out: master-kernel { 78661025b81SSibi Sankar qcom,entry-name = "master-kernel"; 78761025b81SSibi Sankar #qcom,smem-state-cells = <1>; 78861025b81SSibi Sankar }; 78961025b81SSibi Sankar 79061025b81SSibi Sankar cdsp_smp2p_in: slave-kernel { 79161025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 79261025b81SSibi Sankar 79361025b81SSibi Sankar interrupt-controller; 79461025b81SSibi Sankar #interrupt-cells = <2>; 79561025b81SSibi Sankar }; 79661025b81SSibi Sankar }; 79761025b81SSibi Sankar 79861025b81SSibi Sankar smp2p-lpass { 79961025b81SSibi Sankar compatible = "qcom,smp2p"; 80061025b81SSibi Sankar qcom,smem = <443>, <429>; 80161025b81SSibi Sankar 80261025b81SSibi Sankar interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 80361025b81SSibi Sankar 80461025b81SSibi Sankar mboxes = <&apss_shared 10>; 80561025b81SSibi Sankar 80661025b81SSibi Sankar qcom,local-pid = <0>; 80761025b81SSibi Sankar qcom,remote-pid = <2>; 80861025b81SSibi Sankar 80961025b81SSibi Sankar adsp_smp2p_out: master-kernel { 81061025b81SSibi Sankar qcom,entry-name = "master-kernel"; 81161025b81SSibi Sankar #qcom,smem-state-cells = <1>; 81261025b81SSibi Sankar }; 81361025b81SSibi Sankar 81461025b81SSibi Sankar adsp_smp2p_in: slave-kernel { 81561025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 81661025b81SSibi Sankar 81761025b81SSibi Sankar interrupt-controller; 81861025b81SSibi Sankar #interrupt-cells = <2>; 81961025b81SSibi Sankar }; 82061025b81SSibi Sankar }; 82161025b81SSibi Sankar 82261025b81SSibi Sankar smp2p-mpss { 82361025b81SSibi Sankar compatible = "qcom,smp2p"; 82461025b81SSibi Sankar qcom,smem = <435>, <428>; 82561025b81SSibi Sankar 82661025b81SSibi Sankar interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 82761025b81SSibi Sankar 82861025b81SSibi Sankar mboxes = <&apss_shared 14>; 82961025b81SSibi Sankar 83061025b81SSibi Sankar qcom,local-pid = <0>; 83161025b81SSibi Sankar qcom,remote-pid = <1>; 83261025b81SSibi Sankar 83361025b81SSibi Sankar modem_smp2p_out: master-kernel { 83461025b81SSibi Sankar qcom,entry-name = "master-kernel"; 83561025b81SSibi Sankar #qcom,smem-state-cells = <1>; 83661025b81SSibi Sankar }; 83761025b81SSibi Sankar 83861025b81SSibi Sankar modem_smp2p_in: slave-kernel { 83961025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 84061025b81SSibi Sankar 84161025b81SSibi Sankar interrupt-controller; 84261025b81SSibi Sankar #interrupt-cells = <2>; 84361025b81SSibi Sankar }; 84461025b81SSibi Sankar }; 84561025b81SSibi Sankar 84661025b81SSibi Sankar smp2p-slpi { 84761025b81SSibi Sankar compatible = "qcom,smp2p"; 84861025b81SSibi Sankar qcom,smem = <481>, <430>; 84961025b81SSibi Sankar 85061025b81SSibi Sankar interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 85161025b81SSibi Sankar 85261025b81SSibi Sankar mboxes = <&apss_shared 26>; 85361025b81SSibi Sankar 85461025b81SSibi Sankar qcom,local-pid = <0>; 85561025b81SSibi Sankar qcom,remote-pid = <3>; 85661025b81SSibi Sankar 85761025b81SSibi Sankar slpi_smp2p_out: master-kernel { 85861025b81SSibi Sankar qcom,entry-name = "master-kernel"; 85961025b81SSibi Sankar #qcom,smem-state-cells = <1>; 86061025b81SSibi Sankar }; 86161025b81SSibi Sankar 86261025b81SSibi Sankar slpi_smp2p_in: slave-kernel { 86361025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 86461025b81SSibi Sankar 86561025b81SSibi Sankar interrupt-controller; 86661025b81SSibi Sankar #interrupt-cells = <2>; 86761025b81SSibi Sankar }; 86861025b81SSibi Sankar }; 86961025b81SSibi Sankar 870e13c6d14SVinod Koul soc: soc@0 { 871e13c6d14SVinod Koul #address-cells = <2>; 872e13c6d14SVinod Koul #size-cells = <2>; 873e13c6d14SVinod Koul ranges = <0 0 0 0 0x10 0>; 874e13c6d14SVinod Koul dma-ranges = <0 0 0 0 0x10 0>; 875e13c6d14SVinod Koul compatible = "simple-bus"; 876e13c6d14SVinod Koul 877e13c6d14SVinod Koul gcc: clock-controller@100000 { 878e13c6d14SVinod Koul compatible = "qcom,gcc-sm8150"; 879e13c6d14SVinod Koul reg = <0x0 0x00100000 0x0 0x1f0000>; 880e13c6d14SVinod Koul #clock-cells = <1>; 881e13c6d14SVinod Koul #reset-cells = <1>; 882e13c6d14SVinod Koul #power-domain-cells = <1>; 883e13c6d14SVinod Koul clock-names = "bi_tcxo", 884e13c6d14SVinod Koul "sleep_clk"; 885e13c6d14SVinod Koul clocks = <&rpmhcc RPMH_CXO_CLK>, 886e13c6d14SVinod Koul <&sleep_clk>; 887e13c6d14SVinod Koul }; 888e13c6d14SVinod Koul 88905006290SFelipe Balbi gpi_dma0: dma-controller@800000 { 890e7e24786SRichard Acayan compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 89105006290SFelipe Balbi reg = <0 0x800000 0 0x60000>; 89205006290SFelipe Balbi interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 89305006290SFelipe Balbi <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 89405006290SFelipe Balbi <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 89505006290SFelipe Balbi <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 89605006290SFelipe Balbi <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 89705006290SFelipe Balbi <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 89805006290SFelipe Balbi <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 89905006290SFelipe Balbi <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 90005006290SFelipe Balbi <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 90105006290SFelipe Balbi <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 90205006290SFelipe Balbi <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 90305006290SFelipe Balbi <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 90405006290SFelipe Balbi <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 90505006290SFelipe Balbi dma-channels = <13>; 90605006290SFelipe Balbi dma-channel-mask = <0xfa>; 90705006290SFelipe Balbi iommus = <&apps_smmu 0x00d6 0x0>; 90805006290SFelipe Balbi #dma-cells = <3>; 90905006290SFelipe Balbi status = "disabled"; 91005006290SFelipe Balbi }; 91105006290SFelipe Balbi 91205f333b7SVinod Koul ethernet: ethernet@20000 { 91305f333b7SVinod Koul compatible = "qcom,sm8150-ethqos"; 91405f333b7SVinod Koul reg = <0x0 0x00020000 0x0 0x10000>, 91505f333b7SVinod Koul <0x0 0x00036000 0x0 0x100>; 91605f333b7SVinod Koul reg-names = "stmmaceth", "rgmii"; 91705f333b7SVinod Koul clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 91805f333b7SVinod Koul clocks = <&gcc GCC_EMAC_AXI_CLK>, 91905f333b7SVinod Koul <&gcc GCC_EMAC_SLV_AHB_CLK>, 92005f333b7SVinod Koul <&gcc GCC_EMAC_PTP_CLK>, 92105f333b7SVinod Koul <&gcc GCC_EMAC_RGMII_CLK>; 92205f333b7SVinod Koul interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 92305f333b7SVinod Koul <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 92405f333b7SVinod Koul interrupt-names = "macirq", "eth_lpi"; 92505f333b7SVinod Koul 92605f333b7SVinod Koul power-domains = <&gcc EMAC_GDSC>; 92705f333b7SVinod Koul resets = <&gcc GCC_EMAC_BCR>; 92805f333b7SVinod Koul 92905f333b7SVinod Koul iommus = <&apps_smmu 0x3C0 0x0>; 93005f333b7SVinod Koul 93105f333b7SVinod Koul snps,tso; 93205f333b7SVinod Koul rx-fifo-depth = <4096>; 93305f333b7SVinod Koul tx-fifo-depth = <4096>; 93405f333b7SVinod Koul 93505f333b7SVinod Koul status = "disabled"; 93605f333b7SVinod Koul }; 93705f333b7SVinod Koul 93805f333b7SVinod Koul 9399cf3ebd1SCaleb Connolly qupv3_id_0: geniqup@8c0000 { 9409cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 9419cf3ebd1SCaleb Connolly reg = <0x0 0x008c0000 0x0 0x6000>; 9429cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 9439cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 9449cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 9459cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0xc3 0x0>; 9469cf3ebd1SCaleb Connolly #address-cells = <2>; 9479cf3ebd1SCaleb Connolly #size-cells = <2>; 9489cf3ebd1SCaleb Connolly ranges; 9499cf3ebd1SCaleb Connolly status = "disabled"; 95081bee695SCaleb Connolly 95181bee695SCaleb Connolly i2c0: i2c@880000 { 95281bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 95381bee695SCaleb Connolly reg = <0 0x00880000 0 0x4000>; 95481bee695SCaleb Connolly clock-names = "se"; 95581bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 956abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 957abdd4b7aSFelipe Balbi <&gpi_dma0 1 0 QCOM_GPI_I2C>; 958abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 95981bee695SCaleb Connolly pinctrl-names = "default"; 96081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c0_default>; 96181bee695SCaleb Connolly interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 96281bee695SCaleb Connolly #address-cells = <1>; 96381bee695SCaleb Connolly #size-cells = <0>; 96481bee695SCaleb Connolly status = "disabled"; 96581bee695SCaleb Connolly }; 96681bee695SCaleb Connolly 967129e1c96SFelipe Balbi spi0: spi@880000 { 968129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 969129e1c96SFelipe Balbi reg = <0 0x880000 0 0x4000>; 970129e1c96SFelipe Balbi reg-names = "se"; 971129e1c96SFelipe Balbi clock-names = "se"; 972129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 973abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 974abdd4b7aSFelipe Balbi <&gpi_dma0 1 0 QCOM_GPI_SPI>; 975abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 976129e1c96SFelipe Balbi pinctrl-names = "default"; 977129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi0_default>; 978129e1c96SFelipe Balbi interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 979129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 980129e1c96SFelipe Balbi #address-cells = <1>; 981129e1c96SFelipe Balbi #size-cells = <0>; 982129e1c96SFelipe Balbi status = "disabled"; 983129e1c96SFelipe Balbi }; 984129e1c96SFelipe Balbi 98581bee695SCaleb Connolly i2c1: i2c@884000 { 98681bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 98781bee695SCaleb Connolly reg = <0 0x00884000 0 0x4000>; 98881bee695SCaleb Connolly clock-names = "se"; 98981bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 990abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 991abdd4b7aSFelipe Balbi <&gpi_dma0 1 1 QCOM_GPI_I2C>; 992abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 99381bee695SCaleb Connolly pinctrl-names = "default"; 99481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c1_default>; 99581bee695SCaleb Connolly interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 99681bee695SCaleb Connolly #address-cells = <1>; 99781bee695SCaleb Connolly #size-cells = <0>; 99881bee695SCaleb Connolly status = "disabled"; 99981bee695SCaleb Connolly }; 100081bee695SCaleb Connolly 1001129e1c96SFelipe Balbi spi1: spi@884000 { 1002129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1003129e1c96SFelipe Balbi reg = <0 0x884000 0 0x4000>; 1004129e1c96SFelipe Balbi reg-names = "se"; 1005129e1c96SFelipe Balbi clock-names = "se"; 1006129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1007abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1008abdd4b7aSFelipe Balbi <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1009abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1010129e1c96SFelipe Balbi pinctrl-names = "default"; 1011129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi1_default>; 1012129e1c96SFelipe Balbi interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1013129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1014129e1c96SFelipe Balbi #address-cells = <1>; 1015129e1c96SFelipe Balbi #size-cells = <0>; 1016129e1c96SFelipe Balbi status = "disabled"; 1017129e1c96SFelipe Balbi }; 1018129e1c96SFelipe Balbi 101981bee695SCaleb Connolly i2c2: i2c@888000 { 102081bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 102181bee695SCaleb Connolly reg = <0 0x00888000 0 0x4000>; 102281bee695SCaleb Connolly clock-names = "se"; 102381bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1024abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1025abdd4b7aSFelipe Balbi <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1026abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 102781bee695SCaleb Connolly pinctrl-names = "default"; 102881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c2_default>; 102981bee695SCaleb Connolly interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 103081bee695SCaleb Connolly #address-cells = <1>; 103181bee695SCaleb Connolly #size-cells = <0>; 103281bee695SCaleb Connolly status = "disabled"; 103381bee695SCaleb Connolly }; 103481bee695SCaleb Connolly 1035129e1c96SFelipe Balbi spi2: spi@888000 { 1036129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1037129e1c96SFelipe Balbi reg = <0 0x888000 0 0x4000>; 1038129e1c96SFelipe Balbi reg-names = "se"; 1039129e1c96SFelipe Balbi clock-names = "se"; 1040129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1041abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1042abdd4b7aSFelipe Balbi <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1043abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1044129e1c96SFelipe Balbi pinctrl-names = "default"; 1045129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi2_default>; 1046129e1c96SFelipe Balbi interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1047129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1048129e1c96SFelipe Balbi #address-cells = <1>; 1049129e1c96SFelipe Balbi #size-cells = <0>; 1050129e1c96SFelipe Balbi status = "disabled"; 1051129e1c96SFelipe Balbi }; 1052129e1c96SFelipe Balbi 105381bee695SCaleb Connolly i2c3: i2c@88c000 { 105481bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 105581bee695SCaleb Connolly reg = <0 0x0088c000 0 0x4000>; 105681bee695SCaleb Connolly clock-names = "se"; 105781bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1058abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1059abdd4b7aSFelipe Balbi <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1060abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 106181bee695SCaleb Connolly pinctrl-names = "default"; 106281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c3_default>; 106381bee695SCaleb Connolly interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 106481bee695SCaleb Connolly #address-cells = <1>; 106581bee695SCaleb Connolly #size-cells = <0>; 106681bee695SCaleb Connolly status = "disabled"; 106781bee695SCaleb Connolly }; 106881bee695SCaleb Connolly 1069129e1c96SFelipe Balbi spi3: spi@88c000 { 1070129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1071129e1c96SFelipe Balbi reg = <0 0x88c000 0 0x4000>; 1072129e1c96SFelipe Balbi reg-names = "se"; 1073129e1c96SFelipe Balbi clock-names = "se"; 1074129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1075abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1076abdd4b7aSFelipe Balbi <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1077abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1078129e1c96SFelipe Balbi pinctrl-names = "default"; 1079129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi3_default>; 1080129e1c96SFelipe Balbi interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1081129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1082129e1c96SFelipe Balbi #address-cells = <1>; 1083129e1c96SFelipe Balbi #size-cells = <0>; 1084129e1c96SFelipe Balbi status = "disabled"; 1085129e1c96SFelipe Balbi }; 1086129e1c96SFelipe Balbi 108781bee695SCaleb Connolly i2c4: i2c@890000 { 108881bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 108981bee695SCaleb Connolly reg = <0 0x00890000 0 0x4000>; 109081bee695SCaleb Connolly clock-names = "se"; 109181bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1092abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1093abdd4b7aSFelipe Balbi <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1094abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 109581bee695SCaleb Connolly pinctrl-names = "default"; 109681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c4_default>; 109781bee695SCaleb Connolly interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 109881bee695SCaleb Connolly #address-cells = <1>; 109981bee695SCaleb Connolly #size-cells = <0>; 110081bee695SCaleb Connolly status = "disabled"; 110181bee695SCaleb Connolly }; 110281bee695SCaleb Connolly 1103129e1c96SFelipe Balbi spi4: spi@890000 { 1104129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1105129e1c96SFelipe Balbi reg = <0 0x890000 0 0x4000>; 1106129e1c96SFelipe Balbi reg-names = "se"; 1107129e1c96SFelipe Balbi clock-names = "se"; 1108129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1109abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1110abdd4b7aSFelipe Balbi <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1111abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1112129e1c96SFelipe Balbi pinctrl-names = "default"; 1113129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi4_default>; 1114129e1c96SFelipe Balbi interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1115129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1116129e1c96SFelipe Balbi #address-cells = <1>; 1117129e1c96SFelipe Balbi #size-cells = <0>; 1118129e1c96SFelipe Balbi status = "disabled"; 1119129e1c96SFelipe Balbi }; 1120129e1c96SFelipe Balbi 112181bee695SCaleb Connolly i2c5: i2c@894000 { 112281bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 112381bee695SCaleb Connolly reg = <0 0x00894000 0 0x4000>; 112481bee695SCaleb Connolly clock-names = "se"; 112581bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1126abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1127abdd4b7aSFelipe Balbi <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1128abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 112981bee695SCaleb Connolly pinctrl-names = "default"; 113081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c5_default>; 113181bee695SCaleb Connolly interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 113281bee695SCaleb Connolly #address-cells = <1>; 113381bee695SCaleb Connolly #size-cells = <0>; 113481bee695SCaleb Connolly status = "disabled"; 113581bee695SCaleb Connolly }; 113681bee695SCaleb Connolly 1137129e1c96SFelipe Balbi spi5: spi@894000 { 1138129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1139129e1c96SFelipe Balbi reg = <0 0x894000 0 0x4000>; 1140129e1c96SFelipe Balbi reg-names = "se"; 1141129e1c96SFelipe Balbi clock-names = "se"; 1142129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1143abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1144abdd4b7aSFelipe Balbi <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1145abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1146129e1c96SFelipe Balbi pinctrl-names = "default"; 1147129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi5_default>; 1148129e1c96SFelipe Balbi interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1149129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1150129e1c96SFelipe Balbi #address-cells = <1>; 1151129e1c96SFelipe Balbi #size-cells = <0>; 1152129e1c96SFelipe Balbi status = "disabled"; 1153129e1c96SFelipe Balbi }; 1154129e1c96SFelipe Balbi 115581bee695SCaleb Connolly i2c6: i2c@898000 { 115681bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 115781bee695SCaleb Connolly reg = <0 0x00898000 0 0x4000>; 115881bee695SCaleb Connolly clock-names = "se"; 115981bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1160abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1161abdd4b7aSFelipe Balbi <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1162abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 116381bee695SCaleb Connolly pinctrl-names = "default"; 116481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c6_default>; 116581bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 116681bee695SCaleb Connolly #address-cells = <1>; 116781bee695SCaleb Connolly #size-cells = <0>; 116881bee695SCaleb Connolly status = "disabled"; 116981bee695SCaleb Connolly }; 117081bee695SCaleb Connolly 1171129e1c96SFelipe Balbi spi6: spi@898000 { 1172129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1173129e1c96SFelipe Balbi reg = <0 0x898000 0 0x4000>; 1174129e1c96SFelipe Balbi reg-names = "se"; 1175129e1c96SFelipe Balbi clock-names = "se"; 1176129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1177abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1178abdd4b7aSFelipe Balbi <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1179abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1180129e1c96SFelipe Balbi pinctrl-names = "default"; 1181129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi6_default>; 1182129e1c96SFelipe Balbi interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1183129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1184129e1c96SFelipe Balbi #address-cells = <1>; 1185129e1c96SFelipe Balbi #size-cells = <0>; 1186129e1c96SFelipe Balbi status = "disabled"; 1187129e1c96SFelipe Balbi }; 1188129e1c96SFelipe Balbi 118981bee695SCaleb Connolly i2c7: i2c@89c000 { 119081bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 119181bee695SCaleb Connolly reg = <0 0x0089c000 0 0x4000>; 119281bee695SCaleb Connolly clock-names = "se"; 119381bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1194abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1195abdd4b7aSFelipe Balbi <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1196abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 119781bee695SCaleb Connolly pinctrl-names = "default"; 119881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c7_default>; 119981bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 120081bee695SCaleb Connolly #address-cells = <1>; 120181bee695SCaleb Connolly #size-cells = <0>; 120281bee695SCaleb Connolly status = "disabled"; 120381bee695SCaleb Connolly }; 120481bee695SCaleb Connolly 1205129e1c96SFelipe Balbi spi7: spi@89c000 { 1206129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1207129e1c96SFelipe Balbi reg = <0 0x89c000 0 0x4000>; 1208129e1c96SFelipe Balbi reg-names = "se"; 1209129e1c96SFelipe Balbi clock-names = "se"; 1210129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1211abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1212abdd4b7aSFelipe Balbi <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1213abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1214129e1c96SFelipe Balbi pinctrl-names = "default"; 1215129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi7_default>; 1216129e1c96SFelipe Balbi interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1217129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1218129e1c96SFelipe Balbi #address-cells = <1>; 1219129e1c96SFelipe Balbi #size-cells = <0>; 1220129e1c96SFelipe Balbi status = "disabled"; 1221129e1c96SFelipe Balbi }; 12229cf3ebd1SCaleb Connolly }; 12239cf3ebd1SCaleb Connolly 122405006290SFelipe Balbi gpi_dma1: dma-controller@a00000 { 1225e7e24786SRichard Acayan compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 122605006290SFelipe Balbi reg = <0 0xa00000 0 0x60000>; 122705006290SFelipe Balbi interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 122805006290SFelipe Balbi <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 122905006290SFelipe Balbi <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 123005006290SFelipe Balbi <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 123105006290SFelipe Balbi <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 123205006290SFelipe Balbi <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 123305006290SFelipe Balbi <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 123405006290SFelipe Balbi <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 123505006290SFelipe Balbi <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 123605006290SFelipe Balbi <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 123705006290SFelipe Balbi <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 123805006290SFelipe Balbi <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 123905006290SFelipe Balbi <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 124005006290SFelipe Balbi dma-channels = <13>; 124105006290SFelipe Balbi dma-channel-mask = <0xfa>; 124205006290SFelipe Balbi iommus = <&apps_smmu 0x0616 0x0>; 124305006290SFelipe Balbi #dma-cells = <3>; 124405006290SFelipe Balbi status = "disabled"; 124505006290SFelipe Balbi }; 124605006290SFelipe Balbi 1247e13c6d14SVinod Koul qupv3_id_1: geniqup@ac0000 { 1248e13c6d14SVinod Koul compatible = "qcom,geni-se-qup"; 1249e13c6d14SVinod Koul reg = <0x0 0x00ac0000 0x0 0x6000>; 1250e13c6d14SVinod Koul clock-names = "m-ahb", "s-ahb"; 1251d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1252d6f55763SVinod Koul <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 12539cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x603 0x0>; 1254e13c6d14SVinod Koul #address-cells = <2>; 1255e13c6d14SVinod Koul #size-cells = <2>; 1256e13c6d14SVinod Koul ranges; 1257e13c6d14SVinod Koul status = "disabled"; 1258e13c6d14SVinod Koul 125981bee695SCaleb Connolly i2c8: i2c@a80000 { 126081bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 126181bee695SCaleb Connolly reg = <0 0x00a80000 0 0x4000>; 126281bee695SCaleb Connolly clock-names = "se"; 126381bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1264abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1265abdd4b7aSFelipe Balbi <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1266abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 126781bee695SCaleb Connolly pinctrl-names = "default"; 126881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c8_default>; 126981bee695SCaleb Connolly interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 127081bee695SCaleb Connolly #address-cells = <1>; 127181bee695SCaleb Connolly #size-cells = <0>; 127281bee695SCaleb Connolly status = "disabled"; 127381bee695SCaleb Connolly }; 127481bee695SCaleb Connolly 1275129e1c96SFelipe Balbi spi8: spi@a80000 { 1276129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1277129e1c96SFelipe Balbi reg = <0 0xa80000 0 0x4000>; 1278129e1c96SFelipe Balbi reg-names = "se"; 1279129e1c96SFelipe Balbi clock-names = "se"; 1280129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1281abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1282abdd4b7aSFelipe Balbi <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1283abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1284129e1c96SFelipe Balbi pinctrl-names = "default"; 1285129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi8_default>; 1286129e1c96SFelipe Balbi interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1287129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1288129e1c96SFelipe Balbi #address-cells = <1>; 1289129e1c96SFelipe Balbi #size-cells = <0>; 1290129e1c96SFelipe Balbi status = "disabled"; 1291129e1c96SFelipe Balbi }; 1292129e1c96SFelipe Balbi 129381bee695SCaleb Connolly i2c9: i2c@a84000 { 129481bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 129581bee695SCaleb Connolly reg = <0 0x00a84000 0 0x4000>; 129681bee695SCaleb Connolly clock-names = "se"; 129781bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1298abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1299abdd4b7aSFelipe Balbi <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1300abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 130181bee695SCaleb Connolly pinctrl-names = "default"; 130281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c9_default>; 130381bee695SCaleb Connolly interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 130481bee695SCaleb Connolly #address-cells = <1>; 130581bee695SCaleb Connolly #size-cells = <0>; 130681bee695SCaleb Connolly status = "disabled"; 130781bee695SCaleb Connolly }; 130881bee695SCaleb Connolly 1309129e1c96SFelipe Balbi spi9: spi@a84000 { 1310129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1311129e1c96SFelipe Balbi reg = <0 0xa84000 0 0x4000>; 1312129e1c96SFelipe Balbi reg-names = "se"; 1313129e1c96SFelipe Balbi clock-names = "se"; 1314129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1315abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1316abdd4b7aSFelipe Balbi <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1317abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1318129e1c96SFelipe Balbi pinctrl-names = "default"; 1319129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi9_default>; 1320129e1c96SFelipe Balbi interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1321129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1322129e1c96SFelipe Balbi #address-cells = <1>; 1323129e1c96SFelipe Balbi #size-cells = <0>; 1324129e1c96SFelipe Balbi status = "disabled"; 1325129e1c96SFelipe Balbi }; 1326129e1c96SFelipe Balbi 132781bee695SCaleb Connolly i2c10: i2c@a88000 { 132881bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 132981bee695SCaleb Connolly reg = <0 0x00a88000 0 0x4000>; 133081bee695SCaleb Connolly clock-names = "se"; 133181bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1332abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1333abdd4b7aSFelipe Balbi <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1334abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 133581bee695SCaleb Connolly pinctrl-names = "default"; 133681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c10_default>; 133781bee695SCaleb Connolly interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 133881bee695SCaleb Connolly #address-cells = <1>; 133981bee695SCaleb Connolly #size-cells = <0>; 134081bee695SCaleb Connolly status = "disabled"; 134181bee695SCaleb Connolly }; 134281bee695SCaleb Connolly 1343129e1c96SFelipe Balbi spi10: spi@a88000 { 1344129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1345129e1c96SFelipe Balbi reg = <0 0xa88000 0 0x4000>; 1346129e1c96SFelipe Balbi reg-names = "se"; 1347129e1c96SFelipe Balbi clock-names = "se"; 1348129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1349abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1350abdd4b7aSFelipe Balbi <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1351abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1352129e1c96SFelipe Balbi pinctrl-names = "default"; 1353129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi10_default>; 1354129e1c96SFelipe Balbi interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1355129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1356129e1c96SFelipe Balbi #address-cells = <1>; 1357129e1c96SFelipe Balbi #size-cells = <0>; 1358129e1c96SFelipe Balbi status = "disabled"; 1359129e1c96SFelipe Balbi }; 1360129e1c96SFelipe Balbi 136181bee695SCaleb Connolly i2c11: i2c@a8c000 { 136281bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 136381bee695SCaleb Connolly reg = <0 0x00a8c000 0 0x4000>; 136481bee695SCaleb Connolly clock-names = "se"; 136581bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1366abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1367abdd4b7aSFelipe Balbi <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1368abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 136981bee695SCaleb Connolly pinctrl-names = "default"; 137081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c11_default>; 137181bee695SCaleb Connolly interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 137281bee695SCaleb Connolly #address-cells = <1>; 137381bee695SCaleb Connolly #size-cells = <0>; 137481bee695SCaleb Connolly status = "disabled"; 137581bee695SCaleb Connolly }; 137681bee695SCaleb Connolly 1377129e1c96SFelipe Balbi spi11: spi@a8c000 { 1378129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1379129e1c96SFelipe Balbi reg = <0 0xa8c000 0 0x4000>; 1380129e1c96SFelipe Balbi reg-names = "se"; 1381129e1c96SFelipe Balbi clock-names = "se"; 1382129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1383abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1384abdd4b7aSFelipe Balbi <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1385abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1386129e1c96SFelipe Balbi pinctrl-names = "default"; 1387129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi11_default>; 1388129e1c96SFelipe Balbi interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1389129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1390129e1c96SFelipe Balbi #address-cells = <1>; 1391129e1c96SFelipe Balbi #size-cells = <0>; 1392129e1c96SFelipe Balbi status = "disabled"; 1393129e1c96SFelipe Balbi }; 1394129e1c96SFelipe Balbi 1395e13c6d14SVinod Koul uart2: serial@a90000 { 1396e13c6d14SVinod Koul compatible = "qcom,geni-debug-uart"; 1397e13c6d14SVinod Koul reg = <0x0 0x00a90000 0x0 0x4000>; 1398e13c6d14SVinod Koul clock-names = "se"; 1399d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1400e13c6d14SVinod Koul interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1401e13c6d14SVinod Koul status = "disabled"; 1402e13c6d14SVinod Koul }; 140381bee695SCaleb Connolly 140481bee695SCaleb Connolly i2c12: i2c@a90000 { 140581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 140681bee695SCaleb Connolly reg = <0 0x00a90000 0 0x4000>; 140781bee695SCaleb Connolly clock-names = "se"; 140881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1409abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1410abdd4b7aSFelipe Balbi <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1411abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 141281bee695SCaleb Connolly pinctrl-names = "default"; 141381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c12_default>; 141481bee695SCaleb Connolly interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 141581bee695SCaleb Connolly #address-cells = <1>; 141681bee695SCaleb Connolly #size-cells = <0>; 141781bee695SCaleb Connolly status = "disabled"; 141881bee695SCaleb Connolly }; 141981bee695SCaleb Connolly 1420129e1c96SFelipe Balbi spi12: spi@a90000 { 1421129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1422129e1c96SFelipe Balbi reg = <0 0xa90000 0 0x4000>; 1423129e1c96SFelipe Balbi reg-names = "se"; 1424129e1c96SFelipe Balbi clock-names = "se"; 1425129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1426abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1427abdd4b7aSFelipe Balbi <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1428abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1429129e1c96SFelipe Balbi pinctrl-names = "default"; 1430129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi12_default>; 1431129e1c96SFelipe Balbi interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1432129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1433129e1c96SFelipe Balbi #address-cells = <1>; 1434129e1c96SFelipe Balbi #size-cells = <0>; 1435129e1c96SFelipe Balbi status = "disabled"; 1436129e1c96SFelipe Balbi }; 1437129e1c96SFelipe Balbi 143881bee695SCaleb Connolly i2c16: i2c@94000 { 143981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 144081bee695SCaleb Connolly reg = <0 0x0094000 0 0x4000>; 144181bee695SCaleb Connolly clock-names = "se"; 144281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1443abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1444abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1445abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 144681bee695SCaleb Connolly pinctrl-names = "default"; 144781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c16_default>; 144881bee695SCaleb Connolly interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 144981bee695SCaleb Connolly #address-cells = <1>; 145081bee695SCaleb Connolly #size-cells = <0>; 145181bee695SCaleb Connolly status = "disabled"; 145281bee695SCaleb Connolly }; 1453129e1c96SFelipe Balbi 1454129e1c96SFelipe Balbi spi16: spi@a94000 { 1455129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1456129e1c96SFelipe Balbi reg = <0 0xa94000 0 0x4000>; 1457129e1c96SFelipe Balbi reg-names = "se"; 1458129e1c96SFelipe Balbi clock-names = "se"; 1459129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1460abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1461abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1462abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1463129e1c96SFelipe Balbi pinctrl-names = "default"; 1464129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi16_default>; 1465129e1c96SFelipe Balbi interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1466129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1467129e1c96SFelipe Balbi #address-cells = <1>; 1468129e1c96SFelipe Balbi #size-cells = <0>; 1469129e1c96SFelipe Balbi status = "disabled"; 1470129e1c96SFelipe Balbi }; 1471e13c6d14SVinod Koul }; 1472e13c6d14SVinod Koul 147305006290SFelipe Balbi gpi_dma2: dma-controller@c00000 { 1474e7e24786SRichard Acayan compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 147505006290SFelipe Balbi reg = <0 0xc00000 0 0x60000>; 147605006290SFelipe Balbi interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 147705006290SFelipe Balbi <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 147805006290SFelipe Balbi <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 147905006290SFelipe Balbi <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 148005006290SFelipe Balbi <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 148105006290SFelipe Balbi <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 148205006290SFelipe Balbi <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 148305006290SFelipe Balbi <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 148405006290SFelipe Balbi <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 148505006290SFelipe Balbi <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 148605006290SFelipe Balbi <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 148705006290SFelipe Balbi <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 148805006290SFelipe Balbi <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 148905006290SFelipe Balbi dma-channels = <13>; 149005006290SFelipe Balbi dma-channel-mask = <0xfa>; 149105006290SFelipe Balbi iommus = <&apps_smmu 0x07b6 0x0>; 149205006290SFelipe Balbi #dma-cells = <3>; 149305006290SFelipe Balbi status = "disabled"; 149405006290SFelipe Balbi }; 149505006290SFelipe Balbi 14969cf3ebd1SCaleb Connolly qupv3_id_2: geniqup@cc0000 { 14979cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 14989cf3ebd1SCaleb Connolly reg = <0x0 0x00cc0000 0x0 0x6000>; 14999cf3ebd1SCaleb Connolly 15009cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 15019cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 15029cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 15039cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x7a3 0x0>; 15049cf3ebd1SCaleb Connolly #address-cells = <2>; 15059cf3ebd1SCaleb Connolly #size-cells = <2>; 15069cf3ebd1SCaleb Connolly ranges; 15079cf3ebd1SCaleb Connolly status = "disabled"; 150881bee695SCaleb Connolly 150981bee695SCaleb Connolly i2c17: i2c@c80000 { 151081bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 151181bee695SCaleb Connolly reg = <0 0x00c80000 0 0x4000>; 151281bee695SCaleb Connolly clock-names = "se"; 151381bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1514abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1515abdd4b7aSFelipe Balbi <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1516abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 151781bee695SCaleb Connolly pinctrl-names = "default"; 151881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c17_default>; 151981bee695SCaleb Connolly interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 152081bee695SCaleb Connolly #address-cells = <1>; 152181bee695SCaleb Connolly #size-cells = <0>; 152281bee695SCaleb Connolly status = "disabled"; 152381bee695SCaleb Connolly }; 152481bee695SCaleb Connolly 1525129e1c96SFelipe Balbi spi17: spi@c80000 { 1526129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1527129e1c96SFelipe Balbi reg = <0 0xc80000 0 0x4000>; 1528129e1c96SFelipe Balbi reg-names = "se"; 1529129e1c96SFelipe Balbi clock-names = "se"; 1530129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1531abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1532abdd4b7aSFelipe Balbi <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1533abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1534129e1c96SFelipe Balbi pinctrl-names = "default"; 1535129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi17_default>; 1536129e1c96SFelipe Balbi interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1537129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1538129e1c96SFelipe Balbi #address-cells = <1>; 1539129e1c96SFelipe Balbi #size-cells = <0>; 1540129e1c96SFelipe Balbi status = "disabled"; 1541129e1c96SFelipe Balbi }; 1542129e1c96SFelipe Balbi 154381bee695SCaleb Connolly i2c18: i2c@c84000 { 154481bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 154581bee695SCaleb Connolly reg = <0 0x00c84000 0 0x4000>; 154681bee695SCaleb Connolly clock-names = "se"; 154781bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1548abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1549abdd4b7aSFelipe Balbi <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1550abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 155181bee695SCaleb Connolly pinctrl-names = "default"; 155281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c18_default>; 155381bee695SCaleb Connolly interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 155481bee695SCaleb Connolly #address-cells = <1>; 155581bee695SCaleb Connolly #size-cells = <0>; 155681bee695SCaleb Connolly status = "disabled"; 155781bee695SCaleb Connolly }; 155881bee695SCaleb Connolly 1559129e1c96SFelipe Balbi spi18: spi@c84000 { 1560129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1561129e1c96SFelipe Balbi reg = <0 0xc84000 0 0x4000>; 1562129e1c96SFelipe Balbi reg-names = "se"; 1563129e1c96SFelipe Balbi clock-names = "se"; 1564129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1565abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1566abdd4b7aSFelipe Balbi <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1567abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1568129e1c96SFelipe Balbi pinctrl-names = "default"; 1569129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi18_default>; 1570129e1c96SFelipe Balbi interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1571129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1572129e1c96SFelipe Balbi #address-cells = <1>; 1573129e1c96SFelipe Balbi #size-cells = <0>; 1574129e1c96SFelipe Balbi status = "disabled"; 1575129e1c96SFelipe Balbi }; 1576129e1c96SFelipe Balbi 157781bee695SCaleb Connolly i2c19: i2c@c88000 { 157881bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 157981bee695SCaleb Connolly reg = <0 0x00c88000 0 0x4000>; 158081bee695SCaleb Connolly clock-names = "se"; 158181bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1582abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1583abdd4b7aSFelipe Balbi <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1584abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 158581bee695SCaleb Connolly pinctrl-names = "default"; 158681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c19_default>; 158781bee695SCaleb Connolly interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 158881bee695SCaleb Connolly #address-cells = <1>; 158981bee695SCaleb Connolly #size-cells = <0>; 159081bee695SCaleb Connolly status = "disabled"; 159181bee695SCaleb Connolly }; 159281bee695SCaleb Connolly 1593129e1c96SFelipe Balbi spi19: spi@c88000 { 1594129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1595129e1c96SFelipe Balbi reg = <0 0xc88000 0 0x4000>; 1596129e1c96SFelipe Balbi reg-names = "se"; 1597129e1c96SFelipe Balbi clock-names = "se"; 1598129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1599abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1600abdd4b7aSFelipe Balbi <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1601abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1602129e1c96SFelipe Balbi pinctrl-names = "default"; 1603129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi19_default>; 1604129e1c96SFelipe Balbi interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1605129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1606129e1c96SFelipe Balbi #address-cells = <1>; 1607129e1c96SFelipe Balbi #size-cells = <0>; 1608129e1c96SFelipe Balbi status = "disabled"; 1609129e1c96SFelipe Balbi }; 1610129e1c96SFelipe Balbi 161181bee695SCaleb Connolly i2c13: i2c@c8c000 { 161281bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 161381bee695SCaleb Connolly reg = <0 0x00c8c000 0 0x4000>; 161481bee695SCaleb Connolly clock-names = "se"; 161581bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1616abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1617abdd4b7aSFelipe Balbi <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1618abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 161981bee695SCaleb Connolly pinctrl-names = "default"; 162081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c13_default>; 162181bee695SCaleb Connolly interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 162281bee695SCaleb Connolly #address-cells = <1>; 162381bee695SCaleb Connolly #size-cells = <0>; 162481bee695SCaleb Connolly status = "disabled"; 162581bee695SCaleb Connolly }; 162681bee695SCaleb Connolly 1627129e1c96SFelipe Balbi spi13: spi@c8c000 { 1628129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1629129e1c96SFelipe Balbi reg = <0 0xc8c000 0 0x4000>; 1630129e1c96SFelipe Balbi reg-names = "se"; 1631129e1c96SFelipe Balbi clock-names = "se"; 1632129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1633abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1634abdd4b7aSFelipe Balbi <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1635abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1636129e1c96SFelipe Balbi pinctrl-names = "default"; 1637129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi13_default>; 1638129e1c96SFelipe Balbi interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1639129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1640129e1c96SFelipe Balbi #address-cells = <1>; 1641129e1c96SFelipe Balbi #size-cells = <0>; 1642129e1c96SFelipe Balbi status = "disabled"; 1643129e1c96SFelipe Balbi }; 1644129e1c96SFelipe Balbi 164581bee695SCaleb Connolly i2c14: i2c@c90000 { 164681bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 164781bee695SCaleb Connolly reg = <0 0x00c90000 0 0x4000>; 164881bee695SCaleb Connolly clock-names = "se"; 164981bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1650abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1651abdd4b7aSFelipe Balbi <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1652abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 165381bee695SCaleb Connolly pinctrl-names = "default"; 165481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c14_default>; 165581bee695SCaleb Connolly interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 165681bee695SCaleb Connolly #address-cells = <1>; 165781bee695SCaleb Connolly #size-cells = <0>; 165881bee695SCaleb Connolly status = "disabled"; 165981bee695SCaleb Connolly }; 166081bee695SCaleb Connolly 1661129e1c96SFelipe Balbi spi14: spi@c90000 { 1662129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1663129e1c96SFelipe Balbi reg = <0 0xc90000 0 0x4000>; 1664129e1c96SFelipe Balbi reg-names = "se"; 1665129e1c96SFelipe Balbi clock-names = "se"; 1666129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1667abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1668abdd4b7aSFelipe Balbi <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1669abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1670129e1c96SFelipe Balbi pinctrl-names = "default"; 1671129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi14_default>; 1672129e1c96SFelipe Balbi interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1673129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1674129e1c96SFelipe Balbi #address-cells = <1>; 1675129e1c96SFelipe Balbi #size-cells = <0>; 1676129e1c96SFelipe Balbi status = "disabled"; 1677129e1c96SFelipe Balbi }; 1678129e1c96SFelipe Balbi 167981bee695SCaleb Connolly i2c15: i2c@c94000 { 168081bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 168181bee695SCaleb Connolly reg = <0 0x00c94000 0 0x4000>; 168281bee695SCaleb Connolly clock-names = "se"; 168381bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1684abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1685abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1686abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 168781bee695SCaleb Connolly pinctrl-names = "default"; 168881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c15_default>; 168981bee695SCaleb Connolly interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 169081bee695SCaleb Connolly #address-cells = <1>; 169181bee695SCaleb Connolly #size-cells = <0>; 169281bee695SCaleb Connolly status = "disabled"; 169381bee695SCaleb Connolly }; 1694129e1c96SFelipe Balbi 1695129e1c96SFelipe Balbi spi15: spi@c94000 { 1696129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1697129e1c96SFelipe Balbi reg = <0 0xc94000 0 0x4000>; 1698129e1c96SFelipe Balbi reg-names = "se"; 1699129e1c96SFelipe Balbi clock-names = "se"; 1700129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1701abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1702abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1703abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1704129e1c96SFelipe Balbi pinctrl-names = "default"; 1705129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi15_default>; 1706129e1c96SFelipe Balbi interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1707129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1708129e1c96SFelipe Balbi #address-cells = <1>; 1709129e1c96SFelipe Balbi #size-cells = <0>; 1710129e1c96SFelipe Balbi status = "disabled"; 1711129e1c96SFelipe Balbi }; 17129cf3ebd1SCaleb Connolly }; 17139cf3ebd1SCaleb Connolly 171471a2fc6eSJonathan Marek config_noc: interconnect@1500000 { 171571a2fc6eSJonathan Marek compatible = "qcom,sm8150-config-noc"; 171671a2fc6eSJonathan Marek reg = <0 0x01500000 0 0x7400>; 171771a2fc6eSJonathan Marek #interconnect-cells = <1>; 171871a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 171971a2fc6eSJonathan Marek }; 172071a2fc6eSJonathan Marek 172171a2fc6eSJonathan Marek system_noc: interconnect@1620000 { 172271a2fc6eSJonathan Marek compatible = "qcom,sm8150-system-noc"; 172371a2fc6eSJonathan Marek reg = <0 0x01620000 0 0x19400>; 172471a2fc6eSJonathan Marek #interconnect-cells = <1>; 172571a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 172671a2fc6eSJonathan Marek }; 172771a2fc6eSJonathan Marek 172871a2fc6eSJonathan Marek mc_virt: interconnect@163a000 { 172971a2fc6eSJonathan Marek compatible = "qcom,sm8150-mc-virt"; 173071a2fc6eSJonathan Marek reg = <0 0x0163a000 0 0x1000>; 173171a2fc6eSJonathan Marek #interconnect-cells = <1>; 173271a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 173371a2fc6eSJonathan Marek }; 173471a2fc6eSJonathan Marek 173571a2fc6eSJonathan Marek aggre1_noc: interconnect@16e0000 { 173671a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre1-noc"; 173771a2fc6eSJonathan Marek reg = <0 0x016e0000 0 0xd080>; 173871a2fc6eSJonathan Marek #interconnect-cells = <1>; 173971a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 174071a2fc6eSJonathan Marek }; 174171a2fc6eSJonathan Marek 174271a2fc6eSJonathan Marek aggre2_noc: interconnect@1700000 { 174371a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre2-noc"; 174471a2fc6eSJonathan Marek reg = <0 0x01700000 0 0x20000>; 174571a2fc6eSJonathan Marek #interconnect-cells = <1>; 174671a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 174771a2fc6eSJonathan Marek }; 174871a2fc6eSJonathan Marek 174971a2fc6eSJonathan Marek compute_noc: interconnect@1720000 { 175071a2fc6eSJonathan Marek compatible = "qcom,sm8150-compute-noc"; 175171a2fc6eSJonathan Marek reg = <0 0x01720000 0 0x7000>; 175271a2fc6eSJonathan Marek #interconnect-cells = <1>; 175371a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 175471a2fc6eSJonathan Marek }; 175571a2fc6eSJonathan Marek 175671a2fc6eSJonathan Marek mmss_noc: interconnect@1740000 { 175771a2fc6eSJonathan Marek compatible = "qcom,sm8150-mmss-noc"; 175871a2fc6eSJonathan Marek reg = <0 0x01740000 0 0x1c100>; 175971a2fc6eSJonathan Marek #interconnect-cells = <1>; 176071a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 176171a2fc6eSJonathan Marek }; 176271a2fc6eSJonathan Marek 1763bb1f7cf6SSouradeep Chowdhury system-cache-controller@9200000 { 1764bb1f7cf6SSouradeep Chowdhury compatible = "qcom,sm8150-llcc"; 1765bb1f7cf6SSouradeep Chowdhury reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 1766bb1f7cf6SSouradeep Chowdhury reg-names = "llcc_base", "llcc_broadcast_base"; 1767bb1f7cf6SSouradeep Chowdhury interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1768bb1f7cf6SSouradeep Chowdhury }; 1769bb1f7cf6SSouradeep Chowdhury 1770a1c86c68SBhupesh Sharma pcie0: pci@1c00000 { 1771a1c86c68SBhupesh Sharma compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1772a1c86c68SBhupesh Sharma reg = <0 0x01c00000 0 0x3000>, 1773a1c86c68SBhupesh Sharma <0 0x60000000 0 0xf1d>, 1774a1c86c68SBhupesh Sharma <0 0x60000f20 0 0xa8>, 1775a1c86c68SBhupesh Sharma <0 0x60001000 0 0x1000>, 1776a1c86c68SBhupesh Sharma <0 0x60100000 0 0x100000>; 1777a1c86c68SBhupesh Sharma reg-names = "parf", "dbi", "elbi", "atu", "config"; 1778a1c86c68SBhupesh Sharma device_type = "pci"; 1779a1c86c68SBhupesh Sharma linux,pci-domain = <0>; 1780a1c86c68SBhupesh Sharma bus-range = <0x00 0xff>; 1781a1c86c68SBhupesh Sharma num-lanes = <1>; 1782a1c86c68SBhupesh Sharma 1783a1c86c68SBhupesh Sharma #address-cells = <3>; 1784a1c86c68SBhupesh Sharma #size-cells = <2>; 1785a1c86c68SBhupesh Sharma 1786a1c86c68SBhupesh Sharma ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1787a1c86c68SBhupesh Sharma <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1788a1c86c68SBhupesh Sharma 1789a1c86c68SBhupesh Sharma interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1790a1c86c68SBhupesh Sharma interrupt-names = "msi"; 1791a1c86c68SBhupesh Sharma #interrupt-cells = <1>; 1792a1c86c68SBhupesh Sharma interrupt-map-mask = <0 0 0 0x7>; 1793a1c86c68SBhupesh Sharma interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1794a1c86c68SBhupesh Sharma <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1795a1c86c68SBhupesh Sharma <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1796a1c86c68SBhupesh Sharma <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1797a1c86c68SBhupesh Sharma 1798a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1799a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_AUX_CLK>, 1800a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1801a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1802a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1803a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1804a1c86c68SBhupesh Sharma <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1805a1c86c68SBhupesh Sharma clock-names = "pipe", 1806a1c86c68SBhupesh Sharma "aux", 1807a1c86c68SBhupesh Sharma "cfg", 1808a1c86c68SBhupesh Sharma "bus_master", 1809a1c86c68SBhupesh Sharma "bus_slave", 1810a1c86c68SBhupesh Sharma "slave_q2a", 1811a1c86c68SBhupesh Sharma "tbu"; 1812a1c86c68SBhupesh Sharma 1813a1c86c68SBhupesh Sharma iommus = <&apps_smmu 0x1d80 0x7f>; 1814a1c86c68SBhupesh Sharma iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1815a1c86c68SBhupesh Sharma <0x100 &apps_smmu 0x1d81 0x1>; 1816a1c86c68SBhupesh Sharma 1817a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_0_BCR>; 1818a1c86c68SBhupesh Sharma reset-names = "pci"; 1819a1c86c68SBhupesh Sharma 1820a1c86c68SBhupesh Sharma power-domains = <&gcc PCIE_0_GDSC>; 1821a1c86c68SBhupesh Sharma 1822a1c86c68SBhupesh Sharma phys = <&pcie0_lane>; 1823a1c86c68SBhupesh Sharma phy-names = "pciephy"; 1824a1c86c68SBhupesh Sharma 1825a1c86c68SBhupesh Sharma perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1826a1c86c68SBhupesh Sharma enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1827a1c86c68SBhupesh Sharma 1828a1c86c68SBhupesh Sharma pinctrl-names = "default"; 1829a1c86c68SBhupesh Sharma pinctrl-0 = <&pcie0_default_state>; 1830a1c86c68SBhupesh Sharma 1831a1c86c68SBhupesh Sharma status = "disabled"; 1832a1c86c68SBhupesh Sharma }; 1833a1c86c68SBhupesh Sharma 1834a1c86c68SBhupesh Sharma pcie0_phy: phy@1c06000 { 1835a1c86c68SBhupesh Sharma compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1836a1c86c68SBhupesh Sharma reg = <0 0x01c06000 0 0x1c0>; 1837a1c86c68SBhupesh Sharma #address-cells = <2>; 1838a1c86c68SBhupesh Sharma #size-cells = <2>; 1839a1c86c68SBhupesh Sharma ranges; 1840a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1841a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1842a1c86c68SBhupesh Sharma <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1843a1c86c68SBhupesh Sharma clock-names = "aux", "cfg_ahb", "refgen"; 1844a1c86c68SBhupesh Sharma 1845a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1846a1c86c68SBhupesh Sharma reset-names = "phy"; 1847a1c86c68SBhupesh Sharma 1848a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1849a1c86c68SBhupesh Sharma assigned-clock-rates = <100000000>; 1850a1c86c68SBhupesh Sharma 1851a1c86c68SBhupesh Sharma status = "disabled"; 1852a1c86c68SBhupesh Sharma 1853a1c86c68SBhupesh Sharma pcie0_lane: phy@1c06200 { 1854a1c86c68SBhupesh Sharma reg = <0 0x1c06200 0 0x170>, /* tx */ 1855a1c86c68SBhupesh Sharma <0 0x1c06400 0 0x200>, /* rx */ 1856a1c86c68SBhupesh Sharma <0 0x1c06800 0 0x1f0>, /* pcs */ 1857a1c86c68SBhupesh Sharma <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1858a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1859a1c86c68SBhupesh Sharma clock-names = "pipe0"; 1860a1c86c68SBhupesh Sharma 1861a1c86c68SBhupesh Sharma #phy-cells = <0>; 1862a1c86c68SBhupesh Sharma clock-output-names = "pcie_0_pipe_clk"; 1863a1c86c68SBhupesh Sharma }; 1864a1c86c68SBhupesh Sharma }; 1865a1c86c68SBhupesh Sharma 1866a1c86c68SBhupesh Sharma pcie1: pci@1c08000 { 1867a1c86c68SBhupesh Sharma compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1868a1c86c68SBhupesh Sharma reg = <0 0x01c08000 0 0x3000>, 1869a1c86c68SBhupesh Sharma <0 0x40000000 0 0xf1d>, 1870a1c86c68SBhupesh Sharma <0 0x40000f20 0 0xa8>, 1871a1c86c68SBhupesh Sharma <0 0x40001000 0 0x1000>, 1872a1c86c68SBhupesh Sharma <0 0x40100000 0 0x100000>; 1873a1c86c68SBhupesh Sharma reg-names = "parf", "dbi", "elbi", "atu", "config"; 1874a1c86c68SBhupesh Sharma device_type = "pci"; 1875a1c86c68SBhupesh Sharma linux,pci-domain = <1>; 1876a1c86c68SBhupesh Sharma bus-range = <0x00 0xff>; 1877a1c86c68SBhupesh Sharma num-lanes = <2>; 1878a1c86c68SBhupesh Sharma 1879a1c86c68SBhupesh Sharma #address-cells = <3>; 1880a1c86c68SBhupesh Sharma #size-cells = <2>; 1881a1c86c68SBhupesh Sharma 1882a1c86c68SBhupesh Sharma ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1883a1c86c68SBhupesh Sharma <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1884a1c86c68SBhupesh Sharma 1885a1c86c68SBhupesh Sharma interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1886a1c86c68SBhupesh Sharma interrupt-names = "msi"; 1887a1c86c68SBhupesh Sharma #interrupt-cells = <1>; 1888a1c86c68SBhupesh Sharma interrupt-map-mask = <0 0 0 0x7>; 1889a1c86c68SBhupesh Sharma interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1890a1c86c68SBhupesh Sharma <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1891a1c86c68SBhupesh Sharma <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1892a1c86c68SBhupesh Sharma <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1893a1c86c68SBhupesh Sharma 1894a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1895a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_AUX_CLK>, 1896a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1897a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1898a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1899a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1900a1c86c68SBhupesh Sharma <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1901a1c86c68SBhupesh Sharma clock-names = "pipe", 1902a1c86c68SBhupesh Sharma "aux", 1903a1c86c68SBhupesh Sharma "cfg", 1904a1c86c68SBhupesh Sharma "bus_master", 1905a1c86c68SBhupesh Sharma "bus_slave", 1906a1c86c68SBhupesh Sharma "slave_q2a", 1907a1c86c68SBhupesh Sharma "tbu"; 1908a1c86c68SBhupesh Sharma 1909a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1910a1c86c68SBhupesh Sharma assigned-clock-rates = <19200000>; 1911a1c86c68SBhupesh Sharma 1912a1c86c68SBhupesh Sharma iommus = <&apps_smmu 0x1e00 0x7f>; 1913a1c86c68SBhupesh Sharma iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1914a1c86c68SBhupesh Sharma <0x100 &apps_smmu 0x1e01 0x1>; 1915a1c86c68SBhupesh Sharma 1916a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_1_BCR>; 1917a1c86c68SBhupesh Sharma reset-names = "pci"; 1918a1c86c68SBhupesh Sharma 1919a1c86c68SBhupesh Sharma power-domains = <&gcc PCIE_1_GDSC>; 1920a1c86c68SBhupesh Sharma 1921a1c86c68SBhupesh Sharma phys = <&pcie1_lane>; 1922a1c86c68SBhupesh Sharma phy-names = "pciephy"; 1923a1c86c68SBhupesh Sharma 1924a1c86c68SBhupesh Sharma perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; 1925a1c86c68SBhupesh Sharma enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 1926a1c86c68SBhupesh Sharma 1927a1c86c68SBhupesh Sharma pinctrl-names = "default"; 1928a1c86c68SBhupesh Sharma pinctrl-0 = <&pcie1_default_state>; 1929a1c86c68SBhupesh Sharma 1930a1c86c68SBhupesh Sharma status = "disabled"; 1931a1c86c68SBhupesh Sharma }; 1932a1c86c68SBhupesh Sharma 1933a1c86c68SBhupesh Sharma pcie1_phy: phy@1c0e000 { 1934a1c86c68SBhupesh Sharma compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 1935a1c86c68SBhupesh Sharma reg = <0 0x01c0e000 0 0x1c0>; 1936a1c86c68SBhupesh Sharma #address-cells = <2>; 1937a1c86c68SBhupesh Sharma #size-cells = <2>; 1938a1c86c68SBhupesh Sharma ranges; 1939a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1940a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1941a1c86c68SBhupesh Sharma <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1942a1c86c68SBhupesh Sharma clock-names = "aux", "cfg_ahb", "refgen"; 1943a1c86c68SBhupesh Sharma 1944a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1945a1c86c68SBhupesh Sharma reset-names = "phy"; 1946a1c86c68SBhupesh Sharma 1947a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1948a1c86c68SBhupesh Sharma assigned-clock-rates = <100000000>; 1949a1c86c68SBhupesh Sharma 1950a1c86c68SBhupesh Sharma status = "disabled"; 1951a1c86c68SBhupesh Sharma 1952a1c86c68SBhupesh Sharma pcie1_lane: phy@1c0e200 { 1953a1c86c68SBhupesh Sharma reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1954a1c86c68SBhupesh Sharma <0 0x1c0e400 0 0x200>, /* rx0 */ 1955a1c86c68SBhupesh Sharma <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1956a1c86c68SBhupesh Sharma <0 0x1c0e600 0 0x170>, /* tx1 */ 1957a1c86c68SBhupesh Sharma <0 0x1c0e800 0 0x200>, /* rx1 */ 1958a1c86c68SBhupesh Sharma <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1959a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1960a1c86c68SBhupesh Sharma clock-names = "pipe0"; 1961a1c86c68SBhupesh Sharma 1962a1c86c68SBhupesh Sharma #phy-cells = <0>; 1963a1c86c68SBhupesh Sharma clock-output-names = "pcie_1_pipe_clk"; 1964a1c86c68SBhupesh Sharma }; 1965a1c86c68SBhupesh Sharma }; 1966a1c86c68SBhupesh Sharma 19673834a2e9SVinod Koul ufs_mem_hc: ufshc@1d84000 { 19683834a2e9SVinod Koul compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 19693834a2e9SVinod Koul "jedec,ufs-2.0"; 197098aee1e3SBhupesh Sharma reg = <0 0x01d84000 0 0x2500>, 197198aee1e3SBhupesh Sharma <0 0x01d90000 0 0x8000>; 197298aee1e3SBhupesh Sharma reg-names = "std", "ice"; 19733834a2e9SVinod Koul interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 19743834a2e9SVinod Koul phys = <&ufs_mem_phy_lanes>; 19753834a2e9SVinod Koul phy-names = "ufsphy"; 19763834a2e9SVinod Koul lanes-per-direction = <2>; 19773834a2e9SVinod Koul #reset-cells = <1>; 19783834a2e9SVinod Koul resets = <&gcc GCC_UFS_PHY_BCR>; 19793834a2e9SVinod Koul reset-names = "rst"; 19803834a2e9SVinod Koul 198148156232SJonathan Marek iommus = <&apps_smmu 0x300 0>; 198248156232SJonathan Marek 19833834a2e9SVinod Koul clock-names = 19843834a2e9SVinod Koul "core_clk", 19853834a2e9SVinod Koul "bus_aggr_clk", 19863834a2e9SVinod Koul "iface_clk", 19873834a2e9SVinod Koul "core_clk_unipro", 19883834a2e9SVinod Koul "ref_clk", 19893834a2e9SVinod Koul "tx_lane0_sync_clk", 19903834a2e9SVinod Koul "rx_lane0_sync_clk", 199198aee1e3SBhupesh Sharma "rx_lane1_sync_clk", 199298aee1e3SBhupesh Sharma "ice_core_clk"; 19933834a2e9SVinod Koul clocks = 19943834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AXI_CLK>, 19953834a2e9SVinod Koul <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 19963834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AHB_CLK>, 19973834a2e9SVinod Koul <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 19983834a2e9SVinod Koul <&rpmhcc RPMH_CXO_CLK>, 19993834a2e9SVinod Koul <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 20003834a2e9SVinod Koul <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 200198aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 200298aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 20033834a2e9SVinod Koul freq-table-hz = 20043834a2e9SVinod Koul <37500000 300000000>, 20053834a2e9SVinod Koul <0 0>, 20063834a2e9SVinod Koul <0 0>, 20073834a2e9SVinod Koul <37500000 300000000>, 20083834a2e9SVinod Koul <0 0>, 20093834a2e9SVinod Koul <0 0>, 20103834a2e9SVinod Koul <0 0>, 201198aee1e3SBhupesh Sharma <0 0>, 201298aee1e3SBhupesh Sharma <0 300000000>; 20133834a2e9SVinod Koul 20143834a2e9SVinod Koul status = "disabled"; 20153834a2e9SVinod Koul }; 20163834a2e9SVinod Koul 20173834a2e9SVinod Koul ufs_mem_phy: phy@1d87000 { 20183834a2e9SVinod Koul compatible = "qcom,sm8150-qmp-ufs-phy"; 2019c79ec891SVinod Koul reg = <0 0x01d87000 0 0x1c0>; 20203834a2e9SVinod Koul #address-cells = <2>; 20213834a2e9SVinod Koul #size-cells = <2>; 20223834a2e9SVinod Koul ranges; 20233834a2e9SVinod Koul clock-names = "ref", 20243834a2e9SVinod Koul "ref_aux"; 20253834a2e9SVinod Koul clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 20263834a2e9SVinod Koul <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 20273834a2e9SVinod Koul 2028fe75b0c4SBhupesh Sharma power-domains = <&gcc UFS_PHY_GDSC>; 2029fe75b0c4SBhupesh Sharma 20303834a2e9SVinod Koul resets = <&ufs_mem_hc 0>; 20313834a2e9SVinod Koul reset-names = "ufsphy"; 20323834a2e9SVinod Koul status = "disabled"; 20333834a2e9SVinod Koul 20341351512fSShawn Guo ufs_mem_phy_lanes: phy@1d87400 { 203536a31b3aSJohan Hovold reg = <0 0x01d87400 0 0x16c>, 203636a31b3aSJohan Hovold <0 0x01d87600 0 0x200>, 203736a31b3aSJohan Hovold <0 0x01d87c00 0 0x200>, 203836a31b3aSJohan Hovold <0 0x01d87800 0 0x16c>, 203936a31b3aSJohan Hovold <0 0x01d87a00 0 0x200>; 20403834a2e9SVinod Koul #phy-cells = <0>; 20413834a2e9SVinod Koul }; 20423834a2e9SVinod Koul }; 20433834a2e9SVinod Koul 204471a2fc6eSJonathan Marek ipa_virt: interconnect@1e00000 { 204571a2fc6eSJonathan Marek compatible = "qcom,sm8150-ipa-virt"; 204671a2fc6eSJonathan Marek reg = <0 0x01e00000 0 0x1000>; 204771a2fc6eSJonathan Marek #interconnect-cells = <1>; 204871a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 204971a2fc6eSJonathan Marek }; 205071a2fc6eSJonathan Marek 2051c752d491SKrzysztof Kozlowski tcsr_mutex: hwlock@1f40000 { 2052c752d491SKrzysztof Kozlowski compatible = "qcom,tcsr-mutex"; 205386d7c946SKrzysztof Kozlowski reg = <0x0 0x01f40000 0x0 0x20000>; 2054c752d491SKrzysztof Kozlowski #hwlock-cells = <1>; 205586d7c946SKrzysztof Kozlowski }; 205686d7c946SKrzysztof Kozlowski 2057d0909bf4SJohan Hovold tcsr_regs_1: syscon@1f60000 { 205886d7c946SKrzysztof Kozlowski compatible = "qcom,sm8150-tcsr", "syscon"; 205986d7c946SKrzysztof Kozlowski reg = <0x0 0x01f60000 0x0 0x20000>; 2060d8cf9372SVinod Koul }; 2061d8cf9372SVinod Koul 206249076351SSibi Sankar remoteproc_slpi: remoteproc@2400000 { 206349076351SSibi Sankar compatible = "qcom,sm8150-slpi-pas"; 206449076351SSibi Sankar reg = <0x0 0x02400000 0x0 0x4040>; 206549076351SSibi Sankar 206649076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 206749076351SSibi Sankar <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 206849076351SSibi Sankar <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 206949076351SSibi Sankar <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 207049076351SSibi Sankar <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 207149076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 207249076351SSibi Sankar "handover", "stop-ack"; 207349076351SSibi Sankar 207449076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 207549076351SSibi Sankar clock-names = "xo"; 207649076351SSibi Sankar 2077d9d327f6SSibi Sankar power-domains = <&rpmhpd 3>, 2078d0770627SBjorn Andersson <&rpmhpd 2>; 2079d9d327f6SSibi Sankar power-domain-names = "lcx", "lmx"; 208049076351SSibi Sankar 208149076351SSibi Sankar memory-region = <&slpi_mem>; 208249076351SSibi Sankar 2083d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 2084d9d327f6SSibi Sankar 208549076351SSibi Sankar qcom,smem-states = <&slpi_smp2p_out 0>; 208649076351SSibi Sankar qcom,smem-state-names = "stop"; 208749076351SSibi Sankar 208849076351SSibi Sankar status = "disabled"; 208949076351SSibi Sankar 209049076351SSibi Sankar glink-edge { 209149076351SSibi Sankar interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 209249076351SSibi Sankar label = "dsps"; 209349076351SSibi Sankar qcom,remote-pid = <3>; 209449076351SSibi Sankar mboxes = <&apss_shared 24>; 209581729330SBhupesh Sharma 209681729330SBhupesh Sharma fastrpc { 209781729330SBhupesh Sharma compatible = "qcom,fastrpc"; 209881729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 209981729330SBhupesh Sharma label = "sdsp"; 21008c8ce95bSJeya R qcom,non-secure-domain; 210181729330SBhupesh Sharma #address-cells = <1>; 210281729330SBhupesh Sharma #size-cells = <0>; 210381729330SBhupesh Sharma 210481729330SBhupesh Sharma compute-cb@1 { 210581729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 210681729330SBhupesh Sharma reg = <1>; 210781729330SBhupesh Sharma iommus = <&apps_smmu 0x05a1 0x0>; 210881729330SBhupesh Sharma }; 210981729330SBhupesh Sharma 211081729330SBhupesh Sharma compute-cb@2 { 211181729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 211281729330SBhupesh Sharma reg = <2>; 211381729330SBhupesh Sharma iommus = <&apps_smmu 0x05a2 0x0>; 211481729330SBhupesh Sharma }; 211581729330SBhupesh Sharma 211681729330SBhupesh Sharma compute-cb@3 { 211781729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 211881729330SBhupesh Sharma reg = <3>; 211981729330SBhupesh Sharma iommus = <&apps_smmu 0x05a3 0x0>; 212081729330SBhupesh Sharma /* note: shared-cb = <4> in downstream */ 212181729330SBhupesh Sharma }; 212281729330SBhupesh Sharma }; 212349076351SSibi Sankar }; 212449076351SSibi Sankar }; 212549076351SSibi Sankar 2126f30ac26dSJonathan Marek gpu: gpu@2c00000 { 2127f30ac26dSJonathan Marek /* 2128f30ac26dSJonathan Marek * note: the amd,imageon compatible makes it possible 2129f30ac26dSJonathan Marek * to use the drm/msm driver without the display node, 2130f30ac26dSJonathan Marek * make sure to remove it when display node is added 2131f30ac26dSJonathan Marek */ 2132f30ac26dSJonathan Marek compatible = "qcom,adreno-640.1", 2133f30ac26dSJonathan Marek "qcom,adreno", 2134f30ac26dSJonathan Marek "amd,imageon"; 2135f30ac26dSJonathan Marek 2136f30ac26dSJonathan Marek reg = <0 0x02c00000 0 0x40000>; 2137f30ac26dSJonathan Marek reg-names = "kgsl_3d0_reg_memory"; 2138f30ac26dSJonathan Marek 2139f30ac26dSJonathan Marek interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2140f30ac26dSJonathan Marek 2141f30ac26dSJonathan Marek iommus = <&adreno_smmu 0 0x401>; 2142f30ac26dSJonathan Marek 2143f30ac26dSJonathan Marek operating-points-v2 = <&gpu_opp_table>; 2144f30ac26dSJonathan Marek 2145f30ac26dSJonathan Marek qcom,gmu = <&gmu>; 2146f30ac26dSJonathan Marek 2147b1dc3c6bSKonrad Dybcio status = "disabled"; 2148b1dc3c6bSKonrad Dybcio 2149f30ac26dSJonathan Marek zap-shader { 2150f30ac26dSJonathan Marek memory-region = <&gpu_mem>; 2151f30ac26dSJonathan Marek }; 2152f30ac26dSJonathan Marek 2153f30ac26dSJonathan Marek /* note: downstream checks gpu binning for 675 Mhz */ 2154f30ac26dSJonathan Marek gpu_opp_table: opp-table { 2155f30ac26dSJonathan Marek compatible = "operating-points-v2"; 2156f30ac26dSJonathan Marek 2157f30ac26dSJonathan Marek opp-675000000 { 2158f30ac26dSJonathan Marek opp-hz = /bits/ 64 <675000000>; 2159f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2160f30ac26dSJonathan Marek }; 2161f30ac26dSJonathan Marek 2162f30ac26dSJonathan Marek opp-585000000 { 2163f30ac26dSJonathan Marek opp-hz = /bits/ 64 <585000000>; 2164f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2165f30ac26dSJonathan Marek }; 2166f30ac26dSJonathan Marek 2167f30ac26dSJonathan Marek opp-499200000 { 2168f30ac26dSJonathan Marek opp-hz = /bits/ 64 <499200000>; 2169f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2170f30ac26dSJonathan Marek }; 2171f30ac26dSJonathan Marek 2172f30ac26dSJonathan Marek opp-427000000 { 2173f30ac26dSJonathan Marek opp-hz = /bits/ 64 <427000000>; 2174f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2175f30ac26dSJonathan Marek }; 2176f30ac26dSJonathan Marek 2177f30ac26dSJonathan Marek opp-345000000 { 2178f30ac26dSJonathan Marek opp-hz = /bits/ 64 <345000000>; 2179f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2180f30ac26dSJonathan Marek }; 2181f30ac26dSJonathan Marek 2182f30ac26dSJonathan Marek opp-257000000 { 2183f30ac26dSJonathan Marek opp-hz = /bits/ 64 <257000000>; 2184f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2185f30ac26dSJonathan Marek }; 2186f30ac26dSJonathan Marek }; 2187f30ac26dSJonathan Marek }; 2188f30ac26dSJonathan Marek 2189f30ac26dSJonathan Marek gmu: gmu@2c6a000 { 2190f30ac26dSJonathan Marek compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2191f30ac26dSJonathan Marek 2192f30ac26dSJonathan Marek reg = <0 0x02c6a000 0 0x30000>, 2193f30ac26dSJonathan Marek <0 0x0b290000 0 0x10000>, 2194f30ac26dSJonathan Marek <0 0x0b490000 0 0x10000>; 2195f30ac26dSJonathan Marek reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2196f30ac26dSJonathan Marek 2197f30ac26dSJonathan Marek interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2198f30ac26dSJonathan Marek <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2199f30ac26dSJonathan Marek interrupt-names = "hfi", "gmu"; 2200f30ac26dSJonathan Marek 2201f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 2202f1269916SJonathan Marek <&gpucc GPU_CC_CX_GMU_CLK>, 2203f1269916SJonathan Marek <&gpucc GPU_CC_CXO_CLK>, 2204f30ac26dSJonathan Marek <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2205f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2206f30ac26dSJonathan Marek clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2207f30ac26dSJonathan Marek 2208f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>, 2209f1269916SJonathan Marek <&gpucc GPU_GX_GDSC>; 2210f30ac26dSJonathan Marek power-domain-names = "cx", "gx"; 2211f30ac26dSJonathan Marek 2212f30ac26dSJonathan Marek iommus = <&adreno_smmu 5 0x400>; 2213f30ac26dSJonathan Marek 2214f30ac26dSJonathan Marek operating-points-v2 = <&gmu_opp_table>; 2215f30ac26dSJonathan Marek 2216b1dc3c6bSKonrad Dybcio status = "disabled"; 2217b1dc3c6bSKonrad Dybcio 2218f30ac26dSJonathan Marek gmu_opp_table: opp-table { 2219f30ac26dSJonathan Marek compatible = "operating-points-v2"; 2220f30ac26dSJonathan Marek 2221f30ac26dSJonathan Marek opp-200000000 { 2222f30ac26dSJonathan Marek opp-hz = /bits/ 64 <200000000>; 2223f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2224f30ac26dSJonathan Marek }; 2225f30ac26dSJonathan Marek }; 2226f30ac26dSJonathan Marek }; 2227f30ac26dSJonathan Marek 2228f30ac26dSJonathan Marek gpucc: clock-controller@2c90000 { 2229f30ac26dSJonathan Marek compatible = "qcom,sm8150-gpucc"; 2230f30ac26dSJonathan Marek reg = <0 0x02c90000 0 0x9000>; 2231f30ac26dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>, 2232f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2233f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2234f30ac26dSJonathan Marek clock-names = "bi_tcxo", 2235f30ac26dSJonathan Marek "gcc_gpu_gpll0_clk_src", 2236f30ac26dSJonathan Marek "gcc_gpu_gpll0_div_clk_src"; 2237f30ac26dSJonathan Marek #clock-cells = <1>; 2238f30ac26dSJonathan Marek #reset-cells = <1>; 2239f30ac26dSJonathan Marek #power-domain-cells = <1>; 2240f30ac26dSJonathan Marek }; 2241f30ac26dSJonathan Marek 2242f30ac26dSJonathan Marek adreno_smmu: iommu@2ca0000 { 2243f30ac26dSJonathan Marek compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 2244f30ac26dSJonathan Marek reg = <0 0x02ca0000 0 0x10000>; 2245f30ac26dSJonathan Marek #iommu-cells = <2>; 2246f30ac26dSJonathan Marek #global-interrupts = <1>; 2247f30ac26dSJonathan Marek interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2248f30ac26dSJonathan Marek <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2249f30ac26dSJonathan Marek <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2250f30ac26dSJonathan Marek <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2251f30ac26dSJonathan Marek <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2252f30ac26dSJonathan Marek <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2253f30ac26dSJonathan Marek <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2254f30ac26dSJonathan Marek <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2255f30ac26dSJonathan Marek <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2256f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 2257f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2258f30ac26dSJonathan Marek <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2259f30ac26dSJonathan Marek clock-names = "ahb", "bus", "iface"; 2260f30ac26dSJonathan Marek 2261f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>; 2262f30ac26dSJonathan Marek }; 2263f30ac26dSJonathan Marek 2264e13c6d14SVinod Koul tlmm: pinctrl@3100000 { 2265e13c6d14SVinod Koul compatible = "qcom,sm8150-pinctrl"; 2266e13c6d14SVinod Koul reg = <0x0 0x03100000 0x0 0x300000>, 2267e13c6d14SVinod Koul <0x0 0x03500000 0x0 0x300000>, 2268e13c6d14SVinod Koul <0x0 0x03900000 0x0 0x300000>, 2269e13c6d14SVinod Koul <0x0 0x03D00000 0x0 0x300000>; 2270e13c6d14SVinod Koul reg-names = "west", "east", "north", "south"; 2271e13c6d14SVinod Koul interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2272de3abdf3SShawn Guo gpio-ranges = <&tlmm 0 0 176>; 2273e13c6d14SVinod Koul gpio-controller; 2274e13c6d14SVinod Koul #gpio-cells = <2>; 2275e13c6d14SVinod Koul interrupt-controller; 2276e13c6d14SVinod Koul #interrupt-cells = <2>; 22776127d8e4SBhupesh Sharma wakeup-parent = <&pdc>; 227881bee695SCaleb Connolly 2279028fe09cSKrzysztof Kozlowski qup_i2c0_default: qup-i2c0-default-state { 228081bee695SCaleb Connolly pins = "gpio0", "gpio1"; 228181bee695SCaleb Connolly function = "qup0"; 228281bee695SCaleb Connolly drive-strength = <0x02>; 228381bee695SCaleb Connolly bias-disable; 228481bee695SCaleb Connolly }; 228581bee695SCaleb Connolly 2286028fe09cSKrzysztof Kozlowski qup_spi0_default: qup-spi0-default-state { 2287129e1c96SFelipe Balbi pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2288129e1c96SFelipe Balbi function = "qup0"; 2289129e1c96SFelipe Balbi drive-strength = <6>; 2290129e1c96SFelipe Balbi bias-disable; 2291129e1c96SFelipe Balbi }; 2292129e1c96SFelipe Balbi 2293028fe09cSKrzysztof Kozlowski qup_i2c1_default: qup-i2c1-default-state { 229481bee695SCaleb Connolly pins = "gpio114", "gpio115"; 229581bee695SCaleb Connolly function = "qup1"; 2296028fe09cSKrzysztof Kozlowski drive-strength = <2>; 229781bee695SCaleb Connolly bias-disable; 229881bee695SCaleb Connolly }; 229981bee695SCaleb Connolly 2300028fe09cSKrzysztof Kozlowski qup_spi1_default: qup-spi1-default-state { 2301129e1c96SFelipe Balbi pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2302129e1c96SFelipe Balbi function = "qup1"; 2303129e1c96SFelipe Balbi drive-strength = <6>; 2304129e1c96SFelipe Balbi bias-disable; 2305129e1c96SFelipe Balbi }; 2306129e1c96SFelipe Balbi 2307028fe09cSKrzysztof Kozlowski qup_i2c2_default: qup-i2c2-default-state { 230881bee695SCaleb Connolly pins = "gpio126", "gpio127"; 230981bee695SCaleb Connolly function = "qup2"; 2310028fe09cSKrzysztof Kozlowski drive-strength = <2>; 231181bee695SCaleb Connolly bias-disable; 231281bee695SCaleb Connolly }; 231381bee695SCaleb Connolly 2314028fe09cSKrzysztof Kozlowski qup_spi2_default: qup-spi2-default-state { 2315129e1c96SFelipe Balbi pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2316129e1c96SFelipe Balbi function = "qup2"; 2317129e1c96SFelipe Balbi drive-strength = <6>; 2318129e1c96SFelipe Balbi bias-disable; 2319129e1c96SFelipe Balbi }; 2320129e1c96SFelipe Balbi 2321028fe09cSKrzysztof Kozlowski qup_i2c3_default: qup-i2c3-default-state { 232281bee695SCaleb Connolly pins = "gpio144", "gpio145"; 232381bee695SCaleb Connolly function = "qup3"; 2324028fe09cSKrzysztof Kozlowski drive-strength = <2>; 232581bee695SCaleb Connolly bias-disable; 232681bee695SCaleb Connolly }; 232781bee695SCaleb Connolly 2328028fe09cSKrzysztof Kozlowski qup_spi3_default: qup-spi3-default-state { 2329129e1c96SFelipe Balbi pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2330129e1c96SFelipe Balbi function = "qup3"; 2331129e1c96SFelipe Balbi drive-strength = <6>; 2332129e1c96SFelipe Balbi bias-disable; 2333129e1c96SFelipe Balbi }; 2334129e1c96SFelipe Balbi 2335028fe09cSKrzysztof Kozlowski qup_i2c4_default: qup-i2c4-default-state { 233681bee695SCaleb Connolly pins = "gpio51", "gpio52"; 233781bee695SCaleb Connolly function = "qup4"; 2338028fe09cSKrzysztof Kozlowski drive-strength = <2>; 233981bee695SCaleb Connolly bias-disable; 234081bee695SCaleb Connolly }; 234181bee695SCaleb Connolly 2342028fe09cSKrzysztof Kozlowski qup_spi4_default: qup-spi4-default-state { 2343129e1c96SFelipe Balbi pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2344129e1c96SFelipe Balbi function = "qup4"; 2345129e1c96SFelipe Balbi drive-strength = <6>; 2346129e1c96SFelipe Balbi bias-disable; 2347129e1c96SFelipe Balbi }; 2348129e1c96SFelipe Balbi 2349028fe09cSKrzysztof Kozlowski qup_i2c5_default: qup-i2c5-default-state { 235081bee695SCaleb Connolly pins = "gpio121", "gpio122"; 235181bee695SCaleb Connolly function = "qup5"; 2352028fe09cSKrzysztof Kozlowski drive-strength = <2>; 235381bee695SCaleb Connolly bias-disable; 235481bee695SCaleb Connolly }; 235581bee695SCaleb Connolly 2356028fe09cSKrzysztof Kozlowski qup_spi5_default: qup-spi5-default-state { 2357129e1c96SFelipe Balbi pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2358129e1c96SFelipe Balbi function = "qup5"; 2359129e1c96SFelipe Balbi drive-strength = <6>; 2360129e1c96SFelipe Balbi bias-disable; 2361129e1c96SFelipe Balbi }; 2362129e1c96SFelipe Balbi 2363028fe09cSKrzysztof Kozlowski qup_i2c6_default: qup-i2c6-default-state { 236481bee695SCaleb Connolly pins = "gpio6", "gpio7"; 236581bee695SCaleb Connolly function = "qup6"; 2366028fe09cSKrzysztof Kozlowski drive-strength = <2>; 236781bee695SCaleb Connolly bias-disable; 236881bee695SCaleb Connolly }; 236981bee695SCaleb Connolly 2370028fe09cSKrzysztof Kozlowski qup_spi6_default: qup-spi6_default-state { 2371129e1c96SFelipe Balbi pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2372129e1c96SFelipe Balbi function = "qup6"; 2373129e1c96SFelipe Balbi drive-strength = <6>; 2374129e1c96SFelipe Balbi bias-disable; 2375129e1c96SFelipe Balbi }; 2376129e1c96SFelipe Balbi 2377028fe09cSKrzysztof Kozlowski qup_i2c7_default: qup-i2c7-default-state { 237881bee695SCaleb Connolly pins = "gpio98", "gpio99"; 237981bee695SCaleb Connolly function = "qup7"; 2380028fe09cSKrzysztof Kozlowski drive-strength = <2>; 238181bee695SCaleb Connolly bias-disable; 238281bee695SCaleb Connolly }; 238381bee695SCaleb Connolly 2384028fe09cSKrzysztof Kozlowski qup_spi7_default: qup-spi7_default-state { 2385129e1c96SFelipe Balbi pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2386129e1c96SFelipe Balbi function = "qup7"; 2387129e1c96SFelipe Balbi drive-strength = <6>; 2388129e1c96SFelipe Balbi bias-disable; 2389129e1c96SFelipe Balbi }; 2390129e1c96SFelipe Balbi 2391028fe09cSKrzysztof Kozlowski qup_i2c8_default: qup-i2c8-default-state { 239281bee695SCaleb Connolly pins = "gpio88", "gpio89"; 239381bee695SCaleb Connolly function = "qup8"; 2394028fe09cSKrzysztof Kozlowski drive-strength = <2>; 239581bee695SCaleb Connolly bias-disable; 239681bee695SCaleb Connolly }; 239781bee695SCaleb Connolly 2398028fe09cSKrzysztof Kozlowski qup_spi8_default: qup-spi8-default-state { 2399129e1c96SFelipe Balbi pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2400129e1c96SFelipe Balbi function = "qup8"; 2401129e1c96SFelipe Balbi drive-strength = <6>; 2402129e1c96SFelipe Balbi bias-disable; 2403129e1c96SFelipe Balbi }; 2404129e1c96SFelipe Balbi 2405028fe09cSKrzysztof Kozlowski qup_i2c9_default: qup-i2c9-default-state { 240681bee695SCaleb Connolly pins = "gpio39", "gpio40"; 240781bee695SCaleb Connolly function = "qup9"; 2408028fe09cSKrzysztof Kozlowski drive-strength = <2>; 240981bee695SCaleb Connolly bias-disable; 241081bee695SCaleb Connolly }; 241181bee695SCaleb Connolly 2412028fe09cSKrzysztof Kozlowski qup_spi9_default: qup-spi9-default-state { 2413129e1c96SFelipe Balbi pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2414129e1c96SFelipe Balbi function = "qup9"; 2415129e1c96SFelipe Balbi drive-strength = <6>; 2416129e1c96SFelipe Balbi bias-disable; 2417129e1c96SFelipe Balbi }; 2418129e1c96SFelipe Balbi 2419028fe09cSKrzysztof Kozlowski qup_i2c10_default: qup-i2c10-default-state { 242081bee695SCaleb Connolly pins = "gpio9", "gpio10"; 242181bee695SCaleb Connolly function = "qup10"; 2422028fe09cSKrzysztof Kozlowski drive-strength = <2>; 242381bee695SCaleb Connolly bias-disable; 242481bee695SCaleb Connolly }; 242581bee695SCaleb Connolly 2426028fe09cSKrzysztof Kozlowski qup_spi10_default: qup-spi10-default-state { 2427129e1c96SFelipe Balbi pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2428129e1c96SFelipe Balbi function = "qup10"; 2429129e1c96SFelipe Balbi drive-strength = <6>; 2430129e1c96SFelipe Balbi bias-disable; 2431129e1c96SFelipe Balbi }; 2432129e1c96SFelipe Balbi 2433028fe09cSKrzysztof Kozlowski qup_i2c11_default: qup-i2c11-default-state { 243481bee695SCaleb Connolly pins = "gpio94", "gpio95"; 243581bee695SCaleb Connolly function = "qup11"; 2436028fe09cSKrzysztof Kozlowski drive-strength = <2>; 243781bee695SCaleb Connolly bias-disable; 243881bee695SCaleb Connolly }; 243981bee695SCaleb Connolly 2440028fe09cSKrzysztof Kozlowski qup_spi11_default: qup-spi11-default-state { 2441129e1c96SFelipe Balbi pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2442129e1c96SFelipe Balbi function = "qup11"; 2443129e1c96SFelipe Balbi drive-strength = <6>; 2444129e1c96SFelipe Balbi bias-disable; 2445129e1c96SFelipe Balbi }; 2446129e1c96SFelipe Balbi 2447028fe09cSKrzysztof Kozlowski qup_i2c12_default: qup-i2c12-default-state { 244881bee695SCaleb Connolly pins = "gpio83", "gpio84"; 244981bee695SCaleb Connolly function = "qup12"; 2450028fe09cSKrzysztof Kozlowski drive-strength = <2>; 245181bee695SCaleb Connolly bias-disable; 245281bee695SCaleb Connolly }; 245381bee695SCaleb Connolly 2454028fe09cSKrzysztof Kozlowski qup_spi12_default: qup-spi12-default-state { 2455129e1c96SFelipe Balbi pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2456129e1c96SFelipe Balbi function = "qup12"; 2457129e1c96SFelipe Balbi drive-strength = <6>; 2458129e1c96SFelipe Balbi bias-disable; 2459129e1c96SFelipe Balbi }; 2460129e1c96SFelipe Balbi 2461028fe09cSKrzysztof Kozlowski qup_i2c13_default: qup-i2c13-default-state { 246281bee695SCaleb Connolly pins = "gpio43", "gpio44"; 246381bee695SCaleb Connolly function = "qup13"; 2464028fe09cSKrzysztof Kozlowski drive-strength = <2>; 246581bee695SCaleb Connolly bias-disable; 246681bee695SCaleb Connolly }; 246781bee695SCaleb Connolly 2468028fe09cSKrzysztof Kozlowski qup_spi13_default: qup-spi13-default-state { 2469129e1c96SFelipe Balbi pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2470129e1c96SFelipe Balbi function = "qup13"; 2471129e1c96SFelipe Balbi drive-strength = <6>; 2472129e1c96SFelipe Balbi bias-disable; 2473129e1c96SFelipe Balbi }; 2474129e1c96SFelipe Balbi 2475028fe09cSKrzysztof Kozlowski qup_i2c14_default: qup-i2c14-default-state { 247681bee695SCaleb Connolly pins = "gpio47", "gpio48"; 247781bee695SCaleb Connolly function = "qup14"; 2478028fe09cSKrzysztof Kozlowski drive-strength = <2>; 247981bee695SCaleb Connolly bias-disable; 248081bee695SCaleb Connolly }; 248181bee695SCaleb Connolly 2482028fe09cSKrzysztof Kozlowski qup_spi14_default: qup-spi14-default-state { 2483129e1c96SFelipe Balbi pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2484129e1c96SFelipe Balbi function = "qup14"; 2485129e1c96SFelipe Balbi drive-strength = <6>; 2486129e1c96SFelipe Balbi bias-disable; 2487129e1c96SFelipe Balbi }; 2488129e1c96SFelipe Balbi 2489028fe09cSKrzysztof Kozlowski qup_i2c15_default: qup-i2c15-default-state { 249081bee695SCaleb Connolly pins = "gpio27", "gpio28"; 249181bee695SCaleb Connolly function = "qup15"; 2492028fe09cSKrzysztof Kozlowski drive-strength = <2>; 249381bee695SCaleb Connolly bias-disable; 249481bee695SCaleb Connolly }; 249581bee695SCaleb Connolly 2496028fe09cSKrzysztof Kozlowski qup_spi15_default: qup-spi15-default-state { 2497129e1c96SFelipe Balbi pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2498129e1c96SFelipe Balbi function = "qup15"; 2499129e1c96SFelipe Balbi drive-strength = <6>; 2500129e1c96SFelipe Balbi bias-disable; 2501129e1c96SFelipe Balbi }; 2502129e1c96SFelipe Balbi 2503028fe09cSKrzysztof Kozlowski qup_i2c16_default: qup-i2c16-default-state { 250481bee695SCaleb Connolly pins = "gpio86", "gpio85"; 250581bee695SCaleb Connolly function = "qup16"; 2506028fe09cSKrzysztof Kozlowski drive-strength = <2>; 250781bee695SCaleb Connolly bias-disable; 250881bee695SCaleb Connolly }; 250981bee695SCaleb Connolly 2510028fe09cSKrzysztof Kozlowski qup_spi16_default: qup-spi16-default-state { 2511129e1c96SFelipe Balbi pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2512129e1c96SFelipe Balbi function = "qup16"; 2513129e1c96SFelipe Balbi drive-strength = <6>; 2514129e1c96SFelipe Balbi bias-disable; 2515129e1c96SFelipe Balbi }; 2516129e1c96SFelipe Balbi 2517028fe09cSKrzysztof Kozlowski qup_i2c17_default: qup-i2c17-default-state { 251881bee695SCaleb Connolly pins = "gpio55", "gpio56"; 251981bee695SCaleb Connolly function = "qup17"; 2520028fe09cSKrzysztof Kozlowski drive-strength = <2>; 252181bee695SCaleb Connolly bias-disable; 252281bee695SCaleb Connolly }; 252381bee695SCaleb Connolly 2524028fe09cSKrzysztof Kozlowski qup_spi17_default: qup-spi17-default-state { 2525129e1c96SFelipe Balbi pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2526129e1c96SFelipe Balbi function = "qup17"; 2527129e1c96SFelipe Balbi drive-strength = <6>; 2528129e1c96SFelipe Balbi bias-disable; 2529129e1c96SFelipe Balbi }; 2530129e1c96SFelipe Balbi 2531028fe09cSKrzysztof Kozlowski qup_i2c18_default: qup-i2c18-default-state { 253281bee695SCaleb Connolly pins = "gpio23", "gpio24"; 253381bee695SCaleb Connolly function = "qup18"; 2534028fe09cSKrzysztof Kozlowski drive-strength = <2>; 253581bee695SCaleb Connolly bias-disable; 253681bee695SCaleb Connolly }; 253781bee695SCaleb Connolly 2538028fe09cSKrzysztof Kozlowski qup_spi18_default: qup-spi18-default-state { 2539129e1c96SFelipe Balbi pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2540129e1c96SFelipe Balbi function = "qup18"; 2541129e1c96SFelipe Balbi drive-strength = <6>; 2542129e1c96SFelipe Balbi bias-disable; 2543129e1c96SFelipe Balbi }; 2544129e1c96SFelipe Balbi 2545028fe09cSKrzysztof Kozlowski qup_i2c19_default: qup-i2c19-default-state { 254681bee695SCaleb Connolly pins = "gpio57", "gpio58"; 254781bee695SCaleb Connolly function = "qup19"; 2548028fe09cSKrzysztof Kozlowski drive-strength = <2>; 254981bee695SCaleb Connolly bias-disable; 255081bee695SCaleb Connolly }; 2551129e1c96SFelipe Balbi 2552028fe09cSKrzysztof Kozlowski qup_spi19_default: qup-spi19-default-state { 2553129e1c96SFelipe Balbi pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2554129e1c96SFelipe Balbi function = "qup19"; 2555129e1c96SFelipe Balbi drive-strength = <6>; 2556129e1c96SFelipe Balbi bias-disable; 2557129e1c96SFelipe Balbi }; 2558a1c86c68SBhupesh Sharma 2559028fe09cSKrzysztof Kozlowski pcie0_default_state: pcie0-default-state { 2560028fe09cSKrzysztof Kozlowski perst-pins { 2561a1c86c68SBhupesh Sharma pins = "gpio35"; 2562a1c86c68SBhupesh Sharma function = "gpio"; 2563a1c86c68SBhupesh Sharma drive-strength = <2>; 2564a1c86c68SBhupesh Sharma bias-pull-down; 2565a1c86c68SBhupesh Sharma }; 2566a1c86c68SBhupesh Sharma 2567028fe09cSKrzysztof Kozlowski clkreq-pins { 2568a1c86c68SBhupesh Sharma pins = "gpio36"; 2569a1c86c68SBhupesh Sharma function = "pci_e0"; 2570a1c86c68SBhupesh Sharma drive-strength = <2>; 2571a1c86c68SBhupesh Sharma bias-pull-up; 2572a1c86c68SBhupesh Sharma }; 2573a1c86c68SBhupesh Sharma 2574028fe09cSKrzysztof Kozlowski wake-pins { 2575a1c86c68SBhupesh Sharma pins = "gpio37"; 2576a1c86c68SBhupesh Sharma function = "gpio"; 2577a1c86c68SBhupesh Sharma drive-strength = <2>; 2578a1c86c68SBhupesh Sharma bias-pull-up; 2579a1c86c68SBhupesh Sharma }; 2580a1c86c68SBhupesh Sharma }; 2581a1c86c68SBhupesh Sharma 2582028fe09cSKrzysztof Kozlowski pcie1_default_state: pcie1-default-state { 2583028fe09cSKrzysztof Kozlowski perst-pins { 2584a1c86c68SBhupesh Sharma pins = "gpio102"; 2585a1c86c68SBhupesh Sharma function = "gpio"; 2586a1c86c68SBhupesh Sharma drive-strength = <2>; 2587a1c86c68SBhupesh Sharma bias-pull-down; 2588a1c86c68SBhupesh Sharma }; 2589a1c86c68SBhupesh Sharma 2590028fe09cSKrzysztof Kozlowski clkreq-pins { 2591a1c86c68SBhupesh Sharma pins = "gpio103"; 2592a1c86c68SBhupesh Sharma function = "pci_e1"; 2593a1c86c68SBhupesh Sharma drive-strength = <2>; 2594a1c86c68SBhupesh Sharma bias-pull-up; 2595a1c86c68SBhupesh Sharma }; 2596a1c86c68SBhupesh Sharma 2597028fe09cSKrzysztof Kozlowski wake-pins { 2598a1c86c68SBhupesh Sharma pins = "gpio104"; 2599a1c86c68SBhupesh Sharma function = "gpio"; 2600a1c86c68SBhupesh Sharma drive-strength = <2>; 2601a1c86c68SBhupesh Sharma bias-pull-up; 2602a1c86c68SBhupesh Sharma }; 2603a1c86c68SBhupesh Sharma }; 2604e13c6d14SVinod Koul }; 2605e13c6d14SVinod Koul 260649076351SSibi Sankar remoteproc_mpss: remoteproc@4080000 { 260749076351SSibi Sankar compatible = "qcom,sm8150-mpss-pas"; 260849076351SSibi Sankar reg = <0x0 0x04080000 0x0 0x4040>; 260949076351SSibi Sankar 261049076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 261149076351SSibi Sankar <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 261249076351SSibi Sankar <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 261349076351SSibi Sankar <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 261449076351SSibi Sankar <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 261549076351SSibi Sankar <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 261649076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", "handover", 261749076351SSibi Sankar "stop-ack", "shutdown-ack"; 261849076351SSibi Sankar 261949076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 262049076351SSibi Sankar clock-names = "xo"; 262149076351SSibi Sankar 2622d9d327f6SSibi Sankar power-domains = <&rpmhpd 7>, 2623d0770627SBjorn Andersson <&rpmhpd 0>; 2624d9d327f6SSibi Sankar power-domain-names = "cx", "mss"; 262549076351SSibi Sankar 262649076351SSibi Sankar memory-region = <&mpss_mem>; 262749076351SSibi Sankar 2628d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 2629d9d327f6SSibi Sankar 263049076351SSibi Sankar qcom,smem-states = <&modem_smp2p_out 0>; 263149076351SSibi Sankar qcom,smem-state-names = "stop"; 263249076351SSibi Sankar 2633b1dc3c6bSKonrad Dybcio status = "disabled"; 2634b1dc3c6bSKonrad Dybcio 263549076351SSibi Sankar glink-edge { 263649076351SSibi Sankar interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 263749076351SSibi Sankar label = "modem"; 263849076351SSibi Sankar qcom,remote-pid = <1>; 263949076351SSibi Sankar mboxes = <&apss_shared 12>; 264049076351SSibi Sankar }; 264149076351SSibi Sankar }; 264249076351SSibi Sankar 264324244cefSSai Prakash Ranjan stm@6002000 { 264424244cefSSai Prakash Ranjan compatible = "arm,coresight-stm", "arm,primecell"; 264524244cefSSai Prakash Ranjan reg = <0 0x06002000 0 0x1000>, 264624244cefSSai Prakash Ranjan <0 0x16280000 0 0x180000>; 264724244cefSSai Prakash Ranjan reg-names = "stm-base", "stm-stimulus-base"; 264824244cefSSai Prakash Ranjan 264924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 265024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 265124244cefSSai Prakash Ranjan 265224244cefSSai Prakash Ranjan out-ports { 265324244cefSSai Prakash Ranjan port { 265424244cefSSai Prakash Ranjan stm_out: endpoint { 265524244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_in7>; 265624244cefSSai Prakash Ranjan }; 265724244cefSSai Prakash Ranjan }; 265824244cefSSai Prakash Ranjan }; 265924244cefSSai Prakash Ranjan }; 266024244cefSSai Prakash Ranjan 266124244cefSSai Prakash Ranjan funnel@6041000 { 266224244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 266324244cefSSai Prakash Ranjan reg = <0 0x06041000 0 0x1000>; 266424244cefSSai Prakash Ranjan 266524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 266624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 266724244cefSSai Prakash Ranjan 266824244cefSSai Prakash Ranjan out-ports { 266924244cefSSai Prakash Ranjan port { 267024244cefSSai Prakash Ranjan funnel0_out: endpoint { 267124244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in0>; 267224244cefSSai Prakash Ranjan }; 267324244cefSSai Prakash Ranjan }; 267424244cefSSai Prakash Ranjan }; 267524244cefSSai Prakash Ranjan 267624244cefSSai Prakash Ranjan in-ports { 267724244cefSSai Prakash Ranjan #address-cells = <1>; 267824244cefSSai Prakash Ranjan #size-cells = <0>; 267924244cefSSai Prakash Ranjan 268024244cefSSai Prakash Ranjan port@7 { 268124244cefSSai Prakash Ranjan reg = <7>; 268224244cefSSai Prakash Ranjan funnel0_in7: endpoint { 268324244cefSSai Prakash Ranjan remote-endpoint = <&stm_out>; 268424244cefSSai Prakash Ranjan }; 268524244cefSSai Prakash Ranjan }; 268624244cefSSai Prakash Ranjan }; 268724244cefSSai Prakash Ranjan }; 268824244cefSSai Prakash Ranjan 268924244cefSSai Prakash Ranjan funnel@6042000 { 269024244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 269124244cefSSai Prakash Ranjan reg = <0 0x06042000 0 0x1000>; 269224244cefSSai Prakash Ranjan 269324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 269424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 269524244cefSSai Prakash Ranjan 269624244cefSSai Prakash Ranjan out-ports { 269724244cefSSai Prakash Ranjan port { 269824244cefSSai Prakash Ranjan funnel1_out: endpoint { 269924244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in1>; 270024244cefSSai Prakash Ranjan }; 270124244cefSSai Prakash Ranjan }; 270224244cefSSai Prakash Ranjan }; 270324244cefSSai Prakash Ranjan 270424244cefSSai Prakash Ranjan in-ports { 270524244cefSSai Prakash Ranjan #address-cells = <1>; 270624244cefSSai Prakash Ranjan #size-cells = <0>; 270724244cefSSai Prakash Ranjan 270824244cefSSai Prakash Ranjan port@4 { 270924244cefSSai Prakash Ranjan reg = <4>; 271024244cefSSai Prakash Ranjan funnel1_in4: endpoint { 271124244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_out>; 271224244cefSSai Prakash Ranjan }; 271324244cefSSai Prakash Ranjan }; 271424244cefSSai Prakash Ranjan }; 271524244cefSSai Prakash Ranjan }; 271624244cefSSai Prakash Ranjan 271724244cefSSai Prakash Ranjan funnel@6043000 { 271824244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 271924244cefSSai Prakash Ranjan reg = <0 0x06043000 0 0x1000>; 272024244cefSSai Prakash Ranjan 272124244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 272224244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 272324244cefSSai Prakash Ranjan 272424244cefSSai Prakash Ranjan out-ports { 272524244cefSSai Prakash Ranjan port { 272624244cefSSai Prakash Ranjan funnel2_out: endpoint { 272724244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in2>; 272824244cefSSai Prakash Ranjan }; 272924244cefSSai Prakash Ranjan }; 273024244cefSSai Prakash Ranjan }; 273124244cefSSai Prakash Ranjan 273224244cefSSai Prakash Ranjan in-ports { 273324244cefSSai Prakash Ranjan #address-cells = <1>; 273424244cefSSai Prakash Ranjan #size-cells = <0>; 273524244cefSSai Prakash Ranjan 273624244cefSSai Prakash Ranjan port@2 { 273724244cefSSai Prakash Ranjan reg = <2>; 273824244cefSSai Prakash Ranjan funnel2_in2: endpoint { 273924244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_out>; 274024244cefSSai Prakash Ranjan }; 274124244cefSSai Prakash Ranjan }; 274224244cefSSai Prakash Ranjan }; 274324244cefSSai Prakash Ranjan }; 274424244cefSSai Prakash Ranjan 274524244cefSSai Prakash Ranjan funnel@6045000 { 274624244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 274724244cefSSai Prakash Ranjan reg = <0 0x06045000 0 0x1000>; 274824244cefSSai Prakash Ranjan 274924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 275024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 275124244cefSSai Prakash Ranjan 275224244cefSSai Prakash Ranjan out-ports { 275324244cefSSai Prakash Ranjan port { 275424244cefSSai Prakash Ranjan merge_funnel_out: endpoint { 275524244cefSSai Prakash Ranjan remote-endpoint = <&etf_in>; 275624244cefSSai Prakash Ranjan }; 275724244cefSSai Prakash Ranjan }; 275824244cefSSai Prakash Ranjan }; 275924244cefSSai Prakash Ranjan 276024244cefSSai Prakash Ranjan in-ports { 276124244cefSSai Prakash Ranjan #address-cells = <1>; 276224244cefSSai Prakash Ranjan #size-cells = <0>; 276324244cefSSai Prakash Ranjan 276424244cefSSai Prakash Ranjan port@0 { 276524244cefSSai Prakash Ranjan reg = <0>; 276624244cefSSai Prakash Ranjan merge_funnel_in0: endpoint { 276724244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_out>; 276824244cefSSai Prakash Ranjan }; 276924244cefSSai Prakash Ranjan }; 277024244cefSSai Prakash Ranjan 277124244cefSSai Prakash Ranjan port@1 { 277224244cefSSai Prakash Ranjan reg = <1>; 277324244cefSSai Prakash Ranjan merge_funnel_in1: endpoint { 277424244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_out>; 277524244cefSSai Prakash Ranjan }; 277624244cefSSai Prakash Ranjan }; 277724244cefSSai Prakash Ranjan 277824244cefSSai Prakash Ranjan port@2 { 277924244cefSSai Prakash Ranjan reg = <2>; 278024244cefSSai Prakash Ranjan merge_funnel_in2: endpoint { 278124244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_out>; 278224244cefSSai Prakash Ranjan }; 278324244cefSSai Prakash Ranjan }; 278424244cefSSai Prakash Ranjan }; 278524244cefSSai Prakash Ranjan }; 278624244cefSSai Prakash Ranjan 278724244cefSSai Prakash Ranjan replicator@6046000 { 278824244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 278924244cefSSai Prakash Ranjan reg = <0 0x06046000 0 0x1000>; 279024244cefSSai Prakash Ranjan 279124244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 279224244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 279324244cefSSai Prakash Ranjan 279424244cefSSai Prakash Ranjan out-ports { 279524244cefSSai Prakash Ranjan #address-cells = <1>; 279624244cefSSai Prakash Ranjan #size-cells = <0>; 279724244cefSSai Prakash Ranjan 279824244cefSSai Prakash Ranjan port@0 { 279924244cefSSai Prakash Ranjan reg = <0>; 280024244cefSSai Prakash Ranjan replicator_out0: endpoint { 280124244cefSSai Prakash Ranjan remote-endpoint = <&etr_in>; 280224244cefSSai Prakash Ranjan }; 280324244cefSSai Prakash Ranjan }; 280424244cefSSai Prakash Ranjan 280524244cefSSai Prakash Ranjan port@1 { 280624244cefSSai Prakash Ranjan reg = <1>; 280724244cefSSai Prakash Ranjan replicator_out1: endpoint { 280824244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_in>; 280924244cefSSai Prakash Ranjan }; 281024244cefSSai Prakash Ranjan }; 281124244cefSSai Prakash Ranjan }; 281224244cefSSai Prakash Ranjan 281324244cefSSai Prakash Ranjan in-ports { 281424244cefSSai Prakash Ranjan port { 281524244cefSSai Prakash Ranjan replicator_in0: endpoint { 281624244cefSSai Prakash Ranjan remote-endpoint = <&etf_out>; 281724244cefSSai Prakash Ranjan }; 281824244cefSSai Prakash Ranjan }; 281924244cefSSai Prakash Ranjan }; 282024244cefSSai Prakash Ranjan }; 282124244cefSSai Prakash Ranjan 282224244cefSSai Prakash Ranjan etf@6047000 { 282324244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 282424244cefSSai Prakash Ranjan reg = <0 0x06047000 0 0x1000>; 282524244cefSSai Prakash Ranjan 282624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 282724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 282824244cefSSai Prakash Ranjan 282924244cefSSai Prakash Ranjan out-ports { 283024244cefSSai Prakash Ranjan port { 283124244cefSSai Prakash Ranjan etf_out: endpoint { 283224244cefSSai Prakash Ranjan remote-endpoint = <&replicator_in0>; 283324244cefSSai Prakash Ranjan }; 283424244cefSSai Prakash Ranjan }; 283524244cefSSai Prakash Ranjan }; 283624244cefSSai Prakash Ranjan 283724244cefSSai Prakash Ranjan in-ports { 283824244cefSSai Prakash Ranjan port { 283924244cefSSai Prakash Ranjan etf_in: endpoint { 284024244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_out>; 284124244cefSSai Prakash Ranjan }; 284224244cefSSai Prakash Ranjan }; 284324244cefSSai Prakash Ranjan }; 284424244cefSSai Prakash Ranjan }; 284524244cefSSai Prakash Ranjan 284624244cefSSai Prakash Ranjan etr@6048000 { 284724244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 284824244cefSSai Prakash Ranjan reg = <0 0x06048000 0 0x1000>; 284924244cefSSai Prakash Ranjan iommus = <&apps_smmu 0x05e0 0x0>; 285024244cefSSai Prakash Ranjan 285124244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 285224244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 285324244cefSSai Prakash Ranjan arm,scatter-gather; 285424244cefSSai Prakash Ranjan 285524244cefSSai Prakash Ranjan in-ports { 285624244cefSSai Prakash Ranjan port { 285724244cefSSai Prakash Ranjan etr_in: endpoint { 285824244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out0>; 285924244cefSSai Prakash Ranjan }; 286024244cefSSai Prakash Ranjan }; 286124244cefSSai Prakash Ranjan }; 286224244cefSSai Prakash Ranjan }; 286324244cefSSai Prakash Ranjan 286424244cefSSai Prakash Ranjan replicator@604a000 { 286524244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 286624244cefSSai Prakash Ranjan reg = <0 0x0604a000 0 0x1000>; 286724244cefSSai Prakash Ranjan 286824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 286924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 287024244cefSSai Prakash Ranjan 287124244cefSSai Prakash Ranjan out-ports { 287224244cefSSai Prakash Ranjan #address-cells = <1>; 287324244cefSSai Prakash Ranjan #size-cells = <0>; 287424244cefSSai Prakash Ranjan 287524244cefSSai Prakash Ranjan port@1 { 287624244cefSSai Prakash Ranjan reg = <1>; 287724244cefSSai Prakash Ranjan replicator1_out: endpoint { 287824244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_in>; 287924244cefSSai Prakash Ranjan }; 288024244cefSSai Prakash Ranjan }; 288124244cefSSai Prakash Ranjan }; 288224244cefSSai Prakash Ranjan 288324244cefSSai Prakash Ranjan in-ports { 288424244cefSSai Prakash Ranjan #address-cells = <1>; 288524244cefSSai Prakash Ranjan #size-cells = <0>; 288624244cefSSai Prakash Ranjan 288724244cefSSai Prakash Ranjan port@1 { 288824244cefSSai Prakash Ranjan reg = <1>; 288924244cefSSai Prakash Ranjan replicator1_in: endpoint { 289024244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out1>; 289124244cefSSai Prakash Ranjan }; 289224244cefSSai Prakash Ranjan }; 289324244cefSSai Prakash Ranjan }; 289424244cefSSai Prakash Ranjan }; 289524244cefSSai Prakash Ranjan 289624244cefSSai Prakash Ranjan funnel@6b08000 { 289724244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 289824244cefSSai Prakash Ranjan reg = <0 0x06b08000 0 0x1000>; 289924244cefSSai Prakash Ranjan 290024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 290124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 290224244cefSSai Prakash Ranjan 290324244cefSSai Prakash Ranjan out-ports { 290424244cefSSai Prakash Ranjan port { 290524244cefSSai Prakash Ranjan swao_funnel_out: endpoint { 290624244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_in>; 290724244cefSSai Prakash Ranjan }; 290824244cefSSai Prakash Ranjan }; 290924244cefSSai Prakash Ranjan }; 291024244cefSSai Prakash Ranjan 291124244cefSSai Prakash Ranjan in-ports { 291224244cefSSai Prakash Ranjan #address-cells = <1>; 291324244cefSSai Prakash Ranjan #size-cells = <0>; 291424244cefSSai Prakash Ranjan 291524244cefSSai Prakash Ranjan port@6 { 291624244cefSSai Prakash Ranjan reg = <6>; 291724244cefSSai Prakash Ranjan swao_funnel_in: endpoint { 291824244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_out>; 291924244cefSSai Prakash Ranjan }; 292024244cefSSai Prakash Ranjan }; 292124244cefSSai Prakash Ranjan }; 292224244cefSSai Prakash Ranjan }; 292324244cefSSai Prakash Ranjan 292424244cefSSai Prakash Ranjan etf@6b09000 { 292524244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 292624244cefSSai Prakash Ranjan reg = <0 0x06b09000 0 0x1000>; 292724244cefSSai Prakash Ranjan 292824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 292924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 293024244cefSSai Prakash Ranjan 293124244cefSSai Prakash Ranjan out-ports { 293224244cefSSai Prakash Ranjan port { 293324244cefSSai Prakash Ranjan swao_etf_out: endpoint { 293424244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_in>; 293524244cefSSai Prakash Ranjan }; 293624244cefSSai Prakash Ranjan }; 293724244cefSSai Prakash Ranjan }; 293824244cefSSai Prakash Ranjan 293924244cefSSai Prakash Ranjan in-ports { 294024244cefSSai Prakash Ranjan port { 294124244cefSSai Prakash Ranjan swao_etf_in: endpoint { 294224244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_out>; 294324244cefSSai Prakash Ranjan }; 294424244cefSSai Prakash Ranjan }; 294524244cefSSai Prakash Ranjan }; 294624244cefSSai Prakash Ranjan }; 294724244cefSSai Prakash Ranjan 294824244cefSSai Prakash Ranjan replicator@6b0a000 { 294924244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 295024244cefSSai Prakash Ranjan reg = <0 0x06b0a000 0 0x1000>; 295124244cefSSai Prakash Ranjan 295224244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 295324244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 295424244cefSSai Prakash Ranjan qcom,replicator-loses-context; 295524244cefSSai Prakash Ranjan 295624244cefSSai Prakash Ranjan out-ports { 295724244cefSSai Prakash Ranjan port { 295824244cefSSai Prakash Ranjan swao_replicator_out: endpoint { 295924244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_in4>; 296024244cefSSai Prakash Ranjan }; 296124244cefSSai Prakash Ranjan }; 296224244cefSSai Prakash Ranjan }; 296324244cefSSai Prakash Ranjan 296424244cefSSai Prakash Ranjan in-ports { 296524244cefSSai Prakash Ranjan port { 296624244cefSSai Prakash Ranjan swao_replicator_in: endpoint { 296724244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_out>; 296824244cefSSai Prakash Ranjan }; 296924244cefSSai Prakash Ranjan }; 297024244cefSSai Prakash Ranjan }; 297124244cefSSai Prakash Ranjan }; 297224244cefSSai Prakash Ranjan 297324244cefSSai Prakash Ranjan etm@7040000 { 297424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 297524244cefSSai Prakash Ranjan reg = <0 0x07040000 0 0x1000>; 297624244cefSSai Prakash Ranjan 297724244cefSSai Prakash Ranjan cpu = <&CPU0>; 297824244cefSSai Prakash Ranjan 297924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 298024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 298124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 298224244cefSSai Prakash Ranjan qcom,skip-power-up; 298324244cefSSai Prakash Ranjan 298424244cefSSai Prakash Ranjan out-ports { 298524244cefSSai Prakash Ranjan port { 298624244cefSSai Prakash Ranjan etm0_out: endpoint { 298724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in0>; 298824244cefSSai Prakash Ranjan }; 298924244cefSSai Prakash Ranjan }; 299024244cefSSai Prakash Ranjan }; 299124244cefSSai Prakash Ranjan }; 299224244cefSSai Prakash Ranjan 299324244cefSSai Prakash Ranjan etm@7140000 { 299424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 299524244cefSSai Prakash Ranjan reg = <0 0x07140000 0 0x1000>; 299624244cefSSai Prakash Ranjan 299724244cefSSai Prakash Ranjan cpu = <&CPU1>; 299824244cefSSai Prakash Ranjan 299924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 300024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 300124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 300224244cefSSai Prakash Ranjan qcom,skip-power-up; 300324244cefSSai Prakash Ranjan 300424244cefSSai Prakash Ranjan out-ports { 300524244cefSSai Prakash Ranjan port { 300624244cefSSai Prakash Ranjan etm1_out: endpoint { 300724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in1>; 300824244cefSSai Prakash Ranjan }; 300924244cefSSai Prakash Ranjan }; 301024244cefSSai Prakash Ranjan }; 301124244cefSSai Prakash Ranjan }; 301224244cefSSai Prakash Ranjan 301324244cefSSai Prakash Ranjan etm@7240000 { 301424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 301524244cefSSai Prakash Ranjan reg = <0 0x07240000 0 0x1000>; 301624244cefSSai Prakash Ranjan 301724244cefSSai Prakash Ranjan cpu = <&CPU2>; 301824244cefSSai Prakash Ranjan 301924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 302024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 302124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 302224244cefSSai Prakash Ranjan qcom,skip-power-up; 302324244cefSSai Prakash Ranjan 302424244cefSSai Prakash Ranjan out-ports { 302524244cefSSai Prakash Ranjan port { 302624244cefSSai Prakash Ranjan etm2_out: endpoint { 302724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in2>; 302824244cefSSai Prakash Ranjan }; 302924244cefSSai Prakash Ranjan }; 303024244cefSSai Prakash Ranjan }; 303124244cefSSai Prakash Ranjan }; 303224244cefSSai Prakash Ranjan 303324244cefSSai Prakash Ranjan etm@7340000 { 303424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 303524244cefSSai Prakash Ranjan reg = <0 0x07340000 0 0x1000>; 303624244cefSSai Prakash Ranjan 303724244cefSSai Prakash Ranjan cpu = <&CPU3>; 303824244cefSSai Prakash Ranjan 303924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 304024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 304124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 304224244cefSSai Prakash Ranjan qcom,skip-power-up; 304324244cefSSai Prakash Ranjan 304424244cefSSai Prakash Ranjan out-ports { 304524244cefSSai Prakash Ranjan port { 304624244cefSSai Prakash Ranjan etm3_out: endpoint { 304724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in3>; 304824244cefSSai Prakash Ranjan }; 304924244cefSSai Prakash Ranjan }; 305024244cefSSai Prakash Ranjan }; 305124244cefSSai Prakash Ranjan }; 305224244cefSSai Prakash Ranjan 305324244cefSSai Prakash Ranjan etm@7440000 { 305424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 305524244cefSSai Prakash Ranjan reg = <0 0x07440000 0 0x1000>; 305624244cefSSai Prakash Ranjan 305724244cefSSai Prakash Ranjan cpu = <&CPU4>; 305824244cefSSai Prakash Ranjan 305924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 306024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 306124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 306224244cefSSai Prakash Ranjan qcom,skip-power-up; 306324244cefSSai Prakash Ranjan 306424244cefSSai Prakash Ranjan out-ports { 306524244cefSSai Prakash Ranjan port { 306624244cefSSai Prakash Ranjan etm4_out: endpoint { 306724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in4>; 306824244cefSSai Prakash Ranjan }; 306924244cefSSai Prakash Ranjan }; 307024244cefSSai Prakash Ranjan }; 307124244cefSSai Prakash Ranjan }; 307224244cefSSai Prakash Ranjan 307324244cefSSai Prakash Ranjan etm@7540000 { 307424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 307524244cefSSai Prakash Ranjan reg = <0 0x07540000 0 0x1000>; 307624244cefSSai Prakash Ranjan 307724244cefSSai Prakash Ranjan cpu = <&CPU5>; 307824244cefSSai Prakash Ranjan 307924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 308024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 308124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 308224244cefSSai Prakash Ranjan qcom,skip-power-up; 308324244cefSSai Prakash Ranjan 308424244cefSSai Prakash Ranjan out-ports { 308524244cefSSai Prakash Ranjan port { 308624244cefSSai Prakash Ranjan etm5_out: endpoint { 308724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in5>; 308824244cefSSai Prakash Ranjan }; 308924244cefSSai Prakash Ranjan }; 309024244cefSSai Prakash Ranjan }; 309124244cefSSai Prakash Ranjan }; 309224244cefSSai Prakash Ranjan 309324244cefSSai Prakash Ranjan etm@7640000 { 309424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 309524244cefSSai Prakash Ranjan reg = <0 0x07640000 0 0x1000>; 309624244cefSSai Prakash Ranjan 309724244cefSSai Prakash Ranjan cpu = <&CPU6>; 309824244cefSSai Prakash Ranjan 309924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 310024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 310124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 310224244cefSSai Prakash Ranjan qcom,skip-power-up; 310324244cefSSai Prakash Ranjan 310424244cefSSai Prakash Ranjan out-ports { 310524244cefSSai Prakash Ranjan port { 310624244cefSSai Prakash Ranjan etm6_out: endpoint { 310724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in6>; 310824244cefSSai Prakash Ranjan }; 310924244cefSSai Prakash Ranjan }; 311024244cefSSai Prakash Ranjan }; 311124244cefSSai Prakash Ranjan }; 311224244cefSSai Prakash Ranjan 311324244cefSSai Prakash Ranjan etm@7740000 { 311424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 311524244cefSSai Prakash Ranjan reg = <0 0x07740000 0 0x1000>; 311624244cefSSai Prakash Ranjan 311724244cefSSai Prakash Ranjan cpu = <&CPU7>; 311824244cefSSai Prakash Ranjan 311924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 312024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 312124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 312224244cefSSai Prakash Ranjan qcom,skip-power-up; 312324244cefSSai Prakash Ranjan 312424244cefSSai Prakash Ranjan out-ports { 312524244cefSSai Prakash Ranjan port { 312624244cefSSai Prakash Ranjan etm7_out: endpoint { 312724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in7>; 312824244cefSSai Prakash Ranjan }; 312924244cefSSai Prakash Ranjan }; 313024244cefSSai Prakash Ranjan }; 313124244cefSSai Prakash Ranjan }; 313224244cefSSai Prakash Ranjan 313324244cefSSai Prakash Ranjan funnel@7800000 { /* APSS Funnel */ 313424244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 313524244cefSSai Prakash Ranjan reg = <0 0x07800000 0 0x1000>; 313624244cefSSai Prakash Ranjan 313724244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 313824244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 313924244cefSSai Prakash Ranjan 314024244cefSSai Prakash Ranjan out-ports { 314124244cefSSai Prakash Ranjan port { 314224244cefSSai Prakash Ranjan apss_funnel_out: endpoint { 314324244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_in>; 314424244cefSSai Prakash Ranjan }; 314524244cefSSai Prakash Ranjan }; 314624244cefSSai Prakash Ranjan }; 314724244cefSSai Prakash Ranjan 314824244cefSSai Prakash Ranjan in-ports { 314924244cefSSai Prakash Ranjan #address-cells = <1>; 315024244cefSSai Prakash Ranjan #size-cells = <0>; 315124244cefSSai Prakash Ranjan 315224244cefSSai Prakash Ranjan port@0 { 315324244cefSSai Prakash Ranjan reg = <0>; 315424244cefSSai Prakash Ranjan apss_funnel_in0: endpoint { 315524244cefSSai Prakash Ranjan remote-endpoint = <&etm0_out>; 315624244cefSSai Prakash Ranjan }; 315724244cefSSai Prakash Ranjan }; 315824244cefSSai Prakash Ranjan 315924244cefSSai Prakash Ranjan port@1 { 316024244cefSSai Prakash Ranjan reg = <1>; 316124244cefSSai Prakash Ranjan apss_funnel_in1: endpoint { 316224244cefSSai Prakash Ranjan remote-endpoint = <&etm1_out>; 316324244cefSSai Prakash Ranjan }; 316424244cefSSai Prakash Ranjan }; 316524244cefSSai Prakash Ranjan 316624244cefSSai Prakash Ranjan port@2 { 316724244cefSSai Prakash Ranjan reg = <2>; 316824244cefSSai Prakash Ranjan apss_funnel_in2: endpoint { 316924244cefSSai Prakash Ranjan remote-endpoint = <&etm2_out>; 317024244cefSSai Prakash Ranjan }; 317124244cefSSai Prakash Ranjan }; 317224244cefSSai Prakash Ranjan 317324244cefSSai Prakash Ranjan port@3 { 317424244cefSSai Prakash Ranjan reg = <3>; 317524244cefSSai Prakash Ranjan apss_funnel_in3: endpoint { 317624244cefSSai Prakash Ranjan remote-endpoint = <&etm3_out>; 317724244cefSSai Prakash Ranjan }; 317824244cefSSai Prakash Ranjan }; 317924244cefSSai Prakash Ranjan 318024244cefSSai Prakash Ranjan port@4 { 318124244cefSSai Prakash Ranjan reg = <4>; 318224244cefSSai Prakash Ranjan apss_funnel_in4: endpoint { 318324244cefSSai Prakash Ranjan remote-endpoint = <&etm4_out>; 318424244cefSSai Prakash Ranjan }; 318524244cefSSai Prakash Ranjan }; 318624244cefSSai Prakash Ranjan 318724244cefSSai Prakash Ranjan port@5 { 318824244cefSSai Prakash Ranjan reg = <5>; 318924244cefSSai Prakash Ranjan apss_funnel_in5: endpoint { 319024244cefSSai Prakash Ranjan remote-endpoint = <&etm5_out>; 319124244cefSSai Prakash Ranjan }; 319224244cefSSai Prakash Ranjan }; 319324244cefSSai Prakash Ranjan 319424244cefSSai Prakash Ranjan port@6 { 319524244cefSSai Prakash Ranjan reg = <6>; 319624244cefSSai Prakash Ranjan apss_funnel_in6: endpoint { 319724244cefSSai Prakash Ranjan remote-endpoint = <&etm6_out>; 319824244cefSSai Prakash Ranjan }; 319924244cefSSai Prakash Ranjan }; 320024244cefSSai Prakash Ranjan 320124244cefSSai Prakash Ranjan port@7 { 320224244cefSSai Prakash Ranjan reg = <7>; 320324244cefSSai Prakash Ranjan apss_funnel_in7: endpoint { 320424244cefSSai Prakash Ranjan remote-endpoint = <&etm7_out>; 320524244cefSSai Prakash Ranjan }; 320624244cefSSai Prakash Ranjan }; 320724244cefSSai Prakash Ranjan }; 320824244cefSSai Prakash Ranjan }; 320924244cefSSai Prakash Ranjan 321024244cefSSai Prakash Ranjan funnel@7810000 { 321124244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 321224244cefSSai Prakash Ranjan reg = <0 0x07810000 0 0x1000>; 321324244cefSSai Prakash Ranjan 321424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 321524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 321624244cefSSai Prakash Ranjan 321724244cefSSai Prakash Ranjan out-ports { 321824244cefSSai Prakash Ranjan port { 321924244cefSSai Prakash Ranjan apss_merge_funnel_out: endpoint { 322024244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_in2>; 322124244cefSSai Prakash Ranjan }; 322224244cefSSai Prakash Ranjan }; 322324244cefSSai Prakash Ranjan }; 322424244cefSSai Prakash Ranjan 322524244cefSSai Prakash Ranjan in-ports { 322624244cefSSai Prakash Ranjan port { 322724244cefSSai Prakash Ranjan apss_merge_funnel_in: endpoint { 322824244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_out>; 322924244cefSSai Prakash Ranjan }; 323024244cefSSai Prakash Ranjan }; 323124244cefSSai Prakash Ranjan }; 323224244cefSSai Prakash Ranjan }; 323324244cefSSai Prakash Ranjan 323449076351SSibi Sankar remoteproc_cdsp: remoteproc@8300000 { 323549076351SSibi Sankar compatible = "qcom,sm8150-cdsp-pas"; 323649076351SSibi Sankar reg = <0x0 0x08300000 0x0 0x4040>; 323749076351SSibi Sankar 323849076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 323949076351SSibi Sankar <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 324049076351SSibi Sankar <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 324149076351SSibi Sankar <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 324249076351SSibi Sankar <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 324349076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 324449076351SSibi Sankar "handover", "stop-ack"; 324549076351SSibi Sankar 324649076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 324749076351SSibi Sankar clock-names = "xo"; 324849076351SSibi Sankar 3249d9d327f6SSibi Sankar power-domains = <&rpmhpd 7>; 325049076351SSibi Sankar 325149076351SSibi Sankar memory-region = <&cdsp_mem>; 325249076351SSibi Sankar 3253d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 3254d9d327f6SSibi Sankar 325549076351SSibi Sankar qcom,smem-states = <&cdsp_smp2p_out 0>; 325649076351SSibi Sankar qcom,smem-state-names = "stop"; 325749076351SSibi Sankar 325849076351SSibi Sankar status = "disabled"; 325949076351SSibi Sankar 326049076351SSibi Sankar glink-edge { 326149076351SSibi Sankar interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 326249076351SSibi Sankar label = "cdsp"; 326349076351SSibi Sankar qcom,remote-pid = <5>; 326449076351SSibi Sankar mboxes = <&apss_shared 4>; 326581729330SBhupesh Sharma 326681729330SBhupesh Sharma fastrpc { 326781729330SBhupesh Sharma compatible = "qcom,fastrpc"; 326881729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 326981729330SBhupesh Sharma label = "cdsp"; 32708c8ce95bSJeya R qcom,non-secure-domain; 327181729330SBhupesh Sharma #address-cells = <1>; 327281729330SBhupesh Sharma #size-cells = <0>; 327381729330SBhupesh Sharma 327481729330SBhupesh Sharma compute-cb@1 { 327581729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 327681729330SBhupesh Sharma reg = <1>; 32771d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1001 0x0460>; 327881729330SBhupesh Sharma }; 327981729330SBhupesh Sharma 328081729330SBhupesh Sharma compute-cb@2 { 328181729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 328281729330SBhupesh Sharma reg = <2>; 32831d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1002 0x0460>; 328481729330SBhupesh Sharma }; 328581729330SBhupesh Sharma 328681729330SBhupesh Sharma compute-cb@3 { 328781729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 328881729330SBhupesh Sharma reg = <3>; 32891d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1003 0x0460>; 329081729330SBhupesh Sharma }; 329181729330SBhupesh Sharma 329281729330SBhupesh Sharma compute-cb@4 { 329381729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 329481729330SBhupesh Sharma reg = <4>; 32951d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1004 0x0460>; 329681729330SBhupesh Sharma }; 329781729330SBhupesh Sharma 329881729330SBhupesh Sharma compute-cb@5 { 329981729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 330081729330SBhupesh Sharma reg = <5>; 33011d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1005 0x0460>; 330281729330SBhupesh Sharma }; 330381729330SBhupesh Sharma 330481729330SBhupesh Sharma compute-cb@6 { 330581729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 330681729330SBhupesh Sharma reg = <6>; 33071d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1006 0x0460>; 330881729330SBhupesh Sharma }; 330981729330SBhupesh Sharma 331081729330SBhupesh Sharma compute-cb@7 { 331181729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 331281729330SBhupesh Sharma reg = <7>; 33131d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1007 0x0460>; 331481729330SBhupesh Sharma }; 331581729330SBhupesh Sharma 331681729330SBhupesh Sharma compute-cb@8 { 331781729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 331881729330SBhupesh Sharma reg = <8>; 33191d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1008 0x0460>; 332081729330SBhupesh Sharma }; 332181729330SBhupesh Sharma 332281729330SBhupesh Sharma /* note: secure cb9 in downstream */ 332381729330SBhupesh Sharma }; 332449076351SSibi Sankar }; 332549076351SSibi Sankar }; 332649076351SSibi Sankar 3327b33d2868SJack Pham usb_1_hsphy: phy@88e2000 { 3328b33d2868SJack Pham compatible = "qcom,sm8150-usb-hs-phy", 3329b33d2868SJack Pham "qcom,usb-snps-hs-7nm-phy"; 3330b33d2868SJack Pham reg = <0 0x088e2000 0 0x400>; 3331b33d2868SJack Pham status = "disabled"; 3332b33d2868SJack Pham #phy-cells = <0>; 3333b33d2868SJack Pham 3334b33d2868SJack Pham clocks = <&rpmhcc RPMH_CXO_CLK>; 3335b33d2868SJack Pham clock-names = "ref"; 3336b33d2868SJack Pham 3337b33d2868SJack Pham resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3338b33d2868SJack Pham }; 3339b33d2868SJack Pham 33400c9dde0dSJonathan Marek usb_2_hsphy: phy@88e3000 { 33410c9dde0dSJonathan Marek compatible = "qcom,sm8150-usb-hs-phy", 33420c9dde0dSJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 33430c9dde0dSJonathan Marek reg = <0 0x088e3000 0 0x400>; 33440c9dde0dSJonathan Marek status = "disabled"; 33450c9dde0dSJonathan Marek #phy-cells = <0>; 33460c9dde0dSJonathan Marek 33470c9dde0dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 33480c9dde0dSJonathan Marek clock-names = "ref"; 33490c9dde0dSJonathan Marek 33500c9dde0dSJonathan Marek resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 33510c9dde0dSJonathan Marek }; 33520c9dde0dSJonathan Marek 3353b33d2868SJack Pham usb_1_qmpphy: phy@88e9000 { 3354b33d2868SJack Pham compatible = "qcom,sm8150-qmp-usb3-phy"; 3355b33d2868SJack Pham reg = <0 0x088e9000 0 0x18c>, 3356b33d2868SJack Pham <0 0x088e8000 0 0x10>; 3357b33d2868SJack Pham status = "disabled"; 3358b33d2868SJack Pham #address-cells = <2>; 3359b33d2868SJack Pham #size-cells = <2>; 3360b33d2868SJack Pham ranges; 3361b33d2868SJack Pham 3362b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3363b33d2868SJack Pham <&rpmhcc RPMH_CXO_CLK>, 3364b33d2868SJack Pham <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3365b33d2868SJack Pham <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3366b33d2868SJack Pham clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3367b33d2868SJack Pham 3368b33d2868SJack Pham resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3369b33d2868SJack Pham <&gcc GCC_USB3_PHY_PRIM_BCR>; 3370b33d2868SJack Pham reset-names = "phy", "common"; 3371b33d2868SJack Pham 33721351512fSShawn Guo usb_1_ssphy: phy@88e9200 { 3373b33d2868SJack Pham reg = <0 0x088e9200 0 0x200>, 3374b33d2868SJack Pham <0 0x088e9400 0 0x200>, 3375b33d2868SJack Pham <0 0x088e9c00 0 0x218>, 3376b33d2868SJack Pham <0 0x088e9600 0 0x200>, 3377b33d2868SJack Pham <0 0x088e9800 0 0x200>, 3378b33d2868SJack Pham <0 0x088e9a00 0 0x100>; 33797178d4ccSJonathan Marek #clock-cells = <0>; 3380b33d2868SJack Pham #phy-cells = <0>; 3381b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3382b33d2868SJack Pham clock-names = "pipe0"; 3383b33d2868SJack Pham clock-output-names = "usb3_phy_pipe_clk_src"; 3384b33d2868SJack Pham }; 3385b33d2868SJack Pham }; 3386b33d2868SJack Pham 33870c9dde0dSJonathan Marek usb_2_qmpphy: phy@88eb000 { 33880c9dde0dSJonathan Marek compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 33890c9dde0dSJonathan Marek reg = <0 0x088eb000 0 0x200>; 33900c9dde0dSJonathan Marek status = "disabled"; 33910c9dde0dSJonathan Marek #address-cells = <2>; 33920c9dde0dSJonathan Marek #size-cells = <2>; 33930c9dde0dSJonathan Marek ranges; 33940c9dde0dSJonathan Marek 33950c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 33960c9dde0dSJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 33970c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>, 33980c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 33990c9dde0dSJonathan Marek clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 34000c9dde0dSJonathan Marek 34010c9dde0dSJonathan Marek resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 34020c9dde0dSJonathan Marek <&gcc GCC_USB3_PHY_SEC_BCR>; 34030c9dde0dSJonathan Marek reset-names = "phy", "common"; 34040c9dde0dSJonathan Marek 34051351512fSShawn Guo usb_2_ssphy: phy@88eb200 { 34060c9dde0dSJonathan Marek reg = <0 0x088eb200 0 0x200>, 34070c9dde0dSJonathan Marek <0 0x088eb400 0 0x200>, 34080c9dde0dSJonathan Marek <0 0x088eb800 0 0x800>, 34090c9dde0dSJonathan Marek <0 0x088eb600 0 0x200>; 34107178d4ccSJonathan Marek #clock-cells = <0>; 34110c9dde0dSJonathan Marek #phy-cells = <0>; 34120c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 34130c9dde0dSJonathan Marek clock-names = "pipe0"; 34140c9dde0dSJonathan Marek clock-output-names = "usb3_uni_phy_pipe_clk_src"; 34150c9dde0dSJonathan Marek }; 34160c9dde0dSJonathan Marek }; 34170c9dde0dSJonathan Marek 341896bb736fSBhupesh Sharma sdhc_2: mmc@8804000 { 3419876644c7SBhupesh Sharma compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3420876644c7SBhupesh Sharma reg = <0 0x08804000 0 0x1000>; 3421876644c7SBhupesh Sharma 3422876644c7SBhupesh Sharma interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3423876644c7SBhupesh Sharma <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3424876644c7SBhupesh Sharma interrupt-names = "hc_irq", "pwr_irq"; 3425876644c7SBhupesh Sharma 3426876644c7SBhupesh Sharma clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3427876644c7SBhupesh Sharma <&gcc GCC_SDCC2_APPS_CLK>, 3428876644c7SBhupesh Sharma <&rpmhcc RPMH_CXO_CLK>; 3429876644c7SBhupesh Sharma clock-names = "iface", "core", "xo"; 343095830090SBhupesh Sharma iommus = <&apps_smmu 0x6a0 0x0>; 3431876644c7SBhupesh Sharma qcom,dll-config = <0x0007642c>; 3432876644c7SBhupesh Sharma qcom,ddr-config = <0x80040868>; 3433876644c7SBhupesh Sharma power-domains = <&rpmhpd 0>; 3434876644c7SBhupesh Sharma operating-points-v2 = <&sdhc2_opp_table>; 3435876644c7SBhupesh Sharma 3436876644c7SBhupesh Sharma status = "disabled"; 3437876644c7SBhupesh Sharma 34380e3e6546SKrzysztof Kozlowski sdhc2_opp_table: opp-table { 3439876644c7SBhupesh Sharma compatible = "operating-points-v2"; 3440876644c7SBhupesh Sharma 3441876644c7SBhupesh Sharma opp-19200000 { 3442876644c7SBhupesh Sharma opp-hz = /bits/ 64 <19200000>; 3443876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_min_svs>; 3444876644c7SBhupesh Sharma }; 3445876644c7SBhupesh Sharma 3446876644c7SBhupesh Sharma opp-50000000 { 3447876644c7SBhupesh Sharma opp-hz = /bits/ 64 <50000000>; 3448876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_low_svs>; 3449876644c7SBhupesh Sharma }; 3450876644c7SBhupesh Sharma 3451876644c7SBhupesh Sharma opp-100000000 { 3452876644c7SBhupesh Sharma opp-hz = /bits/ 64 <100000000>; 3453876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_svs>; 3454876644c7SBhupesh Sharma }; 3455876644c7SBhupesh Sharma 3456876644c7SBhupesh Sharma opp-202000000 { 3457876644c7SBhupesh Sharma opp-hz = /bits/ 64 <202000000>; 3458876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_svs_l1>; 3459876644c7SBhupesh Sharma }; 3460876644c7SBhupesh Sharma }; 3461876644c7SBhupesh Sharma }; 3462876644c7SBhupesh Sharma 34635dc43d3bSBhupesh Sharma dc_noc: interconnect@9160000 { 34645dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-dc-noc"; 34655dc43d3bSBhupesh Sharma reg = <0 0x09160000 0 0x3200>; 34665dc43d3bSBhupesh Sharma #interconnect-cells = <1>; 34675dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 34685dc43d3bSBhupesh Sharma }; 34695dc43d3bSBhupesh Sharma 34705dc43d3bSBhupesh Sharma gem_noc: interconnect@9680000 { 34715dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-gem-noc"; 34725dc43d3bSBhupesh Sharma reg = <0 0x09680000 0 0x3e200>; 34735dc43d3bSBhupesh Sharma #interconnect-cells = <1>; 34745dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 34755dc43d3bSBhupesh Sharma }; 34765dc43d3bSBhupesh Sharma 3477b33d2868SJack Pham usb_1: usb@a6f8800 { 3478b33d2868SJack Pham compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3479b33d2868SJack Pham reg = <0 0x0a6f8800 0 0x400>; 3480b33d2868SJack Pham status = "disabled"; 3481b33d2868SJack Pham #address-cells = <2>; 3482b33d2868SJack Pham #size-cells = <2>; 3483b33d2868SJack Pham ranges; 3484b33d2868SJack Pham dma-ranges; 3485b33d2868SJack Pham 3486b33d2868SJack Pham clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3487b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3488b33d2868SJack Pham <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3489b33d2868SJack Pham <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 34908d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3491b33d2868SJack Pham <&gcc GCC_USB3_SEC_CLKREF_CLK>; 34928d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 34938d5fd4e4SKrzysztof Kozlowski "core", 34948d5fd4e4SKrzysztof Kozlowski "iface", 34958d5fd4e4SKrzysztof Kozlowski "sleep", 34968d5fd4e4SKrzysztof Kozlowski "mock_utmi", 34978d5fd4e4SKrzysztof Kozlowski "xo"; 3498b33d2868SJack Pham 3499b33d2868SJack Pham assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3500b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>; 350179493db5SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 3502b33d2868SJack Pham 3503b33d2868SJack Pham interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3504b33d2868SJack Pham <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3505b33d2868SJack Pham <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3506b33d2868SJack Pham <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3507b33d2868SJack Pham interrupt-names = "hs_phy_irq", "ss_phy_irq", 3508b33d2868SJack Pham "dm_hs_phy_irq", "dp_hs_phy_irq"; 3509b33d2868SJack Pham 3510b33d2868SJack Pham power-domains = <&gcc USB30_PRIM_GDSC>; 3511b33d2868SJack Pham 3512b33d2868SJack Pham resets = <&gcc GCC_USB30_PRIM_BCR>; 3513b33d2868SJack Pham 3514b77a1c4dSKrzysztof Kozlowski usb_1_dwc3: usb@a600000 { 3515b33d2868SJack Pham compatible = "snps,dwc3"; 3516b33d2868SJack Pham reg = <0 0x0a600000 0 0xcd00>; 3517b33d2868SJack Pham interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 351848156232SJonathan Marek iommus = <&apps_smmu 0x140 0>; 3519b33d2868SJack Pham snps,dis_u2_susphy_quirk; 3520b33d2868SJack Pham snps,dis_enblslpm_quirk; 3521b33d2868SJack Pham phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3522b33d2868SJack Pham phy-names = "usb2-phy", "usb3-phy"; 3523b33d2868SJack Pham }; 3524b33d2868SJack Pham }; 3525b33d2868SJack Pham 35260c9dde0dSJonathan Marek usb_2: usb@a8f8800 { 35270c9dde0dSJonathan Marek compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 35280c9dde0dSJonathan Marek reg = <0 0x0a8f8800 0 0x400>; 35290c9dde0dSJonathan Marek status = "disabled"; 35300c9dde0dSJonathan Marek #address-cells = <2>; 35310c9dde0dSJonathan Marek #size-cells = <2>; 35320c9dde0dSJonathan Marek ranges; 35330c9dde0dSJonathan Marek dma-ranges; 35340c9dde0dSJonathan Marek 35350c9dde0dSJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 35360c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>, 35370c9dde0dSJonathan Marek <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 35380c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_SLEEP_CLK>, 35398d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 35400c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>; 35418d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 35428d5fd4e4SKrzysztof Kozlowski "core", 35438d5fd4e4SKrzysztof Kozlowski "iface", 35448d5fd4e4SKrzysztof Kozlowski "sleep", 35458d5fd4e4SKrzysztof Kozlowski "mock_utmi", 35468d5fd4e4SKrzysztof Kozlowski "xo"; 35470c9dde0dSJonathan Marek 35480c9dde0dSJonathan Marek assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 35490c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>; 35500c9dde0dSJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 35510c9dde0dSJonathan Marek 35520c9dde0dSJonathan Marek interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 35530c9dde0dSJonathan Marek <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 35540c9dde0dSJonathan Marek <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 35550c9dde0dSJonathan Marek <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 35560c9dde0dSJonathan Marek interrupt-names = "hs_phy_irq", "ss_phy_irq", 35570c9dde0dSJonathan Marek "dm_hs_phy_irq", "dp_hs_phy_irq"; 35580c9dde0dSJonathan Marek 35590c9dde0dSJonathan Marek power-domains = <&gcc USB30_SEC_GDSC>; 35600c9dde0dSJonathan Marek 35610c9dde0dSJonathan Marek resets = <&gcc GCC_USB30_SEC_BCR>; 35620c9dde0dSJonathan Marek 35632aa2b50dSBhupesh Sharma usb_2_dwc3: usb@a800000 { 35640c9dde0dSJonathan Marek compatible = "snps,dwc3"; 35650c9dde0dSJonathan Marek reg = <0 0x0a800000 0 0xcd00>; 35660c9dde0dSJonathan Marek interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 35670c9dde0dSJonathan Marek iommus = <&apps_smmu 0x160 0>; 35680c9dde0dSJonathan Marek snps,dis_u2_susphy_quirk; 35690c9dde0dSJonathan Marek snps,dis_enblslpm_quirk; 35700c9dde0dSJonathan Marek phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 35710c9dde0dSJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 35720c9dde0dSJonathan Marek }; 35730c9dde0dSJonathan Marek }; 35740c9dde0dSJonathan Marek 35756acb71fdSJonathan Marek camnoc_virt: interconnect@ac00000 { 35766acb71fdSJonathan Marek compatible = "qcom,sm8150-camnoc-virt"; 35776acb71fdSJonathan Marek reg = <0 0x0ac00000 0 0x1000>; 35786acb71fdSJonathan Marek #interconnect-cells = <1>; 35796acb71fdSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 35806acb71fdSJonathan Marek }; 35816acb71fdSJonathan Marek 3582397ad946SBhupesh Sharma pdc: interrupt-controller@b220000 { 3583397ad946SBhupesh Sharma compatible = "qcom,sm8150-pdc", "qcom,pdc"; 3584397ad946SBhupesh Sharma reg = <0 0x0b220000 0 0x400>; 3585397ad946SBhupesh Sharma qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3586397ad946SBhupesh Sharma <125 63 1>; 3587397ad946SBhupesh Sharma #interrupt-cells = <2>; 3588397ad946SBhupesh Sharma interrupt-parent = <&intc>; 3589397ad946SBhupesh Sharma interrupt-controller; 3590397ad946SBhupesh Sharma }; 3591397ad946SBhupesh Sharma 3592d8cf9372SVinod Koul aoss_qmp: power-controller@c300000 { 35936ba93ba9SKrzysztof Kozlowski compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 359447cb6a06SMaulik Shah reg = <0x0 0x0c300000 0x0 0x400>; 3595d8cf9372SVinod Koul interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3596d8cf9372SVinod Koul mboxes = <&apss_shared 0>; 3597d8cf9372SVinod Koul 3598d8cf9372SVinod Koul #clock-cells = <0>; 3599d8cf9372SVinod Koul }; 3600d8cf9372SVinod Koul 360147cb6a06SMaulik Shah sram@c3f0000 { 360247cb6a06SMaulik Shah compatible = "qcom,rpmh-stats"; 360347cb6a06SMaulik Shah reg = <0 0x0c3f0000 0 0x400>; 360447cb6a06SMaulik Shah }; 360547cb6a06SMaulik Shah 3606d2fa630cSAmit Kucheria tsens0: thermal-sensor@c263000 { 3607d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3608d2fa630cSAmit Kucheria reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3609d2fa630cSAmit Kucheria <0 0x0c222000 0 0x1ff>; /* SROT */ 3610d2fa630cSAmit Kucheria #qcom,sensors = <16>; 3611d2fa630cSAmit Kucheria interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3612d2fa630cSAmit Kucheria <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3613d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 3614d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 3615d2fa630cSAmit Kucheria }; 3616d2fa630cSAmit Kucheria 3617d2fa630cSAmit Kucheria tsens1: thermal-sensor@c265000 { 3618d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3619d2fa630cSAmit Kucheria reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3620d2fa630cSAmit Kucheria <0 0x0c223000 0 0x1ff>; /* SROT */ 3621d2fa630cSAmit Kucheria #qcom,sensors = <8>; 3622d2fa630cSAmit Kucheria interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3623d2fa630cSAmit Kucheria <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3624d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 3625d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 3626d2fa630cSAmit Kucheria }; 3627d2fa630cSAmit Kucheria 3628e13c6d14SVinod Koul spmi_bus: spmi@c440000 { 3629e13c6d14SVinod Koul compatible = "qcom,spmi-pmic-arb"; 3630e13c6d14SVinod Koul reg = <0x0 0x0c440000 0x0 0x0001100>, 3631e13c6d14SVinod Koul <0x0 0x0c600000 0x0 0x2000000>, 3632e13c6d14SVinod Koul <0x0 0x0e600000 0x0 0x0100000>, 3633e13c6d14SVinod Koul <0x0 0x0e700000 0x0 0x00a0000>, 3634e13c6d14SVinod Koul <0x0 0x0c40a000 0x0 0x0026000>; 3635e13c6d14SVinod Koul reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3636e13c6d14SVinod Koul interrupt-names = "periph_irq"; 3637e13c6d14SVinod Koul interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3638e13c6d14SVinod Koul qcom,ee = <0>; 3639e13c6d14SVinod Koul qcom,channel = <0>; 3640e13c6d14SVinod Koul #address-cells = <2>; 3641e13c6d14SVinod Koul #size-cells = <0>; 3642e13c6d14SVinod Koul interrupt-controller; 3643e13c6d14SVinod Koul #interrupt-cells = <4>; 3644e13c6d14SVinod Koul cell-index = <0>; 3645e13c6d14SVinod Koul }; 3646e13c6d14SVinod Koul 364748156232SJonathan Marek apps_smmu: iommu@15000000 { 364848156232SJonathan Marek compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 364948156232SJonathan Marek reg = <0 0x15000000 0 0x100000>; 365048156232SJonathan Marek #iommu-cells = <2>; 365148156232SJonathan Marek #global-interrupts = <1>; 365248156232SJonathan Marek interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 365348156232SJonathan Marek <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 365448156232SJonathan Marek <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 365548156232SJonathan Marek <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 365648156232SJonathan Marek <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 365748156232SJonathan Marek <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 365848156232SJonathan Marek <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 365948156232SJonathan Marek <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 366048156232SJonathan Marek <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 366148156232SJonathan Marek <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 366248156232SJonathan Marek <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 366348156232SJonathan Marek <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 366448156232SJonathan Marek <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 366548156232SJonathan Marek <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 366648156232SJonathan Marek <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 366748156232SJonathan Marek <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 366848156232SJonathan Marek <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 366948156232SJonathan Marek <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 367048156232SJonathan Marek <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 367148156232SJonathan Marek <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 367248156232SJonathan Marek <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 367348156232SJonathan Marek <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 367448156232SJonathan Marek <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 367548156232SJonathan Marek <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 367648156232SJonathan Marek <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 367748156232SJonathan Marek <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 367848156232SJonathan Marek <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 367948156232SJonathan Marek <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 368048156232SJonathan Marek <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 368148156232SJonathan Marek <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 368248156232SJonathan Marek <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 368348156232SJonathan Marek <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 368448156232SJonathan Marek <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 368548156232SJonathan Marek <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 368648156232SJonathan Marek <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 368748156232SJonathan Marek <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 368848156232SJonathan Marek <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 368948156232SJonathan Marek <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 369048156232SJonathan Marek <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 369148156232SJonathan Marek <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 369248156232SJonathan Marek <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 369348156232SJonathan Marek <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 369448156232SJonathan Marek <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 369548156232SJonathan Marek <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 369648156232SJonathan Marek <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 369748156232SJonathan Marek <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 369848156232SJonathan Marek <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 369948156232SJonathan Marek <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 370048156232SJonathan Marek <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 370148156232SJonathan Marek <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 370248156232SJonathan Marek <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 370348156232SJonathan Marek <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 370448156232SJonathan Marek <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 370548156232SJonathan Marek <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 370648156232SJonathan Marek <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 370748156232SJonathan Marek <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 370848156232SJonathan Marek <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 370948156232SJonathan Marek <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 371048156232SJonathan Marek <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 371148156232SJonathan Marek <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 371248156232SJonathan Marek <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 371348156232SJonathan Marek <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 371448156232SJonathan Marek <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 371548156232SJonathan Marek <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 371648156232SJonathan Marek <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 371748156232SJonathan Marek <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 371848156232SJonathan Marek <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 371948156232SJonathan Marek <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 372048156232SJonathan Marek <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 372148156232SJonathan Marek <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 372248156232SJonathan Marek <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 372348156232SJonathan Marek <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 372448156232SJonathan Marek <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 372548156232SJonathan Marek <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 372648156232SJonathan Marek <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 372748156232SJonathan Marek <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 372848156232SJonathan Marek <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 372948156232SJonathan Marek <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 373048156232SJonathan Marek <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 373148156232SJonathan Marek <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 373248156232SJonathan Marek <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 373348156232SJonathan Marek }; 373448156232SJonathan Marek 373549076351SSibi Sankar remoteproc_adsp: remoteproc@17300000 { 373649076351SSibi Sankar compatible = "qcom,sm8150-adsp-pas"; 373749076351SSibi Sankar reg = <0x0 0x17300000 0x0 0x4040>; 373849076351SSibi Sankar 373949076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 374049076351SSibi Sankar <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 374149076351SSibi Sankar <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 374249076351SSibi Sankar <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 374349076351SSibi Sankar <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 374449076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 374549076351SSibi Sankar "handover", "stop-ack"; 374649076351SSibi Sankar 374749076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 374849076351SSibi Sankar clock-names = "xo"; 374949076351SSibi Sankar 3750d9d327f6SSibi Sankar power-domains = <&rpmhpd 7>; 375149076351SSibi Sankar 375249076351SSibi Sankar memory-region = <&adsp_mem>; 375349076351SSibi Sankar 3754d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 3755d9d327f6SSibi Sankar 375649076351SSibi Sankar qcom,smem-states = <&adsp_smp2p_out 0>; 375749076351SSibi Sankar qcom,smem-state-names = "stop"; 375849076351SSibi Sankar 375949076351SSibi Sankar status = "disabled"; 376049076351SSibi Sankar 376149076351SSibi Sankar glink-edge { 376249076351SSibi Sankar interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 376349076351SSibi Sankar label = "lpass"; 376449076351SSibi Sankar qcom,remote-pid = <2>; 376549076351SSibi Sankar mboxes = <&apss_shared 8>; 376681729330SBhupesh Sharma 376781729330SBhupesh Sharma fastrpc { 376881729330SBhupesh Sharma compatible = "qcom,fastrpc"; 376981729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 377081729330SBhupesh Sharma label = "adsp"; 37718c8ce95bSJeya R qcom,non-secure-domain; 377281729330SBhupesh Sharma #address-cells = <1>; 377381729330SBhupesh Sharma #size-cells = <0>; 377481729330SBhupesh Sharma 377581729330SBhupesh Sharma compute-cb@3 { 377681729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 377781729330SBhupesh Sharma reg = <3>; 377881729330SBhupesh Sharma iommus = <&apps_smmu 0x1b23 0x0>; 377981729330SBhupesh Sharma }; 378081729330SBhupesh Sharma 378181729330SBhupesh Sharma compute-cb@4 { 378281729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 378381729330SBhupesh Sharma reg = <4>; 378481729330SBhupesh Sharma iommus = <&apps_smmu 0x1b24 0x0>; 378581729330SBhupesh Sharma }; 378681729330SBhupesh Sharma 378781729330SBhupesh Sharma compute-cb@5 { 378881729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 378981729330SBhupesh Sharma reg = <5>; 379081729330SBhupesh Sharma iommus = <&apps_smmu 0x1b25 0x0>; 379181729330SBhupesh Sharma }; 379281729330SBhupesh Sharma }; 379349076351SSibi Sankar }; 379449076351SSibi Sankar }; 379549076351SSibi Sankar 3796e13c6d14SVinod Koul intc: interrupt-controller@17a00000 { 3797e13c6d14SVinod Koul compatible = "arm,gic-v3"; 3798e13c6d14SVinod Koul interrupt-controller; 3799e13c6d14SVinod Koul #interrupt-cells = <3>; 3800e13c6d14SVinod Koul reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3801e13c6d14SVinod Koul <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3802e13c6d14SVinod Koul interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3803e13c6d14SVinod Koul }; 3804e13c6d14SVinod Koul 3805d8cf9372SVinod Koul apss_shared: mailbox@17c00000 { 3806d8cf9372SVinod Koul compatible = "qcom,sm8150-apss-shared"; 3807d8cf9372SVinod Koul reg = <0x0 0x17c00000 0x0 0x1000>; 3808d8cf9372SVinod Koul #mbox-cells = <1>; 3809d8cf9372SVinod Koul }; 3810d8cf9372SVinod Koul 3811fb2d8150SSai Prakash Ranjan watchdog@17c10000 { 3812fb2d8150SSai Prakash Ranjan compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 3813fb2d8150SSai Prakash Ranjan reg = <0 0x17c10000 0 0x1000>; 3814fb2d8150SSai Prakash Ranjan clocks = <&sleep_clk>; 3815b094c8f8SSai Prakash Ranjan interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3816fb2d8150SSai Prakash Ranjan }; 3817fb2d8150SSai Prakash Ranjan 3818e13c6d14SVinod Koul timer@17c20000 { 3819458ebdbbSDavid Heidelberg #address-cells = <1>; 3820458ebdbbSDavid Heidelberg #size-cells = <1>; 3821458ebdbbSDavid Heidelberg ranges = <0 0 0 0x20000000>; 3822e13c6d14SVinod Koul compatible = "arm,armv7-timer-mem"; 3823e13c6d14SVinod Koul reg = <0x0 0x17c20000 0x0 0x1000>; 3824e13c6d14SVinod Koul clock-frequency = <19200000>; 3825e13c6d14SVinod Koul 3826e13c6d14SVinod Koul frame@17c21000{ 3827e13c6d14SVinod Koul frame-number = <0>; 3828e13c6d14SVinod Koul interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3829e13c6d14SVinod Koul <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3830458ebdbbSDavid Heidelberg reg = <0x17c21000 0x1000>, 3831458ebdbbSDavid Heidelberg <0x17c22000 0x1000>; 3832e13c6d14SVinod Koul }; 3833e13c6d14SVinod Koul 3834e13c6d14SVinod Koul frame@17c23000 { 3835e13c6d14SVinod Koul frame-number = <1>; 3836e13c6d14SVinod Koul interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3837458ebdbbSDavid Heidelberg reg = <0x17c23000 0x1000>; 3838e13c6d14SVinod Koul status = "disabled"; 3839e13c6d14SVinod Koul }; 3840e13c6d14SVinod Koul 3841e13c6d14SVinod Koul frame@17c25000 { 3842e13c6d14SVinod Koul frame-number = <2>; 3843e13c6d14SVinod Koul interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3844458ebdbbSDavid Heidelberg reg = <0x17c25000 0x1000>; 3845e13c6d14SVinod Koul status = "disabled"; 3846e13c6d14SVinod Koul }; 3847e13c6d14SVinod Koul 3848e13c6d14SVinod Koul frame@17c27000 { 3849e13c6d14SVinod Koul frame-number = <3>; 3850e13c6d14SVinod Koul interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3851458ebdbbSDavid Heidelberg reg = <0x17c26000 0x1000>; 3852e13c6d14SVinod Koul status = "disabled"; 3853e13c6d14SVinod Koul }; 3854e13c6d14SVinod Koul 3855e13c6d14SVinod Koul frame@17c29000 { 3856e13c6d14SVinod Koul frame-number = <4>; 3857e13c6d14SVinod Koul interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3858458ebdbbSDavid Heidelberg reg = <0x17c29000 0x1000>; 3859e13c6d14SVinod Koul status = "disabled"; 3860e13c6d14SVinod Koul }; 3861e13c6d14SVinod Koul 3862e13c6d14SVinod Koul frame@17c2b000 { 3863e13c6d14SVinod Koul frame-number = <5>; 3864e13c6d14SVinod Koul interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3865458ebdbbSDavid Heidelberg reg = <0x17c2b000 0x1000>; 3866e13c6d14SVinod Koul status = "disabled"; 3867e13c6d14SVinod Koul }; 3868e13c6d14SVinod Koul 3869e13c6d14SVinod Koul frame@17c2d000 { 3870e13c6d14SVinod Koul frame-number = <6>; 3871e13c6d14SVinod Koul interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3872458ebdbbSDavid Heidelberg reg = <0x17c2d000 0x1000>; 3873e13c6d14SVinod Koul status = "disabled"; 3874e13c6d14SVinod Koul }; 3875e13c6d14SVinod Koul }; 3876d8cf9372SVinod Koul 3877d8cf9372SVinod Koul apps_rsc: rsc@18200000 { 3878d8cf9372SVinod Koul label = "apps_rsc"; 3879d8cf9372SVinod Koul compatible = "qcom,rpmh-rsc"; 3880d8cf9372SVinod Koul reg = <0x0 0x18200000 0x0 0x10000>, 3881d8cf9372SVinod Koul <0x0 0x18210000 0x0 0x10000>, 3882d8cf9372SVinod Koul <0x0 0x18220000 0x0 0x10000>; 3883d8cf9372SVinod Koul reg-names = "drv-0", "drv-1", "drv-2"; 3884d8cf9372SVinod Koul interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3885d8cf9372SVinod Koul <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3886d8cf9372SVinod Koul <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3887d8cf9372SVinod Koul qcom,tcs-offset = <0xd00>; 3888d8cf9372SVinod Koul qcom,drv-id = <2>; 3889d8cf9372SVinod Koul qcom,tcs-config = <ACTIVE_TCS 2>, 389017ac8af6SMaulik Shah <SLEEP_TCS 3>, 389117ac8af6SMaulik Shah <WAKE_TCS 3>, 389217ac8af6SMaulik Shah <CONTROL_TCS 1>; 3893*2ffa0ca4SMaulik Shah power-domains = <&CLUSTER_PD>; 3894d8cf9372SVinod Koul 3895d8cf9372SVinod Koul rpmhcc: clock-controller { 3896d8cf9372SVinod Koul compatible = "qcom,sm8150-rpmh-clk"; 3897d8cf9372SVinod Koul #clock-cells = <1>; 3898d8cf9372SVinod Koul clock-names = "xo"; 3899d8cf9372SVinod Koul clocks = <&xo_board>; 3900d8cf9372SVinod Koul }; 3901017e7856SSibi Sankar 3902017e7856SSibi Sankar rpmhpd: power-controller { 3903017e7856SSibi Sankar compatible = "qcom,sm8150-rpmhpd"; 3904017e7856SSibi Sankar #power-domain-cells = <1>; 3905017e7856SSibi Sankar operating-points-v2 = <&rpmhpd_opp_table>; 3906017e7856SSibi Sankar 3907017e7856SSibi Sankar rpmhpd_opp_table: opp-table { 3908017e7856SSibi Sankar compatible = "operating-points-v2"; 3909017e7856SSibi Sankar 3910017e7856SSibi Sankar rpmhpd_opp_ret: opp1 { 3911017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3912017e7856SSibi Sankar }; 3913017e7856SSibi Sankar 3914017e7856SSibi Sankar rpmhpd_opp_min_svs: opp2 { 3915017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3916017e7856SSibi Sankar }; 3917017e7856SSibi Sankar 3918017e7856SSibi Sankar rpmhpd_opp_low_svs: opp3 { 3919017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3920017e7856SSibi Sankar }; 3921017e7856SSibi Sankar 3922017e7856SSibi Sankar rpmhpd_opp_svs: opp4 { 3923017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3924017e7856SSibi Sankar }; 3925017e7856SSibi Sankar 3926017e7856SSibi Sankar rpmhpd_opp_svs_l1: opp5 { 3927017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3928017e7856SSibi Sankar }; 3929017e7856SSibi Sankar 3930017e7856SSibi Sankar rpmhpd_opp_svs_l2: opp6 { 3931017e7856SSibi Sankar opp-level = <224>; 3932017e7856SSibi Sankar }; 3933017e7856SSibi Sankar 3934017e7856SSibi Sankar rpmhpd_opp_nom: opp7 { 3935017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3936017e7856SSibi Sankar }; 3937017e7856SSibi Sankar 3938017e7856SSibi Sankar rpmhpd_opp_nom_l1: opp8 { 3939017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3940017e7856SSibi Sankar }; 3941017e7856SSibi Sankar 3942017e7856SSibi Sankar rpmhpd_opp_nom_l2: opp9 { 3943017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3944017e7856SSibi Sankar }; 3945017e7856SSibi Sankar 3946017e7856SSibi Sankar rpmhpd_opp_turbo: opp10 { 3947017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3948017e7856SSibi Sankar }; 3949017e7856SSibi Sankar 3950017e7856SSibi Sankar rpmhpd_opp_turbo_l1: opp11 { 3951017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3952017e7856SSibi Sankar }; 3953017e7856SSibi Sankar }; 3954017e7856SSibi Sankar }; 395571a2fc6eSJonathan Marek 3956fc0e7dd6SKrzysztof Kozlowski apps_bcm_voter: bcm-voter { 395771a2fc6eSJonathan Marek compatible = "qcom,bcm-voter"; 395871a2fc6eSJonathan Marek }; 3959d8cf9372SVinod Koul }; 3960fea8930bSSibi Sankar 3961a6d435c1SSibi Sankar osm_l3: interconnect@18321000 { 3962a6d435c1SSibi Sankar compatible = "qcom,sm8150-osm-l3"; 3963a6d435c1SSibi Sankar reg = <0 0x18321000 0 0x1400>; 3964a6d435c1SSibi Sankar 3965a6d435c1SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3966a6d435c1SSibi Sankar clock-names = "xo", "alternate"; 3967a6d435c1SSibi Sankar 3968a6d435c1SSibi Sankar #interconnect-cells = <1>; 3969a6d435c1SSibi Sankar }; 3970a6d435c1SSibi Sankar 3971fea8930bSSibi Sankar cpufreq_hw: cpufreq@18323000 { 3972fea8930bSSibi Sankar compatible = "qcom,cpufreq-hw"; 3973fea8930bSSibi Sankar reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 3974fea8930bSSibi Sankar <0 0x18327800 0 0x1400>; 3975fea8930bSSibi Sankar reg-names = "freq-domain0", "freq-domain1", 3976fea8930bSSibi Sankar "freq-domain2"; 3977fea8930bSSibi Sankar 3978fea8930bSSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3979fea8930bSSibi Sankar clock-names = "xo", "alternate"; 3980fea8930bSSibi Sankar 3981fea8930bSSibi Sankar #freq-domain-cells = <1>; 3982fea8930bSSibi Sankar }; 398305090bb9SJonathan Marek 39842ffcfe79SThara Gopinath lmh_cluster1: lmh@18350800 { 39852ffcfe79SThara Gopinath compatible = "qcom,sm8150-lmh"; 39862ffcfe79SThara Gopinath reg = <0 0x18350800 0 0x400>; 39872ffcfe79SThara Gopinath interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 39882ffcfe79SThara Gopinath cpus = <&CPU4>; 39892ffcfe79SThara Gopinath qcom,lmh-temp-arm-millicelsius = <60000>; 39902ffcfe79SThara Gopinath qcom,lmh-temp-low-millicelsius = <84500>; 39912ffcfe79SThara Gopinath qcom,lmh-temp-high-millicelsius = <85000>; 39922ffcfe79SThara Gopinath interrupt-controller; 39932ffcfe79SThara Gopinath #interrupt-cells = <1>; 39942ffcfe79SThara Gopinath }; 39952ffcfe79SThara Gopinath 39962ffcfe79SThara Gopinath lmh_cluster0: lmh@18358800 { 39972ffcfe79SThara Gopinath compatible = "qcom,sm8150-lmh"; 39982ffcfe79SThara Gopinath reg = <0 0x18358800 0 0x400>; 39992ffcfe79SThara Gopinath interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 40002ffcfe79SThara Gopinath cpus = <&CPU0>; 40012ffcfe79SThara Gopinath qcom,lmh-temp-arm-millicelsius = <60000>; 40022ffcfe79SThara Gopinath qcom,lmh-temp-low-millicelsius = <84500>; 40032ffcfe79SThara Gopinath qcom,lmh-temp-high-millicelsius = <85000>; 40042ffcfe79SThara Gopinath interrupt-controller; 40052ffcfe79SThara Gopinath #interrupt-cells = <1>; 40062ffcfe79SThara Gopinath }; 40072ffcfe79SThara Gopinath 400805090bb9SJonathan Marek wifi: wifi@18800000 { 400905090bb9SJonathan Marek compatible = "qcom,wcn3990-wifi"; 401005090bb9SJonathan Marek reg = <0 0x18800000 0 0x800000>; 401105090bb9SJonathan Marek reg-names = "membase"; 401205090bb9SJonathan Marek memory-region = <&wlan_mem>; 401305090bb9SJonathan Marek clock-names = "cxo_ref_clk_pin", "qdss"; 401405090bb9SJonathan Marek clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 401505090bb9SJonathan Marek interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 401605090bb9SJonathan Marek <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 401705090bb9SJonathan Marek <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 401805090bb9SJonathan Marek <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 401905090bb9SJonathan Marek <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 402005090bb9SJonathan Marek <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 402105090bb9SJonathan Marek <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 402205090bb9SJonathan Marek <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 402305090bb9SJonathan Marek <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 402405090bb9SJonathan Marek <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 402505090bb9SJonathan Marek <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 402605090bb9SJonathan Marek <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 402705090bb9SJonathan Marek iommus = <&apps_smmu 0x0640 0x1>; 402805090bb9SJonathan Marek status = "disabled"; 402905090bb9SJonathan Marek }; 4030e13c6d14SVinod Koul }; 4031e13c6d14SVinod Koul 4032e13c6d14SVinod Koul timer { 4033e13c6d14SVinod Koul compatible = "arm,armv8-timer"; 4034e13c6d14SVinod Koul interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4035e13c6d14SVinod Koul <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4036e13c6d14SVinod Koul <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4037e13c6d14SVinod Koul <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4038e13c6d14SVinod Koul }; 4039d2fa630cSAmit Kucheria 4040d2fa630cSAmit Kucheria thermal-zones { 4041d2fa630cSAmit Kucheria cpu0-thermal { 4042d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4043d2fa630cSAmit Kucheria polling-delay = <1000>; 4044d2fa630cSAmit Kucheria 4045d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 1>; 4046d2fa630cSAmit Kucheria 4047d2fa630cSAmit Kucheria trips { 4048d2fa630cSAmit Kucheria cpu0_alert0: trip-point0 { 4049d2fa630cSAmit Kucheria temperature = <90000>; 4050d2fa630cSAmit Kucheria hysteresis = <2000>; 4051d2fa630cSAmit Kucheria type = "passive"; 4052d2fa630cSAmit Kucheria }; 4053d2fa630cSAmit Kucheria 4054d2fa630cSAmit Kucheria cpu0_alert1: trip-point1 { 4055d2fa630cSAmit Kucheria temperature = <95000>; 4056d2fa630cSAmit Kucheria hysteresis = <2000>; 4057d2fa630cSAmit Kucheria type = "passive"; 4058d2fa630cSAmit Kucheria }; 4059d2fa630cSAmit Kucheria 4060d2fa630cSAmit Kucheria cpu0_crit: cpu_crit { 4061d2fa630cSAmit Kucheria temperature = <110000>; 4062d2fa630cSAmit Kucheria hysteresis = <1000>; 4063d2fa630cSAmit Kucheria type = "critical"; 4064d2fa630cSAmit Kucheria }; 4065d2fa630cSAmit Kucheria }; 4066d2fa630cSAmit Kucheria 4067d2fa630cSAmit Kucheria cooling-maps { 4068d2fa630cSAmit Kucheria map0 { 4069d2fa630cSAmit Kucheria trip = <&cpu0_alert0>; 4070d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4071d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4072d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4073d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4074d2fa630cSAmit Kucheria }; 4075d2fa630cSAmit Kucheria map1 { 4076d2fa630cSAmit Kucheria trip = <&cpu0_alert1>; 4077d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4078d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4079d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4080d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4081d2fa630cSAmit Kucheria }; 4082d2fa630cSAmit Kucheria }; 4083d2fa630cSAmit Kucheria }; 4084d2fa630cSAmit Kucheria 4085d2fa630cSAmit Kucheria cpu1-thermal { 4086d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4087d2fa630cSAmit Kucheria polling-delay = <1000>; 4088d2fa630cSAmit Kucheria 4089d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 2>; 4090d2fa630cSAmit Kucheria 4091d2fa630cSAmit Kucheria trips { 4092d2fa630cSAmit Kucheria cpu1_alert0: trip-point0 { 4093d2fa630cSAmit Kucheria temperature = <90000>; 4094d2fa630cSAmit Kucheria hysteresis = <2000>; 4095d2fa630cSAmit Kucheria type = "passive"; 4096d2fa630cSAmit Kucheria }; 4097d2fa630cSAmit Kucheria 4098d2fa630cSAmit Kucheria cpu1_alert1: trip-point1 { 4099d2fa630cSAmit Kucheria temperature = <95000>; 4100d2fa630cSAmit Kucheria hysteresis = <2000>; 4101d2fa630cSAmit Kucheria type = "passive"; 4102d2fa630cSAmit Kucheria }; 4103d2fa630cSAmit Kucheria 4104d2fa630cSAmit Kucheria cpu1_crit: cpu_crit { 4105d2fa630cSAmit Kucheria temperature = <110000>; 4106d2fa630cSAmit Kucheria hysteresis = <1000>; 4107d2fa630cSAmit Kucheria type = "critical"; 4108d2fa630cSAmit Kucheria }; 4109d2fa630cSAmit Kucheria }; 4110d2fa630cSAmit Kucheria 4111d2fa630cSAmit Kucheria cooling-maps { 4112d2fa630cSAmit Kucheria map0 { 4113d2fa630cSAmit Kucheria trip = <&cpu1_alert0>; 4114d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4115d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4116d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4117d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4118d2fa630cSAmit Kucheria }; 4119d2fa630cSAmit Kucheria map1 { 4120d2fa630cSAmit Kucheria trip = <&cpu1_alert1>; 4121d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4122d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4123d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4124d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4125d2fa630cSAmit Kucheria }; 4126d2fa630cSAmit Kucheria }; 4127d2fa630cSAmit Kucheria }; 4128d2fa630cSAmit Kucheria 4129d2fa630cSAmit Kucheria cpu2-thermal { 4130d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4131d2fa630cSAmit Kucheria polling-delay = <1000>; 4132d2fa630cSAmit Kucheria 4133d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 3>; 4134d2fa630cSAmit Kucheria 4135d2fa630cSAmit Kucheria trips { 4136d2fa630cSAmit Kucheria cpu2_alert0: trip-point0 { 4137d2fa630cSAmit Kucheria temperature = <90000>; 4138d2fa630cSAmit Kucheria hysteresis = <2000>; 4139d2fa630cSAmit Kucheria type = "passive"; 4140d2fa630cSAmit Kucheria }; 4141d2fa630cSAmit Kucheria 4142d2fa630cSAmit Kucheria cpu2_alert1: trip-point1 { 4143d2fa630cSAmit Kucheria temperature = <95000>; 4144d2fa630cSAmit Kucheria hysteresis = <2000>; 4145d2fa630cSAmit Kucheria type = "passive"; 4146d2fa630cSAmit Kucheria }; 4147d2fa630cSAmit Kucheria 4148d2fa630cSAmit Kucheria cpu2_crit: cpu_crit { 4149d2fa630cSAmit Kucheria temperature = <110000>; 4150d2fa630cSAmit Kucheria hysteresis = <1000>; 4151d2fa630cSAmit Kucheria type = "critical"; 4152d2fa630cSAmit Kucheria }; 4153d2fa630cSAmit Kucheria }; 4154d2fa630cSAmit Kucheria 4155d2fa630cSAmit Kucheria cooling-maps { 4156d2fa630cSAmit Kucheria map0 { 4157d2fa630cSAmit Kucheria trip = <&cpu2_alert0>; 4158d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4159d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4160d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4161d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4162d2fa630cSAmit Kucheria }; 4163d2fa630cSAmit Kucheria map1 { 4164d2fa630cSAmit Kucheria trip = <&cpu2_alert1>; 4165d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4166d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4167d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4168d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4169d2fa630cSAmit Kucheria }; 4170d2fa630cSAmit Kucheria }; 4171d2fa630cSAmit Kucheria }; 4172d2fa630cSAmit Kucheria 4173d2fa630cSAmit Kucheria cpu3-thermal { 4174d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4175d2fa630cSAmit Kucheria polling-delay = <1000>; 4176d2fa630cSAmit Kucheria 4177d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 4>; 4178d2fa630cSAmit Kucheria 4179d2fa630cSAmit Kucheria trips { 4180d2fa630cSAmit Kucheria cpu3_alert0: trip-point0 { 4181d2fa630cSAmit Kucheria temperature = <90000>; 4182d2fa630cSAmit Kucheria hysteresis = <2000>; 4183d2fa630cSAmit Kucheria type = "passive"; 4184d2fa630cSAmit Kucheria }; 4185d2fa630cSAmit Kucheria 4186d2fa630cSAmit Kucheria cpu3_alert1: trip-point1 { 4187d2fa630cSAmit Kucheria temperature = <95000>; 4188d2fa630cSAmit Kucheria hysteresis = <2000>; 4189d2fa630cSAmit Kucheria type = "passive"; 4190d2fa630cSAmit Kucheria }; 4191d2fa630cSAmit Kucheria 4192d2fa630cSAmit Kucheria cpu3_crit: cpu_crit { 4193d2fa630cSAmit Kucheria temperature = <110000>; 4194d2fa630cSAmit Kucheria hysteresis = <1000>; 4195d2fa630cSAmit Kucheria type = "critical"; 4196d2fa630cSAmit Kucheria }; 4197d2fa630cSAmit Kucheria }; 4198d2fa630cSAmit Kucheria 4199d2fa630cSAmit Kucheria cooling-maps { 4200d2fa630cSAmit Kucheria map0 { 4201d2fa630cSAmit Kucheria trip = <&cpu3_alert0>; 4202d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4203d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4204d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4205d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4206d2fa630cSAmit Kucheria }; 4207d2fa630cSAmit Kucheria map1 { 4208d2fa630cSAmit Kucheria trip = <&cpu3_alert1>; 4209d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4210d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4211d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4212d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4213d2fa630cSAmit Kucheria }; 4214d2fa630cSAmit Kucheria }; 4215d2fa630cSAmit Kucheria }; 4216d2fa630cSAmit Kucheria 4217d2fa630cSAmit Kucheria cpu4-top-thermal { 4218d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4219d2fa630cSAmit Kucheria polling-delay = <1000>; 4220d2fa630cSAmit Kucheria 4221d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 7>; 4222d2fa630cSAmit Kucheria 4223d2fa630cSAmit Kucheria trips { 4224d2fa630cSAmit Kucheria cpu4_top_alert0: trip-point0 { 4225d2fa630cSAmit Kucheria temperature = <90000>; 4226d2fa630cSAmit Kucheria hysteresis = <2000>; 4227d2fa630cSAmit Kucheria type = "passive"; 4228d2fa630cSAmit Kucheria }; 4229d2fa630cSAmit Kucheria 4230d2fa630cSAmit Kucheria cpu4_top_alert1: trip-point1 { 4231d2fa630cSAmit Kucheria temperature = <95000>; 4232d2fa630cSAmit Kucheria hysteresis = <2000>; 4233d2fa630cSAmit Kucheria type = "passive"; 4234d2fa630cSAmit Kucheria }; 4235d2fa630cSAmit Kucheria 4236d2fa630cSAmit Kucheria cpu4_top_crit: cpu_crit { 4237d2fa630cSAmit Kucheria temperature = <110000>; 4238d2fa630cSAmit Kucheria hysteresis = <1000>; 4239d2fa630cSAmit Kucheria type = "critical"; 4240d2fa630cSAmit Kucheria }; 4241d2fa630cSAmit Kucheria }; 4242d2fa630cSAmit Kucheria 4243d2fa630cSAmit Kucheria cooling-maps { 4244d2fa630cSAmit Kucheria map0 { 4245d2fa630cSAmit Kucheria trip = <&cpu4_top_alert0>; 4246d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4247d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4248d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4249d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4250d2fa630cSAmit Kucheria }; 4251d2fa630cSAmit Kucheria map1 { 4252d2fa630cSAmit Kucheria trip = <&cpu4_top_alert1>; 4253d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4254d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4255d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4256d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4257d2fa630cSAmit Kucheria }; 4258d2fa630cSAmit Kucheria }; 4259d2fa630cSAmit Kucheria }; 4260d2fa630cSAmit Kucheria 4261d2fa630cSAmit Kucheria cpu5-top-thermal { 4262d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4263d2fa630cSAmit Kucheria polling-delay = <1000>; 4264d2fa630cSAmit Kucheria 4265d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 8>; 4266d2fa630cSAmit Kucheria 4267d2fa630cSAmit Kucheria trips { 4268d2fa630cSAmit Kucheria cpu5_top_alert0: trip-point0 { 4269d2fa630cSAmit Kucheria temperature = <90000>; 4270d2fa630cSAmit Kucheria hysteresis = <2000>; 4271d2fa630cSAmit Kucheria type = "passive"; 4272d2fa630cSAmit Kucheria }; 4273d2fa630cSAmit Kucheria 4274d2fa630cSAmit Kucheria cpu5_top_alert1: trip-point1 { 4275d2fa630cSAmit Kucheria temperature = <95000>; 4276d2fa630cSAmit Kucheria hysteresis = <2000>; 4277d2fa630cSAmit Kucheria type = "passive"; 4278d2fa630cSAmit Kucheria }; 4279d2fa630cSAmit Kucheria 4280d2fa630cSAmit Kucheria cpu5_top_crit: cpu_crit { 4281d2fa630cSAmit Kucheria temperature = <110000>; 4282d2fa630cSAmit Kucheria hysteresis = <1000>; 4283d2fa630cSAmit Kucheria type = "critical"; 4284d2fa630cSAmit Kucheria }; 4285d2fa630cSAmit Kucheria }; 4286d2fa630cSAmit Kucheria 4287d2fa630cSAmit Kucheria cooling-maps { 4288d2fa630cSAmit Kucheria map0 { 4289d2fa630cSAmit Kucheria trip = <&cpu5_top_alert0>; 4290d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4291d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4292d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4293d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4294d2fa630cSAmit Kucheria }; 4295d2fa630cSAmit Kucheria map1 { 4296d2fa630cSAmit Kucheria trip = <&cpu5_top_alert1>; 4297d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4298d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4299d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4300d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4301d2fa630cSAmit Kucheria }; 4302d2fa630cSAmit Kucheria }; 4303d2fa630cSAmit Kucheria }; 4304d2fa630cSAmit Kucheria 4305d2fa630cSAmit Kucheria cpu6-top-thermal { 4306d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4307d2fa630cSAmit Kucheria polling-delay = <1000>; 4308d2fa630cSAmit Kucheria 4309d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 9>; 4310d2fa630cSAmit Kucheria 4311d2fa630cSAmit Kucheria trips { 4312d2fa630cSAmit Kucheria cpu6_top_alert0: trip-point0 { 4313d2fa630cSAmit Kucheria temperature = <90000>; 4314d2fa630cSAmit Kucheria hysteresis = <2000>; 4315d2fa630cSAmit Kucheria type = "passive"; 4316d2fa630cSAmit Kucheria }; 4317d2fa630cSAmit Kucheria 4318d2fa630cSAmit Kucheria cpu6_top_alert1: trip-point1 { 4319d2fa630cSAmit Kucheria temperature = <95000>; 4320d2fa630cSAmit Kucheria hysteresis = <2000>; 4321d2fa630cSAmit Kucheria type = "passive"; 4322d2fa630cSAmit Kucheria }; 4323d2fa630cSAmit Kucheria 4324d2fa630cSAmit Kucheria cpu6_top_crit: cpu_crit { 4325d2fa630cSAmit Kucheria temperature = <110000>; 4326d2fa630cSAmit Kucheria hysteresis = <1000>; 4327d2fa630cSAmit Kucheria type = "critical"; 4328d2fa630cSAmit Kucheria }; 4329d2fa630cSAmit Kucheria }; 4330d2fa630cSAmit Kucheria 4331d2fa630cSAmit Kucheria cooling-maps { 4332d2fa630cSAmit Kucheria map0 { 4333d2fa630cSAmit Kucheria trip = <&cpu6_top_alert0>; 4334d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4335d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4336d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4337d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4338d2fa630cSAmit Kucheria }; 4339d2fa630cSAmit Kucheria map1 { 4340d2fa630cSAmit Kucheria trip = <&cpu6_top_alert1>; 4341d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4342d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4343d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4344d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4345d2fa630cSAmit Kucheria }; 4346d2fa630cSAmit Kucheria }; 4347d2fa630cSAmit Kucheria }; 4348d2fa630cSAmit Kucheria 4349d2fa630cSAmit Kucheria cpu7-top-thermal { 4350d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4351d2fa630cSAmit Kucheria polling-delay = <1000>; 4352d2fa630cSAmit Kucheria 4353d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 10>; 4354d2fa630cSAmit Kucheria 4355d2fa630cSAmit Kucheria trips { 4356d2fa630cSAmit Kucheria cpu7_top_alert0: trip-point0 { 4357d2fa630cSAmit Kucheria temperature = <90000>; 4358d2fa630cSAmit Kucheria hysteresis = <2000>; 4359d2fa630cSAmit Kucheria type = "passive"; 4360d2fa630cSAmit Kucheria }; 4361d2fa630cSAmit Kucheria 4362d2fa630cSAmit Kucheria cpu7_top_alert1: trip-point1 { 4363d2fa630cSAmit Kucheria temperature = <95000>; 4364d2fa630cSAmit Kucheria hysteresis = <2000>; 4365d2fa630cSAmit Kucheria type = "passive"; 4366d2fa630cSAmit Kucheria }; 4367d2fa630cSAmit Kucheria 4368d2fa630cSAmit Kucheria cpu7_top_crit: cpu_crit { 4369d2fa630cSAmit Kucheria temperature = <110000>; 4370d2fa630cSAmit Kucheria hysteresis = <1000>; 4371d2fa630cSAmit Kucheria type = "critical"; 4372d2fa630cSAmit Kucheria }; 4373d2fa630cSAmit Kucheria }; 4374d2fa630cSAmit Kucheria 4375d2fa630cSAmit Kucheria cooling-maps { 4376d2fa630cSAmit Kucheria map0 { 4377d2fa630cSAmit Kucheria trip = <&cpu7_top_alert0>; 4378d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4379d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4380d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4381d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4382d2fa630cSAmit Kucheria }; 4383d2fa630cSAmit Kucheria map1 { 4384d2fa630cSAmit Kucheria trip = <&cpu7_top_alert1>; 4385d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4386d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4387d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4388d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4389d2fa630cSAmit Kucheria }; 4390d2fa630cSAmit Kucheria }; 4391d2fa630cSAmit Kucheria }; 4392d2fa630cSAmit Kucheria 4393d2fa630cSAmit Kucheria cpu4-bottom-thermal { 4394d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4395d2fa630cSAmit Kucheria polling-delay = <1000>; 4396d2fa630cSAmit Kucheria 4397d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 11>; 4398d2fa630cSAmit Kucheria 4399d2fa630cSAmit Kucheria trips { 4400d2fa630cSAmit Kucheria cpu4_bottom_alert0: trip-point0 { 4401d2fa630cSAmit Kucheria temperature = <90000>; 4402d2fa630cSAmit Kucheria hysteresis = <2000>; 4403d2fa630cSAmit Kucheria type = "passive"; 4404d2fa630cSAmit Kucheria }; 4405d2fa630cSAmit Kucheria 4406d2fa630cSAmit Kucheria cpu4_bottom_alert1: trip-point1 { 4407d2fa630cSAmit Kucheria temperature = <95000>; 4408d2fa630cSAmit Kucheria hysteresis = <2000>; 4409d2fa630cSAmit Kucheria type = "passive"; 4410d2fa630cSAmit Kucheria }; 4411d2fa630cSAmit Kucheria 4412d2fa630cSAmit Kucheria cpu4_bottom_crit: cpu_crit { 4413d2fa630cSAmit Kucheria temperature = <110000>; 4414d2fa630cSAmit Kucheria hysteresis = <1000>; 4415d2fa630cSAmit Kucheria type = "critical"; 4416d2fa630cSAmit Kucheria }; 4417d2fa630cSAmit Kucheria }; 4418d2fa630cSAmit Kucheria 4419d2fa630cSAmit Kucheria cooling-maps { 4420d2fa630cSAmit Kucheria map0 { 4421d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert0>; 4422d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4423d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4424d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4425d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4426d2fa630cSAmit Kucheria }; 4427d2fa630cSAmit Kucheria map1 { 4428d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert1>; 4429d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4430d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4431d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4432d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4433d2fa630cSAmit Kucheria }; 4434d2fa630cSAmit Kucheria }; 4435d2fa630cSAmit Kucheria }; 4436d2fa630cSAmit Kucheria 4437d2fa630cSAmit Kucheria cpu5-bottom-thermal { 4438d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4439d2fa630cSAmit Kucheria polling-delay = <1000>; 4440d2fa630cSAmit Kucheria 4441d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 12>; 4442d2fa630cSAmit Kucheria 4443d2fa630cSAmit Kucheria trips { 4444d2fa630cSAmit Kucheria cpu5_bottom_alert0: trip-point0 { 4445d2fa630cSAmit Kucheria temperature = <90000>; 4446d2fa630cSAmit Kucheria hysteresis = <2000>; 4447d2fa630cSAmit Kucheria type = "passive"; 4448d2fa630cSAmit Kucheria }; 4449d2fa630cSAmit Kucheria 4450d2fa630cSAmit Kucheria cpu5_bottom_alert1: trip-point1 { 4451d2fa630cSAmit Kucheria temperature = <95000>; 4452d2fa630cSAmit Kucheria hysteresis = <2000>; 4453d2fa630cSAmit Kucheria type = "passive"; 4454d2fa630cSAmit Kucheria }; 4455d2fa630cSAmit Kucheria 4456d2fa630cSAmit Kucheria cpu5_bottom_crit: cpu_crit { 4457d2fa630cSAmit Kucheria temperature = <110000>; 4458d2fa630cSAmit Kucheria hysteresis = <1000>; 4459d2fa630cSAmit Kucheria type = "critical"; 4460d2fa630cSAmit Kucheria }; 4461d2fa630cSAmit Kucheria }; 4462d2fa630cSAmit Kucheria 4463d2fa630cSAmit Kucheria cooling-maps { 4464d2fa630cSAmit Kucheria map0 { 4465d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert0>; 4466d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4467d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4468d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4469d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4470d2fa630cSAmit Kucheria }; 4471d2fa630cSAmit Kucheria map1 { 4472d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert1>; 4473d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4474d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4475d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4476d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4477d2fa630cSAmit Kucheria }; 4478d2fa630cSAmit Kucheria }; 4479d2fa630cSAmit Kucheria }; 4480d2fa630cSAmit Kucheria 4481d2fa630cSAmit Kucheria cpu6-bottom-thermal { 4482d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4483d2fa630cSAmit Kucheria polling-delay = <1000>; 4484d2fa630cSAmit Kucheria 4485d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 13>; 4486d2fa630cSAmit Kucheria 4487d2fa630cSAmit Kucheria trips { 4488d2fa630cSAmit Kucheria cpu6_bottom_alert0: trip-point0 { 4489d2fa630cSAmit Kucheria temperature = <90000>; 4490d2fa630cSAmit Kucheria hysteresis = <2000>; 4491d2fa630cSAmit Kucheria type = "passive"; 4492d2fa630cSAmit Kucheria }; 4493d2fa630cSAmit Kucheria 4494d2fa630cSAmit Kucheria cpu6_bottom_alert1: trip-point1 { 4495d2fa630cSAmit Kucheria temperature = <95000>; 4496d2fa630cSAmit Kucheria hysteresis = <2000>; 4497d2fa630cSAmit Kucheria type = "passive"; 4498d2fa630cSAmit Kucheria }; 4499d2fa630cSAmit Kucheria 4500d2fa630cSAmit Kucheria cpu6_bottom_crit: cpu_crit { 4501d2fa630cSAmit Kucheria temperature = <110000>; 4502d2fa630cSAmit Kucheria hysteresis = <1000>; 4503d2fa630cSAmit Kucheria type = "critical"; 4504d2fa630cSAmit Kucheria }; 4505d2fa630cSAmit Kucheria }; 4506d2fa630cSAmit Kucheria 4507d2fa630cSAmit Kucheria cooling-maps { 4508d2fa630cSAmit Kucheria map0 { 4509d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert0>; 4510d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4511d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4512d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4513d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4514d2fa630cSAmit Kucheria }; 4515d2fa630cSAmit Kucheria map1 { 4516d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert1>; 4517d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4518d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4519d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4520d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4521d2fa630cSAmit Kucheria }; 4522d2fa630cSAmit Kucheria }; 4523d2fa630cSAmit Kucheria }; 4524d2fa630cSAmit Kucheria 4525d2fa630cSAmit Kucheria cpu7-bottom-thermal { 4526d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4527d2fa630cSAmit Kucheria polling-delay = <1000>; 4528d2fa630cSAmit Kucheria 4529d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 14>; 4530d2fa630cSAmit Kucheria 4531d2fa630cSAmit Kucheria trips { 4532d2fa630cSAmit Kucheria cpu7_bottom_alert0: trip-point0 { 4533d2fa630cSAmit Kucheria temperature = <90000>; 4534d2fa630cSAmit Kucheria hysteresis = <2000>; 4535d2fa630cSAmit Kucheria type = "passive"; 4536d2fa630cSAmit Kucheria }; 4537d2fa630cSAmit Kucheria 4538d2fa630cSAmit Kucheria cpu7_bottom_alert1: trip-point1 { 4539d2fa630cSAmit Kucheria temperature = <95000>; 4540d2fa630cSAmit Kucheria hysteresis = <2000>; 4541d2fa630cSAmit Kucheria type = "passive"; 4542d2fa630cSAmit Kucheria }; 4543d2fa630cSAmit Kucheria 4544d2fa630cSAmit Kucheria cpu7_bottom_crit: cpu_crit { 4545d2fa630cSAmit Kucheria temperature = <110000>; 4546d2fa630cSAmit Kucheria hysteresis = <1000>; 4547d2fa630cSAmit Kucheria type = "critical"; 4548d2fa630cSAmit Kucheria }; 4549d2fa630cSAmit Kucheria }; 4550d2fa630cSAmit Kucheria 4551d2fa630cSAmit Kucheria cooling-maps { 4552d2fa630cSAmit Kucheria map0 { 4553d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert0>; 4554d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4555d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4556d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4557d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4558d2fa630cSAmit Kucheria }; 4559d2fa630cSAmit Kucheria map1 { 4560d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert1>; 4561d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4562d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4563d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4564d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4565d2fa630cSAmit Kucheria }; 4566d2fa630cSAmit Kucheria }; 4567d2fa630cSAmit Kucheria }; 4568d2fa630cSAmit Kucheria 4569d2fa630cSAmit Kucheria aoss0-thermal { 4570d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4571d2fa630cSAmit Kucheria polling-delay = <1000>; 4572d2fa630cSAmit Kucheria 4573d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 0>; 4574d2fa630cSAmit Kucheria 4575d2fa630cSAmit Kucheria trips { 4576d2fa630cSAmit Kucheria aoss0_alert0: trip-point0 { 4577d2fa630cSAmit Kucheria temperature = <90000>; 4578d2fa630cSAmit Kucheria hysteresis = <2000>; 4579d2fa630cSAmit Kucheria type = "hot"; 4580d2fa630cSAmit Kucheria }; 4581d2fa630cSAmit Kucheria }; 4582d2fa630cSAmit Kucheria }; 4583d2fa630cSAmit Kucheria 4584d2fa630cSAmit Kucheria cluster0-thermal { 4585d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4586d2fa630cSAmit Kucheria polling-delay = <1000>; 4587d2fa630cSAmit Kucheria 4588d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 5>; 4589d2fa630cSAmit Kucheria 4590d2fa630cSAmit Kucheria trips { 4591d2fa630cSAmit Kucheria cluster0_alert0: trip-point0 { 4592d2fa630cSAmit Kucheria temperature = <90000>; 4593d2fa630cSAmit Kucheria hysteresis = <2000>; 4594d2fa630cSAmit Kucheria type = "hot"; 4595d2fa630cSAmit Kucheria }; 4596d2fa630cSAmit Kucheria cluster0_crit: cluster0_crit { 4597d2fa630cSAmit Kucheria temperature = <110000>; 4598d2fa630cSAmit Kucheria hysteresis = <2000>; 4599d2fa630cSAmit Kucheria type = "critical"; 4600d2fa630cSAmit Kucheria }; 4601d2fa630cSAmit Kucheria }; 4602d2fa630cSAmit Kucheria }; 4603d2fa630cSAmit Kucheria 4604d2fa630cSAmit Kucheria cluster1-thermal { 4605d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4606d2fa630cSAmit Kucheria polling-delay = <1000>; 4607d2fa630cSAmit Kucheria 4608d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 6>; 4609d2fa630cSAmit Kucheria 4610d2fa630cSAmit Kucheria trips { 4611d2fa630cSAmit Kucheria cluster1_alert0: trip-point0 { 4612d2fa630cSAmit Kucheria temperature = <90000>; 4613d2fa630cSAmit Kucheria hysteresis = <2000>; 4614d2fa630cSAmit Kucheria type = "hot"; 4615d2fa630cSAmit Kucheria }; 4616d2fa630cSAmit Kucheria cluster1_crit: cluster1_crit { 4617d2fa630cSAmit Kucheria temperature = <110000>; 4618d2fa630cSAmit Kucheria hysteresis = <2000>; 4619d2fa630cSAmit Kucheria type = "critical"; 4620d2fa630cSAmit Kucheria }; 4621d2fa630cSAmit Kucheria }; 4622d2fa630cSAmit Kucheria }; 4623d2fa630cSAmit Kucheria 46247be1c395SDavid Heidelberg gpu-top-thermal { 4625d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4626d2fa630cSAmit Kucheria polling-delay = <1000>; 4627d2fa630cSAmit Kucheria 4628d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 15>; 4629d2fa630cSAmit Kucheria 4630d2fa630cSAmit Kucheria trips { 4631d2fa630cSAmit Kucheria gpu1_alert0: trip-point0 { 4632d2fa630cSAmit Kucheria temperature = <90000>; 4633d2fa630cSAmit Kucheria hysteresis = <2000>; 4634d2fa630cSAmit Kucheria type = "hot"; 4635d2fa630cSAmit Kucheria }; 4636d2fa630cSAmit Kucheria }; 4637d2fa630cSAmit Kucheria }; 4638d2fa630cSAmit Kucheria 4639d2fa630cSAmit Kucheria aoss1-thermal { 4640d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4641d2fa630cSAmit Kucheria polling-delay = <1000>; 4642d2fa630cSAmit Kucheria 4643d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 0>; 4644d2fa630cSAmit Kucheria 4645d2fa630cSAmit Kucheria trips { 4646d2fa630cSAmit Kucheria aoss1_alert0: trip-point0 { 4647d2fa630cSAmit Kucheria temperature = <90000>; 4648d2fa630cSAmit Kucheria hysteresis = <2000>; 4649d2fa630cSAmit Kucheria type = "hot"; 4650d2fa630cSAmit Kucheria }; 4651d2fa630cSAmit Kucheria }; 4652d2fa630cSAmit Kucheria }; 4653d2fa630cSAmit Kucheria 4654d2fa630cSAmit Kucheria wlan-thermal { 4655d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4656d2fa630cSAmit Kucheria polling-delay = <1000>; 4657d2fa630cSAmit Kucheria 4658d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 1>; 4659d2fa630cSAmit Kucheria 4660d2fa630cSAmit Kucheria trips { 4661d2fa630cSAmit Kucheria wlan_alert0: trip-point0 { 4662d2fa630cSAmit Kucheria temperature = <90000>; 4663d2fa630cSAmit Kucheria hysteresis = <2000>; 4664d2fa630cSAmit Kucheria type = "hot"; 4665d2fa630cSAmit Kucheria }; 4666d2fa630cSAmit Kucheria }; 4667d2fa630cSAmit Kucheria }; 4668d2fa630cSAmit Kucheria 4669d2fa630cSAmit Kucheria video-thermal { 4670d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4671d2fa630cSAmit Kucheria polling-delay = <1000>; 4672d2fa630cSAmit Kucheria 4673d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 2>; 4674d2fa630cSAmit Kucheria 4675d2fa630cSAmit Kucheria trips { 4676d2fa630cSAmit Kucheria video_alert0: trip-point0 { 4677d2fa630cSAmit Kucheria temperature = <90000>; 4678d2fa630cSAmit Kucheria hysteresis = <2000>; 4679d2fa630cSAmit Kucheria type = "hot"; 4680d2fa630cSAmit Kucheria }; 4681d2fa630cSAmit Kucheria }; 4682d2fa630cSAmit Kucheria }; 4683d2fa630cSAmit Kucheria 4684d2fa630cSAmit Kucheria mem-thermal { 4685d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4686d2fa630cSAmit Kucheria polling-delay = <1000>; 4687d2fa630cSAmit Kucheria 4688d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 3>; 4689d2fa630cSAmit Kucheria 4690d2fa630cSAmit Kucheria trips { 4691d2fa630cSAmit Kucheria mem_alert0: trip-point0 { 4692d2fa630cSAmit Kucheria temperature = <90000>; 4693d2fa630cSAmit Kucheria hysteresis = <2000>; 4694d2fa630cSAmit Kucheria type = "hot"; 4695d2fa630cSAmit Kucheria }; 4696d2fa630cSAmit Kucheria }; 4697d2fa630cSAmit Kucheria }; 4698d2fa630cSAmit Kucheria 4699d2fa630cSAmit Kucheria q6-hvx-thermal { 4700d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4701d2fa630cSAmit Kucheria polling-delay = <1000>; 4702d2fa630cSAmit Kucheria 4703d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 4>; 4704d2fa630cSAmit Kucheria 4705d2fa630cSAmit Kucheria trips { 4706d2fa630cSAmit Kucheria q6_hvx_alert0: trip-point0 { 4707d2fa630cSAmit Kucheria temperature = <90000>; 4708d2fa630cSAmit Kucheria hysteresis = <2000>; 4709d2fa630cSAmit Kucheria type = "hot"; 4710d2fa630cSAmit Kucheria }; 4711d2fa630cSAmit Kucheria }; 4712d2fa630cSAmit Kucheria }; 4713d2fa630cSAmit Kucheria 4714d2fa630cSAmit Kucheria camera-thermal { 4715d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4716d2fa630cSAmit Kucheria polling-delay = <1000>; 4717d2fa630cSAmit Kucheria 4718d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 5>; 4719d2fa630cSAmit Kucheria 4720d2fa630cSAmit Kucheria trips { 4721d2fa630cSAmit Kucheria camera_alert0: trip-point0 { 4722d2fa630cSAmit Kucheria temperature = <90000>; 4723d2fa630cSAmit Kucheria hysteresis = <2000>; 4724d2fa630cSAmit Kucheria type = "hot"; 4725d2fa630cSAmit Kucheria }; 4726d2fa630cSAmit Kucheria }; 4727d2fa630cSAmit Kucheria }; 4728d2fa630cSAmit Kucheria 4729d2fa630cSAmit Kucheria compute-thermal { 4730d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4731d2fa630cSAmit Kucheria polling-delay = <1000>; 4732d2fa630cSAmit Kucheria 4733d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 6>; 4734d2fa630cSAmit Kucheria 4735d2fa630cSAmit Kucheria trips { 4736d2fa630cSAmit Kucheria compute_alert0: trip-point0 { 4737d2fa630cSAmit Kucheria temperature = <90000>; 4738d2fa630cSAmit Kucheria hysteresis = <2000>; 4739d2fa630cSAmit Kucheria type = "hot"; 4740d2fa630cSAmit Kucheria }; 4741d2fa630cSAmit Kucheria }; 4742d2fa630cSAmit Kucheria }; 4743d2fa630cSAmit Kucheria 4744d2fa630cSAmit Kucheria modem-thermal { 4745d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4746d2fa630cSAmit Kucheria polling-delay = <1000>; 4747d2fa630cSAmit Kucheria 4748d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 7>; 4749d2fa630cSAmit Kucheria 4750d2fa630cSAmit Kucheria trips { 4751d2fa630cSAmit Kucheria modem_alert0: trip-point0 { 4752d2fa630cSAmit Kucheria temperature = <90000>; 4753d2fa630cSAmit Kucheria hysteresis = <2000>; 4754d2fa630cSAmit Kucheria type = "hot"; 4755d2fa630cSAmit Kucheria }; 4756d2fa630cSAmit Kucheria }; 4757d2fa630cSAmit Kucheria }; 4758d2fa630cSAmit Kucheria 4759d2fa630cSAmit Kucheria npu-thermal { 4760d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4761d2fa630cSAmit Kucheria polling-delay = <1000>; 4762d2fa630cSAmit Kucheria 4763d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 8>; 4764d2fa630cSAmit Kucheria 4765d2fa630cSAmit Kucheria trips { 4766d2fa630cSAmit Kucheria npu_alert0: trip-point0 { 4767d2fa630cSAmit Kucheria temperature = <90000>; 4768d2fa630cSAmit Kucheria hysteresis = <2000>; 4769d2fa630cSAmit Kucheria type = "hot"; 4770d2fa630cSAmit Kucheria }; 4771d2fa630cSAmit Kucheria }; 4772d2fa630cSAmit Kucheria }; 4773d2fa630cSAmit Kucheria 4774d2fa630cSAmit Kucheria modem-vec-thermal { 4775d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4776d2fa630cSAmit Kucheria polling-delay = <1000>; 4777d2fa630cSAmit Kucheria 4778d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 9>; 4779d2fa630cSAmit Kucheria 4780d2fa630cSAmit Kucheria trips { 4781d2fa630cSAmit Kucheria modem_vec_alert0: trip-point0 { 4782d2fa630cSAmit Kucheria temperature = <90000>; 4783d2fa630cSAmit Kucheria hysteresis = <2000>; 4784d2fa630cSAmit Kucheria type = "hot"; 4785d2fa630cSAmit Kucheria }; 4786d2fa630cSAmit Kucheria }; 4787d2fa630cSAmit Kucheria }; 4788d2fa630cSAmit Kucheria 4789d2fa630cSAmit Kucheria modem-scl-thermal { 4790d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4791d2fa630cSAmit Kucheria polling-delay = <1000>; 4792d2fa630cSAmit Kucheria 4793d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 10>; 4794d2fa630cSAmit Kucheria 4795d2fa630cSAmit Kucheria trips { 4796d2fa630cSAmit Kucheria modem_scl_alert0: trip-point0 { 4797d2fa630cSAmit Kucheria temperature = <90000>; 4798d2fa630cSAmit Kucheria hysteresis = <2000>; 4799d2fa630cSAmit Kucheria type = "hot"; 4800d2fa630cSAmit Kucheria }; 4801d2fa630cSAmit Kucheria }; 4802d2fa630cSAmit Kucheria }; 4803d2fa630cSAmit Kucheria 48047be1c395SDavid Heidelberg gpu-bottom-thermal { 4805d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4806d2fa630cSAmit Kucheria polling-delay = <1000>; 4807d2fa630cSAmit Kucheria 4808d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 11>; 4809d2fa630cSAmit Kucheria 4810d2fa630cSAmit Kucheria trips { 4811d2fa630cSAmit Kucheria gpu2_alert0: trip-point0 { 4812d2fa630cSAmit Kucheria temperature = <90000>; 4813d2fa630cSAmit Kucheria hysteresis = <2000>; 4814d2fa630cSAmit Kucheria type = "hot"; 4815d2fa630cSAmit Kucheria }; 4816d2fa630cSAmit Kucheria }; 4817d2fa630cSAmit Kucheria }; 4818d2fa630cSAmit Kucheria }; 4819e13c6d14SVinod Koul}; 4820