1e13c6d14SVinod Koul// SPDX-License-Identifier: BSD-3-Clause 2e13c6d14SVinod Koul/* 3e13c6d14SVinod Koul * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4e13c6d14SVinod Koul * Copyright (c) 2019, Linaro Limited 5e13c6d14SVinod Koul */ 6e13c6d14SVinod Koul 705006290SFelipe Balbi#include <dt-bindings/dma/qcom-gpi.h> 8e13c6d14SVinod Koul#include <dt-bindings/interrupt-controller/arm-gic.h> 9017e7856SSibi Sankar#include <dt-bindings/power/qcom-rpmpd.h> 10e13c6d14SVinod Koul#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11e13c6d14SVinod Koul#include <dt-bindings/clock/qcom,rpmh.h> 12d6f55763SVinod Koul#include <dt-bindings/clock/qcom,gcc-sm8150.h> 13f1269916SJonathan Marek#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 14a6d435c1SSibi Sankar#include <dt-bindings/interconnect/qcom,osm-l3.h> 152b6187abSThara Gopinath#include <dt-bindings/interconnect/qcom,sm8150.h> 16d2fa630cSAmit Kucheria#include <dt-bindings/thermal/thermal.h> 17e13c6d14SVinod Koul 18e13c6d14SVinod Koul/ { 19e13c6d14SVinod Koul interrupt-parent = <&intc>; 20e13c6d14SVinod Koul 21e13c6d14SVinod Koul #address-cells = <2>; 22e13c6d14SVinod Koul #size-cells = <2>; 23e13c6d14SVinod Koul 24e13c6d14SVinod Koul chosen { }; 25e13c6d14SVinod Koul 26e13c6d14SVinod Koul clocks { 27e13c6d14SVinod Koul xo_board: xo-board { 28e13c6d14SVinod Koul compatible = "fixed-clock"; 29e13c6d14SVinod Koul #clock-cells = <0>; 30e13c6d14SVinod Koul clock-frequency = <38400000>; 31e13c6d14SVinod Koul clock-output-names = "xo_board"; 32e13c6d14SVinod Koul }; 33e13c6d14SVinod Koul 34e13c6d14SVinod Koul sleep_clk: sleep-clk { 35e13c6d14SVinod Koul compatible = "fixed-clock"; 36e13c6d14SVinod Koul #clock-cells = <0>; 37e13c6d14SVinod Koul clock-frequency = <32764>; 38e13c6d14SVinod Koul clock-output-names = "sleep_clk"; 39e13c6d14SVinod Koul }; 40e13c6d14SVinod Koul }; 41e13c6d14SVinod Koul 42e13c6d14SVinod Koul cpus { 43e13c6d14SVinod Koul #address-cells = <2>; 44e13c6d14SVinod Koul #size-cells = <0>; 45e13c6d14SVinod Koul 46e13c6d14SVinod Koul CPU0: cpu@0 { 47e13c6d14SVinod Koul device_type = "cpu"; 48e13c6d14SVinod Koul compatible = "qcom,kryo485"; 49e13c6d14SVinod Koul reg = <0x0 0x0>; 50e13c6d14SVinod Koul enable-method = "psci"; 515b2dae72SDanny Lin capacity-dmips-mhz = <488>; 525b2dae72SDanny Lin dynamic-power-coefficient = <232>; 53e13c6d14SVinod Koul next-level-cache = <&L2_0>; 54fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 552b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 562b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 572b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 58b2e3f897SDanny Lin power-domains = <&CPU_PD0>; 59b2e3f897SDanny Lin power-domain-names = "psci"; 60d2fa630cSAmit Kucheria #cooling-cells = <2>; 61e13c6d14SVinod Koul L2_0: l2-cache { 62e13c6d14SVinod Koul compatible = "cache"; 63e13c6d14SVinod Koul next-level-cache = <&L3_0>; 64e13c6d14SVinod Koul L3_0: l3-cache { 65e13c6d14SVinod Koul compatible = "cache"; 66e13c6d14SVinod Koul }; 67e13c6d14SVinod Koul }; 68e13c6d14SVinod Koul }; 69e13c6d14SVinod Koul 70e13c6d14SVinod Koul CPU1: cpu@100 { 71e13c6d14SVinod Koul device_type = "cpu"; 72e13c6d14SVinod Koul compatible = "qcom,kryo485"; 73e13c6d14SVinod Koul reg = <0x0 0x100>; 74e13c6d14SVinod Koul enable-method = "psci"; 755b2dae72SDanny Lin capacity-dmips-mhz = <488>; 765b2dae72SDanny Lin dynamic-power-coefficient = <232>; 77e13c6d14SVinod Koul next-level-cache = <&L2_100>; 78fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 792b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 802b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 812b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 82b2e3f897SDanny Lin power-domains = <&CPU_PD1>; 83b2e3f897SDanny Lin power-domain-names = "psci"; 84d2fa630cSAmit Kucheria #cooling-cells = <2>; 85e13c6d14SVinod Koul L2_100: l2-cache { 86e13c6d14SVinod Koul compatible = "cache"; 87e13c6d14SVinod Koul next-level-cache = <&L3_0>; 88e13c6d14SVinod Koul }; 89e13c6d14SVinod Koul 90e13c6d14SVinod Koul }; 91e13c6d14SVinod Koul 92e13c6d14SVinod Koul CPU2: cpu@200 { 93e13c6d14SVinod Koul device_type = "cpu"; 94e13c6d14SVinod Koul compatible = "qcom,kryo485"; 95e13c6d14SVinod Koul reg = <0x0 0x200>; 96e13c6d14SVinod Koul enable-method = "psci"; 975b2dae72SDanny Lin capacity-dmips-mhz = <488>; 985b2dae72SDanny Lin dynamic-power-coefficient = <232>; 99e13c6d14SVinod Koul next-level-cache = <&L2_200>; 100fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1012b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1022b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1032b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 104b2e3f897SDanny Lin power-domains = <&CPU_PD2>; 105b2e3f897SDanny Lin power-domain-names = "psci"; 106d2fa630cSAmit Kucheria #cooling-cells = <2>; 107e13c6d14SVinod Koul L2_200: l2-cache { 108e13c6d14SVinod Koul compatible = "cache"; 109e13c6d14SVinod Koul next-level-cache = <&L3_0>; 110e13c6d14SVinod Koul }; 111e13c6d14SVinod Koul }; 112e13c6d14SVinod Koul 113e13c6d14SVinod Koul CPU3: cpu@300 { 114e13c6d14SVinod Koul device_type = "cpu"; 115e13c6d14SVinod Koul compatible = "qcom,kryo485"; 116e13c6d14SVinod Koul reg = <0x0 0x300>; 117e13c6d14SVinod Koul enable-method = "psci"; 1185b2dae72SDanny Lin capacity-dmips-mhz = <488>; 1195b2dae72SDanny Lin dynamic-power-coefficient = <232>; 120e13c6d14SVinod Koul next-level-cache = <&L2_300>; 121fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1222b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1232b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1242b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 125b2e3f897SDanny Lin power-domains = <&CPU_PD3>; 126b2e3f897SDanny Lin power-domain-names = "psci"; 127d2fa630cSAmit Kucheria #cooling-cells = <2>; 128e13c6d14SVinod Koul L2_300: l2-cache { 129e13c6d14SVinod Koul compatible = "cache"; 130e13c6d14SVinod Koul next-level-cache = <&L3_0>; 131e13c6d14SVinod Koul }; 132e13c6d14SVinod Koul }; 133e13c6d14SVinod Koul 134e13c6d14SVinod Koul CPU4: cpu@400 { 135e13c6d14SVinod Koul device_type = "cpu"; 136e13c6d14SVinod Koul compatible = "qcom,kryo485"; 137e13c6d14SVinod Koul reg = <0x0 0x400>; 138e13c6d14SVinod Koul enable-method = "psci"; 1395b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1405b2dae72SDanny Lin dynamic-power-coefficient = <369>; 141e13c6d14SVinod Koul next-level-cache = <&L2_400>; 142fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1432b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1442b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1452b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 146b2e3f897SDanny Lin power-domains = <&CPU_PD4>; 147b2e3f897SDanny Lin power-domain-names = "psci"; 148d2fa630cSAmit Kucheria #cooling-cells = <2>; 149e13c6d14SVinod Koul L2_400: l2-cache { 150e13c6d14SVinod Koul compatible = "cache"; 151e13c6d14SVinod Koul next-level-cache = <&L3_0>; 152e13c6d14SVinod Koul }; 153e13c6d14SVinod Koul }; 154e13c6d14SVinod Koul 155e13c6d14SVinod Koul CPU5: cpu@500 { 156e13c6d14SVinod Koul device_type = "cpu"; 157e13c6d14SVinod Koul compatible = "qcom,kryo485"; 158e13c6d14SVinod Koul reg = <0x0 0x500>; 159e13c6d14SVinod Koul enable-method = "psci"; 1605b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1615b2dae72SDanny Lin dynamic-power-coefficient = <369>; 162e13c6d14SVinod Koul next-level-cache = <&L2_500>; 163fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1642b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1652b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1662b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 167b2e3f897SDanny Lin power-domains = <&CPU_PD5>; 168b2e3f897SDanny Lin power-domain-names = "psci"; 169d2fa630cSAmit Kucheria #cooling-cells = <2>; 170e13c6d14SVinod Koul L2_500: l2-cache { 171e13c6d14SVinod Koul compatible = "cache"; 172e13c6d14SVinod Koul next-level-cache = <&L3_0>; 173e13c6d14SVinod Koul }; 174e13c6d14SVinod Koul }; 175e13c6d14SVinod Koul 176e13c6d14SVinod Koul CPU6: cpu@600 { 177e13c6d14SVinod Koul device_type = "cpu"; 178e13c6d14SVinod Koul compatible = "qcom,kryo485"; 179e13c6d14SVinod Koul reg = <0x0 0x600>; 180e13c6d14SVinod Koul enable-method = "psci"; 1815b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1825b2dae72SDanny Lin dynamic-power-coefficient = <369>; 183e13c6d14SVinod Koul next-level-cache = <&L2_600>; 184fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1852b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1862b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1872b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 188b2e3f897SDanny Lin power-domains = <&CPU_PD6>; 189b2e3f897SDanny Lin power-domain-names = "psci"; 190d2fa630cSAmit Kucheria #cooling-cells = <2>; 191e13c6d14SVinod Koul L2_600: l2-cache { 192e13c6d14SVinod Koul compatible = "cache"; 193e13c6d14SVinod Koul next-level-cache = <&L3_0>; 194e13c6d14SVinod Koul }; 195e13c6d14SVinod Koul }; 196e13c6d14SVinod Koul 197e13c6d14SVinod Koul CPU7: cpu@700 { 198e13c6d14SVinod Koul device_type = "cpu"; 199e13c6d14SVinod Koul compatible = "qcom,kryo485"; 200e13c6d14SVinod Koul reg = <0x0 0x700>; 201e13c6d14SVinod Koul enable-method = "psci"; 2025b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 2035b2dae72SDanny Lin dynamic-power-coefficient = <421>; 204e13c6d14SVinod Koul next-level-cache = <&L2_700>; 205fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 2>; 2062b6187abSThara Gopinath operating-points-v2 = <&cpu7_opp_table>; 2072b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 2082b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 209b2e3f897SDanny Lin power-domains = <&CPU_PD7>; 210b2e3f897SDanny Lin power-domain-names = "psci"; 211d2fa630cSAmit Kucheria #cooling-cells = <2>; 212e13c6d14SVinod Koul L2_700: l2-cache { 213e13c6d14SVinod Koul compatible = "cache"; 214e13c6d14SVinod Koul next-level-cache = <&L3_0>; 215e13c6d14SVinod Koul }; 216e13c6d14SVinod Koul }; 217066d21bcSDanny Lin 218066d21bcSDanny Lin cpu-map { 219066d21bcSDanny Lin cluster0 { 220066d21bcSDanny Lin core0 { 221066d21bcSDanny Lin cpu = <&CPU0>; 222066d21bcSDanny Lin }; 223066d21bcSDanny Lin 224066d21bcSDanny Lin core1 { 225066d21bcSDanny Lin cpu = <&CPU1>; 226066d21bcSDanny Lin }; 227066d21bcSDanny Lin 228066d21bcSDanny Lin core2 { 229066d21bcSDanny Lin cpu = <&CPU2>; 230066d21bcSDanny Lin }; 231066d21bcSDanny Lin 232066d21bcSDanny Lin core3 { 233066d21bcSDanny Lin cpu = <&CPU3>; 234066d21bcSDanny Lin }; 235066d21bcSDanny Lin 236066d21bcSDanny Lin core4 { 237066d21bcSDanny Lin cpu = <&CPU4>; 238066d21bcSDanny Lin }; 239066d21bcSDanny Lin 240066d21bcSDanny Lin core5 { 241066d21bcSDanny Lin cpu = <&CPU5>; 242066d21bcSDanny Lin }; 243066d21bcSDanny Lin 244066d21bcSDanny Lin core6 { 245066d21bcSDanny Lin cpu = <&CPU6>; 246066d21bcSDanny Lin }; 247066d21bcSDanny Lin 248066d21bcSDanny Lin core7 { 249066d21bcSDanny Lin cpu = <&CPU7>; 250066d21bcSDanny Lin }; 251066d21bcSDanny Lin }; 252066d21bcSDanny Lin }; 25381188f58SDanny Lin 25481188f58SDanny Lin idle-states { 25581188f58SDanny Lin entry-method = "psci"; 25681188f58SDanny Lin 25781188f58SDanny Lin LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 25881188f58SDanny Lin compatible = "arm,idle-state"; 25981188f58SDanny Lin idle-state-name = "little-rail-power-collapse"; 26081188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 26181188f58SDanny Lin entry-latency-us = <355>; 26281188f58SDanny Lin exit-latency-us = <909>; 26381188f58SDanny Lin min-residency-us = <3934>; 26481188f58SDanny Lin local-timer-stop; 26581188f58SDanny Lin }; 26681188f58SDanny Lin 26781188f58SDanny Lin BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 26881188f58SDanny Lin compatible = "arm,idle-state"; 26981188f58SDanny Lin idle-state-name = "big-rail-power-collapse"; 27081188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 27181188f58SDanny Lin entry-latency-us = <241>; 27281188f58SDanny Lin exit-latency-us = <1461>; 27381188f58SDanny Lin min-residency-us = <4488>; 27481188f58SDanny Lin local-timer-stop; 27581188f58SDanny Lin }; 276b2e3f897SDanny Lin }; 27781188f58SDanny Lin 278b2e3f897SDanny Lin domain-idle-states { 27981188f58SDanny Lin CLUSTER_SLEEP_0: cluster-sleep-0 { 280b2e3f897SDanny Lin compatible = "domain-idle-state"; 28181188f58SDanny Lin idle-state-name = "cluster-power-collapse"; 282b2e3f897SDanny Lin arm,psci-suspend-param = <0x4100c244>; 28381188f58SDanny Lin entry-latency-us = <3263>; 28481188f58SDanny Lin exit-latency-us = <6562>; 28581188f58SDanny Lin min-residency-us = <9987>; 28681188f58SDanny Lin local-timer-stop; 28781188f58SDanny Lin }; 28881188f58SDanny Lin }; 289e13c6d14SVinod Koul }; 290e13c6d14SVinod Koul 2910e3e6546SKrzysztof Kozlowski cpu0_opp_table: opp-table-cpu0 { 2922b6187abSThara Gopinath compatible = "operating-points-v2"; 2932b6187abSThara Gopinath opp-shared; 2942b6187abSThara Gopinath 2952b6187abSThara Gopinath cpu0_opp1: opp-300000000 { 2962b6187abSThara Gopinath opp-hz = /bits/ 64 <300000000>; 2972b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 2982b6187abSThara Gopinath }; 2992b6187abSThara Gopinath 3002b6187abSThara Gopinath cpu0_opp2: opp-403200000 { 3012b6187abSThara Gopinath opp-hz = /bits/ 64 <403200000>; 3022b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 3032b6187abSThara Gopinath }; 3042b6187abSThara Gopinath 3052b6187abSThara Gopinath cpu0_opp3: opp-499200000 { 3062b6187abSThara Gopinath opp-hz = /bits/ 64 <499200000>; 3072b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3082b6187abSThara Gopinath }; 3092b6187abSThara Gopinath 3102b6187abSThara Gopinath cpu0_opp4: opp-576000000 { 3112b6187abSThara Gopinath opp-hz = /bits/ 64 <576000000>; 3122b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3132b6187abSThara Gopinath }; 3142b6187abSThara Gopinath 3152b6187abSThara Gopinath cpu0_opp5: opp-672000000 { 3162b6187abSThara Gopinath opp-hz = /bits/ 64 <672000000>; 3172b6187abSThara Gopinath opp-peak-kBps = <800000 15974400>; 3182b6187abSThara Gopinath }; 3192b6187abSThara Gopinath 3202b6187abSThara Gopinath cpu0_opp6: opp-768000000 { 321ce3b50cfSThara Gopinath opp-hz = /bits/ 64 <768000000>; 3222b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3232b6187abSThara Gopinath }; 3242b6187abSThara Gopinath 3252b6187abSThara Gopinath cpu0_opp7: opp-844800000 { 3262b6187abSThara Gopinath opp-hz = /bits/ 64 <844800000>; 3272b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3282b6187abSThara Gopinath }; 3292b6187abSThara Gopinath 3302b6187abSThara Gopinath cpu0_opp8: opp-940800000 { 3312b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 3322b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3332b6187abSThara Gopinath }; 3342b6187abSThara Gopinath 3352b6187abSThara Gopinath cpu0_opp9: opp-1036800000 { 3362b6187abSThara Gopinath opp-hz = /bits/ 64 <1036800000>; 3372b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3382b6187abSThara Gopinath }; 3392b6187abSThara Gopinath 3402b6187abSThara Gopinath cpu0_opp10: opp-1113600000 { 3412b6187abSThara Gopinath opp-hz = /bits/ 64 <1113600000>; 3422b6187abSThara Gopinath opp-peak-kBps = <2188000 25804800>; 3432b6187abSThara Gopinath }; 3442b6187abSThara Gopinath 3452b6187abSThara Gopinath cpu0_opp11: opp-1209600000 { 3462b6187abSThara Gopinath opp-hz = /bits/ 64 <1209600000>; 3472b6187abSThara Gopinath opp-peak-kBps = <2188000 31948800>; 3482b6187abSThara Gopinath }; 3492b6187abSThara Gopinath 3502b6187abSThara Gopinath cpu0_opp12: opp-1305600000 { 3512b6187abSThara Gopinath opp-hz = /bits/ 64 <1305600000>; 3522b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3532b6187abSThara Gopinath }; 3542b6187abSThara Gopinath 3552b6187abSThara Gopinath cpu0_opp13: opp-1382400000 { 3562b6187abSThara Gopinath opp-hz = /bits/ 64 <1382400000>; 3572b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3582b6187abSThara Gopinath }; 3592b6187abSThara Gopinath 3602b6187abSThara Gopinath cpu0_opp14: opp-1478400000 { 3612b6187abSThara Gopinath opp-hz = /bits/ 64 <1478400000>; 3622b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3632b6187abSThara Gopinath }; 3642b6187abSThara Gopinath 3652b6187abSThara Gopinath cpu0_opp15: opp-1555200000 { 3662b6187abSThara Gopinath opp-hz = /bits/ 64 <1555200000>; 3672b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3682b6187abSThara Gopinath }; 3692b6187abSThara Gopinath 3702b6187abSThara Gopinath cpu0_opp16: opp-1632000000 { 3712b6187abSThara Gopinath opp-hz = /bits/ 64 <1632000000>; 3722b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3732b6187abSThara Gopinath }; 3742b6187abSThara Gopinath 3752b6187abSThara Gopinath cpu0_opp17: opp-1708800000 { 3762b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 3772b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 3782b6187abSThara Gopinath }; 3792b6187abSThara Gopinath 3802b6187abSThara Gopinath cpu0_opp18: opp-1785600000 { 3812b6187abSThara Gopinath opp-hz = /bits/ 64 <1785600000>; 3822b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 3832b6187abSThara Gopinath }; 3842b6187abSThara Gopinath }; 3852b6187abSThara Gopinath 3860e3e6546SKrzysztof Kozlowski cpu4_opp_table: opp-table-cpu4 { 3872b6187abSThara Gopinath compatible = "operating-points-v2"; 3882b6187abSThara Gopinath opp-shared; 3892b6187abSThara Gopinath 3902b6187abSThara Gopinath cpu4_opp1: opp-710400000 { 3912b6187abSThara Gopinath opp-hz = /bits/ 64 <710400000>; 3922b6187abSThara Gopinath opp-peak-kBps = <1804000 15974400>; 3932b6187abSThara Gopinath }; 3942b6187abSThara Gopinath 3952b6187abSThara Gopinath cpu4_opp2: opp-825600000 { 3962b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 3972b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 3982b6187abSThara Gopinath }; 3992b6187abSThara Gopinath 4002b6187abSThara Gopinath cpu4_opp3: opp-940800000 { 4012b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 4022b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 4032b6187abSThara Gopinath }; 4042b6187abSThara Gopinath 4052b6187abSThara Gopinath cpu4_opp4: opp-1056000000 { 4062b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 4072b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 4082b6187abSThara Gopinath }; 4092b6187abSThara Gopinath 4102b6187abSThara Gopinath cpu4_opp5: opp-1171200000 { 4112b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 4122b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 4132b6187abSThara Gopinath }; 4142b6187abSThara Gopinath 4152b6187abSThara Gopinath cpu4_opp6: opp-1286400000 { 4162b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 4172b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4182b6187abSThara Gopinath }; 4192b6187abSThara Gopinath 4202b6187abSThara Gopinath cpu4_opp7: opp-1401600000 { 4212b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 4222b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4232b6187abSThara Gopinath }; 4242b6187abSThara Gopinath 4252b6187abSThara Gopinath cpu4_opp8: opp-1497600000 { 4262b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 4272b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4282b6187abSThara Gopinath }; 4292b6187abSThara Gopinath 4302b6187abSThara Gopinath cpu4_opp9: opp-1612800000 { 4312b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 4322b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4332b6187abSThara Gopinath }; 4342b6187abSThara Gopinath 4352b6187abSThara Gopinath cpu4_opp10: opp-1708800000 { 4362b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 4372b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 4382b6187abSThara Gopinath }; 4392b6187abSThara Gopinath 4402b6187abSThara Gopinath cpu4_opp11: opp-1804800000 { 4412b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 4422b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 4432b6187abSThara Gopinath }; 4442b6187abSThara Gopinath 4452b6187abSThara Gopinath cpu4_opp12: opp-1920000000 { 4462b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 4472b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 4482b6187abSThara Gopinath }; 4492b6187abSThara Gopinath 4502b6187abSThara Gopinath cpu4_opp13: opp-2016000000 { 4512b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 4522b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 4532b6187abSThara Gopinath }; 4542b6187abSThara Gopinath 4552b6187abSThara Gopinath cpu4_opp14: opp-2131200000 { 4562b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 4572b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 4582b6187abSThara Gopinath }; 4592b6187abSThara Gopinath 4602b6187abSThara Gopinath cpu4_opp15: opp-2227200000 { 4612b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 4622b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4632b6187abSThara Gopinath }; 4642b6187abSThara Gopinath 4652b6187abSThara Gopinath cpu4_opp16: opp-2323200000 { 4662b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 4672b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4682b6187abSThara Gopinath }; 4692b6187abSThara Gopinath 4702b6187abSThara Gopinath cpu4_opp17: opp-2419200000 { 4712b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 4722b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4732b6187abSThara Gopinath }; 4742b6187abSThara Gopinath }; 4752b6187abSThara Gopinath 4760e3e6546SKrzysztof Kozlowski cpu7_opp_table: opp-table-cpu7 { 4772b6187abSThara Gopinath compatible = "operating-points-v2"; 4782b6187abSThara Gopinath opp-shared; 4792b6187abSThara Gopinath 4802b6187abSThara Gopinath cpu7_opp1: opp-825600000 { 4812b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 4822b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 4832b6187abSThara Gopinath }; 4842b6187abSThara Gopinath 4852b6187abSThara Gopinath cpu7_opp2: opp-940800000 { 4862b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 4872b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 4882b6187abSThara Gopinath }; 4892b6187abSThara Gopinath 4902b6187abSThara Gopinath cpu7_opp3: opp-1056000000 { 4912b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 4922b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 4932b6187abSThara Gopinath }; 4942b6187abSThara Gopinath 4952b6187abSThara Gopinath cpu7_opp4: opp-1171200000 { 4962b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 4972b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 4982b6187abSThara Gopinath }; 4992b6187abSThara Gopinath 5002b6187abSThara Gopinath cpu7_opp5: opp-1286400000 { 5012b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 5022b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5032b6187abSThara Gopinath }; 5042b6187abSThara Gopinath 5052b6187abSThara Gopinath cpu7_opp6: opp-1401600000 { 5062b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 5072b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5082b6187abSThara Gopinath }; 5092b6187abSThara Gopinath 5102b6187abSThara Gopinath cpu7_opp7: opp-1497600000 { 5112b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 5122b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5132b6187abSThara Gopinath }; 5142b6187abSThara Gopinath 5152b6187abSThara Gopinath cpu7_opp8: opp-1612800000 { 5162b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 5172b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5182b6187abSThara Gopinath }; 5192b6187abSThara Gopinath 5202b6187abSThara Gopinath cpu7_opp9: opp-1708800000 { 5212b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 5222b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 5232b6187abSThara Gopinath }; 5242b6187abSThara Gopinath 5252b6187abSThara Gopinath cpu7_opp10: opp-1804800000 { 5262b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 5272b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 5282b6187abSThara Gopinath }; 5292b6187abSThara Gopinath 5302b6187abSThara Gopinath cpu7_opp11: opp-1920000000 { 5312b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 5322b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 5332b6187abSThara Gopinath }; 5342b6187abSThara Gopinath 5352b6187abSThara Gopinath cpu7_opp12: opp-2016000000 { 5362b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 5372b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 5382b6187abSThara Gopinath }; 5392b6187abSThara Gopinath 5402b6187abSThara Gopinath cpu7_opp13: opp-2131200000 { 5412b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 5422b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 5432b6187abSThara Gopinath }; 5442b6187abSThara Gopinath 5452b6187abSThara Gopinath cpu7_opp14: opp-2227200000 { 5462b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 5472b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5482b6187abSThara Gopinath }; 5492b6187abSThara Gopinath 5502b6187abSThara Gopinath cpu7_opp15: opp-2323200000 { 5512b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 5522b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5532b6187abSThara Gopinath }; 5542b6187abSThara Gopinath 5552b6187abSThara Gopinath cpu7_opp16: opp-2419200000 { 5562b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 5572b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5582b6187abSThara Gopinath }; 5592b6187abSThara Gopinath 5602b6187abSThara Gopinath cpu7_opp17: opp-2534400000 { 5612b6187abSThara Gopinath opp-hz = /bits/ 64 <2534400000>; 5622b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5632b6187abSThara Gopinath }; 5642b6187abSThara Gopinath 5652b6187abSThara Gopinath cpu7_opp18: opp-2649600000 { 5662b6187abSThara Gopinath opp-hz = /bits/ 64 <2649600000>; 5672b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5682b6187abSThara Gopinath }; 5692b6187abSThara Gopinath 5702b6187abSThara Gopinath cpu7_opp19: opp-2745600000 { 5712b6187abSThara Gopinath opp-hz = /bits/ 64 <2745600000>; 5722b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5732b6187abSThara Gopinath }; 5742b6187abSThara Gopinath 5752b6187abSThara Gopinath cpu7_opp20: opp-2841600000 { 5762b6187abSThara Gopinath opp-hz = /bits/ 64 <2841600000>; 5772b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5782b6187abSThara Gopinath }; 5792b6187abSThara Gopinath }; 5802b6187abSThara Gopinath 581e13c6d14SVinod Koul firmware { 582e13c6d14SVinod Koul scm: scm { 583e13c6d14SVinod Koul compatible = "qcom,scm-sm8150", "qcom,scm"; 584e13c6d14SVinod Koul #reset-cells = <1>; 585e13c6d14SVinod Koul }; 586e13c6d14SVinod Koul }; 587e13c6d14SVinod Koul 588d8cf9372SVinod Koul tcsr_mutex: hwlock { 589d8cf9372SVinod Koul compatible = "qcom,tcsr-mutex"; 590d8cf9372SVinod Koul syscon = <&tcsr_mutex_regs 0 0x1000>; 591d8cf9372SVinod Koul #hwlock-cells = <1>; 592d8cf9372SVinod Koul }; 593d8cf9372SVinod Koul 594e13c6d14SVinod Koul memory@80000000 { 595e13c6d14SVinod Koul device_type = "memory"; 596e13c6d14SVinod Koul /* We expect the bootloader to fill in the size */ 597e13c6d14SVinod Koul reg = <0x0 0x80000000 0x0 0x0>; 598e13c6d14SVinod Koul }; 599e13c6d14SVinod Koul 600d8cf9372SVinod Koul pmu { 601d8cf9372SVinod Koul compatible = "arm,armv8-pmuv3"; 602d8cf9372SVinod Koul interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 603d8cf9372SVinod Koul }; 604d8cf9372SVinod Koul 605e13c6d14SVinod Koul psci { 606e13c6d14SVinod Koul compatible = "arm,psci-1.0"; 607e13c6d14SVinod Koul method = "smc"; 608b2e3f897SDanny Lin 609b2e3f897SDanny Lin CPU_PD0: cpu0 { 610b2e3f897SDanny Lin #power-domain-cells = <0>; 611b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 612b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 613b2e3f897SDanny Lin }; 614b2e3f897SDanny Lin 615b2e3f897SDanny Lin CPU_PD1: cpu1 { 616b2e3f897SDanny Lin #power-domain-cells = <0>; 617b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 618b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 619b2e3f897SDanny Lin }; 620b2e3f897SDanny Lin 621b2e3f897SDanny Lin CPU_PD2: cpu2 { 622b2e3f897SDanny Lin #power-domain-cells = <0>; 623b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 624b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 625b2e3f897SDanny Lin }; 626b2e3f897SDanny Lin 627b2e3f897SDanny Lin CPU_PD3: cpu3 { 628b2e3f897SDanny Lin #power-domain-cells = <0>; 629b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 630b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 631b2e3f897SDanny Lin }; 632b2e3f897SDanny Lin 633b2e3f897SDanny Lin CPU_PD4: cpu4 { 634b2e3f897SDanny Lin #power-domain-cells = <0>; 635b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 636b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 637b2e3f897SDanny Lin }; 638b2e3f897SDanny Lin 639b2e3f897SDanny Lin CPU_PD5: cpu5 { 640b2e3f897SDanny Lin #power-domain-cells = <0>; 641b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 642b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 643b2e3f897SDanny Lin }; 644b2e3f897SDanny Lin 645b2e3f897SDanny Lin CPU_PD6: cpu6 { 646b2e3f897SDanny Lin #power-domain-cells = <0>; 647b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 648b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 649b2e3f897SDanny Lin }; 650b2e3f897SDanny Lin 651b2e3f897SDanny Lin CPU_PD7: cpu7 { 652b2e3f897SDanny Lin #power-domain-cells = <0>; 653b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 654b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 655b2e3f897SDanny Lin }; 656b2e3f897SDanny Lin 657b2e3f897SDanny Lin CLUSTER_PD: cpu-cluster0 { 658b2e3f897SDanny Lin #power-domain-cells = <0>; 659b2e3f897SDanny Lin domain-idle-states = <&CLUSTER_SLEEP_0>; 660b2e3f897SDanny Lin }; 661e13c6d14SVinod Koul }; 662e13c6d14SVinod Koul 663912c373aSVinod Koul reserved-memory { 664912c373aSVinod Koul #address-cells = <2>; 665912c373aSVinod Koul #size-cells = <2>; 666912c373aSVinod Koul ranges; 667912c373aSVinod Koul 668912c373aSVinod Koul hyp_mem: memory@85700000 { 669912c373aSVinod Koul reg = <0x0 0x85700000 0x0 0x600000>; 670912c373aSVinod Koul no-map; 671912c373aSVinod Koul }; 672912c373aSVinod Koul 673912c373aSVinod Koul xbl_mem: memory@85d00000 { 674912c373aSVinod Koul reg = <0x0 0x85d00000 0x0 0x140000>; 675912c373aSVinod Koul no-map; 676912c373aSVinod Koul }; 677912c373aSVinod Koul 678912c373aSVinod Koul aop_mem: memory@85f00000 { 679912c373aSVinod Koul reg = <0x0 0x85f00000 0x0 0x20000>; 680912c373aSVinod Koul no-map; 681912c373aSVinod Koul }; 682912c373aSVinod Koul 683912c373aSVinod Koul aop_cmd_db: memory@85f20000 { 684912c373aSVinod Koul compatible = "qcom,cmd-db"; 685912c373aSVinod Koul reg = <0x0 0x85f20000 0x0 0x20000>; 686912c373aSVinod Koul no-map; 687912c373aSVinod Koul }; 688912c373aSVinod Koul 689912c373aSVinod Koul smem_mem: memory@86000000 { 690912c373aSVinod Koul reg = <0x0 0x86000000 0x0 0x200000>; 691912c373aSVinod Koul no-map; 692912c373aSVinod Koul }; 693912c373aSVinod Koul 694912c373aSVinod Koul tz_mem: memory@86200000 { 695912c373aSVinod Koul reg = <0x0 0x86200000 0x0 0x3900000>; 696912c373aSVinod Koul no-map; 697912c373aSVinod Koul }; 698912c373aSVinod Koul 699912c373aSVinod Koul rmtfs_mem: memory@89b00000 { 700912c373aSVinod Koul compatible = "qcom,rmtfs-mem"; 701912c373aSVinod Koul reg = <0x0 0x89b00000 0x0 0x200000>; 702912c373aSVinod Koul no-map; 703912c373aSVinod Koul 704912c373aSVinod Koul qcom,client-id = <1>; 705912c373aSVinod Koul qcom,vmid = <15>; 706912c373aSVinod Koul }; 707912c373aSVinod Koul 708912c373aSVinod Koul camera_mem: memory@8b700000 { 709912c373aSVinod Koul reg = <0x0 0x8b700000 0x0 0x500000>; 710912c373aSVinod Koul no-map; 711912c373aSVinod Koul }; 712912c373aSVinod Koul 713912c373aSVinod Koul wlan_mem: memory@8bc00000 { 714912c373aSVinod Koul reg = <0x0 0x8bc00000 0x0 0x180000>; 715912c373aSVinod Koul no-map; 716912c373aSVinod Koul }; 717912c373aSVinod Koul 718912c373aSVinod Koul npu_mem: memory@8bd80000 { 719912c373aSVinod Koul reg = <0x0 0x8bd80000 0x0 0x80000>; 720912c373aSVinod Koul no-map; 721912c373aSVinod Koul }; 722912c373aSVinod Koul 723912c373aSVinod Koul adsp_mem: memory@8be00000 { 724912c373aSVinod Koul reg = <0x0 0x8be00000 0x0 0x1a00000>; 725912c373aSVinod Koul no-map; 726912c373aSVinod Koul }; 727912c373aSVinod Koul 728912c373aSVinod Koul mpss_mem: memory@8d800000 { 729912c373aSVinod Koul reg = <0x0 0x8d800000 0x0 0x9600000>; 730912c373aSVinod Koul no-map; 731912c373aSVinod Koul }; 732912c373aSVinod Koul 733912c373aSVinod Koul venus_mem: memory@96e00000 { 734912c373aSVinod Koul reg = <0x0 0x96e00000 0x0 0x500000>; 735912c373aSVinod Koul no-map; 736912c373aSVinod Koul }; 737912c373aSVinod Koul 738912c373aSVinod Koul slpi_mem: memory@97300000 { 739912c373aSVinod Koul reg = <0x0 0x97300000 0x0 0x1400000>; 740912c373aSVinod Koul no-map; 741912c373aSVinod Koul }; 742912c373aSVinod Koul 743912c373aSVinod Koul ipa_fw_mem: memory@98700000 { 744912c373aSVinod Koul reg = <0x0 0x98700000 0x0 0x10000>; 745912c373aSVinod Koul no-map; 746912c373aSVinod Koul }; 747912c373aSVinod Koul 748912c373aSVinod Koul ipa_gsi_mem: memory@98710000 { 749912c373aSVinod Koul reg = <0x0 0x98710000 0x0 0x5000>; 750912c373aSVinod Koul no-map; 751912c373aSVinod Koul }; 752912c373aSVinod Koul 753912c373aSVinod Koul gpu_mem: memory@98715000 { 754912c373aSVinod Koul reg = <0x0 0x98715000 0x0 0x2000>; 755912c373aSVinod Koul no-map; 756912c373aSVinod Koul }; 757912c373aSVinod Koul 758912c373aSVinod Koul spss_mem: memory@98800000 { 759912c373aSVinod Koul reg = <0x0 0x98800000 0x0 0x100000>; 760912c373aSVinod Koul no-map; 761912c373aSVinod Koul }; 762912c373aSVinod Koul 763912c373aSVinod Koul cdsp_mem: memory@98900000 { 764912c373aSVinod Koul reg = <0x0 0x98900000 0x0 0x1400000>; 765912c373aSVinod Koul no-map; 766912c373aSVinod Koul }; 767912c373aSVinod Koul 768912c373aSVinod Koul qseecom_mem: memory@9e400000 { 769912c373aSVinod Koul reg = <0x0 0x9e400000 0x0 0x1400000>; 770912c373aSVinod Koul no-map; 771912c373aSVinod Koul }; 772912c373aSVinod Koul }; 773912c373aSVinod Koul 774d8cf9372SVinod Koul smem { 775d8cf9372SVinod Koul compatible = "qcom,smem"; 776d8cf9372SVinod Koul memory-region = <&smem_mem>; 777d8cf9372SVinod Koul hwlocks = <&tcsr_mutex 3>; 778d8cf9372SVinod Koul }; 779d8cf9372SVinod Koul 78061025b81SSibi Sankar smp2p-cdsp { 78161025b81SSibi Sankar compatible = "qcom,smp2p"; 78261025b81SSibi Sankar qcom,smem = <94>, <432>; 78361025b81SSibi Sankar 78461025b81SSibi Sankar interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 78561025b81SSibi Sankar 78661025b81SSibi Sankar mboxes = <&apss_shared 6>; 78761025b81SSibi Sankar 78861025b81SSibi Sankar qcom,local-pid = <0>; 78961025b81SSibi Sankar qcom,remote-pid = <5>; 79061025b81SSibi Sankar 79161025b81SSibi Sankar cdsp_smp2p_out: master-kernel { 79261025b81SSibi Sankar qcom,entry-name = "master-kernel"; 79361025b81SSibi Sankar #qcom,smem-state-cells = <1>; 79461025b81SSibi Sankar }; 79561025b81SSibi Sankar 79661025b81SSibi Sankar cdsp_smp2p_in: slave-kernel { 79761025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 79861025b81SSibi Sankar 79961025b81SSibi Sankar interrupt-controller; 80061025b81SSibi Sankar #interrupt-cells = <2>; 80161025b81SSibi Sankar }; 80261025b81SSibi Sankar }; 80361025b81SSibi Sankar 80461025b81SSibi Sankar smp2p-lpass { 80561025b81SSibi Sankar compatible = "qcom,smp2p"; 80661025b81SSibi Sankar qcom,smem = <443>, <429>; 80761025b81SSibi Sankar 80861025b81SSibi Sankar interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 80961025b81SSibi Sankar 81061025b81SSibi Sankar mboxes = <&apss_shared 10>; 81161025b81SSibi Sankar 81261025b81SSibi Sankar qcom,local-pid = <0>; 81361025b81SSibi Sankar qcom,remote-pid = <2>; 81461025b81SSibi Sankar 81561025b81SSibi Sankar adsp_smp2p_out: master-kernel { 81661025b81SSibi Sankar qcom,entry-name = "master-kernel"; 81761025b81SSibi Sankar #qcom,smem-state-cells = <1>; 81861025b81SSibi Sankar }; 81961025b81SSibi Sankar 82061025b81SSibi Sankar adsp_smp2p_in: slave-kernel { 82161025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 82261025b81SSibi Sankar 82361025b81SSibi Sankar interrupt-controller; 82461025b81SSibi Sankar #interrupt-cells = <2>; 82561025b81SSibi Sankar }; 82661025b81SSibi Sankar }; 82761025b81SSibi Sankar 82861025b81SSibi Sankar smp2p-mpss { 82961025b81SSibi Sankar compatible = "qcom,smp2p"; 83061025b81SSibi Sankar qcom,smem = <435>, <428>; 83161025b81SSibi Sankar 83261025b81SSibi Sankar interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 83361025b81SSibi Sankar 83461025b81SSibi Sankar mboxes = <&apss_shared 14>; 83561025b81SSibi Sankar 83661025b81SSibi Sankar qcom,local-pid = <0>; 83761025b81SSibi Sankar qcom,remote-pid = <1>; 83861025b81SSibi Sankar 83961025b81SSibi Sankar modem_smp2p_out: master-kernel { 84061025b81SSibi Sankar qcom,entry-name = "master-kernel"; 84161025b81SSibi Sankar #qcom,smem-state-cells = <1>; 84261025b81SSibi Sankar }; 84361025b81SSibi Sankar 84461025b81SSibi Sankar modem_smp2p_in: slave-kernel { 84561025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 84661025b81SSibi Sankar 84761025b81SSibi Sankar interrupt-controller; 84861025b81SSibi Sankar #interrupt-cells = <2>; 84961025b81SSibi Sankar }; 85061025b81SSibi Sankar }; 85161025b81SSibi Sankar 85261025b81SSibi Sankar smp2p-slpi { 85361025b81SSibi Sankar compatible = "qcom,smp2p"; 85461025b81SSibi Sankar qcom,smem = <481>, <430>; 85561025b81SSibi Sankar 85661025b81SSibi Sankar interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 85761025b81SSibi Sankar 85861025b81SSibi Sankar mboxes = <&apss_shared 26>; 85961025b81SSibi Sankar 86061025b81SSibi Sankar qcom,local-pid = <0>; 86161025b81SSibi Sankar qcom,remote-pid = <3>; 86261025b81SSibi Sankar 86361025b81SSibi Sankar slpi_smp2p_out: master-kernel { 86461025b81SSibi Sankar qcom,entry-name = "master-kernel"; 86561025b81SSibi Sankar #qcom,smem-state-cells = <1>; 86661025b81SSibi Sankar }; 86761025b81SSibi Sankar 86861025b81SSibi Sankar slpi_smp2p_in: slave-kernel { 86961025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 87061025b81SSibi Sankar 87161025b81SSibi Sankar interrupt-controller; 87261025b81SSibi Sankar #interrupt-cells = <2>; 87361025b81SSibi Sankar }; 87461025b81SSibi Sankar }; 87561025b81SSibi Sankar 876e13c6d14SVinod Koul soc: soc@0 { 877e13c6d14SVinod Koul #address-cells = <2>; 878e13c6d14SVinod Koul #size-cells = <2>; 879e13c6d14SVinod Koul ranges = <0 0 0 0 0x10 0>; 880e13c6d14SVinod Koul dma-ranges = <0 0 0 0 0x10 0>; 881e13c6d14SVinod Koul compatible = "simple-bus"; 882e13c6d14SVinod Koul 883e13c6d14SVinod Koul gcc: clock-controller@100000 { 884e13c6d14SVinod Koul compatible = "qcom,gcc-sm8150"; 885e13c6d14SVinod Koul reg = <0x0 0x00100000 0x0 0x1f0000>; 886e13c6d14SVinod Koul #clock-cells = <1>; 887e13c6d14SVinod Koul #reset-cells = <1>; 888e13c6d14SVinod Koul #power-domain-cells = <1>; 889e13c6d14SVinod Koul clock-names = "bi_tcxo", 890e13c6d14SVinod Koul "sleep_clk"; 891e13c6d14SVinod Koul clocks = <&rpmhcc RPMH_CXO_CLK>, 892e13c6d14SVinod Koul <&sleep_clk>; 893e13c6d14SVinod Koul }; 894e13c6d14SVinod Koul 89505006290SFelipe Balbi gpi_dma0: dma-controller@800000 { 89605006290SFelipe Balbi compatible = "qcom,sm8150-gpi-dma"; 89705006290SFelipe Balbi reg = <0 0x800000 0 0x60000>; 89805006290SFelipe Balbi interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 89905006290SFelipe Balbi <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 90005006290SFelipe Balbi <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 90105006290SFelipe Balbi <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 90205006290SFelipe Balbi <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 90305006290SFelipe Balbi <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 90405006290SFelipe Balbi <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 90505006290SFelipe Balbi <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 90605006290SFelipe Balbi <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 90705006290SFelipe Balbi <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 90805006290SFelipe Balbi <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 90905006290SFelipe Balbi <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 91005006290SFelipe Balbi <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 91105006290SFelipe Balbi dma-channels = <13>; 91205006290SFelipe Balbi dma-channel-mask = <0xfa>; 91305006290SFelipe Balbi iommus = <&apps_smmu 0x00d6 0x0>; 91405006290SFelipe Balbi #dma-cells = <3>; 91505006290SFelipe Balbi status = "disabled"; 91605006290SFelipe Balbi }; 91705006290SFelipe Balbi 91805f333b7SVinod Koul ethernet: ethernet@20000 { 91905f333b7SVinod Koul compatible = "qcom,sm8150-ethqos"; 92005f333b7SVinod Koul reg = <0x0 0x00020000 0x0 0x10000>, 92105f333b7SVinod Koul <0x0 0x00036000 0x0 0x100>; 92205f333b7SVinod Koul reg-names = "stmmaceth", "rgmii"; 92305f333b7SVinod Koul clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 92405f333b7SVinod Koul clocks = <&gcc GCC_EMAC_AXI_CLK>, 92505f333b7SVinod Koul <&gcc GCC_EMAC_SLV_AHB_CLK>, 92605f333b7SVinod Koul <&gcc GCC_EMAC_PTP_CLK>, 92705f333b7SVinod Koul <&gcc GCC_EMAC_RGMII_CLK>; 92805f333b7SVinod Koul interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 92905f333b7SVinod Koul <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 93005f333b7SVinod Koul interrupt-names = "macirq", "eth_lpi"; 93105f333b7SVinod Koul 93205f333b7SVinod Koul power-domains = <&gcc EMAC_GDSC>; 93305f333b7SVinod Koul resets = <&gcc GCC_EMAC_BCR>; 93405f333b7SVinod Koul 93505f333b7SVinod Koul iommus = <&apps_smmu 0x3C0 0x0>; 93605f333b7SVinod Koul 93705f333b7SVinod Koul snps,tso; 93805f333b7SVinod Koul rx-fifo-depth = <4096>; 93905f333b7SVinod Koul tx-fifo-depth = <4096>; 94005f333b7SVinod Koul 94105f333b7SVinod Koul status = "disabled"; 94205f333b7SVinod Koul }; 94305f333b7SVinod Koul 94405f333b7SVinod Koul 9459cf3ebd1SCaleb Connolly qupv3_id_0: geniqup@8c0000 { 9469cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 9479cf3ebd1SCaleb Connolly reg = <0x0 0x008c0000 0x0 0x6000>; 9489cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 9499cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 9509cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 9519cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0xc3 0x0>; 9529cf3ebd1SCaleb Connolly #address-cells = <2>; 9539cf3ebd1SCaleb Connolly #size-cells = <2>; 9549cf3ebd1SCaleb Connolly ranges; 9559cf3ebd1SCaleb Connolly status = "disabled"; 95681bee695SCaleb Connolly 95781bee695SCaleb Connolly i2c0: i2c@880000 { 95881bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 95981bee695SCaleb Connolly reg = <0 0x00880000 0 0x4000>; 96081bee695SCaleb Connolly clock-names = "se"; 96181bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 962abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 963abdd4b7aSFelipe Balbi <&gpi_dma0 1 0 QCOM_GPI_I2C>; 964abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 96581bee695SCaleb Connolly pinctrl-names = "default"; 96681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c0_default>; 96781bee695SCaleb Connolly interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 96881bee695SCaleb Connolly #address-cells = <1>; 96981bee695SCaleb Connolly #size-cells = <0>; 97081bee695SCaleb Connolly status = "disabled"; 97181bee695SCaleb Connolly }; 97281bee695SCaleb Connolly 973129e1c96SFelipe Balbi spi0: spi@880000 { 974129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 975129e1c96SFelipe Balbi reg = <0 0x880000 0 0x4000>; 976129e1c96SFelipe Balbi reg-names = "se"; 977129e1c96SFelipe Balbi clock-names = "se"; 978129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 979abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 980abdd4b7aSFelipe Balbi <&gpi_dma0 1 0 QCOM_GPI_SPI>; 981abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 982129e1c96SFelipe Balbi pinctrl-names = "default"; 983129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi0_default>; 984129e1c96SFelipe Balbi interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 985129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 986129e1c96SFelipe Balbi #address-cells = <1>; 987129e1c96SFelipe Balbi #size-cells = <0>; 988129e1c96SFelipe Balbi status = "disabled"; 989129e1c96SFelipe Balbi }; 990129e1c96SFelipe Balbi 99181bee695SCaleb Connolly i2c1: i2c@884000 { 99281bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 99381bee695SCaleb Connolly reg = <0 0x00884000 0 0x4000>; 99481bee695SCaleb Connolly clock-names = "se"; 99581bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 996abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 997abdd4b7aSFelipe Balbi <&gpi_dma0 1 1 QCOM_GPI_I2C>; 998abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 99981bee695SCaleb Connolly pinctrl-names = "default"; 100081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c1_default>; 100181bee695SCaleb Connolly interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 100281bee695SCaleb Connolly #address-cells = <1>; 100381bee695SCaleb Connolly #size-cells = <0>; 100481bee695SCaleb Connolly status = "disabled"; 100581bee695SCaleb Connolly }; 100681bee695SCaleb Connolly 1007129e1c96SFelipe Balbi spi1: spi@884000 { 1008129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1009129e1c96SFelipe Balbi reg = <0 0x884000 0 0x4000>; 1010129e1c96SFelipe Balbi reg-names = "se"; 1011129e1c96SFelipe Balbi clock-names = "se"; 1012129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1013abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1014abdd4b7aSFelipe Balbi <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1015abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1016129e1c96SFelipe Balbi pinctrl-names = "default"; 1017129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi1_default>; 1018129e1c96SFelipe Balbi interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1019129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1020129e1c96SFelipe Balbi #address-cells = <1>; 1021129e1c96SFelipe Balbi #size-cells = <0>; 1022129e1c96SFelipe Balbi status = "disabled"; 1023129e1c96SFelipe Balbi }; 1024129e1c96SFelipe Balbi 102581bee695SCaleb Connolly i2c2: i2c@888000 { 102681bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 102781bee695SCaleb Connolly reg = <0 0x00888000 0 0x4000>; 102881bee695SCaleb Connolly clock-names = "se"; 102981bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1030abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1031abdd4b7aSFelipe Balbi <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1032abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 103381bee695SCaleb Connolly pinctrl-names = "default"; 103481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c2_default>; 103581bee695SCaleb Connolly interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 103681bee695SCaleb Connolly #address-cells = <1>; 103781bee695SCaleb Connolly #size-cells = <0>; 103881bee695SCaleb Connolly status = "disabled"; 103981bee695SCaleb Connolly }; 104081bee695SCaleb Connolly 1041129e1c96SFelipe Balbi spi2: spi@888000 { 1042129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1043129e1c96SFelipe Balbi reg = <0 0x888000 0 0x4000>; 1044129e1c96SFelipe Balbi reg-names = "se"; 1045129e1c96SFelipe Balbi clock-names = "se"; 1046129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1047abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1048abdd4b7aSFelipe Balbi <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1049abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1050129e1c96SFelipe Balbi pinctrl-names = "default"; 1051129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi2_default>; 1052129e1c96SFelipe Balbi interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1053129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1054129e1c96SFelipe Balbi #address-cells = <1>; 1055129e1c96SFelipe Balbi #size-cells = <0>; 1056129e1c96SFelipe Balbi status = "disabled"; 1057129e1c96SFelipe Balbi }; 1058129e1c96SFelipe Balbi 105981bee695SCaleb Connolly i2c3: i2c@88c000 { 106081bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 106181bee695SCaleb Connolly reg = <0 0x0088c000 0 0x4000>; 106281bee695SCaleb Connolly clock-names = "se"; 106381bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1064abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1065abdd4b7aSFelipe Balbi <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1066abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 106781bee695SCaleb Connolly pinctrl-names = "default"; 106881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c3_default>; 106981bee695SCaleb Connolly interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 107081bee695SCaleb Connolly #address-cells = <1>; 107181bee695SCaleb Connolly #size-cells = <0>; 107281bee695SCaleb Connolly status = "disabled"; 107381bee695SCaleb Connolly }; 107481bee695SCaleb Connolly 1075129e1c96SFelipe Balbi spi3: spi@88c000 { 1076129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1077129e1c96SFelipe Balbi reg = <0 0x88c000 0 0x4000>; 1078129e1c96SFelipe Balbi reg-names = "se"; 1079129e1c96SFelipe Balbi clock-names = "se"; 1080129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1081abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1082abdd4b7aSFelipe Balbi <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1083abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1084129e1c96SFelipe Balbi pinctrl-names = "default"; 1085129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi3_default>; 1086129e1c96SFelipe Balbi interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1087129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1088129e1c96SFelipe Balbi #address-cells = <1>; 1089129e1c96SFelipe Balbi #size-cells = <0>; 1090129e1c96SFelipe Balbi status = "disabled"; 1091129e1c96SFelipe Balbi }; 1092129e1c96SFelipe Balbi 109381bee695SCaleb Connolly i2c4: i2c@890000 { 109481bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 109581bee695SCaleb Connolly reg = <0 0x00890000 0 0x4000>; 109681bee695SCaleb Connolly clock-names = "se"; 109781bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1098abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1099abdd4b7aSFelipe Balbi <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1100abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 110181bee695SCaleb Connolly pinctrl-names = "default"; 110281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c4_default>; 110381bee695SCaleb Connolly interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 110481bee695SCaleb Connolly #address-cells = <1>; 110581bee695SCaleb Connolly #size-cells = <0>; 110681bee695SCaleb Connolly status = "disabled"; 110781bee695SCaleb Connolly }; 110881bee695SCaleb Connolly 1109129e1c96SFelipe Balbi spi4: spi@890000 { 1110129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1111129e1c96SFelipe Balbi reg = <0 0x890000 0 0x4000>; 1112129e1c96SFelipe Balbi reg-names = "se"; 1113129e1c96SFelipe Balbi clock-names = "se"; 1114129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1115abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1116abdd4b7aSFelipe Balbi <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1117abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1118129e1c96SFelipe Balbi pinctrl-names = "default"; 1119129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi4_default>; 1120129e1c96SFelipe Balbi interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1121129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1122129e1c96SFelipe Balbi #address-cells = <1>; 1123129e1c96SFelipe Balbi #size-cells = <0>; 1124129e1c96SFelipe Balbi status = "disabled"; 1125129e1c96SFelipe Balbi }; 1126129e1c96SFelipe Balbi 112781bee695SCaleb Connolly i2c5: i2c@894000 { 112881bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 112981bee695SCaleb Connolly reg = <0 0x00894000 0 0x4000>; 113081bee695SCaleb Connolly clock-names = "se"; 113181bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1132abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1133abdd4b7aSFelipe Balbi <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1134abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 113581bee695SCaleb Connolly pinctrl-names = "default"; 113681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c5_default>; 113781bee695SCaleb Connolly interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 113881bee695SCaleb Connolly #address-cells = <1>; 113981bee695SCaleb Connolly #size-cells = <0>; 114081bee695SCaleb Connolly status = "disabled"; 114181bee695SCaleb Connolly }; 114281bee695SCaleb Connolly 1143129e1c96SFelipe Balbi spi5: spi@894000 { 1144129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1145129e1c96SFelipe Balbi reg = <0 0x894000 0 0x4000>; 1146129e1c96SFelipe Balbi reg-names = "se"; 1147129e1c96SFelipe Balbi clock-names = "se"; 1148129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1149abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1150abdd4b7aSFelipe Balbi <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1151abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1152129e1c96SFelipe Balbi pinctrl-names = "default"; 1153129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi5_default>; 1154129e1c96SFelipe Balbi interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1155129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1156129e1c96SFelipe Balbi #address-cells = <1>; 1157129e1c96SFelipe Balbi #size-cells = <0>; 1158129e1c96SFelipe Balbi status = "disabled"; 1159129e1c96SFelipe Balbi }; 1160129e1c96SFelipe Balbi 116181bee695SCaleb Connolly i2c6: i2c@898000 { 116281bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 116381bee695SCaleb Connolly reg = <0 0x00898000 0 0x4000>; 116481bee695SCaleb Connolly clock-names = "se"; 116581bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1166abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1167abdd4b7aSFelipe Balbi <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1168abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 116981bee695SCaleb Connolly pinctrl-names = "default"; 117081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c6_default>; 117181bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 117281bee695SCaleb Connolly #address-cells = <1>; 117381bee695SCaleb Connolly #size-cells = <0>; 117481bee695SCaleb Connolly status = "disabled"; 117581bee695SCaleb Connolly }; 117681bee695SCaleb Connolly 1177129e1c96SFelipe Balbi spi6: spi@898000 { 1178129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1179129e1c96SFelipe Balbi reg = <0 0x898000 0 0x4000>; 1180129e1c96SFelipe Balbi reg-names = "se"; 1181129e1c96SFelipe Balbi clock-names = "se"; 1182129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1183abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1184abdd4b7aSFelipe Balbi <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1185abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1186129e1c96SFelipe Balbi pinctrl-names = "default"; 1187129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi6_default>; 1188129e1c96SFelipe Balbi interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1189129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1190129e1c96SFelipe Balbi #address-cells = <1>; 1191129e1c96SFelipe Balbi #size-cells = <0>; 1192129e1c96SFelipe Balbi status = "disabled"; 1193129e1c96SFelipe Balbi }; 1194129e1c96SFelipe Balbi 119581bee695SCaleb Connolly i2c7: i2c@89c000 { 119681bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 119781bee695SCaleb Connolly reg = <0 0x0089c000 0 0x4000>; 119881bee695SCaleb Connolly clock-names = "se"; 119981bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1200abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1201abdd4b7aSFelipe Balbi <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1202abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 120381bee695SCaleb Connolly pinctrl-names = "default"; 120481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c7_default>; 120581bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 120681bee695SCaleb Connolly #address-cells = <1>; 120781bee695SCaleb Connolly #size-cells = <0>; 120881bee695SCaleb Connolly status = "disabled"; 120981bee695SCaleb Connolly }; 121081bee695SCaleb Connolly 1211129e1c96SFelipe Balbi spi7: spi@89c000 { 1212129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1213129e1c96SFelipe Balbi reg = <0 0x89c000 0 0x4000>; 1214129e1c96SFelipe Balbi reg-names = "se"; 1215129e1c96SFelipe Balbi clock-names = "se"; 1216129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1217abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1218abdd4b7aSFelipe Balbi <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1219abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1220129e1c96SFelipe Balbi pinctrl-names = "default"; 1221129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi7_default>; 1222129e1c96SFelipe Balbi interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1223129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1224129e1c96SFelipe Balbi #address-cells = <1>; 1225129e1c96SFelipe Balbi #size-cells = <0>; 1226129e1c96SFelipe Balbi status = "disabled"; 1227129e1c96SFelipe Balbi }; 12289cf3ebd1SCaleb Connolly }; 12299cf3ebd1SCaleb Connolly 123005006290SFelipe Balbi gpi_dma1: dma-controller@a00000 { 123105006290SFelipe Balbi compatible = "qcom,sm8150-gpi-dma"; 123205006290SFelipe Balbi reg = <0 0xa00000 0 0x60000>; 123305006290SFelipe Balbi interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 123405006290SFelipe Balbi <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 123505006290SFelipe Balbi <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 123605006290SFelipe Balbi <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 123705006290SFelipe Balbi <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 123805006290SFelipe Balbi <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 123905006290SFelipe Balbi <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 124005006290SFelipe Balbi <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 124105006290SFelipe Balbi <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 124205006290SFelipe Balbi <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 124305006290SFelipe Balbi <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 124405006290SFelipe Balbi <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 124505006290SFelipe Balbi <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 124605006290SFelipe Balbi dma-channels = <13>; 124705006290SFelipe Balbi dma-channel-mask = <0xfa>; 124805006290SFelipe Balbi iommus = <&apps_smmu 0x0616 0x0>; 124905006290SFelipe Balbi #dma-cells = <3>; 125005006290SFelipe Balbi status = "disabled"; 125105006290SFelipe Balbi }; 125205006290SFelipe Balbi 1253e13c6d14SVinod Koul qupv3_id_1: geniqup@ac0000 { 1254e13c6d14SVinod Koul compatible = "qcom,geni-se-qup"; 1255e13c6d14SVinod Koul reg = <0x0 0x00ac0000 0x0 0x6000>; 1256e13c6d14SVinod Koul clock-names = "m-ahb", "s-ahb"; 1257d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1258d6f55763SVinod Koul <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 12599cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x603 0x0>; 1260e13c6d14SVinod Koul #address-cells = <2>; 1261e13c6d14SVinod Koul #size-cells = <2>; 1262e13c6d14SVinod Koul ranges; 1263e13c6d14SVinod Koul status = "disabled"; 1264e13c6d14SVinod Koul 126581bee695SCaleb Connolly i2c8: i2c@a80000 { 126681bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 126781bee695SCaleb Connolly reg = <0 0x00a80000 0 0x4000>; 126881bee695SCaleb Connolly clock-names = "se"; 126981bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1270abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1271abdd4b7aSFelipe Balbi <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1272abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 127381bee695SCaleb Connolly pinctrl-names = "default"; 127481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c8_default>; 127581bee695SCaleb Connolly interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 127681bee695SCaleb Connolly #address-cells = <1>; 127781bee695SCaleb Connolly #size-cells = <0>; 127881bee695SCaleb Connolly status = "disabled"; 127981bee695SCaleb Connolly }; 128081bee695SCaleb Connolly 1281129e1c96SFelipe Balbi spi8: spi@a80000 { 1282129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1283129e1c96SFelipe Balbi reg = <0 0xa80000 0 0x4000>; 1284129e1c96SFelipe Balbi reg-names = "se"; 1285129e1c96SFelipe Balbi clock-names = "se"; 1286129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1287abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1288abdd4b7aSFelipe Balbi <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1289abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1290129e1c96SFelipe Balbi pinctrl-names = "default"; 1291129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi8_default>; 1292129e1c96SFelipe Balbi interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1293129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1294129e1c96SFelipe Balbi #address-cells = <1>; 1295129e1c96SFelipe Balbi #size-cells = <0>; 1296129e1c96SFelipe Balbi status = "disabled"; 1297129e1c96SFelipe Balbi }; 1298129e1c96SFelipe Balbi 129981bee695SCaleb Connolly i2c9: i2c@a84000 { 130081bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 130181bee695SCaleb Connolly reg = <0 0x00a84000 0 0x4000>; 130281bee695SCaleb Connolly clock-names = "se"; 130381bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1304abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1305abdd4b7aSFelipe Balbi <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1306abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 130781bee695SCaleb Connolly pinctrl-names = "default"; 130881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c9_default>; 130981bee695SCaleb Connolly interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 131081bee695SCaleb Connolly #address-cells = <1>; 131181bee695SCaleb Connolly #size-cells = <0>; 131281bee695SCaleb Connolly status = "disabled"; 131381bee695SCaleb Connolly }; 131481bee695SCaleb Connolly 1315129e1c96SFelipe Balbi spi9: spi@a84000 { 1316129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1317129e1c96SFelipe Balbi reg = <0 0xa84000 0 0x4000>; 1318129e1c96SFelipe Balbi reg-names = "se"; 1319129e1c96SFelipe Balbi clock-names = "se"; 1320129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1321abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1322abdd4b7aSFelipe Balbi <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1323abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1324129e1c96SFelipe Balbi pinctrl-names = "default"; 1325129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi9_default>; 1326129e1c96SFelipe Balbi interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1327129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1328129e1c96SFelipe Balbi #address-cells = <1>; 1329129e1c96SFelipe Balbi #size-cells = <0>; 1330129e1c96SFelipe Balbi status = "disabled"; 1331129e1c96SFelipe Balbi }; 1332129e1c96SFelipe Balbi 133381bee695SCaleb Connolly i2c10: i2c@a88000 { 133481bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 133581bee695SCaleb Connolly reg = <0 0x00a88000 0 0x4000>; 133681bee695SCaleb Connolly clock-names = "se"; 133781bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1338abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1339abdd4b7aSFelipe Balbi <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1340abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 134181bee695SCaleb Connolly pinctrl-names = "default"; 134281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c10_default>; 134381bee695SCaleb Connolly interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 134481bee695SCaleb Connolly #address-cells = <1>; 134581bee695SCaleb Connolly #size-cells = <0>; 134681bee695SCaleb Connolly status = "disabled"; 134781bee695SCaleb Connolly }; 134881bee695SCaleb Connolly 1349129e1c96SFelipe Balbi spi10: spi@a88000 { 1350129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1351129e1c96SFelipe Balbi reg = <0 0xa88000 0 0x4000>; 1352129e1c96SFelipe Balbi reg-names = "se"; 1353129e1c96SFelipe Balbi clock-names = "se"; 1354129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1355abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1356abdd4b7aSFelipe Balbi <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1357abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1358129e1c96SFelipe Balbi pinctrl-names = "default"; 1359129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi10_default>; 1360129e1c96SFelipe Balbi interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1361129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1362129e1c96SFelipe Balbi #address-cells = <1>; 1363129e1c96SFelipe Balbi #size-cells = <0>; 1364129e1c96SFelipe Balbi status = "disabled"; 1365129e1c96SFelipe Balbi }; 1366129e1c96SFelipe Balbi 136781bee695SCaleb Connolly i2c11: i2c@a8c000 { 136881bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 136981bee695SCaleb Connolly reg = <0 0x00a8c000 0 0x4000>; 137081bee695SCaleb Connolly clock-names = "se"; 137181bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1372abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1373abdd4b7aSFelipe Balbi <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1374abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 137581bee695SCaleb Connolly pinctrl-names = "default"; 137681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c11_default>; 137781bee695SCaleb Connolly interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 137881bee695SCaleb Connolly #address-cells = <1>; 137981bee695SCaleb Connolly #size-cells = <0>; 138081bee695SCaleb Connolly status = "disabled"; 138181bee695SCaleb Connolly }; 138281bee695SCaleb Connolly 1383129e1c96SFelipe Balbi spi11: spi@a8c000 { 1384129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1385129e1c96SFelipe Balbi reg = <0 0xa8c000 0 0x4000>; 1386129e1c96SFelipe Balbi reg-names = "se"; 1387129e1c96SFelipe Balbi clock-names = "se"; 1388129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1389abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1390abdd4b7aSFelipe Balbi <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1391abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1392129e1c96SFelipe Balbi pinctrl-names = "default"; 1393129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi11_default>; 1394129e1c96SFelipe Balbi interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1395129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1396129e1c96SFelipe Balbi #address-cells = <1>; 1397129e1c96SFelipe Balbi #size-cells = <0>; 1398129e1c96SFelipe Balbi status = "disabled"; 1399129e1c96SFelipe Balbi }; 1400129e1c96SFelipe Balbi 1401e13c6d14SVinod Koul uart2: serial@a90000 { 1402e13c6d14SVinod Koul compatible = "qcom,geni-debug-uart"; 1403e13c6d14SVinod Koul reg = <0x0 0x00a90000 0x0 0x4000>; 1404e13c6d14SVinod Koul clock-names = "se"; 1405d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1406e13c6d14SVinod Koul interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1407e13c6d14SVinod Koul status = "disabled"; 1408e13c6d14SVinod Koul }; 140981bee695SCaleb Connolly 141081bee695SCaleb Connolly i2c12: i2c@a90000 { 141181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 141281bee695SCaleb Connolly reg = <0 0x00a90000 0 0x4000>; 141381bee695SCaleb Connolly clock-names = "se"; 141481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1415abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1416abdd4b7aSFelipe Balbi <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1417abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 141881bee695SCaleb Connolly pinctrl-names = "default"; 141981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c12_default>; 142081bee695SCaleb Connolly interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 142181bee695SCaleb Connolly #address-cells = <1>; 142281bee695SCaleb Connolly #size-cells = <0>; 142381bee695SCaleb Connolly status = "disabled"; 142481bee695SCaleb Connolly }; 142581bee695SCaleb Connolly 1426129e1c96SFelipe Balbi spi12: spi@a90000 { 1427129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1428129e1c96SFelipe Balbi reg = <0 0xa90000 0 0x4000>; 1429129e1c96SFelipe Balbi reg-names = "se"; 1430129e1c96SFelipe Balbi clock-names = "se"; 1431129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1432abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1433abdd4b7aSFelipe Balbi <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1434abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1435129e1c96SFelipe Balbi pinctrl-names = "default"; 1436129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi12_default>; 1437129e1c96SFelipe Balbi interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1438129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1439129e1c96SFelipe Balbi #address-cells = <1>; 1440129e1c96SFelipe Balbi #size-cells = <0>; 1441129e1c96SFelipe Balbi status = "disabled"; 1442129e1c96SFelipe Balbi }; 1443129e1c96SFelipe Balbi 144481bee695SCaleb Connolly i2c16: i2c@94000 { 144581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 144681bee695SCaleb Connolly reg = <0 0x0094000 0 0x4000>; 144781bee695SCaleb Connolly clock-names = "se"; 144881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1449abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1450abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1451abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 145281bee695SCaleb Connolly pinctrl-names = "default"; 145381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c16_default>; 145481bee695SCaleb Connolly interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 145581bee695SCaleb Connolly #address-cells = <1>; 145681bee695SCaleb Connolly #size-cells = <0>; 145781bee695SCaleb Connolly status = "disabled"; 145881bee695SCaleb Connolly }; 1459129e1c96SFelipe Balbi 1460129e1c96SFelipe Balbi spi16: spi@a94000 { 1461129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1462129e1c96SFelipe Balbi reg = <0 0xa94000 0 0x4000>; 1463129e1c96SFelipe Balbi reg-names = "se"; 1464129e1c96SFelipe Balbi clock-names = "se"; 1465129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1466abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1467abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1468abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1469129e1c96SFelipe Balbi pinctrl-names = "default"; 1470129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi16_default>; 1471129e1c96SFelipe Balbi interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1472129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1473129e1c96SFelipe Balbi #address-cells = <1>; 1474129e1c96SFelipe Balbi #size-cells = <0>; 1475129e1c96SFelipe Balbi status = "disabled"; 1476129e1c96SFelipe Balbi }; 1477e13c6d14SVinod Koul }; 1478e13c6d14SVinod Koul 147905006290SFelipe Balbi gpi_dma2: dma-controller@c00000 { 148005006290SFelipe Balbi compatible = "qcom,sm8150-gpi-dma"; 148105006290SFelipe Balbi reg = <0 0xc00000 0 0x60000>; 148205006290SFelipe Balbi interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 148305006290SFelipe Balbi <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 148405006290SFelipe Balbi <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 148505006290SFelipe Balbi <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 148605006290SFelipe Balbi <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 148705006290SFelipe Balbi <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 148805006290SFelipe Balbi <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 148905006290SFelipe Balbi <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 149005006290SFelipe Balbi <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 149105006290SFelipe Balbi <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 149205006290SFelipe Balbi <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 149305006290SFelipe Balbi <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 149405006290SFelipe Balbi <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 149505006290SFelipe Balbi dma-channels = <13>; 149605006290SFelipe Balbi dma-channel-mask = <0xfa>; 149705006290SFelipe Balbi iommus = <&apps_smmu 0x07b6 0x0>; 149805006290SFelipe Balbi #dma-cells = <3>; 149905006290SFelipe Balbi status = "disabled"; 150005006290SFelipe Balbi }; 150105006290SFelipe Balbi 15029cf3ebd1SCaleb Connolly qupv3_id_2: geniqup@cc0000 { 15039cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 15049cf3ebd1SCaleb Connolly reg = <0x0 0x00cc0000 0x0 0x6000>; 15059cf3ebd1SCaleb Connolly 15069cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 15079cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 15089cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 15099cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x7a3 0x0>; 15109cf3ebd1SCaleb Connolly #address-cells = <2>; 15119cf3ebd1SCaleb Connolly #size-cells = <2>; 15129cf3ebd1SCaleb Connolly ranges; 15139cf3ebd1SCaleb Connolly status = "disabled"; 151481bee695SCaleb Connolly 151581bee695SCaleb Connolly i2c17: i2c@c80000 { 151681bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 151781bee695SCaleb Connolly reg = <0 0x00c80000 0 0x4000>; 151881bee695SCaleb Connolly clock-names = "se"; 151981bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1520abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1521abdd4b7aSFelipe Balbi <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1522abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 152381bee695SCaleb Connolly pinctrl-names = "default"; 152481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c17_default>; 152581bee695SCaleb Connolly interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 152681bee695SCaleb Connolly #address-cells = <1>; 152781bee695SCaleb Connolly #size-cells = <0>; 152881bee695SCaleb Connolly status = "disabled"; 152981bee695SCaleb Connolly }; 153081bee695SCaleb Connolly 1531129e1c96SFelipe Balbi spi17: spi@c80000 { 1532129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1533129e1c96SFelipe Balbi reg = <0 0xc80000 0 0x4000>; 1534129e1c96SFelipe Balbi reg-names = "se"; 1535129e1c96SFelipe Balbi clock-names = "se"; 1536129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1537abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1538abdd4b7aSFelipe Balbi <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1539abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1540129e1c96SFelipe Balbi pinctrl-names = "default"; 1541129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi17_default>; 1542129e1c96SFelipe Balbi interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1543129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1544129e1c96SFelipe Balbi #address-cells = <1>; 1545129e1c96SFelipe Balbi #size-cells = <0>; 1546129e1c96SFelipe Balbi status = "disabled"; 1547129e1c96SFelipe Balbi }; 1548129e1c96SFelipe Balbi 154981bee695SCaleb Connolly i2c18: i2c@c84000 { 155081bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 155181bee695SCaleb Connolly reg = <0 0x00c84000 0 0x4000>; 155281bee695SCaleb Connolly clock-names = "se"; 155381bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1554abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1555abdd4b7aSFelipe Balbi <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1556abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 155781bee695SCaleb Connolly pinctrl-names = "default"; 155881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c18_default>; 155981bee695SCaleb Connolly interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 156081bee695SCaleb Connolly #address-cells = <1>; 156181bee695SCaleb Connolly #size-cells = <0>; 156281bee695SCaleb Connolly status = "disabled"; 156381bee695SCaleb Connolly }; 156481bee695SCaleb Connolly 1565129e1c96SFelipe Balbi spi18: spi@c84000 { 1566129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1567129e1c96SFelipe Balbi reg = <0 0xc84000 0 0x4000>; 1568129e1c96SFelipe Balbi reg-names = "se"; 1569129e1c96SFelipe Balbi clock-names = "se"; 1570129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1571abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1572abdd4b7aSFelipe Balbi <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1573abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1574129e1c96SFelipe Balbi pinctrl-names = "default"; 1575129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi18_default>; 1576129e1c96SFelipe Balbi interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1577129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1578129e1c96SFelipe Balbi #address-cells = <1>; 1579129e1c96SFelipe Balbi #size-cells = <0>; 1580129e1c96SFelipe Balbi status = "disabled"; 1581129e1c96SFelipe Balbi }; 1582129e1c96SFelipe Balbi 158381bee695SCaleb Connolly i2c19: i2c@c88000 { 158481bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 158581bee695SCaleb Connolly reg = <0 0x00c88000 0 0x4000>; 158681bee695SCaleb Connolly clock-names = "se"; 158781bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1588abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1589abdd4b7aSFelipe Balbi <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1590abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 159181bee695SCaleb Connolly pinctrl-names = "default"; 159281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c19_default>; 159381bee695SCaleb Connolly interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 159481bee695SCaleb Connolly #address-cells = <1>; 159581bee695SCaleb Connolly #size-cells = <0>; 159681bee695SCaleb Connolly status = "disabled"; 159781bee695SCaleb Connolly }; 159881bee695SCaleb Connolly 1599129e1c96SFelipe Balbi spi19: spi@c88000 { 1600129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1601129e1c96SFelipe Balbi reg = <0 0xc88000 0 0x4000>; 1602129e1c96SFelipe Balbi reg-names = "se"; 1603129e1c96SFelipe Balbi clock-names = "se"; 1604129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1605abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1606abdd4b7aSFelipe Balbi <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1607abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1608129e1c96SFelipe Balbi pinctrl-names = "default"; 1609129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi19_default>; 1610129e1c96SFelipe Balbi interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1611129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1612129e1c96SFelipe Balbi #address-cells = <1>; 1613129e1c96SFelipe Balbi #size-cells = <0>; 1614129e1c96SFelipe Balbi status = "disabled"; 1615129e1c96SFelipe Balbi }; 1616129e1c96SFelipe Balbi 161781bee695SCaleb Connolly i2c13: i2c@c8c000 { 161881bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 161981bee695SCaleb Connolly reg = <0 0x00c8c000 0 0x4000>; 162081bee695SCaleb Connolly clock-names = "se"; 162181bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1622abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1623abdd4b7aSFelipe Balbi <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1624abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 162581bee695SCaleb Connolly pinctrl-names = "default"; 162681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c13_default>; 162781bee695SCaleb Connolly interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 162881bee695SCaleb Connolly #address-cells = <1>; 162981bee695SCaleb Connolly #size-cells = <0>; 163081bee695SCaleb Connolly status = "disabled"; 163181bee695SCaleb Connolly }; 163281bee695SCaleb Connolly 1633129e1c96SFelipe Balbi spi13: spi@c8c000 { 1634129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1635129e1c96SFelipe Balbi reg = <0 0xc8c000 0 0x4000>; 1636129e1c96SFelipe Balbi reg-names = "se"; 1637129e1c96SFelipe Balbi clock-names = "se"; 1638129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1639abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1640abdd4b7aSFelipe Balbi <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1641abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1642129e1c96SFelipe Balbi pinctrl-names = "default"; 1643129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi13_default>; 1644129e1c96SFelipe Balbi interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1645129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1646129e1c96SFelipe Balbi #address-cells = <1>; 1647129e1c96SFelipe Balbi #size-cells = <0>; 1648129e1c96SFelipe Balbi status = "disabled"; 1649129e1c96SFelipe Balbi }; 1650129e1c96SFelipe Balbi 165181bee695SCaleb Connolly i2c14: i2c@c90000 { 165281bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 165381bee695SCaleb Connolly reg = <0 0x00c90000 0 0x4000>; 165481bee695SCaleb Connolly clock-names = "se"; 165581bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1656abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1657abdd4b7aSFelipe Balbi <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1658abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 165981bee695SCaleb Connolly pinctrl-names = "default"; 166081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c14_default>; 166181bee695SCaleb Connolly interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 166281bee695SCaleb Connolly #address-cells = <1>; 166381bee695SCaleb Connolly #size-cells = <0>; 166481bee695SCaleb Connolly status = "disabled"; 166581bee695SCaleb Connolly }; 166681bee695SCaleb Connolly 1667129e1c96SFelipe Balbi spi14: spi@c90000 { 1668129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1669129e1c96SFelipe Balbi reg = <0 0xc90000 0 0x4000>; 1670129e1c96SFelipe Balbi reg-names = "se"; 1671129e1c96SFelipe Balbi clock-names = "se"; 1672129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1673abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1674abdd4b7aSFelipe Balbi <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1675abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1676129e1c96SFelipe Balbi pinctrl-names = "default"; 1677129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi14_default>; 1678129e1c96SFelipe Balbi interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1679129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1680129e1c96SFelipe Balbi #address-cells = <1>; 1681129e1c96SFelipe Balbi #size-cells = <0>; 1682129e1c96SFelipe Balbi status = "disabled"; 1683129e1c96SFelipe Balbi }; 1684129e1c96SFelipe Balbi 168581bee695SCaleb Connolly i2c15: i2c@c94000 { 168681bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 168781bee695SCaleb Connolly reg = <0 0x00c94000 0 0x4000>; 168881bee695SCaleb Connolly clock-names = "se"; 168981bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1690abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1691abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1692abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 169381bee695SCaleb Connolly pinctrl-names = "default"; 169481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c15_default>; 169581bee695SCaleb Connolly interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 169681bee695SCaleb Connolly #address-cells = <1>; 169781bee695SCaleb Connolly #size-cells = <0>; 169881bee695SCaleb Connolly status = "disabled"; 169981bee695SCaleb Connolly }; 1700129e1c96SFelipe Balbi 1701129e1c96SFelipe Balbi spi15: spi@c94000 { 1702129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1703129e1c96SFelipe Balbi reg = <0 0xc94000 0 0x4000>; 1704129e1c96SFelipe Balbi reg-names = "se"; 1705129e1c96SFelipe Balbi clock-names = "se"; 1706129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1707abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1708abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1709abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1710129e1c96SFelipe Balbi pinctrl-names = "default"; 1711129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi15_default>; 1712129e1c96SFelipe Balbi interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1713129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1714129e1c96SFelipe Balbi #address-cells = <1>; 1715129e1c96SFelipe Balbi #size-cells = <0>; 1716129e1c96SFelipe Balbi status = "disabled"; 1717129e1c96SFelipe Balbi }; 17189cf3ebd1SCaleb Connolly }; 17199cf3ebd1SCaleb Connolly 172071a2fc6eSJonathan Marek config_noc: interconnect@1500000 { 172171a2fc6eSJonathan Marek compatible = "qcom,sm8150-config-noc"; 172271a2fc6eSJonathan Marek reg = <0 0x01500000 0 0x7400>; 172371a2fc6eSJonathan Marek #interconnect-cells = <1>; 172471a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 172571a2fc6eSJonathan Marek }; 172671a2fc6eSJonathan Marek 172771a2fc6eSJonathan Marek system_noc: interconnect@1620000 { 172871a2fc6eSJonathan Marek compatible = "qcom,sm8150-system-noc"; 172971a2fc6eSJonathan Marek reg = <0 0x01620000 0 0x19400>; 173071a2fc6eSJonathan Marek #interconnect-cells = <1>; 173171a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 173271a2fc6eSJonathan Marek }; 173371a2fc6eSJonathan Marek 173471a2fc6eSJonathan Marek mc_virt: interconnect@163a000 { 173571a2fc6eSJonathan Marek compatible = "qcom,sm8150-mc-virt"; 173671a2fc6eSJonathan Marek reg = <0 0x0163a000 0 0x1000>; 173771a2fc6eSJonathan Marek #interconnect-cells = <1>; 173871a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 173971a2fc6eSJonathan Marek }; 174071a2fc6eSJonathan Marek 174171a2fc6eSJonathan Marek aggre1_noc: interconnect@16e0000 { 174271a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre1-noc"; 174371a2fc6eSJonathan Marek reg = <0 0x016e0000 0 0xd080>; 174471a2fc6eSJonathan Marek #interconnect-cells = <1>; 174571a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 174671a2fc6eSJonathan Marek }; 174771a2fc6eSJonathan Marek 174871a2fc6eSJonathan Marek aggre2_noc: interconnect@1700000 { 174971a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre2-noc"; 175071a2fc6eSJonathan Marek reg = <0 0x01700000 0 0x20000>; 175171a2fc6eSJonathan Marek #interconnect-cells = <1>; 175271a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 175371a2fc6eSJonathan Marek }; 175471a2fc6eSJonathan Marek 175571a2fc6eSJonathan Marek compute_noc: interconnect@1720000 { 175671a2fc6eSJonathan Marek compatible = "qcom,sm8150-compute-noc"; 175771a2fc6eSJonathan Marek reg = <0 0x01720000 0 0x7000>; 175871a2fc6eSJonathan Marek #interconnect-cells = <1>; 175971a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 176071a2fc6eSJonathan Marek }; 176171a2fc6eSJonathan Marek 176271a2fc6eSJonathan Marek mmss_noc: interconnect@1740000 { 176371a2fc6eSJonathan Marek compatible = "qcom,sm8150-mmss-noc"; 176471a2fc6eSJonathan Marek reg = <0 0x01740000 0 0x1c100>; 176571a2fc6eSJonathan Marek #interconnect-cells = <1>; 176671a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 176771a2fc6eSJonathan Marek }; 176871a2fc6eSJonathan Marek 1769bb1f7cf6SSouradeep Chowdhury system-cache-controller@9200000 { 1770bb1f7cf6SSouradeep Chowdhury compatible = "qcom,sm8150-llcc"; 1771bb1f7cf6SSouradeep Chowdhury reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 1772bb1f7cf6SSouradeep Chowdhury reg-names = "llcc_base", "llcc_broadcast_base"; 1773bb1f7cf6SSouradeep Chowdhury interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1774bb1f7cf6SSouradeep Chowdhury }; 1775bb1f7cf6SSouradeep Chowdhury 1776a1c86c68SBhupesh Sharma pcie0: pci@1c00000 { 1777a1c86c68SBhupesh Sharma compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1778a1c86c68SBhupesh Sharma reg = <0 0x01c00000 0 0x3000>, 1779a1c86c68SBhupesh Sharma <0 0x60000000 0 0xf1d>, 1780a1c86c68SBhupesh Sharma <0 0x60000f20 0 0xa8>, 1781a1c86c68SBhupesh Sharma <0 0x60001000 0 0x1000>, 1782a1c86c68SBhupesh Sharma <0 0x60100000 0 0x100000>; 1783a1c86c68SBhupesh Sharma reg-names = "parf", "dbi", "elbi", "atu", "config"; 1784a1c86c68SBhupesh Sharma device_type = "pci"; 1785a1c86c68SBhupesh Sharma linux,pci-domain = <0>; 1786a1c86c68SBhupesh Sharma bus-range = <0x00 0xff>; 1787a1c86c68SBhupesh Sharma num-lanes = <1>; 1788a1c86c68SBhupesh Sharma 1789a1c86c68SBhupesh Sharma #address-cells = <3>; 1790a1c86c68SBhupesh Sharma #size-cells = <2>; 1791a1c86c68SBhupesh Sharma 1792a1c86c68SBhupesh Sharma ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1793a1c86c68SBhupesh Sharma <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1794a1c86c68SBhupesh Sharma 1795a1c86c68SBhupesh Sharma interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1796a1c86c68SBhupesh Sharma interrupt-names = "msi"; 1797a1c86c68SBhupesh Sharma #interrupt-cells = <1>; 1798a1c86c68SBhupesh Sharma interrupt-map-mask = <0 0 0 0x7>; 1799a1c86c68SBhupesh Sharma interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1800a1c86c68SBhupesh Sharma <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1801a1c86c68SBhupesh Sharma <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1802a1c86c68SBhupesh Sharma <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1803a1c86c68SBhupesh Sharma 1804a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1805a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_AUX_CLK>, 1806a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1807a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1808a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1809a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1810a1c86c68SBhupesh Sharma <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1811a1c86c68SBhupesh Sharma clock-names = "pipe", 1812a1c86c68SBhupesh Sharma "aux", 1813a1c86c68SBhupesh Sharma "cfg", 1814a1c86c68SBhupesh Sharma "bus_master", 1815a1c86c68SBhupesh Sharma "bus_slave", 1816a1c86c68SBhupesh Sharma "slave_q2a", 1817a1c86c68SBhupesh Sharma "tbu"; 1818a1c86c68SBhupesh Sharma 1819a1c86c68SBhupesh Sharma iommus = <&apps_smmu 0x1d80 0x7f>; 1820a1c86c68SBhupesh Sharma iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1821a1c86c68SBhupesh Sharma <0x100 &apps_smmu 0x1d81 0x1>; 1822a1c86c68SBhupesh Sharma 1823a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_0_BCR>; 1824a1c86c68SBhupesh Sharma reset-names = "pci"; 1825a1c86c68SBhupesh Sharma 1826a1c86c68SBhupesh Sharma power-domains = <&gcc PCIE_0_GDSC>; 1827a1c86c68SBhupesh Sharma 1828a1c86c68SBhupesh Sharma phys = <&pcie0_lane>; 1829a1c86c68SBhupesh Sharma phy-names = "pciephy"; 1830a1c86c68SBhupesh Sharma 1831a1c86c68SBhupesh Sharma perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1832a1c86c68SBhupesh Sharma enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1833a1c86c68SBhupesh Sharma 1834a1c86c68SBhupesh Sharma pinctrl-names = "default"; 1835a1c86c68SBhupesh Sharma pinctrl-0 = <&pcie0_default_state>; 1836a1c86c68SBhupesh Sharma 1837a1c86c68SBhupesh Sharma status = "disabled"; 1838a1c86c68SBhupesh Sharma }; 1839a1c86c68SBhupesh Sharma 1840a1c86c68SBhupesh Sharma pcie0_phy: phy@1c06000 { 1841a1c86c68SBhupesh Sharma compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1842a1c86c68SBhupesh Sharma reg = <0 0x01c06000 0 0x1c0>; 1843a1c86c68SBhupesh Sharma #address-cells = <2>; 1844a1c86c68SBhupesh Sharma #size-cells = <2>; 1845a1c86c68SBhupesh Sharma ranges; 1846a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1847a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1848a1c86c68SBhupesh Sharma <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1849a1c86c68SBhupesh Sharma clock-names = "aux", "cfg_ahb", "refgen"; 1850a1c86c68SBhupesh Sharma 1851a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1852a1c86c68SBhupesh Sharma reset-names = "phy"; 1853a1c86c68SBhupesh Sharma 1854a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1855a1c86c68SBhupesh Sharma assigned-clock-rates = <100000000>; 1856a1c86c68SBhupesh Sharma 1857a1c86c68SBhupesh Sharma status = "disabled"; 1858a1c86c68SBhupesh Sharma 1859a1c86c68SBhupesh Sharma pcie0_lane: phy@1c06200 { 1860a1c86c68SBhupesh Sharma reg = <0 0x1c06200 0 0x170>, /* tx */ 1861a1c86c68SBhupesh Sharma <0 0x1c06400 0 0x200>, /* rx */ 1862a1c86c68SBhupesh Sharma <0 0x1c06800 0 0x1f0>, /* pcs */ 1863a1c86c68SBhupesh Sharma <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1864a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1865a1c86c68SBhupesh Sharma clock-names = "pipe0"; 1866a1c86c68SBhupesh Sharma 1867a1c86c68SBhupesh Sharma #phy-cells = <0>; 1868a1c86c68SBhupesh Sharma clock-output-names = "pcie_0_pipe_clk"; 1869a1c86c68SBhupesh Sharma }; 1870a1c86c68SBhupesh Sharma }; 1871a1c86c68SBhupesh Sharma 1872a1c86c68SBhupesh Sharma pcie1: pci@1c08000 { 1873a1c86c68SBhupesh Sharma compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1874a1c86c68SBhupesh Sharma reg = <0 0x01c08000 0 0x3000>, 1875a1c86c68SBhupesh Sharma <0 0x40000000 0 0xf1d>, 1876a1c86c68SBhupesh Sharma <0 0x40000f20 0 0xa8>, 1877a1c86c68SBhupesh Sharma <0 0x40001000 0 0x1000>, 1878a1c86c68SBhupesh Sharma <0 0x40100000 0 0x100000>; 1879a1c86c68SBhupesh Sharma reg-names = "parf", "dbi", "elbi", "atu", "config"; 1880a1c86c68SBhupesh Sharma device_type = "pci"; 1881a1c86c68SBhupesh Sharma linux,pci-domain = <1>; 1882a1c86c68SBhupesh Sharma bus-range = <0x00 0xff>; 1883a1c86c68SBhupesh Sharma num-lanes = <2>; 1884a1c86c68SBhupesh Sharma 1885a1c86c68SBhupesh Sharma #address-cells = <3>; 1886a1c86c68SBhupesh Sharma #size-cells = <2>; 1887a1c86c68SBhupesh Sharma 1888a1c86c68SBhupesh Sharma ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1889a1c86c68SBhupesh Sharma <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1890a1c86c68SBhupesh Sharma 1891a1c86c68SBhupesh Sharma interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1892a1c86c68SBhupesh Sharma interrupt-names = "msi"; 1893a1c86c68SBhupesh Sharma #interrupt-cells = <1>; 1894a1c86c68SBhupesh Sharma interrupt-map-mask = <0 0 0 0x7>; 1895a1c86c68SBhupesh Sharma interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1896a1c86c68SBhupesh Sharma <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1897a1c86c68SBhupesh Sharma <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1898a1c86c68SBhupesh Sharma <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1899a1c86c68SBhupesh Sharma 1900a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1901a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_AUX_CLK>, 1902a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1903a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1904a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1905a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1906a1c86c68SBhupesh Sharma <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1907a1c86c68SBhupesh Sharma clock-names = "pipe", 1908a1c86c68SBhupesh Sharma "aux", 1909a1c86c68SBhupesh Sharma "cfg", 1910a1c86c68SBhupesh Sharma "bus_master", 1911a1c86c68SBhupesh Sharma "bus_slave", 1912a1c86c68SBhupesh Sharma "slave_q2a", 1913a1c86c68SBhupesh Sharma "tbu"; 1914a1c86c68SBhupesh Sharma 1915a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1916a1c86c68SBhupesh Sharma assigned-clock-rates = <19200000>; 1917a1c86c68SBhupesh Sharma 1918a1c86c68SBhupesh Sharma iommus = <&apps_smmu 0x1e00 0x7f>; 1919a1c86c68SBhupesh Sharma iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1920a1c86c68SBhupesh Sharma <0x100 &apps_smmu 0x1e01 0x1>; 1921a1c86c68SBhupesh Sharma 1922a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_1_BCR>; 1923a1c86c68SBhupesh Sharma reset-names = "pci"; 1924a1c86c68SBhupesh Sharma 1925a1c86c68SBhupesh Sharma power-domains = <&gcc PCIE_1_GDSC>; 1926a1c86c68SBhupesh Sharma 1927a1c86c68SBhupesh Sharma phys = <&pcie1_lane>; 1928a1c86c68SBhupesh Sharma phy-names = "pciephy"; 1929a1c86c68SBhupesh Sharma 1930a1c86c68SBhupesh Sharma perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; 1931a1c86c68SBhupesh Sharma enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 1932a1c86c68SBhupesh Sharma 1933a1c86c68SBhupesh Sharma pinctrl-names = "default"; 1934a1c86c68SBhupesh Sharma pinctrl-0 = <&pcie1_default_state>; 1935a1c86c68SBhupesh Sharma 1936a1c86c68SBhupesh Sharma status = "disabled"; 1937a1c86c68SBhupesh Sharma }; 1938a1c86c68SBhupesh Sharma 1939a1c86c68SBhupesh Sharma pcie1_phy: phy@1c0e000 { 1940a1c86c68SBhupesh Sharma compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 1941a1c86c68SBhupesh Sharma reg = <0 0x01c0e000 0 0x1c0>; 1942a1c86c68SBhupesh Sharma #address-cells = <2>; 1943a1c86c68SBhupesh Sharma #size-cells = <2>; 1944a1c86c68SBhupesh Sharma ranges; 1945a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1946a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1947a1c86c68SBhupesh Sharma <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1948a1c86c68SBhupesh Sharma clock-names = "aux", "cfg_ahb", "refgen"; 1949a1c86c68SBhupesh Sharma 1950a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1951a1c86c68SBhupesh Sharma reset-names = "phy"; 1952a1c86c68SBhupesh Sharma 1953a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1954a1c86c68SBhupesh Sharma assigned-clock-rates = <100000000>; 1955a1c86c68SBhupesh Sharma 1956a1c86c68SBhupesh Sharma status = "disabled"; 1957a1c86c68SBhupesh Sharma 1958a1c86c68SBhupesh Sharma pcie1_lane: phy@1c0e200 { 1959a1c86c68SBhupesh Sharma reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1960a1c86c68SBhupesh Sharma <0 0x1c0e400 0 0x200>, /* rx0 */ 1961a1c86c68SBhupesh Sharma <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1962a1c86c68SBhupesh Sharma <0 0x1c0e600 0 0x170>, /* tx1 */ 1963a1c86c68SBhupesh Sharma <0 0x1c0e800 0 0x200>, /* rx1 */ 1964a1c86c68SBhupesh Sharma <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1965a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1966a1c86c68SBhupesh Sharma clock-names = "pipe0"; 1967a1c86c68SBhupesh Sharma 1968a1c86c68SBhupesh Sharma #phy-cells = <0>; 1969a1c86c68SBhupesh Sharma clock-output-names = "pcie_1_pipe_clk"; 1970a1c86c68SBhupesh Sharma }; 1971a1c86c68SBhupesh Sharma }; 1972a1c86c68SBhupesh Sharma 19733834a2e9SVinod Koul ufs_mem_hc: ufshc@1d84000 { 19743834a2e9SVinod Koul compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 19753834a2e9SVinod Koul "jedec,ufs-2.0"; 197698aee1e3SBhupesh Sharma reg = <0 0x01d84000 0 0x2500>, 197798aee1e3SBhupesh Sharma <0 0x01d90000 0 0x8000>; 197898aee1e3SBhupesh Sharma reg-names = "std", "ice"; 19793834a2e9SVinod Koul interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 19803834a2e9SVinod Koul phys = <&ufs_mem_phy_lanes>; 19813834a2e9SVinod Koul phy-names = "ufsphy"; 19823834a2e9SVinod Koul lanes-per-direction = <2>; 19833834a2e9SVinod Koul #reset-cells = <1>; 19843834a2e9SVinod Koul resets = <&gcc GCC_UFS_PHY_BCR>; 19853834a2e9SVinod Koul reset-names = "rst"; 19863834a2e9SVinod Koul 198748156232SJonathan Marek iommus = <&apps_smmu 0x300 0>; 198848156232SJonathan Marek 19893834a2e9SVinod Koul clock-names = 19903834a2e9SVinod Koul "core_clk", 19913834a2e9SVinod Koul "bus_aggr_clk", 19923834a2e9SVinod Koul "iface_clk", 19933834a2e9SVinod Koul "core_clk_unipro", 19943834a2e9SVinod Koul "ref_clk", 19953834a2e9SVinod Koul "tx_lane0_sync_clk", 19963834a2e9SVinod Koul "rx_lane0_sync_clk", 199798aee1e3SBhupesh Sharma "rx_lane1_sync_clk", 199898aee1e3SBhupesh Sharma "ice_core_clk"; 19993834a2e9SVinod Koul clocks = 20003834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AXI_CLK>, 20013834a2e9SVinod Koul <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 20023834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AHB_CLK>, 20033834a2e9SVinod Koul <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 20043834a2e9SVinod Koul <&rpmhcc RPMH_CXO_CLK>, 20053834a2e9SVinod Koul <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 20063834a2e9SVinod Koul <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 200798aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 200898aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 20093834a2e9SVinod Koul freq-table-hz = 20103834a2e9SVinod Koul <37500000 300000000>, 20113834a2e9SVinod Koul <0 0>, 20123834a2e9SVinod Koul <0 0>, 20133834a2e9SVinod Koul <37500000 300000000>, 20143834a2e9SVinod Koul <0 0>, 20153834a2e9SVinod Koul <0 0>, 20163834a2e9SVinod Koul <0 0>, 201798aee1e3SBhupesh Sharma <0 0>, 201898aee1e3SBhupesh Sharma <0 300000000>; 20193834a2e9SVinod Koul 20203834a2e9SVinod Koul status = "disabled"; 20213834a2e9SVinod Koul }; 20223834a2e9SVinod Koul 20233834a2e9SVinod Koul ufs_mem_phy: phy@1d87000 { 20243834a2e9SVinod Koul compatible = "qcom,sm8150-qmp-ufs-phy"; 2025c79ec891SVinod Koul reg = <0 0x01d87000 0 0x1c0>; 20263834a2e9SVinod Koul #address-cells = <2>; 20273834a2e9SVinod Koul #size-cells = <2>; 20283834a2e9SVinod Koul ranges; 20293834a2e9SVinod Koul clock-names = "ref", 20303834a2e9SVinod Koul "ref_aux"; 20313834a2e9SVinod Koul clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 20323834a2e9SVinod Koul <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 20333834a2e9SVinod Koul 2034fe75b0c4SBhupesh Sharma power-domains = <&gcc UFS_PHY_GDSC>; 2035fe75b0c4SBhupesh Sharma 20363834a2e9SVinod Koul resets = <&ufs_mem_hc 0>; 20373834a2e9SVinod Koul reset-names = "ufsphy"; 20383834a2e9SVinod Koul status = "disabled"; 20393834a2e9SVinod Koul 20401351512fSShawn Guo ufs_mem_phy_lanes: phy@1d87400 { 20413834a2e9SVinod Koul reg = <0 0x01d87400 0 0x108>, 20423834a2e9SVinod Koul <0 0x01d87600 0 0x1e0>, 20433834a2e9SVinod Koul <0 0x01d87c00 0 0x1dc>, 20443834a2e9SVinod Koul <0 0x01d87800 0 0x108>, 20453834a2e9SVinod Koul <0 0x01d87a00 0 0x1e0>; 20463834a2e9SVinod Koul #phy-cells = <0>; 20473834a2e9SVinod Koul }; 20483834a2e9SVinod Koul }; 20493834a2e9SVinod Koul 205071a2fc6eSJonathan Marek ipa_virt: interconnect@1e00000 { 205171a2fc6eSJonathan Marek compatible = "qcom,sm8150-ipa-virt"; 205271a2fc6eSJonathan Marek reg = <0 0x01e00000 0 0x1000>; 205371a2fc6eSJonathan Marek #interconnect-cells = <1>; 205471a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 205571a2fc6eSJonathan Marek }; 205671a2fc6eSJonathan Marek 2057d8cf9372SVinod Koul tcsr_mutex_regs: syscon@1f40000 { 2058d8cf9372SVinod Koul compatible = "syscon"; 2059d8cf9372SVinod Koul reg = <0x0 0x01f40000 0x0 0x40000>; 2060d8cf9372SVinod Koul }; 2061d8cf9372SVinod Koul 206249076351SSibi Sankar remoteproc_slpi: remoteproc@2400000 { 206349076351SSibi Sankar compatible = "qcom,sm8150-slpi-pas"; 206449076351SSibi Sankar reg = <0x0 0x02400000 0x0 0x4040>; 206549076351SSibi Sankar 206649076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 206749076351SSibi Sankar <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 206849076351SSibi Sankar <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 206949076351SSibi Sankar <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 207049076351SSibi Sankar <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 207149076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 207249076351SSibi Sankar "handover", "stop-ack"; 207349076351SSibi Sankar 207449076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 207549076351SSibi Sankar clock-names = "xo"; 207649076351SSibi Sankar 2077d9d327f6SSibi Sankar power-domains = <&rpmhpd 3>, 2078d0770627SBjorn Andersson <&rpmhpd 2>; 2079d9d327f6SSibi Sankar power-domain-names = "lcx", "lmx"; 208049076351SSibi Sankar 208149076351SSibi Sankar memory-region = <&slpi_mem>; 208249076351SSibi Sankar 2083d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 2084d9d327f6SSibi Sankar 208549076351SSibi Sankar qcom,smem-states = <&slpi_smp2p_out 0>; 208649076351SSibi Sankar qcom,smem-state-names = "stop"; 208749076351SSibi Sankar 208849076351SSibi Sankar status = "disabled"; 208949076351SSibi Sankar 209049076351SSibi Sankar glink-edge { 209149076351SSibi Sankar interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 209249076351SSibi Sankar label = "dsps"; 209349076351SSibi Sankar qcom,remote-pid = <3>; 209449076351SSibi Sankar mboxes = <&apss_shared 24>; 209581729330SBhupesh Sharma 209681729330SBhupesh Sharma fastrpc { 209781729330SBhupesh Sharma compatible = "qcom,fastrpc"; 209881729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 209981729330SBhupesh Sharma label = "sdsp"; 21008c8ce95bSJeya R qcom,non-secure-domain; 210181729330SBhupesh Sharma #address-cells = <1>; 210281729330SBhupesh Sharma #size-cells = <0>; 210381729330SBhupesh Sharma 210481729330SBhupesh Sharma compute-cb@1 { 210581729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 210681729330SBhupesh Sharma reg = <1>; 210781729330SBhupesh Sharma iommus = <&apps_smmu 0x05a1 0x0>; 210881729330SBhupesh Sharma }; 210981729330SBhupesh Sharma 211081729330SBhupesh Sharma compute-cb@2 { 211181729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 211281729330SBhupesh Sharma reg = <2>; 211381729330SBhupesh Sharma iommus = <&apps_smmu 0x05a2 0x0>; 211481729330SBhupesh Sharma }; 211581729330SBhupesh Sharma 211681729330SBhupesh Sharma compute-cb@3 { 211781729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 211881729330SBhupesh Sharma reg = <3>; 211981729330SBhupesh Sharma iommus = <&apps_smmu 0x05a3 0x0>; 212081729330SBhupesh Sharma /* note: shared-cb = <4> in downstream */ 212181729330SBhupesh Sharma }; 212281729330SBhupesh Sharma }; 212349076351SSibi Sankar }; 212449076351SSibi Sankar }; 212549076351SSibi Sankar 2126f30ac26dSJonathan Marek gpu: gpu@2c00000 { 2127f30ac26dSJonathan Marek /* 2128f30ac26dSJonathan Marek * note: the amd,imageon compatible makes it possible 2129f30ac26dSJonathan Marek * to use the drm/msm driver without the display node, 2130f30ac26dSJonathan Marek * make sure to remove it when display node is added 2131f30ac26dSJonathan Marek */ 2132f30ac26dSJonathan Marek compatible = "qcom,adreno-640.1", 2133f30ac26dSJonathan Marek "qcom,adreno", 2134f30ac26dSJonathan Marek "amd,imageon"; 2135f30ac26dSJonathan Marek 2136f30ac26dSJonathan Marek reg = <0 0x02c00000 0 0x40000>; 2137f30ac26dSJonathan Marek reg-names = "kgsl_3d0_reg_memory"; 2138f30ac26dSJonathan Marek 2139f30ac26dSJonathan Marek interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2140f30ac26dSJonathan Marek 2141f30ac26dSJonathan Marek iommus = <&adreno_smmu 0 0x401>; 2142f30ac26dSJonathan Marek 2143f30ac26dSJonathan Marek operating-points-v2 = <&gpu_opp_table>; 2144f30ac26dSJonathan Marek 2145f30ac26dSJonathan Marek qcom,gmu = <&gmu>; 2146f30ac26dSJonathan Marek 2147b1dc3c6bSKonrad Dybcio status = "disabled"; 2148b1dc3c6bSKonrad Dybcio 2149f30ac26dSJonathan Marek zap-shader { 2150f30ac26dSJonathan Marek memory-region = <&gpu_mem>; 2151f30ac26dSJonathan Marek }; 2152f30ac26dSJonathan Marek 2153f30ac26dSJonathan Marek /* note: downstream checks gpu binning for 675 Mhz */ 2154f30ac26dSJonathan Marek gpu_opp_table: opp-table { 2155f30ac26dSJonathan Marek compatible = "operating-points-v2"; 2156f30ac26dSJonathan Marek 2157f30ac26dSJonathan Marek opp-675000000 { 2158f30ac26dSJonathan Marek opp-hz = /bits/ 64 <675000000>; 2159f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2160f30ac26dSJonathan Marek }; 2161f30ac26dSJonathan Marek 2162f30ac26dSJonathan Marek opp-585000000 { 2163f30ac26dSJonathan Marek opp-hz = /bits/ 64 <585000000>; 2164f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2165f30ac26dSJonathan Marek }; 2166f30ac26dSJonathan Marek 2167f30ac26dSJonathan Marek opp-499200000 { 2168f30ac26dSJonathan Marek opp-hz = /bits/ 64 <499200000>; 2169f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2170f30ac26dSJonathan Marek }; 2171f30ac26dSJonathan Marek 2172f30ac26dSJonathan Marek opp-427000000 { 2173f30ac26dSJonathan Marek opp-hz = /bits/ 64 <427000000>; 2174f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2175f30ac26dSJonathan Marek }; 2176f30ac26dSJonathan Marek 2177f30ac26dSJonathan Marek opp-345000000 { 2178f30ac26dSJonathan Marek opp-hz = /bits/ 64 <345000000>; 2179f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2180f30ac26dSJonathan Marek }; 2181f30ac26dSJonathan Marek 2182f30ac26dSJonathan Marek opp-257000000 { 2183f30ac26dSJonathan Marek opp-hz = /bits/ 64 <257000000>; 2184f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2185f30ac26dSJonathan Marek }; 2186f30ac26dSJonathan Marek }; 2187f30ac26dSJonathan Marek }; 2188f30ac26dSJonathan Marek 2189f30ac26dSJonathan Marek gmu: gmu@2c6a000 { 2190f30ac26dSJonathan Marek compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2191f30ac26dSJonathan Marek 2192f30ac26dSJonathan Marek reg = <0 0x02c6a000 0 0x30000>, 2193f30ac26dSJonathan Marek <0 0x0b290000 0 0x10000>, 2194f30ac26dSJonathan Marek <0 0x0b490000 0 0x10000>; 2195f30ac26dSJonathan Marek reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2196f30ac26dSJonathan Marek 2197f30ac26dSJonathan Marek interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2198f30ac26dSJonathan Marek <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2199f30ac26dSJonathan Marek interrupt-names = "hfi", "gmu"; 2200f30ac26dSJonathan Marek 2201f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 2202f1269916SJonathan Marek <&gpucc GPU_CC_CX_GMU_CLK>, 2203f1269916SJonathan Marek <&gpucc GPU_CC_CXO_CLK>, 2204f30ac26dSJonathan Marek <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2205f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2206f30ac26dSJonathan Marek clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2207f30ac26dSJonathan Marek 2208f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>, 2209f1269916SJonathan Marek <&gpucc GPU_GX_GDSC>; 2210f30ac26dSJonathan Marek power-domain-names = "cx", "gx"; 2211f30ac26dSJonathan Marek 2212f30ac26dSJonathan Marek iommus = <&adreno_smmu 5 0x400>; 2213f30ac26dSJonathan Marek 2214f30ac26dSJonathan Marek operating-points-v2 = <&gmu_opp_table>; 2215f30ac26dSJonathan Marek 2216b1dc3c6bSKonrad Dybcio status = "disabled"; 2217b1dc3c6bSKonrad Dybcio 2218f30ac26dSJonathan Marek gmu_opp_table: opp-table { 2219f30ac26dSJonathan Marek compatible = "operating-points-v2"; 2220f30ac26dSJonathan Marek 2221f30ac26dSJonathan Marek opp-200000000 { 2222f30ac26dSJonathan Marek opp-hz = /bits/ 64 <200000000>; 2223f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2224f30ac26dSJonathan Marek }; 2225f30ac26dSJonathan Marek }; 2226f30ac26dSJonathan Marek }; 2227f30ac26dSJonathan Marek 2228f30ac26dSJonathan Marek gpucc: clock-controller@2c90000 { 2229f30ac26dSJonathan Marek compatible = "qcom,sm8150-gpucc"; 2230f30ac26dSJonathan Marek reg = <0 0x02c90000 0 0x9000>; 2231f30ac26dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>, 2232f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2233f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2234f30ac26dSJonathan Marek clock-names = "bi_tcxo", 2235f30ac26dSJonathan Marek "gcc_gpu_gpll0_clk_src", 2236f30ac26dSJonathan Marek "gcc_gpu_gpll0_div_clk_src"; 2237f30ac26dSJonathan Marek #clock-cells = <1>; 2238f30ac26dSJonathan Marek #reset-cells = <1>; 2239f30ac26dSJonathan Marek #power-domain-cells = <1>; 2240f30ac26dSJonathan Marek }; 2241f30ac26dSJonathan Marek 2242f30ac26dSJonathan Marek adreno_smmu: iommu@2ca0000 { 2243f30ac26dSJonathan Marek compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 2244f30ac26dSJonathan Marek reg = <0 0x02ca0000 0 0x10000>; 2245f30ac26dSJonathan Marek #iommu-cells = <2>; 2246f30ac26dSJonathan Marek #global-interrupts = <1>; 2247f30ac26dSJonathan Marek interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2248f30ac26dSJonathan Marek <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2249f30ac26dSJonathan Marek <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2250f30ac26dSJonathan Marek <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2251f30ac26dSJonathan Marek <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2252f30ac26dSJonathan Marek <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2253f30ac26dSJonathan Marek <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2254f30ac26dSJonathan Marek <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2255f30ac26dSJonathan Marek <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2256f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 2257f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2258f30ac26dSJonathan Marek <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2259f30ac26dSJonathan Marek clock-names = "ahb", "bus", "iface"; 2260f30ac26dSJonathan Marek 2261f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>; 2262f30ac26dSJonathan Marek }; 2263f30ac26dSJonathan Marek 2264e13c6d14SVinod Koul tlmm: pinctrl@3100000 { 2265e13c6d14SVinod Koul compatible = "qcom,sm8150-pinctrl"; 2266e13c6d14SVinod Koul reg = <0x0 0x03100000 0x0 0x300000>, 2267e13c6d14SVinod Koul <0x0 0x03500000 0x0 0x300000>, 2268e13c6d14SVinod Koul <0x0 0x03900000 0x0 0x300000>, 2269e13c6d14SVinod Koul <0x0 0x03D00000 0x0 0x300000>; 2270e13c6d14SVinod Koul reg-names = "west", "east", "north", "south"; 2271e13c6d14SVinod Koul interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2272de3abdf3SShawn Guo gpio-ranges = <&tlmm 0 0 176>; 2273e13c6d14SVinod Koul gpio-controller; 2274e13c6d14SVinod Koul #gpio-cells = <2>; 2275e13c6d14SVinod Koul interrupt-controller; 2276e13c6d14SVinod Koul #interrupt-cells = <2>; 22776127d8e4SBhupesh Sharma wakeup-parent = <&pdc>; 227881bee695SCaleb Connolly 227981bee695SCaleb Connolly qup_i2c0_default: qup-i2c0-default { 228081bee695SCaleb Connolly mux { 228181bee695SCaleb Connolly pins = "gpio0", "gpio1"; 228281bee695SCaleb Connolly function = "qup0"; 228381bee695SCaleb Connolly }; 228481bee695SCaleb Connolly 228581bee695SCaleb Connolly config { 228681bee695SCaleb Connolly pins = "gpio0", "gpio1"; 228781bee695SCaleb Connolly drive-strength = <0x02>; 228881bee695SCaleb Connolly bias-disable; 228981bee695SCaleb Connolly }; 229081bee695SCaleb Connolly }; 229181bee695SCaleb Connolly 2292129e1c96SFelipe Balbi qup_spi0_default: qup-spi0-default { 2293129e1c96SFelipe Balbi pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2294129e1c96SFelipe Balbi function = "qup0"; 2295129e1c96SFelipe Balbi drive-strength = <6>; 2296129e1c96SFelipe Balbi bias-disable; 2297129e1c96SFelipe Balbi }; 2298129e1c96SFelipe Balbi 229981bee695SCaleb Connolly qup_i2c1_default: qup-i2c1-default { 230081bee695SCaleb Connolly mux { 230181bee695SCaleb Connolly pins = "gpio114", "gpio115"; 230281bee695SCaleb Connolly function = "qup1"; 230381bee695SCaleb Connolly }; 230481bee695SCaleb Connolly 230581bee695SCaleb Connolly config { 230681bee695SCaleb Connolly pins = "gpio114", "gpio115"; 230781bee695SCaleb Connolly drive-strength = <0x02>; 230881bee695SCaleb Connolly bias-disable; 230981bee695SCaleb Connolly }; 231081bee695SCaleb Connolly }; 231181bee695SCaleb Connolly 2312129e1c96SFelipe Balbi qup_spi1_default: qup-spi1-default { 2313129e1c96SFelipe Balbi pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2314129e1c96SFelipe Balbi function = "qup1"; 2315129e1c96SFelipe Balbi drive-strength = <6>; 2316129e1c96SFelipe Balbi bias-disable; 2317129e1c96SFelipe Balbi }; 2318129e1c96SFelipe Balbi 231981bee695SCaleb Connolly qup_i2c2_default: qup-i2c2-default { 232081bee695SCaleb Connolly mux { 232181bee695SCaleb Connolly pins = "gpio126", "gpio127"; 232281bee695SCaleb Connolly function = "qup2"; 232381bee695SCaleb Connolly }; 232481bee695SCaleb Connolly 232581bee695SCaleb Connolly config { 232681bee695SCaleb Connolly pins = "gpio126", "gpio127"; 232781bee695SCaleb Connolly drive-strength = <0x02>; 232881bee695SCaleb Connolly bias-disable; 232981bee695SCaleb Connolly }; 233081bee695SCaleb Connolly }; 233181bee695SCaleb Connolly 2332129e1c96SFelipe Balbi qup_spi2_default: qup-spi2-default { 2333129e1c96SFelipe Balbi pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2334129e1c96SFelipe Balbi function = "qup2"; 2335129e1c96SFelipe Balbi drive-strength = <6>; 2336129e1c96SFelipe Balbi bias-disable; 2337129e1c96SFelipe Balbi }; 2338129e1c96SFelipe Balbi 233981bee695SCaleb Connolly qup_i2c3_default: qup-i2c3-default { 234081bee695SCaleb Connolly mux { 234181bee695SCaleb Connolly pins = "gpio144", "gpio145"; 234281bee695SCaleb Connolly function = "qup3"; 234381bee695SCaleb Connolly }; 234481bee695SCaleb Connolly 234581bee695SCaleb Connolly config { 234681bee695SCaleb Connolly pins = "gpio144", "gpio145"; 234781bee695SCaleb Connolly drive-strength = <0x02>; 234881bee695SCaleb Connolly bias-disable; 234981bee695SCaleb Connolly }; 235081bee695SCaleb Connolly }; 235181bee695SCaleb Connolly 2352129e1c96SFelipe Balbi qup_spi3_default: qup-spi3-default { 2353129e1c96SFelipe Balbi pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2354129e1c96SFelipe Balbi function = "qup3"; 2355129e1c96SFelipe Balbi drive-strength = <6>; 2356129e1c96SFelipe Balbi bias-disable; 2357129e1c96SFelipe Balbi }; 2358129e1c96SFelipe Balbi 235981bee695SCaleb Connolly qup_i2c4_default: qup-i2c4-default { 236081bee695SCaleb Connolly mux { 236181bee695SCaleb Connolly pins = "gpio51", "gpio52"; 236281bee695SCaleb Connolly function = "qup4"; 236381bee695SCaleb Connolly }; 236481bee695SCaleb Connolly 236581bee695SCaleb Connolly config { 236681bee695SCaleb Connolly pins = "gpio51", "gpio52"; 236781bee695SCaleb Connolly drive-strength = <0x02>; 236881bee695SCaleb Connolly bias-disable; 236981bee695SCaleb Connolly }; 237081bee695SCaleb Connolly }; 237181bee695SCaleb Connolly 2372129e1c96SFelipe Balbi qup_spi4_default: qup-spi4-default { 2373129e1c96SFelipe Balbi pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2374129e1c96SFelipe Balbi function = "qup4"; 2375129e1c96SFelipe Balbi drive-strength = <6>; 2376129e1c96SFelipe Balbi bias-disable; 2377129e1c96SFelipe Balbi }; 2378129e1c96SFelipe Balbi 237981bee695SCaleb Connolly qup_i2c5_default: qup-i2c5-default { 238081bee695SCaleb Connolly mux { 238181bee695SCaleb Connolly pins = "gpio121", "gpio122"; 238281bee695SCaleb Connolly function = "qup5"; 238381bee695SCaleb Connolly }; 238481bee695SCaleb Connolly 238581bee695SCaleb Connolly config { 238681bee695SCaleb Connolly pins = "gpio121", "gpio122"; 238781bee695SCaleb Connolly drive-strength = <0x02>; 238881bee695SCaleb Connolly bias-disable; 238981bee695SCaleb Connolly }; 239081bee695SCaleb Connolly }; 239181bee695SCaleb Connolly 2392129e1c96SFelipe Balbi qup_spi5_default: qup-spi5-default { 2393129e1c96SFelipe Balbi pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2394129e1c96SFelipe Balbi function = "qup5"; 2395129e1c96SFelipe Balbi drive-strength = <6>; 2396129e1c96SFelipe Balbi bias-disable; 2397129e1c96SFelipe Balbi }; 2398129e1c96SFelipe Balbi 239981bee695SCaleb Connolly qup_i2c6_default: qup-i2c6-default { 240081bee695SCaleb Connolly mux { 240181bee695SCaleb Connolly pins = "gpio6", "gpio7"; 240281bee695SCaleb Connolly function = "qup6"; 240381bee695SCaleb Connolly }; 240481bee695SCaleb Connolly 240581bee695SCaleb Connolly config { 240681bee695SCaleb Connolly pins = "gpio6", "gpio7"; 240781bee695SCaleb Connolly drive-strength = <0x02>; 240881bee695SCaleb Connolly bias-disable; 240981bee695SCaleb Connolly }; 241081bee695SCaleb Connolly }; 241181bee695SCaleb Connolly 2412129e1c96SFelipe Balbi qup_spi6_default: qup-spi6_default { 2413129e1c96SFelipe Balbi pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2414129e1c96SFelipe Balbi function = "qup6"; 2415129e1c96SFelipe Balbi drive-strength = <6>; 2416129e1c96SFelipe Balbi bias-disable; 2417129e1c96SFelipe Balbi }; 2418129e1c96SFelipe Balbi 241981bee695SCaleb Connolly qup_i2c7_default: qup-i2c7-default { 242081bee695SCaleb Connolly mux { 242181bee695SCaleb Connolly pins = "gpio98", "gpio99"; 242281bee695SCaleb Connolly function = "qup7"; 242381bee695SCaleb Connolly }; 242481bee695SCaleb Connolly 242581bee695SCaleb Connolly config { 242681bee695SCaleb Connolly pins = "gpio98", "gpio99"; 242781bee695SCaleb Connolly drive-strength = <0x02>; 242881bee695SCaleb Connolly bias-disable; 242981bee695SCaleb Connolly }; 243081bee695SCaleb Connolly }; 243181bee695SCaleb Connolly 2432129e1c96SFelipe Balbi qup_spi7_default: qup-spi7_default { 2433129e1c96SFelipe Balbi pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2434129e1c96SFelipe Balbi function = "qup7"; 2435129e1c96SFelipe Balbi drive-strength = <6>; 2436129e1c96SFelipe Balbi bias-disable; 2437129e1c96SFelipe Balbi }; 2438129e1c96SFelipe Balbi 243981bee695SCaleb Connolly qup_i2c8_default: qup-i2c8-default { 244081bee695SCaleb Connolly mux { 244181bee695SCaleb Connolly pins = "gpio88", "gpio89"; 244281bee695SCaleb Connolly function = "qup8"; 244381bee695SCaleb Connolly }; 244481bee695SCaleb Connolly 244581bee695SCaleb Connolly config { 244681bee695SCaleb Connolly pins = "gpio88", "gpio89"; 244781bee695SCaleb Connolly drive-strength = <0x02>; 244881bee695SCaleb Connolly bias-disable; 244981bee695SCaleb Connolly }; 245081bee695SCaleb Connolly }; 245181bee695SCaleb Connolly 2452129e1c96SFelipe Balbi qup_spi8_default: qup-spi8-default { 2453129e1c96SFelipe Balbi pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2454129e1c96SFelipe Balbi function = "qup8"; 2455129e1c96SFelipe Balbi drive-strength = <6>; 2456129e1c96SFelipe Balbi bias-disable; 2457129e1c96SFelipe Balbi }; 2458129e1c96SFelipe Balbi 245981bee695SCaleb Connolly qup_i2c9_default: qup-i2c9-default { 246081bee695SCaleb Connolly mux { 246181bee695SCaleb Connolly pins = "gpio39", "gpio40"; 246281bee695SCaleb Connolly function = "qup9"; 246381bee695SCaleb Connolly }; 246481bee695SCaleb Connolly 246581bee695SCaleb Connolly config { 246681bee695SCaleb Connolly pins = "gpio39", "gpio40"; 246781bee695SCaleb Connolly drive-strength = <0x02>; 246881bee695SCaleb Connolly bias-disable; 246981bee695SCaleb Connolly }; 247081bee695SCaleb Connolly }; 247181bee695SCaleb Connolly 2472129e1c96SFelipe Balbi qup_spi9_default: qup-spi9-default { 2473129e1c96SFelipe Balbi pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2474129e1c96SFelipe Balbi function = "qup9"; 2475129e1c96SFelipe Balbi drive-strength = <6>; 2476129e1c96SFelipe Balbi bias-disable; 2477129e1c96SFelipe Balbi }; 2478129e1c96SFelipe Balbi 247981bee695SCaleb Connolly qup_i2c10_default: qup-i2c10-default { 248081bee695SCaleb Connolly mux { 248181bee695SCaleb Connolly pins = "gpio9", "gpio10"; 248281bee695SCaleb Connolly function = "qup10"; 248381bee695SCaleb Connolly }; 248481bee695SCaleb Connolly 248581bee695SCaleb Connolly config { 248681bee695SCaleb Connolly pins = "gpio9", "gpio10"; 248781bee695SCaleb Connolly drive-strength = <0x02>; 248881bee695SCaleb Connolly bias-disable; 248981bee695SCaleb Connolly }; 249081bee695SCaleb Connolly }; 249181bee695SCaleb Connolly 2492129e1c96SFelipe Balbi qup_spi10_default: qup-spi10-default { 2493129e1c96SFelipe Balbi pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2494129e1c96SFelipe Balbi function = "qup10"; 2495129e1c96SFelipe Balbi drive-strength = <6>; 2496129e1c96SFelipe Balbi bias-disable; 2497129e1c96SFelipe Balbi }; 2498129e1c96SFelipe Balbi 249981bee695SCaleb Connolly qup_i2c11_default: qup-i2c11-default { 250081bee695SCaleb Connolly mux { 250181bee695SCaleb Connolly pins = "gpio94", "gpio95"; 250281bee695SCaleb Connolly function = "qup11"; 250381bee695SCaleb Connolly }; 250481bee695SCaleb Connolly 250581bee695SCaleb Connolly config { 250681bee695SCaleb Connolly pins = "gpio94", "gpio95"; 250781bee695SCaleb Connolly drive-strength = <0x02>; 250881bee695SCaleb Connolly bias-disable; 250981bee695SCaleb Connolly }; 251081bee695SCaleb Connolly }; 251181bee695SCaleb Connolly 2512129e1c96SFelipe Balbi qup_spi11_default: qup-spi11-default { 2513129e1c96SFelipe Balbi pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2514129e1c96SFelipe Balbi function = "qup11"; 2515129e1c96SFelipe Balbi drive-strength = <6>; 2516129e1c96SFelipe Balbi bias-disable; 2517129e1c96SFelipe Balbi }; 2518129e1c96SFelipe Balbi 251981bee695SCaleb Connolly qup_i2c12_default: qup-i2c12-default { 252081bee695SCaleb Connolly mux { 252181bee695SCaleb Connolly pins = "gpio83", "gpio84"; 252281bee695SCaleb Connolly function = "qup12"; 252381bee695SCaleb Connolly }; 252481bee695SCaleb Connolly 252581bee695SCaleb Connolly config { 252681bee695SCaleb Connolly pins = "gpio83", "gpio84"; 252781bee695SCaleb Connolly drive-strength = <0x02>; 252881bee695SCaleb Connolly bias-disable; 252981bee695SCaleb Connolly }; 253081bee695SCaleb Connolly }; 253181bee695SCaleb Connolly 2532129e1c96SFelipe Balbi qup_spi12_default: qup-spi12-default { 2533129e1c96SFelipe Balbi pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2534129e1c96SFelipe Balbi function = "qup12"; 2535129e1c96SFelipe Balbi drive-strength = <6>; 2536129e1c96SFelipe Balbi bias-disable; 2537129e1c96SFelipe Balbi }; 2538129e1c96SFelipe Balbi 253981bee695SCaleb Connolly qup_i2c13_default: qup-i2c13-default { 254081bee695SCaleb Connolly mux { 254181bee695SCaleb Connolly pins = "gpio43", "gpio44"; 254281bee695SCaleb Connolly function = "qup13"; 254381bee695SCaleb Connolly }; 254481bee695SCaleb Connolly 254581bee695SCaleb Connolly config { 254681bee695SCaleb Connolly pins = "gpio43", "gpio44"; 254781bee695SCaleb Connolly drive-strength = <0x02>; 254881bee695SCaleb Connolly bias-disable; 254981bee695SCaleb Connolly }; 255081bee695SCaleb Connolly }; 255181bee695SCaleb Connolly 2552129e1c96SFelipe Balbi qup_spi13_default: qup-spi13-default { 2553129e1c96SFelipe Balbi pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2554129e1c96SFelipe Balbi function = "qup13"; 2555129e1c96SFelipe Balbi drive-strength = <6>; 2556129e1c96SFelipe Balbi bias-disable; 2557129e1c96SFelipe Balbi }; 2558129e1c96SFelipe Balbi 255981bee695SCaleb Connolly qup_i2c14_default: qup-i2c14-default { 256081bee695SCaleb Connolly mux { 256181bee695SCaleb Connolly pins = "gpio47", "gpio48"; 256281bee695SCaleb Connolly function = "qup14"; 256381bee695SCaleb Connolly }; 256481bee695SCaleb Connolly 256581bee695SCaleb Connolly config { 256681bee695SCaleb Connolly pins = "gpio47", "gpio48"; 256781bee695SCaleb Connolly drive-strength = <0x02>; 256881bee695SCaleb Connolly bias-disable; 256981bee695SCaleb Connolly }; 257081bee695SCaleb Connolly }; 257181bee695SCaleb Connolly 2572129e1c96SFelipe Balbi qup_spi14_default: qup-spi14-default { 2573129e1c96SFelipe Balbi pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2574129e1c96SFelipe Balbi function = "qup14"; 2575129e1c96SFelipe Balbi drive-strength = <6>; 2576129e1c96SFelipe Balbi bias-disable; 2577129e1c96SFelipe Balbi }; 2578129e1c96SFelipe Balbi 257981bee695SCaleb Connolly qup_i2c15_default: qup-i2c15-default { 258081bee695SCaleb Connolly mux { 258181bee695SCaleb Connolly pins = "gpio27", "gpio28"; 258281bee695SCaleb Connolly function = "qup15"; 258381bee695SCaleb Connolly }; 258481bee695SCaleb Connolly 258581bee695SCaleb Connolly config { 258681bee695SCaleb Connolly pins = "gpio27", "gpio28"; 258781bee695SCaleb Connolly drive-strength = <0x02>; 258881bee695SCaleb Connolly bias-disable; 258981bee695SCaleb Connolly }; 259081bee695SCaleb Connolly }; 259181bee695SCaleb Connolly 2592129e1c96SFelipe Balbi qup_spi15_default: qup-spi15-default { 2593129e1c96SFelipe Balbi pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2594129e1c96SFelipe Balbi function = "qup15"; 2595129e1c96SFelipe Balbi drive-strength = <6>; 2596129e1c96SFelipe Balbi bias-disable; 2597129e1c96SFelipe Balbi }; 2598129e1c96SFelipe Balbi 259981bee695SCaleb Connolly qup_i2c16_default: qup-i2c16-default { 260081bee695SCaleb Connolly mux { 260181bee695SCaleb Connolly pins = "gpio86", "gpio85"; 260281bee695SCaleb Connolly function = "qup16"; 260381bee695SCaleb Connolly }; 260481bee695SCaleb Connolly 260581bee695SCaleb Connolly config { 260681bee695SCaleb Connolly pins = "gpio86", "gpio85"; 260781bee695SCaleb Connolly drive-strength = <0x02>; 260881bee695SCaleb Connolly bias-disable; 260981bee695SCaleb Connolly }; 261081bee695SCaleb Connolly }; 261181bee695SCaleb Connolly 2612129e1c96SFelipe Balbi qup_spi16_default: qup-spi16-default { 2613129e1c96SFelipe Balbi pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2614129e1c96SFelipe Balbi function = "qup16"; 2615129e1c96SFelipe Balbi drive-strength = <6>; 2616129e1c96SFelipe Balbi bias-disable; 2617129e1c96SFelipe Balbi }; 2618129e1c96SFelipe Balbi 261981bee695SCaleb Connolly qup_i2c17_default: qup-i2c17-default { 262081bee695SCaleb Connolly mux { 262181bee695SCaleb Connolly pins = "gpio55", "gpio56"; 262281bee695SCaleb Connolly function = "qup17"; 262381bee695SCaleb Connolly }; 262481bee695SCaleb Connolly 262581bee695SCaleb Connolly config { 262681bee695SCaleb Connolly pins = "gpio55", "gpio56"; 262781bee695SCaleb Connolly drive-strength = <0x02>; 262881bee695SCaleb Connolly bias-disable; 262981bee695SCaleb Connolly }; 263081bee695SCaleb Connolly }; 263181bee695SCaleb Connolly 2632129e1c96SFelipe Balbi qup_spi17_default: qup-spi17-default { 2633129e1c96SFelipe Balbi pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2634129e1c96SFelipe Balbi function = "qup17"; 2635129e1c96SFelipe Balbi drive-strength = <6>; 2636129e1c96SFelipe Balbi bias-disable; 2637129e1c96SFelipe Balbi }; 2638129e1c96SFelipe Balbi 263981bee695SCaleb Connolly qup_i2c18_default: qup-i2c18-default { 264081bee695SCaleb Connolly mux { 264181bee695SCaleb Connolly pins = "gpio23", "gpio24"; 264281bee695SCaleb Connolly function = "qup18"; 264381bee695SCaleb Connolly }; 264481bee695SCaleb Connolly 264581bee695SCaleb Connolly config { 264681bee695SCaleb Connolly pins = "gpio23", "gpio24"; 264781bee695SCaleb Connolly drive-strength = <0x02>; 264881bee695SCaleb Connolly bias-disable; 264981bee695SCaleb Connolly }; 265081bee695SCaleb Connolly }; 265181bee695SCaleb Connolly 2652129e1c96SFelipe Balbi qup_spi18_default: qup-spi18-default { 2653129e1c96SFelipe Balbi pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2654129e1c96SFelipe Balbi function = "qup18"; 2655129e1c96SFelipe Balbi drive-strength = <6>; 2656129e1c96SFelipe Balbi bias-disable; 2657129e1c96SFelipe Balbi }; 2658129e1c96SFelipe Balbi 265981bee695SCaleb Connolly qup_i2c19_default: qup-i2c19-default { 266081bee695SCaleb Connolly mux { 266181bee695SCaleb Connolly pins = "gpio57", "gpio58"; 266281bee695SCaleb Connolly function = "qup19"; 266381bee695SCaleb Connolly }; 266481bee695SCaleb Connolly 266581bee695SCaleb Connolly config { 266681bee695SCaleb Connolly pins = "gpio57", "gpio58"; 266781bee695SCaleb Connolly drive-strength = <0x02>; 266881bee695SCaleb Connolly bias-disable; 266981bee695SCaleb Connolly }; 267081bee695SCaleb Connolly }; 2671129e1c96SFelipe Balbi 2672129e1c96SFelipe Balbi qup_spi19_default: qup-spi19-default { 2673129e1c96SFelipe Balbi pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2674129e1c96SFelipe Balbi function = "qup19"; 2675129e1c96SFelipe Balbi drive-strength = <6>; 2676129e1c96SFelipe Balbi bias-disable; 2677129e1c96SFelipe Balbi }; 2678a1c86c68SBhupesh Sharma 2679a1c86c68SBhupesh Sharma pcie0_default_state: pcie0-default { 2680a1c86c68SBhupesh Sharma perst { 2681a1c86c68SBhupesh Sharma pins = "gpio35"; 2682a1c86c68SBhupesh Sharma function = "gpio"; 2683a1c86c68SBhupesh Sharma drive-strength = <2>; 2684a1c86c68SBhupesh Sharma bias-pull-down; 2685a1c86c68SBhupesh Sharma }; 2686a1c86c68SBhupesh Sharma 2687a1c86c68SBhupesh Sharma clkreq { 2688a1c86c68SBhupesh Sharma pins = "gpio36"; 2689a1c86c68SBhupesh Sharma function = "pci_e0"; 2690a1c86c68SBhupesh Sharma drive-strength = <2>; 2691a1c86c68SBhupesh Sharma bias-pull-up; 2692a1c86c68SBhupesh Sharma }; 2693a1c86c68SBhupesh Sharma 2694a1c86c68SBhupesh Sharma wake { 2695a1c86c68SBhupesh Sharma pins = "gpio37"; 2696a1c86c68SBhupesh Sharma function = "gpio"; 2697a1c86c68SBhupesh Sharma drive-strength = <2>; 2698a1c86c68SBhupesh Sharma bias-pull-up; 2699a1c86c68SBhupesh Sharma }; 2700a1c86c68SBhupesh Sharma }; 2701a1c86c68SBhupesh Sharma 2702a1c86c68SBhupesh Sharma pcie1_default_state: pcie1-default { 2703a1c86c68SBhupesh Sharma perst { 2704a1c86c68SBhupesh Sharma pins = "gpio102"; 2705a1c86c68SBhupesh Sharma function = "gpio"; 2706a1c86c68SBhupesh Sharma drive-strength = <2>; 2707a1c86c68SBhupesh Sharma bias-pull-down; 2708a1c86c68SBhupesh Sharma }; 2709a1c86c68SBhupesh Sharma 2710a1c86c68SBhupesh Sharma clkreq { 2711a1c86c68SBhupesh Sharma pins = "gpio103"; 2712a1c86c68SBhupesh Sharma function = "pci_e1"; 2713a1c86c68SBhupesh Sharma drive-strength = <2>; 2714a1c86c68SBhupesh Sharma bias-pull-up; 2715a1c86c68SBhupesh Sharma }; 2716a1c86c68SBhupesh Sharma 2717a1c86c68SBhupesh Sharma wake { 2718a1c86c68SBhupesh Sharma pins = "gpio104"; 2719a1c86c68SBhupesh Sharma function = "gpio"; 2720a1c86c68SBhupesh Sharma drive-strength = <2>; 2721a1c86c68SBhupesh Sharma bias-pull-up; 2722a1c86c68SBhupesh Sharma }; 2723a1c86c68SBhupesh Sharma }; 2724e13c6d14SVinod Koul }; 2725e13c6d14SVinod Koul 272649076351SSibi Sankar remoteproc_mpss: remoteproc@4080000 { 272749076351SSibi Sankar compatible = "qcom,sm8150-mpss-pas"; 272849076351SSibi Sankar reg = <0x0 0x04080000 0x0 0x4040>; 272949076351SSibi Sankar 273049076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 273149076351SSibi Sankar <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 273249076351SSibi Sankar <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 273349076351SSibi Sankar <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 273449076351SSibi Sankar <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 273549076351SSibi Sankar <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 273649076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", "handover", 273749076351SSibi Sankar "stop-ack", "shutdown-ack"; 273849076351SSibi Sankar 273949076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 274049076351SSibi Sankar clock-names = "xo"; 274149076351SSibi Sankar 2742d9d327f6SSibi Sankar power-domains = <&rpmhpd 7>, 2743d0770627SBjorn Andersson <&rpmhpd 0>; 2744d9d327f6SSibi Sankar power-domain-names = "cx", "mss"; 274549076351SSibi Sankar 274649076351SSibi Sankar memory-region = <&mpss_mem>; 274749076351SSibi Sankar 2748d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 2749d9d327f6SSibi Sankar 275049076351SSibi Sankar qcom,smem-states = <&modem_smp2p_out 0>; 275149076351SSibi Sankar qcom,smem-state-names = "stop"; 275249076351SSibi Sankar 2753b1dc3c6bSKonrad Dybcio status = "disabled"; 2754b1dc3c6bSKonrad Dybcio 275549076351SSibi Sankar glink-edge { 275649076351SSibi Sankar interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 275749076351SSibi Sankar label = "modem"; 275849076351SSibi Sankar qcom,remote-pid = <1>; 275949076351SSibi Sankar mboxes = <&apss_shared 12>; 276049076351SSibi Sankar }; 276149076351SSibi Sankar }; 276249076351SSibi Sankar 276324244cefSSai Prakash Ranjan stm@6002000 { 276424244cefSSai Prakash Ranjan compatible = "arm,coresight-stm", "arm,primecell"; 276524244cefSSai Prakash Ranjan reg = <0 0x06002000 0 0x1000>, 276624244cefSSai Prakash Ranjan <0 0x16280000 0 0x180000>; 276724244cefSSai Prakash Ranjan reg-names = "stm-base", "stm-stimulus-base"; 276824244cefSSai Prakash Ranjan 276924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 277024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 277124244cefSSai Prakash Ranjan 277224244cefSSai Prakash Ranjan out-ports { 277324244cefSSai Prakash Ranjan port { 277424244cefSSai Prakash Ranjan stm_out: endpoint { 277524244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_in7>; 277624244cefSSai Prakash Ranjan }; 277724244cefSSai Prakash Ranjan }; 277824244cefSSai Prakash Ranjan }; 277924244cefSSai Prakash Ranjan }; 278024244cefSSai Prakash Ranjan 278124244cefSSai Prakash Ranjan funnel@6041000 { 278224244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 278324244cefSSai Prakash Ranjan reg = <0 0x06041000 0 0x1000>; 278424244cefSSai Prakash Ranjan 278524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 278624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 278724244cefSSai Prakash Ranjan 278824244cefSSai Prakash Ranjan out-ports { 278924244cefSSai Prakash Ranjan port { 279024244cefSSai Prakash Ranjan funnel0_out: endpoint { 279124244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in0>; 279224244cefSSai Prakash Ranjan }; 279324244cefSSai Prakash Ranjan }; 279424244cefSSai Prakash Ranjan }; 279524244cefSSai Prakash Ranjan 279624244cefSSai Prakash Ranjan in-ports { 279724244cefSSai Prakash Ranjan #address-cells = <1>; 279824244cefSSai Prakash Ranjan #size-cells = <0>; 279924244cefSSai Prakash Ranjan 280024244cefSSai Prakash Ranjan port@7 { 280124244cefSSai Prakash Ranjan reg = <7>; 280224244cefSSai Prakash Ranjan funnel0_in7: endpoint { 280324244cefSSai Prakash Ranjan remote-endpoint = <&stm_out>; 280424244cefSSai Prakash Ranjan }; 280524244cefSSai Prakash Ranjan }; 280624244cefSSai Prakash Ranjan }; 280724244cefSSai Prakash Ranjan }; 280824244cefSSai Prakash Ranjan 280924244cefSSai Prakash Ranjan funnel@6042000 { 281024244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 281124244cefSSai Prakash Ranjan reg = <0 0x06042000 0 0x1000>; 281224244cefSSai Prakash Ranjan 281324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 281424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 281524244cefSSai Prakash Ranjan 281624244cefSSai Prakash Ranjan out-ports { 281724244cefSSai Prakash Ranjan port { 281824244cefSSai Prakash Ranjan funnel1_out: endpoint { 281924244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in1>; 282024244cefSSai Prakash Ranjan }; 282124244cefSSai Prakash Ranjan }; 282224244cefSSai Prakash Ranjan }; 282324244cefSSai Prakash Ranjan 282424244cefSSai Prakash Ranjan in-ports { 282524244cefSSai Prakash Ranjan #address-cells = <1>; 282624244cefSSai Prakash Ranjan #size-cells = <0>; 282724244cefSSai Prakash Ranjan 282824244cefSSai Prakash Ranjan port@4 { 282924244cefSSai Prakash Ranjan reg = <4>; 283024244cefSSai Prakash Ranjan funnel1_in4: endpoint { 283124244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_out>; 283224244cefSSai Prakash Ranjan }; 283324244cefSSai Prakash Ranjan }; 283424244cefSSai Prakash Ranjan }; 283524244cefSSai Prakash Ranjan }; 283624244cefSSai Prakash Ranjan 283724244cefSSai Prakash Ranjan funnel@6043000 { 283824244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 283924244cefSSai Prakash Ranjan reg = <0 0x06043000 0 0x1000>; 284024244cefSSai Prakash Ranjan 284124244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 284224244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 284324244cefSSai Prakash Ranjan 284424244cefSSai Prakash Ranjan out-ports { 284524244cefSSai Prakash Ranjan port { 284624244cefSSai Prakash Ranjan funnel2_out: endpoint { 284724244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in2>; 284824244cefSSai Prakash Ranjan }; 284924244cefSSai Prakash Ranjan }; 285024244cefSSai Prakash Ranjan }; 285124244cefSSai Prakash Ranjan 285224244cefSSai Prakash Ranjan in-ports { 285324244cefSSai Prakash Ranjan #address-cells = <1>; 285424244cefSSai Prakash Ranjan #size-cells = <0>; 285524244cefSSai Prakash Ranjan 285624244cefSSai Prakash Ranjan port@2 { 285724244cefSSai Prakash Ranjan reg = <2>; 285824244cefSSai Prakash Ranjan funnel2_in2: endpoint { 285924244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_out>; 286024244cefSSai Prakash Ranjan }; 286124244cefSSai Prakash Ranjan }; 286224244cefSSai Prakash Ranjan }; 286324244cefSSai Prakash Ranjan }; 286424244cefSSai Prakash Ranjan 286524244cefSSai Prakash Ranjan funnel@6045000 { 286624244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 286724244cefSSai Prakash Ranjan reg = <0 0x06045000 0 0x1000>; 286824244cefSSai Prakash Ranjan 286924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 287024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 287124244cefSSai Prakash Ranjan 287224244cefSSai Prakash Ranjan out-ports { 287324244cefSSai Prakash Ranjan port { 287424244cefSSai Prakash Ranjan merge_funnel_out: endpoint { 287524244cefSSai Prakash Ranjan remote-endpoint = <&etf_in>; 287624244cefSSai Prakash Ranjan }; 287724244cefSSai Prakash Ranjan }; 287824244cefSSai Prakash Ranjan }; 287924244cefSSai Prakash Ranjan 288024244cefSSai Prakash Ranjan in-ports { 288124244cefSSai Prakash Ranjan #address-cells = <1>; 288224244cefSSai Prakash Ranjan #size-cells = <0>; 288324244cefSSai Prakash Ranjan 288424244cefSSai Prakash Ranjan port@0 { 288524244cefSSai Prakash Ranjan reg = <0>; 288624244cefSSai Prakash Ranjan merge_funnel_in0: endpoint { 288724244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_out>; 288824244cefSSai Prakash Ranjan }; 288924244cefSSai Prakash Ranjan }; 289024244cefSSai Prakash Ranjan 289124244cefSSai Prakash Ranjan port@1 { 289224244cefSSai Prakash Ranjan reg = <1>; 289324244cefSSai Prakash Ranjan merge_funnel_in1: endpoint { 289424244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_out>; 289524244cefSSai Prakash Ranjan }; 289624244cefSSai Prakash Ranjan }; 289724244cefSSai Prakash Ranjan 289824244cefSSai Prakash Ranjan port@2 { 289924244cefSSai Prakash Ranjan reg = <2>; 290024244cefSSai Prakash Ranjan merge_funnel_in2: endpoint { 290124244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_out>; 290224244cefSSai Prakash Ranjan }; 290324244cefSSai Prakash Ranjan }; 290424244cefSSai Prakash Ranjan }; 290524244cefSSai Prakash Ranjan }; 290624244cefSSai Prakash Ranjan 290724244cefSSai Prakash Ranjan replicator@6046000 { 290824244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 290924244cefSSai Prakash Ranjan reg = <0 0x06046000 0 0x1000>; 291024244cefSSai Prakash Ranjan 291124244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 291224244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 291324244cefSSai Prakash Ranjan 291424244cefSSai Prakash Ranjan out-ports { 291524244cefSSai Prakash Ranjan #address-cells = <1>; 291624244cefSSai Prakash Ranjan #size-cells = <0>; 291724244cefSSai Prakash Ranjan 291824244cefSSai Prakash Ranjan port@0 { 291924244cefSSai Prakash Ranjan reg = <0>; 292024244cefSSai Prakash Ranjan replicator_out0: endpoint { 292124244cefSSai Prakash Ranjan remote-endpoint = <&etr_in>; 292224244cefSSai Prakash Ranjan }; 292324244cefSSai Prakash Ranjan }; 292424244cefSSai Prakash Ranjan 292524244cefSSai Prakash Ranjan port@1 { 292624244cefSSai Prakash Ranjan reg = <1>; 292724244cefSSai Prakash Ranjan replicator_out1: endpoint { 292824244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_in>; 292924244cefSSai Prakash Ranjan }; 293024244cefSSai Prakash Ranjan }; 293124244cefSSai Prakash Ranjan }; 293224244cefSSai Prakash Ranjan 293324244cefSSai Prakash Ranjan in-ports { 293424244cefSSai Prakash Ranjan port { 293524244cefSSai Prakash Ranjan replicator_in0: endpoint { 293624244cefSSai Prakash Ranjan remote-endpoint = <&etf_out>; 293724244cefSSai Prakash Ranjan }; 293824244cefSSai Prakash Ranjan }; 293924244cefSSai Prakash Ranjan }; 294024244cefSSai Prakash Ranjan }; 294124244cefSSai Prakash Ranjan 294224244cefSSai Prakash Ranjan etf@6047000 { 294324244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 294424244cefSSai Prakash Ranjan reg = <0 0x06047000 0 0x1000>; 294524244cefSSai Prakash Ranjan 294624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 294724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 294824244cefSSai Prakash Ranjan 294924244cefSSai Prakash Ranjan out-ports { 295024244cefSSai Prakash Ranjan port { 295124244cefSSai Prakash Ranjan etf_out: endpoint { 295224244cefSSai Prakash Ranjan remote-endpoint = <&replicator_in0>; 295324244cefSSai Prakash Ranjan }; 295424244cefSSai Prakash Ranjan }; 295524244cefSSai Prakash Ranjan }; 295624244cefSSai Prakash Ranjan 295724244cefSSai Prakash Ranjan in-ports { 295824244cefSSai Prakash Ranjan port { 295924244cefSSai Prakash Ranjan etf_in: endpoint { 296024244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_out>; 296124244cefSSai Prakash Ranjan }; 296224244cefSSai Prakash Ranjan }; 296324244cefSSai Prakash Ranjan }; 296424244cefSSai Prakash Ranjan }; 296524244cefSSai Prakash Ranjan 296624244cefSSai Prakash Ranjan etr@6048000 { 296724244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 296824244cefSSai Prakash Ranjan reg = <0 0x06048000 0 0x1000>; 296924244cefSSai Prakash Ranjan iommus = <&apps_smmu 0x05e0 0x0>; 297024244cefSSai Prakash Ranjan 297124244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 297224244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 297324244cefSSai Prakash Ranjan arm,scatter-gather; 297424244cefSSai Prakash Ranjan 297524244cefSSai Prakash Ranjan in-ports { 297624244cefSSai Prakash Ranjan port { 297724244cefSSai Prakash Ranjan etr_in: endpoint { 297824244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out0>; 297924244cefSSai Prakash Ranjan }; 298024244cefSSai Prakash Ranjan }; 298124244cefSSai Prakash Ranjan }; 298224244cefSSai Prakash Ranjan }; 298324244cefSSai Prakash Ranjan 298424244cefSSai Prakash Ranjan replicator@604a000 { 298524244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 298624244cefSSai Prakash Ranjan reg = <0 0x0604a000 0 0x1000>; 298724244cefSSai Prakash Ranjan 298824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 298924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 299024244cefSSai Prakash Ranjan 299124244cefSSai Prakash Ranjan out-ports { 299224244cefSSai Prakash Ranjan #address-cells = <1>; 299324244cefSSai Prakash Ranjan #size-cells = <0>; 299424244cefSSai Prakash Ranjan 299524244cefSSai Prakash Ranjan port@1 { 299624244cefSSai Prakash Ranjan reg = <1>; 299724244cefSSai Prakash Ranjan replicator1_out: endpoint { 299824244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_in>; 299924244cefSSai Prakash Ranjan }; 300024244cefSSai Prakash Ranjan }; 300124244cefSSai Prakash Ranjan }; 300224244cefSSai Prakash Ranjan 300324244cefSSai Prakash Ranjan in-ports { 300424244cefSSai Prakash Ranjan #address-cells = <1>; 300524244cefSSai Prakash Ranjan #size-cells = <0>; 300624244cefSSai Prakash Ranjan 300724244cefSSai Prakash Ranjan port@1 { 300824244cefSSai Prakash Ranjan reg = <1>; 300924244cefSSai Prakash Ranjan replicator1_in: endpoint { 301024244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out1>; 301124244cefSSai Prakash Ranjan }; 301224244cefSSai Prakash Ranjan }; 301324244cefSSai Prakash Ranjan }; 301424244cefSSai Prakash Ranjan }; 301524244cefSSai Prakash Ranjan 301624244cefSSai Prakash Ranjan funnel@6b08000 { 301724244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 301824244cefSSai Prakash Ranjan reg = <0 0x06b08000 0 0x1000>; 301924244cefSSai Prakash Ranjan 302024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 302124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 302224244cefSSai Prakash Ranjan 302324244cefSSai Prakash Ranjan out-ports { 302424244cefSSai Prakash Ranjan port { 302524244cefSSai Prakash Ranjan swao_funnel_out: endpoint { 302624244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_in>; 302724244cefSSai Prakash Ranjan }; 302824244cefSSai Prakash Ranjan }; 302924244cefSSai Prakash Ranjan }; 303024244cefSSai Prakash Ranjan 303124244cefSSai Prakash Ranjan in-ports { 303224244cefSSai Prakash Ranjan #address-cells = <1>; 303324244cefSSai Prakash Ranjan #size-cells = <0>; 303424244cefSSai Prakash Ranjan 303524244cefSSai Prakash Ranjan port@6 { 303624244cefSSai Prakash Ranjan reg = <6>; 303724244cefSSai Prakash Ranjan swao_funnel_in: endpoint { 303824244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_out>; 303924244cefSSai Prakash Ranjan }; 304024244cefSSai Prakash Ranjan }; 304124244cefSSai Prakash Ranjan }; 304224244cefSSai Prakash Ranjan }; 304324244cefSSai Prakash Ranjan 304424244cefSSai Prakash Ranjan etf@6b09000 { 304524244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 304624244cefSSai Prakash Ranjan reg = <0 0x06b09000 0 0x1000>; 304724244cefSSai Prakash Ranjan 304824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 304924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 305024244cefSSai Prakash Ranjan 305124244cefSSai Prakash Ranjan out-ports { 305224244cefSSai Prakash Ranjan port { 305324244cefSSai Prakash Ranjan swao_etf_out: endpoint { 305424244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_in>; 305524244cefSSai Prakash Ranjan }; 305624244cefSSai Prakash Ranjan }; 305724244cefSSai Prakash Ranjan }; 305824244cefSSai Prakash Ranjan 305924244cefSSai Prakash Ranjan in-ports { 306024244cefSSai Prakash Ranjan port { 306124244cefSSai Prakash Ranjan swao_etf_in: endpoint { 306224244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_out>; 306324244cefSSai Prakash Ranjan }; 306424244cefSSai Prakash Ranjan }; 306524244cefSSai Prakash Ranjan }; 306624244cefSSai Prakash Ranjan }; 306724244cefSSai Prakash Ranjan 306824244cefSSai Prakash Ranjan replicator@6b0a000 { 306924244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 307024244cefSSai Prakash Ranjan reg = <0 0x06b0a000 0 0x1000>; 307124244cefSSai Prakash Ranjan 307224244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 307324244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 307424244cefSSai Prakash Ranjan qcom,replicator-loses-context; 307524244cefSSai Prakash Ranjan 307624244cefSSai Prakash Ranjan out-ports { 307724244cefSSai Prakash Ranjan port { 307824244cefSSai Prakash Ranjan swao_replicator_out: endpoint { 307924244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_in4>; 308024244cefSSai Prakash Ranjan }; 308124244cefSSai Prakash Ranjan }; 308224244cefSSai Prakash Ranjan }; 308324244cefSSai Prakash Ranjan 308424244cefSSai Prakash Ranjan in-ports { 308524244cefSSai Prakash Ranjan port { 308624244cefSSai Prakash Ranjan swao_replicator_in: endpoint { 308724244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_out>; 308824244cefSSai Prakash Ranjan }; 308924244cefSSai Prakash Ranjan }; 309024244cefSSai Prakash Ranjan }; 309124244cefSSai Prakash Ranjan }; 309224244cefSSai Prakash Ranjan 309324244cefSSai Prakash Ranjan etm@7040000 { 309424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 309524244cefSSai Prakash Ranjan reg = <0 0x07040000 0 0x1000>; 309624244cefSSai Prakash Ranjan 309724244cefSSai Prakash Ranjan cpu = <&CPU0>; 309824244cefSSai Prakash Ranjan 309924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 310024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 310124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 310224244cefSSai Prakash Ranjan qcom,skip-power-up; 310324244cefSSai Prakash Ranjan 310424244cefSSai Prakash Ranjan out-ports { 310524244cefSSai Prakash Ranjan port { 310624244cefSSai Prakash Ranjan etm0_out: endpoint { 310724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in0>; 310824244cefSSai Prakash Ranjan }; 310924244cefSSai Prakash Ranjan }; 311024244cefSSai Prakash Ranjan }; 311124244cefSSai Prakash Ranjan }; 311224244cefSSai Prakash Ranjan 311324244cefSSai Prakash Ranjan etm@7140000 { 311424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 311524244cefSSai Prakash Ranjan reg = <0 0x07140000 0 0x1000>; 311624244cefSSai Prakash Ranjan 311724244cefSSai Prakash Ranjan cpu = <&CPU1>; 311824244cefSSai Prakash Ranjan 311924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 312024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 312124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 312224244cefSSai Prakash Ranjan qcom,skip-power-up; 312324244cefSSai Prakash Ranjan 312424244cefSSai Prakash Ranjan out-ports { 312524244cefSSai Prakash Ranjan port { 312624244cefSSai Prakash Ranjan etm1_out: endpoint { 312724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in1>; 312824244cefSSai Prakash Ranjan }; 312924244cefSSai Prakash Ranjan }; 313024244cefSSai Prakash Ranjan }; 313124244cefSSai Prakash Ranjan }; 313224244cefSSai Prakash Ranjan 313324244cefSSai Prakash Ranjan etm@7240000 { 313424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 313524244cefSSai Prakash Ranjan reg = <0 0x07240000 0 0x1000>; 313624244cefSSai Prakash Ranjan 313724244cefSSai Prakash Ranjan cpu = <&CPU2>; 313824244cefSSai Prakash Ranjan 313924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 314024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 314124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 314224244cefSSai Prakash Ranjan qcom,skip-power-up; 314324244cefSSai Prakash Ranjan 314424244cefSSai Prakash Ranjan out-ports { 314524244cefSSai Prakash Ranjan port { 314624244cefSSai Prakash Ranjan etm2_out: endpoint { 314724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in2>; 314824244cefSSai Prakash Ranjan }; 314924244cefSSai Prakash Ranjan }; 315024244cefSSai Prakash Ranjan }; 315124244cefSSai Prakash Ranjan }; 315224244cefSSai Prakash Ranjan 315324244cefSSai Prakash Ranjan etm@7340000 { 315424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 315524244cefSSai Prakash Ranjan reg = <0 0x07340000 0 0x1000>; 315624244cefSSai Prakash Ranjan 315724244cefSSai Prakash Ranjan cpu = <&CPU3>; 315824244cefSSai Prakash Ranjan 315924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 316024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 316124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 316224244cefSSai Prakash Ranjan qcom,skip-power-up; 316324244cefSSai Prakash Ranjan 316424244cefSSai Prakash Ranjan out-ports { 316524244cefSSai Prakash Ranjan port { 316624244cefSSai Prakash Ranjan etm3_out: endpoint { 316724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in3>; 316824244cefSSai Prakash Ranjan }; 316924244cefSSai Prakash Ranjan }; 317024244cefSSai Prakash Ranjan }; 317124244cefSSai Prakash Ranjan }; 317224244cefSSai Prakash Ranjan 317324244cefSSai Prakash Ranjan etm@7440000 { 317424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 317524244cefSSai Prakash Ranjan reg = <0 0x07440000 0 0x1000>; 317624244cefSSai Prakash Ranjan 317724244cefSSai Prakash Ranjan cpu = <&CPU4>; 317824244cefSSai Prakash Ranjan 317924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 318024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 318124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 318224244cefSSai Prakash Ranjan qcom,skip-power-up; 318324244cefSSai Prakash Ranjan 318424244cefSSai Prakash Ranjan out-ports { 318524244cefSSai Prakash Ranjan port { 318624244cefSSai Prakash Ranjan etm4_out: endpoint { 318724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in4>; 318824244cefSSai Prakash Ranjan }; 318924244cefSSai Prakash Ranjan }; 319024244cefSSai Prakash Ranjan }; 319124244cefSSai Prakash Ranjan }; 319224244cefSSai Prakash Ranjan 319324244cefSSai Prakash Ranjan etm@7540000 { 319424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 319524244cefSSai Prakash Ranjan reg = <0 0x07540000 0 0x1000>; 319624244cefSSai Prakash Ranjan 319724244cefSSai Prakash Ranjan cpu = <&CPU5>; 319824244cefSSai Prakash Ranjan 319924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 320024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 320124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 320224244cefSSai Prakash Ranjan qcom,skip-power-up; 320324244cefSSai Prakash Ranjan 320424244cefSSai Prakash Ranjan out-ports { 320524244cefSSai Prakash Ranjan port { 320624244cefSSai Prakash Ranjan etm5_out: endpoint { 320724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in5>; 320824244cefSSai Prakash Ranjan }; 320924244cefSSai Prakash Ranjan }; 321024244cefSSai Prakash Ranjan }; 321124244cefSSai Prakash Ranjan }; 321224244cefSSai Prakash Ranjan 321324244cefSSai Prakash Ranjan etm@7640000 { 321424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 321524244cefSSai Prakash Ranjan reg = <0 0x07640000 0 0x1000>; 321624244cefSSai Prakash Ranjan 321724244cefSSai Prakash Ranjan cpu = <&CPU6>; 321824244cefSSai Prakash Ranjan 321924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 322024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 322124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 322224244cefSSai Prakash Ranjan qcom,skip-power-up; 322324244cefSSai Prakash Ranjan 322424244cefSSai Prakash Ranjan out-ports { 322524244cefSSai Prakash Ranjan port { 322624244cefSSai Prakash Ranjan etm6_out: endpoint { 322724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in6>; 322824244cefSSai Prakash Ranjan }; 322924244cefSSai Prakash Ranjan }; 323024244cefSSai Prakash Ranjan }; 323124244cefSSai Prakash Ranjan }; 323224244cefSSai Prakash Ranjan 323324244cefSSai Prakash Ranjan etm@7740000 { 323424244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 323524244cefSSai Prakash Ranjan reg = <0 0x07740000 0 0x1000>; 323624244cefSSai Prakash Ranjan 323724244cefSSai Prakash Ranjan cpu = <&CPU7>; 323824244cefSSai Prakash Ranjan 323924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 324024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 324124244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 324224244cefSSai Prakash Ranjan qcom,skip-power-up; 324324244cefSSai Prakash Ranjan 324424244cefSSai Prakash Ranjan out-ports { 324524244cefSSai Prakash Ranjan port { 324624244cefSSai Prakash Ranjan etm7_out: endpoint { 324724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in7>; 324824244cefSSai Prakash Ranjan }; 324924244cefSSai Prakash Ranjan }; 325024244cefSSai Prakash Ranjan }; 325124244cefSSai Prakash Ranjan }; 325224244cefSSai Prakash Ranjan 325324244cefSSai Prakash Ranjan funnel@7800000 { /* APSS Funnel */ 325424244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 325524244cefSSai Prakash Ranjan reg = <0 0x07800000 0 0x1000>; 325624244cefSSai Prakash Ranjan 325724244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 325824244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 325924244cefSSai Prakash Ranjan 326024244cefSSai Prakash Ranjan out-ports { 326124244cefSSai Prakash Ranjan port { 326224244cefSSai Prakash Ranjan apss_funnel_out: endpoint { 326324244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_in>; 326424244cefSSai Prakash Ranjan }; 326524244cefSSai Prakash Ranjan }; 326624244cefSSai Prakash Ranjan }; 326724244cefSSai Prakash Ranjan 326824244cefSSai Prakash Ranjan in-ports { 326924244cefSSai Prakash Ranjan #address-cells = <1>; 327024244cefSSai Prakash Ranjan #size-cells = <0>; 327124244cefSSai Prakash Ranjan 327224244cefSSai Prakash Ranjan port@0 { 327324244cefSSai Prakash Ranjan reg = <0>; 327424244cefSSai Prakash Ranjan apss_funnel_in0: endpoint { 327524244cefSSai Prakash Ranjan remote-endpoint = <&etm0_out>; 327624244cefSSai Prakash Ranjan }; 327724244cefSSai Prakash Ranjan }; 327824244cefSSai Prakash Ranjan 327924244cefSSai Prakash Ranjan port@1 { 328024244cefSSai Prakash Ranjan reg = <1>; 328124244cefSSai Prakash Ranjan apss_funnel_in1: endpoint { 328224244cefSSai Prakash Ranjan remote-endpoint = <&etm1_out>; 328324244cefSSai Prakash Ranjan }; 328424244cefSSai Prakash Ranjan }; 328524244cefSSai Prakash Ranjan 328624244cefSSai Prakash Ranjan port@2 { 328724244cefSSai Prakash Ranjan reg = <2>; 328824244cefSSai Prakash Ranjan apss_funnel_in2: endpoint { 328924244cefSSai Prakash Ranjan remote-endpoint = <&etm2_out>; 329024244cefSSai Prakash Ranjan }; 329124244cefSSai Prakash Ranjan }; 329224244cefSSai Prakash Ranjan 329324244cefSSai Prakash Ranjan port@3 { 329424244cefSSai Prakash Ranjan reg = <3>; 329524244cefSSai Prakash Ranjan apss_funnel_in3: endpoint { 329624244cefSSai Prakash Ranjan remote-endpoint = <&etm3_out>; 329724244cefSSai Prakash Ranjan }; 329824244cefSSai Prakash Ranjan }; 329924244cefSSai Prakash Ranjan 330024244cefSSai Prakash Ranjan port@4 { 330124244cefSSai Prakash Ranjan reg = <4>; 330224244cefSSai Prakash Ranjan apss_funnel_in4: endpoint { 330324244cefSSai Prakash Ranjan remote-endpoint = <&etm4_out>; 330424244cefSSai Prakash Ranjan }; 330524244cefSSai Prakash Ranjan }; 330624244cefSSai Prakash Ranjan 330724244cefSSai Prakash Ranjan port@5 { 330824244cefSSai Prakash Ranjan reg = <5>; 330924244cefSSai Prakash Ranjan apss_funnel_in5: endpoint { 331024244cefSSai Prakash Ranjan remote-endpoint = <&etm5_out>; 331124244cefSSai Prakash Ranjan }; 331224244cefSSai Prakash Ranjan }; 331324244cefSSai Prakash Ranjan 331424244cefSSai Prakash Ranjan port@6 { 331524244cefSSai Prakash Ranjan reg = <6>; 331624244cefSSai Prakash Ranjan apss_funnel_in6: endpoint { 331724244cefSSai Prakash Ranjan remote-endpoint = <&etm6_out>; 331824244cefSSai Prakash Ranjan }; 331924244cefSSai Prakash Ranjan }; 332024244cefSSai Prakash Ranjan 332124244cefSSai Prakash Ranjan port@7 { 332224244cefSSai Prakash Ranjan reg = <7>; 332324244cefSSai Prakash Ranjan apss_funnel_in7: endpoint { 332424244cefSSai Prakash Ranjan remote-endpoint = <&etm7_out>; 332524244cefSSai Prakash Ranjan }; 332624244cefSSai Prakash Ranjan }; 332724244cefSSai Prakash Ranjan }; 332824244cefSSai Prakash Ranjan }; 332924244cefSSai Prakash Ranjan 333024244cefSSai Prakash Ranjan funnel@7810000 { 333124244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 333224244cefSSai Prakash Ranjan reg = <0 0x07810000 0 0x1000>; 333324244cefSSai Prakash Ranjan 333424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 333524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 333624244cefSSai Prakash Ranjan 333724244cefSSai Prakash Ranjan out-ports { 333824244cefSSai Prakash Ranjan port { 333924244cefSSai Prakash Ranjan apss_merge_funnel_out: endpoint { 334024244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_in2>; 334124244cefSSai Prakash Ranjan }; 334224244cefSSai Prakash Ranjan }; 334324244cefSSai Prakash Ranjan }; 334424244cefSSai Prakash Ranjan 334524244cefSSai Prakash Ranjan in-ports { 334624244cefSSai Prakash Ranjan port { 334724244cefSSai Prakash Ranjan apss_merge_funnel_in: endpoint { 334824244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_out>; 334924244cefSSai Prakash Ranjan }; 335024244cefSSai Prakash Ranjan }; 335124244cefSSai Prakash Ranjan }; 335224244cefSSai Prakash Ranjan }; 335324244cefSSai Prakash Ranjan 335449076351SSibi Sankar remoteproc_cdsp: remoteproc@8300000 { 335549076351SSibi Sankar compatible = "qcom,sm8150-cdsp-pas"; 335649076351SSibi Sankar reg = <0x0 0x08300000 0x0 0x4040>; 335749076351SSibi Sankar 335849076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 335949076351SSibi Sankar <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 336049076351SSibi Sankar <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 336149076351SSibi Sankar <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 336249076351SSibi Sankar <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 336349076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 336449076351SSibi Sankar "handover", "stop-ack"; 336549076351SSibi Sankar 336649076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 336749076351SSibi Sankar clock-names = "xo"; 336849076351SSibi Sankar 3369d9d327f6SSibi Sankar power-domains = <&rpmhpd 7>; 337049076351SSibi Sankar 337149076351SSibi Sankar memory-region = <&cdsp_mem>; 337249076351SSibi Sankar 3373d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 3374d9d327f6SSibi Sankar 337549076351SSibi Sankar qcom,smem-states = <&cdsp_smp2p_out 0>; 337649076351SSibi Sankar qcom,smem-state-names = "stop"; 337749076351SSibi Sankar 337849076351SSibi Sankar status = "disabled"; 337949076351SSibi Sankar 338049076351SSibi Sankar glink-edge { 338149076351SSibi Sankar interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 338249076351SSibi Sankar label = "cdsp"; 338349076351SSibi Sankar qcom,remote-pid = <5>; 338449076351SSibi Sankar mboxes = <&apss_shared 4>; 338581729330SBhupesh Sharma 338681729330SBhupesh Sharma fastrpc { 338781729330SBhupesh Sharma compatible = "qcom,fastrpc"; 338881729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 338981729330SBhupesh Sharma label = "cdsp"; 33908c8ce95bSJeya R qcom,non-secure-domain; 339181729330SBhupesh Sharma #address-cells = <1>; 339281729330SBhupesh Sharma #size-cells = <0>; 339381729330SBhupesh Sharma 339481729330SBhupesh Sharma compute-cb@1 { 339581729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 339681729330SBhupesh Sharma reg = <1>; 3397*1d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1001 0x0460>; 339881729330SBhupesh Sharma }; 339981729330SBhupesh Sharma 340081729330SBhupesh Sharma compute-cb@2 { 340181729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 340281729330SBhupesh Sharma reg = <2>; 3403*1d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1002 0x0460>; 340481729330SBhupesh Sharma }; 340581729330SBhupesh Sharma 340681729330SBhupesh Sharma compute-cb@3 { 340781729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 340881729330SBhupesh Sharma reg = <3>; 3409*1d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1003 0x0460>; 341081729330SBhupesh Sharma }; 341181729330SBhupesh Sharma 341281729330SBhupesh Sharma compute-cb@4 { 341381729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 341481729330SBhupesh Sharma reg = <4>; 3415*1d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1004 0x0460>; 341681729330SBhupesh Sharma }; 341781729330SBhupesh Sharma 341881729330SBhupesh Sharma compute-cb@5 { 341981729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 342081729330SBhupesh Sharma reg = <5>; 3421*1d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1005 0x0460>; 342281729330SBhupesh Sharma }; 342381729330SBhupesh Sharma 342481729330SBhupesh Sharma compute-cb@6 { 342581729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 342681729330SBhupesh Sharma reg = <6>; 3427*1d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1006 0x0460>; 342881729330SBhupesh Sharma }; 342981729330SBhupesh Sharma 343081729330SBhupesh Sharma compute-cb@7 { 343181729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 343281729330SBhupesh Sharma reg = <7>; 3433*1d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1007 0x0460>; 343481729330SBhupesh Sharma }; 343581729330SBhupesh Sharma 343681729330SBhupesh Sharma compute-cb@8 { 343781729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 343881729330SBhupesh Sharma reg = <8>; 3439*1d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1008 0x0460>; 344081729330SBhupesh Sharma }; 344181729330SBhupesh Sharma 344281729330SBhupesh Sharma /* note: secure cb9 in downstream */ 344381729330SBhupesh Sharma }; 344449076351SSibi Sankar }; 344549076351SSibi Sankar }; 344649076351SSibi Sankar 3447b33d2868SJack Pham usb_1_hsphy: phy@88e2000 { 3448b33d2868SJack Pham compatible = "qcom,sm8150-usb-hs-phy", 3449b33d2868SJack Pham "qcom,usb-snps-hs-7nm-phy"; 3450b33d2868SJack Pham reg = <0 0x088e2000 0 0x400>; 3451b33d2868SJack Pham status = "disabled"; 3452b33d2868SJack Pham #phy-cells = <0>; 3453b33d2868SJack Pham 3454b33d2868SJack Pham clocks = <&rpmhcc RPMH_CXO_CLK>; 3455b33d2868SJack Pham clock-names = "ref"; 3456b33d2868SJack Pham 3457b33d2868SJack Pham resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3458b33d2868SJack Pham }; 3459b33d2868SJack Pham 34600c9dde0dSJonathan Marek usb_2_hsphy: phy@88e3000 { 34610c9dde0dSJonathan Marek compatible = "qcom,sm8150-usb-hs-phy", 34620c9dde0dSJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 34630c9dde0dSJonathan Marek reg = <0 0x088e3000 0 0x400>; 34640c9dde0dSJonathan Marek status = "disabled"; 34650c9dde0dSJonathan Marek #phy-cells = <0>; 34660c9dde0dSJonathan Marek 34670c9dde0dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 34680c9dde0dSJonathan Marek clock-names = "ref"; 34690c9dde0dSJonathan Marek 34700c9dde0dSJonathan Marek resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 34710c9dde0dSJonathan Marek }; 34720c9dde0dSJonathan Marek 3473b33d2868SJack Pham usb_1_qmpphy: phy@88e9000 { 3474b33d2868SJack Pham compatible = "qcom,sm8150-qmp-usb3-phy"; 3475b33d2868SJack Pham reg = <0 0x088e9000 0 0x18c>, 3476b33d2868SJack Pham <0 0x088e8000 0 0x10>; 3477b33d2868SJack Pham status = "disabled"; 3478b33d2868SJack Pham #address-cells = <2>; 3479b33d2868SJack Pham #size-cells = <2>; 3480b33d2868SJack Pham ranges; 3481b33d2868SJack Pham 3482b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3483b33d2868SJack Pham <&rpmhcc RPMH_CXO_CLK>, 3484b33d2868SJack Pham <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3485b33d2868SJack Pham <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3486b33d2868SJack Pham clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3487b33d2868SJack Pham 3488b33d2868SJack Pham resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3489b33d2868SJack Pham <&gcc GCC_USB3_PHY_PRIM_BCR>; 3490b33d2868SJack Pham reset-names = "phy", "common"; 3491b33d2868SJack Pham 34921351512fSShawn Guo usb_1_ssphy: phy@88e9200 { 3493b33d2868SJack Pham reg = <0 0x088e9200 0 0x200>, 3494b33d2868SJack Pham <0 0x088e9400 0 0x200>, 3495b33d2868SJack Pham <0 0x088e9c00 0 0x218>, 3496b33d2868SJack Pham <0 0x088e9600 0 0x200>, 3497b33d2868SJack Pham <0 0x088e9800 0 0x200>, 3498b33d2868SJack Pham <0 0x088e9a00 0 0x100>; 34997178d4ccSJonathan Marek #clock-cells = <0>; 3500b33d2868SJack Pham #phy-cells = <0>; 3501b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3502b33d2868SJack Pham clock-names = "pipe0"; 3503b33d2868SJack Pham clock-output-names = "usb3_phy_pipe_clk_src"; 3504b33d2868SJack Pham }; 3505b33d2868SJack Pham }; 3506b33d2868SJack Pham 35070c9dde0dSJonathan Marek usb_2_qmpphy: phy@88eb000 { 35080c9dde0dSJonathan Marek compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 35090c9dde0dSJonathan Marek reg = <0 0x088eb000 0 0x200>; 35100c9dde0dSJonathan Marek status = "disabled"; 35110c9dde0dSJonathan Marek #address-cells = <2>; 35120c9dde0dSJonathan Marek #size-cells = <2>; 35130c9dde0dSJonathan Marek ranges; 35140c9dde0dSJonathan Marek 35150c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 35160c9dde0dSJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 35170c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>, 35180c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 35190c9dde0dSJonathan Marek clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 35200c9dde0dSJonathan Marek 35210c9dde0dSJonathan Marek resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 35220c9dde0dSJonathan Marek <&gcc GCC_USB3_PHY_SEC_BCR>; 35230c9dde0dSJonathan Marek reset-names = "phy", "common"; 35240c9dde0dSJonathan Marek 35251351512fSShawn Guo usb_2_ssphy: phy@88eb200 { 35260c9dde0dSJonathan Marek reg = <0 0x088eb200 0 0x200>, 35270c9dde0dSJonathan Marek <0 0x088eb400 0 0x200>, 35280c9dde0dSJonathan Marek <0 0x088eb800 0 0x800>, 35290c9dde0dSJonathan Marek <0 0x088eb600 0 0x200>; 35307178d4ccSJonathan Marek #clock-cells = <0>; 35310c9dde0dSJonathan Marek #phy-cells = <0>; 35320c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 35330c9dde0dSJonathan Marek clock-names = "pipe0"; 35340c9dde0dSJonathan Marek clock-output-names = "usb3_uni_phy_pipe_clk_src"; 35350c9dde0dSJonathan Marek }; 35360c9dde0dSJonathan Marek }; 35370c9dde0dSJonathan Marek 353896bb736fSBhupesh Sharma sdhc_2: mmc@8804000 { 3539876644c7SBhupesh Sharma compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3540876644c7SBhupesh Sharma reg = <0 0x08804000 0 0x1000>; 3541876644c7SBhupesh Sharma 3542876644c7SBhupesh Sharma interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3543876644c7SBhupesh Sharma <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3544876644c7SBhupesh Sharma interrupt-names = "hc_irq", "pwr_irq"; 3545876644c7SBhupesh Sharma 3546876644c7SBhupesh Sharma clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3547876644c7SBhupesh Sharma <&gcc GCC_SDCC2_APPS_CLK>, 3548876644c7SBhupesh Sharma <&rpmhcc RPMH_CXO_CLK>; 3549876644c7SBhupesh Sharma clock-names = "iface", "core", "xo"; 355095830090SBhupesh Sharma iommus = <&apps_smmu 0x6a0 0x0>; 3551876644c7SBhupesh Sharma qcom,dll-config = <0x0007642c>; 3552876644c7SBhupesh Sharma qcom,ddr-config = <0x80040868>; 3553876644c7SBhupesh Sharma power-domains = <&rpmhpd 0>; 3554876644c7SBhupesh Sharma operating-points-v2 = <&sdhc2_opp_table>; 3555876644c7SBhupesh Sharma 3556876644c7SBhupesh Sharma status = "disabled"; 3557876644c7SBhupesh Sharma 35580e3e6546SKrzysztof Kozlowski sdhc2_opp_table: opp-table { 3559876644c7SBhupesh Sharma compatible = "operating-points-v2"; 3560876644c7SBhupesh Sharma 3561876644c7SBhupesh Sharma opp-19200000 { 3562876644c7SBhupesh Sharma opp-hz = /bits/ 64 <19200000>; 3563876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_min_svs>; 3564876644c7SBhupesh Sharma }; 3565876644c7SBhupesh Sharma 3566876644c7SBhupesh Sharma opp-50000000 { 3567876644c7SBhupesh Sharma opp-hz = /bits/ 64 <50000000>; 3568876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_low_svs>; 3569876644c7SBhupesh Sharma }; 3570876644c7SBhupesh Sharma 3571876644c7SBhupesh Sharma opp-100000000 { 3572876644c7SBhupesh Sharma opp-hz = /bits/ 64 <100000000>; 3573876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_svs>; 3574876644c7SBhupesh Sharma }; 3575876644c7SBhupesh Sharma 3576876644c7SBhupesh Sharma opp-202000000 { 3577876644c7SBhupesh Sharma opp-hz = /bits/ 64 <202000000>; 3578876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_svs_l1>; 3579876644c7SBhupesh Sharma }; 3580876644c7SBhupesh Sharma }; 3581876644c7SBhupesh Sharma }; 3582876644c7SBhupesh Sharma 35835dc43d3bSBhupesh Sharma dc_noc: interconnect@9160000 { 35845dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-dc-noc"; 35855dc43d3bSBhupesh Sharma reg = <0 0x09160000 0 0x3200>; 35865dc43d3bSBhupesh Sharma #interconnect-cells = <1>; 35875dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 35885dc43d3bSBhupesh Sharma }; 35895dc43d3bSBhupesh Sharma 35905dc43d3bSBhupesh Sharma gem_noc: interconnect@9680000 { 35915dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-gem-noc"; 35925dc43d3bSBhupesh Sharma reg = <0 0x09680000 0 0x3e200>; 35935dc43d3bSBhupesh Sharma #interconnect-cells = <1>; 35945dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 35955dc43d3bSBhupesh Sharma }; 35965dc43d3bSBhupesh Sharma 3597b33d2868SJack Pham usb_1: usb@a6f8800 { 3598b33d2868SJack Pham compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3599b33d2868SJack Pham reg = <0 0x0a6f8800 0 0x400>; 3600b33d2868SJack Pham status = "disabled"; 3601b33d2868SJack Pham #address-cells = <2>; 3602b33d2868SJack Pham #size-cells = <2>; 3603b33d2868SJack Pham ranges; 3604b33d2868SJack Pham dma-ranges; 3605b33d2868SJack Pham 3606b33d2868SJack Pham clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3607b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3608b33d2868SJack Pham <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3609b33d2868SJack Pham <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 36108d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3611b33d2868SJack Pham <&gcc GCC_USB3_SEC_CLKREF_CLK>; 36128d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 36138d5fd4e4SKrzysztof Kozlowski "core", 36148d5fd4e4SKrzysztof Kozlowski "iface", 36158d5fd4e4SKrzysztof Kozlowski "sleep", 36168d5fd4e4SKrzysztof Kozlowski "mock_utmi", 36178d5fd4e4SKrzysztof Kozlowski "xo"; 3618b33d2868SJack Pham 3619b33d2868SJack Pham assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3620b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>; 362179493db5SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 3622b33d2868SJack Pham 3623b33d2868SJack Pham interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3624b33d2868SJack Pham <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3625b33d2868SJack Pham <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3626b33d2868SJack Pham <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3627b33d2868SJack Pham interrupt-names = "hs_phy_irq", "ss_phy_irq", 3628b33d2868SJack Pham "dm_hs_phy_irq", "dp_hs_phy_irq"; 3629b33d2868SJack Pham 3630b33d2868SJack Pham power-domains = <&gcc USB30_PRIM_GDSC>; 3631b33d2868SJack Pham 3632b33d2868SJack Pham resets = <&gcc GCC_USB30_PRIM_BCR>; 3633b33d2868SJack Pham 3634b77a1c4dSKrzysztof Kozlowski usb_1_dwc3: usb@a600000 { 3635b33d2868SJack Pham compatible = "snps,dwc3"; 3636b33d2868SJack Pham reg = <0 0x0a600000 0 0xcd00>; 3637b33d2868SJack Pham interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 363848156232SJonathan Marek iommus = <&apps_smmu 0x140 0>; 3639b33d2868SJack Pham snps,dis_u2_susphy_quirk; 3640b33d2868SJack Pham snps,dis_enblslpm_quirk; 3641b33d2868SJack Pham phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3642b33d2868SJack Pham phy-names = "usb2-phy", "usb3-phy"; 3643b33d2868SJack Pham }; 3644b33d2868SJack Pham }; 3645b33d2868SJack Pham 36460c9dde0dSJonathan Marek usb_2: usb@a8f8800 { 36470c9dde0dSJonathan Marek compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 36480c9dde0dSJonathan Marek reg = <0 0x0a8f8800 0 0x400>; 36490c9dde0dSJonathan Marek status = "disabled"; 36500c9dde0dSJonathan Marek #address-cells = <2>; 36510c9dde0dSJonathan Marek #size-cells = <2>; 36520c9dde0dSJonathan Marek ranges; 36530c9dde0dSJonathan Marek dma-ranges; 36540c9dde0dSJonathan Marek 36550c9dde0dSJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 36560c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>, 36570c9dde0dSJonathan Marek <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 36580c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_SLEEP_CLK>, 36598d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 36600c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>; 36618d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 36628d5fd4e4SKrzysztof Kozlowski "core", 36638d5fd4e4SKrzysztof Kozlowski "iface", 36648d5fd4e4SKrzysztof Kozlowski "sleep", 36658d5fd4e4SKrzysztof Kozlowski "mock_utmi", 36668d5fd4e4SKrzysztof Kozlowski "xo"; 36670c9dde0dSJonathan Marek 36680c9dde0dSJonathan Marek assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 36690c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>; 36700c9dde0dSJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 36710c9dde0dSJonathan Marek 36720c9dde0dSJonathan Marek interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 36730c9dde0dSJonathan Marek <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 36740c9dde0dSJonathan Marek <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 36750c9dde0dSJonathan Marek <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 36760c9dde0dSJonathan Marek interrupt-names = "hs_phy_irq", "ss_phy_irq", 36770c9dde0dSJonathan Marek "dm_hs_phy_irq", "dp_hs_phy_irq"; 36780c9dde0dSJonathan Marek 36790c9dde0dSJonathan Marek power-domains = <&gcc USB30_SEC_GDSC>; 36800c9dde0dSJonathan Marek 36810c9dde0dSJonathan Marek resets = <&gcc GCC_USB30_SEC_BCR>; 36820c9dde0dSJonathan Marek 36832aa2b50dSBhupesh Sharma usb_2_dwc3: usb@a800000 { 36840c9dde0dSJonathan Marek compatible = "snps,dwc3"; 36850c9dde0dSJonathan Marek reg = <0 0x0a800000 0 0xcd00>; 36860c9dde0dSJonathan Marek interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 36870c9dde0dSJonathan Marek iommus = <&apps_smmu 0x160 0>; 36880c9dde0dSJonathan Marek snps,dis_u2_susphy_quirk; 36890c9dde0dSJonathan Marek snps,dis_enblslpm_quirk; 36900c9dde0dSJonathan Marek phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 36910c9dde0dSJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 36920c9dde0dSJonathan Marek }; 36930c9dde0dSJonathan Marek }; 36940c9dde0dSJonathan Marek 36956acb71fdSJonathan Marek camnoc_virt: interconnect@ac00000 { 36966acb71fdSJonathan Marek compatible = "qcom,sm8150-camnoc-virt"; 36976acb71fdSJonathan Marek reg = <0 0x0ac00000 0 0x1000>; 36986acb71fdSJonathan Marek #interconnect-cells = <1>; 36996acb71fdSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 37006acb71fdSJonathan Marek }; 37016acb71fdSJonathan Marek 3702397ad946SBhupesh Sharma pdc: interrupt-controller@b220000 { 3703397ad946SBhupesh Sharma compatible = "qcom,sm8150-pdc", "qcom,pdc"; 3704397ad946SBhupesh Sharma reg = <0 0x0b220000 0 0x400>; 3705397ad946SBhupesh Sharma qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3706397ad946SBhupesh Sharma <125 63 1>; 3707397ad946SBhupesh Sharma #interrupt-cells = <2>; 3708397ad946SBhupesh Sharma interrupt-parent = <&intc>; 3709397ad946SBhupesh Sharma interrupt-controller; 3710397ad946SBhupesh Sharma }; 3711397ad946SBhupesh Sharma 3712d8cf9372SVinod Koul aoss_qmp: power-controller@c300000 { 37136ba93ba9SKrzysztof Kozlowski compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 371447cb6a06SMaulik Shah reg = <0x0 0x0c300000 0x0 0x400>; 3715d8cf9372SVinod Koul interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3716d8cf9372SVinod Koul mboxes = <&apss_shared 0>; 3717d8cf9372SVinod Koul 3718d8cf9372SVinod Koul #clock-cells = <0>; 3719d8cf9372SVinod Koul }; 3720d8cf9372SVinod Koul 372147cb6a06SMaulik Shah sram@c3f0000 { 372247cb6a06SMaulik Shah compatible = "qcom,rpmh-stats"; 372347cb6a06SMaulik Shah reg = <0 0x0c3f0000 0 0x400>; 372447cb6a06SMaulik Shah }; 372547cb6a06SMaulik Shah 3726d2fa630cSAmit Kucheria tsens0: thermal-sensor@c263000 { 3727d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3728d2fa630cSAmit Kucheria reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3729d2fa630cSAmit Kucheria <0 0x0c222000 0 0x1ff>; /* SROT */ 3730d2fa630cSAmit Kucheria #qcom,sensors = <16>; 3731d2fa630cSAmit Kucheria interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3732d2fa630cSAmit Kucheria <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3733d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 3734d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 3735d2fa630cSAmit Kucheria }; 3736d2fa630cSAmit Kucheria 3737d2fa630cSAmit Kucheria tsens1: thermal-sensor@c265000 { 3738d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3739d2fa630cSAmit Kucheria reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3740d2fa630cSAmit Kucheria <0 0x0c223000 0 0x1ff>; /* SROT */ 3741d2fa630cSAmit Kucheria #qcom,sensors = <8>; 3742d2fa630cSAmit Kucheria interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3743d2fa630cSAmit Kucheria <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3744d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 3745d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 3746d2fa630cSAmit Kucheria }; 3747d2fa630cSAmit Kucheria 3748e13c6d14SVinod Koul spmi_bus: spmi@c440000 { 3749e13c6d14SVinod Koul compatible = "qcom,spmi-pmic-arb"; 3750e13c6d14SVinod Koul reg = <0x0 0x0c440000 0x0 0x0001100>, 3751e13c6d14SVinod Koul <0x0 0x0c600000 0x0 0x2000000>, 3752e13c6d14SVinod Koul <0x0 0x0e600000 0x0 0x0100000>, 3753e13c6d14SVinod Koul <0x0 0x0e700000 0x0 0x00a0000>, 3754e13c6d14SVinod Koul <0x0 0x0c40a000 0x0 0x0026000>; 3755e13c6d14SVinod Koul reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3756e13c6d14SVinod Koul interrupt-names = "periph_irq"; 3757e13c6d14SVinod Koul interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3758e13c6d14SVinod Koul qcom,ee = <0>; 3759e13c6d14SVinod Koul qcom,channel = <0>; 3760e13c6d14SVinod Koul #address-cells = <2>; 3761e13c6d14SVinod Koul #size-cells = <0>; 3762e13c6d14SVinod Koul interrupt-controller; 3763e13c6d14SVinod Koul #interrupt-cells = <4>; 3764e13c6d14SVinod Koul cell-index = <0>; 3765e13c6d14SVinod Koul }; 3766e13c6d14SVinod Koul 376748156232SJonathan Marek apps_smmu: iommu@15000000 { 376848156232SJonathan Marek compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 376948156232SJonathan Marek reg = <0 0x15000000 0 0x100000>; 377048156232SJonathan Marek #iommu-cells = <2>; 377148156232SJonathan Marek #global-interrupts = <1>; 377248156232SJonathan Marek interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 377348156232SJonathan Marek <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 377448156232SJonathan Marek <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 377548156232SJonathan Marek <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 377648156232SJonathan Marek <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 377748156232SJonathan Marek <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 377848156232SJonathan Marek <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 377948156232SJonathan Marek <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 378048156232SJonathan Marek <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 378148156232SJonathan Marek <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 378248156232SJonathan Marek <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 378348156232SJonathan Marek <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 378448156232SJonathan Marek <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 378548156232SJonathan Marek <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 378648156232SJonathan Marek <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 378748156232SJonathan Marek <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 378848156232SJonathan Marek <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 378948156232SJonathan Marek <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 379048156232SJonathan Marek <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 379148156232SJonathan Marek <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 379248156232SJonathan Marek <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 379348156232SJonathan Marek <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 379448156232SJonathan Marek <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 379548156232SJonathan Marek <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 379648156232SJonathan Marek <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 379748156232SJonathan Marek <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 379848156232SJonathan Marek <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 379948156232SJonathan Marek <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 380048156232SJonathan Marek <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 380148156232SJonathan Marek <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 380248156232SJonathan Marek <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 380348156232SJonathan Marek <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 380448156232SJonathan Marek <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 380548156232SJonathan Marek <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 380648156232SJonathan Marek <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 380748156232SJonathan Marek <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 380848156232SJonathan Marek <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 380948156232SJonathan Marek <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 381048156232SJonathan Marek <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 381148156232SJonathan Marek <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 381248156232SJonathan Marek <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 381348156232SJonathan Marek <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 381448156232SJonathan Marek <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 381548156232SJonathan Marek <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 381648156232SJonathan Marek <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 381748156232SJonathan Marek <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 381848156232SJonathan Marek <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 381948156232SJonathan Marek <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 382048156232SJonathan Marek <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 382148156232SJonathan Marek <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 382248156232SJonathan Marek <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 382348156232SJonathan Marek <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 382448156232SJonathan Marek <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 382548156232SJonathan Marek <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 382648156232SJonathan Marek <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 382748156232SJonathan Marek <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 382848156232SJonathan Marek <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 382948156232SJonathan Marek <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 383048156232SJonathan Marek <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 383148156232SJonathan Marek <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 383248156232SJonathan Marek <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 383348156232SJonathan Marek <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 383448156232SJonathan Marek <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 383548156232SJonathan Marek <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 383648156232SJonathan Marek <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 383748156232SJonathan Marek <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 383848156232SJonathan Marek <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 383948156232SJonathan Marek <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 384048156232SJonathan Marek <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 384148156232SJonathan Marek <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 384248156232SJonathan Marek <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 384348156232SJonathan Marek <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 384448156232SJonathan Marek <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 384548156232SJonathan Marek <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 384648156232SJonathan Marek <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 384748156232SJonathan Marek <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 384848156232SJonathan Marek <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 384948156232SJonathan Marek <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 385048156232SJonathan Marek <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 385148156232SJonathan Marek <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 385248156232SJonathan Marek <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 385348156232SJonathan Marek }; 385448156232SJonathan Marek 385549076351SSibi Sankar remoteproc_adsp: remoteproc@17300000 { 385649076351SSibi Sankar compatible = "qcom,sm8150-adsp-pas"; 385749076351SSibi Sankar reg = <0x0 0x17300000 0x0 0x4040>; 385849076351SSibi Sankar 385949076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 386049076351SSibi Sankar <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 386149076351SSibi Sankar <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 386249076351SSibi Sankar <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 386349076351SSibi Sankar <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 386449076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 386549076351SSibi Sankar "handover", "stop-ack"; 386649076351SSibi Sankar 386749076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 386849076351SSibi Sankar clock-names = "xo"; 386949076351SSibi Sankar 3870d9d327f6SSibi Sankar power-domains = <&rpmhpd 7>; 387149076351SSibi Sankar 387249076351SSibi Sankar memory-region = <&adsp_mem>; 387349076351SSibi Sankar 3874d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 3875d9d327f6SSibi Sankar 387649076351SSibi Sankar qcom,smem-states = <&adsp_smp2p_out 0>; 387749076351SSibi Sankar qcom,smem-state-names = "stop"; 387849076351SSibi Sankar 387949076351SSibi Sankar status = "disabled"; 388049076351SSibi Sankar 388149076351SSibi Sankar glink-edge { 388249076351SSibi Sankar interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 388349076351SSibi Sankar label = "lpass"; 388449076351SSibi Sankar qcom,remote-pid = <2>; 388549076351SSibi Sankar mboxes = <&apss_shared 8>; 388681729330SBhupesh Sharma 388781729330SBhupesh Sharma fastrpc { 388881729330SBhupesh Sharma compatible = "qcom,fastrpc"; 388981729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 389081729330SBhupesh Sharma label = "adsp"; 38918c8ce95bSJeya R qcom,non-secure-domain; 389281729330SBhupesh Sharma #address-cells = <1>; 389381729330SBhupesh Sharma #size-cells = <0>; 389481729330SBhupesh Sharma 389581729330SBhupesh Sharma compute-cb@3 { 389681729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 389781729330SBhupesh Sharma reg = <3>; 389881729330SBhupesh Sharma iommus = <&apps_smmu 0x1b23 0x0>; 389981729330SBhupesh Sharma }; 390081729330SBhupesh Sharma 390181729330SBhupesh Sharma compute-cb@4 { 390281729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 390381729330SBhupesh Sharma reg = <4>; 390481729330SBhupesh Sharma iommus = <&apps_smmu 0x1b24 0x0>; 390581729330SBhupesh Sharma }; 390681729330SBhupesh Sharma 390781729330SBhupesh Sharma compute-cb@5 { 390881729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 390981729330SBhupesh Sharma reg = <5>; 391081729330SBhupesh Sharma iommus = <&apps_smmu 0x1b25 0x0>; 391181729330SBhupesh Sharma }; 391281729330SBhupesh Sharma }; 391349076351SSibi Sankar }; 391449076351SSibi Sankar }; 391549076351SSibi Sankar 3916e13c6d14SVinod Koul intc: interrupt-controller@17a00000 { 3917e13c6d14SVinod Koul compatible = "arm,gic-v3"; 3918e13c6d14SVinod Koul interrupt-controller; 3919e13c6d14SVinod Koul #interrupt-cells = <3>; 3920e13c6d14SVinod Koul reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3921e13c6d14SVinod Koul <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3922e13c6d14SVinod Koul interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3923e13c6d14SVinod Koul }; 3924e13c6d14SVinod Koul 3925d8cf9372SVinod Koul apss_shared: mailbox@17c00000 { 3926d8cf9372SVinod Koul compatible = "qcom,sm8150-apss-shared"; 3927d8cf9372SVinod Koul reg = <0x0 0x17c00000 0x0 0x1000>; 3928d8cf9372SVinod Koul #mbox-cells = <1>; 3929d8cf9372SVinod Koul }; 3930d8cf9372SVinod Koul 3931fb2d8150SSai Prakash Ranjan watchdog@17c10000 { 3932fb2d8150SSai Prakash Ranjan compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 3933fb2d8150SSai Prakash Ranjan reg = <0 0x17c10000 0 0x1000>; 3934fb2d8150SSai Prakash Ranjan clocks = <&sleep_clk>; 3935b094c8f8SSai Prakash Ranjan interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3936fb2d8150SSai Prakash Ranjan }; 3937fb2d8150SSai Prakash Ranjan 3938e13c6d14SVinod Koul timer@17c20000 { 3939458ebdbbSDavid Heidelberg #address-cells = <1>; 3940458ebdbbSDavid Heidelberg #size-cells = <1>; 3941458ebdbbSDavid Heidelberg ranges = <0 0 0 0x20000000>; 3942e13c6d14SVinod Koul compatible = "arm,armv7-timer-mem"; 3943e13c6d14SVinod Koul reg = <0x0 0x17c20000 0x0 0x1000>; 3944e13c6d14SVinod Koul clock-frequency = <19200000>; 3945e13c6d14SVinod Koul 3946e13c6d14SVinod Koul frame@17c21000{ 3947e13c6d14SVinod Koul frame-number = <0>; 3948e13c6d14SVinod Koul interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3949e13c6d14SVinod Koul <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3950458ebdbbSDavid Heidelberg reg = <0x17c21000 0x1000>, 3951458ebdbbSDavid Heidelberg <0x17c22000 0x1000>; 3952e13c6d14SVinod Koul }; 3953e13c6d14SVinod Koul 3954e13c6d14SVinod Koul frame@17c23000 { 3955e13c6d14SVinod Koul frame-number = <1>; 3956e13c6d14SVinod Koul interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3957458ebdbbSDavid Heidelberg reg = <0x17c23000 0x1000>; 3958e13c6d14SVinod Koul status = "disabled"; 3959e13c6d14SVinod Koul }; 3960e13c6d14SVinod Koul 3961e13c6d14SVinod Koul frame@17c25000 { 3962e13c6d14SVinod Koul frame-number = <2>; 3963e13c6d14SVinod Koul interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3964458ebdbbSDavid Heidelberg reg = <0x17c25000 0x1000>; 3965e13c6d14SVinod Koul status = "disabled"; 3966e13c6d14SVinod Koul }; 3967e13c6d14SVinod Koul 3968e13c6d14SVinod Koul frame@17c27000 { 3969e13c6d14SVinod Koul frame-number = <3>; 3970e13c6d14SVinod Koul interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3971458ebdbbSDavid Heidelberg reg = <0x17c26000 0x1000>; 3972e13c6d14SVinod Koul status = "disabled"; 3973e13c6d14SVinod Koul }; 3974e13c6d14SVinod Koul 3975e13c6d14SVinod Koul frame@17c29000 { 3976e13c6d14SVinod Koul frame-number = <4>; 3977e13c6d14SVinod Koul interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3978458ebdbbSDavid Heidelberg reg = <0x17c29000 0x1000>; 3979e13c6d14SVinod Koul status = "disabled"; 3980e13c6d14SVinod Koul }; 3981e13c6d14SVinod Koul 3982e13c6d14SVinod Koul frame@17c2b000 { 3983e13c6d14SVinod Koul frame-number = <5>; 3984e13c6d14SVinod Koul interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3985458ebdbbSDavid Heidelberg reg = <0x17c2b000 0x1000>; 3986e13c6d14SVinod Koul status = "disabled"; 3987e13c6d14SVinod Koul }; 3988e13c6d14SVinod Koul 3989e13c6d14SVinod Koul frame@17c2d000 { 3990e13c6d14SVinod Koul frame-number = <6>; 3991e13c6d14SVinod Koul interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3992458ebdbbSDavid Heidelberg reg = <0x17c2d000 0x1000>; 3993e13c6d14SVinod Koul status = "disabled"; 3994e13c6d14SVinod Koul }; 3995e13c6d14SVinod Koul }; 3996d8cf9372SVinod Koul 3997d8cf9372SVinod Koul apps_rsc: rsc@18200000 { 3998d8cf9372SVinod Koul label = "apps_rsc"; 3999d8cf9372SVinod Koul compatible = "qcom,rpmh-rsc"; 4000d8cf9372SVinod Koul reg = <0x0 0x18200000 0x0 0x10000>, 4001d8cf9372SVinod Koul <0x0 0x18210000 0x0 0x10000>, 4002d8cf9372SVinod Koul <0x0 0x18220000 0x0 0x10000>; 4003d8cf9372SVinod Koul reg-names = "drv-0", "drv-1", "drv-2"; 4004d8cf9372SVinod Koul interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4005d8cf9372SVinod Koul <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4006d8cf9372SVinod Koul <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4007d8cf9372SVinod Koul qcom,tcs-offset = <0xd00>; 4008d8cf9372SVinod Koul qcom,drv-id = <2>; 4009d8cf9372SVinod Koul qcom,tcs-config = <ACTIVE_TCS 2>, 401017ac8af6SMaulik Shah <SLEEP_TCS 3>, 401117ac8af6SMaulik Shah <WAKE_TCS 3>, 401217ac8af6SMaulik Shah <CONTROL_TCS 1>; 4013d8cf9372SVinod Koul 4014d8cf9372SVinod Koul rpmhcc: clock-controller { 4015d8cf9372SVinod Koul compatible = "qcom,sm8150-rpmh-clk"; 4016d8cf9372SVinod Koul #clock-cells = <1>; 4017d8cf9372SVinod Koul clock-names = "xo"; 4018d8cf9372SVinod Koul clocks = <&xo_board>; 4019d8cf9372SVinod Koul }; 4020017e7856SSibi Sankar 4021017e7856SSibi Sankar rpmhpd: power-controller { 4022017e7856SSibi Sankar compatible = "qcom,sm8150-rpmhpd"; 4023017e7856SSibi Sankar #power-domain-cells = <1>; 4024017e7856SSibi Sankar operating-points-v2 = <&rpmhpd_opp_table>; 4025017e7856SSibi Sankar 4026017e7856SSibi Sankar rpmhpd_opp_table: opp-table { 4027017e7856SSibi Sankar compatible = "operating-points-v2"; 4028017e7856SSibi Sankar 4029017e7856SSibi Sankar rpmhpd_opp_ret: opp1 { 4030017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4031017e7856SSibi Sankar }; 4032017e7856SSibi Sankar 4033017e7856SSibi Sankar rpmhpd_opp_min_svs: opp2 { 4034017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4035017e7856SSibi Sankar }; 4036017e7856SSibi Sankar 4037017e7856SSibi Sankar rpmhpd_opp_low_svs: opp3 { 4038017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4039017e7856SSibi Sankar }; 4040017e7856SSibi Sankar 4041017e7856SSibi Sankar rpmhpd_opp_svs: opp4 { 4042017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4043017e7856SSibi Sankar }; 4044017e7856SSibi Sankar 4045017e7856SSibi Sankar rpmhpd_opp_svs_l1: opp5 { 4046017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4047017e7856SSibi Sankar }; 4048017e7856SSibi Sankar 4049017e7856SSibi Sankar rpmhpd_opp_svs_l2: opp6 { 4050017e7856SSibi Sankar opp-level = <224>; 4051017e7856SSibi Sankar }; 4052017e7856SSibi Sankar 4053017e7856SSibi Sankar rpmhpd_opp_nom: opp7 { 4054017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4055017e7856SSibi Sankar }; 4056017e7856SSibi Sankar 4057017e7856SSibi Sankar rpmhpd_opp_nom_l1: opp8 { 4058017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4059017e7856SSibi Sankar }; 4060017e7856SSibi Sankar 4061017e7856SSibi Sankar rpmhpd_opp_nom_l2: opp9 { 4062017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4063017e7856SSibi Sankar }; 4064017e7856SSibi Sankar 4065017e7856SSibi Sankar rpmhpd_opp_turbo: opp10 { 4066017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4067017e7856SSibi Sankar }; 4068017e7856SSibi Sankar 4069017e7856SSibi Sankar rpmhpd_opp_turbo_l1: opp11 { 4070017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4071017e7856SSibi Sankar }; 4072017e7856SSibi Sankar }; 4073017e7856SSibi Sankar }; 407471a2fc6eSJonathan Marek 4075fc0e7dd6SKrzysztof Kozlowski apps_bcm_voter: bcm-voter { 407671a2fc6eSJonathan Marek compatible = "qcom,bcm-voter"; 407771a2fc6eSJonathan Marek }; 4078d8cf9372SVinod Koul }; 4079fea8930bSSibi Sankar 4080a6d435c1SSibi Sankar osm_l3: interconnect@18321000 { 4081a6d435c1SSibi Sankar compatible = "qcom,sm8150-osm-l3"; 4082a6d435c1SSibi Sankar reg = <0 0x18321000 0 0x1400>; 4083a6d435c1SSibi Sankar 4084a6d435c1SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4085a6d435c1SSibi Sankar clock-names = "xo", "alternate"; 4086a6d435c1SSibi Sankar 4087a6d435c1SSibi Sankar #interconnect-cells = <1>; 4088a6d435c1SSibi Sankar }; 4089a6d435c1SSibi Sankar 4090fea8930bSSibi Sankar cpufreq_hw: cpufreq@18323000 { 4091fea8930bSSibi Sankar compatible = "qcom,cpufreq-hw"; 4092fea8930bSSibi Sankar reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 4093fea8930bSSibi Sankar <0 0x18327800 0 0x1400>; 4094fea8930bSSibi Sankar reg-names = "freq-domain0", "freq-domain1", 4095fea8930bSSibi Sankar "freq-domain2"; 4096fea8930bSSibi Sankar 4097fea8930bSSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4098fea8930bSSibi Sankar clock-names = "xo", "alternate"; 4099fea8930bSSibi Sankar 4100fea8930bSSibi Sankar #freq-domain-cells = <1>; 4101fea8930bSSibi Sankar }; 410205090bb9SJonathan Marek 41032ffcfe79SThara Gopinath lmh_cluster1: lmh@18350800 { 41042ffcfe79SThara Gopinath compatible = "qcom,sm8150-lmh"; 41052ffcfe79SThara Gopinath reg = <0 0x18350800 0 0x400>; 41062ffcfe79SThara Gopinath interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 41072ffcfe79SThara Gopinath cpus = <&CPU4>; 41082ffcfe79SThara Gopinath qcom,lmh-temp-arm-millicelsius = <60000>; 41092ffcfe79SThara Gopinath qcom,lmh-temp-low-millicelsius = <84500>; 41102ffcfe79SThara Gopinath qcom,lmh-temp-high-millicelsius = <85000>; 41112ffcfe79SThara Gopinath interrupt-controller; 41122ffcfe79SThara Gopinath #interrupt-cells = <1>; 41132ffcfe79SThara Gopinath }; 41142ffcfe79SThara Gopinath 41152ffcfe79SThara Gopinath lmh_cluster0: lmh@18358800 { 41162ffcfe79SThara Gopinath compatible = "qcom,sm8150-lmh"; 41172ffcfe79SThara Gopinath reg = <0 0x18358800 0 0x400>; 41182ffcfe79SThara Gopinath interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 41192ffcfe79SThara Gopinath cpus = <&CPU0>; 41202ffcfe79SThara Gopinath qcom,lmh-temp-arm-millicelsius = <60000>; 41212ffcfe79SThara Gopinath qcom,lmh-temp-low-millicelsius = <84500>; 41222ffcfe79SThara Gopinath qcom,lmh-temp-high-millicelsius = <85000>; 41232ffcfe79SThara Gopinath interrupt-controller; 41242ffcfe79SThara Gopinath #interrupt-cells = <1>; 41252ffcfe79SThara Gopinath }; 41262ffcfe79SThara Gopinath 412705090bb9SJonathan Marek wifi: wifi@18800000 { 412805090bb9SJonathan Marek compatible = "qcom,wcn3990-wifi"; 412905090bb9SJonathan Marek reg = <0 0x18800000 0 0x800000>; 413005090bb9SJonathan Marek reg-names = "membase"; 413105090bb9SJonathan Marek memory-region = <&wlan_mem>; 413205090bb9SJonathan Marek clock-names = "cxo_ref_clk_pin", "qdss"; 413305090bb9SJonathan Marek clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 413405090bb9SJonathan Marek interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 413505090bb9SJonathan Marek <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 413605090bb9SJonathan Marek <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 413705090bb9SJonathan Marek <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 413805090bb9SJonathan Marek <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 413905090bb9SJonathan Marek <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 414005090bb9SJonathan Marek <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 414105090bb9SJonathan Marek <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 414205090bb9SJonathan Marek <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 414305090bb9SJonathan Marek <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 414405090bb9SJonathan Marek <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 414505090bb9SJonathan Marek <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 414605090bb9SJonathan Marek iommus = <&apps_smmu 0x0640 0x1>; 414705090bb9SJonathan Marek status = "disabled"; 414805090bb9SJonathan Marek }; 4149e13c6d14SVinod Koul }; 4150e13c6d14SVinod Koul 4151e13c6d14SVinod Koul timer { 4152e13c6d14SVinod Koul compatible = "arm,armv8-timer"; 4153e13c6d14SVinod Koul interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4154e13c6d14SVinod Koul <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4155e13c6d14SVinod Koul <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4156e13c6d14SVinod Koul <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4157e13c6d14SVinod Koul }; 4158d2fa630cSAmit Kucheria 4159d2fa630cSAmit Kucheria thermal-zones { 4160d2fa630cSAmit Kucheria cpu0-thermal { 4161d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4162d2fa630cSAmit Kucheria polling-delay = <1000>; 4163d2fa630cSAmit Kucheria 4164d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 1>; 4165d2fa630cSAmit Kucheria 4166d2fa630cSAmit Kucheria trips { 4167d2fa630cSAmit Kucheria cpu0_alert0: trip-point0 { 4168d2fa630cSAmit Kucheria temperature = <90000>; 4169d2fa630cSAmit Kucheria hysteresis = <2000>; 4170d2fa630cSAmit Kucheria type = "passive"; 4171d2fa630cSAmit Kucheria }; 4172d2fa630cSAmit Kucheria 4173d2fa630cSAmit Kucheria cpu0_alert1: trip-point1 { 4174d2fa630cSAmit Kucheria temperature = <95000>; 4175d2fa630cSAmit Kucheria hysteresis = <2000>; 4176d2fa630cSAmit Kucheria type = "passive"; 4177d2fa630cSAmit Kucheria }; 4178d2fa630cSAmit Kucheria 4179d2fa630cSAmit Kucheria cpu0_crit: cpu_crit { 4180d2fa630cSAmit Kucheria temperature = <110000>; 4181d2fa630cSAmit Kucheria hysteresis = <1000>; 4182d2fa630cSAmit Kucheria type = "critical"; 4183d2fa630cSAmit Kucheria }; 4184d2fa630cSAmit Kucheria }; 4185d2fa630cSAmit Kucheria 4186d2fa630cSAmit Kucheria cooling-maps { 4187d2fa630cSAmit Kucheria map0 { 4188d2fa630cSAmit Kucheria trip = <&cpu0_alert0>; 4189d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4190d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4191d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4192d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4193d2fa630cSAmit Kucheria }; 4194d2fa630cSAmit Kucheria map1 { 4195d2fa630cSAmit Kucheria trip = <&cpu0_alert1>; 4196d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4197d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4198d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4199d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4200d2fa630cSAmit Kucheria }; 4201d2fa630cSAmit Kucheria }; 4202d2fa630cSAmit Kucheria }; 4203d2fa630cSAmit Kucheria 4204d2fa630cSAmit Kucheria cpu1-thermal { 4205d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4206d2fa630cSAmit Kucheria polling-delay = <1000>; 4207d2fa630cSAmit Kucheria 4208d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 2>; 4209d2fa630cSAmit Kucheria 4210d2fa630cSAmit Kucheria trips { 4211d2fa630cSAmit Kucheria cpu1_alert0: trip-point0 { 4212d2fa630cSAmit Kucheria temperature = <90000>; 4213d2fa630cSAmit Kucheria hysteresis = <2000>; 4214d2fa630cSAmit Kucheria type = "passive"; 4215d2fa630cSAmit Kucheria }; 4216d2fa630cSAmit Kucheria 4217d2fa630cSAmit Kucheria cpu1_alert1: trip-point1 { 4218d2fa630cSAmit Kucheria temperature = <95000>; 4219d2fa630cSAmit Kucheria hysteresis = <2000>; 4220d2fa630cSAmit Kucheria type = "passive"; 4221d2fa630cSAmit Kucheria }; 4222d2fa630cSAmit Kucheria 4223d2fa630cSAmit Kucheria cpu1_crit: cpu_crit { 4224d2fa630cSAmit Kucheria temperature = <110000>; 4225d2fa630cSAmit Kucheria hysteresis = <1000>; 4226d2fa630cSAmit Kucheria type = "critical"; 4227d2fa630cSAmit Kucheria }; 4228d2fa630cSAmit Kucheria }; 4229d2fa630cSAmit Kucheria 4230d2fa630cSAmit Kucheria cooling-maps { 4231d2fa630cSAmit Kucheria map0 { 4232d2fa630cSAmit Kucheria trip = <&cpu1_alert0>; 4233d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4234d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4235d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4236d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4237d2fa630cSAmit Kucheria }; 4238d2fa630cSAmit Kucheria map1 { 4239d2fa630cSAmit Kucheria trip = <&cpu1_alert1>; 4240d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4241d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4242d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4243d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4244d2fa630cSAmit Kucheria }; 4245d2fa630cSAmit Kucheria }; 4246d2fa630cSAmit Kucheria }; 4247d2fa630cSAmit Kucheria 4248d2fa630cSAmit Kucheria cpu2-thermal { 4249d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4250d2fa630cSAmit Kucheria polling-delay = <1000>; 4251d2fa630cSAmit Kucheria 4252d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 3>; 4253d2fa630cSAmit Kucheria 4254d2fa630cSAmit Kucheria trips { 4255d2fa630cSAmit Kucheria cpu2_alert0: trip-point0 { 4256d2fa630cSAmit Kucheria temperature = <90000>; 4257d2fa630cSAmit Kucheria hysteresis = <2000>; 4258d2fa630cSAmit Kucheria type = "passive"; 4259d2fa630cSAmit Kucheria }; 4260d2fa630cSAmit Kucheria 4261d2fa630cSAmit Kucheria cpu2_alert1: trip-point1 { 4262d2fa630cSAmit Kucheria temperature = <95000>; 4263d2fa630cSAmit Kucheria hysteresis = <2000>; 4264d2fa630cSAmit Kucheria type = "passive"; 4265d2fa630cSAmit Kucheria }; 4266d2fa630cSAmit Kucheria 4267d2fa630cSAmit Kucheria cpu2_crit: cpu_crit { 4268d2fa630cSAmit Kucheria temperature = <110000>; 4269d2fa630cSAmit Kucheria hysteresis = <1000>; 4270d2fa630cSAmit Kucheria type = "critical"; 4271d2fa630cSAmit Kucheria }; 4272d2fa630cSAmit Kucheria }; 4273d2fa630cSAmit Kucheria 4274d2fa630cSAmit Kucheria cooling-maps { 4275d2fa630cSAmit Kucheria map0 { 4276d2fa630cSAmit Kucheria trip = <&cpu2_alert0>; 4277d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4278d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4279d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4280d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4281d2fa630cSAmit Kucheria }; 4282d2fa630cSAmit Kucheria map1 { 4283d2fa630cSAmit Kucheria trip = <&cpu2_alert1>; 4284d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4285d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4286d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4287d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4288d2fa630cSAmit Kucheria }; 4289d2fa630cSAmit Kucheria }; 4290d2fa630cSAmit Kucheria }; 4291d2fa630cSAmit Kucheria 4292d2fa630cSAmit Kucheria cpu3-thermal { 4293d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4294d2fa630cSAmit Kucheria polling-delay = <1000>; 4295d2fa630cSAmit Kucheria 4296d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 4>; 4297d2fa630cSAmit Kucheria 4298d2fa630cSAmit Kucheria trips { 4299d2fa630cSAmit Kucheria cpu3_alert0: trip-point0 { 4300d2fa630cSAmit Kucheria temperature = <90000>; 4301d2fa630cSAmit Kucheria hysteresis = <2000>; 4302d2fa630cSAmit Kucheria type = "passive"; 4303d2fa630cSAmit Kucheria }; 4304d2fa630cSAmit Kucheria 4305d2fa630cSAmit Kucheria cpu3_alert1: trip-point1 { 4306d2fa630cSAmit Kucheria temperature = <95000>; 4307d2fa630cSAmit Kucheria hysteresis = <2000>; 4308d2fa630cSAmit Kucheria type = "passive"; 4309d2fa630cSAmit Kucheria }; 4310d2fa630cSAmit Kucheria 4311d2fa630cSAmit Kucheria cpu3_crit: cpu_crit { 4312d2fa630cSAmit Kucheria temperature = <110000>; 4313d2fa630cSAmit Kucheria hysteresis = <1000>; 4314d2fa630cSAmit Kucheria type = "critical"; 4315d2fa630cSAmit Kucheria }; 4316d2fa630cSAmit Kucheria }; 4317d2fa630cSAmit Kucheria 4318d2fa630cSAmit Kucheria cooling-maps { 4319d2fa630cSAmit Kucheria map0 { 4320d2fa630cSAmit Kucheria trip = <&cpu3_alert0>; 4321d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4322d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4323d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4324d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4325d2fa630cSAmit Kucheria }; 4326d2fa630cSAmit Kucheria map1 { 4327d2fa630cSAmit Kucheria trip = <&cpu3_alert1>; 4328d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4329d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4330d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4331d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4332d2fa630cSAmit Kucheria }; 4333d2fa630cSAmit Kucheria }; 4334d2fa630cSAmit Kucheria }; 4335d2fa630cSAmit Kucheria 4336d2fa630cSAmit Kucheria cpu4-top-thermal { 4337d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4338d2fa630cSAmit Kucheria polling-delay = <1000>; 4339d2fa630cSAmit Kucheria 4340d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 7>; 4341d2fa630cSAmit Kucheria 4342d2fa630cSAmit Kucheria trips { 4343d2fa630cSAmit Kucheria cpu4_top_alert0: trip-point0 { 4344d2fa630cSAmit Kucheria temperature = <90000>; 4345d2fa630cSAmit Kucheria hysteresis = <2000>; 4346d2fa630cSAmit Kucheria type = "passive"; 4347d2fa630cSAmit Kucheria }; 4348d2fa630cSAmit Kucheria 4349d2fa630cSAmit Kucheria cpu4_top_alert1: trip-point1 { 4350d2fa630cSAmit Kucheria temperature = <95000>; 4351d2fa630cSAmit Kucheria hysteresis = <2000>; 4352d2fa630cSAmit Kucheria type = "passive"; 4353d2fa630cSAmit Kucheria }; 4354d2fa630cSAmit Kucheria 4355d2fa630cSAmit Kucheria cpu4_top_crit: cpu_crit { 4356d2fa630cSAmit Kucheria temperature = <110000>; 4357d2fa630cSAmit Kucheria hysteresis = <1000>; 4358d2fa630cSAmit Kucheria type = "critical"; 4359d2fa630cSAmit Kucheria }; 4360d2fa630cSAmit Kucheria }; 4361d2fa630cSAmit Kucheria 4362d2fa630cSAmit Kucheria cooling-maps { 4363d2fa630cSAmit Kucheria map0 { 4364d2fa630cSAmit Kucheria trip = <&cpu4_top_alert0>; 4365d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4366d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4367d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4368d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4369d2fa630cSAmit Kucheria }; 4370d2fa630cSAmit Kucheria map1 { 4371d2fa630cSAmit Kucheria trip = <&cpu4_top_alert1>; 4372d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4373d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4374d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4375d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4376d2fa630cSAmit Kucheria }; 4377d2fa630cSAmit Kucheria }; 4378d2fa630cSAmit Kucheria }; 4379d2fa630cSAmit Kucheria 4380d2fa630cSAmit Kucheria cpu5-top-thermal { 4381d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4382d2fa630cSAmit Kucheria polling-delay = <1000>; 4383d2fa630cSAmit Kucheria 4384d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 8>; 4385d2fa630cSAmit Kucheria 4386d2fa630cSAmit Kucheria trips { 4387d2fa630cSAmit Kucheria cpu5_top_alert0: trip-point0 { 4388d2fa630cSAmit Kucheria temperature = <90000>; 4389d2fa630cSAmit Kucheria hysteresis = <2000>; 4390d2fa630cSAmit Kucheria type = "passive"; 4391d2fa630cSAmit Kucheria }; 4392d2fa630cSAmit Kucheria 4393d2fa630cSAmit Kucheria cpu5_top_alert1: trip-point1 { 4394d2fa630cSAmit Kucheria temperature = <95000>; 4395d2fa630cSAmit Kucheria hysteresis = <2000>; 4396d2fa630cSAmit Kucheria type = "passive"; 4397d2fa630cSAmit Kucheria }; 4398d2fa630cSAmit Kucheria 4399d2fa630cSAmit Kucheria cpu5_top_crit: cpu_crit { 4400d2fa630cSAmit Kucheria temperature = <110000>; 4401d2fa630cSAmit Kucheria hysteresis = <1000>; 4402d2fa630cSAmit Kucheria type = "critical"; 4403d2fa630cSAmit Kucheria }; 4404d2fa630cSAmit Kucheria }; 4405d2fa630cSAmit Kucheria 4406d2fa630cSAmit Kucheria cooling-maps { 4407d2fa630cSAmit Kucheria map0 { 4408d2fa630cSAmit Kucheria trip = <&cpu5_top_alert0>; 4409d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4410d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4411d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4412d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4413d2fa630cSAmit Kucheria }; 4414d2fa630cSAmit Kucheria map1 { 4415d2fa630cSAmit Kucheria trip = <&cpu5_top_alert1>; 4416d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4417d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4418d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4419d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4420d2fa630cSAmit Kucheria }; 4421d2fa630cSAmit Kucheria }; 4422d2fa630cSAmit Kucheria }; 4423d2fa630cSAmit Kucheria 4424d2fa630cSAmit Kucheria cpu6-top-thermal { 4425d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4426d2fa630cSAmit Kucheria polling-delay = <1000>; 4427d2fa630cSAmit Kucheria 4428d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 9>; 4429d2fa630cSAmit Kucheria 4430d2fa630cSAmit Kucheria trips { 4431d2fa630cSAmit Kucheria cpu6_top_alert0: trip-point0 { 4432d2fa630cSAmit Kucheria temperature = <90000>; 4433d2fa630cSAmit Kucheria hysteresis = <2000>; 4434d2fa630cSAmit Kucheria type = "passive"; 4435d2fa630cSAmit Kucheria }; 4436d2fa630cSAmit Kucheria 4437d2fa630cSAmit Kucheria cpu6_top_alert1: trip-point1 { 4438d2fa630cSAmit Kucheria temperature = <95000>; 4439d2fa630cSAmit Kucheria hysteresis = <2000>; 4440d2fa630cSAmit Kucheria type = "passive"; 4441d2fa630cSAmit Kucheria }; 4442d2fa630cSAmit Kucheria 4443d2fa630cSAmit Kucheria cpu6_top_crit: cpu_crit { 4444d2fa630cSAmit Kucheria temperature = <110000>; 4445d2fa630cSAmit Kucheria hysteresis = <1000>; 4446d2fa630cSAmit Kucheria type = "critical"; 4447d2fa630cSAmit Kucheria }; 4448d2fa630cSAmit Kucheria }; 4449d2fa630cSAmit Kucheria 4450d2fa630cSAmit Kucheria cooling-maps { 4451d2fa630cSAmit Kucheria map0 { 4452d2fa630cSAmit Kucheria trip = <&cpu6_top_alert0>; 4453d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4454d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4455d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4456d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4457d2fa630cSAmit Kucheria }; 4458d2fa630cSAmit Kucheria map1 { 4459d2fa630cSAmit Kucheria trip = <&cpu6_top_alert1>; 4460d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4461d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4462d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4463d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4464d2fa630cSAmit Kucheria }; 4465d2fa630cSAmit Kucheria }; 4466d2fa630cSAmit Kucheria }; 4467d2fa630cSAmit Kucheria 4468d2fa630cSAmit Kucheria cpu7-top-thermal { 4469d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4470d2fa630cSAmit Kucheria polling-delay = <1000>; 4471d2fa630cSAmit Kucheria 4472d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 10>; 4473d2fa630cSAmit Kucheria 4474d2fa630cSAmit Kucheria trips { 4475d2fa630cSAmit Kucheria cpu7_top_alert0: trip-point0 { 4476d2fa630cSAmit Kucheria temperature = <90000>; 4477d2fa630cSAmit Kucheria hysteresis = <2000>; 4478d2fa630cSAmit Kucheria type = "passive"; 4479d2fa630cSAmit Kucheria }; 4480d2fa630cSAmit Kucheria 4481d2fa630cSAmit Kucheria cpu7_top_alert1: trip-point1 { 4482d2fa630cSAmit Kucheria temperature = <95000>; 4483d2fa630cSAmit Kucheria hysteresis = <2000>; 4484d2fa630cSAmit Kucheria type = "passive"; 4485d2fa630cSAmit Kucheria }; 4486d2fa630cSAmit Kucheria 4487d2fa630cSAmit Kucheria cpu7_top_crit: cpu_crit { 4488d2fa630cSAmit Kucheria temperature = <110000>; 4489d2fa630cSAmit Kucheria hysteresis = <1000>; 4490d2fa630cSAmit Kucheria type = "critical"; 4491d2fa630cSAmit Kucheria }; 4492d2fa630cSAmit Kucheria }; 4493d2fa630cSAmit Kucheria 4494d2fa630cSAmit Kucheria cooling-maps { 4495d2fa630cSAmit Kucheria map0 { 4496d2fa630cSAmit Kucheria trip = <&cpu7_top_alert0>; 4497d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4498d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4499d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4500d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4501d2fa630cSAmit Kucheria }; 4502d2fa630cSAmit Kucheria map1 { 4503d2fa630cSAmit Kucheria trip = <&cpu7_top_alert1>; 4504d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4505d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4506d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4507d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4508d2fa630cSAmit Kucheria }; 4509d2fa630cSAmit Kucheria }; 4510d2fa630cSAmit Kucheria }; 4511d2fa630cSAmit Kucheria 4512d2fa630cSAmit Kucheria cpu4-bottom-thermal { 4513d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4514d2fa630cSAmit Kucheria polling-delay = <1000>; 4515d2fa630cSAmit Kucheria 4516d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 11>; 4517d2fa630cSAmit Kucheria 4518d2fa630cSAmit Kucheria trips { 4519d2fa630cSAmit Kucheria cpu4_bottom_alert0: trip-point0 { 4520d2fa630cSAmit Kucheria temperature = <90000>; 4521d2fa630cSAmit Kucheria hysteresis = <2000>; 4522d2fa630cSAmit Kucheria type = "passive"; 4523d2fa630cSAmit Kucheria }; 4524d2fa630cSAmit Kucheria 4525d2fa630cSAmit Kucheria cpu4_bottom_alert1: trip-point1 { 4526d2fa630cSAmit Kucheria temperature = <95000>; 4527d2fa630cSAmit Kucheria hysteresis = <2000>; 4528d2fa630cSAmit Kucheria type = "passive"; 4529d2fa630cSAmit Kucheria }; 4530d2fa630cSAmit Kucheria 4531d2fa630cSAmit Kucheria cpu4_bottom_crit: cpu_crit { 4532d2fa630cSAmit Kucheria temperature = <110000>; 4533d2fa630cSAmit Kucheria hysteresis = <1000>; 4534d2fa630cSAmit Kucheria type = "critical"; 4535d2fa630cSAmit Kucheria }; 4536d2fa630cSAmit Kucheria }; 4537d2fa630cSAmit Kucheria 4538d2fa630cSAmit Kucheria cooling-maps { 4539d2fa630cSAmit Kucheria map0 { 4540d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert0>; 4541d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4542d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4543d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4544d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4545d2fa630cSAmit Kucheria }; 4546d2fa630cSAmit Kucheria map1 { 4547d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert1>; 4548d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4549d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4550d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4551d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4552d2fa630cSAmit Kucheria }; 4553d2fa630cSAmit Kucheria }; 4554d2fa630cSAmit Kucheria }; 4555d2fa630cSAmit Kucheria 4556d2fa630cSAmit Kucheria cpu5-bottom-thermal { 4557d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4558d2fa630cSAmit Kucheria polling-delay = <1000>; 4559d2fa630cSAmit Kucheria 4560d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 12>; 4561d2fa630cSAmit Kucheria 4562d2fa630cSAmit Kucheria trips { 4563d2fa630cSAmit Kucheria cpu5_bottom_alert0: trip-point0 { 4564d2fa630cSAmit Kucheria temperature = <90000>; 4565d2fa630cSAmit Kucheria hysteresis = <2000>; 4566d2fa630cSAmit Kucheria type = "passive"; 4567d2fa630cSAmit Kucheria }; 4568d2fa630cSAmit Kucheria 4569d2fa630cSAmit Kucheria cpu5_bottom_alert1: trip-point1 { 4570d2fa630cSAmit Kucheria temperature = <95000>; 4571d2fa630cSAmit Kucheria hysteresis = <2000>; 4572d2fa630cSAmit Kucheria type = "passive"; 4573d2fa630cSAmit Kucheria }; 4574d2fa630cSAmit Kucheria 4575d2fa630cSAmit Kucheria cpu5_bottom_crit: cpu_crit { 4576d2fa630cSAmit Kucheria temperature = <110000>; 4577d2fa630cSAmit Kucheria hysteresis = <1000>; 4578d2fa630cSAmit Kucheria type = "critical"; 4579d2fa630cSAmit Kucheria }; 4580d2fa630cSAmit Kucheria }; 4581d2fa630cSAmit Kucheria 4582d2fa630cSAmit Kucheria cooling-maps { 4583d2fa630cSAmit Kucheria map0 { 4584d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert0>; 4585d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4586d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4587d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4588d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4589d2fa630cSAmit Kucheria }; 4590d2fa630cSAmit Kucheria map1 { 4591d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert1>; 4592d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4593d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4594d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4595d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4596d2fa630cSAmit Kucheria }; 4597d2fa630cSAmit Kucheria }; 4598d2fa630cSAmit Kucheria }; 4599d2fa630cSAmit Kucheria 4600d2fa630cSAmit Kucheria cpu6-bottom-thermal { 4601d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4602d2fa630cSAmit Kucheria polling-delay = <1000>; 4603d2fa630cSAmit Kucheria 4604d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 13>; 4605d2fa630cSAmit Kucheria 4606d2fa630cSAmit Kucheria trips { 4607d2fa630cSAmit Kucheria cpu6_bottom_alert0: trip-point0 { 4608d2fa630cSAmit Kucheria temperature = <90000>; 4609d2fa630cSAmit Kucheria hysteresis = <2000>; 4610d2fa630cSAmit Kucheria type = "passive"; 4611d2fa630cSAmit Kucheria }; 4612d2fa630cSAmit Kucheria 4613d2fa630cSAmit Kucheria cpu6_bottom_alert1: trip-point1 { 4614d2fa630cSAmit Kucheria temperature = <95000>; 4615d2fa630cSAmit Kucheria hysteresis = <2000>; 4616d2fa630cSAmit Kucheria type = "passive"; 4617d2fa630cSAmit Kucheria }; 4618d2fa630cSAmit Kucheria 4619d2fa630cSAmit Kucheria cpu6_bottom_crit: cpu_crit { 4620d2fa630cSAmit Kucheria temperature = <110000>; 4621d2fa630cSAmit Kucheria hysteresis = <1000>; 4622d2fa630cSAmit Kucheria type = "critical"; 4623d2fa630cSAmit Kucheria }; 4624d2fa630cSAmit Kucheria }; 4625d2fa630cSAmit Kucheria 4626d2fa630cSAmit Kucheria cooling-maps { 4627d2fa630cSAmit Kucheria map0 { 4628d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert0>; 4629d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4630d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4631d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4632d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4633d2fa630cSAmit Kucheria }; 4634d2fa630cSAmit Kucheria map1 { 4635d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert1>; 4636d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4637d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4638d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4639d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4640d2fa630cSAmit Kucheria }; 4641d2fa630cSAmit Kucheria }; 4642d2fa630cSAmit Kucheria }; 4643d2fa630cSAmit Kucheria 4644d2fa630cSAmit Kucheria cpu7-bottom-thermal { 4645d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4646d2fa630cSAmit Kucheria polling-delay = <1000>; 4647d2fa630cSAmit Kucheria 4648d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 14>; 4649d2fa630cSAmit Kucheria 4650d2fa630cSAmit Kucheria trips { 4651d2fa630cSAmit Kucheria cpu7_bottom_alert0: trip-point0 { 4652d2fa630cSAmit Kucheria temperature = <90000>; 4653d2fa630cSAmit Kucheria hysteresis = <2000>; 4654d2fa630cSAmit Kucheria type = "passive"; 4655d2fa630cSAmit Kucheria }; 4656d2fa630cSAmit Kucheria 4657d2fa630cSAmit Kucheria cpu7_bottom_alert1: trip-point1 { 4658d2fa630cSAmit Kucheria temperature = <95000>; 4659d2fa630cSAmit Kucheria hysteresis = <2000>; 4660d2fa630cSAmit Kucheria type = "passive"; 4661d2fa630cSAmit Kucheria }; 4662d2fa630cSAmit Kucheria 4663d2fa630cSAmit Kucheria cpu7_bottom_crit: cpu_crit { 4664d2fa630cSAmit Kucheria temperature = <110000>; 4665d2fa630cSAmit Kucheria hysteresis = <1000>; 4666d2fa630cSAmit Kucheria type = "critical"; 4667d2fa630cSAmit Kucheria }; 4668d2fa630cSAmit Kucheria }; 4669d2fa630cSAmit Kucheria 4670d2fa630cSAmit Kucheria cooling-maps { 4671d2fa630cSAmit Kucheria map0 { 4672d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert0>; 4673d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4674d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4675d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4676d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4677d2fa630cSAmit Kucheria }; 4678d2fa630cSAmit Kucheria map1 { 4679d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert1>; 4680d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4681d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4682d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4683d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4684d2fa630cSAmit Kucheria }; 4685d2fa630cSAmit Kucheria }; 4686d2fa630cSAmit Kucheria }; 4687d2fa630cSAmit Kucheria 4688d2fa630cSAmit Kucheria aoss0-thermal { 4689d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4690d2fa630cSAmit Kucheria polling-delay = <1000>; 4691d2fa630cSAmit Kucheria 4692d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 0>; 4693d2fa630cSAmit Kucheria 4694d2fa630cSAmit Kucheria trips { 4695d2fa630cSAmit Kucheria aoss0_alert0: trip-point0 { 4696d2fa630cSAmit Kucheria temperature = <90000>; 4697d2fa630cSAmit Kucheria hysteresis = <2000>; 4698d2fa630cSAmit Kucheria type = "hot"; 4699d2fa630cSAmit Kucheria }; 4700d2fa630cSAmit Kucheria }; 4701d2fa630cSAmit Kucheria }; 4702d2fa630cSAmit Kucheria 4703d2fa630cSAmit Kucheria cluster0-thermal { 4704d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4705d2fa630cSAmit Kucheria polling-delay = <1000>; 4706d2fa630cSAmit Kucheria 4707d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 5>; 4708d2fa630cSAmit Kucheria 4709d2fa630cSAmit Kucheria trips { 4710d2fa630cSAmit Kucheria cluster0_alert0: trip-point0 { 4711d2fa630cSAmit Kucheria temperature = <90000>; 4712d2fa630cSAmit Kucheria hysteresis = <2000>; 4713d2fa630cSAmit Kucheria type = "hot"; 4714d2fa630cSAmit Kucheria }; 4715d2fa630cSAmit Kucheria cluster0_crit: cluster0_crit { 4716d2fa630cSAmit Kucheria temperature = <110000>; 4717d2fa630cSAmit Kucheria hysteresis = <2000>; 4718d2fa630cSAmit Kucheria type = "critical"; 4719d2fa630cSAmit Kucheria }; 4720d2fa630cSAmit Kucheria }; 4721d2fa630cSAmit Kucheria }; 4722d2fa630cSAmit Kucheria 4723d2fa630cSAmit Kucheria cluster1-thermal { 4724d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4725d2fa630cSAmit Kucheria polling-delay = <1000>; 4726d2fa630cSAmit Kucheria 4727d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 6>; 4728d2fa630cSAmit Kucheria 4729d2fa630cSAmit Kucheria trips { 4730d2fa630cSAmit Kucheria cluster1_alert0: trip-point0 { 4731d2fa630cSAmit Kucheria temperature = <90000>; 4732d2fa630cSAmit Kucheria hysteresis = <2000>; 4733d2fa630cSAmit Kucheria type = "hot"; 4734d2fa630cSAmit Kucheria }; 4735d2fa630cSAmit Kucheria cluster1_crit: cluster1_crit { 4736d2fa630cSAmit Kucheria temperature = <110000>; 4737d2fa630cSAmit Kucheria hysteresis = <2000>; 4738d2fa630cSAmit Kucheria type = "critical"; 4739d2fa630cSAmit Kucheria }; 4740d2fa630cSAmit Kucheria }; 4741d2fa630cSAmit Kucheria }; 4742d2fa630cSAmit Kucheria 47437be1c395SDavid Heidelberg gpu-top-thermal { 4744d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4745d2fa630cSAmit Kucheria polling-delay = <1000>; 4746d2fa630cSAmit Kucheria 4747d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 15>; 4748d2fa630cSAmit Kucheria 4749d2fa630cSAmit Kucheria trips { 4750d2fa630cSAmit Kucheria gpu1_alert0: trip-point0 { 4751d2fa630cSAmit Kucheria temperature = <90000>; 4752d2fa630cSAmit Kucheria hysteresis = <2000>; 4753d2fa630cSAmit Kucheria type = "hot"; 4754d2fa630cSAmit Kucheria }; 4755d2fa630cSAmit Kucheria }; 4756d2fa630cSAmit Kucheria }; 4757d2fa630cSAmit Kucheria 4758d2fa630cSAmit Kucheria aoss1-thermal { 4759d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4760d2fa630cSAmit Kucheria polling-delay = <1000>; 4761d2fa630cSAmit Kucheria 4762d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 0>; 4763d2fa630cSAmit Kucheria 4764d2fa630cSAmit Kucheria trips { 4765d2fa630cSAmit Kucheria aoss1_alert0: trip-point0 { 4766d2fa630cSAmit Kucheria temperature = <90000>; 4767d2fa630cSAmit Kucheria hysteresis = <2000>; 4768d2fa630cSAmit Kucheria type = "hot"; 4769d2fa630cSAmit Kucheria }; 4770d2fa630cSAmit Kucheria }; 4771d2fa630cSAmit Kucheria }; 4772d2fa630cSAmit Kucheria 4773d2fa630cSAmit Kucheria wlan-thermal { 4774d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4775d2fa630cSAmit Kucheria polling-delay = <1000>; 4776d2fa630cSAmit Kucheria 4777d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 1>; 4778d2fa630cSAmit Kucheria 4779d2fa630cSAmit Kucheria trips { 4780d2fa630cSAmit Kucheria wlan_alert0: trip-point0 { 4781d2fa630cSAmit Kucheria temperature = <90000>; 4782d2fa630cSAmit Kucheria hysteresis = <2000>; 4783d2fa630cSAmit Kucheria type = "hot"; 4784d2fa630cSAmit Kucheria }; 4785d2fa630cSAmit Kucheria }; 4786d2fa630cSAmit Kucheria }; 4787d2fa630cSAmit Kucheria 4788d2fa630cSAmit Kucheria video-thermal { 4789d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4790d2fa630cSAmit Kucheria polling-delay = <1000>; 4791d2fa630cSAmit Kucheria 4792d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 2>; 4793d2fa630cSAmit Kucheria 4794d2fa630cSAmit Kucheria trips { 4795d2fa630cSAmit Kucheria video_alert0: trip-point0 { 4796d2fa630cSAmit Kucheria temperature = <90000>; 4797d2fa630cSAmit Kucheria hysteresis = <2000>; 4798d2fa630cSAmit Kucheria type = "hot"; 4799d2fa630cSAmit Kucheria }; 4800d2fa630cSAmit Kucheria }; 4801d2fa630cSAmit Kucheria }; 4802d2fa630cSAmit Kucheria 4803d2fa630cSAmit Kucheria mem-thermal { 4804d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4805d2fa630cSAmit Kucheria polling-delay = <1000>; 4806d2fa630cSAmit Kucheria 4807d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 3>; 4808d2fa630cSAmit Kucheria 4809d2fa630cSAmit Kucheria trips { 4810d2fa630cSAmit Kucheria mem_alert0: trip-point0 { 4811d2fa630cSAmit Kucheria temperature = <90000>; 4812d2fa630cSAmit Kucheria hysteresis = <2000>; 4813d2fa630cSAmit Kucheria type = "hot"; 4814d2fa630cSAmit Kucheria }; 4815d2fa630cSAmit Kucheria }; 4816d2fa630cSAmit Kucheria }; 4817d2fa630cSAmit Kucheria 4818d2fa630cSAmit Kucheria q6-hvx-thermal { 4819d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4820d2fa630cSAmit Kucheria polling-delay = <1000>; 4821d2fa630cSAmit Kucheria 4822d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 4>; 4823d2fa630cSAmit Kucheria 4824d2fa630cSAmit Kucheria trips { 4825d2fa630cSAmit Kucheria q6_hvx_alert0: trip-point0 { 4826d2fa630cSAmit Kucheria temperature = <90000>; 4827d2fa630cSAmit Kucheria hysteresis = <2000>; 4828d2fa630cSAmit Kucheria type = "hot"; 4829d2fa630cSAmit Kucheria }; 4830d2fa630cSAmit Kucheria }; 4831d2fa630cSAmit Kucheria }; 4832d2fa630cSAmit Kucheria 4833d2fa630cSAmit Kucheria camera-thermal { 4834d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4835d2fa630cSAmit Kucheria polling-delay = <1000>; 4836d2fa630cSAmit Kucheria 4837d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 5>; 4838d2fa630cSAmit Kucheria 4839d2fa630cSAmit Kucheria trips { 4840d2fa630cSAmit Kucheria camera_alert0: trip-point0 { 4841d2fa630cSAmit Kucheria temperature = <90000>; 4842d2fa630cSAmit Kucheria hysteresis = <2000>; 4843d2fa630cSAmit Kucheria type = "hot"; 4844d2fa630cSAmit Kucheria }; 4845d2fa630cSAmit Kucheria }; 4846d2fa630cSAmit Kucheria }; 4847d2fa630cSAmit Kucheria 4848d2fa630cSAmit Kucheria compute-thermal { 4849d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4850d2fa630cSAmit Kucheria polling-delay = <1000>; 4851d2fa630cSAmit Kucheria 4852d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 6>; 4853d2fa630cSAmit Kucheria 4854d2fa630cSAmit Kucheria trips { 4855d2fa630cSAmit Kucheria compute_alert0: trip-point0 { 4856d2fa630cSAmit Kucheria temperature = <90000>; 4857d2fa630cSAmit Kucheria hysteresis = <2000>; 4858d2fa630cSAmit Kucheria type = "hot"; 4859d2fa630cSAmit Kucheria }; 4860d2fa630cSAmit Kucheria }; 4861d2fa630cSAmit Kucheria }; 4862d2fa630cSAmit Kucheria 4863d2fa630cSAmit Kucheria modem-thermal { 4864d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4865d2fa630cSAmit Kucheria polling-delay = <1000>; 4866d2fa630cSAmit Kucheria 4867d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 7>; 4868d2fa630cSAmit Kucheria 4869d2fa630cSAmit Kucheria trips { 4870d2fa630cSAmit Kucheria modem_alert0: trip-point0 { 4871d2fa630cSAmit Kucheria temperature = <90000>; 4872d2fa630cSAmit Kucheria hysteresis = <2000>; 4873d2fa630cSAmit Kucheria type = "hot"; 4874d2fa630cSAmit Kucheria }; 4875d2fa630cSAmit Kucheria }; 4876d2fa630cSAmit Kucheria }; 4877d2fa630cSAmit Kucheria 4878d2fa630cSAmit Kucheria npu-thermal { 4879d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4880d2fa630cSAmit Kucheria polling-delay = <1000>; 4881d2fa630cSAmit Kucheria 4882d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 8>; 4883d2fa630cSAmit Kucheria 4884d2fa630cSAmit Kucheria trips { 4885d2fa630cSAmit Kucheria npu_alert0: trip-point0 { 4886d2fa630cSAmit Kucheria temperature = <90000>; 4887d2fa630cSAmit Kucheria hysteresis = <2000>; 4888d2fa630cSAmit Kucheria type = "hot"; 4889d2fa630cSAmit Kucheria }; 4890d2fa630cSAmit Kucheria }; 4891d2fa630cSAmit Kucheria }; 4892d2fa630cSAmit Kucheria 4893d2fa630cSAmit Kucheria modem-vec-thermal { 4894d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4895d2fa630cSAmit Kucheria polling-delay = <1000>; 4896d2fa630cSAmit Kucheria 4897d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 9>; 4898d2fa630cSAmit Kucheria 4899d2fa630cSAmit Kucheria trips { 4900d2fa630cSAmit Kucheria modem_vec_alert0: trip-point0 { 4901d2fa630cSAmit Kucheria temperature = <90000>; 4902d2fa630cSAmit Kucheria hysteresis = <2000>; 4903d2fa630cSAmit Kucheria type = "hot"; 4904d2fa630cSAmit Kucheria }; 4905d2fa630cSAmit Kucheria }; 4906d2fa630cSAmit Kucheria }; 4907d2fa630cSAmit Kucheria 4908d2fa630cSAmit Kucheria modem-scl-thermal { 4909d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4910d2fa630cSAmit Kucheria polling-delay = <1000>; 4911d2fa630cSAmit Kucheria 4912d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 10>; 4913d2fa630cSAmit Kucheria 4914d2fa630cSAmit Kucheria trips { 4915d2fa630cSAmit Kucheria modem_scl_alert0: trip-point0 { 4916d2fa630cSAmit Kucheria temperature = <90000>; 4917d2fa630cSAmit Kucheria hysteresis = <2000>; 4918d2fa630cSAmit Kucheria type = "hot"; 4919d2fa630cSAmit Kucheria }; 4920d2fa630cSAmit Kucheria }; 4921d2fa630cSAmit Kucheria }; 4922d2fa630cSAmit Kucheria 49237be1c395SDavid Heidelberg gpu-bottom-thermal { 4924d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4925d2fa630cSAmit Kucheria polling-delay = <1000>; 4926d2fa630cSAmit Kucheria 4927d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 11>; 4928d2fa630cSAmit Kucheria 4929d2fa630cSAmit Kucheria trips { 4930d2fa630cSAmit Kucheria gpu2_alert0: trip-point0 { 4931d2fa630cSAmit Kucheria temperature = <90000>; 4932d2fa630cSAmit Kucheria hysteresis = <2000>; 4933d2fa630cSAmit Kucheria type = "hot"; 4934d2fa630cSAmit Kucheria }; 4935d2fa630cSAmit Kucheria }; 4936d2fa630cSAmit Kucheria }; 4937d2fa630cSAmit Kucheria }; 4938e13c6d14SVinod Koul}; 4939