1e13c6d14SVinod Koul// SPDX-License-Identifier: BSD-3-Clause 2e13c6d14SVinod Koul/* 3e13c6d14SVinod Koul * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4e13c6d14SVinod Koul * Copyright (c) 2019, Linaro Limited 5e13c6d14SVinod Koul */ 6e13c6d14SVinod Koul 705006290SFelipe Balbi#include <dt-bindings/dma/qcom-gpi.h> 8e13c6d14SVinod Koul#include <dt-bindings/interrupt-controller/arm-gic.h> 9017e7856SSibi Sankar#include <dt-bindings/power/qcom-rpmpd.h> 10e13c6d14SVinod Koul#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11e13c6d14SVinod Koul#include <dt-bindings/clock/qcom,rpmh.h> 1298874a46SKonrad Dybcio#include <dt-bindings/clock/qcom,dispcc-sm8150.h> 13d6f55763SVinod Koul#include <dt-bindings/clock/qcom,gcc-sm8150.h> 14f1269916SJonathan Marek#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 15a6d435c1SSibi Sankar#include <dt-bindings/interconnect/qcom,osm-l3.h> 162b6187abSThara Gopinath#include <dt-bindings/interconnect/qcom,sm8150.h> 17d2fa630cSAmit Kucheria#include <dt-bindings/thermal/thermal.h> 18e13c6d14SVinod Koul 19e13c6d14SVinod Koul/ { 20e13c6d14SVinod Koul interrupt-parent = <&intc>; 21e13c6d14SVinod Koul 22e13c6d14SVinod Koul #address-cells = <2>; 23e13c6d14SVinod Koul #size-cells = <2>; 24e13c6d14SVinod Koul 25e13c6d14SVinod Koul chosen { }; 26e13c6d14SVinod Koul 27e13c6d14SVinod Koul clocks { 28e13c6d14SVinod Koul xo_board: xo-board { 29e13c6d14SVinod Koul compatible = "fixed-clock"; 30e13c6d14SVinod Koul #clock-cells = <0>; 31e13c6d14SVinod Koul clock-frequency = <38400000>; 32e13c6d14SVinod Koul clock-output-names = "xo_board"; 33e13c6d14SVinod Koul }; 34e13c6d14SVinod Koul 35e13c6d14SVinod Koul sleep_clk: sleep-clk { 36e13c6d14SVinod Koul compatible = "fixed-clock"; 37e13c6d14SVinod Koul #clock-cells = <0>; 38e13c6d14SVinod Koul clock-frequency = <32764>; 39e13c6d14SVinod Koul clock-output-names = "sleep_clk"; 40e13c6d14SVinod Koul }; 41e13c6d14SVinod Koul }; 42e13c6d14SVinod Koul 43e13c6d14SVinod Koul cpus { 44e13c6d14SVinod Koul #address-cells = <2>; 45e13c6d14SVinod Koul #size-cells = <0>; 46e13c6d14SVinod Koul 47e13c6d14SVinod Koul CPU0: cpu@0 { 48e13c6d14SVinod Koul device_type = "cpu"; 49e13c6d14SVinod Koul compatible = "qcom,kryo485"; 50e13c6d14SVinod Koul reg = <0x0 0x0>; 51fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 52e13c6d14SVinod Koul enable-method = "psci"; 535b2dae72SDanny Lin capacity-dmips-mhz = <488>; 545b2dae72SDanny Lin dynamic-power-coefficient = <232>; 55e13c6d14SVinod Koul next-level-cache = <&L2_0>; 56fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 572b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 582b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 592b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 60b2e3f897SDanny Lin power-domains = <&CPU_PD0>; 61b2e3f897SDanny Lin power-domain-names = "psci"; 62d2fa630cSAmit Kucheria #cooling-cells = <2>; 63e13c6d14SVinod Koul L2_0: l2-cache { 64e13c6d14SVinod Koul compatible = "cache"; 659435294cSPierre Gondois cache-level = <2>; 66e13c6d14SVinod Koul next-level-cache = <&L3_0>; 67e13c6d14SVinod Koul L3_0: l3-cache { 68e13c6d14SVinod Koul compatible = "cache"; 699435294cSPierre Gondois cache-level = <3>; 70e13c6d14SVinod Koul }; 71e13c6d14SVinod Koul }; 72e13c6d14SVinod Koul }; 73e13c6d14SVinod Koul 74e13c6d14SVinod Koul CPU1: cpu@100 { 75e13c6d14SVinod Koul device_type = "cpu"; 76e13c6d14SVinod Koul compatible = "qcom,kryo485"; 77e13c6d14SVinod Koul reg = <0x0 0x100>; 78fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 79e13c6d14SVinod Koul enable-method = "psci"; 805b2dae72SDanny Lin capacity-dmips-mhz = <488>; 815b2dae72SDanny Lin dynamic-power-coefficient = <232>; 82e13c6d14SVinod Koul next-level-cache = <&L2_100>; 83fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 842b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 852b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 862b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 87b2e3f897SDanny Lin power-domains = <&CPU_PD1>; 88b2e3f897SDanny Lin power-domain-names = "psci"; 89d2fa630cSAmit Kucheria #cooling-cells = <2>; 90e13c6d14SVinod Koul L2_100: l2-cache { 91e13c6d14SVinod Koul compatible = "cache"; 929435294cSPierre Gondois cache-level = <2>; 93e13c6d14SVinod Koul next-level-cache = <&L3_0>; 94e13c6d14SVinod Koul }; 95e13c6d14SVinod Koul }; 96e13c6d14SVinod Koul 97e13c6d14SVinod Koul CPU2: cpu@200 { 98e13c6d14SVinod Koul device_type = "cpu"; 99e13c6d14SVinod Koul compatible = "qcom,kryo485"; 100e13c6d14SVinod Koul reg = <0x0 0x200>; 101fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 102e13c6d14SVinod Koul enable-method = "psci"; 1035b2dae72SDanny Lin capacity-dmips-mhz = <488>; 1045b2dae72SDanny Lin dynamic-power-coefficient = <232>; 105e13c6d14SVinod Koul next-level-cache = <&L2_200>; 106fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1072b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1082b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1092b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 110b2e3f897SDanny Lin power-domains = <&CPU_PD2>; 111b2e3f897SDanny Lin power-domain-names = "psci"; 112d2fa630cSAmit Kucheria #cooling-cells = <2>; 113e13c6d14SVinod Koul L2_200: l2-cache { 114e13c6d14SVinod Koul compatible = "cache"; 1159435294cSPierre Gondois cache-level = <2>; 116e13c6d14SVinod Koul next-level-cache = <&L3_0>; 117e13c6d14SVinod Koul }; 118e13c6d14SVinod Koul }; 119e13c6d14SVinod Koul 120e13c6d14SVinod Koul CPU3: cpu@300 { 121e13c6d14SVinod Koul device_type = "cpu"; 122e13c6d14SVinod Koul compatible = "qcom,kryo485"; 123e13c6d14SVinod Koul reg = <0x0 0x300>; 124fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 125e13c6d14SVinod Koul enable-method = "psci"; 1265b2dae72SDanny Lin capacity-dmips-mhz = <488>; 1275b2dae72SDanny Lin dynamic-power-coefficient = <232>; 128e13c6d14SVinod Koul next-level-cache = <&L2_300>; 129fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1302b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1312b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1322b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 133b2e3f897SDanny Lin power-domains = <&CPU_PD3>; 134b2e3f897SDanny Lin power-domain-names = "psci"; 135d2fa630cSAmit Kucheria #cooling-cells = <2>; 136e13c6d14SVinod Koul L2_300: l2-cache { 137e13c6d14SVinod Koul compatible = "cache"; 1389435294cSPierre Gondois cache-level = <2>; 139e13c6d14SVinod Koul next-level-cache = <&L3_0>; 140e13c6d14SVinod Koul }; 141e13c6d14SVinod Koul }; 142e13c6d14SVinod Koul 143e13c6d14SVinod Koul CPU4: cpu@400 { 144e13c6d14SVinod Koul device_type = "cpu"; 145e13c6d14SVinod Koul compatible = "qcom,kryo485"; 146e13c6d14SVinod Koul reg = <0x0 0x400>; 147fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 1>; 148e13c6d14SVinod Koul enable-method = "psci"; 1495b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1505b2dae72SDanny Lin dynamic-power-coefficient = <369>; 151e13c6d14SVinod Koul next-level-cache = <&L2_400>; 152fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1532b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1542b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1552b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 156b2e3f897SDanny Lin power-domains = <&CPU_PD4>; 157b2e3f897SDanny Lin power-domain-names = "psci"; 158d2fa630cSAmit Kucheria #cooling-cells = <2>; 159e13c6d14SVinod Koul L2_400: l2-cache { 160e13c6d14SVinod Koul compatible = "cache"; 1619435294cSPierre Gondois cache-level = <2>; 162e13c6d14SVinod Koul next-level-cache = <&L3_0>; 163e13c6d14SVinod Koul }; 164e13c6d14SVinod Koul }; 165e13c6d14SVinod Koul 166e13c6d14SVinod Koul CPU5: cpu@500 { 167e13c6d14SVinod Koul device_type = "cpu"; 168e13c6d14SVinod Koul compatible = "qcom,kryo485"; 169e13c6d14SVinod Koul reg = <0x0 0x500>; 170fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 1>; 171e13c6d14SVinod Koul enable-method = "psci"; 1725b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1735b2dae72SDanny Lin dynamic-power-coefficient = <369>; 174e13c6d14SVinod Koul next-level-cache = <&L2_500>; 175fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1762b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1772b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1782b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 179b2e3f897SDanny Lin power-domains = <&CPU_PD5>; 180b2e3f897SDanny Lin power-domain-names = "psci"; 181d2fa630cSAmit Kucheria #cooling-cells = <2>; 182e13c6d14SVinod Koul L2_500: l2-cache { 183e13c6d14SVinod Koul compatible = "cache"; 1849435294cSPierre Gondois cache-level = <2>; 185e13c6d14SVinod Koul next-level-cache = <&L3_0>; 186e13c6d14SVinod Koul }; 187e13c6d14SVinod Koul }; 188e13c6d14SVinod Koul 189e13c6d14SVinod Koul CPU6: cpu@600 { 190e13c6d14SVinod Koul device_type = "cpu"; 191e13c6d14SVinod Koul compatible = "qcom,kryo485"; 192e13c6d14SVinod Koul reg = <0x0 0x600>; 193fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 1>; 194e13c6d14SVinod Koul enable-method = "psci"; 1955b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1965b2dae72SDanny Lin dynamic-power-coefficient = <369>; 197e13c6d14SVinod Koul next-level-cache = <&L2_600>; 198fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1992b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 2002b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 2012b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 202b2e3f897SDanny Lin power-domains = <&CPU_PD6>; 203b2e3f897SDanny Lin power-domain-names = "psci"; 204d2fa630cSAmit Kucheria #cooling-cells = <2>; 205e13c6d14SVinod Koul L2_600: l2-cache { 206e13c6d14SVinod Koul compatible = "cache"; 2079435294cSPierre Gondois cache-level = <2>; 208e13c6d14SVinod Koul next-level-cache = <&L3_0>; 209e13c6d14SVinod Koul }; 210e13c6d14SVinod Koul }; 211e13c6d14SVinod Koul 212e13c6d14SVinod Koul CPU7: cpu@700 { 213e13c6d14SVinod Koul device_type = "cpu"; 214e13c6d14SVinod Koul compatible = "qcom,kryo485"; 215e13c6d14SVinod Koul reg = <0x0 0x700>; 216fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 2>; 217e13c6d14SVinod Koul enable-method = "psci"; 2185b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 2195b2dae72SDanny Lin dynamic-power-coefficient = <421>; 220e13c6d14SVinod Koul next-level-cache = <&L2_700>; 221fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 2>; 2222b6187abSThara Gopinath operating-points-v2 = <&cpu7_opp_table>; 2232b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 2242b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 225b2e3f897SDanny Lin power-domains = <&CPU_PD7>; 226b2e3f897SDanny Lin power-domain-names = "psci"; 227d2fa630cSAmit Kucheria #cooling-cells = <2>; 228e13c6d14SVinod Koul L2_700: l2-cache { 229e13c6d14SVinod Koul compatible = "cache"; 2309435294cSPierre Gondois cache-level = <2>; 231e13c6d14SVinod Koul next-level-cache = <&L3_0>; 232e13c6d14SVinod Koul }; 233e13c6d14SVinod Koul }; 234066d21bcSDanny Lin 235066d21bcSDanny Lin cpu-map { 236066d21bcSDanny Lin cluster0 { 237066d21bcSDanny Lin core0 { 238066d21bcSDanny Lin cpu = <&CPU0>; 239066d21bcSDanny Lin }; 240066d21bcSDanny Lin 241066d21bcSDanny Lin core1 { 242066d21bcSDanny Lin cpu = <&CPU1>; 243066d21bcSDanny Lin }; 244066d21bcSDanny Lin 245066d21bcSDanny Lin core2 { 246066d21bcSDanny Lin cpu = <&CPU2>; 247066d21bcSDanny Lin }; 248066d21bcSDanny Lin 249066d21bcSDanny Lin core3 { 250066d21bcSDanny Lin cpu = <&CPU3>; 251066d21bcSDanny Lin }; 252066d21bcSDanny Lin 253066d21bcSDanny Lin core4 { 254066d21bcSDanny Lin cpu = <&CPU4>; 255066d21bcSDanny Lin }; 256066d21bcSDanny Lin 257066d21bcSDanny Lin core5 { 258066d21bcSDanny Lin cpu = <&CPU5>; 259066d21bcSDanny Lin }; 260066d21bcSDanny Lin 261066d21bcSDanny Lin core6 { 262066d21bcSDanny Lin cpu = <&CPU6>; 263066d21bcSDanny Lin }; 264066d21bcSDanny Lin 265066d21bcSDanny Lin core7 { 266066d21bcSDanny Lin cpu = <&CPU7>; 267066d21bcSDanny Lin }; 268066d21bcSDanny Lin }; 269066d21bcSDanny Lin }; 27081188f58SDanny Lin 27181188f58SDanny Lin idle-states { 27281188f58SDanny Lin entry-method = "psci"; 27381188f58SDanny Lin 27481188f58SDanny Lin LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 27581188f58SDanny Lin compatible = "arm,idle-state"; 27681188f58SDanny Lin idle-state-name = "little-rail-power-collapse"; 27781188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 27881188f58SDanny Lin entry-latency-us = <355>; 27981188f58SDanny Lin exit-latency-us = <909>; 28081188f58SDanny Lin min-residency-us = <3934>; 28181188f58SDanny Lin local-timer-stop; 28281188f58SDanny Lin }; 28381188f58SDanny Lin 28481188f58SDanny Lin BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 28581188f58SDanny Lin compatible = "arm,idle-state"; 28681188f58SDanny Lin idle-state-name = "big-rail-power-collapse"; 28781188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 28881188f58SDanny Lin entry-latency-us = <241>; 28981188f58SDanny Lin exit-latency-us = <1461>; 29081188f58SDanny Lin min-residency-us = <4488>; 29181188f58SDanny Lin local-timer-stop; 29281188f58SDanny Lin }; 293b2e3f897SDanny Lin }; 29481188f58SDanny Lin 295b2e3f897SDanny Lin domain-idle-states { 29681188f58SDanny Lin CLUSTER_SLEEP_0: cluster-sleep-0 { 297b2e3f897SDanny Lin compatible = "domain-idle-state"; 298b2e3f897SDanny Lin arm,psci-suspend-param = <0x4100c244>; 29981188f58SDanny Lin entry-latency-us = <3263>; 30081188f58SDanny Lin exit-latency-us = <6562>; 30181188f58SDanny Lin min-residency-us = <9987>; 30281188f58SDanny Lin }; 30381188f58SDanny Lin }; 304e13c6d14SVinod Koul }; 305e13c6d14SVinod Koul 3060e3e6546SKrzysztof Kozlowski cpu0_opp_table: opp-table-cpu0 { 3072b6187abSThara Gopinath compatible = "operating-points-v2"; 3082b6187abSThara Gopinath opp-shared; 3092b6187abSThara Gopinath 3102b6187abSThara Gopinath cpu0_opp1: opp-300000000 { 3112b6187abSThara Gopinath opp-hz = /bits/ 64 <300000000>; 3122b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 3132b6187abSThara Gopinath }; 3142b6187abSThara Gopinath 3152b6187abSThara Gopinath cpu0_opp2: opp-403200000 { 3162b6187abSThara Gopinath opp-hz = /bits/ 64 <403200000>; 3172b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 3182b6187abSThara Gopinath }; 3192b6187abSThara Gopinath 3202b6187abSThara Gopinath cpu0_opp3: opp-499200000 { 3212b6187abSThara Gopinath opp-hz = /bits/ 64 <499200000>; 3222b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3232b6187abSThara Gopinath }; 3242b6187abSThara Gopinath 3252b6187abSThara Gopinath cpu0_opp4: opp-576000000 { 3262b6187abSThara Gopinath opp-hz = /bits/ 64 <576000000>; 3272b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3282b6187abSThara Gopinath }; 3292b6187abSThara Gopinath 3302b6187abSThara Gopinath cpu0_opp5: opp-672000000 { 3312b6187abSThara Gopinath opp-hz = /bits/ 64 <672000000>; 3322b6187abSThara Gopinath opp-peak-kBps = <800000 15974400>; 3332b6187abSThara Gopinath }; 3342b6187abSThara Gopinath 3352b6187abSThara Gopinath cpu0_opp6: opp-768000000 { 336ce3b50cfSThara Gopinath opp-hz = /bits/ 64 <768000000>; 3372b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3382b6187abSThara Gopinath }; 3392b6187abSThara Gopinath 3402b6187abSThara Gopinath cpu0_opp7: opp-844800000 { 3412b6187abSThara Gopinath opp-hz = /bits/ 64 <844800000>; 3422b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3432b6187abSThara Gopinath }; 3442b6187abSThara Gopinath 3452b6187abSThara Gopinath cpu0_opp8: opp-940800000 { 3462b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 3472b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3482b6187abSThara Gopinath }; 3492b6187abSThara Gopinath 3502b6187abSThara Gopinath cpu0_opp9: opp-1036800000 { 3512b6187abSThara Gopinath opp-hz = /bits/ 64 <1036800000>; 3522b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3532b6187abSThara Gopinath }; 3542b6187abSThara Gopinath 3552b6187abSThara Gopinath cpu0_opp10: opp-1113600000 { 3562b6187abSThara Gopinath opp-hz = /bits/ 64 <1113600000>; 3572b6187abSThara Gopinath opp-peak-kBps = <2188000 25804800>; 3582b6187abSThara Gopinath }; 3592b6187abSThara Gopinath 3602b6187abSThara Gopinath cpu0_opp11: opp-1209600000 { 3612b6187abSThara Gopinath opp-hz = /bits/ 64 <1209600000>; 3622b6187abSThara Gopinath opp-peak-kBps = <2188000 31948800>; 3632b6187abSThara Gopinath }; 3642b6187abSThara Gopinath 3652b6187abSThara Gopinath cpu0_opp12: opp-1305600000 { 3662b6187abSThara Gopinath opp-hz = /bits/ 64 <1305600000>; 3672b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3682b6187abSThara Gopinath }; 3692b6187abSThara Gopinath 3702b6187abSThara Gopinath cpu0_opp13: opp-1382400000 { 3712b6187abSThara Gopinath opp-hz = /bits/ 64 <1382400000>; 3722b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3732b6187abSThara Gopinath }; 3742b6187abSThara Gopinath 3752b6187abSThara Gopinath cpu0_opp14: opp-1478400000 { 3762b6187abSThara Gopinath opp-hz = /bits/ 64 <1478400000>; 3772b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3782b6187abSThara Gopinath }; 3792b6187abSThara Gopinath 3802b6187abSThara Gopinath cpu0_opp15: opp-1555200000 { 3812b6187abSThara Gopinath opp-hz = /bits/ 64 <1555200000>; 3822b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3832b6187abSThara Gopinath }; 3842b6187abSThara Gopinath 3852b6187abSThara Gopinath cpu0_opp16: opp-1632000000 { 3862b6187abSThara Gopinath opp-hz = /bits/ 64 <1632000000>; 3872b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3882b6187abSThara Gopinath }; 3892b6187abSThara Gopinath 3902b6187abSThara Gopinath cpu0_opp17: opp-1708800000 { 3912b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 3922b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 3932b6187abSThara Gopinath }; 3942b6187abSThara Gopinath 3952b6187abSThara Gopinath cpu0_opp18: opp-1785600000 { 3962b6187abSThara Gopinath opp-hz = /bits/ 64 <1785600000>; 3972b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 3982b6187abSThara Gopinath }; 3992b6187abSThara Gopinath }; 4002b6187abSThara Gopinath 4010e3e6546SKrzysztof Kozlowski cpu4_opp_table: opp-table-cpu4 { 4022b6187abSThara Gopinath compatible = "operating-points-v2"; 4032b6187abSThara Gopinath opp-shared; 4042b6187abSThara Gopinath 4052b6187abSThara Gopinath cpu4_opp1: opp-710400000 { 4062b6187abSThara Gopinath opp-hz = /bits/ 64 <710400000>; 4072b6187abSThara Gopinath opp-peak-kBps = <1804000 15974400>; 4082b6187abSThara Gopinath }; 4092b6187abSThara Gopinath 4102b6187abSThara Gopinath cpu4_opp2: opp-825600000 { 4112b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 4122b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 4132b6187abSThara Gopinath }; 4142b6187abSThara Gopinath 4152b6187abSThara Gopinath cpu4_opp3: opp-940800000 { 4162b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 4172b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 4182b6187abSThara Gopinath }; 4192b6187abSThara Gopinath 4202b6187abSThara Gopinath cpu4_opp4: opp-1056000000 { 4212b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 4222b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 4232b6187abSThara Gopinath }; 4242b6187abSThara Gopinath 4252b6187abSThara Gopinath cpu4_opp5: opp-1171200000 { 4262b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 4272b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 4282b6187abSThara Gopinath }; 4292b6187abSThara Gopinath 4302b6187abSThara Gopinath cpu4_opp6: opp-1286400000 { 4312b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 4322b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4332b6187abSThara Gopinath }; 4342b6187abSThara Gopinath 4352b6187abSThara Gopinath cpu4_opp7: opp-1401600000 { 4362b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 4372b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4382b6187abSThara Gopinath }; 4392b6187abSThara Gopinath 4402b6187abSThara Gopinath cpu4_opp8: opp-1497600000 { 4412b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 4422b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4432b6187abSThara Gopinath }; 4442b6187abSThara Gopinath 4452b6187abSThara Gopinath cpu4_opp9: opp-1612800000 { 4462b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 4472b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4482b6187abSThara Gopinath }; 4492b6187abSThara Gopinath 4502b6187abSThara Gopinath cpu4_opp10: opp-1708800000 { 4512b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 4522b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 4532b6187abSThara Gopinath }; 4542b6187abSThara Gopinath 4552b6187abSThara Gopinath cpu4_opp11: opp-1804800000 { 4562b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 4572b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 4582b6187abSThara Gopinath }; 4592b6187abSThara Gopinath 4602b6187abSThara Gopinath cpu4_opp12: opp-1920000000 { 4612b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 4622b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 4632b6187abSThara Gopinath }; 4642b6187abSThara Gopinath 4652b6187abSThara Gopinath cpu4_opp13: opp-2016000000 { 4662b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 4672b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 4682b6187abSThara Gopinath }; 4692b6187abSThara Gopinath 4702b6187abSThara Gopinath cpu4_opp14: opp-2131200000 { 4712b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 4722b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 4732b6187abSThara Gopinath }; 4742b6187abSThara Gopinath 4752b6187abSThara Gopinath cpu4_opp15: opp-2227200000 { 4762b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 4772b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4782b6187abSThara Gopinath }; 4792b6187abSThara Gopinath 4802b6187abSThara Gopinath cpu4_opp16: opp-2323200000 { 4812b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 4822b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4832b6187abSThara Gopinath }; 4842b6187abSThara Gopinath 4852b6187abSThara Gopinath cpu4_opp17: opp-2419200000 { 4862b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 4872b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4882b6187abSThara Gopinath }; 4892b6187abSThara Gopinath }; 4902b6187abSThara Gopinath 4910e3e6546SKrzysztof Kozlowski cpu7_opp_table: opp-table-cpu7 { 4922b6187abSThara Gopinath compatible = "operating-points-v2"; 4932b6187abSThara Gopinath opp-shared; 4942b6187abSThara Gopinath 4952b6187abSThara Gopinath cpu7_opp1: opp-825600000 { 4962b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 4972b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 4982b6187abSThara Gopinath }; 4992b6187abSThara Gopinath 5002b6187abSThara Gopinath cpu7_opp2: opp-940800000 { 5012b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 5022b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 5032b6187abSThara Gopinath }; 5042b6187abSThara Gopinath 5052b6187abSThara Gopinath cpu7_opp3: opp-1056000000 { 5062b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 5072b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 5082b6187abSThara Gopinath }; 5092b6187abSThara Gopinath 5102b6187abSThara Gopinath cpu7_opp4: opp-1171200000 { 5112b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 5122b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 5132b6187abSThara Gopinath }; 5142b6187abSThara Gopinath 5152b6187abSThara Gopinath cpu7_opp5: opp-1286400000 { 5162b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 5172b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5182b6187abSThara Gopinath }; 5192b6187abSThara Gopinath 5202b6187abSThara Gopinath cpu7_opp6: opp-1401600000 { 5212b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 5222b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5232b6187abSThara Gopinath }; 5242b6187abSThara Gopinath 5252b6187abSThara Gopinath cpu7_opp7: opp-1497600000 { 5262b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 5272b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5282b6187abSThara Gopinath }; 5292b6187abSThara Gopinath 5302b6187abSThara Gopinath cpu7_opp8: opp-1612800000 { 5312b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 5322b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5332b6187abSThara Gopinath }; 5342b6187abSThara Gopinath 5352b6187abSThara Gopinath cpu7_opp9: opp-1708800000 { 5362b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 5372b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 5382b6187abSThara Gopinath }; 5392b6187abSThara Gopinath 5402b6187abSThara Gopinath cpu7_opp10: opp-1804800000 { 5412b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 5422b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 5432b6187abSThara Gopinath }; 5442b6187abSThara Gopinath 5452b6187abSThara Gopinath cpu7_opp11: opp-1920000000 { 5462b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 5472b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 5482b6187abSThara Gopinath }; 5492b6187abSThara Gopinath 5502b6187abSThara Gopinath cpu7_opp12: opp-2016000000 { 5512b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 5522b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 5532b6187abSThara Gopinath }; 5542b6187abSThara Gopinath 5552b6187abSThara Gopinath cpu7_opp13: opp-2131200000 { 5562b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 5572b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 5582b6187abSThara Gopinath }; 5592b6187abSThara Gopinath 5602b6187abSThara Gopinath cpu7_opp14: opp-2227200000 { 5612b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 5622b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5632b6187abSThara Gopinath }; 5642b6187abSThara Gopinath 5652b6187abSThara Gopinath cpu7_opp15: opp-2323200000 { 5662b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 5672b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5682b6187abSThara Gopinath }; 5692b6187abSThara Gopinath 5702b6187abSThara Gopinath cpu7_opp16: opp-2419200000 { 5712b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 5722b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5732b6187abSThara Gopinath }; 5742b6187abSThara Gopinath 5752b6187abSThara Gopinath cpu7_opp17: opp-2534400000 { 5762b6187abSThara Gopinath opp-hz = /bits/ 64 <2534400000>; 5772b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5782b6187abSThara Gopinath }; 5792b6187abSThara Gopinath 5802b6187abSThara Gopinath cpu7_opp18: opp-2649600000 { 5812b6187abSThara Gopinath opp-hz = /bits/ 64 <2649600000>; 5822b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5832b6187abSThara Gopinath }; 5842b6187abSThara Gopinath 5852b6187abSThara Gopinath cpu7_opp19: opp-2745600000 { 5862b6187abSThara Gopinath opp-hz = /bits/ 64 <2745600000>; 5872b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5882b6187abSThara Gopinath }; 5892b6187abSThara Gopinath 5902b6187abSThara Gopinath cpu7_opp20: opp-2841600000 { 5912b6187abSThara Gopinath opp-hz = /bits/ 64 <2841600000>; 5922b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5932b6187abSThara Gopinath }; 5942b6187abSThara Gopinath }; 5952b6187abSThara Gopinath 596e13c6d14SVinod Koul firmware { 597e13c6d14SVinod Koul scm: scm { 598e13c6d14SVinod Koul compatible = "qcom,scm-sm8150", "qcom,scm"; 599e13c6d14SVinod Koul #reset-cells = <1>; 600e13c6d14SVinod Koul }; 601e13c6d14SVinod Koul }; 602e13c6d14SVinod Koul 603e13c6d14SVinod Koul memory@80000000 { 604e13c6d14SVinod Koul device_type = "memory"; 605e13c6d14SVinod Koul /* We expect the bootloader to fill in the size */ 606e13c6d14SVinod Koul reg = <0x0 0x80000000 0x0 0x0>; 607e13c6d14SVinod Koul }; 608e13c6d14SVinod Koul 609d8cf9372SVinod Koul pmu { 610d8cf9372SVinod Koul compatible = "arm,armv8-pmuv3"; 611d8cf9372SVinod Koul interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 612d8cf9372SVinod Koul }; 613d8cf9372SVinod Koul 614e13c6d14SVinod Koul psci { 615e13c6d14SVinod Koul compatible = "arm,psci-1.0"; 616e13c6d14SVinod Koul method = "smc"; 617b2e3f897SDanny Lin 6185ca45690SKrzysztof Kozlowski CPU_PD0: power-domain-cpu0 { 619b2e3f897SDanny Lin #power-domain-cells = <0>; 620b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 621b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 622b2e3f897SDanny Lin }; 623b2e3f897SDanny Lin 6245ca45690SKrzysztof Kozlowski CPU_PD1: power-domain-cpu1 { 625b2e3f897SDanny Lin #power-domain-cells = <0>; 626b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 627b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 628b2e3f897SDanny Lin }; 629b2e3f897SDanny Lin 6305ca45690SKrzysztof Kozlowski CPU_PD2: power-domain-cpu2 { 631b2e3f897SDanny Lin #power-domain-cells = <0>; 632b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 633b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 634b2e3f897SDanny Lin }; 635b2e3f897SDanny Lin 6365ca45690SKrzysztof Kozlowski CPU_PD3: power-domain-cpu3 { 637b2e3f897SDanny Lin #power-domain-cells = <0>; 638b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 639b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 640b2e3f897SDanny Lin }; 641b2e3f897SDanny Lin 6425ca45690SKrzysztof Kozlowski CPU_PD4: power-domain-cpu4 { 643b2e3f897SDanny Lin #power-domain-cells = <0>; 644b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 645b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 646b2e3f897SDanny Lin }; 647b2e3f897SDanny Lin 6485ca45690SKrzysztof Kozlowski CPU_PD5: power-domain-cpu5 { 649b2e3f897SDanny Lin #power-domain-cells = <0>; 650b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 651b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 652b2e3f897SDanny Lin }; 653b2e3f897SDanny Lin 6545ca45690SKrzysztof Kozlowski CPU_PD6: power-domain-cpu6 { 655b2e3f897SDanny Lin #power-domain-cells = <0>; 656b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 657b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 658b2e3f897SDanny Lin }; 659b2e3f897SDanny Lin 6605ca45690SKrzysztof Kozlowski CPU_PD7: power-domain-cpu7 { 661b2e3f897SDanny Lin #power-domain-cells = <0>; 662b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 663b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 664b2e3f897SDanny Lin }; 665b2e3f897SDanny Lin 6665ca45690SKrzysztof Kozlowski CLUSTER_PD: power-domain-cpu-cluster0 { 667b2e3f897SDanny Lin #power-domain-cells = <0>; 668b2e3f897SDanny Lin domain-idle-states = <&CLUSTER_SLEEP_0>; 669b2e3f897SDanny Lin }; 670e13c6d14SVinod Koul }; 671e13c6d14SVinod Koul 672912c373aSVinod Koul reserved-memory { 673912c373aSVinod Koul #address-cells = <2>; 674912c373aSVinod Koul #size-cells = <2>; 675912c373aSVinod Koul ranges; 676912c373aSVinod Koul 677912c373aSVinod Koul hyp_mem: memory@85700000 { 678912c373aSVinod Koul reg = <0x0 0x85700000 0x0 0x600000>; 679912c373aSVinod Koul no-map; 680912c373aSVinod Koul }; 681912c373aSVinod Koul 682912c373aSVinod Koul xbl_mem: memory@85d00000 { 683912c373aSVinod Koul reg = <0x0 0x85d00000 0x0 0x140000>; 684912c373aSVinod Koul no-map; 685912c373aSVinod Koul }; 686912c373aSVinod Koul 687912c373aSVinod Koul aop_mem: memory@85f00000 { 688912c373aSVinod Koul reg = <0x0 0x85f00000 0x0 0x20000>; 689912c373aSVinod Koul no-map; 690912c373aSVinod Koul }; 691912c373aSVinod Koul 692912c373aSVinod Koul aop_cmd_db: memory@85f20000 { 693912c373aSVinod Koul compatible = "qcom,cmd-db"; 694912c373aSVinod Koul reg = <0x0 0x85f20000 0x0 0x20000>; 695912c373aSVinod Koul no-map; 696912c373aSVinod Koul }; 697912c373aSVinod Koul 698912c373aSVinod Koul smem_mem: memory@86000000 { 699912c373aSVinod Koul reg = <0x0 0x86000000 0x0 0x200000>; 700912c373aSVinod Koul no-map; 701912c373aSVinod Koul }; 702912c373aSVinod Koul 703912c373aSVinod Koul tz_mem: memory@86200000 { 704912c373aSVinod Koul reg = <0x0 0x86200000 0x0 0x3900000>; 705912c373aSVinod Koul no-map; 706912c373aSVinod Koul }; 707912c373aSVinod Koul 708912c373aSVinod Koul rmtfs_mem: memory@89b00000 { 709912c373aSVinod Koul compatible = "qcom,rmtfs-mem"; 710912c373aSVinod Koul reg = <0x0 0x89b00000 0x0 0x200000>; 711912c373aSVinod Koul no-map; 712912c373aSVinod Koul 713912c373aSVinod Koul qcom,client-id = <1>; 714912c373aSVinod Koul qcom,vmid = <15>; 715912c373aSVinod Koul }; 716912c373aSVinod Koul 717912c373aSVinod Koul camera_mem: memory@8b700000 { 718912c373aSVinod Koul reg = <0x0 0x8b700000 0x0 0x500000>; 719912c373aSVinod Koul no-map; 720912c373aSVinod Koul }; 721912c373aSVinod Koul 722912c373aSVinod Koul wlan_mem: memory@8bc00000 { 723912c373aSVinod Koul reg = <0x0 0x8bc00000 0x0 0x180000>; 724912c373aSVinod Koul no-map; 725912c373aSVinod Koul }; 726912c373aSVinod Koul 727912c373aSVinod Koul npu_mem: memory@8bd80000 { 728912c373aSVinod Koul reg = <0x0 0x8bd80000 0x0 0x80000>; 729912c373aSVinod Koul no-map; 730912c373aSVinod Koul }; 731912c373aSVinod Koul 732912c373aSVinod Koul adsp_mem: memory@8be00000 { 733912c373aSVinod Koul reg = <0x0 0x8be00000 0x0 0x1a00000>; 734912c373aSVinod Koul no-map; 735912c373aSVinod Koul }; 736912c373aSVinod Koul 737912c373aSVinod Koul mpss_mem: memory@8d800000 { 738912c373aSVinod Koul reg = <0x0 0x8d800000 0x0 0x9600000>; 739912c373aSVinod Koul no-map; 740912c373aSVinod Koul }; 741912c373aSVinod Koul 742912c373aSVinod Koul venus_mem: memory@96e00000 { 743912c373aSVinod Koul reg = <0x0 0x96e00000 0x0 0x500000>; 744912c373aSVinod Koul no-map; 745912c373aSVinod Koul }; 746912c373aSVinod Koul 747912c373aSVinod Koul slpi_mem: memory@97300000 { 748912c373aSVinod Koul reg = <0x0 0x97300000 0x0 0x1400000>; 749912c373aSVinod Koul no-map; 750912c373aSVinod Koul }; 751912c373aSVinod Koul 752912c373aSVinod Koul ipa_fw_mem: memory@98700000 { 753912c373aSVinod Koul reg = <0x0 0x98700000 0x0 0x10000>; 754912c373aSVinod Koul no-map; 755912c373aSVinod Koul }; 756912c373aSVinod Koul 757912c373aSVinod Koul ipa_gsi_mem: memory@98710000 { 758912c373aSVinod Koul reg = <0x0 0x98710000 0x0 0x5000>; 759912c373aSVinod Koul no-map; 760912c373aSVinod Koul }; 761912c373aSVinod Koul 762912c373aSVinod Koul gpu_mem: memory@98715000 { 763912c373aSVinod Koul reg = <0x0 0x98715000 0x0 0x2000>; 764912c373aSVinod Koul no-map; 765912c373aSVinod Koul }; 766912c373aSVinod Koul 767912c373aSVinod Koul spss_mem: memory@98800000 { 768912c373aSVinod Koul reg = <0x0 0x98800000 0x0 0x100000>; 769912c373aSVinod Koul no-map; 770912c373aSVinod Koul }; 771912c373aSVinod Koul 772912c373aSVinod Koul cdsp_mem: memory@98900000 { 773912c373aSVinod Koul reg = <0x0 0x98900000 0x0 0x1400000>; 774912c373aSVinod Koul no-map; 775912c373aSVinod Koul }; 776912c373aSVinod Koul 777912c373aSVinod Koul qseecom_mem: memory@9e400000 { 778912c373aSVinod Koul reg = <0x0 0x9e400000 0x0 0x1400000>; 779912c373aSVinod Koul no-map; 780912c373aSVinod Koul }; 781912c373aSVinod Koul }; 782912c373aSVinod Koul 783d8cf9372SVinod Koul smem { 784d8cf9372SVinod Koul compatible = "qcom,smem"; 785d8cf9372SVinod Koul memory-region = <&smem_mem>; 786d8cf9372SVinod Koul hwlocks = <&tcsr_mutex 3>; 787d8cf9372SVinod Koul }; 788d8cf9372SVinod Koul 78961025b81SSibi Sankar smp2p-cdsp { 79061025b81SSibi Sankar compatible = "qcom,smp2p"; 79161025b81SSibi Sankar qcom,smem = <94>, <432>; 79261025b81SSibi Sankar 79361025b81SSibi Sankar interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 79461025b81SSibi Sankar 79561025b81SSibi Sankar mboxes = <&apss_shared 6>; 79661025b81SSibi Sankar 79761025b81SSibi Sankar qcom,local-pid = <0>; 79861025b81SSibi Sankar qcom,remote-pid = <5>; 79961025b81SSibi Sankar 80061025b81SSibi Sankar cdsp_smp2p_out: master-kernel { 80161025b81SSibi Sankar qcom,entry-name = "master-kernel"; 80261025b81SSibi Sankar #qcom,smem-state-cells = <1>; 80361025b81SSibi Sankar }; 80461025b81SSibi Sankar 80561025b81SSibi Sankar cdsp_smp2p_in: slave-kernel { 80661025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 80761025b81SSibi Sankar 80861025b81SSibi Sankar interrupt-controller; 80961025b81SSibi Sankar #interrupt-cells = <2>; 81061025b81SSibi Sankar }; 81161025b81SSibi Sankar }; 81261025b81SSibi Sankar 81361025b81SSibi Sankar smp2p-lpass { 81461025b81SSibi Sankar compatible = "qcom,smp2p"; 81561025b81SSibi Sankar qcom,smem = <443>, <429>; 81661025b81SSibi Sankar 81761025b81SSibi Sankar interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 81861025b81SSibi Sankar 81961025b81SSibi Sankar mboxes = <&apss_shared 10>; 82061025b81SSibi Sankar 82161025b81SSibi Sankar qcom,local-pid = <0>; 82261025b81SSibi Sankar qcom,remote-pid = <2>; 82361025b81SSibi Sankar 82461025b81SSibi Sankar adsp_smp2p_out: master-kernel { 82561025b81SSibi Sankar qcom,entry-name = "master-kernel"; 82661025b81SSibi Sankar #qcom,smem-state-cells = <1>; 82761025b81SSibi Sankar }; 82861025b81SSibi Sankar 82961025b81SSibi Sankar adsp_smp2p_in: slave-kernel { 83061025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 83161025b81SSibi Sankar 83261025b81SSibi Sankar interrupt-controller; 83361025b81SSibi Sankar #interrupt-cells = <2>; 83461025b81SSibi Sankar }; 83561025b81SSibi Sankar }; 83661025b81SSibi Sankar 83761025b81SSibi Sankar smp2p-mpss { 83861025b81SSibi Sankar compatible = "qcom,smp2p"; 83961025b81SSibi Sankar qcom,smem = <435>, <428>; 84061025b81SSibi Sankar 84161025b81SSibi Sankar interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 84261025b81SSibi Sankar 84361025b81SSibi Sankar mboxes = <&apss_shared 14>; 84461025b81SSibi Sankar 84561025b81SSibi Sankar qcom,local-pid = <0>; 84661025b81SSibi Sankar qcom,remote-pid = <1>; 84761025b81SSibi Sankar 84861025b81SSibi Sankar modem_smp2p_out: master-kernel { 84961025b81SSibi Sankar qcom,entry-name = "master-kernel"; 85061025b81SSibi Sankar #qcom,smem-state-cells = <1>; 85161025b81SSibi Sankar }; 85261025b81SSibi Sankar 85361025b81SSibi Sankar modem_smp2p_in: slave-kernel { 85461025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 85561025b81SSibi Sankar 85661025b81SSibi Sankar interrupt-controller; 85761025b81SSibi Sankar #interrupt-cells = <2>; 85861025b81SSibi Sankar }; 85961025b81SSibi Sankar }; 86061025b81SSibi Sankar 86161025b81SSibi Sankar smp2p-slpi { 86261025b81SSibi Sankar compatible = "qcom,smp2p"; 86361025b81SSibi Sankar qcom,smem = <481>, <430>; 86461025b81SSibi Sankar 86561025b81SSibi Sankar interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 86661025b81SSibi Sankar 86761025b81SSibi Sankar mboxes = <&apss_shared 26>; 86861025b81SSibi Sankar 86961025b81SSibi Sankar qcom,local-pid = <0>; 87061025b81SSibi Sankar qcom,remote-pid = <3>; 87161025b81SSibi Sankar 87261025b81SSibi Sankar slpi_smp2p_out: master-kernel { 87361025b81SSibi Sankar qcom,entry-name = "master-kernel"; 87461025b81SSibi Sankar #qcom,smem-state-cells = <1>; 87561025b81SSibi Sankar }; 87661025b81SSibi Sankar 87761025b81SSibi Sankar slpi_smp2p_in: slave-kernel { 87861025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 87961025b81SSibi Sankar 88061025b81SSibi Sankar interrupt-controller; 88161025b81SSibi Sankar #interrupt-cells = <2>; 88261025b81SSibi Sankar }; 88361025b81SSibi Sankar }; 88461025b81SSibi Sankar 885e13c6d14SVinod Koul soc: soc@0 { 886e13c6d14SVinod Koul #address-cells = <2>; 887e13c6d14SVinod Koul #size-cells = <2>; 888e13c6d14SVinod Koul ranges = <0 0 0 0 0x10 0>; 889e13c6d14SVinod Koul dma-ranges = <0 0 0 0 0x10 0>; 890e13c6d14SVinod Koul compatible = "simple-bus"; 891e13c6d14SVinod Koul 892e13c6d14SVinod Koul gcc: clock-controller@100000 { 893e13c6d14SVinod Koul compatible = "qcom,gcc-sm8150"; 894e13c6d14SVinod Koul reg = <0x0 0x00100000 0x0 0x1f0000>; 895e13c6d14SVinod Koul #clock-cells = <1>; 896e13c6d14SVinod Koul #reset-cells = <1>; 897e13c6d14SVinod Koul #power-domain-cells = <1>; 898e13c6d14SVinod Koul clock-names = "bi_tcxo", 899e13c6d14SVinod Koul "sleep_clk"; 900e13c6d14SVinod Koul clocks = <&rpmhcc RPMH_CXO_CLK>, 901e13c6d14SVinod Koul <&sleep_clk>; 902e13c6d14SVinod Koul }; 903e13c6d14SVinod Koul 90405006290SFelipe Balbi gpi_dma0: dma-controller@800000 { 905e7e24786SRichard Acayan compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 906f6973229SKonrad Dybcio reg = <0 0x00800000 0 0x60000>; 90705006290SFelipe Balbi interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 90805006290SFelipe Balbi <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 90905006290SFelipe Balbi <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 91005006290SFelipe Balbi <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 91105006290SFelipe Balbi <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 91205006290SFelipe Balbi <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 91305006290SFelipe Balbi <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 91405006290SFelipe Balbi <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 91505006290SFelipe Balbi <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 91605006290SFelipe Balbi <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 91705006290SFelipe Balbi <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 91805006290SFelipe Balbi <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 91905006290SFelipe Balbi <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 92005006290SFelipe Balbi dma-channels = <13>; 92105006290SFelipe Balbi dma-channel-mask = <0xfa>; 92205006290SFelipe Balbi iommus = <&apps_smmu 0x00d6 0x0>; 92305006290SFelipe Balbi #dma-cells = <3>; 92405006290SFelipe Balbi status = "disabled"; 92505006290SFelipe Balbi }; 92605006290SFelipe Balbi 92705f333b7SVinod Koul ethernet: ethernet@20000 { 92805f333b7SVinod Koul compatible = "qcom,sm8150-ethqos"; 92905f333b7SVinod Koul reg = <0x0 0x00020000 0x0 0x10000>, 93005f333b7SVinod Koul <0x0 0x00036000 0x0 0x100>; 93105f333b7SVinod Koul reg-names = "stmmaceth", "rgmii"; 93205f333b7SVinod Koul clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 93305f333b7SVinod Koul clocks = <&gcc GCC_EMAC_AXI_CLK>, 93405f333b7SVinod Koul <&gcc GCC_EMAC_SLV_AHB_CLK>, 93505f333b7SVinod Koul <&gcc GCC_EMAC_PTP_CLK>, 93605f333b7SVinod Koul <&gcc GCC_EMAC_RGMII_CLK>; 93705f333b7SVinod Koul interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 93805f333b7SVinod Koul <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 93905f333b7SVinod Koul interrupt-names = "macirq", "eth_lpi"; 94005f333b7SVinod Koul 94105f333b7SVinod Koul power-domains = <&gcc EMAC_GDSC>; 94205f333b7SVinod Koul resets = <&gcc GCC_EMAC_BCR>; 94305f333b7SVinod Koul 94451f748c6SKonrad Dybcio iommus = <&apps_smmu 0x3c0 0x0>; 94505f333b7SVinod Koul 94605f333b7SVinod Koul snps,tso; 94705f333b7SVinod Koul rx-fifo-depth = <4096>; 94805f333b7SVinod Koul tx-fifo-depth = <4096>; 94905f333b7SVinod Koul 95005f333b7SVinod Koul status = "disabled"; 95105f333b7SVinod Koul }; 95205f333b7SVinod Koul 95305f333b7SVinod Koul 9549cf3ebd1SCaleb Connolly qupv3_id_0: geniqup@8c0000 { 9559cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 9569cf3ebd1SCaleb Connolly reg = <0x0 0x008c0000 0x0 0x6000>; 9579cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 9589cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 9599cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 9609cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0xc3 0x0>; 9619cf3ebd1SCaleb Connolly #address-cells = <2>; 9629cf3ebd1SCaleb Connolly #size-cells = <2>; 9639cf3ebd1SCaleb Connolly ranges; 9649cf3ebd1SCaleb Connolly status = "disabled"; 96581bee695SCaleb Connolly 96681bee695SCaleb Connolly i2c0: i2c@880000 { 96781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 96881bee695SCaleb Connolly reg = <0 0x00880000 0 0x4000>; 96981bee695SCaleb Connolly clock-names = "se"; 97081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 971abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 972abdd4b7aSFelipe Balbi <&gpi_dma0 1 0 QCOM_GPI_I2C>; 973abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 97481bee695SCaleb Connolly pinctrl-names = "default"; 97581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c0_default>; 97681bee695SCaleb Connolly interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 97781bee695SCaleb Connolly #address-cells = <1>; 97881bee695SCaleb Connolly #size-cells = <0>; 97981bee695SCaleb Connolly status = "disabled"; 98081bee695SCaleb Connolly }; 98181bee695SCaleb Connolly 982129e1c96SFelipe Balbi spi0: spi@880000 { 983129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 984f6973229SKonrad Dybcio reg = <0 0x00880000 0 0x4000>; 985129e1c96SFelipe Balbi reg-names = "se"; 986129e1c96SFelipe Balbi clock-names = "se"; 987129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 988abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 989abdd4b7aSFelipe Balbi <&gpi_dma0 1 0 QCOM_GPI_SPI>; 990abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 991129e1c96SFelipe Balbi pinctrl-names = "default"; 992129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi0_default>; 993129e1c96SFelipe Balbi interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 994129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 995129e1c96SFelipe Balbi #address-cells = <1>; 996129e1c96SFelipe Balbi #size-cells = <0>; 997129e1c96SFelipe Balbi status = "disabled"; 998129e1c96SFelipe Balbi }; 999129e1c96SFelipe Balbi 100081bee695SCaleb Connolly i2c1: i2c@884000 { 100181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 100281bee695SCaleb Connolly reg = <0 0x00884000 0 0x4000>; 100381bee695SCaleb Connolly clock-names = "se"; 100481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1005abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1006abdd4b7aSFelipe Balbi <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1007abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 100881bee695SCaleb Connolly pinctrl-names = "default"; 100981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c1_default>; 101081bee695SCaleb Connolly interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 101181bee695SCaleb Connolly #address-cells = <1>; 101281bee695SCaleb Connolly #size-cells = <0>; 101381bee695SCaleb Connolly status = "disabled"; 101481bee695SCaleb Connolly }; 101581bee695SCaleb Connolly 1016129e1c96SFelipe Balbi spi1: spi@884000 { 1017129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1018f6973229SKonrad Dybcio reg = <0 0x00884000 0 0x4000>; 1019129e1c96SFelipe Balbi reg-names = "se"; 1020129e1c96SFelipe Balbi clock-names = "se"; 1021129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1022abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1023abdd4b7aSFelipe Balbi <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1024abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1025129e1c96SFelipe Balbi pinctrl-names = "default"; 1026129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi1_default>; 1027129e1c96SFelipe Balbi interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1028129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1029129e1c96SFelipe Balbi #address-cells = <1>; 1030129e1c96SFelipe Balbi #size-cells = <0>; 1031129e1c96SFelipe Balbi status = "disabled"; 1032129e1c96SFelipe Balbi }; 1033129e1c96SFelipe Balbi 103481bee695SCaleb Connolly i2c2: i2c@888000 { 103581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 103681bee695SCaleb Connolly reg = <0 0x00888000 0 0x4000>; 103781bee695SCaleb Connolly clock-names = "se"; 103881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1039abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1040abdd4b7aSFelipe Balbi <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1041abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 104281bee695SCaleb Connolly pinctrl-names = "default"; 104381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c2_default>; 104481bee695SCaleb Connolly interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 104581bee695SCaleb Connolly #address-cells = <1>; 104681bee695SCaleb Connolly #size-cells = <0>; 104781bee695SCaleb Connolly status = "disabled"; 104881bee695SCaleb Connolly }; 104981bee695SCaleb Connolly 1050129e1c96SFelipe Balbi spi2: spi@888000 { 1051129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1052f6973229SKonrad Dybcio reg = <0 0x00888000 0 0x4000>; 1053129e1c96SFelipe Balbi reg-names = "se"; 1054129e1c96SFelipe Balbi clock-names = "se"; 1055129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1056abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1057abdd4b7aSFelipe Balbi <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1058abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1059129e1c96SFelipe Balbi pinctrl-names = "default"; 1060129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi2_default>; 1061129e1c96SFelipe Balbi interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1062129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1063129e1c96SFelipe Balbi #address-cells = <1>; 1064129e1c96SFelipe Balbi #size-cells = <0>; 1065129e1c96SFelipe Balbi status = "disabled"; 1066129e1c96SFelipe Balbi }; 1067129e1c96SFelipe Balbi 106881bee695SCaleb Connolly i2c3: i2c@88c000 { 106981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 107081bee695SCaleb Connolly reg = <0 0x0088c000 0 0x4000>; 107181bee695SCaleb Connolly clock-names = "se"; 107281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1073abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1074abdd4b7aSFelipe Balbi <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1075abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 107681bee695SCaleb Connolly pinctrl-names = "default"; 107781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c3_default>; 107881bee695SCaleb Connolly interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 107981bee695SCaleb Connolly #address-cells = <1>; 108081bee695SCaleb Connolly #size-cells = <0>; 108181bee695SCaleb Connolly status = "disabled"; 108281bee695SCaleb Connolly }; 108381bee695SCaleb Connolly 1084129e1c96SFelipe Balbi spi3: spi@88c000 { 1085129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1086f6973229SKonrad Dybcio reg = <0 0x0088c000 0 0x4000>; 1087129e1c96SFelipe Balbi reg-names = "se"; 1088129e1c96SFelipe Balbi clock-names = "se"; 1089129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1090abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1091abdd4b7aSFelipe Balbi <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1092abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1093129e1c96SFelipe Balbi pinctrl-names = "default"; 1094129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi3_default>; 1095129e1c96SFelipe Balbi interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1096129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1097129e1c96SFelipe Balbi #address-cells = <1>; 1098129e1c96SFelipe Balbi #size-cells = <0>; 1099129e1c96SFelipe Balbi status = "disabled"; 1100129e1c96SFelipe Balbi }; 1101129e1c96SFelipe Balbi 110281bee695SCaleb Connolly i2c4: i2c@890000 { 110381bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 110481bee695SCaleb Connolly reg = <0 0x00890000 0 0x4000>; 110581bee695SCaleb Connolly clock-names = "se"; 110681bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1107abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1108abdd4b7aSFelipe Balbi <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1109abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 111081bee695SCaleb Connolly pinctrl-names = "default"; 111181bee695SCaleb Connolly pinctrl-0 = <&qup_i2c4_default>; 111281bee695SCaleb Connolly interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 111381bee695SCaleb Connolly #address-cells = <1>; 111481bee695SCaleb Connolly #size-cells = <0>; 111581bee695SCaleb Connolly status = "disabled"; 111681bee695SCaleb Connolly }; 111781bee695SCaleb Connolly 1118129e1c96SFelipe Balbi spi4: spi@890000 { 1119129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1120f6973229SKonrad Dybcio reg = <0 0x00890000 0 0x4000>; 1121129e1c96SFelipe Balbi reg-names = "se"; 1122129e1c96SFelipe Balbi clock-names = "se"; 1123129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1124abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1125abdd4b7aSFelipe Balbi <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1126abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1127129e1c96SFelipe Balbi pinctrl-names = "default"; 1128129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi4_default>; 1129129e1c96SFelipe Balbi interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1130129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1131129e1c96SFelipe Balbi #address-cells = <1>; 1132129e1c96SFelipe Balbi #size-cells = <0>; 1133129e1c96SFelipe Balbi status = "disabled"; 1134129e1c96SFelipe Balbi }; 1135129e1c96SFelipe Balbi 113681bee695SCaleb Connolly i2c5: i2c@894000 { 113781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 113881bee695SCaleb Connolly reg = <0 0x00894000 0 0x4000>; 113981bee695SCaleb Connolly clock-names = "se"; 114081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1141abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1142abdd4b7aSFelipe Balbi <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1143abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 114481bee695SCaleb Connolly pinctrl-names = "default"; 114581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c5_default>; 114681bee695SCaleb Connolly interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 114781bee695SCaleb Connolly #address-cells = <1>; 114881bee695SCaleb Connolly #size-cells = <0>; 114981bee695SCaleb Connolly status = "disabled"; 115081bee695SCaleb Connolly }; 115181bee695SCaleb Connolly 1152129e1c96SFelipe Balbi spi5: spi@894000 { 1153129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1154f6973229SKonrad Dybcio reg = <0 0x00894000 0 0x4000>; 1155129e1c96SFelipe Balbi reg-names = "se"; 1156129e1c96SFelipe Balbi clock-names = "se"; 1157129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1158abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1159abdd4b7aSFelipe Balbi <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1160abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1161129e1c96SFelipe Balbi pinctrl-names = "default"; 1162129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi5_default>; 1163129e1c96SFelipe Balbi interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1164129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1165129e1c96SFelipe Balbi #address-cells = <1>; 1166129e1c96SFelipe Balbi #size-cells = <0>; 1167129e1c96SFelipe Balbi status = "disabled"; 1168129e1c96SFelipe Balbi }; 1169129e1c96SFelipe Balbi 117081bee695SCaleb Connolly i2c6: i2c@898000 { 117181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 117281bee695SCaleb Connolly reg = <0 0x00898000 0 0x4000>; 117381bee695SCaleb Connolly clock-names = "se"; 117481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1175abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1176abdd4b7aSFelipe Balbi <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1177abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 117881bee695SCaleb Connolly pinctrl-names = "default"; 117981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c6_default>; 118081bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 118181bee695SCaleb Connolly #address-cells = <1>; 118281bee695SCaleb Connolly #size-cells = <0>; 118381bee695SCaleb Connolly status = "disabled"; 118481bee695SCaleb Connolly }; 118581bee695SCaleb Connolly 1186129e1c96SFelipe Balbi spi6: spi@898000 { 1187129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1188f6973229SKonrad Dybcio reg = <0 0x00898000 0 0x4000>; 1189129e1c96SFelipe Balbi reg-names = "se"; 1190129e1c96SFelipe Balbi clock-names = "se"; 1191129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1192abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1193abdd4b7aSFelipe Balbi <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1194abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1195129e1c96SFelipe Balbi pinctrl-names = "default"; 1196129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi6_default>; 1197129e1c96SFelipe Balbi interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1198129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1199129e1c96SFelipe Balbi #address-cells = <1>; 1200129e1c96SFelipe Balbi #size-cells = <0>; 1201129e1c96SFelipe Balbi status = "disabled"; 1202129e1c96SFelipe Balbi }; 1203129e1c96SFelipe Balbi 120481bee695SCaleb Connolly i2c7: i2c@89c000 { 120581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 120681bee695SCaleb Connolly reg = <0 0x0089c000 0 0x4000>; 120781bee695SCaleb Connolly clock-names = "se"; 120881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1209abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1210abdd4b7aSFelipe Balbi <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1211abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 121281bee695SCaleb Connolly pinctrl-names = "default"; 121381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c7_default>; 121481bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 121581bee695SCaleb Connolly #address-cells = <1>; 121681bee695SCaleb Connolly #size-cells = <0>; 121781bee695SCaleb Connolly status = "disabled"; 121881bee695SCaleb Connolly }; 121981bee695SCaleb Connolly 1220129e1c96SFelipe Balbi spi7: spi@89c000 { 1221129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1222f6973229SKonrad Dybcio reg = <0 0x0089c000 0 0x4000>; 1223129e1c96SFelipe Balbi reg-names = "se"; 1224129e1c96SFelipe Balbi clock-names = "se"; 1225129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1226abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1227abdd4b7aSFelipe Balbi <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1228abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1229129e1c96SFelipe Balbi pinctrl-names = "default"; 1230129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi7_default>; 1231129e1c96SFelipe Balbi interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1232129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1233129e1c96SFelipe Balbi #address-cells = <1>; 1234129e1c96SFelipe Balbi #size-cells = <0>; 1235129e1c96SFelipe Balbi status = "disabled"; 1236129e1c96SFelipe Balbi }; 12379cf3ebd1SCaleb Connolly }; 12389cf3ebd1SCaleb Connolly 123905006290SFelipe Balbi gpi_dma1: dma-controller@a00000 { 1240e7e24786SRichard Acayan compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1241f6973229SKonrad Dybcio reg = <0 0x00a00000 0 0x60000>; 124205006290SFelipe Balbi interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 124305006290SFelipe Balbi <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 124405006290SFelipe Balbi <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 124505006290SFelipe Balbi <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 124605006290SFelipe Balbi <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 124705006290SFelipe Balbi <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 124805006290SFelipe Balbi <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 124905006290SFelipe Balbi <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 125005006290SFelipe Balbi <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 125105006290SFelipe Balbi <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 125205006290SFelipe Balbi <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 125305006290SFelipe Balbi <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 125405006290SFelipe Balbi <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 125505006290SFelipe Balbi dma-channels = <13>; 125605006290SFelipe Balbi dma-channel-mask = <0xfa>; 125705006290SFelipe Balbi iommus = <&apps_smmu 0x0616 0x0>; 125805006290SFelipe Balbi #dma-cells = <3>; 125905006290SFelipe Balbi status = "disabled"; 126005006290SFelipe Balbi }; 126105006290SFelipe Balbi 1262e13c6d14SVinod Koul qupv3_id_1: geniqup@ac0000 { 1263e13c6d14SVinod Koul compatible = "qcom,geni-se-qup"; 1264e13c6d14SVinod Koul reg = <0x0 0x00ac0000 0x0 0x6000>; 1265e13c6d14SVinod Koul clock-names = "m-ahb", "s-ahb"; 1266d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1267d6f55763SVinod Koul <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 12689cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x603 0x0>; 1269e13c6d14SVinod Koul #address-cells = <2>; 1270e13c6d14SVinod Koul #size-cells = <2>; 1271e13c6d14SVinod Koul ranges; 1272e13c6d14SVinod Koul status = "disabled"; 1273e13c6d14SVinod Koul 127481bee695SCaleb Connolly i2c8: i2c@a80000 { 127581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 127681bee695SCaleb Connolly reg = <0 0x00a80000 0 0x4000>; 127781bee695SCaleb Connolly clock-names = "se"; 127881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1279abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1280abdd4b7aSFelipe Balbi <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1281abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 128281bee695SCaleb Connolly pinctrl-names = "default"; 128381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c8_default>; 128481bee695SCaleb Connolly interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 128581bee695SCaleb Connolly #address-cells = <1>; 128681bee695SCaleb Connolly #size-cells = <0>; 128781bee695SCaleb Connolly status = "disabled"; 128881bee695SCaleb Connolly }; 128981bee695SCaleb Connolly 1290129e1c96SFelipe Balbi spi8: spi@a80000 { 1291129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1292f6973229SKonrad Dybcio reg = <0 0x00a80000 0 0x4000>; 1293129e1c96SFelipe Balbi reg-names = "se"; 1294129e1c96SFelipe Balbi clock-names = "se"; 1295129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1296abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1297abdd4b7aSFelipe Balbi <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1298abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1299129e1c96SFelipe Balbi pinctrl-names = "default"; 1300129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi8_default>; 1301129e1c96SFelipe Balbi interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1302129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1303129e1c96SFelipe Balbi #address-cells = <1>; 1304129e1c96SFelipe Balbi #size-cells = <0>; 1305129e1c96SFelipe Balbi status = "disabled"; 1306129e1c96SFelipe Balbi }; 1307129e1c96SFelipe Balbi 130881bee695SCaleb Connolly i2c9: i2c@a84000 { 130981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 131081bee695SCaleb Connolly reg = <0 0x00a84000 0 0x4000>; 131181bee695SCaleb Connolly clock-names = "se"; 131281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1313abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1314abdd4b7aSFelipe Balbi <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1315abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 131681bee695SCaleb Connolly pinctrl-names = "default"; 131781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c9_default>; 131881bee695SCaleb Connolly interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 131981bee695SCaleb Connolly #address-cells = <1>; 132081bee695SCaleb Connolly #size-cells = <0>; 132181bee695SCaleb Connolly status = "disabled"; 132281bee695SCaleb Connolly }; 132381bee695SCaleb Connolly 1324129e1c96SFelipe Balbi spi9: spi@a84000 { 1325129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1326f6973229SKonrad Dybcio reg = <0 0x00a84000 0 0x4000>; 1327129e1c96SFelipe Balbi reg-names = "se"; 1328129e1c96SFelipe Balbi clock-names = "se"; 1329129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1330abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1331abdd4b7aSFelipe Balbi <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1332abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1333129e1c96SFelipe Balbi pinctrl-names = "default"; 1334129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi9_default>; 1335129e1c96SFelipe Balbi interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1336129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1337129e1c96SFelipe Balbi #address-cells = <1>; 1338129e1c96SFelipe Balbi #size-cells = <0>; 1339129e1c96SFelipe Balbi status = "disabled"; 1340129e1c96SFelipe Balbi }; 1341129e1c96SFelipe Balbi 13429ebaa4a8SBartosz Golaszewski uart9: serial@a84000 { 134310d900a8SBartosz Golaszewski compatible = "qcom,geni-uart"; 134410d900a8SBartosz Golaszewski reg = <0x0 0x00a84000 0x0 0x4000>; 134510d900a8SBartosz Golaszewski reg-names = "se"; 134610d900a8SBartosz Golaszewski clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 134710d900a8SBartosz Golaszewski clock-names = "se"; 134810d900a8SBartosz Golaszewski pinctrl-0 = <&qup_uart9_default>; 134910d900a8SBartosz Golaszewski pinctrl-names = "default"; 135010d900a8SBartosz Golaszewski interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 135110d900a8SBartosz Golaszewski #address-cells = <1>; 135210d900a8SBartosz Golaszewski #size-cells = <0>; 135310d900a8SBartosz Golaszewski status = "disabled"; 135410d900a8SBartosz Golaszewski }; 135510d900a8SBartosz Golaszewski 135681bee695SCaleb Connolly i2c10: i2c@a88000 { 135781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 135881bee695SCaleb Connolly reg = <0 0x00a88000 0 0x4000>; 135981bee695SCaleb Connolly clock-names = "se"; 136081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1361abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1362abdd4b7aSFelipe Balbi <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1363abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 136481bee695SCaleb Connolly pinctrl-names = "default"; 136581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c10_default>; 136681bee695SCaleb Connolly interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 136781bee695SCaleb Connolly #address-cells = <1>; 136881bee695SCaleb Connolly #size-cells = <0>; 136981bee695SCaleb Connolly status = "disabled"; 137081bee695SCaleb Connolly }; 137181bee695SCaleb Connolly 1372129e1c96SFelipe Balbi spi10: spi@a88000 { 1373129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1374f6973229SKonrad Dybcio reg = <0 0x00a88000 0 0x4000>; 1375129e1c96SFelipe Balbi reg-names = "se"; 1376129e1c96SFelipe Balbi clock-names = "se"; 1377129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1378abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1379abdd4b7aSFelipe Balbi <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1380abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1381129e1c96SFelipe Balbi pinctrl-names = "default"; 1382129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi10_default>; 1383129e1c96SFelipe Balbi interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1384129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1385129e1c96SFelipe Balbi #address-cells = <1>; 1386129e1c96SFelipe Balbi #size-cells = <0>; 1387129e1c96SFelipe Balbi status = "disabled"; 1388129e1c96SFelipe Balbi }; 1389129e1c96SFelipe Balbi 139081bee695SCaleb Connolly i2c11: i2c@a8c000 { 139181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 139281bee695SCaleb Connolly reg = <0 0x00a8c000 0 0x4000>; 139381bee695SCaleb Connolly clock-names = "se"; 139481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1395abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1396abdd4b7aSFelipe Balbi <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1397abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 139881bee695SCaleb Connolly pinctrl-names = "default"; 139981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c11_default>; 140081bee695SCaleb Connolly interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 140181bee695SCaleb Connolly #address-cells = <1>; 140281bee695SCaleb Connolly #size-cells = <0>; 140381bee695SCaleb Connolly status = "disabled"; 140481bee695SCaleb Connolly }; 140581bee695SCaleb Connolly 1406129e1c96SFelipe Balbi spi11: spi@a8c000 { 1407129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1408f6973229SKonrad Dybcio reg = <0 0x00a8c000 0 0x4000>; 1409129e1c96SFelipe Balbi reg-names = "se"; 1410129e1c96SFelipe Balbi clock-names = "se"; 1411129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1412abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1413abdd4b7aSFelipe Balbi <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1414abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1415129e1c96SFelipe Balbi pinctrl-names = "default"; 1416129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi11_default>; 1417129e1c96SFelipe Balbi interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1418129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1419129e1c96SFelipe Balbi #address-cells = <1>; 1420129e1c96SFelipe Balbi #size-cells = <0>; 1421129e1c96SFelipe Balbi status = "disabled"; 1422129e1c96SFelipe Balbi }; 1423129e1c96SFelipe Balbi 1424e13c6d14SVinod Koul uart2: serial@a90000 { 1425e13c6d14SVinod Koul compatible = "qcom,geni-debug-uart"; 1426e13c6d14SVinod Koul reg = <0x0 0x00a90000 0x0 0x4000>; 1427e13c6d14SVinod Koul clock-names = "se"; 1428d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1429e13c6d14SVinod Koul interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1430e13c6d14SVinod Koul status = "disabled"; 1431e13c6d14SVinod Koul }; 143281bee695SCaleb Connolly 143381bee695SCaleb Connolly i2c12: i2c@a90000 { 143481bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 143581bee695SCaleb Connolly reg = <0 0x00a90000 0 0x4000>; 143681bee695SCaleb Connolly clock-names = "se"; 143781bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1438abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1439abdd4b7aSFelipe Balbi <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1440abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 144181bee695SCaleb Connolly pinctrl-names = "default"; 144281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c12_default>; 144381bee695SCaleb Connolly interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 144481bee695SCaleb Connolly #address-cells = <1>; 144581bee695SCaleb Connolly #size-cells = <0>; 144681bee695SCaleb Connolly status = "disabled"; 144781bee695SCaleb Connolly }; 144881bee695SCaleb Connolly 1449129e1c96SFelipe Balbi spi12: spi@a90000 { 1450129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1451f6973229SKonrad Dybcio reg = <0 0x00a90000 0 0x4000>; 1452129e1c96SFelipe Balbi reg-names = "se"; 1453129e1c96SFelipe Balbi clock-names = "se"; 1454129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1455abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1456abdd4b7aSFelipe Balbi <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1457abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1458129e1c96SFelipe Balbi pinctrl-names = "default"; 1459129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi12_default>; 1460129e1c96SFelipe Balbi interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1461129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1462129e1c96SFelipe Balbi #address-cells = <1>; 1463129e1c96SFelipe Balbi #size-cells = <0>; 1464129e1c96SFelipe Balbi status = "disabled"; 1465129e1c96SFelipe Balbi }; 1466129e1c96SFelipe Balbi 146781bee695SCaleb Connolly i2c16: i2c@94000 { 146881bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 1469f6973229SKonrad Dybcio reg = <0 0x00094000 0 0x4000>; 147081bee695SCaleb Connolly clock-names = "se"; 147181bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1472abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1473abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1474abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 147581bee695SCaleb Connolly pinctrl-names = "default"; 147681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c16_default>; 147781bee695SCaleb Connolly interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 147881bee695SCaleb Connolly #address-cells = <1>; 147981bee695SCaleb Connolly #size-cells = <0>; 148081bee695SCaleb Connolly status = "disabled"; 148181bee695SCaleb Connolly }; 1482129e1c96SFelipe Balbi 1483129e1c96SFelipe Balbi spi16: spi@a94000 { 1484129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1485f6973229SKonrad Dybcio reg = <0 0x00a94000 0 0x4000>; 1486129e1c96SFelipe Balbi reg-names = "se"; 1487129e1c96SFelipe Balbi clock-names = "se"; 1488129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1489abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1490abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1491abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1492129e1c96SFelipe Balbi pinctrl-names = "default"; 1493129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi16_default>; 1494129e1c96SFelipe Balbi interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1495129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1496129e1c96SFelipe Balbi #address-cells = <1>; 1497129e1c96SFelipe Balbi #size-cells = <0>; 1498129e1c96SFelipe Balbi status = "disabled"; 1499129e1c96SFelipe Balbi }; 1500e13c6d14SVinod Koul }; 1501e13c6d14SVinod Koul 150205006290SFelipe Balbi gpi_dma2: dma-controller@c00000 { 1503e7e24786SRichard Acayan compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1504f6973229SKonrad Dybcio reg = <0 0x00c00000 0 0x60000>; 150505006290SFelipe Balbi interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 150605006290SFelipe Balbi <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 150705006290SFelipe Balbi <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 150805006290SFelipe Balbi <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 150905006290SFelipe Balbi <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 151005006290SFelipe Balbi <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 151105006290SFelipe Balbi <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 151205006290SFelipe Balbi <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 151305006290SFelipe Balbi <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 151405006290SFelipe Balbi <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 151505006290SFelipe Balbi <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 151605006290SFelipe Balbi <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 151705006290SFelipe Balbi <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 151805006290SFelipe Balbi dma-channels = <13>; 151905006290SFelipe Balbi dma-channel-mask = <0xfa>; 152005006290SFelipe Balbi iommus = <&apps_smmu 0x07b6 0x0>; 152105006290SFelipe Balbi #dma-cells = <3>; 152205006290SFelipe Balbi status = "disabled"; 152305006290SFelipe Balbi }; 152405006290SFelipe Balbi 15259cf3ebd1SCaleb Connolly qupv3_id_2: geniqup@cc0000 { 15269cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 15279cf3ebd1SCaleb Connolly reg = <0x0 0x00cc0000 0x0 0x6000>; 15289cf3ebd1SCaleb Connolly 15299cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 15309cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 15319cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 15329cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x7a3 0x0>; 15339cf3ebd1SCaleb Connolly #address-cells = <2>; 15349cf3ebd1SCaleb Connolly #size-cells = <2>; 15359cf3ebd1SCaleb Connolly ranges; 15369cf3ebd1SCaleb Connolly status = "disabled"; 153781bee695SCaleb Connolly 153881bee695SCaleb Connolly i2c17: i2c@c80000 { 153981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 154081bee695SCaleb Connolly reg = <0 0x00c80000 0 0x4000>; 154181bee695SCaleb Connolly clock-names = "se"; 154281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1543abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1544abdd4b7aSFelipe Balbi <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1545abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 154681bee695SCaleb Connolly pinctrl-names = "default"; 154781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c17_default>; 154881bee695SCaleb Connolly interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 154981bee695SCaleb Connolly #address-cells = <1>; 155081bee695SCaleb Connolly #size-cells = <0>; 155181bee695SCaleb Connolly status = "disabled"; 155281bee695SCaleb Connolly }; 155381bee695SCaleb Connolly 1554129e1c96SFelipe Balbi spi17: spi@c80000 { 1555129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1556f6973229SKonrad Dybcio reg = <0 0x00c80000 0 0x4000>; 1557129e1c96SFelipe Balbi reg-names = "se"; 1558129e1c96SFelipe Balbi clock-names = "se"; 1559129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1560abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1561abdd4b7aSFelipe Balbi <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1562abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1563129e1c96SFelipe Balbi pinctrl-names = "default"; 1564129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi17_default>; 1565129e1c96SFelipe Balbi interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1566129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1567129e1c96SFelipe Balbi #address-cells = <1>; 1568129e1c96SFelipe Balbi #size-cells = <0>; 1569129e1c96SFelipe Balbi status = "disabled"; 1570129e1c96SFelipe Balbi }; 1571129e1c96SFelipe Balbi 157281bee695SCaleb Connolly i2c18: i2c@c84000 { 157381bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 157481bee695SCaleb Connolly reg = <0 0x00c84000 0 0x4000>; 157581bee695SCaleb Connolly clock-names = "se"; 157681bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1577abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1578abdd4b7aSFelipe Balbi <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1579abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 158081bee695SCaleb Connolly pinctrl-names = "default"; 158181bee695SCaleb Connolly pinctrl-0 = <&qup_i2c18_default>; 158281bee695SCaleb Connolly interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 158381bee695SCaleb Connolly #address-cells = <1>; 158481bee695SCaleb Connolly #size-cells = <0>; 158581bee695SCaleb Connolly status = "disabled"; 158681bee695SCaleb Connolly }; 158781bee695SCaleb Connolly 1588129e1c96SFelipe Balbi spi18: spi@c84000 { 1589129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1590f6973229SKonrad Dybcio reg = <0 0x00c84000 0 0x4000>; 1591129e1c96SFelipe Balbi reg-names = "se"; 1592129e1c96SFelipe Balbi clock-names = "se"; 1593129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1594abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1595abdd4b7aSFelipe Balbi <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1596abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1597129e1c96SFelipe Balbi pinctrl-names = "default"; 1598129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi18_default>; 1599129e1c96SFelipe Balbi interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1600129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1601129e1c96SFelipe Balbi #address-cells = <1>; 1602129e1c96SFelipe Balbi #size-cells = <0>; 1603129e1c96SFelipe Balbi status = "disabled"; 1604129e1c96SFelipe Balbi }; 1605129e1c96SFelipe Balbi 160681bee695SCaleb Connolly i2c19: i2c@c88000 { 160781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 160881bee695SCaleb Connolly reg = <0 0x00c88000 0 0x4000>; 160981bee695SCaleb Connolly clock-names = "se"; 161081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1611abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1612abdd4b7aSFelipe Balbi <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1613abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 161481bee695SCaleb Connolly pinctrl-names = "default"; 161581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c19_default>; 161681bee695SCaleb Connolly interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 161781bee695SCaleb Connolly #address-cells = <1>; 161881bee695SCaleb Connolly #size-cells = <0>; 161981bee695SCaleb Connolly status = "disabled"; 162081bee695SCaleb Connolly }; 162181bee695SCaleb Connolly 1622129e1c96SFelipe Balbi spi19: spi@c88000 { 1623129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1624f6973229SKonrad Dybcio reg = <0 0x00c88000 0 0x4000>; 1625129e1c96SFelipe Balbi reg-names = "se"; 1626129e1c96SFelipe Balbi clock-names = "se"; 1627129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1628abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1629abdd4b7aSFelipe Balbi <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1630abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1631129e1c96SFelipe Balbi pinctrl-names = "default"; 1632129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi19_default>; 1633129e1c96SFelipe Balbi interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1634129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1635129e1c96SFelipe Balbi #address-cells = <1>; 1636129e1c96SFelipe Balbi #size-cells = <0>; 1637129e1c96SFelipe Balbi status = "disabled"; 1638129e1c96SFelipe Balbi }; 1639129e1c96SFelipe Balbi 164081bee695SCaleb Connolly i2c13: i2c@c8c000 { 164181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 164281bee695SCaleb Connolly reg = <0 0x00c8c000 0 0x4000>; 164381bee695SCaleb Connolly clock-names = "se"; 164481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1645abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1646abdd4b7aSFelipe Balbi <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1647abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 164881bee695SCaleb Connolly pinctrl-names = "default"; 164981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c13_default>; 165081bee695SCaleb Connolly interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 165181bee695SCaleb Connolly #address-cells = <1>; 165281bee695SCaleb Connolly #size-cells = <0>; 165381bee695SCaleb Connolly status = "disabled"; 165481bee695SCaleb Connolly }; 165581bee695SCaleb Connolly 1656129e1c96SFelipe Balbi spi13: spi@c8c000 { 1657129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1658f6973229SKonrad Dybcio reg = <0 0x00c8c000 0 0x4000>; 1659129e1c96SFelipe Balbi reg-names = "se"; 1660129e1c96SFelipe Balbi clock-names = "se"; 1661129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1662abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1663abdd4b7aSFelipe Balbi <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1664abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1665129e1c96SFelipe Balbi pinctrl-names = "default"; 1666129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi13_default>; 1667129e1c96SFelipe Balbi interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1668129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1669129e1c96SFelipe Balbi #address-cells = <1>; 1670129e1c96SFelipe Balbi #size-cells = <0>; 1671129e1c96SFelipe Balbi status = "disabled"; 1672129e1c96SFelipe Balbi }; 1673129e1c96SFelipe Balbi 167481bee695SCaleb Connolly i2c14: i2c@c90000 { 167581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 167681bee695SCaleb Connolly reg = <0 0x00c90000 0 0x4000>; 167781bee695SCaleb Connolly clock-names = "se"; 167881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1679abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1680abdd4b7aSFelipe Balbi <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1681abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 168281bee695SCaleb Connolly pinctrl-names = "default"; 168381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c14_default>; 168481bee695SCaleb Connolly interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 168581bee695SCaleb Connolly #address-cells = <1>; 168681bee695SCaleb Connolly #size-cells = <0>; 168781bee695SCaleb Connolly status = "disabled"; 168881bee695SCaleb Connolly }; 168981bee695SCaleb Connolly 1690129e1c96SFelipe Balbi spi14: spi@c90000 { 1691129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1692f6973229SKonrad Dybcio reg = <0 0x00c90000 0 0x4000>; 1693129e1c96SFelipe Balbi reg-names = "se"; 1694129e1c96SFelipe Balbi clock-names = "se"; 1695129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1696abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1697abdd4b7aSFelipe Balbi <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1698abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1699129e1c96SFelipe Balbi pinctrl-names = "default"; 1700129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi14_default>; 1701129e1c96SFelipe Balbi interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1702129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1703129e1c96SFelipe Balbi #address-cells = <1>; 1704129e1c96SFelipe Balbi #size-cells = <0>; 1705129e1c96SFelipe Balbi status = "disabled"; 1706129e1c96SFelipe Balbi }; 1707129e1c96SFelipe Balbi 170881bee695SCaleb Connolly i2c15: i2c@c94000 { 170981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 171081bee695SCaleb Connolly reg = <0 0x00c94000 0 0x4000>; 171181bee695SCaleb Connolly clock-names = "se"; 171281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1713abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1714abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1715abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 171681bee695SCaleb Connolly pinctrl-names = "default"; 171781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c15_default>; 171881bee695SCaleb Connolly interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 171981bee695SCaleb Connolly #address-cells = <1>; 172081bee695SCaleb Connolly #size-cells = <0>; 172181bee695SCaleb Connolly status = "disabled"; 172281bee695SCaleb Connolly }; 1723129e1c96SFelipe Balbi 1724129e1c96SFelipe Balbi spi15: spi@c94000 { 1725129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1726f6973229SKonrad Dybcio reg = <0 0x00c94000 0 0x4000>; 1727129e1c96SFelipe Balbi reg-names = "se"; 1728129e1c96SFelipe Balbi clock-names = "se"; 1729129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1730abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1731abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1732abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1733129e1c96SFelipe Balbi pinctrl-names = "default"; 1734129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi15_default>; 1735129e1c96SFelipe Balbi interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1736129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1737129e1c96SFelipe Balbi #address-cells = <1>; 1738129e1c96SFelipe Balbi #size-cells = <0>; 1739129e1c96SFelipe Balbi status = "disabled"; 1740129e1c96SFelipe Balbi }; 17419cf3ebd1SCaleb Connolly }; 17429cf3ebd1SCaleb Connolly 174371a2fc6eSJonathan Marek config_noc: interconnect@1500000 { 174471a2fc6eSJonathan Marek compatible = "qcom,sm8150-config-noc"; 174571a2fc6eSJonathan Marek reg = <0 0x01500000 0 0x7400>; 174671a2fc6eSJonathan Marek #interconnect-cells = <1>; 174771a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 174871a2fc6eSJonathan Marek }; 174971a2fc6eSJonathan Marek 175071a2fc6eSJonathan Marek system_noc: interconnect@1620000 { 175171a2fc6eSJonathan Marek compatible = "qcom,sm8150-system-noc"; 175271a2fc6eSJonathan Marek reg = <0 0x01620000 0 0x19400>; 175371a2fc6eSJonathan Marek #interconnect-cells = <1>; 175471a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 175571a2fc6eSJonathan Marek }; 175671a2fc6eSJonathan Marek 175771a2fc6eSJonathan Marek mc_virt: interconnect@163a000 { 175871a2fc6eSJonathan Marek compatible = "qcom,sm8150-mc-virt"; 175971a2fc6eSJonathan Marek reg = <0 0x0163a000 0 0x1000>; 176071a2fc6eSJonathan Marek #interconnect-cells = <1>; 176171a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 176271a2fc6eSJonathan Marek }; 176371a2fc6eSJonathan Marek 176471a2fc6eSJonathan Marek aggre1_noc: interconnect@16e0000 { 176571a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre1-noc"; 176671a2fc6eSJonathan Marek reg = <0 0x016e0000 0 0xd080>; 176771a2fc6eSJonathan Marek #interconnect-cells = <1>; 176871a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 176971a2fc6eSJonathan Marek }; 177071a2fc6eSJonathan Marek 177171a2fc6eSJonathan Marek aggre2_noc: interconnect@1700000 { 177271a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre2-noc"; 177371a2fc6eSJonathan Marek reg = <0 0x01700000 0 0x20000>; 177471a2fc6eSJonathan Marek #interconnect-cells = <1>; 177571a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 177671a2fc6eSJonathan Marek }; 177771a2fc6eSJonathan Marek 177871a2fc6eSJonathan Marek compute_noc: interconnect@1720000 { 177971a2fc6eSJonathan Marek compatible = "qcom,sm8150-compute-noc"; 178071a2fc6eSJonathan Marek reg = <0 0x01720000 0 0x7000>; 178171a2fc6eSJonathan Marek #interconnect-cells = <1>; 178271a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 178371a2fc6eSJonathan Marek }; 178471a2fc6eSJonathan Marek 178571a2fc6eSJonathan Marek mmss_noc: interconnect@1740000 { 178671a2fc6eSJonathan Marek compatible = "qcom,sm8150-mmss-noc"; 178771a2fc6eSJonathan Marek reg = <0 0x01740000 0 0x1c100>; 178871a2fc6eSJonathan Marek #interconnect-cells = <1>; 178971a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 179071a2fc6eSJonathan Marek }; 179171a2fc6eSJonathan Marek 1792bb1f7cf6SSouradeep Chowdhury system-cache-controller@9200000 { 1793bb1f7cf6SSouradeep Chowdhury compatible = "qcom,sm8150-llcc"; 1794c5ccf8d3SManivannan Sadhasivam reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 1795c5ccf8d3SManivannan Sadhasivam <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 1796c5ccf8d3SManivannan Sadhasivam <0 0x09600000 0 0x50000>; 1797c5ccf8d3SManivannan Sadhasivam reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 1798c5ccf8d3SManivannan Sadhasivam "llcc3_base", "llcc_broadcast_base"; 1799bb1f7cf6SSouradeep Chowdhury interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1800bb1f7cf6SSouradeep Chowdhury }; 1801bb1f7cf6SSouradeep Chowdhury 1802d4b94c82SSouradeep Chowdhury dma@10a2000 { 1803d4b94c82SSouradeep Chowdhury compatible = "qcom,sm8150-dcc", "qcom,dcc"; 1804d4b94c82SSouradeep Chowdhury reg = <0x0 0x010a2000 0x0 0x1000>, 1805d4b94c82SSouradeep Chowdhury <0x0 0x010ad000 0x0 0x3000>; 1806d4b94c82SSouradeep Chowdhury }; 1807d4b94c82SSouradeep Chowdhury 1808a1c86c68SBhupesh Sharma pcie0: pci@1c00000 { 1809a1c86c68SBhupesh Sharma compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1810a1c86c68SBhupesh Sharma reg = <0 0x01c00000 0 0x3000>, 1811a1c86c68SBhupesh Sharma <0 0x60000000 0 0xf1d>, 1812a1c86c68SBhupesh Sharma <0 0x60000f20 0 0xa8>, 1813a1c86c68SBhupesh Sharma <0 0x60001000 0 0x1000>, 1814a1c86c68SBhupesh Sharma <0 0x60100000 0 0x100000>; 1815a1c86c68SBhupesh Sharma reg-names = "parf", "dbi", "elbi", "atu", "config"; 1816a1c86c68SBhupesh Sharma device_type = "pci"; 1817a1c86c68SBhupesh Sharma linux,pci-domain = <0>; 1818a1c86c68SBhupesh Sharma bus-range = <0x00 0xff>; 1819a1c86c68SBhupesh Sharma num-lanes = <1>; 1820a1c86c68SBhupesh Sharma 1821a1c86c68SBhupesh Sharma #address-cells = <3>; 1822a1c86c68SBhupesh Sharma #size-cells = <2>; 1823a1c86c68SBhupesh Sharma 1824422b110bSManivannan Sadhasivam ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1825422b110bSManivannan Sadhasivam <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1826a1c86c68SBhupesh Sharma 1827a1c86c68SBhupesh Sharma interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1828a1c86c68SBhupesh Sharma interrupt-names = "msi"; 1829a1c86c68SBhupesh Sharma #interrupt-cells = <1>; 1830a1c86c68SBhupesh Sharma interrupt-map-mask = <0 0 0 0x7>; 1831a1c86c68SBhupesh Sharma interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1832a1c86c68SBhupesh Sharma <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1833a1c86c68SBhupesh Sharma <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1834a1c86c68SBhupesh Sharma <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1835a1c86c68SBhupesh Sharma 1836a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1837a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_AUX_CLK>, 1838a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1839a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1840a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1841a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1842a1c86c68SBhupesh Sharma <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1843a1c86c68SBhupesh Sharma clock-names = "pipe", 1844a1c86c68SBhupesh Sharma "aux", 1845a1c86c68SBhupesh Sharma "cfg", 1846a1c86c68SBhupesh Sharma "bus_master", 1847a1c86c68SBhupesh Sharma "bus_slave", 1848a1c86c68SBhupesh Sharma "slave_q2a", 1849a1c86c68SBhupesh Sharma "tbu"; 1850a1c86c68SBhupesh Sharma 1851a1c86c68SBhupesh Sharma iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1852a1c86c68SBhupesh Sharma <0x100 &apps_smmu 0x1d81 0x1>; 1853a1c86c68SBhupesh Sharma 1854a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_0_BCR>; 1855a1c86c68SBhupesh Sharma reset-names = "pci"; 1856a1c86c68SBhupesh Sharma 1857a1c86c68SBhupesh Sharma power-domains = <&gcc PCIE_0_GDSC>; 1858a1c86c68SBhupesh Sharma 1859a1c86c68SBhupesh Sharma phys = <&pcie0_lane>; 1860a1c86c68SBhupesh Sharma phy-names = "pciephy"; 1861a1c86c68SBhupesh Sharma 1862a1c86c68SBhupesh Sharma perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1863a1c86c68SBhupesh Sharma enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1864a1c86c68SBhupesh Sharma 1865a1c86c68SBhupesh Sharma pinctrl-names = "default"; 1866a1c86c68SBhupesh Sharma pinctrl-0 = <&pcie0_default_state>; 1867a1c86c68SBhupesh Sharma 1868a1c86c68SBhupesh Sharma status = "disabled"; 1869a1c86c68SBhupesh Sharma }; 1870a1c86c68SBhupesh Sharma 1871a1c86c68SBhupesh Sharma pcie0_phy: phy@1c06000 { 1872a1c86c68SBhupesh Sharma compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1873a1c86c68SBhupesh Sharma reg = <0 0x01c06000 0 0x1c0>; 1874a1c86c68SBhupesh Sharma #address-cells = <2>; 1875a1c86c68SBhupesh Sharma #size-cells = <2>; 1876a1c86c68SBhupesh Sharma ranges; 1877a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1878a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1879a1c86c68SBhupesh Sharma <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1880a1c86c68SBhupesh Sharma clock-names = "aux", "cfg_ahb", "refgen"; 1881a1c86c68SBhupesh Sharma 1882a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1883a1c86c68SBhupesh Sharma reset-names = "phy"; 1884a1c86c68SBhupesh Sharma 1885a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1886a1c86c68SBhupesh Sharma assigned-clock-rates = <100000000>; 1887a1c86c68SBhupesh Sharma 1888a1c86c68SBhupesh Sharma status = "disabled"; 1889a1c86c68SBhupesh Sharma 1890a1c86c68SBhupesh Sharma pcie0_lane: phy@1c06200 { 1891f6973229SKonrad Dybcio reg = <0 0x01c06200 0 0x170>, /* tx */ 1892f6973229SKonrad Dybcio <0 0x01c06400 0 0x200>, /* rx */ 1893f6973229SKonrad Dybcio <0 0x01c06800 0 0x1f0>, /* pcs */ 1894f6973229SKonrad Dybcio <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1895a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1896a1c86c68SBhupesh Sharma clock-names = "pipe0"; 1897a1c86c68SBhupesh Sharma 1898a1c86c68SBhupesh Sharma #phy-cells = <0>; 1899a1c86c68SBhupesh Sharma clock-output-names = "pcie_0_pipe_clk"; 1900a1c86c68SBhupesh Sharma }; 1901a1c86c68SBhupesh Sharma }; 1902a1c86c68SBhupesh Sharma 1903a1c86c68SBhupesh Sharma pcie1: pci@1c08000 { 1904a1c86c68SBhupesh Sharma compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1905a1c86c68SBhupesh Sharma reg = <0 0x01c08000 0 0x3000>, 1906a1c86c68SBhupesh Sharma <0 0x40000000 0 0xf1d>, 1907a1c86c68SBhupesh Sharma <0 0x40000f20 0 0xa8>, 1908a1c86c68SBhupesh Sharma <0 0x40001000 0 0x1000>, 1909a1c86c68SBhupesh Sharma <0 0x40100000 0 0x100000>; 1910a1c86c68SBhupesh Sharma reg-names = "parf", "dbi", "elbi", "atu", "config"; 1911a1c86c68SBhupesh Sharma device_type = "pci"; 1912a1c86c68SBhupesh Sharma linux,pci-domain = <1>; 1913a1c86c68SBhupesh Sharma bus-range = <0x00 0xff>; 1914a1c86c68SBhupesh Sharma num-lanes = <2>; 1915a1c86c68SBhupesh Sharma 1916a1c86c68SBhupesh Sharma #address-cells = <3>; 1917a1c86c68SBhupesh Sharma #size-cells = <2>; 1918a1c86c68SBhupesh Sharma 1919422b110bSManivannan Sadhasivam ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1920a1c86c68SBhupesh Sharma <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1921a1c86c68SBhupesh Sharma 1922a1c86c68SBhupesh Sharma interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1923a1c86c68SBhupesh Sharma interrupt-names = "msi"; 1924a1c86c68SBhupesh Sharma #interrupt-cells = <1>; 1925a1c86c68SBhupesh Sharma interrupt-map-mask = <0 0 0 0x7>; 1926a1c86c68SBhupesh Sharma interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1927a1c86c68SBhupesh Sharma <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1928a1c86c68SBhupesh Sharma <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1929a1c86c68SBhupesh Sharma <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1930a1c86c68SBhupesh Sharma 1931a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1932a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_AUX_CLK>, 1933a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1934a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1935a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1936a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1937a1c86c68SBhupesh Sharma <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1938a1c86c68SBhupesh Sharma clock-names = "pipe", 1939a1c86c68SBhupesh Sharma "aux", 1940a1c86c68SBhupesh Sharma "cfg", 1941a1c86c68SBhupesh Sharma "bus_master", 1942a1c86c68SBhupesh Sharma "bus_slave", 1943a1c86c68SBhupesh Sharma "slave_q2a", 1944a1c86c68SBhupesh Sharma "tbu"; 1945a1c86c68SBhupesh Sharma 1946a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1947a1c86c68SBhupesh Sharma assigned-clock-rates = <19200000>; 1948a1c86c68SBhupesh Sharma 1949a1c86c68SBhupesh Sharma iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1950a1c86c68SBhupesh Sharma <0x100 &apps_smmu 0x1e01 0x1>; 1951a1c86c68SBhupesh Sharma 1952a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_1_BCR>; 1953a1c86c68SBhupesh Sharma reset-names = "pci"; 1954a1c86c68SBhupesh Sharma 1955a1c86c68SBhupesh Sharma power-domains = <&gcc PCIE_1_GDSC>; 1956a1c86c68SBhupesh Sharma 1957a1c86c68SBhupesh Sharma phys = <&pcie1_lane>; 1958a1c86c68SBhupesh Sharma phy-names = "pciephy"; 1959a1c86c68SBhupesh Sharma 1960a1c86c68SBhupesh Sharma perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; 1961a1c86c68SBhupesh Sharma enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 1962a1c86c68SBhupesh Sharma 1963a1c86c68SBhupesh Sharma pinctrl-names = "default"; 1964a1c86c68SBhupesh Sharma pinctrl-0 = <&pcie1_default_state>; 1965a1c86c68SBhupesh Sharma 1966a1c86c68SBhupesh Sharma status = "disabled"; 1967a1c86c68SBhupesh Sharma }; 1968a1c86c68SBhupesh Sharma 1969a1c86c68SBhupesh Sharma pcie1_phy: phy@1c0e000 { 1970a1c86c68SBhupesh Sharma compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 1971a1c86c68SBhupesh Sharma reg = <0 0x01c0e000 0 0x1c0>; 1972a1c86c68SBhupesh Sharma #address-cells = <2>; 1973a1c86c68SBhupesh Sharma #size-cells = <2>; 1974a1c86c68SBhupesh Sharma ranges; 1975a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1976a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1977a1c86c68SBhupesh Sharma <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1978a1c86c68SBhupesh Sharma clock-names = "aux", "cfg_ahb", "refgen"; 1979a1c86c68SBhupesh Sharma 1980a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1981a1c86c68SBhupesh Sharma reset-names = "phy"; 1982a1c86c68SBhupesh Sharma 1983a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1984a1c86c68SBhupesh Sharma assigned-clock-rates = <100000000>; 1985a1c86c68SBhupesh Sharma 1986a1c86c68SBhupesh Sharma status = "disabled"; 1987a1c86c68SBhupesh Sharma 1988a1c86c68SBhupesh Sharma pcie1_lane: phy@1c0e200 { 1989f6973229SKonrad Dybcio reg = <0 0x01c0e200 0 0x170>, /* tx0 */ 1990f6973229SKonrad Dybcio <0 0x01c0e400 0 0x200>, /* rx0 */ 1991f6973229SKonrad Dybcio <0 0x01c0ea00 0 0x1f0>, /* pcs */ 1992f6973229SKonrad Dybcio <0 0x01c0e600 0 0x170>, /* tx1 */ 1993f6973229SKonrad Dybcio <0 0x01c0e800 0 0x200>, /* rx1 */ 1994f6973229SKonrad Dybcio <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1995a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1996a1c86c68SBhupesh Sharma clock-names = "pipe0"; 1997a1c86c68SBhupesh Sharma 1998a1c86c68SBhupesh Sharma #phy-cells = <0>; 1999a1c86c68SBhupesh Sharma clock-output-names = "pcie_1_pipe_clk"; 2000a1c86c68SBhupesh Sharma }; 2001a1c86c68SBhupesh Sharma }; 2002a1c86c68SBhupesh Sharma 20033834a2e9SVinod Koul ufs_mem_hc: ufshc@1d84000 { 20043834a2e9SVinod Koul compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 20053834a2e9SVinod Koul "jedec,ufs-2.0"; 200698aee1e3SBhupesh Sharma reg = <0 0x01d84000 0 0x2500>, 200798aee1e3SBhupesh Sharma <0 0x01d90000 0 0x8000>; 200898aee1e3SBhupesh Sharma reg-names = "std", "ice"; 20093834a2e9SVinod Koul interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 20103834a2e9SVinod Koul phys = <&ufs_mem_phy_lanes>; 20113834a2e9SVinod Koul phy-names = "ufsphy"; 20123834a2e9SVinod Koul lanes-per-direction = <2>; 20133834a2e9SVinod Koul #reset-cells = <1>; 20143834a2e9SVinod Koul resets = <&gcc GCC_UFS_PHY_BCR>; 20153834a2e9SVinod Koul reset-names = "rst"; 20163834a2e9SVinod Koul 201748156232SJonathan Marek iommus = <&apps_smmu 0x300 0>; 201848156232SJonathan Marek 20193834a2e9SVinod Koul clock-names = 20203834a2e9SVinod Koul "core_clk", 20213834a2e9SVinod Koul "bus_aggr_clk", 20223834a2e9SVinod Koul "iface_clk", 20233834a2e9SVinod Koul "core_clk_unipro", 20243834a2e9SVinod Koul "ref_clk", 20253834a2e9SVinod Koul "tx_lane0_sync_clk", 20263834a2e9SVinod Koul "rx_lane0_sync_clk", 202798aee1e3SBhupesh Sharma "rx_lane1_sync_clk", 202898aee1e3SBhupesh Sharma "ice_core_clk"; 20293834a2e9SVinod Koul clocks = 20303834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AXI_CLK>, 20313834a2e9SVinod Koul <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 20323834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AHB_CLK>, 20333834a2e9SVinod Koul <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 20343834a2e9SVinod Koul <&rpmhcc RPMH_CXO_CLK>, 20353834a2e9SVinod Koul <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 20363834a2e9SVinod Koul <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 203798aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 203898aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 20393834a2e9SVinod Koul freq-table-hz = 20403834a2e9SVinod Koul <37500000 300000000>, 20413834a2e9SVinod Koul <0 0>, 20423834a2e9SVinod Koul <0 0>, 20433834a2e9SVinod Koul <37500000 300000000>, 20443834a2e9SVinod Koul <0 0>, 20453834a2e9SVinod Koul <0 0>, 20463834a2e9SVinod Koul <0 0>, 204798aee1e3SBhupesh Sharma <0 0>, 204898aee1e3SBhupesh Sharma <0 300000000>; 20493834a2e9SVinod Koul 20503834a2e9SVinod Koul status = "disabled"; 20513834a2e9SVinod Koul }; 20523834a2e9SVinod Koul 20533834a2e9SVinod Koul ufs_mem_phy: phy@1d87000 { 20543834a2e9SVinod Koul compatible = "qcom,sm8150-qmp-ufs-phy"; 2055c79ec891SVinod Koul reg = <0 0x01d87000 0 0x1c0>; 20563834a2e9SVinod Koul #address-cells = <2>; 20573834a2e9SVinod Koul #size-cells = <2>; 20583834a2e9SVinod Koul ranges; 20593834a2e9SVinod Koul clock-names = "ref", 20603834a2e9SVinod Koul "ref_aux"; 20613834a2e9SVinod Koul clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 20623834a2e9SVinod Koul <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 20633834a2e9SVinod Koul 2064fe75b0c4SBhupesh Sharma power-domains = <&gcc UFS_PHY_GDSC>; 2065fe75b0c4SBhupesh Sharma 20663834a2e9SVinod Koul resets = <&ufs_mem_hc 0>; 20673834a2e9SVinod Koul reset-names = "ufsphy"; 20683834a2e9SVinod Koul status = "disabled"; 20693834a2e9SVinod Koul 20701351512fSShawn Guo ufs_mem_phy_lanes: phy@1d87400 { 207136a31b3aSJohan Hovold reg = <0 0x01d87400 0 0x16c>, 207236a31b3aSJohan Hovold <0 0x01d87600 0 0x200>, 207336a31b3aSJohan Hovold <0 0x01d87c00 0 0x200>, 207436a31b3aSJohan Hovold <0 0x01d87800 0 0x16c>, 207536a31b3aSJohan Hovold <0 0x01d87a00 0 0x200>; 20763834a2e9SVinod Koul #phy-cells = <0>; 20773834a2e9SVinod Koul }; 20783834a2e9SVinod Koul }; 20793834a2e9SVinod Koul 2080c752d491SKrzysztof Kozlowski tcsr_mutex: hwlock@1f40000 { 2081c752d491SKrzysztof Kozlowski compatible = "qcom,tcsr-mutex"; 208286d7c946SKrzysztof Kozlowski reg = <0x0 0x01f40000 0x0 0x20000>; 2083c752d491SKrzysztof Kozlowski #hwlock-cells = <1>; 208486d7c946SKrzysztof Kozlowski }; 208586d7c946SKrzysztof Kozlowski 2086d0909bf4SJohan Hovold tcsr_regs_1: syscon@1f60000 { 208786d7c946SKrzysztof Kozlowski compatible = "qcom,sm8150-tcsr", "syscon"; 208886d7c946SKrzysztof Kozlowski reg = <0x0 0x01f60000 0x0 0x20000>; 2089d8cf9372SVinod Koul }; 2090d8cf9372SVinod Koul 209149076351SSibi Sankar remoteproc_slpi: remoteproc@2400000 { 209249076351SSibi Sankar compatible = "qcom,sm8150-slpi-pas"; 209349076351SSibi Sankar reg = <0x0 0x02400000 0x0 0x4040>; 209449076351SSibi Sankar 209549076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 209649076351SSibi Sankar <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 209749076351SSibi Sankar <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 209849076351SSibi Sankar <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 209949076351SSibi Sankar <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 210049076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 210149076351SSibi Sankar "handover", "stop-ack"; 210249076351SSibi Sankar 210349076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 210449076351SSibi Sankar clock-names = "xo"; 210549076351SSibi Sankar 2106a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_LCX>, 2107a94ed9f3SKonrad Dybcio <&rpmhpd SM8150_LMX>; 2108d9d327f6SSibi Sankar power-domain-names = "lcx", "lmx"; 210949076351SSibi Sankar 211049076351SSibi Sankar memory-region = <&slpi_mem>; 211149076351SSibi Sankar 2112d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 2113d9d327f6SSibi Sankar 211449076351SSibi Sankar qcom,smem-states = <&slpi_smp2p_out 0>; 211549076351SSibi Sankar qcom,smem-state-names = "stop"; 211649076351SSibi Sankar 211749076351SSibi Sankar status = "disabled"; 211849076351SSibi Sankar 211949076351SSibi Sankar glink-edge { 212049076351SSibi Sankar interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 212149076351SSibi Sankar label = "dsps"; 212249076351SSibi Sankar qcom,remote-pid = <3>; 212349076351SSibi Sankar mboxes = <&apss_shared 24>; 212481729330SBhupesh Sharma 212581729330SBhupesh Sharma fastrpc { 212681729330SBhupesh Sharma compatible = "qcom,fastrpc"; 212781729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 212881729330SBhupesh Sharma label = "sdsp"; 21298c8ce95bSJeya R qcom,non-secure-domain; 213081729330SBhupesh Sharma #address-cells = <1>; 213181729330SBhupesh Sharma #size-cells = <0>; 213281729330SBhupesh Sharma 213381729330SBhupesh Sharma compute-cb@1 { 213481729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 213581729330SBhupesh Sharma reg = <1>; 213681729330SBhupesh Sharma iommus = <&apps_smmu 0x05a1 0x0>; 213781729330SBhupesh Sharma }; 213881729330SBhupesh Sharma 213981729330SBhupesh Sharma compute-cb@2 { 214081729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 214181729330SBhupesh Sharma reg = <2>; 214281729330SBhupesh Sharma iommus = <&apps_smmu 0x05a2 0x0>; 214381729330SBhupesh Sharma }; 214481729330SBhupesh Sharma 214581729330SBhupesh Sharma compute-cb@3 { 214681729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 214781729330SBhupesh Sharma reg = <3>; 214881729330SBhupesh Sharma iommus = <&apps_smmu 0x05a3 0x0>; 214981729330SBhupesh Sharma /* note: shared-cb = <4> in downstream */ 215081729330SBhupesh Sharma }; 215181729330SBhupesh Sharma }; 215249076351SSibi Sankar }; 215349076351SSibi Sankar }; 215449076351SSibi Sankar 2155f30ac26dSJonathan Marek gpu: gpu@2c00000 { 2156*1642ab96SKonrad Dybcio compatible = "qcom,adreno-640.1", "qcom,adreno"; 2157f30ac26dSJonathan Marek reg = <0 0x02c00000 0 0x40000>; 2158f30ac26dSJonathan Marek reg-names = "kgsl_3d0_reg_memory"; 2159f30ac26dSJonathan Marek 2160f30ac26dSJonathan Marek interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2161f30ac26dSJonathan Marek 2162f30ac26dSJonathan Marek iommus = <&adreno_smmu 0 0x401>; 2163f30ac26dSJonathan Marek 2164f30ac26dSJonathan Marek operating-points-v2 = <&gpu_opp_table>; 2165f30ac26dSJonathan Marek 2166f30ac26dSJonathan Marek qcom,gmu = <&gmu>; 2167f30ac26dSJonathan Marek 2168b1dc3c6bSKonrad Dybcio status = "disabled"; 2169b1dc3c6bSKonrad Dybcio 2170f30ac26dSJonathan Marek zap-shader { 2171f30ac26dSJonathan Marek memory-region = <&gpu_mem>; 2172f30ac26dSJonathan Marek }; 2173f30ac26dSJonathan Marek 2174f30ac26dSJonathan Marek /* note: downstream checks gpu binning for 675 Mhz */ 2175f30ac26dSJonathan Marek gpu_opp_table: opp-table { 2176f30ac26dSJonathan Marek compatible = "operating-points-v2"; 2177f30ac26dSJonathan Marek 2178f30ac26dSJonathan Marek opp-675000000 { 2179f30ac26dSJonathan Marek opp-hz = /bits/ 64 <675000000>; 2180f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2181f30ac26dSJonathan Marek }; 2182f30ac26dSJonathan Marek 2183f30ac26dSJonathan Marek opp-585000000 { 2184f30ac26dSJonathan Marek opp-hz = /bits/ 64 <585000000>; 2185f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2186f30ac26dSJonathan Marek }; 2187f30ac26dSJonathan Marek 2188f30ac26dSJonathan Marek opp-499200000 { 2189f30ac26dSJonathan Marek opp-hz = /bits/ 64 <499200000>; 2190f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2191f30ac26dSJonathan Marek }; 2192f30ac26dSJonathan Marek 2193f30ac26dSJonathan Marek opp-427000000 { 2194f30ac26dSJonathan Marek opp-hz = /bits/ 64 <427000000>; 2195f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2196f30ac26dSJonathan Marek }; 2197f30ac26dSJonathan Marek 2198f30ac26dSJonathan Marek opp-345000000 { 2199f30ac26dSJonathan Marek opp-hz = /bits/ 64 <345000000>; 2200f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2201f30ac26dSJonathan Marek }; 2202f30ac26dSJonathan Marek 2203f30ac26dSJonathan Marek opp-257000000 { 2204f30ac26dSJonathan Marek opp-hz = /bits/ 64 <257000000>; 2205f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2206f30ac26dSJonathan Marek }; 2207f30ac26dSJonathan Marek }; 2208f30ac26dSJonathan Marek }; 2209f30ac26dSJonathan Marek 2210f30ac26dSJonathan Marek gmu: gmu@2c6a000 { 2211f30ac26dSJonathan Marek compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2212f30ac26dSJonathan Marek 2213f30ac26dSJonathan Marek reg = <0 0x02c6a000 0 0x30000>, 2214f30ac26dSJonathan Marek <0 0x0b290000 0 0x10000>, 2215f30ac26dSJonathan Marek <0 0x0b490000 0 0x10000>; 2216f30ac26dSJonathan Marek reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2217f30ac26dSJonathan Marek 2218f30ac26dSJonathan Marek interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2219f30ac26dSJonathan Marek <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2220f30ac26dSJonathan Marek interrupt-names = "hfi", "gmu"; 2221f30ac26dSJonathan Marek 2222f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 2223f1269916SJonathan Marek <&gpucc GPU_CC_CX_GMU_CLK>, 2224f1269916SJonathan Marek <&gpucc GPU_CC_CXO_CLK>, 2225f30ac26dSJonathan Marek <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2226f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2227f30ac26dSJonathan Marek clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2228f30ac26dSJonathan Marek 2229f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>, 2230f1269916SJonathan Marek <&gpucc GPU_GX_GDSC>; 2231f30ac26dSJonathan Marek power-domain-names = "cx", "gx"; 2232f30ac26dSJonathan Marek 2233f30ac26dSJonathan Marek iommus = <&adreno_smmu 5 0x400>; 2234f30ac26dSJonathan Marek 2235f30ac26dSJonathan Marek operating-points-v2 = <&gmu_opp_table>; 2236f30ac26dSJonathan Marek 2237b1dc3c6bSKonrad Dybcio status = "disabled"; 2238b1dc3c6bSKonrad Dybcio 2239f30ac26dSJonathan Marek gmu_opp_table: opp-table { 2240f30ac26dSJonathan Marek compatible = "operating-points-v2"; 2241f30ac26dSJonathan Marek 2242f30ac26dSJonathan Marek opp-200000000 { 2243f30ac26dSJonathan Marek opp-hz = /bits/ 64 <200000000>; 2244f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2245f30ac26dSJonathan Marek }; 2246f30ac26dSJonathan Marek }; 2247f30ac26dSJonathan Marek }; 2248f30ac26dSJonathan Marek 2249f30ac26dSJonathan Marek gpucc: clock-controller@2c90000 { 2250f30ac26dSJonathan Marek compatible = "qcom,sm8150-gpucc"; 2251f30ac26dSJonathan Marek reg = <0 0x02c90000 0 0x9000>; 2252f30ac26dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>, 2253f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2254f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2255f30ac26dSJonathan Marek clock-names = "bi_tcxo", 2256f30ac26dSJonathan Marek "gcc_gpu_gpll0_clk_src", 2257f30ac26dSJonathan Marek "gcc_gpu_gpll0_div_clk_src"; 2258f30ac26dSJonathan Marek #clock-cells = <1>; 2259f30ac26dSJonathan Marek #reset-cells = <1>; 2260f30ac26dSJonathan Marek #power-domain-cells = <1>; 2261f30ac26dSJonathan Marek }; 2262f30ac26dSJonathan Marek 2263f30ac26dSJonathan Marek adreno_smmu: iommu@2ca0000 { 22643e5c0025SKonrad Dybcio compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", 22653e5c0025SKonrad Dybcio "qcom,smmu-500", "arm,mmu-500"; 2266f30ac26dSJonathan Marek reg = <0 0x02ca0000 0 0x10000>; 2267f30ac26dSJonathan Marek #iommu-cells = <2>; 2268f30ac26dSJonathan Marek #global-interrupts = <1>; 2269f30ac26dSJonathan Marek interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2270f30ac26dSJonathan Marek <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2271f30ac26dSJonathan Marek <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2272f30ac26dSJonathan Marek <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2273f30ac26dSJonathan Marek <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2274f30ac26dSJonathan Marek <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2275f30ac26dSJonathan Marek <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2276f30ac26dSJonathan Marek <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2277f30ac26dSJonathan Marek <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2278f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 2279f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2280f30ac26dSJonathan Marek <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2281f30ac26dSJonathan Marek clock-names = "ahb", "bus", "iface"; 2282f30ac26dSJonathan Marek 2283f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>; 2284f30ac26dSJonathan Marek }; 2285f30ac26dSJonathan Marek 2286e13c6d14SVinod Koul tlmm: pinctrl@3100000 { 2287e13c6d14SVinod Koul compatible = "qcom,sm8150-pinctrl"; 2288e13c6d14SVinod Koul reg = <0x0 0x03100000 0x0 0x300000>, 2289e13c6d14SVinod Koul <0x0 0x03500000 0x0 0x300000>, 2290e13c6d14SVinod Koul <0x0 0x03900000 0x0 0x300000>, 2291e13c6d14SVinod Koul <0x0 0x03D00000 0x0 0x300000>; 2292e13c6d14SVinod Koul reg-names = "west", "east", "north", "south"; 2293e13c6d14SVinod Koul interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2294de3abdf3SShawn Guo gpio-ranges = <&tlmm 0 0 176>; 2295e13c6d14SVinod Koul gpio-controller; 2296e13c6d14SVinod Koul #gpio-cells = <2>; 2297e13c6d14SVinod Koul interrupt-controller; 2298e13c6d14SVinod Koul #interrupt-cells = <2>; 22996127d8e4SBhupesh Sharma wakeup-parent = <&pdc>; 230081bee695SCaleb Connolly 2301028fe09cSKrzysztof Kozlowski qup_i2c0_default: qup-i2c0-default-state { 230281bee695SCaleb Connolly pins = "gpio0", "gpio1"; 230381bee695SCaleb Connolly function = "qup0"; 230481bee695SCaleb Connolly drive-strength = <0x02>; 230581bee695SCaleb Connolly bias-disable; 230681bee695SCaleb Connolly }; 230781bee695SCaleb Connolly 2308028fe09cSKrzysztof Kozlowski qup_spi0_default: qup-spi0-default-state { 2309129e1c96SFelipe Balbi pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2310129e1c96SFelipe Balbi function = "qup0"; 2311129e1c96SFelipe Balbi drive-strength = <6>; 2312129e1c96SFelipe Balbi bias-disable; 2313129e1c96SFelipe Balbi }; 2314129e1c96SFelipe Balbi 2315028fe09cSKrzysztof Kozlowski qup_i2c1_default: qup-i2c1-default-state { 231681bee695SCaleb Connolly pins = "gpio114", "gpio115"; 231781bee695SCaleb Connolly function = "qup1"; 2318028fe09cSKrzysztof Kozlowski drive-strength = <2>; 231981bee695SCaleb Connolly bias-disable; 232081bee695SCaleb Connolly }; 232181bee695SCaleb Connolly 2322028fe09cSKrzysztof Kozlowski qup_spi1_default: qup-spi1-default-state { 2323129e1c96SFelipe Balbi pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2324129e1c96SFelipe Balbi function = "qup1"; 2325129e1c96SFelipe Balbi drive-strength = <6>; 2326129e1c96SFelipe Balbi bias-disable; 2327129e1c96SFelipe Balbi }; 2328129e1c96SFelipe Balbi 2329028fe09cSKrzysztof Kozlowski qup_i2c2_default: qup-i2c2-default-state { 233081bee695SCaleb Connolly pins = "gpio126", "gpio127"; 233181bee695SCaleb Connolly function = "qup2"; 2332028fe09cSKrzysztof Kozlowski drive-strength = <2>; 233381bee695SCaleb Connolly bias-disable; 233481bee695SCaleb Connolly }; 233581bee695SCaleb Connolly 2336028fe09cSKrzysztof Kozlowski qup_spi2_default: qup-spi2-default-state { 2337129e1c96SFelipe Balbi pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2338129e1c96SFelipe Balbi function = "qup2"; 2339129e1c96SFelipe Balbi drive-strength = <6>; 2340129e1c96SFelipe Balbi bias-disable; 2341129e1c96SFelipe Balbi }; 2342129e1c96SFelipe Balbi 2343028fe09cSKrzysztof Kozlowski qup_i2c3_default: qup-i2c3-default-state { 234481bee695SCaleb Connolly pins = "gpio144", "gpio145"; 234581bee695SCaleb Connolly function = "qup3"; 2346028fe09cSKrzysztof Kozlowski drive-strength = <2>; 234781bee695SCaleb Connolly bias-disable; 234881bee695SCaleb Connolly }; 234981bee695SCaleb Connolly 2350028fe09cSKrzysztof Kozlowski qup_spi3_default: qup-spi3-default-state { 2351129e1c96SFelipe Balbi pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2352129e1c96SFelipe Balbi function = "qup3"; 2353129e1c96SFelipe Balbi drive-strength = <6>; 2354129e1c96SFelipe Balbi bias-disable; 2355129e1c96SFelipe Balbi }; 2356129e1c96SFelipe Balbi 2357028fe09cSKrzysztof Kozlowski qup_i2c4_default: qup-i2c4-default-state { 235881bee695SCaleb Connolly pins = "gpio51", "gpio52"; 235981bee695SCaleb Connolly function = "qup4"; 2360028fe09cSKrzysztof Kozlowski drive-strength = <2>; 236181bee695SCaleb Connolly bias-disable; 236281bee695SCaleb Connolly }; 236381bee695SCaleb Connolly 2364028fe09cSKrzysztof Kozlowski qup_spi4_default: qup-spi4-default-state { 2365129e1c96SFelipe Balbi pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2366129e1c96SFelipe Balbi function = "qup4"; 2367129e1c96SFelipe Balbi drive-strength = <6>; 2368129e1c96SFelipe Balbi bias-disable; 2369129e1c96SFelipe Balbi }; 2370129e1c96SFelipe Balbi 2371028fe09cSKrzysztof Kozlowski qup_i2c5_default: qup-i2c5-default-state { 237281bee695SCaleb Connolly pins = "gpio121", "gpio122"; 237381bee695SCaleb Connolly function = "qup5"; 2374028fe09cSKrzysztof Kozlowski drive-strength = <2>; 237581bee695SCaleb Connolly bias-disable; 237681bee695SCaleb Connolly }; 237781bee695SCaleb Connolly 2378028fe09cSKrzysztof Kozlowski qup_spi5_default: qup-spi5-default-state { 2379129e1c96SFelipe Balbi pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2380129e1c96SFelipe Balbi function = "qup5"; 2381129e1c96SFelipe Balbi drive-strength = <6>; 2382129e1c96SFelipe Balbi bias-disable; 2383129e1c96SFelipe Balbi }; 2384129e1c96SFelipe Balbi 2385028fe09cSKrzysztof Kozlowski qup_i2c6_default: qup-i2c6-default-state { 238681bee695SCaleb Connolly pins = "gpio6", "gpio7"; 238781bee695SCaleb Connolly function = "qup6"; 2388028fe09cSKrzysztof Kozlowski drive-strength = <2>; 238981bee695SCaleb Connolly bias-disable; 239081bee695SCaleb Connolly }; 239181bee695SCaleb Connolly 2392028fe09cSKrzysztof Kozlowski qup_spi6_default: qup-spi6_default-state { 2393129e1c96SFelipe Balbi pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2394129e1c96SFelipe Balbi function = "qup6"; 2395129e1c96SFelipe Balbi drive-strength = <6>; 2396129e1c96SFelipe Balbi bias-disable; 2397129e1c96SFelipe Balbi }; 2398129e1c96SFelipe Balbi 2399028fe09cSKrzysztof Kozlowski qup_i2c7_default: qup-i2c7-default-state { 240081bee695SCaleb Connolly pins = "gpio98", "gpio99"; 240181bee695SCaleb Connolly function = "qup7"; 2402028fe09cSKrzysztof Kozlowski drive-strength = <2>; 240381bee695SCaleb Connolly bias-disable; 240481bee695SCaleb Connolly }; 240581bee695SCaleb Connolly 2406028fe09cSKrzysztof Kozlowski qup_spi7_default: qup-spi7_default-state { 2407129e1c96SFelipe Balbi pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2408129e1c96SFelipe Balbi function = "qup7"; 2409129e1c96SFelipe Balbi drive-strength = <6>; 2410129e1c96SFelipe Balbi bias-disable; 2411129e1c96SFelipe Balbi }; 2412129e1c96SFelipe Balbi 2413028fe09cSKrzysztof Kozlowski qup_i2c8_default: qup-i2c8-default-state { 241481bee695SCaleb Connolly pins = "gpio88", "gpio89"; 241581bee695SCaleb Connolly function = "qup8"; 2416028fe09cSKrzysztof Kozlowski drive-strength = <2>; 241781bee695SCaleb Connolly bias-disable; 241881bee695SCaleb Connolly }; 241981bee695SCaleb Connolly 2420028fe09cSKrzysztof Kozlowski qup_spi8_default: qup-spi8-default-state { 2421129e1c96SFelipe Balbi pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2422129e1c96SFelipe Balbi function = "qup8"; 2423129e1c96SFelipe Balbi drive-strength = <6>; 2424129e1c96SFelipe Balbi bias-disable; 2425129e1c96SFelipe Balbi }; 2426129e1c96SFelipe Balbi 2427028fe09cSKrzysztof Kozlowski qup_i2c9_default: qup-i2c9-default-state { 242881bee695SCaleb Connolly pins = "gpio39", "gpio40"; 242981bee695SCaleb Connolly function = "qup9"; 2430028fe09cSKrzysztof Kozlowski drive-strength = <2>; 243181bee695SCaleb Connolly bias-disable; 243281bee695SCaleb Connolly }; 243381bee695SCaleb Connolly 2434028fe09cSKrzysztof Kozlowski qup_spi9_default: qup-spi9-default-state { 2435129e1c96SFelipe Balbi pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2436129e1c96SFelipe Balbi function = "qup9"; 2437129e1c96SFelipe Balbi drive-strength = <6>; 2438129e1c96SFelipe Balbi bias-disable; 2439129e1c96SFelipe Balbi }; 2440129e1c96SFelipe Balbi 244110d900a8SBartosz Golaszewski qup_uart9_default: qup-uart9-default-state { 244210d900a8SBartosz Golaszewski pins = "gpio41", "gpio42"; 244310d900a8SBartosz Golaszewski function = "qup9"; 244410d900a8SBartosz Golaszewski drive-strength = <2>; 244510d900a8SBartosz Golaszewski bias-disable; 244610d900a8SBartosz Golaszewski }; 244710d900a8SBartosz Golaszewski 2448028fe09cSKrzysztof Kozlowski qup_i2c10_default: qup-i2c10-default-state { 244981bee695SCaleb Connolly pins = "gpio9", "gpio10"; 245081bee695SCaleb Connolly function = "qup10"; 2451028fe09cSKrzysztof Kozlowski drive-strength = <2>; 245281bee695SCaleb Connolly bias-disable; 245381bee695SCaleb Connolly }; 245481bee695SCaleb Connolly 2455028fe09cSKrzysztof Kozlowski qup_spi10_default: qup-spi10-default-state { 2456129e1c96SFelipe Balbi pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2457129e1c96SFelipe Balbi function = "qup10"; 2458129e1c96SFelipe Balbi drive-strength = <6>; 2459129e1c96SFelipe Balbi bias-disable; 2460129e1c96SFelipe Balbi }; 2461129e1c96SFelipe Balbi 2462028fe09cSKrzysztof Kozlowski qup_i2c11_default: qup-i2c11-default-state { 246381bee695SCaleb Connolly pins = "gpio94", "gpio95"; 246481bee695SCaleb Connolly function = "qup11"; 2465028fe09cSKrzysztof Kozlowski drive-strength = <2>; 246681bee695SCaleb Connolly bias-disable; 246781bee695SCaleb Connolly }; 246881bee695SCaleb Connolly 2469028fe09cSKrzysztof Kozlowski qup_spi11_default: qup-spi11-default-state { 2470129e1c96SFelipe Balbi pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2471129e1c96SFelipe Balbi function = "qup11"; 2472129e1c96SFelipe Balbi drive-strength = <6>; 2473129e1c96SFelipe Balbi bias-disable; 2474129e1c96SFelipe Balbi }; 2475129e1c96SFelipe Balbi 2476028fe09cSKrzysztof Kozlowski qup_i2c12_default: qup-i2c12-default-state { 247781bee695SCaleb Connolly pins = "gpio83", "gpio84"; 247881bee695SCaleb Connolly function = "qup12"; 2479028fe09cSKrzysztof Kozlowski drive-strength = <2>; 248081bee695SCaleb Connolly bias-disable; 248181bee695SCaleb Connolly }; 248281bee695SCaleb Connolly 2483028fe09cSKrzysztof Kozlowski qup_spi12_default: qup-spi12-default-state { 2484129e1c96SFelipe Balbi pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2485129e1c96SFelipe Balbi function = "qup12"; 2486129e1c96SFelipe Balbi drive-strength = <6>; 2487129e1c96SFelipe Balbi bias-disable; 2488129e1c96SFelipe Balbi }; 2489129e1c96SFelipe Balbi 2490028fe09cSKrzysztof Kozlowski qup_i2c13_default: qup-i2c13-default-state { 249181bee695SCaleb Connolly pins = "gpio43", "gpio44"; 249281bee695SCaleb Connolly function = "qup13"; 2493028fe09cSKrzysztof Kozlowski drive-strength = <2>; 249481bee695SCaleb Connolly bias-disable; 249581bee695SCaleb Connolly }; 249681bee695SCaleb Connolly 2497028fe09cSKrzysztof Kozlowski qup_spi13_default: qup-spi13-default-state { 2498129e1c96SFelipe Balbi pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2499129e1c96SFelipe Balbi function = "qup13"; 2500129e1c96SFelipe Balbi drive-strength = <6>; 2501129e1c96SFelipe Balbi bias-disable; 2502129e1c96SFelipe Balbi }; 2503129e1c96SFelipe Balbi 2504028fe09cSKrzysztof Kozlowski qup_i2c14_default: qup-i2c14-default-state { 250581bee695SCaleb Connolly pins = "gpio47", "gpio48"; 250681bee695SCaleb Connolly function = "qup14"; 2507028fe09cSKrzysztof Kozlowski drive-strength = <2>; 250881bee695SCaleb Connolly bias-disable; 250981bee695SCaleb Connolly }; 251081bee695SCaleb Connolly 2511028fe09cSKrzysztof Kozlowski qup_spi14_default: qup-spi14-default-state { 2512129e1c96SFelipe Balbi pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2513129e1c96SFelipe Balbi function = "qup14"; 2514129e1c96SFelipe Balbi drive-strength = <6>; 2515129e1c96SFelipe Balbi bias-disable; 2516129e1c96SFelipe Balbi }; 2517129e1c96SFelipe Balbi 2518028fe09cSKrzysztof Kozlowski qup_i2c15_default: qup-i2c15-default-state { 251981bee695SCaleb Connolly pins = "gpio27", "gpio28"; 252081bee695SCaleb Connolly function = "qup15"; 2521028fe09cSKrzysztof Kozlowski drive-strength = <2>; 252281bee695SCaleb Connolly bias-disable; 252381bee695SCaleb Connolly }; 252481bee695SCaleb Connolly 2525028fe09cSKrzysztof Kozlowski qup_spi15_default: qup-spi15-default-state { 2526129e1c96SFelipe Balbi pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2527129e1c96SFelipe Balbi function = "qup15"; 2528129e1c96SFelipe Balbi drive-strength = <6>; 2529129e1c96SFelipe Balbi bias-disable; 2530129e1c96SFelipe Balbi }; 2531129e1c96SFelipe Balbi 2532028fe09cSKrzysztof Kozlowski qup_i2c16_default: qup-i2c16-default-state { 253381bee695SCaleb Connolly pins = "gpio86", "gpio85"; 253481bee695SCaleb Connolly function = "qup16"; 2535028fe09cSKrzysztof Kozlowski drive-strength = <2>; 253681bee695SCaleb Connolly bias-disable; 253781bee695SCaleb Connolly }; 253881bee695SCaleb Connolly 2539028fe09cSKrzysztof Kozlowski qup_spi16_default: qup-spi16-default-state { 2540129e1c96SFelipe Balbi pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2541129e1c96SFelipe Balbi function = "qup16"; 2542129e1c96SFelipe Balbi drive-strength = <6>; 2543129e1c96SFelipe Balbi bias-disable; 2544129e1c96SFelipe Balbi }; 2545129e1c96SFelipe Balbi 2546028fe09cSKrzysztof Kozlowski qup_i2c17_default: qup-i2c17-default-state { 254781bee695SCaleb Connolly pins = "gpio55", "gpio56"; 254881bee695SCaleb Connolly function = "qup17"; 2549028fe09cSKrzysztof Kozlowski drive-strength = <2>; 255081bee695SCaleb Connolly bias-disable; 255181bee695SCaleb Connolly }; 255281bee695SCaleb Connolly 2553028fe09cSKrzysztof Kozlowski qup_spi17_default: qup-spi17-default-state { 2554129e1c96SFelipe Balbi pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2555129e1c96SFelipe Balbi function = "qup17"; 2556129e1c96SFelipe Balbi drive-strength = <6>; 2557129e1c96SFelipe Balbi bias-disable; 2558129e1c96SFelipe Balbi }; 2559129e1c96SFelipe Balbi 2560028fe09cSKrzysztof Kozlowski qup_i2c18_default: qup-i2c18-default-state { 256181bee695SCaleb Connolly pins = "gpio23", "gpio24"; 256281bee695SCaleb Connolly function = "qup18"; 2563028fe09cSKrzysztof Kozlowski drive-strength = <2>; 256481bee695SCaleb Connolly bias-disable; 256581bee695SCaleb Connolly }; 256681bee695SCaleb Connolly 2567028fe09cSKrzysztof Kozlowski qup_spi18_default: qup-spi18-default-state { 2568129e1c96SFelipe Balbi pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2569129e1c96SFelipe Balbi function = "qup18"; 2570129e1c96SFelipe Balbi drive-strength = <6>; 2571129e1c96SFelipe Balbi bias-disable; 2572129e1c96SFelipe Balbi }; 2573129e1c96SFelipe Balbi 2574028fe09cSKrzysztof Kozlowski qup_i2c19_default: qup-i2c19-default-state { 257581bee695SCaleb Connolly pins = "gpio57", "gpio58"; 257681bee695SCaleb Connolly function = "qup19"; 2577028fe09cSKrzysztof Kozlowski drive-strength = <2>; 257881bee695SCaleb Connolly bias-disable; 257981bee695SCaleb Connolly }; 2580129e1c96SFelipe Balbi 2581028fe09cSKrzysztof Kozlowski qup_spi19_default: qup-spi19-default-state { 2582129e1c96SFelipe Balbi pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2583129e1c96SFelipe Balbi function = "qup19"; 2584129e1c96SFelipe Balbi drive-strength = <6>; 2585129e1c96SFelipe Balbi bias-disable; 2586129e1c96SFelipe Balbi }; 2587a1c86c68SBhupesh Sharma 2588028fe09cSKrzysztof Kozlowski pcie0_default_state: pcie0-default-state { 2589028fe09cSKrzysztof Kozlowski perst-pins { 2590a1c86c68SBhupesh Sharma pins = "gpio35"; 2591a1c86c68SBhupesh Sharma function = "gpio"; 2592a1c86c68SBhupesh Sharma drive-strength = <2>; 2593a1c86c68SBhupesh Sharma bias-pull-down; 2594a1c86c68SBhupesh Sharma }; 2595a1c86c68SBhupesh Sharma 2596028fe09cSKrzysztof Kozlowski clkreq-pins { 2597a1c86c68SBhupesh Sharma pins = "gpio36"; 2598a1c86c68SBhupesh Sharma function = "pci_e0"; 2599a1c86c68SBhupesh Sharma drive-strength = <2>; 2600a1c86c68SBhupesh Sharma bias-pull-up; 2601a1c86c68SBhupesh Sharma }; 2602a1c86c68SBhupesh Sharma 2603028fe09cSKrzysztof Kozlowski wake-pins { 2604a1c86c68SBhupesh Sharma pins = "gpio37"; 2605a1c86c68SBhupesh Sharma function = "gpio"; 2606a1c86c68SBhupesh Sharma drive-strength = <2>; 2607a1c86c68SBhupesh Sharma bias-pull-up; 2608a1c86c68SBhupesh Sharma }; 2609a1c86c68SBhupesh Sharma }; 2610a1c86c68SBhupesh Sharma 2611028fe09cSKrzysztof Kozlowski pcie1_default_state: pcie1-default-state { 2612028fe09cSKrzysztof Kozlowski perst-pins { 2613a1c86c68SBhupesh Sharma pins = "gpio102"; 2614a1c86c68SBhupesh Sharma function = "gpio"; 2615a1c86c68SBhupesh Sharma drive-strength = <2>; 2616a1c86c68SBhupesh Sharma bias-pull-down; 2617a1c86c68SBhupesh Sharma }; 2618a1c86c68SBhupesh Sharma 2619028fe09cSKrzysztof Kozlowski clkreq-pins { 2620a1c86c68SBhupesh Sharma pins = "gpio103"; 2621a1c86c68SBhupesh Sharma function = "pci_e1"; 2622a1c86c68SBhupesh Sharma drive-strength = <2>; 2623a1c86c68SBhupesh Sharma bias-pull-up; 2624a1c86c68SBhupesh Sharma }; 2625a1c86c68SBhupesh Sharma 2626028fe09cSKrzysztof Kozlowski wake-pins { 2627a1c86c68SBhupesh Sharma pins = "gpio104"; 2628a1c86c68SBhupesh Sharma function = "gpio"; 2629a1c86c68SBhupesh Sharma drive-strength = <2>; 2630a1c86c68SBhupesh Sharma bias-pull-up; 2631a1c86c68SBhupesh Sharma }; 2632a1c86c68SBhupesh Sharma }; 2633e13c6d14SVinod Koul }; 2634e13c6d14SVinod Koul 263549076351SSibi Sankar remoteproc_mpss: remoteproc@4080000 { 263649076351SSibi Sankar compatible = "qcom,sm8150-mpss-pas"; 263749076351SSibi Sankar reg = <0x0 0x04080000 0x0 0x4040>; 263849076351SSibi Sankar 263949076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 264049076351SSibi Sankar <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 264149076351SSibi Sankar <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 264249076351SSibi Sankar <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 264349076351SSibi Sankar <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 264449076351SSibi Sankar <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 264549076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", "handover", 264649076351SSibi Sankar "stop-ack", "shutdown-ack"; 264749076351SSibi Sankar 264849076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 264949076351SSibi Sankar clock-names = "xo"; 265049076351SSibi Sankar 2651a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_CX>, 2652a94ed9f3SKonrad Dybcio <&rpmhpd SM8150_MSS>; 2653d9d327f6SSibi Sankar power-domain-names = "cx", "mss"; 265449076351SSibi Sankar 265549076351SSibi Sankar memory-region = <&mpss_mem>; 265649076351SSibi Sankar 2657d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 2658d9d327f6SSibi Sankar 265949076351SSibi Sankar qcom,smem-states = <&modem_smp2p_out 0>; 266049076351SSibi Sankar qcom,smem-state-names = "stop"; 266149076351SSibi Sankar 2662b1dc3c6bSKonrad Dybcio status = "disabled"; 2663b1dc3c6bSKonrad Dybcio 266449076351SSibi Sankar glink-edge { 266549076351SSibi Sankar interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 266649076351SSibi Sankar label = "modem"; 266749076351SSibi Sankar qcom,remote-pid = <1>; 266849076351SSibi Sankar mboxes = <&apss_shared 12>; 266949076351SSibi Sankar }; 267049076351SSibi Sankar }; 267149076351SSibi Sankar 267224244cefSSai Prakash Ranjan stm@6002000 { 267324244cefSSai Prakash Ranjan compatible = "arm,coresight-stm", "arm,primecell"; 267424244cefSSai Prakash Ranjan reg = <0 0x06002000 0 0x1000>, 267524244cefSSai Prakash Ranjan <0 0x16280000 0 0x180000>; 267624244cefSSai Prakash Ranjan reg-names = "stm-base", "stm-stimulus-base"; 267724244cefSSai Prakash Ranjan 267824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 267924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 268024244cefSSai Prakash Ranjan 268124244cefSSai Prakash Ranjan out-ports { 268224244cefSSai Prakash Ranjan port { 268324244cefSSai Prakash Ranjan stm_out: endpoint { 268424244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_in7>; 268524244cefSSai Prakash Ranjan }; 268624244cefSSai Prakash Ranjan }; 268724244cefSSai Prakash Ranjan }; 268824244cefSSai Prakash Ranjan }; 268924244cefSSai Prakash Ranjan 269024244cefSSai Prakash Ranjan funnel@6041000 { 269124244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 269224244cefSSai Prakash Ranjan reg = <0 0x06041000 0 0x1000>; 269324244cefSSai Prakash Ranjan 269424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 269524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 269624244cefSSai Prakash Ranjan 269724244cefSSai Prakash Ranjan out-ports { 269824244cefSSai Prakash Ranjan port { 269924244cefSSai Prakash Ranjan funnel0_out: endpoint { 270024244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in0>; 270124244cefSSai Prakash Ranjan }; 270224244cefSSai Prakash Ranjan }; 270324244cefSSai Prakash Ranjan }; 270424244cefSSai Prakash Ranjan 270524244cefSSai Prakash Ranjan in-ports { 270624244cefSSai Prakash Ranjan #address-cells = <1>; 270724244cefSSai Prakash Ranjan #size-cells = <0>; 270824244cefSSai Prakash Ranjan 270924244cefSSai Prakash Ranjan port@7 { 271024244cefSSai Prakash Ranjan reg = <7>; 271124244cefSSai Prakash Ranjan funnel0_in7: endpoint { 271224244cefSSai Prakash Ranjan remote-endpoint = <&stm_out>; 271324244cefSSai Prakash Ranjan }; 271424244cefSSai Prakash Ranjan }; 271524244cefSSai Prakash Ranjan }; 271624244cefSSai Prakash Ranjan }; 271724244cefSSai Prakash Ranjan 271824244cefSSai Prakash Ranjan funnel@6042000 { 271924244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 272024244cefSSai Prakash Ranjan reg = <0 0x06042000 0 0x1000>; 272124244cefSSai Prakash Ranjan 272224244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 272324244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 272424244cefSSai Prakash Ranjan 272524244cefSSai Prakash Ranjan out-ports { 272624244cefSSai Prakash Ranjan port { 272724244cefSSai Prakash Ranjan funnel1_out: endpoint { 272824244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in1>; 272924244cefSSai Prakash Ranjan }; 273024244cefSSai Prakash Ranjan }; 273124244cefSSai Prakash Ranjan }; 273224244cefSSai Prakash Ranjan 273324244cefSSai Prakash Ranjan in-ports { 273424244cefSSai Prakash Ranjan #address-cells = <1>; 273524244cefSSai Prakash Ranjan #size-cells = <0>; 273624244cefSSai Prakash Ranjan 273724244cefSSai Prakash Ranjan port@4 { 273824244cefSSai Prakash Ranjan reg = <4>; 273924244cefSSai Prakash Ranjan funnel1_in4: endpoint { 274024244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_out>; 274124244cefSSai Prakash Ranjan }; 274224244cefSSai Prakash Ranjan }; 274324244cefSSai Prakash Ranjan }; 274424244cefSSai Prakash Ranjan }; 274524244cefSSai Prakash Ranjan 274624244cefSSai Prakash Ranjan funnel@6043000 { 274724244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 274824244cefSSai Prakash Ranjan reg = <0 0x06043000 0 0x1000>; 274924244cefSSai Prakash Ranjan 275024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 275124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 275224244cefSSai Prakash Ranjan 275324244cefSSai Prakash Ranjan out-ports { 275424244cefSSai Prakash Ranjan port { 275524244cefSSai Prakash Ranjan funnel2_out: endpoint { 275624244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in2>; 275724244cefSSai Prakash Ranjan }; 275824244cefSSai Prakash Ranjan }; 275924244cefSSai Prakash Ranjan }; 276024244cefSSai Prakash Ranjan 276124244cefSSai Prakash Ranjan in-ports { 276224244cefSSai Prakash Ranjan #address-cells = <1>; 276324244cefSSai Prakash Ranjan #size-cells = <0>; 276424244cefSSai Prakash Ranjan 276524244cefSSai Prakash Ranjan port@2 { 276624244cefSSai Prakash Ranjan reg = <2>; 276724244cefSSai Prakash Ranjan funnel2_in2: endpoint { 276824244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_out>; 276924244cefSSai Prakash Ranjan }; 277024244cefSSai Prakash Ranjan }; 277124244cefSSai Prakash Ranjan }; 277224244cefSSai Prakash Ranjan }; 277324244cefSSai Prakash Ranjan 277424244cefSSai Prakash Ranjan funnel@6045000 { 277524244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 277624244cefSSai Prakash Ranjan reg = <0 0x06045000 0 0x1000>; 277724244cefSSai Prakash Ranjan 277824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 277924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 278024244cefSSai Prakash Ranjan 278124244cefSSai Prakash Ranjan out-ports { 278224244cefSSai Prakash Ranjan port { 278324244cefSSai Prakash Ranjan merge_funnel_out: endpoint { 278424244cefSSai Prakash Ranjan remote-endpoint = <&etf_in>; 278524244cefSSai Prakash Ranjan }; 278624244cefSSai Prakash Ranjan }; 278724244cefSSai Prakash Ranjan }; 278824244cefSSai Prakash Ranjan 278924244cefSSai Prakash Ranjan in-ports { 279024244cefSSai Prakash Ranjan #address-cells = <1>; 279124244cefSSai Prakash Ranjan #size-cells = <0>; 279224244cefSSai Prakash Ranjan 279324244cefSSai Prakash Ranjan port@0 { 279424244cefSSai Prakash Ranjan reg = <0>; 279524244cefSSai Prakash Ranjan merge_funnel_in0: endpoint { 279624244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_out>; 279724244cefSSai Prakash Ranjan }; 279824244cefSSai Prakash Ranjan }; 279924244cefSSai Prakash Ranjan 280024244cefSSai Prakash Ranjan port@1 { 280124244cefSSai Prakash Ranjan reg = <1>; 280224244cefSSai Prakash Ranjan merge_funnel_in1: endpoint { 280324244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_out>; 280424244cefSSai Prakash Ranjan }; 280524244cefSSai Prakash Ranjan }; 280624244cefSSai Prakash Ranjan 280724244cefSSai Prakash Ranjan port@2 { 280824244cefSSai Prakash Ranjan reg = <2>; 280924244cefSSai Prakash Ranjan merge_funnel_in2: endpoint { 281024244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_out>; 281124244cefSSai Prakash Ranjan }; 281224244cefSSai Prakash Ranjan }; 281324244cefSSai Prakash Ranjan }; 281424244cefSSai Prakash Ranjan }; 281524244cefSSai Prakash Ranjan 281624244cefSSai Prakash Ranjan replicator@6046000 { 281724244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 281824244cefSSai Prakash Ranjan reg = <0 0x06046000 0 0x1000>; 281924244cefSSai Prakash Ranjan 282024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 282124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 282224244cefSSai Prakash Ranjan 282324244cefSSai Prakash Ranjan out-ports { 282424244cefSSai Prakash Ranjan #address-cells = <1>; 282524244cefSSai Prakash Ranjan #size-cells = <0>; 282624244cefSSai Prakash Ranjan 282724244cefSSai Prakash Ranjan port@0 { 282824244cefSSai Prakash Ranjan reg = <0>; 282924244cefSSai Prakash Ranjan replicator_out0: endpoint { 283024244cefSSai Prakash Ranjan remote-endpoint = <&etr_in>; 283124244cefSSai Prakash Ranjan }; 283224244cefSSai Prakash Ranjan }; 283324244cefSSai Prakash Ranjan 283424244cefSSai Prakash Ranjan port@1 { 283524244cefSSai Prakash Ranjan reg = <1>; 283624244cefSSai Prakash Ranjan replicator_out1: endpoint { 283724244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_in>; 283824244cefSSai Prakash Ranjan }; 283924244cefSSai Prakash Ranjan }; 284024244cefSSai Prakash Ranjan }; 284124244cefSSai Prakash Ranjan 284224244cefSSai Prakash Ranjan in-ports { 284324244cefSSai Prakash Ranjan port { 284424244cefSSai Prakash Ranjan replicator_in0: endpoint { 284524244cefSSai Prakash Ranjan remote-endpoint = <&etf_out>; 284624244cefSSai Prakash Ranjan }; 284724244cefSSai Prakash Ranjan }; 284824244cefSSai Prakash Ranjan }; 284924244cefSSai Prakash Ranjan }; 285024244cefSSai Prakash Ranjan 285124244cefSSai Prakash Ranjan etf@6047000 { 285224244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 285324244cefSSai Prakash Ranjan reg = <0 0x06047000 0 0x1000>; 285424244cefSSai Prakash Ranjan 285524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 285624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 285724244cefSSai Prakash Ranjan 285824244cefSSai Prakash Ranjan out-ports { 285924244cefSSai Prakash Ranjan port { 286024244cefSSai Prakash Ranjan etf_out: endpoint { 286124244cefSSai Prakash Ranjan remote-endpoint = <&replicator_in0>; 286224244cefSSai Prakash Ranjan }; 286324244cefSSai Prakash Ranjan }; 286424244cefSSai Prakash Ranjan }; 286524244cefSSai Prakash Ranjan 286624244cefSSai Prakash Ranjan in-ports { 286724244cefSSai Prakash Ranjan port { 286824244cefSSai Prakash Ranjan etf_in: endpoint { 286924244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_out>; 287024244cefSSai Prakash Ranjan }; 287124244cefSSai Prakash Ranjan }; 287224244cefSSai Prakash Ranjan }; 287324244cefSSai Prakash Ranjan }; 287424244cefSSai Prakash Ranjan 287524244cefSSai Prakash Ranjan etr@6048000 { 287624244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 287724244cefSSai Prakash Ranjan reg = <0 0x06048000 0 0x1000>; 287824244cefSSai Prakash Ranjan iommus = <&apps_smmu 0x05e0 0x0>; 287924244cefSSai Prakash Ranjan 288024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 288124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 288224244cefSSai Prakash Ranjan arm,scatter-gather; 288324244cefSSai Prakash Ranjan 288424244cefSSai Prakash Ranjan in-ports { 288524244cefSSai Prakash Ranjan port { 288624244cefSSai Prakash Ranjan etr_in: endpoint { 288724244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out0>; 288824244cefSSai Prakash Ranjan }; 288924244cefSSai Prakash Ranjan }; 289024244cefSSai Prakash Ranjan }; 289124244cefSSai Prakash Ranjan }; 289224244cefSSai Prakash Ranjan 289324244cefSSai Prakash Ranjan replicator@604a000 { 289424244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 289524244cefSSai Prakash Ranjan reg = <0 0x0604a000 0 0x1000>; 289624244cefSSai Prakash Ranjan 289724244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 289824244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 289924244cefSSai Prakash Ranjan 290024244cefSSai Prakash Ranjan out-ports { 290124244cefSSai Prakash Ranjan #address-cells = <1>; 290224244cefSSai Prakash Ranjan #size-cells = <0>; 290324244cefSSai Prakash Ranjan 290424244cefSSai Prakash Ranjan port@1 { 290524244cefSSai Prakash Ranjan reg = <1>; 290624244cefSSai Prakash Ranjan replicator1_out: endpoint { 290724244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_in>; 290824244cefSSai Prakash Ranjan }; 290924244cefSSai Prakash Ranjan }; 291024244cefSSai Prakash Ranjan }; 291124244cefSSai Prakash Ranjan 291224244cefSSai Prakash Ranjan in-ports { 291324244cefSSai Prakash Ranjan #address-cells = <1>; 291424244cefSSai Prakash Ranjan #size-cells = <0>; 291524244cefSSai Prakash Ranjan 291624244cefSSai Prakash Ranjan port@1 { 291724244cefSSai Prakash Ranjan reg = <1>; 291824244cefSSai Prakash Ranjan replicator1_in: endpoint { 291924244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out1>; 292024244cefSSai Prakash Ranjan }; 292124244cefSSai Prakash Ranjan }; 292224244cefSSai Prakash Ranjan }; 292324244cefSSai Prakash Ranjan }; 292424244cefSSai Prakash Ranjan 292524244cefSSai Prakash Ranjan funnel@6b08000 { 292624244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 292724244cefSSai Prakash Ranjan reg = <0 0x06b08000 0 0x1000>; 292824244cefSSai Prakash Ranjan 292924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 293024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 293124244cefSSai Prakash Ranjan 293224244cefSSai Prakash Ranjan out-ports { 293324244cefSSai Prakash Ranjan port { 293424244cefSSai Prakash Ranjan swao_funnel_out: endpoint { 293524244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_in>; 293624244cefSSai Prakash Ranjan }; 293724244cefSSai Prakash Ranjan }; 293824244cefSSai Prakash Ranjan }; 293924244cefSSai Prakash Ranjan 294024244cefSSai Prakash Ranjan in-ports { 294124244cefSSai Prakash Ranjan #address-cells = <1>; 294224244cefSSai Prakash Ranjan #size-cells = <0>; 294324244cefSSai Prakash Ranjan 294424244cefSSai Prakash Ranjan port@6 { 294524244cefSSai Prakash Ranjan reg = <6>; 294624244cefSSai Prakash Ranjan swao_funnel_in: endpoint { 294724244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_out>; 294824244cefSSai Prakash Ranjan }; 294924244cefSSai Prakash Ranjan }; 295024244cefSSai Prakash Ranjan }; 295124244cefSSai Prakash Ranjan }; 295224244cefSSai Prakash Ranjan 295324244cefSSai Prakash Ranjan etf@6b09000 { 295424244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 295524244cefSSai Prakash Ranjan reg = <0 0x06b09000 0 0x1000>; 295624244cefSSai Prakash Ranjan 295724244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 295824244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 295924244cefSSai Prakash Ranjan 296024244cefSSai Prakash Ranjan out-ports { 296124244cefSSai Prakash Ranjan port { 296224244cefSSai Prakash Ranjan swao_etf_out: endpoint { 296324244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_in>; 296424244cefSSai Prakash Ranjan }; 296524244cefSSai Prakash Ranjan }; 296624244cefSSai Prakash Ranjan }; 296724244cefSSai Prakash Ranjan 296824244cefSSai Prakash Ranjan in-ports { 296924244cefSSai Prakash Ranjan port { 297024244cefSSai Prakash Ranjan swao_etf_in: endpoint { 297124244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_out>; 297224244cefSSai Prakash Ranjan }; 297324244cefSSai Prakash Ranjan }; 297424244cefSSai Prakash Ranjan }; 297524244cefSSai Prakash Ranjan }; 297624244cefSSai Prakash Ranjan 297724244cefSSai Prakash Ranjan replicator@6b0a000 { 297824244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 297924244cefSSai Prakash Ranjan reg = <0 0x06b0a000 0 0x1000>; 298024244cefSSai Prakash Ranjan 298124244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 298224244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 298324244cefSSai Prakash Ranjan qcom,replicator-loses-context; 298424244cefSSai Prakash Ranjan 298524244cefSSai Prakash Ranjan out-ports { 298624244cefSSai Prakash Ranjan port { 298724244cefSSai Prakash Ranjan swao_replicator_out: endpoint { 298824244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_in4>; 298924244cefSSai Prakash Ranjan }; 299024244cefSSai Prakash Ranjan }; 299124244cefSSai Prakash Ranjan }; 299224244cefSSai Prakash Ranjan 299324244cefSSai Prakash Ranjan in-ports { 299424244cefSSai Prakash Ranjan port { 299524244cefSSai Prakash Ranjan swao_replicator_in: endpoint { 299624244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_out>; 299724244cefSSai Prakash Ranjan }; 299824244cefSSai Prakash Ranjan }; 299924244cefSSai Prakash Ranjan }; 300024244cefSSai Prakash Ranjan }; 300124244cefSSai Prakash Ranjan 300224244cefSSai Prakash Ranjan etm@7040000 { 300324244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 300424244cefSSai Prakash Ranjan reg = <0 0x07040000 0 0x1000>; 300524244cefSSai Prakash Ranjan 300624244cefSSai Prakash Ranjan cpu = <&CPU0>; 300724244cefSSai Prakash Ranjan 300824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 300924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 301024244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 301124244cefSSai Prakash Ranjan qcom,skip-power-up; 301224244cefSSai Prakash Ranjan 301324244cefSSai Prakash Ranjan out-ports { 301424244cefSSai Prakash Ranjan port { 301524244cefSSai Prakash Ranjan etm0_out: endpoint { 301624244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in0>; 301724244cefSSai Prakash Ranjan }; 301824244cefSSai Prakash Ranjan }; 301924244cefSSai Prakash Ranjan }; 302024244cefSSai Prakash Ranjan }; 302124244cefSSai Prakash Ranjan 302224244cefSSai Prakash Ranjan etm@7140000 { 302324244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 302424244cefSSai Prakash Ranjan reg = <0 0x07140000 0 0x1000>; 302524244cefSSai Prakash Ranjan 302624244cefSSai Prakash Ranjan cpu = <&CPU1>; 302724244cefSSai Prakash Ranjan 302824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 302924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 303024244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 303124244cefSSai Prakash Ranjan qcom,skip-power-up; 303224244cefSSai Prakash Ranjan 303324244cefSSai Prakash Ranjan out-ports { 303424244cefSSai Prakash Ranjan port { 303524244cefSSai Prakash Ranjan etm1_out: endpoint { 303624244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in1>; 303724244cefSSai Prakash Ranjan }; 303824244cefSSai Prakash Ranjan }; 303924244cefSSai Prakash Ranjan }; 304024244cefSSai Prakash Ranjan }; 304124244cefSSai Prakash Ranjan 304224244cefSSai Prakash Ranjan etm@7240000 { 304324244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 304424244cefSSai Prakash Ranjan reg = <0 0x07240000 0 0x1000>; 304524244cefSSai Prakash Ranjan 304624244cefSSai Prakash Ranjan cpu = <&CPU2>; 304724244cefSSai Prakash Ranjan 304824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 304924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 305024244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 305124244cefSSai Prakash Ranjan qcom,skip-power-up; 305224244cefSSai Prakash Ranjan 305324244cefSSai Prakash Ranjan out-ports { 305424244cefSSai Prakash Ranjan port { 305524244cefSSai Prakash Ranjan etm2_out: endpoint { 305624244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in2>; 305724244cefSSai Prakash Ranjan }; 305824244cefSSai Prakash Ranjan }; 305924244cefSSai Prakash Ranjan }; 306024244cefSSai Prakash Ranjan }; 306124244cefSSai Prakash Ranjan 306224244cefSSai Prakash Ranjan etm@7340000 { 306324244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 306424244cefSSai Prakash Ranjan reg = <0 0x07340000 0 0x1000>; 306524244cefSSai Prakash Ranjan 306624244cefSSai Prakash Ranjan cpu = <&CPU3>; 306724244cefSSai Prakash Ranjan 306824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 306924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 307024244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 307124244cefSSai Prakash Ranjan qcom,skip-power-up; 307224244cefSSai Prakash Ranjan 307324244cefSSai Prakash Ranjan out-ports { 307424244cefSSai Prakash Ranjan port { 307524244cefSSai Prakash Ranjan etm3_out: endpoint { 307624244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in3>; 307724244cefSSai Prakash Ranjan }; 307824244cefSSai Prakash Ranjan }; 307924244cefSSai Prakash Ranjan }; 308024244cefSSai Prakash Ranjan }; 308124244cefSSai Prakash Ranjan 308224244cefSSai Prakash Ranjan etm@7440000 { 308324244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 308424244cefSSai Prakash Ranjan reg = <0 0x07440000 0 0x1000>; 308524244cefSSai Prakash Ranjan 308624244cefSSai Prakash Ranjan cpu = <&CPU4>; 308724244cefSSai Prakash Ranjan 308824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 308924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 309024244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 309124244cefSSai Prakash Ranjan qcom,skip-power-up; 309224244cefSSai Prakash Ranjan 309324244cefSSai Prakash Ranjan out-ports { 309424244cefSSai Prakash Ranjan port { 309524244cefSSai Prakash Ranjan etm4_out: endpoint { 309624244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in4>; 309724244cefSSai Prakash Ranjan }; 309824244cefSSai Prakash Ranjan }; 309924244cefSSai Prakash Ranjan }; 310024244cefSSai Prakash Ranjan }; 310124244cefSSai Prakash Ranjan 310224244cefSSai Prakash Ranjan etm@7540000 { 310324244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 310424244cefSSai Prakash Ranjan reg = <0 0x07540000 0 0x1000>; 310524244cefSSai Prakash Ranjan 310624244cefSSai Prakash Ranjan cpu = <&CPU5>; 310724244cefSSai Prakash Ranjan 310824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 310924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 311024244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 311124244cefSSai Prakash Ranjan qcom,skip-power-up; 311224244cefSSai Prakash Ranjan 311324244cefSSai Prakash Ranjan out-ports { 311424244cefSSai Prakash Ranjan port { 311524244cefSSai Prakash Ranjan etm5_out: endpoint { 311624244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in5>; 311724244cefSSai Prakash Ranjan }; 311824244cefSSai Prakash Ranjan }; 311924244cefSSai Prakash Ranjan }; 312024244cefSSai Prakash Ranjan }; 312124244cefSSai Prakash Ranjan 312224244cefSSai Prakash Ranjan etm@7640000 { 312324244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 312424244cefSSai Prakash Ranjan reg = <0 0x07640000 0 0x1000>; 312524244cefSSai Prakash Ranjan 312624244cefSSai Prakash Ranjan cpu = <&CPU6>; 312724244cefSSai Prakash Ranjan 312824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 312924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 313024244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 313124244cefSSai Prakash Ranjan qcom,skip-power-up; 313224244cefSSai Prakash Ranjan 313324244cefSSai Prakash Ranjan out-ports { 313424244cefSSai Prakash Ranjan port { 313524244cefSSai Prakash Ranjan etm6_out: endpoint { 313624244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in6>; 313724244cefSSai Prakash Ranjan }; 313824244cefSSai Prakash Ranjan }; 313924244cefSSai Prakash Ranjan }; 314024244cefSSai Prakash Ranjan }; 314124244cefSSai Prakash Ranjan 314224244cefSSai Prakash Ranjan etm@7740000 { 314324244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 314424244cefSSai Prakash Ranjan reg = <0 0x07740000 0 0x1000>; 314524244cefSSai Prakash Ranjan 314624244cefSSai Prakash Ranjan cpu = <&CPU7>; 314724244cefSSai Prakash Ranjan 314824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 314924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 315024244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 315124244cefSSai Prakash Ranjan qcom,skip-power-up; 315224244cefSSai Prakash Ranjan 315324244cefSSai Prakash Ranjan out-ports { 315424244cefSSai Prakash Ranjan port { 315524244cefSSai Prakash Ranjan etm7_out: endpoint { 315624244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in7>; 315724244cefSSai Prakash Ranjan }; 315824244cefSSai Prakash Ranjan }; 315924244cefSSai Prakash Ranjan }; 316024244cefSSai Prakash Ranjan }; 316124244cefSSai Prakash Ranjan 316224244cefSSai Prakash Ranjan funnel@7800000 { /* APSS Funnel */ 316324244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 316424244cefSSai Prakash Ranjan reg = <0 0x07800000 0 0x1000>; 316524244cefSSai Prakash Ranjan 316624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 316724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 316824244cefSSai Prakash Ranjan 316924244cefSSai Prakash Ranjan out-ports { 317024244cefSSai Prakash Ranjan port { 317124244cefSSai Prakash Ranjan apss_funnel_out: endpoint { 317224244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_in>; 317324244cefSSai Prakash Ranjan }; 317424244cefSSai Prakash Ranjan }; 317524244cefSSai Prakash Ranjan }; 317624244cefSSai Prakash Ranjan 317724244cefSSai Prakash Ranjan in-ports { 317824244cefSSai Prakash Ranjan #address-cells = <1>; 317924244cefSSai Prakash Ranjan #size-cells = <0>; 318024244cefSSai Prakash Ranjan 318124244cefSSai Prakash Ranjan port@0 { 318224244cefSSai Prakash Ranjan reg = <0>; 318324244cefSSai Prakash Ranjan apss_funnel_in0: endpoint { 318424244cefSSai Prakash Ranjan remote-endpoint = <&etm0_out>; 318524244cefSSai Prakash Ranjan }; 318624244cefSSai Prakash Ranjan }; 318724244cefSSai Prakash Ranjan 318824244cefSSai Prakash Ranjan port@1 { 318924244cefSSai Prakash Ranjan reg = <1>; 319024244cefSSai Prakash Ranjan apss_funnel_in1: endpoint { 319124244cefSSai Prakash Ranjan remote-endpoint = <&etm1_out>; 319224244cefSSai Prakash Ranjan }; 319324244cefSSai Prakash Ranjan }; 319424244cefSSai Prakash Ranjan 319524244cefSSai Prakash Ranjan port@2 { 319624244cefSSai Prakash Ranjan reg = <2>; 319724244cefSSai Prakash Ranjan apss_funnel_in2: endpoint { 319824244cefSSai Prakash Ranjan remote-endpoint = <&etm2_out>; 319924244cefSSai Prakash Ranjan }; 320024244cefSSai Prakash Ranjan }; 320124244cefSSai Prakash Ranjan 320224244cefSSai Prakash Ranjan port@3 { 320324244cefSSai Prakash Ranjan reg = <3>; 320424244cefSSai Prakash Ranjan apss_funnel_in3: endpoint { 320524244cefSSai Prakash Ranjan remote-endpoint = <&etm3_out>; 320624244cefSSai Prakash Ranjan }; 320724244cefSSai Prakash Ranjan }; 320824244cefSSai Prakash Ranjan 320924244cefSSai Prakash Ranjan port@4 { 321024244cefSSai Prakash Ranjan reg = <4>; 321124244cefSSai Prakash Ranjan apss_funnel_in4: endpoint { 321224244cefSSai Prakash Ranjan remote-endpoint = <&etm4_out>; 321324244cefSSai Prakash Ranjan }; 321424244cefSSai Prakash Ranjan }; 321524244cefSSai Prakash Ranjan 321624244cefSSai Prakash Ranjan port@5 { 321724244cefSSai Prakash Ranjan reg = <5>; 321824244cefSSai Prakash Ranjan apss_funnel_in5: endpoint { 321924244cefSSai Prakash Ranjan remote-endpoint = <&etm5_out>; 322024244cefSSai Prakash Ranjan }; 322124244cefSSai Prakash Ranjan }; 322224244cefSSai Prakash Ranjan 322324244cefSSai Prakash Ranjan port@6 { 322424244cefSSai Prakash Ranjan reg = <6>; 322524244cefSSai Prakash Ranjan apss_funnel_in6: endpoint { 322624244cefSSai Prakash Ranjan remote-endpoint = <&etm6_out>; 322724244cefSSai Prakash Ranjan }; 322824244cefSSai Prakash Ranjan }; 322924244cefSSai Prakash Ranjan 323024244cefSSai Prakash Ranjan port@7 { 323124244cefSSai Prakash Ranjan reg = <7>; 323224244cefSSai Prakash Ranjan apss_funnel_in7: endpoint { 323324244cefSSai Prakash Ranjan remote-endpoint = <&etm7_out>; 323424244cefSSai Prakash Ranjan }; 323524244cefSSai Prakash Ranjan }; 323624244cefSSai Prakash Ranjan }; 323724244cefSSai Prakash Ranjan }; 323824244cefSSai Prakash Ranjan 323924244cefSSai Prakash Ranjan funnel@7810000 { 324024244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 324124244cefSSai Prakash Ranjan reg = <0 0x07810000 0 0x1000>; 324224244cefSSai Prakash Ranjan 324324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 324424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 324524244cefSSai Prakash Ranjan 324624244cefSSai Prakash Ranjan out-ports { 324724244cefSSai Prakash Ranjan port { 324824244cefSSai Prakash Ranjan apss_merge_funnel_out: endpoint { 324924244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_in2>; 325024244cefSSai Prakash Ranjan }; 325124244cefSSai Prakash Ranjan }; 325224244cefSSai Prakash Ranjan }; 325324244cefSSai Prakash Ranjan 325424244cefSSai Prakash Ranjan in-ports { 325524244cefSSai Prakash Ranjan port { 325624244cefSSai Prakash Ranjan apss_merge_funnel_in: endpoint { 325724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_out>; 325824244cefSSai Prakash Ranjan }; 325924244cefSSai Prakash Ranjan }; 326024244cefSSai Prakash Ranjan }; 326124244cefSSai Prakash Ranjan }; 326224244cefSSai Prakash Ranjan 326349076351SSibi Sankar remoteproc_cdsp: remoteproc@8300000 { 326449076351SSibi Sankar compatible = "qcom,sm8150-cdsp-pas"; 326549076351SSibi Sankar reg = <0x0 0x08300000 0x0 0x4040>; 326649076351SSibi Sankar 326749076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 326849076351SSibi Sankar <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 326949076351SSibi Sankar <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 327049076351SSibi Sankar <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 327149076351SSibi Sankar <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 327249076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 327349076351SSibi Sankar "handover", "stop-ack"; 327449076351SSibi Sankar 327549076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 327649076351SSibi Sankar clock-names = "xo"; 327749076351SSibi Sankar 3278a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_CX>; 327949076351SSibi Sankar 328049076351SSibi Sankar memory-region = <&cdsp_mem>; 328149076351SSibi Sankar 3282d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 3283d9d327f6SSibi Sankar 328449076351SSibi Sankar qcom,smem-states = <&cdsp_smp2p_out 0>; 328549076351SSibi Sankar qcom,smem-state-names = "stop"; 328649076351SSibi Sankar 328749076351SSibi Sankar status = "disabled"; 328849076351SSibi Sankar 328949076351SSibi Sankar glink-edge { 329049076351SSibi Sankar interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 329149076351SSibi Sankar label = "cdsp"; 329249076351SSibi Sankar qcom,remote-pid = <5>; 329349076351SSibi Sankar mboxes = <&apss_shared 4>; 329481729330SBhupesh Sharma 329581729330SBhupesh Sharma fastrpc { 329681729330SBhupesh Sharma compatible = "qcom,fastrpc"; 329781729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 329881729330SBhupesh Sharma label = "cdsp"; 32998c8ce95bSJeya R qcom,non-secure-domain; 330081729330SBhupesh Sharma #address-cells = <1>; 330181729330SBhupesh Sharma #size-cells = <0>; 330281729330SBhupesh Sharma 330381729330SBhupesh Sharma compute-cb@1 { 330481729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 330581729330SBhupesh Sharma reg = <1>; 33061d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1001 0x0460>; 330781729330SBhupesh Sharma }; 330881729330SBhupesh Sharma 330981729330SBhupesh Sharma compute-cb@2 { 331081729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 331181729330SBhupesh Sharma reg = <2>; 33121d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1002 0x0460>; 331381729330SBhupesh Sharma }; 331481729330SBhupesh Sharma 331581729330SBhupesh Sharma compute-cb@3 { 331681729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 331781729330SBhupesh Sharma reg = <3>; 33181d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1003 0x0460>; 331981729330SBhupesh Sharma }; 332081729330SBhupesh Sharma 332181729330SBhupesh Sharma compute-cb@4 { 332281729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 332381729330SBhupesh Sharma reg = <4>; 33241d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1004 0x0460>; 332581729330SBhupesh Sharma }; 332681729330SBhupesh Sharma 332781729330SBhupesh Sharma compute-cb@5 { 332881729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 332981729330SBhupesh Sharma reg = <5>; 33301d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1005 0x0460>; 333181729330SBhupesh Sharma }; 333281729330SBhupesh Sharma 333381729330SBhupesh Sharma compute-cb@6 { 333481729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 333581729330SBhupesh Sharma reg = <6>; 33361d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1006 0x0460>; 333781729330SBhupesh Sharma }; 333881729330SBhupesh Sharma 333981729330SBhupesh Sharma compute-cb@7 { 334081729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 334181729330SBhupesh Sharma reg = <7>; 33421d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1007 0x0460>; 334381729330SBhupesh Sharma }; 334481729330SBhupesh Sharma 334581729330SBhupesh Sharma compute-cb@8 { 334681729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 334781729330SBhupesh Sharma reg = <8>; 33481d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1008 0x0460>; 334981729330SBhupesh Sharma }; 335081729330SBhupesh Sharma 335181729330SBhupesh Sharma /* note: secure cb9 in downstream */ 335281729330SBhupesh Sharma }; 335349076351SSibi Sankar }; 335449076351SSibi Sankar }; 335549076351SSibi Sankar 3356b33d2868SJack Pham usb_1_hsphy: phy@88e2000 { 3357b33d2868SJack Pham compatible = "qcom,sm8150-usb-hs-phy", 3358b33d2868SJack Pham "qcom,usb-snps-hs-7nm-phy"; 3359b33d2868SJack Pham reg = <0 0x088e2000 0 0x400>; 3360b33d2868SJack Pham status = "disabled"; 3361b33d2868SJack Pham #phy-cells = <0>; 3362b33d2868SJack Pham 3363b33d2868SJack Pham clocks = <&rpmhcc RPMH_CXO_CLK>; 3364b33d2868SJack Pham clock-names = "ref"; 3365b33d2868SJack Pham 3366b33d2868SJack Pham resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3367b33d2868SJack Pham }; 3368b33d2868SJack Pham 33690c9dde0dSJonathan Marek usb_2_hsphy: phy@88e3000 { 33700c9dde0dSJonathan Marek compatible = "qcom,sm8150-usb-hs-phy", 33710c9dde0dSJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 33720c9dde0dSJonathan Marek reg = <0 0x088e3000 0 0x400>; 33730c9dde0dSJonathan Marek status = "disabled"; 33740c9dde0dSJonathan Marek #phy-cells = <0>; 33750c9dde0dSJonathan Marek 33760c9dde0dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 33770c9dde0dSJonathan Marek clock-names = "ref"; 33780c9dde0dSJonathan Marek 33790c9dde0dSJonathan Marek resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 33800c9dde0dSJonathan Marek }; 33810c9dde0dSJonathan Marek 3382b33d2868SJack Pham usb_1_qmpphy: phy@88e9000 { 3383b33d2868SJack Pham compatible = "qcom,sm8150-qmp-usb3-phy"; 3384b33d2868SJack Pham reg = <0 0x088e9000 0 0x18c>, 3385b33d2868SJack Pham <0 0x088e8000 0 0x10>; 3386b33d2868SJack Pham status = "disabled"; 3387b33d2868SJack Pham #address-cells = <2>; 3388b33d2868SJack Pham #size-cells = <2>; 3389b33d2868SJack Pham ranges; 3390b33d2868SJack Pham 3391b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3392b33d2868SJack Pham <&rpmhcc RPMH_CXO_CLK>, 3393b33d2868SJack Pham <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3394b33d2868SJack Pham <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3395b33d2868SJack Pham clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3396b33d2868SJack Pham 3397b33d2868SJack Pham resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3398b33d2868SJack Pham <&gcc GCC_USB3_PHY_PRIM_BCR>; 3399b33d2868SJack Pham reset-names = "phy", "common"; 3400b33d2868SJack Pham 34011351512fSShawn Guo usb_1_ssphy: phy@88e9200 { 3402b33d2868SJack Pham reg = <0 0x088e9200 0 0x200>, 3403b33d2868SJack Pham <0 0x088e9400 0 0x200>, 3404b33d2868SJack Pham <0 0x088e9c00 0 0x218>, 3405b33d2868SJack Pham <0 0x088e9600 0 0x200>, 3406b33d2868SJack Pham <0 0x088e9800 0 0x200>, 3407b33d2868SJack Pham <0 0x088e9a00 0 0x100>; 34087178d4ccSJonathan Marek #clock-cells = <0>; 3409b33d2868SJack Pham #phy-cells = <0>; 3410b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3411b33d2868SJack Pham clock-names = "pipe0"; 3412b33d2868SJack Pham clock-output-names = "usb3_phy_pipe_clk_src"; 3413b33d2868SJack Pham }; 3414b33d2868SJack Pham }; 3415b33d2868SJack Pham 34160c9dde0dSJonathan Marek usb_2_qmpphy: phy@88eb000 { 34170c9dde0dSJonathan Marek compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 34180c9dde0dSJonathan Marek reg = <0 0x088eb000 0 0x200>; 34190c9dde0dSJonathan Marek status = "disabled"; 34200c9dde0dSJonathan Marek #address-cells = <2>; 34210c9dde0dSJonathan Marek #size-cells = <2>; 34220c9dde0dSJonathan Marek ranges; 34230c9dde0dSJonathan Marek 34240c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 34250c9dde0dSJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 34260c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>, 34270c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 34280c9dde0dSJonathan Marek clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 34290c9dde0dSJonathan Marek 34300c9dde0dSJonathan Marek resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 34310c9dde0dSJonathan Marek <&gcc GCC_USB3_PHY_SEC_BCR>; 34320c9dde0dSJonathan Marek reset-names = "phy", "common"; 34330c9dde0dSJonathan Marek 34341351512fSShawn Guo usb_2_ssphy: phy@88eb200 { 34350c9dde0dSJonathan Marek reg = <0 0x088eb200 0 0x200>, 34360c9dde0dSJonathan Marek <0 0x088eb400 0 0x200>, 34370c9dde0dSJonathan Marek <0 0x088eb800 0 0x800>, 34380c9dde0dSJonathan Marek <0 0x088eb600 0 0x200>; 34397178d4ccSJonathan Marek #clock-cells = <0>; 34400c9dde0dSJonathan Marek #phy-cells = <0>; 34410c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 34420c9dde0dSJonathan Marek clock-names = "pipe0"; 34430c9dde0dSJonathan Marek clock-output-names = "usb3_uni_phy_pipe_clk_src"; 34440c9dde0dSJonathan Marek }; 34450c9dde0dSJonathan Marek }; 34460c9dde0dSJonathan Marek 344796bb736fSBhupesh Sharma sdhc_2: mmc@8804000 { 3448876644c7SBhupesh Sharma compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3449876644c7SBhupesh Sharma reg = <0 0x08804000 0 0x1000>; 3450876644c7SBhupesh Sharma 3451876644c7SBhupesh Sharma interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3452876644c7SBhupesh Sharma <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3453876644c7SBhupesh Sharma interrupt-names = "hc_irq", "pwr_irq"; 3454876644c7SBhupesh Sharma 3455876644c7SBhupesh Sharma clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3456876644c7SBhupesh Sharma <&gcc GCC_SDCC2_APPS_CLK>, 3457876644c7SBhupesh Sharma <&rpmhcc RPMH_CXO_CLK>; 3458876644c7SBhupesh Sharma clock-names = "iface", "core", "xo"; 345995830090SBhupesh Sharma iommus = <&apps_smmu 0x6a0 0x0>; 3460876644c7SBhupesh Sharma qcom,dll-config = <0x0007642c>; 3461876644c7SBhupesh Sharma qcom,ddr-config = <0x80040868>; 3462876644c7SBhupesh Sharma power-domains = <&rpmhpd 0>; 3463876644c7SBhupesh Sharma operating-points-v2 = <&sdhc2_opp_table>; 3464876644c7SBhupesh Sharma 3465876644c7SBhupesh Sharma status = "disabled"; 3466876644c7SBhupesh Sharma 34670e3e6546SKrzysztof Kozlowski sdhc2_opp_table: opp-table { 3468876644c7SBhupesh Sharma compatible = "operating-points-v2"; 3469876644c7SBhupesh Sharma 3470876644c7SBhupesh Sharma opp-19200000 { 3471876644c7SBhupesh Sharma opp-hz = /bits/ 64 <19200000>; 3472876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_min_svs>; 3473876644c7SBhupesh Sharma }; 3474876644c7SBhupesh Sharma 3475876644c7SBhupesh Sharma opp-50000000 { 3476876644c7SBhupesh Sharma opp-hz = /bits/ 64 <50000000>; 3477876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_low_svs>; 3478876644c7SBhupesh Sharma }; 3479876644c7SBhupesh Sharma 3480876644c7SBhupesh Sharma opp-100000000 { 3481876644c7SBhupesh Sharma opp-hz = /bits/ 64 <100000000>; 3482876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_svs>; 3483876644c7SBhupesh Sharma }; 3484876644c7SBhupesh Sharma 3485876644c7SBhupesh Sharma opp-202000000 { 3486876644c7SBhupesh Sharma opp-hz = /bits/ 64 <202000000>; 3487876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_svs_l1>; 3488876644c7SBhupesh Sharma }; 3489876644c7SBhupesh Sharma }; 3490876644c7SBhupesh Sharma }; 3491876644c7SBhupesh Sharma 34925dc43d3bSBhupesh Sharma dc_noc: interconnect@9160000 { 34935dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-dc-noc"; 34945dc43d3bSBhupesh Sharma reg = <0 0x09160000 0 0x3200>; 34955dc43d3bSBhupesh Sharma #interconnect-cells = <1>; 34965dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 34975dc43d3bSBhupesh Sharma }; 34985dc43d3bSBhupesh Sharma 34995dc43d3bSBhupesh Sharma gem_noc: interconnect@9680000 { 35005dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-gem-noc"; 35015dc43d3bSBhupesh Sharma reg = <0 0x09680000 0 0x3e200>; 35025dc43d3bSBhupesh Sharma #interconnect-cells = <1>; 35035dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 35045dc43d3bSBhupesh Sharma }; 35055dc43d3bSBhupesh Sharma 3506b33d2868SJack Pham usb_1: usb@a6f8800 { 3507b33d2868SJack Pham compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3508b33d2868SJack Pham reg = <0 0x0a6f8800 0 0x400>; 3509b33d2868SJack Pham status = "disabled"; 3510b33d2868SJack Pham #address-cells = <2>; 3511b33d2868SJack Pham #size-cells = <2>; 3512b33d2868SJack Pham ranges; 3513b33d2868SJack Pham dma-ranges; 3514b33d2868SJack Pham 3515b33d2868SJack Pham clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3516b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3517b33d2868SJack Pham <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3518b33d2868SJack Pham <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 35198d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3520b33d2868SJack Pham <&gcc GCC_USB3_SEC_CLKREF_CLK>; 35218d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 35228d5fd4e4SKrzysztof Kozlowski "core", 35238d5fd4e4SKrzysztof Kozlowski "iface", 35248d5fd4e4SKrzysztof Kozlowski "sleep", 35258d5fd4e4SKrzysztof Kozlowski "mock_utmi", 35268d5fd4e4SKrzysztof Kozlowski "xo"; 3527b33d2868SJack Pham 3528b33d2868SJack Pham assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3529b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>; 353079493db5SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 3531b33d2868SJack Pham 3532b33d2868SJack Pham interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3533b33d2868SJack Pham <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3534b33d2868SJack Pham <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3535b33d2868SJack Pham <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3536b33d2868SJack Pham interrupt-names = "hs_phy_irq", "ss_phy_irq", 3537b33d2868SJack Pham "dm_hs_phy_irq", "dp_hs_phy_irq"; 3538b33d2868SJack Pham 3539b33d2868SJack Pham power-domains = <&gcc USB30_PRIM_GDSC>; 3540b33d2868SJack Pham 3541b33d2868SJack Pham resets = <&gcc GCC_USB30_PRIM_BCR>; 3542b33d2868SJack Pham 3543b77a1c4dSKrzysztof Kozlowski usb_1_dwc3: usb@a600000 { 3544b33d2868SJack Pham compatible = "snps,dwc3"; 3545b33d2868SJack Pham reg = <0 0x0a600000 0 0xcd00>; 3546b33d2868SJack Pham interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 354748156232SJonathan Marek iommus = <&apps_smmu 0x140 0>; 3548b33d2868SJack Pham snps,dis_u2_susphy_quirk; 3549b33d2868SJack Pham snps,dis_enblslpm_quirk; 3550b33d2868SJack Pham phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3551b33d2868SJack Pham phy-names = "usb2-phy", "usb3-phy"; 3552b33d2868SJack Pham }; 3553b33d2868SJack Pham }; 3554b33d2868SJack Pham 35550c9dde0dSJonathan Marek usb_2: usb@a8f8800 { 35560c9dde0dSJonathan Marek compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 35570c9dde0dSJonathan Marek reg = <0 0x0a8f8800 0 0x400>; 35580c9dde0dSJonathan Marek status = "disabled"; 35590c9dde0dSJonathan Marek #address-cells = <2>; 35600c9dde0dSJonathan Marek #size-cells = <2>; 35610c9dde0dSJonathan Marek ranges; 35620c9dde0dSJonathan Marek dma-ranges; 35630c9dde0dSJonathan Marek 35640c9dde0dSJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 35650c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>, 35660c9dde0dSJonathan Marek <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 35670c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_SLEEP_CLK>, 35688d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 35690c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>; 35708d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 35718d5fd4e4SKrzysztof Kozlowski "core", 35728d5fd4e4SKrzysztof Kozlowski "iface", 35738d5fd4e4SKrzysztof Kozlowski "sleep", 35748d5fd4e4SKrzysztof Kozlowski "mock_utmi", 35758d5fd4e4SKrzysztof Kozlowski "xo"; 35760c9dde0dSJonathan Marek 35770c9dde0dSJonathan Marek assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 35780c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>; 35790c9dde0dSJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 35800c9dde0dSJonathan Marek 35810c9dde0dSJonathan Marek interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 35820c9dde0dSJonathan Marek <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 35830c9dde0dSJonathan Marek <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 35840c9dde0dSJonathan Marek <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 35850c9dde0dSJonathan Marek interrupt-names = "hs_phy_irq", "ss_phy_irq", 35860c9dde0dSJonathan Marek "dm_hs_phy_irq", "dp_hs_phy_irq"; 35870c9dde0dSJonathan Marek 35880c9dde0dSJonathan Marek power-domains = <&gcc USB30_SEC_GDSC>; 35890c9dde0dSJonathan Marek 35900c9dde0dSJonathan Marek resets = <&gcc GCC_USB30_SEC_BCR>; 35910c9dde0dSJonathan Marek 35922aa2b50dSBhupesh Sharma usb_2_dwc3: usb@a800000 { 35930c9dde0dSJonathan Marek compatible = "snps,dwc3"; 35940c9dde0dSJonathan Marek reg = <0 0x0a800000 0 0xcd00>; 35950c9dde0dSJonathan Marek interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 35960c9dde0dSJonathan Marek iommus = <&apps_smmu 0x160 0>; 35970c9dde0dSJonathan Marek snps,dis_u2_susphy_quirk; 35980c9dde0dSJonathan Marek snps,dis_enblslpm_quirk; 35990c9dde0dSJonathan Marek phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 36000c9dde0dSJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 36010c9dde0dSJonathan Marek }; 36020c9dde0dSJonathan Marek }; 36030c9dde0dSJonathan Marek 36046acb71fdSJonathan Marek camnoc_virt: interconnect@ac00000 { 36056acb71fdSJonathan Marek compatible = "qcom,sm8150-camnoc-virt"; 36066acb71fdSJonathan Marek reg = <0 0x0ac00000 0 0x1000>; 36076acb71fdSJonathan Marek #interconnect-cells = <1>; 36086acb71fdSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 36096acb71fdSJonathan Marek }; 36106acb71fdSJonathan Marek 361198874a46SKonrad Dybcio mdss: display-subsystem@ae00000 { 361298874a46SKonrad Dybcio compatible = "qcom,sm8150-mdss"; 361398874a46SKonrad Dybcio reg = <0 0x0ae00000 0 0x1000>; 361498874a46SKonrad Dybcio reg-names = "mdss"; 361598874a46SKonrad Dybcio 361698874a46SKonrad Dybcio interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 361798874a46SKonrad Dybcio <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 361898874a46SKonrad Dybcio interconnect-names = "mdp0-mem", "mdp1-mem"; 361998874a46SKonrad Dybcio 362098874a46SKonrad Dybcio power-domains = <&dispcc MDSS_GDSC>; 362198874a46SKonrad Dybcio 362298874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 362398874a46SKonrad Dybcio <&gcc GCC_DISP_HF_AXI_CLK>, 362498874a46SKonrad Dybcio <&gcc GCC_DISP_SF_AXI_CLK>, 362598874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_MDP_CLK>; 362698874a46SKonrad Dybcio clock-names = "iface", "bus", "nrt_bus", "core"; 362798874a46SKonrad Dybcio 362898874a46SKonrad Dybcio interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 362998874a46SKonrad Dybcio interrupt-controller; 363098874a46SKonrad Dybcio #interrupt-cells = <1>; 363198874a46SKonrad Dybcio 363298874a46SKonrad Dybcio iommus = <&apps_smmu 0x800 0x420>; 363398874a46SKonrad Dybcio 363498874a46SKonrad Dybcio status = "disabled"; 363598874a46SKonrad Dybcio 363698874a46SKonrad Dybcio #address-cells = <2>; 363798874a46SKonrad Dybcio #size-cells = <2>; 363898874a46SKonrad Dybcio ranges; 363998874a46SKonrad Dybcio 364098874a46SKonrad Dybcio mdss_mdp: display-controller@ae01000 { 364198874a46SKonrad Dybcio compatible = "qcom,sm8150-dpu"; 364298874a46SKonrad Dybcio reg = <0 0x0ae01000 0 0x8f000>, 364398874a46SKonrad Dybcio <0 0x0aeb0000 0 0x2008>; 364498874a46SKonrad Dybcio reg-names = "mdp", "vbif"; 364598874a46SKonrad Dybcio 364698874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 364798874a46SKonrad Dybcio <&gcc GCC_DISP_HF_AXI_CLK>, 364898874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_MDP_CLK>, 364998874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 365098874a46SKonrad Dybcio clock-names = "iface", "bus", "core", "vsync"; 365198874a46SKonrad Dybcio 365298874a46SKonrad Dybcio assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 365398874a46SKonrad Dybcio assigned-clock-rates = <19200000>; 365498874a46SKonrad Dybcio 365598874a46SKonrad Dybcio operating-points-v2 = <&mdp_opp_table>; 365698874a46SKonrad Dybcio power-domains = <&rpmhpd SM8150_MMCX>; 365798874a46SKonrad Dybcio 365898874a46SKonrad Dybcio interrupt-parent = <&mdss>; 365998874a46SKonrad Dybcio interrupts = <0>; 366098874a46SKonrad Dybcio 366198874a46SKonrad Dybcio ports { 366298874a46SKonrad Dybcio #address-cells = <1>; 366398874a46SKonrad Dybcio #size-cells = <0>; 366498874a46SKonrad Dybcio 366598874a46SKonrad Dybcio port@0 { 366698874a46SKonrad Dybcio reg = <0>; 366798874a46SKonrad Dybcio dpu_intf1_out: endpoint { 366898874a46SKonrad Dybcio remote-endpoint = <&mdss_dsi0_in>; 366998874a46SKonrad Dybcio }; 367098874a46SKonrad Dybcio }; 367198874a46SKonrad Dybcio 367298874a46SKonrad Dybcio port@1 { 367398874a46SKonrad Dybcio reg = <1>; 367498874a46SKonrad Dybcio dpu_intf2_out: endpoint { 367598874a46SKonrad Dybcio remote-endpoint = <&mdss_dsi1_in>; 367698874a46SKonrad Dybcio }; 367798874a46SKonrad Dybcio }; 367898874a46SKonrad Dybcio }; 367998874a46SKonrad Dybcio 368098874a46SKonrad Dybcio mdp_opp_table: opp-table { 368198874a46SKonrad Dybcio compatible = "operating-points-v2"; 368298874a46SKonrad Dybcio 368398874a46SKonrad Dybcio opp-171428571 { 368498874a46SKonrad Dybcio opp-hz = /bits/ 64 <171428571>; 368598874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_low_svs>; 368698874a46SKonrad Dybcio }; 368798874a46SKonrad Dybcio 368898874a46SKonrad Dybcio opp-300000000 { 368998874a46SKonrad Dybcio opp-hz = /bits/ 64 <300000000>; 369098874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_svs>; 369198874a46SKonrad Dybcio }; 369298874a46SKonrad Dybcio 369398874a46SKonrad Dybcio opp-345000000 { 369498874a46SKonrad Dybcio opp-hz = /bits/ 64 <345000000>; 369598874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_svs_l1>; 369698874a46SKonrad Dybcio }; 369798874a46SKonrad Dybcio 369898874a46SKonrad Dybcio opp-460000000 { 369998874a46SKonrad Dybcio opp-hz = /bits/ 64 <460000000>; 370098874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_nom>; 370198874a46SKonrad Dybcio }; 370298874a46SKonrad Dybcio }; 370398874a46SKonrad Dybcio }; 370498874a46SKonrad Dybcio 370598874a46SKonrad Dybcio mdss_dsi0: dsi@ae94000 { 3706b0b8b34aSDmitry Baryshkov compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 370798874a46SKonrad Dybcio reg = <0 0x0ae94000 0 0x400>; 370898874a46SKonrad Dybcio reg-names = "dsi_ctrl"; 370998874a46SKonrad Dybcio 371098874a46SKonrad Dybcio interrupt-parent = <&mdss>; 371198874a46SKonrad Dybcio interrupts = <4>; 371298874a46SKonrad Dybcio 371398874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 371498874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 371598874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 371698874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_ESC0_CLK>, 371798874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_AHB_CLK>, 371898874a46SKonrad Dybcio <&gcc GCC_DISP_HF_AXI_CLK>; 371998874a46SKonrad Dybcio clock-names = "byte", 372098874a46SKonrad Dybcio "byte_intf", 372198874a46SKonrad Dybcio "pixel", 372298874a46SKonrad Dybcio "core", 372398874a46SKonrad Dybcio "iface", 372498874a46SKonrad Dybcio "bus"; 372598874a46SKonrad Dybcio 372698874a46SKonrad Dybcio assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 372798874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 372898874a46SKonrad Dybcio assigned-clock-parents = <&mdss_dsi0_phy 0>, 372998874a46SKonrad Dybcio <&mdss_dsi0_phy 1>; 373098874a46SKonrad Dybcio 373198874a46SKonrad Dybcio operating-points-v2 = <&dsi_opp_table>; 373298874a46SKonrad Dybcio power-domains = <&rpmhpd SM8150_MMCX>; 373398874a46SKonrad Dybcio 373498874a46SKonrad Dybcio phys = <&mdss_dsi0_phy>; 373598874a46SKonrad Dybcio 373698874a46SKonrad Dybcio status = "disabled"; 373798874a46SKonrad Dybcio 373898874a46SKonrad Dybcio #address-cells = <1>; 373998874a46SKonrad Dybcio #size-cells = <0>; 374098874a46SKonrad Dybcio 374198874a46SKonrad Dybcio ports { 374298874a46SKonrad Dybcio #address-cells = <1>; 374398874a46SKonrad Dybcio #size-cells = <0>; 374498874a46SKonrad Dybcio 374598874a46SKonrad Dybcio port@0 { 374698874a46SKonrad Dybcio reg = <0>; 374798874a46SKonrad Dybcio mdss_dsi0_in: endpoint { 374898874a46SKonrad Dybcio remote-endpoint = <&dpu_intf1_out>; 374998874a46SKonrad Dybcio }; 375098874a46SKonrad Dybcio }; 375198874a46SKonrad Dybcio 375298874a46SKonrad Dybcio port@1 { 375398874a46SKonrad Dybcio reg = <1>; 375498874a46SKonrad Dybcio mdss_dsi0_out: endpoint { 375598874a46SKonrad Dybcio }; 375698874a46SKonrad Dybcio }; 375798874a46SKonrad Dybcio }; 375898874a46SKonrad Dybcio 375998874a46SKonrad Dybcio dsi_opp_table: opp-table { 376098874a46SKonrad Dybcio compatible = "operating-points-v2"; 376198874a46SKonrad Dybcio 376298874a46SKonrad Dybcio opp-187500000 { 376398874a46SKonrad Dybcio opp-hz = /bits/ 64 <187500000>; 376498874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_low_svs>; 376598874a46SKonrad Dybcio }; 376698874a46SKonrad Dybcio 376798874a46SKonrad Dybcio opp-300000000 { 376898874a46SKonrad Dybcio opp-hz = /bits/ 64 <300000000>; 376998874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_svs>; 377098874a46SKonrad Dybcio }; 377198874a46SKonrad Dybcio 377298874a46SKonrad Dybcio opp-358000000 { 377398874a46SKonrad Dybcio opp-hz = /bits/ 64 <358000000>; 377498874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_svs_l1>; 377598874a46SKonrad Dybcio }; 377698874a46SKonrad Dybcio }; 377798874a46SKonrad Dybcio }; 377898874a46SKonrad Dybcio 377998874a46SKonrad Dybcio mdss_dsi0_phy: phy@ae94400 { 378098874a46SKonrad Dybcio compatible = "qcom,dsi-phy-7nm"; 378198874a46SKonrad Dybcio reg = <0 0x0ae94400 0 0x200>, 378298874a46SKonrad Dybcio <0 0x0ae94600 0 0x280>, 378398874a46SKonrad Dybcio <0 0x0ae94900 0 0x260>; 378498874a46SKonrad Dybcio reg-names = "dsi_phy", 378598874a46SKonrad Dybcio "dsi_phy_lane", 378698874a46SKonrad Dybcio "dsi_pll"; 378798874a46SKonrad Dybcio 378898874a46SKonrad Dybcio #clock-cells = <1>; 378998874a46SKonrad Dybcio #phy-cells = <0>; 379098874a46SKonrad Dybcio 379198874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 379298874a46SKonrad Dybcio <&rpmhcc RPMH_CXO_CLK>; 379398874a46SKonrad Dybcio clock-names = "iface", "ref"; 379498874a46SKonrad Dybcio 379598874a46SKonrad Dybcio status = "disabled"; 379698874a46SKonrad Dybcio }; 379798874a46SKonrad Dybcio 379898874a46SKonrad Dybcio mdss_dsi1: dsi@ae96000 { 3799b0b8b34aSDmitry Baryshkov compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 380098874a46SKonrad Dybcio reg = <0 0x0ae96000 0 0x400>; 380198874a46SKonrad Dybcio reg-names = "dsi_ctrl"; 380298874a46SKonrad Dybcio 380398874a46SKonrad Dybcio interrupt-parent = <&mdss>; 380498874a46SKonrad Dybcio interrupts = <5>; 380598874a46SKonrad Dybcio 380698874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 380798874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 380898874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 380998874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_ESC1_CLK>, 381098874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_AHB_CLK>, 381198874a46SKonrad Dybcio <&gcc GCC_DISP_HF_AXI_CLK>; 381298874a46SKonrad Dybcio clock-names = "byte", 381398874a46SKonrad Dybcio "byte_intf", 381498874a46SKonrad Dybcio "pixel", 381598874a46SKonrad Dybcio "core", 381698874a46SKonrad Dybcio "iface", 381798874a46SKonrad Dybcio "bus"; 381898874a46SKonrad Dybcio 381998874a46SKonrad Dybcio assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 382098874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 382198874a46SKonrad Dybcio assigned-clock-parents = <&mdss_dsi1_phy 0>, 382298874a46SKonrad Dybcio <&mdss_dsi1_phy 1>; 382398874a46SKonrad Dybcio 382498874a46SKonrad Dybcio operating-points-v2 = <&dsi_opp_table>; 382598874a46SKonrad Dybcio power-domains = <&rpmhpd SM8150_MMCX>; 382698874a46SKonrad Dybcio 382798874a46SKonrad Dybcio phys = <&mdss_dsi1_phy>; 382898874a46SKonrad Dybcio 382998874a46SKonrad Dybcio status = "disabled"; 383098874a46SKonrad Dybcio 383198874a46SKonrad Dybcio #address-cells = <1>; 383298874a46SKonrad Dybcio #size-cells = <0>; 383398874a46SKonrad Dybcio 383498874a46SKonrad Dybcio ports { 383598874a46SKonrad Dybcio #address-cells = <1>; 383698874a46SKonrad Dybcio #size-cells = <0>; 383798874a46SKonrad Dybcio 383898874a46SKonrad Dybcio port@0 { 383998874a46SKonrad Dybcio reg = <0>; 384098874a46SKonrad Dybcio mdss_dsi1_in: endpoint { 384198874a46SKonrad Dybcio remote-endpoint = <&dpu_intf2_out>; 384298874a46SKonrad Dybcio }; 384398874a46SKonrad Dybcio }; 384498874a46SKonrad Dybcio 384598874a46SKonrad Dybcio port@1 { 384698874a46SKonrad Dybcio reg = <1>; 384798874a46SKonrad Dybcio mdss_dsi1_out: endpoint { 384898874a46SKonrad Dybcio }; 384998874a46SKonrad Dybcio }; 385098874a46SKonrad Dybcio }; 385198874a46SKonrad Dybcio }; 385298874a46SKonrad Dybcio 385398874a46SKonrad Dybcio mdss_dsi1_phy: phy@ae96400 { 385498874a46SKonrad Dybcio compatible = "qcom,dsi-phy-7nm"; 385598874a46SKonrad Dybcio reg = <0 0x0ae96400 0 0x200>, 385698874a46SKonrad Dybcio <0 0x0ae96600 0 0x280>, 385798874a46SKonrad Dybcio <0 0x0ae96900 0 0x260>; 385898874a46SKonrad Dybcio reg-names = "dsi_phy", 385998874a46SKonrad Dybcio "dsi_phy_lane", 386098874a46SKonrad Dybcio "dsi_pll"; 386198874a46SKonrad Dybcio 386298874a46SKonrad Dybcio #clock-cells = <1>; 386398874a46SKonrad Dybcio #phy-cells = <0>; 386498874a46SKonrad Dybcio 386598874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 386698874a46SKonrad Dybcio <&rpmhcc RPMH_CXO_CLK>; 386798874a46SKonrad Dybcio clock-names = "iface", "ref"; 386898874a46SKonrad Dybcio 386998874a46SKonrad Dybcio status = "disabled"; 387098874a46SKonrad Dybcio }; 387198874a46SKonrad Dybcio }; 387298874a46SKonrad Dybcio 38732ef3bb17SKonrad Dybcio dispcc: clock-controller@af00000 { 38742ef3bb17SKonrad Dybcio compatible = "qcom,sm8150-dispcc"; 38752ef3bb17SKonrad Dybcio reg = <0 0x0af00000 0 0x10000>; 38762ef3bb17SKonrad Dybcio clocks = <&rpmhcc RPMH_CXO_CLK>, 387798874a46SKonrad Dybcio <&mdss_dsi0_phy 0>, 387898874a46SKonrad Dybcio <&mdss_dsi0_phy 1>, 387998874a46SKonrad Dybcio <&mdss_dsi1_phy 0>, 388098874a46SKonrad Dybcio <&mdss_dsi1_phy 1>, 38812ef3bb17SKonrad Dybcio <0>, 38822ef3bb17SKonrad Dybcio <0>; 38832ef3bb17SKonrad Dybcio clock-names = "bi_tcxo", 38842ef3bb17SKonrad Dybcio "dsi0_phy_pll_out_byteclk", 38852ef3bb17SKonrad Dybcio "dsi0_phy_pll_out_dsiclk", 38862ef3bb17SKonrad Dybcio "dsi1_phy_pll_out_byteclk", 38872ef3bb17SKonrad Dybcio "dsi1_phy_pll_out_dsiclk", 38882ef3bb17SKonrad Dybcio "dp_phy_pll_link_clk", 38892ef3bb17SKonrad Dybcio "dp_phy_pll_vco_div_clk"; 38902ef3bb17SKonrad Dybcio power-domains = <&rpmhpd SM8150_MMCX>; 38912ef3bb17SKonrad Dybcio #clock-cells = <1>; 38922ef3bb17SKonrad Dybcio #reset-cells = <1>; 38932ef3bb17SKonrad Dybcio #power-domain-cells = <1>; 38942ef3bb17SKonrad Dybcio }; 38952ef3bb17SKonrad Dybcio 3896397ad946SBhupesh Sharma pdc: interrupt-controller@b220000 { 3897397ad946SBhupesh Sharma compatible = "qcom,sm8150-pdc", "qcom,pdc"; 3898397ad946SBhupesh Sharma reg = <0 0x0b220000 0 0x400>; 3899397ad946SBhupesh Sharma qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3900397ad946SBhupesh Sharma <125 63 1>; 3901397ad946SBhupesh Sharma #interrupt-cells = <2>; 3902397ad946SBhupesh Sharma interrupt-parent = <&intc>; 3903397ad946SBhupesh Sharma interrupt-controller; 3904397ad946SBhupesh Sharma }; 3905397ad946SBhupesh Sharma 3906bb99820dSKrzysztof Kozlowski aoss_qmp: power-management@c300000 { 39076ba93ba9SKrzysztof Kozlowski compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 390847cb6a06SMaulik Shah reg = <0x0 0x0c300000 0x0 0x400>; 3909d8cf9372SVinod Koul interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3910d8cf9372SVinod Koul mboxes = <&apss_shared 0>; 3911d8cf9372SVinod Koul 3912d8cf9372SVinod Koul #clock-cells = <0>; 3913d8cf9372SVinod Koul }; 3914d8cf9372SVinod Koul 391547cb6a06SMaulik Shah sram@c3f0000 { 391647cb6a06SMaulik Shah compatible = "qcom,rpmh-stats"; 391747cb6a06SMaulik Shah reg = <0 0x0c3f0000 0 0x400>; 391847cb6a06SMaulik Shah }; 391947cb6a06SMaulik Shah 3920d2fa630cSAmit Kucheria tsens0: thermal-sensor@c263000 { 3921d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3922d2fa630cSAmit Kucheria reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3923d2fa630cSAmit Kucheria <0 0x0c222000 0 0x1ff>; /* SROT */ 3924d2fa630cSAmit Kucheria #qcom,sensors = <16>; 3925d2fa630cSAmit Kucheria interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3926d2fa630cSAmit Kucheria <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3927d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 3928d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 3929d2fa630cSAmit Kucheria }; 3930d2fa630cSAmit Kucheria 3931d2fa630cSAmit Kucheria tsens1: thermal-sensor@c265000 { 3932d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3933d2fa630cSAmit Kucheria reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3934d2fa630cSAmit Kucheria <0 0x0c223000 0 0x1ff>; /* SROT */ 3935d2fa630cSAmit Kucheria #qcom,sensors = <8>; 3936d2fa630cSAmit Kucheria interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3937d2fa630cSAmit Kucheria <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3938d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 3939d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 3940d2fa630cSAmit Kucheria }; 3941d2fa630cSAmit Kucheria 3942e13c6d14SVinod Koul spmi_bus: spmi@c440000 { 3943e13c6d14SVinod Koul compatible = "qcom,spmi-pmic-arb"; 3944e13c6d14SVinod Koul reg = <0x0 0x0c440000 0x0 0x0001100>, 3945e13c6d14SVinod Koul <0x0 0x0c600000 0x0 0x2000000>, 3946e13c6d14SVinod Koul <0x0 0x0e600000 0x0 0x0100000>, 3947e13c6d14SVinod Koul <0x0 0x0e700000 0x0 0x00a0000>, 3948e13c6d14SVinod Koul <0x0 0x0c40a000 0x0 0x0026000>; 3949e13c6d14SVinod Koul reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3950e13c6d14SVinod Koul interrupt-names = "periph_irq"; 3951e13c6d14SVinod Koul interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3952e13c6d14SVinod Koul qcom,ee = <0>; 3953e13c6d14SVinod Koul qcom,channel = <0>; 3954e13c6d14SVinod Koul #address-cells = <2>; 3955e13c6d14SVinod Koul #size-cells = <0>; 3956e13c6d14SVinod Koul interrupt-controller; 3957e13c6d14SVinod Koul #interrupt-cells = <4>; 3958e13c6d14SVinod Koul }; 3959e13c6d14SVinod Koul 396048156232SJonathan Marek apps_smmu: iommu@15000000 { 396148156232SJonathan Marek compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 396248156232SJonathan Marek reg = <0 0x15000000 0 0x100000>; 396348156232SJonathan Marek #iommu-cells = <2>; 396448156232SJonathan Marek #global-interrupts = <1>; 396548156232SJonathan Marek interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 396648156232SJonathan Marek <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 396748156232SJonathan Marek <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 396848156232SJonathan Marek <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 396948156232SJonathan Marek <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 397048156232SJonathan Marek <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 397148156232SJonathan Marek <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 397248156232SJonathan Marek <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 397348156232SJonathan Marek <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 397448156232SJonathan Marek <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 397548156232SJonathan Marek <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 397648156232SJonathan Marek <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 397748156232SJonathan Marek <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 397848156232SJonathan Marek <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 397948156232SJonathan Marek <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 398048156232SJonathan Marek <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 398148156232SJonathan Marek <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 398248156232SJonathan Marek <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 398348156232SJonathan Marek <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 398448156232SJonathan Marek <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 398548156232SJonathan Marek <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 398648156232SJonathan Marek <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 398748156232SJonathan Marek <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 398848156232SJonathan Marek <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 398948156232SJonathan Marek <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 399048156232SJonathan Marek <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 399148156232SJonathan Marek <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 399248156232SJonathan Marek <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 399348156232SJonathan Marek <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 399448156232SJonathan Marek <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 399548156232SJonathan Marek <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 399648156232SJonathan Marek <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 399748156232SJonathan Marek <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 399848156232SJonathan Marek <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 399948156232SJonathan Marek <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 400048156232SJonathan Marek <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 400148156232SJonathan Marek <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 400248156232SJonathan Marek <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 400348156232SJonathan Marek <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 400448156232SJonathan Marek <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 400548156232SJonathan Marek <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 400648156232SJonathan Marek <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 400748156232SJonathan Marek <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 400848156232SJonathan Marek <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 400948156232SJonathan Marek <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 401048156232SJonathan Marek <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 401148156232SJonathan Marek <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 401248156232SJonathan Marek <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 401348156232SJonathan Marek <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 401448156232SJonathan Marek <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 401548156232SJonathan Marek <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 401648156232SJonathan Marek <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 401748156232SJonathan Marek <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 401848156232SJonathan Marek <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 401948156232SJonathan Marek <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 402048156232SJonathan Marek <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 402148156232SJonathan Marek <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 402248156232SJonathan Marek <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 402348156232SJonathan Marek <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 402448156232SJonathan Marek <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 402548156232SJonathan Marek <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 402648156232SJonathan Marek <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 402748156232SJonathan Marek <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 402848156232SJonathan Marek <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 402948156232SJonathan Marek <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 403048156232SJonathan Marek <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 403148156232SJonathan Marek <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 403248156232SJonathan Marek <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 403348156232SJonathan Marek <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 403448156232SJonathan Marek <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 403548156232SJonathan Marek <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 403648156232SJonathan Marek <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 403748156232SJonathan Marek <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 403848156232SJonathan Marek <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 403948156232SJonathan Marek <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 404048156232SJonathan Marek <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 404148156232SJonathan Marek <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 404248156232SJonathan Marek <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 404348156232SJonathan Marek <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 404448156232SJonathan Marek <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 404548156232SJonathan Marek <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 404648156232SJonathan Marek }; 404748156232SJonathan Marek 404849076351SSibi Sankar remoteproc_adsp: remoteproc@17300000 { 404949076351SSibi Sankar compatible = "qcom,sm8150-adsp-pas"; 405049076351SSibi Sankar reg = <0x0 0x17300000 0x0 0x4040>; 405149076351SSibi Sankar 405249076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 405349076351SSibi Sankar <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 405449076351SSibi Sankar <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 405549076351SSibi Sankar <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 405649076351SSibi Sankar <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 405749076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 405849076351SSibi Sankar "handover", "stop-ack"; 405949076351SSibi Sankar 406049076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 406149076351SSibi Sankar clock-names = "xo"; 406249076351SSibi Sankar 4063a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_CX>; 406449076351SSibi Sankar 406549076351SSibi Sankar memory-region = <&adsp_mem>; 406649076351SSibi Sankar 4067d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 4068d9d327f6SSibi Sankar 406949076351SSibi Sankar qcom,smem-states = <&adsp_smp2p_out 0>; 407049076351SSibi Sankar qcom,smem-state-names = "stop"; 407149076351SSibi Sankar 407249076351SSibi Sankar status = "disabled"; 407349076351SSibi Sankar 407449076351SSibi Sankar glink-edge { 407549076351SSibi Sankar interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 407649076351SSibi Sankar label = "lpass"; 407749076351SSibi Sankar qcom,remote-pid = <2>; 407849076351SSibi Sankar mboxes = <&apss_shared 8>; 407981729330SBhupesh Sharma 408081729330SBhupesh Sharma fastrpc { 408181729330SBhupesh Sharma compatible = "qcom,fastrpc"; 408281729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 408381729330SBhupesh Sharma label = "adsp"; 40848c8ce95bSJeya R qcom,non-secure-domain; 408581729330SBhupesh Sharma #address-cells = <1>; 408681729330SBhupesh Sharma #size-cells = <0>; 408781729330SBhupesh Sharma 408881729330SBhupesh Sharma compute-cb@3 { 408981729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 409081729330SBhupesh Sharma reg = <3>; 409181729330SBhupesh Sharma iommus = <&apps_smmu 0x1b23 0x0>; 409281729330SBhupesh Sharma }; 409381729330SBhupesh Sharma 409481729330SBhupesh Sharma compute-cb@4 { 409581729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 409681729330SBhupesh Sharma reg = <4>; 409781729330SBhupesh Sharma iommus = <&apps_smmu 0x1b24 0x0>; 409881729330SBhupesh Sharma }; 409981729330SBhupesh Sharma 410081729330SBhupesh Sharma compute-cb@5 { 410181729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 410281729330SBhupesh Sharma reg = <5>; 410381729330SBhupesh Sharma iommus = <&apps_smmu 0x1b25 0x0>; 410481729330SBhupesh Sharma }; 410581729330SBhupesh Sharma }; 410649076351SSibi Sankar }; 410749076351SSibi Sankar }; 410849076351SSibi Sankar 4109e13c6d14SVinod Koul intc: interrupt-controller@17a00000 { 4110e13c6d14SVinod Koul compatible = "arm,gic-v3"; 4111e13c6d14SVinod Koul interrupt-controller; 4112e13c6d14SVinod Koul #interrupt-cells = <3>; 4113e13c6d14SVinod Koul reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4114e13c6d14SVinod Koul <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4115e13c6d14SVinod Koul interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4116e13c6d14SVinod Koul }; 4117e13c6d14SVinod Koul 4118d8cf9372SVinod Koul apss_shared: mailbox@17c00000 { 41199b2e284aSKrzysztof Kozlowski compatible = "qcom,sm8150-apss-shared", 41209b2e284aSKrzysztof Kozlowski "qcom,sdm845-apss-shared"; 4121d8cf9372SVinod Koul reg = <0x0 0x17c00000 0x0 0x1000>; 4122d8cf9372SVinod Koul #mbox-cells = <1>; 4123d8cf9372SVinod Koul }; 4124d8cf9372SVinod Koul 4125fb2d8150SSai Prakash Ranjan watchdog@17c10000 { 4126fb2d8150SSai Prakash Ranjan compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 4127fb2d8150SSai Prakash Ranjan reg = <0 0x17c10000 0 0x1000>; 4128fb2d8150SSai Prakash Ranjan clocks = <&sleep_clk>; 4129b094c8f8SSai Prakash Ranjan interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4130fb2d8150SSai Prakash Ranjan }; 4131fb2d8150SSai Prakash Ranjan 4132e13c6d14SVinod Koul timer@17c20000 { 4133458ebdbbSDavid Heidelberg #address-cells = <1>; 4134458ebdbbSDavid Heidelberg #size-cells = <1>; 4135458ebdbbSDavid Heidelberg ranges = <0 0 0 0x20000000>; 4136e13c6d14SVinod Koul compatible = "arm,armv7-timer-mem"; 4137e13c6d14SVinod Koul reg = <0x0 0x17c20000 0x0 0x1000>; 4138e13c6d14SVinod Koul clock-frequency = <19200000>; 4139e13c6d14SVinod Koul 4140e13c6d14SVinod Koul frame@17c21000 { 4141e13c6d14SVinod Koul frame-number = <0>; 4142e13c6d14SVinod Koul interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4143e13c6d14SVinod Koul <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4144458ebdbbSDavid Heidelberg reg = <0x17c21000 0x1000>, 4145458ebdbbSDavid Heidelberg <0x17c22000 0x1000>; 4146e13c6d14SVinod Koul }; 4147e13c6d14SVinod Koul 4148e13c6d14SVinod Koul frame@17c23000 { 4149e13c6d14SVinod Koul frame-number = <1>; 4150e13c6d14SVinod Koul interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4151458ebdbbSDavid Heidelberg reg = <0x17c23000 0x1000>; 4152e13c6d14SVinod Koul status = "disabled"; 4153e13c6d14SVinod Koul }; 4154e13c6d14SVinod Koul 4155e13c6d14SVinod Koul frame@17c25000 { 4156e13c6d14SVinod Koul frame-number = <2>; 4157e13c6d14SVinod Koul interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4158458ebdbbSDavid Heidelberg reg = <0x17c25000 0x1000>; 4159e13c6d14SVinod Koul status = "disabled"; 4160e13c6d14SVinod Koul }; 4161e13c6d14SVinod Koul 4162e13c6d14SVinod Koul frame@17c27000 { 4163e13c6d14SVinod Koul frame-number = <3>; 4164e13c6d14SVinod Koul interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4165458ebdbbSDavid Heidelberg reg = <0x17c26000 0x1000>; 4166e13c6d14SVinod Koul status = "disabled"; 4167e13c6d14SVinod Koul }; 4168e13c6d14SVinod Koul 4169e13c6d14SVinod Koul frame@17c29000 { 4170e13c6d14SVinod Koul frame-number = <4>; 4171e13c6d14SVinod Koul interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4172458ebdbbSDavid Heidelberg reg = <0x17c29000 0x1000>; 4173e13c6d14SVinod Koul status = "disabled"; 4174e13c6d14SVinod Koul }; 4175e13c6d14SVinod Koul 4176e13c6d14SVinod Koul frame@17c2b000 { 4177e13c6d14SVinod Koul frame-number = <5>; 4178e13c6d14SVinod Koul interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4179458ebdbbSDavid Heidelberg reg = <0x17c2b000 0x1000>; 4180e13c6d14SVinod Koul status = "disabled"; 4181e13c6d14SVinod Koul }; 4182e13c6d14SVinod Koul 4183e13c6d14SVinod Koul frame@17c2d000 { 4184e13c6d14SVinod Koul frame-number = <6>; 4185e13c6d14SVinod Koul interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4186458ebdbbSDavid Heidelberg reg = <0x17c2d000 0x1000>; 4187e13c6d14SVinod Koul status = "disabled"; 4188e13c6d14SVinod Koul }; 4189e13c6d14SVinod Koul }; 4190d8cf9372SVinod Koul 4191d8cf9372SVinod Koul apps_rsc: rsc@18200000 { 4192d8cf9372SVinod Koul label = "apps_rsc"; 4193d8cf9372SVinod Koul compatible = "qcom,rpmh-rsc"; 4194d8cf9372SVinod Koul reg = <0x0 0x18200000 0x0 0x10000>, 4195d8cf9372SVinod Koul <0x0 0x18210000 0x0 0x10000>, 4196d8cf9372SVinod Koul <0x0 0x18220000 0x0 0x10000>; 4197d8cf9372SVinod Koul reg-names = "drv-0", "drv-1", "drv-2"; 4198d8cf9372SVinod Koul interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4199d8cf9372SVinod Koul <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4200d8cf9372SVinod Koul <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4201d8cf9372SVinod Koul qcom,tcs-offset = <0xd00>; 4202d8cf9372SVinod Koul qcom,drv-id = <2>; 4203d8cf9372SVinod Koul qcom,tcs-config = <ACTIVE_TCS 2>, 420417ac8af6SMaulik Shah <SLEEP_TCS 3>, 420517ac8af6SMaulik Shah <WAKE_TCS 3>, 420617ac8af6SMaulik Shah <CONTROL_TCS 1>; 42072ffa0ca4SMaulik Shah power-domains = <&CLUSTER_PD>; 4208d8cf9372SVinod Koul 4209d8cf9372SVinod Koul rpmhcc: clock-controller { 4210d8cf9372SVinod Koul compatible = "qcom,sm8150-rpmh-clk"; 4211d8cf9372SVinod Koul #clock-cells = <1>; 4212d8cf9372SVinod Koul clock-names = "xo"; 4213d8cf9372SVinod Koul clocks = <&xo_board>; 4214d8cf9372SVinod Koul }; 4215017e7856SSibi Sankar 4216017e7856SSibi Sankar rpmhpd: power-controller { 4217017e7856SSibi Sankar compatible = "qcom,sm8150-rpmhpd"; 4218017e7856SSibi Sankar #power-domain-cells = <1>; 4219017e7856SSibi Sankar operating-points-v2 = <&rpmhpd_opp_table>; 4220017e7856SSibi Sankar 4221017e7856SSibi Sankar rpmhpd_opp_table: opp-table { 4222017e7856SSibi Sankar compatible = "operating-points-v2"; 4223017e7856SSibi Sankar 4224017e7856SSibi Sankar rpmhpd_opp_ret: opp1 { 4225017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4226017e7856SSibi Sankar }; 4227017e7856SSibi Sankar 4228017e7856SSibi Sankar rpmhpd_opp_min_svs: opp2 { 4229017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4230017e7856SSibi Sankar }; 4231017e7856SSibi Sankar 4232017e7856SSibi Sankar rpmhpd_opp_low_svs: opp3 { 4233017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4234017e7856SSibi Sankar }; 4235017e7856SSibi Sankar 4236017e7856SSibi Sankar rpmhpd_opp_svs: opp4 { 4237017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4238017e7856SSibi Sankar }; 4239017e7856SSibi Sankar 4240017e7856SSibi Sankar rpmhpd_opp_svs_l1: opp5 { 4241017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4242017e7856SSibi Sankar }; 4243017e7856SSibi Sankar 4244017e7856SSibi Sankar rpmhpd_opp_svs_l2: opp6 { 4245017e7856SSibi Sankar opp-level = <224>; 4246017e7856SSibi Sankar }; 4247017e7856SSibi Sankar 4248017e7856SSibi Sankar rpmhpd_opp_nom: opp7 { 4249017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4250017e7856SSibi Sankar }; 4251017e7856SSibi Sankar 4252017e7856SSibi Sankar rpmhpd_opp_nom_l1: opp8 { 4253017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4254017e7856SSibi Sankar }; 4255017e7856SSibi Sankar 4256017e7856SSibi Sankar rpmhpd_opp_nom_l2: opp9 { 4257017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4258017e7856SSibi Sankar }; 4259017e7856SSibi Sankar 4260017e7856SSibi Sankar rpmhpd_opp_turbo: opp10 { 4261017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4262017e7856SSibi Sankar }; 4263017e7856SSibi Sankar 4264017e7856SSibi Sankar rpmhpd_opp_turbo_l1: opp11 { 4265017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4266017e7856SSibi Sankar }; 4267017e7856SSibi Sankar }; 4268017e7856SSibi Sankar }; 426971a2fc6eSJonathan Marek 4270fc0e7dd6SKrzysztof Kozlowski apps_bcm_voter: bcm-voter { 427171a2fc6eSJonathan Marek compatible = "qcom,bcm-voter"; 427271a2fc6eSJonathan Marek }; 4273d8cf9372SVinod Koul }; 4274fea8930bSSibi Sankar 4275a6d435c1SSibi Sankar osm_l3: interconnect@18321000 { 4276a0289a10SBjorn Andersson compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4277a6d435c1SSibi Sankar reg = <0 0x18321000 0 0x1400>; 4278a6d435c1SSibi Sankar 4279a6d435c1SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4280a6d435c1SSibi Sankar clock-names = "xo", "alternate"; 4281a6d435c1SSibi Sankar 4282a6d435c1SSibi Sankar #interconnect-cells = <1>; 4283a6d435c1SSibi Sankar }; 4284a6d435c1SSibi Sankar 4285fea8930bSSibi Sankar cpufreq_hw: cpufreq@18323000 { 4286b2e1f870SKonrad Dybcio compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw"; 4287fea8930bSSibi Sankar reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 4288fea8930bSSibi Sankar <0 0x18327800 0 0x1400>; 4289fea8930bSSibi Sankar reg-names = "freq-domain0", "freq-domain1", 4290fea8930bSSibi Sankar "freq-domain2"; 4291fea8930bSSibi Sankar 4292fea8930bSSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4293fea8930bSSibi Sankar clock-names = "xo", "alternate"; 4294fea8930bSSibi Sankar 4295fea8930bSSibi Sankar #freq-domain-cells = <1>; 4296fc725894SManivannan Sadhasivam #clock-cells = <1>; 4297fea8930bSSibi Sankar }; 429805090bb9SJonathan Marek 42992ffcfe79SThara Gopinath lmh_cluster1: lmh@18350800 { 43002ffcfe79SThara Gopinath compatible = "qcom,sm8150-lmh"; 43012ffcfe79SThara Gopinath reg = <0 0x18350800 0 0x400>; 43022ffcfe79SThara Gopinath interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 43032ffcfe79SThara Gopinath cpus = <&CPU4>; 43042ffcfe79SThara Gopinath qcom,lmh-temp-arm-millicelsius = <60000>; 43052ffcfe79SThara Gopinath qcom,lmh-temp-low-millicelsius = <84500>; 43062ffcfe79SThara Gopinath qcom,lmh-temp-high-millicelsius = <85000>; 43072ffcfe79SThara Gopinath interrupt-controller; 43082ffcfe79SThara Gopinath #interrupt-cells = <1>; 43092ffcfe79SThara Gopinath }; 43102ffcfe79SThara Gopinath 43112ffcfe79SThara Gopinath lmh_cluster0: lmh@18358800 { 43122ffcfe79SThara Gopinath compatible = "qcom,sm8150-lmh"; 43132ffcfe79SThara Gopinath reg = <0 0x18358800 0 0x400>; 43142ffcfe79SThara Gopinath interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 43152ffcfe79SThara Gopinath cpus = <&CPU0>; 43162ffcfe79SThara Gopinath qcom,lmh-temp-arm-millicelsius = <60000>; 43172ffcfe79SThara Gopinath qcom,lmh-temp-low-millicelsius = <84500>; 43182ffcfe79SThara Gopinath qcom,lmh-temp-high-millicelsius = <85000>; 43192ffcfe79SThara Gopinath interrupt-controller; 43202ffcfe79SThara Gopinath #interrupt-cells = <1>; 43212ffcfe79SThara Gopinath }; 43222ffcfe79SThara Gopinath 432305090bb9SJonathan Marek wifi: wifi@18800000 { 432405090bb9SJonathan Marek compatible = "qcom,wcn3990-wifi"; 432505090bb9SJonathan Marek reg = <0 0x18800000 0 0x800000>; 432605090bb9SJonathan Marek reg-names = "membase"; 432705090bb9SJonathan Marek memory-region = <&wlan_mem>; 432805090bb9SJonathan Marek clock-names = "cxo_ref_clk_pin", "qdss"; 432905090bb9SJonathan Marek clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 433005090bb9SJonathan Marek interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 433105090bb9SJonathan Marek <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 433205090bb9SJonathan Marek <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 433305090bb9SJonathan Marek <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 433405090bb9SJonathan Marek <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 433505090bb9SJonathan Marek <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 433605090bb9SJonathan Marek <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 433705090bb9SJonathan Marek <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 433805090bb9SJonathan Marek <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 433905090bb9SJonathan Marek <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 434005090bb9SJonathan Marek <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 434105090bb9SJonathan Marek <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 434205090bb9SJonathan Marek iommus = <&apps_smmu 0x0640 0x1>; 434305090bb9SJonathan Marek status = "disabled"; 434405090bb9SJonathan Marek }; 4345e13c6d14SVinod Koul }; 4346e13c6d14SVinod Koul 4347e13c6d14SVinod Koul timer { 4348e13c6d14SVinod Koul compatible = "arm,armv8-timer"; 4349e13c6d14SVinod Koul interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4350e13c6d14SVinod Koul <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4351e13c6d14SVinod Koul <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4352e13c6d14SVinod Koul <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4353e13c6d14SVinod Koul }; 4354d2fa630cSAmit Kucheria 4355d2fa630cSAmit Kucheria thermal-zones { 4356d2fa630cSAmit Kucheria cpu0-thermal { 4357d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4358d2fa630cSAmit Kucheria polling-delay = <1000>; 4359d2fa630cSAmit Kucheria 4360d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 1>; 4361d2fa630cSAmit Kucheria 4362d2fa630cSAmit Kucheria trips { 4363d2fa630cSAmit Kucheria cpu0_alert0: trip-point0 { 4364d2fa630cSAmit Kucheria temperature = <90000>; 4365d2fa630cSAmit Kucheria hysteresis = <2000>; 4366d2fa630cSAmit Kucheria type = "passive"; 4367d2fa630cSAmit Kucheria }; 4368d2fa630cSAmit Kucheria 4369d2fa630cSAmit Kucheria cpu0_alert1: trip-point1 { 4370d2fa630cSAmit Kucheria temperature = <95000>; 4371d2fa630cSAmit Kucheria hysteresis = <2000>; 4372d2fa630cSAmit Kucheria type = "passive"; 4373d2fa630cSAmit Kucheria }; 4374d2fa630cSAmit Kucheria 43751364acc3SKrzysztof Kozlowski cpu0_crit: cpu-crit { 4376d2fa630cSAmit Kucheria temperature = <110000>; 4377d2fa630cSAmit Kucheria hysteresis = <1000>; 4378d2fa630cSAmit Kucheria type = "critical"; 4379d2fa630cSAmit Kucheria }; 4380d2fa630cSAmit Kucheria }; 4381d2fa630cSAmit Kucheria 4382d2fa630cSAmit Kucheria cooling-maps { 4383d2fa630cSAmit Kucheria map0 { 4384d2fa630cSAmit Kucheria trip = <&cpu0_alert0>; 4385d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4386d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4387d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4388d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4389d2fa630cSAmit Kucheria }; 4390d2fa630cSAmit Kucheria map1 { 4391d2fa630cSAmit Kucheria trip = <&cpu0_alert1>; 4392d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4393d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4394d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4395d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4396d2fa630cSAmit Kucheria }; 4397d2fa630cSAmit Kucheria }; 4398d2fa630cSAmit Kucheria }; 4399d2fa630cSAmit Kucheria 4400d2fa630cSAmit Kucheria cpu1-thermal { 4401d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4402d2fa630cSAmit Kucheria polling-delay = <1000>; 4403d2fa630cSAmit Kucheria 4404d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 2>; 4405d2fa630cSAmit Kucheria 4406d2fa630cSAmit Kucheria trips { 4407d2fa630cSAmit Kucheria cpu1_alert0: trip-point0 { 4408d2fa630cSAmit Kucheria temperature = <90000>; 4409d2fa630cSAmit Kucheria hysteresis = <2000>; 4410d2fa630cSAmit Kucheria type = "passive"; 4411d2fa630cSAmit Kucheria }; 4412d2fa630cSAmit Kucheria 4413d2fa630cSAmit Kucheria cpu1_alert1: trip-point1 { 4414d2fa630cSAmit Kucheria temperature = <95000>; 4415d2fa630cSAmit Kucheria hysteresis = <2000>; 4416d2fa630cSAmit Kucheria type = "passive"; 4417d2fa630cSAmit Kucheria }; 4418d2fa630cSAmit Kucheria 44191364acc3SKrzysztof Kozlowski cpu1_crit: cpu-crit { 4420d2fa630cSAmit Kucheria temperature = <110000>; 4421d2fa630cSAmit Kucheria hysteresis = <1000>; 4422d2fa630cSAmit Kucheria type = "critical"; 4423d2fa630cSAmit Kucheria }; 4424d2fa630cSAmit Kucheria }; 4425d2fa630cSAmit Kucheria 4426d2fa630cSAmit Kucheria cooling-maps { 4427d2fa630cSAmit Kucheria map0 { 4428d2fa630cSAmit Kucheria trip = <&cpu1_alert0>; 4429d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4430d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4431d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4432d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4433d2fa630cSAmit Kucheria }; 4434d2fa630cSAmit Kucheria map1 { 4435d2fa630cSAmit Kucheria trip = <&cpu1_alert1>; 4436d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4437d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4438d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4439d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4440d2fa630cSAmit Kucheria }; 4441d2fa630cSAmit Kucheria }; 4442d2fa630cSAmit Kucheria }; 4443d2fa630cSAmit Kucheria 4444d2fa630cSAmit Kucheria cpu2-thermal { 4445d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4446d2fa630cSAmit Kucheria polling-delay = <1000>; 4447d2fa630cSAmit Kucheria 4448d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 3>; 4449d2fa630cSAmit Kucheria 4450d2fa630cSAmit Kucheria trips { 4451d2fa630cSAmit Kucheria cpu2_alert0: trip-point0 { 4452d2fa630cSAmit Kucheria temperature = <90000>; 4453d2fa630cSAmit Kucheria hysteresis = <2000>; 4454d2fa630cSAmit Kucheria type = "passive"; 4455d2fa630cSAmit Kucheria }; 4456d2fa630cSAmit Kucheria 4457d2fa630cSAmit Kucheria cpu2_alert1: trip-point1 { 4458d2fa630cSAmit Kucheria temperature = <95000>; 4459d2fa630cSAmit Kucheria hysteresis = <2000>; 4460d2fa630cSAmit Kucheria type = "passive"; 4461d2fa630cSAmit Kucheria }; 4462d2fa630cSAmit Kucheria 44631364acc3SKrzysztof Kozlowski cpu2_crit: cpu-crit { 4464d2fa630cSAmit Kucheria temperature = <110000>; 4465d2fa630cSAmit Kucheria hysteresis = <1000>; 4466d2fa630cSAmit Kucheria type = "critical"; 4467d2fa630cSAmit Kucheria }; 4468d2fa630cSAmit Kucheria }; 4469d2fa630cSAmit Kucheria 4470d2fa630cSAmit Kucheria cooling-maps { 4471d2fa630cSAmit Kucheria map0 { 4472d2fa630cSAmit Kucheria trip = <&cpu2_alert0>; 4473d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4474d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4475d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4476d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4477d2fa630cSAmit Kucheria }; 4478d2fa630cSAmit Kucheria map1 { 4479d2fa630cSAmit Kucheria trip = <&cpu2_alert1>; 4480d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4481d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4482d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4483d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4484d2fa630cSAmit Kucheria }; 4485d2fa630cSAmit Kucheria }; 4486d2fa630cSAmit Kucheria }; 4487d2fa630cSAmit Kucheria 4488d2fa630cSAmit Kucheria cpu3-thermal { 4489d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4490d2fa630cSAmit Kucheria polling-delay = <1000>; 4491d2fa630cSAmit Kucheria 4492d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 4>; 4493d2fa630cSAmit Kucheria 4494d2fa630cSAmit Kucheria trips { 4495d2fa630cSAmit Kucheria cpu3_alert0: trip-point0 { 4496d2fa630cSAmit Kucheria temperature = <90000>; 4497d2fa630cSAmit Kucheria hysteresis = <2000>; 4498d2fa630cSAmit Kucheria type = "passive"; 4499d2fa630cSAmit Kucheria }; 4500d2fa630cSAmit Kucheria 4501d2fa630cSAmit Kucheria cpu3_alert1: trip-point1 { 4502d2fa630cSAmit Kucheria temperature = <95000>; 4503d2fa630cSAmit Kucheria hysteresis = <2000>; 4504d2fa630cSAmit Kucheria type = "passive"; 4505d2fa630cSAmit Kucheria }; 4506d2fa630cSAmit Kucheria 45071364acc3SKrzysztof Kozlowski cpu3_crit: cpu-crit { 4508d2fa630cSAmit Kucheria temperature = <110000>; 4509d2fa630cSAmit Kucheria hysteresis = <1000>; 4510d2fa630cSAmit Kucheria type = "critical"; 4511d2fa630cSAmit Kucheria }; 4512d2fa630cSAmit Kucheria }; 4513d2fa630cSAmit Kucheria 4514d2fa630cSAmit Kucheria cooling-maps { 4515d2fa630cSAmit Kucheria map0 { 4516d2fa630cSAmit Kucheria trip = <&cpu3_alert0>; 4517d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4518d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4519d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4520d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4521d2fa630cSAmit Kucheria }; 4522d2fa630cSAmit Kucheria map1 { 4523d2fa630cSAmit Kucheria trip = <&cpu3_alert1>; 4524d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4525d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4526d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4527d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4528d2fa630cSAmit Kucheria }; 4529d2fa630cSAmit Kucheria }; 4530d2fa630cSAmit Kucheria }; 4531d2fa630cSAmit Kucheria 4532d2fa630cSAmit Kucheria cpu4-top-thermal { 4533d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4534d2fa630cSAmit Kucheria polling-delay = <1000>; 4535d2fa630cSAmit Kucheria 4536d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 7>; 4537d2fa630cSAmit Kucheria 4538d2fa630cSAmit Kucheria trips { 4539d2fa630cSAmit Kucheria cpu4_top_alert0: trip-point0 { 4540d2fa630cSAmit Kucheria temperature = <90000>; 4541d2fa630cSAmit Kucheria hysteresis = <2000>; 4542d2fa630cSAmit Kucheria type = "passive"; 4543d2fa630cSAmit Kucheria }; 4544d2fa630cSAmit Kucheria 4545d2fa630cSAmit Kucheria cpu4_top_alert1: trip-point1 { 4546d2fa630cSAmit Kucheria temperature = <95000>; 4547d2fa630cSAmit Kucheria hysteresis = <2000>; 4548d2fa630cSAmit Kucheria type = "passive"; 4549d2fa630cSAmit Kucheria }; 4550d2fa630cSAmit Kucheria 45511364acc3SKrzysztof Kozlowski cpu4_top_crit: cpu-crit { 4552d2fa630cSAmit Kucheria temperature = <110000>; 4553d2fa630cSAmit Kucheria hysteresis = <1000>; 4554d2fa630cSAmit Kucheria type = "critical"; 4555d2fa630cSAmit Kucheria }; 4556d2fa630cSAmit Kucheria }; 4557d2fa630cSAmit Kucheria 4558d2fa630cSAmit Kucheria cooling-maps { 4559d2fa630cSAmit Kucheria map0 { 4560d2fa630cSAmit Kucheria trip = <&cpu4_top_alert0>; 4561d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4562d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4563d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4564d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4565d2fa630cSAmit Kucheria }; 4566d2fa630cSAmit Kucheria map1 { 4567d2fa630cSAmit Kucheria trip = <&cpu4_top_alert1>; 4568d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4569d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4570d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4571d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4572d2fa630cSAmit Kucheria }; 4573d2fa630cSAmit Kucheria }; 4574d2fa630cSAmit Kucheria }; 4575d2fa630cSAmit Kucheria 4576d2fa630cSAmit Kucheria cpu5-top-thermal { 4577d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4578d2fa630cSAmit Kucheria polling-delay = <1000>; 4579d2fa630cSAmit Kucheria 4580d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 8>; 4581d2fa630cSAmit Kucheria 4582d2fa630cSAmit Kucheria trips { 4583d2fa630cSAmit Kucheria cpu5_top_alert0: trip-point0 { 4584d2fa630cSAmit Kucheria temperature = <90000>; 4585d2fa630cSAmit Kucheria hysteresis = <2000>; 4586d2fa630cSAmit Kucheria type = "passive"; 4587d2fa630cSAmit Kucheria }; 4588d2fa630cSAmit Kucheria 4589d2fa630cSAmit Kucheria cpu5_top_alert1: trip-point1 { 4590d2fa630cSAmit Kucheria temperature = <95000>; 4591d2fa630cSAmit Kucheria hysteresis = <2000>; 4592d2fa630cSAmit Kucheria type = "passive"; 4593d2fa630cSAmit Kucheria }; 4594d2fa630cSAmit Kucheria 45951364acc3SKrzysztof Kozlowski cpu5_top_crit: cpu-crit { 4596d2fa630cSAmit Kucheria temperature = <110000>; 4597d2fa630cSAmit Kucheria hysteresis = <1000>; 4598d2fa630cSAmit Kucheria type = "critical"; 4599d2fa630cSAmit Kucheria }; 4600d2fa630cSAmit Kucheria }; 4601d2fa630cSAmit Kucheria 4602d2fa630cSAmit Kucheria cooling-maps { 4603d2fa630cSAmit Kucheria map0 { 4604d2fa630cSAmit Kucheria trip = <&cpu5_top_alert0>; 4605d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4606d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4607d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4608d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4609d2fa630cSAmit Kucheria }; 4610d2fa630cSAmit Kucheria map1 { 4611d2fa630cSAmit Kucheria trip = <&cpu5_top_alert1>; 4612d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4613d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4614d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4615d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4616d2fa630cSAmit Kucheria }; 4617d2fa630cSAmit Kucheria }; 4618d2fa630cSAmit Kucheria }; 4619d2fa630cSAmit Kucheria 4620d2fa630cSAmit Kucheria cpu6-top-thermal { 4621d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4622d2fa630cSAmit Kucheria polling-delay = <1000>; 4623d2fa630cSAmit Kucheria 4624d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 9>; 4625d2fa630cSAmit Kucheria 4626d2fa630cSAmit Kucheria trips { 4627d2fa630cSAmit Kucheria cpu6_top_alert0: trip-point0 { 4628d2fa630cSAmit Kucheria temperature = <90000>; 4629d2fa630cSAmit Kucheria hysteresis = <2000>; 4630d2fa630cSAmit Kucheria type = "passive"; 4631d2fa630cSAmit Kucheria }; 4632d2fa630cSAmit Kucheria 4633d2fa630cSAmit Kucheria cpu6_top_alert1: trip-point1 { 4634d2fa630cSAmit Kucheria temperature = <95000>; 4635d2fa630cSAmit Kucheria hysteresis = <2000>; 4636d2fa630cSAmit Kucheria type = "passive"; 4637d2fa630cSAmit Kucheria }; 4638d2fa630cSAmit Kucheria 46391364acc3SKrzysztof Kozlowski cpu6_top_crit: cpu-crit { 4640d2fa630cSAmit Kucheria temperature = <110000>; 4641d2fa630cSAmit Kucheria hysteresis = <1000>; 4642d2fa630cSAmit Kucheria type = "critical"; 4643d2fa630cSAmit Kucheria }; 4644d2fa630cSAmit Kucheria }; 4645d2fa630cSAmit Kucheria 4646d2fa630cSAmit Kucheria cooling-maps { 4647d2fa630cSAmit Kucheria map0 { 4648d2fa630cSAmit Kucheria trip = <&cpu6_top_alert0>; 4649d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4650d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4651d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4652d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4653d2fa630cSAmit Kucheria }; 4654d2fa630cSAmit Kucheria map1 { 4655d2fa630cSAmit Kucheria trip = <&cpu6_top_alert1>; 4656d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4657d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4658d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4659d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4660d2fa630cSAmit Kucheria }; 4661d2fa630cSAmit Kucheria }; 4662d2fa630cSAmit Kucheria }; 4663d2fa630cSAmit Kucheria 4664d2fa630cSAmit Kucheria cpu7-top-thermal { 4665d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4666d2fa630cSAmit Kucheria polling-delay = <1000>; 4667d2fa630cSAmit Kucheria 4668d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 10>; 4669d2fa630cSAmit Kucheria 4670d2fa630cSAmit Kucheria trips { 4671d2fa630cSAmit Kucheria cpu7_top_alert0: trip-point0 { 4672d2fa630cSAmit Kucheria temperature = <90000>; 4673d2fa630cSAmit Kucheria hysteresis = <2000>; 4674d2fa630cSAmit Kucheria type = "passive"; 4675d2fa630cSAmit Kucheria }; 4676d2fa630cSAmit Kucheria 4677d2fa630cSAmit Kucheria cpu7_top_alert1: trip-point1 { 4678d2fa630cSAmit Kucheria temperature = <95000>; 4679d2fa630cSAmit Kucheria hysteresis = <2000>; 4680d2fa630cSAmit Kucheria type = "passive"; 4681d2fa630cSAmit Kucheria }; 4682d2fa630cSAmit Kucheria 46831364acc3SKrzysztof Kozlowski cpu7_top_crit: cpu-crit { 4684d2fa630cSAmit Kucheria temperature = <110000>; 4685d2fa630cSAmit Kucheria hysteresis = <1000>; 4686d2fa630cSAmit Kucheria type = "critical"; 4687d2fa630cSAmit Kucheria }; 4688d2fa630cSAmit Kucheria }; 4689d2fa630cSAmit Kucheria 4690d2fa630cSAmit Kucheria cooling-maps { 4691d2fa630cSAmit Kucheria map0 { 4692d2fa630cSAmit Kucheria trip = <&cpu7_top_alert0>; 4693d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4694d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4695d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4696d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4697d2fa630cSAmit Kucheria }; 4698d2fa630cSAmit Kucheria map1 { 4699d2fa630cSAmit Kucheria trip = <&cpu7_top_alert1>; 4700d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4701d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4702d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4703d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4704d2fa630cSAmit Kucheria }; 4705d2fa630cSAmit Kucheria }; 4706d2fa630cSAmit Kucheria }; 4707d2fa630cSAmit Kucheria 4708d2fa630cSAmit Kucheria cpu4-bottom-thermal { 4709d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4710d2fa630cSAmit Kucheria polling-delay = <1000>; 4711d2fa630cSAmit Kucheria 4712d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 11>; 4713d2fa630cSAmit Kucheria 4714d2fa630cSAmit Kucheria trips { 4715d2fa630cSAmit Kucheria cpu4_bottom_alert0: trip-point0 { 4716d2fa630cSAmit Kucheria temperature = <90000>; 4717d2fa630cSAmit Kucheria hysteresis = <2000>; 4718d2fa630cSAmit Kucheria type = "passive"; 4719d2fa630cSAmit Kucheria }; 4720d2fa630cSAmit Kucheria 4721d2fa630cSAmit Kucheria cpu4_bottom_alert1: trip-point1 { 4722d2fa630cSAmit Kucheria temperature = <95000>; 4723d2fa630cSAmit Kucheria hysteresis = <2000>; 4724d2fa630cSAmit Kucheria type = "passive"; 4725d2fa630cSAmit Kucheria }; 4726d2fa630cSAmit Kucheria 47271364acc3SKrzysztof Kozlowski cpu4_bottom_crit: cpu-crit { 4728d2fa630cSAmit Kucheria temperature = <110000>; 4729d2fa630cSAmit Kucheria hysteresis = <1000>; 4730d2fa630cSAmit Kucheria type = "critical"; 4731d2fa630cSAmit Kucheria }; 4732d2fa630cSAmit Kucheria }; 4733d2fa630cSAmit Kucheria 4734d2fa630cSAmit Kucheria cooling-maps { 4735d2fa630cSAmit Kucheria map0 { 4736d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert0>; 4737d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4738d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4739d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4740d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4741d2fa630cSAmit Kucheria }; 4742d2fa630cSAmit Kucheria map1 { 4743d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert1>; 4744d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4745d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4746d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4747d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4748d2fa630cSAmit Kucheria }; 4749d2fa630cSAmit Kucheria }; 4750d2fa630cSAmit Kucheria }; 4751d2fa630cSAmit Kucheria 4752d2fa630cSAmit Kucheria cpu5-bottom-thermal { 4753d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4754d2fa630cSAmit Kucheria polling-delay = <1000>; 4755d2fa630cSAmit Kucheria 4756d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 12>; 4757d2fa630cSAmit Kucheria 4758d2fa630cSAmit Kucheria trips { 4759d2fa630cSAmit Kucheria cpu5_bottom_alert0: trip-point0 { 4760d2fa630cSAmit Kucheria temperature = <90000>; 4761d2fa630cSAmit Kucheria hysteresis = <2000>; 4762d2fa630cSAmit Kucheria type = "passive"; 4763d2fa630cSAmit Kucheria }; 4764d2fa630cSAmit Kucheria 4765d2fa630cSAmit Kucheria cpu5_bottom_alert1: trip-point1 { 4766d2fa630cSAmit Kucheria temperature = <95000>; 4767d2fa630cSAmit Kucheria hysteresis = <2000>; 4768d2fa630cSAmit Kucheria type = "passive"; 4769d2fa630cSAmit Kucheria }; 4770d2fa630cSAmit Kucheria 47711364acc3SKrzysztof Kozlowski cpu5_bottom_crit: cpu-crit { 4772d2fa630cSAmit Kucheria temperature = <110000>; 4773d2fa630cSAmit Kucheria hysteresis = <1000>; 4774d2fa630cSAmit Kucheria type = "critical"; 4775d2fa630cSAmit Kucheria }; 4776d2fa630cSAmit Kucheria }; 4777d2fa630cSAmit Kucheria 4778d2fa630cSAmit Kucheria cooling-maps { 4779d2fa630cSAmit Kucheria map0 { 4780d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert0>; 4781d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4782d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4783d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4784d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4785d2fa630cSAmit Kucheria }; 4786d2fa630cSAmit Kucheria map1 { 4787d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert1>; 4788d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4789d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4790d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4791d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4792d2fa630cSAmit Kucheria }; 4793d2fa630cSAmit Kucheria }; 4794d2fa630cSAmit Kucheria }; 4795d2fa630cSAmit Kucheria 4796d2fa630cSAmit Kucheria cpu6-bottom-thermal { 4797d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4798d2fa630cSAmit Kucheria polling-delay = <1000>; 4799d2fa630cSAmit Kucheria 4800d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 13>; 4801d2fa630cSAmit Kucheria 4802d2fa630cSAmit Kucheria trips { 4803d2fa630cSAmit Kucheria cpu6_bottom_alert0: trip-point0 { 4804d2fa630cSAmit Kucheria temperature = <90000>; 4805d2fa630cSAmit Kucheria hysteresis = <2000>; 4806d2fa630cSAmit Kucheria type = "passive"; 4807d2fa630cSAmit Kucheria }; 4808d2fa630cSAmit Kucheria 4809d2fa630cSAmit Kucheria cpu6_bottom_alert1: trip-point1 { 4810d2fa630cSAmit Kucheria temperature = <95000>; 4811d2fa630cSAmit Kucheria hysteresis = <2000>; 4812d2fa630cSAmit Kucheria type = "passive"; 4813d2fa630cSAmit Kucheria }; 4814d2fa630cSAmit Kucheria 48151364acc3SKrzysztof Kozlowski cpu6_bottom_crit: cpu-crit { 4816d2fa630cSAmit Kucheria temperature = <110000>; 4817d2fa630cSAmit Kucheria hysteresis = <1000>; 4818d2fa630cSAmit Kucheria type = "critical"; 4819d2fa630cSAmit Kucheria }; 4820d2fa630cSAmit Kucheria }; 4821d2fa630cSAmit Kucheria 4822d2fa630cSAmit Kucheria cooling-maps { 4823d2fa630cSAmit Kucheria map0 { 4824d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert0>; 4825d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4826d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4827d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4828d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4829d2fa630cSAmit Kucheria }; 4830d2fa630cSAmit Kucheria map1 { 4831d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert1>; 4832d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4833d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4834d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4835d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4836d2fa630cSAmit Kucheria }; 4837d2fa630cSAmit Kucheria }; 4838d2fa630cSAmit Kucheria }; 4839d2fa630cSAmit Kucheria 4840d2fa630cSAmit Kucheria cpu7-bottom-thermal { 4841d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4842d2fa630cSAmit Kucheria polling-delay = <1000>; 4843d2fa630cSAmit Kucheria 4844d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 14>; 4845d2fa630cSAmit Kucheria 4846d2fa630cSAmit Kucheria trips { 4847d2fa630cSAmit Kucheria cpu7_bottom_alert0: trip-point0 { 4848d2fa630cSAmit Kucheria temperature = <90000>; 4849d2fa630cSAmit Kucheria hysteresis = <2000>; 4850d2fa630cSAmit Kucheria type = "passive"; 4851d2fa630cSAmit Kucheria }; 4852d2fa630cSAmit Kucheria 4853d2fa630cSAmit Kucheria cpu7_bottom_alert1: trip-point1 { 4854d2fa630cSAmit Kucheria temperature = <95000>; 4855d2fa630cSAmit Kucheria hysteresis = <2000>; 4856d2fa630cSAmit Kucheria type = "passive"; 4857d2fa630cSAmit Kucheria }; 4858d2fa630cSAmit Kucheria 48591364acc3SKrzysztof Kozlowski cpu7_bottom_crit: cpu-crit { 4860d2fa630cSAmit Kucheria temperature = <110000>; 4861d2fa630cSAmit Kucheria hysteresis = <1000>; 4862d2fa630cSAmit Kucheria type = "critical"; 4863d2fa630cSAmit Kucheria }; 4864d2fa630cSAmit Kucheria }; 4865d2fa630cSAmit Kucheria 4866d2fa630cSAmit Kucheria cooling-maps { 4867d2fa630cSAmit Kucheria map0 { 4868d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert0>; 4869d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4870d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4871d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4872d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4873d2fa630cSAmit Kucheria }; 4874d2fa630cSAmit Kucheria map1 { 4875d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert1>; 4876d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4877d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4878d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4879d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4880d2fa630cSAmit Kucheria }; 4881d2fa630cSAmit Kucheria }; 4882d2fa630cSAmit Kucheria }; 4883d2fa630cSAmit Kucheria 4884d2fa630cSAmit Kucheria aoss0-thermal { 4885d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4886d2fa630cSAmit Kucheria polling-delay = <1000>; 4887d2fa630cSAmit Kucheria 4888d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 0>; 4889d2fa630cSAmit Kucheria 4890d2fa630cSAmit Kucheria trips { 4891d2fa630cSAmit Kucheria aoss0_alert0: trip-point0 { 4892d2fa630cSAmit Kucheria temperature = <90000>; 4893d2fa630cSAmit Kucheria hysteresis = <2000>; 4894d2fa630cSAmit Kucheria type = "hot"; 4895d2fa630cSAmit Kucheria }; 4896d2fa630cSAmit Kucheria }; 4897d2fa630cSAmit Kucheria }; 4898d2fa630cSAmit Kucheria 4899d2fa630cSAmit Kucheria cluster0-thermal { 4900d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4901d2fa630cSAmit Kucheria polling-delay = <1000>; 4902d2fa630cSAmit Kucheria 4903d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 5>; 4904d2fa630cSAmit Kucheria 4905d2fa630cSAmit Kucheria trips { 4906d2fa630cSAmit Kucheria cluster0_alert0: trip-point0 { 4907d2fa630cSAmit Kucheria temperature = <90000>; 4908d2fa630cSAmit Kucheria hysteresis = <2000>; 4909d2fa630cSAmit Kucheria type = "hot"; 4910d2fa630cSAmit Kucheria }; 4911d2fa630cSAmit Kucheria cluster0_crit: cluster0_crit { 4912d2fa630cSAmit Kucheria temperature = <110000>; 4913d2fa630cSAmit Kucheria hysteresis = <2000>; 4914d2fa630cSAmit Kucheria type = "critical"; 4915d2fa630cSAmit Kucheria }; 4916d2fa630cSAmit Kucheria }; 4917d2fa630cSAmit Kucheria }; 4918d2fa630cSAmit Kucheria 4919d2fa630cSAmit Kucheria cluster1-thermal { 4920d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4921d2fa630cSAmit Kucheria polling-delay = <1000>; 4922d2fa630cSAmit Kucheria 4923d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 6>; 4924d2fa630cSAmit Kucheria 4925d2fa630cSAmit Kucheria trips { 4926d2fa630cSAmit Kucheria cluster1_alert0: trip-point0 { 4927d2fa630cSAmit Kucheria temperature = <90000>; 4928d2fa630cSAmit Kucheria hysteresis = <2000>; 4929d2fa630cSAmit Kucheria type = "hot"; 4930d2fa630cSAmit Kucheria }; 4931d2fa630cSAmit Kucheria cluster1_crit: cluster1_crit { 4932d2fa630cSAmit Kucheria temperature = <110000>; 4933d2fa630cSAmit Kucheria hysteresis = <2000>; 4934d2fa630cSAmit Kucheria type = "critical"; 4935d2fa630cSAmit Kucheria }; 4936d2fa630cSAmit Kucheria }; 4937d2fa630cSAmit Kucheria }; 4938d2fa630cSAmit Kucheria 49397be1c395SDavid Heidelberg gpu-top-thermal { 4940d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4941d2fa630cSAmit Kucheria polling-delay = <1000>; 4942d2fa630cSAmit Kucheria 4943d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 15>; 4944d2fa630cSAmit Kucheria 4945d2fa630cSAmit Kucheria trips { 4946d2fa630cSAmit Kucheria gpu1_alert0: trip-point0 { 4947d2fa630cSAmit Kucheria temperature = <90000>; 4948d2fa630cSAmit Kucheria hysteresis = <2000>; 4949d2fa630cSAmit Kucheria type = "hot"; 4950d2fa630cSAmit Kucheria }; 4951d2fa630cSAmit Kucheria }; 4952d2fa630cSAmit Kucheria }; 4953d2fa630cSAmit Kucheria 4954d2fa630cSAmit Kucheria aoss1-thermal { 4955d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4956d2fa630cSAmit Kucheria polling-delay = <1000>; 4957d2fa630cSAmit Kucheria 4958d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 0>; 4959d2fa630cSAmit Kucheria 4960d2fa630cSAmit Kucheria trips { 4961d2fa630cSAmit Kucheria aoss1_alert0: trip-point0 { 4962d2fa630cSAmit Kucheria temperature = <90000>; 4963d2fa630cSAmit Kucheria hysteresis = <2000>; 4964d2fa630cSAmit Kucheria type = "hot"; 4965d2fa630cSAmit Kucheria }; 4966d2fa630cSAmit Kucheria }; 4967d2fa630cSAmit Kucheria }; 4968d2fa630cSAmit Kucheria 4969d2fa630cSAmit Kucheria wlan-thermal { 4970d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4971d2fa630cSAmit Kucheria polling-delay = <1000>; 4972d2fa630cSAmit Kucheria 4973d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 1>; 4974d2fa630cSAmit Kucheria 4975d2fa630cSAmit Kucheria trips { 4976d2fa630cSAmit Kucheria wlan_alert0: trip-point0 { 4977d2fa630cSAmit Kucheria temperature = <90000>; 4978d2fa630cSAmit Kucheria hysteresis = <2000>; 4979d2fa630cSAmit Kucheria type = "hot"; 4980d2fa630cSAmit Kucheria }; 4981d2fa630cSAmit Kucheria }; 4982d2fa630cSAmit Kucheria }; 4983d2fa630cSAmit Kucheria 4984d2fa630cSAmit Kucheria video-thermal { 4985d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4986d2fa630cSAmit Kucheria polling-delay = <1000>; 4987d2fa630cSAmit Kucheria 4988d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 2>; 4989d2fa630cSAmit Kucheria 4990d2fa630cSAmit Kucheria trips { 4991d2fa630cSAmit Kucheria video_alert0: trip-point0 { 4992d2fa630cSAmit Kucheria temperature = <90000>; 4993d2fa630cSAmit Kucheria hysteresis = <2000>; 4994d2fa630cSAmit Kucheria type = "hot"; 4995d2fa630cSAmit Kucheria }; 4996d2fa630cSAmit Kucheria }; 4997d2fa630cSAmit Kucheria }; 4998d2fa630cSAmit Kucheria 4999d2fa630cSAmit Kucheria mem-thermal { 5000d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5001d2fa630cSAmit Kucheria polling-delay = <1000>; 5002d2fa630cSAmit Kucheria 5003d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 3>; 5004d2fa630cSAmit Kucheria 5005d2fa630cSAmit Kucheria trips { 5006d2fa630cSAmit Kucheria mem_alert0: trip-point0 { 5007d2fa630cSAmit Kucheria temperature = <90000>; 5008d2fa630cSAmit Kucheria hysteresis = <2000>; 5009d2fa630cSAmit Kucheria type = "hot"; 5010d2fa630cSAmit Kucheria }; 5011d2fa630cSAmit Kucheria }; 5012d2fa630cSAmit Kucheria }; 5013d2fa630cSAmit Kucheria 5014d2fa630cSAmit Kucheria q6-hvx-thermal { 5015d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5016d2fa630cSAmit Kucheria polling-delay = <1000>; 5017d2fa630cSAmit Kucheria 5018d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 4>; 5019d2fa630cSAmit Kucheria 5020d2fa630cSAmit Kucheria trips { 5021d2fa630cSAmit Kucheria q6_hvx_alert0: trip-point0 { 5022d2fa630cSAmit Kucheria temperature = <90000>; 5023d2fa630cSAmit Kucheria hysteresis = <2000>; 5024d2fa630cSAmit Kucheria type = "hot"; 5025d2fa630cSAmit Kucheria }; 5026d2fa630cSAmit Kucheria }; 5027d2fa630cSAmit Kucheria }; 5028d2fa630cSAmit Kucheria 5029d2fa630cSAmit Kucheria camera-thermal { 5030d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5031d2fa630cSAmit Kucheria polling-delay = <1000>; 5032d2fa630cSAmit Kucheria 5033d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 5>; 5034d2fa630cSAmit Kucheria 5035d2fa630cSAmit Kucheria trips { 5036d2fa630cSAmit Kucheria camera_alert0: trip-point0 { 5037d2fa630cSAmit Kucheria temperature = <90000>; 5038d2fa630cSAmit Kucheria hysteresis = <2000>; 5039d2fa630cSAmit Kucheria type = "hot"; 5040d2fa630cSAmit Kucheria }; 5041d2fa630cSAmit Kucheria }; 5042d2fa630cSAmit Kucheria }; 5043d2fa630cSAmit Kucheria 5044d2fa630cSAmit Kucheria compute-thermal { 5045d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5046d2fa630cSAmit Kucheria polling-delay = <1000>; 5047d2fa630cSAmit Kucheria 5048d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 6>; 5049d2fa630cSAmit Kucheria 5050d2fa630cSAmit Kucheria trips { 5051d2fa630cSAmit Kucheria compute_alert0: trip-point0 { 5052d2fa630cSAmit Kucheria temperature = <90000>; 5053d2fa630cSAmit Kucheria hysteresis = <2000>; 5054d2fa630cSAmit Kucheria type = "hot"; 5055d2fa630cSAmit Kucheria }; 5056d2fa630cSAmit Kucheria }; 5057d2fa630cSAmit Kucheria }; 5058d2fa630cSAmit Kucheria 5059d2fa630cSAmit Kucheria modem-thermal { 5060d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5061d2fa630cSAmit Kucheria polling-delay = <1000>; 5062d2fa630cSAmit Kucheria 5063d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 7>; 5064d2fa630cSAmit Kucheria 5065d2fa630cSAmit Kucheria trips { 5066d2fa630cSAmit Kucheria modem_alert0: trip-point0 { 5067d2fa630cSAmit Kucheria temperature = <90000>; 5068d2fa630cSAmit Kucheria hysteresis = <2000>; 5069d2fa630cSAmit Kucheria type = "hot"; 5070d2fa630cSAmit Kucheria }; 5071d2fa630cSAmit Kucheria }; 5072d2fa630cSAmit Kucheria }; 5073d2fa630cSAmit Kucheria 5074d2fa630cSAmit Kucheria npu-thermal { 5075d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5076d2fa630cSAmit Kucheria polling-delay = <1000>; 5077d2fa630cSAmit Kucheria 5078d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 8>; 5079d2fa630cSAmit Kucheria 5080d2fa630cSAmit Kucheria trips { 5081d2fa630cSAmit Kucheria npu_alert0: trip-point0 { 5082d2fa630cSAmit Kucheria temperature = <90000>; 5083d2fa630cSAmit Kucheria hysteresis = <2000>; 5084d2fa630cSAmit Kucheria type = "hot"; 5085d2fa630cSAmit Kucheria }; 5086d2fa630cSAmit Kucheria }; 5087d2fa630cSAmit Kucheria }; 5088d2fa630cSAmit Kucheria 5089d2fa630cSAmit Kucheria modem-vec-thermal { 5090d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5091d2fa630cSAmit Kucheria polling-delay = <1000>; 5092d2fa630cSAmit Kucheria 5093d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 9>; 5094d2fa630cSAmit Kucheria 5095d2fa630cSAmit Kucheria trips { 5096d2fa630cSAmit Kucheria modem_vec_alert0: trip-point0 { 5097d2fa630cSAmit Kucheria temperature = <90000>; 5098d2fa630cSAmit Kucheria hysteresis = <2000>; 5099d2fa630cSAmit Kucheria type = "hot"; 5100d2fa630cSAmit Kucheria }; 5101d2fa630cSAmit Kucheria }; 5102d2fa630cSAmit Kucheria }; 5103d2fa630cSAmit Kucheria 5104d2fa630cSAmit Kucheria modem-scl-thermal { 5105d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5106d2fa630cSAmit Kucheria polling-delay = <1000>; 5107d2fa630cSAmit Kucheria 5108d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 10>; 5109d2fa630cSAmit Kucheria 5110d2fa630cSAmit Kucheria trips { 5111d2fa630cSAmit Kucheria modem_scl_alert0: trip-point0 { 5112d2fa630cSAmit Kucheria temperature = <90000>; 5113d2fa630cSAmit Kucheria hysteresis = <2000>; 5114d2fa630cSAmit Kucheria type = "hot"; 5115d2fa630cSAmit Kucheria }; 5116d2fa630cSAmit Kucheria }; 5117d2fa630cSAmit Kucheria }; 5118d2fa630cSAmit Kucheria 51197be1c395SDavid Heidelberg gpu-bottom-thermal { 5120d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5121d2fa630cSAmit Kucheria polling-delay = <1000>; 5122d2fa630cSAmit Kucheria 5123d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 11>; 5124d2fa630cSAmit Kucheria 5125d2fa630cSAmit Kucheria trips { 5126d2fa630cSAmit Kucheria gpu2_alert0: trip-point0 { 5127d2fa630cSAmit Kucheria temperature = <90000>; 5128d2fa630cSAmit Kucheria hysteresis = <2000>; 5129d2fa630cSAmit Kucheria type = "hot"; 5130d2fa630cSAmit Kucheria }; 5131d2fa630cSAmit Kucheria }; 5132d2fa630cSAmit Kucheria }; 5133d2fa630cSAmit Kucheria }; 5134e13c6d14SVinod Koul}; 5135