1e13c6d14SVinod Koul// SPDX-License-Identifier: BSD-3-Clause 2e13c6d14SVinod Koul/* 3e13c6d14SVinod Koul * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4e13c6d14SVinod Koul * Copyright (c) 2019, Linaro Limited 5e13c6d14SVinod Koul */ 6e13c6d14SVinod Koul 705006290SFelipe Balbi#include <dt-bindings/dma/qcom-gpi.h> 8e13c6d14SVinod Koul#include <dt-bindings/interrupt-controller/arm-gic.h> 9017e7856SSibi Sankar#include <dt-bindings/power/qcom-rpmpd.h> 10e13c6d14SVinod Koul#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11e13c6d14SVinod Koul#include <dt-bindings/clock/qcom,rpmh.h> 1298874a46SKonrad Dybcio#include <dt-bindings/clock/qcom,dispcc-sm8150.h> 13d6f55763SVinod Koul#include <dt-bindings/clock/qcom,gcc-sm8150.h> 14f1269916SJonathan Marek#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 15a6d435c1SSibi Sankar#include <dt-bindings/interconnect/qcom,osm-l3.h> 162b6187abSThara Gopinath#include <dt-bindings/interconnect/qcom,sm8150.h> 17d2fa630cSAmit Kucheria#include <dt-bindings/thermal/thermal.h> 18e13c6d14SVinod Koul 19e13c6d14SVinod Koul/ { 20e13c6d14SVinod Koul interrupt-parent = <&intc>; 21e13c6d14SVinod Koul 22e13c6d14SVinod Koul #address-cells = <2>; 23e13c6d14SVinod Koul #size-cells = <2>; 24e13c6d14SVinod Koul 25e13c6d14SVinod Koul chosen { }; 26e13c6d14SVinod Koul 27e13c6d14SVinod Koul clocks { 28e13c6d14SVinod Koul xo_board: xo-board { 29e13c6d14SVinod Koul compatible = "fixed-clock"; 30e13c6d14SVinod Koul #clock-cells = <0>; 31e13c6d14SVinod Koul clock-frequency = <38400000>; 32e13c6d14SVinod Koul clock-output-names = "xo_board"; 33e13c6d14SVinod Koul }; 34e13c6d14SVinod Koul 35e13c6d14SVinod Koul sleep_clk: sleep-clk { 36e13c6d14SVinod Koul compatible = "fixed-clock"; 37e13c6d14SVinod Koul #clock-cells = <0>; 38e13c6d14SVinod Koul clock-frequency = <32764>; 39e13c6d14SVinod Koul clock-output-names = "sleep_clk"; 40e13c6d14SVinod Koul }; 41e13c6d14SVinod Koul }; 42e13c6d14SVinod Koul 43e13c6d14SVinod Koul cpus { 44e13c6d14SVinod Koul #address-cells = <2>; 45e13c6d14SVinod Koul #size-cells = <0>; 46e13c6d14SVinod Koul 47e13c6d14SVinod Koul CPU0: cpu@0 { 48e13c6d14SVinod Koul device_type = "cpu"; 49e13c6d14SVinod Koul compatible = "qcom,kryo485"; 50e13c6d14SVinod Koul reg = <0x0 0x0>; 51e13c6d14SVinod Koul enable-method = "psci"; 525b2dae72SDanny Lin capacity-dmips-mhz = <488>; 535b2dae72SDanny Lin dynamic-power-coefficient = <232>; 54e13c6d14SVinod Koul next-level-cache = <&L2_0>; 55fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 562b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 572b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 582b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 59b2e3f897SDanny Lin power-domains = <&CPU_PD0>; 60b2e3f897SDanny Lin power-domain-names = "psci"; 61d2fa630cSAmit Kucheria #cooling-cells = <2>; 62e13c6d14SVinod Koul L2_0: l2-cache { 63e13c6d14SVinod Koul compatible = "cache"; 649435294cSPierre Gondois cache-level = <2>; 65e13c6d14SVinod Koul next-level-cache = <&L3_0>; 66e13c6d14SVinod Koul L3_0: l3-cache { 67e13c6d14SVinod Koul compatible = "cache"; 689435294cSPierre Gondois cache-level = <3>; 69e13c6d14SVinod Koul }; 70e13c6d14SVinod Koul }; 71e13c6d14SVinod Koul }; 72e13c6d14SVinod Koul 73e13c6d14SVinod Koul CPU1: cpu@100 { 74e13c6d14SVinod Koul device_type = "cpu"; 75e13c6d14SVinod Koul compatible = "qcom,kryo485"; 76e13c6d14SVinod Koul reg = <0x0 0x100>; 77e13c6d14SVinod Koul enable-method = "psci"; 785b2dae72SDanny Lin capacity-dmips-mhz = <488>; 795b2dae72SDanny Lin dynamic-power-coefficient = <232>; 80e13c6d14SVinod Koul next-level-cache = <&L2_100>; 81fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 822b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 832b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 842b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 85b2e3f897SDanny Lin power-domains = <&CPU_PD1>; 86b2e3f897SDanny Lin power-domain-names = "psci"; 87d2fa630cSAmit Kucheria #cooling-cells = <2>; 88e13c6d14SVinod Koul L2_100: l2-cache { 89e13c6d14SVinod Koul compatible = "cache"; 909435294cSPierre Gondois cache-level = <2>; 91e13c6d14SVinod Koul next-level-cache = <&L3_0>; 92e13c6d14SVinod Koul }; 93e13c6d14SVinod Koul 94e13c6d14SVinod Koul }; 95e13c6d14SVinod Koul 96e13c6d14SVinod Koul CPU2: cpu@200 { 97e13c6d14SVinod Koul device_type = "cpu"; 98e13c6d14SVinod Koul compatible = "qcom,kryo485"; 99e13c6d14SVinod Koul reg = <0x0 0x200>; 100e13c6d14SVinod Koul enable-method = "psci"; 1015b2dae72SDanny Lin capacity-dmips-mhz = <488>; 1025b2dae72SDanny Lin dynamic-power-coefficient = <232>; 103e13c6d14SVinod Koul next-level-cache = <&L2_200>; 104fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1052b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1062b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1072b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 108b2e3f897SDanny Lin power-domains = <&CPU_PD2>; 109b2e3f897SDanny Lin power-domain-names = "psci"; 110d2fa630cSAmit Kucheria #cooling-cells = <2>; 111e13c6d14SVinod Koul L2_200: l2-cache { 112e13c6d14SVinod Koul compatible = "cache"; 1139435294cSPierre Gondois cache-level = <2>; 114e13c6d14SVinod Koul next-level-cache = <&L3_0>; 115e13c6d14SVinod Koul }; 116e13c6d14SVinod Koul }; 117e13c6d14SVinod Koul 118e13c6d14SVinod Koul CPU3: cpu@300 { 119e13c6d14SVinod Koul device_type = "cpu"; 120e13c6d14SVinod Koul compatible = "qcom,kryo485"; 121e13c6d14SVinod Koul reg = <0x0 0x300>; 122e13c6d14SVinod Koul enable-method = "psci"; 1235b2dae72SDanny Lin capacity-dmips-mhz = <488>; 1245b2dae72SDanny Lin dynamic-power-coefficient = <232>; 125e13c6d14SVinod Koul next-level-cache = <&L2_300>; 126fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1272b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 1282b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1292b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 130b2e3f897SDanny Lin power-domains = <&CPU_PD3>; 131b2e3f897SDanny Lin power-domain-names = "psci"; 132d2fa630cSAmit Kucheria #cooling-cells = <2>; 133e13c6d14SVinod Koul L2_300: l2-cache { 134e13c6d14SVinod Koul compatible = "cache"; 1359435294cSPierre Gondois cache-level = <2>; 136e13c6d14SVinod Koul next-level-cache = <&L3_0>; 137e13c6d14SVinod Koul }; 138e13c6d14SVinod Koul }; 139e13c6d14SVinod Koul 140e13c6d14SVinod Koul CPU4: cpu@400 { 141e13c6d14SVinod Koul device_type = "cpu"; 142e13c6d14SVinod Koul compatible = "qcom,kryo485"; 143e13c6d14SVinod Koul reg = <0x0 0x400>; 144e13c6d14SVinod Koul enable-method = "psci"; 1455b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1465b2dae72SDanny Lin dynamic-power-coefficient = <369>; 147e13c6d14SVinod Koul next-level-cache = <&L2_400>; 148fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1492b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1502b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1512b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 152b2e3f897SDanny Lin power-domains = <&CPU_PD4>; 153b2e3f897SDanny Lin power-domain-names = "psci"; 154d2fa630cSAmit Kucheria #cooling-cells = <2>; 155e13c6d14SVinod Koul L2_400: l2-cache { 156e13c6d14SVinod Koul compatible = "cache"; 1579435294cSPierre Gondois cache-level = <2>; 158e13c6d14SVinod Koul next-level-cache = <&L3_0>; 159e13c6d14SVinod Koul }; 160e13c6d14SVinod Koul }; 161e13c6d14SVinod Koul 162e13c6d14SVinod Koul CPU5: cpu@500 { 163e13c6d14SVinod Koul device_type = "cpu"; 164e13c6d14SVinod Koul compatible = "qcom,kryo485"; 165e13c6d14SVinod Koul reg = <0x0 0x500>; 166e13c6d14SVinod Koul enable-method = "psci"; 1675b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1685b2dae72SDanny Lin dynamic-power-coefficient = <369>; 169e13c6d14SVinod Koul next-level-cache = <&L2_500>; 170fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1712b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1722b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1732b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 174b2e3f897SDanny Lin power-domains = <&CPU_PD5>; 175b2e3f897SDanny Lin power-domain-names = "psci"; 176d2fa630cSAmit Kucheria #cooling-cells = <2>; 177e13c6d14SVinod Koul L2_500: l2-cache { 178e13c6d14SVinod Koul compatible = "cache"; 1799435294cSPierre Gondois cache-level = <2>; 180e13c6d14SVinod Koul next-level-cache = <&L3_0>; 181e13c6d14SVinod Koul }; 182e13c6d14SVinod Koul }; 183e13c6d14SVinod Koul 184e13c6d14SVinod Koul CPU6: cpu@600 { 185e13c6d14SVinod Koul device_type = "cpu"; 186e13c6d14SVinod Koul compatible = "qcom,kryo485"; 187e13c6d14SVinod Koul reg = <0x0 0x600>; 188e13c6d14SVinod Koul enable-method = "psci"; 1895b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1905b2dae72SDanny Lin dynamic-power-coefficient = <369>; 191e13c6d14SVinod Koul next-level-cache = <&L2_600>; 192fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1932b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 1942b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 1952b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 196b2e3f897SDanny Lin power-domains = <&CPU_PD6>; 197b2e3f897SDanny Lin power-domain-names = "psci"; 198d2fa630cSAmit Kucheria #cooling-cells = <2>; 199e13c6d14SVinod Koul L2_600: l2-cache { 200e13c6d14SVinod Koul compatible = "cache"; 2019435294cSPierre Gondois cache-level = <2>; 202e13c6d14SVinod Koul next-level-cache = <&L3_0>; 203e13c6d14SVinod Koul }; 204e13c6d14SVinod Koul }; 205e13c6d14SVinod Koul 206e13c6d14SVinod Koul CPU7: cpu@700 { 207e13c6d14SVinod Koul device_type = "cpu"; 208e13c6d14SVinod Koul compatible = "qcom,kryo485"; 209e13c6d14SVinod Koul reg = <0x0 0x700>; 210e13c6d14SVinod Koul enable-method = "psci"; 2115b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 2125b2dae72SDanny Lin dynamic-power-coefficient = <421>; 213e13c6d14SVinod Koul next-level-cache = <&L2_700>; 214fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 2>; 2152b6187abSThara Gopinath operating-points-v2 = <&cpu7_opp_table>; 2162b6187abSThara Gopinath interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 2172b6187abSThara Gopinath <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 218b2e3f897SDanny Lin power-domains = <&CPU_PD7>; 219b2e3f897SDanny Lin power-domain-names = "psci"; 220d2fa630cSAmit Kucheria #cooling-cells = <2>; 221e13c6d14SVinod Koul L2_700: l2-cache { 222e13c6d14SVinod Koul compatible = "cache"; 2239435294cSPierre Gondois cache-level = <2>; 224e13c6d14SVinod Koul next-level-cache = <&L3_0>; 225e13c6d14SVinod Koul }; 226e13c6d14SVinod Koul }; 227066d21bcSDanny Lin 228066d21bcSDanny Lin cpu-map { 229066d21bcSDanny Lin cluster0 { 230066d21bcSDanny Lin core0 { 231066d21bcSDanny Lin cpu = <&CPU0>; 232066d21bcSDanny Lin }; 233066d21bcSDanny Lin 234066d21bcSDanny Lin core1 { 235066d21bcSDanny Lin cpu = <&CPU1>; 236066d21bcSDanny Lin }; 237066d21bcSDanny Lin 238066d21bcSDanny Lin core2 { 239066d21bcSDanny Lin cpu = <&CPU2>; 240066d21bcSDanny Lin }; 241066d21bcSDanny Lin 242066d21bcSDanny Lin core3 { 243066d21bcSDanny Lin cpu = <&CPU3>; 244066d21bcSDanny Lin }; 245066d21bcSDanny Lin 246066d21bcSDanny Lin core4 { 247066d21bcSDanny Lin cpu = <&CPU4>; 248066d21bcSDanny Lin }; 249066d21bcSDanny Lin 250066d21bcSDanny Lin core5 { 251066d21bcSDanny Lin cpu = <&CPU5>; 252066d21bcSDanny Lin }; 253066d21bcSDanny Lin 254066d21bcSDanny Lin core6 { 255066d21bcSDanny Lin cpu = <&CPU6>; 256066d21bcSDanny Lin }; 257066d21bcSDanny Lin 258066d21bcSDanny Lin core7 { 259066d21bcSDanny Lin cpu = <&CPU7>; 260066d21bcSDanny Lin }; 261066d21bcSDanny Lin }; 262066d21bcSDanny Lin }; 26381188f58SDanny Lin 26481188f58SDanny Lin idle-states { 26581188f58SDanny Lin entry-method = "psci"; 26681188f58SDanny Lin 26781188f58SDanny Lin LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 26881188f58SDanny Lin compatible = "arm,idle-state"; 26981188f58SDanny Lin idle-state-name = "little-rail-power-collapse"; 27081188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 27181188f58SDanny Lin entry-latency-us = <355>; 27281188f58SDanny Lin exit-latency-us = <909>; 27381188f58SDanny Lin min-residency-us = <3934>; 27481188f58SDanny Lin local-timer-stop; 27581188f58SDanny Lin }; 27681188f58SDanny Lin 27781188f58SDanny Lin BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 27881188f58SDanny Lin compatible = "arm,idle-state"; 27981188f58SDanny Lin idle-state-name = "big-rail-power-collapse"; 28081188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 28181188f58SDanny Lin entry-latency-us = <241>; 28281188f58SDanny Lin exit-latency-us = <1461>; 28381188f58SDanny Lin min-residency-us = <4488>; 28481188f58SDanny Lin local-timer-stop; 28581188f58SDanny Lin }; 286b2e3f897SDanny Lin }; 28781188f58SDanny Lin 288b2e3f897SDanny Lin domain-idle-states { 28981188f58SDanny Lin CLUSTER_SLEEP_0: cluster-sleep-0 { 290b2e3f897SDanny Lin compatible = "domain-idle-state"; 29181188f58SDanny Lin idle-state-name = "cluster-power-collapse"; 292b2e3f897SDanny Lin arm,psci-suspend-param = <0x4100c244>; 29381188f58SDanny Lin entry-latency-us = <3263>; 29481188f58SDanny Lin exit-latency-us = <6562>; 29581188f58SDanny Lin min-residency-us = <9987>; 29681188f58SDanny Lin local-timer-stop; 29781188f58SDanny Lin }; 29881188f58SDanny Lin }; 299e13c6d14SVinod Koul }; 300e13c6d14SVinod Koul 3010e3e6546SKrzysztof Kozlowski cpu0_opp_table: opp-table-cpu0 { 3022b6187abSThara Gopinath compatible = "operating-points-v2"; 3032b6187abSThara Gopinath opp-shared; 3042b6187abSThara Gopinath 3052b6187abSThara Gopinath cpu0_opp1: opp-300000000 { 3062b6187abSThara Gopinath opp-hz = /bits/ 64 <300000000>; 3072b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 3082b6187abSThara Gopinath }; 3092b6187abSThara Gopinath 3102b6187abSThara Gopinath cpu0_opp2: opp-403200000 { 3112b6187abSThara Gopinath opp-hz = /bits/ 64 <403200000>; 3122b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 3132b6187abSThara Gopinath }; 3142b6187abSThara Gopinath 3152b6187abSThara Gopinath cpu0_opp3: opp-499200000 { 3162b6187abSThara Gopinath opp-hz = /bits/ 64 <499200000>; 3172b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3182b6187abSThara Gopinath }; 3192b6187abSThara Gopinath 3202b6187abSThara Gopinath cpu0_opp4: opp-576000000 { 3212b6187abSThara Gopinath opp-hz = /bits/ 64 <576000000>; 3222b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3232b6187abSThara Gopinath }; 3242b6187abSThara Gopinath 3252b6187abSThara Gopinath cpu0_opp5: opp-672000000 { 3262b6187abSThara Gopinath opp-hz = /bits/ 64 <672000000>; 3272b6187abSThara Gopinath opp-peak-kBps = <800000 15974400>; 3282b6187abSThara Gopinath }; 3292b6187abSThara Gopinath 3302b6187abSThara Gopinath cpu0_opp6: opp-768000000 { 331ce3b50cfSThara Gopinath opp-hz = /bits/ 64 <768000000>; 3322b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3332b6187abSThara Gopinath }; 3342b6187abSThara Gopinath 3352b6187abSThara Gopinath cpu0_opp7: opp-844800000 { 3362b6187abSThara Gopinath opp-hz = /bits/ 64 <844800000>; 3372b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3382b6187abSThara Gopinath }; 3392b6187abSThara Gopinath 3402b6187abSThara Gopinath cpu0_opp8: opp-940800000 { 3412b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 3422b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3432b6187abSThara Gopinath }; 3442b6187abSThara Gopinath 3452b6187abSThara Gopinath cpu0_opp9: opp-1036800000 { 3462b6187abSThara Gopinath opp-hz = /bits/ 64 <1036800000>; 3472b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3482b6187abSThara Gopinath }; 3492b6187abSThara Gopinath 3502b6187abSThara Gopinath cpu0_opp10: opp-1113600000 { 3512b6187abSThara Gopinath opp-hz = /bits/ 64 <1113600000>; 3522b6187abSThara Gopinath opp-peak-kBps = <2188000 25804800>; 3532b6187abSThara Gopinath }; 3542b6187abSThara Gopinath 3552b6187abSThara Gopinath cpu0_opp11: opp-1209600000 { 3562b6187abSThara Gopinath opp-hz = /bits/ 64 <1209600000>; 3572b6187abSThara Gopinath opp-peak-kBps = <2188000 31948800>; 3582b6187abSThara Gopinath }; 3592b6187abSThara Gopinath 3602b6187abSThara Gopinath cpu0_opp12: opp-1305600000 { 3612b6187abSThara Gopinath opp-hz = /bits/ 64 <1305600000>; 3622b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3632b6187abSThara Gopinath }; 3642b6187abSThara Gopinath 3652b6187abSThara Gopinath cpu0_opp13: opp-1382400000 { 3662b6187abSThara Gopinath opp-hz = /bits/ 64 <1382400000>; 3672b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3682b6187abSThara Gopinath }; 3692b6187abSThara Gopinath 3702b6187abSThara Gopinath cpu0_opp14: opp-1478400000 { 3712b6187abSThara Gopinath opp-hz = /bits/ 64 <1478400000>; 3722b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3732b6187abSThara Gopinath }; 3742b6187abSThara Gopinath 3752b6187abSThara Gopinath cpu0_opp15: opp-1555200000 { 3762b6187abSThara Gopinath opp-hz = /bits/ 64 <1555200000>; 3772b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3782b6187abSThara Gopinath }; 3792b6187abSThara Gopinath 3802b6187abSThara Gopinath cpu0_opp16: opp-1632000000 { 3812b6187abSThara Gopinath opp-hz = /bits/ 64 <1632000000>; 3822b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3832b6187abSThara Gopinath }; 3842b6187abSThara Gopinath 3852b6187abSThara Gopinath cpu0_opp17: opp-1708800000 { 3862b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 3872b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 3882b6187abSThara Gopinath }; 3892b6187abSThara Gopinath 3902b6187abSThara Gopinath cpu0_opp18: opp-1785600000 { 3912b6187abSThara Gopinath opp-hz = /bits/ 64 <1785600000>; 3922b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 3932b6187abSThara Gopinath }; 3942b6187abSThara Gopinath }; 3952b6187abSThara Gopinath 3960e3e6546SKrzysztof Kozlowski cpu4_opp_table: opp-table-cpu4 { 3972b6187abSThara Gopinath compatible = "operating-points-v2"; 3982b6187abSThara Gopinath opp-shared; 3992b6187abSThara Gopinath 4002b6187abSThara Gopinath cpu4_opp1: opp-710400000 { 4012b6187abSThara Gopinath opp-hz = /bits/ 64 <710400000>; 4022b6187abSThara Gopinath opp-peak-kBps = <1804000 15974400>; 4032b6187abSThara Gopinath }; 4042b6187abSThara Gopinath 4052b6187abSThara Gopinath cpu4_opp2: opp-825600000 { 4062b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 4072b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 4082b6187abSThara Gopinath }; 4092b6187abSThara Gopinath 4102b6187abSThara Gopinath cpu4_opp3: opp-940800000 { 4112b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 4122b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 4132b6187abSThara Gopinath }; 4142b6187abSThara Gopinath 4152b6187abSThara Gopinath cpu4_opp4: opp-1056000000 { 4162b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 4172b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 4182b6187abSThara Gopinath }; 4192b6187abSThara Gopinath 4202b6187abSThara Gopinath cpu4_opp5: opp-1171200000 { 4212b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 4222b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 4232b6187abSThara Gopinath }; 4242b6187abSThara Gopinath 4252b6187abSThara Gopinath cpu4_opp6: opp-1286400000 { 4262b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 4272b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4282b6187abSThara Gopinath }; 4292b6187abSThara Gopinath 4302b6187abSThara Gopinath cpu4_opp7: opp-1401600000 { 4312b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 4322b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4332b6187abSThara Gopinath }; 4342b6187abSThara Gopinath 4352b6187abSThara Gopinath cpu4_opp8: opp-1497600000 { 4362b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 4372b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4382b6187abSThara Gopinath }; 4392b6187abSThara Gopinath 4402b6187abSThara Gopinath cpu4_opp9: opp-1612800000 { 4412b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 4422b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4432b6187abSThara Gopinath }; 4442b6187abSThara Gopinath 4452b6187abSThara Gopinath cpu4_opp10: opp-1708800000 { 4462b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 4472b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 4482b6187abSThara Gopinath }; 4492b6187abSThara Gopinath 4502b6187abSThara Gopinath cpu4_opp11: opp-1804800000 { 4512b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 4522b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 4532b6187abSThara Gopinath }; 4542b6187abSThara Gopinath 4552b6187abSThara Gopinath cpu4_opp12: opp-1920000000 { 4562b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 4572b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 4582b6187abSThara Gopinath }; 4592b6187abSThara Gopinath 4602b6187abSThara Gopinath cpu4_opp13: opp-2016000000 { 4612b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 4622b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 4632b6187abSThara Gopinath }; 4642b6187abSThara Gopinath 4652b6187abSThara Gopinath cpu4_opp14: opp-2131200000 { 4662b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 4672b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 4682b6187abSThara Gopinath }; 4692b6187abSThara Gopinath 4702b6187abSThara Gopinath cpu4_opp15: opp-2227200000 { 4712b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 4722b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4732b6187abSThara Gopinath }; 4742b6187abSThara Gopinath 4752b6187abSThara Gopinath cpu4_opp16: opp-2323200000 { 4762b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 4772b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4782b6187abSThara Gopinath }; 4792b6187abSThara Gopinath 4802b6187abSThara Gopinath cpu4_opp17: opp-2419200000 { 4812b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 4822b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4832b6187abSThara Gopinath }; 4842b6187abSThara Gopinath }; 4852b6187abSThara Gopinath 4860e3e6546SKrzysztof Kozlowski cpu7_opp_table: opp-table-cpu7 { 4872b6187abSThara Gopinath compatible = "operating-points-v2"; 4882b6187abSThara Gopinath opp-shared; 4892b6187abSThara Gopinath 4902b6187abSThara Gopinath cpu7_opp1: opp-825600000 { 4912b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 4922b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 4932b6187abSThara Gopinath }; 4942b6187abSThara Gopinath 4952b6187abSThara Gopinath cpu7_opp2: opp-940800000 { 4962b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 4972b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 4982b6187abSThara Gopinath }; 4992b6187abSThara Gopinath 5002b6187abSThara Gopinath cpu7_opp3: opp-1056000000 { 5012b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 5022b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 5032b6187abSThara Gopinath }; 5042b6187abSThara Gopinath 5052b6187abSThara Gopinath cpu7_opp4: opp-1171200000 { 5062b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 5072b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 5082b6187abSThara Gopinath }; 5092b6187abSThara Gopinath 5102b6187abSThara Gopinath cpu7_opp5: opp-1286400000 { 5112b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 5122b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5132b6187abSThara Gopinath }; 5142b6187abSThara Gopinath 5152b6187abSThara Gopinath cpu7_opp6: opp-1401600000 { 5162b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 5172b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5182b6187abSThara Gopinath }; 5192b6187abSThara Gopinath 5202b6187abSThara Gopinath cpu7_opp7: opp-1497600000 { 5212b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 5222b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5232b6187abSThara Gopinath }; 5242b6187abSThara Gopinath 5252b6187abSThara Gopinath cpu7_opp8: opp-1612800000 { 5262b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 5272b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5282b6187abSThara Gopinath }; 5292b6187abSThara Gopinath 5302b6187abSThara Gopinath cpu7_opp9: opp-1708800000 { 5312b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 5322b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 5332b6187abSThara Gopinath }; 5342b6187abSThara Gopinath 5352b6187abSThara Gopinath cpu7_opp10: opp-1804800000 { 5362b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 5372b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 5382b6187abSThara Gopinath }; 5392b6187abSThara Gopinath 5402b6187abSThara Gopinath cpu7_opp11: opp-1920000000 { 5412b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 5422b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 5432b6187abSThara Gopinath }; 5442b6187abSThara Gopinath 5452b6187abSThara Gopinath cpu7_opp12: opp-2016000000 { 5462b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 5472b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 5482b6187abSThara Gopinath }; 5492b6187abSThara Gopinath 5502b6187abSThara Gopinath cpu7_opp13: opp-2131200000 { 5512b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 5522b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 5532b6187abSThara Gopinath }; 5542b6187abSThara Gopinath 5552b6187abSThara Gopinath cpu7_opp14: opp-2227200000 { 5562b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 5572b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5582b6187abSThara Gopinath }; 5592b6187abSThara Gopinath 5602b6187abSThara Gopinath cpu7_opp15: opp-2323200000 { 5612b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 5622b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5632b6187abSThara Gopinath }; 5642b6187abSThara Gopinath 5652b6187abSThara Gopinath cpu7_opp16: opp-2419200000 { 5662b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 5672b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5682b6187abSThara Gopinath }; 5692b6187abSThara Gopinath 5702b6187abSThara Gopinath cpu7_opp17: opp-2534400000 { 5712b6187abSThara Gopinath opp-hz = /bits/ 64 <2534400000>; 5722b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5732b6187abSThara Gopinath }; 5742b6187abSThara Gopinath 5752b6187abSThara Gopinath cpu7_opp18: opp-2649600000 { 5762b6187abSThara Gopinath opp-hz = /bits/ 64 <2649600000>; 5772b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5782b6187abSThara Gopinath }; 5792b6187abSThara Gopinath 5802b6187abSThara Gopinath cpu7_opp19: opp-2745600000 { 5812b6187abSThara Gopinath opp-hz = /bits/ 64 <2745600000>; 5822b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5832b6187abSThara Gopinath }; 5842b6187abSThara Gopinath 5852b6187abSThara Gopinath cpu7_opp20: opp-2841600000 { 5862b6187abSThara Gopinath opp-hz = /bits/ 64 <2841600000>; 5872b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5882b6187abSThara Gopinath }; 5892b6187abSThara Gopinath }; 5902b6187abSThara Gopinath 591e13c6d14SVinod Koul firmware { 592e13c6d14SVinod Koul scm: scm { 593e13c6d14SVinod Koul compatible = "qcom,scm-sm8150", "qcom,scm"; 594e13c6d14SVinod Koul #reset-cells = <1>; 595e13c6d14SVinod Koul }; 596e13c6d14SVinod Koul }; 597e13c6d14SVinod Koul 598e13c6d14SVinod Koul memory@80000000 { 599e13c6d14SVinod Koul device_type = "memory"; 600e13c6d14SVinod Koul /* We expect the bootloader to fill in the size */ 601e13c6d14SVinod Koul reg = <0x0 0x80000000 0x0 0x0>; 602e13c6d14SVinod Koul }; 603e13c6d14SVinod Koul 604d8cf9372SVinod Koul pmu { 605d8cf9372SVinod Koul compatible = "arm,armv8-pmuv3"; 606d8cf9372SVinod Koul interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 607d8cf9372SVinod Koul }; 608d8cf9372SVinod Koul 609e13c6d14SVinod Koul psci { 610e13c6d14SVinod Koul compatible = "arm,psci-1.0"; 611e13c6d14SVinod Koul method = "smc"; 612b2e3f897SDanny Lin 6135ca45690SKrzysztof Kozlowski CPU_PD0: power-domain-cpu0 { 614b2e3f897SDanny Lin #power-domain-cells = <0>; 615b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 616b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 617b2e3f897SDanny Lin }; 618b2e3f897SDanny Lin 6195ca45690SKrzysztof Kozlowski CPU_PD1: power-domain-cpu1 { 620b2e3f897SDanny Lin #power-domain-cells = <0>; 621b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 622b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 623b2e3f897SDanny Lin }; 624b2e3f897SDanny Lin 6255ca45690SKrzysztof Kozlowski CPU_PD2: power-domain-cpu2 { 626b2e3f897SDanny Lin #power-domain-cells = <0>; 627b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 628b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 629b2e3f897SDanny Lin }; 630b2e3f897SDanny Lin 6315ca45690SKrzysztof Kozlowski CPU_PD3: power-domain-cpu3 { 632b2e3f897SDanny Lin #power-domain-cells = <0>; 633b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 634b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 635b2e3f897SDanny Lin }; 636b2e3f897SDanny Lin 6375ca45690SKrzysztof Kozlowski CPU_PD4: power-domain-cpu4 { 638b2e3f897SDanny Lin #power-domain-cells = <0>; 639b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 640b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 641b2e3f897SDanny Lin }; 642b2e3f897SDanny Lin 6435ca45690SKrzysztof Kozlowski CPU_PD5: power-domain-cpu5 { 644b2e3f897SDanny Lin #power-domain-cells = <0>; 645b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 646b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 647b2e3f897SDanny Lin }; 648b2e3f897SDanny Lin 6495ca45690SKrzysztof Kozlowski CPU_PD6: power-domain-cpu6 { 650b2e3f897SDanny Lin #power-domain-cells = <0>; 651b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 652b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 653b2e3f897SDanny Lin }; 654b2e3f897SDanny Lin 6555ca45690SKrzysztof Kozlowski CPU_PD7: power-domain-cpu7 { 656b2e3f897SDanny Lin #power-domain-cells = <0>; 657b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 658b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 659b2e3f897SDanny Lin }; 660b2e3f897SDanny Lin 6615ca45690SKrzysztof Kozlowski CLUSTER_PD: power-domain-cpu-cluster0 { 662b2e3f897SDanny Lin #power-domain-cells = <0>; 663b2e3f897SDanny Lin domain-idle-states = <&CLUSTER_SLEEP_0>; 664b2e3f897SDanny Lin }; 665e13c6d14SVinod Koul }; 666e13c6d14SVinod Koul 667912c373aSVinod Koul reserved-memory { 668912c373aSVinod Koul #address-cells = <2>; 669912c373aSVinod Koul #size-cells = <2>; 670912c373aSVinod Koul ranges; 671912c373aSVinod Koul 672912c373aSVinod Koul hyp_mem: memory@85700000 { 673912c373aSVinod Koul reg = <0x0 0x85700000 0x0 0x600000>; 674912c373aSVinod Koul no-map; 675912c373aSVinod Koul }; 676912c373aSVinod Koul 677912c373aSVinod Koul xbl_mem: memory@85d00000 { 678912c373aSVinod Koul reg = <0x0 0x85d00000 0x0 0x140000>; 679912c373aSVinod Koul no-map; 680912c373aSVinod Koul }; 681912c373aSVinod Koul 682912c373aSVinod Koul aop_mem: memory@85f00000 { 683912c373aSVinod Koul reg = <0x0 0x85f00000 0x0 0x20000>; 684912c373aSVinod Koul no-map; 685912c373aSVinod Koul }; 686912c373aSVinod Koul 687912c373aSVinod Koul aop_cmd_db: memory@85f20000 { 688912c373aSVinod Koul compatible = "qcom,cmd-db"; 689912c373aSVinod Koul reg = <0x0 0x85f20000 0x0 0x20000>; 690912c373aSVinod Koul no-map; 691912c373aSVinod Koul }; 692912c373aSVinod Koul 693912c373aSVinod Koul smem_mem: memory@86000000 { 694912c373aSVinod Koul reg = <0x0 0x86000000 0x0 0x200000>; 695912c373aSVinod Koul no-map; 696912c373aSVinod Koul }; 697912c373aSVinod Koul 698912c373aSVinod Koul tz_mem: memory@86200000 { 699912c373aSVinod Koul reg = <0x0 0x86200000 0x0 0x3900000>; 700912c373aSVinod Koul no-map; 701912c373aSVinod Koul }; 702912c373aSVinod Koul 703912c373aSVinod Koul rmtfs_mem: memory@89b00000 { 704912c373aSVinod Koul compatible = "qcom,rmtfs-mem"; 705912c373aSVinod Koul reg = <0x0 0x89b00000 0x0 0x200000>; 706912c373aSVinod Koul no-map; 707912c373aSVinod Koul 708912c373aSVinod Koul qcom,client-id = <1>; 709912c373aSVinod Koul qcom,vmid = <15>; 710912c373aSVinod Koul }; 711912c373aSVinod Koul 712912c373aSVinod Koul camera_mem: memory@8b700000 { 713912c373aSVinod Koul reg = <0x0 0x8b700000 0x0 0x500000>; 714912c373aSVinod Koul no-map; 715912c373aSVinod Koul }; 716912c373aSVinod Koul 717912c373aSVinod Koul wlan_mem: memory@8bc00000 { 718912c373aSVinod Koul reg = <0x0 0x8bc00000 0x0 0x180000>; 719912c373aSVinod Koul no-map; 720912c373aSVinod Koul }; 721912c373aSVinod Koul 722912c373aSVinod Koul npu_mem: memory@8bd80000 { 723912c373aSVinod Koul reg = <0x0 0x8bd80000 0x0 0x80000>; 724912c373aSVinod Koul no-map; 725912c373aSVinod Koul }; 726912c373aSVinod Koul 727912c373aSVinod Koul adsp_mem: memory@8be00000 { 728912c373aSVinod Koul reg = <0x0 0x8be00000 0x0 0x1a00000>; 729912c373aSVinod Koul no-map; 730912c373aSVinod Koul }; 731912c373aSVinod Koul 732912c373aSVinod Koul mpss_mem: memory@8d800000 { 733912c373aSVinod Koul reg = <0x0 0x8d800000 0x0 0x9600000>; 734912c373aSVinod Koul no-map; 735912c373aSVinod Koul }; 736912c373aSVinod Koul 737912c373aSVinod Koul venus_mem: memory@96e00000 { 738912c373aSVinod Koul reg = <0x0 0x96e00000 0x0 0x500000>; 739912c373aSVinod Koul no-map; 740912c373aSVinod Koul }; 741912c373aSVinod Koul 742912c373aSVinod Koul slpi_mem: memory@97300000 { 743912c373aSVinod Koul reg = <0x0 0x97300000 0x0 0x1400000>; 744912c373aSVinod Koul no-map; 745912c373aSVinod Koul }; 746912c373aSVinod Koul 747912c373aSVinod Koul ipa_fw_mem: memory@98700000 { 748912c373aSVinod Koul reg = <0x0 0x98700000 0x0 0x10000>; 749912c373aSVinod Koul no-map; 750912c373aSVinod Koul }; 751912c373aSVinod Koul 752912c373aSVinod Koul ipa_gsi_mem: memory@98710000 { 753912c373aSVinod Koul reg = <0x0 0x98710000 0x0 0x5000>; 754912c373aSVinod Koul no-map; 755912c373aSVinod Koul }; 756912c373aSVinod Koul 757912c373aSVinod Koul gpu_mem: memory@98715000 { 758912c373aSVinod Koul reg = <0x0 0x98715000 0x0 0x2000>; 759912c373aSVinod Koul no-map; 760912c373aSVinod Koul }; 761912c373aSVinod Koul 762912c373aSVinod Koul spss_mem: memory@98800000 { 763912c373aSVinod Koul reg = <0x0 0x98800000 0x0 0x100000>; 764912c373aSVinod Koul no-map; 765912c373aSVinod Koul }; 766912c373aSVinod Koul 767912c373aSVinod Koul cdsp_mem: memory@98900000 { 768912c373aSVinod Koul reg = <0x0 0x98900000 0x0 0x1400000>; 769912c373aSVinod Koul no-map; 770912c373aSVinod Koul }; 771912c373aSVinod Koul 772912c373aSVinod Koul qseecom_mem: memory@9e400000 { 773912c373aSVinod Koul reg = <0x0 0x9e400000 0x0 0x1400000>; 774912c373aSVinod Koul no-map; 775912c373aSVinod Koul }; 776912c373aSVinod Koul }; 777912c373aSVinod Koul 778d8cf9372SVinod Koul smem { 779d8cf9372SVinod Koul compatible = "qcom,smem"; 780d8cf9372SVinod Koul memory-region = <&smem_mem>; 781d8cf9372SVinod Koul hwlocks = <&tcsr_mutex 3>; 782d8cf9372SVinod Koul }; 783d8cf9372SVinod Koul 78461025b81SSibi Sankar smp2p-cdsp { 78561025b81SSibi Sankar compatible = "qcom,smp2p"; 78661025b81SSibi Sankar qcom,smem = <94>, <432>; 78761025b81SSibi Sankar 78861025b81SSibi Sankar interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 78961025b81SSibi Sankar 79061025b81SSibi Sankar mboxes = <&apss_shared 6>; 79161025b81SSibi Sankar 79261025b81SSibi Sankar qcom,local-pid = <0>; 79361025b81SSibi Sankar qcom,remote-pid = <5>; 79461025b81SSibi Sankar 79561025b81SSibi Sankar cdsp_smp2p_out: master-kernel { 79661025b81SSibi Sankar qcom,entry-name = "master-kernel"; 79761025b81SSibi Sankar #qcom,smem-state-cells = <1>; 79861025b81SSibi Sankar }; 79961025b81SSibi Sankar 80061025b81SSibi Sankar cdsp_smp2p_in: slave-kernel { 80161025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 80261025b81SSibi Sankar 80361025b81SSibi Sankar interrupt-controller; 80461025b81SSibi Sankar #interrupt-cells = <2>; 80561025b81SSibi Sankar }; 80661025b81SSibi Sankar }; 80761025b81SSibi Sankar 80861025b81SSibi Sankar smp2p-lpass { 80961025b81SSibi Sankar compatible = "qcom,smp2p"; 81061025b81SSibi Sankar qcom,smem = <443>, <429>; 81161025b81SSibi Sankar 81261025b81SSibi Sankar interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 81361025b81SSibi Sankar 81461025b81SSibi Sankar mboxes = <&apss_shared 10>; 81561025b81SSibi Sankar 81661025b81SSibi Sankar qcom,local-pid = <0>; 81761025b81SSibi Sankar qcom,remote-pid = <2>; 81861025b81SSibi Sankar 81961025b81SSibi Sankar adsp_smp2p_out: master-kernel { 82061025b81SSibi Sankar qcom,entry-name = "master-kernel"; 82161025b81SSibi Sankar #qcom,smem-state-cells = <1>; 82261025b81SSibi Sankar }; 82361025b81SSibi Sankar 82461025b81SSibi Sankar adsp_smp2p_in: slave-kernel { 82561025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 82661025b81SSibi Sankar 82761025b81SSibi Sankar interrupt-controller; 82861025b81SSibi Sankar #interrupt-cells = <2>; 82961025b81SSibi Sankar }; 83061025b81SSibi Sankar }; 83161025b81SSibi Sankar 83261025b81SSibi Sankar smp2p-mpss { 83361025b81SSibi Sankar compatible = "qcom,smp2p"; 83461025b81SSibi Sankar qcom,smem = <435>, <428>; 83561025b81SSibi Sankar 83661025b81SSibi Sankar interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 83761025b81SSibi Sankar 83861025b81SSibi Sankar mboxes = <&apss_shared 14>; 83961025b81SSibi Sankar 84061025b81SSibi Sankar qcom,local-pid = <0>; 84161025b81SSibi Sankar qcom,remote-pid = <1>; 84261025b81SSibi Sankar 84361025b81SSibi Sankar modem_smp2p_out: master-kernel { 84461025b81SSibi Sankar qcom,entry-name = "master-kernel"; 84561025b81SSibi Sankar #qcom,smem-state-cells = <1>; 84661025b81SSibi Sankar }; 84761025b81SSibi Sankar 84861025b81SSibi Sankar modem_smp2p_in: slave-kernel { 84961025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 85061025b81SSibi Sankar 85161025b81SSibi Sankar interrupt-controller; 85261025b81SSibi Sankar #interrupt-cells = <2>; 85361025b81SSibi Sankar }; 85461025b81SSibi Sankar }; 85561025b81SSibi Sankar 85661025b81SSibi Sankar smp2p-slpi { 85761025b81SSibi Sankar compatible = "qcom,smp2p"; 85861025b81SSibi Sankar qcom,smem = <481>, <430>; 85961025b81SSibi Sankar 86061025b81SSibi Sankar interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 86161025b81SSibi Sankar 86261025b81SSibi Sankar mboxes = <&apss_shared 26>; 86361025b81SSibi Sankar 86461025b81SSibi Sankar qcom,local-pid = <0>; 86561025b81SSibi Sankar qcom,remote-pid = <3>; 86661025b81SSibi Sankar 86761025b81SSibi Sankar slpi_smp2p_out: master-kernel { 86861025b81SSibi Sankar qcom,entry-name = "master-kernel"; 86961025b81SSibi Sankar #qcom,smem-state-cells = <1>; 87061025b81SSibi Sankar }; 87161025b81SSibi Sankar 87261025b81SSibi Sankar slpi_smp2p_in: slave-kernel { 87361025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 87461025b81SSibi Sankar 87561025b81SSibi Sankar interrupt-controller; 87661025b81SSibi Sankar #interrupt-cells = <2>; 87761025b81SSibi Sankar }; 87861025b81SSibi Sankar }; 87961025b81SSibi Sankar 880e13c6d14SVinod Koul soc: soc@0 { 881e13c6d14SVinod Koul #address-cells = <2>; 882e13c6d14SVinod Koul #size-cells = <2>; 883e13c6d14SVinod Koul ranges = <0 0 0 0 0x10 0>; 884e13c6d14SVinod Koul dma-ranges = <0 0 0 0 0x10 0>; 885e13c6d14SVinod Koul compatible = "simple-bus"; 886e13c6d14SVinod Koul 887e13c6d14SVinod Koul gcc: clock-controller@100000 { 888e13c6d14SVinod Koul compatible = "qcom,gcc-sm8150"; 889e13c6d14SVinod Koul reg = <0x0 0x00100000 0x0 0x1f0000>; 890e13c6d14SVinod Koul #clock-cells = <1>; 891e13c6d14SVinod Koul #reset-cells = <1>; 892e13c6d14SVinod Koul #power-domain-cells = <1>; 893e13c6d14SVinod Koul clock-names = "bi_tcxo", 894e13c6d14SVinod Koul "sleep_clk"; 895e13c6d14SVinod Koul clocks = <&rpmhcc RPMH_CXO_CLK>, 896e13c6d14SVinod Koul <&sleep_clk>; 897e13c6d14SVinod Koul }; 898e13c6d14SVinod Koul 89905006290SFelipe Balbi gpi_dma0: dma-controller@800000 { 900e7e24786SRichard Acayan compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 90105006290SFelipe Balbi reg = <0 0x800000 0 0x60000>; 90205006290SFelipe Balbi interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 90305006290SFelipe Balbi <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 90405006290SFelipe Balbi <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 90505006290SFelipe Balbi <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 90605006290SFelipe Balbi <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 90705006290SFelipe Balbi <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 90805006290SFelipe Balbi <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 90905006290SFelipe Balbi <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 91005006290SFelipe Balbi <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 91105006290SFelipe Balbi <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 91205006290SFelipe Balbi <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 91305006290SFelipe Balbi <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 91405006290SFelipe Balbi <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 91505006290SFelipe Balbi dma-channels = <13>; 91605006290SFelipe Balbi dma-channel-mask = <0xfa>; 91705006290SFelipe Balbi iommus = <&apps_smmu 0x00d6 0x0>; 91805006290SFelipe Balbi #dma-cells = <3>; 91905006290SFelipe Balbi status = "disabled"; 92005006290SFelipe Balbi }; 92105006290SFelipe Balbi 92205f333b7SVinod Koul ethernet: ethernet@20000 { 92305f333b7SVinod Koul compatible = "qcom,sm8150-ethqos"; 92405f333b7SVinod Koul reg = <0x0 0x00020000 0x0 0x10000>, 92505f333b7SVinod Koul <0x0 0x00036000 0x0 0x100>; 92605f333b7SVinod Koul reg-names = "stmmaceth", "rgmii"; 92705f333b7SVinod Koul clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 92805f333b7SVinod Koul clocks = <&gcc GCC_EMAC_AXI_CLK>, 92905f333b7SVinod Koul <&gcc GCC_EMAC_SLV_AHB_CLK>, 93005f333b7SVinod Koul <&gcc GCC_EMAC_PTP_CLK>, 93105f333b7SVinod Koul <&gcc GCC_EMAC_RGMII_CLK>; 93205f333b7SVinod Koul interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 93305f333b7SVinod Koul <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 93405f333b7SVinod Koul interrupt-names = "macirq", "eth_lpi"; 93505f333b7SVinod Koul 93605f333b7SVinod Koul power-domains = <&gcc EMAC_GDSC>; 93705f333b7SVinod Koul resets = <&gcc GCC_EMAC_BCR>; 93805f333b7SVinod Koul 93951f748c6SKonrad Dybcio iommus = <&apps_smmu 0x3c0 0x0>; 94005f333b7SVinod Koul 94105f333b7SVinod Koul snps,tso; 94205f333b7SVinod Koul rx-fifo-depth = <4096>; 94305f333b7SVinod Koul tx-fifo-depth = <4096>; 94405f333b7SVinod Koul 94505f333b7SVinod Koul status = "disabled"; 94605f333b7SVinod Koul }; 94705f333b7SVinod Koul 94805f333b7SVinod Koul 9499cf3ebd1SCaleb Connolly qupv3_id_0: geniqup@8c0000 { 9509cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 9519cf3ebd1SCaleb Connolly reg = <0x0 0x008c0000 0x0 0x6000>; 9529cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 9539cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 9549cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 9559cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0xc3 0x0>; 9569cf3ebd1SCaleb Connolly #address-cells = <2>; 9579cf3ebd1SCaleb Connolly #size-cells = <2>; 9589cf3ebd1SCaleb Connolly ranges; 9599cf3ebd1SCaleb Connolly status = "disabled"; 96081bee695SCaleb Connolly 96181bee695SCaleb Connolly i2c0: i2c@880000 { 96281bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 96381bee695SCaleb Connolly reg = <0 0x00880000 0 0x4000>; 96481bee695SCaleb Connolly clock-names = "se"; 96581bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 966abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 967abdd4b7aSFelipe Balbi <&gpi_dma0 1 0 QCOM_GPI_I2C>; 968abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 96981bee695SCaleb Connolly pinctrl-names = "default"; 97081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c0_default>; 97181bee695SCaleb Connolly interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 97281bee695SCaleb Connolly #address-cells = <1>; 97381bee695SCaleb Connolly #size-cells = <0>; 97481bee695SCaleb Connolly status = "disabled"; 97581bee695SCaleb Connolly }; 97681bee695SCaleb Connolly 977129e1c96SFelipe Balbi spi0: spi@880000 { 978129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 979129e1c96SFelipe Balbi reg = <0 0x880000 0 0x4000>; 980129e1c96SFelipe Balbi reg-names = "se"; 981129e1c96SFelipe Balbi clock-names = "se"; 982129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 983abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 984abdd4b7aSFelipe Balbi <&gpi_dma0 1 0 QCOM_GPI_SPI>; 985abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 986129e1c96SFelipe Balbi pinctrl-names = "default"; 987129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi0_default>; 988129e1c96SFelipe Balbi interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 989129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 990129e1c96SFelipe Balbi #address-cells = <1>; 991129e1c96SFelipe Balbi #size-cells = <0>; 992129e1c96SFelipe Balbi status = "disabled"; 993129e1c96SFelipe Balbi }; 994129e1c96SFelipe Balbi 99581bee695SCaleb Connolly i2c1: i2c@884000 { 99681bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 99781bee695SCaleb Connolly reg = <0 0x00884000 0 0x4000>; 99881bee695SCaleb Connolly clock-names = "se"; 99981bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1000abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1001abdd4b7aSFelipe Balbi <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1002abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 100381bee695SCaleb Connolly pinctrl-names = "default"; 100481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c1_default>; 100581bee695SCaleb Connolly interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 100681bee695SCaleb Connolly #address-cells = <1>; 100781bee695SCaleb Connolly #size-cells = <0>; 100881bee695SCaleb Connolly status = "disabled"; 100981bee695SCaleb Connolly }; 101081bee695SCaleb Connolly 1011129e1c96SFelipe Balbi spi1: spi@884000 { 1012129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1013129e1c96SFelipe Balbi reg = <0 0x884000 0 0x4000>; 1014129e1c96SFelipe Balbi reg-names = "se"; 1015129e1c96SFelipe Balbi clock-names = "se"; 1016129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1017abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1018abdd4b7aSFelipe Balbi <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1019abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1020129e1c96SFelipe Balbi pinctrl-names = "default"; 1021129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi1_default>; 1022129e1c96SFelipe Balbi interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1023129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1024129e1c96SFelipe Balbi #address-cells = <1>; 1025129e1c96SFelipe Balbi #size-cells = <0>; 1026129e1c96SFelipe Balbi status = "disabled"; 1027129e1c96SFelipe Balbi }; 1028129e1c96SFelipe Balbi 102981bee695SCaleb Connolly i2c2: i2c@888000 { 103081bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 103181bee695SCaleb Connolly reg = <0 0x00888000 0 0x4000>; 103281bee695SCaleb Connolly clock-names = "se"; 103381bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1034abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1035abdd4b7aSFelipe Balbi <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1036abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 103781bee695SCaleb Connolly pinctrl-names = "default"; 103881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c2_default>; 103981bee695SCaleb Connolly interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 104081bee695SCaleb Connolly #address-cells = <1>; 104181bee695SCaleb Connolly #size-cells = <0>; 104281bee695SCaleb Connolly status = "disabled"; 104381bee695SCaleb Connolly }; 104481bee695SCaleb Connolly 1045129e1c96SFelipe Balbi spi2: spi@888000 { 1046129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1047129e1c96SFelipe Balbi reg = <0 0x888000 0 0x4000>; 1048129e1c96SFelipe Balbi reg-names = "se"; 1049129e1c96SFelipe Balbi clock-names = "se"; 1050129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1051abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1052abdd4b7aSFelipe Balbi <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1053abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1054129e1c96SFelipe Balbi pinctrl-names = "default"; 1055129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi2_default>; 1056129e1c96SFelipe Balbi interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1057129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1058129e1c96SFelipe Balbi #address-cells = <1>; 1059129e1c96SFelipe Balbi #size-cells = <0>; 1060129e1c96SFelipe Balbi status = "disabled"; 1061129e1c96SFelipe Balbi }; 1062129e1c96SFelipe Balbi 106381bee695SCaleb Connolly i2c3: i2c@88c000 { 106481bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 106581bee695SCaleb Connolly reg = <0 0x0088c000 0 0x4000>; 106681bee695SCaleb Connolly clock-names = "se"; 106781bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1068abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1069abdd4b7aSFelipe Balbi <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1070abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 107181bee695SCaleb Connolly pinctrl-names = "default"; 107281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c3_default>; 107381bee695SCaleb Connolly interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 107481bee695SCaleb Connolly #address-cells = <1>; 107581bee695SCaleb Connolly #size-cells = <0>; 107681bee695SCaleb Connolly status = "disabled"; 107781bee695SCaleb Connolly }; 107881bee695SCaleb Connolly 1079129e1c96SFelipe Balbi spi3: spi@88c000 { 1080129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1081129e1c96SFelipe Balbi reg = <0 0x88c000 0 0x4000>; 1082129e1c96SFelipe Balbi reg-names = "se"; 1083129e1c96SFelipe Balbi clock-names = "se"; 1084129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1085abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1086abdd4b7aSFelipe Balbi <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1087abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1088129e1c96SFelipe Balbi pinctrl-names = "default"; 1089129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi3_default>; 1090129e1c96SFelipe Balbi interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1091129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1092129e1c96SFelipe Balbi #address-cells = <1>; 1093129e1c96SFelipe Balbi #size-cells = <0>; 1094129e1c96SFelipe Balbi status = "disabled"; 1095129e1c96SFelipe Balbi }; 1096129e1c96SFelipe Balbi 109781bee695SCaleb Connolly i2c4: i2c@890000 { 109881bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 109981bee695SCaleb Connolly reg = <0 0x00890000 0 0x4000>; 110081bee695SCaleb Connolly clock-names = "se"; 110181bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1102abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1103abdd4b7aSFelipe Balbi <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1104abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 110581bee695SCaleb Connolly pinctrl-names = "default"; 110681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c4_default>; 110781bee695SCaleb Connolly interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 110881bee695SCaleb Connolly #address-cells = <1>; 110981bee695SCaleb Connolly #size-cells = <0>; 111081bee695SCaleb Connolly status = "disabled"; 111181bee695SCaleb Connolly }; 111281bee695SCaleb Connolly 1113129e1c96SFelipe Balbi spi4: spi@890000 { 1114129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1115129e1c96SFelipe Balbi reg = <0 0x890000 0 0x4000>; 1116129e1c96SFelipe Balbi reg-names = "se"; 1117129e1c96SFelipe Balbi clock-names = "se"; 1118129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1119abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1120abdd4b7aSFelipe Balbi <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1121abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1122129e1c96SFelipe Balbi pinctrl-names = "default"; 1123129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi4_default>; 1124129e1c96SFelipe Balbi interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1125129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1126129e1c96SFelipe Balbi #address-cells = <1>; 1127129e1c96SFelipe Balbi #size-cells = <0>; 1128129e1c96SFelipe Balbi status = "disabled"; 1129129e1c96SFelipe Balbi }; 1130129e1c96SFelipe Balbi 113181bee695SCaleb Connolly i2c5: i2c@894000 { 113281bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 113381bee695SCaleb Connolly reg = <0 0x00894000 0 0x4000>; 113481bee695SCaleb Connolly clock-names = "se"; 113581bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1136abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1137abdd4b7aSFelipe Balbi <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1138abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 113981bee695SCaleb Connolly pinctrl-names = "default"; 114081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c5_default>; 114181bee695SCaleb Connolly interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 114281bee695SCaleb Connolly #address-cells = <1>; 114381bee695SCaleb Connolly #size-cells = <0>; 114481bee695SCaleb Connolly status = "disabled"; 114581bee695SCaleb Connolly }; 114681bee695SCaleb Connolly 1147129e1c96SFelipe Balbi spi5: spi@894000 { 1148129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1149129e1c96SFelipe Balbi reg = <0 0x894000 0 0x4000>; 1150129e1c96SFelipe Balbi reg-names = "se"; 1151129e1c96SFelipe Balbi clock-names = "se"; 1152129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1153abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1154abdd4b7aSFelipe Balbi <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1155abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1156129e1c96SFelipe Balbi pinctrl-names = "default"; 1157129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi5_default>; 1158129e1c96SFelipe Balbi interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1159129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1160129e1c96SFelipe Balbi #address-cells = <1>; 1161129e1c96SFelipe Balbi #size-cells = <0>; 1162129e1c96SFelipe Balbi status = "disabled"; 1163129e1c96SFelipe Balbi }; 1164129e1c96SFelipe Balbi 116581bee695SCaleb Connolly i2c6: i2c@898000 { 116681bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 116781bee695SCaleb Connolly reg = <0 0x00898000 0 0x4000>; 116881bee695SCaleb Connolly clock-names = "se"; 116981bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1170abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1171abdd4b7aSFelipe Balbi <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1172abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 117381bee695SCaleb Connolly pinctrl-names = "default"; 117481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c6_default>; 117581bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 117681bee695SCaleb Connolly #address-cells = <1>; 117781bee695SCaleb Connolly #size-cells = <0>; 117881bee695SCaleb Connolly status = "disabled"; 117981bee695SCaleb Connolly }; 118081bee695SCaleb Connolly 1181129e1c96SFelipe Balbi spi6: spi@898000 { 1182129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1183129e1c96SFelipe Balbi reg = <0 0x898000 0 0x4000>; 1184129e1c96SFelipe Balbi reg-names = "se"; 1185129e1c96SFelipe Balbi clock-names = "se"; 1186129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1187abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1188abdd4b7aSFelipe Balbi <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1189abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1190129e1c96SFelipe Balbi pinctrl-names = "default"; 1191129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi6_default>; 1192129e1c96SFelipe Balbi interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1193129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1194129e1c96SFelipe Balbi #address-cells = <1>; 1195129e1c96SFelipe Balbi #size-cells = <0>; 1196129e1c96SFelipe Balbi status = "disabled"; 1197129e1c96SFelipe Balbi }; 1198129e1c96SFelipe Balbi 119981bee695SCaleb Connolly i2c7: i2c@89c000 { 120081bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 120181bee695SCaleb Connolly reg = <0 0x0089c000 0 0x4000>; 120281bee695SCaleb Connolly clock-names = "se"; 120381bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1204abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1205abdd4b7aSFelipe Balbi <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1206abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 120781bee695SCaleb Connolly pinctrl-names = "default"; 120881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c7_default>; 120981bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 121081bee695SCaleb Connolly #address-cells = <1>; 121181bee695SCaleb Connolly #size-cells = <0>; 121281bee695SCaleb Connolly status = "disabled"; 121381bee695SCaleb Connolly }; 121481bee695SCaleb Connolly 1215129e1c96SFelipe Balbi spi7: spi@89c000 { 1216129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1217129e1c96SFelipe Balbi reg = <0 0x89c000 0 0x4000>; 1218129e1c96SFelipe Balbi reg-names = "se"; 1219129e1c96SFelipe Balbi clock-names = "se"; 1220129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1221abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1222abdd4b7aSFelipe Balbi <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1223abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1224129e1c96SFelipe Balbi pinctrl-names = "default"; 1225129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi7_default>; 1226129e1c96SFelipe Balbi interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1227129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1228129e1c96SFelipe Balbi #address-cells = <1>; 1229129e1c96SFelipe Balbi #size-cells = <0>; 1230129e1c96SFelipe Balbi status = "disabled"; 1231129e1c96SFelipe Balbi }; 12329cf3ebd1SCaleb Connolly }; 12339cf3ebd1SCaleb Connolly 123405006290SFelipe Balbi gpi_dma1: dma-controller@a00000 { 1235e7e24786SRichard Acayan compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 123605006290SFelipe Balbi reg = <0 0xa00000 0 0x60000>; 123705006290SFelipe Balbi interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 123805006290SFelipe Balbi <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 123905006290SFelipe Balbi <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 124005006290SFelipe Balbi <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 124105006290SFelipe Balbi <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 124205006290SFelipe Balbi <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 124305006290SFelipe Balbi <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 124405006290SFelipe Balbi <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 124505006290SFelipe Balbi <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 124605006290SFelipe Balbi <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 124705006290SFelipe Balbi <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 124805006290SFelipe Balbi <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 124905006290SFelipe Balbi <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 125005006290SFelipe Balbi dma-channels = <13>; 125105006290SFelipe Balbi dma-channel-mask = <0xfa>; 125205006290SFelipe Balbi iommus = <&apps_smmu 0x0616 0x0>; 125305006290SFelipe Balbi #dma-cells = <3>; 125405006290SFelipe Balbi status = "disabled"; 125505006290SFelipe Balbi }; 125605006290SFelipe Balbi 1257e13c6d14SVinod Koul qupv3_id_1: geniqup@ac0000 { 1258e13c6d14SVinod Koul compatible = "qcom,geni-se-qup"; 1259e13c6d14SVinod Koul reg = <0x0 0x00ac0000 0x0 0x6000>; 1260e13c6d14SVinod Koul clock-names = "m-ahb", "s-ahb"; 1261d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1262d6f55763SVinod Koul <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 12639cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x603 0x0>; 1264e13c6d14SVinod Koul #address-cells = <2>; 1265e13c6d14SVinod Koul #size-cells = <2>; 1266e13c6d14SVinod Koul ranges; 1267e13c6d14SVinod Koul status = "disabled"; 1268e13c6d14SVinod Koul 126981bee695SCaleb Connolly i2c8: i2c@a80000 { 127081bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 127181bee695SCaleb Connolly reg = <0 0x00a80000 0 0x4000>; 127281bee695SCaleb Connolly clock-names = "se"; 127381bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1274abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1275abdd4b7aSFelipe Balbi <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1276abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 127781bee695SCaleb Connolly pinctrl-names = "default"; 127881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c8_default>; 127981bee695SCaleb Connolly interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 128081bee695SCaleb Connolly #address-cells = <1>; 128181bee695SCaleb Connolly #size-cells = <0>; 128281bee695SCaleb Connolly status = "disabled"; 128381bee695SCaleb Connolly }; 128481bee695SCaleb Connolly 1285129e1c96SFelipe Balbi spi8: spi@a80000 { 1286129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1287129e1c96SFelipe Balbi reg = <0 0xa80000 0 0x4000>; 1288129e1c96SFelipe Balbi reg-names = "se"; 1289129e1c96SFelipe Balbi clock-names = "se"; 1290129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1291abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1292abdd4b7aSFelipe Balbi <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1293abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1294129e1c96SFelipe Balbi pinctrl-names = "default"; 1295129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi8_default>; 1296129e1c96SFelipe Balbi interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1297129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1298129e1c96SFelipe Balbi #address-cells = <1>; 1299129e1c96SFelipe Balbi #size-cells = <0>; 1300129e1c96SFelipe Balbi status = "disabled"; 1301129e1c96SFelipe Balbi }; 1302129e1c96SFelipe Balbi 130381bee695SCaleb Connolly i2c9: i2c@a84000 { 130481bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 130581bee695SCaleb Connolly reg = <0 0x00a84000 0 0x4000>; 130681bee695SCaleb Connolly clock-names = "se"; 130781bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1308abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1309abdd4b7aSFelipe Balbi <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1310abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 131181bee695SCaleb Connolly pinctrl-names = "default"; 131281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c9_default>; 131381bee695SCaleb Connolly interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 131481bee695SCaleb Connolly #address-cells = <1>; 131581bee695SCaleb Connolly #size-cells = <0>; 131681bee695SCaleb Connolly status = "disabled"; 131781bee695SCaleb Connolly }; 131881bee695SCaleb Connolly 1319129e1c96SFelipe Balbi spi9: spi@a84000 { 1320129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1321129e1c96SFelipe Balbi reg = <0 0xa84000 0 0x4000>; 1322129e1c96SFelipe Balbi reg-names = "se"; 1323129e1c96SFelipe Balbi clock-names = "se"; 1324129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1325abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1326abdd4b7aSFelipe Balbi <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1327abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1328129e1c96SFelipe Balbi pinctrl-names = "default"; 1329129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi9_default>; 1330129e1c96SFelipe Balbi interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1331129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1332129e1c96SFelipe Balbi #address-cells = <1>; 1333129e1c96SFelipe Balbi #size-cells = <0>; 1334129e1c96SFelipe Balbi status = "disabled"; 1335129e1c96SFelipe Balbi }; 1336129e1c96SFelipe Balbi 133781bee695SCaleb Connolly i2c10: i2c@a88000 { 133881bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 133981bee695SCaleb Connolly reg = <0 0x00a88000 0 0x4000>; 134081bee695SCaleb Connolly clock-names = "se"; 134181bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1342abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1343abdd4b7aSFelipe Balbi <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1344abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 134581bee695SCaleb Connolly pinctrl-names = "default"; 134681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c10_default>; 134781bee695SCaleb Connolly interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 134881bee695SCaleb Connolly #address-cells = <1>; 134981bee695SCaleb Connolly #size-cells = <0>; 135081bee695SCaleb Connolly status = "disabled"; 135181bee695SCaleb Connolly }; 135281bee695SCaleb Connolly 1353129e1c96SFelipe Balbi spi10: spi@a88000 { 1354129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1355129e1c96SFelipe Balbi reg = <0 0xa88000 0 0x4000>; 1356129e1c96SFelipe Balbi reg-names = "se"; 1357129e1c96SFelipe Balbi clock-names = "se"; 1358129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1359abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1360abdd4b7aSFelipe Balbi <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1361abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1362129e1c96SFelipe Balbi pinctrl-names = "default"; 1363129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi10_default>; 1364129e1c96SFelipe Balbi interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1365129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1366129e1c96SFelipe Balbi #address-cells = <1>; 1367129e1c96SFelipe Balbi #size-cells = <0>; 1368129e1c96SFelipe Balbi status = "disabled"; 1369129e1c96SFelipe Balbi }; 1370129e1c96SFelipe Balbi 137181bee695SCaleb Connolly i2c11: i2c@a8c000 { 137281bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 137381bee695SCaleb Connolly reg = <0 0x00a8c000 0 0x4000>; 137481bee695SCaleb Connolly clock-names = "se"; 137581bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1376abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1377abdd4b7aSFelipe Balbi <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1378abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 137981bee695SCaleb Connolly pinctrl-names = "default"; 138081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c11_default>; 138181bee695SCaleb Connolly interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 138281bee695SCaleb Connolly #address-cells = <1>; 138381bee695SCaleb Connolly #size-cells = <0>; 138481bee695SCaleb Connolly status = "disabled"; 138581bee695SCaleb Connolly }; 138681bee695SCaleb Connolly 1387129e1c96SFelipe Balbi spi11: spi@a8c000 { 1388129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1389129e1c96SFelipe Balbi reg = <0 0xa8c000 0 0x4000>; 1390129e1c96SFelipe Balbi reg-names = "se"; 1391129e1c96SFelipe Balbi clock-names = "se"; 1392129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1393abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1394abdd4b7aSFelipe Balbi <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1395abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1396129e1c96SFelipe Balbi pinctrl-names = "default"; 1397129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi11_default>; 1398129e1c96SFelipe Balbi interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1399129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1400129e1c96SFelipe Balbi #address-cells = <1>; 1401129e1c96SFelipe Balbi #size-cells = <0>; 1402129e1c96SFelipe Balbi status = "disabled"; 1403129e1c96SFelipe Balbi }; 1404129e1c96SFelipe Balbi 1405e13c6d14SVinod Koul uart2: serial@a90000 { 1406e13c6d14SVinod Koul compatible = "qcom,geni-debug-uart"; 1407e13c6d14SVinod Koul reg = <0x0 0x00a90000 0x0 0x4000>; 1408e13c6d14SVinod Koul clock-names = "se"; 1409d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1410e13c6d14SVinod Koul interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1411e13c6d14SVinod Koul status = "disabled"; 1412e13c6d14SVinod Koul }; 141381bee695SCaleb Connolly 141481bee695SCaleb Connolly i2c12: i2c@a90000 { 141581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 141681bee695SCaleb Connolly reg = <0 0x00a90000 0 0x4000>; 141781bee695SCaleb Connolly clock-names = "se"; 141881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1419abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1420abdd4b7aSFelipe Balbi <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1421abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 142281bee695SCaleb Connolly pinctrl-names = "default"; 142381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c12_default>; 142481bee695SCaleb Connolly interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 142581bee695SCaleb Connolly #address-cells = <1>; 142681bee695SCaleb Connolly #size-cells = <0>; 142781bee695SCaleb Connolly status = "disabled"; 142881bee695SCaleb Connolly }; 142981bee695SCaleb Connolly 1430129e1c96SFelipe Balbi spi12: spi@a90000 { 1431129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1432129e1c96SFelipe Balbi reg = <0 0xa90000 0 0x4000>; 1433129e1c96SFelipe Balbi reg-names = "se"; 1434129e1c96SFelipe Balbi clock-names = "se"; 1435129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1436abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1437abdd4b7aSFelipe Balbi <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1438abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1439129e1c96SFelipe Balbi pinctrl-names = "default"; 1440129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi12_default>; 1441129e1c96SFelipe Balbi interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1442129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1443129e1c96SFelipe Balbi #address-cells = <1>; 1444129e1c96SFelipe Balbi #size-cells = <0>; 1445129e1c96SFelipe Balbi status = "disabled"; 1446129e1c96SFelipe Balbi }; 1447129e1c96SFelipe Balbi 144881bee695SCaleb Connolly i2c16: i2c@94000 { 144981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 145081bee695SCaleb Connolly reg = <0 0x0094000 0 0x4000>; 145181bee695SCaleb Connolly clock-names = "se"; 145281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1453abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1454abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1455abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 145681bee695SCaleb Connolly pinctrl-names = "default"; 145781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c16_default>; 145881bee695SCaleb Connolly interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 145981bee695SCaleb Connolly #address-cells = <1>; 146081bee695SCaleb Connolly #size-cells = <0>; 146181bee695SCaleb Connolly status = "disabled"; 146281bee695SCaleb Connolly }; 1463129e1c96SFelipe Balbi 1464129e1c96SFelipe Balbi spi16: spi@a94000 { 1465129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1466129e1c96SFelipe Balbi reg = <0 0xa94000 0 0x4000>; 1467129e1c96SFelipe Balbi reg-names = "se"; 1468129e1c96SFelipe Balbi clock-names = "se"; 1469129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1470abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1471abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1472abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1473129e1c96SFelipe Balbi pinctrl-names = "default"; 1474129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi16_default>; 1475129e1c96SFelipe Balbi interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1476129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1477129e1c96SFelipe Balbi #address-cells = <1>; 1478129e1c96SFelipe Balbi #size-cells = <0>; 1479129e1c96SFelipe Balbi status = "disabled"; 1480129e1c96SFelipe Balbi }; 1481e13c6d14SVinod Koul }; 1482e13c6d14SVinod Koul 148305006290SFelipe Balbi gpi_dma2: dma-controller@c00000 { 1484e7e24786SRichard Acayan compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 148505006290SFelipe Balbi reg = <0 0xc00000 0 0x60000>; 148605006290SFelipe Balbi interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 148705006290SFelipe Balbi <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 148805006290SFelipe Balbi <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 148905006290SFelipe Balbi <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 149005006290SFelipe Balbi <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 149105006290SFelipe Balbi <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 149205006290SFelipe Balbi <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 149305006290SFelipe Balbi <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 149405006290SFelipe Balbi <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 149505006290SFelipe Balbi <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 149605006290SFelipe Balbi <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 149705006290SFelipe Balbi <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 149805006290SFelipe Balbi <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 149905006290SFelipe Balbi dma-channels = <13>; 150005006290SFelipe Balbi dma-channel-mask = <0xfa>; 150105006290SFelipe Balbi iommus = <&apps_smmu 0x07b6 0x0>; 150205006290SFelipe Balbi #dma-cells = <3>; 150305006290SFelipe Balbi status = "disabled"; 150405006290SFelipe Balbi }; 150505006290SFelipe Balbi 15069cf3ebd1SCaleb Connolly qupv3_id_2: geniqup@cc0000 { 15079cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 15089cf3ebd1SCaleb Connolly reg = <0x0 0x00cc0000 0x0 0x6000>; 15099cf3ebd1SCaleb Connolly 15109cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 15119cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 15129cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 15139cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x7a3 0x0>; 15149cf3ebd1SCaleb Connolly #address-cells = <2>; 15159cf3ebd1SCaleb Connolly #size-cells = <2>; 15169cf3ebd1SCaleb Connolly ranges; 15179cf3ebd1SCaleb Connolly status = "disabled"; 151881bee695SCaleb Connolly 151981bee695SCaleb Connolly i2c17: i2c@c80000 { 152081bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 152181bee695SCaleb Connolly reg = <0 0x00c80000 0 0x4000>; 152281bee695SCaleb Connolly clock-names = "se"; 152381bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1524abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1525abdd4b7aSFelipe Balbi <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1526abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 152781bee695SCaleb Connolly pinctrl-names = "default"; 152881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c17_default>; 152981bee695SCaleb Connolly interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 153081bee695SCaleb Connolly #address-cells = <1>; 153181bee695SCaleb Connolly #size-cells = <0>; 153281bee695SCaleb Connolly status = "disabled"; 153381bee695SCaleb Connolly }; 153481bee695SCaleb Connolly 1535129e1c96SFelipe Balbi spi17: spi@c80000 { 1536129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1537129e1c96SFelipe Balbi reg = <0 0xc80000 0 0x4000>; 1538129e1c96SFelipe Balbi reg-names = "se"; 1539129e1c96SFelipe Balbi clock-names = "se"; 1540129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1541abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1542abdd4b7aSFelipe Balbi <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1543abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1544129e1c96SFelipe Balbi pinctrl-names = "default"; 1545129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi17_default>; 1546129e1c96SFelipe Balbi interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1547129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1548129e1c96SFelipe Balbi #address-cells = <1>; 1549129e1c96SFelipe Balbi #size-cells = <0>; 1550129e1c96SFelipe Balbi status = "disabled"; 1551129e1c96SFelipe Balbi }; 1552129e1c96SFelipe Balbi 155381bee695SCaleb Connolly i2c18: i2c@c84000 { 155481bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 155581bee695SCaleb Connolly reg = <0 0x00c84000 0 0x4000>; 155681bee695SCaleb Connolly clock-names = "se"; 155781bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1558abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1559abdd4b7aSFelipe Balbi <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1560abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 156181bee695SCaleb Connolly pinctrl-names = "default"; 156281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c18_default>; 156381bee695SCaleb Connolly interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 156481bee695SCaleb Connolly #address-cells = <1>; 156581bee695SCaleb Connolly #size-cells = <0>; 156681bee695SCaleb Connolly status = "disabled"; 156781bee695SCaleb Connolly }; 156881bee695SCaleb Connolly 1569129e1c96SFelipe Balbi spi18: spi@c84000 { 1570129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1571129e1c96SFelipe Balbi reg = <0 0xc84000 0 0x4000>; 1572129e1c96SFelipe Balbi reg-names = "se"; 1573129e1c96SFelipe Balbi clock-names = "se"; 1574129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1575abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1576abdd4b7aSFelipe Balbi <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1577abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1578129e1c96SFelipe Balbi pinctrl-names = "default"; 1579129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi18_default>; 1580129e1c96SFelipe Balbi interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1581129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1582129e1c96SFelipe Balbi #address-cells = <1>; 1583129e1c96SFelipe Balbi #size-cells = <0>; 1584129e1c96SFelipe Balbi status = "disabled"; 1585129e1c96SFelipe Balbi }; 1586129e1c96SFelipe Balbi 158781bee695SCaleb Connolly i2c19: i2c@c88000 { 158881bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 158981bee695SCaleb Connolly reg = <0 0x00c88000 0 0x4000>; 159081bee695SCaleb Connolly clock-names = "se"; 159181bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1592abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1593abdd4b7aSFelipe Balbi <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1594abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 159581bee695SCaleb Connolly pinctrl-names = "default"; 159681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c19_default>; 159781bee695SCaleb Connolly interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 159881bee695SCaleb Connolly #address-cells = <1>; 159981bee695SCaleb Connolly #size-cells = <0>; 160081bee695SCaleb Connolly status = "disabled"; 160181bee695SCaleb Connolly }; 160281bee695SCaleb Connolly 1603129e1c96SFelipe Balbi spi19: spi@c88000 { 1604129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1605129e1c96SFelipe Balbi reg = <0 0xc88000 0 0x4000>; 1606129e1c96SFelipe Balbi reg-names = "se"; 1607129e1c96SFelipe Balbi clock-names = "se"; 1608129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1609abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1610abdd4b7aSFelipe Balbi <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1611abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1612129e1c96SFelipe Balbi pinctrl-names = "default"; 1613129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi19_default>; 1614129e1c96SFelipe Balbi interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1615129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1616129e1c96SFelipe Balbi #address-cells = <1>; 1617129e1c96SFelipe Balbi #size-cells = <0>; 1618129e1c96SFelipe Balbi status = "disabled"; 1619129e1c96SFelipe Balbi }; 1620129e1c96SFelipe Balbi 162181bee695SCaleb Connolly i2c13: i2c@c8c000 { 162281bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 162381bee695SCaleb Connolly reg = <0 0x00c8c000 0 0x4000>; 162481bee695SCaleb Connolly clock-names = "se"; 162581bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1626abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1627abdd4b7aSFelipe Balbi <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1628abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 162981bee695SCaleb Connolly pinctrl-names = "default"; 163081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c13_default>; 163181bee695SCaleb Connolly interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 163281bee695SCaleb Connolly #address-cells = <1>; 163381bee695SCaleb Connolly #size-cells = <0>; 163481bee695SCaleb Connolly status = "disabled"; 163581bee695SCaleb Connolly }; 163681bee695SCaleb Connolly 1637129e1c96SFelipe Balbi spi13: spi@c8c000 { 1638129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1639129e1c96SFelipe Balbi reg = <0 0xc8c000 0 0x4000>; 1640129e1c96SFelipe Balbi reg-names = "se"; 1641129e1c96SFelipe Balbi clock-names = "se"; 1642129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1643abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1644abdd4b7aSFelipe Balbi <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1645abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1646129e1c96SFelipe Balbi pinctrl-names = "default"; 1647129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi13_default>; 1648129e1c96SFelipe Balbi interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1649129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1650129e1c96SFelipe Balbi #address-cells = <1>; 1651129e1c96SFelipe Balbi #size-cells = <0>; 1652129e1c96SFelipe Balbi status = "disabled"; 1653129e1c96SFelipe Balbi }; 1654129e1c96SFelipe Balbi 165581bee695SCaleb Connolly i2c14: i2c@c90000 { 165681bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 165781bee695SCaleb Connolly reg = <0 0x00c90000 0 0x4000>; 165881bee695SCaleb Connolly clock-names = "se"; 165981bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1660abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1661abdd4b7aSFelipe Balbi <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1662abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 166381bee695SCaleb Connolly pinctrl-names = "default"; 166481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c14_default>; 166581bee695SCaleb Connolly interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 166681bee695SCaleb Connolly #address-cells = <1>; 166781bee695SCaleb Connolly #size-cells = <0>; 166881bee695SCaleb Connolly status = "disabled"; 166981bee695SCaleb Connolly }; 167081bee695SCaleb Connolly 1671129e1c96SFelipe Balbi spi14: spi@c90000 { 1672129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1673129e1c96SFelipe Balbi reg = <0 0xc90000 0 0x4000>; 1674129e1c96SFelipe Balbi reg-names = "se"; 1675129e1c96SFelipe Balbi clock-names = "se"; 1676129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1677abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1678abdd4b7aSFelipe Balbi <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1679abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1680129e1c96SFelipe Balbi pinctrl-names = "default"; 1681129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi14_default>; 1682129e1c96SFelipe Balbi interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1683129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1684129e1c96SFelipe Balbi #address-cells = <1>; 1685129e1c96SFelipe Balbi #size-cells = <0>; 1686129e1c96SFelipe Balbi status = "disabled"; 1687129e1c96SFelipe Balbi }; 1688129e1c96SFelipe Balbi 168981bee695SCaleb Connolly i2c15: i2c@c94000 { 169081bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 169181bee695SCaleb Connolly reg = <0 0x00c94000 0 0x4000>; 169281bee695SCaleb Connolly clock-names = "se"; 169381bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1694abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1695abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1696abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 169781bee695SCaleb Connolly pinctrl-names = "default"; 169881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c15_default>; 169981bee695SCaleb Connolly interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 170081bee695SCaleb Connolly #address-cells = <1>; 170181bee695SCaleb Connolly #size-cells = <0>; 170281bee695SCaleb Connolly status = "disabled"; 170381bee695SCaleb Connolly }; 1704129e1c96SFelipe Balbi 1705129e1c96SFelipe Balbi spi15: spi@c94000 { 1706129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1707129e1c96SFelipe Balbi reg = <0 0xc94000 0 0x4000>; 1708129e1c96SFelipe Balbi reg-names = "se"; 1709129e1c96SFelipe Balbi clock-names = "se"; 1710129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1711abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1712abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1713abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1714129e1c96SFelipe Balbi pinctrl-names = "default"; 1715129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi15_default>; 1716129e1c96SFelipe Balbi interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1717129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1718129e1c96SFelipe Balbi #address-cells = <1>; 1719129e1c96SFelipe Balbi #size-cells = <0>; 1720129e1c96SFelipe Balbi status = "disabled"; 1721129e1c96SFelipe Balbi }; 17229cf3ebd1SCaleb Connolly }; 17239cf3ebd1SCaleb Connolly 172471a2fc6eSJonathan Marek config_noc: interconnect@1500000 { 172571a2fc6eSJonathan Marek compatible = "qcom,sm8150-config-noc"; 172671a2fc6eSJonathan Marek reg = <0 0x01500000 0 0x7400>; 172771a2fc6eSJonathan Marek #interconnect-cells = <1>; 172871a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 172971a2fc6eSJonathan Marek }; 173071a2fc6eSJonathan Marek 173171a2fc6eSJonathan Marek system_noc: interconnect@1620000 { 173271a2fc6eSJonathan Marek compatible = "qcom,sm8150-system-noc"; 173371a2fc6eSJonathan Marek reg = <0 0x01620000 0 0x19400>; 173471a2fc6eSJonathan Marek #interconnect-cells = <1>; 173571a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 173671a2fc6eSJonathan Marek }; 173771a2fc6eSJonathan Marek 173871a2fc6eSJonathan Marek mc_virt: interconnect@163a000 { 173971a2fc6eSJonathan Marek compatible = "qcom,sm8150-mc-virt"; 174071a2fc6eSJonathan Marek reg = <0 0x0163a000 0 0x1000>; 174171a2fc6eSJonathan Marek #interconnect-cells = <1>; 174271a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 174371a2fc6eSJonathan Marek }; 174471a2fc6eSJonathan Marek 174571a2fc6eSJonathan Marek aggre1_noc: interconnect@16e0000 { 174671a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre1-noc"; 174771a2fc6eSJonathan Marek reg = <0 0x016e0000 0 0xd080>; 174871a2fc6eSJonathan Marek #interconnect-cells = <1>; 174971a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 175071a2fc6eSJonathan Marek }; 175171a2fc6eSJonathan Marek 175271a2fc6eSJonathan Marek aggre2_noc: interconnect@1700000 { 175371a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre2-noc"; 175471a2fc6eSJonathan Marek reg = <0 0x01700000 0 0x20000>; 175571a2fc6eSJonathan Marek #interconnect-cells = <1>; 175671a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 175771a2fc6eSJonathan Marek }; 175871a2fc6eSJonathan Marek 175971a2fc6eSJonathan Marek compute_noc: interconnect@1720000 { 176071a2fc6eSJonathan Marek compatible = "qcom,sm8150-compute-noc"; 176171a2fc6eSJonathan Marek reg = <0 0x01720000 0 0x7000>; 176271a2fc6eSJonathan Marek #interconnect-cells = <1>; 176371a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 176471a2fc6eSJonathan Marek }; 176571a2fc6eSJonathan Marek 176671a2fc6eSJonathan Marek mmss_noc: interconnect@1740000 { 176771a2fc6eSJonathan Marek compatible = "qcom,sm8150-mmss-noc"; 176871a2fc6eSJonathan Marek reg = <0 0x01740000 0 0x1c100>; 176971a2fc6eSJonathan Marek #interconnect-cells = <1>; 177071a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 177171a2fc6eSJonathan Marek }; 177271a2fc6eSJonathan Marek 1773bb1f7cf6SSouradeep Chowdhury system-cache-controller@9200000 { 1774bb1f7cf6SSouradeep Chowdhury compatible = "qcom,sm8150-llcc"; 1775bb1f7cf6SSouradeep Chowdhury reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 1776bb1f7cf6SSouradeep Chowdhury reg-names = "llcc_base", "llcc_broadcast_base"; 1777bb1f7cf6SSouradeep Chowdhury interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1778bb1f7cf6SSouradeep Chowdhury }; 1779bb1f7cf6SSouradeep Chowdhury 1780d4b94c82SSouradeep Chowdhury dma@10a2000 { 1781d4b94c82SSouradeep Chowdhury compatible = "qcom,sm8150-dcc", "qcom,dcc"; 1782d4b94c82SSouradeep Chowdhury reg = <0x0 0x010a2000 0x0 0x1000>, 1783d4b94c82SSouradeep Chowdhury <0x0 0x010ad000 0x0 0x3000>; 1784d4b94c82SSouradeep Chowdhury }; 1785d4b94c82SSouradeep Chowdhury 1786a1c86c68SBhupesh Sharma pcie0: pci@1c00000 { 1787a1c86c68SBhupesh Sharma compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1788a1c86c68SBhupesh Sharma reg = <0 0x01c00000 0 0x3000>, 1789a1c86c68SBhupesh Sharma <0 0x60000000 0 0xf1d>, 1790a1c86c68SBhupesh Sharma <0 0x60000f20 0 0xa8>, 1791a1c86c68SBhupesh Sharma <0 0x60001000 0 0x1000>, 1792a1c86c68SBhupesh Sharma <0 0x60100000 0 0x100000>; 1793a1c86c68SBhupesh Sharma reg-names = "parf", "dbi", "elbi", "atu", "config"; 1794a1c86c68SBhupesh Sharma device_type = "pci"; 1795a1c86c68SBhupesh Sharma linux,pci-domain = <0>; 1796a1c86c68SBhupesh Sharma bus-range = <0x00 0xff>; 1797a1c86c68SBhupesh Sharma num-lanes = <1>; 1798a1c86c68SBhupesh Sharma 1799a1c86c68SBhupesh Sharma #address-cells = <3>; 1800a1c86c68SBhupesh Sharma #size-cells = <2>; 1801a1c86c68SBhupesh Sharma 1802a1c86c68SBhupesh Sharma ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1803a1c86c68SBhupesh Sharma <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1804a1c86c68SBhupesh Sharma 1805a1c86c68SBhupesh Sharma interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1806a1c86c68SBhupesh Sharma interrupt-names = "msi"; 1807a1c86c68SBhupesh Sharma #interrupt-cells = <1>; 1808a1c86c68SBhupesh Sharma interrupt-map-mask = <0 0 0 0x7>; 1809a1c86c68SBhupesh Sharma interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1810a1c86c68SBhupesh Sharma <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1811a1c86c68SBhupesh Sharma <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1812a1c86c68SBhupesh Sharma <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1813a1c86c68SBhupesh Sharma 1814a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1815a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_AUX_CLK>, 1816a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1817a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1818a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1819a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1820a1c86c68SBhupesh Sharma <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1821a1c86c68SBhupesh Sharma clock-names = "pipe", 1822a1c86c68SBhupesh Sharma "aux", 1823a1c86c68SBhupesh Sharma "cfg", 1824a1c86c68SBhupesh Sharma "bus_master", 1825a1c86c68SBhupesh Sharma "bus_slave", 1826a1c86c68SBhupesh Sharma "slave_q2a", 1827a1c86c68SBhupesh Sharma "tbu"; 1828a1c86c68SBhupesh Sharma 1829a1c86c68SBhupesh Sharma iommus = <&apps_smmu 0x1d80 0x7f>; 1830a1c86c68SBhupesh Sharma iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1831a1c86c68SBhupesh Sharma <0x100 &apps_smmu 0x1d81 0x1>; 1832a1c86c68SBhupesh Sharma 1833a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_0_BCR>; 1834a1c86c68SBhupesh Sharma reset-names = "pci"; 1835a1c86c68SBhupesh Sharma 1836a1c86c68SBhupesh Sharma power-domains = <&gcc PCIE_0_GDSC>; 1837a1c86c68SBhupesh Sharma 1838a1c86c68SBhupesh Sharma phys = <&pcie0_lane>; 1839a1c86c68SBhupesh Sharma phy-names = "pciephy"; 1840a1c86c68SBhupesh Sharma 1841a1c86c68SBhupesh Sharma perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1842a1c86c68SBhupesh Sharma enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1843a1c86c68SBhupesh Sharma 1844a1c86c68SBhupesh Sharma pinctrl-names = "default"; 1845a1c86c68SBhupesh Sharma pinctrl-0 = <&pcie0_default_state>; 1846a1c86c68SBhupesh Sharma 1847a1c86c68SBhupesh Sharma status = "disabled"; 1848a1c86c68SBhupesh Sharma }; 1849a1c86c68SBhupesh Sharma 1850a1c86c68SBhupesh Sharma pcie0_phy: phy@1c06000 { 1851a1c86c68SBhupesh Sharma compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1852a1c86c68SBhupesh Sharma reg = <0 0x01c06000 0 0x1c0>; 1853a1c86c68SBhupesh Sharma #address-cells = <2>; 1854a1c86c68SBhupesh Sharma #size-cells = <2>; 1855a1c86c68SBhupesh Sharma ranges; 1856a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1857a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1858a1c86c68SBhupesh Sharma <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1859a1c86c68SBhupesh Sharma clock-names = "aux", "cfg_ahb", "refgen"; 1860a1c86c68SBhupesh Sharma 1861a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1862a1c86c68SBhupesh Sharma reset-names = "phy"; 1863a1c86c68SBhupesh Sharma 1864a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1865a1c86c68SBhupesh Sharma assigned-clock-rates = <100000000>; 1866a1c86c68SBhupesh Sharma 1867a1c86c68SBhupesh Sharma status = "disabled"; 1868a1c86c68SBhupesh Sharma 1869a1c86c68SBhupesh Sharma pcie0_lane: phy@1c06200 { 1870a1c86c68SBhupesh Sharma reg = <0 0x1c06200 0 0x170>, /* tx */ 1871a1c86c68SBhupesh Sharma <0 0x1c06400 0 0x200>, /* rx */ 1872a1c86c68SBhupesh Sharma <0 0x1c06800 0 0x1f0>, /* pcs */ 1873a1c86c68SBhupesh Sharma <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1874a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1875a1c86c68SBhupesh Sharma clock-names = "pipe0"; 1876a1c86c68SBhupesh Sharma 1877a1c86c68SBhupesh Sharma #phy-cells = <0>; 1878a1c86c68SBhupesh Sharma clock-output-names = "pcie_0_pipe_clk"; 1879a1c86c68SBhupesh Sharma }; 1880a1c86c68SBhupesh Sharma }; 1881a1c86c68SBhupesh Sharma 1882a1c86c68SBhupesh Sharma pcie1: pci@1c08000 { 1883a1c86c68SBhupesh Sharma compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1884a1c86c68SBhupesh Sharma reg = <0 0x01c08000 0 0x3000>, 1885a1c86c68SBhupesh Sharma <0 0x40000000 0 0xf1d>, 1886a1c86c68SBhupesh Sharma <0 0x40000f20 0 0xa8>, 1887a1c86c68SBhupesh Sharma <0 0x40001000 0 0x1000>, 1888a1c86c68SBhupesh Sharma <0 0x40100000 0 0x100000>; 1889a1c86c68SBhupesh Sharma reg-names = "parf", "dbi", "elbi", "atu", "config"; 1890a1c86c68SBhupesh Sharma device_type = "pci"; 1891a1c86c68SBhupesh Sharma linux,pci-domain = <1>; 1892a1c86c68SBhupesh Sharma bus-range = <0x00 0xff>; 1893a1c86c68SBhupesh Sharma num-lanes = <2>; 1894a1c86c68SBhupesh Sharma 1895a1c86c68SBhupesh Sharma #address-cells = <3>; 1896a1c86c68SBhupesh Sharma #size-cells = <2>; 1897a1c86c68SBhupesh Sharma 1898a1c86c68SBhupesh Sharma ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1899a1c86c68SBhupesh Sharma <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1900a1c86c68SBhupesh Sharma 1901a1c86c68SBhupesh Sharma interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1902a1c86c68SBhupesh Sharma interrupt-names = "msi"; 1903a1c86c68SBhupesh Sharma #interrupt-cells = <1>; 1904a1c86c68SBhupesh Sharma interrupt-map-mask = <0 0 0 0x7>; 1905a1c86c68SBhupesh Sharma interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1906a1c86c68SBhupesh Sharma <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1907a1c86c68SBhupesh Sharma <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1908a1c86c68SBhupesh Sharma <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1909a1c86c68SBhupesh Sharma 1910a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1911a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_AUX_CLK>, 1912a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1913a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1914a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1915a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1916a1c86c68SBhupesh Sharma <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1917a1c86c68SBhupesh Sharma clock-names = "pipe", 1918a1c86c68SBhupesh Sharma "aux", 1919a1c86c68SBhupesh Sharma "cfg", 1920a1c86c68SBhupesh Sharma "bus_master", 1921a1c86c68SBhupesh Sharma "bus_slave", 1922a1c86c68SBhupesh Sharma "slave_q2a", 1923a1c86c68SBhupesh Sharma "tbu"; 1924a1c86c68SBhupesh Sharma 1925a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1926a1c86c68SBhupesh Sharma assigned-clock-rates = <19200000>; 1927a1c86c68SBhupesh Sharma 1928a1c86c68SBhupesh Sharma iommus = <&apps_smmu 0x1e00 0x7f>; 1929a1c86c68SBhupesh Sharma iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1930a1c86c68SBhupesh Sharma <0x100 &apps_smmu 0x1e01 0x1>; 1931a1c86c68SBhupesh Sharma 1932a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_1_BCR>; 1933a1c86c68SBhupesh Sharma reset-names = "pci"; 1934a1c86c68SBhupesh Sharma 1935a1c86c68SBhupesh Sharma power-domains = <&gcc PCIE_1_GDSC>; 1936a1c86c68SBhupesh Sharma 1937a1c86c68SBhupesh Sharma phys = <&pcie1_lane>; 1938a1c86c68SBhupesh Sharma phy-names = "pciephy"; 1939a1c86c68SBhupesh Sharma 1940a1c86c68SBhupesh Sharma perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; 1941a1c86c68SBhupesh Sharma enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 1942a1c86c68SBhupesh Sharma 1943a1c86c68SBhupesh Sharma pinctrl-names = "default"; 1944a1c86c68SBhupesh Sharma pinctrl-0 = <&pcie1_default_state>; 1945a1c86c68SBhupesh Sharma 1946a1c86c68SBhupesh Sharma status = "disabled"; 1947a1c86c68SBhupesh Sharma }; 1948a1c86c68SBhupesh Sharma 1949a1c86c68SBhupesh Sharma pcie1_phy: phy@1c0e000 { 1950a1c86c68SBhupesh Sharma compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 1951a1c86c68SBhupesh Sharma reg = <0 0x01c0e000 0 0x1c0>; 1952a1c86c68SBhupesh Sharma #address-cells = <2>; 1953a1c86c68SBhupesh Sharma #size-cells = <2>; 1954a1c86c68SBhupesh Sharma ranges; 1955a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1956a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1957a1c86c68SBhupesh Sharma <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1958a1c86c68SBhupesh Sharma clock-names = "aux", "cfg_ahb", "refgen"; 1959a1c86c68SBhupesh Sharma 1960a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1961a1c86c68SBhupesh Sharma reset-names = "phy"; 1962a1c86c68SBhupesh Sharma 1963a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1964a1c86c68SBhupesh Sharma assigned-clock-rates = <100000000>; 1965a1c86c68SBhupesh Sharma 1966a1c86c68SBhupesh Sharma status = "disabled"; 1967a1c86c68SBhupesh Sharma 1968a1c86c68SBhupesh Sharma pcie1_lane: phy@1c0e200 { 1969a1c86c68SBhupesh Sharma reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1970a1c86c68SBhupesh Sharma <0 0x1c0e400 0 0x200>, /* rx0 */ 1971a1c86c68SBhupesh Sharma <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1972a1c86c68SBhupesh Sharma <0 0x1c0e600 0 0x170>, /* tx1 */ 1973a1c86c68SBhupesh Sharma <0 0x1c0e800 0 0x200>, /* rx1 */ 1974a1c86c68SBhupesh Sharma <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1975a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1976a1c86c68SBhupesh Sharma clock-names = "pipe0"; 1977a1c86c68SBhupesh Sharma 1978a1c86c68SBhupesh Sharma #phy-cells = <0>; 1979a1c86c68SBhupesh Sharma clock-output-names = "pcie_1_pipe_clk"; 1980a1c86c68SBhupesh Sharma }; 1981a1c86c68SBhupesh Sharma }; 1982a1c86c68SBhupesh Sharma 19833834a2e9SVinod Koul ufs_mem_hc: ufshc@1d84000 { 19843834a2e9SVinod Koul compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 19853834a2e9SVinod Koul "jedec,ufs-2.0"; 198698aee1e3SBhupesh Sharma reg = <0 0x01d84000 0 0x2500>, 198798aee1e3SBhupesh Sharma <0 0x01d90000 0 0x8000>; 198898aee1e3SBhupesh Sharma reg-names = "std", "ice"; 19893834a2e9SVinod Koul interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 19903834a2e9SVinod Koul phys = <&ufs_mem_phy_lanes>; 19913834a2e9SVinod Koul phy-names = "ufsphy"; 19923834a2e9SVinod Koul lanes-per-direction = <2>; 19933834a2e9SVinod Koul #reset-cells = <1>; 19943834a2e9SVinod Koul resets = <&gcc GCC_UFS_PHY_BCR>; 19953834a2e9SVinod Koul reset-names = "rst"; 19963834a2e9SVinod Koul 199748156232SJonathan Marek iommus = <&apps_smmu 0x300 0>; 199848156232SJonathan Marek 19993834a2e9SVinod Koul clock-names = 20003834a2e9SVinod Koul "core_clk", 20013834a2e9SVinod Koul "bus_aggr_clk", 20023834a2e9SVinod Koul "iface_clk", 20033834a2e9SVinod Koul "core_clk_unipro", 20043834a2e9SVinod Koul "ref_clk", 20053834a2e9SVinod Koul "tx_lane0_sync_clk", 20063834a2e9SVinod Koul "rx_lane0_sync_clk", 200798aee1e3SBhupesh Sharma "rx_lane1_sync_clk", 200898aee1e3SBhupesh Sharma "ice_core_clk"; 20093834a2e9SVinod Koul clocks = 20103834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AXI_CLK>, 20113834a2e9SVinod Koul <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 20123834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AHB_CLK>, 20133834a2e9SVinod Koul <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 20143834a2e9SVinod Koul <&rpmhcc RPMH_CXO_CLK>, 20153834a2e9SVinod Koul <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 20163834a2e9SVinod Koul <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 201798aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 201898aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 20193834a2e9SVinod Koul freq-table-hz = 20203834a2e9SVinod Koul <37500000 300000000>, 20213834a2e9SVinod Koul <0 0>, 20223834a2e9SVinod Koul <0 0>, 20233834a2e9SVinod Koul <37500000 300000000>, 20243834a2e9SVinod Koul <0 0>, 20253834a2e9SVinod Koul <0 0>, 20263834a2e9SVinod Koul <0 0>, 202798aee1e3SBhupesh Sharma <0 0>, 202898aee1e3SBhupesh Sharma <0 300000000>; 20293834a2e9SVinod Koul 20303834a2e9SVinod Koul status = "disabled"; 20313834a2e9SVinod Koul }; 20323834a2e9SVinod Koul 20333834a2e9SVinod Koul ufs_mem_phy: phy@1d87000 { 20343834a2e9SVinod Koul compatible = "qcom,sm8150-qmp-ufs-phy"; 2035c79ec891SVinod Koul reg = <0 0x01d87000 0 0x1c0>; 20363834a2e9SVinod Koul #address-cells = <2>; 20373834a2e9SVinod Koul #size-cells = <2>; 20383834a2e9SVinod Koul ranges; 20393834a2e9SVinod Koul clock-names = "ref", 20403834a2e9SVinod Koul "ref_aux"; 20413834a2e9SVinod Koul clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 20423834a2e9SVinod Koul <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 20433834a2e9SVinod Koul 2044fe75b0c4SBhupesh Sharma power-domains = <&gcc UFS_PHY_GDSC>; 2045fe75b0c4SBhupesh Sharma 20463834a2e9SVinod Koul resets = <&ufs_mem_hc 0>; 20473834a2e9SVinod Koul reset-names = "ufsphy"; 20483834a2e9SVinod Koul status = "disabled"; 20493834a2e9SVinod Koul 20501351512fSShawn Guo ufs_mem_phy_lanes: phy@1d87400 { 205136a31b3aSJohan Hovold reg = <0 0x01d87400 0 0x16c>, 205236a31b3aSJohan Hovold <0 0x01d87600 0 0x200>, 205336a31b3aSJohan Hovold <0 0x01d87c00 0 0x200>, 205436a31b3aSJohan Hovold <0 0x01d87800 0 0x16c>, 205536a31b3aSJohan Hovold <0 0x01d87a00 0 0x200>; 20563834a2e9SVinod Koul #phy-cells = <0>; 20573834a2e9SVinod Koul }; 20583834a2e9SVinod Koul }; 20593834a2e9SVinod Koul 206071a2fc6eSJonathan Marek ipa_virt: interconnect@1e00000 { 206171a2fc6eSJonathan Marek compatible = "qcom,sm8150-ipa-virt"; 206271a2fc6eSJonathan Marek reg = <0 0x01e00000 0 0x1000>; 206371a2fc6eSJonathan Marek #interconnect-cells = <1>; 206471a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 206571a2fc6eSJonathan Marek }; 206671a2fc6eSJonathan Marek 2067c752d491SKrzysztof Kozlowski tcsr_mutex: hwlock@1f40000 { 2068c752d491SKrzysztof Kozlowski compatible = "qcom,tcsr-mutex"; 206986d7c946SKrzysztof Kozlowski reg = <0x0 0x01f40000 0x0 0x20000>; 2070c752d491SKrzysztof Kozlowski #hwlock-cells = <1>; 207186d7c946SKrzysztof Kozlowski }; 207286d7c946SKrzysztof Kozlowski 2073d0909bf4SJohan Hovold tcsr_regs_1: syscon@1f60000 { 207486d7c946SKrzysztof Kozlowski compatible = "qcom,sm8150-tcsr", "syscon"; 207586d7c946SKrzysztof Kozlowski reg = <0x0 0x01f60000 0x0 0x20000>; 2076d8cf9372SVinod Koul }; 2077d8cf9372SVinod Koul 207849076351SSibi Sankar remoteproc_slpi: remoteproc@2400000 { 207949076351SSibi Sankar compatible = "qcom,sm8150-slpi-pas"; 208049076351SSibi Sankar reg = <0x0 0x02400000 0x0 0x4040>; 208149076351SSibi Sankar 208249076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 208349076351SSibi Sankar <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 208449076351SSibi Sankar <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 208549076351SSibi Sankar <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 208649076351SSibi Sankar <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 208749076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 208849076351SSibi Sankar "handover", "stop-ack"; 208949076351SSibi Sankar 209049076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 209149076351SSibi Sankar clock-names = "xo"; 209249076351SSibi Sankar 2093a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_LCX>, 2094a94ed9f3SKonrad Dybcio <&rpmhpd SM8150_LMX>; 2095d9d327f6SSibi Sankar power-domain-names = "lcx", "lmx"; 209649076351SSibi Sankar 209749076351SSibi Sankar memory-region = <&slpi_mem>; 209849076351SSibi Sankar 2099d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 2100d9d327f6SSibi Sankar 210149076351SSibi Sankar qcom,smem-states = <&slpi_smp2p_out 0>; 210249076351SSibi Sankar qcom,smem-state-names = "stop"; 210349076351SSibi Sankar 210449076351SSibi Sankar status = "disabled"; 210549076351SSibi Sankar 210649076351SSibi Sankar glink-edge { 210749076351SSibi Sankar interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 210849076351SSibi Sankar label = "dsps"; 210949076351SSibi Sankar qcom,remote-pid = <3>; 211049076351SSibi Sankar mboxes = <&apss_shared 24>; 211181729330SBhupesh Sharma 211281729330SBhupesh Sharma fastrpc { 211381729330SBhupesh Sharma compatible = "qcom,fastrpc"; 211481729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 211581729330SBhupesh Sharma label = "sdsp"; 21168c8ce95bSJeya R qcom,non-secure-domain; 211781729330SBhupesh Sharma #address-cells = <1>; 211881729330SBhupesh Sharma #size-cells = <0>; 211981729330SBhupesh Sharma 212081729330SBhupesh Sharma compute-cb@1 { 212181729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 212281729330SBhupesh Sharma reg = <1>; 212381729330SBhupesh Sharma iommus = <&apps_smmu 0x05a1 0x0>; 212481729330SBhupesh Sharma }; 212581729330SBhupesh Sharma 212681729330SBhupesh Sharma compute-cb@2 { 212781729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 212881729330SBhupesh Sharma reg = <2>; 212981729330SBhupesh Sharma iommus = <&apps_smmu 0x05a2 0x0>; 213081729330SBhupesh Sharma }; 213181729330SBhupesh Sharma 213281729330SBhupesh Sharma compute-cb@3 { 213381729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 213481729330SBhupesh Sharma reg = <3>; 213581729330SBhupesh Sharma iommus = <&apps_smmu 0x05a3 0x0>; 213681729330SBhupesh Sharma /* note: shared-cb = <4> in downstream */ 213781729330SBhupesh Sharma }; 213881729330SBhupesh Sharma }; 213949076351SSibi Sankar }; 214049076351SSibi Sankar }; 214149076351SSibi Sankar 2142f30ac26dSJonathan Marek gpu: gpu@2c00000 { 2143f30ac26dSJonathan Marek /* 2144f30ac26dSJonathan Marek * note: the amd,imageon compatible makes it possible 2145f30ac26dSJonathan Marek * to use the drm/msm driver without the display node, 2146f30ac26dSJonathan Marek * make sure to remove it when display node is added 2147f30ac26dSJonathan Marek */ 2148f30ac26dSJonathan Marek compatible = "qcom,adreno-640.1", 2149f30ac26dSJonathan Marek "qcom,adreno", 2150f30ac26dSJonathan Marek "amd,imageon"; 2151f30ac26dSJonathan Marek 2152f30ac26dSJonathan Marek reg = <0 0x02c00000 0 0x40000>; 2153f30ac26dSJonathan Marek reg-names = "kgsl_3d0_reg_memory"; 2154f30ac26dSJonathan Marek 2155f30ac26dSJonathan Marek interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2156f30ac26dSJonathan Marek 2157f30ac26dSJonathan Marek iommus = <&adreno_smmu 0 0x401>; 2158f30ac26dSJonathan Marek 2159f30ac26dSJonathan Marek operating-points-v2 = <&gpu_opp_table>; 2160f30ac26dSJonathan Marek 2161f30ac26dSJonathan Marek qcom,gmu = <&gmu>; 2162f30ac26dSJonathan Marek 2163b1dc3c6bSKonrad Dybcio status = "disabled"; 2164b1dc3c6bSKonrad Dybcio 2165f30ac26dSJonathan Marek zap-shader { 2166f30ac26dSJonathan Marek memory-region = <&gpu_mem>; 2167f30ac26dSJonathan Marek }; 2168f30ac26dSJonathan Marek 2169f30ac26dSJonathan Marek /* note: downstream checks gpu binning for 675 Mhz */ 2170f30ac26dSJonathan Marek gpu_opp_table: opp-table { 2171f30ac26dSJonathan Marek compatible = "operating-points-v2"; 2172f30ac26dSJonathan Marek 2173f30ac26dSJonathan Marek opp-675000000 { 2174f30ac26dSJonathan Marek opp-hz = /bits/ 64 <675000000>; 2175f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2176f30ac26dSJonathan Marek }; 2177f30ac26dSJonathan Marek 2178f30ac26dSJonathan Marek opp-585000000 { 2179f30ac26dSJonathan Marek opp-hz = /bits/ 64 <585000000>; 2180f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2181f30ac26dSJonathan Marek }; 2182f30ac26dSJonathan Marek 2183f30ac26dSJonathan Marek opp-499200000 { 2184f30ac26dSJonathan Marek opp-hz = /bits/ 64 <499200000>; 2185f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2186f30ac26dSJonathan Marek }; 2187f30ac26dSJonathan Marek 2188f30ac26dSJonathan Marek opp-427000000 { 2189f30ac26dSJonathan Marek opp-hz = /bits/ 64 <427000000>; 2190f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2191f30ac26dSJonathan Marek }; 2192f30ac26dSJonathan Marek 2193f30ac26dSJonathan Marek opp-345000000 { 2194f30ac26dSJonathan Marek opp-hz = /bits/ 64 <345000000>; 2195f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2196f30ac26dSJonathan Marek }; 2197f30ac26dSJonathan Marek 2198f30ac26dSJonathan Marek opp-257000000 { 2199f30ac26dSJonathan Marek opp-hz = /bits/ 64 <257000000>; 2200f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2201f30ac26dSJonathan Marek }; 2202f30ac26dSJonathan Marek }; 2203f30ac26dSJonathan Marek }; 2204f30ac26dSJonathan Marek 2205f30ac26dSJonathan Marek gmu: gmu@2c6a000 { 2206f30ac26dSJonathan Marek compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2207f30ac26dSJonathan Marek 2208f30ac26dSJonathan Marek reg = <0 0x02c6a000 0 0x30000>, 2209f30ac26dSJonathan Marek <0 0x0b290000 0 0x10000>, 2210f30ac26dSJonathan Marek <0 0x0b490000 0 0x10000>; 2211f30ac26dSJonathan Marek reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2212f30ac26dSJonathan Marek 2213f30ac26dSJonathan Marek interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2214f30ac26dSJonathan Marek <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2215f30ac26dSJonathan Marek interrupt-names = "hfi", "gmu"; 2216f30ac26dSJonathan Marek 2217f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 2218f1269916SJonathan Marek <&gpucc GPU_CC_CX_GMU_CLK>, 2219f1269916SJonathan Marek <&gpucc GPU_CC_CXO_CLK>, 2220f30ac26dSJonathan Marek <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2221f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2222f30ac26dSJonathan Marek clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2223f30ac26dSJonathan Marek 2224f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>, 2225f1269916SJonathan Marek <&gpucc GPU_GX_GDSC>; 2226f30ac26dSJonathan Marek power-domain-names = "cx", "gx"; 2227f30ac26dSJonathan Marek 2228f30ac26dSJonathan Marek iommus = <&adreno_smmu 5 0x400>; 2229f30ac26dSJonathan Marek 2230f30ac26dSJonathan Marek operating-points-v2 = <&gmu_opp_table>; 2231f30ac26dSJonathan Marek 2232b1dc3c6bSKonrad Dybcio status = "disabled"; 2233b1dc3c6bSKonrad Dybcio 2234f30ac26dSJonathan Marek gmu_opp_table: opp-table { 2235f30ac26dSJonathan Marek compatible = "operating-points-v2"; 2236f30ac26dSJonathan Marek 2237f30ac26dSJonathan Marek opp-200000000 { 2238f30ac26dSJonathan Marek opp-hz = /bits/ 64 <200000000>; 2239f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2240f30ac26dSJonathan Marek }; 2241f30ac26dSJonathan Marek }; 2242f30ac26dSJonathan Marek }; 2243f30ac26dSJonathan Marek 2244f30ac26dSJonathan Marek gpucc: clock-controller@2c90000 { 2245f30ac26dSJonathan Marek compatible = "qcom,sm8150-gpucc"; 2246f30ac26dSJonathan Marek reg = <0 0x02c90000 0 0x9000>; 2247f30ac26dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>, 2248f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2249f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2250f30ac26dSJonathan Marek clock-names = "bi_tcxo", 2251f30ac26dSJonathan Marek "gcc_gpu_gpll0_clk_src", 2252f30ac26dSJonathan Marek "gcc_gpu_gpll0_div_clk_src"; 2253f30ac26dSJonathan Marek #clock-cells = <1>; 2254f30ac26dSJonathan Marek #reset-cells = <1>; 2255f30ac26dSJonathan Marek #power-domain-cells = <1>; 2256f30ac26dSJonathan Marek }; 2257f30ac26dSJonathan Marek 2258f30ac26dSJonathan Marek adreno_smmu: iommu@2ca0000 { 2259c34bef62SMarijn Suijten compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2260f30ac26dSJonathan Marek reg = <0 0x02ca0000 0 0x10000>; 2261f30ac26dSJonathan Marek #iommu-cells = <2>; 2262f30ac26dSJonathan Marek #global-interrupts = <1>; 2263f30ac26dSJonathan Marek interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2264f30ac26dSJonathan Marek <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2265f30ac26dSJonathan Marek <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2266f30ac26dSJonathan Marek <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2267f30ac26dSJonathan Marek <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2268f30ac26dSJonathan Marek <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2269f30ac26dSJonathan Marek <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2270f30ac26dSJonathan Marek <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2271f30ac26dSJonathan Marek <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2272f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 2273f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2274f30ac26dSJonathan Marek <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2275f30ac26dSJonathan Marek clock-names = "ahb", "bus", "iface"; 2276f30ac26dSJonathan Marek 2277f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>; 2278f30ac26dSJonathan Marek }; 2279f30ac26dSJonathan Marek 2280e13c6d14SVinod Koul tlmm: pinctrl@3100000 { 2281e13c6d14SVinod Koul compatible = "qcom,sm8150-pinctrl"; 2282e13c6d14SVinod Koul reg = <0x0 0x03100000 0x0 0x300000>, 2283e13c6d14SVinod Koul <0x0 0x03500000 0x0 0x300000>, 2284e13c6d14SVinod Koul <0x0 0x03900000 0x0 0x300000>, 2285e13c6d14SVinod Koul <0x0 0x03D00000 0x0 0x300000>; 2286e13c6d14SVinod Koul reg-names = "west", "east", "north", "south"; 2287e13c6d14SVinod Koul interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2288de3abdf3SShawn Guo gpio-ranges = <&tlmm 0 0 176>; 2289e13c6d14SVinod Koul gpio-controller; 2290e13c6d14SVinod Koul #gpio-cells = <2>; 2291e13c6d14SVinod Koul interrupt-controller; 2292e13c6d14SVinod Koul #interrupt-cells = <2>; 22936127d8e4SBhupesh Sharma wakeup-parent = <&pdc>; 229481bee695SCaleb Connolly 2295028fe09cSKrzysztof Kozlowski qup_i2c0_default: qup-i2c0-default-state { 229681bee695SCaleb Connolly pins = "gpio0", "gpio1"; 229781bee695SCaleb Connolly function = "qup0"; 229881bee695SCaleb Connolly drive-strength = <0x02>; 229981bee695SCaleb Connolly bias-disable; 230081bee695SCaleb Connolly }; 230181bee695SCaleb Connolly 2302028fe09cSKrzysztof Kozlowski qup_spi0_default: qup-spi0-default-state { 2303129e1c96SFelipe Balbi pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2304129e1c96SFelipe Balbi function = "qup0"; 2305129e1c96SFelipe Balbi drive-strength = <6>; 2306129e1c96SFelipe Balbi bias-disable; 2307129e1c96SFelipe Balbi }; 2308129e1c96SFelipe Balbi 2309028fe09cSKrzysztof Kozlowski qup_i2c1_default: qup-i2c1-default-state { 231081bee695SCaleb Connolly pins = "gpio114", "gpio115"; 231181bee695SCaleb Connolly function = "qup1"; 2312028fe09cSKrzysztof Kozlowski drive-strength = <2>; 231381bee695SCaleb Connolly bias-disable; 231481bee695SCaleb Connolly }; 231581bee695SCaleb Connolly 2316028fe09cSKrzysztof Kozlowski qup_spi1_default: qup-spi1-default-state { 2317129e1c96SFelipe Balbi pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2318129e1c96SFelipe Balbi function = "qup1"; 2319129e1c96SFelipe Balbi drive-strength = <6>; 2320129e1c96SFelipe Balbi bias-disable; 2321129e1c96SFelipe Balbi }; 2322129e1c96SFelipe Balbi 2323028fe09cSKrzysztof Kozlowski qup_i2c2_default: qup-i2c2-default-state { 232481bee695SCaleb Connolly pins = "gpio126", "gpio127"; 232581bee695SCaleb Connolly function = "qup2"; 2326028fe09cSKrzysztof Kozlowski drive-strength = <2>; 232781bee695SCaleb Connolly bias-disable; 232881bee695SCaleb Connolly }; 232981bee695SCaleb Connolly 2330028fe09cSKrzysztof Kozlowski qup_spi2_default: qup-spi2-default-state { 2331129e1c96SFelipe Balbi pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2332129e1c96SFelipe Balbi function = "qup2"; 2333129e1c96SFelipe Balbi drive-strength = <6>; 2334129e1c96SFelipe Balbi bias-disable; 2335129e1c96SFelipe Balbi }; 2336129e1c96SFelipe Balbi 2337028fe09cSKrzysztof Kozlowski qup_i2c3_default: qup-i2c3-default-state { 233881bee695SCaleb Connolly pins = "gpio144", "gpio145"; 233981bee695SCaleb Connolly function = "qup3"; 2340028fe09cSKrzysztof Kozlowski drive-strength = <2>; 234181bee695SCaleb Connolly bias-disable; 234281bee695SCaleb Connolly }; 234381bee695SCaleb Connolly 2344028fe09cSKrzysztof Kozlowski qup_spi3_default: qup-spi3-default-state { 2345129e1c96SFelipe Balbi pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2346129e1c96SFelipe Balbi function = "qup3"; 2347129e1c96SFelipe Balbi drive-strength = <6>; 2348129e1c96SFelipe Balbi bias-disable; 2349129e1c96SFelipe Balbi }; 2350129e1c96SFelipe Balbi 2351028fe09cSKrzysztof Kozlowski qup_i2c4_default: qup-i2c4-default-state { 235281bee695SCaleb Connolly pins = "gpio51", "gpio52"; 235381bee695SCaleb Connolly function = "qup4"; 2354028fe09cSKrzysztof Kozlowski drive-strength = <2>; 235581bee695SCaleb Connolly bias-disable; 235681bee695SCaleb Connolly }; 235781bee695SCaleb Connolly 2358028fe09cSKrzysztof Kozlowski qup_spi4_default: qup-spi4-default-state { 2359129e1c96SFelipe Balbi pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2360129e1c96SFelipe Balbi function = "qup4"; 2361129e1c96SFelipe Balbi drive-strength = <6>; 2362129e1c96SFelipe Balbi bias-disable; 2363129e1c96SFelipe Balbi }; 2364129e1c96SFelipe Balbi 2365028fe09cSKrzysztof Kozlowski qup_i2c5_default: qup-i2c5-default-state { 236681bee695SCaleb Connolly pins = "gpio121", "gpio122"; 236781bee695SCaleb Connolly function = "qup5"; 2368028fe09cSKrzysztof Kozlowski drive-strength = <2>; 236981bee695SCaleb Connolly bias-disable; 237081bee695SCaleb Connolly }; 237181bee695SCaleb Connolly 2372028fe09cSKrzysztof Kozlowski qup_spi5_default: qup-spi5-default-state { 2373129e1c96SFelipe Balbi pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2374129e1c96SFelipe Balbi function = "qup5"; 2375129e1c96SFelipe Balbi drive-strength = <6>; 2376129e1c96SFelipe Balbi bias-disable; 2377129e1c96SFelipe Balbi }; 2378129e1c96SFelipe Balbi 2379028fe09cSKrzysztof Kozlowski qup_i2c6_default: qup-i2c6-default-state { 238081bee695SCaleb Connolly pins = "gpio6", "gpio7"; 238181bee695SCaleb Connolly function = "qup6"; 2382028fe09cSKrzysztof Kozlowski drive-strength = <2>; 238381bee695SCaleb Connolly bias-disable; 238481bee695SCaleb Connolly }; 238581bee695SCaleb Connolly 2386028fe09cSKrzysztof Kozlowski qup_spi6_default: qup-spi6_default-state { 2387129e1c96SFelipe Balbi pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2388129e1c96SFelipe Balbi function = "qup6"; 2389129e1c96SFelipe Balbi drive-strength = <6>; 2390129e1c96SFelipe Balbi bias-disable; 2391129e1c96SFelipe Balbi }; 2392129e1c96SFelipe Balbi 2393028fe09cSKrzysztof Kozlowski qup_i2c7_default: qup-i2c7-default-state { 239481bee695SCaleb Connolly pins = "gpio98", "gpio99"; 239581bee695SCaleb Connolly function = "qup7"; 2396028fe09cSKrzysztof Kozlowski drive-strength = <2>; 239781bee695SCaleb Connolly bias-disable; 239881bee695SCaleb Connolly }; 239981bee695SCaleb Connolly 2400028fe09cSKrzysztof Kozlowski qup_spi7_default: qup-spi7_default-state { 2401129e1c96SFelipe Balbi pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2402129e1c96SFelipe Balbi function = "qup7"; 2403129e1c96SFelipe Balbi drive-strength = <6>; 2404129e1c96SFelipe Balbi bias-disable; 2405129e1c96SFelipe Balbi }; 2406129e1c96SFelipe Balbi 2407028fe09cSKrzysztof Kozlowski qup_i2c8_default: qup-i2c8-default-state { 240881bee695SCaleb Connolly pins = "gpio88", "gpio89"; 240981bee695SCaleb Connolly function = "qup8"; 2410028fe09cSKrzysztof Kozlowski drive-strength = <2>; 241181bee695SCaleb Connolly bias-disable; 241281bee695SCaleb Connolly }; 241381bee695SCaleb Connolly 2414028fe09cSKrzysztof Kozlowski qup_spi8_default: qup-spi8-default-state { 2415129e1c96SFelipe Balbi pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2416129e1c96SFelipe Balbi function = "qup8"; 2417129e1c96SFelipe Balbi drive-strength = <6>; 2418129e1c96SFelipe Balbi bias-disable; 2419129e1c96SFelipe Balbi }; 2420129e1c96SFelipe Balbi 2421028fe09cSKrzysztof Kozlowski qup_i2c9_default: qup-i2c9-default-state { 242281bee695SCaleb Connolly pins = "gpio39", "gpio40"; 242381bee695SCaleb Connolly function = "qup9"; 2424028fe09cSKrzysztof Kozlowski drive-strength = <2>; 242581bee695SCaleb Connolly bias-disable; 242681bee695SCaleb Connolly }; 242781bee695SCaleb Connolly 2428028fe09cSKrzysztof Kozlowski qup_spi9_default: qup-spi9-default-state { 2429129e1c96SFelipe Balbi pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2430129e1c96SFelipe Balbi function = "qup9"; 2431129e1c96SFelipe Balbi drive-strength = <6>; 2432129e1c96SFelipe Balbi bias-disable; 2433129e1c96SFelipe Balbi }; 2434129e1c96SFelipe Balbi 2435028fe09cSKrzysztof Kozlowski qup_i2c10_default: qup-i2c10-default-state { 243681bee695SCaleb Connolly pins = "gpio9", "gpio10"; 243781bee695SCaleb Connolly function = "qup10"; 2438028fe09cSKrzysztof Kozlowski drive-strength = <2>; 243981bee695SCaleb Connolly bias-disable; 244081bee695SCaleb Connolly }; 244181bee695SCaleb Connolly 2442028fe09cSKrzysztof Kozlowski qup_spi10_default: qup-spi10-default-state { 2443129e1c96SFelipe Balbi pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2444129e1c96SFelipe Balbi function = "qup10"; 2445129e1c96SFelipe Balbi drive-strength = <6>; 2446129e1c96SFelipe Balbi bias-disable; 2447129e1c96SFelipe Balbi }; 2448129e1c96SFelipe Balbi 2449028fe09cSKrzysztof Kozlowski qup_i2c11_default: qup-i2c11-default-state { 245081bee695SCaleb Connolly pins = "gpio94", "gpio95"; 245181bee695SCaleb Connolly function = "qup11"; 2452028fe09cSKrzysztof Kozlowski drive-strength = <2>; 245381bee695SCaleb Connolly bias-disable; 245481bee695SCaleb Connolly }; 245581bee695SCaleb Connolly 2456028fe09cSKrzysztof Kozlowski qup_spi11_default: qup-spi11-default-state { 2457129e1c96SFelipe Balbi pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2458129e1c96SFelipe Balbi function = "qup11"; 2459129e1c96SFelipe Balbi drive-strength = <6>; 2460129e1c96SFelipe Balbi bias-disable; 2461129e1c96SFelipe Balbi }; 2462129e1c96SFelipe Balbi 2463028fe09cSKrzysztof Kozlowski qup_i2c12_default: qup-i2c12-default-state { 246481bee695SCaleb Connolly pins = "gpio83", "gpio84"; 246581bee695SCaleb Connolly function = "qup12"; 2466028fe09cSKrzysztof Kozlowski drive-strength = <2>; 246781bee695SCaleb Connolly bias-disable; 246881bee695SCaleb Connolly }; 246981bee695SCaleb Connolly 2470028fe09cSKrzysztof Kozlowski qup_spi12_default: qup-spi12-default-state { 2471129e1c96SFelipe Balbi pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2472129e1c96SFelipe Balbi function = "qup12"; 2473129e1c96SFelipe Balbi drive-strength = <6>; 2474129e1c96SFelipe Balbi bias-disable; 2475129e1c96SFelipe Balbi }; 2476129e1c96SFelipe Balbi 2477028fe09cSKrzysztof Kozlowski qup_i2c13_default: qup-i2c13-default-state { 247881bee695SCaleb Connolly pins = "gpio43", "gpio44"; 247981bee695SCaleb Connolly function = "qup13"; 2480028fe09cSKrzysztof Kozlowski drive-strength = <2>; 248181bee695SCaleb Connolly bias-disable; 248281bee695SCaleb Connolly }; 248381bee695SCaleb Connolly 2484028fe09cSKrzysztof Kozlowski qup_spi13_default: qup-spi13-default-state { 2485129e1c96SFelipe Balbi pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2486129e1c96SFelipe Balbi function = "qup13"; 2487129e1c96SFelipe Balbi drive-strength = <6>; 2488129e1c96SFelipe Balbi bias-disable; 2489129e1c96SFelipe Balbi }; 2490129e1c96SFelipe Balbi 2491028fe09cSKrzysztof Kozlowski qup_i2c14_default: qup-i2c14-default-state { 249281bee695SCaleb Connolly pins = "gpio47", "gpio48"; 249381bee695SCaleb Connolly function = "qup14"; 2494028fe09cSKrzysztof Kozlowski drive-strength = <2>; 249581bee695SCaleb Connolly bias-disable; 249681bee695SCaleb Connolly }; 249781bee695SCaleb Connolly 2498028fe09cSKrzysztof Kozlowski qup_spi14_default: qup-spi14-default-state { 2499129e1c96SFelipe Balbi pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2500129e1c96SFelipe Balbi function = "qup14"; 2501129e1c96SFelipe Balbi drive-strength = <6>; 2502129e1c96SFelipe Balbi bias-disable; 2503129e1c96SFelipe Balbi }; 2504129e1c96SFelipe Balbi 2505028fe09cSKrzysztof Kozlowski qup_i2c15_default: qup-i2c15-default-state { 250681bee695SCaleb Connolly pins = "gpio27", "gpio28"; 250781bee695SCaleb Connolly function = "qup15"; 2508028fe09cSKrzysztof Kozlowski drive-strength = <2>; 250981bee695SCaleb Connolly bias-disable; 251081bee695SCaleb Connolly }; 251181bee695SCaleb Connolly 2512028fe09cSKrzysztof Kozlowski qup_spi15_default: qup-spi15-default-state { 2513129e1c96SFelipe Balbi pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2514129e1c96SFelipe Balbi function = "qup15"; 2515129e1c96SFelipe Balbi drive-strength = <6>; 2516129e1c96SFelipe Balbi bias-disable; 2517129e1c96SFelipe Balbi }; 2518129e1c96SFelipe Balbi 2519028fe09cSKrzysztof Kozlowski qup_i2c16_default: qup-i2c16-default-state { 252081bee695SCaleb Connolly pins = "gpio86", "gpio85"; 252181bee695SCaleb Connolly function = "qup16"; 2522028fe09cSKrzysztof Kozlowski drive-strength = <2>; 252381bee695SCaleb Connolly bias-disable; 252481bee695SCaleb Connolly }; 252581bee695SCaleb Connolly 2526028fe09cSKrzysztof Kozlowski qup_spi16_default: qup-spi16-default-state { 2527129e1c96SFelipe Balbi pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2528129e1c96SFelipe Balbi function = "qup16"; 2529129e1c96SFelipe Balbi drive-strength = <6>; 2530129e1c96SFelipe Balbi bias-disable; 2531129e1c96SFelipe Balbi }; 2532129e1c96SFelipe Balbi 2533028fe09cSKrzysztof Kozlowski qup_i2c17_default: qup-i2c17-default-state { 253481bee695SCaleb Connolly pins = "gpio55", "gpio56"; 253581bee695SCaleb Connolly function = "qup17"; 2536028fe09cSKrzysztof Kozlowski drive-strength = <2>; 253781bee695SCaleb Connolly bias-disable; 253881bee695SCaleb Connolly }; 253981bee695SCaleb Connolly 2540028fe09cSKrzysztof Kozlowski qup_spi17_default: qup-spi17-default-state { 2541129e1c96SFelipe Balbi pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2542129e1c96SFelipe Balbi function = "qup17"; 2543129e1c96SFelipe Balbi drive-strength = <6>; 2544129e1c96SFelipe Balbi bias-disable; 2545129e1c96SFelipe Balbi }; 2546129e1c96SFelipe Balbi 2547028fe09cSKrzysztof Kozlowski qup_i2c18_default: qup-i2c18-default-state { 254881bee695SCaleb Connolly pins = "gpio23", "gpio24"; 254981bee695SCaleb Connolly function = "qup18"; 2550028fe09cSKrzysztof Kozlowski drive-strength = <2>; 255181bee695SCaleb Connolly bias-disable; 255281bee695SCaleb Connolly }; 255381bee695SCaleb Connolly 2554028fe09cSKrzysztof Kozlowski qup_spi18_default: qup-spi18-default-state { 2555129e1c96SFelipe Balbi pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2556129e1c96SFelipe Balbi function = "qup18"; 2557129e1c96SFelipe Balbi drive-strength = <6>; 2558129e1c96SFelipe Balbi bias-disable; 2559129e1c96SFelipe Balbi }; 2560129e1c96SFelipe Balbi 2561028fe09cSKrzysztof Kozlowski qup_i2c19_default: qup-i2c19-default-state { 256281bee695SCaleb Connolly pins = "gpio57", "gpio58"; 256381bee695SCaleb Connolly function = "qup19"; 2564028fe09cSKrzysztof Kozlowski drive-strength = <2>; 256581bee695SCaleb Connolly bias-disable; 256681bee695SCaleb Connolly }; 2567129e1c96SFelipe Balbi 2568028fe09cSKrzysztof Kozlowski qup_spi19_default: qup-spi19-default-state { 2569129e1c96SFelipe Balbi pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2570129e1c96SFelipe Balbi function = "qup19"; 2571129e1c96SFelipe Balbi drive-strength = <6>; 2572129e1c96SFelipe Balbi bias-disable; 2573129e1c96SFelipe Balbi }; 2574a1c86c68SBhupesh Sharma 2575028fe09cSKrzysztof Kozlowski pcie0_default_state: pcie0-default-state { 2576028fe09cSKrzysztof Kozlowski perst-pins { 2577a1c86c68SBhupesh Sharma pins = "gpio35"; 2578a1c86c68SBhupesh Sharma function = "gpio"; 2579a1c86c68SBhupesh Sharma drive-strength = <2>; 2580a1c86c68SBhupesh Sharma bias-pull-down; 2581a1c86c68SBhupesh Sharma }; 2582a1c86c68SBhupesh Sharma 2583028fe09cSKrzysztof Kozlowski clkreq-pins { 2584a1c86c68SBhupesh Sharma pins = "gpio36"; 2585a1c86c68SBhupesh Sharma function = "pci_e0"; 2586a1c86c68SBhupesh Sharma drive-strength = <2>; 2587a1c86c68SBhupesh Sharma bias-pull-up; 2588a1c86c68SBhupesh Sharma }; 2589a1c86c68SBhupesh Sharma 2590028fe09cSKrzysztof Kozlowski wake-pins { 2591a1c86c68SBhupesh Sharma pins = "gpio37"; 2592a1c86c68SBhupesh Sharma function = "gpio"; 2593a1c86c68SBhupesh Sharma drive-strength = <2>; 2594a1c86c68SBhupesh Sharma bias-pull-up; 2595a1c86c68SBhupesh Sharma }; 2596a1c86c68SBhupesh Sharma }; 2597a1c86c68SBhupesh Sharma 2598028fe09cSKrzysztof Kozlowski pcie1_default_state: pcie1-default-state { 2599028fe09cSKrzysztof Kozlowski perst-pins { 2600a1c86c68SBhupesh Sharma pins = "gpio102"; 2601a1c86c68SBhupesh Sharma function = "gpio"; 2602a1c86c68SBhupesh Sharma drive-strength = <2>; 2603a1c86c68SBhupesh Sharma bias-pull-down; 2604a1c86c68SBhupesh Sharma }; 2605a1c86c68SBhupesh Sharma 2606028fe09cSKrzysztof Kozlowski clkreq-pins { 2607a1c86c68SBhupesh Sharma pins = "gpio103"; 2608a1c86c68SBhupesh Sharma function = "pci_e1"; 2609a1c86c68SBhupesh Sharma drive-strength = <2>; 2610a1c86c68SBhupesh Sharma bias-pull-up; 2611a1c86c68SBhupesh Sharma }; 2612a1c86c68SBhupesh Sharma 2613028fe09cSKrzysztof Kozlowski wake-pins { 2614a1c86c68SBhupesh Sharma pins = "gpio104"; 2615a1c86c68SBhupesh Sharma function = "gpio"; 2616a1c86c68SBhupesh Sharma drive-strength = <2>; 2617a1c86c68SBhupesh Sharma bias-pull-up; 2618a1c86c68SBhupesh Sharma }; 2619a1c86c68SBhupesh Sharma }; 2620e13c6d14SVinod Koul }; 2621e13c6d14SVinod Koul 262249076351SSibi Sankar remoteproc_mpss: remoteproc@4080000 { 262349076351SSibi Sankar compatible = "qcom,sm8150-mpss-pas"; 262449076351SSibi Sankar reg = <0x0 0x04080000 0x0 0x4040>; 262549076351SSibi Sankar 262649076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 262749076351SSibi Sankar <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 262849076351SSibi Sankar <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 262949076351SSibi Sankar <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 263049076351SSibi Sankar <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 263149076351SSibi Sankar <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 263249076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", "handover", 263349076351SSibi Sankar "stop-ack", "shutdown-ack"; 263449076351SSibi Sankar 263549076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 263649076351SSibi Sankar clock-names = "xo"; 263749076351SSibi Sankar 2638a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_CX>, 2639a94ed9f3SKonrad Dybcio <&rpmhpd SM8150_MSS>; 2640d9d327f6SSibi Sankar power-domain-names = "cx", "mss"; 264149076351SSibi Sankar 264249076351SSibi Sankar memory-region = <&mpss_mem>; 264349076351SSibi Sankar 2644d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 2645d9d327f6SSibi Sankar 264649076351SSibi Sankar qcom,smem-states = <&modem_smp2p_out 0>; 264749076351SSibi Sankar qcom,smem-state-names = "stop"; 264849076351SSibi Sankar 2649b1dc3c6bSKonrad Dybcio status = "disabled"; 2650b1dc3c6bSKonrad Dybcio 265149076351SSibi Sankar glink-edge { 265249076351SSibi Sankar interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 265349076351SSibi Sankar label = "modem"; 265449076351SSibi Sankar qcom,remote-pid = <1>; 265549076351SSibi Sankar mboxes = <&apss_shared 12>; 265649076351SSibi Sankar }; 265749076351SSibi Sankar }; 265849076351SSibi Sankar 265924244cefSSai Prakash Ranjan stm@6002000 { 266024244cefSSai Prakash Ranjan compatible = "arm,coresight-stm", "arm,primecell"; 266124244cefSSai Prakash Ranjan reg = <0 0x06002000 0 0x1000>, 266224244cefSSai Prakash Ranjan <0 0x16280000 0 0x180000>; 266324244cefSSai Prakash Ranjan reg-names = "stm-base", "stm-stimulus-base"; 266424244cefSSai Prakash Ranjan 266524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 266624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 266724244cefSSai Prakash Ranjan 266824244cefSSai Prakash Ranjan out-ports { 266924244cefSSai Prakash Ranjan port { 267024244cefSSai Prakash Ranjan stm_out: endpoint { 267124244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_in7>; 267224244cefSSai Prakash Ranjan }; 267324244cefSSai Prakash Ranjan }; 267424244cefSSai Prakash Ranjan }; 267524244cefSSai Prakash Ranjan }; 267624244cefSSai Prakash Ranjan 267724244cefSSai Prakash Ranjan funnel@6041000 { 267824244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 267924244cefSSai Prakash Ranjan reg = <0 0x06041000 0 0x1000>; 268024244cefSSai Prakash Ranjan 268124244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 268224244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 268324244cefSSai Prakash Ranjan 268424244cefSSai Prakash Ranjan out-ports { 268524244cefSSai Prakash Ranjan port { 268624244cefSSai Prakash Ranjan funnel0_out: endpoint { 268724244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in0>; 268824244cefSSai Prakash Ranjan }; 268924244cefSSai Prakash Ranjan }; 269024244cefSSai Prakash Ranjan }; 269124244cefSSai Prakash Ranjan 269224244cefSSai Prakash Ranjan in-ports { 269324244cefSSai Prakash Ranjan #address-cells = <1>; 269424244cefSSai Prakash Ranjan #size-cells = <0>; 269524244cefSSai Prakash Ranjan 269624244cefSSai Prakash Ranjan port@7 { 269724244cefSSai Prakash Ranjan reg = <7>; 269824244cefSSai Prakash Ranjan funnel0_in7: endpoint { 269924244cefSSai Prakash Ranjan remote-endpoint = <&stm_out>; 270024244cefSSai Prakash Ranjan }; 270124244cefSSai Prakash Ranjan }; 270224244cefSSai Prakash Ranjan }; 270324244cefSSai Prakash Ranjan }; 270424244cefSSai Prakash Ranjan 270524244cefSSai Prakash Ranjan funnel@6042000 { 270624244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 270724244cefSSai Prakash Ranjan reg = <0 0x06042000 0 0x1000>; 270824244cefSSai Prakash Ranjan 270924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 271024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 271124244cefSSai Prakash Ranjan 271224244cefSSai Prakash Ranjan out-ports { 271324244cefSSai Prakash Ranjan port { 271424244cefSSai Prakash Ranjan funnel1_out: endpoint { 271524244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in1>; 271624244cefSSai Prakash Ranjan }; 271724244cefSSai Prakash Ranjan }; 271824244cefSSai Prakash Ranjan }; 271924244cefSSai Prakash Ranjan 272024244cefSSai Prakash Ranjan in-ports { 272124244cefSSai Prakash Ranjan #address-cells = <1>; 272224244cefSSai Prakash Ranjan #size-cells = <0>; 272324244cefSSai Prakash Ranjan 272424244cefSSai Prakash Ranjan port@4 { 272524244cefSSai Prakash Ranjan reg = <4>; 272624244cefSSai Prakash Ranjan funnel1_in4: endpoint { 272724244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_out>; 272824244cefSSai Prakash Ranjan }; 272924244cefSSai Prakash Ranjan }; 273024244cefSSai Prakash Ranjan }; 273124244cefSSai Prakash Ranjan }; 273224244cefSSai Prakash Ranjan 273324244cefSSai Prakash Ranjan funnel@6043000 { 273424244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 273524244cefSSai Prakash Ranjan reg = <0 0x06043000 0 0x1000>; 273624244cefSSai Prakash Ranjan 273724244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 273824244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 273924244cefSSai Prakash Ranjan 274024244cefSSai Prakash Ranjan out-ports { 274124244cefSSai Prakash Ranjan port { 274224244cefSSai Prakash Ranjan funnel2_out: endpoint { 274324244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in2>; 274424244cefSSai Prakash Ranjan }; 274524244cefSSai Prakash Ranjan }; 274624244cefSSai Prakash Ranjan }; 274724244cefSSai Prakash Ranjan 274824244cefSSai Prakash Ranjan in-ports { 274924244cefSSai Prakash Ranjan #address-cells = <1>; 275024244cefSSai Prakash Ranjan #size-cells = <0>; 275124244cefSSai Prakash Ranjan 275224244cefSSai Prakash Ranjan port@2 { 275324244cefSSai Prakash Ranjan reg = <2>; 275424244cefSSai Prakash Ranjan funnel2_in2: endpoint { 275524244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_out>; 275624244cefSSai Prakash Ranjan }; 275724244cefSSai Prakash Ranjan }; 275824244cefSSai Prakash Ranjan }; 275924244cefSSai Prakash Ranjan }; 276024244cefSSai Prakash Ranjan 276124244cefSSai Prakash Ranjan funnel@6045000 { 276224244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 276324244cefSSai Prakash Ranjan reg = <0 0x06045000 0 0x1000>; 276424244cefSSai Prakash Ranjan 276524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 276624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 276724244cefSSai Prakash Ranjan 276824244cefSSai Prakash Ranjan out-ports { 276924244cefSSai Prakash Ranjan port { 277024244cefSSai Prakash Ranjan merge_funnel_out: endpoint { 277124244cefSSai Prakash Ranjan remote-endpoint = <&etf_in>; 277224244cefSSai Prakash Ranjan }; 277324244cefSSai Prakash Ranjan }; 277424244cefSSai Prakash Ranjan }; 277524244cefSSai Prakash Ranjan 277624244cefSSai Prakash Ranjan in-ports { 277724244cefSSai Prakash Ranjan #address-cells = <1>; 277824244cefSSai Prakash Ranjan #size-cells = <0>; 277924244cefSSai Prakash Ranjan 278024244cefSSai Prakash Ranjan port@0 { 278124244cefSSai Prakash Ranjan reg = <0>; 278224244cefSSai Prakash Ranjan merge_funnel_in0: endpoint { 278324244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_out>; 278424244cefSSai Prakash Ranjan }; 278524244cefSSai Prakash Ranjan }; 278624244cefSSai Prakash Ranjan 278724244cefSSai Prakash Ranjan port@1 { 278824244cefSSai Prakash Ranjan reg = <1>; 278924244cefSSai Prakash Ranjan merge_funnel_in1: endpoint { 279024244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_out>; 279124244cefSSai Prakash Ranjan }; 279224244cefSSai Prakash Ranjan }; 279324244cefSSai Prakash Ranjan 279424244cefSSai Prakash Ranjan port@2 { 279524244cefSSai Prakash Ranjan reg = <2>; 279624244cefSSai Prakash Ranjan merge_funnel_in2: endpoint { 279724244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_out>; 279824244cefSSai Prakash Ranjan }; 279924244cefSSai Prakash Ranjan }; 280024244cefSSai Prakash Ranjan }; 280124244cefSSai Prakash Ranjan }; 280224244cefSSai Prakash Ranjan 280324244cefSSai Prakash Ranjan replicator@6046000 { 280424244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 280524244cefSSai Prakash Ranjan reg = <0 0x06046000 0 0x1000>; 280624244cefSSai Prakash Ranjan 280724244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 280824244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 280924244cefSSai Prakash Ranjan 281024244cefSSai Prakash Ranjan out-ports { 281124244cefSSai Prakash Ranjan #address-cells = <1>; 281224244cefSSai Prakash Ranjan #size-cells = <0>; 281324244cefSSai Prakash Ranjan 281424244cefSSai Prakash Ranjan port@0 { 281524244cefSSai Prakash Ranjan reg = <0>; 281624244cefSSai Prakash Ranjan replicator_out0: endpoint { 281724244cefSSai Prakash Ranjan remote-endpoint = <&etr_in>; 281824244cefSSai Prakash Ranjan }; 281924244cefSSai Prakash Ranjan }; 282024244cefSSai Prakash Ranjan 282124244cefSSai Prakash Ranjan port@1 { 282224244cefSSai Prakash Ranjan reg = <1>; 282324244cefSSai Prakash Ranjan replicator_out1: endpoint { 282424244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_in>; 282524244cefSSai Prakash Ranjan }; 282624244cefSSai Prakash Ranjan }; 282724244cefSSai Prakash Ranjan }; 282824244cefSSai Prakash Ranjan 282924244cefSSai Prakash Ranjan in-ports { 283024244cefSSai Prakash Ranjan port { 283124244cefSSai Prakash Ranjan replicator_in0: endpoint { 283224244cefSSai Prakash Ranjan remote-endpoint = <&etf_out>; 283324244cefSSai Prakash Ranjan }; 283424244cefSSai Prakash Ranjan }; 283524244cefSSai Prakash Ranjan }; 283624244cefSSai Prakash Ranjan }; 283724244cefSSai Prakash Ranjan 283824244cefSSai Prakash Ranjan etf@6047000 { 283924244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 284024244cefSSai Prakash Ranjan reg = <0 0x06047000 0 0x1000>; 284124244cefSSai Prakash Ranjan 284224244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 284324244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 284424244cefSSai Prakash Ranjan 284524244cefSSai Prakash Ranjan out-ports { 284624244cefSSai Prakash Ranjan port { 284724244cefSSai Prakash Ranjan etf_out: endpoint { 284824244cefSSai Prakash Ranjan remote-endpoint = <&replicator_in0>; 284924244cefSSai Prakash Ranjan }; 285024244cefSSai Prakash Ranjan }; 285124244cefSSai Prakash Ranjan }; 285224244cefSSai Prakash Ranjan 285324244cefSSai Prakash Ranjan in-ports { 285424244cefSSai Prakash Ranjan port { 285524244cefSSai Prakash Ranjan etf_in: endpoint { 285624244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_out>; 285724244cefSSai Prakash Ranjan }; 285824244cefSSai Prakash Ranjan }; 285924244cefSSai Prakash Ranjan }; 286024244cefSSai Prakash Ranjan }; 286124244cefSSai Prakash Ranjan 286224244cefSSai Prakash Ranjan etr@6048000 { 286324244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 286424244cefSSai Prakash Ranjan reg = <0 0x06048000 0 0x1000>; 286524244cefSSai Prakash Ranjan iommus = <&apps_smmu 0x05e0 0x0>; 286624244cefSSai Prakash Ranjan 286724244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 286824244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 286924244cefSSai Prakash Ranjan arm,scatter-gather; 287024244cefSSai Prakash Ranjan 287124244cefSSai Prakash Ranjan in-ports { 287224244cefSSai Prakash Ranjan port { 287324244cefSSai Prakash Ranjan etr_in: endpoint { 287424244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out0>; 287524244cefSSai Prakash Ranjan }; 287624244cefSSai Prakash Ranjan }; 287724244cefSSai Prakash Ranjan }; 287824244cefSSai Prakash Ranjan }; 287924244cefSSai Prakash Ranjan 288024244cefSSai Prakash Ranjan replicator@604a000 { 288124244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 288224244cefSSai Prakash Ranjan reg = <0 0x0604a000 0 0x1000>; 288324244cefSSai Prakash Ranjan 288424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 288524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 288624244cefSSai Prakash Ranjan 288724244cefSSai Prakash Ranjan out-ports { 288824244cefSSai Prakash Ranjan #address-cells = <1>; 288924244cefSSai Prakash Ranjan #size-cells = <0>; 289024244cefSSai Prakash Ranjan 289124244cefSSai Prakash Ranjan port@1 { 289224244cefSSai Prakash Ranjan reg = <1>; 289324244cefSSai Prakash Ranjan replicator1_out: endpoint { 289424244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_in>; 289524244cefSSai Prakash Ranjan }; 289624244cefSSai Prakash Ranjan }; 289724244cefSSai Prakash Ranjan }; 289824244cefSSai Prakash Ranjan 289924244cefSSai Prakash Ranjan in-ports { 290024244cefSSai Prakash Ranjan #address-cells = <1>; 290124244cefSSai Prakash Ranjan #size-cells = <0>; 290224244cefSSai Prakash Ranjan 290324244cefSSai Prakash Ranjan port@1 { 290424244cefSSai Prakash Ranjan reg = <1>; 290524244cefSSai Prakash Ranjan replicator1_in: endpoint { 290624244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out1>; 290724244cefSSai Prakash Ranjan }; 290824244cefSSai Prakash Ranjan }; 290924244cefSSai Prakash Ranjan }; 291024244cefSSai Prakash Ranjan }; 291124244cefSSai Prakash Ranjan 291224244cefSSai Prakash Ranjan funnel@6b08000 { 291324244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 291424244cefSSai Prakash Ranjan reg = <0 0x06b08000 0 0x1000>; 291524244cefSSai Prakash Ranjan 291624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 291724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 291824244cefSSai Prakash Ranjan 291924244cefSSai Prakash Ranjan out-ports { 292024244cefSSai Prakash Ranjan port { 292124244cefSSai Prakash Ranjan swao_funnel_out: endpoint { 292224244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_in>; 292324244cefSSai Prakash Ranjan }; 292424244cefSSai Prakash Ranjan }; 292524244cefSSai Prakash Ranjan }; 292624244cefSSai Prakash Ranjan 292724244cefSSai Prakash Ranjan in-ports { 292824244cefSSai Prakash Ranjan #address-cells = <1>; 292924244cefSSai Prakash Ranjan #size-cells = <0>; 293024244cefSSai Prakash Ranjan 293124244cefSSai Prakash Ranjan port@6 { 293224244cefSSai Prakash Ranjan reg = <6>; 293324244cefSSai Prakash Ranjan swao_funnel_in: endpoint { 293424244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_out>; 293524244cefSSai Prakash Ranjan }; 293624244cefSSai Prakash Ranjan }; 293724244cefSSai Prakash Ranjan }; 293824244cefSSai Prakash Ranjan }; 293924244cefSSai Prakash Ranjan 294024244cefSSai Prakash Ranjan etf@6b09000 { 294124244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 294224244cefSSai Prakash Ranjan reg = <0 0x06b09000 0 0x1000>; 294324244cefSSai Prakash Ranjan 294424244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 294524244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 294624244cefSSai Prakash Ranjan 294724244cefSSai Prakash Ranjan out-ports { 294824244cefSSai Prakash Ranjan port { 294924244cefSSai Prakash Ranjan swao_etf_out: endpoint { 295024244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_in>; 295124244cefSSai Prakash Ranjan }; 295224244cefSSai Prakash Ranjan }; 295324244cefSSai Prakash Ranjan }; 295424244cefSSai Prakash Ranjan 295524244cefSSai Prakash Ranjan in-ports { 295624244cefSSai Prakash Ranjan port { 295724244cefSSai Prakash Ranjan swao_etf_in: endpoint { 295824244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_out>; 295924244cefSSai Prakash Ranjan }; 296024244cefSSai Prakash Ranjan }; 296124244cefSSai Prakash Ranjan }; 296224244cefSSai Prakash Ranjan }; 296324244cefSSai Prakash Ranjan 296424244cefSSai Prakash Ranjan replicator@6b0a000 { 296524244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 296624244cefSSai Prakash Ranjan reg = <0 0x06b0a000 0 0x1000>; 296724244cefSSai Prakash Ranjan 296824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 296924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 297024244cefSSai Prakash Ranjan qcom,replicator-loses-context; 297124244cefSSai Prakash Ranjan 297224244cefSSai Prakash Ranjan out-ports { 297324244cefSSai Prakash Ranjan port { 297424244cefSSai Prakash Ranjan swao_replicator_out: endpoint { 297524244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_in4>; 297624244cefSSai Prakash Ranjan }; 297724244cefSSai Prakash Ranjan }; 297824244cefSSai Prakash Ranjan }; 297924244cefSSai Prakash Ranjan 298024244cefSSai Prakash Ranjan in-ports { 298124244cefSSai Prakash Ranjan port { 298224244cefSSai Prakash Ranjan swao_replicator_in: endpoint { 298324244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_out>; 298424244cefSSai Prakash Ranjan }; 298524244cefSSai Prakash Ranjan }; 298624244cefSSai Prakash Ranjan }; 298724244cefSSai Prakash Ranjan }; 298824244cefSSai Prakash Ranjan 298924244cefSSai Prakash Ranjan etm@7040000 { 299024244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 299124244cefSSai Prakash Ranjan reg = <0 0x07040000 0 0x1000>; 299224244cefSSai Prakash Ranjan 299324244cefSSai Prakash Ranjan cpu = <&CPU0>; 299424244cefSSai Prakash Ranjan 299524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 299624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 299724244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 299824244cefSSai Prakash Ranjan qcom,skip-power-up; 299924244cefSSai Prakash Ranjan 300024244cefSSai Prakash Ranjan out-ports { 300124244cefSSai Prakash Ranjan port { 300224244cefSSai Prakash Ranjan etm0_out: endpoint { 300324244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in0>; 300424244cefSSai Prakash Ranjan }; 300524244cefSSai Prakash Ranjan }; 300624244cefSSai Prakash Ranjan }; 300724244cefSSai Prakash Ranjan }; 300824244cefSSai Prakash Ranjan 300924244cefSSai Prakash Ranjan etm@7140000 { 301024244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 301124244cefSSai Prakash Ranjan reg = <0 0x07140000 0 0x1000>; 301224244cefSSai Prakash Ranjan 301324244cefSSai Prakash Ranjan cpu = <&CPU1>; 301424244cefSSai Prakash Ranjan 301524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 301624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 301724244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 301824244cefSSai Prakash Ranjan qcom,skip-power-up; 301924244cefSSai Prakash Ranjan 302024244cefSSai Prakash Ranjan out-ports { 302124244cefSSai Prakash Ranjan port { 302224244cefSSai Prakash Ranjan etm1_out: endpoint { 302324244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in1>; 302424244cefSSai Prakash Ranjan }; 302524244cefSSai Prakash Ranjan }; 302624244cefSSai Prakash Ranjan }; 302724244cefSSai Prakash Ranjan }; 302824244cefSSai Prakash Ranjan 302924244cefSSai Prakash Ranjan etm@7240000 { 303024244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 303124244cefSSai Prakash Ranjan reg = <0 0x07240000 0 0x1000>; 303224244cefSSai Prakash Ranjan 303324244cefSSai Prakash Ranjan cpu = <&CPU2>; 303424244cefSSai Prakash Ranjan 303524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 303624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 303724244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 303824244cefSSai Prakash Ranjan qcom,skip-power-up; 303924244cefSSai Prakash Ranjan 304024244cefSSai Prakash Ranjan out-ports { 304124244cefSSai Prakash Ranjan port { 304224244cefSSai Prakash Ranjan etm2_out: endpoint { 304324244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in2>; 304424244cefSSai Prakash Ranjan }; 304524244cefSSai Prakash Ranjan }; 304624244cefSSai Prakash Ranjan }; 304724244cefSSai Prakash Ranjan }; 304824244cefSSai Prakash Ranjan 304924244cefSSai Prakash Ranjan etm@7340000 { 305024244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 305124244cefSSai Prakash Ranjan reg = <0 0x07340000 0 0x1000>; 305224244cefSSai Prakash Ranjan 305324244cefSSai Prakash Ranjan cpu = <&CPU3>; 305424244cefSSai Prakash Ranjan 305524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 305624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 305724244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 305824244cefSSai Prakash Ranjan qcom,skip-power-up; 305924244cefSSai Prakash Ranjan 306024244cefSSai Prakash Ranjan out-ports { 306124244cefSSai Prakash Ranjan port { 306224244cefSSai Prakash Ranjan etm3_out: endpoint { 306324244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in3>; 306424244cefSSai Prakash Ranjan }; 306524244cefSSai Prakash Ranjan }; 306624244cefSSai Prakash Ranjan }; 306724244cefSSai Prakash Ranjan }; 306824244cefSSai Prakash Ranjan 306924244cefSSai Prakash Ranjan etm@7440000 { 307024244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 307124244cefSSai Prakash Ranjan reg = <0 0x07440000 0 0x1000>; 307224244cefSSai Prakash Ranjan 307324244cefSSai Prakash Ranjan cpu = <&CPU4>; 307424244cefSSai Prakash Ranjan 307524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 307624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 307724244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 307824244cefSSai Prakash Ranjan qcom,skip-power-up; 307924244cefSSai Prakash Ranjan 308024244cefSSai Prakash Ranjan out-ports { 308124244cefSSai Prakash Ranjan port { 308224244cefSSai Prakash Ranjan etm4_out: endpoint { 308324244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in4>; 308424244cefSSai Prakash Ranjan }; 308524244cefSSai Prakash Ranjan }; 308624244cefSSai Prakash Ranjan }; 308724244cefSSai Prakash Ranjan }; 308824244cefSSai Prakash Ranjan 308924244cefSSai Prakash Ranjan etm@7540000 { 309024244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 309124244cefSSai Prakash Ranjan reg = <0 0x07540000 0 0x1000>; 309224244cefSSai Prakash Ranjan 309324244cefSSai Prakash Ranjan cpu = <&CPU5>; 309424244cefSSai Prakash Ranjan 309524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 309624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 309724244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 309824244cefSSai Prakash Ranjan qcom,skip-power-up; 309924244cefSSai Prakash Ranjan 310024244cefSSai Prakash Ranjan out-ports { 310124244cefSSai Prakash Ranjan port { 310224244cefSSai Prakash Ranjan etm5_out: endpoint { 310324244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in5>; 310424244cefSSai Prakash Ranjan }; 310524244cefSSai Prakash Ranjan }; 310624244cefSSai Prakash Ranjan }; 310724244cefSSai Prakash Ranjan }; 310824244cefSSai Prakash Ranjan 310924244cefSSai Prakash Ranjan etm@7640000 { 311024244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 311124244cefSSai Prakash Ranjan reg = <0 0x07640000 0 0x1000>; 311224244cefSSai Prakash Ranjan 311324244cefSSai Prakash Ranjan cpu = <&CPU6>; 311424244cefSSai Prakash Ranjan 311524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 311624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 311724244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 311824244cefSSai Prakash Ranjan qcom,skip-power-up; 311924244cefSSai Prakash Ranjan 312024244cefSSai Prakash Ranjan out-ports { 312124244cefSSai Prakash Ranjan port { 312224244cefSSai Prakash Ranjan etm6_out: endpoint { 312324244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in6>; 312424244cefSSai Prakash Ranjan }; 312524244cefSSai Prakash Ranjan }; 312624244cefSSai Prakash Ranjan }; 312724244cefSSai Prakash Ranjan }; 312824244cefSSai Prakash Ranjan 312924244cefSSai Prakash Ranjan etm@7740000 { 313024244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 313124244cefSSai Prakash Ranjan reg = <0 0x07740000 0 0x1000>; 313224244cefSSai Prakash Ranjan 313324244cefSSai Prakash Ranjan cpu = <&CPU7>; 313424244cefSSai Prakash Ranjan 313524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 313624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 313724244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 313824244cefSSai Prakash Ranjan qcom,skip-power-up; 313924244cefSSai Prakash Ranjan 314024244cefSSai Prakash Ranjan out-ports { 314124244cefSSai Prakash Ranjan port { 314224244cefSSai Prakash Ranjan etm7_out: endpoint { 314324244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in7>; 314424244cefSSai Prakash Ranjan }; 314524244cefSSai Prakash Ranjan }; 314624244cefSSai Prakash Ranjan }; 314724244cefSSai Prakash Ranjan }; 314824244cefSSai Prakash Ranjan 314924244cefSSai Prakash Ranjan funnel@7800000 { /* APSS Funnel */ 315024244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 315124244cefSSai Prakash Ranjan reg = <0 0x07800000 0 0x1000>; 315224244cefSSai Prakash Ranjan 315324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 315424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 315524244cefSSai Prakash Ranjan 315624244cefSSai Prakash Ranjan out-ports { 315724244cefSSai Prakash Ranjan port { 315824244cefSSai Prakash Ranjan apss_funnel_out: endpoint { 315924244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_in>; 316024244cefSSai Prakash Ranjan }; 316124244cefSSai Prakash Ranjan }; 316224244cefSSai Prakash Ranjan }; 316324244cefSSai Prakash Ranjan 316424244cefSSai Prakash Ranjan in-ports { 316524244cefSSai Prakash Ranjan #address-cells = <1>; 316624244cefSSai Prakash Ranjan #size-cells = <0>; 316724244cefSSai Prakash Ranjan 316824244cefSSai Prakash Ranjan port@0 { 316924244cefSSai Prakash Ranjan reg = <0>; 317024244cefSSai Prakash Ranjan apss_funnel_in0: endpoint { 317124244cefSSai Prakash Ranjan remote-endpoint = <&etm0_out>; 317224244cefSSai Prakash Ranjan }; 317324244cefSSai Prakash Ranjan }; 317424244cefSSai Prakash Ranjan 317524244cefSSai Prakash Ranjan port@1 { 317624244cefSSai Prakash Ranjan reg = <1>; 317724244cefSSai Prakash Ranjan apss_funnel_in1: endpoint { 317824244cefSSai Prakash Ranjan remote-endpoint = <&etm1_out>; 317924244cefSSai Prakash Ranjan }; 318024244cefSSai Prakash Ranjan }; 318124244cefSSai Prakash Ranjan 318224244cefSSai Prakash Ranjan port@2 { 318324244cefSSai Prakash Ranjan reg = <2>; 318424244cefSSai Prakash Ranjan apss_funnel_in2: endpoint { 318524244cefSSai Prakash Ranjan remote-endpoint = <&etm2_out>; 318624244cefSSai Prakash Ranjan }; 318724244cefSSai Prakash Ranjan }; 318824244cefSSai Prakash Ranjan 318924244cefSSai Prakash Ranjan port@3 { 319024244cefSSai Prakash Ranjan reg = <3>; 319124244cefSSai Prakash Ranjan apss_funnel_in3: endpoint { 319224244cefSSai Prakash Ranjan remote-endpoint = <&etm3_out>; 319324244cefSSai Prakash Ranjan }; 319424244cefSSai Prakash Ranjan }; 319524244cefSSai Prakash Ranjan 319624244cefSSai Prakash Ranjan port@4 { 319724244cefSSai Prakash Ranjan reg = <4>; 319824244cefSSai Prakash Ranjan apss_funnel_in4: endpoint { 319924244cefSSai Prakash Ranjan remote-endpoint = <&etm4_out>; 320024244cefSSai Prakash Ranjan }; 320124244cefSSai Prakash Ranjan }; 320224244cefSSai Prakash Ranjan 320324244cefSSai Prakash Ranjan port@5 { 320424244cefSSai Prakash Ranjan reg = <5>; 320524244cefSSai Prakash Ranjan apss_funnel_in5: endpoint { 320624244cefSSai Prakash Ranjan remote-endpoint = <&etm5_out>; 320724244cefSSai Prakash Ranjan }; 320824244cefSSai Prakash Ranjan }; 320924244cefSSai Prakash Ranjan 321024244cefSSai Prakash Ranjan port@6 { 321124244cefSSai Prakash Ranjan reg = <6>; 321224244cefSSai Prakash Ranjan apss_funnel_in6: endpoint { 321324244cefSSai Prakash Ranjan remote-endpoint = <&etm6_out>; 321424244cefSSai Prakash Ranjan }; 321524244cefSSai Prakash Ranjan }; 321624244cefSSai Prakash Ranjan 321724244cefSSai Prakash Ranjan port@7 { 321824244cefSSai Prakash Ranjan reg = <7>; 321924244cefSSai Prakash Ranjan apss_funnel_in7: endpoint { 322024244cefSSai Prakash Ranjan remote-endpoint = <&etm7_out>; 322124244cefSSai Prakash Ranjan }; 322224244cefSSai Prakash Ranjan }; 322324244cefSSai Prakash Ranjan }; 322424244cefSSai Prakash Ranjan }; 322524244cefSSai Prakash Ranjan 322624244cefSSai Prakash Ranjan funnel@7810000 { 322724244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 322824244cefSSai Prakash Ranjan reg = <0 0x07810000 0 0x1000>; 322924244cefSSai Prakash Ranjan 323024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 323124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 323224244cefSSai Prakash Ranjan 323324244cefSSai Prakash Ranjan out-ports { 323424244cefSSai Prakash Ranjan port { 323524244cefSSai Prakash Ranjan apss_merge_funnel_out: endpoint { 323624244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_in2>; 323724244cefSSai Prakash Ranjan }; 323824244cefSSai Prakash Ranjan }; 323924244cefSSai Prakash Ranjan }; 324024244cefSSai Prakash Ranjan 324124244cefSSai Prakash Ranjan in-ports { 324224244cefSSai Prakash Ranjan port { 324324244cefSSai Prakash Ranjan apss_merge_funnel_in: endpoint { 324424244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_out>; 324524244cefSSai Prakash Ranjan }; 324624244cefSSai Prakash Ranjan }; 324724244cefSSai Prakash Ranjan }; 324824244cefSSai Prakash Ranjan }; 324924244cefSSai Prakash Ranjan 325049076351SSibi Sankar remoteproc_cdsp: remoteproc@8300000 { 325149076351SSibi Sankar compatible = "qcom,sm8150-cdsp-pas"; 325249076351SSibi Sankar reg = <0x0 0x08300000 0x0 0x4040>; 325349076351SSibi Sankar 325449076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 325549076351SSibi Sankar <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 325649076351SSibi Sankar <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 325749076351SSibi Sankar <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 325849076351SSibi Sankar <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 325949076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 326049076351SSibi Sankar "handover", "stop-ack"; 326149076351SSibi Sankar 326249076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 326349076351SSibi Sankar clock-names = "xo"; 326449076351SSibi Sankar 3265a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_CX>; 326649076351SSibi Sankar 326749076351SSibi Sankar memory-region = <&cdsp_mem>; 326849076351SSibi Sankar 3269d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 3270d9d327f6SSibi Sankar 327149076351SSibi Sankar qcom,smem-states = <&cdsp_smp2p_out 0>; 327249076351SSibi Sankar qcom,smem-state-names = "stop"; 327349076351SSibi Sankar 327449076351SSibi Sankar status = "disabled"; 327549076351SSibi Sankar 327649076351SSibi Sankar glink-edge { 327749076351SSibi Sankar interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 327849076351SSibi Sankar label = "cdsp"; 327949076351SSibi Sankar qcom,remote-pid = <5>; 328049076351SSibi Sankar mboxes = <&apss_shared 4>; 328181729330SBhupesh Sharma 328281729330SBhupesh Sharma fastrpc { 328381729330SBhupesh Sharma compatible = "qcom,fastrpc"; 328481729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 328581729330SBhupesh Sharma label = "cdsp"; 32868c8ce95bSJeya R qcom,non-secure-domain; 328781729330SBhupesh Sharma #address-cells = <1>; 328881729330SBhupesh Sharma #size-cells = <0>; 328981729330SBhupesh Sharma 329081729330SBhupesh Sharma compute-cb@1 { 329181729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 329281729330SBhupesh Sharma reg = <1>; 32931d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1001 0x0460>; 329481729330SBhupesh Sharma }; 329581729330SBhupesh Sharma 329681729330SBhupesh Sharma compute-cb@2 { 329781729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 329881729330SBhupesh Sharma reg = <2>; 32991d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1002 0x0460>; 330081729330SBhupesh Sharma }; 330181729330SBhupesh Sharma 330281729330SBhupesh Sharma compute-cb@3 { 330381729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 330481729330SBhupesh Sharma reg = <3>; 33051d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1003 0x0460>; 330681729330SBhupesh Sharma }; 330781729330SBhupesh Sharma 330881729330SBhupesh Sharma compute-cb@4 { 330981729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 331081729330SBhupesh Sharma reg = <4>; 33111d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1004 0x0460>; 331281729330SBhupesh Sharma }; 331381729330SBhupesh Sharma 331481729330SBhupesh Sharma compute-cb@5 { 331581729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 331681729330SBhupesh Sharma reg = <5>; 33171d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1005 0x0460>; 331881729330SBhupesh Sharma }; 331981729330SBhupesh Sharma 332081729330SBhupesh Sharma compute-cb@6 { 332181729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 332281729330SBhupesh Sharma reg = <6>; 33231d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1006 0x0460>; 332481729330SBhupesh Sharma }; 332581729330SBhupesh Sharma 332681729330SBhupesh Sharma compute-cb@7 { 332781729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 332881729330SBhupesh Sharma reg = <7>; 33291d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1007 0x0460>; 333081729330SBhupesh Sharma }; 333181729330SBhupesh Sharma 333281729330SBhupesh Sharma compute-cb@8 { 333381729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 333481729330SBhupesh Sharma reg = <8>; 33351d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1008 0x0460>; 333681729330SBhupesh Sharma }; 333781729330SBhupesh Sharma 333881729330SBhupesh Sharma /* note: secure cb9 in downstream */ 333981729330SBhupesh Sharma }; 334049076351SSibi Sankar }; 334149076351SSibi Sankar }; 334249076351SSibi Sankar 3343b33d2868SJack Pham usb_1_hsphy: phy@88e2000 { 3344b33d2868SJack Pham compatible = "qcom,sm8150-usb-hs-phy", 3345b33d2868SJack Pham "qcom,usb-snps-hs-7nm-phy"; 3346b33d2868SJack Pham reg = <0 0x088e2000 0 0x400>; 3347b33d2868SJack Pham status = "disabled"; 3348b33d2868SJack Pham #phy-cells = <0>; 3349b33d2868SJack Pham 3350b33d2868SJack Pham clocks = <&rpmhcc RPMH_CXO_CLK>; 3351b33d2868SJack Pham clock-names = "ref"; 3352b33d2868SJack Pham 3353b33d2868SJack Pham resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3354b33d2868SJack Pham }; 3355b33d2868SJack Pham 33560c9dde0dSJonathan Marek usb_2_hsphy: phy@88e3000 { 33570c9dde0dSJonathan Marek compatible = "qcom,sm8150-usb-hs-phy", 33580c9dde0dSJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 33590c9dde0dSJonathan Marek reg = <0 0x088e3000 0 0x400>; 33600c9dde0dSJonathan Marek status = "disabled"; 33610c9dde0dSJonathan Marek #phy-cells = <0>; 33620c9dde0dSJonathan Marek 33630c9dde0dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 33640c9dde0dSJonathan Marek clock-names = "ref"; 33650c9dde0dSJonathan Marek 33660c9dde0dSJonathan Marek resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 33670c9dde0dSJonathan Marek }; 33680c9dde0dSJonathan Marek 3369b33d2868SJack Pham usb_1_qmpphy: phy@88e9000 { 3370b33d2868SJack Pham compatible = "qcom,sm8150-qmp-usb3-phy"; 3371b33d2868SJack Pham reg = <0 0x088e9000 0 0x18c>, 3372b33d2868SJack Pham <0 0x088e8000 0 0x10>; 3373b33d2868SJack Pham status = "disabled"; 3374b33d2868SJack Pham #address-cells = <2>; 3375b33d2868SJack Pham #size-cells = <2>; 3376b33d2868SJack Pham ranges; 3377b33d2868SJack Pham 3378b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3379b33d2868SJack Pham <&rpmhcc RPMH_CXO_CLK>, 3380b33d2868SJack Pham <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3381b33d2868SJack Pham <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3382b33d2868SJack Pham clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3383b33d2868SJack Pham 3384b33d2868SJack Pham resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3385b33d2868SJack Pham <&gcc GCC_USB3_PHY_PRIM_BCR>; 3386b33d2868SJack Pham reset-names = "phy", "common"; 3387b33d2868SJack Pham 33881351512fSShawn Guo usb_1_ssphy: phy@88e9200 { 3389b33d2868SJack Pham reg = <0 0x088e9200 0 0x200>, 3390b33d2868SJack Pham <0 0x088e9400 0 0x200>, 3391b33d2868SJack Pham <0 0x088e9c00 0 0x218>, 3392b33d2868SJack Pham <0 0x088e9600 0 0x200>, 3393b33d2868SJack Pham <0 0x088e9800 0 0x200>, 3394b33d2868SJack Pham <0 0x088e9a00 0 0x100>; 33957178d4ccSJonathan Marek #clock-cells = <0>; 3396b33d2868SJack Pham #phy-cells = <0>; 3397b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3398b33d2868SJack Pham clock-names = "pipe0"; 3399b33d2868SJack Pham clock-output-names = "usb3_phy_pipe_clk_src"; 3400b33d2868SJack Pham }; 3401b33d2868SJack Pham }; 3402b33d2868SJack Pham 34030c9dde0dSJonathan Marek usb_2_qmpphy: phy@88eb000 { 34040c9dde0dSJonathan Marek compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 34050c9dde0dSJonathan Marek reg = <0 0x088eb000 0 0x200>; 34060c9dde0dSJonathan Marek status = "disabled"; 34070c9dde0dSJonathan Marek #address-cells = <2>; 34080c9dde0dSJonathan Marek #size-cells = <2>; 34090c9dde0dSJonathan Marek ranges; 34100c9dde0dSJonathan Marek 34110c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 34120c9dde0dSJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 34130c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>, 34140c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 34150c9dde0dSJonathan Marek clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 34160c9dde0dSJonathan Marek 34170c9dde0dSJonathan Marek resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 34180c9dde0dSJonathan Marek <&gcc GCC_USB3_PHY_SEC_BCR>; 34190c9dde0dSJonathan Marek reset-names = "phy", "common"; 34200c9dde0dSJonathan Marek 34211351512fSShawn Guo usb_2_ssphy: phy@88eb200 { 34220c9dde0dSJonathan Marek reg = <0 0x088eb200 0 0x200>, 34230c9dde0dSJonathan Marek <0 0x088eb400 0 0x200>, 34240c9dde0dSJonathan Marek <0 0x088eb800 0 0x800>, 34250c9dde0dSJonathan Marek <0 0x088eb600 0 0x200>; 34267178d4ccSJonathan Marek #clock-cells = <0>; 34270c9dde0dSJonathan Marek #phy-cells = <0>; 34280c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 34290c9dde0dSJonathan Marek clock-names = "pipe0"; 34300c9dde0dSJonathan Marek clock-output-names = "usb3_uni_phy_pipe_clk_src"; 34310c9dde0dSJonathan Marek }; 34320c9dde0dSJonathan Marek }; 34330c9dde0dSJonathan Marek 343496bb736fSBhupesh Sharma sdhc_2: mmc@8804000 { 3435876644c7SBhupesh Sharma compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3436876644c7SBhupesh Sharma reg = <0 0x08804000 0 0x1000>; 3437876644c7SBhupesh Sharma 3438876644c7SBhupesh Sharma interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3439876644c7SBhupesh Sharma <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3440876644c7SBhupesh Sharma interrupt-names = "hc_irq", "pwr_irq"; 3441876644c7SBhupesh Sharma 3442876644c7SBhupesh Sharma clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3443876644c7SBhupesh Sharma <&gcc GCC_SDCC2_APPS_CLK>, 3444876644c7SBhupesh Sharma <&rpmhcc RPMH_CXO_CLK>; 3445876644c7SBhupesh Sharma clock-names = "iface", "core", "xo"; 344695830090SBhupesh Sharma iommus = <&apps_smmu 0x6a0 0x0>; 3447876644c7SBhupesh Sharma qcom,dll-config = <0x0007642c>; 3448876644c7SBhupesh Sharma qcom,ddr-config = <0x80040868>; 3449876644c7SBhupesh Sharma power-domains = <&rpmhpd 0>; 3450876644c7SBhupesh Sharma operating-points-v2 = <&sdhc2_opp_table>; 3451876644c7SBhupesh Sharma 3452876644c7SBhupesh Sharma status = "disabled"; 3453876644c7SBhupesh Sharma 34540e3e6546SKrzysztof Kozlowski sdhc2_opp_table: opp-table { 3455876644c7SBhupesh Sharma compatible = "operating-points-v2"; 3456876644c7SBhupesh Sharma 3457876644c7SBhupesh Sharma opp-19200000 { 3458876644c7SBhupesh Sharma opp-hz = /bits/ 64 <19200000>; 3459876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_min_svs>; 3460876644c7SBhupesh Sharma }; 3461876644c7SBhupesh Sharma 3462876644c7SBhupesh Sharma opp-50000000 { 3463876644c7SBhupesh Sharma opp-hz = /bits/ 64 <50000000>; 3464876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_low_svs>; 3465876644c7SBhupesh Sharma }; 3466876644c7SBhupesh Sharma 3467876644c7SBhupesh Sharma opp-100000000 { 3468876644c7SBhupesh Sharma opp-hz = /bits/ 64 <100000000>; 3469876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_svs>; 3470876644c7SBhupesh Sharma }; 3471876644c7SBhupesh Sharma 3472876644c7SBhupesh Sharma opp-202000000 { 3473876644c7SBhupesh Sharma opp-hz = /bits/ 64 <202000000>; 3474876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_svs_l1>; 3475876644c7SBhupesh Sharma }; 3476876644c7SBhupesh Sharma }; 3477876644c7SBhupesh Sharma }; 3478876644c7SBhupesh Sharma 34795dc43d3bSBhupesh Sharma dc_noc: interconnect@9160000 { 34805dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-dc-noc"; 34815dc43d3bSBhupesh Sharma reg = <0 0x09160000 0 0x3200>; 34825dc43d3bSBhupesh Sharma #interconnect-cells = <1>; 34835dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 34845dc43d3bSBhupesh Sharma }; 34855dc43d3bSBhupesh Sharma 34865dc43d3bSBhupesh Sharma gem_noc: interconnect@9680000 { 34875dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-gem-noc"; 34885dc43d3bSBhupesh Sharma reg = <0 0x09680000 0 0x3e200>; 34895dc43d3bSBhupesh Sharma #interconnect-cells = <1>; 34905dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 34915dc43d3bSBhupesh Sharma }; 34925dc43d3bSBhupesh Sharma 3493b33d2868SJack Pham usb_1: usb@a6f8800 { 3494b33d2868SJack Pham compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3495b33d2868SJack Pham reg = <0 0x0a6f8800 0 0x400>; 3496b33d2868SJack Pham status = "disabled"; 3497b33d2868SJack Pham #address-cells = <2>; 3498b33d2868SJack Pham #size-cells = <2>; 3499b33d2868SJack Pham ranges; 3500b33d2868SJack Pham dma-ranges; 3501b33d2868SJack Pham 3502b33d2868SJack Pham clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3503b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3504b33d2868SJack Pham <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3505b33d2868SJack Pham <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 35068d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3507b33d2868SJack Pham <&gcc GCC_USB3_SEC_CLKREF_CLK>; 35088d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 35098d5fd4e4SKrzysztof Kozlowski "core", 35108d5fd4e4SKrzysztof Kozlowski "iface", 35118d5fd4e4SKrzysztof Kozlowski "sleep", 35128d5fd4e4SKrzysztof Kozlowski "mock_utmi", 35138d5fd4e4SKrzysztof Kozlowski "xo"; 3514b33d2868SJack Pham 3515b33d2868SJack Pham assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3516b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>; 351779493db5SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 3518b33d2868SJack Pham 3519b33d2868SJack Pham interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3520b33d2868SJack Pham <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3521b33d2868SJack Pham <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3522b33d2868SJack Pham <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3523b33d2868SJack Pham interrupt-names = "hs_phy_irq", "ss_phy_irq", 3524b33d2868SJack Pham "dm_hs_phy_irq", "dp_hs_phy_irq"; 3525b33d2868SJack Pham 3526b33d2868SJack Pham power-domains = <&gcc USB30_PRIM_GDSC>; 3527b33d2868SJack Pham 3528b33d2868SJack Pham resets = <&gcc GCC_USB30_PRIM_BCR>; 3529b33d2868SJack Pham 3530b77a1c4dSKrzysztof Kozlowski usb_1_dwc3: usb@a600000 { 3531b33d2868SJack Pham compatible = "snps,dwc3"; 3532b33d2868SJack Pham reg = <0 0x0a600000 0 0xcd00>; 3533b33d2868SJack Pham interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 353448156232SJonathan Marek iommus = <&apps_smmu 0x140 0>; 3535b33d2868SJack Pham snps,dis_u2_susphy_quirk; 3536b33d2868SJack Pham snps,dis_enblslpm_quirk; 3537b33d2868SJack Pham phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3538b33d2868SJack Pham phy-names = "usb2-phy", "usb3-phy"; 3539b33d2868SJack Pham }; 3540b33d2868SJack Pham }; 3541b33d2868SJack Pham 35420c9dde0dSJonathan Marek usb_2: usb@a8f8800 { 35430c9dde0dSJonathan Marek compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 35440c9dde0dSJonathan Marek reg = <0 0x0a8f8800 0 0x400>; 35450c9dde0dSJonathan Marek status = "disabled"; 35460c9dde0dSJonathan Marek #address-cells = <2>; 35470c9dde0dSJonathan Marek #size-cells = <2>; 35480c9dde0dSJonathan Marek ranges; 35490c9dde0dSJonathan Marek dma-ranges; 35500c9dde0dSJonathan Marek 35510c9dde0dSJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 35520c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>, 35530c9dde0dSJonathan Marek <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 35540c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_SLEEP_CLK>, 35558d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 35560c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>; 35578d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 35588d5fd4e4SKrzysztof Kozlowski "core", 35598d5fd4e4SKrzysztof Kozlowski "iface", 35608d5fd4e4SKrzysztof Kozlowski "sleep", 35618d5fd4e4SKrzysztof Kozlowski "mock_utmi", 35628d5fd4e4SKrzysztof Kozlowski "xo"; 35630c9dde0dSJonathan Marek 35640c9dde0dSJonathan Marek assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 35650c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>; 35660c9dde0dSJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 35670c9dde0dSJonathan Marek 35680c9dde0dSJonathan Marek interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 35690c9dde0dSJonathan Marek <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 35700c9dde0dSJonathan Marek <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 35710c9dde0dSJonathan Marek <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 35720c9dde0dSJonathan Marek interrupt-names = "hs_phy_irq", "ss_phy_irq", 35730c9dde0dSJonathan Marek "dm_hs_phy_irq", "dp_hs_phy_irq"; 35740c9dde0dSJonathan Marek 35750c9dde0dSJonathan Marek power-domains = <&gcc USB30_SEC_GDSC>; 35760c9dde0dSJonathan Marek 35770c9dde0dSJonathan Marek resets = <&gcc GCC_USB30_SEC_BCR>; 35780c9dde0dSJonathan Marek 35792aa2b50dSBhupesh Sharma usb_2_dwc3: usb@a800000 { 35800c9dde0dSJonathan Marek compatible = "snps,dwc3"; 35810c9dde0dSJonathan Marek reg = <0 0x0a800000 0 0xcd00>; 35820c9dde0dSJonathan Marek interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 35830c9dde0dSJonathan Marek iommus = <&apps_smmu 0x160 0>; 35840c9dde0dSJonathan Marek snps,dis_u2_susphy_quirk; 35850c9dde0dSJonathan Marek snps,dis_enblslpm_quirk; 35860c9dde0dSJonathan Marek phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 35870c9dde0dSJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 35880c9dde0dSJonathan Marek }; 35890c9dde0dSJonathan Marek }; 35900c9dde0dSJonathan Marek 35916acb71fdSJonathan Marek camnoc_virt: interconnect@ac00000 { 35926acb71fdSJonathan Marek compatible = "qcom,sm8150-camnoc-virt"; 35936acb71fdSJonathan Marek reg = <0 0x0ac00000 0 0x1000>; 35946acb71fdSJonathan Marek #interconnect-cells = <1>; 35956acb71fdSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 35966acb71fdSJonathan Marek }; 35976acb71fdSJonathan Marek 359898874a46SKonrad Dybcio mdss: display-subsystem@ae00000 { 359998874a46SKonrad Dybcio compatible = "qcom,sm8150-mdss"; 360098874a46SKonrad Dybcio reg = <0 0x0ae00000 0 0x1000>; 360198874a46SKonrad Dybcio reg-names = "mdss"; 360298874a46SKonrad Dybcio 360398874a46SKonrad Dybcio interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 360498874a46SKonrad Dybcio <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 360598874a46SKonrad Dybcio interconnect-names = "mdp0-mem", "mdp1-mem"; 360698874a46SKonrad Dybcio 360798874a46SKonrad Dybcio power-domains = <&dispcc MDSS_GDSC>; 360898874a46SKonrad Dybcio 360998874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 361098874a46SKonrad Dybcio <&gcc GCC_DISP_HF_AXI_CLK>, 361198874a46SKonrad Dybcio <&gcc GCC_DISP_SF_AXI_CLK>, 361298874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_MDP_CLK>; 361398874a46SKonrad Dybcio clock-names = "iface", "bus", "nrt_bus", "core"; 361498874a46SKonrad Dybcio 361598874a46SKonrad Dybcio interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 361698874a46SKonrad Dybcio interrupt-controller; 361798874a46SKonrad Dybcio #interrupt-cells = <1>; 361898874a46SKonrad Dybcio 361998874a46SKonrad Dybcio iommus = <&apps_smmu 0x800 0x420>; 362098874a46SKonrad Dybcio 362198874a46SKonrad Dybcio status = "disabled"; 362298874a46SKonrad Dybcio 362398874a46SKonrad Dybcio #address-cells = <2>; 362498874a46SKonrad Dybcio #size-cells = <2>; 362598874a46SKonrad Dybcio ranges; 362698874a46SKonrad Dybcio 362798874a46SKonrad Dybcio mdss_mdp: display-controller@ae01000 { 362898874a46SKonrad Dybcio compatible = "qcom,sm8150-dpu"; 362998874a46SKonrad Dybcio reg = <0 0x0ae01000 0 0x8f000>, 363098874a46SKonrad Dybcio <0 0x0aeb0000 0 0x2008>; 363198874a46SKonrad Dybcio reg-names = "mdp", "vbif"; 363298874a46SKonrad Dybcio 363398874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 363498874a46SKonrad Dybcio <&gcc GCC_DISP_HF_AXI_CLK>, 363598874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_MDP_CLK>, 363698874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 363798874a46SKonrad Dybcio clock-names = "iface", "bus", "core", "vsync"; 363898874a46SKonrad Dybcio 363998874a46SKonrad Dybcio assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 364098874a46SKonrad Dybcio assigned-clock-rates = <19200000>; 364198874a46SKonrad Dybcio 364298874a46SKonrad Dybcio operating-points-v2 = <&mdp_opp_table>; 364398874a46SKonrad Dybcio power-domains = <&rpmhpd SM8150_MMCX>; 364498874a46SKonrad Dybcio 364598874a46SKonrad Dybcio interrupt-parent = <&mdss>; 364698874a46SKonrad Dybcio interrupts = <0>; 364798874a46SKonrad Dybcio 364898874a46SKonrad Dybcio ports { 364998874a46SKonrad Dybcio #address-cells = <1>; 365098874a46SKonrad Dybcio #size-cells = <0>; 365198874a46SKonrad Dybcio 365298874a46SKonrad Dybcio port@0 { 365398874a46SKonrad Dybcio reg = <0>; 365498874a46SKonrad Dybcio dpu_intf1_out: endpoint { 365598874a46SKonrad Dybcio remote-endpoint = <&mdss_dsi0_in>; 365698874a46SKonrad Dybcio }; 365798874a46SKonrad Dybcio }; 365898874a46SKonrad Dybcio 365998874a46SKonrad Dybcio port@1 { 366098874a46SKonrad Dybcio reg = <1>; 366198874a46SKonrad Dybcio dpu_intf2_out: endpoint { 366298874a46SKonrad Dybcio remote-endpoint = <&mdss_dsi1_in>; 366398874a46SKonrad Dybcio }; 366498874a46SKonrad Dybcio }; 366598874a46SKonrad Dybcio }; 366698874a46SKonrad Dybcio 366798874a46SKonrad Dybcio mdp_opp_table: opp-table { 366898874a46SKonrad Dybcio compatible = "operating-points-v2"; 366998874a46SKonrad Dybcio 367098874a46SKonrad Dybcio opp-171428571 { 367198874a46SKonrad Dybcio opp-hz = /bits/ 64 <171428571>; 367298874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_low_svs>; 367398874a46SKonrad Dybcio }; 367498874a46SKonrad Dybcio 367598874a46SKonrad Dybcio opp-300000000 { 367698874a46SKonrad Dybcio opp-hz = /bits/ 64 <300000000>; 367798874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_svs>; 367898874a46SKonrad Dybcio }; 367998874a46SKonrad Dybcio 368098874a46SKonrad Dybcio opp-345000000 { 368198874a46SKonrad Dybcio opp-hz = /bits/ 64 <345000000>; 368298874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_svs_l1>; 368398874a46SKonrad Dybcio }; 368498874a46SKonrad Dybcio 368598874a46SKonrad Dybcio opp-460000000 { 368698874a46SKonrad Dybcio opp-hz = /bits/ 64 <460000000>; 368798874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_nom>; 368898874a46SKonrad Dybcio }; 368998874a46SKonrad Dybcio }; 369098874a46SKonrad Dybcio }; 369198874a46SKonrad Dybcio 369298874a46SKonrad Dybcio mdss_dsi0: dsi@ae94000 { 3693b0b8b34aSDmitry Baryshkov compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 369498874a46SKonrad Dybcio reg = <0 0x0ae94000 0 0x400>; 369598874a46SKonrad Dybcio reg-names = "dsi_ctrl"; 369698874a46SKonrad Dybcio 369798874a46SKonrad Dybcio interrupt-parent = <&mdss>; 369898874a46SKonrad Dybcio interrupts = <4>; 369998874a46SKonrad Dybcio 370098874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 370198874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 370298874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 370398874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_ESC0_CLK>, 370498874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_AHB_CLK>, 370598874a46SKonrad Dybcio <&gcc GCC_DISP_HF_AXI_CLK>; 370698874a46SKonrad Dybcio clock-names = "byte", 370798874a46SKonrad Dybcio "byte_intf", 370898874a46SKonrad Dybcio "pixel", 370998874a46SKonrad Dybcio "core", 371098874a46SKonrad Dybcio "iface", 371198874a46SKonrad Dybcio "bus"; 371298874a46SKonrad Dybcio 371398874a46SKonrad Dybcio assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 371498874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 371598874a46SKonrad Dybcio assigned-clock-parents = <&mdss_dsi0_phy 0>, 371698874a46SKonrad Dybcio <&mdss_dsi0_phy 1>; 371798874a46SKonrad Dybcio 371898874a46SKonrad Dybcio operating-points-v2 = <&dsi_opp_table>; 371998874a46SKonrad Dybcio power-domains = <&rpmhpd SM8150_MMCX>; 372098874a46SKonrad Dybcio 372198874a46SKonrad Dybcio phys = <&mdss_dsi0_phy>; 372298874a46SKonrad Dybcio 372398874a46SKonrad Dybcio status = "disabled"; 372498874a46SKonrad Dybcio 372598874a46SKonrad Dybcio #address-cells = <1>; 372698874a46SKonrad Dybcio #size-cells = <0>; 372798874a46SKonrad Dybcio 372898874a46SKonrad Dybcio ports { 372998874a46SKonrad Dybcio #address-cells = <1>; 373098874a46SKonrad Dybcio #size-cells = <0>; 373198874a46SKonrad Dybcio 373298874a46SKonrad Dybcio port@0 { 373398874a46SKonrad Dybcio reg = <0>; 373498874a46SKonrad Dybcio mdss_dsi0_in: endpoint { 373598874a46SKonrad Dybcio remote-endpoint = <&dpu_intf1_out>; 373698874a46SKonrad Dybcio }; 373798874a46SKonrad Dybcio }; 373898874a46SKonrad Dybcio 373998874a46SKonrad Dybcio port@1 { 374098874a46SKonrad Dybcio reg = <1>; 374198874a46SKonrad Dybcio mdss_dsi0_out: endpoint { 374298874a46SKonrad Dybcio }; 374398874a46SKonrad Dybcio }; 374498874a46SKonrad Dybcio }; 374598874a46SKonrad Dybcio 374698874a46SKonrad Dybcio dsi_opp_table: opp-table { 374798874a46SKonrad Dybcio compatible = "operating-points-v2"; 374898874a46SKonrad Dybcio 374998874a46SKonrad Dybcio opp-187500000 { 375098874a46SKonrad Dybcio opp-hz = /bits/ 64 <187500000>; 375198874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_low_svs>; 375298874a46SKonrad Dybcio }; 375398874a46SKonrad Dybcio 375498874a46SKonrad Dybcio opp-300000000 { 375598874a46SKonrad Dybcio opp-hz = /bits/ 64 <300000000>; 375698874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_svs>; 375798874a46SKonrad Dybcio }; 375898874a46SKonrad Dybcio 375998874a46SKonrad Dybcio opp-358000000 { 376098874a46SKonrad Dybcio opp-hz = /bits/ 64 <358000000>; 376198874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_svs_l1>; 376298874a46SKonrad Dybcio }; 376398874a46SKonrad Dybcio }; 376498874a46SKonrad Dybcio }; 376598874a46SKonrad Dybcio 376698874a46SKonrad Dybcio mdss_dsi0_phy: phy@ae94400 { 376798874a46SKonrad Dybcio compatible = "qcom,dsi-phy-7nm"; 376898874a46SKonrad Dybcio reg = <0 0x0ae94400 0 0x200>, 376998874a46SKonrad Dybcio <0 0x0ae94600 0 0x280>, 377098874a46SKonrad Dybcio <0 0x0ae94900 0 0x260>; 377198874a46SKonrad Dybcio reg-names = "dsi_phy", 377298874a46SKonrad Dybcio "dsi_phy_lane", 377398874a46SKonrad Dybcio "dsi_pll"; 377498874a46SKonrad Dybcio 377598874a46SKonrad Dybcio #clock-cells = <1>; 377698874a46SKonrad Dybcio #phy-cells = <0>; 377798874a46SKonrad Dybcio 377898874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 377998874a46SKonrad Dybcio <&rpmhcc RPMH_CXO_CLK>; 378098874a46SKonrad Dybcio clock-names = "iface", "ref"; 378198874a46SKonrad Dybcio 378298874a46SKonrad Dybcio status = "disabled"; 378398874a46SKonrad Dybcio }; 378498874a46SKonrad Dybcio 378598874a46SKonrad Dybcio mdss_dsi1: dsi@ae96000 { 3786b0b8b34aSDmitry Baryshkov compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 378798874a46SKonrad Dybcio reg = <0 0x0ae96000 0 0x400>; 378898874a46SKonrad Dybcio reg-names = "dsi_ctrl"; 378998874a46SKonrad Dybcio 379098874a46SKonrad Dybcio interrupt-parent = <&mdss>; 379198874a46SKonrad Dybcio interrupts = <5>; 379298874a46SKonrad Dybcio 379398874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 379498874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 379598874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 379698874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_ESC1_CLK>, 379798874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_AHB_CLK>, 379898874a46SKonrad Dybcio <&gcc GCC_DISP_HF_AXI_CLK>; 379998874a46SKonrad Dybcio clock-names = "byte", 380098874a46SKonrad Dybcio "byte_intf", 380198874a46SKonrad Dybcio "pixel", 380298874a46SKonrad Dybcio "core", 380398874a46SKonrad Dybcio "iface", 380498874a46SKonrad Dybcio "bus"; 380598874a46SKonrad Dybcio 380698874a46SKonrad Dybcio assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 380798874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 380898874a46SKonrad Dybcio assigned-clock-parents = <&mdss_dsi1_phy 0>, 380998874a46SKonrad Dybcio <&mdss_dsi1_phy 1>; 381098874a46SKonrad Dybcio 381198874a46SKonrad Dybcio operating-points-v2 = <&dsi_opp_table>; 381298874a46SKonrad Dybcio power-domains = <&rpmhpd SM8150_MMCX>; 381398874a46SKonrad Dybcio 381498874a46SKonrad Dybcio phys = <&mdss_dsi1_phy>; 381598874a46SKonrad Dybcio 381698874a46SKonrad Dybcio status = "disabled"; 381798874a46SKonrad Dybcio 381898874a46SKonrad Dybcio #address-cells = <1>; 381998874a46SKonrad Dybcio #size-cells = <0>; 382098874a46SKonrad Dybcio 382198874a46SKonrad Dybcio ports { 382298874a46SKonrad Dybcio #address-cells = <1>; 382398874a46SKonrad Dybcio #size-cells = <0>; 382498874a46SKonrad Dybcio 382598874a46SKonrad Dybcio port@0 { 382698874a46SKonrad Dybcio reg = <0>; 382798874a46SKonrad Dybcio mdss_dsi1_in: endpoint { 382898874a46SKonrad Dybcio remote-endpoint = <&dpu_intf2_out>; 382998874a46SKonrad Dybcio }; 383098874a46SKonrad Dybcio }; 383198874a46SKonrad Dybcio 383298874a46SKonrad Dybcio port@1 { 383398874a46SKonrad Dybcio reg = <1>; 383498874a46SKonrad Dybcio mdss_dsi1_out: endpoint { 383598874a46SKonrad Dybcio }; 383698874a46SKonrad Dybcio }; 383798874a46SKonrad Dybcio }; 383898874a46SKonrad Dybcio }; 383998874a46SKonrad Dybcio 384098874a46SKonrad Dybcio mdss_dsi1_phy: phy@ae96400 { 384198874a46SKonrad Dybcio compatible = "qcom,dsi-phy-7nm"; 384298874a46SKonrad Dybcio reg = <0 0x0ae96400 0 0x200>, 384398874a46SKonrad Dybcio <0 0x0ae96600 0 0x280>, 384498874a46SKonrad Dybcio <0 0x0ae96900 0 0x260>; 384598874a46SKonrad Dybcio reg-names = "dsi_phy", 384698874a46SKonrad Dybcio "dsi_phy_lane", 384798874a46SKonrad Dybcio "dsi_pll"; 384898874a46SKonrad Dybcio 384998874a46SKonrad Dybcio #clock-cells = <1>; 385098874a46SKonrad Dybcio #phy-cells = <0>; 385198874a46SKonrad Dybcio 385298874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 385398874a46SKonrad Dybcio <&rpmhcc RPMH_CXO_CLK>; 385498874a46SKonrad Dybcio clock-names = "iface", "ref"; 385598874a46SKonrad Dybcio 385698874a46SKonrad Dybcio status = "disabled"; 385798874a46SKonrad Dybcio }; 385898874a46SKonrad Dybcio }; 385998874a46SKonrad Dybcio 38602ef3bb17SKonrad Dybcio dispcc: clock-controller@af00000 { 38612ef3bb17SKonrad Dybcio compatible = "qcom,sm8150-dispcc"; 38622ef3bb17SKonrad Dybcio reg = <0 0x0af00000 0 0x10000>; 38632ef3bb17SKonrad Dybcio clocks = <&rpmhcc RPMH_CXO_CLK>, 386498874a46SKonrad Dybcio <&mdss_dsi0_phy 0>, 386598874a46SKonrad Dybcio <&mdss_dsi0_phy 1>, 386698874a46SKonrad Dybcio <&mdss_dsi1_phy 0>, 386798874a46SKonrad Dybcio <&mdss_dsi1_phy 1>, 38682ef3bb17SKonrad Dybcio <0>, 38692ef3bb17SKonrad Dybcio <0>; 38702ef3bb17SKonrad Dybcio clock-names = "bi_tcxo", 38712ef3bb17SKonrad Dybcio "dsi0_phy_pll_out_byteclk", 38722ef3bb17SKonrad Dybcio "dsi0_phy_pll_out_dsiclk", 38732ef3bb17SKonrad Dybcio "dsi1_phy_pll_out_byteclk", 38742ef3bb17SKonrad Dybcio "dsi1_phy_pll_out_dsiclk", 38752ef3bb17SKonrad Dybcio "dp_phy_pll_link_clk", 38762ef3bb17SKonrad Dybcio "dp_phy_pll_vco_div_clk"; 38772ef3bb17SKonrad Dybcio power-domains = <&rpmhpd SM8150_MMCX>; 38782ef3bb17SKonrad Dybcio #clock-cells = <1>; 38792ef3bb17SKonrad Dybcio #reset-cells = <1>; 38802ef3bb17SKonrad Dybcio #power-domain-cells = <1>; 38812ef3bb17SKonrad Dybcio }; 38822ef3bb17SKonrad Dybcio 3883397ad946SBhupesh Sharma pdc: interrupt-controller@b220000 { 3884397ad946SBhupesh Sharma compatible = "qcom,sm8150-pdc", "qcom,pdc"; 3885397ad946SBhupesh Sharma reg = <0 0x0b220000 0 0x400>; 3886397ad946SBhupesh Sharma qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3887397ad946SBhupesh Sharma <125 63 1>; 3888397ad946SBhupesh Sharma #interrupt-cells = <2>; 3889397ad946SBhupesh Sharma interrupt-parent = <&intc>; 3890397ad946SBhupesh Sharma interrupt-controller; 3891397ad946SBhupesh Sharma }; 3892397ad946SBhupesh Sharma 3893bb99820dSKrzysztof Kozlowski aoss_qmp: power-management@c300000 { 38946ba93ba9SKrzysztof Kozlowski compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 389547cb6a06SMaulik Shah reg = <0x0 0x0c300000 0x0 0x400>; 3896d8cf9372SVinod Koul interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3897d8cf9372SVinod Koul mboxes = <&apss_shared 0>; 3898d8cf9372SVinod Koul 3899d8cf9372SVinod Koul #clock-cells = <0>; 3900d8cf9372SVinod Koul }; 3901d8cf9372SVinod Koul 390247cb6a06SMaulik Shah sram@c3f0000 { 390347cb6a06SMaulik Shah compatible = "qcom,rpmh-stats"; 390447cb6a06SMaulik Shah reg = <0 0x0c3f0000 0 0x400>; 390547cb6a06SMaulik Shah }; 390647cb6a06SMaulik Shah 3907d2fa630cSAmit Kucheria tsens0: thermal-sensor@c263000 { 3908d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3909d2fa630cSAmit Kucheria reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3910d2fa630cSAmit Kucheria <0 0x0c222000 0 0x1ff>; /* SROT */ 3911d2fa630cSAmit Kucheria #qcom,sensors = <16>; 3912d2fa630cSAmit Kucheria interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3913d2fa630cSAmit Kucheria <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3914d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 3915d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 3916d2fa630cSAmit Kucheria }; 3917d2fa630cSAmit Kucheria 3918d2fa630cSAmit Kucheria tsens1: thermal-sensor@c265000 { 3919d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3920d2fa630cSAmit Kucheria reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3921d2fa630cSAmit Kucheria <0 0x0c223000 0 0x1ff>; /* SROT */ 3922d2fa630cSAmit Kucheria #qcom,sensors = <8>; 3923d2fa630cSAmit Kucheria interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3924d2fa630cSAmit Kucheria <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3925d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 3926d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 3927d2fa630cSAmit Kucheria }; 3928d2fa630cSAmit Kucheria 3929e13c6d14SVinod Koul spmi_bus: spmi@c440000 { 3930e13c6d14SVinod Koul compatible = "qcom,spmi-pmic-arb"; 3931e13c6d14SVinod Koul reg = <0x0 0x0c440000 0x0 0x0001100>, 3932e13c6d14SVinod Koul <0x0 0x0c600000 0x0 0x2000000>, 3933e13c6d14SVinod Koul <0x0 0x0e600000 0x0 0x0100000>, 3934e13c6d14SVinod Koul <0x0 0x0e700000 0x0 0x00a0000>, 3935e13c6d14SVinod Koul <0x0 0x0c40a000 0x0 0x0026000>; 3936e13c6d14SVinod Koul reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3937e13c6d14SVinod Koul interrupt-names = "periph_irq"; 3938e13c6d14SVinod Koul interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3939e13c6d14SVinod Koul qcom,ee = <0>; 3940e13c6d14SVinod Koul qcom,channel = <0>; 3941e13c6d14SVinod Koul #address-cells = <2>; 3942e13c6d14SVinod Koul #size-cells = <0>; 3943e13c6d14SVinod Koul interrupt-controller; 3944e13c6d14SVinod Koul #interrupt-cells = <4>; 3945e13c6d14SVinod Koul cell-index = <0>; 3946e13c6d14SVinod Koul }; 3947e13c6d14SVinod Koul 394848156232SJonathan Marek apps_smmu: iommu@15000000 { 394948156232SJonathan Marek compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 395048156232SJonathan Marek reg = <0 0x15000000 0 0x100000>; 395148156232SJonathan Marek #iommu-cells = <2>; 395248156232SJonathan Marek #global-interrupts = <1>; 395348156232SJonathan Marek interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 395448156232SJonathan Marek <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 395548156232SJonathan Marek <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 395648156232SJonathan Marek <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 395748156232SJonathan Marek <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 395848156232SJonathan Marek <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 395948156232SJonathan Marek <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 396048156232SJonathan Marek <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 396148156232SJonathan Marek <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 396248156232SJonathan Marek <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 396348156232SJonathan Marek <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 396448156232SJonathan Marek <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 396548156232SJonathan Marek <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 396648156232SJonathan Marek <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 396748156232SJonathan Marek <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 396848156232SJonathan Marek <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 396948156232SJonathan Marek <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 397048156232SJonathan Marek <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 397148156232SJonathan Marek <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 397248156232SJonathan Marek <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 397348156232SJonathan Marek <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 397448156232SJonathan Marek <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 397548156232SJonathan Marek <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 397648156232SJonathan Marek <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 397748156232SJonathan Marek <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 397848156232SJonathan Marek <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 397948156232SJonathan Marek <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 398048156232SJonathan Marek <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 398148156232SJonathan Marek <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 398248156232SJonathan Marek <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 398348156232SJonathan Marek <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 398448156232SJonathan Marek <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 398548156232SJonathan Marek <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 398648156232SJonathan Marek <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 398748156232SJonathan Marek <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 398848156232SJonathan Marek <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 398948156232SJonathan Marek <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 399048156232SJonathan Marek <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 399148156232SJonathan Marek <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 399248156232SJonathan Marek <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 399348156232SJonathan Marek <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 399448156232SJonathan Marek <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 399548156232SJonathan Marek <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 399648156232SJonathan Marek <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 399748156232SJonathan Marek <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 399848156232SJonathan Marek <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 399948156232SJonathan Marek <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 400048156232SJonathan Marek <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 400148156232SJonathan Marek <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 400248156232SJonathan Marek <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 400348156232SJonathan Marek <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 400448156232SJonathan Marek <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 400548156232SJonathan Marek <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 400648156232SJonathan Marek <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 400748156232SJonathan Marek <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 400848156232SJonathan Marek <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 400948156232SJonathan Marek <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 401048156232SJonathan Marek <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 401148156232SJonathan Marek <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 401248156232SJonathan Marek <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 401348156232SJonathan Marek <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 401448156232SJonathan Marek <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 401548156232SJonathan Marek <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 401648156232SJonathan Marek <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 401748156232SJonathan Marek <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 401848156232SJonathan Marek <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 401948156232SJonathan Marek <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 402048156232SJonathan Marek <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 402148156232SJonathan Marek <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 402248156232SJonathan Marek <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 402348156232SJonathan Marek <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 402448156232SJonathan Marek <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 402548156232SJonathan Marek <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 402648156232SJonathan Marek <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 402748156232SJonathan Marek <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 402848156232SJonathan Marek <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 402948156232SJonathan Marek <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 403048156232SJonathan Marek <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 403148156232SJonathan Marek <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 403248156232SJonathan Marek <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 403348156232SJonathan Marek <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 403448156232SJonathan Marek }; 403548156232SJonathan Marek 403649076351SSibi Sankar remoteproc_adsp: remoteproc@17300000 { 403749076351SSibi Sankar compatible = "qcom,sm8150-adsp-pas"; 403849076351SSibi Sankar reg = <0x0 0x17300000 0x0 0x4040>; 403949076351SSibi Sankar 404049076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 404149076351SSibi Sankar <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 404249076351SSibi Sankar <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 404349076351SSibi Sankar <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 404449076351SSibi Sankar <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 404549076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 404649076351SSibi Sankar "handover", "stop-ack"; 404749076351SSibi Sankar 404849076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 404949076351SSibi Sankar clock-names = "xo"; 405049076351SSibi Sankar 4051a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_CX>; 405249076351SSibi Sankar 405349076351SSibi Sankar memory-region = <&adsp_mem>; 405449076351SSibi Sankar 4055d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 4056d9d327f6SSibi Sankar 405749076351SSibi Sankar qcom,smem-states = <&adsp_smp2p_out 0>; 405849076351SSibi Sankar qcom,smem-state-names = "stop"; 405949076351SSibi Sankar 406049076351SSibi Sankar status = "disabled"; 406149076351SSibi Sankar 406249076351SSibi Sankar glink-edge { 406349076351SSibi Sankar interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 406449076351SSibi Sankar label = "lpass"; 406549076351SSibi Sankar qcom,remote-pid = <2>; 406649076351SSibi Sankar mboxes = <&apss_shared 8>; 406781729330SBhupesh Sharma 406881729330SBhupesh Sharma fastrpc { 406981729330SBhupesh Sharma compatible = "qcom,fastrpc"; 407081729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 407181729330SBhupesh Sharma label = "adsp"; 40728c8ce95bSJeya R qcom,non-secure-domain; 407381729330SBhupesh Sharma #address-cells = <1>; 407481729330SBhupesh Sharma #size-cells = <0>; 407581729330SBhupesh Sharma 407681729330SBhupesh Sharma compute-cb@3 { 407781729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 407881729330SBhupesh Sharma reg = <3>; 407981729330SBhupesh Sharma iommus = <&apps_smmu 0x1b23 0x0>; 408081729330SBhupesh Sharma }; 408181729330SBhupesh Sharma 408281729330SBhupesh Sharma compute-cb@4 { 408381729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 408481729330SBhupesh Sharma reg = <4>; 408581729330SBhupesh Sharma iommus = <&apps_smmu 0x1b24 0x0>; 408681729330SBhupesh Sharma }; 408781729330SBhupesh Sharma 408881729330SBhupesh Sharma compute-cb@5 { 408981729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 409081729330SBhupesh Sharma reg = <5>; 409181729330SBhupesh Sharma iommus = <&apps_smmu 0x1b25 0x0>; 409281729330SBhupesh Sharma }; 409381729330SBhupesh Sharma }; 409449076351SSibi Sankar }; 409549076351SSibi Sankar }; 409649076351SSibi Sankar 4097e13c6d14SVinod Koul intc: interrupt-controller@17a00000 { 4098e13c6d14SVinod Koul compatible = "arm,gic-v3"; 4099e13c6d14SVinod Koul interrupt-controller; 4100e13c6d14SVinod Koul #interrupt-cells = <3>; 4101e13c6d14SVinod Koul reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4102e13c6d14SVinod Koul <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4103e13c6d14SVinod Koul interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4104e13c6d14SVinod Koul }; 4105e13c6d14SVinod Koul 4106d8cf9372SVinod Koul apss_shared: mailbox@17c00000 { 4107d8cf9372SVinod Koul compatible = "qcom,sm8150-apss-shared"; 4108d8cf9372SVinod Koul reg = <0x0 0x17c00000 0x0 0x1000>; 4109d8cf9372SVinod Koul #mbox-cells = <1>; 4110d8cf9372SVinod Koul }; 4111d8cf9372SVinod Koul 4112fb2d8150SSai Prakash Ranjan watchdog@17c10000 { 4113fb2d8150SSai Prakash Ranjan compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 4114fb2d8150SSai Prakash Ranjan reg = <0 0x17c10000 0 0x1000>; 4115fb2d8150SSai Prakash Ranjan clocks = <&sleep_clk>; 4116b094c8f8SSai Prakash Ranjan interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4117fb2d8150SSai Prakash Ranjan }; 4118fb2d8150SSai Prakash Ranjan 4119e13c6d14SVinod Koul timer@17c20000 { 4120458ebdbbSDavid Heidelberg #address-cells = <1>; 4121458ebdbbSDavid Heidelberg #size-cells = <1>; 4122458ebdbbSDavid Heidelberg ranges = <0 0 0 0x20000000>; 4123e13c6d14SVinod Koul compatible = "arm,armv7-timer-mem"; 4124e13c6d14SVinod Koul reg = <0x0 0x17c20000 0x0 0x1000>; 4125e13c6d14SVinod Koul clock-frequency = <19200000>; 4126e13c6d14SVinod Koul 4127e13c6d14SVinod Koul frame@17c21000{ 4128e13c6d14SVinod Koul frame-number = <0>; 4129e13c6d14SVinod Koul interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4130e13c6d14SVinod Koul <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4131458ebdbbSDavid Heidelberg reg = <0x17c21000 0x1000>, 4132458ebdbbSDavid Heidelberg <0x17c22000 0x1000>; 4133e13c6d14SVinod Koul }; 4134e13c6d14SVinod Koul 4135e13c6d14SVinod Koul frame@17c23000 { 4136e13c6d14SVinod Koul frame-number = <1>; 4137e13c6d14SVinod Koul interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4138458ebdbbSDavid Heidelberg reg = <0x17c23000 0x1000>; 4139e13c6d14SVinod Koul status = "disabled"; 4140e13c6d14SVinod Koul }; 4141e13c6d14SVinod Koul 4142e13c6d14SVinod Koul frame@17c25000 { 4143e13c6d14SVinod Koul frame-number = <2>; 4144e13c6d14SVinod Koul interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4145458ebdbbSDavid Heidelberg reg = <0x17c25000 0x1000>; 4146e13c6d14SVinod Koul status = "disabled"; 4147e13c6d14SVinod Koul }; 4148e13c6d14SVinod Koul 4149e13c6d14SVinod Koul frame@17c27000 { 4150e13c6d14SVinod Koul frame-number = <3>; 4151e13c6d14SVinod Koul interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4152458ebdbbSDavid Heidelberg reg = <0x17c26000 0x1000>; 4153e13c6d14SVinod Koul status = "disabled"; 4154e13c6d14SVinod Koul }; 4155e13c6d14SVinod Koul 4156e13c6d14SVinod Koul frame@17c29000 { 4157e13c6d14SVinod Koul frame-number = <4>; 4158e13c6d14SVinod Koul interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4159458ebdbbSDavid Heidelberg reg = <0x17c29000 0x1000>; 4160e13c6d14SVinod Koul status = "disabled"; 4161e13c6d14SVinod Koul }; 4162e13c6d14SVinod Koul 4163e13c6d14SVinod Koul frame@17c2b000 { 4164e13c6d14SVinod Koul frame-number = <5>; 4165e13c6d14SVinod Koul interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4166458ebdbbSDavid Heidelberg reg = <0x17c2b000 0x1000>; 4167e13c6d14SVinod Koul status = "disabled"; 4168e13c6d14SVinod Koul }; 4169e13c6d14SVinod Koul 4170e13c6d14SVinod Koul frame@17c2d000 { 4171e13c6d14SVinod Koul frame-number = <6>; 4172e13c6d14SVinod Koul interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4173458ebdbbSDavid Heidelberg reg = <0x17c2d000 0x1000>; 4174e13c6d14SVinod Koul status = "disabled"; 4175e13c6d14SVinod Koul }; 4176e13c6d14SVinod Koul }; 4177d8cf9372SVinod Koul 4178d8cf9372SVinod Koul apps_rsc: rsc@18200000 { 4179d8cf9372SVinod Koul label = "apps_rsc"; 4180d8cf9372SVinod Koul compatible = "qcom,rpmh-rsc"; 4181d8cf9372SVinod Koul reg = <0x0 0x18200000 0x0 0x10000>, 4182d8cf9372SVinod Koul <0x0 0x18210000 0x0 0x10000>, 4183d8cf9372SVinod Koul <0x0 0x18220000 0x0 0x10000>; 4184d8cf9372SVinod Koul reg-names = "drv-0", "drv-1", "drv-2"; 4185d8cf9372SVinod Koul interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4186d8cf9372SVinod Koul <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4187d8cf9372SVinod Koul <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4188d8cf9372SVinod Koul qcom,tcs-offset = <0xd00>; 4189d8cf9372SVinod Koul qcom,drv-id = <2>; 4190d8cf9372SVinod Koul qcom,tcs-config = <ACTIVE_TCS 2>, 419117ac8af6SMaulik Shah <SLEEP_TCS 3>, 419217ac8af6SMaulik Shah <WAKE_TCS 3>, 419317ac8af6SMaulik Shah <CONTROL_TCS 1>; 41942ffa0ca4SMaulik Shah power-domains = <&CLUSTER_PD>; 4195d8cf9372SVinod Koul 4196d8cf9372SVinod Koul rpmhcc: clock-controller { 4197d8cf9372SVinod Koul compatible = "qcom,sm8150-rpmh-clk"; 4198d8cf9372SVinod Koul #clock-cells = <1>; 4199d8cf9372SVinod Koul clock-names = "xo"; 4200d8cf9372SVinod Koul clocks = <&xo_board>; 4201d8cf9372SVinod Koul }; 4202017e7856SSibi Sankar 4203017e7856SSibi Sankar rpmhpd: power-controller { 4204017e7856SSibi Sankar compatible = "qcom,sm8150-rpmhpd"; 4205017e7856SSibi Sankar #power-domain-cells = <1>; 4206017e7856SSibi Sankar operating-points-v2 = <&rpmhpd_opp_table>; 4207017e7856SSibi Sankar 4208017e7856SSibi Sankar rpmhpd_opp_table: opp-table { 4209017e7856SSibi Sankar compatible = "operating-points-v2"; 4210017e7856SSibi Sankar 4211017e7856SSibi Sankar rpmhpd_opp_ret: opp1 { 4212017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4213017e7856SSibi Sankar }; 4214017e7856SSibi Sankar 4215017e7856SSibi Sankar rpmhpd_opp_min_svs: opp2 { 4216017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4217017e7856SSibi Sankar }; 4218017e7856SSibi Sankar 4219017e7856SSibi Sankar rpmhpd_opp_low_svs: opp3 { 4220017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4221017e7856SSibi Sankar }; 4222017e7856SSibi Sankar 4223017e7856SSibi Sankar rpmhpd_opp_svs: opp4 { 4224017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4225017e7856SSibi Sankar }; 4226017e7856SSibi Sankar 4227017e7856SSibi Sankar rpmhpd_opp_svs_l1: opp5 { 4228017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4229017e7856SSibi Sankar }; 4230017e7856SSibi Sankar 4231017e7856SSibi Sankar rpmhpd_opp_svs_l2: opp6 { 4232017e7856SSibi Sankar opp-level = <224>; 4233017e7856SSibi Sankar }; 4234017e7856SSibi Sankar 4235017e7856SSibi Sankar rpmhpd_opp_nom: opp7 { 4236017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4237017e7856SSibi Sankar }; 4238017e7856SSibi Sankar 4239017e7856SSibi Sankar rpmhpd_opp_nom_l1: opp8 { 4240017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4241017e7856SSibi Sankar }; 4242017e7856SSibi Sankar 4243017e7856SSibi Sankar rpmhpd_opp_nom_l2: opp9 { 4244017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4245017e7856SSibi Sankar }; 4246017e7856SSibi Sankar 4247017e7856SSibi Sankar rpmhpd_opp_turbo: opp10 { 4248017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4249017e7856SSibi Sankar }; 4250017e7856SSibi Sankar 4251017e7856SSibi Sankar rpmhpd_opp_turbo_l1: opp11 { 4252017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4253017e7856SSibi Sankar }; 4254017e7856SSibi Sankar }; 4255017e7856SSibi Sankar }; 425671a2fc6eSJonathan Marek 4257fc0e7dd6SKrzysztof Kozlowski apps_bcm_voter: bcm-voter { 425871a2fc6eSJonathan Marek compatible = "qcom,bcm-voter"; 425971a2fc6eSJonathan Marek }; 4260d8cf9372SVinod Koul }; 4261fea8930bSSibi Sankar 4262a6d435c1SSibi Sankar osm_l3: interconnect@18321000 { 4263a0289a10SBjorn Andersson compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4264a6d435c1SSibi Sankar reg = <0 0x18321000 0 0x1400>; 4265a6d435c1SSibi Sankar 4266a6d435c1SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4267a6d435c1SSibi Sankar clock-names = "xo", "alternate"; 4268a6d435c1SSibi Sankar 4269a6d435c1SSibi Sankar #interconnect-cells = <1>; 4270a6d435c1SSibi Sankar }; 4271a6d435c1SSibi Sankar 4272fea8930bSSibi Sankar cpufreq_hw: cpufreq@18323000 { 4273fea8930bSSibi Sankar compatible = "qcom,cpufreq-hw"; 4274fea8930bSSibi Sankar reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 4275fea8930bSSibi Sankar <0 0x18327800 0 0x1400>; 4276fea8930bSSibi Sankar reg-names = "freq-domain0", "freq-domain1", 4277fea8930bSSibi Sankar "freq-domain2"; 4278fea8930bSSibi Sankar 4279fea8930bSSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4280fea8930bSSibi Sankar clock-names = "xo", "alternate"; 4281fea8930bSSibi Sankar 4282fea8930bSSibi Sankar #freq-domain-cells = <1>; 4283fea8930bSSibi Sankar }; 428405090bb9SJonathan Marek 42852ffcfe79SThara Gopinath lmh_cluster1: lmh@18350800 { 42862ffcfe79SThara Gopinath compatible = "qcom,sm8150-lmh"; 42872ffcfe79SThara Gopinath reg = <0 0x18350800 0 0x400>; 42882ffcfe79SThara Gopinath interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 42892ffcfe79SThara Gopinath cpus = <&CPU4>; 42902ffcfe79SThara Gopinath qcom,lmh-temp-arm-millicelsius = <60000>; 42912ffcfe79SThara Gopinath qcom,lmh-temp-low-millicelsius = <84500>; 42922ffcfe79SThara Gopinath qcom,lmh-temp-high-millicelsius = <85000>; 42932ffcfe79SThara Gopinath interrupt-controller; 42942ffcfe79SThara Gopinath #interrupt-cells = <1>; 42952ffcfe79SThara Gopinath }; 42962ffcfe79SThara Gopinath 42972ffcfe79SThara Gopinath lmh_cluster0: lmh@18358800 { 42982ffcfe79SThara Gopinath compatible = "qcom,sm8150-lmh"; 42992ffcfe79SThara Gopinath reg = <0 0x18358800 0 0x400>; 43002ffcfe79SThara Gopinath interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 43012ffcfe79SThara Gopinath cpus = <&CPU0>; 43022ffcfe79SThara Gopinath qcom,lmh-temp-arm-millicelsius = <60000>; 43032ffcfe79SThara Gopinath qcom,lmh-temp-low-millicelsius = <84500>; 43042ffcfe79SThara Gopinath qcom,lmh-temp-high-millicelsius = <85000>; 43052ffcfe79SThara Gopinath interrupt-controller; 43062ffcfe79SThara Gopinath #interrupt-cells = <1>; 43072ffcfe79SThara Gopinath }; 43082ffcfe79SThara Gopinath 430905090bb9SJonathan Marek wifi: wifi@18800000 { 431005090bb9SJonathan Marek compatible = "qcom,wcn3990-wifi"; 431105090bb9SJonathan Marek reg = <0 0x18800000 0 0x800000>; 431205090bb9SJonathan Marek reg-names = "membase"; 431305090bb9SJonathan Marek memory-region = <&wlan_mem>; 431405090bb9SJonathan Marek clock-names = "cxo_ref_clk_pin", "qdss"; 431505090bb9SJonathan Marek clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 431605090bb9SJonathan Marek interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 431705090bb9SJonathan Marek <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 431805090bb9SJonathan Marek <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 431905090bb9SJonathan Marek <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 432005090bb9SJonathan Marek <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 432105090bb9SJonathan Marek <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 432205090bb9SJonathan Marek <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 432305090bb9SJonathan Marek <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 432405090bb9SJonathan Marek <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 432505090bb9SJonathan Marek <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 432605090bb9SJonathan Marek <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 432705090bb9SJonathan Marek <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 432805090bb9SJonathan Marek iommus = <&apps_smmu 0x0640 0x1>; 432905090bb9SJonathan Marek status = "disabled"; 433005090bb9SJonathan Marek }; 4331e13c6d14SVinod Koul }; 4332e13c6d14SVinod Koul 4333e13c6d14SVinod Koul timer { 4334e13c6d14SVinod Koul compatible = "arm,armv8-timer"; 4335e13c6d14SVinod Koul interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4336e13c6d14SVinod Koul <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4337e13c6d14SVinod Koul <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4338e13c6d14SVinod Koul <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4339e13c6d14SVinod Koul }; 4340d2fa630cSAmit Kucheria 4341d2fa630cSAmit Kucheria thermal-zones { 4342d2fa630cSAmit Kucheria cpu0-thermal { 4343d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4344d2fa630cSAmit Kucheria polling-delay = <1000>; 4345d2fa630cSAmit Kucheria 4346d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 1>; 4347d2fa630cSAmit Kucheria 4348d2fa630cSAmit Kucheria trips { 4349d2fa630cSAmit Kucheria cpu0_alert0: trip-point0 { 4350d2fa630cSAmit Kucheria temperature = <90000>; 4351d2fa630cSAmit Kucheria hysteresis = <2000>; 4352d2fa630cSAmit Kucheria type = "passive"; 4353d2fa630cSAmit Kucheria }; 4354d2fa630cSAmit Kucheria 4355d2fa630cSAmit Kucheria cpu0_alert1: trip-point1 { 4356d2fa630cSAmit Kucheria temperature = <95000>; 4357d2fa630cSAmit Kucheria hysteresis = <2000>; 4358d2fa630cSAmit Kucheria type = "passive"; 4359d2fa630cSAmit Kucheria }; 4360d2fa630cSAmit Kucheria 4361*1364acc3SKrzysztof Kozlowski cpu0_crit: cpu-crit { 4362d2fa630cSAmit Kucheria temperature = <110000>; 4363d2fa630cSAmit Kucheria hysteresis = <1000>; 4364d2fa630cSAmit Kucheria type = "critical"; 4365d2fa630cSAmit Kucheria }; 4366d2fa630cSAmit Kucheria }; 4367d2fa630cSAmit Kucheria 4368d2fa630cSAmit Kucheria cooling-maps { 4369d2fa630cSAmit Kucheria map0 { 4370d2fa630cSAmit Kucheria trip = <&cpu0_alert0>; 4371d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4372d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4373d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4374d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4375d2fa630cSAmit Kucheria }; 4376d2fa630cSAmit Kucheria map1 { 4377d2fa630cSAmit Kucheria trip = <&cpu0_alert1>; 4378d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4379d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4380d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4381d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4382d2fa630cSAmit Kucheria }; 4383d2fa630cSAmit Kucheria }; 4384d2fa630cSAmit Kucheria }; 4385d2fa630cSAmit Kucheria 4386d2fa630cSAmit Kucheria cpu1-thermal { 4387d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4388d2fa630cSAmit Kucheria polling-delay = <1000>; 4389d2fa630cSAmit Kucheria 4390d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 2>; 4391d2fa630cSAmit Kucheria 4392d2fa630cSAmit Kucheria trips { 4393d2fa630cSAmit Kucheria cpu1_alert0: trip-point0 { 4394d2fa630cSAmit Kucheria temperature = <90000>; 4395d2fa630cSAmit Kucheria hysteresis = <2000>; 4396d2fa630cSAmit Kucheria type = "passive"; 4397d2fa630cSAmit Kucheria }; 4398d2fa630cSAmit Kucheria 4399d2fa630cSAmit Kucheria cpu1_alert1: trip-point1 { 4400d2fa630cSAmit Kucheria temperature = <95000>; 4401d2fa630cSAmit Kucheria hysteresis = <2000>; 4402d2fa630cSAmit Kucheria type = "passive"; 4403d2fa630cSAmit Kucheria }; 4404d2fa630cSAmit Kucheria 4405*1364acc3SKrzysztof Kozlowski cpu1_crit: cpu-crit { 4406d2fa630cSAmit Kucheria temperature = <110000>; 4407d2fa630cSAmit Kucheria hysteresis = <1000>; 4408d2fa630cSAmit Kucheria type = "critical"; 4409d2fa630cSAmit Kucheria }; 4410d2fa630cSAmit Kucheria }; 4411d2fa630cSAmit Kucheria 4412d2fa630cSAmit Kucheria cooling-maps { 4413d2fa630cSAmit Kucheria map0 { 4414d2fa630cSAmit Kucheria trip = <&cpu1_alert0>; 4415d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4416d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4417d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4418d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4419d2fa630cSAmit Kucheria }; 4420d2fa630cSAmit Kucheria map1 { 4421d2fa630cSAmit Kucheria trip = <&cpu1_alert1>; 4422d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4423d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4424d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4425d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4426d2fa630cSAmit Kucheria }; 4427d2fa630cSAmit Kucheria }; 4428d2fa630cSAmit Kucheria }; 4429d2fa630cSAmit Kucheria 4430d2fa630cSAmit Kucheria cpu2-thermal { 4431d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4432d2fa630cSAmit Kucheria polling-delay = <1000>; 4433d2fa630cSAmit Kucheria 4434d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 3>; 4435d2fa630cSAmit Kucheria 4436d2fa630cSAmit Kucheria trips { 4437d2fa630cSAmit Kucheria cpu2_alert0: trip-point0 { 4438d2fa630cSAmit Kucheria temperature = <90000>; 4439d2fa630cSAmit Kucheria hysteresis = <2000>; 4440d2fa630cSAmit Kucheria type = "passive"; 4441d2fa630cSAmit Kucheria }; 4442d2fa630cSAmit Kucheria 4443d2fa630cSAmit Kucheria cpu2_alert1: trip-point1 { 4444d2fa630cSAmit Kucheria temperature = <95000>; 4445d2fa630cSAmit Kucheria hysteresis = <2000>; 4446d2fa630cSAmit Kucheria type = "passive"; 4447d2fa630cSAmit Kucheria }; 4448d2fa630cSAmit Kucheria 4449*1364acc3SKrzysztof Kozlowski cpu2_crit: cpu-crit { 4450d2fa630cSAmit Kucheria temperature = <110000>; 4451d2fa630cSAmit Kucheria hysteresis = <1000>; 4452d2fa630cSAmit Kucheria type = "critical"; 4453d2fa630cSAmit Kucheria }; 4454d2fa630cSAmit Kucheria }; 4455d2fa630cSAmit Kucheria 4456d2fa630cSAmit Kucheria cooling-maps { 4457d2fa630cSAmit Kucheria map0 { 4458d2fa630cSAmit Kucheria trip = <&cpu2_alert0>; 4459d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4460d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4461d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4462d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4463d2fa630cSAmit Kucheria }; 4464d2fa630cSAmit Kucheria map1 { 4465d2fa630cSAmit Kucheria trip = <&cpu2_alert1>; 4466d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4467d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4468d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4469d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4470d2fa630cSAmit Kucheria }; 4471d2fa630cSAmit Kucheria }; 4472d2fa630cSAmit Kucheria }; 4473d2fa630cSAmit Kucheria 4474d2fa630cSAmit Kucheria cpu3-thermal { 4475d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4476d2fa630cSAmit Kucheria polling-delay = <1000>; 4477d2fa630cSAmit Kucheria 4478d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 4>; 4479d2fa630cSAmit Kucheria 4480d2fa630cSAmit Kucheria trips { 4481d2fa630cSAmit Kucheria cpu3_alert0: trip-point0 { 4482d2fa630cSAmit Kucheria temperature = <90000>; 4483d2fa630cSAmit Kucheria hysteresis = <2000>; 4484d2fa630cSAmit Kucheria type = "passive"; 4485d2fa630cSAmit Kucheria }; 4486d2fa630cSAmit Kucheria 4487d2fa630cSAmit Kucheria cpu3_alert1: trip-point1 { 4488d2fa630cSAmit Kucheria temperature = <95000>; 4489d2fa630cSAmit Kucheria hysteresis = <2000>; 4490d2fa630cSAmit Kucheria type = "passive"; 4491d2fa630cSAmit Kucheria }; 4492d2fa630cSAmit Kucheria 4493*1364acc3SKrzysztof Kozlowski cpu3_crit: cpu-crit { 4494d2fa630cSAmit Kucheria temperature = <110000>; 4495d2fa630cSAmit Kucheria hysteresis = <1000>; 4496d2fa630cSAmit Kucheria type = "critical"; 4497d2fa630cSAmit Kucheria }; 4498d2fa630cSAmit Kucheria }; 4499d2fa630cSAmit Kucheria 4500d2fa630cSAmit Kucheria cooling-maps { 4501d2fa630cSAmit Kucheria map0 { 4502d2fa630cSAmit Kucheria trip = <&cpu3_alert0>; 4503d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4504d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4505d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4506d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4507d2fa630cSAmit Kucheria }; 4508d2fa630cSAmit Kucheria map1 { 4509d2fa630cSAmit Kucheria trip = <&cpu3_alert1>; 4510d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4511d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4512d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4513d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4514d2fa630cSAmit Kucheria }; 4515d2fa630cSAmit Kucheria }; 4516d2fa630cSAmit Kucheria }; 4517d2fa630cSAmit Kucheria 4518d2fa630cSAmit Kucheria cpu4-top-thermal { 4519d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4520d2fa630cSAmit Kucheria polling-delay = <1000>; 4521d2fa630cSAmit Kucheria 4522d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 7>; 4523d2fa630cSAmit Kucheria 4524d2fa630cSAmit Kucheria trips { 4525d2fa630cSAmit Kucheria cpu4_top_alert0: trip-point0 { 4526d2fa630cSAmit Kucheria temperature = <90000>; 4527d2fa630cSAmit Kucheria hysteresis = <2000>; 4528d2fa630cSAmit Kucheria type = "passive"; 4529d2fa630cSAmit Kucheria }; 4530d2fa630cSAmit Kucheria 4531d2fa630cSAmit Kucheria cpu4_top_alert1: trip-point1 { 4532d2fa630cSAmit Kucheria temperature = <95000>; 4533d2fa630cSAmit Kucheria hysteresis = <2000>; 4534d2fa630cSAmit Kucheria type = "passive"; 4535d2fa630cSAmit Kucheria }; 4536d2fa630cSAmit Kucheria 4537*1364acc3SKrzysztof Kozlowski cpu4_top_crit: cpu-crit { 4538d2fa630cSAmit Kucheria temperature = <110000>; 4539d2fa630cSAmit Kucheria hysteresis = <1000>; 4540d2fa630cSAmit Kucheria type = "critical"; 4541d2fa630cSAmit Kucheria }; 4542d2fa630cSAmit Kucheria }; 4543d2fa630cSAmit Kucheria 4544d2fa630cSAmit Kucheria cooling-maps { 4545d2fa630cSAmit Kucheria map0 { 4546d2fa630cSAmit Kucheria trip = <&cpu4_top_alert0>; 4547d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4548d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4549d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4550d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4551d2fa630cSAmit Kucheria }; 4552d2fa630cSAmit Kucheria map1 { 4553d2fa630cSAmit Kucheria trip = <&cpu4_top_alert1>; 4554d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4555d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4556d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4557d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4558d2fa630cSAmit Kucheria }; 4559d2fa630cSAmit Kucheria }; 4560d2fa630cSAmit Kucheria }; 4561d2fa630cSAmit Kucheria 4562d2fa630cSAmit Kucheria cpu5-top-thermal { 4563d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4564d2fa630cSAmit Kucheria polling-delay = <1000>; 4565d2fa630cSAmit Kucheria 4566d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 8>; 4567d2fa630cSAmit Kucheria 4568d2fa630cSAmit Kucheria trips { 4569d2fa630cSAmit Kucheria cpu5_top_alert0: trip-point0 { 4570d2fa630cSAmit Kucheria temperature = <90000>; 4571d2fa630cSAmit Kucheria hysteresis = <2000>; 4572d2fa630cSAmit Kucheria type = "passive"; 4573d2fa630cSAmit Kucheria }; 4574d2fa630cSAmit Kucheria 4575d2fa630cSAmit Kucheria cpu5_top_alert1: trip-point1 { 4576d2fa630cSAmit Kucheria temperature = <95000>; 4577d2fa630cSAmit Kucheria hysteresis = <2000>; 4578d2fa630cSAmit Kucheria type = "passive"; 4579d2fa630cSAmit Kucheria }; 4580d2fa630cSAmit Kucheria 4581*1364acc3SKrzysztof Kozlowski cpu5_top_crit: cpu-crit { 4582d2fa630cSAmit Kucheria temperature = <110000>; 4583d2fa630cSAmit Kucheria hysteresis = <1000>; 4584d2fa630cSAmit Kucheria type = "critical"; 4585d2fa630cSAmit Kucheria }; 4586d2fa630cSAmit Kucheria }; 4587d2fa630cSAmit Kucheria 4588d2fa630cSAmit Kucheria cooling-maps { 4589d2fa630cSAmit Kucheria map0 { 4590d2fa630cSAmit Kucheria trip = <&cpu5_top_alert0>; 4591d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4592d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4593d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4594d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4595d2fa630cSAmit Kucheria }; 4596d2fa630cSAmit Kucheria map1 { 4597d2fa630cSAmit Kucheria trip = <&cpu5_top_alert1>; 4598d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4599d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4600d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4601d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4602d2fa630cSAmit Kucheria }; 4603d2fa630cSAmit Kucheria }; 4604d2fa630cSAmit Kucheria }; 4605d2fa630cSAmit Kucheria 4606d2fa630cSAmit Kucheria cpu6-top-thermal { 4607d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4608d2fa630cSAmit Kucheria polling-delay = <1000>; 4609d2fa630cSAmit Kucheria 4610d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 9>; 4611d2fa630cSAmit Kucheria 4612d2fa630cSAmit Kucheria trips { 4613d2fa630cSAmit Kucheria cpu6_top_alert0: trip-point0 { 4614d2fa630cSAmit Kucheria temperature = <90000>; 4615d2fa630cSAmit Kucheria hysteresis = <2000>; 4616d2fa630cSAmit Kucheria type = "passive"; 4617d2fa630cSAmit Kucheria }; 4618d2fa630cSAmit Kucheria 4619d2fa630cSAmit Kucheria cpu6_top_alert1: trip-point1 { 4620d2fa630cSAmit Kucheria temperature = <95000>; 4621d2fa630cSAmit Kucheria hysteresis = <2000>; 4622d2fa630cSAmit Kucheria type = "passive"; 4623d2fa630cSAmit Kucheria }; 4624d2fa630cSAmit Kucheria 4625*1364acc3SKrzysztof Kozlowski cpu6_top_crit: cpu-crit { 4626d2fa630cSAmit Kucheria temperature = <110000>; 4627d2fa630cSAmit Kucheria hysteresis = <1000>; 4628d2fa630cSAmit Kucheria type = "critical"; 4629d2fa630cSAmit Kucheria }; 4630d2fa630cSAmit Kucheria }; 4631d2fa630cSAmit Kucheria 4632d2fa630cSAmit Kucheria cooling-maps { 4633d2fa630cSAmit Kucheria map0 { 4634d2fa630cSAmit Kucheria trip = <&cpu6_top_alert0>; 4635d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4636d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4637d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4638d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4639d2fa630cSAmit Kucheria }; 4640d2fa630cSAmit Kucheria map1 { 4641d2fa630cSAmit Kucheria trip = <&cpu6_top_alert1>; 4642d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4643d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4644d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4645d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4646d2fa630cSAmit Kucheria }; 4647d2fa630cSAmit Kucheria }; 4648d2fa630cSAmit Kucheria }; 4649d2fa630cSAmit Kucheria 4650d2fa630cSAmit Kucheria cpu7-top-thermal { 4651d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4652d2fa630cSAmit Kucheria polling-delay = <1000>; 4653d2fa630cSAmit Kucheria 4654d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 10>; 4655d2fa630cSAmit Kucheria 4656d2fa630cSAmit Kucheria trips { 4657d2fa630cSAmit Kucheria cpu7_top_alert0: trip-point0 { 4658d2fa630cSAmit Kucheria temperature = <90000>; 4659d2fa630cSAmit Kucheria hysteresis = <2000>; 4660d2fa630cSAmit Kucheria type = "passive"; 4661d2fa630cSAmit Kucheria }; 4662d2fa630cSAmit Kucheria 4663d2fa630cSAmit Kucheria cpu7_top_alert1: trip-point1 { 4664d2fa630cSAmit Kucheria temperature = <95000>; 4665d2fa630cSAmit Kucheria hysteresis = <2000>; 4666d2fa630cSAmit Kucheria type = "passive"; 4667d2fa630cSAmit Kucheria }; 4668d2fa630cSAmit Kucheria 4669*1364acc3SKrzysztof Kozlowski cpu7_top_crit: cpu-crit { 4670d2fa630cSAmit Kucheria temperature = <110000>; 4671d2fa630cSAmit Kucheria hysteresis = <1000>; 4672d2fa630cSAmit Kucheria type = "critical"; 4673d2fa630cSAmit Kucheria }; 4674d2fa630cSAmit Kucheria }; 4675d2fa630cSAmit Kucheria 4676d2fa630cSAmit Kucheria cooling-maps { 4677d2fa630cSAmit Kucheria map0 { 4678d2fa630cSAmit Kucheria trip = <&cpu7_top_alert0>; 4679d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4680d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4681d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4682d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4683d2fa630cSAmit Kucheria }; 4684d2fa630cSAmit Kucheria map1 { 4685d2fa630cSAmit Kucheria trip = <&cpu7_top_alert1>; 4686d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4687d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4688d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4689d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4690d2fa630cSAmit Kucheria }; 4691d2fa630cSAmit Kucheria }; 4692d2fa630cSAmit Kucheria }; 4693d2fa630cSAmit Kucheria 4694d2fa630cSAmit Kucheria cpu4-bottom-thermal { 4695d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4696d2fa630cSAmit Kucheria polling-delay = <1000>; 4697d2fa630cSAmit Kucheria 4698d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 11>; 4699d2fa630cSAmit Kucheria 4700d2fa630cSAmit Kucheria trips { 4701d2fa630cSAmit Kucheria cpu4_bottom_alert0: trip-point0 { 4702d2fa630cSAmit Kucheria temperature = <90000>; 4703d2fa630cSAmit Kucheria hysteresis = <2000>; 4704d2fa630cSAmit Kucheria type = "passive"; 4705d2fa630cSAmit Kucheria }; 4706d2fa630cSAmit Kucheria 4707d2fa630cSAmit Kucheria cpu4_bottom_alert1: trip-point1 { 4708d2fa630cSAmit Kucheria temperature = <95000>; 4709d2fa630cSAmit Kucheria hysteresis = <2000>; 4710d2fa630cSAmit Kucheria type = "passive"; 4711d2fa630cSAmit Kucheria }; 4712d2fa630cSAmit Kucheria 4713*1364acc3SKrzysztof Kozlowski cpu4_bottom_crit: cpu-crit { 4714d2fa630cSAmit Kucheria temperature = <110000>; 4715d2fa630cSAmit Kucheria hysteresis = <1000>; 4716d2fa630cSAmit Kucheria type = "critical"; 4717d2fa630cSAmit Kucheria }; 4718d2fa630cSAmit Kucheria }; 4719d2fa630cSAmit Kucheria 4720d2fa630cSAmit Kucheria cooling-maps { 4721d2fa630cSAmit Kucheria map0 { 4722d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert0>; 4723d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4724d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4725d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4726d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4727d2fa630cSAmit Kucheria }; 4728d2fa630cSAmit Kucheria map1 { 4729d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert1>; 4730d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4731d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4732d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4733d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4734d2fa630cSAmit Kucheria }; 4735d2fa630cSAmit Kucheria }; 4736d2fa630cSAmit Kucheria }; 4737d2fa630cSAmit Kucheria 4738d2fa630cSAmit Kucheria cpu5-bottom-thermal { 4739d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4740d2fa630cSAmit Kucheria polling-delay = <1000>; 4741d2fa630cSAmit Kucheria 4742d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 12>; 4743d2fa630cSAmit Kucheria 4744d2fa630cSAmit Kucheria trips { 4745d2fa630cSAmit Kucheria cpu5_bottom_alert0: trip-point0 { 4746d2fa630cSAmit Kucheria temperature = <90000>; 4747d2fa630cSAmit Kucheria hysteresis = <2000>; 4748d2fa630cSAmit Kucheria type = "passive"; 4749d2fa630cSAmit Kucheria }; 4750d2fa630cSAmit Kucheria 4751d2fa630cSAmit Kucheria cpu5_bottom_alert1: trip-point1 { 4752d2fa630cSAmit Kucheria temperature = <95000>; 4753d2fa630cSAmit Kucheria hysteresis = <2000>; 4754d2fa630cSAmit Kucheria type = "passive"; 4755d2fa630cSAmit Kucheria }; 4756d2fa630cSAmit Kucheria 4757*1364acc3SKrzysztof Kozlowski cpu5_bottom_crit: cpu-crit { 4758d2fa630cSAmit Kucheria temperature = <110000>; 4759d2fa630cSAmit Kucheria hysteresis = <1000>; 4760d2fa630cSAmit Kucheria type = "critical"; 4761d2fa630cSAmit Kucheria }; 4762d2fa630cSAmit Kucheria }; 4763d2fa630cSAmit Kucheria 4764d2fa630cSAmit Kucheria cooling-maps { 4765d2fa630cSAmit Kucheria map0 { 4766d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert0>; 4767d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4768d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4769d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4770d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4771d2fa630cSAmit Kucheria }; 4772d2fa630cSAmit Kucheria map1 { 4773d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert1>; 4774d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4775d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4776d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4777d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4778d2fa630cSAmit Kucheria }; 4779d2fa630cSAmit Kucheria }; 4780d2fa630cSAmit Kucheria }; 4781d2fa630cSAmit Kucheria 4782d2fa630cSAmit Kucheria cpu6-bottom-thermal { 4783d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4784d2fa630cSAmit Kucheria polling-delay = <1000>; 4785d2fa630cSAmit Kucheria 4786d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 13>; 4787d2fa630cSAmit Kucheria 4788d2fa630cSAmit Kucheria trips { 4789d2fa630cSAmit Kucheria cpu6_bottom_alert0: trip-point0 { 4790d2fa630cSAmit Kucheria temperature = <90000>; 4791d2fa630cSAmit Kucheria hysteresis = <2000>; 4792d2fa630cSAmit Kucheria type = "passive"; 4793d2fa630cSAmit Kucheria }; 4794d2fa630cSAmit Kucheria 4795d2fa630cSAmit Kucheria cpu6_bottom_alert1: trip-point1 { 4796d2fa630cSAmit Kucheria temperature = <95000>; 4797d2fa630cSAmit Kucheria hysteresis = <2000>; 4798d2fa630cSAmit Kucheria type = "passive"; 4799d2fa630cSAmit Kucheria }; 4800d2fa630cSAmit Kucheria 4801*1364acc3SKrzysztof Kozlowski cpu6_bottom_crit: cpu-crit { 4802d2fa630cSAmit Kucheria temperature = <110000>; 4803d2fa630cSAmit Kucheria hysteresis = <1000>; 4804d2fa630cSAmit Kucheria type = "critical"; 4805d2fa630cSAmit Kucheria }; 4806d2fa630cSAmit Kucheria }; 4807d2fa630cSAmit Kucheria 4808d2fa630cSAmit Kucheria cooling-maps { 4809d2fa630cSAmit Kucheria map0 { 4810d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert0>; 4811d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4812d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4813d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4814d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4815d2fa630cSAmit Kucheria }; 4816d2fa630cSAmit Kucheria map1 { 4817d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert1>; 4818d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4819d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4820d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4821d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4822d2fa630cSAmit Kucheria }; 4823d2fa630cSAmit Kucheria }; 4824d2fa630cSAmit Kucheria }; 4825d2fa630cSAmit Kucheria 4826d2fa630cSAmit Kucheria cpu7-bottom-thermal { 4827d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4828d2fa630cSAmit Kucheria polling-delay = <1000>; 4829d2fa630cSAmit Kucheria 4830d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 14>; 4831d2fa630cSAmit Kucheria 4832d2fa630cSAmit Kucheria trips { 4833d2fa630cSAmit Kucheria cpu7_bottom_alert0: trip-point0 { 4834d2fa630cSAmit Kucheria temperature = <90000>; 4835d2fa630cSAmit Kucheria hysteresis = <2000>; 4836d2fa630cSAmit Kucheria type = "passive"; 4837d2fa630cSAmit Kucheria }; 4838d2fa630cSAmit Kucheria 4839d2fa630cSAmit Kucheria cpu7_bottom_alert1: trip-point1 { 4840d2fa630cSAmit Kucheria temperature = <95000>; 4841d2fa630cSAmit Kucheria hysteresis = <2000>; 4842d2fa630cSAmit Kucheria type = "passive"; 4843d2fa630cSAmit Kucheria }; 4844d2fa630cSAmit Kucheria 4845*1364acc3SKrzysztof Kozlowski cpu7_bottom_crit: cpu-crit { 4846d2fa630cSAmit Kucheria temperature = <110000>; 4847d2fa630cSAmit Kucheria hysteresis = <1000>; 4848d2fa630cSAmit Kucheria type = "critical"; 4849d2fa630cSAmit Kucheria }; 4850d2fa630cSAmit Kucheria }; 4851d2fa630cSAmit Kucheria 4852d2fa630cSAmit Kucheria cooling-maps { 4853d2fa630cSAmit Kucheria map0 { 4854d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert0>; 4855d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4856d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4857d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4858d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4859d2fa630cSAmit Kucheria }; 4860d2fa630cSAmit Kucheria map1 { 4861d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert1>; 4862d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4863d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4864d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4865d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4866d2fa630cSAmit Kucheria }; 4867d2fa630cSAmit Kucheria }; 4868d2fa630cSAmit Kucheria }; 4869d2fa630cSAmit Kucheria 4870d2fa630cSAmit Kucheria aoss0-thermal { 4871d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4872d2fa630cSAmit Kucheria polling-delay = <1000>; 4873d2fa630cSAmit Kucheria 4874d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 0>; 4875d2fa630cSAmit Kucheria 4876d2fa630cSAmit Kucheria trips { 4877d2fa630cSAmit Kucheria aoss0_alert0: trip-point0 { 4878d2fa630cSAmit Kucheria temperature = <90000>; 4879d2fa630cSAmit Kucheria hysteresis = <2000>; 4880d2fa630cSAmit Kucheria type = "hot"; 4881d2fa630cSAmit Kucheria }; 4882d2fa630cSAmit Kucheria }; 4883d2fa630cSAmit Kucheria }; 4884d2fa630cSAmit Kucheria 4885d2fa630cSAmit Kucheria cluster0-thermal { 4886d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4887d2fa630cSAmit Kucheria polling-delay = <1000>; 4888d2fa630cSAmit Kucheria 4889d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 5>; 4890d2fa630cSAmit Kucheria 4891d2fa630cSAmit Kucheria trips { 4892d2fa630cSAmit Kucheria cluster0_alert0: trip-point0 { 4893d2fa630cSAmit Kucheria temperature = <90000>; 4894d2fa630cSAmit Kucheria hysteresis = <2000>; 4895d2fa630cSAmit Kucheria type = "hot"; 4896d2fa630cSAmit Kucheria }; 4897d2fa630cSAmit Kucheria cluster0_crit: cluster0_crit { 4898d2fa630cSAmit Kucheria temperature = <110000>; 4899d2fa630cSAmit Kucheria hysteresis = <2000>; 4900d2fa630cSAmit Kucheria type = "critical"; 4901d2fa630cSAmit Kucheria }; 4902d2fa630cSAmit Kucheria }; 4903d2fa630cSAmit Kucheria }; 4904d2fa630cSAmit Kucheria 4905d2fa630cSAmit Kucheria cluster1-thermal { 4906d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4907d2fa630cSAmit Kucheria polling-delay = <1000>; 4908d2fa630cSAmit Kucheria 4909d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 6>; 4910d2fa630cSAmit Kucheria 4911d2fa630cSAmit Kucheria trips { 4912d2fa630cSAmit Kucheria cluster1_alert0: trip-point0 { 4913d2fa630cSAmit Kucheria temperature = <90000>; 4914d2fa630cSAmit Kucheria hysteresis = <2000>; 4915d2fa630cSAmit Kucheria type = "hot"; 4916d2fa630cSAmit Kucheria }; 4917d2fa630cSAmit Kucheria cluster1_crit: cluster1_crit { 4918d2fa630cSAmit Kucheria temperature = <110000>; 4919d2fa630cSAmit Kucheria hysteresis = <2000>; 4920d2fa630cSAmit Kucheria type = "critical"; 4921d2fa630cSAmit Kucheria }; 4922d2fa630cSAmit Kucheria }; 4923d2fa630cSAmit Kucheria }; 4924d2fa630cSAmit Kucheria 49257be1c395SDavid Heidelberg gpu-top-thermal { 4926d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4927d2fa630cSAmit Kucheria polling-delay = <1000>; 4928d2fa630cSAmit Kucheria 4929d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 15>; 4930d2fa630cSAmit Kucheria 4931d2fa630cSAmit Kucheria trips { 4932d2fa630cSAmit Kucheria gpu1_alert0: trip-point0 { 4933d2fa630cSAmit Kucheria temperature = <90000>; 4934d2fa630cSAmit Kucheria hysteresis = <2000>; 4935d2fa630cSAmit Kucheria type = "hot"; 4936d2fa630cSAmit Kucheria }; 4937d2fa630cSAmit Kucheria }; 4938d2fa630cSAmit Kucheria }; 4939d2fa630cSAmit Kucheria 4940d2fa630cSAmit Kucheria aoss1-thermal { 4941d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4942d2fa630cSAmit Kucheria polling-delay = <1000>; 4943d2fa630cSAmit Kucheria 4944d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 0>; 4945d2fa630cSAmit Kucheria 4946d2fa630cSAmit Kucheria trips { 4947d2fa630cSAmit Kucheria aoss1_alert0: trip-point0 { 4948d2fa630cSAmit Kucheria temperature = <90000>; 4949d2fa630cSAmit Kucheria hysteresis = <2000>; 4950d2fa630cSAmit Kucheria type = "hot"; 4951d2fa630cSAmit Kucheria }; 4952d2fa630cSAmit Kucheria }; 4953d2fa630cSAmit Kucheria }; 4954d2fa630cSAmit Kucheria 4955d2fa630cSAmit Kucheria wlan-thermal { 4956d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4957d2fa630cSAmit Kucheria polling-delay = <1000>; 4958d2fa630cSAmit Kucheria 4959d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 1>; 4960d2fa630cSAmit Kucheria 4961d2fa630cSAmit Kucheria trips { 4962d2fa630cSAmit Kucheria wlan_alert0: trip-point0 { 4963d2fa630cSAmit Kucheria temperature = <90000>; 4964d2fa630cSAmit Kucheria hysteresis = <2000>; 4965d2fa630cSAmit Kucheria type = "hot"; 4966d2fa630cSAmit Kucheria }; 4967d2fa630cSAmit Kucheria }; 4968d2fa630cSAmit Kucheria }; 4969d2fa630cSAmit Kucheria 4970d2fa630cSAmit Kucheria video-thermal { 4971d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4972d2fa630cSAmit Kucheria polling-delay = <1000>; 4973d2fa630cSAmit Kucheria 4974d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 2>; 4975d2fa630cSAmit Kucheria 4976d2fa630cSAmit Kucheria trips { 4977d2fa630cSAmit Kucheria video_alert0: trip-point0 { 4978d2fa630cSAmit Kucheria temperature = <90000>; 4979d2fa630cSAmit Kucheria hysteresis = <2000>; 4980d2fa630cSAmit Kucheria type = "hot"; 4981d2fa630cSAmit Kucheria }; 4982d2fa630cSAmit Kucheria }; 4983d2fa630cSAmit Kucheria }; 4984d2fa630cSAmit Kucheria 4985d2fa630cSAmit Kucheria mem-thermal { 4986d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4987d2fa630cSAmit Kucheria polling-delay = <1000>; 4988d2fa630cSAmit Kucheria 4989d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 3>; 4990d2fa630cSAmit Kucheria 4991d2fa630cSAmit Kucheria trips { 4992d2fa630cSAmit Kucheria mem_alert0: trip-point0 { 4993d2fa630cSAmit Kucheria temperature = <90000>; 4994d2fa630cSAmit Kucheria hysteresis = <2000>; 4995d2fa630cSAmit Kucheria type = "hot"; 4996d2fa630cSAmit Kucheria }; 4997d2fa630cSAmit Kucheria }; 4998d2fa630cSAmit Kucheria }; 4999d2fa630cSAmit Kucheria 5000d2fa630cSAmit Kucheria q6-hvx-thermal { 5001d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5002d2fa630cSAmit Kucheria polling-delay = <1000>; 5003d2fa630cSAmit Kucheria 5004d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 4>; 5005d2fa630cSAmit Kucheria 5006d2fa630cSAmit Kucheria trips { 5007d2fa630cSAmit Kucheria q6_hvx_alert0: trip-point0 { 5008d2fa630cSAmit Kucheria temperature = <90000>; 5009d2fa630cSAmit Kucheria hysteresis = <2000>; 5010d2fa630cSAmit Kucheria type = "hot"; 5011d2fa630cSAmit Kucheria }; 5012d2fa630cSAmit Kucheria }; 5013d2fa630cSAmit Kucheria }; 5014d2fa630cSAmit Kucheria 5015d2fa630cSAmit Kucheria camera-thermal { 5016d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5017d2fa630cSAmit Kucheria polling-delay = <1000>; 5018d2fa630cSAmit Kucheria 5019d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 5>; 5020d2fa630cSAmit Kucheria 5021d2fa630cSAmit Kucheria trips { 5022d2fa630cSAmit Kucheria camera_alert0: trip-point0 { 5023d2fa630cSAmit Kucheria temperature = <90000>; 5024d2fa630cSAmit Kucheria hysteresis = <2000>; 5025d2fa630cSAmit Kucheria type = "hot"; 5026d2fa630cSAmit Kucheria }; 5027d2fa630cSAmit Kucheria }; 5028d2fa630cSAmit Kucheria }; 5029d2fa630cSAmit Kucheria 5030d2fa630cSAmit Kucheria compute-thermal { 5031d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5032d2fa630cSAmit Kucheria polling-delay = <1000>; 5033d2fa630cSAmit Kucheria 5034d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 6>; 5035d2fa630cSAmit Kucheria 5036d2fa630cSAmit Kucheria trips { 5037d2fa630cSAmit Kucheria compute_alert0: trip-point0 { 5038d2fa630cSAmit Kucheria temperature = <90000>; 5039d2fa630cSAmit Kucheria hysteresis = <2000>; 5040d2fa630cSAmit Kucheria type = "hot"; 5041d2fa630cSAmit Kucheria }; 5042d2fa630cSAmit Kucheria }; 5043d2fa630cSAmit Kucheria }; 5044d2fa630cSAmit Kucheria 5045d2fa630cSAmit Kucheria modem-thermal { 5046d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5047d2fa630cSAmit Kucheria polling-delay = <1000>; 5048d2fa630cSAmit Kucheria 5049d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 7>; 5050d2fa630cSAmit Kucheria 5051d2fa630cSAmit Kucheria trips { 5052d2fa630cSAmit Kucheria modem_alert0: trip-point0 { 5053d2fa630cSAmit Kucheria temperature = <90000>; 5054d2fa630cSAmit Kucheria hysteresis = <2000>; 5055d2fa630cSAmit Kucheria type = "hot"; 5056d2fa630cSAmit Kucheria }; 5057d2fa630cSAmit Kucheria }; 5058d2fa630cSAmit Kucheria }; 5059d2fa630cSAmit Kucheria 5060d2fa630cSAmit Kucheria npu-thermal { 5061d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5062d2fa630cSAmit Kucheria polling-delay = <1000>; 5063d2fa630cSAmit Kucheria 5064d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 8>; 5065d2fa630cSAmit Kucheria 5066d2fa630cSAmit Kucheria trips { 5067d2fa630cSAmit Kucheria npu_alert0: trip-point0 { 5068d2fa630cSAmit Kucheria temperature = <90000>; 5069d2fa630cSAmit Kucheria hysteresis = <2000>; 5070d2fa630cSAmit Kucheria type = "hot"; 5071d2fa630cSAmit Kucheria }; 5072d2fa630cSAmit Kucheria }; 5073d2fa630cSAmit Kucheria }; 5074d2fa630cSAmit Kucheria 5075d2fa630cSAmit Kucheria modem-vec-thermal { 5076d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5077d2fa630cSAmit Kucheria polling-delay = <1000>; 5078d2fa630cSAmit Kucheria 5079d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 9>; 5080d2fa630cSAmit Kucheria 5081d2fa630cSAmit Kucheria trips { 5082d2fa630cSAmit Kucheria modem_vec_alert0: trip-point0 { 5083d2fa630cSAmit Kucheria temperature = <90000>; 5084d2fa630cSAmit Kucheria hysteresis = <2000>; 5085d2fa630cSAmit Kucheria type = "hot"; 5086d2fa630cSAmit Kucheria }; 5087d2fa630cSAmit Kucheria }; 5088d2fa630cSAmit Kucheria }; 5089d2fa630cSAmit Kucheria 5090d2fa630cSAmit Kucheria modem-scl-thermal { 5091d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5092d2fa630cSAmit Kucheria polling-delay = <1000>; 5093d2fa630cSAmit Kucheria 5094d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 10>; 5095d2fa630cSAmit Kucheria 5096d2fa630cSAmit Kucheria trips { 5097d2fa630cSAmit Kucheria modem_scl_alert0: trip-point0 { 5098d2fa630cSAmit Kucheria temperature = <90000>; 5099d2fa630cSAmit Kucheria hysteresis = <2000>; 5100d2fa630cSAmit Kucheria type = "hot"; 5101d2fa630cSAmit Kucheria }; 5102d2fa630cSAmit Kucheria }; 5103d2fa630cSAmit Kucheria }; 5104d2fa630cSAmit Kucheria 51057be1c395SDavid Heidelberg gpu-bottom-thermal { 5106d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5107d2fa630cSAmit Kucheria polling-delay = <1000>; 5108d2fa630cSAmit Kucheria 5109d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 11>; 5110d2fa630cSAmit Kucheria 5111d2fa630cSAmit Kucheria trips { 5112d2fa630cSAmit Kucheria gpu2_alert0: trip-point0 { 5113d2fa630cSAmit Kucheria temperature = <90000>; 5114d2fa630cSAmit Kucheria hysteresis = <2000>; 5115d2fa630cSAmit Kucheria type = "hot"; 5116d2fa630cSAmit Kucheria }; 5117d2fa630cSAmit Kucheria }; 5118d2fa630cSAmit Kucheria }; 5119d2fa630cSAmit Kucheria }; 5120e13c6d14SVinod Koul}; 5121