1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/clock/qcom,sm6375-gcc.h> 8#include <dt-bindings/dma/qcom-gpi.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/mailbox/qcom-ipcc.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { }; 20 21 clocks { 22 xo_board_clk: xo-board-clk { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 }; 26 27 sleep_clk: sleep-clk { 28 compatible = "fixed-clock"; 29 clock-frequency = <32000>; 30 #clock-cells = <0>; 31 }; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 CPU0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "qcom,kryo660"; 41 reg = <0x0 0x0>; 42 enable-method = "psci"; 43 next-level-cache = <&L2_0>; 44 qcom,freq-domain = <&cpufreq_hw 0>; 45 power-domains = <&CPU_PD0>; 46 power-domain-names = "psci"; 47 #cooling-cells = <2>; 48 L2_0: l2-cache { 49 compatible = "cache"; 50 next-level-cache = <&L3_0>; 51 L3_0: l3-cache { 52 compatible = "cache"; 53 }; 54 }; 55 }; 56 57 CPU1: cpu@100 { 58 device_type = "cpu"; 59 compatible = "qcom,kryo660"; 60 reg = <0x0 0x100>; 61 enable-method = "psci"; 62 next-level-cache = <&L2_100>; 63 qcom,freq-domain = <&cpufreq_hw 0>; 64 power-domains = <&CPU_PD1>; 65 power-domain-names = "psci"; 66 #cooling-cells = <2>; 67 L2_100: l2-cache { 68 compatible = "cache"; 69 next-level-cache = <&L3_0>; 70 }; 71 }; 72 73 CPU2: cpu@200 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo660"; 76 reg = <0x0 0x200>; 77 enable-method = "psci"; 78 next-level-cache = <&L2_200>; 79 qcom,freq-domain = <&cpufreq_hw 0>; 80 power-domains = <&CPU_PD2>; 81 power-domain-names = "psci"; 82 #cooling-cells = <2>; 83 L2_200: l2-cache { 84 compatible = "cache"; 85 next-level-cache = <&L3_0>; 86 }; 87 }; 88 89 CPU3: cpu@300 { 90 device_type = "cpu"; 91 compatible = "qcom,kryo660"; 92 reg = <0x0 0x300>; 93 enable-method = "psci"; 94 next-level-cache = <&L2_300>; 95 qcom,freq-domain = <&cpufreq_hw 0>; 96 power-domains = <&CPU_PD3>; 97 power-domain-names = "psci"; 98 #cooling-cells = <2>; 99 L2_300: l2-cache { 100 compatible = "cache"; 101 next-level-cache = <&L3_0>; 102 }; 103 }; 104 105 CPU4: cpu@400 { 106 device_type = "cpu"; 107 compatible = "qcom,kryo660"; 108 reg = <0x0 0x400>; 109 enable-method = "psci"; 110 next-level-cache = <&L2_400>; 111 qcom,freq-domain = <&cpufreq_hw 0>; 112 power-domains = <&CPU_PD4>; 113 power-domain-names = "psci"; 114 #cooling-cells = <2>; 115 L2_400: l2-cache { 116 compatible = "cache"; 117 next-level-cache = <&L3_0>; 118 }; 119 }; 120 121 CPU5: cpu@500 { 122 device_type = "cpu"; 123 compatible = "qcom,kryo660"; 124 reg = <0x0 0x500>; 125 enable-method = "psci"; 126 next-level-cache = <&L2_500>; 127 qcom,freq-domain = <&cpufreq_hw 0>; 128 power-domains = <&CPU_PD5>; 129 power-domain-names = "psci"; 130 #cooling-cells = <2>; 131 L2_500: l2-cache { 132 compatible = "cache"; 133 next-level-cache = <&L3_0>; 134 }; 135 136 }; 137 138 CPU6: cpu@600 { 139 device_type = "cpu"; 140 compatible = "qcom,kryo660"; 141 reg = <0x0 0x600>; 142 enable-method = "psci"; 143 next-level-cache = <&L2_600>; 144 qcom,freq-domain = <&cpufreq_hw 1>; 145 power-domains = <&CPU_PD6>; 146 power-domain-names = "psci"; 147 #cooling-cells = <2>; 148 L2_600: l2-cache { 149 compatible = "cache"; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU7: cpu@700 { 155 device_type = "cpu"; 156 compatible = "qcom,kryo660"; 157 reg = <0x0 0x700>; 158 enable-method = "psci"; 159 next-level-cache = <&L2_700>; 160 qcom,freq-domain = <&cpufreq_hw 1>; 161 power-domains = <&CPU_PD7>; 162 power-domain-names = "psci"; 163 #cooling-cells = <2>; 164 L2_700: l2-cache { 165 compatible = "cache"; 166 next-level-cache = <&L3_0>; 167 }; 168 }; 169 170 cpu-map { 171 cluster0 { 172 core0 { 173 cpu = <&CPU0>; 174 }; 175 176 core1 { 177 cpu = <&CPU1>; 178 }; 179 180 core2 { 181 cpu = <&CPU2>; 182 }; 183 184 core3 { 185 cpu = <&CPU3>; 186 }; 187 188 core4 { 189 cpu = <&CPU4>; 190 }; 191 192 core5 { 193 cpu = <&CPU5>; 194 }; 195 196 core6 { 197 cpu = <&CPU6>; 198 }; 199 200 core7 { 201 cpu = <&CPU7>; 202 }; 203 }; 204 }; 205 206 idle-states { 207 entry-method = "psci"; 208 209 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 210 compatible = "arm,idle-state"; 211 idle-state-name = "silver-rail-power-collapse"; 212 arm,psci-suspend-param = <0x40000004>; 213 entry-latency-us = <702>; 214 exit-latency-us = <915>; 215 min-residency-us = <4001>; 216 local-timer-stop; 217 }; 218 219 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 220 compatible = "arm,idle-state"; 221 idle-state-name = "gold-rail-power-collapse"; 222 arm,psci-suspend-param = <0x40000004>; 223 entry-latency-us = <526>; 224 exit-latency-us = <1854>; 225 min-residency-us = <5555>; 226 local-timer-stop; 227 }; 228 }; 229 230 domain-idle-states { 231 CLUSTER_SLEEP_0: cluster-sleep-0 { 232 compatible = "domain-idle-state"; 233 idle-state-name = "cluster-power-collapse"; 234 arm,psci-suspend-param = <0x41000044>; 235 entry-latency-us = <2752>; 236 exit-latency-us = <3048>; 237 min-residency-us = <6118>; 238 local-timer-stop; 239 }; 240 }; 241 }; 242 243 firmware { 244 scm { 245 compatible = "qcom,scm-sm6375", "qcom,scm"; 246 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 247 clock-names = "core"; 248 #reset-cells = <1>; 249 }; 250 }; 251 252 memory@80000000 { 253 device_type = "memory"; 254 /* We expect the bootloader to fill in the size */ 255 reg = <0x0 0x80000000 0x0 0x0>; 256 }; 257 258 pmu { 259 compatible = "arm,armv8-pmuv3"; 260 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 261 }; 262 263 psci { 264 compatible = "arm,psci-1.0"; 265 method = "smc"; 266 267 CPU_PD0: cpu0 { 268 #power-domain-cells = <0>; 269 power-domains = <&CLUSTER_PD>; 270 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 271 }; 272 273 CPU_PD1: cpu1 { 274 #power-domain-cells = <0>; 275 power-domains = <&CLUSTER_PD>; 276 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 277 }; 278 279 CPU_PD2: cpu2 { 280 #power-domain-cells = <0>; 281 power-domains = <&CLUSTER_PD>; 282 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 283 }; 284 285 CPU_PD3: cpu3 { 286 #power-domain-cells = <0>; 287 power-domains = <&CLUSTER_PD>; 288 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 289 }; 290 291 CPU_PD4: cpu4 { 292 #power-domain-cells = <0>; 293 power-domains = <&CLUSTER_PD>; 294 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 295 }; 296 297 CPU_PD5: cpu5 { 298 #power-domain-cells = <0>; 299 power-domains = <&CLUSTER_PD>; 300 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 301 }; 302 303 CPU_PD6: cpu6 { 304 #power-domain-cells = <0>; 305 power-domains = <&CLUSTER_PD>; 306 domain-idle-states = <&BIG_CPU_SLEEP_0>; 307 }; 308 309 CPU_PD7: cpu7 { 310 #power-domain-cells = <0>; 311 power-domains = <&CLUSTER_PD>; 312 domain-idle-states = <&BIG_CPU_SLEEP_0>; 313 }; 314 315 CLUSTER_PD: cpu-cluster0 { 316 #power-domain-cells = <0>; 317 domain-idle-states = <&CLUSTER_SLEEP_0>; 318 }; 319 }; 320 321 qup_opp_table: opp-table-qup { 322 compatible = "operating-points-v2"; 323 324 opp-75000000 { 325 opp-hz = /bits/ 64 <75000000>; 326 required-opps = <&rpmpd_opp_low_svs>; 327 }; 328 329 opp-100000000 { 330 opp-hz = /bits/ 64 <100000000>; 331 required-opps = <&rpmpd_opp_svs>; 332 }; 333 334 opp-128000000 { 335 opp-hz = /bits/ 64 <128000000>; 336 required-opps = <&rpmpd_opp_nom>; 337 }; 338 }; 339 340 reserved_memory: reserved-memory { 341 #address-cells = <2>; 342 #size-cells = <2>; 343 ranges; 344 345 hyp_mem: hypervisor@80000000 { 346 reg = <0 0x80000000 0 0x600000>; 347 no-map; 348 }; 349 350 xbl_aop_mem: xbl-aop@80700000 { 351 reg = <0 0x80700000 0 0x100000>; 352 no-map; 353 }; 354 355 reserved_xbl_uefi: xbl-uefi-res@80880000 { 356 reg = <0 0x80880000 0 0x14000>; 357 no-map; 358 }; 359 360 smem_mem: smem@80900000 { 361 compatible = "qcom,smem"; 362 reg = <0 0x80900000 0 0x200000>; 363 hwlocks = <&tcsr_mutex 3>; 364 no-map; 365 }; 366 367 fw_mem: fw@80b00000 { 368 reg = <0 0x80b00000 0 0x100000>; 369 no-map; 370 }; 371 372 cdsp_secure_heap_mem: cdsp-sec-heap@80c00000 { 373 reg = <0 0x80c00000 0 0x1e00000>; 374 no-map; 375 }; 376 377 dfps_data_mem: dpfs-data@85e00000 { 378 reg = <0 0x85e00000 0 0x100000>; 379 no-map; 380 }; 381 382 pil_wlan_mem: pil-wlan@86500000 { 383 reg = <0 0x86500000 0 0x200000>; 384 no-map; 385 }; 386 387 pil_adsp_mem: pil-adsp@86700000 { 388 reg = <0 0x86700000 0 0x2000000>; 389 no-map; 390 }; 391 392 pil_cdsp_mem: pil-cdsp@88700000 { 393 reg = <0 0x88700000 0 0x1e00000>; 394 no-map; 395 }; 396 397 pil_video_mem: pil-video@8a500000 { 398 reg = <0 0x8a500000 0 0x500000>; 399 no-map; 400 }; 401 402 pil_ipa_fw_mem: pil-ipa-fw@8aa00000 { 403 reg = <0 0x8aa00000 0 0x10000>; 404 no-map; 405 }; 406 407 pil_ipa_gsi_mem: pil-ipa-gsi@8aa10000 { 408 reg = <0 0x8aa10000 0 0xa000>; 409 no-map; 410 }; 411 412 pil_gpu_micro_code_mem: pil-gpu-ucode@8aa1a000 { 413 reg = <0 0x8aa1a000 0 0x2000>; 414 no-map; 415 }; 416 417 pil_mpss_wlan_mem: pil-mpss-wlan@8b800000 { 418 reg = <0 0x8b800000 0 0x10000000>; 419 no-map; 420 }; 421 422 removed_mem: removed@c0000000 { 423 reg = <0 0xc0000000 0 0x5100000>; 424 no-map; 425 }; 426 427 debug_mem: debug@ffb00000 { 428 reg = <0 0xffb00000 0 0xc0000>; 429 no-map; 430 }; 431 432 last_log_mem: lastlog@ffbc0000 { 433 reg = <0 0xffbc0000 0 0x80000>; 434 no-map; 435 }; 436 437 cmdline_region: cmdline@ffd00000 { 438 reg = <0 0xffd00000 0 0x1000>; 439 no-map; 440 }; 441 }; 442 443 rpm-glink { 444 compatible = "qcom,glink-rpm"; 445 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 446 IPCC_MPROC_SIGNAL_GLINK_QMP 447 IRQ_TYPE_EDGE_RISING>; 448 qcom,rpm-msg-ram = <&rpm_msg_ram>; 449 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 450 451 rpm_requests: rpm-requests { 452 compatible = "qcom,rpm-sm6375"; 453 qcom,glink-channels = "rpm_requests"; 454 455 rpmcc: clock-controller { 456 compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc"; 457 clocks = <&xo_board_clk>; 458 clock-names = "xo"; 459 #clock-cells = <1>; 460 }; 461 462 rpmpd: power-controller { 463 compatible = "qcom,sm6375-rpmpd"; 464 #power-domain-cells = <1>; 465 operating-points-v2 = <&rpmpd_opp_table>; 466 467 rpmpd_opp_table: opp-table { 468 compatible = "operating-points-v2"; 469 470 rpmpd_opp_ret: opp1 { 471 opp-level = <RPM_SMD_LEVEL_RETENTION>; 472 }; 473 474 rpmpd_opp_min_svs: opp2 { 475 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 476 }; 477 478 rpmpd_opp_low_svs: opp3 { 479 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 480 }; 481 482 rpmpd_opp_svs: opp4 { 483 opp-level = <RPM_SMD_LEVEL_SVS>; 484 }; 485 486 rpmpd_opp_svs_plus: opp5 { 487 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 488 }; 489 490 rpmpd_opp_nom: opp6 { 491 opp-level = <RPM_SMD_LEVEL_NOM>; 492 }; 493 494 rpmpd_opp_nom_plus: opp7 { 495 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 496 }; 497 498 rpmpd_opp_turbo: opp8 { 499 opp-level = <RPM_SMD_LEVEL_TURBO>; 500 }; 501 502 rpmpd_opp_turbo_no_cpr: opp9 { 503 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 504 }; 505 }; 506 }; 507 }; 508 }; 509 510 smp2p-adsp { 511 compatible = "qcom,smp2p"; 512 qcom,smem = <443>, <429>; 513 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 514 IPCC_MPROC_SIGNAL_SMP2P 515 IRQ_TYPE_EDGE_RISING>; 516 mboxes = <&ipcc IPCC_CLIENT_LPASS 517 IPCC_MPROC_SIGNAL_SMP2P>; 518 519 qcom,local-pid = <0>; 520 qcom,remote-pid = <2>; 521 522 smp2p_adsp_out: master-kernel { 523 qcom,entry-name = "master-kernel"; 524 #qcom,smem-state-cells = <1>; 525 }; 526 527 smp2p_adsp_in: slave-kernel { 528 qcom,entry-name = "slave-kernel"; 529 interrupt-controller; 530 #interrupt-cells = <2>; 531 }; 532 }; 533 534 smp2p-cdsp { 535 compatible = "qcom,smp2p"; 536 qcom,smem = <94>, <432>; 537 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 538 IPCC_MPROC_SIGNAL_SMP2P 539 IRQ_TYPE_EDGE_RISING>; 540 mboxes = <&ipcc IPCC_CLIENT_CDSP 541 IPCC_MPROC_SIGNAL_SMP2P>; 542 543 qcom,local-pid = <0>; 544 qcom,remote-pid = <5>; 545 546 smp2p_cdsp_out: master-kernel { 547 qcom,entry-name = "master-kernel"; 548 #qcom,smem-state-cells = <1>; 549 }; 550 551 smp2p_cdsp_in: slave-kernel { 552 qcom,entry-name = "slave-kernel"; 553 interrupt-controller; 554 #interrupt-cells = <2>; 555 }; 556 }; 557 558 soc: soc@0 { 559 #address-cells = <2>; 560 #size-cells = <2>; 561 ranges = <0 0 0 0 0x10 0>; 562 dma-ranges = <0 0 0 0 0x10 0>; 563 compatible = "simple-bus"; 564 565 ipcc: mailbox@208000 { 566 compatible = "qcom,sm6375-ipcc", "qcom,ipcc"; 567 reg = <0 0x00208000 0 0x1000>; 568 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 569 interrupt-controller; 570 #interrupt-cells = <3>; 571 #mbox-cells = <2>; 572 }; 573 574 tcsr_mutex: hwlock@340000 { 575 compatible = "qcom,tcsr-mutex"; 576 reg = <0x0 0x00340000 0x0 0x40000>; 577 #hwlock-cells = <1>; 578 }; 579 580 tlmm: pinctrl@500000 { 581 compatible = "qcom,sm6375-tlmm"; 582 reg = <0 0x00500000 0 0x800000>; 583 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 584 gpio-ranges = <&tlmm 0 0 157>; 585 /* TODO: Hook up MPM as wakeup-parent when it's there */ 586 interrupt-controller; 587 gpio-controller; 588 #interrupt-cells = <2>; 589 #gpio-cells = <2>; 590 591 sdc2_off_state: sdc2-off-state { 592 clk-pins { 593 pins = "sdc2_clk"; 594 drive-strength = <2>; 595 bias-disable; 596 }; 597 598 cmd-pins { 599 pins = "sdc2_cmd"; 600 drive-strength = <2>; 601 bias-pull-up; 602 }; 603 604 data-pins { 605 pins = "sdc2_data"; 606 drive-strength = <2>; 607 bias-pull-up; 608 }; 609 }; 610 611 sdc2_on_state: sdc2-on-state { 612 clk-pins { 613 pins = "sdc2_clk"; 614 drive-strength = <16>; 615 bias-disable; 616 }; 617 618 cmd-pins { 619 pins = "sdc2_cmd"; 620 drive-strength = <10>; 621 bias-pull-up; 622 }; 623 624 data-pins { 625 pins = "sdc2_data"; 626 drive-strength = <10>; 627 bias-pull-up; 628 }; 629 }; 630 631 qup_i2c0_default: qup-i2c0-default-state { 632 pins = "gpio0", "gpio1"; 633 function = "qup00"; 634 drive-strength = <2>; 635 bias-pull-up; 636 }; 637 638 qup_i2c1_default: qup-i2c1-default-state { 639 pins = "gpio61", "gpio62"; 640 function = "qup01"; 641 drive-strength = <2>; 642 bias-pull-up; 643 }; 644 645 qup_i2c2_default: qup-i2c2-default-state { 646 pins = "gpio45", "gpio46"; 647 function = "qup02"; 648 drive-strength = <2>; 649 bias-pull-up; 650 }; 651 652 qup_i2c8_default: qup-i2c8-default-state { 653 pins = "gpio19", "gpio20"; 654 /* TLMM, GCC and vendor DT all have different indices.. */ 655 function = "qup12"; 656 drive-strength = <2>; 657 bias-pull-up; 658 }; 659 660 qup_i2c10_default: qup-i2c10-default-state { 661 pins = "gpio4", "gpio5"; 662 function = "qup10"; 663 drive-strength = <2>; 664 bias-pull-up; 665 }; 666 667 qup_spi0_default: qup-spi0-default-state { 668 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 669 function = "qup00"; 670 drive-strength = <6>; 671 bias-disable; 672 }; 673 }; 674 675 gcc: clock-controller@1400000 { 676 compatible = "qcom,sm6375-gcc"; 677 reg = <0 0x01400000 0 0x1f0000>; 678 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 679 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 680 <&sleep_clk>; 681 #power-domain-cells = <1>; 682 #clock-cells = <1>; 683 #reset-cells = <1>; 684 }; 685 686 usb_1_hsphy: phy@162b000 { 687 compatible = "qcom,sm6375-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; 688 reg = <0 0x0162b000 0 0x400>; 689 690 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 691 clock-names = "ref"; 692 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 693 #phy-cells = <0>; 694 695 status = "disabled"; 696 }; 697 698 spmi_bus: spmi@1c40000 { 699 compatible = "qcom,spmi-pmic-arb"; 700 reg = <0 0x01c40000 0 0x1100>, 701 <0 0x01e00000 0 0x2000000>, 702 <0 0x03e00000 0 0x100000>, 703 <0 0x03f00000 0 0xa0000>, 704 <0 0x01c0a000 0 0x26000>; 705 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 706 interrupt-names = "periph_irq"; 707 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 708 qcom,ee = <0>; 709 qcom,channel = <0>; 710 #address-cells = <2>; 711 #size-cells = <0>; 712 interrupt-controller; 713 #interrupt-cells = <4>; 714 }; 715 716 rpm_msg_ram: sram@45f0000 { 717 compatible = "qcom,rpm-msg-ram"; 718 reg = <0 0x045f0000 0 0x7000>; 719 }; 720 721 sdhc_2: mmc@4784000 { 722 compatible = "qcom,sm6375-sdhci", "qcom,sdhci-msm-v5"; 723 reg = <0 0x04784000 0 0x1000>; 724 725 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 727 interrupt-names = "hc_irq", "pwr_irq"; 728 729 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 730 <&gcc GCC_SDCC2_APPS_CLK>, 731 <&rpmcc RPM_SMD_XO_CLK_SRC>; 732 clock-names = "iface", "core", "xo"; 733 resets = <&gcc GCC_SDCC2_BCR>; 734 iommus = <&apps_smmu 0x40 0x0>; 735 736 pinctrl-0 = <&sdc2_on_state>; 737 pinctrl-1 = <&sdc2_off_state>; 738 pinctrl-names = "default", "sleep"; 739 740 qcom,dll-config = <0x0007642c>; 741 qcom,ddr-config = <0x80040868>; 742 power-domains = <&rpmpd SM6375_VDDCX>; 743 operating-points-v2 = <&sdhc2_opp_table>; 744 bus-width = <4>; 745 746 status = "disabled"; 747 748 sdhc2_opp_table: opp-table { 749 compatible = "operating-points-v2"; 750 751 opp-100000000 { 752 opp-hz = /bits/ 64 <100000000>; 753 required-opps = <&rpmpd_opp_low_svs>; 754 }; 755 756 opp-202000000 { 757 opp-hz = /bits/ 64 <202000000>; 758 required-opps = <&rpmpd_opp_svs_plus>; 759 }; 760 }; 761 }; 762 763 gpi_dma0: dma-controller@4a00000 { 764 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; 765 reg = <0 0x04a00000 0 0x60000>; 766 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 776 dma-channels = <10>; 777 dma-channel-mask = <0x1f>; 778 iommus = <&apps_smmu 0x16 0x0>; 779 #dma-cells = <3>; 780 status = "disabled"; 781 }; 782 783 qupv3_id_0: geniqup@4ac0000 { 784 compatible = "qcom,geni-se-qup"; 785 reg = <0x0 0x04ac0000 0x0 0x2000>; 786 clock-names = "m-ahb", "s-ahb"; 787 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 788 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 789 iommus = <&apps_smmu 0x3 0x0>; 790 #address-cells = <2>; 791 #size-cells = <2>; 792 ranges; 793 status = "disabled"; 794 795 i2c0: i2c@4a80000 { 796 compatible = "qcom,geni-i2c"; 797 reg = <0x0 0x04a80000 0x0 0x4000>; 798 clock-names = "se"; 799 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 800 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 801 pinctrl-names = "default"; 802 pinctrl-0 = <&qup_i2c0_default>; 803 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 804 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 805 dma-names = "tx", "rx"; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 status = "disabled"; 809 }; 810 811 spi0: spi@4a80000 { 812 compatible = "qcom,geni-spi"; 813 reg = <0x0 0x04a80000 0x0 0x4000>; 814 clock-names = "se"; 815 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 816 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 817 pinctrl-names = "default"; 818 pinctrl-0 = <&qup_spi0_default>; 819 power-domains = <&rpmpd SM6375_VDDCX>; 820 operating-points-v2 = <&qup_opp_table>; 821 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 822 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 823 dma-names = "tx", "rx"; 824 #address-cells = <1>; 825 #size-cells = <0>; 826 status = "disabled"; 827 }; 828 829 i2c1: i2c@4a84000 { 830 compatible = "qcom,geni-i2c"; 831 reg = <0x0 0x04a84000 0x0 0x4000>; 832 clock-names = "se"; 833 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 834 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 835 pinctrl-names = "default"; 836 pinctrl-0 = <&qup_i2c1_default>; 837 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 838 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 839 dma-names = "tx", "rx"; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 status = "disabled"; 843 }; 844 845 spi1: spi@4a84000 { 846 compatible = "qcom,geni-spi"; 847 reg = <0x0 0x04a84000 0x0 0x4000>; 848 clock-names = "se"; 849 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 850 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 851 power-domains = <&rpmpd SM6375_VDDCX>; 852 operating-points-v2 = <&qup_opp_table>; 853 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 854 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 855 dma-names = "tx", "rx"; 856 #address-cells = <1>; 857 #size-cells = <0>; 858 status = "disabled"; 859 }; 860 861 i2c2: i2c@4a88000 { 862 compatible = "qcom,geni-i2c"; 863 reg = <0x0 0x04a88000 0x0 0x4000>; 864 clock-names = "se"; 865 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 866 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 867 pinctrl-names = "default"; 868 pinctrl-0 = <&qup_i2c2_default>; 869 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 870 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 871 dma-names = "tx", "rx"; 872 #address-cells = <1>; 873 #size-cells = <0>; 874 status = "disabled"; 875 }; 876 877 spi2: spi@4a88000 { 878 compatible = "qcom,geni-spi"; 879 reg = <0x0 0x04a88000 0x0 0x4000>; 880 clock-names = "se"; 881 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 882 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 883 power-domains = <&rpmpd SM6375_VDDCX>; 884 operating-points-v2 = <&qup_opp_table>; 885 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 886 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 887 dma-names = "tx", "rx"; 888 #address-cells = <1>; 889 #size-cells = <0>; 890 status = "disabled"; 891 }; 892 893 /* 894 * As per GCC, QUP3/4/5/11 also exist, but are not even defined downstream. 895 * There is a comment in the included DTSI of another SoC saying that they 896 * are not "bolled out" (probably meaning not routed to solder balls) 897 * TLMM driver however, suggests there are as many as 15 QUPs in total! 898 * Most of which don't even have pin configurations for.. Sad stuff! 899 */ 900 }; 901 902 gpi_dma1: dma-controller@4c00000 { 903 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; 904 reg = <0 0x04c00000 0 0x60000>; 905 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 915 dma-channels = <10>; 916 dma-channel-mask = <0x1f>; 917 iommus = <&apps_smmu 0xd6 0x0>; 918 #dma-cells = <3>; 919 status = "disabled"; 920 }; 921 922 qupv3_id_1: geniqup@4cc0000 { 923 compatible = "qcom,geni-se-qup"; 924 reg = <0x0 0x04cc0000 0x0 0x2000>; 925 clock-names = "m-ahb", "s-ahb"; 926 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 927 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 928 iommus = <&apps_smmu 0xc3 0x0>; 929 #address-cells = <2>; 930 #size-cells = <2>; 931 ranges; 932 status = "disabled"; 933 934 i2c6: i2c@4c80000 { 935 compatible = "qcom,geni-i2c"; 936 reg = <0x0 0x04c80000 0x0 0x4000>; 937 clock-names = "se"; 938 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 939 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; 940 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 941 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 942 dma-names = "tx", "rx"; 943 #address-cells = <1>; 944 #size-cells = <0>; 945 status = "disabled"; 946 }; 947 948 spi6: spi@4c80000 { 949 compatible = "qcom,geni-spi"; 950 reg = <0x0 0x04c80000 0x0 0x4000>; 951 clock-names = "se"; 952 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 953 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; 954 power-domains = <&rpmpd SM6375_VDDCX>; 955 operating-points-v2 = <&qup_opp_table>; 956 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 957 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 958 dma-names = "tx", "rx"; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 status = "disabled"; 962 }; 963 964 i2c7: i2c@4c84000 { 965 compatible = "qcom,geni-i2c"; 966 reg = <0x0 0x04c84000 0x0 0x4000>; 967 clock-names = "se"; 968 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 969 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 970 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 971 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 972 dma-names = "tx", "rx"; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 status = "disabled"; 976 }; 977 978 spi7: spi@4c84000 { 979 compatible = "qcom,geni-spi"; 980 reg = <0x0 0x04c84000 0x0 0x4000>; 981 clock-names = "se"; 982 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 983 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 984 power-domains = <&rpmpd SM6375_VDDCX>; 985 operating-points-v2 = <&qup_opp_table>; 986 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 987 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 988 dma-names = "tx", "rx"; 989 #address-cells = <1>; 990 #size-cells = <0>; 991 status = "disabled"; 992 }; 993 994 i2c8: i2c@4c88000 { 995 compatible = "qcom,geni-i2c"; 996 reg = <0x0 0x04c88000 0x0 0x4000>; 997 clock-names = "se"; 998 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 999 interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1000 pinctrl-names = "default"; 1001 pinctrl-0 = <&qup_i2c8_default>; 1002 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1003 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1004 dma-names = "tx", "rx"; 1005 #address-cells = <1>; 1006 #size-cells = <0>; 1007 status = "disabled"; 1008 }; 1009 1010 spi8: spi@4c88000 { 1011 compatible = "qcom,geni-spi"; 1012 reg = <0x0 0x04c88000 0x0 0x4000>; 1013 clock-names = "se"; 1014 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1015 interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1016 power-domains = <&rpmpd SM6375_VDDCX>; 1017 operating-points-v2 = <&qup_opp_table>; 1018 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1019 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1020 dma-names = "tx", "rx"; 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 status = "disabled"; 1024 }; 1025 1026 i2c9: i2c@4c8c000 { 1027 compatible = "qcom,geni-i2c"; 1028 reg = <0x0 0x04c8c000 0x0 0x4000>; 1029 clock-names = "se"; 1030 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1031 interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>; 1032 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1033 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1034 dma-names = "tx", "rx"; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 status = "disabled"; 1038 }; 1039 1040 spi9: spi@4c8c000 { 1041 compatible = "qcom,geni-spi"; 1042 reg = <0x0 0x04c8c000 0x0 0x4000>; 1043 clock-names = "se"; 1044 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1045 interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>; 1046 power-domains = <&rpmpd SM6375_VDDCX>; 1047 operating-points-v2 = <&qup_opp_table>; 1048 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1049 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1050 dma-names = "tx", "rx"; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 status = "disabled"; 1054 }; 1055 1056 i2c10: i2c@4c90000 { 1057 compatible = "qcom,geni-i2c"; 1058 reg = <0x0 0x04c90000 0x0 0x4000>; 1059 clock-names = "se"; 1060 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1061 interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>; 1062 pinctrl-names = "default"; 1063 pinctrl-0 = <&qup_i2c10_default>; 1064 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1065 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1066 dma-names = "tx", "rx"; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 status = "disabled"; 1070 }; 1071 1072 spi10: spi@4c90000 { 1073 compatible = "qcom,geni-spi"; 1074 reg = <0x0 0x04c90000 0x0 0x4000>; 1075 clock-names = "se"; 1076 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1077 interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>; 1078 power-domains = <&rpmpd SM6375_VDDCX>; 1079 operating-points-v2 = <&qup_opp_table>; 1080 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1081 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1082 dma-names = "tx", "rx"; 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 status = "disabled"; 1086 }; 1087 }; 1088 1089 usb_1: usb@4ef8800 { 1090 compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; 1091 reg = <0 0x04ef8800 0 0x400>; 1092 1093 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1094 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1095 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1096 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1097 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1098 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1099 clock-names = "cfg_noc", 1100 "core", 1101 "iface", 1102 "sleep", 1103 "mock_utmi", 1104 "xo"; 1105 1106 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1107 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1108 assigned-clock-rates = <19200000>, <133333333>; 1109 1110 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1114 interrupt-names = "hs_phy_irq", 1115 "ss_phy_irq", 1116 "dm_hs_phy_irq", 1117 "dp_hs_phy_irq"; 1118 1119 power-domains = <&gcc USB30_PRIM_GDSC>; 1120 1121 resets = <&gcc GCC_USB30_PRIM_BCR>; 1122 1123 /* 1124 * This property is there to allow USB2 to work, as 1125 * USB3 is not implemented yet - (re)move it when 1126 * proper support is in place. 1127 */ 1128 qcom,select-utmi-as-pipe-clk; 1129 1130 #address-cells = <2>; 1131 #size-cells = <2>; 1132 ranges; 1133 1134 status = "disabled"; 1135 1136 usb_1_dwc3: usb@4e00000 { 1137 compatible = "snps,dwc3"; 1138 reg = <0 0x04e00000 0 0xcd00>; 1139 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1140 maximum-speed = "high-speed"; 1141 phys = <&usb_1_hsphy>; 1142 phy-names = "usb2-phy"; 1143 iommus = <&apps_smmu 0xe0 0x0>; 1144 1145 /* Yes, this impl *does* have an unfunny number of quirks.. */ 1146 snps,hird-threshold = /bits/ 8 <0x10>; 1147 snps,usb2-gadget-lpm-disable; 1148 snps,dis_u2_susphy_quirk; 1149 snps,is-utmi-l1-suspend; 1150 snps,dis-u1-entry-quirk; 1151 snps,dis-u2-entry-quirk; 1152 snps,usb3_lpm_capable; 1153 snps,has-lpm-erratum; 1154 tx-fifo-resize; 1155 }; 1156 }; 1157 1158 remoteproc_adsp: remoteproc@a400000 { 1159 compatible = "qcom,sm6375-adsp-pas"; 1160 reg = <0 0x0a400000 0 0x100>; 1161 1162 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1163 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1164 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1165 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1166 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1167 interrupt-names = "wdog", "fatal", "ready", 1168 "handover", "stop-ack"; 1169 1170 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1171 clock-names = "xo"; 1172 1173 power-domains = <&rpmpd SM6375_VDD_LPI_CX>, 1174 <&rpmpd SM6375_VDD_LPI_MX>; 1175 power-domain-names = "lcx", "lmx"; 1176 1177 memory-region = <&pil_adsp_mem>; 1178 1179 qcom,smem-states = <&smp2p_adsp_out 0>; 1180 qcom,smem-state-names = "stop"; 1181 1182 status = "disabled"; 1183 1184 glink-edge { 1185 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1186 IPCC_MPROC_SIGNAL_GLINK_QMP 1187 IRQ_TYPE_EDGE_RISING>; 1188 mboxes = <&ipcc IPCC_CLIENT_LPASS 1189 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1190 1191 label = "lpass"; 1192 qcom,remote-pid = <2>; 1193 }; 1194 }; 1195 1196 remoteproc_cdsp: remoteproc@b000000 { 1197 compatible = "qcom,sm6375-cdsp-pas"; 1198 reg = <0x0 0x0b000000 0x0 0x100000>; 1199 1200 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 1201 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1202 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1203 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1204 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1205 interrupt-names = "wdog", "fatal", "ready", 1206 "handover", "stop-ack"; 1207 1208 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1209 clock-names = "xo"; 1210 1211 power-domains = <&rpmpd SM6375_VDDCX>; 1212 1213 memory-region = <&pil_cdsp_mem>; 1214 1215 qcom,smem-states = <&smp2p_cdsp_out 0>; 1216 qcom,smem-state-names = "stop"; 1217 1218 status = "disabled"; 1219 1220 glink-edge { 1221 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1222 IPCC_MPROC_SIGNAL_GLINK_QMP 1223 IRQ_TYPE_EDGE_RISING>; 1224 mboxes = <&ipcc IPCC_CLIENT_CDSP 1225 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1226 label = "cdsp"; 1227 qcom,remote-pid = <5>; 1228 }; 1229 }; 1230 1231 apps_smmu: iommu@c600000 { 1232 compatible = "qcom,sm6375-smmu-500", "arm,mmu-500"; 1233 reg = <0 0x0c600000 0 0x100000>; 1234 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1259 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1261 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1262 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1278 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1279 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1280 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1281 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1282 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1283 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1284 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1285 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1286 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1287 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1288 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1290 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1299 1300 power-domains = <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC>, 1301 <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC>, 1302 <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; 1303 #global-interrupts = <1>; 1304 #iommu-cells = <2>; 1305 }; 1306 1307 intc: interrupt-controller@f200000 { 1308 compatible = "arm,gic-v3"; 1309 reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */ 1310 <0x0 0x0f240000 0x0 0x100000>; /* GICR * 8 */ 1311 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 1312 #redistributor-regions = <1>; 1313 #interrupt-cells = <3>; 1314 redistributor-stride = <0 0x20000>; 1315 interrupt-controller; 1316 }; 1317 1318 timer@f420000 { 1319 compatible = "arm,armv7-timer-mem"; 1320 reg = <0 0x0f420000 0 0x1000>; 1321 ranges = <0 0 0 0x20000000>; 1322 #address-cells = <1>; 1323 #size-cells = <1>; 1324 1325 frame@f421000 { 1326 reg = <0x0f421000 0x1000>, <0x0f422000 0x1000>; 1327 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1329 frame-number = <0>; 1330 }; 1331 1332 frame@f423000 { 1333 reg = <0x0f243000 0x1000>; 1334 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1335 frame-number = <1>; 1336 status = "disabled"; 1337 }; 1338 1339 frame@f425000 { 1340 reg = <0x0f425000 0x1000>; 1341 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1342 frame-number = <2>; 1343 status = "disabled"; 1344 }; 1345 1346 frame@f427000 { 1347 reg = <0x0f427000 0x1000>; 1348 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1349 frame-number = <3>; 1350 status = "disabled"; 1351 }; 1352 1353 frame@f429000 { 1354 reg = <0x0f429000 0x1000>; 1355 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1356 frame-number = <4>; 1357 status = "disabled"; 1358 }; 1359 1360 frame@f42b000 { 1361 reg = <0x0f42b000 0x1000>; 1362 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1363 frame-number = <5>; 1364 status = "disabled"; 1365 }; 1366 1367 frame@f42d000 { 1368 reg = <0x0f42d000 0x1000>; 1369 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1370 frame-number = <6>; 1371 status = "disabled"; 1372 }; 1373 }; 1374 1375 cpufreq_hw: cpufreq@fd91000 { 1376 compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss"; 1377 reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>; 1378 reg-names = "freq-domain0", "freq-domain1"; 1379 1380 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1381 clock-names = "xo", "alternate"; 1382 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1384 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; 1385 #freq-domain-cells = <1>; 1386 }; 1387 }; 1388 1389 timer { 1390 compatible = "arm,armv8-timer"; 1391 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1392 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1393 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1394 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1395 }; 1396}; 1397