1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/clock/qcom,sm6375-gcc.h> 8#include <dt-bindings/dma/qcom-gpi.h> 9#include <dt-bindings/firmware/qcom,scm.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/mailbox/qcom-ipcc.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { }; 21 22 clocks { 23 xo_board_clk: xo-board-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 clock-frequency = <32000>; 31 #clock-cells = <0>; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <2>; 37 #size-cells = <0>; 38 39 CPU0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "qcom,kryo660"; 42 reg = <0x0 0x0>; 43 clocks = <&cpufreq_hw 0>; 44 enable-method = "psci"; 45 next-level-cache = <&L2_0>; 46 qcom,freq-domain = <&cpufreq_hw 0>; 47 power-domains = <&CPU_PD0>; 48 power-domain-names = "psci"; 49 #cooling-cells = <2>; 50 L2_0: l2-cache { 51 compatible = "cache"; 52 next-level-cache = <&L3_0>; 53 L3_0: l3-cache { 54 compatible = "cache"; 55 }; 56 }; 57 }; 58 59 CPU1: cpu@100 { 60 device_type = "cpu"; 61 compatible = "qcom,kryo660"; 62 reg = <0x0 0x100>; 63 clocks = <&cpufreq_hw 0>; 64 enable-method = "psci"; 65 next-level-cache = <&L2_100>; 66 qcom,freq-domain = <&cpufreq_hw 0>; 67 power-domains = <&CPU_PD1>; 68 power-domain-names = "psci"; 69 #cooling-cells = <2>; 70 L2_100: l2-cache { 71 compatible = "cache"; 72 next-level-cache = <&L3_0>; 73 }; 74 }; 75 76 CPU2: cpu@200 { 77 device_type = "cpu"; 78 compatible = "qcom,kryo660"; 79 reg = <0x0 0x200>; 80 clocks = <&cpufreq_hw 0>; 81 enable-method = "psci"; 82 next-level-cache = <&L2_200>; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 power-domains = <&CPU_PD2>; 85 power-domain-names = "psci"; 86 #cooling-cells = <2>; 87 L2_200: l2-cache { 88 compatible = "cache"; 89 next-level-cache = <&L3_0>; 90 }; 91 }; 92 93 CPU3: cpu@300 { 94 device_type = "cpu"; 95 compatible = "qcom,kryo660"; 96 reg = <0x0 0x300>; 97 clocks = <&cpufreq_hw 0>; 98 enable-method = "psci"; 99 next-level-cache = <&L2_300>; 100 qcom,freq-domain = <&cpufreq_hw 0>; 101 power-domains = <&CPU_PD3>; 102 power-domain-names = "psci"; 103 #cooling-cells = <2>; 104 L2_300: l2-cache { 105 compatible = "cache"; 106 next-level-cache = <&L3_0>; 107 }; 108 }; 109 110 CPU4: cpu@400 { 111 device_type = "cpu"; 112 compatible = "qcom,kryo660"; 113 reg = <0x0 0x400>; 114 clocks = <&cpufreq_hw 0>; 115 enable-method = "psci"; 116 next-level-cache = <&L2_400>; 117 qcom,freq-domain = <&cpufreq_hw 0>; 118 power-domains = <&CPU_PD4>; 119 power-domain-names = "psci"; 120 #cooling-cells = <2>; 121 L2_400: l2-cache { 122 compatible = "cache"; 123 next-level-cache = <&L3_0>; 124 }; 125 }; 126 127 CPU5: cpu@500 { 128 device_type = "cpu"; 129 compatible = "qcom,kryo660"; 130 reg = <0x0 0x500>; 131 clocks = <&cpufreq_hw 0>; 132 enable-method = "psci"; 133 next-level-cache = <&L2_500>; 134 qcom,freq-domain = <&cpufreq_hw 0>; 135 power-domains = <&CPU_PD5>; 136 power-domain-names = "psci"; 137 #cooling-cells = <2>; 138 L2_500: l2-cache { 139 compatible = "cache"; 140 next-level-cache = <&L3_0>; 141 }; 142 }; 143 144 CPU6: cpu@600 { 145 device_type = "cpu"; 146 compatible = "qcom,kryo660"; 147 reg = <0x0 0x600>; 148 clocks = <&cpufreq_hw 1>; 149 enable-method = "psci"; 150 next-level-cache = <&L2_600>; 151 qcom,freq-domain = <&cpufreq_hw 1>; 152 power-domains = <&CPU_PD6>; 153 power-domain-names = "psci"; 154 #cooling-cells = <2>; 155 L2_600: l2-cache { 156 compatible = "cache"; 157 next-level-cache = <&L3_0>; 158 }; 159 }; 160 161 CPU7: cpu@700 { 162 device_type = "cpu"; 163 compatible = "qcom,kryo660"; 164 reg = <0x0 0x700>; 165 clocks = <&cpufreq_hw 1>; 166 enable-method = "psci"; 167 next-level-cache = <&L2_700>; 168 qcom,freq-domain = <&cpufreq_hw 1>; 169 power-domains = <&CPU_PD7>; 170 power-domain-names = "psci"; 171 #cooling-cells = <2>; 172 L2_700: l2-cache { 173 compatible = "cache"; 174 next-level-cache = <&L3_0>; 175 }; 176 }; 177 178 cpu-map { 179 cluster0 { 180 core0 { 181 cpu = <&CPU0>; 182 }; 183 184 core1 { 185 cpu = <&CPU1>; 186 }; 187 188 core2 { 189 cpu = <&CPU2>; 190 }; 191 192 core3 { 193 cpu = <&CPU3>; 194 }; 195 196 core4 { 197 cpu = <&CPU4>; 198 }; 199 200 core5 { 201 cpu = <&CPU5>; 202 }; 203 204 core6 { 205 cpu = <&CPU6>; 206 }; 207 208 core7 { 209 cpu = <&CPU7>; 210 }; 211 }; 212 }; 213 214 idle-states { 215 entry-method = "psci"; 216 217 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 218 compatible = "arm,idle-state"; 219 idle-state-name = "silver-power-collapse"; 220 arm,psci-suspend-param = <0x40000003>; 221 entry-latency-us = <549>; 222 exit-latency-us = <901>; 223 min-residency-us = <1774>; 224 local-timer-stop; 225 }; 226 227 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 228 compatible = "arm,idle-state"; 229 idle-state-name = "silver-rail-power-collapse"; 230 arm,psci-suspend-param = <0x40000004>; 231 entry-latency-us = <702>; 232 exit-latency-us = <915>; 233 min-residency-us = <4001>; 234 local-timer-stop; 235 }; 236 237 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 238 compatible = "arm,idle-state"; 239 idle-state-name = "gold-power-collapse"; 240 arm,psci-suspend-param = <0x40000003>; 241 entry-latency-us = <523>; 242 exit-latency-us = <1244>; 243 min-residency-us = <2207>; 244 local-timer-stop; 245 }; 246 247 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 248 compatible = "arm,idle-state"; 249 idle-state-name = "gold-rail-power-collapse"; 250 arm,psci-suspend-param = <0x40000004>; 251 entry-latency-us = <526>; 252 exit-latency-us = <1854>; 253 min-residency-us = <5555>; 254 local-timer-stop; 255 }; 256 }; 257 258 domain-idle-states { 259 CLUSTER_SLEEP_0: cluster-sleep-0 { 260 compatible = "domain-idle-state"; 261 arm,psci-suspend-param = <0x41000044>; 262 entry-latency-us = <2752>; 263 exit-latency-us = <3048>; 264 min-residency-us = <6118>; 265 }; 266 }; 267 }; 268 269 firmware { 270 scm { 271 compatible = "qcom,scm-sm6375", "qcom,scm"; 272 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 273 clock-names = "core"; 274 #reset-cells = <1>; 275 }; 276 }; 277 278 memory@80000000 { 279 device_type = "memory"; 280 /* We expect the bootloader to fill in the size */ 281 reg = <0x0 0x80000000 0x0 0x0>; 282 }; 283 284 pmu { 285 compatible = "arm,armv8-pmuv3"; 286 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 287 }; 288 289 psci { 290 compatible = "arm,psci-1.0"; 291 method = "smc"; 292 293 CPU_PD0: power-domain-cpu0 { 294 #power-domain-cells = <0>; 295 power-domains = <&CLUSTER_PD>; 296 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 297 }; 298 299 CPU_PD1: power-domain-cpu1 { 300 #power-domain-cells = <0>; 301 power-domains = <&CLUSTER_PD>; 302 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 303 }; 304 305 CPU_PD2: power-domain-cpu2 { 306 #power-domain-cells = <0>; 307 power-domains = <&CLUSTER_PD>; 308 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 309 }; 310 311 CPU_PD3: power-domain-cpu3 { 312 #power-domain-cells = <0>; 313 power-domains = <&CLUSTER_PD>; 314 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 315 }; 316 317 CPU_PD4: power-domain-cpu4 { 318 #power-domain-cells = <0>; 319 power-domains = <&CLUSTER_PD>; 320 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 321 }; 322 323 CPU_PD5: power-domain-cpu5 { 324 #power-domain-cells = <0>; 325 power-domains = <&CLUSTER_PD>; 326 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 327 }; 328 329 CPU_PD6: power-domain-cpu6 { 330 #power-domain-cells = <0>; 331 power-domains = <&CLUSTER_PD>; 332 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 333 }; 334 335 CPU_PD7: power-domain-cpu7 { 336 #power-domain-cells = <0>; 337 power-domains = <&CLUSTER_PD>; 338 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 339 }; 340 341 CLUSTER_PD: power-domain-cpu-cluster0 { 342 #power-domain-cells = <0>; 343 domain-idle-states = <&CLUSTER_SLEEP_0>; 344 }; 345 }; 346 347 qup_opp_table: opp-table-qup { 348 compatible = "operating-points-v2"; 349 350 opp-75000000 { 351 opp-hz = /bits/ 64 <75000000>; 352 required-opps = <&rpmpd_opp_low_svs>; 353 }; 354 355 opp-100000000 { 356 opp-hz = /bits/ 64 <100000000>; 357 required-opps = <&rpmpd_opp_svs>; 358 }; 359 360 opp-128000000 { 361 opp-hz = /bits/ 64 <128000000>; 362 required-opps = <&rpmpd_opp_nom>; 363 }; 364 }; 365 366 reserved_memory: reserved-memory { 367 #address-cells = <2>; 368 #size-cells = <2>; 369 ranges; 370 371 hyp_mem: hypervisor@80000000 { 372 reg = <0 0x80000000 0 0x600000>; 373 no-map; 374 }; 375 376 xbl_aop_mem: xbl-aop@80700000 { 377 reg = <0 0x80700000 0 0x100000>; 378 no-map; 379 }; 380 381 reserved_xbl_uefi: xbl-uefi-res@80880000 { 382 reg = <0 0x80880000 0 0x14000>; 383 no-map; 384 }; 385 386 smem_mem: smem@80900000 { 387 compatible = "qcom,smem"; 388 reg = <0 0x80900000 0 0x200000>; 389 hwlocks = <&tcsr_mutex 3>; 390 no-map; 391 }; 392 393 fw_mem: fw@80b00000 { 394 reg = <0 0x80b00000 0 0x100000>; 395 no-map; 396 }; 397 398 cdsp_secure_heap_mem: cdsp-sec-heap@80c00000 { 399 reg = <0 0x80c00000 0 0x1e00000>; 400 no-map; 401 }; 402 403 dfps_data_mem: dpfs-data@85e00000 { 404 reg = <0 0x85e00000 0 0x100000>; 405 no-map; 406 }; 407 408 pil_wlan_mem: pil-wlan@86500000 { 409 reg = <0 0x86500000 0 0x200000>; 410 no-map; 411 }; 412 413 pil_adsp_mem: pil-adsp@86700000 { 414 reg = <0 0x86700000 0 0x2000000>; 415 no-map; 416 }; 417 418 pil_cdsp_mem: pil-cdsp@88700000 { 419 reg = <0 0x88700000 0 0x1e00000>; 420 no-map; 421 }; 422 423 pil_video_mem: pil-video@8a500000 { 424 reg = <0 0x8a500000 0 0x500000>; 425 no-map; 426 }; 427 428 pil_ipa_fw_mem: pil-ipa-fw@8aa00000 { 429 reg = <0 0x8aa00000 0 0x10000>; 430 no-map; 431 }; 432 433 pil_ipa_gsi_mem: pil-ipa-gsi@8aa10000 { 434 reg = <0 0x8aa10000 0 0xa000>; 435 no-map; 436 }; 437 438 pil_gpu_micro_code_mem: pil-gpu-ucode@8aa1a000 { 439 reg = <0 0x8aa1a000 0 0x2000>; 440 no-map; 441 }; 442 443 pil_mpss_wlan_mem: pil-mpss-wlan@8b800000 { 444 reg = <0 0x8b800000 0 0x10000000>; 445 no-map; 446 }; 447 448 removed_mem: removed@c0000000 { 449 reg = <0 0xc0000000 0 0x5100000>; 450 no-map; 451 }; 452 453 rmtfs_mem: rmtfs@f3900000 { 454 compatible = "qcom,rmtfs-mem"; 455 reg = <0 0xf3900000 0 0x280000>; 456 no-map; 457 458 qcom,client-id = <1>; 459 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 460 }; 461 462 debug_mem: debug@ffb00000 { 463 reg = <0 0xffb00000 0 0xc0000>; 464 no-map; 465 }; 466 467 last_log_mem: lastlog@ffbc0000 { 468 reg = <0 0xffbc0000 0 0x80000>; 469 no-map; 470 }; 471 472 cmdline_region: cmdline@ffd00000 { 473 reg = <0 0xffd00000 0 0x1000>; 474 no-map; 475 }; 476 }; 477 478 rpm-glink { 479 compatible = "qcom,glink-rpm"; 480 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 481 IPCC_MPROC_SIGNAL_GLINK_QMP 482 IRQ_TYPE_EDGE_RISING>; 483 qcom,rpm-msg-ram = <&rpm_msg_ram>; 484 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 485 486 rpm_requests: rpm-requests { 487 compatible = "qcom,rpm-sm6375"; 488 qcom,glink-channels = "rpm_requests"; 489 490 rpmcc: clock-controller { 491 compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc"; 492 clocks = <&xo_board_clk>; 493 clock-names = "xo"; 494 #clock-cells = <1>; 495 }; 496 497 rpmpd: power-controller { 498 compatible = "qcom,sm6375-rpmpd"; 499 #power-domain-cells = <1>; 500 operating-points-v2 = <&rpmpd_opp_table>; 501 502 rpmpd_opp_table: opp-table { 503 compatible = "operating-points-v2"; 504 505 rpmpd_opp_ret: opp1 { 506 opp-level = <RPM_SMD_LEVEL_RETENTION>; 507 }; 508 509 rpmpd_opp_min_svs: opp2 { 510 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 511 }; 512 513 rpmpd_opp_low_svs: opp3 { 514 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 515 }; 516 517 rpmpd_opp_svs: opp4 { 518 opp-level = <RPM_SMD_LEVEL_SVS>; 519 }; 520 521 rpmpd_opp_svs_plus: opp5 { 522 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 523 }; 524 525 rpmpd_opp_nom: opp6 { 526 opp-level = <RPM_SMD_LEVEL_NOM>; 527 }; 528 529 rpmpd_opp_nom_plus: opp7 { 530 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 531 }; 532 533 rpmpd_opp_turbo: opp8 { 534 opp-level = <RPM_SMD_LEVEL_TURBO>; 535 }; 536 537 rpmpd_opp_turbo_no_cpr: opp9 { 538 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 539 }; 540 }; 541 }; 542 }; 543 }; 544 545 smp2p-adsp { 546 compatible = "qcom,smp2p"; 547 qcom,smem = <443>, <429>; 548 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 549 IPCC_MPROC_SIGNAL_SMP2P 550 IRQ_TYPE_EDGE_RISING>; 551 mboxes = <&ipcc IPCC_CLIENT_LPASS 552 IPCC_MPROC_SIGNAL_SMP2P>; 553 554 qcom,local-pid = <0>; 555 qcom,remote-pid = <2>; 556 557 smp2p_adsp_out: master-kernel { 558 qcom,entry-name = "master-kernel"; 559 #qcom,smem-state-cells = <1>; 560 }; 561 562 smp2p_adsp_in: slave-kernel { 563 qcom,entry-name = "slave-kernel"; 564 interrupt-controller; 565 #interrupt-cells = <2>; 566 }; 567 }; 568 569 smp2p-cdsp { 570 compatible = "qcom,smp2p"; 571 qcom,smem = <94>, <432>; 572 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 573 IPCC_MPROC_SIGNAL_SMP2P 574 IRQ_TYPE_EDGE_RISING>; 575 mboxes = <&ipcc IPCC_CLIENT_CDSP 576 IPCC_MPROC_SIGNAL_SMP2P>; 577 578 qcom,local-pid = <0>; 579 qcom,remote-pid = <5>; 580 581 smp2p_cdsp_out: master-kernel { 582 qcom,entry-name = "master-kernel"; 583 #qcom,smem-state-cells = <1>; 584 }; 585 586 smp2p_cdsp_in: slave-kernel { 587 qcom,entry-name = "slave-kernel"; 588 interrupt-controller; 589 #interrupt-cells = <2>; 590 }; 591 }; 592 593 smp2p-modem { 594 compatible = "qcom,smp2p"; 595 qcom,smem = <435>, <428>; 596 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 597 IPCC_MPROC_SIGNAL_SMP2P 598 IRQ_TYPE_EDGE_RISING>; 599 mboxes = <&ipcc IPCC_CLIENT_MPSS 600 IPCC_MPROC_SIGNAL_SMP2P>; 601 602 qcom,local-pid = <0>; 603 qcom,remote-pid = <1>; 604 605 smp2p_modem_out: master-kernel { 606 qcom,entry-name = "master-kernel"; 607 #qcom,smem-state-cells = <1>; 608 }; 609 610 smp2p_modem_in: slave-kernel { 611 qcom,entry-name = "slave-kernel"; 612 interrupt-controller; 613 #interrupt-cells = <2>; 614 }; 615 616 ipa_smp2p_out: ipa-ap-to-modem { 617 qcom,entry-name = "ipa"; 618 #qcom,smem-state-cells = <1>; 619 }; 620 621 ipa_smp2p_in: ipa-modem-to-ap { 622 qcom,entry-name = "ipa"; 623 interrupt-controller; 624 #interrupt-cells = <2>; 625 }; 626 627 wlan_smp2p_in: wlan-wpss-to-ap { 628 qcom,entry-name = "wlan"; 629 interrupt-controller; 630 #interrupt-cells = <2>; 631 }; 632 }; 633 634 soc: soc@0 { 635 #address-cells = <2>; 636 #size-cells = <2>; 637 ranges = <0 0 0 0 0x10 0>; 638 dma-ranges = <0 0 0 0 0x10 0>; 639 compatible = "simple-bus"; 640 641 ipcc: mailbox@208000 { 642 compatible = "qcom,sm6375-ipcc", "qcom,ipcc"; 643 reg = <0 0x00208000 0 0x1000>; 644 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 645 interrupt-controller; 646 #interrupt-cells = <3>; 647 #mbox-cells = <2>; 648 }; 649 650 tcsr_mutex: hwlock@340000 { 651 compatible = "qcom,tcsr-mutex"; 652 reg = <0x0 0x00340000 0x0 0x40000>; 653 #hwlock-cells = <1>; 654 }; 655 656 tlmm: pinctrl@500000 { 657 compatible = "qcom,sm6375-tlmm"; 658 reg = <0 0x00500000 0 0x800000>; 659 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 660 gpio-ranges = <&tlmm 0 0 157>; 661 /* TODO: Hook up MPM as wakeup-parent when it's there */ 662 interrupt-controller; 663 gpio-controller; 664 #interrupt-cells = <2>; 665 #gpio-cells = <2>; 666 667 sdc2_off_state: sdc2-off-state { 668 clk-pins { 669 pins = "sdc2_clk"; 670 drive-strength = <2>; 671 bias-disable; 672 }; 673 674 cmd-pins { 675 pins = "sdc2_cmd"; 676 drive-strength = <2>; 677 bias-pull-up; 678 }; 679 680 data-pins { 681 pins = "sdc2_data"; 682 drive-strength = <2>; 683 bias-pull-up; 684 }; 685 }; 686 687 sdc2_on_state: sdc2-on-state { 688 clk-pins { 689 pins = "sdc2_clk"; 690 drive-strength = <16>; 691 bias-disable; 692 }; 693 694 cmd-pins { 695 pins = "sdc2_cmd"; 696 drive-strength = <10>; 697 bias-pull-up; 698 }; 699 700 data-pins { 701 pins = "sdc2_data"; 702 drive-strength = <10>; 703 bias-pull-up; 704 }; 705 }; 706 707 qup_i2c0_default: qup-i2c0-default-state { 708 pins = "gpio0", "gpio1"; 709 function = "qup00"; 710 drive-strength = <2>; 711 bias-pull-up; 712 }; 713 714 qup_i2c1_default: qup-i2c1-default-state { 715 pins = "gpio61", "gpio62"; 716 function = "qup01"; 717 drive-strength = <2>; 718 bias-pull-up; 719 }; 720 721 qup_i2c2_default: qup-i2c2-default-state { 722 pins = "gpio45", "gpio46"; 723 function = "qup02"; 724 drive-strength = <2>; 725 bias-pull-up; 726 }; 727 728 qup_i2c8_default: qup-i2c8-default-state { 729 pins = "gpio19", "gpio20"; 730 /* TLMM, GCC and vendor DT all have different indices.. */ 731 function = "qup12"; 732 drive-strength = <2>; 733 bias-pull-up; 734 }; 735 736 qup_i2c10_default: qup-i2c10-default-state { 737 pins = "gpio4", "gpio5"; 738 function = "qup10"; 739 drive-strength = <2>; 740 bias-pull-up; 741 }; 742 743 qup_spi0_default: qup-spi0-default-state { 744 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 745 function = "qup00"; 746 drive-strength = <6>; 747 bias-disable; 748 }; 749 }; 750 751 gcc: clock-controller@1400000 { 752 compatible = "qcom,sm6375-gcc"; 753 reg = <0 0x01400000 0 0x1f0000>; 754 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 755 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 756 <&sleep_clk>; 757 #power-domain-cells = <1>; 758 #clock-cells = <1>; 759 #reset-cells = <1>; 760 }; 761 762 usb_1_hsphy: phy@162b000 { 763 compatible = "qcom,sm6375-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; 764 reg = <0 0x0162b000 0 0x400>; 765 766 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 767 clock-names = "ref"; 768 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 769 #phy-cells = <0>; 770 771 status = "disabled"; 772 }; 773 774 spmi_bus: spmi@1c40000 { 775 compatible = "qcom,spmi-pmic-arb"; 776 reg = <0 0x01c40000 0 0x1100>, 777 <0 0x01e00000 0 0x2000000>, 778 <0 0x03e00000 0 0x100000>, 779 <0 0x03f00000 0 0xa0000>, 780 <0 0x01c0a000 0 0x26000>; 781 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 782 interrupt-names = "periph_irq"; 783 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 784 qcom,ee = <0>; 785 qcom,channel = <0>; 786 #address-cells = <2>; 787 #size-cells = <0>; 788 interrupt-controller; 789 #interrupt-cells = <4>; 790 }; 791 792 tsens0: thermal-sensor@4411000 { 793 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2"; 794 reg = <0 0x04411000 0 0x140>, /* TM */ 795 <0 0x04410000 0 0x20>; /* SROT */ 796 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 798 interrupt-names = "uplow", "critical"; 799 #thermal-sensor-cells = <1>; 800 #qcom,sensors = <15>; 801 }; 802 803 tsens1: thermal-sensor@4413000 { 804 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2"; 805 reg = <0 0x04413000 0 0x140>, /* TM */ 806 <0 0x04412000 0 0x20>; /* SROT */ 807 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 809 interrupt-names = "uplow", "critical"; 810 #thermal-sensor-cells = <1>; 811 #qcom,sensors = <11>; 812 }; 813 814 rpm_msg_ram: sram@45f0000 { 815 compatible = "qcom,rpm-msg-ram"; 816 reg = <0 0x045f0000 0 0x7000>; 817 }; 818 819 sram@4690000 { 820 compatible = "qcom,rpm-stats"; 821 reg = <0 0x04690000 0 0x400>; 822 }; 823 824 sdhc_2: mmc@4784000 { 825 compatible = "qcom,sm6375-sdhci", "qcom,sdhci-msm-v5"; 826 reg = <0 0x04784000 0 0x1000>; 827 828 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 830 interrupt-names = "hc_irq", "pwr_irq"; 831 832 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 833 <&gcc GCC_SDCC2_APPS_CLK>, 834 <&rpmcc RPM_SMD_XO_CLK_SRC>; 835 clock-names = "iface", "core", "xo"; 836 resets = <&gcc GCC_SDCC2_BCR>; 837 iommus = <&apps_smmu 0x40 0x0>; 838 839 pinctrl-0 = <&sdc2_on_state>; 840 pinctrl-1 = <&sdc2_off_state>; 841 pinctrl-names = "default", "sleep"; 842 843 qcom,dll-config = <0x0007642c>; 844 qcom,ddr-config = <0x80040868>; 845 power-domains = <&rpmpd SM6375_VDDCX>; 846 operating-points-v2 = <&sdhc2_opp_table>; 847 bus-width = <4>; 848 849 status = "disabled"; 850 851 sdhc2_opp_table: opp-table { 852 compatible = "operating-points-v2"; 853 854 opp-100000000 { 855 opp-hz = /bits/ 64 <100000000>; 856 required-opps = <&rpmpd_opp_low_svs>; 857 }; 858 859 opp-202000000 { 860 opp-hz = /bits/ 64 <202000000>; 861 required-opps = <&rpmpd_opp_svs_plus>; 862 }; 863 }; 864 }; 865 866 gpi_dma0: dma-controller@4a00000 { 867 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; 868 reg = <0 0x04a00000 0 0x60000>; 869 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 879 dma-channels = <10>; 880 dma-channel-mask = <0x1f>; 881 iommus = <&apps_smmu 0x16 0x0>; 882 #dma-cells = <3>; 883 status = "disabled"; 884 }; 885 886 qupv3_id_0: geniqup@4ac0000 { 887 compatible = "qcom,geni-se-qup"; 888 reg = <0x0 0x04ac0000 0x0 0x2000>; 889 clock-names = "m-ahb", "s-ahb"; 890 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 891 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 892 iommus = <&apps_smmu 0x3 0x0>; 893 #address-cells = <2>; 894 #size-cells = <2>; 895 ranges; 896 status = "disabled"; 897 898 i2c0: i2c@4a80000 { 899 compatible = "qcom,geni-i2c"; 900 reg = <0x0 0x04a80000 0x0 0x4000>; 901 clock-names = "se"; 902 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 903 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 904 pinctrl-names = "default"; 905 pinctrl-0 = <&qup_i2c0_default>; 906 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 907 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 908 dma-names = "tx", "rx"; 909 #address-cells = <1>; 910 #size-cells = <0>; 911 status = "disabled"; 912 }; 913 914 spi0: spi@4a80000 { 915 compatible = "qcom,geni-spi"; 916 reg = <0x0 0x04a80000 0x0 0x4000>; 917 clock-names = "se"; 918 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 919 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 920 pinctrl-names = "default"; 921 pinctrl-0 = <&qup_spi0_default>; 922 power-domains = <&rpmpd SM6375_VDDCX>; 923 operating-points-v2 = <&qup_opp_table>; 924 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 925 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 926 dma-names = "tx", "rx"; 927 #address-cells = <1>; 928 #size-cells = <0>; 929 status = "disabled"; 930 }; 931 932 i2c1: i2c@4a84000 { 933 compatible = "qcom,geni-i2c"; 934 reg = <0x0 0x04a84000 0x0 0x4000>; 935 clock-names = "se"; 936 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 937 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 938 pinctrl-names = "default"; 939 pinctrl-0 = <&qup_i2c1_default>; 940 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 941 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 942 dma-names = "tx", "rx"; 943 #address-cells = <1>; 944 #size-cells = <0>; 945 status = "disabled"; 946 }; 947 948 spi1: spi@4a84000 { 949 compatible = "qcom,geni-spi"; 950 reg = <0x0 0x04a84000 0x0 0x4000>; 951 clock-names = "se"; 952 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 953 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 954 power-domains = <&rpmpd SM6375_VDDCX>; 955 operating-points-v2 = <&qup_opp_table>; 956 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 957 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 958 dma-names = "tx", "rx"; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 status = "disabled"; 962 }; 963 964 i2c2: i2c@4a88000 { 965 compatible = "qcom,geni-i2c"; 966 reg = <0x0 0x04a88000 0x0 0x4000>; 967 clock-names = "se"; 968 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 969 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 970 pinctrl-names = "default"; 971 pinctrl-0 = <&qup_i2c2_default>; 972 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 973 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 974 dma-names = "tx", "rx"; 975 #address-cells = <1>; 976 #size-cells = <0>; 977 status = "disabled"; 978 }; 979 980 spi2: spi@4a88000 { 981 compatible = "qcom,geni-spi"; 982 reg = <0x0 0x04a88000 0x0 0x4000>; 983 clock-names = "se"; 984 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 985 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 986 power-domains = <&rpmpd SM6375_VDDCX>; 987 operating-points-v2 = <&qup_opp_table>; 988 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 989 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 990 dma-names = "tx", "rx"; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 status = "disabled"; 994 }; 995 996 /* 997 * As per GCC, QUP3/4/5/11 also exist, but are not even defined downstream. 998 * There is a comment in the included DTSI of another SoC saying that they 999 * are not "bolled out" (probably meaning not routed to solder balls) 1000 * TLMM driver however, suggests there are as many as 15 QUPs in total! 1001 * Most of which don't even have pin configurations for.. Sad stuff! 1002 */ 1003 }; 1004 1005 gpi_dma1: dma-controller@4c00000 { 1006 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; 1007 reg = <0 0x04c00000 0 0x60000>; 1008 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 1012 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 1018 dma-channels = <10>; 1019 dma-channel-mask = <0x1f>; 1020 iommus = <&apps_smmu 0xd6 0x0>; 1021 #dma-cells = <3>; 1022 status = "disabled"; 1023 }; 1024 1025 qupv3_id_1: geniqup@4cc0000 { 1026 compatible = "qcom,geni-se-qup"; 1027 reg = <0x0 0x04cc0000 0x0 0x2000>; 1028 clock-names = "m-ahb", "s-ahb"; 1029 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1030 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1031 iommus = <&apps_smmu 0xc3 0x0>; 1032 #address-cells = <2>; 1033 #size-cells = <2>; 1034 ranges; 1035 status = "disabled"; 1036 1037 i2c6: i2c@4c80000 { 1038 compatible = "qcom,geni-i2c"; 1039 reg = <0x0 0x04c80000 0x0 0x4000>; 1040 clock-names = "se"; 1041 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1042 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; 1043 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1044 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1045 dma-names = "tx", "rx"; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 status = "disabled"; 1049 }; 1050 1051 spi6: spi@4c80000 { 1052 compatible = "qcom,geni-spi"; 1053 reg = <0x0 0x04c80000 0x0 0x4000>; 1054 clock-names = "se"; 1055 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1056 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; 1057 power-domains = <&rpmpd SM6375_VDDCX>; 1058 operating-points-v2 = <&qup_opp_table>; 1059 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1060 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1061 dma-names = "tx", "rx"; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 status = "disabled"; 1065 }; 1066 1067 i2c7: i2c@4c84000 { 1068 compatible = "qcom,geni-i2c"; 1069 reg = <0x0 0x04c84000 0x0 0x4000>; 1070 clock-names = "se"; 1071 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1072 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1073 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1074 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1075 dma-names = "tx", "rx"; 1076 #address-cells = <1>; 1077 #size-cells = <0>; 1078 status = "disabled"; 1079 }; 1080 1081 spi7: spi@4c84000 { 1082 compatible = "qcom,geni-spi"; 1083 reg = <0x0 0x04c84000 0x0 0x4000>; 1084 clock-names = "se"; 1085 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1086 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1087 power-domains = <&rpmpd SM6375_VDDCX>; 1088 operating-points-v2 = <&qup_opp_table>; 1089 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1090 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1091 dma-names = "tx", "rx"; 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 status = "disabled"; 1095 }; 1096 1097 i2c8: i2c@4c88000 { 1098 compatible = "qcom,geni-i2c"; 1099 reg = <0x0 0x04c88000 0x0 0x4000>; 1100 clock-names = "se"; 1101 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1102 interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1103 pinctrl-names = "default"; 1104 pinctrl-0 = <&qup_i2c8_default>; 1105 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1106 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1107 dma-names = "tx", "rx"; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 status = "disabled"; 1111 }; 1112 1113 spi8: spi@4c88000 { 1114 compatible = "qcom,geni-spi"; 1115 reg = <0x0 0x04c88000 0x0 0x4000>; 1116 clock-names = "se"; 1117 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1118 interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1119 power-domains = <&rpmpd SM6375_VDDCX>; 1120 operating-points-v2 = <&qup_opp_table>; 1121 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1122 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1123 dma-names = "tx", "rx"; 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 status = "disabled"; 1127 }; 1128 1129 i2c9: i2c@4c8c000 { 1130 compatible = "qcom,geni-i2c"; 1131 reg = <0x0 0x04c8c000 0x0 0x4000>; 1132 clock-names = "se"; 1133 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1134 interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>; 1135 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1136 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1137 dma-names = "tx", "rx"; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 status = "disabled"; 1141 }; 1142 1143 spi9: spi@4c8c000 { 1144 compatible = "qcom,geni-spi"; 1145 reg = <0x0 0x04c8c000 0x0 0x4000>; 1146 clock-names = "se"; 1147 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1148 interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>; 1149 power-domains = <&rpmpd SM6375_VDDCX>; 1150 operating-points-v2 = <&qup_opp_table>; 1151 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1152 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1153 dma-names = "tx", "rx"; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 status = "disabled"; 1157 }; 1158 1159 i2c10: i2c@4c90000 { 1160 compatible = "qcom,geni-i2c"; 1161 reg = <0x0 0x04c90000 0x0 0x4000>; 1162 clock-names = "se"; 1163 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1164 interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>; 1165 pinctrl-names = "default"; 1166 pinctrl-0 = <&qup_i2c10_default>; 1167 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1168 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1169 dma-names = "tx", "rx"; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 status = "disabled"; 1173 }; 1174 1175 spi10: spi@4c90000 { 1176 compatible = "qcom,geni-spi"; 1177 reg = <0x0 0x04c90000 0x0 0x4000>; 1178 clock-names = "se"; 1179 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1180 interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>; 1181 power-domains = <&rpmpd SM6375_VDDCX>; 1182 operating-points-v2 = <&qup_opp_table>; 1183 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1184 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1185 dma-names = "tx", "rx"; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 status = "disabled"; 1189 }; 1190 }; 1191 1192 usb_1: usb@4ef8800 { 1193 compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; 1194 reg = <0 0x04ef8800 0 0x400>; 1195 1196 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1197 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1198 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1199 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1200 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1201 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1202 clock-names = "cfg_noc", 1203 "core", 1204 "iface", 1205 "sleep", 1206 "mock_utmi", 1207 "xo"; 1208 1209 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1210 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1211 assigned-clock-rates = <19200000>, <133333333>; 1212 1213 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1217 interrupt-names = "hs_phy_irq", 1218 "ss_phy_irq", 1219 "dm_hs_phy_irq", 1220 "dp_hs_phy_irq"; 1221 1222 power-domains = <&gcc USB30_PRIM_GDSC>; 1223 1224 resets = <&gcc GCC_USB30_PRIM_BCR>; 1225 1226 /* 1227 * This property is there to allow USB2 to work, as 1228 * USB3 is not implemented yet - (re)move it when 1229 * proper support is in place. 1230 */ 1231 qcom,select-utmi-as-pipe-clk; 1232 1233 #address-cells = <2>; 1234 #size-cells = <2>; 1235 ranges; 1236 1237 status = "disabled"; 1238 1239 usb_1_dwc3: usb@4e00000 { 1240 compatible = "snps,dwc3"; 1241 reg = <0 0x04e00000 0 0xcd00>; 1242 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1243 maximum-speed = "high-speed"; 1244 phys = <&usb_1_hsphy>; 1245 phy-names = "usb2-phy"; 1246 iommus = <&apps_smmu 0xe0 0x0>; 1247 1248 /* Yes, this impl *does* have an unfunny number of quirks.. */ 1249 snps,hird-threshold = /bits/ 8 <0x10>; 1250 snps,usb2-gadget-lpm-disable; 1251 snps,dis_u2_susphy_quirk; 1252 snps,is-utmi-l1-suspend; 1253 snps,dis-u1-entry-quirk; 1254 snps,dis-u2-entry-quirk; 1255 snps,usb3_lpm_capable; 1256 snps,has-lpm-erratum; 1257 tx-fifo-resize; 1258 }; 1259 }; 1260 1261 remoteproc_mss: remoteproc@6000000 { 1262 compatible = "qcom,sm6375-mpss-pas"; 1263 reg = <0 0x06000000 0 0x4040>; 1264 1265 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1266 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1267 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1268 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1269 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1270 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1271 interrupt-names = "wdog", 1272 "fatal", 1273 "ready", 1274 "handover", 1275 "stop-ack", 1276 "shutdown-ack"; 1277 1278 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1279 clock-names = "xo"; 1280 1281 power-domains = <&rpmpd SM6375_VDDCX>; 1282 power-domain-names = "cx"; 1283 1284 memory-region = <&pil_mpss_wlan_mem>; 1285 1286 qcom,smem-states = <&smp2p_modem_out 0>; 1287 qcom,smem-state-names = "stop"; 1288 1289 status = "disabled"; 1290 1291 glink-edge { 1292 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1293 IPCC_MPROC_SIGNAL_GLINK_QMP 1294 IRQ_TYPE_EDGE_RISING>; 1295 mboxes = <&ipcc IPCC_CLIENT_MPSS 1296 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1297 label = "modem"; 1298 qcom,remote-pid = <1>; 1299 }; 1300 }; 1301 1302 remoteproc_adsp: remoteproc@a400000 { 1303 compatible = "qcom,sm6375-adsp-pas"; 1304 reg = <0 0x0a400000 0 0x100>; 1305 1306 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1307 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1308 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1309 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1310 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1311 interrupt-names = "wdog", "fatal", "ready", 1312 "handover", "stop-ack"; 1313 1314 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1315 clock-names = "xo"; 1316 1317 power-domains = <&rpmpd SM6375_VDD_LPI_CX>, 1318 <&rpmpd SM6375_VDD_LPI_MX>; 1319 power-domain-names = "lcx", "lmx"; 1320 1321 memory-region = <&pil_adsp_mem>; 1322 1323 qcom,smem-states = <&smp2p_adsp_out 0>; 1324 qcom,smem-state-names = "stop"; 1325 1326 status = "disabled"; 1327 1328 glink-edge { 1329 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1330 IPCC_MPROC_SIGNAL_GLINK_QMP 1331 IRQ_TYPE_EDGE_RISING>; 1332 mboxes = <&ipcc IPCC_CLIENT_LPASS 1333 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1334 1335 label = "lpass"; 1336 qcom,remote-pid = <2>; 1337 }; 1338 }; 1339 1340 remoteproc_cdsp: remoteproc@b000000 { 1341 compatible = "qcom,sm6375-cdsp-pas"; 1342 reg = <0x0 0x0b000000 0x0 0x100000>; 1343 1344 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 1345 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1346 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1347 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1348 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1349 interrupt-names = "wdog", "fatal", "ready", 1350 "handover", "stop-ack"; 1351 1352 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1353 clock-names = "xo"; 1354 1355 power-domains = <&rpmpd SM6375_VDDCX>; 1356 power-domain-names = "cx"; 1357 1358 memory-region = <&pil_cdsp_mem>; 1359 1360 qcom,smem-states = <&smp2p_cdsp_out 0>; 1361 qcom,smem-state-names = "stop"; 1362 1363 status = "disabled"; 1364 1365 glink-edge { 1366 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1367 IPCC_MPROC_SIGNAL_GLINK_QMP 1368 IRQ_TYPE_EDGE_RISING>; 1369 mboxes = <&ipcc IPCC_CLIENT_CDSP 1370 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1371 label = "cdsp"; 1372 qcom,remote-pid = <5>; 1373 }; 1374 }; 1375 1376 sram@c125000 { 1377 compatible = "qcom,sm6375-imem", "syscon", "simple-mfd"; 1378 reg = <0 0x0c125000 0 0x1000>; 1379 ranges = <0 0 0x0c125000 0x1000>; 1380 1381 #address-cells = <1>; 1382 #size-cells = <1>; 1383 1384 pil-reloc@94c { 1385 compatible = "qcom,pil-reloc-info"; 1386 reg = <0x94c 0xc8>; 1387 }; 1388 }; 1389 1390 apps_smmu: iommu@c600000 { 1391 compatible = "qcom,sm6375-smmu-500", "arm,mmu-500"; 1392 reg = <0 0x0c600000 0 0x100000>; 1393 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1413 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1414 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1415 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1416 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1417 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1458 1459 power-domains = <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC>, 1460 <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC>, 1461 <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; 1462 #global-interrupts = <1>; 1463 #iommu-cells = <2>; 1464 }; 1465 1466 wifi: wifi@c800000 { 1467 compatible = "qcom,wcn3990-wifi"; 1468 reg = <0 0x0c800000 0 0x800000>; 1469 reg-names = "membase"; 1470 memory-region = <&pil_wlan_mem>; 1471 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1483 iommus = <&apps_smmu 0x80 0x1>; 1484 qcom,msa-fixed-perm; 1485 status = "disabled"; 1486 }; 1487 1488 intc: interrupt-controller@f200000 { 1489 compatible = "arm,gic-v3"; 1490 reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */ 1491 <0x0 0x0f240000 0x0 0x100000>; /* GICR * 8 */ 1492 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 1493 #redistributor-regions = <1>; 1494 #interrupt-cells = <3>; 1495 redistributor-stride = <0 0x20000>; 1496 interrupt-controller; 1497 }; 1498 1499 timer@f420000 { 1500 compatible = "arm,armv7-timer-mem"; 1501 reg = <0 0x0f420000 0 0x1000>; 1502 ranges = <0 0 0 0x20000000>; 1503 #address-cells = <1>; 1504 #size-cells = <1>; 1505 1506 frame@f421000 { 1507 reg = <0x0f421000 0x1000>, <0x0f422000 0x1000>; 1508 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1510 frame-number = <0>; 1511 }; 1512 1513 frame@f423000 { 1514 reg = <0x0f243000 0x1000>; 1515 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1516 frame-number = <1>; 1517 status = "disabled"; 1518 }; 1519 1520 frame@f425000 { 1521 reg = <0x0f425000 0x1000>; 1522 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1523 frame-number = <2>; 1524 status = "disabled"; 1525 }; 1526 1527 frame@f427000 { 1528 reg = <0x0f427000 0x1000>; 1529 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1530 frame-number = <3>; 1531 status = "disabled"; 1532 }; 1533 1534 frame@f429000 { 1535 reg = <0x0f429000 0x1000>; 1536 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1537 frame-number = <4>; 1538 status = "disabled"; 1539 }; 1540 1541 frame@f42b000 { 1542 reg = <0x0f42b000 0x1000>; 1543 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1544 frame-number = <5>; 1545 status = "disabled"; 1546 }; 1547 1548 frame@f42d000 { 1549 reg = <0x0f42d000 0x1000>; 1550 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1551 frame-number = <6>; 1552 status = "disabled"; 1553 }; 1554 }; 1555 1556 cpucp_l3: interconnect@fd90000 { 1557 compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3"; 1558 reg = <0 0x0fd90000 0 0x1000>; 1559 1560 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1561 clock-names = "xo", "alternate"; 1562 #interconnect-cells = <1>; 1563 }; 1564 1565 cpufreq_hw: cpufreq@fd91000 { 1566 compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss"; 1567 reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>; 1568 reg-names = "freq-domain0", "freq-domain1"; 1569 1570 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1571 clock-names = "xo", "alternate"; 1572 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1574 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; 1575 #freq-domain-cells = <1>; 1576 #clock-cells = <1>; 1577 }; 1578 }; 1579 1580 thermal-zones { 1581 mapss0-thermal { 1582 polling-delay-passive = <0>; 1583 polling-delay = <0>; 1584 1585 thermal-sensors = <&tsens0 0>; 1586 1587 trips { 1588 mapss0_alert0: trip-point0 { 1589 temperature = <90000>; 1590 hysteresis = <2000>; 1591 type = "passive"; 1592 }; 1593 1594 mapss0_alert1: trip-point1 { 1595 temperature = <95000>; 1596 hysteresis = <2000>; 1597 type = "passive"; 1598 }; 1599 1600 mapss0_crit: mapss-crit { 1601 temperature = <110000>; 1602 hysteresis = <1000>; 1603 type = "critical"; 1604 }; 1605 }; 1606 }; 1607 1608 cpu0-thermal { 1609 polling-delay-passive = <0>; 1610 polling-delay = <0>; 1611 1612 thermal-sensors = <&tsens0 1>; 1613 1614 trips { 1615 cpu0_alert0: trip-point0 { 1616 temperature = <90000>; 1617 hysteresis = <2000>; 1618 type = "passive"; 1619 }; 1620 1621 cpu0_alert1: trip-point1 { 1622 temperature = <95000>; 1623 hysteresis = <2000>; 1624 type = "passive"; 1625 }; 1626 1627 cpu0_crit: cpu-crit { 1628 temperature = <110000>; 1629 hysteresis = <1000>; 1630 type = "critical"; 1631 }; 1632 }; 1633 }; 1634 1635 cpu1-thermal { 1636 polling-delay-passive = <0>; 1637 polling-delay = <0>; 1638 1639 thermal-sensors = <&tsens0 2>; 1640 1641 trips { 1642 cpu1_alert0: trip-point0 { 1643 temperature = <90000>; 1644 hysteresis = <2000>; 1645 type = "passive"; 1646 }; 1647 1648 cpu1_alert1: trip-point1 { 1649 temperature = <95000>; 1650 hysteresis = <2000>; 1651 type = "passive"; 1652 }; 1653 1654 cpu1_crit: cpu-crit { 1655 temperature = <110000>; 1656 hysteresis = <1000>; 1657 type = "critical"; 1658 }; 1659 }; 1660 }; 1661 1662 cpu2-thermal { 1663 polling-delay-passive = <0>; 1664 polling-delay = <0>; 1665 1666 thermal-sensors = <&tsens0 3>; 1667 1668 trips { 1669 cpu2_alert0: trip-point0 { 1670 temperature = <90000>; 1671 hysteresis = <2000>; 1672 type = "passive"; 1673 }; 1674 1675 cpu2_alert1: trip-point1 { 1676 temperature = <95000>; 1677 hysteresis = <2000>; 1678 type = "passive"; 1679 }; 1680 1681 cpu2_crit: cpu-crit { 1682 temperature = <110000>; 1683 hysteresis = <1000>; 1684 type = "critical"; 1685 }; 1686 }; 1687 }; 1688 1689 cpu3-thermal { 1690 polling-delay-passive = <0>; 1691 polling-delay = <0>; 1692 1693 thermal-sensors = <&tsens0 4>; 1694 1695 trips { 1696 cpu3_alert0: trip-point0 { 1697 temperature = <90000>; 1698 hysteresis = <2000>; 1699 type = "passive"; 1700 }; 1701 1702 cpu3_alert1: trip-point1 { 1703 temperature = <95000>; 1704 hysteresis = <2000>; 1705 type = "passive"; 1706 }; 1707 1708 cpu3_crit: cpu-crit { 1709 temperature = <110000>; 1710 hysteresis = <1000>; 1711 type = "critical"; 1712 }; 1713 }; 1714 }; 1715 1716 cpu4-thermal { 1717 polling-delay-passive = <0>; 1718 polling-delay = <0>; 1719 1720 thermal-sensors = <&tsens0 5>; 1721 1722 trips { 1723 cpu4_alert0: trip-point0 { 1724 temperature = <90000>; 1725 hysteresis = <2000>; 1726 type = "passive"; 1727 }; 1728 1729 cpu4_alert1: trip-point1 { 1730 temperature = <95000>; 1731 hysteresis = <2000>; 1732 type = "passive"; 1733 }; 1734 1735 cpu4_crit: cpu-crit { 1736 temperature = <110000>; 1737 hysteresis = <1000>; 1738 type = "critical"; 1739 }; 1740 }; 1741 }; 1742 1743 cpu5-thermal { 1744 polling-delay-passive = <0>; 1745 polling-delay = <0>; 1746 1747 thermal-sensors = <&tsens0 6>; 1748 1749 trips { 1750 cpu5_alert0: trip-point0 { 1751 temperature = <90000>; 1752 hysteresis = <2000>; 1753 type = "passive"; 1754 }; 1755 1756 cpu5_alert1: trip-point1 { 1757 temperature = <95000>; 1758 hysteresis = <2000>; 1759 type = "passive"; 1760 }; 1761 1762 cpu5_crit: cpu-crit { 1763 temperature = <110000>; 1764 hysteresis = <1000>; 1765 type = "critical"; 1766 }; 1767 }; 1768 }; 1769 1770 cluster0-thermal { 1771 polling-delay-passive = <0>; 1772 polling-delay = <0>; 1773 1774 thermal-sensors = <&tsens0 7>; 1775 1776 trips { 1777 cluster0_alert0: trip-point0 { 1778 temperature = <90000>; 1779 hysteresis = <2000>; 1780 type = "passive"; 1781 }; 1782 1783 cluster0_alert1: trip-point1 { 1784 temperature = <95000>; 1785 hysteresis = <2000>; 1786 type = "passive"; 1787 }; 1788 1789 cluster0_crit: cpu-crit { 1790 temperature = <110000>; 1791 hysteresis = <1000>; 1792 type = "critical"; 1793 }; 1794 }; 1795 }; 1796 1797 cluster1-thermal { 1798 polling-delay-passive = <0>; 1799 polling-delay = <0>; 1800 1801 thermal-sensors = <&tsens0 8>; 1802 1803 trips { 1804 cluster1_alert0: trip-point0 { 1805 temperature = <90000>; 1806 hysteresis = <2000>; 1807 type = "passive"; 1808 }; 1809 1810 cluster1_alert1: trip-point1 { 1811 temperature = <95000>; 1812 hysteresis = <2000>; 1813 type = "passive"; 1814 }; 1815 1816 cluster1_crit: cpu-crit { 1817 temperature = <110000>; 1818 hysteresis = <1000>; 1819 type = "critical"; 1820 }; 1821 }; 1822 }; 1823 1824 cpu6-thermal { 1825 polling-delay-passive = <0>; 1826 polling-delay = <0>; 1827 1828 thermal-sensors = <&tsens0 9>; 1829 1830 trips { 1831 cpu6_alert0: trip-point0 { 1832 temperature = <90000>; 1833 hysteresis = <2000>; 1834 type = "passive"; 1835 }; 1836 1837 cpu6_alert1: trip-point1 { 1838 temperature = <95000>; 1839 hysteresis = <2000>; 1840 type = "passive"; 1841 }; 1842 1843 cpu6_crit: cpu-crit { 1844 temperature = <110000>; 1845 hysteresis = <1000>; 1846 type = "critical"; 1847 }; 1848 }; 1849 }; 1850 1851 cpu7-thermal { 1852 polling-delay-passive = <0>; 1853 polling-delay = <0>; 1854 1855 thermal-sensors = <&tsens0 10>; 1856 1857 trips { 1858 cpu7_alert0: trip-point0 { 1859 temperature = <90000>; 1860 hysteresis = <2000>; 1861 type = "passive"; 1862 }; 1863 1864 cpu7_alert1: trip-point1 { 1865 temperature = <95000>; 1866 hysteresis = <2000>; 1867 type = "passive"; 1868 }; 1869 1870 cpu7_crit: cpu-crit { 1871 temperature = <110000>; 1872 hysteresis = <1000>; 1873 type = "critical"; 1874 }; 1875 }; 1876 }; 1877 1878 cpu-unk0-thermal { 1879 polling-delay-passive = <0>; 1880 polling-delay = <0>; 1881 1882 thermal-sensors = <&tsens0 11>; 1883 1884 trips { 1885 cpu_unk0_alert0: trip-point0 { 1886 temperature = <90000>; 1887 hysteresis = <2000>; 1888 type = "passive"; 1889 }; 1890 1891 cpu_unk0_alert1: trip-point1 { 1892 temperature = <95000>; 1893 hysteresis = <2000>; 1894 type = "passive"; 1895 }; 1896 1897 cpu_unk0_crit: cpu-crit { 1898 temperature = <110000>; 1899 hysteresis = <1000>; 1900 type = "critical"; 1901 }; 1902 }; 1903 }; 1904 1905 cpu-unk1-thermal { 1906 polling-delay-passive = <0>; 1907 polling-delay = <0>; 1908 1909 thermal-sensors = <&tsens0 12>; 1910 1911 trips { 1912 cpu_unk1_alert0: trip-point0 { 1913 temperature = <90000>; 1914 hysteresis = <2000>; 1915 type = "passive"; 1916 }; 1917 1918 cpu_unk1_alert1: trip-point1 { 1919 temperature = <95000>; 1920 hysteresis = <2000>; 1921 type = "passive"; 1922 }; 1923 1924 cpu_unk1_crit: cpu-crit { 1925 temperature = <110000>; 1926 hysteresis = <1000>; 1927 type = "critical"; 1928 }; 1929 }; 1930 }; 1931 1932 gpuss0-thermal { 1933 polling-delay-passive = <0>; 1934 polling-delay = <0>; 1935 1936 thermal-sensors = <&tsens0 13>; 1937 1938 trips { 1939 gpuss0_alert0: trip-point0 { 1940 temperature = <90000>; 1941 hysteresis = <2000>; 1942 type = "passive"; 1943 }; 1944 1945 gpuss0_alert1: trip-point1 { 1946 temperature = <95000>; 1947 hysteresis = <2000>; 1948 type = "passive"; 1949 }; 1950 1951 gpuss0_crit: gpu-crit { 1952 temperature = <110000>; 1953 hysteresis = <1000>; 1954 type = "critical"; 1955 }; 1956 }; 1957 }; 1958 1959 gpuss1-thermal { 1960 polling-delay-passive = <0>; 1961 polling-delay = <0>; 1962 1963 thermal-sensors = <&tsens0 14>; 1964 1965 trips { 1966 gpuss1_alert0: trip-point0 { 1967 temperature = <90000>; 1968 hysteresis = <2000>; 1969 type = "passive"; 1970 }; 1971 1972 gpuss1_alert1: trip-point1 { 1973 temperature = <95000>; 1974 hysteresis = <2000>; 1975 type = "passive"; 1976 }; 1977 1978 gpuss1_crit: gpu-crit { 1979 temperature = <110000>; 1980 hysteresis = <1000>; 1981 type = "critical"; 1982 }; 1983 }; 1984 }; 1985 1986 mapss1-thermal { 1987 polling-delay-passive = <0>; 1988 polling-delay = <0>; 1989 1990 thermal-sensors = <&tsens1 0>; 1991 1992 trips { 1993 mapss1_alert0: trip-point0 { 1994 temperature = <90000>; 1995 hysteresis = <2000>; 1996 type = "passive"; 1997 }; 1998 1999 mapss1_alert1: trip-point1 { 2000 temperature = <95000>; 2001 hysteresis = <2000>; 2002 type = "passive"; 2003 }; 2004 2005 mapss1_crit: mapss-crit { 2006 temperature = <110000>; 2007 hysteresis = <1000>; 2008 type = "critical"; 2009 }; 2010 }; 2011 }; 2012 2013 cwlan-thermal { 2014 polling-delay-passive = <0>; 2015 polling-delay = <0>; 2016 2017 thermal-sensors = <&tsens1 1>; 2018 2019 trips { 2020 cwlan_alert0: trip-point0 { 2021 temperature = <90000>; 2022 hysteresis = <2000>; 2023 type = "passive"; 2024 }; 2025 2026 cwlan_alert1: trip-point1 { 2027 temperature = <95000>; 2028 hysteresis = <2000>; 2029 type = "passive"; 2030 }; 2031 2032 cwlan_crit: cwlan-crit { 2033 temperature = <110000>; 2034 hysteresis = <1000>; 2035 type = "critical"; 2036 }; 2037 }; 2038 }; 2039 2040 audio-thermal { 2041 polling-delay-passive = <0>; 2042 polling-delay = <0>; 2043 2044 thermal-sensors = <&tsens1 2>; 2045 2046 trips { 2047 audio_alert0: trip-point0 { 2048 temperature = <90000>; 2049 hysteresis = <2000>; 2050 type = "passive"; 2051 }; 2052 2053 audio_alert1: trip-point1 { 2054 temperature = <95000>; 2055 hysteresis = <2000>; 2056 type = "passive"; 2057 }; 2058 2059 audio_crit: audio-crit { 2060 temperature = <110000>; 2061 hysteresis = <1000>; 2062 type = "critical"; 2063 }; 2064 }; 2065 }; 2066 2067 ddr-thermal { 2068 polling-delay-passive = <0>; 2069 polling-delay = <0>; 2070 2071 thermal-sensors = <&tsens1 3>; 2072 2073 trips { 2074 ddr_alert0: trip-point0 { 2075 temperature = <90000>; 2076 hysteresis = <2000>; 2077 type = "passive"; 2078 }; 2079 2080 ddr_alert1: trip-point1 { 2081 temperature = <95000>; 2082 hysteresis = <2000>; 2083 type = "passive"; 2084 }; 2085 2086 ddr_crit: ddr-crit { 2087 temperature = <110000>; 2088 hysteresis = <1000>; 2089 type = "critical"; 2090 }; 2091 }; 2092 }; 2093 2094 q6hvx-thermal { 2095 polling-delay-passive = <0>; 2096 polling-delay = <0>; 2097 2098 thermal-sensors = <&tsens1 4>; 2099 2100 trips { 2101 q6hvx_alert0: trip-point0 { 2102 temperature = <90000>; 2103 hysteresis = <2000>; 2104 type = "passive"; 2105 }; 2106 2107 q6hvx_alert1: trip-point1 { 2108 temperature = <95000>; 2109 hysteresis = <2000>; 2110 type = "passive"; 2111 }; 2112 2113 q6hvx_crit: q6hvx-crit { 2114 temperature = <110000>; 2115 hysteresis = <1000>; 2116 type = "critical"; 2117 }; 2118 }; 2119 }; 2120 2121 camera-thermal { 2122 polling-delay-passive = <0>; 2123 polling-delay = <0>; 2124 2125 thermal-sensors = <&tsens1 5>; 2126 2127 trips { 2128 camera_alert0: trip-point0 { 2129 temperature = <90000>; 2130 hysteresis = <2000>; 2131 type = "passive"; 2132 }; 2133 2134 camera_alert1: trip-point1 { 2135 temperature = <95000>; 2136 hysteresis = <2000>; 2137 type = "passive"; 2138 }; 2139 2140 camera_crit: camera-crit { 2141 temperature = <110000>; 2142 hysteresis = <1000>; 2143 type = "critical"; 2144 }; 2145 }; 2146 }; 2147 2148 mdm-core0-thermal { 2149 polling-delay-passive = <0>; 2150 polling-delay = <0>; 2151 2152 thermal-sensors = <&tsens1 6>; 2153 2154 trips { 2155 mdm_core0_alert0: trip-point0 { 2156 temperature = <90000>; 2157 hysteresis = <2000>; 2158 type = "passive"; 2159 }; 2160 2161 mdm_core0_alert1: trip-point1 { 2162 temperature = <95000>; 2163 hysteresis = <2000>; 2164 type = "passive"; 2165 }; 2166 2167 mdm_core0_crit: mdm-core0-crit { 2168 temperature = <110000>; 2169 hysteresis = <1000>; 2170 type = "critical"; 2171 }; 2172 }; 2173 }; 2174 2175 mdm-core1-thermal { 2176 polling-delay-passive = <0>; 2177 polling-delay = <0>; 2178 2179 thermal-sensors = <&tsens1 7>; 2180 2181 trips { 2182 mdm_core1_alert0: trip-point0 { 2183 temperature = <90000>; 2184 hysteresis = <2000>; 2185 type = "passive"; 2186 }; 2187 2188 mdm_core1_alert1: trip-point1 { 2189 temperature = <95000>; 2190 hysteresis = <2000>; 2191 type = "passive"; 2192 }; 2193 2194 mdm_core1_crit: mdm-core1-crit { 2195 temperature = <110000>; 2196 hysteresis = <1000>; 2197 type = "critical"; 2198 }; 2199 }; 2200 }; 2201 2202 mdm-vec-thermal { 2203 polling-delay-passive = <0>; 2204 polling-delay = <0>; 2205 2206 thermal-sensors = <&tsens1 8>; 2207 2208 trips { 2209 mdm_vec_alert0: trip-point0 { 2210 temperature = <90000>; 2211 hysteresis = <2000>; 2212 type = "passive"; 2213 }; 2214 2215 mdm_vec_alert1: trip-point1 { 2216 temperature = <95000>; 2217 hysteresis = <2000>; 2218 type = "passive"; 2219 }; 2220 2221 mdm_vec_crit: mdm-vec-crit { 2222 temperature = <110000>; 2223 hysteresis = <1000>; 2224 type = "critical"; 2225 }; 2226 }; 2227 }; 2228 2229 msm-scl-thermal { 2230 polling-delay-passive = <0>; 2231 polling-delay = <0>; 2232 2233 thermal-sensors = <&tsens1 9>; 2234 2235 trips { 2236 msm_scl_alert0: trip-point0 { 2237 temperature = <90000>; 2238 hysteresis = <2000>; 2239 type = "passive"; 2240 }; 2241 2242 msm_scl_alert1: trip-point1 { 2243 temperature = <95000>; 2244 hysteresis = <2000>; 2245 type = "passive"; 2246 }; 2247 2248 msm_scl_crit: msm-scl-crit { 2249 temperature = <110000>; 2250 hysteresis = <1000>; 2251 type = "critical"; 2252 }; 2253 }; 2254 }; 2255 2256 video-thermal { 2257 polling-delay-passive = <0>; 2258 polling-delay = <0>; 2259 2260 thermal-sensors = <&tsens1 10>; 2261 2262 trips { 2263 video_alert0: trip-point0 { 2264 temperature = <90000>; 2265 hysteresis = <2000>; 2266 type = "passive"; 2267 }; 2268 2269 video_alert1: trip-point1 { 2270 temperature = <95000>; 2271 hysteresis = <2000>; 2272 type = "passive"; 2273 }; 2274 2275 video_crit: video-crit { 2276 temperature = <110000>; 2277 hysteresis = <1000>; 2278 type = "critical"; 2279 }; 2280 }; 2281 }; 2282 }; 2283 2284 timer { 2285 compatible = "arm,armv8-timer"; 2286 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2287 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2288 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2289 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2290 }; 2291}; 2292