1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/clock/qcom,sm6375-gcc.h> 8#include <dt-bindings/clock/qcom,sm6375-gpucc.h> 9#include <dt-bindings/dma/qcom-gpi.h> 10#include <dt-bindings/firmware/qcom,scm.h> 11#include <dt-bindings/interconnect/qcom,osm-l3.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/mailbox/qcom-ipcc.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board_clk: xo-board-clk { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 clock-frequency = <32000>; 33 #clock-cells = <0>; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 CPU0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "qcom,kryo660"; 44 reg = <0x0 0x0>; 45 clocks = <&cpufreq_hw 0>; 46 enable-method = "psci"; 47 next-level-cache = <&L2_0>; 48 qcom,freq-domain = <&cpufreq_hw 0>; 49 operating-points-v2 = <&cpu0_opp_table>; 50 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 51 power-domains = <&CPU_PD0>; 52 power-domain-names = "psci"; 53 #cooling-cells = <2>; 54 L2_0: l2-cache { 55 compatible = "cache"; 56 cache-level = <2>; 57 cache-unified; 58 next-level-cache = <&L3_0>; 59 L3_0: l3-cache { 60 compatible = "cache"; 61 cache-level = <3>; 62 cache-unified; 63 }; 64 }; 65 }; 66 67 CPU1: cpu@100 { 68 device_type = "cpu"; 69 compatible = "qcom,kryo660"; 70 reg = <0x0 0x100>; 71 clocks = <&cpufreq_hw 0>; 72 enable-method = "psci"; 73 next-level-cache = <&L2_100>; 74 qcom,freq-domain = <&cpufreq_hw 0>; 75 operating-points-v2 = <&cpu0_opp_table>; 76 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 77 power-domains = <&CPU_PD1>; 78 power-domain-names = "psci"; 79 #cooling-cells = <2>; 80 L2_100: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 cache-unified; 84 next-level-cache = <&L3_0>; 85 }; 86 }; 87 88 CPU2: cpu@200 { 89 device_type = "cpu"; 90 compatible = "qcom,kryo660"; 91 reg = <0x0 0x200>; 92 clocks = <&cpufreq_hw 0>; 93 enable-method = "psci"; 94 next-level-cache = <&L2_200>; 95 qcom,freq-domain = <&cpufreq_hw 0>; 96 operating-points-v2 = <&cpu0_opp_table>; 97 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 98 power-domains = <&CPU_PD2>; 99 power-domain-names = "psci"; 100 #cooling-cells = <2>; 101 L2_200: l2-cache { 102 compatible = "cache"; 103 cache-level = <2>; 104 cache-unified; 105 next-level-cache = <&L3_0>; 106 }; 107 }; 108 109 CPU3: cpu@300 { 110 device_type = "cpu"; 111 compatible = "qcom,kryo660"; 112 reg = <0x0 0x300>; 113 clocks = <&cpufreq_hw 0>; 114 enable-method = "psci"; 115 next-level-cache = <&L2_300>; 116 qcom,freq-domain = <&cpufreq_hw 0>; 117 operating-points-v2 = <&cpu0_opp_table>; 118 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 119 power-domains = <&CPU_PD3>; 120 power-domain-names = "psci"; 121 #cooling-cells = <2>; 122 L2_300: l2-cache { 123 compatible = "cache"; 124 cache-level = <2>; 125 cache-unified; 126 next-level-cache = <&L3_0>; 127 }; 128 }; 129 130 CPU4: cpu@400 { 131 device_type = "cpu"; 132 compatible = "qcom,kryo660"; 133 reg = <0x0 0x400>; 134 clocks = <&cpufreq_hw 0>; 135 enable-method = "psci"; 136 next-level-cache = <&L2_400>; 137 qcom,freq-domain = <&cpufreq_hw 0>; 138 operating-points-v2 = <&cpu0_opp_table>; 139 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 140 power-domains = <&CPU_PD4>; 141 power-domain-names = "psci"; 142 #cooling-cells = <2>; 143 L2_400: l2-cache { 144 compatible = "cache"; 145 cache-level = <2>; 146 cache-unified; 147 next-level-cache = <&L3_0>; 148 }; 149 }; 150 151 CPU5: cpu@500 { 152 device_type = "cpu"; 153 compatible = "qcom,kryo660"; 154 reg = <0x0 0x500>; 155 clocks = <&cpufreq_hw 0>; 156 enable-method = "psci"; 157 next-level-cache = <&L2_500>; 158 qcom,freq-domain = <&cpufreq_hw 0>; 159 operating-points-v2 = <&cpu0_opp_table>; 160 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 161 power-domains = <&CPU_PD5>; 162 power-domain-names = "psci"; 163 #cooling-cells = <2>; 164 L2_500: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&L3_0>; 169 }; 170 }; 171 172 CPU6: cpu@600 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo660"; 175 reg = <0x0 0x600>; 176 clocks = <&cpufreq_hw 1>; 177 enable-method = "psci"; 178 next-level-cache = <&L2_600>; 179 qcom,freq-domain = <&cpufreq_hw 1>; 180 operating-points-v2 = <&cpu6_opp_table>; 181 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 182 power-domains = <&CPU_PD6>; 183 power-domain-names = "psci"; 184 #cooling-cells = <2>; 185 L2_600: l2-cache { 186 compatible = "cache"; 187 cache-level = <2>; 188 cache-unified; 189 next-level-cache = <&L3_0>; 190 }; 191 }; 192 193 CPU7: cpu@700 { 194 device_type = "cpu"; 195 compatible = "qcom,kryo660"; 196 reg = <0x0 0x700>; 197 clocks = <&cpufreq_hw 1>; 198 enable-method = "psci"; 199 next-level-cache = <&L2_700>; 200 qcom,freq-domain = <&cpufreq_hw 1>; 201 operating-points-v2 = <&cpu6_opp_table>; 202 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 203 power-domains = <&CPU_PD7>; 204 power-domain-names = "psci"; 205 #cooling-cells = <2>; 206 L2_700: l2-cache { 207 compatible = "cache"; 208 cache-level = <2>; 209 cache-unified; 210 next-level-cache = <&L3_0>; 211 }; 212 }; 213 214 cpu-map { 215 cluster0 { 216 core0 { 217 cpu = <&CPU0>; 218 }; 219 220 core1 { 221 cpu = <&CPU1>; 222 }; 223 224 core2 { 225 cpu = <&CPU2>; 226 }; 227 228 core3 { 229 cpu = <&CPU3>; 230 }; 231 232 core4 { 233 cpu = <&CPU4>; 234 }; 235 236 core5 { 237 cpu = <&CPU5>; 238 }; 239 240 core6 { 241 cpu = <&CPU6>; 242 }; 243 244 core7 { 245 cpu = <&CPU7>; 246 }; 247 }; 248 }; 249 250 idle-states { 251 entry-method = "psci"; 252 253 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 254 compatible = "arm,idle-state"; 255 idle-state-name = "silver-power-collapse"; 256 arm,psci-suspend-param = <0x40000003>; 257 entry-latency-us = <549>; 258 exit-latency-us = <901>; 259 min-residency-us = <1774>; 260 local-timer-stop; 261 }; 262 263 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 264 compatible = "arm,idle-state"; 265 idle-state-name = "silver-rail-power-collapse"; 266 arm,psci-suspend-param = <0x40000004>; 267 entry-latency-us = <702>; 268 exit-latency-us = <915>; 269 min-residency-us = <4001>; 270 local-timer-stop; 271 }; 272 273 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 274 compatible = "arm,idle-state"; 275 idle-state-name = "gold-power-collapse"; 276 arm,psci-suspend-param = <0x40000003>; 277 entry-latency-us = <523>; 278 exit-latency-us = <1244>; 279 min-residency-us = <2207>; 280 local-timer-stop; 281 }; 282 283 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 284 compatible = "arm,idle-state"; 285 idle-state-name = "gold-rail-power-collapse"; 286 arm,psci-suspend-param = <0x40000004>; 287 entry-latency-us = <526>; 288 exit-latency-us = <1854>; 289 min-residency-us = <5555>; 290 local-timer-stop; 291 }; 292 }; 293 294 domain-idle-states { 295 CLUSTER_SLEEP_0: cluster-sleep-0 { 296 compatible = "domain-idle-state"; 297 arm,psci-suspend-param = <0x41000044>; 298 entry-latency-us = <2752>; 299 exit-latency-us = <3048>; 300 min-residency-us = <6118>; 301 }; 302 }; 303 }; 304 305 firmware { 306 scm { 307 compatible = "qcom,scm-sm6375", "qcom,scm"; 308 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 309 clock-names = "core"; 310 #reset-cells = <1>; 311 }; 312 }; 313 314 memory@80000000 { 315 device_type = "memory"; 316 /* We expect the bootloader to fill in the size */ 317 reg = <0x0 0x80000000 0x0 0x0>; 318 }; 319 320 cpu0_opp_table: opp-table-cpu0 { 321 compatible = "operating-points-v2"; 322 opp-shared; 323 324 opp-300000000 { 325 opp-hz = /bits/ 64 <300000000>; 326 opp-peak-kBps = <(300000 * 32)>; 327 }; 328 329 opp-576000000 { 330 opp-hz = /bits/ 64 <576000000>; 331 opp-peak-kBps = <(556800 * 32)>; 332 }; 333 334 opp-691200000 { 335 opp-hz = /bits/ 64 <691200000>; 336 opp-peak-kBps = <(652800 * 32)>; 337 }; 338 339 opp-940800000 { 340 opp-hz = /bits/ 64 <940800000>; 341 opp-peak-kBps = <(921600 * 32)>; 342 }; 343 344 opp-1113600000 { 345 opp-hz = /bits/ 64 <1113600000>; 346 opp-peak-kBps = <(921600 * 32)>; 347 }; 348 349 opp-1324800000 { 350 opp-hz = /bits/ 64 <1324800000>; 351 opp-peak-kBps = <(1171200 * 32)>; 352 }; 353 354 opp-1516800000 { 355 opp-hz = /bits/ 64 <1516800000>; 356 opp-peak-kBps = <(1497600 * 32)>; 357 }; 358 359 opp-1651200000 { 360 opp-hz = /bits/ 64 <1651200000>; 361 opp-peak-kBps = <(1497600 * 32)>; 362 }; 363 364 opp-1708800000 { 365 opp-hz = /bits/ 64 <1708800000>; 366 opp-peak-kBps = <(1497600 * 32)>; 367 }; 368 369 opp-1804800000 { 370 opp-hz = /bits/ 64 <1804800000>; 371 opp-peak-kBps = <(1497600 * 32)>; 372 }; 373 }; 374 375 cpu6_opp_table: opp-table-cpu6 { 376 compatible = "operating-points-v2"; 377 opp-shared; 378 379 opp-691200000 { 380 opp-hz = /bits/ 64 <691200000>; 381 opp-peak-kBps = <(556800 * 32)>; 382 }; 383 384 opp-940800000 { 385 opp-hz = /bits/ 64 <940800000>; 386 opp-peak-kBps = <(921600 * 32)>; 387 }; 388 389 opp-1228800000 { 390 opp-hz = /bits/ 64 <1228800000>; 391 opp-peak-kBps = <(1171200 * 32)>; 392 }; 393 394 opp-1401600000 { 395 opp-hz = /bits/ 64 <1401600000>; 396 opp-peak-kBps = <(1382400 * 32)>; 397 }; 398 399 opp-1516800000 { 400 opp-hz = /bits/ 64 <1516800000>; 401 opp-peak-kBps = <(1497600 * 32)>; 402 }; 403 404 opp-1651200000 { 405 opp-hz = /bits/ 64 <1651200000>; 406 opp-peak-kBps = <(1497600 * 32)>; 407 }; 408 409 opp-1804800000 { 410 opp-hz = /bits/ 64 <1804800000>; 411 opp-peak-kBps = <(1497600 * 32)>; 412 }; 413 414 opp-1900800000 { 415 opp-hz = /bits/ 64 <1900800000>; 416 opp-peak-kBps = <(1497600 * 32)>; 417 }; 418 419 opp-2054400000 { 420 opp-hz = /bits/ 64 <2054400000>; 421 opp-peak-kBps = <(1497600 * 32)>; 422 }; 423 424 opp-2208000000 { 425 opp-hz = /bits/ 64 <2208000000>; 426 opp-peak-kBps = <(1497600 * 32)>; 427 }; 428 }; 429 430 pmu { 431 compatible = "arm,armv8-pmuv3"; 432 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 433 }; 434 435 psci { 436 compatible = "arm,psci-1.0"; 437 method = "smc"; 438 439 CPU_PD0: power-domain-cpu0 { 440 #power-domain-cells = <0>; 441 power-domains = <&CLUSTER_PD>; 442 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 443 }; 444 445 CPU_PD1: power-domain-cpu1 { 446 #power-domain-cells = <0>; 447 power-domains = <&CLUSTER_PD>; 448 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 449 }; 450 451 CPU_PD2: power-domain-cpu2 { 452 #power-domain-cells = <0>; 453 power-domains = <&CLUSTER_PD>; 454 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 455 }; 456 457 CPU_PD3: power-domain-cpu3 { 458 #power-domain-cells = <0>; 459 power-domains = <&CLUSTER_PD>; 460 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 461 }; 462 463 CPU_PD4: power-domain-cpu4 { 464 #power-domain-cells = <0>; 465 power-domains = <&CLUSTER_PD>; 466 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 467 }; 468 469 CPU_PD5: power-domain-cpu5 { 470 #power-domain-cells = <0>; 471 power-domains = <&CLUSTER_PD>; 472 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 473 }; 474 475 CPU_PD6: power-domain-cpu6 { 476 #power-domain-cells = <0>; 477 power-domains = <&CLUSTER_PD>; 478 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 479 }; 480 481 CPU_PD7: power-domain-cpu7 { 482 #power-domain-cells = <0>; 483 power-domains = <&CLUSTER_PD>; 484 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 485 }; 486 487 CLUSTER_PD: power-domain-cpu-cluster0 { 488 #power-domain-cells = <0>; 489 domain-idle-states = <&CLUSTER_SLEEP_0>; 490 }; 491 }; 492 493 qup_opp_table: opp-table-qup { 494 compatible = "operating-points-v2"; 495 496 opp-75000000 { 497 opp-hz = /bits/ 64 <75000000>; 498 required-opps = <&rpmpd_opp_low_svs>; 499 }; 500 501 opp-100000000 { 502 opp-hz = /bits/ 64 <100000000>; 503 required-opps = <&rpmpd_opp_svs>; 504 }; 505 506 opp-128000000 { 507 opp-hz = /bits/ 64 <128000000>; 508 required-opps = <&rpmpd_opp_nom>; 509 }; 510 }; 511 512 reserved_memory: reserved-memory { 513 #address-cells = <2>; 514 #size-cells = <2>; 515 ranges; 516 517 hyp_mem: hypervisor@80000000 { 518 reg = <0 0x80000000 0 0x600000>; 519 no-map; 520 }; 521 522 xbl_aop_mem: xbl-aop@80700000 { 523 reg = <0 0x80700000 0 0x100000>; 524 no-map; 525 }; 526 527 reserved_xbl_uefi: xbl-uefi-res@80880000 { 528 reg = <0 0x80880000 0 0x14000>; 529 no-map; 530 }; 531 532 smem_mem: smem@80900000 { 533 compatible = "qcom,smem"; 534 reg = <0 0x80900000 0 0x200000>; 535 hwlocks = <&tcsr_mutex 3>; 536 no-map; 537 }; 538 539 fw_mem: fw@80b00000 { 540 reg = <0 0x80b00000 0 0x100000>; 541 no-map; 542 }; 543 544 cdsp_secure_heap_mem: cdsp-sec-heap@80c00000 { 545 reg = <0 0x80c00000 0 0x1e00000>; 546 no-map; 547 }; 548 549 dfps_data_mem: dpfs-data@85e00000 { 550 reg = <0 0x85e00000 0 0x100000>; 551 no-map; 552 }; 553 554 pil_wlan_mem: pil-wlan@86500000 { 555 reg = <0 0x86500000 0 0x200000>; 556 no-map; 557 }; 558 559 pil_adsp_mem: pil-adsp@86700000 { 560 reg = <0 0x86700000 0 0x2000000>; 561 no-map; 562 }; 563 564 pil_cdsp_mem: pil-cdsp@88700000 { 565 reg = <0 0x88700000 0 0x1e00000>; 566 no-map; 567 }; 568 569 pil_video_mem: pil-video@8a500000 { 570 reg = <0 0x8a500000 0 0x500000>; 571 no-map; 572 }; 573 574 pil_ipa_fw_mem: pil-ipa-fw@8aa00000 { 575 reg = <0 0x8aa00000 0 0x10000>; 576 no-map; 577 }; 578 579 pil_ipa_gsi_mem: pil-ipa-gsi@8aa10000 { 580 reg = <0 0x8aa10000 0 0xa000>; 581 no-map; 582 }; 583 584 pil_gpu_micro_code_mem: pil-gpu-ucode@8aa1a000 { 585 reg = <0 0x8aa1a000 0 0x2000>; 586 no-map; 587 }; 588 589 pil_mpss_wlan_mem: pil-mpss-wlan@8b800000 { 590 reg = <0 0x8b800000 0 0x10000000>; 591 no-map; 592 }; 593 594 removed_mem: removed@c0000000 { 595 reg = <0 0xc0000000 0 0x5100000>; 596 no-map; 597 }; 598 599 rmtfs_mem: rmtfs@f3900000 { 600 compatible = "qcom,rmtfs-mem"; 601 reg = <0 0xf3900000 0 0x280000>; 602 no-map; 603 604 qcom,client-id = <1>; 605 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 606 }; 607 608 debug_mem: debug@ffb00000 { 609 reg = <0 0xffb00000 0 0xc0000>; 610 no-map; 611 }; 612 613 last_log_mem: lastlog@ffbc0000 { 614 reg = <0 0xffbc0000 0 0x80000>; 615 no-map; 616 }; 617 618 cmdline_region: cmdline@ffd00000 { 619 reg = <0 0xffd00000 0 0x1000>; 620 no-map; 621 }; 622 }; 623 624 rpm: remoteproc { 625 compatible = "qcom,sm6375-rpm-proc", "qcom,rpm-proc"; 626 627 glink-edge { 628 compatible = "qcom,glink-rpm"; 629 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 630 IPCC_MPROC_SIGNAL_GLINK_QMP 631 IRQ_TYPE_EDGE_RISING>; 632 qcom,rpm-msg-ram = <&rpm_msg_ram>; 633 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 634 635 rpm_requests: rpm-requests { 636 compatible = "qcom,rpm-sm6375"; 637 qcom,glink-channels = "rpm_requests"; 638 639 rpmcc: clock-controller { 640 compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc"; 641 clocks = <&xo_board_clk>; 642 clock-names = "xo"; 643 #clock-cells = <1>; 644 }; 645 646 rpmpd: power-controller { 647 compatible = "qcom,sm6375-rpmpd"; 648 #power-domain-cells = <1>; 649 operating-points-v2 = <&rpmpd_opp_table>; 650 651 rpmpd_opp_table: opp-table { 652 compatible = "operating-points-v2"; 653 654 rpmpd_opp_ret: opp1 { 655 opp-level = <RPM_SMD_LEVEL_RETENTION>; 656 }; 657 658 rpmpd_opp_min_svs: opp2 { 659 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 660 }; 661 662 rpmpd_opp_low_svs: opp3 { 663 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 664 }; 665 666 rpmpd_opp_svs: opp4 { 667 opp-level = <RPM_SMD_LEVEL_SVS>; 668 }; 669 670 rpmpd_opp_svs_plus: opp5 { 671 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 672 }; 673 674 rpmpd_opp_nom: opp6 { 675 opp-level = <RPM_SMD_LEVEL_NOM>; 676 }; 677 678 rpmpd_opp_nom_plus: opp7 { 679 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 680 }; 681 682 rpmpd_opp_turbo: opp8 { 683 opp-level = <RPM_SMD_LEVEL_TURBO>; 684 }; 685 686 rpmpd_opp_turbo_no_cpr: opp9 { 687 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 688 }; 689 }; 690 }; 691 }; 692 }; 693 }; 694 695 smp2p-adsp { 696 compatible = "qcom,smp2p"; 697 qcom,smem = <443>, <429>; 698 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 699 IPCC_MPROC_SIGNAL_SMP2P 700 IRQ_TYPE_EDGE_RISING>; 701 mboxes = <&ipcc IPCC_CLIENT_LPASS 702 IPCC_MPROC_SIGNAL_SMP2P>; 703 704 qcom,local-pid = <0>; 705 qcom,remote-pid = <2>; 706 707 smp2p_adsp_out: master-kernel { 708 qcom,entry-name = "master-kernel"; 709 #qcom,smem-state-cells = <1>; 710 }; 711 712 smp2p_adsp_in: slave-kernel { 713 qcom,entry-name = "slave-kernel"; 714 interrupt-controller; 715 #interrupt-cells = <2>; 716 }; 717 }; 718 719 smp2p-cdsp { 720 compatible = "qcom,smp2p"; 721 qcom,smem = <94>, <432>; 722 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 723 IPCC_MPROC_SIGNAL_SMP2P 724 IRQ_TYPE_EDGE_RISING>; 725 mboxes = <&ipcc IPCC_CLIENT_CDSP 726 IPCC_MPROC_SIGNAL_SMP2P>; 727 728 qcom,local-pid = <0>; 729 qcom,remote-pid = <5>; 730 731 smp2p_cdsp_out: master-kernel { 732 qcom,entry-name = "master-kernel"; 733 #qcom,smem-state-cells = <1>; 734 }; 735 736 smp2p_cdsp_in: slave-kernel { 737 qcom,entry-name = "slave-kernel"; 738 interrupt-controller; 739 #interrupt-cells = <2>; 740 }; 741 }; 742 743 smp2p-modem { 744 compatible = "qcom,smp2p"; 745 qcom,smem = <435>, <428>; 746 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 747 IPCC_MPROC_SIGNAL_SMP2P 748 IRQ_TYPE_EDGE_RISING>; 749 mboxes = <&ipcc IPCC_CLIENT_MPSS 750 IPCC_MPROC_SIGNAL_SMP2P>; 751 752 qcom,local-pid = <0>; 753 qcom,remote-pid = <1>; 754 755 smp2p_modem_out: master-kernel { 756 qcom,entry-name = "master-kernel"; 757 #qcom,smem-state-cells = <1>; 758 }; 759 760 smp2p_modem_in: slave-kernel { 761 qcom,entry-name = "slave-kernel"; 762 interrupt-controller; 763 #interrupt-cells = <2>; 764 }; 765 766 ipa_smp2p_out: ipa-ap-to-modem { 767 qcom,entry-name = "ipa"; 768 #qcom,smem-state-cells = <1>; 769 }; 770 771 ipa_smp2p_in: ipa-modem-to-ap { 772 qcom,entry-name = "ipa"; 773 interrupt-controller; 774 #interrupt-cells = <2>; 775 }; 776 777 wlan_smp2p_in: wlan-wpss-to-ap { 778 qcom,entry-name = "wlan"; 779 interrupt-controller; 780 #interrupt-cells = <2>; 781 }; 782 }; 783 784 soc: soc@0 { 785 #address-cells = <2>; 786 #size-cells = <2>; 787 ranges = <0 0 0 0 0x10 0>; 788 dma-ranges = <0 0 0 0 0x10 0>; 789 compatible = "simple-bus"; 790 791 ipcc: mailbox@208000 { 792 compatible = "qcom,sm6375-ipcc", "qcom,ipcc"; 793 reg = <0 0x00208000 0 0x1000>; 794 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 795 interrupt-controller; 796 #interrupt-cells = <3>; 797 #mbox-cells = <2>; 798 }; 799 800 tcsr_mutex: hwlock@340000 { 801 compatible = "qcom,tcsr-mutex"; 802 reg = <0x0 0x00340000 0x0 0x40000>; 803 #hwlock-cells = <1>; 804 }; 805 806 tlmm: pinctrl@500000 { 807 compatible = "qcom,sm6375-tlmm"; 808 reg = <0 0x00500000 0 0x800000>; 809 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 810 gpio-ranges = <&tlmm 0 0 157>; 811 /* TODO: Hook up MPM as wakeup-parent when it's there */ 812 interrupt-controller; 813 gpio-controller; 814 #interrupt-cells = <2>; 815 #gpio-cells = <2>; 816 817 sdc2_off_state: sdc2-off-state { 818 clk-pins { 819 pins = "sdc2_clk"; 820 drive-strength = <2>; 821 bias-disable; 822 }; 823 824 cmd-pins { 825 pins = "sdc2_cmd"; 826 drive-strength = <2>; 827 bias-pull-up; 828 }; 829 830 data-pins { 831 pins = "sdc2_data"; 832 drive-strength = <2>; 833 bias-pull-up; 834 }; 835 }; 836 837 sdc2_on_state: sdc2-on-state { 838 clk-pins { 839 pins = "sdc2_clk"; 840 drive-strength = <16>; 841 bias-disable; 842 }; 843 844 cmd-pins { 845 pins = "sdc2_cmd"; 846 drive-strength = <10>; 847 bias-pull-up; 848 }; 849 850 data-pins { 851 pins = "sdc2_data"; 852 drive-strength = <10>; 853 bias-pull-up; 854 }; 855 }; 856 857 qup_i2c0_default: qup-i2c0-default-state { 858 pins = "gpio0", "gpio1"; 859 function = "qup00"; 860 drive-strength = <2>; 861 bias-pull-up; 862 }; 863 864 qup_i2c1_default: qup-i2c1-default-state { 865 pins = "gpio61", "gpio62"; 866 function = "qup01"; 867 drive-strength = <2>; 868 bias-pull-up; 869 }; 870 871 qup_i2c2_default: qup-i2c2-default-state { 872 pins = "gpio45", "gpio46"; 873 function = "qup02"; 874 drive-strength = <2>; 875 bias-pull-up; 876 }; 877 878 qup_i2c8_default: qup-i2c8-default-state { 879 pins = "gpio19", "gpio20"; 880 /* TLMM, GCC and vendor DT all have different indices.. */ 881 function = "qup12"; 882 drive-strength = <2>; 883 bias-pull-up; 884 }; 885 886 qup_i2c10_default: qup-i2c10-default-state { 887 pins = "gpio4", "gpio5"; 888 function = "qup10"; 889 drive-strength = <2>; 890 bias-pull-up; 891 }; 892 893 qup_spi0_default: qup-spi0-default-state { 894 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 895 function = "qup00"; 896 drive-strength = <6>; 897 bias-disable; 898 }; 899 }; 900 901 gcc: clock-controller@1400000 { 902 compatible = "qcom,sm6375-gcc"; 903 reg = <0 0x01400000 0 0x1f0000>; 904 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 905 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 906 <&sleep_clk>; 907 #power-domain-cells = <1>; 908 #clock-cells = <1>; 909 #reset-cells = <1>; 910 }; 911 912 usb_1_hsphy: phy@162b000 { 913 compatible = "qcom,sm6375-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; 914 reg = <0 0x0162b000 0 0x400>; 915 916 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 917 clock-names = "ref"; 918 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 919 #phy-cells = <0>; 920 921 status = "disabled"; 922 }; 923 924 spmi_bus: spmi@1c40000 { 925 compatible = "qcom,spmi-pmic-arb"; 926 reg = <0 0x01c40000 0 0x1100>, 927 <0 0x01e00000 0 0x2000000>, 928 <0 0x03e00000 0 0x100000>, 929 <0 0x03f00000 0 0xa0000>, 930 <0 0x01c0a000 0 0x26000>; 931 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 932 interrupt-names = "periph_irq"; 933 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 934 qcom,ee = <0>; 935 qcom,channel = <0>; 936 #address-cells = <2>; 937 #size-cells = <0>; 938 interrupt-controller; 939 #interrupt-cells = <4>; 940 }; 941 942 tsens0: thermal-sensor@4411000 { 943 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2"; 944 reg = <0 0x04411000 0 0x140>, /* TM */ 945 <0 0x04410000 0 0x20>; /* SROT */ 946 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 948 interrupt-names = "uplow", "critical"; 949 #thermal-sensor-cells = <1>; 950 #qcom,sensors = <15>; 951 }; 952 953 tsens1: thermal-sensor@4413000 { 954 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2"; 955 reg = <0 0x04413000 0 0x140>, /* TM */ 956 <0 0x04412000 0 0x20>; /* SROT */ 957 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 959 interrupt-names = "uplow", "critical"; 960 #thermal-sensor-cells = <1>; 961 #qcom,sensors = <11>; 962 }; 963 964 rpm_msg_ram: sram@45f0000 { 965 compatible = "qcom,rpm-msg-ram"; 966 reg = <0 0x045f0000 0 0x7000>; 967 }; 968 969 sram@4690000 { 970 compatible = "qcom,rpm-stats"; 971 reg = <0 0x04690000 0 0x400>; 972 }; 973 974 sdhc_2: mmc@4784000 { 975 compatible = "qcom,sm6375-sdhci", "qcom,sdhci-msm-v5"; 976 reg = <0 0x04784000 0 0x1000>; 977 978 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 980 interrupt-names = "hc_irq", "pwr_irq"; 981 982 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 983 <&gcc GCC_SDCC2_APPS_CLK>, 984 <&rpmcc RPM_SMD_XO_CLK_SRC>; 985 clock-names = "iface", "core", "xo"; 986 resets = <&gcc GCC_SDCC2_BCR>; 987 iommus = <&apps_smmu 0x40 0x0>; 988 989 pinctrl-0 = <&sdc2_on_state>; 990 pinctrl-1 = <&sdc2_off_state>; 991 pinctrl-names = "default", "sleep"; 992 993 qcom,dll-config = <0x0007642c>; 994 qcom,ddr-config = <0x80040868>; 995 power-domains = <&rpmpd SM6375_VDDCX>; 996 operating-points-v2 = <&sdhc2_opp_table>; 997 bus-width = <4>; 998 999 status = "disabled"; 1000 1001 sdhc2_opp_table: opp-table { 1002 compatible = "operating-points-v2"; 1003 1004 opp-100000000 { 1005 opp-hz = /bits/ 64 <100000000>; 1006 required-opps = <&rpmpd_opp_low_svs>; 1007 }; 1008 1009 opp-202000000 { 1010 opp-hz = /bits/ 64 <202000000>; 1011 required-opps = <&rpmpd_opp_svs_plus>; 1012 }; 1013 }; 1014 }; 1015 1016 gpi_dma0: dma-controller@4a00000 { 1017 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; 1018 reg = <0 0x04a00000 0 0x60000>; 1019 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1029 dma-channels = <10>; 1030 dma-channel-mask = <0x1f>; 1031 iommus = <&apps_smmu 0x16 0x0>; 1032 #dma-cells = <3>; 1033 status = "disabled"; 1034 }; 1035 1036 qupv3_id_0: geniqup@4ac0000 { 1037 compatible = "qcom,geni-se-qup"; 1038 reg = <0x0 0x04ac0000 0x0 0x2000>; 1039 clock-names = "m-ahb", "s-ahb"; 1040 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1041 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1042 iommus = <&apps_smmu 0x3 0x0>; 1043 #address-cells = <2>; 1044 #size-cells = <2>; 1045 ranges; 1046 status = "disabled"; 1047 1048 i2c0: i2c@4a80000 { 1049 compatible = "qcom,geni-i2c"; 1050 reg = <0x0 0x04a80000 0x0 0x4000>; 1051 clock-names = "se"; 1052 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1053 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1054 pinctrl-names = "default"; 1055 pinctrl-0 = <&qup_i2c0_default>; 1056 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1057 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1058 dma-names = "tx", "rx"; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 status = "disabled"; 1062 }; 1063 1064 spi0: spi@4a80000 { 1065 compatible = "qcom,geni-spi"; 1066 reg = <0x0 0x04a80000 0x0 0x4000>; 1067 clock-names = "se"; 1068 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1069 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1070 pinctrl-names = "default"; 1071 pinctrl-0 = <&qup_spi0_default>; 1072 power-domains = <&rpmpd SM6375_VDDCX>; 1073 operating-points-v2 = <&qup_opp_table>; 1074 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1075 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1076 dma-names = "tx", "rx"; 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 status = "disabled"; 1080 }; 1081 1082 i2c1: i2c@4a84000 { 1083 compatible = "qcom,geni-i2c"; 1084 reg = <0x0 0x04a84000 0x0 0x4000>; 1085 clock-names = "se"; 1086 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1087 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1088 pinctrl-names = "default"; 1089 pinctrl-0 = <&qup_i2c1_default>; 1090 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1091 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1092 dma-names = "tx", "rx"; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 status = "disabled"; 1096 }; 1097 1098 spi1: spi@4a84000 { 1099 compatible = "qcom,geni-spi"; 1100 reg = <0x0 0x04a84000 0x0 0x4000>; 1101 clock-names = "se"; 1102 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1103 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1104 power-domains = <&rpmpd SM6375_VDDCX>; 1105 operating-points-v2 = <&qup_opp_table>; 1106 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1107 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1108 dma-names = "tx", "rx"; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 status = "disabled"; 1112 }; 1113 1114 i2c2: i2c@4a88000 { 1115 compatible = "qcom,geni-i2c"; 1116 reg = <0x0 0x04a88000 0x0 0x4000>; 1117 clock-names = "se"; 1118 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1119 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1120 pinctrl-names = "default"; 1121 pinctrl-0 = <&qup_i2c2_default>; 1122 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1123 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1124 dma-names = "tx", "rx"; 1125 #address-cells = <1>; 1126 #size-cells = <0>; 1127 status = "disabled"; 1128 }; 1129 1130 spi2: spi@4a88000 { 1131 compatible = "qcom,geni-spi"; 1132 reg = <0x0 0x04a88000 0x0 0x4000>; 1133 clock-names = "se"; 1134 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1135 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1136 power-domains = <&rpmpd SM6375_VDDCX>; 1137 operating-points-v2 = <&qup_opp_table>; 1138 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1139 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1140 dma-names = "tx", "rx"; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 status = "disabled"; 1144 }; 1145 1146 /* 1147 * As per GCC, QUP3/4/5/11 also exist, but are not even defined downstream. 1148 * There is a comment in the included DTSI of another SoC saying that they 1149 * are not "bolled out" (probably meaning not routed to solder balls) 1150 * TLMM driver however, suggests there are as many as 15 QUPs in total! 1151 * Most of which don't even have pin configurations for.. Sad stuff! 1152 */ 1153 }; 1154 1155 gpi_dma1: dma-controller@4c00000 { 1156 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; 1157 reg = <0 0x04c00000 0 0x60000>; 1158 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 1168 dma-channels = <10>; 1169 dma-channel-mask = <0x1f>; 1170 iommus = <&apps_smmu 0xd6 0x0>; 1171 #dma-cells = <3>; 1172 status = "disabled"; 1173 }; 1174 1175 qupv3_id_1: geniqup@4cc0000 { 1176 compatible = "qcom,geni-se-qup"; 1177 reg = <0x0 0x04cc0000 0x0 0x2000>; 1178 clock-names = "m-ahb", "s-ahb"; 1179 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1180 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1181 iommus = <&apps_smmu 0xc3 0x0>; 1182 #address-cells = <2>; 1183 #size-cells = <2>; 1184 ranges; 1185 status = "disabled"; 1186 1187 i2c6: i2c@4c80000 { 1188 compatible = "qcom,geni-i2c"; 1189 reg = <0x0 0x04c80000 0x0 0x4000>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1192 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; 1193 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1194 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1195 dma-names = "tx", "rx"; 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 status = "disabled"; 1199 }; 1200 1201 spi6: spi@4c80000 { 1202 compatible = "qcom,geni-spi"; 1203 reg = <0x0 0x04c80000 0x0 0x4000>; 1204 clock-names = "se"; 1205 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1206 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; 1207 power-domains = <&rpmpd SM6375_VDDCX>; 1208 operating-points-v2 = <&qup_opp_table>; 1209 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1210 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1211 dma-names = "tx", "rx"; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 status = "disabled"; 1215 }; 1216 1217 i2c7: i2c@4c84000 { 1218 compatible = "qcom,geni-i2c"; 1219 reg = <0x0 0x04c84000 0x0 0x4000>; 1220 clock-names = "se"; 1221 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1222 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1223 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1224 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1225 dma-names = "tx", "rx"; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 status = "disabled"; 1229 }; 1230 1231 spi7: spi@4c84000 { 1232 compatible = "qcom,geni-spi"; 1233 reg = <0x0 0x04c84000 0x0 0x4000>; 1234 clock-names = "se"; 1235 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1236 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1237 power-domains = <&rpmpd SM6375_VDDCX>; 1238 operating-points-v2 = <&qup_opp_table>; 1239 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1240 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1241 dma-names = "tx", "rx"; 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 status = "disabled"; 1245 }; 1246 1247 i2c8: i2c@4c88000 { 1248 compatible = "qcom,geni-i2c"; 1249 reg = <0x0 0x04c88000 0x0 0x4000>; 1250 clock-names = "se"; 1251 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1252 interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1253 pinctrl-names = "default"; 1254 pinctrl-0 = <&qup_i2c8_default>; 1255 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1256 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1257 dma-names = "tx", "rx"; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 status = "disabled"; 1261 }; 1262 1263 spi8: spi@4c88000 { 1264 compatible = "qcom,geni-spi"; 1265 reg = <0x0 0x04c88000 0x0 0x4000>; 1266 clock-names = "se"; 1267 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1268 interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1269 power-domains = <&rpmpd SM6375_VDDCX>; 1270 operating-points-v2 = <&qup_opp_table>; 1271 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1272 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1273 dma-names = "tx", "rx"; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 status = "disabled"; 1277 }; 1278 1279 i2c9: i2c@4c8c000 { 1280 compatible = "qcom,geni-i2c"; 1281 reg = <0x0 0x04c8c000 0x0 0x4000>; 1282 clock-names = "se"; 1283 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1284 interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>; 1285 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1286 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1287 dma-names = "tx", "rx"; 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 status = "disabled"; 1291 }; 1292 1293 spi9: spi@4c8c000 { 1294 compatible = "qcom,geni-spi"; 1295 reg = <0x0 0x04c8c000 0x0 0x4000>; 1296 clock-names = "se"; 1297 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1298 interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>; 1299 power-domains = <&rpmpd SM6375_VDDCX>; 1300 operating-points-v2 = <&qup_opp_table>; 1301 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1302 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1303 dma-names = "tx", "rx"; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 status = "disabled"; 1307 }; 1308 1309 i2c10: i2c@4c90000 { 1310 compatible = "qcom,geni-i2c"; 1311 reg = <0x0 0x04c90000 0x0 0x4000>; 1312 clock-names = "se"; 1313 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1314 interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>; 1315 pinctrl-names = "default"; 1316 pinctrl-0 = <&qup_i2c10_default>; 1317 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1318 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1319 dma-names = "tx", "rx"; 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 status = "disabled"; 1323 }; 1324 1325 spi10: spi@4c90000 { 1326 compatible = "qcom,geni-spi"; 1327 reg = <0x0 0x04c90000 0x0 0x4000>; 1328 clock-names = "se"; 1329 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1330 interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>; 1331 power-domains = <&rpmpd SM6375_VDDCX>; 1332 operating-points-v2 = <&qup_opp_table>; 1333 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1334 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1335 dma-names = "tx", "rx"; 1336 #address-cells = <1>; 1337 #size-cells = <0>; 1338 status = "disabled"; 1339 }; 1340 }; 1341 1342 usb_1: usb@4ef8800 { 1343 compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; 1344 reg = <0 0x04ef8800 0 0x400>; 1345 1346 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1347 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1348 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1349 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1350 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1351 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1352 clock-names = "cfg_noc", 1353 "core", 1354 "iface", 1355 "sleep", 1356 "mock_utmi", 1357 "xo"; 1358 1359 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1360 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1361 assigned-clock-rates = <19200000>, <133333333>; 1362 1363 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 1364 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1367 interrupt-names = "hs_phy_irq", 1368 "ss_phy_irq", 1369 "dm_hs_phy_irq", 1370 "dp_hs_phy_irq"; 1371 1372 power-domains = <&gcc USB30_PRIM_GDSC>; 1373 1374 resets = <&gcc GCC_USB30_PRIM_BCR>; 1375 1376 /* 1377 * This property is there to allow USB2 to work, as 1378 * USB3 is not implemented yet - (re)move it when 1379 * proper support is in place. 1380 */ 1381 qcom,select-utmi-as-pipe-clk; 1382 1383 #address-cells = <2>; 1384 #size-cells = <2>; 1385 ranges; 1386 1387 status = "disabled"; 1388 1389 usb_1_dwc3: usb@4e00000 { 1390 compatible = "snps,dwc3"; 1391 reg = <0 0x04e00000 0 0xcd00>; 1392 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1393 maximum-speed = "high-speed"; 1394 phys = <&usb_1_hsphy>; 1395 phy-names = "usb2-phy"; 1396 iommus = <&apps_smmu 0xe0 0x0>; 1397 1398 /* Yes, this impl *does* have an unfunny number of quirks.. */ 1399 snps,hird-threshold = /bits/ 8 <0x10>; 1400 snps,usb2-gadget-lpm-disable; 1401 snps,dis_u2_susphy_quirk; 1402 snps,is-utmi-l1-suspend; 1403 snps,dis-u1-entry-quirk; 1404 snps,dis-u2-entry-quirk; 1405 snps,usb3_lpm_capable; 1406 snps,has-lpm-erratum; 1407 tx-fifo-resize; 1408 }; 1409 }; 1410 1411 adreno_smmu: iommu@5940000 { 1412 compatible = "qcom,sm6375-smmu-v2", "qcom,smmu-v2"; 1413 reg = <0 0x05940000 0 0x10000>; 1414 #iommu-cells = <1>; 1415 #global-interrupts = <2>; 1416 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 1417 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1426 1427 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1428 clock-names = "bus"; 1429 1430 power-domains = <&gpucc GPU_CX_GDSC>; 1431 }; 1432 1433 gpucc: clock-controller@5990000 { 1434 compatible = "qcom,sm6375-gpucc"; 1435 reg = <0 0x05990000 0 0x9000>; 1436 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1437 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1438 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, 1439 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1440 power-domains = <&rpmpd SM6375_VDDGX>; 1441 required-opps = <&rpmpd_opp_low_svs>; 1442 #clock-cells = <1>; 1443 #reset-cells = <1>; 1444 #power-domain-cells = <1>; 1445 }; 1446 1447 remoteproc_mss: remoteproc@6000000 { 1448 compatible = "qcom,sm6375-mpss-pas"; 1449 reg = <0 0x06000000 0 0x4040>; 1450 1451 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1452 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1453 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1454 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1455 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1456 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1457 interrupt-names = "wdog", 1458 "fatal", 1459 "ready", 1460 "handover", 1461 "stop-ack", 1462 "shutdown-ack"; 1463 1464 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1465 clock-names = "xo"; 1466 1467 power-domains = <&rpmpd SM6375_VDDCX>; 1468 power-domain-names = "cx"; 1469 1470 memory-region = <&pil_mpss_wlan_mem>; 1471 1472 qcom,smem-states = <&smp2p_modem_out 0>; 1473 qcom,smem-state-names = "stop"; 1474 1475 status = "disabled"; 1476 1477 glink-edge { 1478 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1479 IPCC_MPROC_SIGNAL_GLINK_QMP 1480 IRQ_TYPE_EDGE_RISING>; 1481 mboxes = <&ipcc IPCC_CLIENT_MPSS 1482 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1483 label = "modem"; 1484 qcom,remote-pid = <1>; 1485 }; 1486 }; 1487 1488 remoteproc_adsp: remoteproc@a400000 { 1489 compatible = "qcom,sm6375-adsp-pas"; 1490 reg = <0 0x0a400000 0 0x100>; 1491 1492 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1493 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1494 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1495 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1496 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1497 interrupt-names = "wdog", "fatal", "ready", 1498 "handover", "stop-ack"; 1499 1500 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1501 clock-names = "xo"; 1502 1503 power-domains = <&rpmpd SM6375_VDD_LPI_CX>, 1504 <&rpmpd SM6375_VDD_LPI_MX>; 1505 power-domain-names = "lcx", "lmx"; 1506 1507 memory-region = <&pil_adsp_mem>; 1508 1509 qcom,smem-states = <&smp2p_adsp_out 0>; 1510 qcom,smem-state-names = "stop"; 1511 1512 status = "disabled"; 1513 1514 glink-edge { 1515 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1516 IPCC_MPROC_SIGNAL_GLINK_QMP 1517 IRQ_TYPE_EDGE_RISING>; 1518 mboxes = <&ipcc IPCC_CLIENT_LPASS 1519 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1520 1521 label = "lpass"; 1522 qcom,remote-pid = <2>; 1523 }; 1524 }; 1525 1526 remoteproc_cdsp: remoteproc@b000000 { 1527 compatible = "qcom,sm6375-cdsp-pas"; 1528 reg = <0x0 0x0b000000 0x0 0x100000>; 1529 1530 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 1531 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1532 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1533 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1534 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1535 interrupt-names = "wdog", "fatal", "ready", 1536 "handover", "stop-ack"; 1537 1538 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1539 clock-names = "xo"; 1540 1541 power-domains = <&rpmpd SM6375_VDDCX>; 1542 power-domain-names = "cx"; 1543 1544 memory-region = <&pil_cdsp_mem>; 1545 1546 qcom,smem-states = <&smp2p_cdsp_out 0>; 1547 qcom,smem-state-names = "stop"; 1548 1549 status = "disabled"; 1550 1551 glink-edge { 1552 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1553 IPCC_MPROC_SIGNAL_GLINK_QMP 1554 IRQ_TYPE_EDGE_RISING>; 1555 mboxes = <&ipcc IPCC_CLIENT_CDSP 1556 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1557 label = "cdsp"; 1558 qcom,remote-pid = <5>; 1559 }; 1560 }; 1561 1562 sram@c125000 { 1563 compatible = "qcom,sm6375-imem", "syscon", "simple-mfd"; 1564 reg = <0 0x0c125000 0 0x1000>; 1565 ranges = <0 0 0x0c125000 0x1000>; 1566 1567 #address-cells = <1>; 1568 #size-cells = <1>; 1569 1570 pil-reloc@94c { 1571 compatible = "qcom,pil-reloc-info"; 1572 reg = <0x94c 0xc8>; 1573 }; 1574 }; 1575 1576 apps_smmu: iommu@c600000 { 1577 compatible = "qcom,sm6375-smmu-500", "arm,mmu-500"; 1578 reg = <0 0x0c600000 0 0x100000>; 1579 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1582 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1644 1645 power-domains = <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC>, 1646 <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC>, 1647 <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; 1648 #global-interrupts = <1>; 1649 #iommu-cells = <2>; 1650 }; 1651 1652 wifi: wifi@c800000 { 1653 compatible = "qcom,wcn3990-wifi"; 1654 reg = <0 0x0c800000 0 0x800000>; 1655 reg-names = "membase"; 1656 memory-region = <&pil_wlan_mem>; 1657 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1669 iommus = <&apps_smmu 0x80 0x1>; 1670 qcom,msa-fixed-perm; 1671 status = "disabled"; 1672 }; 1673 1674 intc: interrupt-controller@f200000 { 1675 compatible = "arm,gic-v3"; 1676 reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */ 1677 <0x0 0x0f240000 0x0 0x100000>; /* GICR * 8 */ 1678 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 1679 #redistributor-regions = <1>; 1680 #interrupt-cells = <3>; 1681 redistributor-stride = <0 0x20000>; 1682 interrupt-controller; 1683 }; 1684 1685 timer@f420000 { 1686 compatible = "arm,armv7-timer-mem"; 1687 reg = <0 0x0f420000 0 0x1000>; 1688 ranges = <0 0 0 0x20000000>; 1689 #address-cells = <1>; 1690 #size-cells = <1>; 1691 1692 frame@f421000 { 1693 reg = <0x0f421000 0x1000>, <0x0f422000 0x1000>; 1694 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1696 frame-number = <0>; 1697 }; 1698 1699 frame@f423000 { 1700 reg = <0x0f243000 0x1000>; 1701 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1702 frame-number = <1>; 1703 status = "disabled"; 1704 }; 1705 1706 frame@f425000 { 1707 reg = <0x0f425000 0x1000>; 1708 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1709 frame-number = <2>; 1710 status = "disabled"; 1711 }; 1712 1713 frame@f427000 { 1714 reg = <0x0f427000 0x1000>; 1715 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1716 frame-number = <3>; 1717 status = "disabled"; 1718 }; 1719 1720 frame@f429000 { 1721 reg = <0x0f429000 0x1000>; 1722 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1723 frame-number = <4>; 1724 status = "disabled"; 1725 }; 1726 1727 frame@f42b000 { 1728 reg = <0x0f42b000 0x1000>; 1729 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1730 frame-number = <5>; 1731 status = "disabled"; 1732 }; 1733 1734 frame@f42d000 { 1735 reg = <0x0f42d000 0x1000>; 1736 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1737 frame-number = <6>; 1738 status = "disabled"; 1739 }; 1740 }; 1741 1742 cpucp_l3: interconnect@fd90000 { 1743 compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3"; 1744 reg = <0 0x0fd90000 0 0x1000>; 1745 1746 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1747 clock-names = "xo", "alternate"; 1748 #interconnect-cells = <1>; 1749 }; 1750 1751 cpufreq_hw: cpufreq@fd91000 { 1752 compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss"; 1753 reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>; 1754 reg-names = "freq-domain0", "freq-domain1"; 1755 1756 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1757 clock-names = "xo", "alternate"; 1758 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1760 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; 1761 #freq-domain-cells = <1>; 1762 #clock-cells = <1>; 1763 }; 1764 }; 1765 1766 thermal-zones { 1767 mapss0-thermal { 1768 polling-delay-passive = <0>; 1769 polling-delay = <0>; 1770 1771 thermal-sensors = <&tsens0 0>; 1772 1773 trips { 1774 mapss0_alert0: trip-point0 { 1775 temperature = <90000>; 1776 hysteresis = <2000>; 1777 type = "passive"; 1778 }; 1779 1780 mapss0_alert1: trip-point1 { 1781 temperature = <95000>; 1782 hysteresis = <2000>; 1783 type = "passive"; 1784 }; 1785 1786 mapss0_crit: mapss-crit { 1787 temperature = <110000>; 1788 hysteresis = <1000>; 1789 type = "critical"; 1790 }; 1791 }; 1792 }; 1793 1794 cpu0-thermal { 1795 polling-delay-passive = <0>; 1796 polling-delay = <0>; 1797 1798 thermal-sensors = <&tsens0 1>; 1799 1800 trips { 1801 cpu0_alert0: trip-point0 { 1802 temperature = <90000>; 1803 hysteresis = <2000>; 1804 type = "passive"; 1805 }; 1806 1807 cpu0_alert1: trip-point1 { 1808 temperature = <95000>; 1809 hysteresis = <2000>; 1810 type = "passive"; 1811 }; 1812 1813 cpu0_crit: cpu-crit { 1814 temperature = <110000>; 1815 hysteresis = <1000>; 1816 type = "critical"; 1817 }; 1818 }; 1819 }; 1820 1821 cpu1-thermal { 1822 polling-delay-passive = <0>; 1823 polling-delay = <0>; 1824 1825 thermal-sensors = <&tsens0 2>; 1826 1827 trips { 1828 cpu1_alert0: trip-point0 { 1829 temperature = <90000>; 1830 hysteresis = <2000>; 1831 type = "passive"; 1832 }; 1833 1834 cpu1_alert1: trip-point1 { 1835 temperature = <95000>; 1836 hysteresis = <2000>; 1837 type = "passive"; 1838 }; 1839 1840 cpu1_crit: cpu-crit { 1841 temperature = <110000>; 1842 hysteresis = <1000>; 1843 type = "critical"; 1844 }; 1845 }; 1846 }; 1847 1848 cpu2-thermal { 1849 polling-delay-passive = <0>; 1850 polling-delay = <0>; 1851 1852 thermal-sensors = <&tsens0 3>; 1853 1854 trips { 1855 cpu2_alert0: trip-point0 { 1856 temperature = <90000>; 1857 hysteresis = <2000>; 1858 type = "passive"; 1859 }; 1860 1861 cpu2_alert1: trip-point1 { 1862 temperature = <95000>; 1863 hysteresis = <2000>; 1864 type = "passive"; 1865 }; 1866 1867 cpu2_crit: cpu-crit { 1868 temperature = <110000>; 1869 hysteresis = <1000>; 1870 type = "critical"; 1871 }; 1872 }; 1873 }; 1874 1875 cpu3-thermal { 1876 polling-delay-passive = <0>; 1877 polling-delay = <0>; 1878 1879 thermal-sensors = <&tsens0 4>; 1880 1881 trips { 1882 cpu3_alert0: trip-point0 { 1883 temperature = <90000>; 1884 hysteresis = <2000>; 1885 type = "passive"; 1886 }; 1887 1888 cpu3_alert1: trip-point1 { 1889 temperature = <95000>; 1890 hysteresis = <2000>; 1891 type = "passive"; 1892 }; 1893 1894 cpu3_crit: cpu-crit { 1895 temperature = <110000>; 1896 hysteresis = <1000>; 1897 type = "critical"; 1898 }; 1899 }; 1900 }; 1901 1902 cpu4-thermal { 1903 polling-delay-passive = <0>; 1904 polling-delay = <0>; 1905 1906 thermal-sensors = <&tsens0 5>; 1907 1908 trips { 1909 cpu4_alert0: trip-point0 { 1910 temperature = <90000>; 1911 hysteresis = <2000>; 1912 type = "passive"; 1913 }; 1914 1915 cpu4_alert1: trip-point1 { 1916 temperature = <95000>; 1917 hysteresis = <2000>; 1918 type = "passive"; 1919 }; 1920 1921 cpu4_crit: cpu-crit { 1922 temperature = <110000>; 1923 hysteresis = <1000>; 1924 type = "critical"; 1925 }; 1926 }; 1927 }; 1928 1929 cpu5-thermal { 1930 polling-delay-passive = <0>; 1931 polling-delay = <0>; 1932 1933 thermal-sensors = <&tsens0 6>; 1934 1935 trips { 1936 cpu5_alert0: trip-point0 { 1937 temperature = <90000>; 1938 hysteresis = <2000>; 1939 type = "passive"; 1940 }; 1941 1942 cpu5_alert1: trip-point1 { 1943 temperature = <95000>; 1944 hysteresis = <2000>; 1945 type = "passive"; 1946 }; 1947 1948 cpu5_crit: cpu-crit { 1949 temperature = <110000>; 1950 hysteresis = <1000>; 1951 type = "critical"; 1952 }; 1953 }; 1954 }; 1955 1956 cluster0-thermal { 1957 polling-delay-passive = <0>; 1958 polling-delay = <0>; 1959 1960 thermal-sensors = <&tsens0 7>; 1961 1962 trips { 1963 cluster0_alert0: trip-point0 { 1964 temperature = <90000>; 1965 hysteresis = <2000>; 1966 type = "passive"; 1967 }; 1968 1969 cluster0_alert1: trip-point1 { 1970 temperature = <95000>; 1971 hysteresis = <2000>; 1972 type = "passive"; 1973 }; 1974 1975 cluster0_crit: cpu-crit { 1976 temperature = <110000>; 1977 hysteresis = <1000>; 1978 type = "critical"; 1979 }; 1980 }; 1981 }; 1982 1983 cluster1-thermal { 1984 polling-delay-passive = <0>; 1985 polling-delay = <0>; 1986 1987 thermal-sensors = <&tsens0 8>; 1988 1989 trips { 1990 cluster1_alert0: trip-point0 { 1991 temperature = <90000>; 1992 hysteresis = <2000>; 1993 type = "passive"; 1994 }; 1995 1996 cluster1_alert1: trip-point1 { 1997 temperature = <95000>; 1998 hysteresis = <2000>; 1999 type = "passive"; 2000 }; 2001 2002 cluster1_crit: cpu-crit { 2003 temperature = <110000>; 2004 hysteresis = <1000>; 2005 type = "critical"; 2006 }; 2007 }; 2008 }; 2009 2010 cpu6-thermal { 2011 polling-delay-passive = <0>; 2012 polling-delay = <0>; 2013 2014 thermal-sensors = <&tsens0 9>; 2015 2016 trips { 2017 cpu6_alert0: trip-point0 { 2018 temperature = <90000>; 2019 hysteresis = <2000>; 2020 type = "passive"; 2021 }; 2022 2023 cpu6_alert1: trip-point1 { 2024 temperature = <95000>; 2025 hysteresis = <2000>; 2026 type = "passive"; 2027 }; 2028 2029 cpu6_crit: cpu-crit { 2030 temperature = <110000>; 2031 hysteresis = <1000>; 2032 type = "critical"; 2033 }; 2034 }; 2035 }; 2036 2037 cpu7-thermal { 2038 polling-delay-passive = <0>; 2039 polling-delay = <0>; 2040 2041 thermal-sensors = <&tsens0 10>; 2042 2043 trips { 2044 cpu7_alert0: trip-point0 { 2045 temperature = <90000>; 2046 hysteresis = <2000>; 2047 type = "passive"; 2048 }; 2049 2050 cpu7_alert1: trip-point1 { 2051 temperature = <95000>; 2052 hysteresis = <2000>; 2053 type = "passive"; 2054 }; 2055 2056 cpu7_crit: cpu-crit { 2057 temperature = <110000>; 2058 hysteresis = <1000>; 2059 type = "critical"; 2060 }; 2061 }; 2062 }; 2063 2064 cpu-unk0-thermal { 2065 polling-delay-passive = <0>; 2066 polling-delay = <0>; 2067 2068 thermal-sensors = <&tsens0 11>; 2069 2070 trips { 2071 cpu_unk0_alert0: trip-point0 { 2072 temperature = <90000>; 2073 hysteresis = <2000>; 2074 type = "passive"; 2075 }; 2076 2077 cpu_unk0_alert1: trip-point1 { 2078 temperature = <95000>; 2079 hysteresis = <2000>; 2080 type = "passive"; 2081 }; 2082 2083 cpu_unk0_crit: cpu-crit { 2084 temperature = <110000>; 2085 hysteresis = <1000>; 2086 type = "critical"; 2087 }; 2088 }; 2089 }; 2090 2091 cpu-unk1-thermal { 2092 polling-delay-passive = <0>; 2093 polling-delay = <0>; 2094 2095 thermal-sensors = <&tsens0 12>; 2096 2097 trips { 2098 cpu_unk1_alert0: trip-point0 { 2099 temperature = <90000>; 2100 hysteresis = <2000>; 2101 type = "passive"; 2102 }; 2103 2104 cpu_unk1_alert1: trip-point1 { 2105 temperature = <95000>; 2106 hysteresis = <2000>; 2107 type = "passive"; 2108 }; 2109 2110 cpu_unk1_crit: cpu-crit { 2111 temperature = <110000>; 2112 hysteresis = <1000>; 2113 type = "critical"; 2114 }; 2115 }; 2116 }; 2117 2118 gpuss0-thermal { 2119 polling-delay-passive = <0>; 2120 polling-delay = <0>; 2121 2122 thermal-sensors = <&tsens0 13>; 2123 2124 trips { 2125 gpuss0_alert0: trip-point0 { 2126 temperature = <90000>; 2127 hysteresis = <2000>; 2128 type = "passive"; 2129 }; 2130 2131 gpuss0_alert1: trip-point1 { 2132 temperature = <95000>; 2133 hysteresis = <2000>; 2134 type = "passive"; 2135 }; 2136 2137 gpuss0_crit: gpu-crit { 2138 temperature = <110000>; 2139 hysteresis = <1000>; 2140 type = "critical"; 2141 }; 2142 }; 2143 }; 2144 2145 gpuss1-thermal { 2146 polling-delay-passive = <0>; 2147 polling-delay = <0>; 2148 2149 thermal-sensors = <&tsens0 14>; 2150 2151 trips { 2152 gpuss1_alert0: trip-point0 { 2153 temperature = <90000>; 2154 hysteresis = <2000>; 2155 type = "passive"; 2156 }; 2157 2158 gpuss1_alert1: trip-point1 { 2159 temperature = <95000>; 2160 hysteresis = <2000>; 2161 type = "passive"; 2162 }; 2163 2164 gpuss1_crit: gpu-crit { 2165 temperature = <110000>; 2166 hysteresis = <1000>; 2167 type = "critical"; 2168 }; 2169 }; 2170 }; 2171 2172 mapss1-thermal { 2173 polling-delay-passive = <0>; 2174 polling-delay = <0>; 2175 2176 thermal-sensors = <&tsens1 0>; 2177 2178 trips { 2179 mapss1_alert0: trip-point0 { 2180 temperature = <90000>; 2181 hysteresis = <2000>; 2182 type = "passive"; 2183 }; 2184 2185 mapss1_alert1: trip-point1 { 2186 temperature = <95000>; 2187 hysteresis = <2000>; 2188 type = "passive"; 2189 }; 2190 2191 mapss1_crit: mapss-crit { 2192 temperature = <110000>; 2193 hysteresis = <1000>; 2194 type = "critical"; 2195 }; 2196 }; 2197 }; 2198 2199 cwlan-thermal { 2200 polling-delay-passive = <0>; 2201 polling-delay = <0>; 2202 2203 thermal-sensors = <&tsens1 1>; 2204 2205 trips { 2206 cwlan_alert0: trip-point0 { 2207 temperature = <90000>; 2208 hysteresis = <2000>; 2209 type = "passive"; 2210 }; 2211 2212 cwlan_alert1: trip-point1 { 2213 temperature = <95000>; 2214 hysteresis = <2000>; 2215 type = "passive"; 2216 }; 2217 2218 cwlan_crit: cwlan-crit { 2219 temperature = <110000>; 2220 hysteresis = <1000>; 2221 type = "critical"; 2222 }; 2223 }; 2224 }; 2225 2226 audio-thermal { 2227 polling-delay-passive = <0>; 2228 polling-delay = <0>; 2229 2230 thermal-sensors = <&tsens1 2>; 2231 2232 trips { 2233 audio_alert0: trip-point0 { 2234 temperature = <90000>; 2235 hysteresis = <2000>; 2236 type = "passive"; 2237 }; 2238 2239 audio_alert1: trip-point1 { 2240 temperature = <95000>; 2241 hysteresis = <2000>; 2242 type = "passive"; 2243 }; 2244 2245 audio_crit: audio-crit { 2246 temperature = <110000>; 2247 hysteresis = <1000>; 2248 type = "critical"; 2249 }; 2250 }; 2251 }; 2252 2253 ddr-thermal { 2254 polling-delay-passive = <0>; 2255 polling-delay = <0>; 2256 2257 thermal-sensors = <&tsens1 3>; 2258 2259 trips { 2260 ddr_alert0: trip-point0 { 2261 temperature = <90000>; 2262 hysteresis = <2000>; 2263 type = "passive"; 2264 }; 2265 2266 ddr_alert1: trip-point1 { 2267 temperature = <95000>; 2268 hysteresis = <2000>; 2269 type = "passive"; 2270 }; 2271 2272 ddr_crit: ddr-crit { 2273 temperature = <110000>; 2274 hysteresis = <1000>; 2275 type = "critical"; 2276 }; 2277 }; 2278 }; 2279 2280 q6hvx-thermal { 2281 polling-delay-passive = <0>; 2282 polling-delay = <0>; 2283 2284 thermal-sensors = <&tsens1 4>; 2285 2286 trips { 2287 q6hvx_alert0: trip-point0 { 2288 temperature = <90000>; 2289 hysteresis = <2000>; 2290 type = "passive"; 2291 }; 2292 2293 q6hvx_alert1: trip-point1 { 2294 temperature = <95000>; 2295 hysteresis = <2000>; 2296 type = "passive"; 2297 }; 2298 2299 q6hvx_crit: q6hvx-crit { 2300 temperature = <110000>; 2301 hysteresis = <1000>; 2302 type = "critical"; 2303 }; 2304 }; 2305 }; 2306 2307 camera-thermal { 2308 polling-delay-passive = <0>; 2309 polling-delay = <0>; 2310 2311 thermal-sensors = <&tsens1 5>; 2312 2313 trips { 2314 camera_alert0: trip-point0 { 2315 temperature = <90000>; 2316 hysteresis = <2000>; 2317 type = "passive"; 2318 }; 2319 2320 camera_alert1: trip-point1 { 2321 temperature = <95000>; 2322 hysteresis = <2000>; 2323 type = "passive"; 2324 }; 2325 2326 camera_crit: camera-crit { 2327 temperature = <110000>; 2328 hysteresis = <1000>; 2329 type = "critical"; 2330 }; 2331 }; 2332 }; 2333 2334 mdm-core0-thermal { 2335 polling-delay-passive = <0>; 2336 polling-delay = <0>; 2337 2338 thermal-sensors = <&tsens1 6>; 2339 2340 trips { 2341 mdm_core0_alert0: trip-point0 { 2342 temperature = <90000>; 2343 hysteresis = <2000>; 2344 type = "passive"; 2345 }; 2346 2347 mdm_core0_alert1: trip-point1 { 2348 temperature = <95000>; 2349 hysteresis = <2000>; 2350 type = "passive"; 2351 }; 2352 2353 mdm_core0_crit: mdm-core0-crit { 2354 temperature = <110000>; 2355 hysteresis = <1000>; 2356 type = "critical"; 2357 }; 2358 }; 2359 }; 2360 2361 mdm-core1-thermal { 2362 polling-delay-passive = <0>; 2363 polling-delay = <0>; 2364 2365 thermal-sensors = <&tsens1 7>; 2366 2367 trips { 2368 mdm_core1_alert0: trip-point0 { 2369 temperature = <90000>; 2370 hysteresis = <2000>; 2371 type = "passive"; 2372 }; 2373 2374 mdm_core1_alert1: trip-point1 { 2375 temperature = <95000>; 2376 hysteresis = <2000>; 2377 type = "passive"; 2378 }; 2379 2380 mdm_core1_crit: mdm-core1-crit { 2381 temperature = <110000>; 2382 hysteresis = <1000>; 2383 type = "critical"; 2384 }; 2385 }; 2386 }; 2387 2388 mdm-vec-thermal { 2389 polling-delay-passive = <0>; 2390 polling-delay = <0>; 2391 2392 thermal-sensors = <&tsens1 8>; 2393 2394 trips { 2395 mdm_vec_alert0: trip-point0 { 2396 temperature = <90000>; 2397 hysteresis = <2000>; 2398 type = "passive"; 2399 }; 2400 2401 mdm_vec_alert1: trip-point1 { 2402 temperature = <95000>; 2403 hysteresis = <2000>; 2404 type = "passive"; 2405 }; 2406 2407 mdm_vec_crit: mdm-vec-crit { 2408 temperature = <110000>; 2409 hysteresis = <1000>; 2410 type = "critical"; 2411 }; 2412 }; 2413 }; 2414 2415 msm-scl-thermal { 2416 polling-delay-passive = <0>; 2417 polling-delay = <0>; 2418 2419 thermal-sensors = <&tsens1 9>; 2420 2421 trips { 2422 msm_scl_alert0: trip-point0 { 2423 temperature = <90000>; 2424 hysteresis = <2000>; 2425 type = "passive"; 2426 }; 2427 2428 msm_scl_alert1: trip-point1 { 2429 temperature = <95000>; 2430 hysteresis = <2000>; 2431 type = "passive"; 2432 }; 2433 2434 msm_scl_crit: msm-scl-crit { 2435 temperature = <110000>; 2436 hysteresis = <1000>; 2437 type = "critical"; 2438 }; 2439 }; 2440 }; 2441 2442 video-thermal { 2443 polling-delay-passive = <0>; 2444 polling-delay = <0>; 2445 2446 thermal-sensors = <&tsens1 10>; 2447 2448 trips { 2449 video_alert0: trip-point0 { 2450 temperature = <90000>; 2451 hysteresis = <2000>; 2452 type = "passive"; 2453 }; 2454 2455 video_alert1: trip-point1 { 2456 temperature = <95000>; 2457 hysteresis = <2000>; 2458 type = "passive"; 2459 }; 2460 2461 video_crit: video-crit { 2462 temperature = <110000>; 2463 hysteresis = <1000>; 2464 type = "critical"; 2465 }; 2466 }; 2467 }; 2468 }; 2469 2470 timer { 2471 compatible = "arm,armv8-timer"; 2472 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2473 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2474 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2475 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2476 }; 2477}; 2478