1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/clock/qcom,sm6375-gcc.h> 8#include <dt-bindings/clock/qcom,sm6375-gpucc.h> 9#include <dt-bindings/dma/qcom-gpi.h> 10#include <dt-bindings/firmware/qcom,scm.h> 11#include <dt-bindings/interconnect/qcom,osm-l3.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/mailbox/qcom-ipcc.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board_clk: xo-board-clk { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 clock-frequency = <32000>; 33 #clock-cells = <0>; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 CPU0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "qcom,kryo660"; 44 reg = <0x0 0x0>; 45 clocks = <&cpufreq_hw 0>; 46 enable-method = "psci"; 47 next-level-cache = <&L2_0>; 48 qcom,freq-domain = <&cpufreq_hw 0>; 49 operating-points-v2 = <&cpu0_opp_table>; 50 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 51 power-domains = <&CPU_PD0>; 52 power-domain-names = "psci"; 53 #cooling-cells = <2>; 54 L2_0: l2-cache { 55 compatible = "cache"; 56 cache-level = <2>; 57 cache-unified; 58 next-level-cache = <&L3_0>; 59 L3_0: l3-cache { 60 compatible = "cache"; 61 cache-level = <3>; 62 cache-unified; 63 }; 64 }; 65 }; 66 67 CPU1: cpu@100 { 68 device_type = "cpu"; 69 compatible = "qcom,kryo660"; 70 reg = <0x0 0x100>; 71 clocks = <&cpufreq_hw 0>; 72 enable-method = "psci"; 73 next-level-cache = <&L2_100>; 74 qcom,freq-domain = <&cpufreq_hw 0>; 75 operating-points-v2 = <&cpu0_opp_table>; 76 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 77 power-domains = <&CPU_PD1>; 78 power-domain-names = "psci"; 79 #cooling-cells = <2>; 80 L2_100: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 cache-unified; 84 next-level-cache = <&L3_0>; 85 }; 86 }; 87 88 CPU2: cpu@200 { 89 device_type = "cpu"; 90 compatible = "qcom,kryo660"; 91 reg = <0x0 0x200>; 92 clocks = <&cpufreq_hw 0>; 93 enable-method = "psci"; 94 next-level-cache = <&L2_200>; 95 qcom,freq-domain = <&cpufreq_hw 0>; 96 operating-points-v2 = <&cpu0_opp_table>; 97 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 98 power-domains = <&CPU_PD2>; 99 power-domain-names = "psci"; 100 #cooling-cells = <2>; 101 L2_200: l2-cache { 102 compatible = "cache"; 103 cache-level = <2>; 104 cache-unified; 105 next-level-cache = <&L3_0>; 106 }; 107 }; 108 109 CPU3: cpu@300 { 110 device_type = "cpu"; 111 compatible = "qcom,kryo660"; 112 reg = <0x0 0x300>; 113 clocks = <&cpufreq_hw 0>; 114 enable-method = "psci"; 115 next-level-cache = <&L2_300>; 116 qcom,freq-domain = <&cpufreq_hw 0>; 117 operating-points-v2 = <&cpu0_opp_table>; 118 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 119 power-domains = <&CPU_PD3>; 120 power-domain-names = "psci"; 121 #cooling-cells = <2>; 122 L2_300: l2-cache { 123 compatible = "cache"; 124 cache-level = <2>; 125 cache-unified; 126 next-level-cache = <&L3_0>; 127 }; 128 }; 129 130 CPU4: cpu@400 { 131 device_type = "cpu"; 132 compatible = "qcom,kryo660"; 133 reg = <0x0 0x400>; 134 clocks = <&cpufreq_hw 0>; 135 enable-method = "psci"; 136 next-level-cache = <&L2_400>; 137 qcom,freq-domain = <&cpufreq_hw 0>; 138 operating-points-v2 = <&cpu0_opp_table>; 139 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 140 power-domains = <&CPU_PD4>; 141 power-domain-names = "psci"; 142 #cooling-cells = <2>; 143 L2_400: l2-cache { 144 compatible = "cache"; 145 cache-level = <2>; 146 cache-unified; 147 next-level-cache = <&L3_0>; 148 }; 149 }; 150 151 CPU5: cpu@500 { 152 device_type = "cpu"; 153 compatible = "qcom,kryo660"; 154 reg = <0x0 0x500>; 155 clocks = <&cpufreq_hw 0>; 156 enable-method = "psci"; 157 next-level-cache = <&L2_500>; 158 qcom,freq-domain = <&cpufreq_hw 0>; 159 operating-points-v2 = <&cpu0_opp_table>; 160 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 161 power-domains = <&CPU_PD5>; 162 power-domain-names = "psci"; 163 #cooling-cells = <2>; 164 L2_500: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&L3_0>; 169 }; 170 }; 171 172 CPU6: cpu@600 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo660"; 175 reg = <0x0 0x600>; 176 clocks = <&cpufreq_hw 1>; 177 enable-method = "psci"; 178 next-level-cache = <&L2_600>; 179 qcom,freq-domain = <&cpufreq_hw 1>; 180 operating-points-v2 = <&cpu6_opp_table>; 181 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 182 power-domains = <&CPU_PD6>; 183 power-domain-names = "psci"; 184 #cooling-cells = <2>; 185 L2_600: l2-cache { 186 compatible = "cache"; 187 cache-level = <2>; 188 cache-unified; 189 next-level-cache = <&L3_0>; 190 }; 191 }; 192 193 CPU7: cpu@700 { 194 device_type = "cpu"; 195 compatible = "qcom,kryo660"; 196 reg = <0x0 0x700>; 197 clocks = <&cpufreq_hw 1>; 198 enable-method = "psci"; 199 next-level-cache = <&L2_700>; 200 qcom,freq-domain = <&cpufreq_hw 1>; 201 operating-points-v2 = <&cpu6_opp_table>; 202 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 203 power-domains = <&CPU_PD7>; 204 power-domain-names = "psci"; 205 #cooling-cells = <2>; 206 L2_700: l2-cache { 207 compatible = "cache"; 208 cache-level = <2>; 209 cache-unified; 210 next-level-cache = <&L3_0>; 211 }; 212 }; 213 214 cpu-map { 215 cluster0 { 216 core0 { 217 cpu = <&CPU0>; 218 }; 219 220 core1 { 221 cpu = <&CPU1>; 222 }; 223 224 core2 { 225 cpu = <&CPU2>; 226 }; 227 228 core3 { 229 cpu = <&CPU3>; 230 }; 231 232 core4 { 233 cpu = <&CPU4>; 234 }; 235 236 core5 { 237 cpu = <&CPU5>; 238 }; 239 240 core6 { 241 cpu = <&CPU6>; 242 }; 243 244 core7 { 245 cpu = <&CPU7>; 246 }; 247 }; 248 }; 249 250 idle-states { 251 entry-method = "psci"; 252 253 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 254 compatible = "arm,idle-state"; 255 idle-state-name = "silver-power-collapse"; 256 arm,psci-suspend-param = <0x40000003>; 257 entry-latency-us = <549>; 258 exit-latency-us = <901>; 259 min-residency-us = <1774>; 260 local-timer-stop; 261 }; 262 263 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 264 compatible = "arm,idle-state"; 265 idle-state-name = "silver-rail-power-collapse"; 266 arm,psci-suspend-param = <0x40000004>; 267 entry-latency-us = <702>; 268 exit-latency-us = <915>; 269 min-residency-us = <4001>; 270 local-timer-stop; 271 }; 272 273 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 274 compatible = "arm,idle-state"; 275 idle-state-name = "gold-power-collapse"; 276 arm,psci-suspend-param = <0x40000003>; 277 entry-latency-us = <523>; 278 exit-latency-us = <1244>; 279 min-residency-us = <2207>; 280 local-timer-stop; 281 }; 282 283 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 284 compatible = "arm,idle-state"; 285 idle-state-name = "gold-rail-power-collapse"; 286 arm,psci-suspend-param = <0x40000004>; 287 entry-latency-us = <526>; 288 exit-latency-us = <1854>; 289 min-residency-us = <5555>; 290 local-timer-stop; 291 }; 292 }; 293 294 domain-idle-states { 295 CLUSTER_SLEEP_0: cluster-sleep-0 { 296 compatible = "domain-idle-state"; 297 arm,psci-suspend-param = <0x41000044>; 298 entry-latency-us = <2752>; 299 exit-latency-us = <3048>; 300 min-residency-us = <6118>; 301 }; 302 }; 303 }; 304 305 firmware { 306 scm { 307 compatible = "qcom,scm-sm6375", "qcom,scm"; 308 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 309 clock-names = "core"; 310 #reset-cells = <1>; 311 }; 312 }; 313 314 mpm: interrupt-controller { 315 compatible = "qcom,mpm"; 316 qcom,rpm-msg-ram = <&apss_mpm>; 317 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 318 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_SMP2P>; 319 interrupt-controller; 320 #interrupt-cells = <2>; 321 #power-domain-cells = <0>; 322 interrupt-parent = <&intc>; 323 qcom,mpm-pin-count = <96>; 324 qcom,mpm-pin-map = <5 296>, /* Soundwire wake_irq */ 325 <12 422>, /* DWC3 ss_phy_irq */ 326 <86 183>, /* MPM wake, SPMI */ 327 <89 314>, /* TSENS0 0C */ 328 <90 315>, /* TSENS1 0C */ 329 <93 164>, /* DWC3 dm_hs_phy_irq */ 330 <94 165>; /* DWC3 dp_hs_phy_irq */ 331 }; 332 333 memory@80000000 { 334 device_type = "memory"; 335 /* We expect the bootloader to fill in the size */ 336 reg = <0x0 0x80000000 0x0 0x0>; 337 }; 338 339 cpu0_opp_table: opp-table-cpu0 { 340 compatible = "operating-points-v2"; 341 opp-shared; 342 343 opp-300000000 { 344 opp-hz = /bits/ 64 <300000000>; 345 opp-peak-kBps = <(300000 * 32)>; 346 }; 347 348 opp-576000000 { 349 opp-hz = /bits/ 64 <576000000>; 350 opp-peak-kBps = <(556800 * 32)>; 351 }; 352 353 opp-691200000 { 354 opp-hz = /bits/ 64 <691200000>; 355 opp-peak-kBps = <(652800 * 32)>; 356 }; 357 358 opp-940800000 { 359 opp-hz = /bits/ 64 <940800000>; 360 opp-peak-kBps = <(921600 * 32)>; 361 }; 362 363 opp-1113600000 { 364 opp-hz = /bits/ 64 <1113600000>; 365 opp-peak-kBps = <(921600 * 32)>; 366 }; 367 368 opp-1324800000 { 369 opp-hz = /bits/ 64 <1324800000>; 370 opp-peak-kBps = <(1171200 * 32)>; 371 }; 372 373 opp-1516800000 { 374 opp-hz = /bits/ 64 <1516800000>; 375 opp-peak-kBps = <(1497600 * 32)>; 376 }; 377 378 opp-1651200000 { 379 opp-hz = /bits/ 64 <1651200000>; 380 opp-peak-kBps = <(1497600 * 32)>; 381 }; 382 383 opp-1708800000 { 384 opp-hz = /bits/ 64 <1708800000>; 385 opp-peak-kBps = <(1497600 * 32)>; 386 }; 387 388 opp-1804800000 { 389 opp-hz = /bits/ 64 <1804800000>; 390 opp-peak-kBps = <(1497600 * 32)>; 391 }; 392 }; 393 394 cpu6_opp_table: opp-table-cpu6 { 395 compatible = "operating-points-v2"; 396 opp-shared; 397 398 opp-691200000 { 399 opp-hz = /bits/ 64 <691200000>; 400 opp-peak-kBps = <(556800 * 32)>; 401 }; 402 403 opp-940800000 { 404 opp-hz = /bits/ 64 <940800000>; 405 opp-peak-kBps = <(921600 * 32)>; 406 }; 407 408 opp-1228800000 { 409 opp-hz = /bits/ 64 <1228800000>; 410 opp-peak-kBps = <(1171200 * 32)>; 411 }; 412 413 opp-1401600000 { 414 opp-hz = /bits/ 64 <1401600000>; 415 opp-peak-kBps = <(1382400 * 32)>; 416 }; 417 418 opp-1516800000 { 419 opp-hz = /bits/ 64 <1516800000>; 420 opp-peak-kBps = <(1497600 * 32)>; 421 }; 422 423 opp-1651200000 { 424 opp-hz = /bits/ 64 <1651200000>; 425 opp-peak-kBps = <(1497600 * 32)>; 426 }; 427 428 opp-1804800000 { 429 opp-hz = /bits/ 64 <1804800000>; 430 opp-peak-kBps = <(1497600 * 32)>; 431 }; 432 433 opp-1900800000 { 434 opp-hz = /bits/ 64 <1900800000>; 435 opp-peak-kBps = <(1497600 * 32)>; 436 }; 437 438 opp-2054400000 { 439 opp-hz = /bits/ 64 <2054400000>; 440 opp-peak-kBps = <(1497600 * 32)>; 441 }; 442 443 opp-2208000000 { 444 opp-hz = /bits/ 64 <2208000000>; 445 opp-peak-kBps = <(1497600 * 32)>; 446 }; 447 }; 448 449 pmu { 450 compatible = "arm,armv8-pmuv3"; 451 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 452 }; 453 454 psci { 455 compatible = "arm,psci-1.0"; 456 method = "smc"; 457 458 CPU_PD0: power-domain-cpu0 { 459 #power-domain-cells = <0>; 460 power-domains = <&CLUSTER_PD>; 461 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 462 }; 463 464 CPU_PD1: power-domain-cpu1 { 465 #power-domain-cells = <0>; 466 power-domains = <&CLUSTER_PD>; 467 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 468 }; 469 470 CPU_PD2: power-domain-cpu2 { 471 #power-domain-cells = <0>; 472 power-domains = <&CLUSTER_PD>; 473 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 474 }; 475 476 CPU_PD3: power-domain-cpu3 { 477 #power-domain-cells = <0>; 478 power-domains = <&CLUSTER_PD>; 479 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 480 }; 481 482 CPU_PD4: power-domain-cpu4 { 483 #power-domain-cells = <0>; 484 power-domains = <&CLUSTER_PD>; 485 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 486 }; 487 488 CPU_PD5: power-domain-cpu5 { 489 #power-domain-cells = <0>; 490 power-domains = <&CLUSTER_PD>; 491 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 492 }; 493 494 CPU_PD6: power-domain-cpu6 { 495 #power-domain-cells = <0>; 496 power-domains = <&CLUSTER_PD>; 497 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 498 }; 499 500 CPU_PD7: power-domain-cpu7 { 501 #power-domain-cells = <0>; 502 power-domains = <&CLUSTER_PD>; 503 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 504 }; 505 506 CLUSTER_PD: power-domain-cpu-cluster0 { 507 #power-domain-cells = <0>; 508 power-domains = <&mpm>; 509 domain-idle-states = <&CLUSTER_SLEEP_0>; 510 }; 511 }; 512 513 qup_opp_table: opp-table-qup { 514 compatible = "operating-points-v2"; 515 516 opp-75000000 { 517 opp-hz = /bits/ 64 <75000000>; 518 required-opps = <&rpmpd_opp_low_svs>; 519 }; 520 521 opp-100000000 { 522 opp-hz = /bits/ 64 <100000000>; 523 required-opps = <&rpmpd_opp_svs>; 524 }; 525 526 opp-128000000 { 527 opp-hz = /bits/ 64 <128000000>; 528 required-opps = <&rpmpd_opp_nom>; 529 }; 530 }; 531 532 reserved_memory: reserved-memory { 533 #address-cells = <2>; 534 #size-cells = <2>; 535 ranges; 536 537 hyp_mem: hypervisor@80000000 { 538 reg = <0 0x80000000 0 0x600000>; 539 no-map; 540 }; 541 542 xbl_aop_mem: xbl-aop@80700000 { 543 reg = <0 0x80700000 0 0x100000>; 544 no-map; 545 }; 546 547 reserved_xbl_uefi: xbl-uefi-res@80880000 { 548 reg = <0 0x80880000 0 0x14000>; 549 no-map; 550 }; 551 552 smem_mem: smem@80900000 { 553 compatible = "qcom,smem"; 554 reg = <0 0x80900000 0 0x200000>; 555 hwlocks = <&tcsr_mutex 3>; 556 no-map; 557 }; 558 559 fw_mem: fw@80b00000 { 560 reg = <0 0x80b00000 0 0x100000>; 561 no-map; 562 }; 563 564 cdsp_secure_heap_mem: cdsp-sec-heap@80c00000 { 565 reg = <0 0x80c00000 0 0x1e00000>; 566 no-map; 567 }; 568 569 dfps_data_mem: dpfs-data@85e00000 { 570 reg = <0 0x85e00000 0 0x100000>; 571 no-map; 572 }; 573 574 pil_wlan_mem: pil-wlan@86500000 { 575 reg = <0 0x86500000 0 0x200000>; 576 no-map; 577 }; 578 579 pil_adsp_mem: pil-adsp@86700000 { 580 reg = <0 0x86700000 0 0x2000000>; 581 no-map; 582 }; 583 584 pil_cdsp_mem: pil-cdsp@88700000 { 585 reg = <0 0x88700000 0 0x1e00000>; 586 no-map; 587 }; 588 589 pil_video_mem: pil-video@8a500000 { 590 reg = <0 0x8a500000 0 0x500000>; 591 no-map; 592 }; 593 594 pil_ipa_fw_mem: pil-ipa-fw@8aa00000 { 595 reg = <0 0x8aa00000 0 0x10000>; 596 no-map; 597 }; 598 599 pil_ipa_gsi_mem: pil-ipa-gsi@8aa10000 { 600 reg = <0 0x8aa10000 0 0xa000>; 601 no-map; 602 }; 603 604 pil_gpu_micro_code_mem: pil-gpu-ucode@8aa1a000 { 605 reg = <0 0x8aa1a000 0 0x2000>; 606 no-map; 607 }; 608 609 pil_mpss_wlan_mem: pil-mpss-wlan@8b800000 { 610 reg = <0 0x8b800000 0 0x10000000>; 611 no-map; 612 }; 613 614 removed_mem: removed@c0000000 { 615 reg = <0 0xc0000000 0 0x5100000>; 616 no-map; 617 }; 618 619 rmtfs_mem: rmtfs@f3900000 { 620 compatible = "qcom,rmtfs-mem"; 621 reg = <0 0xf3900000 0 0x280000>; 622 no-map; 623 624 qcom,client-id = <1>; 625 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 626 }; 627 628 debug_mem: debug@ffb00000 { 629 reg = <0 0xffb00000 0 0xc0000>; 630 no-map; 631 }; 632 633 last_log_mem: lastlog@ffbc0000 { 634 reg = <0 0xffbc0000 0 0x80000>; 635 no-map; 636 }; 637 638 cmdline_region: cmdline@ffd00000 { 639 reg = <0 0xffd00000 0 0x1000>; 640 no-map; 641 }; 642 }; 643 644 rpm: remoteproc { 645 compatible = "qcom,sm6375-rpm-proc", "qcom,rpm-proc"; 646 647 glink-edge { 648 compatible = "qcom,glink-rpm"; 649 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 650 IPCC_MPROC_SIGNAL_GLINK_QMP 651 IRQ_TYPE_EDGE_RISING>; 652 qcom,rpm-msg-ram = <&rpm_msg_ram>; 653 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 654 655 rpm_requests: rpm-requests { 656 compatible = "qcom,rpm-sm6375"; 657 qcom,glink-channels = "rpm_requests"; 658 659 rpmcc: clock-controller { 660 compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc"; 661 clocks = <&xo_board_clk>; 662 clock-names = "xo"; 663 #clock-cells = <1>; 664 }; 665 666 rpmpd: power-controller { 667 compatible = "qcom,sm6375-rpmpd"; 668 #power-domain-cells = <1>; 669 operating-points-v2 = <&rpmpd_opp_table>; 670 671 rpmpd_opp_table: opp-table { 672 compatible = "operating-points-v2"; 673 674 rpmpd_opp_ret: opp1 { 675 opp-level = <RPM_SMD_LEVEL_RETENTION>; 676 }; 677 678 rpmpd_opp_min_svs: opp2 { 679 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 680 }; 681 682 rpmpd_opp_low_svs: opp3 { 683 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 684 }; 685 686 rpmpd_opp_svs: opp4 { 687 opp-level = <RPM_SMD_LEVEL_SVS>; 688 }; 689 690 rpmpd_opp_svs_plus: opp5 { 691 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 692 }; 693 694 rpmpd_opp_nom: opp6 { 695 opp-level = <RPM_SMD_LEVEL_NOM>; 696 }; 697 698 rpmpd_opp_nom_plus: opp7 { 699 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 700 }; 701 702 rpmpd_opp_turbo: opp8 { 703 opp-level = <RPM_SMD_LEVEL_TURBO>; 704 }; 705 706 rpmpd_opp_turbo_no_cpr: opp9 { 707 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 708 }; 709 }; 710 }; 711 }; 712 }; 713 }; 714 715 smp2p-adsp { 716 compatible = "qcom,smp2p"; 717 qcom,smem = <443>, <429>; 718 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 719 IPCC_MPROC_SIGNAL_SMP2P 720 IRQ_TYPE_EDGE_RISING>; 721 mboxes = <&ipcc IPCC_CLIENT_LPASS 722 IPCC_MPROC_SIGNAL_SMP2P>; 723 724 qcom,local-pid = <0>; 725 qcom,remote-pid = <2>; 726 727 smp2p_adsp_out: master-kernel { 728 qcom,entry-name = "master-kernel"; 729 #qcom,smem-state-cells = <1>; 730 }; 731 732 smp2p_adsp_in: slave-kernel { 733 qcom,entry-name = "slave-kernel"; 734 interrupt-controller; 735 #interrupt-cells = <2>; 736 }; 737 }; 738 739 smp2p-cdsp { 740 compatible = "qcom,smp2p"; 741 qcom,smem = <94>, <432>; 742 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 743 IPCC_MPROC_SIGNAL_SMP2P 744 IRQ_TYPE_EDGE_RISING>; 745 mboxes = <&ipcc IPCC_CLIENT_CDSP 746 IPCC_MPROC_SIGNAL_SMP2P>; 747 748 qcom,local-pid = <0>; 749 qcom,remote-pid = <5>; 750 751 smp2p_cdsp_out: master-kernel { 752 qcom,entry-name = "master-kernel"; 753 #qcom,smem-state-cells = <1>; 754 }; 755 756 smp2p_cdsp_in: slave-kernel { 757 qcom,entry-name = "slave-kernel"; 758 interrupt-controller; 759 #interrupt-cells = <2>; 760 }; 761 }; 762 763 smp2p-modem { 764 compatible = "qcom,smp2p"; 765 qcom,smem = <435>, <428>; 766 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 767 IPCC_MPROC_SIGNAL_SMP2P 768 IRQ_TYPE_EDGE_RISING>; 769 mboxes = <&ipcc IPCC_CLIENT_MPSS 770 IPCC_MPROC_SIGNAL_SMP2P>; 771 772 qcom,local-pid = <0>; 773 qcom,remote-pid = <1>; 774 775 smp2p_modem_out: master-kernel { 776 qcom,entry-name = "master-kernel"; 777 #qcom,smem-state-cells = <1>; 778 }; 779 780 smp2p_modem_in: slave-kernel { 781 qcom,entry-name = "slave-kernel"; 782 interrupt-controller; 783 #interrupt-cells = <2>; 784 }; 785 786 ipa_smp2p_out: ipa-ap-to-modem { 787 qcom,entry-name = "ipa"; 788 #qcom,smem-state-cells = <1>; 789 }; 790 791 ipa_smp2p_in: ipa-modem-to-ap { 792 qcom,entry-name = "ipa"; 793 interrupt-controller; 794 #interrupt-cells = <2>; 795 }; 796 797 wlan_smp2p_in: wlan-wpss-to-ap { 798 qcom,entry-name = "wlan"; 799 interrupt-controller; 800 #interrupt-cells = <2>; 801 }; 802 }; 803 804 soc: soc@0 { 805 #address-cells = <2>; 806 #size-cells = <2>; 807 ranges = <0 0 0 0 0x10 0>; 808 dma-ranges = <0 0 0 0 0x10 0>; 809 compatible = "simple-bus"; 810 811 ipcc: mailbox@208000 { 812 compatible = "qcom,sm6375-ipcc", "qcom,ipcc"; 813 reg = <0 0x00208000 0 0x1000>; 814 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 815 interrupt-controller; 816 #interrupt-cells = <3>; 817 #mbox-cells = <2>; 818 }; 819 820 tcsr_mutex: hwlock@340000 { 821 compatible = "qcom,tcsr-mutex"; 822 reg = <0x0 0x00340000 0x0 0x40000>; 823 #hwlock-cells = <1>; 824 }; 825 826 tlmm: pinctrl@500000 { 827 compatible = "qcom,sm6375-tlmm"; 828 reg = <0 0x00500000 0 0x800000>; 829 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 830 gpio-ranges = <&tlmm 0 0 157>; 831 wakeup-parent = <&mpm>; 832 interrupt-controller; 833 gpio-controller; 834 #interrupt-cells = <2>; 835 #gpio-cells = <2>; 836 837 sdc2_off_state: sdc2-off-state { 838 clk-pins { 839 pins = "sdc2_clk"; 840 drive-strength = <2>; 841 bias-disable; 842 }; 843 844 cmd-pins { 845 pins = "sdc2_cmd"; 846 drive-strength = <2>; 847 bias-pull-up; 848 }; 849 850 data-pins { 851 pins = "sdc2_data"; 852 drive-strength = <2>; 853 bias-pull-up; 854 }; 855 }; 856 857 sdc2_on_state: sdc2-on-state { 858 clk-pins { 859 pins = "sdc2_clk"; 860 drive-strength = <16>; 861 bias-disable; 862 }; 863 864 cmd-pins { 865 pins = "sdc2_cmd"; 866 drive-strength = <10>; 867 bias-pull-up; 868 }; 869 870 data-pins { 871 pins = "sdc2_data"; 872 drive-strength = <10>; 873 bias-pull-up; 874 }; 875 }; 876 877 qup_i2c0_default: qup-i2c0-default-state { 878 pins = "gpio0", "gpio1"; 879 function = "qup00"; 880 drive-strength = <2>; 881 bias-pull-up; 882 }; 883 884 qup_i2c1_default: qup-i2c1-default-state { 885 pins = "gpio61", "gpio62"; 886 function = "qup01"; 887 drive-strength = <2>; 888 bias-pull-up; 889 }; 890 891 qup_i2c2_default: qup-i2c2-default-state { 892 pins = "gpio45", "gpio46"; 893 function = "qup02"; 894 drive-strength = <2>; 895 bias-pull-up; 896 }; 897 898 qup_i2c8_default: qup-i2c8-default-state { 899 pins = "gpio19", "gpio20"; 900 /* TLMM, GCC and vendor DT all have different indices.. */ 901 function = "qup12"; 902 drive-strength = <2>; 903 bias-pull-up; 904 }; 905 906 qup_i2c10_default: qup-i2c10-default-state { 907 pins = "gpio4", "gpio5"; 908 function = "qup10"; 909 drive-strength = <2>; 910 bias-pull-up; 911 }; 912 913 qup_spi0_default: qup-spi0-default-state { 914 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 915 function = "qup00"; 916 drive-strength = <6>; 917 bias-disable; 918 }; 919 }; 920 921 gcc: clock-controller@1400000 { 922 compatible = "qcom,sm6375-gcc"; 923 reg = <0 0x01400000 0 0x1f0000>; 924 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 925 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 926 <&sleep_clk>; 927 #power-domain-cells = <1>; 928 #clock-cells = <1>; 929 #reset-cells = <1>; 930 }; 931 932 usb_1_hsphy: phy@162b000 { 933 compatible = "qcom,sm6375-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; 934 reg = <0 0x0162b000 0 0x400>; 935 936 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 937 clock-names = "ref"; 938 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 939 #phy-cells = <0>; 940 941 status = "disabled"; 942 }; 943 944 spmi_bus: spmi@1c40000 { 945 compatible = "qcom,spmi-pmic-arb"; 946 reg = <0 0x01c40000 0 0x1100>, 947 <0 0x01e00000 0 0x2000000>, 948 <0 0x03e00000 0 0x100000>, 949 <0 0x03f00000 0 0xa0000>, 950 <0 0x01c0a000 0 0x26000>; 951 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 952 interrupt-names = "periph_irq"; 953 interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; 954 qcom,ee = <0>; 955 qcom,channel = <0>; 956 #address-cells = <2>; 957 #size-cells = <0>; 958 interrupt-controller; 959 #interrupt-cells = <4>; 960 }; 961 962 tsens0: thermal-sensor@4411000 { 963 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2"; 964 reg = <0 0x04411000 0 0x140>, /* TM */ 965 <0 0x04410000 0 0x20>; /* SROT */ 966 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 968 interrupt-names = "uplow", "critical"; 969 #thermal-sensor-cells = <1>; 970 #qcom,sensors = <15>; 971 }; 972 973 tsens1: thermal-sensor@4413000 { 974 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2"; 975 reg = <0 0x04413000 0 0x140>, /* TM */ 976 <0 0x04412000 0 0x20>; /* SROT */ 977 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 979 interrupt-names = "uplow", "critical"; 980 #thermal-sensor-cells = <1>; 981 #qcom,sensors = <11>; 982 }; 983 984 rpm_msg_ram: sram@45f0000 { 985 compatible = "qcom,rpm-msg-ram", "mmio-sram"; 986 reg = <0 0x045f0000 0 0x7000>; 987 #address-cells = <1>; 988 #size-cells = <1>; 989 ranges = <0 0x0 0x045f0000 0x7000>; 990 991 apss_mpm: sram@1b8 { 992 reg = <0x1b8 0x48>; 993 }; 994 }; 995 996 sram@4690000 { 997 compatible = "qcom,rpm-stats"; 998 reg = <0 0x04690000 0 0x400>; 999 }; 1000 1001 sdhc_2: mmc@4784000 { 1002 compatible = "qcom,sm6375-sdhci", "qcom,sdhci-msm-v5"; 1003 reg = <0 0x04784000 0 0x1000>; 1004 1005 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1007 interrupt-names = "hc_irq", "pwr_irq"; 1008 1009 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1010 <&gcc GCC_SDCC2_APPS_CLK>, 1011 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1012 clock-names = "iface", "core", "xo"; 1013 resets = <&gcc GCC_SDCC2_BCR>; 1014 iommus = <&apps_smmu 0x40 0x0>; 1015 1016 pinctrl-0 = <&sdc2_on_state>; 1017 pinctrl-1 = <&sdc2_off_state>; 1018 pinctrl-names = "default", "sleep"; 1019 1020 qcom,dll-config = <0x0007642c>; 1021 qcom,ddr-config = <0x80040868>; 1022 power-domains = <&rpmpd SM6375_VDDCX>; 1023 operating-points-v2 = <&sdhc2_opp_table>; 1024 bus-width = <4>; 1025 1026 status = "disabled"; 1027 1028 sdhc2_opp_table: opp-table { 1029 compatible = "operating-points-v2"; 1030 1031 opp-100000000 { 1032 opp-hz = /bits/ 64 <100000000>; 1033 required-opps = <&rpmpd_opp_low_svs>; 1034 }; 1035 1036 opp-202000000 { 1037 opp-hz = /bits/ 64 <202000000>; 1038 required-opps = <&rpmpd_opp_svs_plus>; 1039 }; 1040 }; 1041 }; 1042 1043 gpi_dma0: dma-controller@4a00000 { 1044 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; 1045 reg = <0 0x04a00000 0 0x60000>; 1046 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1056 dma-channels = <10>; 1057 dma-channel-mask = <0x1f>; 1058 iommus = <&apps_smmu 0x16 0x0>; 1059 #dma-cells = <3>; 1060 status = "disabled"; 1061 }; 1062 1063 qupv3_id_0: geniqup@4ac0000 { 1064 compatible = "qcom,geni-se-qup"; 1065 reg = <0x0 0x04ac0000 0x0 0x2000>; 1066 clock-names = "m-ahb", "s-ahb"; 1067 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1068 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1069 iommus = <&apps_smmu 0x3 0x0>; 1070 #address-cells = <2>; 1071 #size-cells = <2>; 1072 ranges; 1073 status = "disabled"; 1074 1075 i2c0: i2c@4a80000 { 1076 compatible = "qcom,geni-i2c"; 1077 reg = <0x0 0x04a80000 0x0 0x4000>; 1078 clock-names = "se"; 1079 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1080 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1081 pinctrl-names = "default"; 1082 pinctrl-0 = <&qup_i2c0_default>; 1083 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1084 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1085 dma-names = "tx", "rx"; 1086 #address-cells = <1>; 1087 #size-cells = <0>; 1088 status = "disabled"; 1089 }; 1090 1091 spi0: spi@4a80000 { 1092 compatible = "qcom,geni-spi"; 1093 reg = <0x0 0x04a80000 0x0 0x4000>; 1094 clock-names = "se"; 1095 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1096 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1097 pinctrl-names = "default"; 1098 pinctrl-0 = <&qup_spi0_default>; 1099 power-domains = <&rpmpd SM6375_VDDCX>; 1100 operating-points-v2 = <&qup_opp_table>; 1101 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1102 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1103 dma-names = "tx", "rx"; 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 status = "disabled"; 1107 }; 1108 1109 i2c1: i2c@4a84000 { 1110 compatible = "qcom,geni-i2c"; 1111 reg = <0x0 0x04a84000 0x0 0x4000>; 1112 clock-names = "se"; 1113 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1114 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1115 pinctrl-names = "default"; 1116 pinctrl-0 = <&qup_i2c1_default>; 1117 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1118 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1119 dma-names = "tx", "rx"; 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 status = "disabled"; 1123 }; 1124 1125 spi1: spi@4a84000 { 1126 compatible = "qcom,geni-spi"; 1127 reg = <0x0 0x04a84000 0x0 0x4000>; 1128 clock-names = "se"; 1129 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1130 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1131 power-domains = <&rpmpd SM6375_VDDCX>; 1132 operating-points-v2 = <&qup_opp_table>; 1133 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1134 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1135 dma-names = "tx", "rx"; 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 status = "disabled"; 1139 }; 1140 1141 i2c2: i2c@4a88000 { 1142 compatible = "qcom,geni-i2c"; 1143 reg = <0x0 0x04a88000 0x0 0x4000>; 1144 clock-names = "se"; 1145 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1146 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1147 pinctrl-names = "default"; 1148 pinctrl-0 = <&qup_i2c2_default>; 1149 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1150 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1151 dma-names = "tx", "rx"; 1152 #address-cells = <1>; 1153 #size-cells = <0>; 1154 status = "disabled"; 1155 }; 1156 1157 spi2: spi@4a88000 { 1158 compatible = "qcom,geni-spi"; 1159 reg = <0x0 0x04a88000 0x0 0x4000>; 1160 clock-names = "se"; 1161 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1162 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1163 power-domains = <&rpmpd SM6375_VDDCX>; 1164 operating-points-v2 = <&qup_opp_table>; 1165 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1166 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1167 dma-names = "tx", "rx"; 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 status = "disabled"; 1171 }; 1172 1173 /* 1174 * As per GCC, QUP3/4/5/11 also exist, but are not even defined downstream. 1175 * There is a comment in the included DTSI of another SoC saying that they 1176 * are not "bolled out" (probably meaning not routed to solder balls) 1177 * TLMM driver however, suggests there are as many as 15 QUPs in total! 1178 * Most of which don't even have pin configurations for.. Sad stuff! 1179 */ 1180 }; 1181 1182 gpi_dma1: dma-controller@4c00000 { 1183 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; 1184 reg = <0 0x04c00000 0 0x60000>; 1185 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 1195 dma-channels = <10>; 1196 dma-channel-mask = <0x1f>; 1197 iommus = <&apps_smmu 0xd6 0x0>; 1198 #dma-cells = <3>; 1199 status = "disabled"; 1200 }; 1201 1202 qupv3_id_1: geniqup@4cc0000 { 1203 compatible = "qcom,geni-se-qup"; 1204 reg = <0x0 0x04cc0000 0x0 0x2000>; 1205 clock-names = "m-ahb", "s-ahb"; 1206 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1207 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1208 iommus = <&apps_smmu 0xc3 0x0>; 1209 #address-cells = <2>; 1210 #size-cells = <2>; 1211 ranges; 1212 status = "disabled"; 1213 1214 i2c6: i2c@4c80000 { 1215 compatible = "qcom,geni-i2c"; 1216 reg = <0x0 0x04c80000 0x0 0x4000>; 1217 clock-names = "se"; 1218 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1219 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; 1220 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1221 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1222 dma-names = "tx", "rx"; 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 status = "disabled"; 1226 }; 1227 1228 spi6: spi@4c80000 { 1229 compatible = "qcom,geni-spi"; 1230 reg = <0x0 0x04c80000 0x0 0x4000>; 1231 clock-names = "se"; 1232 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1233 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; 1234 power-domains = <&rpmpd SM6375_VDDCX>; 1235 operating-points-v2 = <&qup_opp_table>; 1236 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1237 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1238 dma-names = "tx", "rx"; 1239 #address-cells = <1>; 1240 #size-cells = <0>; 1241 status = "disabled"; 1242 }; 1243 1244 i2c7: i2c@4c84000 { 1245 compatible = "qcom,geni-i2c"; 1246 reg = <0x0 0x04c84000 0x0 0x4000>; 1247 clock-names = "se"; 1248 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1249 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1250 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1251 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1252 dma-names = "tx", "rx"; 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 status = "disabled"; 1256 }; 1257 1258 spi7: spi@4c84000 { 1259 compatible = "qcom,geni-spi"; 1260 reg = <0x0 0x04c84000 0x0 0x4000>; 1261 clock-names = "se"; 1262 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1263 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1264 power-domains = <&rpmpd SM6375_VDDCX>; 1265 operating-points-v2 = <&qup_opp_table>; 1266 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1267 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1268 dma-names = "tx", "rx"; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 status = "disabled"; 1272 }; 1273 1274 i2c8: i2c@4c88000 { 1275 compatible = "qcom,geni-i2c"; 1276 reg = <0x0 0x04c88000 0x0 0x4000>; 1277 clock-names = "se"; 1278 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1279 interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1280 pinctrl-names = "default"; 1281 pinctrl-0 = <&qup_i2c8_default>; 1282 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1283 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1284 dma-names = "tx", "rx"; 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 status = "disabled"; 1288 }; 1289 1290 spi8: spi@4c88000 { 1291 compatible = "qcom,geni-spi"; 1292 reg = <0x0 0x04c88000 0x0 0x4000>; 1293 clock-names = "se"; 1294 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1295 interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1296 power-domains = <&rpmpd SM6375_VDDCX>; 1297 operating-points-v2 = <&qup_opp_table>; 1298 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1299 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1300 dma-names = "tx", "rx"; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 status = "disabled"; 1304 }; 1305 1306 i2c9: i2c@4c8c000 { 1307 compatible = "qcom,geni-i2c"; 1308 reg = <0x0 0x04c8c000 0x0 0x4000>; 1309 clock-names = "se"; 1310 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1311 interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>; 1312 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1313 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1314 dma-names = "tx", "rx"; 1315 #address-cells = <1>; 1316 #size-cells = <0>; 1317 status = "disabled"; 1318 }; 1319 1320 spi9: spi@4c8c000 { 1321 compatible = "qcom,geni-spi"; 1322 reg = <0x0 0x04c8c000 0x0 0x4000>; 1323 clock-names = "se"; 1324 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1325 interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>; 1326 power-domains = <&rpmpd SM6375_VDDCX>; 1327 operating-points-v2 = <&qup_opp_table>; 1328 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1329 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1330 dma-names = "tx", "rx"; 1331 #address-cells = <1>; 1332 #size-cells = <0>; 1333 status = "disabled"; 1334 }; 1335 1336 i2c10: i2c@4c90000 { 1337 compatible = "qcom,geni-i2c"; 1338 reg = <0x0 0x04c90000 0x0 0x4000>; 1339 clock-names = "se"; 1340 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1341 interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>; 1342 pinctrl-names = "default"; 1343 pinctrl-0 = <&qup_i2c10_default>; 1344 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1345 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1346 dma-names = "tx", "rx"; 1347 #address-cells = <1>; 1348 #size-cells = <0>; 1349 status = "disabled"; 1350 }; 1351 1352 spi10: spi@4c90000 { 1353 compatible = "qcom,geni-spi"; 1354 reg = <0x0 0x04c90000 0x0 0x4000>; 1355 clock-names = "se"; 1356 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1357 interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>; 1358 power-domains = <&rpmpd SM6375_VDDCX>; 1359 operating-points-v2 = <&qup_opp_table>; 1360 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1361 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1362 dma-names = "tx", "rx"; 1363 #address-cells = <1>; 1364 #size-cells = <0>; 1365 status = "disabled"; 1366 }; 1367 }; 1368 1369 usb_1: usb@4ef8800 { 1370 compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; 1371 reg = <0 0x04ef8800 0 0x400>; 1372 1373 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1374 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1375 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1376 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1377 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1378 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1379 clock-names = "cfg_noc", 1380 "core", 1381 "iface", 1382 "sleep", 1383 "mock_utmi", 1384 "xo"; 1385 1386 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1387 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1388 assigned-clock-rates = <19200000>, <133333333>; 1389 1390 interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 1391 <&mpm 12 IRQ_TYPE_LEVEL_HIGH>, 1392 <&mpm 93 IRQ_TYPE_EDGE_BOTH>, 1393 <&mpm 94 IRQ_TYPE_EDGE_BOTH>; 1394 interrupt-names = "hs_phy_irq", 1395 "ss_phy_irq", 1396 "dm_hs_phy_irq", 1397 "dp_hs_phy_irq"; 1398 1399 power-domains = <&gcc USB30_PRIM_GDSC>; 1400 1401 resets = <&gcc GCC_USB30_PRIM_BCR>; 1402 1403 /* 1404 * This property is there to allow USB2 to work, as 1405 * USB3 is not implemented yet - (re)move it when 1406 * proper support is in place. 1407 */ 1408 qcom,select-utmi-as-pipe-clk; 1409 1410 #address-cells = <2>; 1411 #size-cells = <2>; 1412 ranges; 1413 1414 status = "disabled"; 1415 1416 usb_1_dwc3: usb@4e00000 { 1417 compatible = "snps,dwc3"; 1418 reg = <0 0x04e00000 0 0xcd00>; 1419 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1420 maximum-speed = "high-speed"; 1421 phys = <&usb_1_hsphy>; 1422 phy-names = "usb2-phy"; 1423 iommus = <&apps_smmu 0xe0 0x0>; 1424 1425 /* Yes, this impl *does* have an unfunny number of quirks.. */ 1426 snps,hird-threshold = /bits/ 8 <0x10>; 1427 snps,usb2-gadget-lpm-disable; 1428 snps,dis_u2_susphy_quirk; 1429 snps,is-utmi-l1-suspend; 1430 snps,dis-u1-entry-quirk; 1431 snps,dis-u2-entry-quirk; 1432 snps,usb3_lpm_capable; 1433 snps,has-lpm-erratum; 1434 tx-fifo-resize; 1435 }; 1436 }; 1437 1438 adreno_smmu: iommu@5940000 { 1439 compatible = "qcom,sm6375-smmu-v2", "qcom,smmu-v2"; 1440 reg = <0 0x05940000 0 0x10000>; 1441 #iommu-cells = <1>; 1442 #global-interrupts = <2>; 1443 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1453 1454 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1455 clock-names = "bus"; 1456 1457 power-domains = <&gpucc GPU_CX_GDSC>; 1458 }; 1459 1460 gpucc: clock-controller@5990000 { 1461 compatible = "qcom,sm6375-gpucc"; 1462 reg = <0 0x05990000 0 0x9000>; 1463 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1464 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1465 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, 1466 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1467 power-domains = <&rpmpd SM6375_VDDGX>; 1468 required-opps = <&rpmpd_opp_low_svs>; 1469 #clock-cells = <1>; 1470 #reset-cells = <1>; 1471 #power-domain-cells = <1>; 1472 }; 1473 1474 remoteproc_mss: remoteproc@6000000 { 1475 compatible = "qcom,sm6375-mpss-pas"; 1476 reg = <0 0x06000000 0 0x4040>; 1477 1478 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1479 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1480 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1481 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1482 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1483 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1484 interrupt-names = "wdog", 1485 "fatal", 1486 "ready", 1487 "handover", 1488 "stop-ack", 1489 "shutdown-ack"; 1490 1491 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1492 clock-names = "xo"; 1493 1494 power-domains = <&rpmpd SM6375_VDDCX>; 1495 power-domain-names = "cx"; 1496 1497 memory-region = <&pil_mpss_wlan_mem>; 1498 1499 qcom,smem-states = <&smp2p_modem_out 0>; 1500 qcom,smem-state-names = "stop"; 1501 1502 status = "disabled"; 1503 1504 glink-edge { 1505 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1506 IPCC_MPROC_SIGNAL_GLINK_QMP 1507 IRQ_TYPE_EDGE_RISING>; 1508 mboxes = <&ipcc IPCC_CLIENT_MPSS 1509 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1510 label = "modem"; 1511 qcom,remote-pid = <1>; 1512 }; 1513 }; 1514 1515 remoteproc_adsp: remoteproc@a400000 { 1516 compatible = "qcom,sm6375-adsp-pas"; 1517 reg = <0 0x0a400000 0 0x100>; 1518 1519 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1520 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1521 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1522 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1523 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1524 interrupt-names = "wdog", "fatal", "ready", 1525 "handover", "stop-ack"; 1526 1527 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1528 clock-names = "xo"; 1529 1530 power-domains = <&rpmpd SM6375_VDD_LPI_CX>, 1531 <&rpmpd SM6375_VDD_LPI_MX>; 1532 power-domain-names = "lcx", "lmx"; 1533 1534 memory-region = <&pil_adsp_mem>; 1535 1536 qcom,smem-states = <&smp2p_adsp_out 0>; 1537 qcom,smem-state-names = "stop"; 1538 1539 status = "disabled"; 1540 1541 glink-edge { 1542 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1543 IPCC_MPROC_SIGNAL_GLINK_QMP 1544 IRQ_TYPE_EDGE_RISING>; 1545 mboxes = <&ipcc IPCC_CLIENT_LPASS 1546 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1547 1548 label = "lpass"; 1549 qcom,remote-pid = <2>; 1550 }; 1551 }; 1552 1553 remoteproc_cdsp: remoteproc@b000000 { 1554 compatible = "qcom,sm6375-cdsp-pas"; 1555 reg = <0x0 0x0b000000 0x0 0x100000>; 1556 1557 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 1558 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1559 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1560 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1561 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1562 interrupt-names = "wdog", "fatal", "ready", 1563 "handover", "stop-ack"; 1564 1565 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1566 clock-names = "xo"; 1567 1568 power-domains = <&rpmpd SM6375_VDDCX>; 1569 power-domain-names = "cx"; 1570 1571 memory-region = <&pil_cdsp_mem>; 1572 1573 qcom,smem-states = <&smp2p_cdsp_out 0>; 1574 qcom,smem-state-names = "stop"; 1575 1576 status = "disabled"; 1577 1578 glink-edge { 1579 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1580 IPCC_MPROC_SIGNAL_GLINK_QMP 1581 IRQ_TYPE_EDGE_RISING>; 1582 mboxes = <&ipcc IPCC_CLIENT_CDSP 1583 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1584 label = "cdsp"; 1585 qcom,remote-pid = <5>; 1586 }; 1587 }; 1588 1589 sram@c125000 { 1590 compatible = "qcom,sm6375-imem", "syscon", "simple-mfd"; 1591 reg = <0 0x0c125000 0 0x1000>; 1592 ranges = <0 0 0x0c125000 0x1000>; 1593 1594 #address-cells = <1>; 1595 #size-cells = <1>; 1596 1597 pil-reloc@94c { 1598 compatible = "qcom,pil-reloc-info"; 1599 reg = <0x94c 0xc8>; 1600 }; 1601 }; 1602 1603 apps_smmu: iommu@c600000 { 1604 compatible = "qcom,sm6375-smmu-500", "arm,mmu-500"; 1605 reg = <0 0x0c600000 0 0x100000>; 1606 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1671 1672 power-domains = <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC>, 1673 <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC>, 1674 <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; 1675 #global-interrupts = <1>; 1676 #iommu-cells = <2>; 1677 }; 1678 1679 wifi: wifi@c800000 { 1680 compatible = "qcom,wcn3990-wifi"; 1681 reg = <0 0x0c800000 0 0x800000>; 1682 reg-names = "membase"; 1683 memory-region = <&pil_wlan_mem>; 1684 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1693 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1696 iommus = <&apps_smmu 0x80 0x1>; 1697 qcom,msa-fixed-perm; 1698 status = "disabled"; 1699 }; 1700 1701 intc: interrupt-controller@f200000 { 1702 compatible = "arm,gic-v3"; 1703 reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */ 1704 <0x0 0x0f240000 0x0 0x100000>; /* GICR * 8 */ 1705 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 1706 #redistributor-regions = <1>; 1707 #interrupt-cells = <3>; 1708 redistributor-stride = <0 0x20000>; 1709 interrupt-controller; 1710 }; 1711 1712 timer@f420000 { 1713 compatible = "arm,armv7-timer-mem"; 1714 reg = <0 0x0f420000 0 0x1000>; 1715 ranges = <0 0 0 0x20000000>; 1716 #address-cells = <1>; 1717 #size-cells = <1>; 1718 1719 frame@f421000 { 1720 reg = <0x0f421000 0x1000>, <0x0f422000 0x1000>; 1721 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1722 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1723 frame-number = <0>; 1724 }; 1725 1726 frame@f423000 { 1727 reg = <0x0f243000 0x1000>; 1728 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1729 frame-number = <1>; 1730 status = "disabled"; 1731 }; 1732 1733 frame@f425000 { 1734 reg = <0x0f425000 0x1000>; 1735 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1736 frame-number = <2>; 1737 status = "disabled"; 1738 }; 1739 1740 frame@f427000 { 1741 reg = <0x0f427000 0x1000>; 1742 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1743 frame-number = <3>; 1744 status = "disabled"; 1745 }; 1746 1747 frame@f429000 { 1748 reg = <0x0f429000 0x1000>; 1749 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1750 frame-number = <4>; 1751 status = "disabled"; 1752 }; 1753 1754 frame@f42b000 { 1755 reg = <0x0f42b000 0x1000>; 1756 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1757 frame-number = <5>; 1758 status = "disabled"; 1759 }; 1760 1761 frame@f42d000 { 1762 reg = <0x0f42d000 0x1000>; 1763 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1764 frame-number = <6>; 1765 status = "disabled"; 1766 }; 1767 }; 1768 1769 cpucp_l3: interconnect@fd90000 { 1770 compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3"; 1771 reg = <0 0x0fd90000 0 0x1000>; 1772 1773 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1774 clock-names = "xo", "alternate"; 1775 #interconnect-cells = <1>; 1776 }; 1777 1778 cpufreq_hw: cpufreq@fd91000 { 1779 compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss"; 1780 reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>; 1781 reg-names = "freq-domain0", "freq-domain1"; 1782 1783 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1784 clock-names = "xo", "alternate"; 1785 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1787 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; 1788 #freq-domain-cells = <1>; 1789 #clock-cells = <1>; 1790 }; 1791 }; 1792 1793 thermal-zones { 1794 mapss0-thermal { 1795 polling-delay-passive = <0>; 1796 polling-delay = <0>; 1797 1798 thermal-sensors = <&tsens0 0>; 1799 1800 trips { 1801 mapss0_alert0: trip-point0 { 1802 temperature = <90000>; 1803 hysteresis = <2000>; 1804 type = "passive"; 1805 }; 1806 1807 mapss0_alert1: trip-point1 { 1808 temperature = <95000>; 1809 hysteresis = <2000>; 1810 type = "passive"; 1811 }; 1812 1813 mapss0_crit: mapss-crit { 1814 temperature = <110000>; 1815 hysteresis = <1000>; 1816 type = "critical"; 1817 }; 1818 }; 1819 }; 1820 1821 cpu0-thermal { 1822 polling-delay-passive = <0>; 1823 polling-delay = <0>; 1824 1825 thermal-sensors = <&tsens0 1>; 1826 1827 trips { 1828 cpu0_alert0: trip-point0 { 1829 temperature = <90000>; 1830 hysteresis = <2000>; 1831 type = "passive"; 1832 }; 1833 1834 cpu0_alert1: trip-point1 { 1835 temperature = <95000>; 1836 hysteresis = <2000>; 1837 type = "passive"; 1838 }; 1839 1840 cpu0_crit: cpu-crit { 1841 temperature = <110000>; 1842 hysteresis = <1000>; 1843 type = "critical"; 1844 }; 1845 }; 1846 }; 1847 1848 cpu1-thermal { 1849 polling-delay-passive = <0>; 1850 polling-delay = <0>; 1851 1852 thermal-sensors = <&tsens0 2>; 1853 1854 trips { 1855 cpu1_alert0: trip-point0 { 1856 temperature = <90000>; 1857 hysteresis = <2000>; 1858 type = "passive"; 1859 }; 1860 1861 cpu1_alert1: trip-point1 { 1862 temperature = <95000>; 1863 hysteresis = <2000>; 1864 type = "passive"; 1865 }; 1866 1867 cpu1_crit: cpu-crit { 1868 temperature = <110000>; 1869 hysteresis = <1000>; 1870 type = "critical"; 1871 }; 1872 }; 1873 }; 1874 1875 cpu2-thermal { 1876 polling-delay-passive = <0>; 1877 polling-delay = <0>; 1878 1879 thermal-sensors = <&tsens0 3>; 1880 1881 trips { 1882 cpu2_alert0: trip-point0 { 1883 temperature = <90000>; 1884 hysteresis = <2000>; 1885 type = "passive"; 1886 }; 1887 1888 cpu2_alert1: trip-point1 { 1889 temperature = <95000>; 1890 hysteresis = <2000>; 1891 type = "passive"; 1892 }; 1893 1894 cpu2_crit: cpu-crit { 1895 temperature = <110000>; 1896 hysteresis = <1000>; 1897 type = "critical"; 1898 }; 1899 }; 1900 }; 1901 1902 cpu3-thermal { 1903 polling-delay-passive = <0>; 1904 polling-delay = <0>; 1905 1906 thermal-sensors = <&tsens0 4>; 1907 1908 trips { 1909 cpu3_alert0: trip-point0 { 1910 temperature = <90000>; 1911 hysteresis = <2000>; 1912 type = "passive"; 1913 }; 1914 1915 cpu3_alert1: trip-point1 { 1916 temperature = <95000>; 1917 hysteresis = <2000>; 1918 type = "passive"; 1919 }; 1920 1921 cpu3_crit: cpu-crit { 1922 temperature = <110000>; 1923 hysteresis = <1000>; 1924 type = "critical"; 1925 }; 1926 }; 1927 }; 1928 1929 cpu4-thermal { 1930 polling-delay-passive = <0>; 1931 polling-delay = <0>; 1932 1933 thermal-sensors = <&tsens0 5>; 1934 1935 trips { 1936 cpu4_alert0: trip-point0 { 1937 temperature = <90000>; 1938 hysteresis = <2000>; 1939 type = "passive"; 1940 }; 1941 1942 cpu4_alert1: trip-point1 { 1943 temperature = <95000>; 1944 hysteresis = <2000>; 1945 type = "passive"; 1946 }; 1947 1948 cpu4_crit: cpu-crit { 1949 temperature = <110000>; 1950 hysteresis = <1000>; 1951 type = "critical"; 1952 }; 1953 }; 1954 }; 1955 1956 cpu5-thermal { 1957 polling-delay-passive = <0>; 1958 polling-delay = <0>; 1959 1960 thermal-sensors = <&tsens0 6>; 1961 1962 trips { 1963 cpu5_alert0: trip-point0 { 1964 temperature = <90000>; 1965 hysteresis = <2000>; 1966 type = "passive"; 1967 }; 1968 1969 cpu5_alert1: trip-point1 { 1970 temperature = <95000>; 1971 hysteresis = <2000>; 1972 type = "passive"; 1973 }; 1974 1975 cpu5_crit: cpu-crit { 1976 temperature = <110000>; 1977 hysteresis = <1000>; 1978 type = "critical"; 1979 }; 1980 }; 1981 }; 1982 1983 cluster0-thermal { 1984 polling-delay-passive = <0>; 1985 polling-delay = <0>; 1986 1987 thermal-sensors = <&tsens0 7>; 1988 1989 trips { 1990 cluster0_alert0: trip-point0 { 1991 temperature = <90000>; 1992 hysteresis = <2000>; 1993 type = "passive"; 1994 }; 1995 1996 cluster0_alert1: trip-point1 { 1997 temperature = <95000>; 1998 hysteresis = <2000>; 1999 type = "passive"; 2000 }; 2001 2002 cluster0_crit: cpu-crit { 2003 temperature = <110000>; 2004 hysteresis = <1000>; 2005 type = "critical"; 2006 }; 2007 }; 2008 }; 2009 2010 cluster1-thermal { 2011 polling-delay-passive = <0>; 2012 polling-delay = <0>; 2013 2014 thermal-sensors = <&tsens0 8>; 2015 2016 trips { 2017 cluster1_alert0: trip-point0 { 2018 temperature = <90000>; 2019 hysteresis = <2000>; 2020 type = "passive"; 2021 }; 2022 2023 cluster1_alert1: trip-point1 { 2024 temperature = <95000>; 2025 hysteresis = <2000>; 2026 type = "passive"; 2027 }; 2028 2029 cluster1_crit: cpu-crit { 2030 temperature = <110000>; 2031 hysteresis = <1000>; 2032 type = "critical"; 2033 }; 2034 }; 2035 }; 2036 2037 cpu6-thermal { 2038 polling-delay-passive = <0>; 2039 polling-delay = <0>; 2040 2041 thermal-sensors = <&tsens0 9>; 2042 2043 trips { 2044 cpu6_alert0: trip-point0 { 2045 temperature = <90000>; 2046 hysteresis = <2000>; 2047 type = "passive"; 2048 }; 2049 2050 cpu6_alert1: trip-point1 { 2051 temperature = <95000>; 2052 hysteresis = <2000>; 2053 type = "passive"; 2054 }; 2055 2056 cpu6_crit: cpu-crit { 2057 temperature = <110000>; 2058 hysteresis = <1000>; 2059 type = "critical"; 2060 }; 2061 }; 2062 }; 2063 2064 cpu7-thermal { 2065 polling-delay-passive = <0>; 2066 polling-delay = <0>; 2067 2068 thermal-sensors = <&tsens0 10>; 2069 2070 trips { 2071 cpu7_alert0: trip-point0 { 2072 temperature = <90000>; 2073 hysteresis = <2000>; 2074 type = "passive"; 2075 }; 2076 2077 cpu7_alert1: trip-point1 { 2078 temperature = <95000>; 2079 hysteresis = <2000>; 2080 type = "passive"; 2081 }; 2082 2083 cpu7_crit: cpu-crit { 2084 temperature = <110000>; 2085 hysteresis = <1000>; 2086 type = "critical"; 2087 }; 2088 }; 2089 }; 2090 2091 cpu-unk0-thermal { 2092 polling-delay-passive = <0>; 2093 polling-delay = <0>; 2094 2095 thermal-sensors = <&tsens0 11>; 2096 2097 trips { 2098 cpu_unk0_alert0: trip-point0 { 2099 temperature = <90000>; 2100 hysteresis = <2000>; 2101 type = "passive"; 2102 }; 2103 2104 cpu_unk0_alert1: trip-point1 { 2105 temperature = <95000>; 2106 hysteresis = <2000>; 2107 type = "passive"; 2108 }; 2109 2110 cpu_unk0_crit: cpu-crit { 2111 temperature = <110000>; 2112 hysteresis = <1000>; 2113 type = "critical"; 2114 }; 2115 }; 2116 }; 2117 2118 cpu-unk1-thermal { 2119 polling-delay-passive = <0>; 2120 polling-delay = <0>; 2121 2122 thermal-sensors = <&tsens0 12>; 2123 2124 trips { 2125 cpu_unk1_alert0: trip-point0 { 2126 temperature = <90000>; 2127 hysteresis = <2000>; 2128 type = "passive"; 2129 }; 2130 2131 cpu_unk1_alert1: trip-point1 { 2132 temperature = <95000>; 2133 hysteresis = <2000>; 2134 type = "passive"; 2135 }; 2136 2137 cpu_unk1_crit: cpu-crit { 2138 temperature = <110000>; 2139 hysteresis = <1000>; 2140 type = "critical"; 2141 }; 2142 }; 2143 }; 2144 2145 gpuss0-thermal { 2146 polling-delay-passive = <0>; 2147 polling-delay = <0>; 2148 2149 thermal-sensors = <&tsens0 13>; 2150 2151 trips { 2152 gpuss0_alert0: trip-point0 { 2153 temperature = <90000>; 2154 hysteresis = <2000>; 2155 type = "passive"; 2156 }; 2157 2158 gpuss0_alert1: trip-point1 { 2159 temperature = <95000>; 2160 hysteresis = <2000>; 2161 type = "passive"; 2162 }; 2163 2164 gpuss0_crit: gpu-crit { 2165 temperature = <110000>; 2166 hysteresis = <1000>; 2167 type = "critical"; 2168 }; 2169 }; 2170 }; 2171 2172 gpuss1-thermal { 2173 polling-delay-passive = <0>; 2174 polling-delay = <0>; 2175 2176 thermal-sensors = <&tsens0 14>; 2177 2178 trips { 2179 gpuss1_alert0: trip-point0 { 2180 temperature = <90000>; 2181 hysteresis = <2000>; 2182 type = "passive"; 2183 }; 2184 2185 gpuss1_alert1: trip-point1 { 2186 temperature = <95000>; 2187 hysteresis = <2000>; 2188 type = "passive"; 2189 }; 2190 2191 gpuss1_crit: gpu-crit { 2192 temperature = <110000>; 2193 hysteresis = <1000>; 2194 type = "critical"; 2195 }; 2196 }; 2197 }; 2198 2199 mapss1-thermal { 2200 polling-delay-passive = <0>; 2201 polling-delay = <0>; 2202 2203 thermal-sensors = <&tsens1 0>; 2204 2205 trips { 2206 mapss1_alert0: trip-point0 { 2207 temperature = <90000>; 2208 hysteresis = <2000>; 2209 type = "passive"; 2210 }; 2211 2212 mapss1_alert1: trip-point1 { 2213 temperature = <95000>; 2214 hysteresis = <2000>; 2215 type = "passive"; 2216 }; 2217 2218 mapss1_crit: mapss-crit { 2219 temperature = <110000>; 2220 hysteresis = <1000>; 2221 type = "critical"; 2222 }; 2223 }; 2224 }; 2225 2226 cwlan-thermal { 2227 polling-delay-passive = <0>; 2228 polling-delay = <0>; 2229 2230 thermal-sensors = <&tsens1 1>; 2231 2232 trips { 2233 cwlan_alert0: trip-point0 { 2234 temperature = <90000>; 2235 hysteresis = <2000>; 2236 type = "passive"; 2237 }; 2238 2239 cwlan_alert1: trip-point1 { 2240 temperature = <95000>; 2241 hysteresis = <2000>; 2242 type = "passive"; 2243 }; 2244 2245 cwlan_crit: cwlan-crit { 2246 temperature = <110000>; 2247 hysteresis = <1000>; 2248 type = "critical"; 2249 }; 2250 }; 2251 }; 2252 2253 audio-thermal { 2254 polling-delay-passive = <0>; 2255 polling-delay = <0>; 2256 2257 thermal-sensors = <&tsens1 2>; 2258 2259 trips { 2260 audio_alert0: trip-point0 { 2261 temperature = <90000>; 2262 hysteresis = <2000>; 2263 type = "passive"; 2264 }; 2265 2266 audio_alert1: trip-point1 { 2267 temperature = <95000>; 2268 hysteresis = <2000>; 2269 type = "passive"; 2270 }; 2271 2272 audio_crit: audio-crit { 2273 temperature = <110000>; 2274 hysteresis = <1000>; 2275 type = "critical"; 2276 }; 2277 }; 2278 }; 2279 2280 ddr-thermal { 2281 polling-delay-passive = <0>; 2282 polling-delay = <0>; 2283 2284 thermal-sensors = <&tsens1 3>; 2285 2286 trips { 2287 ddr_alert0: trip-point0 { 2288 temperature = <90000>; 2289 hysteresis = <2000>; 2290 type = "passive"; 2291 }; 2292 2293 ddr_alert1: trip-point1 { 2294 temperature = <95000>; 2295 hysteresis = <2000>; 2296 type = "passive"; 2297 }; 2298 2299 ddr_crit: ddr-crit { 2300 temperature = <110000>; 2301 hysteresis = <1000>; 2302 type = "critical"; 2303 }; 2304 }; 2305 }; 2306 2307 q6hvx-thermal { 2308 polling-delay-passive = <0>; 2309 polling-delay = <0>; 2310 2311 thermal-sensors = <&tsens1 4>; 2312 2313 trips { 2314 q6hvx_alert0: trip-point0 { 2315 temperature = <90000>; 2316 hysteresis = <2000>; 2317 type = "passive"; 2318 }; 2319 2320 q6hvx_alert1: trip-point1 { 2321 temperature = <95000>; 2322 hysteresis = <2000>; 2323 type = "passive"; 2324 }; 2325 2326 q6hvx_crit: q6hvx-crit { 2327 temperature = <110000>; 2328 hysteresis = <1000>; 2329 type = "critical"; 2330 }; 2331 }; 2332 }; 2333 2334 camera-thermal { 2335 polling-delay-passive = <0>; 2336 polling-delay = <0>; 2337 2338 thermal-sensors = <&tsens1 5>; 2339 2340 trips { 2341 camera_alert0: trip-point0 { 2342 temperature = <90000>; 2343 hysteresis = <2000>; 2344 type = "passive"; 2345 }; 2346 2347 camera_alert1: trip-point1 { 2348 temperature = <95000>; 2349 hysteresis = <2000>; 2350 type = "passive"; 2351 }; 2352 2353 camera_crit: camera-crit { 2354 temperature = <110000>; 2355 hysteresis = <1000>; 2356 type = "critical"; 2357 }; 2358 }; 2359 }; 2360 2361 mdm-core0-thermal { 2362 polling-delay-passive = <0>; 2363 polling-delay = <0>; 2364 2365 thermal-sensors = <&tsens1 6>; 2366 2367 trips { 2368 mdm_core0_alert0: trip-point0 { 2369 temperature = <90000>; 2370 hysteresis = <2000>; 2371 type = "passive"; 2372 }; 2373 2374 mdm_core0_alert1: trip-point1 { 2375 temperature = <95000>; 2376 hysteresis = <2000>; 2377 type = "passive"; 2378 }; 2379 2380 mdm_core0_crit: mdm-core0-crit { 2381 temperature = <110000>; 2382 hysteresis = <1000>; 2383 type = "critical"; 2384 }; 2385 }; 2386 }; 2387 2388 mdm-core1-thermal { 2389 polling-delay-passive = <0>; 2390 polling-delay = <0>; 2391 2392 thermal-sensors = <&tsens1 7>; 2393 2394 trips { 2395 mdm_core1_alert0: trip-point0 { 2396 temperature = <90000>; 2397 hysteresis = <2000>; 2398 type = "passive"; 2399 }; 2400 2401 mdm_core1_alert1: trip-point1 { 2402 temperature = <95000>; 2403 hysteresis = <2000>; 2404 type = "passive"; 2405 }; 2406 2407 mdm_core1_crit: mdm-core1-crit { 2408 temperature = <110000>; 2409 hysteresis = <1000>; 2410 type = "critical"; 2411 }; 2412 }; 2413 }; 2414 2415 mdm-vec-thermal { 2416 polling-delay-passive = <0>; 2417 polling-delay = <0>; 2418 2419 thermal-sensors = <&tsens1 8>; 2420 2421 trips { 2422 mdm_vec_alert0: trip-point0 { 2423 temperature = <90000>; 2424 hysteresis = <2000>; 2425 type = "passive"; 2426 }; 2427 2428 mdm_vec_alert1: trip-point1 { 2429 temperature = <95000>; 2430 hysteresis = <2000>; 2431 type = "passive"; 2432 }; 2433 2434 mdm_vec_crit: mdm-vec-crit { 2435 temperature = <110000>; 2436 hysteresis = <1000>; 2437 type = "critical"; 2438 }; 2439 }; 2440 }; 2441 2442 msm-scl-thermal { 2443 polling-delay-passive = <0>; 2444 polling-delay = <0>; 2445 2446 thermal-sensors = <&tsens1 9>; 2447 2448 trips { 2449 msm_scl_alert0: trip-point0 { 2450 temperature = <90000>; 2451 hysteresis = <2000>; 2452 type = "passive"; 2453 }; 2454 2455 msm_scl_alert1: trip-point1 { 2456 temperature = <95000>; 2457 hysteresis = <2000>; 2458 type = "passive"; 2459 }; 2460 2461 msm_scl_crit: msm-scl-crit { 2462 temperature = <110000>; 2463 hysteresis = <1000>; 2464 type = "critical"; 2465 }; 2466 }; 2467 }; 2468 2469 video-thermal { 2470 polling-delay-passive = <0>; 2471 polling-delay = <0>; 2472 2473 thermal-sensors = <&tsens1 10>; 2474 2475 trips { 2476 video_alert0: trip-point0 { 2477 temperature = <90000>; 2478 hysteresis = <2000>; 2479 type = "passive"; 2480 }; 2481 2482 video_alert1: trip-point1 { 2483 temperature = <95000>; 2484 hysteresis = <2000>; 2485 type = "passive"; 2486 }; 2487 2488 video_crit: video-crit { 2489 temperature = <110000>; 2490 hysteresis = <1000>; 2491 type = "critical"; 2492 }; 2493 }; 2494 }; 2495 }; 2496 2497 timer { 2498 compatible = "arm,armv8-timer"; 2499 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2500 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2501 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2502 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2503 }; 2504}; 2505