1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/clock/qcom,sm6375-gcc.h> 8#include <dt-bindings/clock/qcom,sm6375-gpucc.h> 9#include <dt-bindings/dma/qcom-gpi.h> 10#include <dt-bindings/firmware/qcom,scm.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/mailbox/qcom-ipcc.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 clocks { 24 xo_board_clk: xo-board-clk { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 }; 28 29 sleep_clk: sleep-clk { 30 compatible = "fixed-clock"; 31 clock-frequency = <32000>; 32 #clock-cells = <0>; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 CPU0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "qcom,kryo660"; 43 reg = <0x0 0x0>; 44 clocks = <&cpufreq_hw 0>; 45 enable-method = "psci"; 46 next-level-cache = <&L2_0>; 47 qcom,freq-domain = <&cpufreq_hw 0>; 48 power-domains = <&CPU_PD0>; 49 power-domain-names = "psci"; 50 #cooling-cells = <2>; 51 L2_0: l2-cache { 52 compatible = "cache"; 53 cache-level = <2>; 54 cache-unified; 55 next-level-cache = <&L3_0>; 56 L3_0: l3-cache { 57 compatible = "cache"; 58 cache-level = <3>; 59 cache-unified; 60 }; 61 }; 62 }; 63 64 CPU1: cpu@100 { 65 device_type = "cpu"; 66 compatible = "qcom,kryo660"; 67 reg = <0x0 0x100>; 68 clocks = <&cpufreq_hw 0>; 69 enable-method = "psci"; 70 next-level-cache = <&L2_100>; 71 qcom,freq-domain = <&cpufreq_hw 0>; 72 power-domains = <&CPU_PD1>; 73 power-domain-names = "psci"; 74 #cooling-cells = <2>; 75 L2_100: l2-cache { 76 compatible = "cache"; 77 cache-level = <2>; 78 cache-unified; 79 next-level-cache = <&L3_0>; 80 }; 81 }; 82 83 CPU2: cpu@200 { 84 device_type = "cpu"; 85 compatible = "qcom,kryo660"; 86 reg = <0x0 0x200>; 87 clocks = <&cpufreq_hw 0>; 88 enable-method = "psci"; 89 next-level-cache = <&L2_200>; 90 qcom,freq-domain = <&cpufreq_hw 0>; 91 power-domains = <&CPU_PD2>; 92 power-domain-names = "psci"; 93 #cooling-cells = <2>; 94 L2_200: l2-cache { 95 compatible = "cache"; 96 cache-level = <2>; 97 cache-unified; 98 next-level-cache = <&L3_0>; 99 }; 100 }; 101 102 CPU3: cpu@300 { 103 device_type = "cpu"; 104 compatible = "qcom,kryo660"; 105 reg = <0x0 0x300>; 106 clocks = <&cpufreq_hw 0>; 107 enable-method = "psci"; 108 next-level-cache = <&L2_300>; 109 qcom,freq-domain = <&cpufreq_hw 0>; 110 power-domains = <&CPU_PD3>; 111 power-domain-names = "psci"; 112 #cooling-cells = <2>; 113 L2_300: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-unified; 117 next-level-cache = <&L3_0>; 118 }; 119 }; 120 121 CPU4: cpu@400 { 122 device_type = "cpu"; 123 compatible = "qcom,kryo660"; 124 reg = <0x0 0x400>; 125 clocks = <&cpufreq_hw 0>; 126 enable-method = "psci"; 127 next-level-cache = <&L2_400>; 128 qcom,freq-domain = <&cpufreq_hw 0>; 129 power-domains = <&CPU_PD4>; 130 power-domain-names = "psci"; 131 #cooling-cells = <2>; 132 L2_400: l2-cache { 133 compatible = "cache"; 134 cache-level = <2>; 135 cache-unified; 136 next-level-cache = <&L3_0>; 137 }; 138 }; 139 140 CPU5: cpu@500 { 141 device_type = "cpu"; 142 compatible = "qcom,kryo660"; 143 reg = <0x0 0x500>; 144 clocks = <&cpufreq_hw 0>; 145 enable-method = "psci"; 146 next-level-cache = <&L2_500>; 147 qcom,freq-domain = <&cpufreq_hw 0>; 148 power-domains = <&CPU_PD5>; 149 power-domain-names = "psci"; 150 #cooling-cells = <2>; 151 L2_500: l2-cache { 152 compatible = "cache"; 153 cache-level = <2>; 154 cache-unified; 155 next-level-cache = <&L3_0>; 156 }; 157 }; 158 159 CPU6: cpu@600 { 160 device_type = "cpu"; 161 compatible = "qcom,kryo660"; 162 reg = <0x0 0x600>; 163 clocks = <&cpufreq_hw 1>; 164 enable-method = "psci"; 165 next-level-cache = <&L2_600>; 166 qcom,freq-domain = <&cpufreq_hw 1>; 167 power-domains = <&CPU_PD6>; 168 power-domain-names = "psci"; 169 #cooling-cells = <2>; 170 L2_600: l2-cache { 171 compatible = "cache"; 172 cache-level = <2>; 173 cache-unified; 174 next-level-cache = <&L3_0>; 175 }; 176 }; 177 178 CPU7: cpu@700 { 179 device_type = "cpu"; 180 compatible = "qcom,kryo660"; 181 reg = <0x0 0x700>; 182 clocks = <&cpufreq_hw 1>; 183 enable-method = "psci"; 184 next-level-cache = <&L2_700>; 185 qcom,freq-domain = <&cpufreq_hw 1>; 186 power-domains = <&CPU_PD7>; 187 power-domain-names = "psci"; 188 #cooling-cells = <2>; 189 L2_700: l2-cache { 190 compatible = "cache"; 191 cache-level = <2>; 192 cache-unified; 193 next-level-cache = <&L3_0>; 194 }; 195 }; 196 197 cpu-map { 198 cluster0 { 199 core0 { 200 cpu = <&CPU0>; 201 }; 202 203 core1 { 204 cpu = <&CPU1>; 205 }; 206 207 core2 { 208 cpu = <&CPU2>; 209 }; 210 211 core3 { 212 cpu = <&CPU3>; 213 }; 214 215 core4 { 216 cpu = <&CPU4>; 217 }; 218 219 core5 { 220 cpu = <&CPU5>; 221 }; 222 223 core6 { 224 cpu = <&CPU6>; 225 }; 226 227 core7 { 228 cpu = <&CPU7>; 229 }; 230 }; 231 }; 232 233 idle-states { 234 entry-method = "psci"; 235 236 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 237 compatible = "arm,idle-state"; 238 idle-state-name = "silver-power-collapse"; 239 arm,psci-suspend-param = <0x40000003>; 240 entry-latency-us = <549>; 241 exit-latency-us = <901>; 242 min-residency-us = <1774>; 243 local-timer-stop; 244 }; 245 246 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 247 compatible = "arm,idle-state"; 248 idle-state-name = "silver-rail-power-collapse"; 249 arm,psci-suspend-param = <0x40000004>; 250 entry-latency-us = <702>; 251 exit-latency-us = <915>; 252 min-residency-us = <4001>; 253 local-timer-stop; 254 }; 255 256 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 257 compatible = "arm,idle-state"; 258 idle-state-name = "gold-power-collapse"; 259 arm,psci-suspend-param = <0x40000003>; 260 entry-latency-us = <523>; 261 exit-latency-us = <1244>; 262 min-residency-us = <2207>; 263 local-timer-stop; 264 }; 265 266 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 267 compatible = "arm,idle-state"; 268 idle-state-name = "gold-rail-power-collapse"; 269 arm,psci-suspend-param = <0x40000004>; 270 entry-latency-us = <526>; 271 exit-latency-us = <1854>; 272 min-residency-us = <5555>; 273 local-timer-stop; 274 }; 275 }; 276 277 domain-idle-states { 278 CLUSTER_SLEEP_0: cluster-sleep-0 { 279 compatible = "domain-idle-state"; 280 arm,psci-suspend-param = <0x41000044>; 281 entry-latency-us = <2752>; 282 exit-latency-us = <3048>; 283 min-residency-us = <6118>; 284 }; 285 }; 286 }; 287 288 firmware { 289 scm { 290 compatible = "qcom,scm-sm6375", "qcom,scm"; 291 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 292 clock-names = "core"; 293 #reset-cells = <1>; 294 }; 295 }; 296 297 memory@80000000 { 298 device_type = "memory"; 299 /* We expect the bootloader to fill in the size */ 300 reg = <0x0 0x80000000 0x0 0x0>; 301 }; 302 303 pmu { 304 compatible = "arm,armv8-pmuv3"; 305 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 306 }; 307 308 psci { 309 compatible = "arm,psci-1.0"; 310 method = "smc"; 311 312 CPU_PD0: power-domain-cpu0 { 313 #power-domain-cells = <0>; 314 power-domains = <&CLUSTER_PD>; 315 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 316 }; 317 318 CPU_PD1: power-domain-cpu1 { 319 #power-domain-cells = <0>; 320 power-domains = <&CLUSTER_PD>; 321 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 322 }; 323 324 CPU_PD2: power-domain-cpu2 { 325 #power-domain-cells = <0>; 326 power-domains = <&CLUSTER_PD>; 327 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 328 }; 329 330 CPU_PD3: power-domain-cpu3 { 331 #power-domain-cells = <0>; 332 power-domains = <&CLUSTER_PD>; 333 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 334 }; 335 336 CPU_PD4: power-domain-cpu4 { 337 #power-domain-cells = <0>; 338 power-domains = <&CLUSTER_PD>; 339 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 340 }; 341 342 CPU_PD5: power-domain-cpu5 { 343 #power-domain-cells = <0>; 344 power-domains = <&CLUSTER_PD>; 345 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 346 }; 347 348 CPU_PD6: power-domain-cpu6 { 349 #power-domain-cells = <0>; 350 power-domains = <&CLUSTER_PD>; 351 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 352 }; 353 354 CPU_PD7: power-domain-cpu7 { 355 #power-domain-cells = <0>; 356 power-domains = <&CLUSTER_PD>; 357 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 358 }; 359 360 CLUSTER_PD: power-domain-cpu-cluster0 { 361 #power-domain-cells = <0>; 362 domain-idle-states = <&CLUSTER_SLEEP_0>; 363 }; 364 }; 365 366 qup_opp_table: opp-table-qup { 367 compatible = "operating-points-v2"; 368 369 opp-75000000 { 370 opp-hz = /bits/ 64 <75000000>; 371 required-opps = <&rpmpd_opp_low_svs>; 372 }; 373 374 opp-100000000 { 375 opp-hz = /bits/ 64 <100000000>; 376 required-opps = <&rpmpd_opp_svs>; 377 }; 378 379 opp-128000000 { 380 opp-hz = /bits/ 64 <128000000>; 381 required-opps = <&rpmpd_opp_nom>; 382 }; 383 }; 384 385 reserved_memory: reserved-memory { 386 #address-cells = <2>; 387 #size-cells = <2>; 388 ranges; 389 390 hyp_mem: hypervisor@80000000 { 391 reg = <0 0x80000000 0 0x600000>; 392 no-map; 393 }; 394 395 xbl_aop_mem: xbl-aop@80700000 { 396 reg = <0 0x80700000 0 0x100000>; 397 no-map; 398 }; 399 400 reserved_xbl_uefi: xbl-uefi-res@80880000 { 401 reg = <0 0x80880000 0 0x14000>; 402 no-map; 403 }; 404 405 smem_mem: smem@80900000 { 406 compatible = "qcom,smem"; 407 reg = <0 0x80900000 0 0x200000>; 408 hwlocks = <&tcsr_mutex 3>; 409 no-map; 410 }; 411 412 fw_mem: fw@80b00000 { 413 reg = <0 0x80b00000 0 0x100000>; 414 no-map; 415 }; 416 417 cdsp_secure_heap_mem: cdsp-sec-heap@80c00000 { 418 reg = <0 0x80c00000 0 0x1e00000>; 419 no-map; 420 }; 421 422 dfps_data_mem: dpfs-data@85e00000 { 423 reg = <0 0x85e00000 0 0x100000>; 424 no-map; 425 }; 426 427 pil_wlan_mem: pil-wlan@86500000 { 428 reg = <0 0x86500000 0 0x200000>; 429 no-map; 430 }; 431 432 pil_adsp_mem: pil-adsp@86700000 { 433 reg = <0 0x86700000 0 0x2000000>; 434 no-map; 435 }; 436 437 pil_cdsp_mem: pil-cdsp@88700000 { 438 reg = <0 0x88700000 0 0x1e00000>; 439 no-map; 440 }; 441 442 pil_video_mem: pil-video@8a500000 { 443 reg = <0 0x8a500000 0 0x500000>; 444 no-map; 445 }; 446 447 pil_ipa_fw_mem: pil-ipa-fw@8aa00000 { 448 reg = <0 0x8aa00000 0 0x10000>; 449 no-map; 450 }; 451 452 pil_ipa_gsi_mem: pil-ipa-gsi@8aa10000 { 453 reg = <0 0x8aa10000 0 0xa000>; 454 no-map; 455 }; 456 457 pil_gpu_micro_code_mem: pil-gpu-ucode@8aa1a000 { 458 reg = <0 0x8aa1a000 0 0x2000>; 459 no-map; 460 }; 461 462 pil_mpss_wlan_mem: pil-mpss-wlan@8b800000 { 463 reg = <0 0x8b800000 0 0x10000000>; 464 no-map; 465 }; 466 467 removed_mem: removed@c0000000 { 468 reg = <0 0xc0000000 0 0x5100000>; 469 no-map; 470 }; 471 472 rmtfs_mem: rmtfs@f3900000 { 473 compatible = "qcom,rmtfs-mem"; 474 reg = <0 0xf3900000 0 0x280000>; 475 no-map; 476 477 qcom,client-id = <1>; 478 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 479 }; 480 481 debug_mem: debug@ffb00000 { 482 reg = <0 0xffb00000 0 0xc0000>; 483 no-map; 484 }; 485 486 last_log_mem: lastlog@ffbc0000 { 487 reg = <0 0xffbc0000 0 0x80000>; 488 no-map; 489 }; 490 491 cmdline_region: cmdline@ffd00000 { 492 reg = <0 0xffd00000 0 0x1000>; 493 no-map; 494 }; 495 }; 496 497 rpm-glink { 498 compatible = "qcom,glink-rpm"; 499 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 500 IPCC_MPROC_SIGNAL_GLINK_QMP 501 IRQ_TYPE_EDGE_RISING>; 502 qcom,rpm-msg-ram = <&rpm_msg_ram>; 503 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 504 505 rpm_requests: rpm-requests { 506 compatible = "qcom,rpm-sm6375"; 507 qcom,glink-channels = "rpm_requests"; 508 509 rpmcc: clock-controller { 510 compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc"; 511 clocks = <&xo_board_clk>; 512 clock-names = "xo"; 513 #clock-cells = <1>; 514 }; 515 516 rpmpd: power-controller { 517 compatible = "qcom,sm6375-rpmpd"; 518 #power-domain-cells = <1>; 519 operating-points-v2 = <&rpmpd_opp_table>; 520 521 rpmpd_opp_table: opp-table { 522 compatible = "operating-points-v2"; 523 524 rpmpd_opp_ret: opp1 { 525 opp-level = <RPM_SMD_LEVEL_RETENTION>; 526 }; 527 528 rpmpd_opp_min_svs: opp2 { 529 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 530 }; 531 532 rpmpd_opp_low_svs: opp3 { 533 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 534 }; 535 536 rpmpd_opp_svs: opp4 { 537 opp-level = <RPM_SMD_LEVEL_SVS>; 538 }; 539 540 rpmpd_opp_svs_plus: opp5 { 541 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 542 }; 543 544 rpmpd_opp_nom: opp6 { 545 opp-level = <RPM_SMD_LEVEL_NOM>; 546 }; 547 548 rpmpd_opp_nom_plus: opp7 { 549 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 550 }; 551 552 rpmpd_opp_turbo: opp8 { 553 opp-level = <RPM_SMD_LEVEL_TURBO>; 554 }; 555 556 rpmpd_opp_turbo_no_cpr: opp9 { 557 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 558 }; 559 }; 560 }; 561 }; 562 }; 563 564 smp2p-adsp { 565 compatible = "qcom,smp2p"; 566 qcom,smem = <443>, <429>; 567 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 568 IPCC_MPROC_SIGNAL_SMP2P 569 IRQ_TYPE_EDGE_RISING>; 570 mboxes = <&ipcc IPCC_CLIENT_LPASS 571 IPCC_MPROC_SIGNAL_SMP2P>; 572 573 qcom,local-pid = <0>; 574 qcom,remote-pid = <2>; 575 576 smp2p_adsp_out: master-kernel { 577 qcom,entry-name = "master-kernel"; 578 #qcom,smem-state-cells = <1>; 579 }; 580 581 smp2p_adsp_in: slave-kernel { 582 qcom,entry-name = "slave-kernel"; 583 interrupt-controller; 584 #interrupt-cells = <2>; 585 }; 586 }; 587 588 smp2p-cdsp { 589 compatible = "qcom,smp2p"; 590 qcom,smem = <94>, <432>; 591 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 592 IPCC_MPROC_SIGNAL_SMP2P 593 IRQ_TYPE_EDGE_RISING>; 594 mboxes = <&ipcc IPCC_CLIENT_CDSP 595 IPCC_MPROC_SIGNAL_SMP2P>; 596 597 qcom,local-pid = <0>; 598 qcom,remote-pid = <5>; 599 600 smp2p_cdsp_out: master-kernel { 601 qcom,entry-name = "master-kernel"; 602 #qcom,smem-state-cells = <1>; 603 }; 604 605 smp2p_cdsp_in: slave-kernel { 606 qcom,entry-name = "slave-kernel"; 607 interrupt-controller; 608 #interrupt-cells = <2>; 609 }; 610 }; 611 612 smp2p-modem { 613 compatible = "qcom,smp2p"; 614 qcom,smem = <435>, <428>; 615 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 616 IPCC_MPROC_SIGNAL_SMP2P 617 IRQ_TYPE_EDGE_RISING>; 618 mboxes = <&ipcc IPCC_CLIENT_MPSS 619 IPCC_MPROC_SIGNAL_SMP2P>; 620 621 qcom,local-pid = <0>; 622 qcom,remote-pid = <1>; 623 624 smp2p_modem_out: master-kernel { 625 qcom,entry-name = "master-kernel"; 626 #qcom,smem-state-cells = <1>; 627 }; 628 629 smp2p_modem_in: slave-kernel { 630 qcom,entry-name = "slave-kernel"; 631 interrupt-controller; 632 #interrupt-cells = <2>; 633 }; 634 635 ipa_smp2p_out: ipa-ap-to-modem { 636 qcom,entry-name = "ipa"; 637 #qcom,smem-state-cells = <1>; 638 }; 639 640 ipa_smp2p_in: ipa-modem-to-ap { 641 qcom,entry-name = "ipa"; 642 interrupt-controller; 643 #interrupt-cells = <2>; 644 }; 645 646 wlan_smp2p_in: wlan-wpss-to-ap { 647 qcom,entry-name = "wlan"; 648 interrupt-controller; 649 #interrupt-cells = <2>; 650 }; 651 }; 652 653 soc: soc@0 { 654 #address-cells = <2>; 655 #size-cells = <2>; 656 ranges = <0 0 0 0 0x10 0>; 657 dma-ranges = <0 0 0 0 0x10 0>; 658 compatible = "simple-bus"; 659 660 ipcc: mailbox@208000 { 661 compatible = "qcom,sm6375-ipcc", "qcom,ipcc"; 662 reg = <0 0x00208000 0 0x1000>; 663 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 664 interrupt-controller; 665 #interrupt-cells = <3>; 666 #mbox-cells = <2>; 667 }; 668 669 tcsr_mutex: hwlock@340000 { 670 compatible = "qcom,tcsr-mutex"; 671 reg = <0x0 0x00340000 0x0 0x40000>; 672 #hwlock-cells = <1>; 673 }; 674 675 tlmm: pinctrl@500000 { 676 compatible = "qcom,sm6375-tlmm"; 677 reg = <0 0x00500000 0 0x800000>; 678 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 679 gpio-ranges = <&tlmm 0 0 157>; 680 /* TODO: Hook up MPM as wakeup-parent when it's there */ 681 interrupt-controller; 682 gpio-controller; 683 #interrupt-cells = <2>; 684 #gpio-cells = <2>; 685 686 sdc2_off_state: sdc2-off-state { 687 clk-pins { 688 pins = "sdc2_clk"; 689 drive-strength = <2>; 690 bias-disable; 691 }; 692 693 cmd-pins { 694 pins = "sdc2_cmd"; 695 drive-strength = <2>; 696 bias-pull-up; 697 }; 698 699 data-pins { 700 pins = "sdc2_data"; 701 drive-strength = <2>; 702 bias-pull-up; 703 }; 704 }; 705 706 sdc2_on_state: sdc2-on-state { 707 clk-pins { 708 pins = "sdc2_clk"; 709 drive-strength = <16>; 710 bias-disable; 711 }; 712 713 cmd-pins { 714 pins = "sdc2_cmd"; 715 drive-strength = <10>; 716 bias-pull-up; 717 }; 718 719 data-pins { 720 pins = "sdc2_data"; 721 drive-strength = <10>; 722 bias-pull-up; 723 }; 724 }; 725 726 qup_i2c0_default: qup-i2c0-default-state { 727 pins = "gpio0", "gpio1"; 728 function = "qup00"; 729 drive-strength = <2>; 730 bias-pull-up; 731 }; 732 733 qup_i2c1_default: qup-i2c1-default-state { 734 pins = "gpio61", "gpio62"; 735 function = "qup01"; 736 drive-strength = <2>; 737 bias-pull-up; 738 }; 739 740 qup_i2c2_default: qup-i2c2-default-state { 741 pins = "gpio45", "gpio46"; 742 function = "qup02"; 743 drive-strength = <2>; 744 bias-pull-up; 745 }; 746 747 qup_i2c8_default: qup-i2c8-default-state { 748 pins = "gpio19", "gpio20"; 749 /* TLMM, GCC and vendor DT all have different indices.. */ 750 function = "qup12"; 751 drive-strength = <2>; 752 bias-pull-up; 753 }; 754 755 qup_i2c10_default: qup-i2c10-default-state { 756 pins = "gpio4", "gpio5"; 757 function = "qup10"; 758 drive-strength = <2>; 759 bias-pull-up; 760 }; 761 762 qup_spi0_default: qup-spi0-default-state { 763 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 764 function = "qup00"; 765 drive-strength = <6>; 766 bias-disable; 767 }; 768 }; 769 770 gcc: clock-controller@1400000 { 771 compatible = "qcom,sm6375-gcc"; 772 reg = <0 0x01400000 0 0x1f0000>; 773 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 774 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 775 <&sleep_clk>; 776 #power-domain-cells = <1>; 777 #clock-cells = <1>; 778 #reset-cells = <1>; 779 }; 780 781 usb_1_hsphy: phy@162b000 { 782 compatible = "qcom,sm6375-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; 783 reg = <0 0x0162b000 0 0x400>; 784 785 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 786 clock-names = "ref"; 787 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 788 #phy-cells = <0>; 789 790 status = "disabled"; 791 }; 792 793 spmi_bus: spmi@1c40000 { 794 compatible = "qcom,spmi-pmic-arb"; 795 reg = <0 0x01c40000 0 0x1100>, 796 <0 0x01e00000 0 0x2000000>, 797 <0 0x03e00000 0 0x100000>, 798 <0 0x03f00000 0 0xa0000>, 799 <0 0x01c0a000 0 0x26000>; 800 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 801 interrupt-names = "periph_irq"; 802 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 803 qcom,ee = <0>; 804 qcom,channel = <0>; 805 #address-cells = <2>; 806 #size-cells = <0>; 807 interrupt-controller; 808 #interrupt-cells = <4>; 809 }; 810 811 tsens0: thermal-sensor@4411000 { 812 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2"; 813 reg = <0 0x04411000 0 0x140>, /* TM */ 814 <0 0x04410000 0 0x20>; /* SROT */ 815 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 817 interrupt-names = "uplow", "critical"; 818 #thermal-sensor-cells = <1>; 819 #qcom,sensors = <15>; 820 }; 821 822 tsens1: thermal-sensor@4413000 { 823 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2"; 824 reg = <0 0x04413000 0 0x140>, /* TM */ 825 <0 0x04412000 0 0x20>; /* SROT */ 826 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 828 interrupt-names = "uplow", "critical"; 829 #thermal-sensor-cells = <1>; 830 #qcom,sensors = <11>; 831 }; 832 833 rpm_msg_ram: sram@45f0000 { 834 compatible = "qcom,rpm-msg-ram"; 835 reg = <0 0x045f0000 0 0x7000>; 836 }; 837 838 sram@4690000 { 839 compatible = "qcom,rpm-stats"; 840 reg = <0 0x04690000 0 0x400>; 841 }; 842 843 sdhc_2: mmc@4784000 { 844 compatible = "qcom,sm6375-sdhci", "qcom,sdhci-msm-v5"; 845 reg = <0 0x04784000 0 0x1000>; 846 847 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 849 interrupt-names = "hc_irq", "pwr_irq"; 850 851 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 852 <&gcc GCC_SDCC2_APPS_CLK>, 853 <&rpmcc RPM_SMD_XO_CLK_SRC>; 854 clock-names = "iface", "core", "xo"; 855 resets = <&gcc GCC_SDCC2_BCR>; 856 iommus = <&apps_smmu 0x40 0x0>; 857 858 pinctrl-0 = <&sdc2_on_state>; 859 pinctrl-1 = <&sdc2_off_state>; 860 pinctrl-names = "default", "sleep"; 861 862 qcom,dll-config = <0x0007642c>; 863 qcom,ddr-config = <0x80040868>; 864 power-domains = <&rpmpd SM6375_VDDCX>; 865 operating-points-v2 = <&sdhc2_opp_table>; 866 bus-width = <4>; 867 868 status = "disabled"; 869 870 sdhc2_opp_table: opp-table { 871 compatible = "operating-points-v2"; 872 873 opp-100000000 { 874 opp-hz = /bits/ 64 <100000000>; 875 required-opps = <&rpmpd_opp_low_svs>; 876 }; 877 878 opp-202000000 { 879 opp-hz = /bits/ 64 <202000000>; 880 required-opps = <&rpmpd_opp_svs_plus>; 881 }; 882 }; 883 }; 884 885 gpi_dma0: dma-controller@4a00000 { 886 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; 887 reg = <0 0x04a00000 0 0x60000>; 888 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 898 dma-channels = <10>; 899 dma-channel-mask = <0x1f>; 900 iommus = <&apps_smmu 0x16 0x0>; 901 #dma-cells = <3>; 902 status = "disabled"; 903 }; 904 905 qupv3_id_0: geniqup@4ac0000 { 906 compatible = "qcom,geni-se-qup"; 907 reg = <0x0 0x04ac0000 0x0 0x2000>; 908 clock-names = "m-ahb", "s-ahb"; 909 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 910 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 911 iommus = <&apps_smmu 0x3 0x0>; 912 #address-cells = <2>; 913 #size-cells = <2>; 914 ranges; 915 status = "disabled"; 916 917 i2c0: i2c@4a80000 { 918 compatible = "qcom,geni-i2c"; 919 reg = <0x0 0x04a80000 0x0 0x4000>; 920 clock-names = "se"; 921 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 922 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 923 pinctrl-names = "default"; 924 pinctrl-0 = <&qup_i2c0_default>; 925 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 926 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 927 dma-names = "tx", "rx"; 928 #address-cells = <1>; 929 #size-cells = <0>; 930 status = "disabled"; 931 }; 932 933 spi0: spi@4a80000 { 934 compatible = "qcom,geni-spi"; 935 reg = <0x0 0x04a80000 0x0 0x4000>; 936 clock-names = "se"; 937 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 938 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 939 pinctrl-names = "default"; 940 pinctrl-0 = <&qup_spi0_default>; 941 power-domains = <&rpmpd SM6375_VDDCX>; 942 operating-points-v2 = <&qup_opp_table>; 943 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 944 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 945 dma-names = "tx", "rx"; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 status = "disabled"; 949 }; 950 951 i2c1: i2c@4a84000 { 952 compatible = "qcom,geni-i2c"; 953 reg = <0x0 0x04a84000 0x0 0x4000>; 954 clock-names = "se"; 955 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 956 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 957 pinctrl-names = "default"; 958 pinctrl-0 = <&qup_i2c1_default>; 959 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 960 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 961 dma-names = "tx", "rx"; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 status = "disabled"; 965 }; 966 967 spi1: spi@4a84000 { 968 compatible = "qcom,geni-spi"; 969 reg = <0x0 0x04a84000 0x0 0x4000>; 970 clock-names = "se"; 971 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 972 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 973 power-domains = <&rpmpd SM6375_VDDCX>; 974 operating-points-v2 = <&qup_opp_table>; 975 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 976 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 977 dma-names = "tx", "rx"; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 status = "disabled"; 981 }; 982 983 i2c2: i2c@4a88000 { 984 compatible = "qcom,geni-i2c"; 985 reg = <0x0 0x04a88000 0x0 0x4000>; 986 clock-names = "se"; 987 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 988 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 989 pinctrl-names = "default"; 990 pinctrl-0 = <&qup_i2c2_default>; 991 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 992 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 993 dma-names = "tx", "rx"; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 status = "disabled"; 997 }; 998 999 spi2: spi@4a88000 { 1000 compatible = "qcom,geni-spi"; 1001 reg = <0x0 0x04a88000 0x0 0x4000>; 1002 clock-names = "se"; 1003 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1004 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1005 power-domains = <&rpmpd SM6375_VDDCX>; 1006 operating-points-v2 = <&qup_opp_table>; 1007 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1008 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1009 dma-names = "tx", "rx"; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 status = "disabled"; 1013 }; 1014 1015 /* 1016 * As per GCC, QUP3/4/5/11 also exist, but are not even defined downstream. 1017 * There is a comment in the included DTSI of another SoC saying that they 1018 * are not "bolled out" (probably meaning not routed to solder balls) 1019 * TLMM driver however, suggests there are as many as 15 QUPs in total! 1020 * Most of which don't even have pin configurations for.. Sad stuff! 1021 */ 1022 }; 1023 1024 gpi_dma1: dma-controller@4c00000 { 1025 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; 1026 reg = <0 0x04c00000 0 0x60000>; 1027 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 1037 dma-channels = <10>; 1038 dma-channel-mask = <0x1f>; 1039 iommus = <&apps_smmu 0xd6 0x0>; 1040 #dma-cells = <3>; 1041 status = "disabled"; 1042 }; 1043 1044 qupv3_id_1: geniqup@4cc0000 { 1045 compatible = "qcom,geni-se-qup"; 1046 reg = <0x0 0x04cc0000 0x0 0x2000>; 1047 clock-names = "m-ahb", "s-ahb"; 1048 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1049 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1050 iommus = <&apps_smmu 0xc3 0x0>; 1051 #address-cells = <2>; 1052 #size-cells = <2>; 1053 ranges; 1054 status = "disabled"; 1055 1056 i2c6: i2c@4c80000 { 1057 compatible = "qcom,geni-i2c"; 1058 reg = <0x0 0x04c80000 0x0 0x4000>; 1059 clock-names = "se"; 1060 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1061 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; 1062 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1063 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1064 dma-names = "tx", "rx"; 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 status = "disabled"; 1068 }; 1069 1070 spi6: spi@4c80000 { 1071 compatible = "qcom,geni-spi"; 1072 reg = <0x0 0x04c80000 0x0 0x4000>; 1073 clock-names = "se"; 1074 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1075 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; 1076 power-domains = <&rpmpd SM6375_VDDCX>; 1077 operating-points-v2 = <&qup_opp_table>; 1078 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1079 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1080 dma-names = "tx", "rx"; 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 status = "disabled"; 1084 }; 1085 1086 i2c7: i2c@4c84000 { 1087 compatible = "qcom,geni-i2c"; 1088 reg = <0x0 0x04c84000 0x0 0x4000>; 1089 clock-names = "se"; 1090 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1091 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1092 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1093 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1094 dma-names = "tx", "rx"; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 status = "disabled"; 1098 }; 1099 1100 spi7: spi@4c84000 { 1101 compatible = "qcom,geni-spi"; 1102 reg = <0x0 0x04c84000 0x0 0x4000>; 1103 clock-names = "se"; 1104 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1105 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1106 power-domains = <&rpmpd SM6375_VDDCX>; 1107 operating-points-v2 = <&qup_opp_table>; 1108 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1109 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1110 dma-names = "tx", "rx"; 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 status = "disabled"; 1114 }; 1115 1116 i2c8: i2c@4c88000 { 1117 compatible = "qcom,geni-i2c"; 1118 reg = <0x0 0x04c88000 0x0 0x4000>; 1119 clock-names = "se"; 1120 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1121 interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1122 pinctrl-names = "default"; 1123 pinctrl-0 = <&qup_i2c8_default>; 1124 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1125 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1126 dma-names = "tx", "rx"; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 status = "disabled"; 1130 }; 1131 1132 spi8: spi@4c88000 { 1133 compatible = "qcom,geni-spi"; 1134 reg = <0x0 0x04c88000 0x0 0x4000>; 1135 clock-names = "se"; 1136 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1137 interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1138 power-domains = <&rpmpd SM6375_VDDCX>; 1139 operating-points-v2 = <&qup_opp_table>; 1140 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1141 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1142 dma-names = "tx", "rx"; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 status = "disabled"; 1146 }; 1147 1148 i2c9: i2c@4c8c000 { 1149 compatible = "qcom,geni-i2c"; 1150 reg = <0x0 0x04c8c000 0x0 0x4000>; 1151 clock-names = "se"; 1152 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1153 interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>; 1154 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1155 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1156 dma-names = "tx", "rx"; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 status = "disabled"; 1160 }; 1161 1162 spi9: spi@4c8c000 { 1163 compatible = "qcom,geni-spi"; 1164 reg = <0x0 0x04c8c000 0x0 0x4000>; 1165 clock-names = "se"; 1166 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1167 interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>; 1168 power-domains = <&rpmpd SM6375_VDDCX>; 1169 operating-points-v2 = <&qup_opp_table>; 1170 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1171 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1172 dma-names = "tx", "rx"; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 status = "disabled"; 1176 }; 1177 1178 i2c10: i2c@4c90000 { 1179 compatible = "qcom,geni-i2c"; 1180 reg = <0x0 0x04c90000 0x0 0x4000>; 1181 clock-names = "se"; 1182 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1183 interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>; 1184 pinctrl-names = "default"; 1185 pinctrl-0 = <&qup_i2c10_default>; 1186 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1187 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1188 dma-names = "tx", "rx"; 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 status = "disabled"; 1192 }; 1193 1194 spi10: spi@4c90000 { 1195 compatible = "qcom,geni-spi"; 1196 reg = <0x0 0x04c90000 0x0 0x4000>; 1197 clock-names = "se"; 1198 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1199 interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>; 1200 power-domains = <&rpmpd SM6375_VDDCX>; 1201 operating-points-v2 = <&qup_opp_table>; 1202 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1203 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1204 dma-names = "tx", "rx"; 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 status = "disabled"; 1208 }; 1209 }; 1210 1211 usb_1: usb@4ef8800 { 1212 compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; 1213 reg = <0 0x04ef8800 0 0x400>; 1214 1215 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1216 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1217 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1218 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1219 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1220 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1221 clock-names = "cfg_noc", 1222 "core", 1223 "iface", 1224 "sleep", 1225 "mock_utmi", 1226 "xo"; 1227 1228 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1229 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1230 assigned-clock-rates = <19200000>, <133333333>; 1231 1232 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1236 interrupt-names = "hs_phy_irq", 1237 "ss_phy_irq", 1238 "dm_hs_phy_irq", 1239 "dp_hs_phy_irq"; 1240 1241 power-domains = <&gcc USB30_PRIM_GDSC>; 1242 1243 resets = <&gcc GCC_USB30_PRIM_BCR>; 1244 1245 /* 1246 * This property is there to allow USB2 to work, as 1247 * USB3 is not implemented yet - (re)move it when 1248 * proper support is in place. 1249 */ 1250 qcom,select-utmi-as-pipe-clk; 1251 1252 #address-cells = <2>; 1253 #size-cells = <2>; 1254 ranges; 1255 1256 status = "disabled"; 1257 1258 usb_1_dwc3: usb@4e00000 { 1259 compatible = "snps,dwc3"; 1260 reg = <0 0x04e00000 0 0xcd00>; 1261 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1262 maximum-speed = "high-speed"; 1263 phys = <&usb_1_hsphy>; 1264 phy-names = "usb2-phy"; 1265 iommus = <&apps_smmu 0xe0 0x0>; 1266 1267 /* Yes, this impl *does* have an unfunny number of quirks.. */ 1268 snps,hird-threshold = /bits/ 8 <0x10>; 1269 snps,usb2-gadget-lpm-disable; 1270 snps,dis_u2_susphy_quirk; 1271 snps,is-utmi-l1-suspend; 1272 snps,dis-u1-entry-quirk; 1273 snps,dis-u2-entry-quirk; 1274 snps,usb3_lpm_capable; 1275 snps,has-lpm-erratum; 1276 tx-fifo-resize; 1277 }; 1278 }; 1279 1280 adreno_smmu: iommu@5940000 { 1281 compatible = "qcom,sm6375-smmu-v2", "qcom,smmu-v2"; 1282 reg = <0 0x05940000 0 0x10000>; 1283 #iommu-cells = <1>; 1284 #global-interrupts = <2>; 1285 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 1286 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 1287 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 1288 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 1290 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1295 1296 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1297 clock-names = "bus"; 1298 1299 power-domains = <&gpucc GPU_CX_GDSC>; 1300 }; 1301 1302 gpucc: clock-controller@5990000 { 1303 compatible = "qcom,sm6375-gpucc"; 1304 reg = <0 0x05990000 0 0x9000>; 1305 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1306 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1307 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, 1308 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1309 power-domains = <&rpmpd SM6375_VDDGX>; 1310 required-opps = <&rpmpd_opp_low_svs>; 1311 #clock-cells = <1>; 1312 #reset-cells = <1>; 1313 #power-domain-cells = <1>; 1314 }; 1315 1316 remoteproc_mss: remoteproc@6000000 { 1317 compatible = "qcom,sm6375-mpss-pas"; 1318 reg = <0 0x06000000 0 0x4040>; 1319 1320 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1321 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1322 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1323 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1324 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1325 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1326 interrupt-names = "wdog", 1327 "fatal", 1328 "ready", 1329 "handover", 1330 "stop-ack", 1331 "shutdown-ack"; 1332 1333 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1334 clock-names = "xo"; 1335 1336 power-domains = <&rpmpd SM6375_VDDCX>; 1337 power-domain-names = "cx"; 1338 1339 memory-region = <&pil_mpss_wlan_mem>; 1340 1341 qcom,smem-states = <&smp2p_modem_out 0>; 1342 qcom,smem-state-names = "stop"; 1343 1344 status = "disabled"; 1345 1346 glink-edge { 1347 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1348 IPCC_MPROC_SIGNAL_GLINK_QMP 1349 IRQ_TYPE_EDGE_RISING>; 1350 mboxes = <&ipcc IPCC_CLIENT_MPSS 1351 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1352 label = "modem"; 1353 qcom,remote-pid = <1>; 1354 }; 1355 }; 1356 1357 remoteproc_adsp: remoteproc@a400000 { 1358 compatible = "qcom,sm6375-adsp-pas"; 1359 reg = <0 0x0a400000 0 0x100>; 1360 1361 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1362 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1363 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1364 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1365 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1366 interrupt-names = "wdog", "fatal", "ready", 1367 "handover", "stop-ack"; 1368 1369 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1370 clock-names = "xo"; 1371 1372 power-domains = <&rpmpd SM6375_VDD_LPI_CX>, 1373 <&rpmpd SM6375_VDD_LPI_MX>; 1374 power-domain-names = "lcx", "lmx"; 1375 1376 memory-region = <&pil_adsp_mem>; 1377 1378 qcom,smem-states = <&smp2p_adsp_out 0>; 1379 qcom,smem-state-names = "stop"; 1380 1381 status = "disabled"; 1382 1383 glink-edge { 1384 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1385 IPCC_MPROC_SIGNAL_GLINK_QMP 1386 IRQ_TYPE_EDGE_RISING>; 1387 mboxes = <&ipcc IPCC_CLIENT_LPASS 1388 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1389 1390 label = "lpass"; 1391 qcom,remote-pid = <2>; 1392 }; 1393 }; 1394 1395 remoteproc_cdsp: remoteproc@b000000 { 1396 compatible = "qcom,sm6375-cdsp-pas"; 1397 reg = <0x0 0x0b000000 0x0 0x100000>; 1398 1399 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 1400 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1401 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1402 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1403 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1404 interrupt-names = "wdog", "fatal", "ready", 1405 "handover", "stop-ack"; 1406 1407 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1408 clock-names = "xo"; 1409 1410 power-domains = <&rpmpd SM6375_VDDCX>; 1411 power-domain-names = "cx"; 1412 1413 memory-region = <&pil_cdsp_mem>; 1414 1415 qcom,smem-states = <&smp2p_cdsp_out 0>; 1416 qcom,smem-state-names = "stop"; 1417 1418 status = "disabled"; 1419 1420 glink-edge { 1421 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1422 IPCC_MPROC_SIGNAL_GLINK_QMP 1423 IRQ_TYPE_EDGE_RISING>; 1424 mboxes = <&ipcc IPCC_CLIENT_CDSP 1425 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1426 label = "cdsp"; 1427 qcom,remote-pid = <5>; 1428 }; 1429 }; 1430 1431 sram@c125000 { 1432 compatible = "qcom,sm6375-imem", "syscon", "simple-mfd"; 1433 reg = <0 0x0c125000 0 0x1000>; 1434 ranges = <0 0 0x0c125000 0x1000>; 1435 1436 #address-cells = <1>; 1437 #size-cells = <1>; 1438 1439 pil-reloc@94c { 1440 compatible = "qcom,pil-reloc-info"; 1441 reg = <0x94c 0xc8>; 1442 }; 1443 }; 1444 1445 apps_smmu: iommu@c600000 { 1446 compatible = "qcom,sm6375-smmu-500", "arm,mmu-500"; 1447 reg = <0 0x0c600000 0 0x100000>; 1448 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1513 1514 power-domains = <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC>, 1515 <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC>, 1516 <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; 1517 #global-interrupts = <1>; 1518 #iommu-cells = <2>; 1519 }; 1520 1521 wifi: wifi@c800000 { 1522 compatible = "qcom,wcn3990-wifi"; 1523 reg = <0 0x0c800000 0 0x800000>; 1524 reg-names = "membase"; 1525 memory-region = <&pil_wlan_mem>; 1526 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1538 iommus = <&apps_smmu 0x80 0x1>; 1539 qcom,msa-fixed-perm; 1540 status = "disabled"; 1541 }; 1542 1543 intc: interrupt-controller@f200000 { 1544 compatible = "arm,gic-v3"; 1545 reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */ 1546 <0x0 0x0f240000 0x0 0x100000>; /* GICR * 8 */ 1547 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 1548 #redistributor-regions = <1>; 1549 #interrupt-cells = <3>; 1550 redistributor-stride = <0 0x20000>; 1551 interrupt-controller; 1552 }; 1553 1554 timer@f420000 { 1555 compatible = "arm,armv7-timer-mem"; 1556 reg = <0 0x0f420000 0 0x1000>; 1557 ranges = <0 0 0 0x20000000>; 1558 #address-cells = <1>; 1559 #size-cells = <1>; 1560 1561 frame@f421000 { 1562 reg = <0x0f421000 0x1000>, <0x0f422000 0x1000>; 1563 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1565 frame-number = <0>; 1566 }; 1567 1568 frame@f423000 { 1569 reg = <0x0f243000 0x1000>; 1570 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1571 frame-number = <1>; 1572 status = "disabled"; 1573 }; 1574 1575 frame@f425000 { 1576 reg = <0x0f425000 0x1000>; 1577 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1578 frame-number = <2>; 1579 status = "disabled"; 1580 }; 1581 1582 frame@f427000 { 1583 reg = <0x0f427000 0x1000>; 1584 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1585 frame-number = <3>; 1586 status = "disabled"; 1587 }; 1588 1589 frame@f429000 { 1590 reg = <0x0f429000 0x1000>; 1591 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1592 frame-number = <4>; 1593 status = "disabled"; 1594 }; 1595 1596 frame@f42b000 { 1597 reg = <0x0f42b000 0x1000>; 1598 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1599 frame-number = <5>; 1600 status = "disabled"; 1601 }; 1602 1603 frame@f42d000 { 1604 reg = <0x0f42d000 0x1000>; 1605 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1606 frame-number = <6>; 1607 status = "disabled"; 1608 }; 1609 }; 1610 1611 cpucp_l3: interconnect@fd90000 { 1612 compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3"; 1613 reg = <0 0x0fd90000 0 0x1000>; 1614 1615 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1616 clock-names = "xo", "alternate"; 1617 #interconnect-cells = <1>; 1618 }; 1619 1620 cpufreq_hw: cpufreq@fd91000 { 1621 compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss"; 1622 reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>; 1623 reg-names = "freq-domain0", "freq-domain1"; 1624 1625 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1626 clock-names = "xo", "alternate"; 1627 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1629 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; 1630 #freq-domain-cells = <1>; 1631 #clock-cells = <1>; 1632 }; 1633 }; 1634 1635 thermal-zones { 1636 mapss0-thermal { 1637 polling-delay-passive = <0>; 1638 polling-delay = <0>; 1639 1640 thermal-sensors = <&tsens0 0>; 1641 1642 trips { 1643 mapss0_alert0: trip-point0 { 1644 temperature = <90000>; 1645 hysteresis = <2000>; 1646 type = "passive"; 1647 }; 1648 1649 mapss0_alert1: trip-point1 { 1650 temperature = <95000>; 1651 hysteresis = <2000>; 1652 type = "passive"; 1653 }; 1654 1655 mapss0_crit: mapss-crit { 1656 temperature = <110000>; 1657 hysteresis = <1000>; 1658 type = "critical"; 1659 }; 1660 }; 1661 }; 1662 1663 cpu0-thermal { 1664 polling-delay-passive = <0>; 1665 polling-delay = <0>; 1666 1667 thermal-sensors = <&tsens0 1>; 1668 1669 trips { 1670 cpu0_alert0: trip-point0 { 1671 temperature = <90000>; 1672 hysteresis = <2000>; 1673 type = "passive"; 1674 }; 1675 1676 cpu0_alert1: trip-point1 { 1677 temperature = <95000>; 1678 hysteresis = <2000>; 1679 type = "passive"; 1680 }; 1681 1682 cpu0_crit: cpu-crit { 1683 temperature = <110000>; 1684 hysteresis = <1000>; 1685 type = "critical"; 1686 }; 1687 }; 1688 }; 1689 1690 cpu1-thermal { 1691 polling-delay-passive = <0>; 1692 polling-delay = <0>; 1693 1694 thermal-sensors = <&tsens0 2>; 1695 1696 trips { 1697 cpu1_alert0: trip-point0 { 1698 temperature = <90000>; 1699 hysteresis = <2000>; 1700 type = "passive"; 1701 }; 1702 1703 cpu1_alert1: trip-point1 { 1704 temperature = <95000>; 1705 hysteresis = <2000>; 1706 type = "passive"; 1707 }; 1708 1709 cpu1_crit: cpu-crit { 1710 temperature = <110000>; 1711 hysteresis = <1000>; 1712 type = "critical"; 1713 }; 1714 }; 1715 }; 1716 1717 cpu2-thermal { 1718 polling-delay-passive = <0>; 1719 polling-delay = <0>; 1720 1721 thermal-sensors = <&tsens0 3>; 1722 1723 trips { 1724 cpu2_alert0: trip-point0 { 1725 temperature = <90000>; 1726 hysteresis = <2000>; 1727 type = "passive"; 1728 }; 1729 1730 cpu2_alert1: trip-point1 { 1731 temperature = <95000>; 1732 hysteresis = <2000>; 1733 type = "passive"; 1734 }; 1735 1736 cpu2_crit: cpu-crit { 1737 temperature = <110000>; 1738 hysteresis = <1000>; 1739 type = "critical"; 1740 }; 1741 }; 1742 }; 1743 1744 cpu3-thermal { 1745 polling-delay-passive = <0>; 1746 polling-delay = <0>; 1747 1748 thermal-sensors = <&tsens0 4>; 1749 1750 trips { 1751 cpu3_alert0: trip-point0 { 1752 temperature = <90000>; 1753 hysteresis = <2000>; 1754 type = "passive"; 1755 }; 1756 1757 cpu3_alert1: trip-point1 { 1758 temperature = <95000>; 1759 hysteresis = <2000>; 1760 type = "passive"; 1761 }; 1762 1763 cpu3_crit: cpu-crit { 1764 temperature = <110000>; 1765 hysteresis = <1000>; 1766 type = "critical"; 1767 }; 1768 }; 1769 }; 1770 1771 cpu4-thermal { 1772 polling-delay-passive = <0>; 1773 polling-delay = <0>; 1774 1775 thermal-sensors = <&tsens0 5>; 1776 1777 trips { 1778 cpu4_alert0: trip-point0 { 1779 temperature = <90000>; 1780 hysteresis = <2000>; 1781 type = "passive"; 1782 }; 1783 1784 cpu4_alert1: trip-point1 { 1785 temperature = <95000>; 1786 hysteresis = <2000>; 1787 type = "passive"; 1788 }; 1789 1790 cpu4_crit: cpu-crit { 1791 temperature = <110000>; 1792 hysteresis = <1000>; 1793 type = "critical"; 1794 }; 1795 }; 1796 }; 1797 1798 cpu5-thermal { 1799 polling-delay-passive = <0>; 1800 polling-delay = <0>; 1801 1802 thermal-sensors = <&tsens0 6>; 1803 1804 trips { 1805 cpu5_alert0: trip-point0 { 1806 temperature = <90000>; 1807 hysteresis = <2000>; 1808 type = "passive"; 1809 }; 1810 1811 cpu5_alert1: trip-point1 { 1812 temperature = <95000>; 1813 hysteresis = <2000>; 1814 type = "passive"; 1815 }; 1816 1817 cpu5_crit: cpu-crit { 1818 temperature = <110000>; 1819 hysteresis = <1000>; 1820 type = "critical"; 1821 }; 1822 }; 1823 }; 1824 1825 cluster0-thermal { 1826 polling-delay-passive = <0>; 1827 polling-delay = <0>; 1828 1829 thermal-sensors = <&tsens0 7>; 1830 1831 trips { 1832 cluster0_alert0: trip-point0 { 1833 temperature = <90000>; 1834 hysteresis = <2000>; 1835 type = "passive"; 1836 }; 1837 1838 cluster0_alert1: trip-point1 { 1839 temperature = <95000>; 1840 hysteresis = <2000>; 1841 type = "passive"; 1842 }; 1843 1844 cluster0_crit: cpu-crit { 1845 temperature = <110000>; 1846 hysteresis = <1000>; 1847 type = "critical"; 1848 }; 1849 }; 1850 }; 1851 1852 cluster1-thermal { 1853 polling-delay-passive = <0>; 1854 polling-delay = <0>; 1855 1856 thermal-sensors = <&tsens0 8>; 1857 1858 trips { 1859 cluster1_alert0: trip-point0 { 1860 temperature = <90000>; 1861 hysteresis = <2000>; 1862 type = "passive"; 1863 }; 1864 1865 cluster1_alert1: trip-point1 { 1866 temperature = <95000>; 1867 hysteresis = <2000>; 1868 type = "passive"; 1869 }; 1870 1871 cluster1_crit: cpu-crit { 1872 temperature = <110000>; 1873 hysteresis = <1000>; 1874 type = "critical"; 1875 }; 1876 }; 1877 }; 1878 1879 cpu6-thermal { 1880 polling-delay-passive = <0>; 1881 polling-delay = <0>; 1882 1883 thermal-sensors = <&tsens0 9>; 1884 1885 trips { 1886 cpu6_alert0: trip-point0 { 1887 temperature = <90000>; 1888 hysteresis = <2000>; 1889 type = "passive"; 1890 }; 1891 1892 cpu6_alert1: trip-point1 { 1893 temperature = <95000>; 1894 hysteresis = <2000>; 1895 type = "passive"; 1896 }; 1897 1898 cpu6_crit: cpu-crit { 1899 temperature = <110000>; 1900 hysteresis = <1000>; 1901 type = "critical"; 1902 }; 1903 }; 1904 }; 1905 1906 cpu7-thermal { 1907 polling-delay-passive = <0>; 1908 polling-delay = <0>; 1909 1910 thermal-sensors = <&tsens0 10>; 1911 1912 trips { 1913 cpu7_alert0: trip-point0 { 1914 temperature = <90000>; 1915 hysteresis = <2000>; 1916 type = "passive"; 1917 }; 1918 1919 cpu7_alert1: trip-point1 { 1920 temperature = <95000>; 1921 hysteresis = <2000>; 1922 type = "passive"; 1923 }; 1924 1925 cpu7_crit: cpu-crit { 1926 temperature = <110000>; 1927 hysteresis = <1000>; 1928 type = "critical"; 1929 }; 1930 }; 1931 }; 1932 1933 cpu-unk0-thermal { 1934 polling-delay-passive = <0>; 1935 polling-delay = <0>; 1936 1937 thermal-sensors = <&tsens0 11>; 1938 1939 trips { 1940 cpu_unk0_alert0: trip-point0 { 1941 temperature = <90000>; 1942 hysteresis = <2000>; 1943 type = "passive"; 1944 }; 1945 1946 cpu_unk0_alert1: trip-point1 { 1947 temperature = <95000>; 1948 hysteresis = <2000>; 1949 type = "passive"; 1950 }; 1951 1952 cpu_unk0_crit: cpu-crit { 1953 temperature = <110000>; 1954 hysteresis = <1000>; 1955 type = "critical"; 1956 }; 1957 }; 1958 }; 1959 1960 cpu-unk1-thermal { 1961 polling-delay-passive = <0>; 1962 polling-delay = <0>; 1963 1964 thermal-sensors = <&tsens0 12>; 1965 1966 trips { 1967 cpu_unk1_alert0: trip-point0 { 1968 temperature = <90000>; 1969 hysteresis = <2000>; 1970 type = "passive"; 1971 }; 1972 1973 cpu_unk1_alert1: trip-point1 { 1974 temperature = <95000>; 1975 hysteresis = <2000>; 1976 type = "passive"; 1977 }; 1978 1979 cpu_unk1_crit: cpu-crit { 1980 temperature = <110000>; 1981 hysteresis = <1000>; 1982 type = "critical"; 1983 }; 1984 }; 1985 }; 1986 1987 gpuss0-thermal { 1988 polling-delay-passive = <0>; 1989 polling-delay = <0>; 1990 1991 thermal-sensors = <&tsens0 13>; 1992 1993 trips { 1994 gpuss0_alert0: trip-point0 { 1995 temperature = <90000>; 1996 hysteresis = <2000>; 1997 type = "passive"; 1998 }; 1999 2000 gpuss0_alert1: trip-point1 { 2001 temperature = <95000>; 2002 hysteresis = <2000>; 2003 type = "passive"; 2004 }; 2005 2006 gpuss0_crit: gpu-crit { 2007 temperature = <110000>; 2008 hysteresis = <1000>; 2009 type = "critical"; 2010 }; 2011 }; 2012 }; 2013 2014 gpuss1-thermal { 2015 polling-delay-passive = <0>; 2016 polling-delay = <0>; 2017 2018 thermal-sensors = <&tsens0 14>; 2019 2020 trips { 2021 gpuss1_alert0: trip-point0 { 2022 temperature = <90000>; 2023 hysteresis = <2000>; 2024 type = "passive"; 2025 }; 2026 2027 gpuss1_alert1: trip-point1 { 2028 temperature = <95000>; 2029 hysteresis = <2000>; 2030 type = "passive"; 2031 }; 2032 2033 gpuss1_crit: gpu-crit { 2034 temperature = <110000>; 2035 hysteresis = <1000>; 2036 type = "critical"; 2037 }; 2038 }; 2039 }; 2040 2041 mapss1-thermal { 2042 polling-delay-passive = <0>; 2043 polling-delay = <0>; 2044 2045 thermal-sensors = <&tsens1 0>; 2046 2047 trips { 2048 mapss1_alert0: trip-point0 { 2049 temperature = <90000>; 2050 hysteresis = <2000>; 2051 type = "passive"; 2052 }; 2053 2054 mapss1_alert1: trip-point1 { 2055 temperature = <95000>; 2056 hysteresis = <2000>; 2057 type = "passive"; 2058 }; 2059 2060 mapss1_crit: mapss-crit { 2061 temperature = <110000>; 2062 hysteresis = <1000>; 2063 type = "critical"; 2064 }; 2065 }; 2066 }; 2067 2068 cwlan-thermal { 2069 polling-delay-passive = <0>; 2070 polling-delay = <0>; 2071 2072 thermal-sensors = <&tsens1 1>; 2073 2074 trips { 2075 cwlan_alert0: trip-point0 { 2076 temperature = <90000>; 2077 hysteresis = <2000>; 2078 type = "passive"; 2079 }; 2080 2081 cwlan_alert1: trip-point1 { 2082 temperature = <95000>; 2083 hysteresis = <2000>; 2084 type = "passive"; 2085 }; 2086 2087 cwlan_crit: cwlan-crit { 2088 temperature = <110000>; 2089 hysteresis = <1000>; 2090 type = "critical"; 2091 }; 2092 }; 2093 }; 2094 2095 audio-thermal { 2096 polling-delay-passive = <0>; 2097 polling-delay = <0>; 2098 2099 thermal-sensors = <&tsens1 2>; 2100 2101 trips { 2102 audio_alert0: trip-point0 { 2103 temperature = <90000>; 2104 hysteresis = <2000>; 2105 type = "passive"; 2106 }; 2107 2108 audio_alert1: trip-point1 { 2109 temperature = <95000>; 2110 hysteresis = <2000>; 2111 type = "passive"; 2112 }; 2113 2114 audio_crit: audio-crit { 2115 temperature = <110000>; 2116 hysteresis = <1000>; 2117 type = "critical"; 2118 }; 2119 }; 2120 }; 2121 2122 ddr-thermal { 2123 polling-delay-passive = <0>; 2124 polling-delay = <0>; 2125 2126 thermal-sensors = <&tsens1 3>; 2127 2128 trips { 2129 ddr_alert0: trip-point0 { 2130 temperature = <90000>; 2131 hysteresis = <2000>; 2132 type = "passive"; 2133 }; 2134 2135 ddr_alert1: trip-point1 { 2136 temperature = <95000>; 2137 hysteresis = <2000>; 2138 type = "passive"; 2139 }; 2140 2141 ddr_crit: ddr-crit { 2142 temperature = <110000>; 2143 hysteresis = <1000>; 2144 type = "critical"; 2145 }; 2146 }; 2147 }; 2148 2149 q6hvx-thermal { 2150 polling-delay-passive = <0>; 2151 polling-delay = <0>; 2152 2153 thermal-sensors = <&tsens1 4>; 2154 2155 trips { 2156 q6hvx_alert0: trip-point0 { 2157 temperature = <90000>; 2158 hysteresis = <2000>; 2159 type = "passive"; 2160 }; 2161 2162 q6hvx_alert1: trip-point1 { 2163 temperature = <95000>; 2164 hysteresis = <2000>; 2165 type = "passive"; 2166 }; 2167 2168 q6hvx_crit: q6hvx-crit { 2169 temperature = <110000>; 2170 hysteresis = <1000>; 2171 type = "critical"; 2172 }; 2173 }; 2174 }; 2175 2176 camera-thermal { 2177 polling-delay-passive = <0>; 2178 polling-delay = <0>; 2179 2180 thermal-sensors = <&tsens1 5>; 2181 2182 trips { 2183 camera_alert0: trip-point0 { 2184 temperature = <90000>; 2185 hysteresis = <2000>; 2186 type = "passive"; 2187 }; 2188 2189 camera_alert1: trip-point1 { 2190 temperature = <95000>; 2191 hysteresis = <2000>; 2192 type = "passive"; 2193 }; 2194 2195 camera_crit: camera-crit { 2196 temperature = <110000>; 2197 hysteresis = <1000>; 2198 type = "critical"; 2199 }; 2200 }; 2201 }; 2202 2203 mdm-core0-thermal { 2204 polling-delay-passive = <0>; 2205 polling-delay = <0>; 2206 2207 thermal-sensors = <&tsens1 6>; 2208 2209 trips { 2210 mdm_core0_alert0: trip-point0 { 2211 temperature = <90000>; 2212 hysteresis = <2000>; 2213 type = "passive"; 2214 }; 2215 2216 mdm_core0_alert1: trip-point1 { 2217 temperature = <95000>; 2218 hysteresis = <2000>; 2219 type = "passive"; 2220 }; 2221 2222 mdm_core0_crit: mdm-core0-crit { 2223 temperature = <110000>; 2224 hysteresis = <1000>; 2225 type = "critical"; 2226 }; 2227 }; 2228 }; 2229 2230 mdm-core1-thermal { 2231 polling-delay-passive = <0>; 2232 polling-delay = <0>; 2233 2234 thermal-sensors = <&tsens1 7>; 2235 2236 trips { 2237 mdm_core1_alert0: trip-point0 { 2238 temperature = <90000>; 2239 hysteresis = <2000>; 2240 type = "passive"; 2241 }; 2242 2243 mdm_core1_alert1: trip-point1 { 2244 temperature = <95000>; 2245 hysteresis = <2000>; 2246 type = "passive"; 2247 }; 2248 2249 mdm_core1_crit: mdm-core1-crit { 2250 temperature = <110000>; 2251 hysteresis = <1000>; 2252 type = "critical"; 2253 }; 2254 }; 2255 }; 2256 2257 mdm-vec-thermal { 2258 polling-delay-passive = <0>; 2259 polling-delay = <0>; 2260 2261 thermal-sensors = <&tsens1 8>; 2262 2263 trips { 2264 mdm_vec_alert0: trip-point0 { 2265 temperature = <90000>; 2266 hysteresis = <2000>; 2267 type = "passive"; 2268 }; 2269 2270 mdm_vec_alert1: trip-point1 { 2271 temperature = <95000>; 2272 hysteresis = <2000>; 2273 type = "passive"; 2274 }; 2275 2276 mdm_vec_crit: mdm-vec-crit { 2277 temperature = <110000>; 2278 hysteresis = <1000>; 2279 type = "critical"; 2280 }; 2281 }; 2282 }; 2283 2284 msm-scl-thermal { 2285 polling-delay-passive = <0>; 2286 polling-delay = <0>; 2287 2288 thermal-sensors = <&tsens1 9>; 2289 2290 trips { 2291 msm_scl_alert0: trip-point0 { 2292 temperature = <90000>; 2293 hysteresis = <2000>; 2294 type = "passive"; 2295 }; 2296 2297 msm_scl_alert1: trip-point1 { 2298 temperature = <95000>; 2299 hysteresis = <2000>; 2300 type = "passive"; 2301 }; 2302 2303 msm_scl_crit: msm-scl-crit { 2304 temperature = <110000>; 2305 hysteresis = <1000>; 2306 type = "critical"; 2307 }; 2308 }; 2309 }; 2310 2311 video-thermal { 2312 polling-delay-passive = <0>; 2313 polling-delay = <0>; 2314 2315 thermal-sensors = <&tsens1 10>; 2316 2317 trips { 2318 video_alert0: trip-point0 { 2319 temperature = <90000>; 2320 hysteresis = <2000>; 2321 type = "passive"; 2322 }; 2323 2324 video_alert1: trip-point1 { 2325 temperature = <95000>; 2326 hysteresis = <2000>; 2327 type = "passive"; 2328 }; 2329 2330 video_crit: video-crit { 2331 temperature = <110000>; 2332 hysteresis = <1000>; 2333 type = "critical"; 2334 }; 2335 }; 2336 }; 2337 }; 2338 2339 timer { 2340 compatible = "arm,armv8-timer"; 2341 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2342 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2343 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2344 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2345 }; 2346}; 2347