1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sm6350.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm6350-camcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interconnect/qcom,icc.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sm6350.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <76800000>; 31 clock-output-names = "xo_board"; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 clock-frequency = <32764>; 37 #clock-cells = <0>; 38 }; 39 }; 40 41 cpus { 42 #address-cells = <2>; 43 #size-cells = <0>; 44 45 CPU0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "qcom,kryo560"; 48 reg = <0x0 0x0>; 49 clocks = <&cpufreq_hw 0>; 50 enable-method = "psci"; 51 capacity-dmips-mhz = <1024>; 52 dynamic-power-coefficient = <100>; 53 next-level-cache = <&L2_0>; 54 qcom,freq-domain = <&cpufreq_hw 0>; 55 operating-points-v2 = <&cpu0_opp_table>; 56 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 57 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 58 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 59 #cooling-cells = <2>; 60 L2_0: l2-cache { 61 compatible = "cache"; 62 cache-level = <2>; 63 cache-unified; 64 next-level-cache = <&L3_0>; 65 L3_0: l3-cache { 66 compatible = "cache"; 67 cache-level = <3>; 68 cache-unified; 69 }; 70 }; 71 }; 72 73 CPU1: cpu@100 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo560"; 76 reg = <0x0 0x100>; 77 clocks = <&cpufreq_hw 0>; 78 enable-method = "psci"; 79 capacity-dmips-mhz = <1024>; 80 dynamic-power-coefficient = <100>; 81 next-level-cache = <&L2_100>; 82 qcom,freq-domain = <&cpufreq_hw 0>; 83 operating-points-v2 = <&cpu0_opp_table>; 84 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 85 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 86 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 87 #cooling-cells = <2>; 88 L2_100: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 cache-unified; 92 next-level-cache = <&L3_0>; 93 }; 94 }; 95 96 CPU2: cpu@200 { 97 device_type = "cpu"; 98 compatible = "qcom,kryo560"; 99 reg = <0x0 0x200>; 100 clocks = <&cpufreq_hw 0>; 101 enable-method = "psci"; 102 capacity-dmips-mhz = <1024>; 103 dynamic-power-coefficient = <100>; 104 next-level-cache = <&L2_200>; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 operating-points-v2 = <&cpu0_opp_table>; 107 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 108 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 109 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 110 #cooling-cells = <2>; 111 L2_200: l2-cache { 112 compatible = "cache"; 113 cache-level = <2>; 114 cache-unified; 115 next-level-cache = <&L3_0>; 116 }; 117 }; 118 119 CPU3: cpu@300 { 120 device_type = "cpu"; 121 compatible = "qcom,kryo560"; 122 reg = <0x0 0x300>; 123 clocks = <&cpufreq_hw 0>; 124 enable-method = "psci"; 125 capacity-dmips-mhz = <1024>; 126 dynamic-power-coefficient = <100>; 127 next-level-cache = <&L2_300>; 128 qcom,freq-domain = <&cpufreq_hw 0>; 129 operating-points-v2 = <&cpu0_opp_table>; 130 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 131 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 132 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 133 #cooling-cells = <2>; 134 L2_300: l2-cache { 135 compatible = "cache"; 136 cache-level = <2>; 137 cache-unified; 138 next-level-cache = <&L3_0>; 139 }; 140 }; 141 142 CPU4: cpu@400 { 143 device_type = "cpu"; 144 compatible = "qcom,kryo560"; 145 reg = <0x0 0x400>; 146 clocks = <&cpufreq_hw 0>; 147 enable-method = "psci"; 148 capacity-dmips-mhz = <1024>; 149 dynamic-power-coefficient = <100>; 150 next-level-cache = <&L2_400>; 151 qcom,freq-domain = <&cpufreq_hw 0>; 152 operating-points-v2 = <&cpu0_opp_table>; 153 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 154 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 155 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 156 #cooling-cells = <2>; 157 L2_400: l2-cache { 158 compatible = "cache"; 159 cache-level = <2>; 160 cache-unified; 161 next-level-cache = <&L3_0>; 162 }; 163 }; 164 165 CPU5: cpu@500 { 166 device_type = "cpu"; 167 compatible = "qcom,kryo560"; 168 reg = <0x0 0x500>; 169 clocks = <&cpufreq_hw 0>; 170 enable-method = "psci"; 171 capacity-dmips-mhz = <1024>; 172 dynamic-power-coefficient = <100>; 173 next-level-cache = <&L2_500>; 174 qcom,freq-domain = <&cpufreq_hw 0>; 175 operating-points-v2 = <&cpu0_opp_table>; 176 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 177 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 178 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 179 #cooling-cells = <2>; 180 L2_500: l2-cache { 181 compatible = "cache"; 182 cache-level = <2>; 183 cache-unified; 184 next-level-cache = <&L3_0>; 185 }; 186 }; 187 188 CPU6: cpu@600 { 189 device_type = "cpu"; 190 compatible = "qcom,kryo560"; 191 reg = <0x0 0x600>; 192 clocks = <&cpufreq_hw 1>; 193 enable-method = "psci"; 194 capacity-dmips-mhz = <1894>; 195 dynamic-power-coefficient = <703>; 196 next-level-cache = <&L2_600>; 197 qcom,freq-domain = <&cpufreq_hw 1>; 198 operating-points-v2 = <&cpu6_opp_table>; 199 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 200 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 201 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 202 #cooling-cells = <2>; 203 L2_600: l2-cache { 204 compatible = "cache"; 205 cache-level = <2>; 206 cache-unified; 207 next-level-cache = <&L3_0>; 208 }; 209 }; 210 211 CPU7: cpu@700 { 212 device_type = "cpu"; 213 compatible = "qcom,kryo560"; 214 reg = <0x0 0x700>; 215 clocks = <&cpufreq_hw 1>; 216 enable-method = "psci"; 217 capacity-dmips-mhz = <1894>; 218 dynamic-power-coefficient = <703>; 219 next-level-cache = <&L2_700>; 220 qcom,freq-domain = <&cpufreq_hw 1>; 221 operating-points-v2 = <&cpu6_opp_table>; 222 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 223 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 224 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 225 #cooling-cells = <2>; 226 L2_700: l2-cache { 227 compatible = "cache"; 228 cache-level = <2>; 229 cache-unified; 230 next-level-cache = <&L3_0>; 231 }; 232 }; 233 234 cpu-map { 235 cluster0 { 236 core0 { 237 cpu = <&CPU0>; 238 }; 239 240 core1 { 241 cpu = <&CPU1>; 242 }; 243 244 core2 { 245 cpu = <&CPU2>; 246 }; 247 248 core3 { 249 cpu = <&CPU3>; 250 }; 251 252 core4 { 253 cpu = <&CPU4>; 254 }; 255 256 core5 { 257 cpu = <&CPU5>; 258 }; 259 260 core6 { 261 cpu = <&CPU6>; 262 }; 263 264 core7 { 265 cpu = <&CPU7>; 266 }; 267 }; 268 }; 269 }; 270 271 firmware { 272 scm: scm { 273 compatible = "qcom,scm-sm6350", "qcom,scm"; 274 #reset-cells = <1>; 275 }; 276 }; 277 278 memory@80000000 { 279 device_type = "memory"; 280 /* We expect the bootloader to fill in the size */ 281 reg = <0x0 0x80000000 0x0 0x0>; 282 }; 283 284 cpu0_opp_table: opp-table-cpu0 { 285 compatible = "operating-points-v2"; 286 opp-shared; 287 288 opp-300000000 { 289 opp-hz = /bits/ 64 <300000000>; 290 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ 291 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 292 }; 293 294 opp-576000000 { 295 opp-hz = /bits/ 64 <576000000>; 296 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>; 297 }; 298 299 opp-768000000 { 300 opp-hz = /bits/ 64 <768000000>; 301 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 302 }; 303 304 opp-1017600000 { 305 opp-hz = /bits/ 64 <1017600000>; 306 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 307 }; 308 309 opp-1248000000 { 310 opp-hz = /bits/ 64 <1248000000>; 311 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 312 }; 313 314 opp-1324800000 { 315 opp-hz = /bits/ 64 <1324800000>; 316 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>; 317 }; 318 319 opp-1516800000 { 320 opp-hz = /bits/ 64 <1516800000>; 321 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 322 }; 323 324 opp-1612800000 { 325 opp-hz = /bits/ 64 <1612800000>; 326 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 327 }; 328 329 opp-1708800000 { 330 opp-hz = /bits/ 64 <1708800000>; 331 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 332 }; 333 }; 334 335 cpu6_opp_table: opp-table-cpu6 { 336 compatible = "operating-points-v2"; 337 opp-shared; 338 339 opp-300000000 { 340 opp-hz = /bits/ 64 <300000000>; 341 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 342 }; 343 344 opp-787200000 { 345 opp-hz = /bits/ 64 <787200000>; 346 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 347 }; 348 349 opp-979200000 { 350 opp-hz = /bits/ 64 <979200000>; 351 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>; 352 }; 353 354 opp-1036800000 { 355 opp-hz = /bits/ 64 <1036800000>; 356 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 357 }; 358 359 opp-1248000000 { 360 opp-hz = /bits/ 64 <1248000000>; 361 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 362 }; 363 364 opp-1401600000 { 365 opp-hz = /bits/ 64 <1401600000>; 366 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>; 367 }; 368 369 opp-1555200000 { 370 opp-hz = /bits/ 64 <1555200000>; 371 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 372 }; 373 374 opp-1766400000 { 375 opp-hz = /bits/ 64 <1766400000>; 376 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 377 }; 378 379 opp-1900800000 { 380 opp-hz = /bits/ 64 <1900800000>; 381 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 382 }; 383 384 opp-2073600000 { 385 opp-hz = /bits/ 64 <2073600000>; 386 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 387 }; 388 }; 389 390 pmu { 391 compatible = "arm,armv8-pmuv3"; 392 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 393 }; 394 395 psci { 396 compatible = "arm,psci-1.0"; 397 method = "smc"; 398 }; 399 400 reserved_memory: reserved-memory { 401 #address-cells = <2>; 402 #size-cells = <2>; 403 ranges; 404 405 hyp_mem: memory@80000000 { 406 reg = <0 0x80000000 0 0x600000>; 407 no-map; 408 }; 409 410 xbl_aop_mem: memory@80700000 { 411 reg = <0 0x80700000 0 0x160000>; 412 no-map; 413 }; 414 415 cmd_db: memory@80860000 { 416 compatible = "qcom,cmd-db"; 417 reg = <0 0x80860000 0 0x20000>; 418 no-map; 419 }; 420 421 sec_apps_mem: memory@808ff000 { 422 reg = <0 0x808ff000 0 0x1000>; 423 no-map; 424 }; 425 426 smem_mem: memory@80900000 { 427 reg = <0 0x80900000 0 0x200000>; 428 no-map; 429 }; 430 431 cdsp_sec_mem: memory@80b00000 { 432 reg = <0 0x80b00000 0 0x1e00000>; 433 no-map; 434 }; 435 436 pil_camera_mem: memory@86000000 { 437 reg = <0 0x86000000 0 0x500000>; 438 no-map; 439 }; 440 441 pil_npu_mem: memory@86500000 { 442 reg = <0 0x86500000 0 0x500000>; 443 no-map; 444 }; 445 446 pil_video_mem: memory@86a00000 { 447 reg = <0 0x86a00000 0 0x500000>; 448 no-map; 449 }; 450 451 pil_cdsp_mem: memory@86f00000 { 452 reg = <0 0x86f00000 0 0x1e00000>; 453 no-map; 454 }; 455 456 pil_adsp_mem: memory@88d00000 { 457 reg = <0 0x88d00000 0 0x2800000>; 458 no-map; 459 }; 460 461 wlan_fw_mem: memory@8b500000 { 462 reg = <0 0x8b500000 0 0x200000>; 463 no-map; 464 }; 465 466 pil_ipa_fw_mem: memory@8b700000 { 467 reg = <0 0x8b700000 0 0x10000>; 468 no-map; 469 }; 470 471 pil_ipa_gsi_mem: memory@8b710000 { 472 reg = <0 0x8b710000 0 0x5400>; 473 no-map; 474 }; 475 476 pil_gpu_mem: memory@8b715400 { 477 reg = <0 0x8b715400 0 0x2000>; 478 no-map; 479 }; 480 481 pil_modem_mem: memory@8b800000 { 482 reg = <0 0x8b800000 0 0xf800000>; 483 no-map; 484 }; 485 486 cont_splash_memory: memory@a0000000 { 487 reg = <0 0xa0000000 0 0x2300000>; 488 no-map; 489 }; 490 491 dfps_data_memory: memory@a2300000 { 492 reg = <0 0xa2300000 0 0x100000>; 493 no-map; 494 }; 495 496 removed_region: memory@c0000000 { 497 reg = <0 0xc0000000 0 0x3900000>; 498 no-map; 499 }; 500 501 debug_region: memory@ffb00000 { 502 reg = <0 0xffb00000 0 0xc0000>; 503 no-map; 504 }; 505 506 last_log_region: memory@ffbc0000 { 507 reg = <0 0xffbc0000 0 0x40000>; 508 no-map; 509 }; 510 511 ramoops: ramoops@ffc00000 { 512 compatible = "ramoops"; 513 reg = <0 0xffc00000 0 0x100000>; 514 record-size = <0x1000>; 515 console-size = <0x40000>; 516 msg-size = <0x20000 0x20000>; 517 ecc-size = <16>; 518 no-map; 519 }; 520 521 cmdline_region: memory@ffd00000 { 522 reg = <0 0xffd00000 0 0x1000>; 523 no-map; 524 }; 525 }; 526 527 smem { 528 compatible = "qcom,smem"; 529 memory-region = <&smem_mem>; 530 hwlocks = <&tcsr_mutex 3>; 531 }; 532 533 smp2p-adsp { 534 compatible = "qcom,smp2p"; 535 qcom,smem = <443>, <429>; 536 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 537 IPCC_MPROC_SIGNAL_SMP2P 538 IRQ_TYPE_EDGE_RISING>; 539 mboxes = <&ipcc IPCC_CLIENT_LPASS 540 IPCC_MPROC_SIGNAL_SMP2P>; 541 542 qcom,local-pid = <0>; 543 qcom,remote-pid = <2>; 544 545 smp2p_adsp_out: master-kernel { 546 qcom,entry-name = "master-kernel"; 547 #qcom,smem-state-cells = <1>; 548 }; 549 550 smp2p_adsp_in: slave-kernel { 551 qcom,entry-name = "slave-kernel"; 552 interrupt-controller; 553 #interrupt-cells = <2>; 554 }; 555 }; 556 557 smp2p-cdsp { 558 compatible = "qcom,smp2p"; 559 qcom,smem = <94>, <432>; 560 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 561 IPCC_MPROC_SIGNAL_SMP2P 562 IRQ_TYPE_EDGE_RISING>; 563 mboxes = <&ipcc IPCC_CLIENT_CDSP 564 IPCC_MPROC_SIGNAL_SMP2P>; 565 566 qcom,local-pid = <0>; 567 qcom,remote-pid = <5>; 568 569 smp2p_cdsp_out: master-kernel { 570 qcom,entry-name = "master-kernel"; 571 #qcom,smem-state-cells = <1>; 572 }; 573 574 smp2p_cdsp_in: slave-kernel { 575 qcom,entry-name = "slave-kernel"; 576 interrupt-controller; 577 #interrupt-cells = <2>; 578 }; 579 }; 580 581 smp2p-mpss { 582 compatible = "qcom,smp2p"; 583 qcom,smem = <435>, <428>; 584 585 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 586 IPCC_MPROC_SIGNAL_SMP2P 587 IRQ_TYPE_EDGE_RISING>; 588 mboxes = <&ipcc IPCC_CLIENT_MPSS 589 IPCC_MPROC_SIGNAL_SMP2P>; 590 591 qcom,local-pid = <0>; 592 qcom,remote-pid = <1>; 593 594 modem_smp2p_out: master-kernel { 595 qcom,entry-name = "master-kernel"; 596 #qcom,smem-state-cells = <1>; 597 }; 598 599 modem_smp2p_in: slave-kernel { 600 qcom,entry-name = "slave-kernel"; 601 interrupt-controller; 602 #interrupt-cells = <2>; 603 }; 604 605 ipa_smp2p_out: ipa-ap-to-modem { 606 qcom,entry-name = "ipa"; 607 #qcom,smem-state-cells = <1>; 608 }; 609 610 ipa_smp2p_in: ipa-modem-to-ap { 611 qcom,entry-name = "ipa"; 612 interrupt-controller; 613 #interrupt-cells = <2>; 614 }; 615 }; 616 617 soc: soc@0 { 618 #address-cells = <2>; 619 #size-cells = <2>; 620 ranges = <0 0 0 0 0x10 0>; 621 dma-ranges = <0 0 0 0 0x10 0>; 622 compatible = "simple-bus"; 623 624 gcc: clock-controller@100000 { 625 compatible = "qcom,gcc-sm6350"; 626 reg = <0 0x00100000 0 0x1f0000>; 627 #clock-cells = <1>; 628 #reset-cells = <1>; 629 #power-domain-cells = <1>; 630 clock-names = "bi_tcxo", 631 "bi_tcxo_ao", 632 "sleep_clk"; 633 clocks = <&rpmhcc RPMH_CXO_CLK>, 634 <&rpmhcc RPMH_CXO_CLK_A>, 635 <&sleep_clk>; 636 }; 637 638 ipcc: mailbox@408000 { 639 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 640 reg = <0 0x00408000 0 0x1000>; 641 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 642 interrupt-controller; 643 #interrupt-cells = <3>; 644 #mbox-cells = <2>; 645 }; 646 647 rng: rng@793000 { 648 compatible = "qcom,prng-ee"; 649 reg = <0 0x00793000 0 0x1000>; 650 clocks = <&gcc GCC_PRNG_AHB_CLK>; 651 clock-names = "core"; 652 }; 653 654 sdhc_1: mmc@7c4000 { 655 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 656 reg = <0 0x007c4000 0 0x1000>, 657 <0 0x007c5000 0 0x1000>, 658 <0 0x007c8000 0 0x8000>; 659 reg-names = "hc", "cqhci", "ice"; 660 661 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 663 interrupt-names = "hc_irq", "pwr_irq"; 664 iommus = <&apps_smmu 0x60 0x0>; 665 666 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 667 <&gcc GCC_SDCC1_APPS_CLK>, 668 <&rpmhcc RPMH_CXO_CLK>; 669 clock-names = "iface", "core", "xo"; 670 resets = <&gcc GCC_SDCC1_BCR>; 671 qcom,dll-config = <0x000f642c>; 672 qcom,ddr-config = <0x80040868>; 673 power-domains = <&rpmhpd SM6350_CX>; 674 operating-points-v2 = <&sdhc1_opp_table>; 675 bus-width = <8>; 676 non-removable; 677 supports-cqe; 678 679 status = "disabled"; 680 681 sdhc1_opp_table: opp-table { 682 compatible = "operating-points-v2"; 683 684 opp-19200000 { 685 opp-hz = /bits/ 64 <19200000>; 686 required-opps = <&rpmhpd_opp_min_svs>; 687 }; 688 689 opp-100000000 { 690 opp-hz = /bits/ 64 <100000000>; 691 required-opps = <&rpmhpd_opp_low_svs>; 692 }; 693 694 opp-384000000 { 695 opp-hz = /bits/ 64 <384000000>; 696 required-opps = <&rpmhpd_opp_svs_l1>; 697 }; 698 }; 699 }; 700 701 gpi_dma0: dma-controller@800000 { 702 compatible = "qcom,sm6350-gpi-dma"; 703 reg = <0 0x00800000 0 0x60000>; 704 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 714 dma-channels = <10>; 715 dma-channel-mask = <0x1f>; 716 iommus = <&apps_smmu 0x56 0x0>; 717 #dma-cells = <3>; 718 status = "disabled"; 719 }; 720 721 qupv3_id_0: geniqup@8c0000 { 722 compatible = "qcom,geni-se-qup"; 723 reg = <0x0 0x008c0000 0x0 0x2000>; 724 clock-names = "m-ahb", "s-ahb"; 725 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 726 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 727 #address-cells = <2>; 728 #size-cells = <2>; 729 iommus = <&apps_smmu 0x43 0x0>; 730 ranges; 731 status = "disabled"; 732 733 i2c0: i2c@880000 { 734 compatible = "qcom,geni-i2c"; 735 reg = <0 0x00880000 0 0x4000>; 736 clock-names = "se"; 737 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 738 pinctrl-names = "default"; 739 pinctrl-0 = <&qup_i2c0_default>; 740 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 741 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 742 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 743 dma-names = "tx", "rx"; 744 #address-cells = <1>; 745 #size-cells = <0>; 746 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 747 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 748 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 749 interconnect-names = "qup-core", "qup-config", "qup-memory"; 750 status = "disabled"; 751 }; 752 753 i2c2: i2c@888000 { 754 compatible = "qcom,geni-i2c"; 755 reg = <0 0x00888000 0 0x4000>; 756 clock-names = "se"; 757 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 758 pinctrl-names = "default"; 759 pinctrl-0 = <&qup_i2c2_default>; 760 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 761 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 762 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 763 dma-names = "tx", "rx"; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 767 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 768 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 769 interconnect-names = "qup-core", "qup-config", "qup-memory"; 770 status = "disabled"; 771 }; 772 }; 773 774 gpi_dma1: dma-controller@900000 { 775 compatible = "qcom,sm6350-gpi-dma"; 776 reg = <0 0x00900000 0 0x60000>; 777 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 787 dma-channels = <10>; 788 dma-channel-mask = <0x3f>; 789 iommus = <&apps_smmu 0x4d6 0x0>; 790 #dma-cells = <3>; 791 status = "disabled"; 792 }; 793 794 qupv3_id_1: geniqup@9c0000 { 795 compatible = "qcom,geni-se-qup"; 796 reg = <0x0 0x009c0000 0x0 0x2000>; 797 clock-names = "m-ahb", "s-ahb"; 798 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 799 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 800 #address-cells = <2>; 801 #size-cells = <2>; 802 iommus = <&apps_smmu 0x4c3 0x0>; 803 ranges; 804 status = "disabled"; 805 806 i2c6: i2c@980000 { 807 compatible = "qcom,geni-i2c"; 808 reg = <0 0x00980000 0 0x4000>; 809 clock-names = "se"; 810 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 811 pinctrl-names = "default"; 812 pinctrl-0 = <&qup_i2c6_default>; 813 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 814 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 815 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 816 dma-names = "tx", "rx"; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 820 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 821 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 822 interconnect-names = "qup-core", "qup-config", "qup-memory"; 823 status = "disabled"; 824 }; 825 826 i2c7: i2c@984000 { 827 compatible = "qcom,geni-i2c"; 828 reg = <0 0x00984000 0 0x4000>; 829 clock-names = "se"; 830 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 831 pinctrl-names = "default"; 832 pinctrl-0 = <&qup_i2c7_default>; 833 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 834 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 835 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 836 dma-names = "tx", "rx"; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 840 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 841 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 842 interconnect-names = "qup-core", "qup-config", "qup-memory"; 843 status = "disabled"; 844 }; 845 846 i2c8: i2c@988000 { 847 compatible = "qcom,geni-i2c"; 848 reg = <0 0x00988000 0 0x4000>; 849 clock-names = "se"; 850 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 851 pinctrl-names = "default"; 852 pinctrl-0 = <&qup_i2c8_default>; 853 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 854 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 855 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 856 dma-names = "tx", "rx"; 857 #address-cells = <1>; 858 #size-cells = <0>; 859 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 860 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 861 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 862 interconnect-names = "qup-core", "qup-config", "qup-memory"; 863 status = "disabled"; 864 }; 865 866 uart9: serial@98c000 { 867 compatible = "qcom,geni-debug-uart"; 868 reg = <0 0x0098c000 0 0x4000>; 869 clock-names = "se"; 870 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 871 pinctrl-names = "default"; 872 pinctrl-0 = <&qup_uart9_default>; 873 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 874 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 875 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 876 interconnect-names = "qup-core", "qup-config"; 877 status = "disabled"; 878 }; 879 880 i2c10: i2c@990000 { 881 compatible = "qcom,geni-i2c"; 882 reg = <0 0x00990000 0 0x4000>; 883 clock-names = "se"; 884 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 885 pinctrl-names = "default"; 886 pinctrl-0 = <&qup_i2c10_default>; 887 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 888 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 889 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 890 dma-names = "tx", "rx"; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 894 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 895 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 896 interconnect-names = "qup-core", "qup-config", "qup-memory"; 897 status = "disabled"; 898 }; 899 }; 900 901 config_noc: interconnect@1500000 { 902 compatible = "qcom,sm6350-config-noc"; 903 reg = <0 0x01500000 0 0x28000>; 904 #interconnect-cells = <2>; 905 qcom,bcm-voters = <&apps_bcm_voter>; 906 }; 907 908 system_noc: interconnect@1620000 { 909 compatible = "qcom,sm6350-system-noc"; 910 reg = <0 0x01620000 0 0x17080>; 911 #interconnect-cells = <2>; 912 qcom,bcm-voters = <&apps_bcm_voter>; 913 914 clk_virt: interconnect-clk-virt { 915 compatible = "qcom,sm6350-clk-virt"; 916 #interconnect-cells = <2>; 917 qcom,bcm-voters = <&apps_bcm_voter>; 918 }; 919 }; 920 921 aggre1_noc: interconnect@16e0000 { 922 compatible = "qcom,sm6350-aggre1-noc"; 923 reg = <0 0x016e0000 0 0x15080>; 924 #interconnect-cells = <2>; 925 qcom,bcm-voters = <&apps_bcm_voter>; 926 }; 927 928 aggre2_noc: interconnect@1700000 { 929 compatible = "qcom,sm6350-aggre2-noc"; 930 reg = <0 0x01700000 0 0x1f880>; 931 #interconnect-cells = <2>; 932 qcom,bcm-voters = <&apps_bcm_voter>; 933 934 compute_noc: interconnect-compute-noc { 935 compatible = "qcom,sm6350-compute-noc"; 936 #interconnect-cells = <2>; 937 qcom,bcm-voters = <&apps_bcm_voter>; 938 }; 939 }; 940 941 mmss_noc: interconnect@1740000 { 942 compatible = "qcom,sm6350-mmss-noc"; 943 reg = <0 0x01740000 0 0x1c100>; 944 #interconnect-cells = <2>; 945 qcom,bcm-voters = <&apps_bcm_voter>; 946 }; 947 948 ufs_mem_hc: ufs@1d84000 { 949 compatible = "qcom,sm6350-ufshc", "qcom,ufshc", 950 "jedec,ufs-2.0"; 951 reg = <0 0x01d84000 0 0x3000>, 952 <0 0x01d90000 0 0x8000>; 953 reg-names = "std", "ice"; 954 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 955 phys = <&ufs_mem_phy_lanes>; 956 phy-names = "ufsphy"; 957 lanes-per-direction = <2>; 958 #reset-cells = <1>; 959 resets = <&gcc GCC_UFS_PHY_BCR>; 960 reset-names = "rst"; 961 962 power-domains = <&gcc UFS_PHY_GDSC>; 963 964 iommus = <&apps_smmu 0x80 0x0>; 965 966 clock-names = "core_clk", 967 "bus_aggr_clk", 968 "iface_clk", 969 "core_clk_unipro", 970 "ref_clk", 971 "tx_lane0_sync_clk", 972 "rx_lane0_sync_clk", 973 "rx_lane1_sync_clk", 974 "ice_core_clk"; 975 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 976 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 977 <&gcc GCC_UFS_PHY_AHB_CLK>, 978 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 979 <&rpmhcc RPMH_QLINK_CLK>, 980 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 981 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 982 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 983 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 984 freq-table-hz = 985 <50000000 200000000>, 986 <0 0>, 987 <0 0>, 988 <37500000 150000000>, 989 <75000000 300000000>, 990 <0 0>, 991 <0 0>, 992 <0 0>, 993 <0 0>; 994 995 status = "disabled"; 996 }; 997 998 ufs_mem_phy: phy@1d87000 { 999 compatible = "qcom,sm6350-qmp-ufs-phy"; 1000 reg = <0 0x01d87000 0 0x18c>; 1001 #address-cells = <2>; 1002 #size-cells = <2>; 1003 ranges; 1004 1005 clock-names = "ref", 1006 "ref_aux"; 1007 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 1008 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1009 1010 resets = <&ufs_mem_hc 0>; 1011 reset-names = "ufsphy"; 1012 1013 status = "disabled"; 1014 1015 ufs_mem_phy_lanes: phy@1d87400 { 1016 reg = <0 0x01d87400 0 0x128>, 1017 <0 0x01d87600 0 0x1fc>, 1018 <0 0x01d87c00 0 0x1dc>, 1019 <0 0x01d87800 0 0x128>, 1020 <0 0x01d87a00 0 0x1fc>; 1021 #phy-cells = <0>; 1022 }; 1023 }; 1024 1025 ipa: ipa@1e40000 { 1026 compatible = "qcom,sm6350-ipa"; 1027 1028 iommus = <&apps_smmu 0x440 0x0>, 1029 <&apps_smmu 0x442 0x0>; 1030 reg = <0 0x01e40000 0 0x8000>, 1031 <0 0x01e50000 0 0x3000>, 1032 <0 0x01e04000 0 0x23000>; 1033 reg-names = "ipa-reg", 1034 "ipa-shared", 1035 "gsi"; 1036 1037 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1038 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1039 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1040 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1041 interrupt-names = "ipa", 1042 "gsi", 1043 "ipa-clock-query", 1044 "ipa-setup-ready"; 1045 1046 clocks = <&rpmhcc RPMH_IPA_CLK>; 1047 clock-names = "core"; 1048 1049 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>, 1050 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, 1051 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; 1052 interconnect-names = "memory", "imem", "config"; 1053 1054 qcom,smem-states = <&ipa_smp2p_out 0>, 1055 <&ipa_smp2p_out 1>; 1056 qcom,smem-state-names = "ipa-clock-enabled-valid", 1057 "ipa-clock-enabled"; 1058 1059 status = "disabled"; 1060 }; 1061 1062 tcsr_mutex: hwlock@1f40000 { 1063 compatible = "qcom,tcsr-mutex"; 1064 reg = <0x0 0x01f40000 0x0 0x40000>; 1065 #hwlock-cells = <1>; 1066 }; 1067 1068 adsp: remoteproc@3000000 { 1069 compatible = "qcom,sm6350-adsp-pas"; 1070 reg = <0 0x03000000 0 0x100>; 1071 1072 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 1073 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1074 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1075 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1076 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1077 interrupt-names = "wdog", "fatal", "ready", 1078 "handover", "stop-ack"; 1079 1080 clocks = <&rpmhcc RPMH_CXO_CLK>; 1081 clock-names = "xo"; 1082 1083 power-domains = <&rpmhpd SM6350_LCX>, 1084 <&rpmhpd SM6350_LMX>; 1085 power-domain-names = "lcx", "lmx"; 1086 1087 memory-region = <&pil_adsp_mem>; 1088 1089 qcom,qmp = <&aoss_qmp>; 1090 1091 qcom,smem-states = <&smp2p_adsp_out 0>; 1092 qcom,smem-state-names = "stop"; 1093 1094 status = "disabled"; 1095 1096 glink-edge { 1097 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1098 IPCC_MPROC_SIGNAL_GLINK_QMP 1099 IRQ_TYPE_EDGE_RISING>; 1100 mboxes = <&ipcc IPCC_CLIENT_LPASS 1101 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1102 1103 label = "lpass"; 1104 qcom,remote-pid = <2>; 1105 1106 fastrpc { 1107 compatible = "qcom,fastrpc"; 1108 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1109 label = "adsp"; 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 1113 compute-cb@3 { 1114 compatible = "qcom,fastrpc-compute-cb"; 1115 reg = <3>; 1116 iommus = <&apps_smmu 0x1003 0x0>; 1117 }; 1118 1119 compute-cb@4 { 1120 compatible = "qcom,fastrpc-compute-cb"; 1121 reg = <4>; 1122 iommus = <&apps_smmu 0x1004 0x0>; 1123 }; 1124 1125 compute-cb@5 { 1126 compatible = "qcom,fastrpc-compute-cb"; 1127 reg = <5>; 1128 iommus = <&apps_smmu 0x1005 0x0>; 1129 qcom,nsessions = <5>; 1130 }; 1131 }; 1132 }; 1133 }; 1134 1135 mpss: remoteproc@4080000 { 1136 compatible = "qcom,sm6350-mpss-pas"; 1137 reg = <0x0 0x04080000 0x0 0x4040>; 1138 1139 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 1140 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1141 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1142 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1143 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1144 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1145 interrupt-names = "wdog", "fatal", "ready", "handover", 1146 "stop-ack", "shutdown-ack"; 1147 1148 clocks = <&rpmhcc RPMH_CXO_CLK>; 1149 clock-names = "xo"; 1150 1151 power-domains = <&rpmhpd SM6350_CX>, 1152 <&rpmhpd SM6350_MSS>; 1153 power-domain-names = "cx", "mss"; 1154 1155 memory-region = <&pil_modem_mem>; 1156 1157 qcom,qmp = <&aoss_qmp>; 1158 1159 qcom,smem-states = <&modem_smp2p_out 0>; 1160 qcom,smem-state-names = "stop"; 1161 1162 status = "disabled"; 1163 1164 glink-edge { 1165 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1166 IPCC_MPROC_SIGNAL_GLINK_QMP 1167 IRQ_TYPE_EDGE_RISING>; 1168 mboxes = <&ipcc IPCC_CLIENT_MPSS 1169 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1170 label = "modem"; 1171 qcom,remote-pid = <1>; 1172 }; 1173 }; 1174 1175 cdsp: remoteproc@8300000 { 1176 compatible = "qcom,sm6350-cdsp-pas"; 1177 reg = <0 0x08300000 0 0x10000>; 1178 1179 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 1180 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1181 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1182 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1183 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1184 interrupt-names = "wdog", "fatal", "ready", 1185 "handover", "stop-ack"; 1186 1187 clocks = <&rpmhcc RPMH_CXO_CLK>; 1188 clock-names = "xo"; 1189 1190 power-domains = <&rpmhpd SM6350_CX>, 1191 <&rpmhpd SM6350_MX>; 1192 power-domain-names = "cx", "mx"; 1193 1194 memory-region = <&pil_cdsp_mem>; 1195 1196 qcom,qmp = <&aoss_qmp>; 1197 1198 qcom,smem-states = <&smp2p_cdsp_out 0>; 1199 qcom,smem-state-names = "stop"; 1200 1201 status = "disabled"; 1202 1203 glink-edge { 1204 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1205 IPCC_MPROC_SIGNAL_GLINK_QMP 1206 IRQ_TYPE_EDGE_RISING>; 1207 mboxes = <&ipcc IPCC_CLIENT_CDSP 1208 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1209 1210 label = "cdsp"; 1211 qcom,remote-pid = <5>; 1212 1213 fastrpc { 1214 compatible = "qcom,fastrpc"; 1215 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1216 label = "cdsp"; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 1220 compute-cb@1 { 1221 compatible = "qcom,fastrpc-compute-cb"; 1222 reg = <1>; 1223 iommus = <&apps_smmu 0x1401 0x20>; 1224 }; 1225 1226 compute-cb@2 { 1227 compatible = "qcom,fastrpc-compute-cb"; 1228 reg = <2>; 1229 iommus = <&apps_smmu 0x1402 0x20>; 1230 }; 1231 1232 compute-cb@3 { 1233 compatible = "qcom,fastrpc-compute-cb"; 1234 reg = <3>; 1235 iommus = <&apps_smmu 0x1403 0x20>; 1236 }; 1237 1238 compute-cb@4 { 1239 compatible = "qcom,fastrpc-compute-cb"; 1240 reg = <4>; 1241 iommus = <&apps_smmu 0x1404 0x20>; 1242 }; 1243 1244 compute-cb@5 { 1245 compatible = "qcom,fastrpc-compute-cb"; 1246 reg = <5>; 1247 iommus = <&apps_smmu 0x1405 0x20>; 1248 }; 1249 1250 compute-cb@6 { 1251 compatible = "qcom,fastrpc-compute-cb"; 1252 reg = <6>; 1253 iommus = <&apps_smmu 0x1406 0x20>; 1254 }; 1255 1256 compute-cb@7 { 1257 compatible = "qcom,fastrpc-compute-cb"; 1258 reg = <7>; 1259 iommus = <&apps_smmu 0x1407 0x20>; 1260 }; 1261 1262 compute-cb@8 { 1263 compatible = "qcom,fastrpc-compute-cb"; 1264 reg = <8>; 1265 iommus = <&apps_smmu 0x1408 0x20>; 1266 }; 1267 1268 /* note: secure cb9 in downstream */ 1269 }; 1270 }; 1271 }; 1272 1273 sdhc_2: mmc@8804000 { 1274 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 1275 reg = <0 0x08804000 0 0x1000>; 1276 1277 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1278 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1279 interrupt-names = "hc_irq", "pwr_irq"; 1280 iommus = <&apps_smmu 0x560 0x0>; 1281 1282 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1283 <&gcc GCC_SDCC2_APPS_CLK>, 1284 <&rpmhcc RPMH_CXO_CLK>; 1285 clock-names = "iface", "core", "xo"; 1286 resets = <&gcc GCC_SDCC2_BCR>; 1287 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, 1288 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; 1289 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1290 1291 pinctrl-0 = <&sdc2_on_state>; 1292 pinctrl-1 = <&sdc2_off_state>; 1293 pinctrl-names = "default", "sleep"; 1294 1295 qcom,dll-config = <0x0007642c>; 1296 qcom,ddr-config = <0x80040868>; 1297 power-domains = <&rpmhpd SM6350_CX>; 1298 operating-points-v2 = <&sdhc2_opp_table>; 1299 bus-width = <4>; 1300 1301 status = "disabled"; 1302 1303 sdhc2_opp_table: opp-table { 1304 compatible = "operating-points-v2"; 1305 1306 opp-100000000 { 1307 opp-hz = /bits/ 64 <100000000>; 1308 required-opps = <&rpmhpd_opp_svs_l1>; 1309 opp-peak-kBps = <790000 131000>; 1310 opp-avg-kBps = <50000 50000>; 1311 }; 1312 1313 opp-202000000 { 1314 opp-hz = /bits/ 64 <202000000>; 1315 required-opps = <&rpmhpd_opp_nom>; 1316 opp-peak-kBps = <3190000 294000>; 1317 opp-avg-kBps = <261438 300000>; 1318 }; 1319 }; 1320 }; 1321 1322 usb_1_hsphy: phy@88e3000 { 1323 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 1324 reg = <0 0x088e3000 0 0x400>; 1325 status = "disabled"; 1326 #phy-cells = <0>; 1327 1328 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 1329 clock-names = "cfg_ahb", "ref"; 1330 1331 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1332 }; 1333 1334 usb_1_qmpphy: phy@88e8000 { 1335 compatible = "qcom,sm6350-qmp-usb3-dp-phy"; 1336 reg = <0 0x088e8000 0 0x3000>; 1337 1338 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1339 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1340 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1341 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1342 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 1343 1344 power-domains = <&gcc USB30_PRIM_GDSC>; 1345 1346 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1347 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1348 reset-names = "phy", "common"; 1349 1350 #clock-cells = <1>; 1351 #phy-cells = <1>; 1352 1353 status = "disabled"; 1354 }; 1355 1356 dc_noc: interconnect@9160000 { 1357 compatible = "qcom,sm6350-dc-noc"; 1358 reg = <0 0x09160000 0 0x3200>; 1359 #interconnect-cells = <2>; 1360 qcom,bcm-voters = <&apps_bcm_voter>; 1361 }; 1362 1363 system-cache-controller@9200000 { 1364 compatible = "qcom,sm6350-llcc"; 1365 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 1366 reg-names = "llcc0_base", "llcc_broadcast_base"; 1367 }; 1368 1369 gem_noc: interconnect@9680000 { 1370 compatible = "qcom,sm6350-gem-noc"; 1371 reg = <0 0x09680000 0 0x3e200>; 1372 #interconnect-cells = <2>; 1373 qcom,bcm-voters = <&apps_bcm_voter>; 1374 }; 1375 1376 npu_noc: interconnect@9990000 { 1377 compatible = "qcom,sm6350-npu-noc"; 1378 reg = <0 0x09990000 0 0x1600>; 1379 #interconnect-cells = <2>; 1380 qcom,bcm-voters = <&apps_bcm_voter>; 1381 }; 1382 1383 usb_1: usb@a6f8800 { 1384 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 1385 reg = <0 0x0a6f8800 0 0x400>; 1386 status = "disabled"; 1387 #address-cells = <2>; 1388 #size-cells = <2>; 1389 ranges; 1390 1391 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1392 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1393 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1394 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1395 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1396 clock-names = "cfg_noc", 1397 "core", 1398 "iface", 1399 "sleep", 1400 "mock_utmi"; 1401 1402 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1403 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 1404 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1405 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 1406 1407 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1408 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1409 1410 power-domains = <&gcc USB30_PRIM_GDSC>; 1411 1412 resets = <&gcc GCC_USB30_PRIM_BCR>; 1413 1414 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, 1415 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1416 interconnect-names = "usb-ddr", "apps-usb"; 1417 1418 usb_1_dwc3: usb@a600000 { 1419 compatible = "snps,dwc3"; 1420 reg = <0 0x0a600000 0 0xcd00>; 1421 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1422 iommus = <&apps_smmu 0x540 0x0>; 1423 snps,dis_u2_susphy_quirk; 1424 snps,dis_enblslpm_quirk; 1425 snps,has-lpm-erratum; 1426 snps,hird-threshold = /bits/ 8 <0x10>; 1427 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 1428 phy-names = "usb2-phy", "usb3-phy"; 1429 }; 1430 }; 1431 1432 cci0: cci@ac4a000 { 1433 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 1434 reg = <0 0x0ac4a000 0 0x1000>; 1435 interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; 1436 power-domains = <&camcc TITAN_TOP_GDSC>; 1437 1438 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1439 <&camcc CAMCC_SOC_AHB_CLK>, 1440 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 1441 <&camcc CAMCC_CPAS_AHB_CLK>, 1442 <&camcc CAMCC_CCI_0_CLK>, 1443 <&camcc CAMCC_CCI_0_CLK_SRC>; 1444 clock-names = "camnoc_axi", 1445 "soc_ahb", 1446 "slow_ahb_src", 1447 "cpas_ahb", 1448 "cci", 1449 "cci_src"; 1450 1451 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1452 <&camcc CAMCC_CCI_0_CLK>; 1453 assigned-clock-rates = <80000000>, <37500000>; 1454 1455 pinctrl-0 = <&cci0_default &cci1_default>; 1456 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 1457 pinctrl-names = "default", "sleep"; 1458 1459 #address-cells = <1>; 1460 #size-cells = <0>; 1461 1462 status = "disabled"; 1463 1464 cci0_i2c0: i2c-bus@0 { 1465 reg = <0>; 1466 clock-frequency = <1000000>; 1467 #address-cells = <1>; 1468 #size-cells = <0>; 1469 }; 1470 1471 cci0_i2c1: i2c-bus@1 { 1472 reg = <1>; 1473 clock-frequency = <1000000>; 1474 #address-cells = <1>; 1475 #size-cells = <0>; 1476 }; 1477 }; 1478 1479 cci1: cci@ac4b000 { 1480 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 1481 reg = <0 0x0ac4b000 0 0x1000>; 1482 interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; 1483 power-domains = <&camcc TITAN_TOP_GDSC>; 1484 1485 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1486 <&camcc CAMCC_SOC_AHB_CLK>, 1487 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 1488 <&camcc CAMCC_CPAS_AHB_CLK>, 1489 <&camcc CAMCC_CCI_1_CLK>, 1490 <&camcc CAMCC_CCI_1_CLK_SRC>; 1491 clock-names = "camnoc_axi", 1492 "soc_ahb", 1493 "slow_ahb_src", 1494 "cpas_ahb", 1495 "cci", 1496 "cci_src"; 1497 1498 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1499 <&camcc CAMCC_CCI_1_CLK>; 1500 assigned-clock-rates = <80000000>, <37500000>; 1501 1502 pinctrl-0 = <&cci2_default>; 1503 pinctrl-1 = <&cci2_sleep>; 1504 pinctrl-names = "default", "sleep"; 1505 1506 #address-cells = <1>; 1507 #size-cells = <0>; 1508 1509 status = "disabled"; 1510 1511 cci1_i2c0: i2c-bus@0 { 1512 reg = <0>; 1513 clock-frequency = <1000000>; 1514 #address-cells = <1>; 1515 #size-cells = <0>; 1516 }; 1517 1518 /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ 1519 }; 1520 1521 camcc: clock-controller@ad00000 { 1522 compatible = "qcom,sm6350-camcc"; 1523 reg = <0 0x0ad00000 0 0x16000>; 1524 clocks = <&rpmhcc RPMH_CXO_CLK>; 1525 #clock-cells = <1>; 1526 #reset-cells = <1>; 1527 #power-domain-cells = <1>; 1528 }; 1529 1530 pdc: interrupt-controller@b220000 { 1531 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 1532 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; 1533 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 1534 <125 63 1>, <126 655 12>, <138 139 15>; 1535 #interrupt-cells = <2>; 1536 interrupt-parent = <&intc>; 1537 interrupt-controller; 1538 }; 1539 1540 tsens0: thermal-sensor@c263000 { 1541 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1542 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1543 <0 0x0c222000 0 0x8>; /* SROT */ 1544 #qcom,sensors = <16>; 1545 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 1546 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 1547 interrupt-names = "uplow", "critical"; 1548 #thermal-sensor-cells = <1>; 1549 }; 1550 1551 tsens1: thermal-sensor@c265000 { 1552 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1553 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1554 <0 0x0c223000 0 0x8>; /* SROT */ 1555 #qcom,sensors = <16>; 1556 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 1557 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 1558 interrupt-names = "uplow", "critical"; 1559 #thermal-sensor-cells = <1>; 1560 }; 1561 1562 aoss_qmp: power-management@c300000 { 1563 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 1564 reg = <0 0x0c300000 0 0x1000>; 1565 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 1566 IRQ_TYPE_EDGE_RISING>; 1567 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 1568 1569 #clock-cells = <0>; 1570 }; 1571 1572 spmi_bus: spmi@c440000 { 1573 compatible = "qcom,spmi-pmic-arb"; 1574 reg = <0 0x0c440000 0 0x1100>, 1575 <0 0x0c600000 0 0x2000000>, 1576 <0 0x0e600000 0 0x100000>, 1577 <0 0x0e700000 0 0xa0000>, 1578 <0 0x0c40a000 0 0x26000>; 1579 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1580 interrupt-names = "periph_irq"; 1581 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1582 qcom,ee = <0>; 1583 qcom,channel = <0>; 1584 #address-cells = <2>; 1585 #size-cells = <0>; 1586 interrupt-controller; 1587 #interrupt-cells = <4>; 1588 }; 1589 1590 tlmm: pinctrl@f100000 { 1591 compatible = "qcom,sm6350-tlmm"; 1592 reg = <0 0x0f100000 0 0x300000>; 1593 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 1602 gpio-controller; 1603 #gpio-cells = <2>; 1604 interrupt-controller; 1605 #interrupt-cells = <2>; 1606 gpio-ranges = <&tlmm 0 0 157>; 1607 1608 cci0_default: cci0-default-state { 1609 pins = "gpio39", "gpio40"; 1610 function = "cci_i2c"; 1611 drive-strength = <2>; 1612 bias-pull-up; 1613 }; 1614 1615 cci0_sleep: cci0-sleep-state { 1616 pins = "gpio39", "gpio40"; 1617 function = "cci_i2c"; 1618 drive-strength = <2>; 1619 bias-pull-down; 1620 }; 1621 1622 cci1_default: cci1-default-state { 1623 pins = "gpio41", "gpio42"; 1624 function = "cci_i2c"; 1625 drive-strength = <2>; 1626 bias-pull-up; 1627 }; 1628 1629 cci1_sleep: cci1-sleep-state { 1630 pins = "gpio41", "gpio42"; 1631 function = "cci_i2c"; 1632 drive-strength = <2>; 1633 bias-pull-down; 1634 }; 1635 1636 cci2_default: cci2-default-state { 1637 pins = "gpio43", "gpio44"; 1638 function = "cci_i2c"; 1639 drive-strength = <2>; 1640 bias-pull-up; 1641 }; 1642 1643 cci2_sleep: cci2-sleep-state { 1644 pins = "gpio43", "gpio44"; 1645 function = "cci_i2c"; 1646 drive-strength = <2>; 1647 bias-pull-down; 1648 }; 1649 1650 sdc2_off_state: sdc2-off-state { 1651 clk-pins { 1652 pins = "sdc2_clk"; 1653 drive-strength = <2>; 1654 bias-disable; 1655 }; 1656 1657 cmd-pins { 1658 pins = "sdc2_cmd"; 1659 drive-strength = <2>; 1660 bias-pull-up; 1661 }; 1662 1663 data-pins { 1664 pins = "sdc2_data"; 1665 drive-strength = <2>; 1666 bias-pull-up; 1667 }; 1668 }; 1669 1670 sdc2_on_state: sdc2-on-state { 1671 clk-pins { 1672 pins = "sdc2_clk"; 1673 drive-strength = <16>; 1674 bias-disable; 1675 }; 1676 1677 cmd-pins { 1678 pins = "sdc2_cmd"; 1679 drive-strength = <10>; 1680 bias-pull-up; 1681 }; 1682 1683 data-pins { 1684 pins = "sdc2_data"; 1685 drive-strength = <10>; 1686 bias-pull-up; 1687 }; 1688 }; 1689 1690 qup_uart9_default: qup-uart9-default-state { 1691 pins = "gpio25", "gpio26"; 1692 function = "qup13_f2"; 1693 drive-strength = <2>; 1694 bias-disable; 1695 }; 1696 1697 qup_i2c0_default: qup-i2c0-default-state { 1698 pins = "gpio0", "gpio1"; 1699 function = "qup00"; 1700 drive-strength = <2>; 1701 bias-pull-up; 1702 }; 1703 1704 qup_i2c2_default: qup-i2c2-default-state { 1705 pins = "gpio45", "gpio46"; 1706 function = "qup02"; 1707 drive-strength = <2>; 1708 bias-pull-up; 1709 }; 1710 1711 qup_i2c6_default: qup-i2c6-default-state { 1712 pins = "gpio13", "gpio14"; 1713 function = "qup10"; 1714 drive-strength = <2>; 1715 bias-pull-up; 1716 }; 1717 1718 qup_i2c7_default: qup-i2c7-default-state { 1719 pins = "gpio27", "gpio28"; 1720 function = "qup11"; 1721 drive-strength = <2>; 1722 bias-pull-up; 1723 }; 1724 1725 qup_i2c8_default: qup-i2c8-default-state { 1726 pins = "gpio19", "gpio20"; 1727 function = "qup12"; 1728 drive-strength = <2>; 1729 bias-pull-up; 1730 }; 1731 1732 qup_i2c10_default: qup-i2c10-default-state { 1733 pins = "gpio4", "gpio5"; 1734 function = "qup14"; 1735 drive-strength = <2>; 1736 bias-pull-up; 1737 }; 1738 }; 1739 1740 apps_smmu: iommu@15000000 { 1741 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 1742 reg = <0 0x15000000 0 0x100000>; 1743 #iommu-cells = <2>; 1744 #global-interrupts = <1>; 1745 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1748 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1749 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1826 }; 1827 1828 intc: interrupt-controller@17a00000 { 1829 compatible = "arm,gic-v3"; 1830 #interrupt-cells = <3>; 1831 interrupt-controller; 1832 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 1833 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 1834 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 1835 }; 1836 1837 watchdog@17c10000 { 1838 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 1839 reg = <0 0x17c10000 0 0x1000>; 1840 clocks = <&sleep_clk>; 1841 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1842 }; 1843 1844 timer@17c20000 { 1845 compatible = "arm,armv7-timer-mem"; 1846 reg = <0x0 0x17c20000 0x0 0x1000>; 1847 clock-frequency = <19200000>; 1848 #address-cells = <1>; 1849 #size-cells = <1>; 1850 ranges = <0 0 0 0x20000000>; 1851 1852 frame@17c21000 { 1853 frame-number = <0>; 1854 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1856 reg = <0x17c21000 0x1000>, 1857 <0x17c22000 0x1000>; 1858 }; 1859 1860 frame@17c23000 { 1861 frame-number = <1>; 1862 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1863 reg = <0x17c23000 0x1000>; 1864 status = "disabled"; 1865 }; 1866 1867 frame@17c25000 { 1868 frame-number = <2>; 1869 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1870 reg = <0x17c25000 0x1000>; 1871 status = "disabled"; 1872 }; 1873 1874 frame@17c27000 { 1875 frame-number = <3>; 1876 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1877 reg = <0x17c27000 0x1000>; 1878 status = "disabled"; 1879 }; 1880 1881 frame@17c29000 { 1882 frame-number = <4>; 1883 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1884 reg = <0x17c29000 0x1000>; 1885 status = "disabled"; 1886 }; 1887 1888 frame@17c2b000 { 1889 frame-number = <5>; 1890 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1891 reg = <0x17c2b000 0x1000>; 1892 status = "disabled"; 1893 }; 1894 1895 frame@17c2d000 { 1896 frame-number = <6>; 1897 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1898 reg = <0x17c2d000 0x1000>; 1899 status = "disabled"; 1900 }; 1901 }; 1902 1903 wifi: wifi@18800000 { 1904 compatible = "qcom,wcn3990-wifi"; 1905 reg = <0 0x18800000 0 0x800000>; 1906 reg-names = "membase"; 1907 memory-region = <&wlan_fw_mem>; 1908 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 1909 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 1910 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 1911 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 1912 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1913 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1914 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 1915 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 1917 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 1920 iommus = <&apps_smmu 0x20 0x1>; 1921 qcom,msa-fixed-perm; 1922 status = "disabled"; 1923 }; 1924 1925 apps_rsc: rsc@18200000 { 1926 compatible = "qcom,rpmh-rsc"; 1927 label = "apps_rsc"; 1928 reg = <0x0 0x18200000 0x0 0x10000>, 1929 <0x0 0x18210000 0x0 0x10000>, 1930 <0x0 0x18220000 0x0 0x10000>; 1931 reg-names = "drv-0", "drv-1", "drv-2"; 1932 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1933 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1934 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1935 qcom,tcs-offset = <0xd00>; 1936 qcom,drv-id = <2>; 1937 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 1938 <WAKE_TCS 3>, <CONTROL_TCS 1>; 1939 1940 rpmhcc: clock-controller { 1941 compatible = "qcom,sm6350-rpmh-clk"; 1942 #clock-cells = <1>; 1943 clock-names = "xo"; 1944 clocks = <&xo_board>; 1945 }; 1946 1947 rpmhpd: power-controller { 1948 compatible = "qcom,sm6350-rpmhpd"; 1949 #power-domain-cells = <1>; 1950 operating-points-v2 = <&rpmhpd_opp_table>; 1951 1952 rpmhpd_opp_table: opp-table { 1953 compatible = "operating-points-v2"; 1954 1955 rpmhpd_opp_ret: opp1 { 1956 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1957 }; 1958 1959 rpmhpd_opp_min_svs: opp2 { 1960 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1961 }; 1962 1963 rpmhpd_opp_low_svs: opp3 { 1964 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1965 }; 1966 1967 rpmhpd_opp_svs: opp4 { 1968 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1969 }; 1970 1971 rpmhpd_opp_svs_l1: opp5 { 1972 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1973 }; 1974 1975 rpmhpd_opp_nom: opp6 { 1976 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1977 }; 1978 1979 rpmhpd_opp_nom_l1: opp7 { 1980 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1981 }; 1982 1983 rpmhpd_opp_nom_l2: opp8 { 1984 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1985 }; 1986 1987 rpmhpd_opp_turbo: opp9 { 1988 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1989 }; 1990 1991 rpmhpd_opp_turbo_l1: opp10 { 1992 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1993 }; 1994 }; 1995 }; 1996 1997 apps_bcm_voter: bcm-voter { 1998 compatible = "qcom,bcm-voter"; 1999 }; 2000 }; 2001 2002 osm_l3: interconnect@18321000 { 2003 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3"; 2004 reg = <0x0 0x18321000 0x0 0x1000>; 2005 2006 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2007 clock-names = "xo", "alternate"; 2008 2009 #interconnect-cells = <1>; 2010 }; 2011 2012 cpufreq_hw: cpufreq@18323000 { 2013 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw"; 2014 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; 2015 reg-names = "freq-domain0", "freq-domain1"; 2016 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2017 clock-names = "xo", "alternate"; 2018 2019 #freq-domain-cells = <1>; 2020 #clock-cells = <1>; 2021 }; 2022 }; 2023 2024 timer { 2025 compatible = "arm,armv8-timer"; 2026 clock-frequency = <19200000>; 2027 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2028 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2029 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2030 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2031 }; 2032}; 2033