1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6350.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/mailbox/qcom-ipcc.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,rpmh-rsc.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 clocks { 20 xo_board: xo-board { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <76800000>; 24 clock-output-names = "xo_board"; 25 }; 26 27 sleep_clk: sleep-clk { 28 compatible = "fixed-clock"; 29 clock-frequency = <32764>; 30 #clock-cells = <0>; 31 }; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 CPU0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "qcom,kryo560"; 41 reg = <0x0 0x0>; 42 enable-method = "psci"; 43 capacity-dmips-mhz = <1024>; 44 dynamic-power-coefficient = <100>; 45 next-level-cache = <&L2_0>; 46 qcom,freq-domain = <&cpufreq_hw 0>; 47 #cooling-cells = <2>; 48 L2_0: l2-cache { 49 compatible = "cache"; 50 next-level-cache = <&L3_0>; 51 L3_0: l3-cache { 52 compatible = "cache"; 53 }; 54 }; 55 }; 56 57 CPU1: cpu@100 { 58 device_type = "cpu"; 59 compatible = "qcom,kryo560"; 60 reg = <0x0 0x100>; 61 enable-method = "psci"; 62 capacity-dmips-mhz = <1024>; 63 dynamic-power-coefficient = <100>; 64 next-level-cache = <&L2_100>; 65 qcom,freq-domain = <&cpufreq_hw 0>; 66 #cooling-cells = <2>; 67 L2_100: l2-cache { 68 compatible = "cache"; 69 next-level-cache = <&L3_0>; 70 }; 71 }; 72 73 CPU2: cpu@200 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo560"; 76 reg = <0x0 0x200>; 77 enable-method = "psci"; 78 capacity-dmips-mhz = <1024>; 79 dynamic-power-coefficient = <100>; 80 next-level-cache = <&L2_200>; 81 qcom,freq-domain = <&cpufreq_hw 0>; 82 #cooling-cells = <2>; 83 L2_200: l2-cache { 84 compatible = "cache"; 85 next-level-cache = <&L3_0>; 86 }; 87 }; 88 89 CPU3: cpu@300 { 90 device_type = "cpu"; 91 compatible = "qcom,kryo560"; 92 reg = <0x0 0x300>; 93 enable-method = "psci"; 94 capacity-dmips-mhz = <1024>; 95 dynamic-power-coefficient = <100>; 96 next-level-cache = <&L2_300>; 97 qcom,freq-domain = <&cpufreq_hw 0>; 98 #cooling-cells = <2>; 99 L2_300: l2-cache { 100 compatible = "cache"; 101 next-level-cache = <&L3_0>; 102 }; 103 }; 104 105 CPU4: cpu@400 { 106 device_type = "cpu"; 107 compatible = "qcom,kryo560"; 108 reg = <0x0 0x400>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <1024>; 111 dynamic-power-coefficient = <100>; 112 next-level-cache = <&L2_400>; 113 qcom,freq-domain = <&cpufreq_hw 0>; 114 #cooling-cells = <2>; 115 L2_400: l2-cache { 116 compatible = "cache"; 117 next-level-cache = <&L3_0>; 118 }; 119 }; 120 121 CPU5: cpu@500 { 122 device_type = "cpu"; 123 compatible = "qcom,kryo560"; 124 reg = <0x0 0x500>; 125 enable-method = "psci"; 126 capacity-dmips-mhz = <1024>; 127 dynamic-power-coefficient = <100>; 128 next-level-cache = <&L2_500>; 129 qcom,freq-domain = <&cpufreq_hw 0>; 130 #cooling-cells = <2>; 131 L2_500: l2-cache { 132 compatible = "cache"; 133 next-level-cache = <&L3_0>; 134 }; 135 136 }; 137 138 CPU6: cpu@600 { 139 device_type = "cpu"; 140 compatible = "qcom,kryo560"; 141 reg = <0x0 0x600>; 142 enable-method = "psci"; 143 capacity-dmips-mhz = <1894>; 144 dynamic-power-coefficient = <703>; 145 next-level-cache = <&L2_600>; 146 qcom,freq-domain = <&cpufreq_hw 1>; 147 #cooling-cells = <2>; 148 L2_600: l2-cache { 149 compatible = "cache"; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU7: cpu@700 { 155 device_type = "cpu"; 156 compatible = "qcom,kryo560"; 157 reg = <0x0 0x700>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <1894>; 160 dynamic-power-coefficient = <703>; 161 next-level-cache = <&L2_700>; 162 qcom,freq-domain = <&cpufreq_hw 1>; 163 #cooling-cells = <2>; 164 L2_700: l2-cache { 165 compatible = "cache"; 166 next-level-cache = <&L3_0>; 167 }; 168 }; 169 170 cpu-map { 171 cluster0 { 172 core0 { 173 cpu = <&CPU0>; 174 }; 175 176 core1 { 177 cpu = <&CPU1>; 178 }; 179 180 core2 { 181 cpu = <&CPU2>; 182 }; 183 184 core3 { 185 cpu = <&CPU3>; 186 }; 187 188 core4 { 189 cpu = <&CPU4>; 190 }; 191 192 core5 { 193 cpu = <&CPU5>; 194 }; 195 196 core6 { 197 cpu = <&CPU6>; 198 }; 199 200 core7 { 201 cpu = <&CPU7>; 202 }; 203 }; 204 }; 205 }; 206 207 firmware { 208 scm: scm { 209 compatible = "qcom,scm-sm6350", "qcom,scm"; 210 #reset-cells = <1>; 211 }; 212 }; 213 214 memory@80000000 { 215 device_type = "memory"; 216 /* We expect the bootloader to fill in the size */ 217 reg = <0x0 0x80000000 0x0 0x0>; 218 }; 219 220 pmu { 221 compatible = "arm,armv8-pmuv3"; 222 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 223 }; 224 225 psci { 226 compatible = "arm,psci-1.0"; 227 method = "smc"; 228 }; 229 230 reserved_memory: reserved-memory { 231 #address-cells = <2>; 232 #size-cells = <2>; 233 ranges; 234 235 hyp_mem: memory@80000000 { 236 reg = <0 0x80000000 0 0x600000>; 237 no-map; 238 }; 239 240 xbl_aop_mem: memory@80700000 { 241 reg = <0 0x80700000 0 0x160000>; 242 no-map; 243 }; 244 245 cmd_db: memory@80860000 { 246 compatible = "qcom,cmd-db"; 247 reg = <0 0x80860000 0 0x20000>; 248 no-map; 249 }; 250 251 sec_apps_mem: memory@808ff000 { 252 reg = <0 0x808ff000 0 0x1000>; 253 no-map; 254 }; 255 256 smem_mem: memory@80900000 { 257 reg = <0 0x80900000 0 0x200000>; 258 no-map; 259 }; 260 261 cdsp_sec_mem: memory@80b00000 { 262 reg = <0 0x80b00000 0 0x1e00000>; 263 no-map; 264 }; 265 266 pil_camera_mem: memory@86000000 { 267 reg = <0 0x86000000 0 0x500000>; 268 no-map; 269 }; 270 271 pil_npu_mem: memory@86500000 { 272 reg = <0 0x86500000 0 0x500000>; 273 no-map; 274 }; 275 276 pil_video_mem: memory@86a00000 { 277 reg = <0 0x86a00000 0 0x500000>; 278 no-map; 279 }; 280 281 pil_cdsp_mem: memory@86f00000 { 282 reg = <0 0x86f00000 0 0x1e00000>; 283 no-map; 284 }; 285 286 pil_adsp_mem: memory@88d00000 { 287 reg = <0 0x88d00000 0 0x2800000>; 288 no-map; 289 }; 290 291 wlan_fw_mem: memory@8b500000 { 292 reg = <0 0x8b500000 0 0x200000>; 293 no-map; 294 }; 295 296 pil_ipa_fw_mem: memory@8b700000 { 297 reg = <0 0x8b700000 0 0x10000>; 298 no-map; 299 }; 300 301 pil_ipa_gsi_mem: memory@8b710000 { 302 reg = <0 0x8b710000 0 0x5400>; 303 no-map; 304 }; 305 306 pil_gpu_mem: memory@8b715400 { 307 reg = <0 0x8b715400 0 0x2000>; 308 no-map; 309 }; 310 311 pil_modem_mem: memory@8b800000 { 312 reg = <0 0x8b800000 0 0xf800000>; 313 no-map; 314 }; 315 316 cont_splash_memory: memory@a0000000 { 317 reg = <0 0xa0000000 0 0x2300000>; 318 no-map; 319 }; 320 321 dfps_data_memory: memory@a2300000 { 322 reg = <0 0xa2300000 0 0x100000>; 323 no-map; 324 }; 325 326 removed_region: memory@c0000000 { 327 reg = <0 0xc0000000 0 0x3900000>; 328 no-map; 329 }; 330 331 debug_region: memory@ffb00000 { 332 reg = <0 0xffb00000 0 0xc0000>; 333 no-map; 334 }; 335 336 last_log_region: memory@ffbc0000 { 337 reg = <0 0xffbc0000 0 0x40000>; 338 no-map; 339 }; 340 341 ramoops: ramoops@ffc00000 { 342 compatible = "removed-dma-pool", "ramoops"; 343 reg = <0 0xffc00000 0 0x00100000>; 344 record-size = <0x1000>; 345 console-size = <0x40000>; 346 ftrace-size = <0x0>; 347 msg-size = <0x20000 0x20000>; 348 cc-size = <0x0>; 349 no-map; 350 }; 351 352 cmdline_region: memory@ffd00000 { 353 reg = <0 0xffd00000 0 0x1000>; 354 no-map; 355 }; 356 }; 357 358 smem { 359 compatible = "qcom,smem"; 360 memory-region = <&smem_mem>; 361 hwlocks = <&tcsr_mutex 3>; 362 }; 363 364 soc: soc@0 { 365 #address-cells = <2>; 366 #size-cells = <2>; 367 ranges = <0 0 0 0 0x10 0>; 368 dma-ranges = <0 0 0 0 0x10 0>; 369 compatible = "simple-bus"; 370 371 gcc: clock-controller@100000 { 372 compatible = "qcom,gcc-sm6350"; 373 reg = <0 0x00100000 0 0x1f0000>; 374 #clock-cells = <1>; 375 #reset-cells = <1>; 376 #power-domain-cells = <1>; 377 clock-names = "bi_tcxo", 378 "bi_tcxo_ao", 379 "sleep_clk"; 380 clocks = <&rpmhcc RPMH_CXO_CLK>, 381 <&rpmhcc RPMH_CXO_CLK_A>, 382 <&sleep_clk>; 383 }; 384 385 ipcc: mailbox@408000 { 386 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 387 reg = <0 0x00408000 0 0x1000>; 388 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 389 interrupt-controller; 390 #interrupt-cells = <3>; 391 #mbox-cells = <2>; 392 }; 393 394 rng: rng@793000 { 395 compatible = "qcom,prng-ee"; 396 reg = <0 0x00793000 0 0x1000>; 397 clocks = <&gcc GCC_PRNG_AHB_CLK>; 398 clock-names = "core"; 399 }; 400 401 sdhc_1: sdhci@7c4000 { 402 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 403 reg = <0 0x007c4000 0 0x1000>, 404 <0 0x007c5000 0 0x1000>, 405 <0 0x007c8000 0 0x8000>; 406 reg-names = "hc", "cqhci", "ice"; 407 408 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 410 interrupt-names = "hc_irq", "pwr_irq"; 411 412 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 413 <&gcc GCC_SDCC1_APPS_CLK>, 414 <&rpmhcc RPMH_CXO_CLK>; 415 clock-names = "iface", "core", "xo"; 416 qcom,dll-config = <0x000f642c>; 417 qcom,ddr-config = <0x80040868>; 418 power-domains = <&rpmhpd 0>; 419 operating-points-v2 = <&sdhc1_opp_table>; 420 bus-width = <8>; 421 non-removable; 422 supports-cqe; 423 424 status = "disabled"; 425 426 sdhc1_opp_table: sdhc1-opp-table { 427 compatible = "operating-points-v2"; 428 429 opp-19200000 { 430 opp-hz = /bits/ 64 <19200000>; 431 required-opps = <&rpmhpd_opp_min_svs>; 432 }; 433 434 opp-100000000 { 435 opp-hz = /bits/ 64 <100000000>; 436 required-opps = <&rpmhpd_opp_low_svs>; 437 }; 438 439 opp-384000000 { 440 opp-hz = /bits/ 64 <384000000>; 441 required-opps = <&rpmhpd_opp_svs_l1>; 442 }; 443 }; 444 }; 445 446 qupv3_id_1: geniqup@9c0000 { 447 compatible = "qcom,geni-se-qup"; 448 reg = <0x0 0x9c0000 0x0 0x2000>; 449 clock-names = "m-ahb", "s-ahb"; 450 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 451 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 452 #address-cells = <2>; 453 #size-cells = <2>; 454 iommus = <&apps_smmu 0x4c3 0x0>; 455 ranges; 456 status = "disabled"; 457 458 uart2: serial@98c000 { 459 compatible = "qcom,geni-debug-uart"; 460 reg = <0 0x98c000 0 0x4000>; 461 clock-names = "se"; 462 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&qup_uart2_default>; 465 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 466 status = "disabled"; 467 }; 468 }; 469 470 tcsr_mutex: hwlock@1f40000 { 471 compatible = "qcom,tcsr-mutex"; 472 reg = <0x0 0x01f40000 0x0 0x40000>; 473 #hwlock-cells = <1>; 474 }; 475 476 sdhc_2: sdhci@8804000 { 477 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 478 reg = <0 0x08804000 0 0x1000>; 479 480 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 482 interrupt-names = "hc_irq", "pwr_irq"; 483 484 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 485 <&gcc GCC_SDCC2_APPS_CLK>, 486 <&rpmhcc RPMH_CXO_CLK>; 487 clock-names = "iface", "core", "xo"; 488 qcom,dll-config = <0x0007642c>; 489 qcom,ddr-config = <0x80040868>; 490 power-domains = <&rpmhpd 0>; 491 operating-points-v2 = <&sdhc2_opp_table>; 492 bus-width = <4>; 493 494 status = "disabled"; 495 496 sdhc2_opp_table: sdhc2-opp-table { 497 compatible = "operating-points-v2"; 498 499 opp-100000000 { 500 opp-hz = /bits/ 64 <100000000>; 501 required-opps = <&rpmhpd_opp_svs_l1>; 502 }; 503 504 opp-202000000 { 505 opp-hz = /bits/ 64 <202000000>; 506 required-opps = <&rpmhpd_opp_nom>; 507 }; 508 }; 509 }; 510 511 usb_1_hsphy: phy@88e3000 { 512 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 513 reg = <0 0x088e3000 0 0x400>; 514 status = "disabled"; 515 #phy-cells = <0>; 516 517 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 518 clock-names = "cfg_ahb", "ref"; 519 520 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 521 }; 522 523 usb_1_qmpphy: phy@88e9000 { 524 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 525 reg = <0 0x088e9000 0 0x200>, 526 <0 0x088e8000 0 0x40>, 527 <0 0x088ea000 0 0x200>; 528 status = "disabled"; 529 #address-cells = <2>; 530 #size-cells = <2>; 531 ranges; 532 533 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 534 <&rpmhcc RPMH_QLINK_CLK>, 535 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 536 <&xo_board>; 537 clock-names = "aux", "ref", "com_aux", "cfg_ahb"; 538 539 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 540 <&gcc GCC_USB3_PHY_PRIM_BCR>; 541 reset-names = "phy", "common"; 542 543 usb_1_ssphy: usb3-phy@88e9200 { 544 reg = <0 0x088e9200 0 0x200>, 545 <0 0x088e9400 0 0x200>, 546 <0 0x088e9c00 0 0x400>, 547 <0 0x088e9600 0 0x200>, 548 <0 0x088e9800 0 0x200>, 549 <0 0x088e9a00 0 0x100>; 550 #clock-cells = <0>; 551 #phy-cells = <0>; 552 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 553 clock-names = "pipe0"; 554 clock-output-names = "usb3_phy_pipe_clk_src"; 555 }; 556 557 dp_phy: dp-phy@88ea200 { 558 reg = <0 0x088ea200 0 0x200>, 559 <0 0x088ea400 0 0x200>, 560 <0 0x088eac00 0 0x400>, 561 <0 0x088ea600 0 0x200>, 562 <0 0x088ea800 0 0x200>, 563 <0 0x088eaa00 0 0x100>; 564 #phy-cells = <0>; 565 #clock-cells = <1>; 566 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 567 clock-names = "pipe0"; 568 clock-output-names = "usb3_phy_pipe_clk_src"; 569 }; 570 }; 571 572 system-cache-controller@9200000 { 573 compatible = "qcom,sm6350-llcc"; 574 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 575 reg-names = "llcc_base", "llcc_broadcast_base"; 576 }; 577 578 usb_1: usb@a6f8800 { 579 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 580 reg = <0 0x0a6f8800 0 0x400>; 581 status = "disabled"; 582 #address-cells = <2>; 583 #size-cells = <2>; 584 ranges; 585 586 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 587 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 588 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 589 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 590 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 591 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 592 "sleep"; 593 594 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 595 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 596 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 597 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 598 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 599 "dm_hs_phy_irq", "ss_phy_irq"; 600 601 power-domains = <&gcc USB30_PRIM_GDSC>; 602 603 resets = <&gcc GCC_USB30_PRIM_BCR>; 604 605 usb_1_dwc3: usb@a600000 { 606 compatible = "snps,dwc3"; 607 reg = <0 0x0a600000 0 0xcd00>; 608 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 609 iommus = <&apps_smmu 0x540 0x0>; 610 snps,dis_u2_susphy_quirk; 611 snps,dis_enblslpm_quirk; 612 snps,has-lpm-erratum; 613 snps,hird-threshold = /bits/ 8 <0x10>; 614 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 615 phy-names = "usb2-phy", "usb3-phy"; 616 }; 617 }; 618 619 pdc: interrupt-controller@b220000 { 620 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 621 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; 622 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 623 <125 63 1>, <126 655 12>, <138 139 15>; 624 #interrupt-cells = <2>; 625 interrupt-parent = <&intc>; 626 interrupt-controller; 627 }; 628 629 tsens0: thermal-sensor@c263000 { 630 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 631 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 632 <0 0x0c222000 0 0x8>; /* SROT */ 633 #qcom,sensors = <16>; 634 interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 635 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 636 interrupt-names = "uplow", "critical"; 637 #thermal-sensor-cells = <1>; 638 }; 639 640 tsens1: thermal-sensor@c265000 { 641 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 642 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 643 <0 0x0c223000 0 0x8>; /* SROT */ 644 #qcom,sensors = <16>; 645 interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 646 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 647 interrupt-names = "uplow", "critical"; 648 #thermal-sensor-cells = <1>; 649 }; 650 651 aoss_qmp: power-controller@c300000 { 652 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 653 reg = <0 0x0c300000 0 0x1000>; 654 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 655 IRQ_TYPE_EDGE_RISING>; 656 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 657 658 #clock-cells = <0>; 659 #power-domain-cells = <1>; 660 }; 661 662 spmi_bus: spmi@c440000 { 663 compatible = "qcom,spmi-pmic-arb"; 664 reg = <0 0xc440000 0 0x1100>, 665 <0 0xc600000 0 0x2000000>, 666 <0 0xe600000 0 0x100000>, 667 <0 0xe700000 0 0xa0000>, 668 <0 0xc40a000 0 0x26000>; 669 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 670 interrupt-names = "periph_irq"; 671 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 672 qcom,ee = <0>; 673 qcom,channel = <0>; 674 #address-cells = <2>; 675 #size-cells = <0>; 676 interrupt-controller; 677 #interrupt-cells = <4>; 678 }; 679 680 tlmm: pinctrl@f100000 { 681 compatible = "qcom,sm6350-tlmm"; 682 reg = <0 0x0f100000 0 0x300000>; 683 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 692 gpio-controller; 693 #gpio-cells = <2>; 694 interrupt-controller; 695 #interrupt-cells = <2>; 696 gpio-ranges = <&tlmm 0 0 157>; 697 698 qup_uart2_default: qup-uart2-default { 699 pins = "gpio25", "gpio26"; 700 function = "qup13_f2"; 701 drive-strength = <2>; 702 bias-disable; 703 }; 704 }; 705 706 apps_smmu: iommu@15000000 { 707 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 708 reg = <0 0x15000000 0 0x100000>; 709 #iommu-cells = <2>; 710 #global-interrupts = <1>; 711 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 792 }; 793 794 intc: interrupt-controller@17a00000 { 795 compatible = "arm,gic-v3"; 796 #interrupt-cells = <3>; 797 interrupt-controller; 798 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 799 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 800 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 801 }; 802 803 watchdog@17c10000 { 804 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 805 reg = <0 0x17c10000 0 0x1000>; 806 clocks = <&sleep_clk>; 807 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 808 }; 809 810 timer@17c20000 { 811 compatible = "arm,armv7-timer-mem"; 812 reg = <0x0 0x17c20000 0x0 0x1000>; 813 clock-frequency = <19200000>; 814 #address-cells = <2>; 815 #size-cells = <2>; 816 ranges; 817 818 frame@17c21000 { 819 frame-number = <0>; 820 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 822 reg = <0x0 0x17c21000 0x0 0x1000>, 823 <0x0 0x17c22000 0x0 0x1000>; 824 }; 825 826 frame@17c23000 { 827 frame-number = <1>; 828 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 829 reg = <0x0 0x17c23000 0x0 0x1000>; 830 status = "disabled"; 831 }; 832 833 frame@17c25000 { 834 frame-number = <2>; 835 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 836 reg = <0x0 0x17c25000 0x0 0x1000>; 837 status = "disabled"; 838 }; 839 840 frame@17c27000 { 841 frame-number = <3>; 842 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 843 reg = <0x0 0x17c27000 0x0 0x1000>; 844 status = "disabled"; 845 }; 846 847 frame@17c29000 { 848 frame-number = <4>; 849 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 850 reg = <0x0 0x17c29000 0x0 0x1000>; 851 status = "disabled"; 852 }; 853 854 frame@17c2b000 { 855 frame-number = <5>; 856 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 857 reg = <0x0 0x17c2b000 0x0 0x1000>; 858 status = "disabled"; 859 }; 860 861 frame@17c2d000 { 862 frame-number = <6>; 863 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 864 reg = <0x0 0x17c2d000 0x0 0x1000>; 865 status = "disabled"; 866 }; 867 }; 868 869 apps_rsc: rsc@18200000 { 870 compatible = "qcom,rpmh-rsc"; 871 label = "apps_rsc"; 872 reg = <0x0 0x18200000 0x0 0x10000>, 873 <0x0 0x18210000 0x0 0x10000>, 874 <0x0 0x18220000 0x0 0x10000>; 875 reg-names = "drv-0", "drv-1", "drv-2"; 876 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 879 qcom,tcs-offset = <0xd00>; 880 qcom,drv-id = <2>; 881 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 882 <WAKE_TCS 3>, <CONTROL_TCS 1>; 883 884 rpmhcc: clock-controller { 885 compatible = "qcom,sm6350-rpmh-clk"; 886 #clock-cells = <1>; 887 clock-names = "xo"; 888 clocks = <&xo_board>; 889 }; 890 891 rpmhpd: power-controller { 892 compatible = "qcom,sm6350-rpmhpd"; 893 #power-domain-cells = <1>; 894 operating-points-v2 = <&rpmhpd_opp_table>; 895 896 rpmhpd_opp_table: opp-table { 897 compatible = "operating-points-v2"; 898 899 rpmhpd_opp_ret: opp1 { 900 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 901 }; 902 903 rpmhpd_opp_min_svs: opp2 { 904 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 905 }; 906 907 rpmhpd_opp_low_svs: opp3 { 908 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 909 }; 910 911 rpmhpd_opp_svs: opp4 { 912 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 913 }; 914 915 rpmhpd_opp_svs_l1: opp5 { 916 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 917 }; 918 919 rpmhpd_opp_nom: opp6 { 920 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 921 }; 922 923 rpmhpd_opp_nom_l1: opp7 { 924 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 925 }; 926 927 rpmhpd_opp_nom_l2: opp8 { 928 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 929 }; 930 931 rpmhpd_opp_turbo: opp9 { 932 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 933 }; 934 935 rpmhpd_opp_turbo_l1: opp10 { 936 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 937 }; 938 }; 939 }; 940 941 apps_bcm_voter: bcm_voter { 942 compatible = "qcom,bcm-voter"; 943 }; 944 }; 945 946 cpufreq_hw: cpufreq@18323000 { 947 compatible = "qcom,cpufreq-hw"; 948 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; 949 reg-names = "freq-domain0", "freq-domain1"; 950 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 951 clock-names = "xo", "alternate"; 952 953 #freq-domain-cells = <1>; 954 }; 955 }; 956 957 timer { 958 compatible = "arm,armv8-timer"; 959 clock-frequency = <19200000>; 960 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 961 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 962 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 963 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 964 }; 965}; 966