1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sm6350.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/dma/qcom-gpi.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interconnect/qcom,sm6350.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/mailbox/qcom-ipcc.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/soc/qcom,rpmh-rsc.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 clocks { 23 xo_board: xo-board { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <76800000>; 27 clock-output-names = "xo_board"; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 clock-frequency = <32764>; 33 #clock-cells = <0>; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 CPU0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "qcom,kryo560"; 44 reg = <0x0 0x0>; 45 enable-method = "psci"; 46 capacity-dmips-mhz = <1024>; 47 dynamic-power-coefficient = <100>; 48 next-level-cache = <&L2_0>; 49 qcom,freq-domain = <&cpufreq_hw 0>; 50 #cooling-cells = <2>; 51 L2_0: l2-cache { 52 compatible = "cache"; 53 next-level-cache = <&L3_0>; 54 L3_0: l3-cache { 55 compatible = "cache"; 56 }; 57 }; 58 }; 59 60 CPU1: cpu@100 { 61 device_type = "cpu"; 62 compatible = "qcom,kryo560"; 63 reg = <0x0 0x100>; 64 enable-method = "psci"; 65 capacity-dmips-mhz = <1024>; 66 dynamic-power-coefficient = <100>; 67 next-level-cache = <&L2_100>; 68 qcom,freq-domain = <&cpufreq_hw 0>; 69 #cooling-cells = <2>; 70 L2_100: l2-cache { 71 compatible = "cache"; 72 next-level-cache = <&L3_0>; 73 }; 74 }; 75 76 CPU2: cpu@200 { 77 device_type = "cpu"; 78 compatible = "qcom,kryo560"; 79 reg = <0x0 0x200>; 80 enable-method = "psci"; 81 capacity-dmips-mhz = <1024>; 82 dynamic-power-coefficient = <100>; 83 next-level-cache = <&L2_200>; 84 qcom,freq-domain = <&cpufreq_hw 0>; 85 #cooling-cells = <2>; 86 L2_200: l2-cache { 87 compatible = "cache"; 88 next-level-cache = <&L3_0>; 89 }; 90 }; 91 92 CPU3: cpu@300 { 93 device_type = "cpu"; 94 compatible = "qcom,kryo560"; 95 reg = <0x0 0x300>; 96 enable-method = "psci"; 97 capacity-dmips-mhz = <1024>; 98 dynamic-power-coefficient = <100>; 99 next-level-cache = <&L2_300>; 100 qcom,freq-domain = <&cpufreq_hw 0>; 101 #cooling-cells = <2>; 102 L2_300: l2-cache { 103 compatible = "cache"; 104 next-level-cache = <&L3_0>; 105 }; 106 }; 107 108 CPU4: cpu@400 { 109 device_type = "cpu"; 110 compatible = "qcom,kryo560"; 111 reg = <0x0 0x400>; 112 enable-method = "psci"; 113 capacity-dmips-mhz = <1024>; 114 dynamic-power-coefficient = <100>; 115 next-level-cache = <&L2_400>; 116 qcom,freq-domain = <&cpufreq_hw 0>; 117 #cooling-cells = <2>; 118 L2_400: l2-cache { 119 compatible = "cache"; 120 next-level-cache = <&L3_0>; 121 }; 122 }; 123 124 CPU5: cpu@500 { 125 device_type = "cpu"; 126 compatible = "qcom,kryo560"; 127 reg = <0x0 0x500>; 128 enable-method = "psci"; 129 capacity-dmips-mhz = <1024>; 130 dynamic-power-coefficient = <100>; 131 next-level-cache = <&L2_500>; 132 qcom,freq-domain = <&cpufreq_hw 0>; 133 #cooling-cells = <2>; 134 L2_500: l2-cache { 135 compatible = "cache"; 136 next-level-cache = <&L3_0>; 137 }; 138 139 }; 140 141 CPU6: cpu@600 { 142 device_type = "cpu"; 143 compatible = "qcom,kryo560"; 144 reg = <0x0 0x600>; 145 enable-method = "psci"; 146 capacity-dmips-mhz = <1894>; 147 dynamic-power-coefficient = <703>; 148 next-level-cache = <&L2_600>; 149 qcom,freq-domain = <&cpufreq_hw 1>; 150 #cooling-cells = <2>; 151 L2_600: l2-cache { 152 compatible = "cache"; 153 next-level-cache = <&L3_0>; 154 }; 155 }; 156 157 CPU7: cpu@700 { 158 device_type = "cpu"; 159 compatible = "qcom,kryo560"; 160 reg = <0x0 0x700>; 161 enable-method = "psci"; 162 capacity-dmips-mhz = <1894>; 163 dynamic-power-coefficient = <703>; 164 next-level-cache = <&L2_700>; 165 qcom,freq-domain = <&cpufreq_hw 1>; 166 #cooling-cells = <2>; 167 L2_700: l2-cache { 168 compatible = "cache"; 169 next-level-cache = <&L3_0>; 170 }; 171 }; 172 173 cpu-map { 174 cluster0 { 175 core0 { 176 cpu = <&CPU0>; 177 }; 178 179 core1 { 180 cpu = <&CPU1>; 181 }; 182 183 core2 { 184 cpu = <&CPU2>; 185 }; 186 187 core3 { 188 cpu = <&CPU3>; 189 }; 190 191 core4 { 192 cpu = <&CPU4>; 193 }; 194 195 core5 { 196 cpu = <&CPU5>; 197 }; 198 199 core6 { 200 cpu = <&CPU6>; 201 }; 202 203 core7 { 204 cpu = <&CPU7>; 205 }; 206 }; 207 }; 208 }; 209 210 firmware { 211 scm: scm { 212 compatible = "qcom,scm-sm6350", "qcom,scm"; 213 #reset-cells = <1>; 214 }; 215 }; 216 217 memory@80000000 { 218 device_type = "memory"; 219 /* We expect the bootloader to fill in the size */ 220 reg = <0x0 0x80000000 0x0 0x0>; 221 }; 222 223 pmu { 224 compatible = "arm,armv8-pmuv3"; 225 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 226 }; 227 228 psci { 229 compatible = "arm,psci-1.0"; 230 method = "smc"; 231 }; 232 233 reserved_memory: reserved-memory { 234 #address-cells = <2>; 235 #size-cells = <2>; 236 ranges; 237 238 hyp_mem: memory@80000000 { 239 reg = <0 0x80000000 0 0x600000>; 240 no-map; 241 }; 242 243 xbl_aop_mem: memory@80700000 { 244 reg = <0 0x80700000 0 0x160000>; 245 no-map; 246 }; 247 248 cmd_db: memory@80860000 { 249 compatible = "qcom,cmd-db"; 250 reg = <0 0x80860000 0 0x20000>; 251 no-map; 252 }; 253 254 sec_apps_mem: memory@808ff000 { 255 reg = <0 0x808ff000 0 0x1000>; 256 no-map; 257 }; 258 259 smem_mem: memory@80900000 { 260 reg = <0 0x80900000 0 0x200000>; 261 no-map; 262 }; 263 264 cdsp_sec_mem: memory@80b00000 { 265 reg = <0 0x80b00000 0 0x1e00000>; 266 no-map; 267 }; 268 269 pil_camera_mem: memory@86000000 { 270 reg = <0 0x86000000 0 0x500000>; 271 no-map; 272 }; 273 274 pil_npu_mem: memory@86500000 { 275 reg = <0 0x86500000 0 0x500000>; 276 no-map; 277 }; 278 279 pil_video_mem: memory@86a00000 { 280 reg = <0 0x86a00000 0 0x500000>; 281 no-map; 282 }; 283 284 pil_cdsp_mem: memory@86f00000 { 285 reg = <0 0x86f00000 0 0x1e00000>; 286 no-map; 287 }; 288 289 pil_adsp_mem: memory@88d00000 { 290 reg = <0 0x88d00000 0 0x2800000>; 291 no-map; 292 }; 293 294 wlan_fw_mem: memory@8b500000 { 295 reg = <0 0x8b500000 0 0x200000>; 296 no-map; 297 }; 298 299 pil_ipa_fw_mem: memory@8b700000 { 300 reg = <0 0x8b700000 0 0x10000>; 301 no-map; 302 }; 303 304 pil_ipa_gsi_mem: memory@8b710000 { 305 reg = <0 0x8b710000 0 0x5400>; 306 no-map; 307 }; 308 309 pil_gpu_mem: memory@8b715400 { 310 reg = <0 0x8b715400 0 0x2000>; 311 no-map; 312 }; 313 314 pil_modem_mem: memory@8b800000 { 315 reg = <0 0x8b800000 0 0xf800000>; 316 no-map; 317 }; 318 319 cont_splash_memory: memory@a0000000 { 320 reg = <0 0xa0000000 0 0x2300000>; 321 no-map; 322 }; 323 324 dfps_data_memory: memory@a2300000 { 325 reg = <0 0xa2300000 0 0x100000>; 326 no-map; 327 }; 328 329 removed_region: memory@c0000000 { 330 reg = <0 0xc0000000 0 0x3900000>; 331 no-map; 332 }; 333 334 debug_region: memory@ffb00000 { 335 reg = <0 0xffb00000 0 0xc0000>; 336 no-map; 337 }; 338 339 last_log_region: memory@ffbc0000 { 340 reg = <0 0xffbc0000 0 0x40000>; 341 no-map; 342 }; 343 344 ramoops: ramoops@ffc00000 { 345 compatible = "removed-dma-pool", "ramoops"; 346 reg = <0 0xffc00000 0 0x00100000>; 347 record-size = <0x1000>; 348 console-size = <0x40000>; 349 ftrace-size = <0x0>; 350 msg-size = <0x20000 0x20000>; 351 cc-size = <0x0>; 352 no-map; 353 }; 354 355 cmdline_region: memory@ffd00000 { 356 reg = <0 0xffd00000 0 0x1000>; 357 no-map; 358 }; 359 }; 360 361 smem { 362 compatible = "qcom,smem"; 363 memory-region = <&smem_mem>; 364 hwlocks = <&tcsr_mutex 3>; 365 }; 366 367 smp2p-adsp { 368 compatible = "qcom,smp2p"; 369 qcom,smem = <443>, <429>; 370 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 371 IPCC_MPROC_SIGNAL_SMP2P 372 IRQ_TYPE_EDGE_RISING>; 373 mboxes = <&ipcc IPCC_CLIENT_LPASS 374 IPCC_MPROC_SIGNAL_SMP2P>; 375 376 qcom,local-pid = <0>; 377 qcom,remote-pid = <2>; 378 379 smp2p_adsp_out: master-kernel { 380 qcom,entry-name = "master-kernel"; 381 #qcom,smem-state-cells = <1>; 382 }; 383 384 smp2p_adsp_in: slave-kernel { 385 qcom,entry-name = "slave-kernel"; 386 interrupt-controller; 387 #interrupt-cells = <2>; 388 }; 389 }; 390 391 smp2p-cdsp { 392 compatible = "qcom,smp2p"; 393 qcom,smem = <94>, <432>; 394 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 395 IPCC_MPROC_SIGNAL_SMP2P 396 IRQ_TYPE_EDGE_RISING>; 397 mboxes = <&ipcc IPCC_CLIENT_CDSP 398 IPCC_MPROC_SIGNAL_SMP2P>; 399 400 qcom,local-pid = <0>; 401 qcom,remote-pid = <5>; 402 403 smp2p_cdsp_out: master-kernel { 404 qcom,entry-name = "master-kernel"; 405 #qcom,smem-state-cells = <1>; 406 }; 407 408 smp2p_cdsp_in: slave-kernel { 409 qcom,entry-name = "slave-kernel"; 410 interrupt-controller; 411 #interrupt-cells = <2>; 412 }; 413 }; 414 415 smp2p-mpss { 416 compatible = "qcom,smp2p"; 417 qcom,smem = <435>, <428>; 418 419 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 420 IPCC_MPROC_SIGNAL_SMP2P 421 IRQ_TYPE_EDGE_RISING>; 422 mboxes = <&ipcc IPCC_CLIENT_MPSS 423 IPCC_MPROC_SIGNAL_SMP2P>; 424 425 qcom,local-pid = <0>; 426 qcom,remote-pid = <1>; 427 428 modem_smp2p_out: master-kernel { 429 qcom,entry-name = "master-kernel"; 430 #qcom,smem-state-cells = <1>; 431 }; 432 433 modem_smp2p_in: slave-kernel { 434 qcom,entry-name = "slave-kernel"; 435 436 interrupt-controller; 437 #interrupt-cells = <2>; 438 }; 439 }; 440 441 soc: soc@0 { 442 #address-cells = <2>; 443 #size-cells = <2>; 444 ranges = <0 0 0 0 0x10 0>; 445 dma-ranges = <0 0 0 0 0x10 0>; 446 compatible = "simple-bus"; 447 448 gcc: clock-controller@100000 { 449 compatible = "qcom,gcc-sm6350"; 450 reg = <0 0x00100000 0 0x1f0000>; 451 #clock-cells = <1>; 452 #reset-cells = <1>; 453 #power-domain-cells = <1>; 454 clock-names = "bi_tcxo", 455 "bi_tcxo_ao", 456 "sleep_clk"; 457 clocks = <&rpmhcc RPMH_CXO_CLK>, 458 <&rpmhcc RPMH_CXO_CLK_A>, 459 <&sleep_clk>; 460 }; 461 462 ipcc: mailbox@408000 { 463 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 464 reg = <0 0x00408000 0 0x1000>; 465 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 466 interrupt-controller; 467 #interrupt-cells = <3>; 468 #mbox-cells = <2>; 469 }; 470 471 rng: rng@793000 { 472 compatible = "qcom,prng-ee"; 473 reg = <0 0x00793000 0 0x1000>; 474 clocks = <&gcc GCC_PRNG_AHB_CLK>; 475 clock-names = "core"; 476 }; 477 478 sdhc_1: mmc@7c4000 { 479 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 480 reg = <0 0x007c4000 0 0x1000>, 481 <0 0x007c5000 0 0x1000>, 482 <0 0x007c8000 0 0x8000>; 483 reg-names = "hc", "cqhci", "ice"; 484 485 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 487 interrupt-names = "hc_irq", "pwr_irq"; 488 489 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 490 <&gcc GCC_SDCC1_APPS_CLK>, 491 <&rpmhcc RPMH_CXO_CLK>; 492 clock-names = "iface", "core", "xo"; 493 qcom,dll-config = <0x000f642c>; 494 qcom,ddr-config = <0x80040868>; 495 power-domains = <&rpmhpd SM6350_CX>; 496 operating-points-v2 = <&sdhc1_opp_table>; 497 bus-width = <8>; 498 non-removable; 499 supports-cqe; 500 501 status = "disabled"; 502 503 sdhc1_opp_table: opp-table { 504 compatible = "operating-points-v2"; 505 506 opp-19200000 { 507 opp-hz = /bits/ 64 <19200000>; 508 required-opps = <&rpmhpd_opp_min_svs>; 509 }; 510 511 opp-100000000 { 512 opp-hz = /bits/ 64 <100000000>; 513 required-opps = <&rpmhpd_opp_low_svs>; 514 }; 515 516 opp-384000000 { 517 opp-hz = /bits/ 64 <384000000>; 518 required-opps = <&rpmhpd_opp_svs_l1>; 519 }; 520 }; 521 }; 522 523 gpi_dma0: dma-controller@800000 { 524 compatible = "qcom,sm6350-gpi-dma"; 525 reg = <0 0x00800000 0 0x60000>; 526 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 536 dma-channels = <10>; 537 dma-channel-mask = <0x1f>; 538 iommus = <&apps_smmu 0x56 0x0>; 539 #dma-cells = <3>; 540 status = "disabled"; 541 }; 542 543 qupv3_id_0: geniqup@8c0000 { 544 compatible = "qcom,geni-se-qup"; 545 reg = <0x0 0x8c0000 0x0 0x2000>; 546 clock-names = "m-ahb", "s-ahb"; 547 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 548 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 549 #address-cells = <2>; 550 #size-cells = <2>; 551 iommus = <&apps_smmu 0x43 0x0>; 552 ranges; 553 status = "disabled"; 554 555 i2c0: i2c@880000 { 556 compatible = "qcom,geni-i2c"; 557 reg = <0 0x00880000 0 0x4000>; 558 clock-names = "se"; 559 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 560 pinctrl-names = "default"; 561 pinctrl-0 = <&qup_i2c0_default>; 562 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 563 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 564 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 565 dma-names = "tx", "rx"; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 569 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 570 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 571 interconnect-names = "qup-core", "qup-config", "qup-memory"; 572 status = "disabled"; 573 }; 574 575 i2c2: i2c@888000 { 576 compatible = "qcom,geni-i2c"; 577 reg = <0 0x00888000 0 0x4000>; 578 clock-names = "se"; 579 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 580 pinctrl-names = "default"; 581 pinctrl-0 = <&qup_i2c2_default>; 582 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 583 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 584 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 585 dma-names = "tx", "rx"; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 589 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 590 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 591 interconnect-names = "qup-core", "qup-config", "qup-memory"; 592 status = "disabled"; 593 }; 594 }; 595 596 gpi_dma1: dma-controller@900000 { 597 compatible = "qcom,sm6350-gpi-dma"; 598 reg = <0 0x00900000 0 0x60000>; 599 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 609 dma-channels = <10>; 610 dma-channel-mask = <0x3f>; 611 iommus = <&apps_smmu 0x4d6 0x0>; 612 #dma-cells = <3>; 613 status = "disabled"; 614 }; 615 616 qupv3_id_1: geniqup@9c0000 { 617 compatible = "qcom,geni-se-qup"; 618 reg = <0x0 0x9c0000 0x0 0x2000>; 619 clock-names = "m-ahb", "s-ahb"; 620 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 621 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 622 #address-cells = <2>; 623 #size-cells = <2>; 624 iommus = <&apps_smmu 0x4c3 0x0>; 625 ranges; 626 status = "disabled"; 627 628 i2c6: i2c@980000 { 629 compatible = "qcom,geni-i2c"; 630 reg = <0 0x00980000 0 0x4000>; 631 clock-names = "se"; 632 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 633 pinctrl-names = "default"; 634 pinctrl-0 = <&qup_i2c6_default>; 635 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 636 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 637 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 638 dma-names = "tx", "rx"; 639 #address-cells = <1>; 640 #size-cells = <0>; 641 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 642 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 643 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 644 interconnect-names = "qup-core", "qup-config", "qup-memory"; 645 status = "disabled"; 646 }; 647 648 i2c7: i2c@984000 { 649 compatible = "qcom,geni-i2c"; 650 reg = <0 0x00984000 0 0x4000>; 651 clock-names = "se"; 652 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 653 pinctrl-names = "default"; 654 pinctrl-0 = <&qup_i2c7_default>; 655 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 656 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 657 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 658 dma-names = "tx", "rx"; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 662 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 663 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 664 interconnect-names = "qup-core", "qup-config", "qup-memory"; 665 status = "disabled"; 666 }; 667 668 i2c8: i2c@988000 { 669 compatible = "qcom,geni-i2c"; 670 reg = <0 0x00988000 0 0x4000>; 671 clock-names = "se"; 672 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 673 pinctrl-names = "default"; 674 pinctrl-0 = <&qup_i2c8_default>; 675 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 676 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 677 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 678 dma-names = "tx", "rx"; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 682 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 683 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 684 interconnect-names = "qup-core", "qup-config", "qup-memory"; 685 status = "disabled"; 686 }; 687 688 uart9: serial@98c000 { 689 compatible = "qcom,geni-debug-uart"; 690 reg = <0 0x98c000 0 0x4000>; 691 clock-names = "se"; 692 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 693 pinctrl-names = "default"; 694 pinctrl-0 = <&qup_uart9_default>; 695 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 696 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 697 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 698 interconnect-names = "qup-core", "qup-config"; 699 status = "disabled"; 700 }; 701 702 i2c10: i2c@990000 { 703 compatible = "qcom,geni-i2c"; 704 reg = <0 0x00990000 0 0x4000>; 705 clock-names = "se"; 706 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 707 pinctrl-names = "default"; 708 pinctrl-0 = <&qup_i2c10_default>; 709 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 710 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 711 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 712 dma-names = "tx", "rx"; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 716 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 717 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 718 interconnect-names = "qup-core", "qup-config", "qup-memory"; 719 status = "disabled"; 720 }; 721 722 }; 723 724 config_noc: interconnect@1500000 { 725 compatible = "qcom,sm6350-config-noc"; 726 reg = <0 0x01500000 0 0x28000>; 727 #interconnect-cells = <2>; 728 qcom,bcm-voters = <&apps_bcm_voter>; 729 }; 730 731 system_noc: interconnect@1620000 { 732 compatible = "qcom,sm6350-system-noc"; 733 reg = <0 0x01620000 0 0x17080>; 734 #interconnect-cells = <2>; 735 qcom,bcm-voters = <&apps_bcm_voter>; 736 737 clk_virt: interconnect-clk-virt { 738 compatible = "qcom,sm6350-clk-virt"; 739 #interconnect-cells = <2>; 740 qcom,bcm-voters = <&apps_bcm_voter>; 741 }; 742 }; 743 744 aggre1_noc: interconnect@16e0000 { 745 compatible = "qcom,sm6350-aggre1-noc"; 746 reg = <0 0x016e0000 0 0x15080>; 747 #interconnect-cells = <2>; 748 qcom,bcm-voters = <&apps_bcm_voter>; 749 }; 750 751 aggre2_noc: interconnect@1700000 { 752 compatible = "qcom,sm6350-aggre2-noc"; 753 reg = <0 0x01700000 0 0x1f880>; 754 #interconnect-cells = <2>; 755 qcom,bcm-voters = <&apps_bcm_voter>; 756 757 compute_noc: interconnect-compute-noc { 758 compatible = "qcom,sm6350-compute-noc"; 759 #interconnect-cells = <2>; 760 qcom,bcm-voters = <&apps_bcm_voter>; 761 }; 762 }; 763 764 mmss_noc: interconnect@1740000 { 765 compatible = "qcom,sm6350-mmss-noc"; 766 reg = <0 0x01740000 0 0x1c100>; 767 #interconnect-cells = <2>; 768 qcom,bcm-voters = <&apps_bcm_voter>; 769 }; 770 771 ufs_mem_hc: ufs@1d84000 { 772 compatible = "qcom,sm6350-ufshc", "qcom,ufshc", 773 "jedec,ufs-2.0"; 774 reg = <0 0x01d84000 0 0x3000>, 775 <0 0x01d90000 0 0x8000>; 776 reg-names = "std", "ice"; 777 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 778 phys = <&ufs_mem_phy_lanes>; 779 phy-names = "ufsphy"; 780 lanes-per-direction = <2>; 781 #reset-cells = <1>; 782 resets = <&gcc GCC_UFS_PHY_BCR>; 783 reset-names = "rst"; 784 785 power-domains = <&gcc UFS_PHY_GDSC>; 786 787 iommus = <&apps_smmu 0x80 0x0>; 788 789 clock-names = "core_clk", 790 "bus_aggr_clk", 791 "iface_clk", 792 "core_clk_unipro", 793 "ref_clk", 794 "tx_lane0_sync_clk", 795 "rx_lane0_sync_clk", 796 "rx_lane1_sync_clk", 797 "ice_core_clk"; 798 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 799 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 800 <&gcc GCC_UFS_PHY_AHB_CLK>, 801 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 802 <&rpmhcc RPMH_QLINK_CLK>, 803 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 804 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 805 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 806 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 807 freq-table-hz = 808 <50000000 200000000>, 809 <0 0>, 810 <0 0>, 811 <37500000 150000000>, 812 <75000000 300000000>, 813 <0 0>, 814 <0 0>, 815 <0 0>, 816 <0 0>; 817 818 status = "disabled"; 819 }; 820 821 ufs_mem_phy: phy@1d87000 { 822 compatible = "qcom,sm6350-qmp-ufs-phy"; 823 reg = <0 0x01d87000 0 0x18c>; 824 #address-cells = <2>; 825 #size-cells = <2>; 826 ranges; 827 828 clock-names = "ref", 829 "ref_aux"; 830 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 831 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 832 833 resets = <&ufs_mem_hc 0>; 834 reset-names = "ufsphy"; 835 836 status = "disabled"; 837 838 ufs_mem_phy_lanes: phy@1d87400 { 839 reg = <0 0x01d87400 0 0x128>, 840 <0 0x01d87600 0 0x1fc>, 841 <0 0x01d87c00 0 0x1dc>, 842 <0 0x01d87800 0 0x128>, 843 <0 0x01d87a00 0 0x1fc>; 844 #phy-cells = <0>; 845 }; 846 }; 847 848 tcsr_mutex: hwlock@1f40000 { 849 compatible = "qcom,tcsr-mutex"; 850 reg = <0x0 0x01f40000 0x0 0x40000>; 851 #hwlock-cells = <1>; 852 }; 853 854 adsp: remoteproc@3000000 { 855 compatible = "qcom,sm6350-adsp-pas"; 856 reg = <0 0x03000000 0 0x100>; 857 858 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 859 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 860 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 861 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 862 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 863 interrupt-names = "wdog", "fatal", "ready", 864 "handover", "stop-ack"; 865 866 clocks = <&rpmhcc RPMH_CXO_CLK>; 867 clock-names = "xo"; 868 869 power-domains = <&rpmhpd SM6350_LCX>, 870 <&rpmhpd SM6350_LMX>; 871 power-domain-names = "lcx", "lmx"; 872 873 memory-region = <&pil_adsp_mem>; 874 875 qcom,qmp = <&aoss_qmp>; 876 877 qcom,smem-states = <&smp2p_adsp_out 0>; 878 qcom,smem-state-names = "stop"; 879 880 status = "disabled"; 881 882 glink-edge { 883 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 884 IPCC_MPROC_SIGNAL_GLINK_QMP 885 IRQ_TYPE_EDGE_RISING>; 886 mboxes = <&ipcc IPCC_CLIENT_LPASS 887 IPCC_MPROC_SIGNAL_GLINK_QMP>; 888 889 label = "lpass"; 890 qcom,remote-pid = <2>; 891 892 fastrpc { 893 compatible = "qcom,fastrpc"; 894 qcom,glink-channels = "fastrpcglink-apps-dsp"; 895 label = "adsp"; 896 #address-cells = <1>; 897 #size-cells = <0>; 898 899 compute-cb@3 { 900 compatible = "qcom,fastrpc-compute-cb"; 901 reg = <3>; 902 iommus = <&apps_smmu 0x1003 0x0>; 903 }; 904 905 compute-cb@4 { 906 compatible = "qcom,fastrpc-compute-cb"; 907 reg = <4>; 908 iommus = <&apps_smmu 0x1004 0x0>; 909 }; 910 911 compute-cb@5 { 912 compatible = "qcom,fastrpc-compute-cb"; 913 reg = <5>; 914 iommus = <&apps_smmu 0x1005 0x0>; 915 qcom,nsessions = <5>; 916 }; 917 }; 918 }; 919 }; 920 921 mpss: remoteproc@4080000 { 922 compatible = "qcom,sm6350-mpss-pas"; 923 reg = <0x0 0x04080000 0x0 0x4040>; 924 925 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 926 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 927 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 928 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 929 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 930 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 931 interrupt-names = "wdog", "fatal", "ready", "handover", 932 "stop-ack", "shutdown-ack"; 933 934 clocks = <&rpmhcc RPMH_CXO_CLK>; 935 clock-names = "xo"; 936 937 power-domains = <&rpmhpd SM6350_CX>, 938 <&rpmhpd SM6350_MSS>; 939 power-domain-names = "cx", "mss"; 940 941 memory-region = <&pil_modem_mem>; 942 943 qcom,qmp = <&aoss_qmp>; 944 945 qcom,smem-states = <&modem_smp2p_out 0>; 946 qcom,smem-state-names = "stop"; 947 948 status = "disabled"; 949 950 glink-edge { 951 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 952 IPCC_MPROC_SIGNAL_GLINK_QMP 953 IRQ_TYPE_EDGE_RISING>; 954 mboxes = <&ipcc IPCC_CLIENT_MPSS 955 IPCC_MPROC_SIGNAL_GLINK_QMP>; 956 label = "modem"; 957 qcom,remote-pid = <1>; 958 }; 959 }; 960 961 cdsp: remoteproc@8300000 { 962 compatible = "qcom,sm6350-cdsp-pas"; 963 reg = <0 0x08300000 0 0x10000>; 964 965 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 966 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 967 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 968 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 969 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 970 interrupt-names = "wdog", "fatal", "ready", 971 "handover", "stop-ack"; 972 973 clocks = <&rpmhcc RPMH_CXO_CLK>; 974 clock-names = "xo"; 975 976 power-domains = <&rpmhpd SM6350_CX>, 977 <&rpmhpd SM6350_MX>; 978 power-domain-names = "cx", "mx"; 979 980 memory-region = <&pil_cdsp_mem>; 981 982 qcom,qmp = <&aoss_qmp>; 983 984 qcom,smem-states = <&smp2p_cdsp_out 0>; 985 qcom,smem-state-names = "stop"; 986 987 status = "disabled"; 988 989 glink-edge { 990 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 991 IPCC_MPROC_SIGNAL_GLINK_QMP 992 IRQ_TYPE_EDGE_RISING>; 993 mboxes = <&ipcc IPCC_CLIENT_CDSP 994 IPCC_MPROC_SIGNAL_GLINK_QMP>; 995 996 label = "cdsp"; 997 qcom,remote-pid = <5>; 998 999 fastrpc { 1000 compatible = "qcom,fastrpc"; 1001 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1002 label = "cdsp"; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 1006 compute-cb@1 { 1007 compatible = "qcom,fastrpc-compute-cb"; 1008 reg = <1>; 1009 iommus = <&apps_smmu 0x1401 0x20>; 1010 }; 1011 1012 compute-cb@2 { 1013 compatible = "qcom,fastrpc-compute-cb"; 1014 reg = <2>; 1015 iommus = <&apps_smmu 0x1402 0x20>; 1016 }; 1017 1018 compute-cb@3 { 1019 compatible = "qcom,fastrpc-compute-cb"; 1020 reg = <3>; 1021 iommus = <&apps_smmu 0x1403 0x20>; 1022 }; 1023 1024 compute-cb@4 { 1025 compatible = "qcom,fastrpc-compute-cb"; 1026 reg = <4>; 1027 iommus = <&apps_smmu 0x1404 0x20>; 1028 }; 1029 1030 compute-cb@5 { 1031 compatible = "qcom,fastrpc-compute-cb"; 1032 reg = <5>; 1033 iommus = <&apps_smmu 0x1405 0x20>; 1034 }; 1035 1036 compute-cb@6 { 1037 compatible = "qcom,fastrpc-compute-cb"; 1038 reg = <6>; 1039 iommus = <&apps_smmu 0x1406 0x20>; 1040 }; 1041 1042 compute-cb@7 { 1043 compatible = "qcom,fastrpc-compute-cb"; 1044 reg = <7>; 1045 iommus = <&apps_smmu 0x1407 0x20>; 1046 }; 1047 1048 compute-cb@8 { 1049 compatible = "qcom,fastrpc-compute-cb"; 1050 reg = <8>; 1051 iommus = <&apps_smmu 0x1408 0x20>; 1052 }; 1053 1054 /* note: secure cb9 in downstream */ 1055 }; 1056 }; 1057 }; 1058 1059 sdhc_2: mmc@8804000 { 1060 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 1061 reg = <0 0x08804000 0 0x1000>; 1062 1063 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1065 interrupt-names = "hc_irq", "pwr_irq"; 1066 1067 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1068 <&gcc GCC_SDCC2_APPS_CLK>, 1069 <&rpmhcc RPMH_CXO_CLK>; 1070 clock-names = "iface", "core", "xo"; 1071 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, 1072 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; 1073 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1074 1075 qcom,dll-config = <0x0007642c>; 1076 qcom,ddr-config = <0x80040868>; 1077 power-domains = <&rpmhpd SM6350_CX>; 1078 operating-points-v2 = <&sdhc2_opp_table>; 1079 bus-width = <4>; 1080 1081 status = "disabled"; 1082 1083 sdhc2_opp_table: opp-table { 1084 compatible = "operating-points-v2"; 1085 1086 opp-100000000 { 1087 opp-hz = /bits/ 64 <100000000>; 1088 required-opps = <&rpmhpd_opp_svs_l1>; 1089 opp-peak-kBps = <790000 131000>; 1090 opp-avg-kBps = <50000 50000>; 1091 }; 1092 1093 opp-202000000 { 1094 opp-hz = /bits/ 64 <202000000>; 1095 required-opps = <&rpmhpd_opp_nom>; 1096 opp-peak-kBps = <3190000 294000>; 1097 opp-avg-kBps = <261438 300000>; 1098 }; 1099 }; 1100 }; 1101 1102 usb_1_hsphy: phy@88e3000 { 1103 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 1104 reg = <0 0x088e3000 0 0x400>; 1105 status = "disabled"; 1106 #phy-cells = <0>; 1107 1108 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 1109 clock-names = "cfg_ahb", "ref"; 1110 1111 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1112 }; 1113 1114 usb_1_qmpphy: phy@88e9000 { 1115 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 1116 reg = <0 0x088e9000 0 0x200>, 1117 <0 0x088e8000 0 0x40>, 1118 <0 0x088ea000 0 0x200>; 1119 status = "disabled"; 1120 #address-cells = <2>; 1121 #size-cells = <2>; 1122 ranges; 1123 1124 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1125 <&xo_board>, 1126 <&rpmhcc RPMH_QLINK_CLK>, 1127 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1128 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 1129 1130 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1131 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1132 reset-names = "phy", "common"; 1133 1134 usb_1_ssphy: usb3-phy@88e9200 { 1135 reg = <0 0x088e9200 0 0x200>, 1136 <0 0x088e9400 0 0x200>, 1137 <0 0x088e9c00 0 0x400>, 1138 <0 0x088e9600 0 0x200>, 1139 <0 0x088e9800 0 0x200>, 1140 <0 0x088e9a00 0 0x100>; 1141 #clock-cells = <0>; 1142 #phy-cells = <0>; 1143 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1144 clock-names = "pipe0"; 1145 clock-output-names = "usb3_phy_pipe_clk_src"; 1146 }; 1147 1148 dp_phy: dp-phy@88ea200 { 1149 reg = <0 0x088ea200 0 0x200>, 1150 <0 0x088ea400 0 0x200>, 1151 <0 0x088eac00 0 0x400>, 1152 <0 0x088ea600 0 0x200>, 1153 <0 0x088ea800 0 0x200>, 1154 <0 0x088eaa00 0 0x100>; 1155 #phy-cells = <0>; 1156 #clock-cells = <1>; 1157 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1158 clock-names = "pipe0"; 1159 clock-output-names = "usb3_phy_pipe_clk_src"; 1160 }; 1161 }; 1162 1163 dc_noc: interconnect@9160000 { 1164 compatible = "qcom,sm6350-dc-noc"; 1165 reg = <0 0x09160000 0 0x3200>; 1166 #interconnect-cells = <2>; 1167 qcom,bcm-voters = <&apps_bcm_voter>; 1168 }; 1169 1170 system-cache-controller@9200000 { 1171 compatible = "qcom,sm6350-llcc"; 1172 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 1173 reg-names = "llcc_base", "llcc_broadcast_base"; 1174 }; 1175 1176 gem_noc: interconnect@9680000 { 1177 compatible = "qcom,sm6350-gem-noc"; 1178 reg = <0 0x09680000 0 0x3e200>; 1179 #interconnect-cells = <2>; 1180 qcom,bcm-voters = <&apps_bcm_voter>; 1181 }; 1182 1183 npu_noc: interconnect@9990000 { 1184 compatible = "qcom,sm6350-npu-noc"; 1185 reg = <0 0x09990000 0 0x1600>; 1186 #interconnect-cells = <2>; 1187 qcom,bcm-voters = <&apps_bcm_voter>; 1188 }; 1189 1190 usb_1: usb@a6f8800 { 1191 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 1192 reg = <0 0x0a6f8800 0 0x400>; 1193 status = "disabled"; 1194 #address-cells = <2>; 1195 #size-cells = <2>; 1196 ranges; 1197 1198 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1199 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1200 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1201 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1202 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1203 clock-names = "cfg_noc", 1204 "core", 1205 "iface", 1206 "sleep", 1207 "mock_utmi"; 1208 1209 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1210 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 1211 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1212 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 1213 1214 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1215 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1216 1217 power-domains = <&gcc USB30_PRIM_GDSC>; 1218 1219 resets = <&gcc GCC_USB30_PRIM_BCR>; 1220 1221 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, 1222 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1223 interconnect-names = "usb-ddr", "apps-usb"; 1224 1225 usb_1_dwc3: usb@a600000 { 1226 compatible = "snps,dwc3"; 1227 reg = <0 0x0a600000 0 0xcd00>; 1228 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1229 iommus = <&apps_smmu 0x540 0x0>; 1230 snps,dis_u2_susphy_quirk; 1231 snps,dis_enblslpm_quirk; 1232 snps,has-lpm-erratum; 1233 snps,hird-threshold = /bits/ 8 <0x10>; 1234 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1235 phy-names = "usb2-phy", "usb3-phy"; 1236 }; 1237 }; 1238 1239 pdc: interrupt-controller@b220000 { 1240 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 1241 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; 1242 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 1243 <125 63 1>, <126 655 12>, <138 139 15>; 1244 #interrupt-cells = <2>; 1245 interrupt-parent = <&intc>; 1246 interrupt-controller; 1247 }; 1248 1249 tsens0: thermal-sensor@c263000 { 1250 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1251 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1252 <0 0x0c222000 0 0x8>; /* SROT */ 1253 #qcom,sensors = <16>; 1254 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 1255 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 1256 interrupt-names = "uplow", "critical"; 1257 #thermal-sensor-cells = <1>; 1258 }; 1259 1260 tsens1: thermal-sensor@c265000 { 1261 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1262 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1263 <0 0x0c223000 0 0x8>; /* SROT */ 1264 #qcom,sensors = <16>; 1265 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 1266 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 1267 interrupt-names = "uplow", "critical"; 1268 #thermal-sensor-cells = <1>; 1269 }; 1270 1271 aoss_qmp: power-controller@c300000 { 1272 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 1273 reg = <0 0x0c300000 0 0x1000>; 1274 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 1275 IRQ_TYPE_EDGE_RISING>; 1276 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 1277 1278 #clock-cells = <0>; 1279 }; 1280 1281 spmi_bus: spmi@c440000 { 1282 compatible = "qcom,spmi-pmic-arb"; 1283 reg = <0 0xc440000 0 0x1100>, 1284 <0 0xc600000 0 0x2000000>, 1285 <0 0xe600000 0 0x100000>, 1286 <0 0xe700000 0 0xa0000>, 1287 <0 0xc40a000 0 0x26000>; 1288 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1289 interrupt-names = "periph_irq"; 1290 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1291 qcom,ee = <0>; 1292 qcom,channel = <0>; 1293 #address-cells = <2>; 1294 #size-cells = <0>; 1295 interrupt-controller; 1296 #interrupt-cells = <4>; 1297 }; 1298 1299 tlmm: pinctrl@f100000 { 1300 compatible = "qcom,sm6350-tlmm"; 1301 reg = <0 0x0f100000 0 0x300000>; 1302 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1306 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1307 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 1311 gpio-controller; 1312 #gpio-cells = <2>; 1313 interrupt-controller; 1314 #interrupt-cells = <2>; 1315 gpio-ranges = <&tlmm 0 0 157>; 1316 1317 qup_uart9_default: qup-uart9-default-state { 1318 pins = "gpio25", "gpio26"; 1319 function = "qup13_f2"; 1320 drive-strength = <2>; 1321 bias-disable; 1322 }; 1323 1324 qup_i2c0_default: qup-i2c0-default-state { 1325 pins = "gpio0", "gpio1"; 1326 function = "qup00"; 1327 drive-strength = <2>; 1328 bias-pull-up; 1329 }; 1330 1331 qup_i2c2_default: qup-i2c2-default-state { 1332 pins = "gpio45", "gpio46"; 1333 function = "qup02"; 1334 drive-strength = <2>; 1335 bias-pull-up; 1336 }; 1337 1338 qup_i2c6_default: qup-i2c6-default-state { 1339 pins = "gpio13", "gpio14"; 1340 function = "qup10"; 1341 drive-strength = <2>; 1342 bias-pull-up; 1343 }; 1344 1345 qup_i2c7_default: qup-i2c7-default-state { 1346 pins = "gpio27", "gpio28"; 1347 function = "qup11"; 1348 drive-strength = <2>; 1349 bias-pull-up; 1350 }; 1351 1352 qup_i2c8_default: qup-i2c8-default-state { 1353 pins = "gpio19", "gpio20"; 1354 function = "qup12"; 1355 drive-strength = <2>; 1356 bias-pull-up; 1357 }; 1358 1359 qup_i2c10_default: qup-i2c10-default-state { 1360 pins = "gpio4", "gpio5"; 1361 function = "qup14"; 1362 drive-strength = <2>; 1363 bias-pull-up; 1364 }; 1365 }; 1366 1367 apps_smmu: iommu@15000000 { 1368 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 1369 reg = <0 0x15000000 0 0x100000>; 1370 #iommu-cells = <2>; 1371 #global-interrupts = <1>; 1372 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1386 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1388 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1389 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1390 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1391 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1413 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1414 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1415 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1416 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1417 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1453 }; 1454 1455 intc: interrupt-controller@17a00000 { 1456 compatible = "arm,gic-v3"; 1457 #interrupt-cells = <3>; 1458 interrupt-controller; 1459 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 1460 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 1461 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 1462 }; 1463 1464 watchdog@17c10000 { 1465 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 1466 reg = <0 0x17c10000 0 0x1000>; 1467 clocks = <&sleep_clk>; 1468 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1469 }; 1470 1471 timer@17c20000 { 1472 compatible = "arm,armv7-timer-mem"; 1473 reg = <0x0 0x17c20000 0x0 0x1000>; 1474 clock-frequency = <19200000>; 1475 #address-cells = <1>; 1476 #size-cells = <1>; 1477 ranges = <0 0 0 0x20000000>; 1478 1479 frame@17c21000 { 1480 frame-number = <0>; 1481 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1483 reg = <0x17c21000 0x1000>, 1484 <0x17c22000 0x1000>; 1485 }; 1486 1487 frame@17c23000 { 1488 frame-number = <1>; 1489 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1490 reg = <0x17c23000 0x1000>; 1491 status = "disabled"; 1492 }; 1493 1494 frame@17c25000 { 1495 frame-number = <2>; 1496 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1497 reg = <0x17c25000 0x1000>; 1498 status = "disabled"; 1499 }; 1500 1501 frame@17c27000 { 1502 frame-number = <3>; 1503 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1504 reg = <0x17c27000 0x1000>; 1505 status = "disabled"; 1506 }; 1507 1508 frame@17c29000 { 1509 frame-number = <4>; 1510 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1511 reg = <0x17c29000 0x1000>; 1512 status = "disabled"; 1513 }; 1514 1515 frame@17c2b000 { 1516 frame-number = <5>; 1517 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1518 reg = <0x17c2b000 0x1000>; 1519 status = "disabled"; 1520 }; 1521 1522 frame@17c2d000 { 1523 frame-number = <6>; 1524 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1525 reg = <0x17c2d000 0x1000>; 1526 status = "disabled"; 1527 }; 1528 }; 1529 1530 wifi: wifi@18800000 { 1531 compatible = "qcom,wcn3990-wifi"; 1532 reg = <0 0x18800000 0 0x800000>; 1533 reg-names = "membase"; 1534 memory-region = <&wlan_fw_mem>; 1535 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 1547 iommus = <&apps_smmu 0x20 0x1>; 1548 qcom,msa-fixed-perm; 1549 status = "disabled"; 1550 }; 1551 1552 apps_rsc: rsc@18200000 { 1553 compatible = "qcom,rpmh-rsc"; 1554 label = "apps_rsc"; 1555 reg = <0x0 0x18200000 0x0 0x10000>, 1556 <0x0 0x18210000 0x0 0x10000>, 1557 <0x0 0x18220000 0x0 0x10000>; 1558 reg-names = "drv-0", "drv-1", "drv-2"; 1559 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1562 qcom,tcs-offset = <0xd00>; 1563 qcom,drv-id = <2>; 1564 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 1565 <WAKE_TCS 3>, <CONTROL_TCS 1>; 1566 1567 rpmhcc: clock-controller { 1568 compatible = "qcom,sm6350-rpmh-clk"; 1569 #clock-cells = <1>; 1570 clock-names = "xo"; 1571 clocks = <&xo_board>; 1572 }; 1573 1574 rpmhpd: power-controller { 1575 compatible = "qcom,sm6350-rpmhpd"; 1576 #power-domain-cells = <1>; 1577 operating-points-v2 = <&rpmhpd_opp_table>; 1578 1579 rpmhpd_opp_table: opp-table { 1580 compatible = "operating-points-v2"; 1581 1582 rpmhpd_opp_ret: opp1 { 1583 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1584 }; 1585 1586 rpmhpd_opp_min_svs: opp2 { 1587 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1588 }; 1589 1590 rpmhpd_opp_low_svs: opp3 { 1591 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1592 }; 1593 1594 rpmhpd_opp_svs: opp4 { 1595 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1596 }; 1597 1598 rpmhpd_opp_svs_l1: opp5 { 1599 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1600 }; 1601 1602 rpmhpd_opp_nom: opp6 { 1603 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1604 }; 1605 1606 rpmhpd_opp_nom_l1: opp7 { 1607 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1608 }; 1609 1610 rpmhpd_opp_nom_l2: opp8 { 1611 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1612 }; 1613 1614 rpmhpd_opp_turbo: opp9 { 1615 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1616 }; 1617 1618 rpmhpd_opp_turbo_l1: opp10 { 1619 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1620 }; 1621 }; 1622 }; 1623 1624 apps_bcm_voter: bcm-voter { 1625 compatible = "qcom,bcm-voter"; 1626 }; 1627 }; 1628 1629 cpufreq_hw: cpufreq@18323000 { 1630 compatible = "qcom,cpufreq-hw"; 1631 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; 1632 reg-names = "freq-domain0", "freq-domain1"; 1633 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 1634 clock-names = "xo", "alternate"; 1635 1636 #freq-domain-cells = <1>; 1637 }; 1638 }; 1639 1640 timer { 1641 compatible = "arm,armv8-timer"; 1642 clock-frequency = <19200000>; 1643 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1644 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1645 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1646 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1647 }; 1648}; 1649