1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sm6350.h> 8#include <dt-bindings/clock/qcom,gcc-sm6350.h> 9#include <dt-bindings/clock/qcom,gpucc-sm6350.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sm6350-camcc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sm6350.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/phy/phy-qcom-qmp.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 clocks { 29 xo_board: xo-board { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <76800000>; 33 clock-output-names = "xo_board"; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 clock-frequency = <32764>; 39 #clock-cells = <0>; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 CPU0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "qcom,kryo560"; 50 reg = <0x0 0x0>; 51 clocks = <&cpufreq_hw 0>; 52 enable-method = "psci"; 53 capacity-dmips-mhz = <1024>; 54 dynamic-power-coefficient = <100>; 55 next-level-cache = <&L2_0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 operating-points-v2 = <&cpu0_opp_table>; 58 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 59 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 60 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 61 power-domains = <&CPU_PD0>; 62 power-domain-names = "psci"; 63 #cooling-cells = <2>; 64 L2_0: l2-cache { 65 compatible = "cache"; 66 cache-level = <2>; 67 cache-unified; 68 next-level-cache = <&L3_0>; 69 L3_0: l3-cache { 70 compatible = "cache"; 71 cache-level = <3>; 72 cache-unified; 73 }; 74 }; 75 }; 76 77 CPU1: cpu@100 { 78 device_type = "cpu"; 79 compatible = "qcom,kryo560"; 80 reg = <0x0 0x100>; 81 clocks = <&cpufreq_hw 0>; 82 enable-method = "psci"; 83 capacity-dmips-mhz = <1024>; 84 dynamic-power-coefficient = <100>; 85 next-level-cache = <&L2_100>; 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 89 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 90 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 91 power-domains = <&CPU_PD1>; 92 power-domain-names = "psci"; 93 #cooling-cells = <2>; 94 L2_100: l2-cache { 95 compatible = "cache"; 96 cache-level = <2>; 97 cache-unified; 98 next-level-cache = <&L3_0>; 99 }; 100 }; 101 102 CPU2: cpu@200 { 103 device_type = "cpu"; 104 compatible = "qcom,kryo560"; 105 reg = <0x0 0x200>; 106 clocks = <&cpufreq_hw 0>; 107 enable-method = "psci"; 108 capacity-dmips-mhz = <1024>; 109 dynamic-power-coefficient = <100>; 110 next-level-cache = <&L2_200>; 111 qcom,freq-domain = <&cpufreq_hw 0>; 112 operating-points-v2 = <&cpu0_opp_table>; 113 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 114 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 115 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 116 power-domains = <&CPU_PD2>; 117 power-domain-names = "psci"; 118 #cooling-cells = <2>; 119 L2_200: l2-cache { 120 compatible = "cache"; 121 cache-level = <2>; 122 cache-unified; 123 next-level-cache = <&L3_0>; 124 }; 125 }; 126 127 CPU3: cpu@300 { 128 device_type = "cpu"; 129 compatible = "qcom,kryo560"; 130 reg = <0x0 0x300>; 131 clocks = <&cpufreq_hw 0>; 132 enable-method = "psci"; 133 capacity-dmips-mhz = <1024>; 134 dynamic-power-coefficient = <100>; 135 next-level-cache = <&L2_300>; 136 qcom,freq-domain = <&cpufreq_hw 0>; 137 operating-points-v2 = <&cpu0_opp_table>; 138 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 139 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 140 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 141 power-domains = <&CPU_PD3>; 142 power-domain-names = "psci"; 143 #cooling-cells = <2>; 144 L2_300: l2-cache { 145 compatible = "cache"; 146 cache-level = <2>; 147 cache-unified; 148 next-level-cache = <&L3_0>; 149 }; 150 }; 151 152 CPU4: cpu@400 { 153 device_type = "cpu"; 154 compatible = "qcom,kryo560"; 155 reg = <0x0 0x400>; 156 clocks = <&cpufreq_hw 0>; 157 enable-method = "psci"; 158 capacity-dmips-mhz = <1024>; 159 dynamic-power-coefficient = <100>; 160 next-level-cache = <&L2_400>; 161 qcom,freq-domain = <&cpufreq_hw 0>; 162 operating-points-v2 = <&cpu0_opp_table>; 163 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 164 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 165 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 166 power-domains = <&CPU_PD4>; 167 power-domain-names = "psci"; 168 #cooling-cells = <2>; 169 L2_400: l2-cache { 170 compatible = "cache"; 171 cache-level = <2>; 172 cache-unified; 173 next-level-cache = <&L3_0>; 174 }; 175 }; 176 177 CPU5: cpu@500 { 178 device_type = "cpu"; 179 compatible = "qcom,kryo560"; 180 reg = <0x0 0x500>; 181 clocks = <&cpufreq_hw 0>; 182 enable-method = "psci"; 183 capacity-dmips-mhz = <1024>; 184 dynamic-power-coefficient = <100>; 185 next-level-cache = <&L2_500>; 186 qcom,freq-domain = <&cpufreq_hw 0>; 187 operating-points-v2 = <&cpu0_opp_table>; 188 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 189 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 190 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 191 power-domains = <&CPU_PD5>; 192 power-domain-names = "psci"; 193 #cooling-cells = <2>; 194 L2_500: l2-cache { 195 compatible = "cache"; 196 cache-level = <2>; 197 cache-unified; 198 next-level-cache = <&L3_0>; 199 }; 200 }; 201 202 CPU6: cpu@600 { 203 device_type = "cpu"; 204 compatible = "qcom,kryo560"; 205 reg = <0x0 0x600>; 206 clocks = <&cpufreq_hw 1>; 207 enable-method = "psci"; 208 capacity-dmips-mhz = <1894>; 209 dynamic-power-coefficient = <703>; 210 next-level-cache = <&L2_600>; 211 qcom,freq-domain = <&cpufreq_hw 1>; 212 operating-points-v2 = <&cpu6_opp_table>; 213 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 214 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 215 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 216 power-domains = <&CPU_PD6>; 217 power-domain-names = "psci"; 218 #cooling-cells = <2>; 219 L2_600: l2-cache { 220 compatible = "cache"; 221 cache-level = <2>; 222 cache-unified; 223 next-level-cache = <&L3_0>; 224 }; 225 }; 226 227 CPU7: cpu@700 { 228 device_type = "cpu"; 229 compatible = "qcom,kryo560"; 230 reg = <0x0 0x700>; 231 clocks = <&cpufreq_hw 1>; 232 enable-method = "psci"; 233 capacity-dmips-mhz = <1894>; 234 dynamic-power-coefficient = <703>; 235 next-level-cache = <&L2_700>; 236 qcom,freq-domain = <&cpufreq_hw 1>; 237 operating-points-v2 = <&cpu6_opp_table>; 238 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 239 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 240 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 241 power-domains = <&CPU_PD7>; 242 power-domain-names = "psci"; 243 #cooling-cells = <2>; 244 L2_700: l2-cache { 245 compatible = "cache"; 246 cache-level = <2>; 247 cache-unified; 248 next-level-cache = <&L3_0>; 249 }; 250 }; 251 252 cpu-map { 253 cluster0 { 254 core0 { 255 cpu = <&CPU0>; 256 }; 257 258 core1 { 259 cpu = <&CPU1>; 260 }; 261 262 core2 { 263 cpu = <&CPU2>; 264 }; 265 266 core3 { 267 cpu = <&CPU3>; 268 }; 269 270 core4 { 271 cpu = <&CPU4>; 272 }; 273 274 core5 { 275 cpu = <&CPU5>; 276 }; 277 278 core6 { 279 cpu = <&CPU6>; 280 }; 281 282 core7 { 283 cpu = <&CPU7>; 284 }; 285 }; 286 }; 287 288 domain-idle-states { 289 CLUSTER_SLEEP_PC: cluster-sleep-0 { 290 compatible = "domain-idle-state"; 291 arm,psci-suspend-param = <0x41000044>; 292 entry-latency-us = <2752>; 293 exit-latency-us = <3048>; 294 min-residency-us = <6118>; 295 }; 296 297 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { 298 compatible = "domain-idle-state"; 299 arm,psci-suspend-param = <0x41001244>; 300 entry-latency-us = <3638>; 301 exit-latency-us = <4562>; 302 min-residency-us = <8467>; 303 }; 304 305 CLUSTER_AOSS_SLEEP: cluster-sleep-2 { 306 compatible = "domain-idle-state"; 307 arm,psci-suspend-param = <0x4100b244>; 308 entry-latency-us = <3263>; 309 exit-latency-us = <6562>; 310 min-residency-us = <9987>; 311 }; 312 }; 313 314 cpu_idle_states: idle-states { 315 entry-method = "psci"; 316 317 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 318 compatible = "arm,idle-state"; 319 idle-state-name = "little-power-collapse"; 320 arm,psci-suspend-param = <0x40000003>; 321 entry-latency-us = <549>; 322 exit-latency-us = <901>; 323 min-residency-us = <1774>; 324 local-timer-stop; 325 }; 326 327 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 328 compatible = "arm,idle-state"; 329 idle-state-name = "little-rail-power-collapse"; 330 arm,psci-suspend-param = <0x40000004>; 331 entry-latency-us = <702>; 332 exit-latency-us = <915>; 333 min-residency-us = <4001>; 334 local-timer-stop; 335 }; 336 337 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 338 compatible = "arm,idle-state"; 339 idle-state-name = "big-power-collapse"; 340 arm,psci-suspend-param = <0x40000003>; 341 entry-latency-us = <523>; 342 exit-latency-us = <1244>; 343 min-residency-us = <2207>; 344 local-timer-stop; 345 }; 346 347 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 348 compatible = "arm,idle-state"; 349 idle-state-name = "big-rail-power-collapse"; 350 arm,psci-suspend-param = <0x40000004>; 351 entry-latency-us = <526>; 352 exit-latency-us = <1854>; 353 min-residency-us = <5555>; 354 local-timer-stop; 355 }; 356 }; 357 }; 358 359 firmware { 360 scm: scm { 361 compatible = "qcom,scm-sm6350", "qcom,scm"; 362 #reset-cells = <1>; 363 }; 364 }; 365 366 memory@80000000 { 367 device_type = "memory"; 368 /* We expect the bootloader to fill in the size */ 369 reg = <0x0 0x80000000 0x0 0x0>; 370 }; 371 372 cpu0_opp_table: opp-table-cpu0 { 373 compatible = "operating-points-v2"; 374 opp-shared; 375 376 opp-300000000 { 377 opp-hz = /bits/ 64 <300000000>; 378 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ 379 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 380 }; 381 382 opp-576000000 { 383 opp-hz = /bits/ 64 <576000000>; 384 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>; 385 }; 386 387 opp-768000000 { 388 opp-hz = /bits/ 64 <768000000>; 389 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 390 }; 391 392 opp-1017600000 { 393 opp-hz = /bits/ 64 <1017600000>; 394 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 395 }; 396 397 opp-1248000000 { 398 opp-hz = /bits/ 64 <1248000000>; 399 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 400 }; 401 402 opp-1324800000 { 403 opp-hz = /bits/ 64 <1324800000>; 404 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>; 405 }; 406 407 opp-1516800000 { 408 opp-hz = /bits/ 64 <1516800000>; 409 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 410 }; 411 412 opp-1612800000 { 413 opp-hz = /bits/ 64 <1612800000>; 414 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 415 }; 416 417 opp-1708800000 { 418 opp-hz = /bits/ 64 <1708800000>; 419 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 420 }; 421 }; 422 423 cpu6_opp_table: opp-table-cpu6 { 424 compatible = "operating-points-v2"; 425 opp-shared; 426 427 opp-300000000 { 428 opp-hz = /bits/ 64 <300000000>; 429 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 430 }; 431 432 opp-787200000 { 433 opp-hz = /bits/ 64 <787200000>; 434 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 435 }; 436 437 opp-979200000 { 438 opp-hz = /bits/ 64 <979200000>; 439 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>; 440 }; 441 442 opp-1036800000 { 443 opp-hz = /bits/ 64 <1036800000>; 444 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 445 }; 446 447 opp-1248000000 { 448 opp-hz = /bits/ 64 <1248000000>; 449 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 450 }; 451 452 opp-1401600000 { 453 opp-hz = /bits/ 64 <1401600000>; 454 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>; 455 }; 456 457 opp-1555200000 { 458 opp-hz = /bits/ 64 <1555200000>; 459 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 460 }; 461 462 opp-1766400000 { 463 opp-hz = /bits/ 64 <1766400000>; 464 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 465 }; 466 467 opp-1900800000 { 468 opp-hz = /bits/ 64 <1900800000>; 469 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 470 }; 471 472 opp-2073600000 { 473 opp-hz = /bits/ 64 <2073600000>; 474 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 475 }; 476 }; 477 478 qup_opp_table: opp-table-qup { 479 compatible = "operating-points-v2"; 480 481 opp-75000000 { 482 opp-hz = /bits/ 64 <75000000>; 483 required-opps = <&rpmhpd_opp_low_svs>; 484 }; 485 486 opp-100000000 { 487 opp-hz = /bits/ 64 <100000000>; 488 required-opps = <&rpmhpd_opp_svs>; 489 }; 490 491 opp-128000000 { 492 opp-hz = /bits/ 64 <128000000>; 493 required-opps = <&rpmhpd_opp_nom>; 494 }; 495 }; 496 497 pmu { 498 compatible = "arm,armv8-pmuv3"; 499 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 500 }; 501 502 psci { 503 compatible = "arm,psci-1.0"; 504 method = "smc"; 505 506 CPU_PD0: power-domain-cpu0 { 507 #power-domain-cells = <0>; 508 power-domains = <&CLUSTER_PD>; 509 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 510 }; 511 512 CPU_PD1: power-domain-cpu1 { 513 #power-domain-cells = <0>; 514 power-domains = <&CLUSTER_PD>; 515 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 516 }; 517 518 CPU_PD2: power-domain-cpu2 { 519 #power-domain-cells = <0>; 520 power-domains = <&CLUSTER_PD>; 521 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 522 }; 523 524 CPU_PD3: power-domain-cpu3 { 525 #power-domain-cells = <0>; 526 power-domains = <&CLUSTER_PD>; 527 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 528 }; 529 530 CPU_PD4: power-domain-cpu4 { 531 #power-domain-cells = <0>; 532 power-domains = <&CLUSTER_PD>; 533 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 534 }; 535 536 CPU_PD5: power-domain-cpu5 { 537 #power-domain-cells = <0>; 538 power-domains = <&CLUSTER_PD>; 539 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 540 }; 541 542 CPU_PD6: power-domain-cpu6 { 543 #power-domain-cells = <0>; 544 power-domains = <&CLUSTER_PD>; 545 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 546 }; 547 548 CPU_PD7: power-domain-cpu7 { 549 #power-domain-cells = <0>; 550 power-domains = <&CLUSTER_PD>; 551 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 552 }; 553 554 CLUSTER_PD: power-domain-cpu-cluster0 { 555 #power-domain-cells = <0>; 556 domain-idle-states = <&CLUSTER_SLEEP_PC 557 &CLUSTER_SLEEP_CX_RET 558 &CLUSTER_AOSS_SLEEP>; 559 }; 560 }; 561 562 reserved_memory: reserved-memory { 563 #address-cells = <2>; 564 #size-cells = <2>; 565 ranges; 566 567 hyp_mem: memory@80000000 { 568 reg = <0 0x80000000 0 0x600000>; 569 no-map; 570 }; 571 572 xbl_aop_mem: memory@80700000 { 573 reg = <0 0x80700000 0 0x160000>; 574 no-map; 575 }; 576 577 cmd_db: memory@80860000 { 578 compatible = "qcom,cmd-db"; 579 reg = <0 0x80860000 0 0x20000>; 580 no-map; 581 }; 582 583 sec_apps_mem: memory@808ff000 { 584 reg = <0 0x808ff000 0 0x1000>; 585 no-map; 586 }; 587 588 smem_mem: memory@80900000 { 589 reg = <0 0x80900000 0 0x200000>; 590 no-map; 591 }; 592 593 cdsp_sec_mem: memory@80b00000 { 594 reg = <0 0x80b00000 0 0x1e00000>; 595 no-map; 596 }; 597 598 pil_camera_mem: memory@86000000 { 599 reg = <0 0x86000000 0 0x500000>; 600 no-map; 601 }; 602 603 pil_npu_mem: memory@86500000 { 604 reg = <0 0x86500000 0 0x500000>; 605 no-map; 606 }; 607 608 pil_video_mem: memory@86a00000 { 609 reg = <0 0x86a00000 0 0x500000>; 610 no-map; 611 }; 612 613 pil_cdsp_mem: memory@86f00000 { 614 reg = <0 0x86f00000 0 0x1e00000>; 615 no-map; 616 }; 617 618 pil_adsp_mem: memory@88d00000 { 619 reg = <0 0x88d00000 0 0x2800000>; 620 no-map; 621 }; 622 623 wlan_fw_mem: memory@8b500000 { 624 reg = <0 0x8b500000 0 0x200000>; 625 no-map; 626 }; 627 628 pil_ipa_fw_mem: memory@8b700000 { 629 reg = <0 0x8b700000 0 0x10000>; 630 no-map; 631 }; 632 633 pil_ipa_gsi_mem: memory@8b710000 { 634 reg = <0 0x8b710000 0 0x5400>; 635 no-map; 636 }; 637 638 pil_modem_mem: memory@8b800000 { 639 reg = <0 0x8b800000 0 0xf800000>; 640 no-map; 641 }; 642 643 cont_splash_memory: memory@a0000000 { 644 reg = <0 0xa0000000 0 0x2300000>; 645 no-map; 646 }; 647 648 dfps_data_memory: memory@a2300000 { 649 reg = <0 0xa2300000 0 0x100000>; 650 no-map; 651 }; 652 653 removed_region: memory@c0000000 { 654 reg = <0 0xc0000000 0 0x3900000>; 655 no-map; 656 }; 657 658 pil_gpu_mem: memory@f0d00000 { 659 reg = <0 0xf0d00000 0 0x1000>; 660 no-map; 661 }; 662 663 debug_region: memory@ffb00000 { 664 reg = <0 0xffb00000 0 0xc0000>; 665 no-map; 666 }; 667 668 last_log_region: memory@ffbc0000 { 669 reg = <0 0xffbc0000 0 0x40000>; 670 no-map; 671 }; 672 673 ramoops: ramoops@ffc00000 { 674 compatible = "ramoops"; 675 reg = <0 0xffc00000 0 0x100000>; 676 record-size = <0x1000>; 677 console-size = <0x40000>; 678 pmsg-size = <0x20000>; 679 ecc-size = <16>; 680 no-map; 681 }; 682 683 cmdline_region: memory@ffd00000 { 684 reg = <0 0xffd00000 0 0x1000>; 685 no-map; 686 }; 687 }; 688 689 smem { 690 compatible = "qcom,smem"; 691 memory-region = <&smem_mem>; 692 hwlocks = <&tcsr_mutex 3>; 693 }; 694 695 smp2p-adsp { 696 compatible = "qcom,smp2p"; 697 qcom,smem = <443>, <429>; 698 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 699 IPCC_MPROC_SIGNAL_SMP2P 700 IRQ_TYPE_EDGE_RISING>; 701 mboxes = <&ipcc IPCC_CLIENT_LPASS 702 IPCC_MPROC_SIGNAL_SMP2P>; 703 704 qcom,local-pid = <0>; 705 qcom,remote-pid = <2>; 706 707 smp2p_adsp_out: master-kernel { 708 qcom,entry-name = "master-kernel"; 709 #qcom,smem-state-cells = <1>; 710 }; 711 712 smp2p_adsp_in: slave-kernel { 713 qcom,entry-name = "slave-kernel"; 714 interrupt-controller; 715 #interrupt-cells = <2>; 716 }; 717 }; 718 719 smp2p-cdsp { 720 compatible = "qcom,smp2p"; 721 qcom,smem = <94>, <432>; 722 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 723 IPCC_MPROC_SIGNAL_SMP2P 724 IRQ_TYPE_EDGE_RISING>; 725 mboxes = <&ipcc IPCC_CLIENT_CDSP 726 IPCC_MPROC_SIGNAL_SMP2P>; 727 728 qcom,local-pid = <0>; 729 qcom,remote-pid = <5>; 730 731 smp2p_cdsp_out: master-kernel { 732 qcom,entry-name = "master-kernel"; 733 #qcom,smem-state-cells = <1>; 734 }; 735 736 smp2p_cdsp_in: slave-kernel { 737 qcom,entry-name = "slave-kernel"; 738 interrupt-controller; 739 #interrupt-cells = <2>; 740 }; 741 }; 742 743 smp2p-mpss { 744 compatible = "qcom,smp2p"; 745 qcom,smem = <435>, <428>; 746 747 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 748 IPCC_MPROC_SIGNAL_SMP2P 749 IRQ_TYPE_EDGE_RISING>; 750 mboxes = <&ipcc IPCC_CLIENT_MPSS 751 IPCC_MPROC_SIGNAL_SMP2P>; 752 753 qcom,local-pid = <0>; 754 qcom,remote-pid = <1>; 755 756 modem_smp2p_out: master-kernel { 757 qcom,entry-name = "master-kernel"; 758 #qcom,smem-state-cells = <1>; 759 }; 760 761 modem_smp2p_in: slave-kernel { 762 qcom,entry-name = "slave-kernel"; 763 interrupt-controller; 764 #interrupt-cells = <2>; 765 }; 766 767 ipa_smp2p_out: ipa-ap-to-modem { 768 qcom,entry-name = "ipa"; 769 #qcom,smem-state-cells = <1>; 770 }; 771 772 ipa_smp2p_in: ipa-modem-to-ap { 773 qcom,entry-name = "ipa"; 774 interrupt-controller; 775 #interrupt-cells = <2>; 776 }; 777 }; 778 779 soc: soc@0 { 780 #address-cells = <2>; 781 #size-cells = <2>; 782 ranges = <0 0 0 0 0x10 0>; 783 dma-ranges = <0 0 0 0 0x10 0>; 784 compatible = "simple-bus"; 785 786 gcc: clock-controller@100000 { 787 compatible = "qcom,gcc-sm6350"; 788 reg = <0 0x00100000 0 0x1f0000>; 789 #clock-cells = <1>; 790 #reset-cells = <1>; 791 #power-domain-cells = <1>; 792 clock-names = "bi_tcxo", 793 "bi_tcxo_ao", 794 "sleep_clk"; 795 clocks = <&rpmhcc RPMH_CXO_CLK>, 796 <&rpmhcc RPMH_CXO_CLK_A>, 797 <&sleep_clk>; 798 }; 799 800 ipcc: mailbox@408000 { 801 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 802 reg = <0 0x00408000 0 0x1000>; 803 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 804 interrupt-controller; 805 #interrupt-cells = <3>; 806 #mbox-cells = <2>; 807 }; 808 809 qfprom: qfprom@784000 { 810 compatible = "qcom,sm6350-qfprom", "qcom,qfprom"; 811 reg = <0 0x00784000 0 0x3000>; 812 #address-cells = <1>; 813 #size-cells = <1>; 814 815 gpu_speed_bin: gpu-speed-bin@2015 { 816 reg = <0x2015 0x1>; 817 bits = <0 8>; 818 }; 819 }; 820 821 rng: rng@793000 { 822 compatible = "qcom,prng-ee"; 823 reg = <0 0x00793000 0 0x1000>; 824 clocks = <&gcc GCC_PRNG_AHB_CLK>; 825 clock-names = "core"; 826 }; 827 828 sdhc_1: mmc@7c4000 { 829 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 830 reg = <0 0x007c4000 0 0x1000>, 831 <0 0x007c5000 0 0x1000>, 832 <0 0x007c8000 0 0x8000>; 833 reg-names = "hc", "cqhci", "ice"; 834 835 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 837 interrupt-names = "hc_irq", "pwr_irq"; 838 iommus = <&apps_smmu 0x60 0x0>; 839 840 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 841 <&gcc GCC_SDCC1_APPS_CLK>, 842 <&rpmhcc RPMH_CXO_CLK>; 843 clock-names = "iface", "core", "xo"; 844 resets = <&gcc GCC_SDCC1_BCR>; 845 qcom,dll-config = <0x000f642c>; 846 qcom,ddr-config = <0x80040868>; 847 power-domains = <&rpmhpd SM6350_CX>; 848 operating-points-v2 = <&sdhc1_opp_table>; 849 bus-width = <8>; 850 non-removable; 851 supports-cqe; 852 853 status = "disabled"; 854 855 sdhc1_opp_table: opp-table { 856 compatible = "operating-points-v2"; 857 858 opp-19200000 { 859 opp-hz = /bits/ 64 <19200000>; 860 required-opps = <&rpmhpd_opp_min_svs>; 861 }; 862 863 opp-100000000 { 864 opp-hz = /bits/ 64 <100000000>; 865 required-opps = <&rpmhpd_opp_low_svs>; 866 }; 867 868 opp-384000000 { 869 opp-hz = /bits/ 64 <384000000>; 870 required-opps = <&rpmhpd_opp_svs_l1>; 871 }; 872 }; 873 }; 874 875 gpi_dma0: dma-controller@800000 { 876 compatible = "qcom,sm6350-gpi-dma"; 877 reg = <0 0x00800000 0 0x60000>; 878 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 888 dma-channels = <10>; 889 dma-channel-mask = <0x1f>; 890 iommus = <&apps_smmu 0x56 0x0>; 891 #dma-cells = <3>; 892 status = "disabled"; 893 }; 894 895 qupv3_id_0: geniqup@8c0000 { 896 compatible = "qcom,geni-se-qup"; 897 reg = <0x0 0x008c0000 0x0 0x2000>; 898 clock-names = "m-ahb", "s-ahb"; 899 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 900 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 901 #address-cells = <2>; 902 #size-cells = <2>; 903 iommus = <&apps_smmu 0x43 0x0>; 904 ranges; 905 status = "disabled"; 906 907 i2c0: i2c@880000 { 908 compatible = "qcom,geni-i2c"; 909 reg = <0 0x00880000 0 0x4000>; 910 clock-names = "se"; 911 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&qup_i2c0_default>; 914 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 915 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 916 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 917 dma-names = "tx", "rx"; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 921 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 922 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 923 interconnect-names = "qup-core", "qup-config", "qup-memory"; 924 status = "disabled"; 925 }; 926 927 uart1: serial@884000 { 928 compatible = "qcom,geni-uart"; 929 reg = <0 0x00884000 0 0x4000>; 930 clock-names = "se"; 931 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 932 pinctrl-names = "default"; 933 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 934 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 935 power-domains = <&rpmhpd SM6350_CX>; 936 operating-points-v2 = <&qup_opp_table>; 937 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 938 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 939 interconnect-names = "qup-core", "qup-config"; 940 status = "disabled"; 941 }; 942 943 i2c2: i2c@888000 { 944 compatible = "qcom,geni-i2c"; 945 reg = <0 0x00888000 0 0x4000>; 946 clock-names = "se"; 947 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 948 pinctrl-names = "default"; 949 pinctrl-0 = <&qup_i2c2_default>; 950 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 951 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 952 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 953 dma-names = "tx", "rx"; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 957 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 958 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 959 interconnect-names = "qup-core", "qup-config", "qup-memory"; 960 status = "disabled"; 961 }; 962 }; 963 964 gpi_dma1: dma-controller@900000 { 965 compatible = "qcom,sm6350-gpi-dma"; 966 reg = <0 0x00900000 0 0x60000>; 967 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 977 dma-channels = <10>; 978 dma-channel-mask = <0x3f>; 979 iommus = <&apps_smmu 0x4d6 0x0>; 980 #dma-cells = <3>; 981 status = "disabled"; 982 }; 983 984 qupv3_id_1: geniqup@9c0000 { 985 compatible = "qcom,geni-se-qup"; 986 reg = <0x0 0x009c0000 0x0 0x2000>; 987 clock-names = "m-ahb", "s-ahb"; 988 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 989 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 990 #address-cells = <2>; 991 #size-cells = <2>; 992 iommus = <&apps_smmu 0x4c3 0x0>; 993 ranges; 994 status = "disabled"; 995 996 i2c6: i2c@980000 { 997 compatible = "qcom,geni-i2c"; 998 reg = <0 0x00980000 0 0x4000>; 999 clock-names = "se"; 1000 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1001 pinctrl-names = "default"; 1002 pinctrl-0 = <&qup_i2c6_default>; 1003 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1004 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1005 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1006 dma-names = "tx", "rx"; 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1010 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1011 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1012 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1013 status = "disabled"; 1014 }; 1015 1016 i2c7: i2c@984000 { 1017 compatible = "qcom,geni-i2c"; 1018 reg = <0 0x00984000 0 0x4000>; 1019 clock-names = "se"; 1020 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1021 pinctrl-names = "default"; 1022 pinctrl-0 = <&qup_i2c7_default>; 1023 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1024 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1025 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1026 dma-names = "tx", "rx"; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1030 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1031 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1032 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1033 status = "disabled"; 1034 }; 1035 1036 i2c8: i2c@988000 { 1037 compatible = "qcom,geni-i2c"; 1038 reg = <0 0x00988000 0 0x4000>; 1039 clock-names = "se"; 1040 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1041 pinctrl-names = "default"; 1042 pinctrl-0 = <&qup_i2c8_default>; 1043 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1044 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1045 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1046 dma-names = "tx", "rx"; 1047 #address-cells = <1>; 1048 #size-cells = <0>; 1049 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1050 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1051 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1052 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1053 status = "disabled"; 1054 }; 1055 1056 uart9: serial@98c000 { 1057 compatible = "qcom,geni-debug-uart"; 1058 reg = <0 0x0098c000 0 0x4000>; 1059 clock-names = "se"; 1060 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1061 pinctrl-names = "default"; 1062 pinctrl-0 = <&qup_uart9_default>; 1063 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1064 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1065 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1066 interconnect-names = "qup-core", "qup-config"; 1067 status = "disabled"; 1068 }; 1069 1070 i2c10: i2c@990000 { 1071 compatible = "qcom,geni-i2c"; 1072 reg = <0 0x00990000 0 0x4000>; 1073 clock-names = "se"; 1074 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1075 pinctrl-names = "default"; 1076 pinctrl-0 = <&qup_i2c10_default>; 1077 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1078 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1079 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1080 dma-names = "tx", "rx"; 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1084 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1085 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1086 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1087 status = "disabled"; 1088 }; 1089 }; 1090 1091 config_noc: interconnect@1500000 { 1092 compatible = "qcom,sm6350-config-noc"; 1093 reg = <0 0x01500000 0 0x28000>; 1094 #interconnect-cells = <2>; 1095 qcom,bcm-voters = <&apps_bcm_voter>; 1096 }; 1097 1098 system_noc: interconnect@1620000 { 1099 compatible = "qcom,sm6350-system-noc"; 1100 reg = <0 0x01620000 0 0x17080>; 1101 #interconnect-cells = <2>; 1102 qcom,bcm-voters = <&apps_bcm_voter>; 1103 1104 clk_virt: interconnect-clk-virt { 1105 compatible = "qcom,sm6350-clk-virt"; 1106 #interconnect-cells = <2>; 1107 qcom,bcm-voters = <&apps_bcm_voter>; 1108 }; 1109 }; 1110 1111 aggre1_noc: interconnect@16e0000 { 1112 compatible = "qcom,sm6350-aggre1-noc"; 1113 reg = <0 0x016e0000 0 0x15080>; 1114 #interconnect-cells = <2>; 1115 qcom,bcm-voters = <&apps_bcm_voter>; 1116 }; 1117 1118 aggre2_noc: interconnect@1700000 { 1119 compatible = "qcom,sm6350-aggre2-noc"; 1120 reg = <0 0x01700000 0 0x1f880>; 1121 #interconnect-cells = <2>; 1122 qcom,bcm-voters = <&apps_bcm_voter>; 1123 1124 compute_noc: interconnect-compute-noc { 1125 compatible = "qcom,sm6350-compute-noc"; 1126 #interconnect-cells = <2>; 1127 qcom,bcm-voters = <&apps_bcm_voter>; 1128 }; 1129 }; 1130 1131 mmss_noc: interconnect@1740000 { 1132 compatible = "qcom,sm6350-mmss-noc"; 1133 reg = <0 0x01740000 0 0x1c100>; 1134 #interconnect-cells = <2>; 1135 qcom,bcm-voters = <&apps_bcm_voter>; 1136 }; 1137 1138 ufs_mem_hc: ufs@1d84000 { 1139 compatible = "qcom,sm6350-ufshc", "qcom,ufshc", 1140 "jedec,ufs-2.0"; 1141 reg = <0 0x01d84000 0 0x3000>, 1142 <0 0x01d90000 0 0x8000>; 1143 reg-names = "std", "ice"; 1144 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1145 phys = <&ufs_mem_phy_lanes>; 1146 phy-names = "ufsphy"; 1147 lanes-per-direction = <2>; 1148 #reset-cells = <1>; 1149 resets = <&gcc GCC_UFS_PHY_BCR>; 1150 reset-names = "rst"; 1151 1152 power-domains = <&gcc UFS_PHY_GDSC>; 1153 1154 iommus = <&apps_smmu 0x80 0x0>; 1155 1156 clock-names = "core_clk", 1157 "bus_aggr_clk", 1158 "iface_clk", 1159 "core_clk_unipro", 1160 "ref_clk", 1161 "tx_lane0_sync_clk", 1162 "rx_lane0_sync_clk", 1163 "rx_lane1_sync_clk", 1164 "ice_core_clk"; 1165 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1166 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1167 <&gcc GCC_UFS_PHY_AHB_CLK>, 1168 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1169 <&rpmhcc RPMH_QLINK_CLK>, 1170 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1171 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1172 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 1173 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1174 freq-table-hz = 1175 <50000000 200000000>, 1176 <0 0>, 1177 <0 0>, 1178 <37500000 150000000>, 1179 <75000000 300000000>, 1180 <0 0>, 1181 <0 0>, 1182 <0 0>, 1183 <0 0>; 1184 1185 status = "disabled"; 1186 }; 1187 1188 ufs_mem_phy: phy@1d87000 { 1189 compatible = "qcom,sm6350-qmp-ufs-phy"; 1190 reg = <0 0x01d87000 0 0x18c>; 1191 #address-cells = <2>; 1192 #size-cells = <2>; 1193 ranges; 1194 1195 clock-names = "ref", 1196 "ref_aux"; 1197 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 1198 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1199 1200 power-domains = <&gcc UFS_PHY_GDSC>; 1201 1202 resets = <&ufs_mem_hc 0>; 1203 reset-names = "ufsphy"; 1204 1205 status = "disabled"; 1206 1207 ufs_mem_phy_lanes: phy@1d87400 { 1208 reg = <0 0x01d87400 0 0x128>, 1209 <0 0x01d87600 0 0x1fc>, 1210 <0 0x01d87c00 0 0x1dc>, 1211 <0 0x01d87800 0 0x128>, 1212 <0 0x01d87a00 0 0x1fc>; 1213 #phy-cells = <0>; 1214 }; 1215 }; 1216 1217 ipa: ipa@1e40000 { 1218 compatible = "qcom,sm6350-ipa"; 1219 1220 iommus = <&apps_smmu 0x440 0x0>, 1221 <&apps_smmu 0x442 0x0>; 1222 reg = <0 0x01e40000 0 0x8000>, 1223 <0 0x01e50000 0 0x3000>, 1224 <0 0x01e04000 0 0x23000>; 1225 reg-names = "ipa-reg", 1226 "ipa-shared", 1227 "gsi"; 1228 1229 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1230 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1231 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1232 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1233 interrupt-names = "ipa", 1234 "gsi", 1235 "ipa-clock-query", 1236 "ipa-setup-ready"; 1237 1238 clocks = <&rpmhcc RPMH_IPA_CLK>; 1239 clock-names = "core"; 1240 1241 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>, 1242 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, 1243 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; 1244 interconnect-names = "memory", "imem", "config"; 1245 1246 qcom,smem-states = <&ipa_smp2p_out 0>, 1247 <&ipa_smp2p_out 1>; 1248 qcom,smem-state-names = "ipa-clock-enabled-valid", 1249 "ipa-clock-enabled"; 1250 1251 status = "disabled"; 1252 }; 1253 1254 tcsr_mutex: hwlock@1f40000 { 1255 compatible = "qcom,tcsr-mutex"; 1256 reg = <0x0 0x01f40000 0x0 0x40000>; 1257 #hwlock-cells = <1>; 1258 }; 1259 1260 adsp: remoteproc@3000000 { 1261 compatible = "qcom,sm6350-adsp-pas"; 1262 reg = <0 0x03000000 0 0x100>; 1263 1264 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 1265 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1266 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1267 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1268 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1269 interrupt-names = "wdog", "fatal", "ready", 1270 "handover", "stop-ack"; 1271 1272 clocks = <&rpmhcc RPMH_CXO_CLK>; 1273 clock-names = "xo"; 1274 1275 power-domains = <&rpmhpd SM6350_LCX>, 1276 <&rpmhpd SM6350_LMX>; 1277 power-domain-names = "lcx", "lmx"; 1278 1279 memory-region = <&pil_adsp_mem>; 1280 1281 qcom,qmp = <&aoss_qmp>; 1282 1283 qcom,smem-states = <&smp2p_adsp_out 0>; 1284 qcom,smem-state-names = "stop"; 1285 1286 status = "disabled"; 1287 1288 glink-edge { 1289 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1290 IPCC_MPROC_SIGNAL_GLINK_QMP 1291 IRQ_TYPE_EDGE_RISING>; 1292 mboxes = <&ipcc IPCC_CLIENT_LPASS 1293 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1294 1295 label = "lpass"; 1296 qcom,remote-pid = <2>; 1297 1298 fastrpc { 1299 compatible = "qcom,fastrpc"; 1300 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1301 label = "adsp"; 1302 qcom,non-secure-domain; 1303 #address-cells = <1>; 1304 #size-cells = <0>; 1305 1306 compute-cb@3 { 1307 compatible = "qcom,fastrpc-compute-cb"; 1308 reg = <3>; 1309 iommus = <&apps_smmu 0x1003 0x0>; 1310 }; 1311 1312 compute-cb@4 { 1313 compatible = "qcom,fastrpc-compute-cb"; 1314 reg = <4>; 1315 iommus = <&apps_smmu 0x1004 0x0>; 1316 }; 1317 1318 compute-cb@5 { 1319 compatible = "qcom,fastrpc-compute-cb"; 1320 reg = <5>; 1321 iommus = <&apps_smmu 0x1005 0x0>; 1322 qcom,nsessions = <5>; 1323 }; 1324 }; 1325 }; 1326 }; 1327 1328 gpu: gpu@3d00000 { 1329 compatible = "qcom,adreno-619.0", "qcom,adreno"; 1330 reg = <0 0x03d00000 0 0x40000>, 1331 <0 0x03d9e000 0 0x1000>; 1332 reg-names = "kgsl_3d0_reg_memory", 1333 "cx_mem"; 1334 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1335 1336 iommus = <&adreno_smmu 0>; 1337 operating-points-v2 = <&gpu_opp_table>; 1338 qcom,gmu = <&gmu>; 1339 nvmem-cells = <&gpu_speed_bin>; 1340 nvmem-cell-names = "speed_bin"; 1341 1342 status = "disabled"; 1343 1344 zap-shader { 1345 memory-region = <&pil_gpu_mem>; 1346 }; 1347 1348 gpu_opp_table: opp-table { 1349 compatible = "operating-points-v2"; 1350 1351 opp-850000000 { 1352 opp-hz = /bits/ 64 <850000000>; 1353 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1354 opp-supported-hw = <0x02>; 1355 }; 1356 1357 opp-800000000 { 1358 opp-hz = /bits/ 64 <800000000>; 1359 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1360 opp-supported-hw = <0x04>; 1361 }; 1362 1363 opp-650000000 { 1364 opp-hz = /bits/ 64 <650000000>; 1365 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1366 opp-supported-hw = <0x08>; 1367 }; 1368 1369 opp-565000000 { 1370 opp-hz = /bits/ 64 <565000000>; 1371 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1372 opp-supported-hw = <0x10>; 1373 }; 1374 1375 opp-430000000 { 1376 opp-hz = /bits/ 64 <430000000>; 1377 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1378 opp-supported-hw = <0xff>; 1379 }; 1380 1381 opp-355000000 { 1382 opp-hz = /bits/ 64 <355000000>; 1383 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1384 opp-supported-hw = <0xff>; 1385 }; 1386 1387 opp-253000000 { 1388 opp-hz = /bits/ 64 <253000000>; 1389 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1390 opp-supported-hw = <0xff>; 1391 }; 1392 }; 1393 }; 1394 1395 adreno_smmu: iommu@3d40000 { 1396 compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 1397 reg = <0 0x03d40000 0 0x10000>; 1398 #iommu-cells = <1>; 1399 #global-interrupts = <2>; 1400 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1410 1411 clocks = <&gpucc GPU_CC_AHB_CLK>, 1412 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1413 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1414 clock-names = "ahb", 1415 "bus", 1416 "iface"; 1417 1418 power-domains = <&gpucc GPU_CX_GDSC>; 1419 }; 1420 1421 gmu: gmu@3d6a000 { 1422 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu"; 1423 reg = <0 0x03d6a000 0 0x31000>, 1424 <0 0x0b290000 0 0x10000>, 1425 <0 0x0b490000 0 0x10000>; 1426 reg-names = "gmu", 1427 "gmu_pdc", 1428 "gmu_pdc_seq"; 1429 1430 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1432 interrupt-names = "hfi", 1433 "gmu"; 1434 1435 clocks = <&gpucc GPU_CC_AHB_CLK>, 1436 <&gpucc GPU_CC_CX_GMU_CLK>, 1437 <&gpucc GPU_CC_CXO_CLK>, 1438 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1439 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1440 clock-names = "ahb", 1441 "gmu", 1442 "cxo", 1443 "axi", 1444 "memnoc"; 1445 1446 power-domains = <&gpucc GPU_CX_GDSC>, 1447 <&gpucc GPU_GX_GDSC>; 1448 power-domain-names = "cx", 1449 "gx"; 1450 1451 iommus = <&adreno_smmu 5>; 1452 1453 operating-points-v2 = <&gmu_opp_table>; 1454 1455 status = "disabled"; 1456 1457 gmu_opp_table: opp-table { 1458 compatible = "operating-points-v2"; 1459 1460 opp-200000000 { 1461 opp-hz = /bits/ 64 <200000000>; 1462 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1463 }; 1464 }; 1465 }; 1466 1467 gpucc: clock-controller@3d90000 { 1468 compatible = "qcom,sm6350-gpucc"; 1469 reg = <0 0x03d90000 0 0x9000>; 1470 clocks = <&rpmhcc RPMH_CXO_CLK>, 1471 <&gcc GCC_GPU_GPLL0_CLK>, 1472 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1473 clock-names = "bi_tcxo", 1474 "gcc_gpu_gpll0_clk_src", 1475 "gcc_gpu_gpll0_div_clk_src"; 1476 #clock-cells = <1>; 1477 #reset-cells = <1>; 1478 #power-domain-cells = <1>; 1479 }; 1480 1481 mpss: remoteproc@4080000 { 1482 compatible = "qcom,sm6350-mpss-pas"; 1483 reg = <0x0 0x04080000 0x0 0x4040>; 1484 1485 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 1486 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1487 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1488 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1489 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1490 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1491 interrupt-names = "wdog", "fatal", "ready", "handover", 1492 "stop-ack", "shutdown-ack"; 1493 1494 clocks = <&rpmhcc RPMH_CXO_CLK>; 1495 clock-names = "xo"; 1496 1497 power-domains = <&rpmhpd SM6350_CX>, 1498 <&rpmhpd SM6350_MSS>; 1499 power-domain-names = "cx", "mss"; 1500 1501 memory-region = <&pil_modem_mem>; 1502 1503 qcom,qmp = <&aoss_qmp>; 1504 1505 qcom,smem-states = <&modem_smp2p_out 0>; 1506 qcom,smem-state-names = "stop"; 1507 1508 status = "disabled"; 1509 1510 glink-edge { 1511 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1512 IPCC_MPROC_SIGNAL_GLINK_QMP 1513 IRQ_TYPE_EDGE_RISING>; 1514 mboxes = <&ipcc IPCC_CLIENT_MPSS 1515 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1516 label = "modem"; 1517 qcom,remote-pid = <1>; 1518 }; 1519 }; 1520 1521 cdsp: remoteproc@8300000 { 1522 compatible = "qcom,sm6350-cdsp-pas"; 1523 reg = <0 0x08300000 0 0x10000>; 1524 1525 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 1526 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1527 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1528 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1529 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1530 interrupt-names = "wdog", "fatal", "ready", 1531 "handover", "stop-ack"; 1532 1533 clocks = <&rpmhcc RPMH_CXO_CLK>; 1534 clock-names = "xo"; 1535 1536 power-domains = <&rpmhpd SM6350_CX>, 1537 <&rpmhpd SM6350_MX>; 1538 power-domain-names = "cx", "mx"; 1539 1540 memory-region = <&pil_cdsp_mem>; 1541 1542 qcom,qmp = <&aoss_qmp>; 1543 1544 qcom,smem-states = <&smp2p_cdsp_out 0>; 1545 qcom,smem-state-names = "stop"; 1546 1547 status = "disabled"; 1548 1549 glink-edge { 1550 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1551 IPCC_MPROC_SIGNAL_GLINK_QMP 1552 IRQ_TYPE_EDGE_RISING>; 1553 mboxes = <&ipcc IPCC_CLIENT_CDSP 1554 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1555 1556 label = "cdsp"; 1557 qcom,remote-pid = <5>; 1558 1559 fastrpc { 1560 compatible = "qcom,fastrpc"; 1561 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1562 label = "cdsp"; 1563 qcom,non-secure-domain; 1564 #address-cells = <1>; 1565 #size-cells = <0>; 1566 1567 compute-cb@1 { 1568 compatible = "qcom,fastrpc-compute-cb"; 1569 reg = <1>; 1570 iommus = <&apps_smmu 0x1401 0x20>; 1571 }; 1572 1573 compute-cb@2 { 1574 compatible = "qcom,fastrpc-compute-cb"; 1575 reg = <2>; 1576 iommus = <&apps_smmu 0x1402 0x20>; 1577 }; 1578 1579 compute-cb@3 { 1580 compatible = "qcom,fastrpc-compute-cb"; 1581 reg = <3>; 1582 iommus = <&apps_smmu 0x1403 0x20>; 1583 }; 1584 1585 compute-cb@4 { 1586 compatible = "qcom,fastrpc-compute-cb"; 1587 reg = <4>; 1588 iommus = <&apps_smmu 0x1404 0x20>; 1589 }; 1590 1591 compute-cb@5 { 1592 compatible = "qcom,fastrpc-compute-cb"; 1593 reg = <5>; 1594 iommus = <&apps_smmu 0x1405 0x20>; 1595 }; 1596 1597 compute-cb@6 { 1598 compatible = "qcom,fastrpc-compute-cb"; 1599 reg = <6>; 1600 iommus = <&apps_smmu 0x1406 0x20>; 1601 }; 1602 1603 compute-cb@7 { 1604 compatible = "qcom,fastrpc-compute-cb"; 1605 reg = <7>; 1606 iommus = <&apps_smmu 0x1407 0x20>; 1607 }; 1608 1609 compute-cb@8 { 1610 compatible = "qcom,fastrpc-compute-cb"; 1611 reg = <8>; 1612 iommus = <&apps_smmu 0x1408 0x20>; 1613 }; 1614 1615 /* note: secure cb9 in downstream */ 1616 }; 1617 }; 1618 }; 1619 1620 sdhc_2: mmc@8804000 { 1621 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 1622 reg = <0 0x08804000 0 0x1000>; 1623 1624 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1626 interrupt-names = "hc_irq", "pwr_irq"; 1627 iommus = <&apps_smmu 0x560 0x0>; 1628 1629 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1630 <&gcc GCC_SDCC2_APPS_CLK>, 1631 <&rpmhcc RPMH_CXO_CLK>; 1632 clock-names = "iface", "core", "xo"; 1633 resets = <&gcc GCC_SDCC2_BCR>; 1634 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, 1635 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; 1636 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1637 1638 pinctrl-0 = <&sdc2_on_state>; 1639 pinctrl-1 = <&sdc2_off_state>; 1640 pinctrl-names = "default", "sleep"; 1641 1642 qcom,dll-config = <0x0007642c>; 1643 qcom,ddr-config = <0x80040868>; 1644 power-domains = <&rpmhpd SM6350_CX>; 1645 operating-points-v2 = <&sdhc2_opp_table>; 1646 bus-width = <4>; 1647 1648 status = "disabled"; 1649 1650 sdhc2_opp_table: opp-table { 1651 compatible = "operating-points-v2"; 1652 1653 opp-100000000 { 1654 opp-hz = /bits/ 64 <100000000>; 1655 required-opps = <&rpmhpd_opp_svs_l1>; 1656 opp-peak-kBps = <790000 131000>; 1657 opp-avg-kBps = <50000 50000>; 1658 }; 1659 1660 opp-202000000 { 1661 opp-hz = /bits/ 64 <202000000>; 1662 required-opps = <&rpmhpd_opp_nom>; 1663 opp-peak-kBps = <3190000 294000>; 1664 opp-avg-kBps = <261438 300000>; 1665 }; 1666 }; 1667 }; 1668 1669 usb_1_hsphy: phy@88e3000 { 1670 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 1671 reg = <0 0x088e3000 0 0x400>; 1672 status = "disabled"; 1673 #phy-cells = <0>; 1674 1675 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 1676 clock-names = "cfg_ahb", "ref"; 1677 1678 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1679 }; 1680 1681 usb_1_qmpphy: phy@88e8000 { 1682 compatible = "qcom,sm6350-qmp-usb3-dp-phy"; 1683 reg = <0 0x088e8000 0 0x3000>; 1684 1685 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1686 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1687 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1688 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1689 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 1690 1691 power-domains = <&gcc USB30_PRIM_GDSC>; 1692 1693 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1694 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1695 reset-names = "phy", "common"; 1696 1697 #clock-cells = <1>; 1698 #phy-cells = <1>; 1699 1700 status = "disabled"; 1701 }; 1702 1703 dc_noc: interconnect@9160000 { 1704 compatible = "qcom,sm6350-dc-noc"; 1705 reg = <0 0x09160000 0 0x3200>; 1706 #interconnect-cells = <2>; 1707 qcom,bcm-voters = <&apps_bcm_voter>; 1708 }; 1709 1710 system-cache-controller@9200000 { 1711 compatible = "qcom,sm6350-llcc"; 1712 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 1713 reg-names = "llcc0_base", "llcc_broadcast_base"; 1714 }; 1715 1716 gem_noc: interconnect@9680000 { 1717 compatible = "qcom,sm6350-gem-noc"; 1718 reg = <0 0x09680000 0 0x3e200>; 1719 #interconnect-cells = <2>; 1720 qcom,bcm-voters = <&apps_bcm_voter>; 1721 }; 1722 1723 npu_noc: interconnect@9990000 { 1724 compatible = "qcom,sm6350-npu-noc"; 1725 reg = <0 0x09990000 0 0x1600>; 1726 #interconnect-cells = <2>; 1727 qcom,bcm-voters = <&apps_bcm_voter>; 1728 }; 1729 1730 pmu@90b6300 { 1731 compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon"; 1732 reg = <0x0 0x090b6300 0x0 0x600>; 1733 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 1734 1735 operating-points-v2 = <&llcc_bwmon_opp_table>; 1736 interconnects = <&clk_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 1737 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1738 1739 llcc_bwmon_opp_table: opp-table { 1740 compatible = "operating-points-v2"; 1741 1742 opp-0 { 1743 opp-peak-kBps = <2288000>; 1744 }; 1745 1746 opp-1 { 1747 opp-peak-kBps = <4577000>; 1748 }; 1749 1750 opp-2 { 1751 opp-peak-kBps = <7110000>; 1752 }; 1753 1754 opp-3 { 1755 opp-peak-kBps = <9155000>; 1756 }; 1757 1758 opp-4 { 1759 opp-peak-kBps = <12298000>; 1760 }; 1761 1762 opp-5 { 1763 opp-peak-kBps = <14236000>; 1764 }; 1765 1766 }; 1767 }; 1768 1769 pmu@90cd000 { 1770 compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon"; 1771 reg = <0x0 0x090cd000 0x0 0x1000>; 1772 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1773 1774 operating-points-v2 = <&cpu_bwmon_opp_table>; 1775 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 1776 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1777 1778 cpu_bwmon_opp_table: opp-table { 1779 compatible = "operating-points-v2"; 1780 1781 opp-0 { 1782 opp-peak-kBps = <762000>; 1783 }; 1784 1785 opp-1 { 1786 opp-peak-kBps = <1144000>; 1787 }; 1788 1789 opp-2 { 1790 opp-peak-kBps = <1720000>; 1791 }; 1792 1793 opp-3 { 1794 opp-peak-kBps = <2086000>; 1795 }; 1796 1797 opp-4 { 1798 opp-peak-kBps = <2597000>; 1799 }; 1800 1801 opp-5 { 1802 opp-peak-kBps = <2929000>; 1803 }; 1804 1805 opp-6 { 1806 opp-peak-kBps = <3879000>; 1807 }; 1808 1809 opp-7 { 1810 opp-peak-kBps = <5161000>; 1811 }; 1812 1813 opp-8 { 1814 opp-peak-kBps = <5931000>; 1815 }; 1816 1817 opp-9 { 1818 opp-peak-kBps = <6881000>; 1819 }; 1820 1821 opp-10 { 1822 opp-peak-kBps = <7980000>; 1823 }; 1824 }; 1825 }; 1826 1827 usb_1: usb@a6f8800 { 1828 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 1829 reg = <0 0x0a6f8800 0 0x400>; 1830 status = "disabled"; 1831 #address-cells = <2>; 1832 #size-cells = <2>; 1833 ranges; 1834 1835 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1836 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1837 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1838 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1839 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1840 clock-names = "cfg_noc", 1841 "core", 1842 "iface", 1843 "sleep", 1844 "mock_utmi"; 1845 1846 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1847 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 1848 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1849 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 1850 1851 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1852 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1853 1854 power-domains = <&gcc USB30_PRIM_GDSC>; 1855 1856 resets = <&gcc GCC_USB30_PRIM_BCR>; 1857 1858 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, 1859 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1860 interconnect-names = "usb-ddr", "apps-usb"; 1861 1862 usb_1_dwc3: usb@a600000 { 1863 compatible = "snps,dwc3"; 1864 reg = <0 0x0a600000 0 0xcd00>; 1865 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1866 iommus = <&apps_smmu 0x540 0x0>; 1867 snps,dis_u2_susphy_quirk; 1868 snps,dis_enblslpm_quirk; 1869 snps,has-lpm-erratum; 1870 snps,hird-threshold = /bits/ 8 <0x10>; 1871 snps,parkmode-disable-ss-quirk; 1872 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 1873 phy-names = "usb2-phy", "usb3-phy"; 1874 }; 1875 }; 1876 1877 cci0: cci@ac4a000 { 1878 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 1879 reg = <0 0x0ac4a000 0 0x1000>; 1880 interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; 1881 power-domains = <&camcc TITAN_TOP_GDSC>; 1882 1883 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1884 <&camcc CAMCC_SOC_AHB_CLK>, 1885 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 1886 <&camcc CAMCC_CPAS_AHB_CLK>, 1887 <&camcc CAMCC_CCI_0_CLK>, 1888 <&camcc CAMCC_CCI_0_CLK_SRC>; 1889 clock-names = "camnoc_axi", 1890 "soc_ahb", 1891 "slow_ahb_src", 1892 "cpas_ahb", 1893 "cci", 1894 "cci_src"; 1895 1896 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1897 <&camcc CAMCC_CCI_0_CLK>; 1898 assigned-clock-rates = <80000000>, <37500000>; 1899 1900 pinctrl-0 = <&cci0_default &cci1_default>; 1901 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 1902 pinctrl-names = "default", "sleep"; 1903 1904 #address-cells = <1>; 1905 #size-cells = <0>; 1906 1907 status = "disabled"; 1908 1909 cci0_i2c0: i2c-bus@0 { 1910 reg = <0>; 1911 clock-frequency = <1000000>; 1912 #address-cells = <1>; 1913 #size-cells = <0>; 1914 }; 1915 1916 cci0_i2c1: i2c-bus@1 { 1917 reg = <1>; 1918 clock-frequency = <1000000>; 1919 #address-cells = <1>; 1920 #size-cells = <0>; 1921 }; 1922 }; 1923 1924 cci1: cci@ac4b000 { 1925 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 1926 reg = <0 0x0ac4b000 0 0x1000>; 1927 interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; 1928 power-domains = <&camcc TITAN_TOP_GDSC>; 1929 1930 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1931 <&camcc CAMCC_SOC_AHB_CLK>, 1932 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 1933 <&camcc CAMCC_CPAS_AHB_CLK>, 1934 <&camcc CAMCC_CCI_1_CLK>, 1935 <&camcc CAMCC_CCI_1_CLK_SRC>; 1936 clock-names = "camnoc_axi", 1937 "soc_ahb", 1938 "slow_ahb_src", 1939 "cpas_ahb", 1940 "cci", 1941 "cci_src"; 1942 1943 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1944 <&camcc CAMCC_CCI_1_CLK>; 1945 assigned-clock-rates = <80000000>, <37500000>; 1946 1947 pinctrl-0 = <&cci2_default>; 1948 pinctrl-1 = <&cci2_sleep>; 1949 pinctrl-names = "default", "sleep"; 1950 1951 #address-cells = <1>; 1952 #size-cells = <0>; 1953 1954 status = "disabled"; 1955 1956 cci1_i2c0: i2c-bus@0 { 1957 reg = <0>; 1958 clock-frequency = <1000000>; 1959 #address-cells = <1>; 1960 #size-cells = <0>; 1961 }; 1962 1963 /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ 1964 }; 1965 1966 camcc: clock-controller@ad00000 { 1967 compatible = "qcom,sm6350-camcc"; 1968 reg = <0 0x0ad00000 0 0x16000>; 1969 clocks = <&rpmhcc RPMH_CXO_CLK>; 1970 #clock-cells = <1>; 1971 #reset-cells = <1>; 1972 #power-domain-cells = <1>; 1973 }; 1974 1975 mdss: display-subsystem@ae00000 { 1976 compatible = "qcom,sm6350-mdss"; 1977 reg = <0 0x0ae00000 0 0x1000>; 1978 reg-names = "mdss"; 1979 1980 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1981 interrupt-controller; 1982 #interrupt-cells = <1>; 1983 1984 clocks = <&gcc GCC_DISP_AHB_CLK>, 1985 <&gcc GCC_DISP_AXI_CLK>, 1986 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1987 clock-names = "iface", 1988 "bus", 1989 "core"; 1990 1991 power-domains = <&dispcc MDSS_GDSC>; 1992 iommus = <&apps_smmu 0x800 0x2>; 1993 1994 #address-cells = <2>; 1995 #size-cells = <2>; 1996 ranges; 1997 1998 status = "disabled"; 1999 2000 mdss_mdp: display-controller@ae01000 { 2001 compatible = "qcom,sm6350-dpu"; 2002 reg = <0 0x0ae01000 0 0x8f000>, 2003 <0 0x0aeb0000 0 0x2008>; 2004 reg-names = "mdp", "vbif"; 2005 2006 interrupt-parent = <&mdss>; 2007 interrupts = <0>; 2008 2009 clocks = <&gcc GCC_DISP_AXI_CLK>, 2010 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2011 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2012 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2013 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2014 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2015 clock-names = "bus", 2016 "iface", 2017 "rot", 2018 "lut", 2019 "core", 2020 "vsync"; 2021 2022 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2023 assigned-clock-rates = <19200000>; 2024 2025 operating-points-v2 = <&mdp_opp_table>; 2026 power-domains = <&rpmhpd SM6350_CX>; 2027 2028 ports { 2029 #address-cells = <1>; 2030 #size-cells = <0>; 2031 2032 port@0 { 2033 reg = <0>; 2034 2035 dpu_intf1_out: endpoint { 2036 remote-endpoint = <&mdss_dsi0_in>; 2037 }; 2038 }; 2039 }; 2040 2041 mdp_opp_table: opp-table { 2042 compatible = "operating-points-v2"; 2043 2044 opp-19200000 { 2045 opp-hz = /bits/ 64 <19200000>; 2046 required-opps = <&rpmhpd_opp_min_svs>; 2047 }; 2048 2049 opp-200000000 { 2050 opp-hz = /bits/ 64 <200000000>; 2051 required-opps = <&rpmhpd_opp_low_svs>; 2052 }; 2053 2054 opp-300000000 { 2055 opp-hz = /bits/ 64 <300000000>; 2056 required-opps = <&rpmhpd_opp_svs>; 2057 }; 2058 2059 opp-373333333 { 2060 opp-hz = /bits/ 64 <373333333>; 2061 required-opps = <&rpmhpd_opp_svs_l1>; 2062 }; 2063 2064 opp-448000000 { 2065 opp-hz = /bits/ 64 <448000000>; 2066 required-opps = <&rpmhpd_opp_nom>; 2067 }; 2068 2069 opp-560000000 { 2070 opp-hz = /bits/ 64 <560000000>; 2071 required-opps = <&rpmhpd_opp_turbo>; 2072 }; 2073 }; 2074 }; 2075 2076 mdss_dsi0: dsi@ae94000 { 2077 compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2078 reg = <0 0x0ae94000 0 0x400>; 2079 reg-names = "dsi_ctrl"; 2080 2081 interrupt-parent = <&mdss>; 2082 interrupts = <4>; 2083 2084 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2085 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2086 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2087 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2088 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2089 <&gcc GCC_DISP_AXI_CLK>; 2090 clock-names = "byte", 2091 "byte_intf", 2092 "pixel", 2093 "core", 2094 "iface", 2095 "bus"; 2096 2097 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2098 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2099 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 2100 2101 operating-points-v2 = <&mdss_dsi_opp_table>; 2102 power-domains = <&rpmhpd SM6350_MX>; 2103 2104 phys = <&mdss_dsi0_phy>; 2105 phy-names = "dsi"; 2106 2107 #address-cells = <1>; 2108 #size-cells = <0>; 2109 2110 status = "disabled"; 2111 2112 ports { 2113 #address-cells = <1>; 2114 #size-cells = <0>; 2115 2116 port@0 { 2117 reg = <0>; 2118 2119 mdss_dsi0_in: endpoint { 2120 remote-endpoint = <&dpu_intf1_out>; 2121 }; 2122 }; 2123 2124 port@1 { 2125 reg = <1>; 2126 2127 mdss_dsi0_out: endpoint { 2128 }; 2129 }; 2130 }; 2131 2132 mdss_dsi_opp_table: opp-table { 2133 compatible = "operating-points-v2"; 2134 2135 opp-187500000 { 2136 opp-hz = /bits/ 64 <187500000>; 2137 required-opps = <&rpmhpd_opp_low_svs>; 2138 }; 2139 2140 opp-300000000 { 2141 opp-hz = /bits/ 64 <300000000>; 2142 required-opps = <&rpmhpd_opp_svs>; 2143 }; 2144 2145 opp-358000000 { 2146 opp-hz = /bits/ 64 <358000000>; 2147 required-opps = <&rpmhpd_opp_svs_l1>; 2148 }; 2149 }; 2150 }; 2151 2152 mdss_dsi0_phy: phy@ae94400 { 2153 compatible = "qcom,dsi-phy-10nm"; 2154 reg = <0 0x0ae94400 0 0x200>, 2155 <0 0x0ae94600 0 0x280>, 2156 <0 0x0ae94a00 0 0x1e0>; 2157 reg-names = "dsi_phy", 2158 "dsi_phy_lane", 2159 "dsi_pll"; 2160 2161 #clock-cells = <1>; 2162 #phy-cells = <0>; 2163 2164 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2165 <&rpmhcc RPMH_CXO_CLK>; 2166 clock-names = "iface", "ref"; 2167 2168 status = "disabled"; 2169 }; 2170 }; 2171 2172 dispcc: clock-controller@af00000 { 2173 compatible = "qcom,sm6350-dispcc"; 2174 reg = <0 0x0af00000 0 0x20000>; 2175 clocks = <&rpmhcc RPMH_CXO_CLK>, 2176 <&gcc GCC_DISP_GPLL0_CLK>, 2177 <&mdss_dsi0_phy 0>, 2178 <&mdss_dsi0_phy 1>, 2179 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2180 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2181 clock-names = "bi_tcxo", 2182 "gcc_disp_gpll0_clk", 2183 "dsi0_phy_pll_out_byteclk", 2184 "dsi0_phy_pll_out_dsiclk", 2185 "dp_phy_pll_link_clk", 2186 "dp_phy_pll_vco_div_clk"; 2187 #clock-cells = <1>; 2188 #reset-cells = <1>; 2189 #power-domain-cells = <1>; 2190 }; 2191 2192 pdc: interrupt-controller@b220000 { 2193 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 2194 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; 2195 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2196 <125 63 1>, <126 655 12>, <138 139 15>; 2197 #interrupt-cells = <2>; 2198 interrupt-parent = <&intc>; 2199 interrupt-controller; 2200 }; 2201 2202 tsens0: thermal-sensor@c263000 { 2203 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 2204 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2205 <0 0x0c222000 0 0x8>; /* SROT */ 2206 #qcom,sensors = <16>; 2207 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2208 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2209 interrupt-names = "uplow", "critical"; 2210 #thermal-sensor-cells = <1>; 2211 }; 2212 2213 tsens1: thermal-sensor@c265000 { 2214 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 2215 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2216 <0 0x0c223000 0 0x8>; /* SROT */ 2217 #qcom,sensors = <16>; 2218 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2219 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2220 interrupt-names = "uplow", "critical"; 2221 #thermal-sensor-cells = <1>; 2222 }; 2223 2224 aoss_qmp: power-management@c300000 { 2225 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 2226 reg = <0 0x0c300000 0 0x1000>; 2227 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2228 IRQ_TYPE_EDGE_RISING>; 2229 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2230 2231 #clock-cells = <0>; 2232 }; 2233 2234 spmi_bus: spmi@c440000 { 2235 compatible = "qcom,spmi-pmic-arb"; 2236 reg = <0 0x0c440000 0 0x1100>, 2237 <0 0x0c600000 0 0x2000000>, 2238 <0 0x0e600000 0 0x100000>, 2239 <0 0x0e700000 0 0xa0000>, 2240 <0 0x0c40a000 0 0x26000>; 2241 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2242 interrupt-names = "periph_irq"; 2243 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2244 qcom,ee = <0>; 2245 qcom,channel = <0>; 2246 #address-cells = <2>; 2247 #size-cells = <0>; 2248 interrupt-controller; 2249 #interrupt-cells = <4>; 2250 }; 2251 2252 tlmm: pinctrl@f100000 { 2253 compatible = "qcom,sm6350-tlmm"; 2254 reg = <0 0x0f100000 0 0x300000>; 2255 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 2256 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 2257 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 2258 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 2259 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 2260 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 2261 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 2262 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 2263 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 2264 gpio-controller; 2265 #gpio-cells = <2>; 2266 interrupt-controller; 2267 #interrupt-cells = <2>; 2268 gpio-ranges = <&tlmm 0 0 157>; 2269 wakeup-parent = <&pdc>; 2270 2271 cci0_default: cci0-default-state { 2272 pins = "gpio39", "gpio40"; 2273 function = "cci_i2c"; 2274 drive-strength = <2>; 2275 bias-pull-up; 2276 }; 2277 2278 cci0_sleep: cci0-sleep-state { 2279 pins = "gpio39", "gpio40"; 2280 function = "cci_i2c"; 2281 drive-strength = <2>; 2282 bias-pull-down; 2283 }; 2284 2285 cci1_default: cci1-default-state { 2286 pins = "gpio41", "gpio42"; 2287 function = "cci_i2c"; 2288 drive-strength = <2>; 2289 bias-pull-up; 2290 }; 2291 2292 cci1_sleep: cci1-sleep-state { 2293 pins = "gpio41", "gpio42"; 2294 function = "cci_i2c"; 2295 drive-strength = <2>; 2296 bias-pull-down; 2297 }; 2298 2299 cci2_default: cci2-default-state { 2300 pins = "gpio43", "gpio44"; 2301 function = "cci_i2c"; 2302 drive-strength = <2>; 2303 bias-pull-up; 2304 }; 2305 2306 cci2_sleep: cci2-sleep-state { 2307 pins = "gpio43", "gpio44"; 2308 function = "cci_i2c"; 2309 drive-strength = <2>; 2310 bias-pull-down; 2311 }; 2312 2313 sdc2_off_state: sdc2-off-state { 2314 clk-pins { 2315 pins = "sdc2_clk"; 2316 drive-strength = <2>; 2317 bias-disable; 2318 }; 2319 2320 cmd-pins { 2321 pins = "sdc2_cmd"; 2322 drive-strength = <2>; 2323 bias-pull-up; 2324 }; 2325 2326 data-pins { 2327 pins = "sdc2_data"; 2328 drive-strength = <2>; 2329 bias-pull-up; 2330 }; 2331 }; 2332 2333 sdc2_on_state: sdc2-on-state { 2334 clk-pins { 2335 pins = "sdc2_clk"; 2336 drive-strength = <16>; 2337 bias-disable; 2338 }; 2339 2340 cmd-pins { 2341 pins = "sdc2_cmd"; 2342 drive-strength = <10>; 2343 bias-pull-up; 2344 }; 2345 2346 data-pins { 2347 pins = "sdc2_data"; 2348 drive-strength = <10>; 2349 bias-pull-up; 2350 }; 2351 }; 2352 2353 qup_uart9_default: qup-uart9-default-state { 2354 pins = "gpio25", "gpio26"; 2355 function = "qup13_f2"; 2356 drive-strength = <2>; 2357 bias-disable; 2358 }; 2359 2360 qup_i2c0_default: qup-i2c0-default-state { 2361 pins = "gpio0", "gpio1"; 2362 function = "qup00"; 2363 drive-strength = <2>; 2364 bias-pull-up; 2365 }; 2366 2367 qup_i2c2_default: qup-i2c2-default-state { 2368 pins = "gpio45", "gpio46"; 2369 function = "qup02"; 2370 drive-strength = <2>; 2371 bias-pull-up; 2372 }; 2373 2374 qup_i2c6_default: qup-i2c6-default-state { 2375 pins = "gpio13", "gpio14"; 2376 function = "qup10"; 2377 drive-strength = <2>; 2378 bias-pull-up; 2379 }; 2380 2381 qup_i2c7_default: qup-i2c7-default-state { 2382 pins = "gpio27", "gpio28"; 2383 function = "qup11"; 2384 drive-strength = <2>; 2385 bias-pull-up; 2386 }; 2387 2388 qup_i2c8_default: qup-i2c8-default-state { 2389 pins = "gpio19", "gpio20"; 2390 function = "qup12"; 2391 drive-strength = <2>; 2392 bias-pull-up; 2393 }; 2394 2395 qup_i2c10_default: qup-i2c10-default-state { 2396 pins = "gpio4", "gpio5"; 2397 function = "qup14"; 2398 drive-strength = <2>; 2399 bias-pull-up; 2400 }; 2401 2402 qup_uart1_cts: qup-uart1-cts-default-state { 2403 pins = "gpio61"; 2404 function = "qup01"; 2405 drive-strength = <2>; 2406 bias-disable; 2407 }; 2408 2409 qup_uart1_rts: qup-uart1-rts-default-state { 2410 pins = "gpio62"; 2411 function = "qup01"; 2412 drive-strength = <2>; 2413 bias-pull-down; 2414 }; 2415 2416 qup_uart1_rx: qup-uart1-rx-default-state { 2417 pins = "gpio64"; 2418 function = "qup01"; 2419 drive-strength = <2>; 2420 bias-disable; 2421 }; 2422 2423 qup_uart1_tx: qup-uart1-tx-default-state { 2424 pins = "gpio63"; 2425 function = "qup01"; 2426 drive-strength = <2>; 2427 bias-pull-up; 2428 }; 2429 }; 2430 2431 apps_smmu: iommu@15000000 { 2432 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 2433 reg = <0 0x15000000 0 0x100000>; 2434 #iommu-cells = <2>; 2435 #global-interrupts = <1>; 2436 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2437 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2438 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2439 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2440 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2441 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2442 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2443 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2444 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2445 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2446 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2447 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2448 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2449 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2450 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2451 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2452 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2453 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2454 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2455 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2456 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2457 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2458 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2459 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2460 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2461 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2462 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2463 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2464 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2465 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2466 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2467 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2468 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2469 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2470 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2471 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2472 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2473 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2474 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2475 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2478 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2479 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2480 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2481 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2482 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2483 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2484 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2485 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2486 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2487 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2488 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2489 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2490 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2491 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2492 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2493 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2494 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2495 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2496 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2497 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2498 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2499 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2500 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2501 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2502 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2503 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2504 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2505 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2506 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2507 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2508 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2509 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2510 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2511 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2512 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2513 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 2514 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 2515 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2516 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 2517 }; 2518 2519 intc: interrupt-controller@17a00000 { 2520 compatible = "arm,gic-v3"; 2521 #interrupt-cells = <3>; 2522 interrupt-controller; 2523 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 2524 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 2525 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 2526 }; 2527 2528 watchdog@17c10000 { 2529 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 2530 reg = <0 0x17c10000 0 0x1000>; 2531 clocks = <&sleep_clk>; 2532 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 2533 }; 2534 2535 timer@17c20000 { 2536 compatible = "arm,armv7-timer-mem"; 2537 reg = <0x0 0x17c20000 0x0 0x1000>; 2538 clock-frequency = <19200000>; 2539 #address-cells = <1>; 2540 #size-cells = <1>; 2541 ranges = <0 0 0 0x20000000>; 2542 2543 frame@17c21000 { 2544 frame-number = <0>; 2545 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2546 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2547 reg = <0x17c21000 0x1000>, 2548 <0x17c22000 0x1000>; 2549 }; 2550 2551 frame@17c23000 { 2552 frame-number = <1>; 2553 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2554 reg = <0x17c23000 0x1000>; 2555 status = "disabled"; 2556 }; 2557 2558 frame@17c25000 { 2559 frame-number = <2>; 2560 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2561 reg = <0x17c25000 0x1000>; 2562 status = "disabled"; 2563 }; 2564 2565 frame@17c27000 { 2566 frame-number = <3>; 2567 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2568 reg = <0x17c27000 0x1000>; 2569 status = "disabled"; 2570 }; 2571 2572 frame@17c29000 { 2573 frame-number = <4>; 2574 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2575 reg = <0x17c29000 0x1000>; 2576 status = "disabled"; 2577 }; 2578 2579 frame@17c2b000 { 2580 frame-number = <5>; 2581 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2582 reg = <0x17c2b000 0x1000>; 2583 status = "disabled"; 2584 }; 2585 2586 frame@17c2d000 { 2587 frame-number = <6>; 2588 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2589 reg = <0x17c2d000 0x1000>; 2590 status = "disabled"; 2591 }; 2592 }; 2593 2594 apps_rsc: rsc@18200000 { 2595 compatible = "qcom,rpmh-rsc"; 2596 label = "apps_rsc"; 2597 reg = <0x0 0x18200000 0x0 0x10000>, 2598 <0x0 0x18210000 0x0 0x10000>, 2599 <0x0 0x18220000 0x0 0x10000>; 2600 reg-names = "drv-0", "drv-1", "drv-2"; 2601 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2602 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2603 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2604 qcom,tcs-offset = <0xd00>; 2605 qcom,drv-id = <2>; 2606 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 2607 <WAKE_TCS 3>, <CONTROL_TCS 1>; 2608 power-domains = <&CLUSTER_PD>; 2609 2610 rpmhcc: clock-controller { 2611 compatible = "qcom,sm6350-rpmh-clk"; 2612 #clock-cells = <1>; 2613 clock-names = "xo"; 2614 clocks = <&xo_board>; 2615 }; 2616 2617 rpmhpd: power-controller { 2618 compatible = "qcom,sm6350-rpmhpd"; 2619 #power-domain-cells = <1>; 2620 operating-points-v2 = <&rpmhpd_opp_table>; 2621 2622 rpmhpd_opp_table: opp-table { 2623 compatible = "operating-points-v2"; 2624 2625 rpmhpd_opp_ret: opp1 { 2626 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2627 }; 2628 2629 rpmhpd_opp_min_svs: opp2 { 2630 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2631 }; 2632 2633 rpmhpd_opp_low_svs: opp3 { 2634 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2635 }; 2636 2637 rpmhpd_opp_svs: opp4 { 2638 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2639 }; 2640 2641 rpmhpd_opp_svs_l1: opp5 { 2642 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2643 }; 2644 2645 rpmhpd_opp_nom: opp6 { 2646 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2647 }; 2648 2649 rpmhpd_opp_nom_l1: opp7 { 2650 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2651 }; 2652 2653 rpmhpd_opp_nom_l2: opp8 { 2654 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2655 }; 2656 2657 rpmhpd_opp_turbo: opp9 { 2658 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2659 }; 2660 2661 rpmhpd_opp_turbo_l1: opp10 { 2662 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2663 }; 2664 }; 2665 }; 2666 2667 apps_bcm_voter: bcm-voter { 2668 compatible = "qcom,bcm-voter"; 2669 }; 2670 }; 2671 2672 osm_l3: interconnect@18321000 { 2673 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3"; 2674 reg = <0x0 0x18321000 0x0 0x1000>; 2675 2676 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2677 clock-names = "xo", "alternate"; 2678 2679 #interconnect-cells = <1>; 2680 }; 2681 2682 cpufreq_hw: cpufreq@18323000 { 2683 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw"; 2684 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; 2685 reg-names = "freq-domain0", "freq-domain1"; 2686 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2687 clock-names = "xo", "alternate"; 2688 2689 #freq-domain-cells = <1>; 2690 #clock-cells = <1>; 2691 }; 2692 2693 wifi: wifi@18800000 { 2694 compatible = "qcom,wcn3990-wifi"; 2695 reg = <0 0x18800000 0 0x800000>; 2696 reg-names = "membase"; 2697 memory-region = <&wlan_fw_mem>; 2698 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2699 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2700 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2701 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2702 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2703 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2704 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2705 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2706 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2707 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2708 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2709 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2710 iommus = <&apps_smmu 0x20 0x1>; 2711 qcom,msa-fixed-perm; 2712 status = "disabled"; 2713 }; 2714 }; 2715 2716 timer { 2717 compatible = "arm,armv8-timer"; 2718 clock-frequency = <19200000>; 2719 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2720 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2721 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2722 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2723 }; 2724}; 2725