1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sm6350.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/dma/qcom-gpi.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interconnect/qcom,icc.h> 12#include <dt-bindings/interconnect/qcom,osm-l3.h> 13#include <dt-bindings/interconnect/qcom,sm6350.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <76800000>; 29 clock-output-names = "xo_board"; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 clock-frequency = <32764>; 35 #clock-cells = <0>; 36 }; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 CPU0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "qcom,kryo560"; 46 reg = <0x0 0x0>; 47 enable-method = "psci"; 48 capacity-dmips-mhz = <1024>; 49 dynamic-power-coefficient = <100>; 50 next-level-cache = <&L2_0>; 51 qcom,freq-domain = <&cpufreq_hw 0>; 52 operating-points-v2 = <&cpu0_opp_table>; 53 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 54 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 55 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 56 #cooling-cells = <2>; 57 L2_0: l2-cache { 58 compatible = "cache"; 59 cache-level = <2>; 60 next-level-cache = <&L3_0>; 61 L3_0: l3-cache { 62 compatible = "cache"; 63 cache-level = <3>; 64 }; 65 }; 66 }; 67 68 CPU1: cpu@100 { 69 device_type = "cpu"; 70 compatible = "qcom,kryo560"; 71 reg = <0x0 0x100>; 72 enable-method = "psci"; 73 capacity-dmips-mhz = <1024>; 74 dynamic-power-coefficient = <100>; 75 next-level-cache = <&L2_100>; 76 qcom,freq-domain = <&cpufreq_hw 0>; 77 operating-points-v2 = <&cpu0_opp_table>; 78 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 79 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 80 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 81 #cooling-cells = <2>; 82 L2_100: l2-cache { 83 compatible = "cache"; 84 cache-level = <2>; 85 next-level-cache = <&L3_0>; 86 }; 87 }; 88 89 CPU2: cpu@200 { 90 device_type = "cpu"; 91 compatible = "qcom,kryo560"; 92 reg = <0x0 0x200>; 93 enable-method = "psci"; 94 capacity-dmips-mhz = <1024>; 95 dynamic-power-coefficient = <100>; 96 next-level-cache = <&L2_200>; 97 qcom,freq-domain = <&cpufreq_hw 0>; 98 operating-points-v2 = <&cpu0_opp_table>; 99 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 100 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 101 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 102 #cooling-cells = <2>; 103 L2_200: l2-cache { 104 compatible = "cache"; 105 cache-level = <2>; 106 next-level-cache = <&L3_0>; 107 }; 108 }; 109 110 CPU3: cpu@300 { 111 device_type = "cpu"; 112 compatible = "qcom,kryo560"; 113 reg = <0x0 0x300>; 114 enable-method = "psci"; 115 capacity-dmips-mhz = <1024>; 116 dynamic-power-coefficient = <100>; 117 next-level-cache = <&L2_300>; 118 qcom,freq-domain = <&cpufreq_hw 0>; 119 operating-points-v2 = <&cpu0_opp_table>; 120 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 121 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 122 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 123 #cooling-cells = <2>; 124 L2_300: l2-cache { 125 compatible = "cache"; 126 cache-level = <2>; 127 next-level-cache = <&L3_0>; 128 }; 129 }; 130 131 CPU4: cpu@400 { 132 device_type = "cpu"; 133 compatible = "qcom,kryo560"; 134 reg = <0x0 0x400>; 135 enable-method = "psci"; 136 capacity-dmips-mhz = <1024>; 137 dynamic-power-coefficient = <100>; 138 next-level-cache = <&L2_400>; 139 qcom,freq-domain = <&cpufreq_hw 0>; 140 operating-points-v2 = <&cpu0_opp_table>; 141 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 142 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 143 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 144 #cooling-cells = <2>; 145 L2_400: l2-cache { 146 compatible = "cache"; 147 cache-level = <2>; 148 next-level-cache = <&L3_0>; 149 }; 150 }; 151 152 CPU5: cpu@500 { 153 device_type = "cpu"; 154 compatible = "qcom,kryo560"; 155 reg = <0x0 0x500>; 156 enable-method = "psci"; 157 capacity-dmips-mhz = <1024>; 158 dynamic-power-coefficient = <100>; 159 next-level-cache = <&L2_500>; 160 qcom,freq-domain = <&cpufreq_hw 0>; 161 operating-points-v2 = <&cpu0_opp_table>; 162 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 163 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 164 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 165 #cooling-cells = <2>; 166 L2_500: l2-cache { 167 compatible = "cache"; 168 cache-level = <2>; 169 next-level-cache = <&L3_0>; 170 }; 171 172 }; 173 174 CPU6: cpu@600 { 175 device_type = "cpu"; 176 compatible = "qcom,kryo560"; 177 reg = <0x0 0x600>; 178 enable-method = "psci"; 179 capacity-dmips-mhz = <1894>; 180 dynamic-power-coefficient = <703>; 181 next-level-cache = <&L2_600>; 182 qcom,freq-domain = <&cpufreq_hw 1>; 183 operating-points-v2 = <&cpu6_opp_table>; 184 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 185 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 186 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 187 #cooling-cells = <2>; 188 L2_600: l2-cache { 189 compatible = "cache"; 190 cache-level = <2>; 191 next-level-cache = <&L3_0>; 192 }; 193 }; 194 195 CPU7: cpu@700 { 196 device_type = "cpu"; 197 compatible = "qcom,kryo560"; 198 reg = <0x0 0x700>; 199 enable-method = "psci"; 200 capacity-dmips-mhz = <1894>; 201 dynamic-power-coefficient = <703>; 202 next-level-cache = <&L2_700>; 203 qcom,freq-domain = <&cpufreq_hw 1>; 204 operating-points-v2 = <&cpu6_opp_table>; 205 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 206 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 207 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 208 #cooling-cells = <2>; 209 L2_700: l2-cache { 210 compatible = "cache"; 211 cache-level = <2>; 212 next-level-cache = <&L3_0>; 213 }; 214 }; 215 216 cpu-map { 217 cluster0 { 218 core0 { 219 cpu = <&CPU0>; 220 }; 221 222 core1 { 223 cpu = <&CPU1>; 224 }; 225 226 core2 { 227 cpu = <&CPU2>; 228 }; 229 230 core3 { 231 cpu = <&CPU3>; 232 }; 233 234 core4 { 235 cpu = <&CPU4>; 236 }; 237 238 core5 { 239 cpu = <&CPU5>; 240 }; 241 242 core6 { 243 cpu = <&CPU6>; 244 }; 245 246 core7 { 247 cpu = <&CPU7>; 248 }; 249 }; 250 }; 251 }; 252 253 firmware { 254 scm: scm { 255 compatible = "qcom,scm-sm6350", "qcom,scm"; 256 #reset-cells = <1>; 257 }; 258 }; 259 260 memory@80000000 { 261 device_type = "memory"; 262 /* We expect the bootloader to fill in the size */ 263 reg = <0x0 0x80000000 0x0 0x0>; 264 }; 265 266 cpu0_opp_table: opp-table-cpu0 { 267 compatible = "operating-points-v2"; 268 opp-shared; 269 270 opp-300000000 { 271 opp-hz = /bits/ 64 <300000000>; 272 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ 273 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 274 }; 275 276 opp-576000000 { 277 opp-hz = /bits/ 64 <576000000>; 278 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>; 279 }; 280 281 opp-768000000 { 282 opp-hz = /bits/ 64 <768000000>; 283 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 284 }; 285 286 opp-1017600000 { 287 opp-hz = /bits/ 64 <1017600000>; 288 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 289 }; 290 291 opp-1248000000 { 292 opp-hz = /bits/ 64 <1248000000>; 293 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 294 }; 295 296 opp-1324800000 { 297 opp-hz = /bits/ 64 <1324800000>; 298 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>; 299 }; 300 301 opp-1516800000 { 302 opp-hz = /bits/ 64 <1516800000>; 303 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 304 }; 305 306 opp-1612800000 { 307 opp-hz = /bits/ 64 <1612800000>; 308 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 309 }; 310 311 opp-1708800000 { 312 opp-hz = /bits/ 64 <1708800000>; 313 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 314 }; 315 }; 316 317 cpu6_opp_table: opp-table-cpu6 { 318 compatible = "operating-points-v2"; 319 opp-shared; 320 321 opp-300000000 { 322 opp-hz = /bits/ 64 <300000000>; 323 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 324 }; 325 326 opp-787200000 { 327 opp-hz = /bits/ 64 <787200000>; 328 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 329 }; 330 331 opp-979200000 { 332 opp-hz = /bits/ 64 <979200000>; 333 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>; 334 }; 335 336 opp-1036800000 { 337 opp-hz = /bits/ 64 <1036800000>; 338 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 339 }; 340 341 opp-1248000000 { 342 opp-hz = /bits/ 64 <1248000000>; 343 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 344 }; 345 346 opp-1401600000 { 347 opp-hz = /bits/ 64 <1401600000>; 348 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>; 349 }; 350 351 opp-1555200000 { 352 opp-hz = /bits/ 64 <1555200000>; 353 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 354 }; 355 356 opp-1766400000 { 357 opp-hz = /bits/ 64 <1766400000>; 358 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 359 }; 360 361 opp-1900800000 { 362 opp-hz = /bits/ 64 <1900800000>; 363 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 364 }; 365 366 opp-2073600000 { 367 opp-hz = /bits/ 64 <2073600000>; 368 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 369 }; 370 }; 371 372 pmu { 373 compatible = "arm,armv8-pmuv3"; 374 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 375 }; 376 377 psci { 378 compatible = "arm,psci-1.0"; 379 method = "smc"; 380 }; 381 382 reserved_memory: reserved-memory { 383 #address-cells = <2>; 384 #size-cells = <2>; 385 ranges; 386 387 hyp_mem: memory@80000000 { 388 reg = <0 0x80000000 0 0x600000>; 389 no-map; 390 }; 391 392 xbl_aop_mem: memory@80700000 { 393 reg = <0 0x80700000 0 0x160000>; 394 no-map; 395 }; 396 397 cmd_db: memory@80860000 { 398 compatible = "qcom,cmd-db"; 399 reg = <0 0x80860000 0 0x20000>; 400 no-map; 401 }; 402 403 sec_apps_mem: memory@808ff000 { 404 reg = <0 0x808ff000 0 0x1000>; 405 no-map; 406 }; 407 408 smem_mem: memory@80900000 { 409 reg = <0 0x80900000 0 0x200000>; 410 no-map; 411 }; 412 413 cdsp_sec_mem: memory@80b00000 { 414 reg = <0 0x80b00000 0 0x1e00000>; 415 no-map; 416 }; 417 418 pil_camera_mem: memory@86000000 { 419 reg = <0 0x86000000 0 0x500000>; 420 no-map; 421 }; 422 423 pil_npu_mem: memory@86500000 { 424 reg = <0 0x86500000 0 0x500000>; 425 no-map; 426 }; 427 428 pil_video_mem: memory@86a00000 { 429 reg = <0 0x86a00000 0 0x500000>; 430 no-map; 431 }; 432 433 pil_cdsp_mem: memory@86f00000 { 434 reg = <0 0x86f00000 0 0x1e00000>; 435 no-map; 436 }; 437 438 pil_adsp_mem: memory@88d00000 { 439 reg = <0 0x88d00000 0 0x2800000>; 440 no-map; 441 }; 442 443 wlan_fw_mem: memory@8b500000 { 444 reg = <0 0x8b500000 0 0x200000>; 445 no-map; 446 }; 447 448 pil_ipa_fw_mem: memory@8b700000 { 449 reg = <0 0x8b700000 0 0x10000>; 450 no-map; 451 }; 452 453 pil_ipa_gsi_mem: memory@8b710000 { 454 reg = <0 0x8b710000 0 0x5400>; 455 no-map; 456 }; 457 458 pil_gpu_mem: memory@8b715400 { 459 reg = <0 0x8b715400 0 0x2000>; 460 no-map; 461 }; 462 463 pil_modem_mem: memory@8b800000 { 464 reg = <0 0x8b800000 0 0xf800000>; 465 no-map; 466 }; 467 468 cont_splash_memory: memory@a0000000 { 469 reg = <0 0xa0000000 0 0x2300000>; 470 no-map; 471 }; 472 473 dfps_data_memory: memory@a2300000 { 474 reg = <0 0xa2300000 0 0x100000>; 475 no-map; 476 }; 477 478 removed_region: memory@c0000000 { 479 reg = <0 0xc0000000 0 0x3900000>; 480 no-map; 481 }; 482 483 debug_region: memory@ffb00000 { 484 reg = <0 0xffb00000 0 0xc0000>; 485 no-map; 486 }; 487 488 last_log_region: memory@ffbc0000 { 489 reg = <0 0xffbc0000 0 0x40000>; 490 no-map; 491 }; 492 493 ramoops: ramoops@ffc00000 { 494 compatible = "ramoops"; 495 reg = <0 0xffc00000 0 0x100000>; 496 record-size = <0x1000>; 497 console-size = <0x40000>; 498 msg-size = <0x20000 0x20000>; 499 ecc-size = <16>; 500 no-map; 501 }; 502 503 cmdline_region: memory@ffd00000 { 504 reg = <0 0xffd00000 0 0x1000>; 505 no-map; 506 }; 507 }; 508 509 smem { 510 compatible = "qcom,smem"; 511 memory-region = <&smem_mem>; 512 hwlocks = <&tcsr_mutex 3>; 513 }; 514 515 smp2p-adsp { 516 compatible = "qcom,smp2p"; 517 qcom,smem = <443>, <429>; 518 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 519 IPCC_MPROC_SIGNAL_SMP2P 520 IRQ_TYPE_EDGE_RISING>; 521 mboxes = <&ipcc IPCC_CLIENT_LPASS 522 IPCC_MPROC_SIGNAL_SMP2P>; 523 524 qcom,local-pid = <0>; 525 qcom,remote-pid = <2>; 526 527 smp2p_adsp_out: master-kernel { 528 qcom,entry-name = "master-kernel"; 529 #qcom,smem-state-cells = <1>; 530 }; 531 532 smp2p_adsp_in: slave-kernel { 533 qcom,entry-name = "slave-kernel"; 534 interrupt-controller; 535 #interrupt-cells = <2>; 536 }; 537 }; 538 539 smp2p-cdsp { 540 compatible = "qcom,smp2p"; 541 qcom,smem = <94>, <432>; 542 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 543 IPCC_MPROC_SIGNAL_SMP2P 544 IRQ_TYPE_EDGE_RISING>; 545 mboxes = <&ipcc IPCC_CLIENT_CDSP 546 IPCC_MPROC_SIGNAL_SMP2P>; 547 548 qcom,local-pid = <0>; 549 qcom,remote-pid = <5>; 550 551 smp2p_cdsp_out: master-kernel { 552 qcom,entry-name = "master-kernel"; 553 #qcom,smem-state-cells = <1>; 554 }; 555 556 smp2p_cdsp_in: slave-kernel { 557 qcom,entry-name = "slave-kernel"; 558 interrupt-controller; 559 #interrupt-cells = <2>; 560 }; 561 }; 562 563 smp2p-mpss { 564 compatible = "qcom,smp2p"; 565 qcom,smem = <435>, <428>; 566 567 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 568 IPCC_MPROC_SIGNAL_SMP2P 569 IRQ_TYPE_EDGE_RISING>; 570 mboxes = <&ipcc IPCC_CLIENT_MPSS 571 IPCC_MPROC_SIGNAL_SMP2P>; 572 573 qcom,local-pid = <0>; 574 qcom,remote-pid = <1>; 575 576 modem_smp2p_out: master-kernel { 577 qcom,entry-name = "master-kernel"; 578 #qcom,smem-state-cells = <1>; 579 }; 580 581 modem_smp2p_in: slave-kernel { 582 qcom,entry-name = "slave-kernel"; 583 interrupt-controller; 584 #interrupt-cells = <2>; 585 }; 586 587 ipa_smp2p_out: ipa-ap-to-modem { 588 qcom,entry-name = "ipa"; 589 #qcom,smem-state-cells = <1>; 590 }; 591 592 ipa_smp2p_in: ipa-modem-to-ap { 593 qcom,entry-name = "ipa"; 594 interrupt-controller; 595 #interrupt-cells = <2>; 596 }; 597 }; 598 599 soc: soc@0 { 600 #address-cells = <2>; 601 #size-cells = <2>; 602 ranges = <0 0 0 0 0x10 0>; 603 dma-ranges = <0 0 0 0 0x10 0>; 604 compatible = "simple-bus"; 605 606 gcc: clock-controller@100000 { 607 compatible = "qcom,gcc-sm6350"; 608 reg = <0 0x00100000 0 0x1f0000>; 609 #clock-cells = <1>; 610 #reset-cells = <1>; 611 #power-domain-cells = <1>; 612 clock-names = "bi_tcxo", 613 "bi_tcxo_ao", 614 "sleep_clk"; 615 clocks = <&rpmhcc RPMH_CXO_CLK>, 616 <&rpmhcc RPMH_CXO_CLK_A>, 617 <&sleep_clk>; 618 }; 619 620 ipcc: mailbox@408000 { 621 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 622 reg = <0 0x00408000 0 0x1000>; 623 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 624 interrupt-controller; 625 #interrupt-cells = <3>; 626 #mbox-cells = <2>; 627 }; 628 629 rng: rng@793000 { 630 compatible = "qcom,prng-ee"; 631 reg = <0 0x00793000 0 0x1000>; 632 clocks = <&gcc GCC_PRNG_AHB_CLK>; 633 clock-names = "core"; 634 }; 635 636 sdhc_1: mmc@7c4000 { 637 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 638 reg = <0 0x007c4000 0 0x1000>, 639 <0 0x007c5000 0 0x1000>, 640 <0 0x007c8000 0 0x8000>; 641 reg-names = "hc", "cqhci", "ice"; 642 643 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 645 interrupt-names = "hc_irq", "pwr_irq"; 646 iommus = <&apps_smmu 0x60 0x0>; 647 648 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 649 <&gcc GCC_SDCC1_APPS_CLK>, 650 <&rpmhcc RPMH_CXO_CLK>; 651 clock-names = "iface", "core", "xo"; 652 resets = <&gcc GCC_SDCC1_BCR>; 653 qcom,dll-config = <0x000f642c>; 654 qcom,ddr-config = <0x80040868>; 655 power-domains = <&rpmhpd SM6350_CX>; 656 operating-points-v2 = <&sdhc1_opp_table>; 657 bus-width = <8>; 658 non-removable; 659 supports-cqe; 660 661 status = "disabled"; 662 663 sdhc1_opp_table: opp-table { 664 compatible = "operating-points-v2"; 665 666 opp-19200000 { 667 opp-hz = /bits/ 64 <19200000>; 668 required-opps = <&rpmhpd_opp_min_svs>; 669 }; 670 671 opp-100000000 { 672 opp-hz = /bits/ 64 <100000000>; 673 required-opps = <&rpmhpd_opp_low_svs>; 674 }; 675 676 opp-384000000 { 677 opp-hz = /bits/ 64 <384000000>; 678 required-opps = <&rpmhpd_opp_svs_l1>; 679 }; 680 }; 681 }; 682 683 gpi_dma0: dma-controller@800000 { 684 compatible = "qcom,sm6350-gpi-dma"; 685 reg = <0 0x00800000 0 0x60000>; 686 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 696 dma-channels = <10>; 697 dma-channel-mask = <0x1f>; 698 iommus = <&apps_smmu 0x56 0x0>; 699 #dma-cells = <3>; 700 status = "disabled"; 701 }; 702 703 qupv3_id_0: geniqup@8c0000 { 704 compatible = "qcom,geni-se-qup"; 705 reg = <0x0 0x008c0000 0x0 0x2000>; 706 clock-names = "m-ahb", "s-ahb"; 707 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 708 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 709 #address-cells = <2>; 710 #size-cells = <2>; 711 iommus = <&apps_smmu 0x43 0x0>; 712 ranges; 713 status = "disabled"; 714 715 i2c0: i2c@880000 { 716 compatible = "qcom,geni-i2c"; 717 reg = <0 0x00880000 0 0x4000>; 718 clock-names = "se"; 719 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 720 pinctrl-names = "default"; 721 pinctrl-0 = <&qup_i2c0_default>; 722 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 723 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 724 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 725 dma-names = "tx", "rx"; 726 #address-cells = <1>; 727 #size-cells = <0>; 728 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 729 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 730 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 731 interconnect-names = "qup-core", "qup-config", "qup-memory"; 732 status = "disabled"; 733 }; 734 735 i2c2: i2c@888000 { 736 compatible = "qcom,geni-i2c"; 737 reg = <0 0x00888000 0 0x4000>; 738 clock-names = "se"; 739 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 740 pinctrl-names = "default"; 741 pinctrl-0 = <&qup_i2c2_default>; 742 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 743 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 744 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 745 dma-names = "tx", "rx"; 746 #address-cells = <1>; 747 #size-cells = <0>; 748 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 749 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 750 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 751 interconnect-names = "qup-core", "qup-config", "qup-memory"; 752 status = "disabled"; 753 }; 754 }; 755 756 gpi_dma1: dma-controller@900000 { 757 compatible = "qcom,sm6350-gpi-dma"; 758 reg = <0 0x00900000 0 0x60000>; 759 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 769 dma-channels = <10>; 770 dma-channel-mask = <0x3f>; 771 iommus = <&apps_smmu 0x4d6 0x0>; 772 #dma-cells = <3>; 773 status = "disabled"; 774 }; 775 776 qupv3_id_1: geniqup@9c0000 { 777 compatible = "qcom,geni-se-qup"; 778 reg = <0x0 0x009c0000 0x0 0x2000>; 779 clock-names = "m-ahb", "s-ahb"; 780 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 781 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 782 #address-cells = <2>; 783 #size-cells = <2>; 784 iommus = <&apps_smmu 0x4c3 0x0>; 785 ranges; 786 status = "disabled"; 787 788 i2c6: i2c@980000 { 789 compatible = "qcom,geni-i2c"; 790 reg = <0 0x00980000 0 0x4000>; 791 clock-names = "se"; 792 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 793 pinctrl-names = "default"; 794 pinctrl-0 = <&qup_i2c6_default>; 795 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 796 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 797 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 798 dma-names = "tx", "rx"; 799 #address-cells = <1>; 800 #size-cells = <0>; 801 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 802 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 803 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 804 interconnect-names = "qup-core", "qup-config", "qup-memory"; 805 status = "disabled"; 806 }; 807 808 i2c7: i2c@984000 { 809 compatible = "qcom,geni-i2c"; 810 reg = <0 0x00984000 0 0x4000>; 811 clock-names = "se"; 812 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 813 pinctrl-names = "default"; 814 pinctrl-0 = <&qup_i2c7_default>; 815 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 816 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 817 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 818 dma-names = "tx", "rx"; 819 #address-cells = <1>; 820 #size-cells = <0>; 821 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 822 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 823 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 824 interconnect-names = "qup-core", "qup-config", "qup-memory"; 825 status = "disabled"; 826 }; 827 828 i2c8: i2c@988000 { 829 compatible = "qcom,geni-i2c"; 830 reg = <0 0x00988000 0 0x4000>; 831 clock-names = "se"; 832 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 833 pinctrl-names = "default"; 834 pinctrl-0 = <&qup_i2c8_default>; 835 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 836 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 837 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 838 dma-names = "tx", "rx"; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 842 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 843 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 844 interconnect-names = "qup-core", "qup-config", "qup-memory"; 845 status = "disabled"; 846 }; 847 848 uart9: serial@98c000 { 849 compatible = "qcom,geni-debug-uart"; 850 reg = <0 0x0098c000 0 0x4000>; 851 clock-names = "se"; 852 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 853 pinctrl-names = "default"; 854 pinctrl-0 = <&qup_uart9_default>; 855 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 856 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 857 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 858 interconnect-names = "qup-core", "qup-config"; 859 status = "disabled"; 860 }; 861 862 i2c10: i2c@990000 { 863 compatible = "qcom,geni-i2c"; 864 reg = <0 0x00990000 0 0x4000>; 865 clock-names = "se"; 866 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 867 pinctrl-names = "default"; 868 pinctrl-0 = <&qup_i2c10_default>; 869 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 870 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 871 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 872 dma-names = "tx", "rx"; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 876 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 877 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 878 interconnect-names = "qup-core", "qup-config", "qup-memory"; 879 status = "disabled"; 880 }; 881 882 }; 883 884 config_noc: interconnect@1500000 { 885 compatible = "qcom,sm6350-config-noc"; 886 reg = <0 0x01500000 0 0x28000>; 887 #interconnect-cells = <2>; 888 qcom,bcm-voters = <&apps_bcm_voter>; 889 }; 890 891 system_noc: interconnect@1620000 { 892 compatible = "qcom,sm6350-system-noc"; 893 reg = <0 0x01620000 0 0x17080>; 894 #interconnect-cells = <2>; 895 qcom,bcm-voters = <&apps_bcm_voter>; 896 897 clk_virt: interconnect-clk-virt { 898 compatible = "qcom,sm6350-clk-virt"; 899 #interconnect-cells = <2>; 900 qcom,bcm-voters = <&apps_bcm_voter>; 901 }; 902 }; 903 904 aggre1_noc: interconnect@16e0000 { 905 compatible = "qcom,sm6350-aggre1-noc"; 906 reg = <0 0x016e0000 0 0x15080>; 907 #interconnect-cells = <2>; 908 qcom,bcm-voters = <&apps_bcm_voter>; 909 }; 910 911 aggre2_noc: interconnect@1700000 { 912 compatible = "qcom,sm6350-aggre2-noc"; 913 reg = <0 0x01700000 0 0x1f880>; 914 #interconnect-cells = <2>; 915 qcom,bcm-voters = <&apps_bcm_voter>; 916 917 compute_noc: interconnect-compute-noc { 918 compatible = "qcom,sm6350-compute-noc"; 919 #interconnect-cells = <2>; 920 qcom,bcm-voters = <&apps_bcm_voter>; 921 }; 922 }; 923 924 mmss_noc: interconnect@1740000 { 925 compatible = "qcom,sm6350-mmss-noc"; 926 reg = <0 0x01740000 0 0x1c100>; 927 #interconnect-cells = <2>; 928 qcom,bcm-voters = <&apps_bcm_voter>; 929 }; 930 931 ufs_mem_hc: ufs@1d84000 { 932 compatible = "qcom,sm6350-ufshc", "qcom,ufshc", 933 "jedec,ufs-2.0"; 934 reg = <0 0x01d84000 0 0x3000>, 935 <0 0x01d90000 0 0x8000>; 936 reg-names = "std", "ice"; 937 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 938 phys = <&ufs_mem_phy_lanes>; 939 phy-names = "ufsphy"; 940 lanes-per-direction = <2>; 941 #reset-cells = <1>; 942 resets = <&gcc GCC_UFS_PHY_BCR>; 943 reset-names = "rst"; 944 945 power-domains = <&gcc UFS_PHY_GDSC>; 946 947 iommus = <&apps_smmu 0x80 0x0>; 948 949 clock-names = "core_clk", 950 "bus_aggr_clk", 951 "iface_clk", 952 "core_clk_unipro", 953 "ref_clk", 954 "tx_lane0_sync_clk", 955 "rx_lane0_sync_clk", 956 "rx_lane1_sync_clk", 957 "ice_core_clk"; 958 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 959 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 960 <&gcc GCC_UFS_PHY_AHB_CLK>, 961 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 962 <&rpmhcc RPMH_QLINK_CLK>, 963 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 964 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 965 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 966 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 967 freq-table-hz = 968 <50000000 200000000>, 969 <0 0>, 970 <0 0>, 971 <37500000 150000000>, 972 <75000000 300000000>, 973 <0 0>, 974 <0 0>, 975 <0 0>, 976 <0 0>; 977 978 status = "disabled"; 979 }; 980 981 ufs_mem_phy: phy@1d87000 { 982 compatible = "qcom,sm6350-qmp-ufs-phy"; 983 reg = <0 0x01d87000 0 0x18c>; 984 #address-cells = <2>; 985 #size-cells = <2>; 986 ranges; 987 988 clock-names = "ref", 989 "ref_aux"; 990 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 991 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 992 993 resets = <&ufs_mem_hc 0>; 994 reset-names = "ufsphy"; 995 996 status = "disabled"; 997 998 ufs_mem_phy_lanes: phy@1d87400 { 999 reg = <0 0x01d87400 0 0x128>, 1000 <0 0x01d87600 0 0x1fc>, 1001 <0 0x01d87c00 0 0x1dc>, 1002 <0 0x01d87800 0 0x128>, 1003 <0 0x01d87a00 0 0x1fc>; 1004 #phy-cells = <0>; 1005 }; 1006 }; 1007 1008 ipa: ipa@1e40000 { 1009 compatible = "qcom,sm6350-ipa"; 1010 1011 iommus = <&apps_smmu 0x440 0x0>, 1012 <&apps_smmu 0x442 0x0>; 1013 reg = <0 0x01e40000 0 0x8000>, 1014 <0 0x01e50000 0 0x3000>, 1015 <0 0x01e04000 0 0x23000>; 1016 reg-names = "ipa-reg", 1017 "ipa-shared", 1018 "gsi"; 1019 1020 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1021 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1022 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1023 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1024 interrupt-names = "ipa", 1025 "gsi", 1026 "ipa-clock-query", 1027 "ipa-setup-ready"; 1028 1029 clocks = <&rpmhcc RPMH_IPA_CLK>; 1030 clock-names = "core"; 1031 1032 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>, 1033 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, 1034 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; 1035 interconnect-names = "memory", "imem", "config"; 1036 1037 qcom,smem-states = <&ipa_smp2p_out 0>, 1038 <&ipa_smp2p_out 1>; 1039 qcom,smem-state-names = "ipa-clock-enabled-valid", 1040 "ipa-clock-enabled"; 1041 1042 status = "disabled"; 1043 }; 1044 1045 tcsr_mutex: hwlock@1f40000 { 1046 compatible = "qcom,tcsr-mutex"; 1047 reg = <0x0 0x01f40000 0x0 0x40000>; 1048 #hwlock-cells = <1>; 1049 }; 1050 1051 adsp: remoteproc@3000000 { 1052 compatible = "qcom,sm6350-adsp-pas"; 1053 reg = <0 0x03000000 0 0x100>; 1054 1055 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 1056 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1057 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1058 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1059 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1060 interrupt-names = "wdog", "fatal", "ready", 1061 "handover", "stop-ack"; 1062 1063 clocks = <&rpmhcc RPMH_CXO_CLK>; 1064 clock-names = "xo"; 1065 1066 power-domains = <&rpmhpd SM6350_LCX>, 1067 <&rpmhpd SM6350_LMX>; 1068 power-domain-names = "lcx", "lmx"; 1069 1070 memory-region = <&pil_adsp_mem>; 1071 1072 qcom,qmp = <&aoss_qmp>; 1073 1074 qcom,smem-states = <&smp2p_adsp_out 0>; 1075 qcom,smem-state-names = "stop"; 1076 1077 status = "disabled"; 1078 1079 glink-edge { 1080 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1081 IPCC_MPROC_SIGNAL_GLINK_QMP 1082 IRQ_TYPE_EDGE_RISING>; 1083 mboxes = <&ipcc IPCC_CLIENT_LPASS 1084 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1085 1086 label = "lpass"; 1087 qcom,remote-pid = <2>; 1088 1089 fastrpc { 1090 compatible = "qcom,fastrpc"; 1091 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1092 label = "adsp"; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 1096 compute-cb@3 { 1097 compatible = "qcom,fastrpc-compute-cb"; 1098 reg = <3>; 1099 iommus = <&apps_smmu 0x1003 0x0>; 1100 }; 1101 1102 compute-cb@4 { 1103 compatible = "qcom,fastrpc-compute-cb"; 1104 reg = <4>; 1105 iommus = <&apps_smmu 0x1004 0x0>; 1106 }; 1107 1108 compute-cb@5 { 1109 compatible = "qcom,fastrpc-compute-cb"; 1110 reg = <5>; 1111 iommus = <&apps_smmu 0x1005 0x0>; 1112 qcom,nsessions = <5>; 1113 }; 1114 }; 1115 }; 1116 }; 1117 1118 mpss: remoteproc@4080000 { 1119 compatible = "qcom,sm6350-mpss-pas"; 1120 reg = <0x0 0x04080000 0x0 0x4040>; 1121 1122 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 1123 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1124 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1125 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1126 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1127 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1128 interrupt-names = "wdog", "fatal", "ready", "handover", 1129 "stop-ack", "shutdown-ack"; 1130 1131 clocks = <&rpmhcc RPMH_CXO_CLK>; 1132 clock-names = "xo"; 1133 1134 power-domains = <&rpmhpd SM6350_CX>, 1135 <&rpmhpd SM6350_MSS>; 1136 power-domain-names = "cx", "mss"; 1137 1138 memory-region = <&pil_modem_mem>; 1139 1140 qcom,qmp = <&aoss_qmp>; 1141 1142 qcom,smem-states = <&modem_smp2p_out 0>; 1143 qcom,smem-state-names = "stop"; 1144 1145 status = "disabled"; 1146 1147 glink-edge { 1148 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1149 IPCC_MPROC_SIGNAL_GLINK_QMP 1150 IRQ_TYPE_EDGE_RISING>; 1151 mboxes = <&ipcc IPCC_CLIENT_MPSS 1152 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1153 label = "modem"; 1154 qcom,remote-pid = <1>; 1155 }; 1156 }; 1157 1158 cdsp: remoteproc@8300000 { 1159 compatible = "qcom,sm6350-cdsp-pas"; 1160 reg = <0 0x08300000 0 0x10000>; 1161 1162 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 1163 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1164 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1165 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1166 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1167 interrupt-names = "wdog", "fatal", "ready", 1168 "handover", "stop-ack"; 1169 1170 clocks = <&rpmhcc RPMH_CXO_CLK>; 1171 clock-names = "xo"; 1172 1173 power-domains = <&rpmhpd SM6350_CX>, 1174 <&rpmhpd SM6350_MX>; 1175 power-domain-names = "cx", "mx"; 1176 1177 memory-region = <&pil_cdsp_mem>; 1178 1179 qcom,qmp = <&aoss_qmp>; 1180 1181 qcom,smem-states = <&smp2p_cdsp_out 0>; 1182 qcom,smem-state-names = "stop"; 1183 1184 status = "disabled"; 1185 1186 glink-edge { 1187 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1188 IPCC_MPROC_SIGNAL_GLINK_QMP 1189 IRQ_TYPE_EDGE_RISING>; 1190 mboxes = <&ipcc IPCC_CLIENT_CDSP 1191 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1192 1193 label = "cdsp"; 1194 qcom,remote-pid = <5>; 1195 1196 fastrpc { 1197 compatible = "qcom,fastrpc"; 1198 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1199 label = "cdsp"; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 1203 compute-cb@1 { 1204 compatible = "qcom,fastrpc-compute-cb"; 1205 reg = <1>; 1206 iommus = <&apps_smmu 0x1401 0x20>; 1207 }; 1208 1209 compute-cb@2 { 1210 compatible = "qcom,fastrpc-compute-cb"; 1211 reg = <2>; 1212 iommus = <&apps_smmu 0x1402 0x20>; 1213 }; 1214 1215 compute-cb@3 { 1216 compatible = "qcom,fastrpc-compute-cb"; 1217 reg = <3>; 1218 iommus = <&apps_smmu 0x1403 0x20>; 1219 }; 1220 1221 compute-cb@4 { 1222 compatible = "qcom,fastrpc-compute-cb"; 1223 reg = <4>; 1224 iommus = <&apps_smmu 0x1404 0x20>; 1225 }; 1226 1227 compute-cb@5 { 1228 compatible = "qcom,fastrpc-compute-cb"; 1229 reg = <5>; 1230 iommus = <&apps_smmu 0x1405 0x20>; 1231 }; 1232 1233 compute-cb@6 { 1234 compatible = "qcom,fastrpc-compute-cb"; 1235 reg = <6>; 1236 iommus = <&apps_smmu 0x1406 0x20>; 1237 }; 1238 1239 compute-cb@7 { 1240 compatible = "qcom,fastrpc-compute-cb"; 1241 reg = <7>; 1242 iommus = <&apps_smmu 0x1407 0x20>; 1243 }; 1244 1245 compute-cb@8 { 1246 compatible = "qcom,fastrpc-compute-cb"; 1247 reg = <8>; 1248 iommus = <&apps_smmu 0x1408 0x20>; 1249 }; 1250 1251 /* note: secure cb9 in downstream */ 1252 }; 1253 }; 1254 }; 1255 1256 sdhc_2: mmc@8804000 { 1257 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 1258 reg = <0 0x08804000 0 0x1000>; 1259 1260 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1261 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1262 interrupt-names = "hc_irq", "pwr_irq"; 1263 iommus = <&apps_smmu 0x560 0x0>; 1264 1265 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1266 <&gcc GCC_SDCC2_APPS_CLK>, 1267 <&rpmhcc RPMH_CXO_CLK>; 1268 clock-names = "iface", "core", "xo"; 1269 resets = <&gcc GCC_SDCC2_BCR>; 1270 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, 1271 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; 1272 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1273 1274 pinctrl-0 = <&sdc2_on_state>; 1275 pinctrl-1 = <&sdc2_off_state>; 1276 pinctrl-names = "default", "sleep"; 1277 1278 qcom,dll-config = <0x0007642c>; 1279 qcom,ddr-config = <0x80040868>; 1280 power-domains = <&rpmhpd SM6350_CX>; 1281 operating-points-v2 = <&sdhc2_opp_table>; 1282 bus-width = <4>; 1283 1284 status = "disabled"; 1285 1286 sdhc2_opp_table: opp-table { 1287 compatible = "operating-points-v2"; 1288 1289 opp-100000000 { 1290 opp-hz = /bits/ 64 <100000000>; 1291 required-opps = <&rpmhpd_opp_svs_l1>; 1292 opp-peak-kBps = <790000 131000>; 1293 opp-avg-kBps = <50000 50000>; 1294 }; 1295 1296 opp-202000000 { 1297 opp-hz = /bits/ 64 <202000000>; 1298 required-opps = <&rpmhpd_opp_nom>; 1299 opp-peak-kBps = <3190000 294000>; 1300 opp-avg-kBps = <261438 300000>; 1301 }; 1302 }; 1303 }; 1304 1305 usb_1_hsphy: phy@88e3000 { 1306 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 1307 reg = <0 0x088e3000 0 0x400>; 1308 status = "disabled"; 1309 #phy-cells = <0>; 1310 1311 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 1312 clock-names = "cfg_ahb", "ref"; 1313 1314 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1315 }; 1316 1317 usb_1_qmpphy: phy@88e9000 { 1318 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 1319 reg = <0 0x088e9000 0 0x200>, 1320 <0 0x088e8000 0 0x40>, 1321 <0 0x088ea000 0 0x200>; 1322 status = "disabled"; 1323 #address-cells = <2>; 1324 #size-cells = <2>; 1325 ranges; 1326 1327 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1328 <&xo_board>, 1329 <&rpmhcc RPMH_QLINK_CLK>, 1330 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1331 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 1332 1333 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1334 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1335 reset-names = "phy", "common"; 1336 1337 usb_1_ssphy: usb3-phy@88e9200 { 1338 reg = <0 0x088e9200 0 0x200>, 1339 <0 0x088e9400 0 0x200>, 1340 <0 0x088e9c00 0 0x400>, 1341 <0 0x088e9600 0 0x200>, 1342 <0 0x088e9800 0 0x200>, 1343 <0 0x088e9a00 0 0x100>; 1344 #clock-cells = <0>; 1345 #phy-cells = <0>; 1346 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1347 clock-names = "pipe0"; 1348 clock-output-names = "usb3_phy_pipe_clk_src"; 1349 }; 1350 1351 dp_phy: dp-phy@88ea200 { 1352 reg = <0 0x088ea200 0 0x200>, 1353 <0 0x088ea400 0 0x200>, 1354 <0 0x088eaa00 0 0x200>, 1355 <0 0x088ea600 0 0x200>, 1356 <0 0x088ea800 0 0x200>; 1357 #phy-cells = <0>; 1358 #clock-cells = <1>; 1359 }; 1360 }; 1361 1362 dc_noc: interconnect@9160000 { 1363 compatible = "qcom,sm6350-dc-noc"; 1364 reg = <0 0x09160000 0 0x3200>; 1365 #interconnect-cells = <2>; 1366 qcom,bcm-voters = <&apps_bcm_voter>; 1367 }; 1368 1369 system-cache-controller@9200000 { 1370 compatible = "qcom,sm6350-llcc"; 1371 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 1372 reg-names = "llcc_base", "llcc_broadcast_base"; 1373 }; 1374 1375 gem_noc: interconnect@9680000 { 1376 compatible = "qcom,sm6350-gem-noc"; 1377 reg = <0 0x09680000 0 0x3e200>; 1378 #interconnect-cells = <2>; 1379 qcom,bcm-voters = <&apps_bcm_voter>; 1380 }; 1381 1382 npu_noc: interconnect@9990000 { 1383 compatible = "qcom,sm6350-npu-noc"; 1384 reg = <0 0x09990000 0 0x1600>; 1385 #interconnect-cells = <2>; 1386 qcom,bcm-voters = <&apps_bcm_voter>; 1387 }; 1388 1389 usb_1: usb@a6f8800 { 1390 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 1391 reg = <0 0x0a6f8800 0 0x400>; 1392 status = "disabled"; 1393 #address-cells = <2>; 1394 #size-cells = <2>; 1395 ranges; 1396 1397 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1398 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1399 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1400 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1401 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1402 clock-names = "cfg_noc", 1403 "core", 1404 "iface", 1405 "sleep", 1406 "mock_utmi"; 1407 1408 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1409 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 1410 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1411 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 1412 1413 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1414 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1415 1416 power-domains = <&gcc USB30_PRIM_GDSC>; 1417 1418 resets = <&gcc GCC_USB30_PRIM_BCR>; 1419 1420 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, 1421 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1422 interconnect-names = "usb-ddr", "apps-usb"; 1423 1424 usb_1_dwc3: usb@a600000 { 1425 compatible = "snps,dwc3"; 1426 reg = <0 0x0a600000 0 0xcd00>; 1427 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1428 iommus = <&apps_smmu 0x540 0x0>; 1429 snps,dis_u2_susphy_quirk; 1430 snps,dis_enblslpm_quirk; 1431 snps,has-lpm-erratum; 1432 snps,hird-threshold = /bits/ 8 <0x10>; 1433 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1434 phy-names = "usb2-phy", "usb3-phy"; 1435 }; 1436 }; 1437 1438 pdc: interrupt-controller@b220000 { 1439 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 1440 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; 1441 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 1442 <125 63 1>, <126 655 12>, <138 139 15>; 1443 #interrupt-cells = <2>; 1444 interrupt-parent = <&intc>; 1445 interrupt-controller; 1446 }; 1447 1448 tsens0: thermal-sensor@c263000 { 1449 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1450 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1451 <0 0x0c222000 0 0x8>; /* SROT */ 1452 #qcom,sensors = <16>; 1453 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 1454 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 1455 interrupt-names = "uplow", "critical"; 1456 #thermal-sensor-cells = <1>; 1457 }; 1458 1459 tsens1: thermal-sensor@c265000 { 1460 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1461 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1462 <0 0x0c223000 0 0x8>; /* SROT */ 1463 #qcom,sensors = <16>; 1464 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 1465 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 1466 interrupt-names = "uplow", "critical"; 1467 #thermal-sensor-cells = <1>; 1468 }; 1469 1470 aoss_qmp: power-management@c300000 { 1471 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 1472 reg = <0 0x0c300000 0 0x1000>; 1473 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 1474 IRQ_TYPE_EDGE_RISING>; 1475 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 1476 1477 #clock-cells = <0>; 1478 }; 1479 1480 spmi_bus: spmi@c440000 { 1481 compatible = "qcom,spmi-pmic-arb"; 1482 reg = <0 0x0c440000 0 0x1100>, 1483 <0 0x0c600000 0 0x2000000>, 1484 <0 0x0e600000 0 0x100000>, 1485 <0 0x0e700000 0 0xa0000>, 1486 <0 0x0c40a000 0 0x26000>; 1487 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1488 interrupt-names = "periph_irq"; 1489 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1490 qcom,ee = <0>; 1491 qcom,channel = <0>; 1492 #address-cells = <2>; 1493 #size-cells = <0>; 1494 interrupt-controller; 1495 #interrupt-cells = <4>; 1496 }; 1497 1498 tlmm: pinctrl@f100000 { 1499 compatible = "qcom,sm6350-tlmm"; 1500 reg = <0 0x0f100000 0 0x300000>; 1501 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 1510 gpio-controller; 1511 #gpio-cells = <2>; 1512 interrupt-controller; 1513 #interrupt-cells = <2>; 1514 gpio-ranges = <&tlmm 0 0 157>; 1515 1516 sdc2_off_state: sdc2-off-state { 1517 clk-pins { 1518 pins = "sdc2_clk"; 1519 drive-strength = <2>; 1520 bias-disable; 1521 }; 1522 1523 cmd-pins { 1524 pins = "sdc2_cmd"; 1525 drive-strength = <2>; 1526 bias-pull-up; 1527 }; 1528 1529 data-pins { 1530 pins = "sdc2_data"; 1531 drive-strength = <2>; 1532 bias-pull-up; 1533 }; 1534 }; 1535 1536 sdc2_on_state: sdc2-on-state { 1537 clk-pins { 1538 pins = "sdc2_clk"; 1539 drive-strength = <16>; 1540 bias-disable; 1541 }; 1542 1543 cmd-pins { 1544 pins = "sdc2_cmd"; 1545 drive-strength = <10>; 1546 bias-pull-up; 1547 }; 1548 1549 data-pins { 1550 pins = "sdc2_data"; 1551 drive-strength = <10>; 1552 bias-pull-up; 1553 }; 1554 }; 1555 1556 qup_uart9_default: qup-uart9-default-state { 1557 pins = "gpio25", "gpio26"; 1558 function = "qup13_f2"; 1559 drive-strength = <2>; 1560 bias-disable; 1561 }; 1562 1563 qup_i2c0_default: qup-i2c0-default-state { 1564 pins = "gpio0", "gpio1"; 1565 function = "qup00"; 1566 drive-strength = <2>; 1567 bias-pull-up; 1568 }; 1569 1570 qup_i2c2_default: qup-i2c2-default-state { 1571 pins = "gpio45", "gpio46"; 1572 function = "qup02"; 1573 drive-strength = <2>; 1574 bias-pull-up; 1575 }; 1576 1577 qup_i2c6_default: qup-i2c6-default-state { 1578 pins = "gpio13", "gpio14"; 1579 function = "qup10"; 1580 drive-strength = <2>; 1581 bias-pull-up; 1582 }; 1583 1584 qup_i2c7_default: qup-i2c7-default-state { 1585 pins = "gpio27", "gpio28"; 1586 function = "qup11"; 1587 drive-strength = <2>; 1588 bias-pull-up; 1589 }; 1590 1591 qup_i2c8_default: qup-i2c8-default-state { 1592 pins = "gpio19", "gpio20"; 1593 function = "qup12"; 1594 drive-strength = <2>; 1595 bias-pull-up; 1596 }; 1597 1598 qup_i2c10_default: qup-i2c10-default-state { 1599 pins = "gpio4", "gpio5"; 1600 function = "qup14"; 1601 drive-strength = <2>; 1602 bias-pull-up; 1603 }; 1604 }; 1605 1606 apps_smmu: iommu@15000000 { 1607 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 1608 reg = <0 0x15000000 0 0x100000>; 1609 #iommu-cells = <2>; 1610 #global-interrupts = <1>; 1611 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1675 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1676 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1677 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1683 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1692 }; 1693 1694 intc: interrupt-controller@17a00000 { 1695 compatible = "arm,gic-v3"; 1696 #interrupt-cells = <3>; 1697 interrupt-controller; 1698 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 1699 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 1700 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 1701 }; 1702 1703 watchdog@17c10000 { 1704 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 1705 reg = <0 0x17c10000 0 0x1000>; 1706 clocks = <&sleep_clk>; 1707 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1708 }; 1709 1710 timer@17c20000 { 1711 compatible = "arm,armv7-timer-mem"; 1712 reg = <0x0 0x17c20000 0x0 0x1000>; 1713 clock-frequency = <19200000>; 1714 #address-cells = <1>; 1715 #size-cells = <1>; 1716 ranges = <0 0 0 0x20000000>; 1717 1718 frame@17c21000 { 1719 frame-number = <0>; 1720 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1722 reg = <0x17c21000 0x1000>, 1723 <0x17c22000 0x1000>; 1724 }; 1725 1726 frame@17c23000 { 1727 frame-number = <1>; 1728 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1729 reg = <0x17c23000 0x1000>; 1730 status = "disabled"; 1731 }; 1732 1733 frame@17c25000 { 1734 frame-number = <2>; 1735 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1736 reg = <0x17c25000 0x1000>; 1737 status = "disabled"; 1738 }; 1739 1740 frame@17c27000 { 1741 frame-number = <3>; 1742 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1743 reg = <0x17c27000 0x1000>; 1744 status = "disabled"; 1745 }; 1746 1747 frame@17c29000 { 1748 frame-number = <4>; 1749 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1750 reg = <0x17c29000 0x1000>; 1751 status = "disabled"; 1752 }; 1753 1754 frame@17c2b000 { 1755 frame-number = <5>; 1756 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1757 reg = <0x17c2b000 0x1000>; 1758 status = "disabled"; 1759 }; 1760 1761 frame@17c2d000 { 1762 frame-number = <6>; 1763 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1764 reg = <0x17c2d000 0x1000>; 1765 status = "disabled"; 1766 }; 1767 }; 1768 1769 wifi: wifi@18800000 { 1770 compatible = "qcom,wcn3990-wifi"; 1771 reg = <0 0x18800000 0 0x800000>; 1772 reg-names = "membase"; 1773 memory-region = <&wlan_fw_mem>; 1774 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 1786 iommus = <&apps_smmu 0x20 0x1>; 1787 qcom,msa-fixed-perm; 1788 status = "disabled"; 1789 }; 1790 1791 apps_rsc: rsc@18200000 { 1792 compatible = "qcom,rpmh-rsc"; 1793 label = "apps_rsc"; 1794 reg = <0x0 0x18200000 0x0 0x10000>, 1795 <0x0 0x18210000 0x0 0x10000>, 1796 <0x0 0x18220000 0x0 0x10000>; 1797 reg-names = "drv-0", "drv-1", "drv-2"; 1798 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1801 qcom,tcs-offset = <0xd00>; 1802 qcom,drv-id = <2>; 1803 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 1804 <WAKE_TCS 3>, <CONTROL_TCS 1>; 1805 1806 rpmhcc: clock-controller { 1807 compatible = "qcom,sm6350-rpmh-clk"; 1808 #clock-cells = <1>; 1809 clock-names = "xo"; 1810 clocks = <&xo_board>; 1811 }; 1812 1813 rpmhpd: power-controller { 1814 compatible = "qcom,sm6350-rpmhpd"; 1815 #power-domain-cells = <1>; 1816 operating-points-v2 = <&rpmhpd_opp_table>; 1817 1818 rpmhpd_opp_table: opp-table { 1819 compatible = "operating-points-v2"; 1820 1821 rpmhpd_opp_ret: opp1 { 1822 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1823 }; 1824 1825 rpmhpd_opp_min_svs: opp2 { 1826 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1827 }; 1828 1829 rpmhpd_opp_low_svs: opp3 { 1830 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1831 }; 1832 1833 rpmhpd_opp_svs: opp4 { 1834 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1835 }; 1836 1837 rpmhpd_opp_svs_l1: opp5 { 1838 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1839 }; 1840 1841 rpmhpd_opp_nom: opp6 { 1842 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1843 }; 1844 1845 rpmhpd_opp_nom_l1: opp7 { 1846 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1847 }; 1848 1849 rpmhpd_opp_nom_l2: opp8 { 1850 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1851 }; 1852 1853 rpmhpd_opp_turbo: opp9 { 1854 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1855 }; 1856 1857 rpmhpd_opp_turbo_l1: opp10 { 1858 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1859 }; 1860 }; 1861 }; 1862 1863 apps_bcm_voter: bcm-voter { 1864 compatible = "qcom,bcm-voter"; 1865 }; 1866 }; 1867 1868 osm_l3: interconnect@18321000 { 1869 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3"; 1870 reg = <0x0 0x18321000 0x0 0x1000>; 1871 1872 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 1873 clock-names = "xo", "alternate"; 1874 1875 #interconnect-cells = <1>; 1876 }; 1877 1878 cpufreq_hw: cpufreq@18323000 { 1879 compatible = "qcom,cpufreq-hw"; 1880 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; 1881 reg-names = "freq-domain0", "freq-domain1"; 1882 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 1883 clock-names = "xo", "alternate"; 1884 1885 #freq-domain-cells = <1>; 1886 }; 1887 }; 1888 1889 timer { 1890 compatible = "arm,armv8-timer"; 1891 clock-frequency = <19200000>; 1892 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1893 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1894 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1895 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1896 }; 1897}; 1898