1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sm6350.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm6350-camcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interconnect/qcom,icc.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sm6350.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <76800000>; 31 clock-output-names = "xo_board"; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 clock-frequency = <32764>; 37 #clock-cells = <0>; 38 }; 39 }; 40 41 cpus { 42 #address-cells = <2>; 43 #size-cells = <0>; 44 45 CPU0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "qcom,kryo560"; 48 reg = <0x0 0x0>; 49 clocks = <&cpufreq_hw 0>; 50 enable-method = "psci"; 51 capacity-dmips-mhz = <1024>; 52 dynamic-power-coefficient = <100>; 53 next-level-cache = <&L2_0>; 54 qcom,freq-domain = <&cpufreq_hw 0>; 55 operating-points-v2 = <&cpu0_opp_table>; 56 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 57 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 58 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 59 #cooling-cells = <2>; 60 L2_0: l2-cache { 61 compatible = "cache"; 62 cache-level = <2>; 63 next-level-cache = <&L3_0>; 64 L3_0: l3-cache { 65 compatible = "cache"; 66 cache-level = <3>; 67 }; 68 }; 69 }; 70 71 CPU1: cpu@100 { 72 device_type = "cpu"; 73 compatible = "qcom,kryo560"; 74 reg = <0x0 0x100>; 75 clocks = <&cpufreq_hw 0>; 76 enable-method = "psci"; 77 capacity-dmips-mhz = <1024>; 78 dynamic-power-coefficient = <100>; 79 next-level-cache = <&L2_100>; 80 qcom,freq-domain = <&cpufreq_hw 0>; 81 operating-points-v2 = <&cpu0_opp_table>; 82 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 83 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 84 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 85 #cooling-cells = <2>; 86 L2_100: l2-cache { 87 compatible = "cache"; 88 cache-level = <2>; 89 next-level-cache = <&L3_0>; 90 }; 91 }; 92 93 CPU2: cpu@200 { 94 device_type = "cpu"; 95 compatible = "qcom,kryo560"; 96 reg = <0x0 0x200>; 97 clocks = <&cpufreq_hw 0>; 98 enable-method = "psci"; 99 capacity-dmips-mhz = <1024>; 100 dynamic-power-coefficient = <100>; 101 next-level-cache = <&L2_200>; 102 qcom,freq-domain = <&cpufreq_hw 0>; 103 operating-points-v2 = <&cpu0_opp_table>; 104 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 105 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 106 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 107 #cooling-cells = <2>; 108 L2_200: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 next-level-cache = <&L3_0>; 112 }; 113 }; 114 115 CPU3: cpu@300 { 116 device_type = "cpu"; 117 compatible = "qcom,kryo560"; 118 reg = <0x0 0x300>; 119 clocks = <&cpufreq_hw 0>; 120 enable-method = "psci"; 121 capacity-dmips-mhz = <1024>; 122 dynamic-power-coefficient = <100>; 123 next-level-cache = <&L2_300>; 124 qcom,freq-domain = <&cpufreq_hw 0>; 125 operating-points-v2 = <&cpu0_opp_table>; 126 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 127 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 128 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 129 #cooling-cells = <2>; 130 L2_300: l2-cache { 131 compatible = "cache"; 132 cache-level = <2>; 133 next-level-cache = <&L3_0>; 134 }; 135 }; 136 137 CPU4: cpu@400 { 138 device_type = "cpu"; 139 compatible = "qcom,kryo560"; 140 reg = <0x0 0x400>; 141 clocks = <&cpufreq_hw 0>; 142 enable-method = "psci"; 143 capacity-dmips-mhz = <1024>; 144 dynamic-power-coefficient = <100>; 145 next-level-cache = <&L2_400>; 146 qcom,freq-domain = <&cpufreq_hw 0>; 147 operating-points-v2 = <&cpu0_opp_table>; 148 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 149 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 150 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 151 #cooling-cells = <2>; 152 L2_400: l2-cache { 153 compatible = "cache"; 154 cache-level = <2>; 155 next-level-cache = <&L3_0>; 156 }; 157 }; 158 159 CPU5: cpu@500 { 160 device_type = "cpu"; 161 compatible = "qcom,kryo560"; 162 reg = <0x0 0x500>; 163 clocks = <&cpufreq_hw 0>; 164 enable-method = "psci"; 165 capacity-dmips-mhz = <1024>; 166 dynamic-power-coefficient = <100>; 167 next-level-cache = <&L2_500>; 168 qcom,freq-domain = <&cpufreq_hw 0>; 169 operating-points-v2 = <&cpu0_opp_table>; 170 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 171 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 172 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 173 #cooling-cells = <2>; 174 L2_500: l2-cache { 175 compatible = "cache"; 176 cache-level = <2>; 177 next-level-cache = <&L3_0>; 178 }; 179 }; 180 181 CPU6: cpu@600 { 182 device_type = "cpu"; 183 compatible = "qcom,kryo560"; 184 reg = <0x0 0x600>; 185 clocks = <&cpufreq_hw 1>; 186 enable-method = "psci"; 187 capacity-dmips-mhz = <1894>; 188 dynamic-power-coefficient = <703>; 189 next-level-cache = <&L2_600>; 190 qcom,freq-domain = <&cpufreq_hw 1>; 191 operating-points-v2 = <&cpu6_opp_table>; 192 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 193 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 194 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 195 #cooling-cells = <2>; 196 L2_600: l2-cache { 197 compatible = "cache"; 198 cache-level = <2>; 199 next-level-cache = <&L3_0>; 200 }; 201 }; 202 203 CPU7: cpu@700 { 204 device_type = "cpu"; 205 compatible = "qcom,kryo560"; 206 reg = <0x0 0x700>; 207 clocks = <&cpufreq_hw 1>; 208 enable-method = "psci"; 209 capacity-dmips-mhz = <1894>; 210 dynamic-power-coefficient = <703>; 211 next-level-cache = <&L2_700>; 212 qcom,freq-domain = <&cpufreq_hw 1>; 213 operating-points-v2 = <&cpu6_opp_table>; 214 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 215 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 216 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 217 #cooling-cells = <2>; 218 L2_700: l2-cache { 219 compatible = "cache"; 220 cache-level = <2>; 221 next-level-cache = <&L3_0>; 222 }; 223 }; 224 225 cpu-map { 226 cluster0 { 227 core0 { 228 cpu = <&CPU0>; 229 }; 230 231 core1 { 232 cpu = <&CPU1>; 233 }; 234 235 core2 { 236 cpu = <&CPU2>; 237 }; 238 239 core3 { 240 cpu = <&CPU3>; 241 }; 242 243 core4 { 244 cpu = <&CPU4>; 245 }; 246 247 core5 { 248 cpu = <&CPU5>; 249 }; 250 251 core6 { 252 cpu = <&CPU6>; 253 }; 254 255 core7 { 256 cpu = <&CPU7>; 257 }; 258 }; 259 }; 260 }; 261 262 firmware { 263 scm: scm { 264 compatible = "qcom,scm-sm6350", "qcom,scm"; 265 #reset-cells = <1>; 266 }; 267 }; 268 269 memory@80000000 { 270 device_type = "memory"; 271 /* We expect the bootloader to fill in the size */ 272 reg = <0x0 0x80000000 0x0 0x0>; 273 }; 274 275 cpu0_opp_table: opp-table-cpu0 { 276 compatible = "operating-points-v2"; 277 opp-shared; 278 279 opp-300000000 { 280 opp-hz = /bits/ 64 <300000000>; 281 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ 282 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 283 }; 284 285 opp-576000000 { 286 opp-hz = /bits/ 64 <576000000>; 287 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>; 288 }; 289 290 opp-768000000 { 291 opp-hz = /bits/ 64 <768000000>; 292 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 293 }; 294 295 opp-1017600000 { 296 opp-hz = /bits/ 64 <1017600000>; 297 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 298 }; 299 300 opp-1248000000 { 301 opp-hz = /bits/ 64 <1248000000>; 302 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 303 }; 304 305 opp-1324800000 { 306 opp-hz = /bits/ 64 <1324800000>; 307 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>; 308 }; 309 310 opp-1516800000 { 311 opp-hz = /bits/ 64 <1516800000>; 312 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 313 }; 314 315 opp-1612800000 { 316 opp-hz = /bits/ 64 <1612800000>; 317 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 318 }; 319 320 opp-1708800000 { 321 opp-hz = /bits/ 64 <1708800000>; 322 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 323 }; 324 }; 325 326 cpu6_opp_table: opp-table-cpu6 { 327 compatible = "operating-points-v2"; 328 opp-shared; 329 330 opp-300000000 { 331 opp-hz = /bits/ 64 <300000000>; 332 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 333 }; 334 335 opp-787200000 { 336 opp-hz = /bits/ 64 <787200000>; 337 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 338 }; 339 340 opp-979200000 { 341 opp-hz = /bits/ 64 <979200000>; 342 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>; 343 }; 344 345 opp-1036800000 { 346 opp-hz = /bits/ 64 <1036800000>; 347 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 348 }; 349 350 opp-1248000000 { 351 opp-hz = /bits/ 64 <1248000000>; 352 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 353 }; 354 355 opp-1401600000 { 356 opp-hz = /bits/ 64 <1401600000>; 357 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>; 358 }; 359 360 opp-1555200000 { 361 opp-hz = /bits/ 64 <1555200000>; 362 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 363 }; 364 365 opp-1766400000 { 366 opp-hz = /bits/ 64 <1766400000>; 367 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 368 }; 369 370 opp-1900800000 { 371 opp-hz = /bits/ 64 <1900800000>; 372 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 373 }; 374 375 opp-2073600000 { 376 opp-hz = /bits/ 64 <2073600000>; 377 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 378 }; 379 }; 380 381 pmu { 382 compatible = "arm,armv8-pmuv3"; 383 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 384 }; 385 386 psci { 387 compatible = "arm,psci-1.0"; 388 method = "smc"; 389 }; 390 391 reserved_memory: reserved-memory { 392 #address-cells = <2>; 393 #size-cells = <2>; 394 ranges; 395 396 hyp_mem: memory@80000000 { 397 reg = <0 0x80000000 0 0x600000>; 398 no-map; 399 }; 400 401 xbl_aop_mem: memory@80700000 { 402 reg = <0 0x80700000 0 0x160000>; 403 no-map; 404 }; 405 406 cmd_db: memory@80860000 { 407 compatible = "qcom,cmd-db"; 408 reg = <0 0x80860000 0 0x20000>; 409 no-map; 410 }; 411 412 sec_apps_mem: memory@808ff000 { 413 reg = <0 0x808ff000 0 0x1000>; 414 no-map; 415 }; 416 417 smem_mem: memory@80900000 { 418 reg = <0 0x80900000 0 0x200000>; 419 no-map; 420 }; 421 422 cdsp_sec_mem: memory@80b00000 { 423 reg = <0 0x80b00000 0 0x1e00000>; 424 no-map; 425 }; 426 427 pil_camera_mem: memory@86000000 { 428 reg = <0 0x86000000 0 0x500000>; 429 no-map; 430 }; 431 432 pil_npu_mem: memory@86500000 { 433 reg = <0 0x86500000 0 0x500000>; 434 no-map; 435 }; 436 437 pil_video_mem: memory@86a00000 { 438 reg = <0 0x86a00000 0 0x500000>; 439 no-map; 440 }; 441 442 pil_cdsp_mem: memory@86f00000 { 443 reg = <0 0x86f00000 0 0x1e00000>; 444 no-map; 445 }; 446 447 pil_adsp_mem: memory@88d00000 { 448 reg = <0 0x88d00000 0 0x2800000>; 449 no-map; 450 }; 451 452 wlan_fw_mem: memory@8b500000 { 453 reg = <0 0x8b500000 0 0x200000>; 454 no-map; 455 }; 456 457 pil_ipa_fw_mem: memory@8b700000 { 458 reg = <0 0x8b700000 0 0x10000>; 459 no-map; 460 }; 461 462 pil_ipa_gsi_mem: memory@8b710000 { 463 reg = <0 0x8b710000 0 0x5400>; 464 no-map; 465 }; 466 467 pil_gpu_mem: memory@8b715400 { 468 reg = <0 0x8b715400 0 0x2000>; 469 no-map; 470 }; 471 472 pil_modem_mem: memory@8b800000 { 473 reg = <0 0x8b800000 0 0xf800000>; 474 no-map; 475 }; 476 477 cont_splash_memory: memory@a0000000 { 478 reg = <0 0xa0000000 0 0x2300000>; 479 no-map; 480 }; 481 482 dfps_data_memory: memory@a2300000 { 483 reg = <0 0xa2300000 0 0x100000>; 484 no-map; 485 }; 486 487 removed_region: memory@c0000000 { 488 reg = <0 0xc0000000 0 0x3900000>; 489 no-map; 490 }; 491 492 debug_region: memory@ffb00000 { 493 reg = <0 0xffb00000 0 0xc0000>; 494 no-map; 495 }; 496 497 last_log_region: memory@ffbc0000 { 498 reg = <0 0xffbc0000 0 0x40000>; 499 no-map; 500 }; 501 502 ramoops: ramoops@ffc00000 { 503 compatible = "ramoops"; 504 reg = <0 0xffc00000 0 0x100000>; 505 record-size = <0x1000>; 506 console-size = <0x40000>; 507 msg-size = <0x20000 0x20000>; 508 ecc-size = <16>; 509 no-map; 510 }; 511 512 cmdline_region: memory@ffd00000 { 513 reg = <0 0xffd00000 0 0x1000>; 514 no-map; 515 }; 516 }; 517 518 smem { 519 compatible = "qcom,smem"; 520 memory-region = <&smem_mem>; 521 hwlocks = <&tcsr_mutex 3>; 522 }; 523 524 smp2p-adsp { 525 compatible = "qcom,smp2p"; 526 qcom,smem = <443>, <429>; 527 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 528 IPCC_MPROC_SIGNAL_SMP2P 529 IRQ_TYPE_EDGE_RISING>; 530 mboxes = <&ipcc IPCC_CLIENT_LPASS 531 IPCC_MPROC_SIGNAL_SMP2P>; 532 533 qcom,local-pid = <0>; 534 qcom,remote-pid = <2>; 535 536 smp2p_adsp_out: master-kernel { 537 qcom,entry-name = "master-kernel"; 538 #qcom,smem-state-cells = <1>; 539 }; 540 541 smp2p_adsp_in: slave-kernel { 542 qcom,entry-name = "slave-kernel"; 543 interrupt-controller; 544 #interrupt-cells = <2>; 545 }; 546 }; 547 548 smp2p-cdsp { 549 compatible = "qcom,smp2p"; 550 qcom,smem = <94>, <432>; 551 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 552 IPCC_MPROC_SIGNAL_SMP2P 553 IRQ_TYPE_EDGE_RISING>; 554 mboxes = <&ipcc IPCC_CLIENT_CDSP 555 IPCC_MPROC_SIGNAL_SMP2P>; 556 557 qcom,local-pid = <0>; 558 qcom,remote-pid = <5>; 559 560 smp2p_cdsp_out: master-kernel { 561 qcom,entry-name = "master-kernel"; 562 #qcom,smem-state-cells = <1>; 563 }; 564 565 smp2p_cdsp_in: slave-kernel { 566 qcom,entry-name = "slave-kernel"; 567 interrupt-controller; 568 #interrupt-cells = <2>; 569 }; 570 }; 571 572 smp2p-mpss { 573 compatible = "qcom,smp2p"; 574 qcom,smem = <435>, <428>; 575 576 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 577 IPCC_MPROC_SIGNAL_SMP2P 578 IRQ_TYPE_EDGE_RISING>; 579 mboxes = <&ipcc IPCC_CLIENT_MPSS 580 IPCC_MPROC_SIGNAL_SMP2P>; 581 582 qcom,local-pid = <0>; 583 qcom,remote-pid = <1>; 584 585 modem_smp2p_out: master-kernel { 586 qcom,entry-name = "master-kernel"; 587 #qcom,smem-state-cells = <1>; 588 }; 589 590 modem_smp2p_in: slave-kernel { 591 qcom,entry-name = "slave-kernel"; 592 interrupt-controller; 593 #interrupt-cells = <2>; 594 }; 595 596 ipa_smp2p_out: ipa-ap-to-modem { 597 qcom,entry-name = "ipa"; 598 #qcom,smem-state-cells = <1>; 599 }; 600 601 ipa_smp2p_in: ipa-modem-to-ap { 602 qcom,entry-name = "ipa"; 603 interrupt-controller; 604 #interrupt-cells = <2>; 605 }; 606 }; 607 608 soc: soc@0 { 609 #address-cells = <2>; 610 #size-cells = <2>; 611 ranges = <0 0 0 0 0x10 0>; 612 dma-ranges = <0 0 0 0 0x10 0>; 613 compatible = "simple-bus"; 614 615 gcc: clock-controller@100000 { 616 compatible = "qcom,gcc-sm6350"; 617 reg = <0 0x00100000 0 0x1f0000>; 618 #clock-cells = <1>; 619 #reset-cells = <1>; 620 #power-domain-cells = <1>; 621 clock-names = "bi_tcxo", 622 "bi_tcxo_ao", 623 "sleep_clk"; 624 clocks = <&rpmhcc RPMH_CXO_CLK>, 625 <&rpmhcc RPMH_CXO_CLK_A>, 626 <&sleep_clk>; 627 }; 628 629 ipcc: mailbox@408000 { 630 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 631 reg = <0 0x00408000 0 0x1000>; 632 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 633 interrupt-controller; 634 #interrupt-cells = <3>; 635 #mbox-cells = <2>; 636 }; 637 638 rng: rng@793000 { 639 compatible = "qcom,prng-ee"; 640 reg = <0 0x00793000 0 0x1000>; 641 clocks = <&gcc GCC_PRNG_AHB_CLK>; 642 clock-names = "core"; 643 }; 644 645 sdhc_1: mmc@7c4000 { 646 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 647 reg = <0 0x007c4000 0 0x1000>, 648 <0 0x007c5000 0 0x1000>, 649 <0 0x007c8000 0 0x8000>; 650 reg-names = "hc", "cqhci", "ice"; 651 652 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 654 interrupt-names = "hc_irq", "pwr_irq"; 655 iommus = <&apps_smmu 0x60 0x0>; 656 657 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 658 <&gcc GCC_SDCC1_APPS_CLK>, 659 <&rpmhcc RPMH_CXO_CLK>; 660 clock-names = "iface", "core", "xo"; 661 resets = <&gcc GCC_SDCC1_BCR>; 662 qcom,dll-config = <0x000f642c>; 663 qcom,ddr-config = <0x80040868>; 664 power-domains = <&rpmhpd SM6350_CX>; 665 operating-points-v2 = <&sdhc1_opp_table>; 666 bus-width = <8>; 667 non-removable; 668 supports-cqe; 669 670 status = "disabled"; 671 672 sdhc1_opp_table: opp-table { 673 compatible = "operating-points-v2"; 674 675 opp-19200000 { 676 opp-hz = /bits/ 64 <19200000>; 677 required-opps = <&rpmhpd_opp_min_svs>; 678 }; 679 680 opp-100000000 { 681 opp-hz = /bits/ 64 <100000000>; 682 required-opps = <&rpmhpd_opp_low_svs>; 683 }; 684 685 opp-384000000 { 686 opp-hz = /bits/ 64 <384000000>; 687 required-opps = <&rpmhpd_opp_svs_l1>; 688 }; 689 }; 690 }; 691 692 gpi_dma0: dma-controller@800000 { 693 compatible = "qcom,sm6350-gpi-dma"; 694 reg = <0 0x00800000 0 0x60000>; 695 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 705 dma-channels = <10>; 706 dma-channel-mask = <0x1f>; 707 iommus = <&apps_smmu 0x56 0x0>; 708 #dma-cells = <3>; 709 status = "disabled"; 710 }; 711 712 qupv3_id_0: geniqup@8c0000 { 713 compatible = "qcom,geni-se-qup"; 714 reg = <0x0 0x008c0000 0x0 0x2000>; 715 clock-names = "m-ahb", "s-ahb"; 716 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 717 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 718 #address-cells = <2>; 719 #size-cells = <2>; 720 iommus = <&apps_smmu 0x43 0x0>; 721 ranges; 722 status = "disabled"; 723 724 i2c0: i2c@880000 { 725 compatible = "qcom,geni-i2c"; 726 reg = <0 0x00880000 0 0x4000>; 727 clock-names = "se"; 728 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 729 pinctrl-names = "default"; 730 pinctrl-0 = <&qup_i2c0_default>; 731 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 732 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 733 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 734 dma-names = "tx", "rx"; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 738 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 739 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 740 interconnect-names = "qup-core", "qup-config", "qup-memory"; 741 status = "disabled"; 742 }; 743 744 i2c2: i2c@888000 { 745 compatible = "qcom,geni-i2c"; 746 reg = <0 0x00888000 0 0x4000>; 747 clock-names = "se"; 748 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 749 pinctrl-names = "default"; 750 pinctrl-0 = <&qup_i2c2_default>; 751 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 752 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 753 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 754 dma-names = "tx", "rx"; 755 #address-cells = <1>; 756 #size-cells = <0>; 757 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 758 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 759 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 760 interconnect-names = "qup-core", "qup-config", "qup-memory"; 761 status = "disabled"; 762 }; 763 }; 764 765 gpi_dma1: dma-controller@900000 { 766 compatible = "qcom,sm6350-gpi-dma"; 767 reg = <0 0x00900000 0 0x60000>; 768 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 778 dma-channels = <10>; 779 dma-channel-mask = <0x3f>; 780 iommus = <&apps_smmu 0x4d6 0x0>; 781 #dma-cells = <3>; 782 status = "disabled"; 783 }; 784 785 qupv3_id_1: geniqup@9c0000 { 786 compatible = "qcom,geni-se-qup"; 787 reg = <0x0 0x009c0000 0x0 0x2000>; 788 clock-names = "m-ahb", "s-ahb"; 789 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 790 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 791 #address-cells = <2>; 792 #size-cells = <2>; 793 iommus = <&apps_smmu 0x4c3 0x0>; 794 ranges; 795 status = "disabled"; 796 797 i2c6: i2c@980000 { 798 compatible = "qcom,geni-i2c"; 799 reg = <0 0x00980000 0 0x4000>; 800 clock-names = "se"; 801 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 802 pinctrl-names = "default"; 803 pinctrl-0 = <&qup_i2c6_default>; 804 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 805 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 806 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 807 dma-names = "tx", "rx"; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 811 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 812 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 813 interconnect-names = "qup-core", "qup-config", "qup-memory"; 814 status = "disabled"; 815 }; 816 817 i2c7: i2c@984000 { 818 compatible = "qcom,geni-i2c"; 819 reg = <0 0x00984000 0 0x4000>; 820 clock-names = "se"; 821 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 822 pinctrl-names = "default"; 823 pinctrl-0 = <&qup_i2c7_default>; 824 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 825 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 826 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 827 dma-names = "tx", "rx"; 828 #address-cells = <1>; 829 #size-cells = <0>; 830 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 831 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 832 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 833 interconnect-names = "qup-core", "qup-config", "qup-memory"; 834 status = "disabled"; 835 }; 836 837 i2c8: i2c@988000 { 838 compatible = "qcom,geni-i2c"; 839 reg = <0 0x00988000 0 0x4000>; 840 clock-names = "se"; 841 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 842 pinctrl-names = "default"; 843 pinctrl-0 = <&qup_i2c8_default>; 844 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 845 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 846 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 847 dma-names = "tx", "rx"; 848 #address-cells = <1>; 849 #size-cells = <0>; 850 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 851 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 852 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 853 interconnect-names = "qup-core", "qup-config", "qup-memory"; 854 status = "disabled"; 855 }; 856 857 uart9: serial@98c000 { 858 compatible = "qcom,geni-debug-uart"; 859 reg = <0 0x0098c000 0 0x4000>; 860 clock-names = "se"; 861 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 862 pinctrl-names = "default"; 863 pinctrl-0 = <&qup_uart9_default>; 864 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 865 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 866 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 867 interconnect-names = "qup-core", "qup-config"; 868 status = "disabled"; 869 }; 870 871 i2c10: i2c@990000 { 872 compatible = "qcom,geni-i2c"; 873 reg = <0 0x00990000 0 0x4000>; 874 clock-names = "se"; 875 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 876 pinctrl-names = "default"; 877 pinctrl-0 = <&qup_i2c10_default>; 878 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 879 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 880 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 881 dma-names = "tx", "rx"; 882 #address-cells = <1>; 883 #size-cells = <0>; 884 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 885 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 886 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 887 interconnect-names = "qup-core", "qup-config", "qup-memory"; 888 status = "disabled"; 889 }; 890 }; 891 892 config_noc: interconnect@1500000 { 893 compatible = "qcom,sm6350-config-noc"; 894 reg = <0 0x01500000 0 0x28000>; 895 #interconnect-cells = <2>; 896 qcom,bcm-voters = <&apps_bcm_voter>; 897 }; 898 899 system_noc: interconnect@1620000 { 900 compatible = "qcom,sm6350-system-noc"; 901 reg = <0 0x01620000 0 0x17080>; 902 #interconnect-cells = <2>; 903 qcom,bcm-voters = <&apps_bcm_voter>; 904 905 clk_virt: interconnect-clk-virt { 906 compatible = "qcom,sm6350-clk-virt"; 907 #interconnect-cells = <2>; 908 qcom,bcm-voters = <&apps_bcm_voter>; 909 }; 910 }; 911 912 aggre1_noc: interconnect@16e0000 { 913 compatible = "qcom,sm6350-aggre1-noc"; 914 reg = <0 0x016e0000 0 0x15080>; 915 #interconnect-cells = <2>; 916 qcom,bcm-voters = <&apps_bcm_voter>; 917 }; 918 919 aggre2_noc: interconnect@1700000 { 920 compatible = "qcom,sm6350-aggre2-noc"; 921 reg = <0 0x01700000 0 0x1f880>; 922 #interconnect-cells = <2>; 923 qcom,bcm-voters = <&apps_bcm_voter>; 924 925 compute_noc: interconnect-compute-noc { 926 compatible = "qcom,sm6350-compute-noc"; 927 #interconnect-cells = <2>; 928 qcom,bcm-voters = <&apps_bcm_voter>; 929 }; 930 }; 931 932 mmss_noc: interconnect@1740000 { 933 compatible = "qcom,sm6350-mmss-noc"; 934 reg = <0 0x01740000 0 0x1c100>; 935 #interconnect-cells = <2>; 936 qcom,bcm-voters = <&apps_bcm_voter>; 937 }; 938 939 ufs_mem_hc: ufs@1d84000 { 940 compatible = "qcom,sm6350-ufshc", "qcom,ufshc", 941 "jedec,ufs-2.0"; 942 reg = <0 0x01d84000 0 0x3000>, 943 <0 0x01d90000 0 0x8000>; 944 reg-names = "std", "ice"; 945 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 946 phys = <&ufs_mem_phy_lanes>; 947 phy-names = "ufsphy"; 948 lanes-per-direction = <2>; 949 #reset-cells = <1>; 950 resets = <&gcc GCC_UFS_PHY_BCR>; 951 reset-names = "rst"; 952 953 power-domains = <&gcc UFS_PHY_GDSC>; 954 955 iommus = <&apps_smmu 0x80 0x0>; 956 957 clock-names = "core_clk", 958 "bus_aggr_clk", 959 "iface_clk", 960 "core_clk_unipro", 961 "ref_clk", 962 "tx_lane0_sync_clk", 963 "rx_lane0_sync_clk", 964 "rx_lane1_sync_clk", 965 "ice_core_clk"; 966 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 967 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 968 <&gcc GCC_UFS_PHY_AHB_CLK>, 969 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 970 <&rpmhcc RPMH_QLINK_CLK>, 971 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 972 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 973 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 974 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 975 freq-table-hz = 976 <50000000 200000000>, 977 <0 0>, 978 <0 0>, 979 <37500000 150000000>, 980 <75000000 300000000>, 981 <0 0>, 982 <0 0>, 983 <0 0>, 984 <0 0>; 985 986 status = "disabled"; 987 }; 988 989 ufs_mem_phy: phy@1d87000 { 990 compatible = "qcom,sm6350-qmp-ufs-phy"; 991 reg = <0 0x01d87000 0 0x18c>; 992 #address-cells = <2>; 993 #size-cells = <2>; 994 ranges; 995 996 clock-names = "ref", 997 "ref_aux"; 998 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 999 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1000 1001 resets = <&ufs_mem_hc 0>; 1002 reset-names = "ufsphy"; 1003 1004 status = "disabled"; 1005 1006 ufs_mem_phy_lanes: phy@1d87400 { 1007 reg = <0 0x01d87400 0 0x128>, 1008 <0 0x01d87600 0 0x1fc>, 1009 <0 0x01d87c00 0 0x1dc>, 1010 <0 0x01d87800 0 0x128>, 1011 <0 0x01d87a00 0 0x1fc>; 1012 #phy-cells = <0>; 1013 }; 1014 }; 1015 1016 ipa: ipa@1e40000 { 1017 compatible = "qcom,sm6350-ipa"; 1018 1019 iommus = <&apps_smmu 0x440 0x0>, 1020 <&apps_smmu 0x442 0x0>; 1021 reg = <0 0x01e40000 0 0x8000>, 1022 <0 0x01e50000 0 0x3000>, 1023 <0 0x01e04000 0 0x23000>; 1024 reg-names = "ipa-reg", 1025 "ipa-shared", 1026 "gsi"; 1027 1028 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1029 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1030 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1031 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1032 interrupt-names = "ipa", 1033 "gsi", 1034 "ipa-clock-query", 1035 "ipa-setup-ready"; 1036 1037 clocks = <&rpmhcc RPMH_IPA_CLK>; 1038 clock-names = "core"; 1039 1040 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>, 1041 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, 1042 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; 1043 interconnect-names = "memory", "imem", "config"; 1044 1045 qcom,smem-states = <&ipa_smp2p_out 0>, 1046 <&ipa_smp2p_out 1>; 1047 qcom,smem-state-names = "ipa-clock-enabled-valid", 1048 "ipa-clock-enabled"; 1049 1050 status = "disabled"; 1051 }; 1052 1053 tcsr_mutex: hwlock@1f40000 { 1054 compatible = "qcom,tcsr-mutex"; 1055 reg = <0x0 0x01f40000 0x0 0x40000>; 1056 #hwlock-cells = <1>; 1057 }; 1058 1059 adsp: remoteproc@3000000 { 1060 compatible = "qcom,sm6350-adsp-pas"; 1061 reg = <0 0x03000000 0 0x100>; 1062 1063 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 1064 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1065 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1066 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1067 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1068 interrupt-names = "wdog", "fatal", "ready", 1069 "handover", "stop-ack"; 1070 1071 clocks = <&rpmhcc RPMH_CXO_CLK>; 1072 clock-names = "xo"; 1073 1074 power-domains = <&rpmhpd SM6350_LCX>, 1075 <&rpmhpd SM6350_LMX>; 1076 power-domain-names = "lcx", "lmx"; 1077 1078 memory-region = <&pil_adsp_mem>; 1079 1080 qcom,qmp = <&aoss_qmp>; 1081 1082 qcom,smem-states = <&smp2p_adsp_out 0>; 1083 qcom,smem-state-names = "stop"; 1084 1085 status = "disabled"; 1086 1087 glink-edge { 1088 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1089 IPCC_MPROC_SIGNAL_GLINK_QMP 1090 IRQ_TYPE_EDGE_RISING>; 1091 mboxes = <&ipcc IPCC_CLIENT_LPASS 1092 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1093 1094 label = "lpass"; 1095 qcom,remote-pid = <2>; 1096 1097 fastrpc { 1098 compatible = "qcom,fastrpc"; 1099 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1100 label = "adsp"; 1101 #address-cells = <1>; 1102 #size-cells = <0>; 1103 1104 compute-cb@3 { 1105 compatible = "qcom,fastrpc-compute-cb"; 1106 reg = <3>; 1107 iommus = <&apps_smmu 0x1003 0x0>; 1108 }; 1109 1110 compute-cb@4 { 1111 compatible = "qcom,fastrpc-compute-cb"; 1112 reg = <4>; 1113 iommus = <&apps_smmu 0x1004 0x0>; 1114 }; 1115 1116 compute-cb@5 { 1117 compatible = "qcom,fastrpc-compute-cb"; 1118 reg = <5>; 1119 iommus = <&apps_smmu 0x1005 0x0>; 1120 qcom,nsessions = <5>; 1121 }; 1122 }; 1123 }; 1124 }; 1125 1126 mpss: remoteproc@4080000 { 1127 compatible = "qcom,sm6350-mpss-pas"; 1128 reg = <0x0 0x04080000 0x0 0x4040>; 1129 1130 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 1131 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1132 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1133 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1134 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1135 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1136 interrupt-names = "wdog", "fatal", "ready", "handover", 1137 "stop-ack", "shutdown-ack"; 1138 1139 clocks = <&rpmhcc RPMH_CXO_CLK>; 1140 clock-names = "xo"; 1141 1142 power-domains = <&rpmhpd SM6350_CX>, 1143 <&rpmhpd SM6350_MSS>; 1144 power-domain-names = "cx", "mss"; 1145 1146 memory-region = <&pil_modem_mem>; 1147 1148 qcom,qmp = <&aoss_qmp>; 1149 1150 qcom,smem-states = <&modem_smp2p_out 0>; 1151 qcom,smem-state-names = "stop"; 1152 1153 status = "disabled"; 1154 1155 glink-edge { 1156 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1157 IPCC_MPROC_SIGNAL_GLINK_QMP 1158 IRQ_TYPE_EDGE_RISING>; 1159 mboxes = <&ipcc IPCC_CLIENT_MPSS 1160 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1161 label = "modem"; 1162 qcom,remote-pid = <1>; 1163 }; 1164 }; 1165 1166 cdsp: remoteproc@8300000 { 1167 compatible = "qcom,sm6350-cdsp-pas"; 1168 reg = <0 0x08300000 0 0x10000>; 1169 1170 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 1171 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1172 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1173 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1174 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1175 interrupt-names = "wdog", "fatal", "ready", 1176 "handover", "stop-ack"; 1177 1178 clocks = <&rpmhcc RPMH_CXO_CLK>; 1179 clock-names = "xo"; 1180 1181 power-domains = <&rpmhpd SM6350_CX>, 1182 <&rpmhpd SM6350_MX>; 1183 power-domain-names = "cx", "mx"; 1184 1185 memory-region = <&pil_cdsp_mem>; 1186 1187 qcom,qmp = <&aoss_qmp>; 1188 1189 qcom,smem-states = <&smp2p_cdsp_out 0>; 1190 qcom,smem-state-names = "stop"; 1191 1192 status = "disabled"; 1193 1194 glink-edge { 1195 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1196 IPCC_MPROC_SIGNAL_GLINK_QMP 1197 IRQ_TYPE_EDGE_RISING>; 1198 mboxes = <&ipcc IPCC_CLIENT_CDSP 1199 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1200 1201 label = "cdsp"; 1202 qcom,remote-pid = <5>; 1203 1204 fastrpc { 1205 compatible = "qcom,fastrpc"; 1206 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1207 label = "cdsp"; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 1211 compute-cb@1 { 1212 compatible = "qcom,fastrpc-compute-cb"; 1213 reg = <1>; 1214 iommus = <&apps_smmu 0x1401 0x20>; 1215 }; 1216 1217 compute-cb@2 { 1218 compatible = "qcom,fastrpc-compute-cb"; 1219 reg = <2>; 1220 iommus = <&apps_smmu 0x1402 0x20>; 1221 }; 1222 1223 compute-cb@3 { 1224 compatible = "qcom,fastrpc-compute-cb"; 1225 reg = <3>; 1226 iommus = <&apps_smmu 0x1403 0x20>; 1227 }; 1228 1229 compute-cb@4 { 1230 compatible = "qcom,fastrpc-compute-cb"; 1231 reg = <4>; 1232 iommus = <&apps_smmu 0x1404 0x20>; 1233 }; 1234 1235 compute-cb@5 { 1236 compatible = "qcom,fastrpc-compute-cb"; 1237 reg = <5>; 1238 iommus = <&apps_smmu 0x1405 0x20>; 1239 }; 1240 1241 compute-cb@6 { 1242 compatible = "qcom,fastrpc-compute-cb"; 1243 reg = <6>; 1244 iommus = <&apps_smmu 0x1406 0x20>; 1245 }; 1246 1247 compute-cb@7 { 1248 compatible = "qcom,fastrpc-compute-cb"; 1249 reg = <7>; 1250 iommus = <&apps_smmu 0x1407 0x20>; 1251 }; 1252 1253 compute-cb@8 { 1254 compatible = "qcom,fastrpc-compute-cb"; 1255 reg = <8>; 1256 iommus = <&apps_smmu 0x1408 0x20>; 1257 }; 1258 1259 /* note: secure cb9 in downstream */ 1260 }; 1261 }; 1262 }; 1263 1264 sdhc_2: mmc@8804000 { 1265 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 1266 reg = <0 0x08804000 0 0x1000>; 1267 1268 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1270 interrupt-names = "hc_irq", "pwr_irq"; 1271 iommus = <&apps_smmu 0x560 0x0>; 1272 1273 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1274 <&gcc GCC_SDCC2_APPS_CLK>, 1275 <&rpmhcc RPMH_CXO_CLK>; 1276 clock-names = "iface", "core", "xo"; 1277 resets = <&gcc GCC_SDCC2_BCR>; 1278 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, 1279 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; 1280 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1281 1282 pinctrl-0 = <&sdc2_on_state>; 1283 pinctrl-1 = <&sdc2_off_state>; 1284 pinctrl-names = "default", "sleep"; 1285 1286 qcom,dll-config = <0x0007642c>; 1287 qcom,ddr-config = <0x80040868>; 1288 power-domains = <&rpmhpd SM6350_CX>; 1289 operating-points-v2 = <&sdhc2_opp_table>; 1290 bus-width = <4>; 1291 1292 status = "disabled"; 1293 1294 sdhc2_opp_table: opp-table { 1295 compatible = "operating-points-v2"; 1296 1297 opp-100000000 { 1298 opp-hz = /bits/ 64 <100000000>; 1299 required-opps = <&rpmhpd_opp_svs_l1>; 1300 opp-peak-kBps = <790000 131000>; 1301 opp-avg-kBps = <50000 50000>; 1302 }; 1303 1304 opp-202000000 { 1305 opp-hz = /bits/ 64 <202000000>; 1306 required-opps = <&rpmhpd_opp_nom>; 1307 opp-peak-kBps = <3190000 294000>; 1308 opp-avg-kBps = <261438 300000>; 1309 }; 1310 }; 1311 }; 1312 1313 usb_1_hsphy: phy@88e3000 { 1314 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 1315 reg = <0 0x088e3000 0 0x400>; 1316 status = "disabled"; 1317 #phy-cells = <0>; 1318 1319 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 1320 clock-names = "cfg_ahb", "ref"; 1321 1322 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1323 }; 1324 1325 usb_1_qmpphy: phy@88e8000 { 1326 compatible = "qcom,sm6350-qmp-usb3-dp-phy"; 1327 reg = <0 0x088e8000 0 0x3000>; 1328 1329 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1330 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1331 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1332 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1333 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 1334 1335 power-domains = <&gcc USB30_PRIM_GDSC>; 1336 1337 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1338 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1339 reset-names = "phy", "common"; 1340 1341 #clock-cells = <1>; 1342 #phy-cells = <1>; 1343 1344 status = "disabled"; 1345 }; 1346 1347 dc_noc: interconnect@9160000 { 1348 compatible = "qcom,sm6350-dc-noc"; 1349 reg = <0 0x09160000 0 0x3200>; 1350 #interconnect-cells = <2>; 1351 qcom,bcm-voters = <&apps_bcm_voter>; 1352 }; 1353 1354 system-cache-controller@9200000 { 1355 compatible = "qcom,sm6350-llcc"; 1356 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 1357 reg-names = "llcc0_base", "llcc_broadcast_base"; 1358 }; 1359 1360 gem_noc: interconnect@9680000 { 1361 compatible = "qcom,sm6350-gem-noc"; 1362 reg = <0 0x09680000 0 0x3e200>; 1363 #interconnect-cells = <2>; 1364 qcom,bcm-voters = <&apps_bcm_voter>; 1365 }; 1366 1367 npu_noc: interconnect@9990000 { 1368 compatible = "qcom,sm6350-npu-noc"; 1369 reg = <0 0x09990000 0 0x1600>; 1370 #interconnect-cells = <2>; 1371 qcom,bcm-voters = <&apps_bcm_voter>; 1372 }; 1373 1374 usb_1: usb@a6f8800 { 1375 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 1376 reg = <0 0x0a6f8800 0 0x400>; 1377 status = "disabled"; 1378 #address-cells = <2>; 1379 #size-cells = <2>; 1380 ranges; 1381 1382 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1383 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1384 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1385 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1386 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1387 clock-names = "cfg_noc", 1388 "core", 1389 "iface", 1390 "sleep", 1391 "mock_utmi"; 1392 1393 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1394 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 1395 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1396 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 1397 1398 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1399 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1400 1401 power-domains = <&gcc USB30_PRIM_GDSC>; 1402 1403 resets = <&gcc GCC_USB30_PRIM_BCR>; 1404 1405 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, 1406 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1407 interconnect-names = "usb-ddr", "apps-usb"; 1408 1409 usb_1_dwc3: usb@a600000 { 1410 compatible = "snps,dwc3"; 1411 reg = <0 0x0a600000 0 0xcd00>; 1412 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1413 iommus = <&apps_smmu 0x540 0x0>; 1414 snps,dis_u2_susphy_quirk; 1415 snps,dis_enblslpm_quirk; 1416 snps,has-lpm-erratum; 1417 snps,hird-threshold = /bits/ 8 <0x10>; 1418 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 1419 phy-names = "usb2-phy", "usb3-phy"; 1420 }; 1421 }; 1422 1423 cci0: cci@ac4a000 { 1424 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 1425 reg = <0 0x0ac4a000 0 0x1000>; 1426 interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; 1427 power-domains = <&camcc TITAN_TOP_GDSC>; 1428 1429 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1430 <&camcc CAMCC_SOC_AHB_CLK>, 1431 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 1432 <&camcc CAMCC_CPAS_AHB_CLK>, 1433 <&camcc CAMCC_CCI_0_CLK>, 1434 <&camcc CAMCC_CCI_0_CLK_SRC>; 1435 clock-names = "camnoc_axi", 1436 "soc_ahb", 1437 "slow_ahb_src", 1438 "cpas_ahb", 1439 "cci", 1440 "cci_src"; 1441 1442 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1443 <&camcc CAMCC_CCI_0_CLK>; 1444 assigned-clock-rates = <80000000>, <37500000>; 1445 1446 pinctrl-0 = <&cci0_default &cci1_default>; 1447 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 1448 pinctrl-names = "default", "sleep"; 1449 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 1453 status = "disabled"; 1454 1455 cci0_i2c0: i2c-bus@0 { 1456 reg = <0>; 1457 clock-frequency = <1000000>; 1458 #address-cells = <1>; 1459 #size-cells = <0>; 1460 }; 1461 1462 cci0_i2c1: i2c-bus@1 { 1463 reg = <1>; 1464 clock-frequency = <1000000>; 1465 #address-cells = <1>; 1466 #size-cells = <0>; 1467 }; 1468 }; 1469 1470 cci1: cci@ac4b000 { 1471 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 1472 reg = <0 0x0ac4b000 0 0x1000>; 1473 interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; 1474 power-domains = <&camcc TITAN_TOP_GDSC>; 1475 1476 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1477 <&camcc CAMCC_SOC_AHB_CLK>, 1478 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 1479 <&camcc CAMCC_CPAS_AHB_CLK>, 1480 <&camcc CAMCC_CCI_1_CLK>, 1481 <&camcc CAMCC_CCI_1_CLK_SRC>; 1482 clock-names = "camnoc_axi", 1483 "soc_ahb", 1484 "slow_ahb_src", 1485 "cpas_ahb", 1486 "cci", 1487 "cci_src"; 1488 1489 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1490 <&camcc CAMCC_CCI_1_CLK>; 1491 assigned-clock-rates = <80000000>, <37500000>; 1492 1493 pinctrl-0 = <&cci2_default>; 1494 pinctrl-1 = <&cci2_sleep>; 1495 pinctrl-names = "default", "sleep"; 1496 1497 #address-cells = <1>; 1498 #size-cells = <0>; 1499 1500 status = "disabled"; 1501 1502 cci1_i2c0: i2c-bus@0 { 1503 reg = <0>; 1504 clock-frequency = <1000000>; 1505 #address-cells = <1>; 1506 #size-cells = <0>; 1507 }; 1508 1509 /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ 1510 }; 1511 1512 camcc: clock-controller@ad00000 { 1513 compatible = "qcom,sm6350-camcc"; 1514 reg = <0 0x0ad00000 0 0x16000>; 1515 clocks = <&rpmhcc RPMH_CXO_CLK>; 1516 #clock-cells = <1>; 1517 #reset-cells = <1>; 1518 #power-domain-cells = <1>; 1519 }; 1520 1521 pdc: interrupt-controller@b220000 { 1522 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 1523 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; 1524 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 1525 <125 63 1>, <126 655 12>, <138 139 15>; 1526 #interrupt-cells = <2>; 1527 interrupt-parent = <&intc>; 1528 interrupt-controller; 1529 }; 1530 1531 tsens0: thermal-sensor@c263000 { 1532 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1533 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1534 <0 0x0c222000 0 0x8>; /* SROT */ 1535 #qcom,sensors = <16>; 1536 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 1537 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 1538 interrupt-names = "uplow", "critical"; 1539 #thermal-sensor-cells = <1>; 1540 }; 1541 1542 tsens1: thermal-sensor@c265000 { 1543 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1544 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1545 <0 0x0c223000 0 0x8>; /* SROT */ 1546 #qcom,sensors = <16>; 1547 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 1548 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 1549 interrupt-names = "uplow", "critical"; 1550 #thermal-sensor-cells = <1>; 1551 }; 1552 1553 aoss_qmp: power-management@c300000 { 1554 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 1555 reg = <0 0x0c300000 0 0x1000>; 1556 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 1557 IRQ_TYPE_EDGE_RISING>; 1558 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 1559 1560 #clock-cells = <0>; 1561 }; 1562 1563 spmi_bus: spmi@c440000 { 1564 compatible = "qcom,spmi-pmic-arb"; 1565 reg = <0 0x0c440000 0 0x1100>, 1566 <0 0x0c600000 0 0x2000000>, 1567 <0 0x0e600000 0 0x100000>, 1568 <0 0x0e700000 0 0xa0000>, 1569 <0 0x0c40a000 0 0x26000>; 1570 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1571 interrupt-names = "periph_irq"; 1572 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1573 qcom,ee = <0>; 1574 qcom,channel = <0>; 1575 #address-cells = <2>; 1576 #size-cells = <0>; 1577 interrupt-controller; 1578 #interrupt-cells = <4>; 1579 }; 1580 1581 tlmm: pinctrl@f100000 { 1582 compatible = "qcom,sm6350-tlmm"; 1583 reg = <0 0x0f100000 0 0x300000>; 1584 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 1593 gpio-controller; 1594 #gpio-cells = <2>; 1595 interrupt-controller; 1596 #interrupt-cells = <2>; 1597 gpio-ranges = <&tlmm 0 0 157>; 1598 1599 cci0_default: cci0-default-state { 1600 pins = "gpio39", "gpio40"; 1601 function = "cci_i2c"; 1602 drive-strength = <2>; 1603 bias-pull-up; 1604 }; 1605 1606 cci0_sleep: cci0-sleep-state { 1607 pins = "gpio39", "gpio40"; 1608 function = "cci_i2c"; 1609 drive-strength = <2>; 1610 bias-pull-down; 1611 }; 1612 1613 cci1_default: cci1-default-state { 1614 pins = "gpio41", "gpio42"; 1615 function = "cci_i2c"; 1616 drive-strength = <2>; 1617 bias-pull-up; 1618 }; 1619 1620 cci1_sleep: cci1-sleep-state { 1621 pins = "gpio41", "gpio42"; 1622 function = "cci_i2c"; 1623 drive-strength = <2>; 1624 bias-pull-down; 1625 }; 1626 1627 cci2_default: cci2-default-state { 1628 pins = "gpio43", "gpio44"; 1629 function = "cci_i2c"; 1630 drive-strength = <2>; 1631 bias-pull-up; 1632 }; 1633 1634 cci2_sleep: cci2-sleep-state { 1635 pins = "gpio43", "gpio44"; 1636 function = "cci_i2c"; 1637 drive-strength = <2>; 1638 bias-pull-down; 1639 }; 1640 1641 sdc2_off_state: sdc2-off-state { 1642 clk-pins { 1643 pins = "sdc2_clk"; 1644 drive-strength = <2>; 1645 bias-disable; 1646 }; 1647 1648 cmd-pins { 1649 pins = "sdc2_cmd"; 1650 drive-strength = <2>; 1651 bias-pull-up; 1652 }; 1653 1654 data-pins { 1655 pins = "sdc2_data"; 1656 drive-strength = <2>; 1657 bias-pull-up; 1658 }; 1659 }; 1660 1661 sdc2_on_state: sdc2-on-state { 1662 clk-pins { 1663 pins = "sdc2_clk"; 1664 drive-strength = <16>; 1665 bias-disable; 1666 }; 1667 1668 cmd-pins { 1669 pins = "sdc2_cmd"; 1670 drive-strength = <10>; 1671 bias-pull-up; 1672 }; 1673 1674 data-pins { 1675 pins = "sdc2_data"; 1676 drive-strength = <10>; 1677 bias-pull-up; 1678 }; 1679 }; 1680 1681 qup_uart9_default: qup-uart9-default-state { 1682 pins = "gpio25", "gpio26"; 1683 function = "qup13_f2"; 1684 drive-strength = <2>; 1685 bias-disable; 1686 }; 1687 1688 qup_i2c0_default: qup-i2c0-default-state { 1689 pins = "gpio0", "gpio1"; 1690 function = "qup00"; 1691 drive-strength = <2>; 1692 bias-pull-up; 1693 }; 1694 1695 qup_i2c2_default: qup-i2c2-default-state { 1696 pins = "gpio45", "gpio46"; 1697 function = "qup02"; 1698 drive-strength = <2>; 1699 bias-pull-up; 1700 }; 1701 1702 qup_i2c6_default: qup-i2c6-default-state { 1703 pins = "gpio13", "gpio14"; 1704 function = "qup10"; 1705 drive-strength = <2>; 1706 bias-pull-up; 1707 }; 1708 1709 qup_i2c7_default: qup-i2c7-default-state { 1710 pins = "gpio27", "gpio28"; 1711 function = "qup11"; 1712 drive-strength = <2>; 1713 bias-pull-up; 1714 }; 1715 1716 qup_i2c8_default: qup-i2c8-default-state { 1717 pins = "gpio19", "gpio20"; 1718 function = "qup12"; 1719 drive-strength = <2>; 1720 bias-pull-up; 1721 }; 1722 1723 qup_i2c10_default: qup-i2c10-default-state { 1724 pins = "gpio4", "gpio5"; 1725 function = "qup14"; 1726 drive-strength = <2>; 1727 bias-pull-up; 1728 }; 1729 }; 1730 1731 apps_smmu: iommu@15000000 { 1732 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 1733 reg = <0 0x15000000 0 0x100000>; 1734 #iommu-cells = <2>; 1735 #global-interrupts = <1>; 1736 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1748 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1749 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1817 }; 1818 1819 intc: interrupt-controller@17a00000 { 1820 compatible = "arm,gic-v3"; 1821 #interrupt-cells = <3>; 1822 interrupt-controller; 1823 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 1824 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 1825 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 1826 }; 1827 1828 watchdog@17c10000 { 1829 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 1830 reg = <0 0x17c10000 0 0x1000>; 1831 clocks = <&sleep_clk>; 1832 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1833 }; 1834 1835 timer@17c20000 { 1836 compatible = "arm,armv7-timer-mem"; 1837 reg = <0x0 0x17c20000 0x0 0x1000>; 1838 clock-frequency = <19200000>; 1839 #address-cells = <1>; 1840 #size-cells = <1>; 1841 ranges = <0 0 0 0x20000000>; 1842 1843 frame@17c21000 { 1844 frame-number = <0>; 1845 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1847 reg = <0x17c21000 0x1000>, 1848 <0x17c22000 0x1000>; 1849 }; 1850 1851 frame@17c23000 { 1852 frame-number = <1>; 1853 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1854 reg = <0x17c23000 0x1000>; 1855 status = "disabled"; 1856 }; 1857 1858 frame@17c25000 { 1859 frame-number = <2>; 1860 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1861 reg = <0x17c25000 0x1000>; 1862 status = "disabled"; 1863 }; 1864 1865 frame@17c27000 { 1866 frame-number = <3>; 1867 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1868 reg = <0x17c27000 0x1000>; 1869 status = "disabled"; 1870 }; 1871 1872 frame@17c29000 { 1873 frame-number = <4>; 1874 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1875 reg = <0x17c29000 0x1000>; 1876 status = "disabled"; 1877 }; 1878 1879 frame@17c2b000 { 1880 frame-number = <5>; 1881 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1882 reg = <0x17c2b000 0x1000>; 1883 status = "disabled"; 1884 }; 1885 1886 frame@17c2d000 { 1887 frame-number = <6>; 1888 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1889 reg = <0x17c2d000 0x1000>; 1890 status = "disabled"; 1891 }; 1892 }; 1893 1894 wifi: wifi@18800000 { 1895 compatible = "qcom,wcn3990-wifi"; 1896 reg = <0 0x18800000 0 0x800000>; 1897 reg-names = "membase"; 1898 memory-region = <&wlan_fw_mem>; 1899 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1909 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1910 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 1911 iommus = <&apps_smmu 0x20 0x1>; 1912 qcom,msa-fixed-perm; 1913 status = "disabled"; 1914 }; 1915 1916 apps_rsc: rsc@18200000 { 1917 compatible = "qcom,rpmh-rsc"; 1918 label = "apps_rsc"; 1919 reg = <0x0 0x18200000 0x0 0x10000>, 1920 <0x0 0x18210000 0x0 0x10000>, 1921 <0x0 0x18220000 0x0 0x10000>; 1922 reg-names = "drv-0", "drv-1", "drv-2"; 1923 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1926 qcom,tcs-offset = <0xd00>; 1927 qcom,drv-id = <2>; 1928 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 1929 <WAKE_TCS 3>, <CONTROL_TCS 1>; 1930 1931 rpmhcc: clock-controller { 1932 compatible = "qcom,sm6350-rpmh-clk"; 1933 #clock-cells = <1>; 1934 clock-names = "xo"; 1935 clocks = <&xo_board>; 1936 }; 1937 1938 rpmhpd: power-controller { 1939 compatible = "qcom,sm6350-rpmhpd"; 1940 #power-domain-cells = <1>; 1941 operating-points-v2 = <&rpmhpd_opp_table>; 1942 1943 rpmhpd_opp_table: opp-table { 1944 compatible = "operating-points-v2"; 1945 1946 rpmhpd_opp_ret: opp1 { 1947 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1948 }; 1949 1950 rpmhpd_opp_min_svs: opp2 { 1951 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1952 }; 1953 1954 rpmhpd_opp_low_svs: opp3 { 1955 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1956 }; 1957 1958 rpmhpd_opp_svs: opp4 { 1959 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1960 }; 1961 1962 rpmhpd_opp_svs_l1: opp5 { 1963 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1964 }; 1965 1966 rpmhpd_opp_nom: opp6 { 1967 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1968 }; 1969 1970 rpmhpd_opp_nom_l1: opp7 { 1971 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1972 }; 1973 1974 rpmhpd_opp_nom_l2: opp8 { 1975 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1976 }; 1977 1978 rpmhpd_opp_turbo: opp9 { 1979 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1980 }; 1981 1982 rpmhpd_opp_turbo_l1: opp10 { 1983 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1984 }; 1985 }; 1986 }; 1987 1988 apps_bcm_voter: bcm-voter { 1989 compatible = "qcom,bcm-voter"; 1990 }; 1991 }; 1992 1993 osm_l3: interconnect@18321000 { 1994 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3"; 1995 reg = <0x0 0x18321000 0x0 0x1000>; 1996 1997 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 1998 clock-names = "xo", "alternate"; 1999 2000 #interconnect-cells = <1>; 2001 }; 2002 2003 cpufreq_hw: cpufreq@18323000 { 2004 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw"; 2005 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; 2006 reg-names = "freq-domain0", "freq-domain1"; 2007 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2008 clock-names = "xo", "alternate"; 2009 2010 #freq-domain-cells = <1>; 2011 #clock-cells = <1>; 2012 }; 2013 }; 2014 2015 timer { 2016 compatible = "arm,armv8-timer"; 2017 clock-frequency = <19200000>; 2018 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2019 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2020 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2021 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2022 }; 2023}; 2024