1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sm6350.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm6350-camcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interconnect/qcom,icc.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sm6350.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <76800000>; 31 clock-output-names = "xo_board"; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 clock-frequency = <32764>; 37 #clock-cells = <0>; 38 }; 39 }; 40 41 cpus { 42 #address-cells = <2>; 43 #size-cells = <0>; 44 45 CPU0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "qcom,kryo560"; 48 reg = <0x0 0x0>; 49 clocks = <&cpufreq_hw 0>; 50 enable-method = "psci"; 51 capacity-dmips-mhz = <1024>; 52 dynamic-power-coefficient = <100>; 53 next-level-cache = <&L2_0>; 54 qcom,freq-domain = <&cpufreq_hw 0>; 55 operating-points-v2 = <&cpu0_opp_table>; 56 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 57 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 58 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 59 power-domains = <&CPU_PD0>; 60 power-domain-names = "psci"; 61 #cooling-cells = <2>; 62 L2_0: l2-cache { 63 compatible = "cache"; 64 cache-level = <2>; 65 cache-unified; 66 next-level-cache = <&L3_0>; 67 L3_0: l3-cache { 68 compatible = "cache"; 69 cache-level = <3>; 70 cache-unified; 71 }; 72 }; 73 }; 74 75 CPU1: cpu@100 { 76 device_type = "cpu"; 77 compatible = "qcom,kryo560"; 78 reg = <0x0 0x100>; 79 clocks = <&cpufreq_hw 0>; 80 enable-method = "psci"; 81 capacity-dmips-mhz = <1024>; 82 dynamic-power-coefficient = <100>; 83 next-level-cache = <&L2_100>; 84 qcom,freq-domain = <&cpufreq_hw 0>; 85 operating-points-v2 = <&cpu0_opp_table>; 86 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 87 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 88 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 89 power-domains = <&CPU_PD1>; 90 power-domain-names = "psci"; 91 #cooling-cells = <2>; 92 L2_100: l2-cache { 93 compatible = "cache"; 94 cache-level = <2>; 95 cache-unified; 96 next-level-cache = <&L3_0>; 97 }; 98 }; 99 100 CPU2: cpu@200 { 101 device_type = "cpu"; 102 compatible = "qcom,kryo560"; 103 reg = <0x0 0x200>; 104 clocks = <&cpufreq_hw 0>; 105 enable-method = "psci"; 106 capacity-dmips-mhz = <1024>; 107 dynamic-power-coefficient = <100>; 108 next-level-cache = <&L2_200>; 109 qcom,freq-domain = <&cpufreq_hw 0>; 110 operating-points-v2 = <&cpu0_opp_table>; 111 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 112 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 113 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 114 power-domains = <&CPU_PD2>; 115 power-domain-names = "psci"; 116 #cooling-cells = <2>; 117 L2_200: l2-cache { 118 compatible = "cache"; 119 cache-level = <2>; 120 cache-unified; 121 next-level-cache = <&L3_0>; 122 }; 123 }; 124 125 CPU3: cpu@300 { 126 device_type = "cpu"; 127 compatible = "qcom,kryo560"; 128 reg = <0x0 0x300>; 129 clocks = <&cpufreq_hw 0>; 130 enable-method = "psci"; 131 capacity-dmips-mhz = <1024>; 132 dynamic-power-coefficient = <100>; 133 next-level-cache = <&L2_300>; 134 qcom,freq-domain = <&cpufreq_hw 0>; 135 operating-points-v2 = <&cpu0_opp_table>; 136 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 137 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 138 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 139 power-domains = <&CPU_PD3>; 140 power-domain-names = "psci"; 141 #cooling-cells = <2>; 142 L2_300: l2-cache { 143 compatible = "cache"; 144 cache-level = <2>; 145 cache-unified; 146 next-level-cache = <&L3_0>; 147 }; 148 }; 149 150 CPU4: cpu@400 { 151 device_type = "cpu"; 152 compatible = "qcom,kryo560"; 153 reg = <0x0 0x400>; 154 clocks = <&cpufreq_hw 0>; 155 enable-method = "psci"; 156 capacity-dmips-mhz = <1024>; 157 dynamic-power-coefficient = <100>; 158 next-level-cache = <&L2_400>; 159 qcom,freq-domain = <&cpufreq_hw 0>; 160 operating-points-v2 = <&cpu0_opp_table>; 161 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 162 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 163 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 164 power-domains = <&CPU_PD4>; 165 power-domain-names = "psci"; 166 #cooling-cells = <2>; 167 L2_400: l2-cache { 168 compatible = "cache"; 169 cache-level = <2>; 170 cache-unified; 171 next-level-cache = <&L3_0>; 172 }; 173 }; 174 175 CPU5: cpu@500 { 176 device_type = "cpu"; 177 compatible = "qcom,kryo560"; 178 reg = <0x0 0x500>; 179 clocks = <&cpufreq_hw 0>; 180 enable-method = "psci"; 181 capacity-dmips-mhz = <1024>; 182 dynamic-power-coefficient = <100>; 183 next-level-cache = <&L2_500>; 184 qcom,freq-domain = <&cpufreq_hw 0>; 185 operating-points-v2 = <&cpu0_opp_table>; 186 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 187 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 188 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 189 power-domains = <&CPU_PD5>; 190 power-domain-names = "psci"; 191 #cooling-cells = <2>; 192 L2_500: l2-cache { 193 compatible = "cache"; 194 cache-level = <2>; 195 cache-unified; 196 next-level-cache = <&L3_0>; 197 }; 198 }; 199 200 CPU6: cpu@600 { 201 device_type = "cpu"; 202 compatible = "qcom,kryo560"; 203 reg = <0x0 0x600>; 204 clocks = <&cpufreq_hw 1>; 205 enable-method = "psci"; 206 capacity-dmips-mhz = <1894>; 207 dynamic-power-coefficient = <703>; 208 next-level-cache = <&L2_600>; 209 qcom,freq-domain = <&cpufreq_hw 1>; 210 operating-points-v2 = <&cpu6_opp_table>; 211 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 212 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 213 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 214 power-domains = <&CPU_PD6>; 215 power-domain-names = "psci"; 216 #cooling-cells = <2>; 217 L2_600: l2-cache { 218 compatible = "cache"; 219 cache-level = <2>; 220 cache-unified; 221 next-level-cache = <&L3_0>; 222 }; 223 }; 224 225 CPU7: cpu@700 { 226 device_type = "cpu"; 227 compatible = "qcom,kryo560"; 228 reg = <0x0 0x700>; 229 clocks = <&cpufreq_hw 1>; 230 enable-method = "psci"; 231 capacity-dmips-mhz = <1894>; 232 dynamic-power-coefficient = <703>; 233 next-level-cache = <&L2_700>; 234 qcom,freq-domain = <&cpufreq_hw 1>; 235 operating-points-v2 = <&cpu6_opp_table>; 236 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 237 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 238 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 239 power-domains = <&CPU_PD7>; 240 power-domain-names = "psci"; 241 #cooling-cells = <2>; 242 L2_700: l2-cache { 243 compatible = "cache"; 244 cache-level = <2>; 245 cache-unified; 246 next-level-cache = <&L3_0>; 247 }; 248 }; 249 250 cpu-map { 251 cluster0 { 252 core0 { 253 cpu = <&CPU0>; 254 }; 255 256 core1 { 257 cpu = <&CPU1>; 258 }; 259 260 core2 { 261 cpu = <&CPU2>; 262 }; 263 264 core3 { 265 cpu = <&CPU3>; 266 }; 267 268 core4 { 269 cpu = <&CPU4>; 270 }; 271 272 core5 { 273 cpu = <&CPU5>; 274 }; 275 276 core6 { 277 cpu = <&CPU6>; 278 }; 279 280 core7 { 281 cpu = <&CPU7>; 282 }; 283 }; 284 }; 285 286 domain-idle-states { 287 CLUSTER_SLEEP_PC: cluster-sleep-0 { 288 compatible = "domain-idle-state"; 289 arm,psci-suspend-param = <0x41000044>; 290 entry-latency-us = <2752>; 291 exit-latency-us = <3048>; 292 min-residency-us = <6118>; 293 }; 294 295 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { 296 compatible = "domain-idle-state"; 297 arm,psci-suspend-param = <0x41001244>; 298 entry-latency-us = <3638>; 299 exit-latency-us = <4562>; 300 min-residency-us = <8467>; 301 }; 302 303 CLUSTER_AOSS_SLEEP: cluster-sleep-2 { 304 compatible = "domain-idle-state"; 305 arm,psci-suspend-param = <0x4100b244>; 306 entry-latency-us = <3263>; 307 exit-latency-us = <6562>; 308 min-residency-us = <9987>; 309 }; 310 }; 311 312 cpu_idle_states: idle-states { 313 entry-method = "psci"; 314 315 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 316 compatible = "arm,idle-state"; 317 idle-state-name = "little-power-collapse"; 318 arm,psci-suspend-param = <0x40000003>; 319 entry-latency-us = <549>; 320 exit-latency-us = <901>; 321 min-residency-us = <1774>; 322 local-timer-stop; 323 }; 324 325 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 326 compatible = "arm,idle-state"; 327 idle-state-name = "little-rail-power-collapse"; 328 arm,psci-suspend-param = <0x40000004>; 329 entry-latency-us = <702>; 330 exit-latency-us = <915>; 331 min-residency-us = <4001>; 332 local-timer-stop; 333 }; 334 335 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 336 compatible = "arm,idle-state"; 337 idle-state-name = "big-power-collapse"; 338 arm,psci-suspend-param = <0x40000003>; 339 entry-latency-us = <523>; 340 exit-latency-us = <1244>; 341 min-residency-us = <2207>; 342 local-timer-stop; 343 }; 344 345 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 346 compatible = "arm,idle-state"; 347 idle-state-name = "big-rail-power-collapse"; 348 arm,psci-suspend-param = <0x40000004>; 349 entry-latency-us = <526>; 350 exit-latency-us = <1854>; 351 min-residency-us = <5555>; 352 local-timer-stop; 353 }; 354 }; 355 }; 356 357 firmware { 358 scm: scm { 359 compatible = "qcom,scm-sm6350", "qcom,scm"; 360 #reset-cells = <1>; 361 }; 362 }; 363 364 memory@80000000 { 365 device_type = "memory"; 366 /* We expect the bootloader to fill in the size */ 367 reg = <0x0 0x80000000 0x0 0x0>; 368 }; 369 370 cpu0_opp_table: opp-table-cpu0 { 371 compatible = "operating-points-v2"; 372 opp-shared; 373 374 opp-300000000 { 375 opp-hz = /bits/ 64 <300000000>; 376 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ 377 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 378 }; 379 380 opp-576000000 { 381 opp-hz = /bits/ 64 <576000000>; 382 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>; 383 }; 384 385 opp-768000000 { 386 opp-hz = /bits/ 64 <768000000>; 387 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 388 }; 389 390 opp-1017600000 { 391 opp-hz = /bits/ 64 <1017600000>; 392 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 393 }; 394 395 opp-1248000000 { 396 opp-hz = /bits/ 64 <1248000000>; 397 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 398 }; 399 400 opp-1324800000 { 401 opp-hz = /bits/ 64 <1324800000>; 402 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>; 403 }; 404 405 opp-1516800000 { 406 opp-hz = /bits/ 64 <1516800000>; 407 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 408 }; 409 410 opp-1612800000 { 411 opp-hz = /bits/ 64 <1612800000>; 412 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 413 }; 414 415 opp-1708800000 { 416 opp-hz = /bits/ 64 <1708800000>; 417 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 418 }; 419 }; 420 421 cpu6_opp_table: opp-table-cpu6 { 422 compatible = "operating-points-v2"; 423 opp-shared; 424 425 opp-300000000 { 426 opp-hz = /bits/ 64 <300000000>; 427 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 428 }; 429 430 opp-787200000 { 431 opp-hz = /bits/ 64 <787200000>; 432 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 433 }; 434 435 opp-979200000 { 436 opp-hz = /bits/ 64 <979200000>; 437 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>; 438 }; 439 440 opp-1036800000 { 441 opp-hz = /bits/ 64 <1036800000>; 442 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 443 }; 444 445 opp-1248000000 { 446 opp-hz = /bits/ 64 <1248000000>; 447 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 448 }; 449 450 opp-1401600000 { 451 opp-hz = /bits/ 64 <1401600000>; 452 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>; 453 }; 454 455 opp-1555200000 { 456 opp-hz = /bits/ 64 <1555200000>; 457 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 458 }; 459 460 opp-1766400000 { 461 opp-hz = /bits/ 64 <1766400000>; 462 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 463 }; 464 465 opp-1900800000 { 466 opp-hz = /bits/ 64 <1900800000>; 467 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 468 }; 469 470 opp-2073600000 { 471 opp-hz = /bits/ 64 <2073600000>; 472 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 473 }; 474 }; 475 476 qup_opp_table: opp-table-qup { 477 compatible = "operating-points-v2"; 478 479 opp-75000000 { 480 opp-hz = /bits/ 64 <75000000>; 481 required-opps = <&rpmhpd_opp_low_svs>; 482 }; 483 484 opp-100000000 { 485 opp-hz = /bits/ 64 <100000000>; 486 required-opps = <&rpmhpd_opp_svs>; 487 }; 488 489 opp-128000000 { 490 opp-hz = /bits/ 64 <128000000>; 491 required-opps = <&rpmhpd_opp_nom>; 492 }; 493 }; 494 495 pmu { 496 compatible = "arm,armv8-pmuv3"; 497 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 498 }; 499 500 psci { 501 compatible = "arm,psci-1.0"; 502 method = "smc"; 503 504 CPU_PD0: power-domain-cpu0 { 505 #power-domain-cells = <0>; 506 power-domains = <&CLUSTER_PD>; 507 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 508 }; 509 510 CPU_PD1: power-domain-cpu1 { 511 #power-domain-cells = <0>; 512 power-domains = <&CLUSTER_PD>; 513 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 514 }; 515 516 CPU_PD2: power-domain-cpu2 { 517 #power-domain-cells = <0>; 518 power-domains = <&CLUSTER_PD>; 519 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 520 }; 521 522 CPU_PD3: power-domain-cpu3 { 523 #power-domain-cells = <0>; 524 power-domains = <&CLUSTER_PD>; 525 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 526 }; 527 528 CPU_PD4: power-domain-cpu4 { 529 #power-domain-cells = <0>; 530 power-domains = <&CLUSTER_PD>; 531 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 532 }; 533 534 CPU_PD5: power-domain-cpu5 { 535 #power-domain-cells = <0>; 536 power-domains = <&CLUSTER_PD>; 537 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 538 }; 539 540 CPU_PD6: power-domain-cpu6 { 541 #power-domain-cells = <0>; 542 power-domains = <&CLUSTER_PD>; 543 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 544 }; 545 546 CPU_PD7: power-domain-cpu7 { 547 #power-domain-cells = <0>; 548 power-domains = <&CLUSTER_PD>; 549 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 550 }; 551 552 CLUSTER_PD: power-domain-cpu-cluster0 { 553 #power-domain-cells = <0>; 554 domain-idle-states = <&CLUSTER_SLEEP_PC 555 &CLUSTER_SLEEP_CX_RET 556 &CLUSTER_AOSS_SLEEP>; 557 }; 558 }; 559 560 reserved_memory: reserved-memory { 561 #address-cells = <2>; 562 #size-cells = <2>; 563 ranges; 564 565 hyp_mem: memory@80000000 { 566 reg = <0 0x80000000 0 0x600000>; 567 no-map; 568 }; 569 570 xbl_aop_mem: memory@80700000 { 571 reg = <0 0x80700000 0 0x160000>; 572 no-map; 573 }; 574 575 cmd_db: memory@80860000 { 576 compatible = "qcom,cmd-db"; 577 reg = <0 0x80860000 0 0x20000>; 578 no-map; 579 }; 580 581 sec_apps_mem: memory@808ff000 { 582 reg = <0 0x808ff000 0 0x1000>; 583 no-map; 584 }; 585 586 smem_mem: memory@80900000 { 587 reg = <0 0x80900000 0 0x200000>; 588 no-map; 589 }; 590 591 cdsp_sec_mem: memory@80b00000 { 592 reg = <0 0x80b00000 0 0x1e00000>; 593 no-map; 594 }; 595 596 pil_camera_mem: memory@86000000 { 597 reg = <0 0x86000000 0 0x500000>; 598 no-map; 599 }; 600 601 pil_npu_mem: memory@86500000 { 602 reg = <0 0x86500000 0 0x500000>; 603 no-map; 604 }; 605 606 pil_video_mem: memory@86a00000 { 607 reg = <0 0x86a00000 0 0x500000>; 608 no-map; 609 }; 610 611 pil_cdsp_mem: memory@86f00000 { 612 reg = <0 0x86f00000 0 0x1e00000>; 613 no-map; 614 }; 615 616 pil_adsp_mem: memory@88d00000 { 617 reg = <0 0x88d00000 0 0x2800000>; 618 no-map; 619 }; 620 621 wlan_fw_mem: memory@8b500000 { 622 reg = <0 0x8b500000 0 0x200000>; 623 no-map; 624 }; 625 626 pil_ipa_fw_mem: memory@8b700000 { 627 reg = <0 0x8b700000 0 0x10000>; 628 no-map; 629 }; 630 631 pil_ipa_gsi_mem: memory@8b710000 { 632 reg = <0 0x8b710000 0 0x5400>; 633 no-map; 634 }; 635 636 pil_gpu_mem: memory@8b715400 { 637 reg = <0 0x8b715400 0 0x2000>; 638 no-map; 639 }; 640 641 pil_modem_mem: memory@8b800000 { 642 reg = <0 0x8b800000 0 0xf800000>; 643 no-map; 644 }; 645 646 cont_splash_memory: memory@a0000000 { 647 reg = <0 0xa0000000 0 0x2300000>; 648 no-map; 649 }; 650 651 dfps_data_memory: memory@a2300000 { 652 reg = <0 0xa2300000 0 0x100000>; 653 no-map; 654 }; 655 656 removed_region: memory@c0000000 { 657 reg = <0 0xc0000000 0 0x3900000>; 658 no-map; 659 }; 660 661 debug_region: memory@ffb00000 { 662 reg = <0 0xffb00000 0 0xc0000>; 663 no-map; 664 }; 665 666 last_log_region: memory@ffbc0000 { 667 reg = <0 0xffbc0000 0 0x40000>; 668 no-map; 669 }; 670 671 ramoops: ramoops@ffc00000 { 672 compatible = "ramoops"; 673 reg = <0 0xffc00000 0 0x100000>; 674 record-size = <0x1000>; 675 console-size = <0x40000>; 676 msg-size = <0x20000 0x20000>; 677 ecc-size = <16>; 678 no-map; 679 }; 680 681 cmdline_region: memory@ffd00000 { 682 reg = <0 0xffd00000 0 0x1000>; 683 no-map; 684 }; 685 }; 686 687 smem { 688 compatible = "qcom,smem"; 689 memory-region = <&smem_mem>; 690 hwlocks = <&tcsr_mutex 3>; 691 }; 692 693 smp2p-adsp { 694 compatible = "qcom,smp2p"; 695 qcom,smem = <443>, <429>; 696 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 697 IPCC_MPROC_SIGNAL_SMP2P 698 IRQ_TYPE_EDGE_RISING>; 699 mboxes = <&ipcc IPCC_CLIENT_LPASS 700 IPCC_MPROC_SIGNAL_SMP2P>; 701 702 qcom,local-pid = <0>; 703 qcom,remote-pid = <2>; 704 705 smp2p_adsp_out: master-kernel { 706 qcom,entry-name = "master-kernel"; 707 #qcom,smem-state-cells = <1>; 708 }; 709 710 smp2p_adsp_in: slave-kernel { 711 qcom,entry-name = "slave-kernel"; 712 interrupt-controller; 713 #interrupt-cells = <2>; 714 }; 715 }; 716 717 smp2p-cdsp { 718 compatible = "qcom,smp2p"; 719 qcom,smem = <94>, <432>; 720 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 721 IPCC_MPROC_SIGNAL_SMP2P 722 IRQ_TYPE_EDGE_RISING>; 723 mboxes = <&ipcc IPCC_CLIENT_CDSP 724 IPCC_MPROC_SIGNAL_SMP2P>; 725 726 qcom,local-pid = <0>; 727 qcom,remote-pid = <5>; 728 729 smp2p_cdsp_out: master-kernel { 730 qcom,entry-name = "master-kernel"; 731 #qcom,smem-state-cells = <1>; 732 }; 733 734 smp2p_cdsp_in: slave-kernel { 735 qcom,entry-name = "slave-kernel"; 736 interrupt-controller; 737 #interrupt-cells = <2>; 738 }; 739 }; 740 741 smp2p-mpss { 742 compatible = "qcom,smp2p"; 743 qcom,smem = <435>, <428>; 744 745 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 746 IPCC_MPROC_SIGNAL_SMP2P 747 IRQ_TYPE_EDGE_RISING>; 748 mboxes = <&ipcc IPCC_CLIENT_MPSS 749 IPCC_MPROC_SIGNAL_SMP2P>; 750 751 qcom,local-pid = <0>; 752 qcom,remote-pid = <1>; 753 754 modem_smp2p_out: master-kernel { 755 qcom,entry-name = "master-kernel"; 756 #qcom,smem-state-cells = <1>; 757 }; 758 759 modem_smp2p_in: slave-kernel { 760 qcom,entry-name = "slave-kernel"; 761 interrupt-controller; 762 #interrupt-cells = <2>; 763 }; 764 765 ipa_smp2p_out: ipa-ap-to-modem { 766 qcom,entry-name = "ipa"; 767 #qcom,smem-state-cells = <1>; 768 }; 769 770 ipa_smp2p_in: ipa-modem-to-ap { 771 qcom,entry-name = "ipa"; 772 interrupt-controller; 773 #interrupt-cells = <2>; 774 }; 775 }; 776 777 soc: soc@0 { 778 #address-cells = <2>; 779 #size-cells = <2>; 780 ranges = <0 0 0 0 0x10 0>; 781 dma-ranges = <0 0 0 0 0x10 0>; 782 compatible = "simple-bus"; 783 784 gcc: clock-controller@100000 { 785 compatible = "qcom,gcc-sm6350"; 786 reg = <0 0x00100000 0 0x1f0000>; 787 #clock-cells = <1>; 788 #reset-cells = <1>; 789 #power-domain-cells = <1>; 790 clock-names = "bi_tcxo", 791 "bi_tcxo_ao", 792 "sleep_clk"; 793 clocks = <&rpmhcc RPMH_CXO_CLK>, 794 <&rpmhcc RPMH_CXO_CLK_A>, 795 <&sleep_clk>; 796 }; 797 798 ipcc: mailbox@408000 { 799 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 800 reg = <0 0x00408000 0 0x1000>; 801 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 802 interrupt-controller; 803 #interrupt-cells = <3>; 804 #mbox-cells = <2>; 805 }; 806 807 rng: rng@793000 { 808 compatible = "qcom,prng-ee"; 809 reg = <0 0x00793000 0 0x1000>; 810 clocks = <&gcc GCC_PRNG_AHB_CLK>; 811 clock-names = "core"; 812 }; 813 814 sdhc_1: mmc@7c4000 { 815 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 816 reg = <0 0x007c4000 0 0x1000>, 817 <0 0x007c5000 0 0x1000>, 818 <0 0x007c8000 0 0x8000>; 819 reg-names = "hc", "cqhci", "ice"; 820 821 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 823 interrupt-names = "hc_irq", "pwr_irq"; 824 iommus = <&apps_smmu 0x60 0x0>; 825 826 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 827 <&gcc GCC_SDCC1_APPS_CLK>, 828 <&rpmhcc RPMH_CXO_CLK>; 829 clock-names = "iface", "core", "xo"; 830 resets = <&gcc GCC_SDCC1_BCR>; 831 qcom,dll-config = <0x000f642c>; 832 qcom,ddr-config = <0x80040868>; 833 power-domains = <&rpmhpd SM6350_CX>; 834 operating-points-v2 = <&sdhc1_opp_table>; 835 bus-width = <8>; 836 non-removable; 837 supports-cqe; 838 839 status = "disabled"; 840 841 sdhc1_opp_table: opp-table { 842 compatible = "operating-points-v2"; 843 844 opp-19200000 { 845 opp-hz = /bits/ 64 <19200000>; 846 required-opps = <&rpmhpd_opp_min_svs>; 847 }; 848 849 opp-100000000 { 850 opp-hz = /bits/ 64 <100000000>; 851 required-opps = <&rpmhpd_opp_low_svs>; 852 }; 853 854 opp-384000000 { 855 opp-hz = /bits/ 64 <384000000>; 856 required-opps = <&rpmhpd_opp_svs_l1>; 857 }; 858 }; 859 }; 860 861 gpi_dma0: dma-controller@800000 { 862 compatible = "qcom,sm6350-gpi-dma"; 863 reg = <0 0x00800000 0 0x60000>; 864 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 874 dma-channels = <10>; 875 dma-channel-mask = <0x1f>; 876 iommus = <&apps_smmu 0x56 0x0>; 877 #dma-cells = <3>; 878 status = "disabled"; 879 }; 880 881 qupv3_id_0: geniqup@8c0000 { 882 compatible = "qcom,geni-se-qup"; 883 reg = <0x0 0x008c0000 0x0 0x2000>; 884 clock-names = "m-ahb", "s-ahb"; 885 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 886 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 887 #address-cells = <2>; 888 #size-cells = <2>; 889 iommus = <&apps_smmu 0x43 0x0>; 890 ranges; 891 status = "disabled"; 892 893 i2c0: i2c@880000 { 894 compatible = "qcom,geni-i2c"; 895 reg = <0 0x00880000 0 0x4000>; 896 clock-names = "se"; 897 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 898 pinctrl-names = "default"; 899 pinctrl-0 = <&qup_i2c0_default>; 900 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 901 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 902 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 903 dma-names = "tx", "rx"; 904 #address-cells = <1>; 905 #size-cells = <0>; 906 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 907 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 908 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 909 interconnect-names = "qup-core", "qup-config", "qup-memory"; 910 status = "disabled"; 911 }; 912 913 uart1: serial@884000 { 914 compatible = "qcom,geni-uart"; 915 reg = <0 0x00884000 0 0x4000>; 916 clock-names = "se"; 917 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 918 pinctrl-names = "default"; 919 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 920 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 921 power-domains = <&rpmhpd SM6350_CX>; 922 operating-points-v2 = <&qup_opp_table>; 923 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 924 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 925 interconnect-names = "qup-core", "qup-config"; 926 status = "disabled"; 927 }; 928 929 i2c2: i2c@888000 { 930 compatible = "qcom,geni-i2c"; 931 reg = <0 0x00888000 0 0x4000>; 932 clock-names = "se"; 933 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 934 pinctrl-names = "default"; 935 pinctrl-0 = <&qup_i2c2_default>; 936 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 937 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 938 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 939 dma-names = "tx", "rx"; 940 #address-cells = <1>; 941 #size-cells = <0>; 942 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 943 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 944 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 945 interconnect-names = "qup-core", "qup-config", "qup-memory"; 946 status = "disabled"; 947 }; 948 }; 949 950 gpi_dma1: dma-controller@900000 { 951 compatible = "qcom,sm6350-gpi-dma"; 952 reg = <0 0x00900000 0 0x60000>; 953 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 963 dma-channels = <10>; 964 dma-channel-mask = <0x3f>; 965 iommus = <&apps_smmu 0x4d6 0x0>; 966 #dma-cells = <3>; 967 status = "disabled"; 968 }; 969 970 qupv3_id_1: geniqup@9c0000 { 971 compatible = "qcom,geni-se-qup"; 972 reg = <0x0 0x009c0000 0x0 0x2000>; 973 clock-names = "m-ahb", "s-ahb"; 974 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 975 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 976 #address-cells = <2>; 977 #size-cells = <2>; 978 iommus = <&apps_smmu 0x4c3 0x0>; 979 ranges; 980 status = "disabled"; 981 982 i2c6: i2c@980000 { 983 compatible = "qcom,geni-i2c"; 984 reg = <0 0x00980000 0 0x4000>; 985 clock-names = "se"; 986 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 987 pinctrl-names = "default"; 988 pinctrl-0 = <&qup_i2c6_default>; 989 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 990 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 991 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 992 dma-names = "tx", "rx"; 993 #address-cells = <1>; 994 #size-cells = <0>; 995 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 996 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 997 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 998 interconnect-names = "qup-core", "qup-config", "qup-memory"; 999 status = "disabled"; 1000 }; 1001 1002 i2c7: i2c@984000 { 1003 compatible = "qcom,geni-i2c"; 1004 reg = <0 0x00984000 0 0x4000>; 1005 clock-names = "se"; 1006 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1007 pinctrl-names = "default"; 1008 pinctrl-0 = <&qup_i2c7_default>; 1009 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1010 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1011 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1012 dma-names = "tx", "rx"; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1016 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1017 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1018 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1019 status = "disabled"; 1020 }; 1021 1022 i2c8: i2c@988000 { 1023 compatible = "qcom,geni-i2c"; 1024 reg = <0 0x00988000 0 0x4000>; 1025 clock-names = "se"; 1026 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1027 pinctrl-names = "default"; 1028 pinctrl-0 = <&qup_i2c8_default>; 1029 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1030 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1031 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1032 dma-names = "tx", "rx"; 1033 #address-cells = <1>; 1034 #size-cells = <0>; 1035 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1036 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1037 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1038 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1039 status = "disabled"; 1040 }; 1041 1042 uart9: serial@98c000 { 1043 compatible = "qcom,geni-debug-uart"; 1044 reg = <0 0x0098c000 0 0x4000>; 1045 clock-names = "se"; 1046 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1047 pinctrl-names = "default"; 1048 pinctrl-0 = <&qup_uart9_default>; 1049 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1050 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1051 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1052 interconnect-names = "qup-core", "qup-config"; 1053 status = "disabled"; 1054 }; 1055 1056 i2c10: i2c@990000 { 1057 compatible = "qcom,geni-i2c"; 1058 reg = <0 0x00990000 0 0x4000>; 1059 clock-names = "se"; 1060 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1061 pinctrl-names = "default"; 1062 pinctrl-0 = <&qup_i2c10_default>; 1063 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1064 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1065 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1066 dma-names = "tx", "rx"; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1070 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1071 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1072 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1073 status = "disabled"; 1074 }; 1075 }; 1076 1077 config_noc: interconnect@1500000 { 1078 compatible = "qcom,sm6350-config-noc"; 1079 reg = <0 0x01500000 0 0x28000>; 1080 #interconnect-cells = <2>; 1081 qcom,bcm-voters = <&apps_bcm_voter>; 1082 }; 1083 1084 system_noc: interconnect@1620000 { 1085 compatible = "qcom,sm6350-system-noc"; 1086 reg = <0 0x01620000 0 0x17080>; 1087 #interconnect-cells = <2>; 1088 qcom,bcm-voters = <&apps_bcm_voter>; 1089 1090 clk_virt: interconnect-clk-virt { 1091 compatible = "qcom,sm6350-clk-virt"; 1092 #interconnect-cells = <2>; 1093 qcom,bcm-voters = <&apps_bcm_voter>; 1094 }; 1095 }; 1096 1097 aggre1_noc: interconnect@16e0000 { 1098 compatible = "qcom,sm6350-aggre1-noc"; 1099 reg = <0 0x016e0000 0 0x15080>; 1100 #interconnect-cells = <2>; 1101 qcom,bcm-voters = <&apps_bcm_voter>; 1102 }; 1103 1104 aggre2_noc: interconnect@1700000 { 1105 compatible = "qcom,sm6350-aggre2-noc"; 1106 reg = <0 0x01700000 0 0x1f880>; 1107 #interconnect-cells = <2>; 1108 qcom,bcm-voters = <&apps_bcm_voter>; 1109 1110 compute_noc: interconnect-compute-noc { 1111 compatible = "qcom,sm6350-compute-noc"; 1112 #interconnect-cells = <2>; 1113 qcom,bcm-voters = <&apps_bcm_voter>; 1114 }; 1115 }; 1116 1117 mmss_noc: interconnect@1740000 { 1118 compatible = "qcom,sm6350-mmss-noc"; 1119 reg = <0 0x01740000 0 0x1c100>; 1120 #interconnect-cells = <2>; 1121 qcom,bcm-voters = <&apps_bcm_voter>; 1122 }; 1123 1124 ufs_mem_hc: ufs@1d84000 { 1125 compatible = "qcom,sm6350-ufshc", "qcom,ufshc", 1126 "jedec,ufs-2.0"; 1127 reg = <0 0x01d84000 0 0x3000>, 1128 <0 0x01d90000 0 0x8000>; 1129 reg-names = "std", "ice"; 1130 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1131 phys = <&ufs_mem_phy_lanes>; 1132 phy-names = "ufsphy"; 1133 lanes-per-direction = <2>; 1134 #reset-cells = <1>; 1135 resets = <&gcc GCC_UFS_PHY_BCR>; 1136 reset-names = "rst"; 1137 1138 power-domains = <&gcc UFS_PHY_GDSC>; 1139 1140 iommus = <&apps_smmu 0x80 0x0>; 1141 1142 clock-names = "core_clk", 1143 "bus_aggr_clk", 1144 "iface_clk", 1145 "core_clk_unipro", 1146 "ref_clk", 1147 "tx_lane0_sync_clk", 1148 "rx_lane0_sync_clk", 1149 "rx_lane1_sync_clk", 1150 "ice_core_clk"; 1151 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1152 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1153 <&gcc GCC_UFS_PHY_AHB_CLK>, 1154 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1155 <&rpmhcc RPMH_QLINK_CLK>, 1156 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1157 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1158 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 1159 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1160 freq-table-hz = 1161 <50000000 200000000>, 1162 <0 0>, 1163 <0 0>, 1164 <37500000 150000000>, 1165 <75000000 300000000>, 1166 <0 0>, 1167 <0 0>, 1168 <0 0>, 1169 <0 0>; 1170 1171 status = "disabled"; 1172 }; 1173 1174 ufs_mem_phy: phy@1d87000 { 1175 compatible = "qcom,sm6350-qmp-ufs-phy"; 1176 reg = <0 0x01d87000 0 0x18c>; 1177 #address-cells = <2>; 1178 #size-cells = <2>; 1179 ranges; 1180 1181 clock-names = "ref", 1182 "ref_aux"; 1183 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 1184 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1185 1186 resets = <&ufs_mem_hc 0>; 1187 reset-names = "ufsphy"; 1188 1189 status = "disabled"; 1190 1191 ufs_mem_phy_lanes: phy@1d87400 { 1192 reg = <0 0x01d87400 0 0x128>, 1193 <0 0x01d87600 0 0x1fc>, 1194 <0 0x01d87c00 0 0x1dc>, 1195 <0 0x01d87800 0 0x128>, 1196 <0 0x01d87a00 0 0x1fc>; 1197 #phy-cells = <0>; 1198 }; 1199 }; 1200 1201 ipa: ipa@1e40000 { 1202 compatible = "qcom,sm6350-ipa"; 1203 1204 iommus = <&apps_smmu 0x440 0x0>, 1205 <&apps_smmu 0x442 0x0>; 1206 reg = <0 0x01e40000 0 0x8000>, 1207 <0 0x01e50000 0 0x3000>, 1208 <0 0x01e04000 0 0x23000>; 1209 reg-names = "ipa-reg", 1210 "ipa-shared", 1211 "gsi"; 1212 1213 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1214 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1215 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1216 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1217 interrupt-names = "ipa", 1218 "gsi", 1219 "ipa-clock-query", 1220 "ipa-setup-ready"; 1221 1222 clocks = <&rpmhcc RPMH_IPA_CLK>; 1223 clock-names = "core"; 1224 1225 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>, 1226 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, 1227 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; 1228 interconnect-names = "memory", "imem", "config"; 1229 1230 qcom,smem-states = <&ipa_smp2p_out 0>, 1231 <&ipa_smp2p_out 1>; 1232 qcom,smem-state-names = "ipa-clock-enabled-valid", 1233 "ipa-clock-enabled"; 1234 1235 status = "disabled"; 1236 }; 1237 1238 tcsr_mutex: hwlock@1f40000 { 1239 compatible = "qcom,tcsr-mutex"; 1240 reg = <0x0 0x01f40000 0x0 0x40000>; 1241 #hwlock-cells = <1>; 1242 }; 1243 1244 adsp: remoteproc@3000000 { 1245 compatible = "qcom,sm6350-adsp-pas"; 1246 reg = <0 0x03000000 0 0x100>; 1247 1248 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 1249 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1250 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1251 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1252 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1253 interrupt-names = "wdog", "fatal", "ready", 1254 "handover", "stop-ack"; 1255 1256 clocks = <&rpmhcc RPMH_CXO_CLK>; 1257 clock-names = "xo"; 1258 1259 power-domains = <&rpmhpd SM6350_LCX>, 1260 <&rpmhpd SM6350_LMX>; 1261 power-domain-names = "lcx", "lmx"; 1262 1263 memory-region = <&pil_adsp_mem>; 1264 1265 qcom,qmp = <&aoss_qmp>; 1266 1267 qcom,smem-states = <&smp2p_adsp_out 0>; 1268 qcom,smem-state-names = "stop"; 1269 1270 status = "disabled"; 1271 1272 glink-edge { 1273 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1274 IPCC_MPROC_SIGNAL_GLINK_QMP 1275 IRQ_TYPE_EDGE_RISING>; 1276 mboxes = <&ipcc IPCC_CLIENT_LPASS 1277 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1278 1279 label = "lpass"; 1280 qcom,remote-pid = <2>; 1281 1282 fastrpc { 1283 compatible = "qcom,fastrpc"; 1284 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1285 label = "adsp"; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 1289 compute-cb@3 { 1290 compatible = "qcom,fastrpc-compute-cb"; 1291 reg = <3>; 1292 iommus = <&apps_smmu 0x1003 0x0>; 1293 }; 1294 1295 compute-cb@4 { 1296 compatible = "qcom,fastrpc-compute-cb"; 1297 reg = <4>; 1298 iommus = <&apps_smmu 0x1004 0x0>; 1299 }; 1300 1301 compute-cb@5 { 1302 compatible = "qcom,fastrpc-compute-cb"; 1303 reg = <5>; 1304 iommus = <&apps_smmu 0x1005 0x0>; 1305 qcom,nsessions = <5>; 1306 }; 1307 }; 1308 }; 1309 }; 1310 1311 mpss: remoteproc@4080000 { 1312 compatible = "qcom,sm6350-mpss-pas"; 1313 reg = <0x0 0x04080000 0x0 0x4040>; 1314 1315 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 1316 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1317 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1318 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1319 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1320 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1321 interrupt-names = "wdog", "fatal", "ready", "handover", 1322 "stop-ack", "shutdown-ack"; 1323 1324 clocks = <&rpmhcc RPMH_CXO_CLK>; 1325 clock-names = "xo"; 1326 1327 power-domains = <&rpmhpd SM6350_CX>, 1328 <&rpmhpd SM6350_MSS>; 1329 power-domain-names = "cx", "mss"; 1330 1331 memory-region = <&pil_modem_mem>; 1332 1333 qcom,qmp = <&aoss_qmp>; 1334 1335 qcom,smem-states = <&modem_smp2p_out 0>; 1336 qcom,smem-state-names = "stop"; 1337 1338 status = "disabled"; 1339 1340 glink-edge { 1341 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1342 IPCC_MPROC_SIGNAL_GLINK_QMP 1343 IRQ_TYPE_EDGE_RISING>; 1344 mboxes = <&ipcc IPCC_CLIENT_MPSS 1345 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1346 label = "modem"; 1347 qcom,remote-pid = <1>; 1348 }; 1349 }; 1350 1351 cdsp: remoteproc@8300000 { 1352 compatible = "qcom,sm6350-cdsp-pas"; 1353 reg = <0 0x08300000 0 0x10000>; 1354 1355 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 1356 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1357 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1358 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1359 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1360 interrupt-names = "wdog", "fatal", "ready", 1361 "handover", "stop-ack"; 1362 1363 clocks = <&rpmhcc RPMH_CXO_CLK>; 1364 clock-names = "xo"; 1365 1366 power-domains = <&rpmhpd SM6350_CX>, 1367 <&rpmhpd SM6350_MX>; 1368 power-domain-names = "cx", "mx"; 1369 1370 memory-region = <&pil_cdsp_mem>; 1371 1372 qcom,qmp = <&aoss_qmp>; 1373 1374 qcom,smem-states = <&smp2p_cdsp_out 0>; 1375 qcom,smem-state-names = "stop"; 1376 1377 status = "disabled"; 1378 1379 glink-edge { 1380 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1381 IPCC_MPROC_SIGNAL_GLINK_QMP 1382 IRQ_TYPE_EDGE_RISING>; 1383 mboxes = <&ipcc IPCC_CLIENT_CDSP 1384 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1385 1386 label = "cdsp"; 1387 qcom,remote-pid = <5>; 1388 1389 fastrpc { 1390 compatible = "qcom,fastrpc"; 1391 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1392 label = "cdsp"; 1393 #address-cells = <1>; 1394 #size-cells = <0>; 1395 1396 compute-cb@1 { 1397 compatible = "qcom,fastrpc-compute-cb"; 1398 reg = <1>; 1399 iommus = <&apps_smmu 0x1401 0x20>; 1400 }; 1401 1402 compute-cb@2 { 1403 compatible = "qcom,fastrpc-compute-cb"; 1404 reg = <2>; 1405 iommus = <&apps_smmu 0x1402 0x20>; 1406 }; 1407 1408 compute-cb@3 { 1409 compatible = "qcom,fastrpc-compute-cb"; 1410 reg = <3>; 1411 iommus = <&apps_smmu 0x1403 0x20>; 1412 }; 1413 1414 compute-cb@4 { 1415 compatible = "qcom,fastrpc-compute-cb"; 1416 reg = <4>; 1417 iommus = <&apps_smmu 0x1404 0x20>; 1418 }; 1419 1420 compute-cb@5 { 1421 compatible = "qcom,fastrpc-compute-cb"; 1422 reg = <5>; 1423 iommus = <&apps_smmu 0x1405 0x20>; 1424 }; 1425 1426 compute-cb@6 { 1427 compatible = "qcom,fastrpc-compute-cb"; 1428 reg = <6>; 1429 iommus = <&apps_smmu 0x1406 0x20>; 1430 }; 1431 1432 compute-cb@7 { 1433 compatible = "qcom,fastrpc-compute-cb"; 1434 reg = <7>; 1435 iommus = <&apps_smmu 0x1407 0x20>; 1436 }; 1437 1438 compute-cb@8 { 1439 compatible = "qcom,fastrpc-compute-cb"; 1440 reg = <8>; 1441 iommus = <&apps_smmu 0x1408 0x20>; 1442 }; 1443 1444 /* note: secure cb9 in downstream */ 1445 }; 1446 }; 1447 }; 1448 1449 sdhc_2: mmc@8804000 { 1450 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 1451 reg = <0 0x08804000 0 0x1000>; 1452 1453 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1455 interrupt-names = "hc_irq", "pwr_irq"; 1456 iommus = <&apps_smmu 0x560 0x0>; 1457 1458 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1459 <&gcc GCC_SDCC2_APPS_CLK>, 1460 <&rpmhcc RPMH_CXO_CLK>; 1461 clock-names = "iface", "core", "xo"; 1462 resets = <&gcc GCC_SDCC2_BCR>; 1463 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, 1464 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; 1465 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1466 1467 pinctrl-0 = <&sdc2_on_state>; 1468 pinctrl-1 = <&sdc2_off_state>; 1469 pinctrl-names = "default", "sleep"; 1470 1471 qcom,dll-config = <0x0007642c>; 1472 qcom,ddr-config = <0x80040868>; 1473 power-domains = <&rpmhpd SM6350_CX>; 1474 operating-points-v2 = <&sdhc2_opp_table>; 1475 bus-width = <4>; 1476 1477 status = "disabled"; 1478 1479 sdhc2_opp_table: opp-table { 1480 compatible = "operating-points-v2"; 1481 1482 opp-100000000 { 1483 opp-hz = /bits/ 64 <100000000>; 1484 required-opps = <&rpmhpd_opp_svs_l1>; 1485 opp-peak-kBps = <790000 131000>; 1486 opp-avg-kBps = <50000 50000>; 1487 }; 1488 1489 opp-202000000 { 1490 opp-hz = /bits/ 64 <202000000>; 1491 required-opps = <&rpmhpd_opp_nom>; 1492 opp-peak-kBps = <3190000 294000>; 1493 opp-avg-kBps = <261438 300000>; 1494 }; 1495 }; 1496 }; 1497 1498 usb_1_hsphy: phy@88e3000 { 1499 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 1500 reg = <0 0x088e3000 0 0x400>; 1501 status = "disabled"; 1502 #phy-cells = <0>; 1503 1504 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 1505 clock-names = "cfg_ahb", "ref"; 1506 1507 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1508 }; 1509 1510 usb_1_qmpphy: phy@88e8000 { 1511 compatible = "qcom,sm6350-qmp-usb3-dp-phy"; 1512 reg = <0 0x088e8000 0 0x3000>; 1513 1514 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1515 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1516 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1517 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1518 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 1519 1520 power-domains = <&gcc USB30_PRIM_GDSC>; 1521 1522 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1523 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1524 reset-names = "phy", "common"; 1525 1526 #clock-cells = <1>; 1527 #phy-cells = <1>; 1528 1529 status = "disabled"; 1530 }; 1531 1532 dc_noc: interconnect@9160000 { 1533 compatible = "qcom,sm6350-dc-noc"; 1534 reg = <0 0x09160000 0 0x3200>; 1535 #interconnect-cells = <2>; 1536 qcom,bcm-voters = <&apps_bcm_voter>; 1537 }; 1538 1539 system-cache-controller@9200000 { 1540 compatible = "qcom,sm6350-llcc"; 1541 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 1542 reg-names = "llcc0_base", "llcc_broadcast_base"; 1543 }; 1544 1545 gem_noc: interconnect@9680000 { 1546 compatible = "qcom,sm6350-gem-noc"; 1547 reg = <0 0x09680000 0 0x3e200>; 1548 #interconnect-cells = <2>; 1549 qcom,bcm-voters = <&apps_bcm_voter>; 1550 }; 1551 1552 npu_noc: interconnect@9990000 { 1553 compatible = "qcom,sm6350-npu-noc"; 1554 reg = <0 0x09990000 0 0x1600>; 1555 #interconnect-cells = <2>; 1556 qcom,bcm-voters = <&apps_bcm_voter>; 1557 }; 1558 1559 usb_1: usb@a6f8800 { 1560 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 1561 reg = <0 0x0a6f8800 0 0x400>; 1562 status = "disabled"; 1563 #address-cells = <2>; 1564 #size-cells = <2>; 1565 ranges; 1566 1567 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1568 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1569 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1570 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1571 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1572 clock-names = "cfg_noc", 1573 "core", 1574 "iface", 1575 "sleep", 1576 "mock_utmi"; 1577 1578 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1579 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 1580 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1581 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 1582 1583 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1584 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1585 1586 power-domains = <&gcc USB30_PRIM_GDSC>; 1587 1588 resets = <&gcc GCC_USB30_PRIM_BCR>; 1589 1590 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, 1591 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1592 interconnect-names = "usb-ddr", "apps-usb"; 1593 1594 usb_1_dwc3: usb@a600000 { 1595 compatible = "snps,dwc3"; 1596 reg = <0 0x0a600000 0 0xcd00>; 1597 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1598 iommus = <&apps_smmu 0x540 0x0>; 1599 snps,dis_u2_susphy_quirk; 1600 snps,dis_enblslpm_quirk; 1601 snps,has-lpm-erratum; 1602 snps,hird-threshold = /bits/ 8 <0x10>; 1603 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 1604 phy-names = "usb2-phy", "usb3-phy"; 1605 }; 1606 }; 1607 1608 cci0: cci@ac4a000 { 1609 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 1610 reg = <0 0x0ac4a000 0 0x1000>; 1611 interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; 1612 power-domains = <&camcc TITAN_TOP_GDSC>; 1613 1614 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1615 <&camcc CAMCC_SOC_AHB_CLK>, 1616 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 1617 <&camcc CAMCC_CPAS_AHB_CLK>, 1618 <&camcc CAMCC_CCI_0_CLK>, 1619 <&camcc CAMCC_CCI_0_CLK_SRC>; 1620 clock-names = "camnoc_axi", 1621 "soc_ahb", 1622 "slow_ahb_src", 1623 "cpas_ahb", 1624 "cci", 1625 "cci_src"; 1626 1627 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1628 <&camcc CAMCC_CCI_0_CLK>; 1629 assigned-clock-rates = <80000000>, <37500000>; 1630 1631 pinctrl-0 = <&cci0_default &cci1_default>; 1632 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 1633 pinctrl-names = "default", "sleep"; 1634 1635 #address-cells = <1>; 1636 #size-cells = <0>; 1637 1638 status = "disabled"; 1639 1640 cci0_i2c0: i2c-bus@0 { 1641 reg = <0>; 1642 clock-frequency = <1000000>; 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 }; 1646 1647 cci0_i2c1: i2c-bus@1 { 1648 reg = <1>; 1649 clock-frequency = <1000000>; 1650 #address-cells = <1>; 1651 #size-cells = <0>; 1652 }; 1653 }; 1654 1655 cci1: cci@ac4b000 { 1656 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 1657 reg = <0 0x0ac4b000 0 0x1000>; 1658 interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; 1659 power-domains = <&camcc TITAN_TOP_GDSC>; 1660 1661 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1662 <&camcc CAMCC_SOC_AHB_CLK>, 1663 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 1664 <&camcc CAMCC_CPAS_AHB_CLK>, 1665 <&camcc CAMCC_CCI_1_CLK>, 1666 <&camcc CAMCC_CCI_1_CLK_SRC>; 1667 clock-names = "camnoc_axi", 1668 "soc_ahb", 1669 "slow_ahb_src", 1670 "cpas_ahb", 1671 "cci", 1672 "cci_src"; 1673 1674 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1675 <&camcc CAMCC_CCI_1_CLK>; 1676 assigned-clock-rates = <80000000>, <37500000>; 1677 1678 pinctrl-0 = <&cci2_default>; 1679 pinctrl-1 = <&cci2_sleep>; 1680 pinctrl-names = "default", "sleep"; 1681 1682 #address-cells = <1>; 1683 #size-cells = <0>; 1684 1685 status = "disabled"; 1686 1687 cci1_i2c0: i2c-bus@0 { 1688 reg = <0>; 1689 clock-frequency = <1000000>; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 }; 1693 1694 /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ 1695 }; 1696 1697 camcc: clock-controller@ad00000 { 1698 compatible = "qcom,sm6350-camcc"; 1699 reg = <0 0x0ad00000 0 0x16000>; 1700 clocks = <&rpmhcc RPMH_CXO_CLK>; 1701 #clock-cells = <1>; 1702 #reset-cells = <1>; 1703 #power-domain-cells = <1>; 1704 }; 1705 1706 pdc: interrupt-controller@b220000 { 1707 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 1708 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; 1709 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 1710 <125 63 1>, <126 655 12>, <138 139 15>; 1711 #interrupt-cells = <2>; 1712 interrupt-parent = <&intc>; 1713 interrupt-controller; 1714 }; 1715 1716 tsens0: thermal-sensor@c263000 { 1717 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1718 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1719 <0 0x0c222000 0 0x8>; /* SROT */ 1720 #qcom,sensors = <16>; 1721 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 1722 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 1723 interrupt-names = "uplow", "critical"; 1724 #thermal-sensor-cells = <1>; 1725 }; 1726 1727 tsens1: thermal-sensor@c265000 { 1728 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1729 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1730 <0 0x0c223000 0 0x8>; /* SROT */ 1731 #qcom,sensors = <16>; 1732 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 1733 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 1734 interrupt-names = "uplow", "critical"; 1735 #thermal-sensor-cells = <1>; 1736 }; 1737 1738 aoss_qmp: power-management@c300000 { 1739 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 1740 reg = <0 0x0c300000 0 0x1000>; 1741 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 1742 IRQ_TYPE_EDGE_RISING>; 1743 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 1744 1745 #clock-cells = <0>; 1746 }; 1747 1748 spmi_bus: spmi@c440000 { 1749 compatible = "qcom,spmi-pmic-arb"; 1750 reg = <0 0x0c440000 0 0x1100>, 1751 <0 0x0c600000 0 0x2000000>, 1752 <0 0x0e600000 0 0x100000>, 1753 <0 0x0e700000 0 0xa0000>, 1754 <0 0x0c40a000 0 0x26000>; 1755 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1756 interrupt-names = "periph_irq"; 1757 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1758 qcom,ee = <0>; 1759 qcom,channel = <0>; 1760 #address-cells = <2>; 1761 #size-cells = <0>; 1762 interrupt-controller; 1763 #interrupt-cells = <4>; 1764 }; 1765 1766 tlmm: pinctrl@f100000 { 1767 compatible = "qcom,sm6350-tlmm"; 1768 reg = <0 0x0f100000 0 0x300000>; 1769 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 1778 gpio-controller; 1779 #gpio-cells = <2>; 1780 interrupt-controller; 1781 #interrupt-cells = <2>; 1782 gpio-ranges = <&tlmm 0 0 157>; 1783 1784 cci0_default: cci0-default-state { 1785 pins = "gpio39", "gpio40"; 1786 function = "cci_i2c"; 1787 drive-strength = <2>; 1788 bias-pull-up; 1789 }; 1790 1791 cci0_sleep: cci0-sleep-state { 1792 pins = "gpio39", "gpio40"; 1793 function = "cci_i2c"; 1794 drive-strength = <2>; 1795 bias-pull-down; 1796 }; 1797 1798 cci1_default: cci1-default-state { 1799 pins = "gpio41", "gpio42"; 1800 function = "cci_i2c"; 1801 drive-strength = <2>; 1802 bias-pull-up; 1803 }; 1804 1805 cci1_sleep: cci1-sleep-state { 1806 pins = "gpio41", "gpio42"; 1807 function = "cci_i2c"; 1808 drive-strength = <2>; 1809 bias-pull-down; 1810 }; 1811 1812 cci2_default: cci2-default-state { 1813 pins = "gpio43", "gpio44"; 1814 function = "cci_i2c"; 1815 drive-strength = <2>; 1816 bias-pull-up; 1817 }; 1818 1819 cci2_sleep: cci2-sleep-state { 1820 pins = "gpio43", "gpio44"; 1821 function = "cci_i2c"; 1822 drive-strength = <2>; 1823 bias-pull-down; 1824 }; 1825 1826 sdc2_off_state: sdc2-off-state { 1827 clk-pins { 1828 pins = "sdc2_clk"; 1829 drive-strength = <2>; 1830 bias-disable; 1831 }; 1832 1833 cmd-pins { 1834 pins = "sdc2_cmd"; 1835 drive-strength = <2>; 1836 bias-pull-up; 1837 }; 1838 1839 data-pins { 1840 pins = "sdc2_data"; 1841 drive-strength = <2>; 1842 bias-pull-up; 1843 }; 1844 }; 1845 1846 sdc2_on_state: sdc2-on-state { 1847 clk-pins { 1848 pins = "sdc2_clk"; 1849 drive-strength = <16>; 1850 bias-disable; 1851 }; 1852 1853 cmd-pins { 1854 pins = "sdc2_cmd"; 1855 drive-strength = <10>; 1856 bias-pull-up; 1857 }; 1858 1859 data-pins { 1860 pins = "sdc2_data"; 1861 drive-strength = <10>; 1862 bias-pull-up; 1863 }; 1864 }; 1865 1866 qup_uart9_default: qup-uart9-default-state { 1867 pins = "gpio25", "gpio26"; 1868 function = "qup13_f2"; 1869 drive-strength = <2>; 1870 bias-disable; 1871 }; 1872 1873 qup_i2c0_default: qup-i2c0-default-state { 1874 pins = "gpio0", "gpio1"; 1875 function = "qup00"; 1876 drive-strength = <2>; 1877 bias-pull-up; 1878 }; 1879 1880 qup_i2c2_default: qup-i2c2-default-state { 1881 pins = "gpio45", "gpio46"; 1882 function = "qup02"; 1883 drive-strength = <2>; 1884 bias-pull-up; 1885 }; 1886 1887 qup_i2c6_default: qup-i2c6-default-state { 1888 pins = "gpio13", "gpio14"; 1889 function = "qup10"; 1890 drive-strength = <2>; 1891 bias-pull-up; 1892 }; 1893 1894 qup_i2c7_default: qup-i2c7-default-state { 1895 pins = "gpio27", "gpio28"; 1896 function = "qup11"; 1897 drive-strength = <2>; 1898 bias-pull-up; 1899 }; 1900 1901 qup_i2c8_default: qup-i2c8-default-state { 1902 pins = "gpio19", "gpio20"; 1903 function = "qup12"; 1904 drive-strength = <2>; 1905 bias-pull-up; 1906 }; 1907 1908 qup_i2c10_default: qup-i2c10-default-state { 1909 pins = "gpio4", "gpio5"; 1910 function = "qup14"; 1911 drive-strength = <2>; 1912 bias-pull-up; 1913 }; 1914 1915 qup_uart1_cts: qup-uart1-cts-default-state { 1916 pins = "gpio61"; 1917 function = "qup01"; 1918 drive-strength = <2>; 1919 bias-disable; 1920 }; 1921 1922 qup_uart1_rts: qup-uart1-rts-default-state { 1923 pins = "gpio62"; 1924 function = "qup01"; 1925 drive-strength = <2>; 1926 bias-pull-down; 1927 }; 1928 1929 qup_uart1_rx: qup-uart1-rx-default-state { 1930 pins = "gpio64"; 1931 function = "qup01"; 1932 drive-strength = <2>; 1933 bias-disable; 1934 }; 1935 1936 qup_uart1_tx: qup-uart1-tx-default-state { 1937 pins = "gpio63"; 1938 function = "qup01"; 1939 drive-strength = <2>; 1940 bias-pull-up; 1941 }; 1942 }; 1943 1944 apps_smmu: iommu@15000000 { 1945 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 1946 reg = <0 0x15000000 0 0x100000>; 1947 #iommu-cells = <2>; 1948 #global-interrupts = <1>; 1949 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1956 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1957 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1958 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1959 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1960 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1961 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1962 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1963 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1964 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1973 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1974 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1975 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1977 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1978 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1979 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1980 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1981 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1982 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1986 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1987 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1988 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1993 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1994 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1995 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1996 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1997 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1998 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1999 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2000 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2001 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2002 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2003 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2004 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2005 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2006 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2007 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2008 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2009 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2010 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2011 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2012 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2013 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2014 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2015 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2016 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2017 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2018 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2019 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2020 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2021 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2022 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2023 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2024 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2025 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2026 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 2027 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 2028 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2029 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 2030 }; 2031 2032 intc: interrupt-controller@17a00000 { 2033 compatible = "arm,gic-v3"; 2034 #interrupt-cells = <3>; 2035 interrupt-controller; 2036 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 2037 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 2038 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 2039 }; 2040 2041 watchdog@17c10000 { 2042 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 2043 reg = <0 0x17c10000 0 0x1000>; 2044 clocks = <&sleep_clk>; 2045 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 2046 }; 2047 2048 timer@17c20000 { 2049 compatible = "arm,armv7-timer-mem"; 2050 reg = <0x0 0x17c20000 0x0 0x1000>; 2051 clock-frequency = <19200000>; 2052 #address-cells = <1>; 2053 #size-cells = <1>; 2054 ranges = <0 0 0 0x20000000>; 2055 2056 frame@17c21000 { 2057 frame-number = <0>; 2058 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2060 reg = <0x17c21000 0x1000>, 2061 <0x17c22000 0x1000>; 2062 }; 2063 2064 frame@17c23000 { 2065 frame-number = <1>; 2066 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2067 reg = <0x17c23000 0x1000>; 2068 status = "disabled"; 2069 }; 2070 2071 frame@17c25000 { 2072 frame-number = <2>; 2073 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2074 reg = <0x17c25000 0x1000>; 2075 status = "disabled"; 2076 }; 2077 2078 frame@17c27000 { 2079 frame-number = <3>; 2080 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2081 reg = <0x17c27000 0x1000>; 2082 status = "disabled"; 2083 }; 2084 2085 frame@17c29000 { 2086 frame-number = <4>; 2087 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2088 reg = <0x17c29000 0x1000>; 2089 status = "disabled"; 2090 }; 2091 2092 frame@17c2b000 { 2093 frame-number = <5>; 2094 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2095 reg = <0x17c2b000 0x1000>; 2096 status = "disabled"; 2097 }; 2098 2099 frame@17c2d000 { 2100 frame-number = <6>; 2101 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2102 reg = <0x17c2d000 0x1000>; 2103 status = "disabled"; 2104 }; 2105 }; 2106 2107 apps_rsc: rsc@18200000 { 2108 compatible = "qcom,rpmh-rsc"; 2109 label = "apps_rsc"; 2110 reg = <0x0 0x18200000 0x0 0x10000>, 2111 <0x0 0x18210000 0x0 0x10000>, 2112 <0x0 0x18220000 0x0 0x10000>; 2113 reg-names = "drv-0", "drv-1", "drv-2"; 2114 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2117 qcom,tcs-offset = <0xd00>; 2118 qcom,drv-id = <2>; 2119 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 2120 <WAKE_TCS 3>, <CONTROL_TCS 1>; 2121 power-domains = <&CLUSTER_PD>; 2122 2123 rpmhcc: clock-controller { 2124 compatible = "qcom,sm6350-rpmh-clk"; 2125 #clock-cells = <1>; 2126 clock-names = "xo"; 2127 clocks = <&xo_board>; 2128 }; 2129 2130 rpmhpd: power-controller { 2131 compatible = "qcom,sm6350-rpmhpd"; 2132 #power-domain-cells = <1>; 2133 operating-points-v2 = <&rpmhpd_opp_table>; 2134 2135 rpmhpd_opp_table: opp-table { 2136 compatible = "operating-points-v2"; 2137 2138 rpmhpd_opp_ret: opp1 { 2139 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2140 }; 2141 2142 rpmhpd_opp_min_svs: opp2 { 2143 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2144 }; 2145 2146 rpmhpd_opp_low_svs: opp3 { 2147 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2148 }; 2149 2150 rpmhpd_opp_svs: opp4 { 2151 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2152 }; 2153 2154 rpmhpd_opp_svs_l1: opp5 { 2155 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2156 }; 2157 2158 rpmhpd_opp_nom: opp6 { 2159 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2160 }; 2161 2162 rpmhpd_opp_nom_l1: opp7 { 2163 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2164 }; 2165 2166 rpmhpd_opp_nom_l2: opp8 { 2167 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2168 }; 2169 2170 rpmhpd_opp_turbo: opp9 { 2171 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2172 }; 2173 2174 rpmhpd_opp_turbo_l1: opp10 { 2175 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2176 }; 2177 }; 2178 }; 2179 2180 apps_bcm_voter: bcm-voter { 2181 compatible = "qcom,bcm-voter"; 2182 }; 2183 }; 2184 2185 osm_l3: interconnect@18321000 { 2186 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3"; 2187 reg = <0x0 0x18321000 0x0 0x1000>; 2188 2189 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2190 clock-names = "xo", "alternate"; 2191 2192 #interconnect-cells = <1>; 2193 }; 2194 2195 cpufreq_hw: cpufreq@18323000 { 2196 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw"; 2197 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; 2198 reg-names = "freq-domain0", "freq-domain1"; 2199 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2200 clock-names = "xo", "alternate"; 2201 2202 #freq-domain-cells = <1>; 2203 #clock-cells = <1>; 2204 }; 2205 2206 wifi: wifi@18800000 { 2207 compatible = "qcom,wcn3990-wifi"; 2208 reg = <0 0x18800000 0 0x800000>; 2209 reg-names = "membase"; 2210 memory-region = <&wlan_fw_mem>; 2211 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2212 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2213 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2214 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2215 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2216 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2217 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2218 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2219 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2220 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2221 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2222 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2223 iommus = <&apps_smmu 0x20 0x1>; 2224 qcom,msa-fixed-perm; 2225 status = "disabled"; 2226 }; 2227 }; 2228 2229 timer { 2230 compatible = "arm,armv8-timer"; 2231 clock-frequency = <19200000>; 2232 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2233 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2234 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2235 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2236 }; 2237}; 2238